1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* See comment on md_parse_option for 80960-specific invocation options. */
25 /* There are 4 different lengths of (potentially) symbol-based displacements
26 in the 80960 instruction set, each of which could require address fix-ups
27 and (in the case of external symbols) emission of relocation directives:
30 This is a standard length for the base assembler and requires no
34 This is a non-standard length, but the base assembler has a
35 hook for bit field address fixups: the fixS structure can
36 point to a descriptor of the field, in which case our
37 md_number_to_field() routine gets called to process it.
39 I made the hook a little cleaner by having fix_new() (in the base
40 assembler) return a pointer to the fixS in question. And I made it a
41 little simpler by storing the field size (in this case 13) instead of
42 of a pointer to another structure: 80960 displacements are ALWAYS
43 stored in the low-order bits of a 4-byte word.
45 Since the target of a COBR cannot be external, no relocation
46 directives for this size displacement have to be generated.
47 But the base assembler had to be modified to issue error
48 messages if the symbol did turn out to be external.
51 Fixups are handled as for the 13-bit case (except that 24 is stored
54 The relocation directive generated is the same as that for the 32-bit
55 displacement, except that it's PC-relative (the 32-bit displacement
56 never is). The i80960 version of the linker needs a mod to
57 distinguish and handle the 24-bit case.
60 MEMA formats are always promoted to MEMB (32-bit) if the displacement
61 is based on a symbol, because it could be relocated at link time.
62 The only time we use the 12-bit format is if an absolute value of
63 less than 4096 is specified, in which case we need neither a fixup nor
64 a relocation directive. */
70 #include "safe-ctype.h"
73 #include "opcode/i960.h"
75 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
77 #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
78 #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
79 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
80 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
82 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
83 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
85 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
86 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
87 #define TC_S_FORCE_TO_SYSPROC(s) {;}
89 #else /* ! OBJ_A/BOUT */
92 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
93 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
94 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
95 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
97 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
98 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
100 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
101 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
102 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
104 #else /* ! OBJ_COFF */
106 #define TC_S_IS_SYSPROC(s) 0
108 #define TC_S_IS_BALNAME(s) 0
109 #define TC_S_IS_CALLNAME(s) 0
110 #define TC_S_IS_BADPROC(s) 0
112 #define TC_S_SET_SYSPROC(s, p)
113 #define TC_S_GET_SYSPROC(s) 0
115 #define TC_S_FORCE_TO_BALNAME(s)
116 #define TC_S_FORCE_TO_CALLNAME(s)
117 #define TC_S_FORCE_TO_SYSPROC(s)
119 #error COFF, a.out, b.out, and ELF are the only supported formats.
120 #endif /* ! OBJ_ELF */
121 #endif /* ! OBJ_COFF */
122 #endif /* ! OBJ_A/BOUT */
124 extern char *input_line_pointer;
126 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
128 const int md_reloc_size = sizeof (struct reloc);
130 const int md_reloc_size = sizeof (struct relocation_info);
131 #endif /* OBJ_COFF */
134 /* Local i80960 routines. */
138 /* Emit branch-prediction instrumentation code */
139 static void brcnt_emit PARAMS ((void));
140 /* Return next branch local label */
141 static char *brlab_next PARAMS ((void));
142 /* Generate COBR instruction */
143 static void cobr_fmt PARAMS ((char *[], long, struct i960_opcode *));
144 /* Generate CTRL instruction */
145 static void ctrl_fmt PARAMS ((char *, long, int));
146 /* Emit (internally) binary */
147 static char *emit PARAMS ((long));
148 /* Break arguments out of comma-separated list */
149 static int get_args PARAMS ((char *, char *[]));
150 /* Handle COBR or CTRL displacement */
151 static void get_cdisp PARAMS ((char *, char *, long, int, int, int));
152 /* Find index specification string */
153 static char *get_ispec PARAMS ((char *));
154 /* Translate text to register number */
155 static int get_regnum PARAMS ((char *));
156 /* Lexical scan of instruction source */
157 static int i_scan PARAMS ((char *, char *[]));
158 /* Generate MEMA or MEMB instruction */
159 static void mem_fmt PARAMS ((char *[], struct i960_opcode *, int));
160 /* Convert MEMA instruction to MEMB format */
161 static void mema_to_memb PARAMS ((char *));
162 /* Parse an expression */
163 static void parse_expr PARAMS ((char *, expressionS *));
164 /* Parse and replace a 'ldconst' pseudo-op */
165 static int parse_ldconst PARAMS ((char *[]));
166 /* Parse a memory operand */
167 static void parse_memop PARAMS ((struct memS *, char *, int));
168 /* Parse machine-dependent pseudo-op */
169 static void parse_po PARAMS ((int));
170 /* Parse a register operand */
171 static void parse_regop PARAMS ((struct regop *, char *, char));
172 /* Generate a REG format instruction */
173 static void reg_fmt PARAMS ((char *[], struct i960_opcode *));
174 /* "De-optimize" cobr into compare/branch */
175 static void relax_cobr PARAMS ((fragS *));
176 /* Process '.leafproc' pseudo-op */
177 static void s_leafproc PARAMS ((int, char *[]));
178 /* Process '.sysproc' pseudo-op */
179 static void s_sysproc PARAMS ((int, char *[]));
180 /* Will a 'shlo' substitute for a 'ldconst'? */
181 static int shift_ok PARAMS ((int));
182 /* Give syntax error */
183 static void syntax PARAMS ((void));
184 /* Target chip supports spec-func register? */
185 static int targ_has_sfr PARAMS ((int));
186 /* Target chip supports instruction set? */
187 static int targ_has_iclass PARAMS ((int));
189 /* See md_parse_option() for meanings of these options */
190 static char norelax; /* True if -norelax switch seen */
191 static char instrument_branches; /* True if -b switch seen */
193 /* Characters that always start a comment.
194 If the pre-processor is disabled, these aren't very useful.
196 const char comment_chars[] = "#";
198 /* Characters that only start a comment at the beginning of
199 a line. If the line seems to have the form '# 123 filename'
200 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
203 first line of the input file. This is because the compiler outputs
204 #NO_APP at the beginning of its output.
207 /* Also note that comments started like this one will always work. */
209 const char line_comment_chars[] = "#";
211 const char line_separator_chars[] = ";";
213 /* Chars that can be used to separate mant from exp in floating point nums */
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant,
217 as in 0f12.456 or 0d1.2345e12
219 const char FLT_CHARS[] = "fFdDtT";
221 /* Table used by base assembler to relax addresses based on varying length
222 instructions. The fields are:
223 1) most positive reach of this state,
224 2) most negative reach of this state,
225 3) how many bytes this mode will add to the size of the current frag
226 4) which index into the table to try if we can't fit into this one.
228 For i80960, the only application is the (de-)optimization of cobr
229 instructions into separate compare and branch instructions when a 13-bit
230 displacement won't hack it.
232 const relax_typeS md_relax_table[] =
234 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
235 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
236 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
239 static void s_endian PARAMS ((int));
241 /* These are the machine dependent pseudo-ops.
243 This table describes all the machine specific pseudo-ops the assembler
244 has to support. The fields are:
245 pseudo-op name without dot
246 function to call to execute this pseudo-op
247 integer arg to pass to the function
252 const pseudo_typeS md_pseudo_table[] =
255 {"endian", s_endian, 0},
256 {"extended", float_cons, 't'},
257 {"leafproc", parse_po, S_LEAFPROC},
258 {"sysproc", parse_po, S_SYSPROC},
266 /* Macros to extract info from an 'expressionS' structure 'e' */
267 #define adds(e) e.X_add_symbol
268 #define offs(e) e.X_add_number
270 /* Branch-prediction bits for CTRL/COBR format opcodes */
271 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
272 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
273 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
275 /* Some instruction opcodes that we need explicitly */
276 #define BE 0x12000000
277 #define BG 0x11000000
278 #define BGE 0x13000000
279 #define BL 0x14000000
280 #define BLE 0x16000000
281 #define BNE 0x15000000
282 #define BNO 0x10000000
283 #define BO 0x17000000
284 #define CHKBIT 0x5a002700
285 #define CMPI 0x5a002080
286 #define CMPO 0x5a002000
289 #define BAL 0x0b000000
290 #define CALL 0x09000000
291 #define CALLS 0x66003800
292 #define RET 0x0a000000
294 /* These masks are used to build up a set of MEMB mode bits. */
297 #define MEMB_BIT 0x1000
300 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
302 #define MEMA_ABASE 0x2000
304 /* Info from which a MEMA or MEMB format instruction can be generated */
307 /* (First) 32 bits of instruction */
309 /* 0-(none), 12- or, 32-bit displacement needed */
311 /* The expression in the source instruction from which the
312 displacement should be determined. */
317 /* The two pieces of info we need to generate a register operand */
320 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
321 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
322 int n; /* Register number or literal value */
325 /* Number and assembler mnemonic for all registers that can appear in
367 /* Numbers for special-function registers are for assembler internal
368 use only: they are scaled back to range [0-31] for binary output. */
404 /* Numbers for floating point registers are for assembler internal
405 use only: they are scaled back to [0-3] for binary output. */
413 { NULL, 0 }, /* END OF LIST */
416 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
417 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
418 #define IS_FP_REG(n) ((n) >= FP0)
420 /* Number and assembler mnemonic for all registers that can appear as
421 'abase' (indirect addressing) registers. */
463 /* For assembler internal use only: this number never appears in binary
467 { NULL, 0 }, /* END OF LIST */
471 static struct hash_control *op_hash; /* Opcode mnemonics */
472 static struct hash_control *reg_hash; /* Register name hash table */
473 static struct hash_control *areg_hash; /* Abase register hash table */
475 /* Architecture for which we are assembling */
476 #define ARCH_ANY 0 /* Default: no architecture checking done */
483 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
484 int iclasses_seen; /* OR of instruction classes (I_* constants)
485 * for which we've actually assembled
489 /* BRANCH-PREDICTION INSTRUMENTATION
491 The following supports generation of branch-prediction instrumentation
492 (turned on by -b switch). The instrumentation collects counts
493 of branches taken/not-taken for later input to a utility that will
494 set the branch prediction bits of the instructions in accordance with
495 the behavior observed. (Note that the KX series does not have
498 The instrumentation consists of:
500 (1) before and after each conditional branch, a call to an external
501 routine that increments and steps over an inline counter. The
502 counter itself, initialized to 0, immediately follows the call
503 instruction. For each branch, the counter following the branch
504 is the number of times the branch was not taken, and the difference
505 between the counters is the number of times it was taken. An
506 example of an instrumented conditional branch:
514 (2) a table of pointers to the instrumented branches, so that an
515 external postprocessing routine can locate all of the counters.
516 the table begins with a 2-word header: a pointer to the next in
517 a linked list of such tables (initialized to 0); and a count
518 of the number of entries in the table (exclusive of the header.
520 Note that input source code is expected to already contain calls
521 an external routine that will link the branch local table into a
525 /* Number of branches instrumented so far. Also used to generate
526 unique local labels for each instrumented branch. */
529 #define BR_LABEL_BASE "LBRANCH"
530 /* Basename of local labels on instrumented branches, to avoid
531 conflict with compiler- generated local labels. */
533 #define BR_CNT_FUNC "__inc_branch"
534 /* Name of the external routine that will increment (and step over) an
537 #define BR_TAB_NAME "__BRANCH_TABLE__"
538 /* Name of the table of pointers to branches. A local (i.e.,
539 non-external) symbol. */
541 /*****************************************************************************
542 md_begin: One-time initialization.
546 *************************************************************************** */
550 int i; /* Loop counter */
551 const struct i960_opcode *oP; /* Pointer into opcode table */
552 const char *retval; /* Value returned by hash functions */
554 op_hash = hash_new ();
555 reg_hash = hash_new ();
556 areg_hash = hash_new ();
558 /* For some reason, the base assembler uses an empty string for "no
559 error message", instead of a NULL pointer. */
562 for (oP = i960_opcodes; oP->name && !retval; oP++)
563 retval = hash_insert (op_hash, oP->name, (PTR) oP);
565 for (i = 0; regnames[i].reg_name && !retval; i++)
566 retval = hash_insert (reg_hash, regnames[i].reg_name,
567 (char *) ®names[i].reg_num);
569 for (i = 0; aregs[i].areg_name && !retval; i++)
570 retval = hash_insert (areg_hash, aregs[i].areg_name,
571 (char *) &aregs[i].areg_num);
574 as_fatal (_("Hashing returned \"%s\"."), retval);
577 /*****************************************************************************
578 md_assemble: Assemble an instruction
580 Assumptions about the passed-in text:
581 - all comments, labels removed
582 - text is an instruction
583 - all white space compressed to single blanks
584 - all character constants have been replaced with decimal
586 *************************************************************************** */
589 char *textP; /* Source text of instruction */
591 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
592 mnemonic arg[1-3]->operands, with char constants replaced by
596 int n_ops; /* Number of instruction operands */
597 /* Pointer to instruction description */
598 struct i960_opcode *oP;
599 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
602 /* Setting of branch-prediction bit(s) to be OR'd into instruction
603 opcode of CTRL/COBR format instructions. */
606 int n; /* Offset of last character in opcode mnemonic */
608 const char *bp_error_msg = _("branch prediction invalid on this opcode");
610 /* Parse instruction into opcode and operands */
611 memset (args, '\0', sizeof (args));
612 n_ops = i_scan (textP, args);
615 return; /* Error message already issued */
618 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
619 if (!strcmp (args[0], "ldconst"))
621 n_ops = parse_ldconst (args);
628 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
629 n = strlen (args[0]) - 1;
632 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
634 /* We could check here to see if the target architecture
635 supports branch prediction, but why bother? The bit will
636 just be ignored by processors that don't use it. */
638 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
639 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
642 /* Look up opcode mnemonic in table and check number of operands.
643 Check that opcode is legal for the target architecture. If all
644 looks good, assemble instruction. */
645 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
646 if (!oP || !targ_has_iclass (oP->iclass))
648 as_bad (_("invalid opcode, \"%s\"."), args[0]);
651 else if (n_ops != oP->num_ops)
653 as_bad (_("improper number of operands. expecting %d, got %d"),
662 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
663 if (oP->format == FBRA)
665 /* Now generate a 'bno' to same arg */
666 ctrl_fmt (args[1], BNO | bp_bits, 1);
671 cobr_fmt (args, oP->opcode | bp_bits, oP);
676 as_warn (bp_error_msg);
681 if (args[0][0] == 'c' && args[0][1] == 'a')
685 as_warn (bp_error_msg);
687 mem_fmt (args, oP, 1);
697 as_warn (bp_error_msg);
699 mem_fmt (args, oP, 0);
704 as_warn (bp_error_msg);
706 /* Output opcode & set up "fixup" (relocation); flag
707 relocation as 'callj' type. */
708 know (oP->num_ops == 1);
709 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
712 BAD_CASE (oP->format);
716 } /* md_assemble() */
718 /*****************************************************************************
719 md_number_to_chars: convert a number to target byte order
721 *************************************************************************** */
723 md_number_to_chars (buf, value, n)
728 number_to_chars_littleendian (buf, value, n);
731 /*****************************************************************************
732 md_chars_to_number: convert from target byte order to host byte order.
734 *************************************************************************** */
735 static int md_chars_to_number PARAMS ((char *, int));
738 md_chars_to_number (val, n)
739 char *val; /* Value in target byte order */
740 int n; /* Number of bytes in the input */
744 for (retval = 0; n--;)
747 retval |= (unsigned char) val[n];
752 #define MAX_LITTLENUMS 6
753 #define LNUM_SIZE sizeof (LITTLENUM_TYPE)
755 /*****************************************************************************
756 md_atof: convert ascii to floating point
758 Turn a string at input_line_pointer into a floating point constant of type
759 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
760 emitted is returned at 'sizeP'. An error message is returned, or a pointer
761 to an empty message if OK.
763 Note we call the i386 floating point routine, rather than complicating
764 things with more files or symbolic links.
766 *************************************************************************** */
768 md_atof (type, litP, sizeP)
773 LITTLENUM_TYPE words[MAX_LITTLENUMS];
774 LITTLENUM_TYPE *wordP;
793 type = 'x'; /* That's what atof_ieee() understands */
798 return _("Bad call to md_atof()");
801 t = atof_ieee (input_line_pointer, type, words);
804 input_line_pointer = t;
807 *sizeP = prec * LNUM_SIZE;
809 /* Output the LITTLENUMs in REVERSE order in accord with i80960
810 word-order. (Dunno why atof_ieee doesn't do it in the right
811 order in the first place -- probably because it's a hack of
814 for (wordP = words + prec - 1; prec--;)
816 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
817 litP += sizeof (LITTLENUM_TYPE);
823 /*****************************************************************************
826 *************************************************************************** */
827 static void md_number_to_imm PARAMS ((char *, long, int));
830 md_number_to_imm (buf, val, n)
835 md_number_to_chars (buf, val, n);
838 /*****************************************************************************
841 Stick a value (an address fixup) into a bit field of
842 previously-generated instruction.
844 *************************************************************************** */
845 static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
848 md_number_to_field (instrP, val, bfixP)
849 char *instrP; /* Pointer to instruction to be fixed */
850 long val; /* Address fixup value */
851 bit_fixS *bfixP; /* Description of bit field to be fixed up */
853 int numbits; /* Length of bit field to be fixed */
854 long instr; /* 32-bit instruction to be fixed-up */
855 long sign; /* 0 or -1, according to sign bit of 'val' */
857 /* Convert instruction back to host byte order. */
858 instr = md_chars_to_number (instrP, 4);
860 /* Surprise! -- we stored the number of bits to be modified rather
861 than a pointer to a structure. */
862 numbits = (int) (size_t) bfixP;
865 /* This is a no-op, stuck here by reloc_callj() */
869 know ((numbits == 13) || (numbits == 24));
871 /* Propagate sign bit of 'val' for the given number of bits. Result
872 should be all 0 or all 1. */
873 sign = val >> ((int) numbits - 1);
874 if (((val < 0) && (sign != -1))
875 || ((val > 0) && (sign != 0)))
877 as_bad (_("Fixup of %ld too large for field width of %d"),
882 /* Put bit field into instruction and write back in target
885 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
887 md_number_to_chars (instrP, instr, 4);
889 } /* md_number_to_field() */
892 /*****************************************************************************
894 Invocation line includes a switch not recognized by the base assembler.
895 See if it's a processor-specific option. For the 960, these are:
898 Conditional branch instructions that require displacements
899 greater than 13 bits (or that have external targets) should
900 generate errors. The default is to replace each such
901 instruction with the corresponding compare (or chkbit) and
902 branch instructions. Note that the Intel "j" cobr directives
903 are ALWAYS "de-optimized" in this way when necessary,
904 regardless of the setting of this option.
907 Add code to collect information about branches taken, for
908 later optimization of branch prediction bits by a separate
909 tool. COBR and CNTL format instructions have branch
910 prediction bits (in the CX architecture); if "BR" represents
911 an instruction in one of these classes, the following rep-
912 resents the code generated by the assembler:
914 call <increment routine>
915 .word 0 # pre-counter
917 call <increment routine>
918 .word 0 # post-counter
920 A table of all such "Labels" is also generated.
922 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
923 Select the 80960 architecture. Instructions or features not
924 supported by the selected architecture cause fatal errors.
925 The default is to generate code for any instruction or feature
926 that is supported by SOME version of the 960 (even if this
927 means mixing architectures!).
929 ****************************************************************************/
931 const char *md_shortopts = "A:b";
932 struct option md_longopts[] =
934 #define OPTION_LINKRELAX (OPTION_MD_BASE)
935 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
936 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
937 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
938 {"norelax", no_argument, NULL, OPTION_NORELAX},
939 {"no-relax", no_argument, NULL, OPTION_NORELAX},
940 {NULL, no_argument, NULL, 0}
942 size_t md_longopts_size = sizeof (md_longopts);
949 static const struct tabentry arch_tab[] =
953 {"SA", ARCH_KA}, /* Synonym for KA */
954 {"SB", ARCH_KB}, /* Synonym for KB */
955 {"KC", ARCH_MC}, /* Synonym for MC */
964 md_parse_option (c, arg)
970 case OPTION_LINKRELAX:
972 flag_keep_locals = 1;
980 instrument_branches = 1;
985 const struct tabentry *tp;
988 for (tp = arch_tab; tp->flag != NULL; tp++)
989 if (!strcmp (p, tp->flag))
992 if (tp->flag == NULL)
994 as_bad (_("invalid architecture %s"), p);
998 architecture = tp->arch;
1010 md_show_usage (stream)
1014 fprintf (stream, _("I960 options:\n"));
1015 for (i = 0; arch_tab[i].flag; i++)
1016 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1017 fprintf (stream, _("\n\
1018 specify variant of 960 architecture\n\
1019 -b add code to collect statistics about branches taken\n\
1020 -link-relax preserve individual alignment directives so linker\n\
1021 can do relaxing (b.out format only)\n\
1022 -no-relax don't alter compare-and-branch instructions for\n\
1023 long displacements\n"));
1027 /*****************************************************************************
1029 Called by base assembler after address relaxation is finished: modify
1030 variable fragments according to how much relaxation was done.
1032 If the fragment substate is still 1, a 13-bit displacement was enough
1033 to reach the symbol in question. Set up an address fixup, but otherwise
1034 leave the cobr instruction alone.
1036 If the fragment substate is 2, a 13-bit displacement was not enough.
1037 Replace the cobr with a two instructions (a compare and a branch).
1039 *************************************************************************** */
1040 #ifndef BFD_ASSEMBLER
1042 md_convert_frag (headers, seg, fragP)
1043 object_headers *headers ATTRIBUTE_UNUSED;
1044 segT seg ATTRIBUTE_UNUSED;
1048 md_convert_frag (abfd, sec, fragP)
1049 bfd *abfd ATTRIBUTE_UNUSED;
1050 segT sec ATTRIBUTE_UNUSED;
1054 fixS *fixP; /* Structure describing needed address fix */
1056 switch (fragP->fr_subtype)
1059 /* LEAVE SINGLE COBR INSTRUCTION */
1060 fixP = fix_new (fragP,
1061 fragP->fr_opcode - fragP->fr_literal,
1068 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1071 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1075 BAD_CASE (fragP->fr_subtype);
1080 /*****************************************************************************
1081 md_estimate_size_before_relax: How much does it look like *fragP will grow?
1083 Called by base assembler just before address relaxation.
1084 Return the amount by which the fragment will grow.
1086 Any symbol that is now undefined will not become defined; cobr's
1087 based on undefined symbols will have to be replaced with a compare
1088 instruction and a branch instruction, and the code fragment will grow
1091 *************************************************************************** */
1093 md_estimate_size_before_relax (fragP, segment_type)
1094 register fragS *fragP;
1095 register segT segment_type;
1097 /* If symbol is undefined in this segment, go to "relaxed" state
1098 (compare and branch instructions instead of cobr) right now. */
1099 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1105 return md_relax_table[fragP->fr_subtype].rlx_length;
1106 } /* md_estimate_size_before_relax() */
1108 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
1110 /*****************************************************************************
1112 This routine exists in order to overcome machine byte-order problems
1113 when dealing with bit-field entries in the relocation_info struct.
1115 But relocation info will be used on the host machine only (only
1116 executable code is actually downloaded to the i80960). Therefore,
1117 we leave it in host byte order.
1119 *************************************************************************** */
1120 static void md_ri_to_chars PARAMS ((char *, struct relocation_info *));
1123 md_ri_to_chars (where, ri)
1125 struct relocation_info *ri;
1127 host_number_to_chars (where, ri->r_address, 4);
1128 host_number_to_chars (where + 4, ri->r_index, 3);
1130 where[7] = (ri->r_pcrel << 7
1138 where[7] = (ri->r_pcrel << 0
1148 #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
1151 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */
1153 /*****************************************************************************
1154 brcnt_emit: Emit code to increment inline branch counter.
1156 See the comments above the declaration of 'br_cnt' for details on
1157 branch-prediction instrumentation.
1158 *************************************************************************** */
1162 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1163 emit (0); /* Emit inline counter to be incremented */
1166 /*****************************************************************************
1167 brlab_next: generate the next branch local label
1169 See the comments above the declaration of 'br_cnt' for details on
1170 branch-prediction instrumentation.
1171 *************************************************************************** */
1175 static char buf[20];
1177 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1181 /*****************************************************************************
1182 brtab_emit: generate the fetch-prediction branch table.
1184 See the comments above the declaration of 'br_cnt' for details on
1185 branch-prediction instrumentation.
1187 The code emitted here would be functionally equivalent to the following
1188 example assembler source.
1193 .word 0 # link to next table
1194 .word 3 # length of table
1195 .word LBRANCH0 # 1st entry in table proper
1198 **************************************************************************** */
1204 char *p; /* Where the binary was output to */
1205 /* Pointer to description of deferred address fixup. */
1208 if (!instrument_branches)
1213 subseg_set (data_section, 0); /* .data */
1214 frag_align (2, 0, 0); /* .align 2 */
1215 record_alignment (now_seg, 2);
1216 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1217 emit (0); /* .word 0 #link to next table */
1218 emit (br_cnt); /* .word n #length of table */
1220 for (i = 0; i < br_cnt; i++)
1222 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1224 fixP = fix_new (frag_now,
1225 p - frag_now->fr_literal,
1234 /*****************************************************************************
1235 cobr_fmt: generate a COBR-format instruction
1237 *************************************************************************** */
1239 cobr_fmt (arg, opcode, oP)
1240 /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1242 /* Opcode, with branch-prediction bits already set if necessary. */
1244 /* Pointer to description of instruction. */
1245 struct i960_opcode *oP;
1247 long instr; /* 32-bit instruction */
1248 struct regop regop; /* Description of register operand */
1249 int n; /* Number of operands */
1250 int var_frag; /* 1 if varying length code fragment should
1251 * be emitted; 0 if an address fix
1252 * should be emitted.
1260 /* First operand (if any) of a COBR is always a register
1261 operand. Parse it. */
1262 parse_regop (®op, arg[1], oP->operand[0]);
1263 instr |= (regop.n << 19) | (regop.mode << 13);
1267 /* Second operand (if any) of a COBR is always a register
1268 operand. Parse it. */
1269 parse_regop (®op, arg[2], oP->operand[1]);
1270 instr |= (regop.n << 14) | regop.special;
1280 if (instrument_branches)
1283 colon (brlab_next ());
1286 /* A third operand to a COBR is always a displacement. Parse
1287 it; if it's relaxable (a cobr "j" directive, or any cobr
1288 other than bbs/bbc when the "-norelax" option is not in use)
1289 set up a variable code fragment; otherwise set up an address
1291 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1292 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1294 if (instrument_branches)
1301 /*****************************************************************************
1302 ctrl_fmt: generate a CTRL-format instruction
1304 *************************************************************************** */
1306 ctrl_fmt (targP, opcode, num_ops)
1307 char *targP; /* Pointer to text of lone operand (if any) */
1308 long opcode; /* Template of instruction */
1309 int num_ops; /* Number of operands */
1311 int instrument; /* TRUE iff we should add instrumentation to track
1312 * how often the branch is taken
1317 emit (opcode); /* Output opcode */
1322 instrument = instrument_branches && (opcode != CALL)
1323 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1328 colon (brlab_next ());
1331 /* The operand MUST be an ip-relative displacement. Parse it
1332 * and set up address fix for the instruction we just output.
1334 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1344 /*****************************************************************************
1345 emit: output instruction binary
1347 Output instruction binary, in target byte order, 4 bytes at a time.
1348 Return pointer to where it was placed.
1350 *************************************************************************** */
1353 long instr; /* Word to be output, host byte order */
1355 char *toP; /* Where to output it */
1357 toP = frag_more (4); /* Allocate storage */
1358 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1362 /*****************************************************************************
1363 get_args: break individual arguments out of comma-separated list
1366 - all comments and labels have been removed
1367 - all strings of whitespace have been collapsed to a single blank.
1368 - all character constants ('x') have been replaced with decimal
1371 args[0] is untouched. args[1] points to first operand, etc. All args:
1372 - are NULL-terminated
1373 - contain no whitespace
1376 Number of operands (0,1,2, or 3) or -1 on error.
1378 *************************************************************************** */
1381 /* Pointer to comma-separated operands; MUCKED BY US */
1383 /* Output arg: pointers to operands placed in args[1-3]. MUST
1384 ACCOMMODATE 4 ENTRIES (args[0-3]). */
1387 register int n; /* Number of operands */
1390 /* Skip lead white space */
1404 /* Squeze blanks out by moving non-blanks toward start of string.
1405 * Isolate operands, whenever comma is found.
1412 && (! ISALNUM (p[1])
1413 || ! ISALNUM (p[-1])))
1421 /* Start of operand */
1424 as_bad (_("too many operands"));
1427 *to++ = '\0'; /* Terminate argument */
1428 args[++n] = to; /* Start next argument */
1441 /*****************************************************************************
1442 get_cdisp: handle displacement for a COBR or CTRL instruction.
1444 Parse displacement for a COBR or CTRL instruction.
1446 If successful, output the instruction opcode and set up for it,
1447 depending on the arg 'var_frag', either:
1448 o an address fixup to be done when all symbol values are known, or
1449 o a varying length code fragment, with address fixup info. This
1450 will be done for cobr instructions that may have to be relaxed
1451 in to compare/branch instructions (8 bytes) if the final
1452 address displacement is greater than 13 bits.
1454 ****************************************************************************/
1456 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1457 /* displacement as specified in source instruction */
1459 /* "COBR" or "CTRL" (for use in error message) */
1461 /* Instruction needing the displacement */
1463 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1465 /* 1 if varying length code fragment should be emitted;
1466 * 0 if an address fix should be emitted.
1469 /* 1 if callj relocation should be done; else 0 */
1472 expressionS e; /* Parsed expression */
1473 fixS *fixP; /* Structure describing needed address fix */
1474 char *outP; /* Where instruction binary is output to */
1478 parse_expr (dispP, &e);
1482 as_bad (_("expression syntax error"));
1485 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1486 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1490 outP = frag_more (8); /* Allocate worst-case storage */
1491 md_number_to_chars (outP, instr, 4);
1492 frag_variant (rs_machine_dependent, 4, 4, 1,
1493 adds (e), offs (e), outP);
1497 /* Set up a new fix structure, so address can be updated
1498 * when all symbol values are known.
1500 outP = emit (instr);
1501 fixP = fix_new (frag_now,
1502 outP - frag_now->fr_literal,
1509 fixP->fx_tcbit = callj;
1511 /* We want to modify a bit field when the address is
1512 * known. But we don't need all the garbage in the
1513 * bit_fix structure. So we're going to lie and store
1514 * the number of bits affected instead of a pointer.
1516 fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
1520 as_bad (_("attempt to branch into different segment"));
1524 as_bad (_("target of %s instruction must be a label"), ifmtP);
1529 /*****************************************************************************
1530 get_ispec: parse a memory operand for an index specification
1532 Here, an "index specification" is taken to be anything surrounded
1533 by square brackets and NOT followed by anything else.
1535 If it's found, detach it from the input string, remove the surrounding
1536 square brackets, and return a pointer to it. Otherwise, return NULL.
1538 *************************************************************************** */
1541 /* Pointer to memory operand from source instruction, no white space. */
1544 /* Points to start of index specification. */
1546 /* Points to end of index specification. */
1549 /* Find opening square bracket, if any. */
1550 start = strchr (textP, '[');
1555 /* Eliminate '[', detach from rest of operand */
1558 end = strchr (start, ']');
1562 as_bad (_("unmatched '['"));
1567 /* Eliminate ']' and make sure it was the last thing
1571 if (*(end + 1) != '\0')
1573 as_bad (_("garbage after index spec ignored"));
1580 /*****************************************************************************
1583 Look up a (suspected) register name in the register table and return the
1584 associated register number (or -1 if not found).
1586 *************************************************************************** */
1588 get_regnum (regname)
1589 char *regname; /* Suspected register name */
1593 rP = (int *) hash_find (reg_hash, regname);
1594 return (rP == NULL) ? -1 : *rP;
1597 /*****************************************************************************
1598 i_scan: perform lexical scan of ascii assembler instruction.
1601 - input string is an i80960 instruction (not a pseudo-op)
1602 - all comments and labels have been removed
1603 - all strings of whitespace have been collapsed to a single blank.
1606 args[0] points to opcode, other entries point to operands. All strings:
1607 - are NULL-terminated
1608 - contain no whitespace
1609 - have character constants ('x') replaced with a decimal number
1612 Number of operands (0,1,2, or 3) or -1 on error.
1614 *************************************************************************** */
1617 /* Pointer to ascii instruction; MUCKED BY US. */
1619 /* Output arg: pointers to opcode and operands placed here. MUST
1620 ACCOMMODATE 4 ENTRIES. */
1624 /* Isolate opcode */
1628 } /* Skip lead space, if any */
1630 for (; *iP != ' '; iP++)
1634 /* There are no operands */
1637 /* We never moved: there was no opcode either! */
1638 as_bad (_("missing opcode"));
1644 *iP++ = '\0'; /* Terminate opcode */
1645 return (get_args (iP, args));
1648 /*****************************************************************************
1649 mem_fmt: generate a MEMA- or MEMB-format instruction
1651 *************************************************************************** */
1653 mem_fmt (args, oP, callx)
1654 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1655 struct i960_opcode *oP; /* Pointer to description of instruction */
1656 int callx; /* Is this a callx opcode */
1658 int i; /* Loop counter */
1659 struct regop regop; /* Description of register operand */
1660 char opdesc; /* Operand descriptor byte */
1661 memS instr; /* Description of binary to be output */
1662 char *outP; /* Where the binary was output to */
1663 expressionS expr; /* Parsed expression */
1664 /* ->description of deferred address fixup */
1668 /* COFF support isn't in place yet for callx relaxing. */
1672 memset (&instr, '\0', sizeof (memS));
1673 instr.opcode = oP->opcode;
1675 /* Process operands. */
1676 for (i = 1; i <= oP->num_ops; i++)
1678 opdesc = oP->operand[i - 1];
1682 parse_memop (&instr, args[i], oP->format);
1686 parse_regop (®op, args[i], opdesc);
1687 instr.opcode |= regop.n << 19;
1691 /* Parse the displacement; this must be done before emitting the
1692 opcode, in case it is an expression using `.'. */
1693 parse_expr (instr.e, &expr);
1696 outP = emit (instr.opcode);
1698 if (instr.disp == 0)
1703 /* Process the displacement */
1707 as_bad (_("expression syntax error"));
1711 if (instr.disp == 32)
1713 (void) emit (offs (expr)); /* Output displacement */
1717 /* 12-bit displacement */
1718 if (offs (expr) & ~0xfff)
1720 /* Won't fit in 12 bits: convert already-output
1721 * instruction to MEMB format, output
1724 mema_to_memb (outP);
1725 (void) emit (offs (expr));
1729 /* WILL fit in 12 bits: OR into opcode and
1730 * overwrite the binary we already put out
1732 instr.opcode |= offs (expr);
1733 md_number_to_chars (outP, instr.opcode, 4);
1739 if (instr.disp == 12)
1741 /* Displacement is dependent on a symbol, whose value
1742 * may change at link time. We HAVE to reserve 32 bits.
1743 * Convert already-output opcode to MEMB format.
1745 mema_to_memb (outP);
1748 /* Output 0 displacement and set up address fixup for when
1749 * this symbol's value becomes known.
1751 outP = emit ((long) 0);
1752 fixP = fix_new_exp (frag_now,
1753 outP - frag_now->fr_literal,
1758 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1759 being in the instruction stream, specifically as part of a callx
1761 fixP->fx_bsr = callx;
1766 /*****************************************************************************
1767 mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1769 There are 2 possible MEMA formats:
1771 - displacement + abase
1773 They are distinguished by the setting of the MEMA_ABASE bit.
1775 *************************************************************************** */
1777 mema_to_memb (opcodeP)
1778 char *opcodeP; /* Where to find the opcode, in target byte order */
1780 long opcode; /* Opcode in host byte order */
1781 long mode; /* Mode bits for MEMB instruction */
1783 opcode = md_chars_to_number (opcodeP, 4);
1784 know (!(opcode & MEMB_BIT));
1786 mode = MEMB_BIT | D_BIT;
1787 if (opcode & MEMA_ABASE)
1792 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1793 opcode |= mode; /* Set MEMB mode bits */
1795 md_number_to_chars (opcodeP, opcode, 4);
1796 } /* mema_to_memb() */
1798 /*****************************************************************************
1799 parse_expr: parse an expression
1801 Use base assembler's expression parser to parse an expression.
1802 It, unfortunately, runs off a global which we have to save/restore
1803 in order to make it work for us.
1805 An empty expression string is treated as an absolute 0.
1807 Sets O_illegal regardless of expression evaluation if entire input
1808 string is not consumed in the evaluation -- tolerate no dangling junk!
1810 *************************************************************************** */
1812 parse_expr (textP, expP)
1813 char *textP; /* Text of expression to be parsed */
1814 expressionS *expP; /* Where to put the results of parsing */
1816 char *save_in; /* Save global here */
1823 /* Treat empty string as absolute 0 */
1824 expP->X_add_symbol = expP->X_op_symbol = NULL;
1825 expP->X_add_number = 0;
1826 expP->X_op = O_constant;
1830 save_in = input_line_pointer; /* Save global */
1831 input_line_pointer = textP; /* Make parser work for us */
1833 (void) expression (expP);
1834 if ((size_t) (input_line_pointer - textP) != strlen (textP))
1836 /* Did not consume all of the input */
1837 expP->X_op = O_illegal;
1839 symP = expP->X_add_symbol;
1840 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1842 /* Register name in an expression */
1843 /* FIXME: this isn't much of a check any more. */
1844 expP->X_op = O_illegal;
1847 input_line_pointer = save_in; /* Restore global */
1851 /*****************************************************************************
1853 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1856 Assumes the input consists of:
1857 arg[0] opcode mnemonic ('ldconst')
1858 arg[1] first operand (constant)
1859 arg[2] name of register to be loaded
1861 Replaces opcode and/or operands as appropriate.
1863 Returns the new number of arguments, or -1 on failure.
1865 *************************************************************************** */
1868 char *arg[]; /* See above */
1870 int n; /* Constant to be loaded */
1871 int shift; /* Shift count for "shlo" instruction */
1872 static char buf[5]; /* Literal for first operand */
1873 static char buf2[5]; /* Literal for second operand */
1874 expressionS e; /* Parsed expression */
1876 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1878 parse_expr (arg[1], &e);
1882 /* We're dependent on one or more symbols -- use "lda" */
1887 /* Try the following mappings:
1888 * ldconst 0,<reg> ->mov 0,<reg>
1889 * ldconst 31,<reg> ->mov 31,<reg>
1890 * ldconst 32,<reg> ->addo 1,31,<reg>
1891 * ldconst 62,<reg> ->addo 31,31,<reg>
1892 * ldconst 64,<reg> ->shlo 8,3,<reg>
1893 * ldconst -1,<reg> ->subo 1,0,<reg>
1894 * ldconst -31,<reg>->subo 31,0,<reg>
1896 * anything else becomes:
1900 if ((0 <= n) && (n <= 31))
1905 else if ((-31 <= n) && (n <= -1))
1909 sprintf (buf, "%d", -n);
1914 else if ((32 <= n) && (n <= 62))
1919 sprintf (buf, "%d", n - 31);
1923 else if ((shift = shift_ok (n)) != 0)
1927 sprintf (buf, "%d", shift);
1929 sprintf (buf2, "%d", n >> shift);
1940 as_bad (_("invalid constant"));
1944 return (arg[3] == 0) ? 2 : 3;
1947 /*****************************************************************************
1948 parse_memop: parse a memory operand
1950 This routine is based on the observation that the 4 mode bits of the
1951 MEMB format, taken individually, have fairly consistent meaning:
1953 M3 (bit 13): 1 if displacement is present (D_BIT)
1954 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1955 M1 (bit 11): 1 if index is present (I_BIT)
1956 M0 (bit 10): 1 if abase is present (A_BIT)
1958 So we parse the memory operand and set bits in the mode as we find
1959 things. Then at the end, if we go to MEMB format, we need only set
1960 the MEMB bit (M2) and our mode is built for us.
1962 Unfortunately, I said "fairly consistent". The exceptions:
1965 0100 Would seem illegal, but means "abase-only".
1967 0101 Would seem to mean "abase-only" -- it means IP-relative.
1968 Must be converted to 0100.
1970 0110 Would seem to mean "index-only", but is reserved.
1971 We turn on the D bit and provide a 0 displacement.
1973 The other thing to observe is that we parse from the right, peeling
1974 things * off as we go: first any index spec, then any abase, then
1977 *************************************************************************** */
1979 parse_memop (memP, argP, optype)
1980 memS *memP; /* Where to put the results */
1981 char *argP; /* Text of the operand to be parsed */
1982 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1984 char *indexP; /* Pointer to index specification with "[]" removed */
1985 char *p; /* Temp char pointer */
1986 char iprel_flag; /* True if this is an IP-relative operand */
1987 int regnum; /* Register number */
1988 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
1989 (0,1,2,3,4 respectively). */
1991 int mode; /* MEMB mode bits */
1992 int *intP; /* Pointer to register number */
1994 /* The following table contains the default scale factors for each
1995 type of memory instruction. It is accessed using (optype-MEM1)
1996 as an index -- thus it assumes the 'optype' constants are
1997 assigned consecutive values, in the order they appear in this
1999 static const int def_scale[] =
2005 -1, /* MEM12 -- no valid default */
2009 iprel_flag = mode = 0;
2011 /* Any index present? */
2012 indexP = get_ispec (argP);
2015 p = strchr (indexP, '*');
2018 /* No explicit scale -- use default for this instruction
2019 type and assembler mode. */
2023 /* GNU960 compatibility */
2024 scale = def_scale[optype - MEM1];
2028 *p++ = '\0'; /* Eliminate '*' */
2030 /* Now indexP->a '\0'-terminated register name,
2031 * and p->a scale factor.
2034 if (!strcmp (p, "16"))
2038 else if (strchr ("1248", *p) && (p[1] == '\0'))
2048 regnum = get_regnum (indexP); /* Get index reg. # */
2049 if (!IS_RG_REG (regnum))
2051 as_bad (_("invalid index register"));
2055 /* Convert scale to its binary encoding */
2074 as_bad (_("invalid scale factor"));
2078 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2079 mode |= I_BIT; /* Found a valid index spec */
2082 /* Any abase (Register Indirect) specification present? */
2083 if ((p = strrchr (argP, '(')) != NULL)
2085 /* "(" is there -- does it start a legal abase spec? If not, it
2086 could be part of a displacement expression. */
2087 intP = (int *) hash_find (areg_hash, p);
2090 /* Got an abase here */
2092 *p = '\0'; /* discard register spec */
2093 if (regnum == IPREL)
2095 /* We have to specialcase ip-rel mode */
2100 memP->opcode |= regnum << 14;
2106 /* Any expression present? */
2113 /* Special-case ip-relative addressing */
2122 memP->opcode |= 5 << 10; /* IP-relative mode */
2128 /* Handle all other modes */
2132 /* Go with MEMA instruction format for now (grow to MEMB later
2133 if 12 bits is not enough for the displacement). MEMA format
2134 has a single mode bit: set it to indicate that abase is
2136 memP->opcode |= MEMA_ABASE;
2141 /* Go with MEMA instruction format for now (grow to MEMB later
2142 if 12 bits is not enough for the displacement). */
2147 /* For some reason, the bit string for this mode is not
2148 consistent: it should be 0 (exclusive of the MEMB bit), so we
2149 set it "by hand" here. */
2150 memP->opcode |= MEMB_BIT;
2154 /* set MEMB bit in mode, and OR in mode bits */
2155 memP->opcode |= mode | MEMB_BIT;
2159 /* Treat missing displacement as displacement of 0. */
2161 /* Fall into next case. */
2162 case D_BIT | A_BIT | I_BIT:
2164 /* set MEMB bit in mode, and OR in mode bits */
2165 memP->opcode |= mode | MEMB_BIT;
2175 /*****************************************************************************
2176 parse_po: parse machine-dependent pseudo-op
2178 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2179 up the rest of the input line, breaks out the individual arguments,
2180 and dispatches them to the correct handler.
2181 *************************************************************************** */
2184 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2186 /* Pointers operands, with no embedded whitespace.
2187 arg[0] unused, arg[1-3]->operands */
2189 int n_ops; /* Number of operands */
2190 char *p; /* Pointer to beginning of unparsed argument string */
2191 char eol; /* Character that indicated end of line */
2193 extern char is_end_of_line[];
2195 /* Advance input pointer to end of line. */
2196 p = input_line_pointer;
2197 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2199 input_line_pointer++;
2201 eol = *input_line_pointer; /* Save end-of-line char */
2202 *input_line_pointer = '\0'; /* Terminate argument list */
2204 /* Parse out operands */
2205 n_ops = get_args (p, args);
2211 /* Dispatch to correct handler */
2215 s_sysproc (n_ops, args);
2218 s_leafproc (n_ops, args);
2225 /* Restore eol, so line numbers get updated correctly. Base
2226 assembler assumes we leave input pointer pointing at char
2227 following the eol. */
2228 *input_line_pointer++ = eol;
2231 /*****************************************************************************
2232 parse_regop: parse a register operand.
2234 In case of illegal operand, issue a message and return some valid
2235 information so instruction processing can continue.
2236 *************************************************************************** */
2238 parse_regop (regopP, optext, opdesc)
2239 struct regop *regopP; /* Where to put description of register operand */
2240 char *optext; /* Text of operand */
2241 char opdesc; /* Descriptor byte: what's legal for this operand */
2243 int n; /* Register number */
2244 expressionS e; /* Parsed expression */
2246 /* See if operand is a register */
2247 n = get_regnum (optext);
2252 /* global or local register */
2253 if (!REG_ALIGN (opdesc, n))
2255 as_bad (_("unaligned register"));
2259 regopP->special = 0;
2262 else if (IS_FP_REG (n) && FP_OK (opdesc))
2264 /* Floating point register, and it's allowed */
2265 regopP->n = n - FP0;
2267 regopP->special = 0;
2270 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2272 /* Special-function register, and it's allowed */
2273 regopP->n = n - SF0;
2275 regopP->special = 1;
2276 if (!targ_has_sfr (regopP->n))
2278 as_bad (_("no such sfr in this architecture"));
2283 else if (LIT_OK (opdesc))
2285 /* How about a literal? */
2287 regopP->special = 0;
2289 { /* floating point literal acceptable */
2290 /* Skip over 0f, 0d, or 0e prefix */
2291 if ((optext[0] == '0')
2292 && (optext[1] >= 'd')
2293 && (optext[1] <= 'f'))
2298 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2303 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2311 { /* fixed point literal acceptable */
2312 parse_expr (optext, &e);
2313 if (e.X_op != O_constant
2314 || (offs (e) < 0) || (offs (e) > 31))
2316 as_bad (_("illegal literal"));
2319 regopP->n = offs (e);
2324 /* Nothing worked */
2326 regopP->mode = 0; /* Register r0 is always a good one */
2328 regopP->special = 0;
2329 } /* parse_regop() */
2331 /*****************************************************************************
2332 reg_fmt: generate a REG-format instruction
2334 *************************************************************************** */
2337 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2338 struct i960_opcode *oP; /* Pointer to description of instruction */
2340 long instr; /* Binary to be output */
2341 struct regop regop; /* Description of register operand */
2342 int n_ops; /* Number of operands */
2345 n_ops = oP->num_ops;
2349 parse_regop (®op, args[1], oP->operand[0]);
2351 if ((n_ops == 1) && !(instr & M3))
2353 /* 1-operand instruction in which the dst field should
2354 * be used (instead of src1).
2359 regop.mode = regop.special;
2366 /* regop.n goes in bit 0, needs no shifting */
2368 regop.special <<= 5;
2370 instr |= regop.n | regop.mode | regop.special;
2375 parse_regop (®op, args[2], oP->operand[1]);
2377 if ((n_ops == 2) && !(instr & M3))
2379 /* 2-operand instruction in which the dst field should
2380 * be used instead of src2).
2385 regop.mode = regop.special;
2394 regop.special <<= 6;
2396 instr |= regop.n | regop.mode | regop.special;
2400 parse_regop (®op, args[3], oP->operand[2]);
2403 regop.mode = regop.special;
2405 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2410 /*****************************************************************************
2412 Replace cobr instruction in a code fragment with equivalent branch and
2413 compare instructions, so it can reach beyond a 13-bit displacement.
2414 Set up an address fix/relocation for the new branch instruction.
2416 *************************************************************************** */
2418 /* This "conditional jump" table maps cobr instructions into
2419 equivalent compare and branch opcodes. */
2428 { /* COBR OPCODE: */
2429 { CHKBIT, BNO }, /* 0x30 - bbc */
2430 { CMPO, BG }, /* 0x31 - cmpobg */
2431 { CMPO, BE }, /* 0x32 - cmpobe */
2432 { CMPO, BGE }, /* 0x33 - cmpobge */
2433 { CMPO, BL }, /* 0x34 - cmpobl */
2434 { CMPO, BNE }, /* 0x35 - cmpobne */
2435 { CMPO, BLE }, /* 0x36 - cmpoble */
2436 { CHKBIT, BO }, /* 0x37 - bbs */
2437 { CMPI, BNO }, /* 0x38 - cmpibno */
2438 { CMPI, BG }, /* 0x39 - cmpibg */
2439 { CMPI, BE }, /* 0x3a - cmpibe */
2440 { CMPI, BGE }, /* 0x3b - cmpibge */
2441 { CMPI, BL }, /* 0x3c - cmpibl */
2442 { CMPI, BNE }, /* 0x3d - cmpibne */
2443 { CMPI, BLE }, /* 0x3e - cmpible */
2444 { CMPI, BO }, /* 0x3f - cmpibo */
2449 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2450 * the cobr instruction, which comes at the
2451 * end of the code fragment.
2454 int opcode, src1, src2, m1, s2;
2455 /* Bit fields from cobr instruction */
2456 long bp_bits; /* Branch prediction bits from cobr instruction */
2457 long instr; /* A single i960 instruction */
2458 /* ->instruction to be replaced */
2460 fixS *fixP; /* Relocation that can be done at assembly time */
2462 /* PICK UP & PARSE COBR INSTRUCTION */
2463 iP = fragP->fr_opcode;
2464 instr = md_chars_to_number (iP, 4);
2465 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2466 src1 = (instr >> 19) & 0x1f;
2467 m1 = (instr >> 13) & 1;
2469 src2 = (instr >> 14) & 0x1f;
2470 bp_bits = instr & BP_MASK;
2472 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2473 instr = coj[opcode].compare
2474 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2475 md_number_to_chars (iP, instr, 4);
2477 /* OUTPUT BRANCH INSTRUCTION */
2478 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2480 /* SET UP ADDRESS FIXUP/RELOCATION */
2481 fixP = fix_new (fragP,
2482 iP + 4 - fragP->fr_literal,
2489 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2495 /*****************************************************************************
2496 reloc_callj: Relocate a 'callj' instruction
2498 This is a "non-(GNU)-standard" machine-dependent hook. The base
2499 assembler calls it when it decides it can relocate an address at
2500 assembly time instead of emitting a relocation directive.
2502 Check to see if the relocation involves a 'callj' instruction to a:
2503 sysproc: Replace the default 'call' instruction with a 'calls'
2504 leafproc: Replace the default 'call' instruction with a 'bal'.
2505 other proc: Do nothing.
2507 See b.out.h for details on the 'n_other' field in a symbol structure.
2510 Assumes the caller has already figured out, in the case of a leafproc,
2511 to use the 'bal' entry point, and has substituted that symbol into the
2512 passed fixup structure.
2514 *************************************************************************** */
2517 /* Relocation that can be done at assembly time */
2520 /* Points to the binary for the instruction being relocated. */
2523 if (!fixP->fx_tcbit)
2525 /* This wasn't a callj instruction in the first place */
2529 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2531 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2533 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2534 procedure number is (other-1). */
2535 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2537 /* Nothing else needs to be done for this instruction. Make
2538 sure 'md_number_to_field()' will perform a no-op. */
2539 fixP->fx_bit_fixP = (bit_fixS *) 1;
2541 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2543 /* Should not happen: see block comment above */
2544 as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2546 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2548 /* Replace 'call' with 'bal'; both instructions have the same
2549 format, so calling code should complete relocation as if
2550 nothing happened here. */
2551 md_number_to_chars (where, BAL, 4);
2553 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2555 as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2556 } /* switch on proc type */
2558 /* else Symbol is neither a sysproc nor a leafproc */
2562 /*****************************************************************************
2563 s_leafproc: process .leafproc pseudo-op
2565 .leafproc takes two arguments, the second one is optional:
2566 arg[1]: name of 'call' entry point to leaf procedure
2567 arg[2]: name of 'bal' entry point to leaf procedure
2569 If the two arguments are identical, or if the second one is missing,
2570 the first argument is taken to be the 'bal' entry point.
2572 If there are 2 distinct arguments, we must make sure that the 'bal'
2573 entry point immediately follows the 'call' entry point in the linked
2576 *************************************************************************** */
2578 s_leafproc (n_ops, args)
2579 int n_ops; /* Number of operands */
2580 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2582 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2583 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2585 if ((n_ops != 1) && (n_ops != 2))
2587 as_bad (_("should have 1 or 2 operands"));
2589 } /* Check number of arguments */
2591 /* Find or create symbol for 'call' entry point. */
2592 callP = symbol_find_or_make (args[1]);
2594 if (TC_S_IS_CALLNAME (callP))
2596 as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2599 /* If that was the only argument, use it as the 'bal' entry point.
2600 * Otherwise, mark it as the 'call' entry point and find or create
2601 * another symbol for the 'bal' entry point.
2603 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2605 TC_S_FORCE_TO_BALNAME (callP);
2610 TC_S_FORCE_TO_CALLNAME (callP);
2612 balP = symbol_find_or_make (args[2]);
2613 if (TC_S_IS_CALLNAME (balP))
2615 as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2617 TC_S_FORCE_TO_BALNAME (balP);
2620 tc_set_bal_of_call (callP, balP);
2622 } /* if only one arg, or the args are the same */
2626 s_sysproc: process .sysproc pseudo-op
2628 .sysproc takes two arguments:
2629 arg[1]: name of entry point to system procedure
2630 arg[2]: 'entry_num' (index) of system procedure in the range
2633 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2634 the symbol. Since that entry is normally 0, we bias 'entrynum'
2635 by adding 1 to it. It must be unbiased before it is used. */
2637 s_sysproc (n_ops, args)
2638 int n_ops; /* Number of operands */
2639 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2646 as_bad (_("should have two operands"));
2648 } /* bad arg count */
2650 /* Parse "entry_num" argument and check it for validity. */
2651 parse_expr (args[2], &exp);
2652 if (exp.X_op != O_constant
2654 || (offs (exp) > 31))
2656 as_bad (_("'entry_num' must be absolute number in [0,31]"));
2660 /* Find/make symbol and stick entry number (biased by +1) into it */
2661 symP = symbol_find_or_make (args[1]);
2663 if (TC_S_IS_SYSPROC (symP))
2665 as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2668 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2669 TC_S_FORCE_TO_SYSPROC (symP);
2672 /*****************************************************************************
2674 Determine if a "shlo" instruction can be used to implement a "ldconst".
2675 This means that some number X < 32 can be shifted left to produce the
2676 constant of interest.
2678 Return the shift count, or 0 if we can't do it.
2679 Caller calculates X by shifting original constant right 'shift' places.
2681 *************************************************************************** */
2684 int n; /* The constant of interest */
2686 int shift; /* The shift count */
2690 /* Can't do it for negative numbers */
2694 /* Shift 'n' right until a 1 is about to be lost */
2695 for (shift = 0; (n & 1) == 0; shift++)
2707 /* syntax: issue syntax error */
2712 as_bad (_("syntax error"));
2717 Return TRUE iff the target architecture supports the specified
2718 special-function register (sfr). */
2722 int n; /* Number (0-31) of sfr */
2724 switch (architecture)
2732 return ((0 <= n) && (n <= 4));
2735 return ((0 <= n) && (n <= 2));
2741 Return TRUE iff the target architecture supports the indicated
2742 class of instructions. */
2744 targ_has_iclass (ic)
2745 /* Instruction class; one of:
2746 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
2750 iclasses_seen |= ic;
2751 switch (architecture)
2754 return ic & (I_BASE | I_KX);
2756 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2758 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2760 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2762 return ic & (I_BASE | I_CX2 | I_JX);
2764 return ic & (I_BASE | I_CX2 | I_JX | I_HX);
2766 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2767 && (iclasses_seen & (I_CX | I_CX2)))
2769 as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
2770 iclasses_seen &= ~ic;
2776 /* Handle the MRI .endian pseudo-op. */
2780 int ignore ATTRIBUTE_UNUSED;
2785 name = input_line_pointer;
2786 c = get_symbol_end ();
2787 if (strcasecmp (name, "little") == 0)
2789 else if (strcasecmp (name, "big") == 0)
2790 as_bad (_("big endian mode is not supported"));
2792 as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2794 *input_line_pointer = c;
2796 demand_empty_rest_of_line ();
2799 /* We have no need to default values of symbols. */
2802 md_undefined_symbol (name)
2803 char *name ATTRIBUTE_UNUSED;
2808 /* Exactly what point is a PC-relative offset relative TO?
2809 On the i960, they're relative to the address of the instruction,
2810 which we have set up as the address of the fixup too. */
2812 md_pcrel_from (fixP)
2815 return fixP->fx_where + fixP->fx_frag->fr_address;
2819 md_apply_fix3 (fixP, valP, seg)
2822 segT seg ATTRIBUTE_UNUSED;
2825 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2827 if (!fixP->fx_bit_fixP)
2829 #ifndef BFD_ASSEMBLER
2830 /* For callx, we always want to write out zero, and emit a
2831 symbolic relocation. */
2835 fixP->fx_addnumber = val;
2838 md_number_to_imm (place, val, fixP->fx_size);
2840 else if ((int) (size_t) fixP->fx_bit_fixP == 13
2841 && fixP->fx_addsy != NULL
2842 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
2844 /* This is a COBR instruction. They have only a
2845 13-bit displacement and are only to be used
2846 for local branches: flag as error, don't generate
2848 as_bad_where (fixP->fx_file, fixP->fx_line,
2849 _("can't use COBR format with external label"));
2850 fixP->fx_addsy = NULL;
2853 md_number_to_field (place, val, fixP->fx_bit_fixP);
2855 if (fixP->fx_addsy == NULL)
2859 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2861 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2864 relax_addressT segment_address_in_file;
2866 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2867 struct relocation_info ri;
2870 memset ((char *) &ri, '\0', sizeof (ri));
2871 symbolP = fixP->fx_addsy;
2872 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2873 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2874 /* These two 'cuz of NS32K */
2875 ri.r_callj = fixP->fx_tcbit;
2876 if (fixP->fx_bit_fixP)
2879 ri.r_length = nbytes_r_length[fixP->fx_size];
2880 ri.r_pcrel = fixP->fx_pcrel;
2881 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2883 if (fixP->fx_r_type != NO_RELOC)
2885 switch (fixP->fx_r_type)
2890 ri.r_length = fixP->fx_size - 1;
2904 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2907 ri.r_index = symbolP->sy_number;
2912 ri.r_index = S_GET_TYPE (symbolP);
2915 /* Output the relocation information in machine-dependent form. */
2916 md_ri_to_chars (where, &ri);
2919 #endif /* OBJ_AOUT or OBJ_BOUT */
2921 #if defined (OBJ_COFF) && defined (BFD)
2923 tc_coff_fix2rtype (fixP)
2929 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2932 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2940 tc_coff_sizemachdep (frag)
2944 return frag->fr_next->fr_address - frag->fr_address;
2950 /* Align an address by rounding it up to the specified boundary. */
2952 md_section_align (seg, addr)
2954 valueT addr; /* Address to be rounded up */
2957 #ifdef BFD_ASSEMBLER
2958 align = bfd_get_section_alignment (stdoutput, seg);
2960 align = section_alignment[(int) seg];
2962 return (addr + (1 << align) - 1) & (-1 << align);
2965 extern int coff_flags;
2969 tc_headers_hook (headers)
2970 object_headers *headers;
2972 switch (architecture)
2975 coff_flags |= F_I960KA;
2979 coff_flags |= F_I960KB;
2983 coff_flags |= F_I960MC;
2987 coff_flags |= F_I960CA;
2991 coff_flags |= F_I960JX;
2995 coff_flags |= F_I960HX;
2999 if (iclasses_seen == I_BASE)
3000 coff_flags |= F_I960CORE;
3001 else if (iclasses_seen & I_CX)
3002 coff_flags |= F_I960CA;
3003 else if (iclasses_seen & I_HX)
3004 coff_flags |= F_I960HX;
3005 else if (iclasses_seen & I_JX)
3006 coff_flags |= F_I960JX;
3007 else if (iclasses_seen & I_CX2)
3008 coff_flags |= F_I960CA;
3009 else if (iclasses_seen & I_MIL)
3010 coff_flags |= F_I960MC;
3011 else if (iclasses_seen & (I_DEC | I_FP))
3012 coff_flags |= F_I960KB;
3014 coff_flags |= F_I960KA;
3018 if (flag_readonly_data_in_text)
3020 headers->filehdr.f_magic = I960RWMAGIC;
3021 headers->aouthdr.magic = OMAGIC;
3025 headers->filehdr.f_magic = I960ROMAGIC;
3026 headers->aouthdr.magic = NMAGIC;
3027 } /* set magic numbers */
3030 #endif /* OBJ_COFF */
3032 #ifndef BFD_ASSEMBLER
3034 /* Things going on here:
3036 For bout, We need to assure a couple of simplifying
3037 assumptions about leafprocs for the linker: the leafproc
3038 entry symbols will be defined in the same assembly in
3039 which they're declared with the '.leafproc' directive;
3040 and if a leafproc has both 'call' and 'bal' entry points
3041 they are both global or both local.
3043 For coff, the call symbol has a second aux entry that
3044 contains the bal entry point. The bal symbol becomes a
3047 For coff representation, the call symbol has a second aux entry that
3048 contains the bal entry point. The bal symbol becomes a label. */
3051 tc_crawl_symbol_chain (headers)
3052 object_headers *headers ATTRIBUTE_UNUSED;
3056 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3059 if (TC_S_IS_SYSPROC (symbolP))
3061 /* second aux entry already contains the sysproc number */
3062 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3063 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3064 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3066 } /* rewrite sysproc */
3067 #endif /* OBJ_COFF */
3069 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3072 } /* Not a leafproc symbol */
3074 if (!S_IS_DEFINED (symbolP))
3076 as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
3077 } /* undefined leaf */
3079 if (TC_S_IS_CALLNAME (symbolP))
3081 symbolS *balP = tc_get_bal_of_call (symbolP);
3082 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3084 S_SET_EXTERNAL (symbolP);
3085 S_SET_EXTERNAL (balP);
3086 as_warn (_("Warning: making leafproc entries %s and %s both global\n"),
3087 S_GET_NAME (symbolP), S_GET_NAME (balP));
3088 } /* externality mismatch */
3090 } /* walk the symbol chain */
3093 #endif /* ! BFD_ASSEMBLER */
3095 /* For aout or bout, the bal immediately follows the call.
3097 For coff, we cheat and store a pointer to the bal symbol in the
3098 second aux entry of the call. */
3109 tc_set_bal_of_call (callP, balP)
3110 symbolS *callP ATTRIBUTE_UNUSED;
3111 symbolS *balP ATTRIBUTE_UNUSED;
3113 know (TC_S_IS_CALLNAME (callP));
3114 know (TC_S_IS_BALNAME (balP));
3118 callP->sy_tc = balP;
3119 S_SET_NUMBER_AUXILIARY (callP, 2);
3121 #else /* ! OBJ_COFF */
3124 /* If the 'bal' entry doesn't immediately follow the 'call'
3125 * symbol, unlink it from the symbol list and re-insert it.
3127 if (symbol_next (callP) != balP)
3129 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3130 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3131 } /* if not in order */
3133 #else /* ! OBJ_ABOUT */
3134 as_fatal ("Only supported for a.out, b.out, or COFF");
3135 #endif /* ! OBJ_ABOUT */
3136 #endif /* ! OBJ_COFF */
3140 tc_get_bal_of_call (callP)
3141 symbolS *callP ATTRIBUTE_UNUSED;
3145 know (TC_S_IS_CALLNAME (callP));
3148 retval = callP->sy_tc;
3151 retval = symbol_next (callP);
3153 as_fatal ("Only supported for a.out, b.out, or COFF");
3154 #endif /* ! OBJ_ABOUT */
3155 #endif /* ! OBJ_COFF */
3157 know (TC_S_IS_BALNAME (retval));
3159 } /* _tc_get_bal_of_call() */
3163 tc_coff_symbol_emit_hook (symbolP)
3164 symbolS *symbolP ATTRIBUTE_UNUSED;
3166 if (TC_S_IS_CALLNAME (symbolP))
3168 symbolS *balP = tc_get_bal_of_call (symbolP);
3170 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3171 if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
3172 S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
3174 S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
3175 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3176 /* fix up the bal symbol */
3177 S_SET_STORAGE_CLASS (balP, C_LABEL);
3178 } /* only on calls */
3180 #endif /* OBJ_COFF */
3183 i960_handle_align (fragp)
3184 fragS *fragp ATTRIBUTE_UNUSED;
3191 as_bad (_("option --link-relax is only supported in b.out format"));
3197 /* The text section "ends" with another alignment reloc, to which we
3198 aren't adding padding. */
3199 if (fragp->fr_next == text_last_frag
3200 || fragp->fr_next == data_last_frag)
3203 /* alignment directive */
3204 fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3205 (int) fragp->fr_type);
3206 #endif /* OBJ_BOUT */
3210 i960_validate_fix (fixP, this_segment_type)
3212 segT this_segment_type ATTRIBUTE_UNUSED;
3214 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
3216 /* Relocation should be done via the associated 'bal'
3217 entry point symbol. */
3219 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
3221 as_bad_where (fixP->fx_file, fixP->fx_line,
3222 _("No 'bal' entry point for leafproc %s"),
3223 S_GET_NAME (fixP->fx_addsy));
3226 fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
3232 #ifdef BFD_ASSEMBLER
3236 static short tc_bfd_fix2rtype PARAMS ((fixS *));
3239 tc_bfd_fix2rtype (fixP)
3242 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
3243 return BFD_RELOC_32;
3245 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
3246 return BFD_RELOC_24_PCREL;
3252 /* Translate internal representation of relocation info to BFD target
3255 FIXME: To what extent can we get all relevant targets to use this? */
3258 tc_gen_reloc (section, fixP)
3259 asection *section ATTRIBUTE_UNUSED;
3264 reloc = (arelent *) xmalloc (sizeof (arelent));
3266 /* HACK: Is this right? */
3267 fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
3269 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
3270 if (reloc->howto == (reloc_howto_type *) NULL)
3272 as_bad_where (fixP->fx_file, fixP->fx_line,
3273 "internal error: can't export reloc type %d (`%s')",
3275 bfd_get_reloc_code_name (fixP->fx_r_type));
3279 assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
3281 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3282 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3283 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
3284 reloc->addend = fixP->fx_addnumber;
3289 /* end from cgen.c */
3291 #endif /* BFD_ASSEMBLER */
3293 /* end of tc-i960.c */