1 /* to sanitize : grep -v XL */
2 /* tc-i960.c - All the i80960-specific stuff
3 Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
5 This file is part of GAS.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /* See comment on md_parse_option for 80960-specific invocation options. */
23 /* There are 4 different lengths of (potentially) symbol-based displacements
24 in the 80960 instruction set, each of which could require address fix-ups
25 and (in the case of external symbols) emission of relocation directives:
28 This is a standard length for the base assembler and requires no
32 This is a non-standard length, but the base assembler has a
33 hook for bit field address fixups: the fixS structure can
34 point to a descriptor of the field, in which case our
35 md_number_to_field() routine gets called to process it.
37 I made the hook a little cleaner by having fix_new() (in the base
38 assembler) return a pointer to the fixS in question. And I made it a
39 little simpler by storing the field size (in this case 13) instead of
40 of a pointer to another structure: 80960 displacements are ALWAYS
41 stored in the low-order bits of a 4-byte word.
43 Since the target of a COBR cannot be external, no relocation
44 directives for this size displacement have to be generated.
45 But the base assembler had to be modified to issue error
46 messages if the symbol did turn out to be external.
49 Fixups are handled as for the 13-bit case (except that 24 is stored
52 The relocation directive generated is the same as that for the 32-bit
53 displacement, except that it's PC-relative (the 32-bit displacement
54 never is). The i80960 version of the linker needs a mod to
55 distinguish and handle the 24-bit case.
58 MEMA formats are always promoted to MEMB (32-bit) if the displacement
59 is based on a symbol, because it could be relocated at link time.
60 The only time we use the 12-bit format is if an absolute value of
61 less than 4096 is specified, in which case we need neither a fixup nor
62 a relocation directive. */
71 #include "opcode/i960.h"
73 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
75 #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
76 #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
77 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
78 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
80 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
81 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
83 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
84 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
85 #define TC_S_FORCE_TO_SYSPROC(s) {;}
87 #else /* ! OBJ_A/BOUT */
90 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
91 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
92 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
93 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
95 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
96 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
98 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
99 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
100 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
102 #else /* ! OBJ_COFF */
104 #endif /* ! OBJ_COFF */
105 #endif /* ! OBJ_A/BOUT */
107 extern char *input_line_pointer;
109 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
111 const int md_reloc_size = sizeof (struct reloc);
113 const int md_reloc_size = sizeof (struct relocation_info);
114 #endif /* OBJ_COFF */
117 /* Local i80960 routines. */
119 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
120 static char *brlab_next (); /* Return next branch local label */
121 void brtab_emit (); /* Emit br-predict instrumentation table */
122 static void cobr_fmt (); /* Generate COBR instruction */
123 static void ctrl_fmt (); /* Generate CTRL instruction */
124 static char *emit (); /* Emit (internally) binary */
125 static int get_args (); /* Break arguments out of comma-separated list */
126 static void get_cdisp (); /* Handle COBR or CTRL displacement */
127 static char *get_ispec (); /* Find index specification string */
128 static int get_regnum (); /* Translate text to register number */
129 static int i_scan (); /* Lexical scan of instruction source */
130 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
131 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
132 static void parse_expr (); /* Parse an expression */
133 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
134 static void parse_memop (); /* Parse a memory operand */
135 static void parse_po (); /* Parse machine-dependent pseudo-op */
136 static void parse_regop (); /* Parse a register operand */
137 static void reg_fmt (); /* Generate a REG format instruction */
138 void reloc_callj (); /* Relocate a 'callj' instruction */
139 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
140 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
141 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
142 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
143 static void syntax (); /* Give syntax error */
144 static int targ_has_sfr (); /* Target chip supports spec-func register? */
145 static int targ_has_iclass (); /* Target chip supports instruction set? */
147 /* See md_parse_option() for meanings of these options */
148 static char norelax; /* True if -norelax switch seen */
149 static char instrument_branches; /* True if -b switch seen */
151 /* Characters that always start a comment.
152 If the pre-processor is disabled, these aren't very useful.
154 const char comment_chars[] = "#";
156 /* Characters that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output.
160 Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output.
165 /* Also note that comments started like this one will always work. */
167 const char line_comment_chars[1];
169 const char line_separator_chars[1];
171 /* Chars that can be used to separate mant from exp in floating point nums */
172 const char EXP_CHARS[] = "eE";
174 /* Chars that mean this number is a floating point constant,
175 as in 0f12.456 or 0d1.2345e12
177 const char FLT_CHARS[] = "fFdDtT";
180 /* Table used by base assembler to relax addresses based on varying length
181 instructions. The fields are:
182 1) most positive reach of this state,
183 2) most negative reach of this state,
184 3) how many bytes this mode will add to the size of the current frag
185 4) which index into the table to try if we can't fit into this one.
187 For i80960, the only application is the (de-)optimization of cobr
188 instructions into separate compare and branch instructions when a 13-bit
189 displacement won't hack it.
191 const relax_typeS md_relax_table[] =
193 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
194 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
195 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
198 static void s_endian PARAMS ((int));
200 /* These are the machine dependent pseudo-ops.
202 This table describes all the machine specific pseudo-ops the assembler
203 has to support. The fields are:
204 pseudo-op name without dot
205 function to call to execute this pseudo-op
206 integer arg to pass to the function
211 const pseudo_typeS md_pseudo_table[] =
214 {"endian", s_endian, 0},
215 {"extended", float_cons, 't'},
216 {"leafproc", parse_po, S_LEAFPROC},
217 {"sysproc", parse_po, S_SYSPROC},
225 /* Macros to extract info from an 'expressionS' structure 'e' */
226 #define adds(e) e.X_add_symbol
227 #define offs(e) e.X_add_number
230 /* Branch-prediction bits for CTRL/COBR format opcodes */
231 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
232 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
233 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
236 /* Some instruction opcodes that we need explicitly */
237 #define BE 0x12000000
238 #define BG 0x11000000
239 #define BGE 0x13000000
240 #define BL 0x14000000
241 #define BLE 0x16000000
242 #define BNE 0x15000000
243 #define BNO 0x10000000
244 #define BO 0x17000000
245 #define CHKBIT 0x5a002700
246 #define CMPI 0x5a002080
247 #define CMPO 0x5a002000
250 #define BAL 0x0b000000
251 #define CALL 0x09000000
252 #define CALLS 0x66003800
253 #define RET 0x0a000000
256 /* These masks are used to build up a set of MEMB mode bits. */
259 #define MEMB_BIT 0x1000
263 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
265 #define MEMA_ABASE 0x2000
267 /* Info from which a MEMA or MEMB format instruction can be generated */
270 /* (First) 32 bits of instruction */
272 /* 0-(none), 12- or, 32-bit displacement needed */
274 /* The expression in the source instruction from which the
275 displacement should be determined. */
282 /* The two pieces of info we need to generate a register operand */
285 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
286 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
287 int n; /* Register number or literal value */
291 /* Number and assembler mnemonic for all registers that can appear in
333 /* Numbers for special-function registers are for assembler internal
334 use only: they are scaled back to range [0-31] for binary output. */
370 /* Numbers for floating point registers are for assembler internal
371 use only: they are scaled back to [0-3] for binary output. */
379 { NULL, 0 }, /* END OF LIST */
382 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
383 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
384 #define IS_FP_REG(n) ((n) >= FP0)
386 /* Number and assembler mnemonic for all registers that can appear as
387 'abase' (indirect addressing) registers. */
429 /* For assembler internal use only: this number never appears in binary
433 { NULL, 0 }, /* END OF LIST */
438 static struct hash_control *op_hash; /* Opcode mnemonics */
439 static struct hash_control *reg_hash; /* Register name hash table */
440 static struct hash_control *areg_hash; /* Abase register hash table */
443 /* Architecture for which we are assembling */
444 #define ARCH_ANY 0 /* Default: no architecture checking done */
450 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
451 int iclasses_seen; /* OR of instruction classes (I_* constants)
452 * for which we've actually assembled
457 /* BRANCH-PREDICTION INSTRUMENTATION
459 The following supports generation of branch-prediction instrumentation
460 (turned on by -b switch). The instrumentation collects counts
461 of branches taken/not-taken for later input to a utility that will
462 set the branch prediction bits of the instructions in accordance with
463 the behavior observed. (Note that the KX series does not have
466 The instrumentation consists of:
468 (1) before and after each conditional branch, a call to an external
469 routine that increments and steps over an inline counter. The
470 counter itself, initialized to 0, immediately follows the call
471 instruction. For each branch, the counter following the branch
472 is the number of times the branch was not taken, and the difference
473 between the counters is the number of times it was taken. An
474 example of an instrumented conditional branch:
482 (2) a table of pointers to the instrumented branches, so that an
483 external postprocessing routine can locate all of the counters.
484 the table begins with a 2-word header: a pointer to the next in
485 a linked list of such tables (initialized to 0); and a count
486 of the number of entries in the table (exclusive of the header.
488 Note that input source code is expected to already contain calls
489 an external routine that will link the branch local table into a
493 /* Number of branches instrumented so far. Also used to generate
494 unique local labels for each instrumented branch. */
497 #define BR_LABEL_BASE "LBRANCH"
498 /* Basename of local labels on instrumented branches, to avoid
499 conflict with compiler- generated local labels. */
501 #define BR_CNT_FUNC "__inc_branch"
502 /* Name of the external routine that will increment (and step over) an
505 #define BR_TAB_NAME "__BRANCH_TABLE__"
506 /* Name of the table of pointers to branches. A local (i.e.,
507 non-external) symbol. */
509 /*****************************************************************************
510 md_begin: One-time initialization.
514 *************************************************************************** */
518 int i; /* Loop counter */
519 const struct i960_opcode *oP; /* Pointer into opcode table */
520 const char *retval; /* Value returned by hash functions */
522 op_hash = hash_new ();
523 reg_hash = hash_new ();
524 areg_hash = hash_new ();
526 /* For some reason, the base assembler uses an empty string for "no
527 error message", instead of a NULL pointer. */
530 for (oP = i960_opcodes; oP->name && !retval; oP++)
531 retval = hash_insert (op_hash, oP->name, (PTR) oP);
533 for (i = 0; regnames[i].reg_name && !retval; i++)
534 retval = hash_insert (reg_hash, regnames[i].reg_name,
535 (char *) ®names[i].reg_num);
537 for (i = 0; aregs[i].areg_name && !retval; i++)
538 retval = hash_insert (areg_hash, aregs[i].areg_name,
539 (char *) &aregs[i].areg_num);
542 as_fatal ("Hashing returned \"%s\".", retval);
545 /*****************************************************************************
546 md_assemble: Assemble an instruction
548 Assumptions about the passed-in text:
549 - all comments, labels removed
550 - text is an instruction
551 - all white space compressed to single blanks
552 - all character constants have been replaced with decimal
554 *************************************************************************** */
557 char *textP; /* Source text of instruction */
559 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
560 mnemonic arg[1-3]->operands, with char constants replaced by
564 int n_ops; /* Number of instruction operands */
565 /* Pointer to instruction description */
566 struct i960_opcode *oP;
567 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
570 /* Setting of branch-prediction bit(s) to be OR'd into instruction
571 opcode of CTRL/COBR format instructions. */
574 int n; /* Offset of last character in opcode mnemonic */
576 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
579 /* Parse instruction into opcode and operands */
580 memset (args, '\0', sizeof (args));
581 n_ops = i_scan (textP, args);
584 return; /* Error message already issued */
587 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
588 if (!strcmp (args[0], "ldconst"))
590 n_ops = parse_ldconst (args);
599 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
600 n = strlen (args[0]) - 1;
603 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
605 /* We could check here to see if the target architecture
606 supports branch prediction, but why bother? The bit will
607 just be ignored by processors that don't use it. */
609 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
610 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
613 /* Look up opcode mnemonic in table and check number of operands.
614 Check that opcode is legal for the target architecture. If all
615 looks good, assemble instruction. */
616 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
617 if (!oP || !targ_has_iclass (oP->iclass))
619 as_bad ("invalid opcode, \"%s\".", args[0]);
622 else if (n_ops != oP->num_ops)
624 as_bad ("improper number of operands. expecting %d, got %d",
633 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
634 if (oP->format == FBRA)
636 /* Now generate a 'bno' to same arg */
637 ctrl_fmt (args[1], BNO | bp_bits, 1);
642 cobr_fmt (args, oP->opcode | bp_bits, oP);
647 as_warn (bp_error_msg);
652 if (args[0][0] == 'c' && args[0][1] == 'a')
656 as_warn (bp_error_msg);
658 mem_fmt (args, oP, 1);
668 as_warn (bp_error_msg);
670 mem_fmt (args, oP, 0);
675 as_warn (bp_error_msg);
677 /* Output opcode & set up "fixup" (relocation); flag
678 relocation as 'callj' type. */
679 know (oP->num_ops == 1);
680 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
683 BAD_CASE (oP->format);
687 } /* md_assemble() */
689 /*****************************************************************************
690 md_number_to_chars: convert a number to target byte order
692 *************************************************************************** */
694 md_number_to_chars (buf, value, n)
699 number_to_chars_littleendian (buf, value, n);
702 /*****************************************************************************
703 md_chars_to_number: convert from target byte order to host byte order.
705 *************************************************************************** */
707 md_chars_to_number (val, n)
708 unsigned char *val; /* Value in target byte order */
709 int n; /* Number of bytes in the input */
713 for (retval = 0; n--;)
722 #define MAX_LITTLENUMS 6
723 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
725 /*****************************************************************************
726 md_atof: convert ascii to floating point
728 Turn a string at input_line_pointer into a floating point constant of type
729 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
730 emitted is returned at 'sizeP'. An error message is returned, or a pointer
731 to an empty message if OK.
733 Note we call the i386 floating point routine, rather than complicating
734 things with more files or symbolic links.
736 *************************************************************************** */
738 md_atof (type, litP, sizeP)
743 LITTLENUM_TYPE words[MAX_LITTLENUMS];
744 LITTLENUM_TYPE *wordP;
764 type = 'x'; /* That's what atof_ieee() understands */
769 return "Bad call to md_atof()";
772 t = atof_ieee (input_line_pointer, type, words);
775 input_line_pointer = t;
778 *sizeP = prec * LNUM_SIZE;
780 /* Output the LITTLENUMs in REVERSE order in accord with i80960
781 word-order. (Dunno why atof_ieee doesn't do it in the right
782 order in the first place -- probably because it's a hack of
785 for (wordP = words + prec - 1; prec--;)
787 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
788 litP += sizeof (LITTLENUM_TYPE);
795 /*****************************************************************************
798 *************************************************************************** */
800 md_number_to_imm (buf, val, n)
805 md_number_to_chars (buf, val, n);
809 /*****************************************************************************
812 *************************************************************************** */
814 md_number_to_disp (buf, val, n)
819 md_number_to_chars (buf, val, n);
822 /*****************************************************************************
825 Stick a value (an address fixup) into a bit field of
826 previously-generated instruction.
828 *************************************************************************** */
830 md_number_to_field (instrP, val, bfixP)
831 char *instrP; /* Pointer to instruction to be fixed */
832 long val; /* Address fixup value */
833 bit_fixS *bfixP; /* Description of bit field to be fixed up */
835 int numbits; /* Length of bit field to be fixed */
836 long instr; /* 32-bit instruction to be fixed-up */
837 long sign; /* 0 or -1, according to sign bit of 'val' */
839 /* Convert instruction back to host byte order. */
840 instr = md_chars_to_number (instrP, 4);
842 /* Surprise! -- we stored the number of bits to be modified rather
843 than a pointer to a structure. */
844 numbits = (int) bfixP;
847 /* This is a no-op, stuck here by reloc_callj() */
851 know ((numbits == 13) || (numbits == 24));
853 /* Propagate sign bit of 'val' for the given number of bits. Result
854 should be all 0 or all 1. */
855 sign = val >> ((int) numbits - 1);
856 if (((val < 0) && (sign != -1))
857 || ((val > 0) && (sign != 0)))
859 as_bad ("Fixup of %ld too large for field width of %d",
864 /* Put bit field into instruction and write back in target
867 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
869 md_number_to_chars (instrP, instr, 4);
871 } /* md_number_to_field() */
874 /*****************************************************************************
876 Invocation line includes a switch not recognized by the base assembler.
877 See if it's a processor-specific option. For the 960, these are:
880 Conditional branch instructions that require displacements
881 greater than 13 bits (or that have external targets) should
882 generate errors. The default is to replace each such
883 instruction with the corresponding compare (or chkbit) and
884 branch instructions. Note that the Intel "j" cobr directives
885 are ALWAYS "de-optimized" in this way when necessary,
886 regardless of the setting of this option.
889 Add code to collect information about branches taken, for
890 later optimization of branch prediction bits by a separate
891 tool. COBR and CNTL format instructions have branch
892 prediction bits (in the CX architecture); if "BR" represents
893 an instruction in one of these classes, the following rep-
894 resents the code generated by the assembler:
896 call <increment routine>
897 .word 0 # pre-counter
899 call <increment routine>
900 .word 0 # post-counter
902 A table of all such "Labels" is also generated.
905 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
906 Select the 80960 architecture. Instructions or features not
907 supported by the selected architecture cause fatal errors.
908 The default is to generate code for any instruction or feature
909 that is supported by SOME version of the 960 (even if this
910 means mixing architectures!).
912 ****************************************************************************/
914 CONST char *md_shortopts = "A:b";
915 struct option md_longopts[] =
917 #define OPTION_LINKRELAX (OPTION_MD_BASE)
918 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
919 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
920 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
921 {"norelax", no_argument, NULL, OPTION_NORELAX},
922 {"no-relax", no_argument, NULL, OPTION_NORELAX},
923 {NULL, no_argument, NULL, 0}
925 size_t md_longopts_size = sizeof (md_longopts);
932 static const struct tabentry arch_tab[] =
936 {"SA", ARCH_KA}, /* Synonym for KA */
937 {"SB", ARCH_KB}, /* Synonym for KB */
938 {"KC", ARCH_MC}, /* Synonym for MC */
946 md_parse_option (c, arg)
952 case OPTION_LINKRELAX:
954 flag_keep_locals = 1;
962 instrument_branches = 1;
967 const struct tabentry *tp;
970 for (tp = arch_tab; tp->flag != NULL; tp++)
971 if (!strcmp (p, tp->flag))
974 if (tp->flag == NULL)
976 as_bad ("invalid architecture %s", p);
980 architecture = tp->arch;
992 md_show_usage (stream)
996 fprintf (stream, "I960 options:\n");
997 for (i = 0; arch_tab[i].flag; i++)
998 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
999 fprintf (stream, "\n\
1000 specify variant of 960 architecture\n\
1001 -b add code to collect statistics about branches taken\n\
1002 -link-relax preserve individual alignment directives so linker\n\
1003 can do relaxing (b.out format only)\n\
1004 -no-relax don't alter compare-and-branch instructions for\n\
1005 long displacements\n");
1009 #ifndef BFD_ASSEMBLER
1010 /*****************************************************************************
1012 Called by base assembler after address relaxation is finished: modify
1013 variable fragments according to how much relaxation was done.
1015 If the fragment substate is still 1, a 13-bit displacement was enough
1016 to reach the symbol in question. Set up an address fixup, but otherwise
1017 leave the cobr instruction alone.
1019 If the fragment substate is 2, a 13-bit displacement was not enough.
1020 Replace the cobr with a two instructions (a compare and a branch).
1022 *************************************************************************** */
1024 md_convert_frag (headers, seg, fragP)
1025 object_headers *headers;
1029 fixS *fixP; /* Structure describing needed address fix */
1031 switch (fragP->fr_subtype)
1034 /* LEAVE SINGLE COBR INSTRUCTION */
1035 fixP = fix_new (fragP,
1036 fragP->fr_opcode - fragP->fr_literal,
1043 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1046 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1050 BAD_CASE (fragP->fr_subtype);
1055 /*****************************************************************************
1056 md_estimate_size_before_relax: How much does it look like *fragP will grow?
1058 Called by base assembler just before address relaxation.
1059 Return the amount by which the fragment will grow.
1061 Any symbol that is now undefined will not become defined; cobr's
1062 based on undefined symbols will have to be replaced with a compare
1063 instruction and a branch instruction, and the code fragment will grow
1066 *************************************************************************** */
1068 md_estimate_size_before_relax (fragP, segment_type)
1069 register fragS *fragP;
1070 register segT segment_type;
1072 /* If symbol is undefined in this segment, go to "relaxed" state
1073 (compare and branch instructions instead of cobr) right now. */
1074 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1080 } /* md_estimate_size_before_relax() */
1083 /*****************************************************************************
1085 This routine exists in order to overcome machine byte-order problems
1086 when dealing with bit-field entries in the relocation_info struct.
1088 But relocation info will be used on the host machine only (only
1089 executable code is actually downloaded to the i80960). Therefore,
1090 we leave it in host byte order.
1092 The above comment is no longer true. This routine now really
1093 does do the reordering (Ian Taylor 28 Aug 92).
1095 *************************************************************************** */
1097 md_ri_to_chars (where, ri)
1099 struct relocation_info *ri;
1101 md_number_to_chars (where, ri->r_address,
1102 sizeof (ri->r_address));
1103 where[4] = ri->r_index & 0x0ff;
1104 where[5] = (ri->r_index >> 8) & 0x0ff;
1105 where[6] = (ri->r_index >> 16) & 0x0ff;
1106 where[7] = ((ri->r_pcrel << 0)
1107 | (ri->r_length << 1)
1108 | (ri->r_extern << 3)
1111 | (ri->r_callj << 6));
1114 #ifndef WORKING_DOT_WORD
1116 int md_short_jump_size = 0;
1117 int md_long_jump_size = 0;
1120 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1127 as_fatal ("failed sanity check.");
1131 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1133 addressT from_addr, to_addr;
1137 as_fatal ("failed sanity check.");
1141 #endif /* BFD_ASSEMBLER */
1143 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */
1145 /*****************************************************************************
1146 brcnt_emit: Emit code to increment inline branch counter.
1148 See the comments above the declaration of 'br_cnt' for details on
1149 branch-prediction instrumentation.
1150 *************************************************************************** */
1154 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1155 emit (0); /* Emit inline counter to be incremented */
1158 /*****************************************************************************
1159 brlab_next: generate the next branch local label
1161 See the comments above the declaration of 'br_cnt' for details on
1162 branch-prediction instrumentation.
1163 *************************************************************************** */
1167 static char buf[20];
1169 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1173 /*****************************************************************************
1174 brtab_emit: generate the fetch-prediction branch table.
1176 See the comments above the declaration of 'br_cnt' for details on
1177 branch-prediction instrumentation.
1179 The code emitted here would be functionally equivalent to the following
1180 example assembler source.
1185 .word 0 # link to next table
1186 .word 3 # length of table
1187 .word LBRANCH0 # 1st entry in table proper
1190 **************************************************************************** */
1196 char *p; /* Where the binary was output to */
1197 /* Pointer to description of deferred address fixup. */
1200 if (!instrument_branches)
1205 subseg_set (data_section, 0); /* .data */
1206 frag_align (2, 0); /* .align 2 */
1207 record_alignment (now_seg, 2);
1208 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1209 emit (0); /* .word 0 #link to next table */
1210 emit (br_cnt); /* .word n #length of table */
1212 for (i = 0; i < br_cnt; i++)
1214 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1216 fixP = fix_new (frag_now,
1217 p - frag_now->fr_literal,
1223 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1227 /*****************************************************************************
1228 cobr_fmt: generate a COBR-format instruction
1230 *************************************************************************** */
1233 cobr_fmt (arg, opcode, oP)
1234 /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1236 /* Opcode, with branch-prediction bits already set if necessary. */
1238 /* Pointer to description of instruction. */
1239 struct i960_opcode *oP;
1241 long instr; /* 32-bit instruction */
1242 struct regop regop; /* Description of register operand */
1243 int n; /* Number of operands */
1244 int var_frag; /* 1 if varying length code fragment should
1245 * be emitted; 0 if an address fix
1246 * should be emitted.
1254 /* First operand (if any) of a COBR is always a register
1255 operand. Parse it. */
1256 parse_regop (®op, arg[1], oP->operand[0]);
1257 instr |= (regop.n << 19) | (regop.mode << 13);
1261 /* Second operand (if any) of a COBR is always a register
1262 operand. Parse it. */
1263 parse_regop (®op, arg[2], oP->operand[1]);
1264 instr |= (regop.n << 14) | regop.special;
1275 if (instrument_branches)
1278 colon (brlab_next ());
1281 /* A third operand to a COBR is always a displacement. Parse
1282 it; if it's relaxable (a cobr "j" directive, or any cobr
1283 other than bbs/bbc when the "-norelax" option is not in use)
1284 set up a variable code fragment; otherwise set up an address
1286 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1287 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1289 if (instrument_branches)
1297 /*****************************************************************************
1298 ctrl_fmt: generate a CTRL-format instruction
1300 *************************************************************************** */
1303 ctrl_fmt (targP, opcode, num_ops)
1304 char *targP; /* Pointer to text of lone operand (if any) */
1305 long opcode; /* Template of instruction */
1306 int num_ops; /* Number of operands */
1308 int instrument; /* TRUE iff we should add instrumentation to track
1309 * how often the branch is taken
1315 emit (opcode); /* Output opcode */
1320 instrument = instrument_branches && (opcode != CALL)
1321 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1326 colon (brlab_next ());
1329 /* The operand MUST be an ip-relative displacment. Parse it
1330 * and set up address fix for the instruction we just output.
1332 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1343 /*****************************************************************************
1344 emit: output instruction binary
1346 Output instruction binary, in target byte order, 4 bytes at a time.
1347 Return pointer to where it was placed.
1349 *************************************************************************** */
1353 long instr; /* Word to be output, host byte order */
1355 char *toP; /* Where to output it */
1357 toP = frag_more (4); /* Allocate storage */
1358 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1363 /*****************************************************************************
1364 get_args: break individual arguments out of comma-separated list
1367 - all comments and labels have been removed
1368 - all strings of whitespace have been collapsed to a single blank.
1369 - all character constants ('x') have been replaced with decimal
1372 args[0] is untouched. args[1] points to first operand, etc. All args:
1373 - are NULL-terminated
1374 - contain no whitespace
1377 Number of operands (0,1,2, or 3) or -1 on error.
1379 *************************************************************************** */
1382 /* Pointer to comma-separated operands; MUCKED BY US */
1384 /* Output arg: pointers to operands placed in args[1-3]. MUST
1385 ACCOMMODATE 4 ENTRIES (args[0-3]). */
1388 register int n; /* Number of operands */
1391 /* Skip lead white space */
1405 /* Squeze blanks out by moving non-blanks toward start of string.
1406 * Isolate operands, whenever comma is found.
1413 && (! isalnum (p[1]) || ! isalnum (p[-1])))
1421 /* Start of operand */
1424 as_bad ("too many operands");
1427 *to++ = '\0'; /* Terminate argument */
1428 args[++n] = to; /* Start next argument */
1442 /*****************************************************************************
1443 get_cdisp: handle displacement for a COBR or CTRL instruction.
1445 Parse displacement for a COBR or CTRL instruction.
1447 If successful, output the instruction opcode and set up for it,
1448 depending on the arg 'var_frag', either:
1449 o an address fixup to be done when all symbol values are known, or
1450 o a varying length code fragment, with address fixup info. This
1451 will be done for cobr instructions that may have to be relaxed
1452 in to compare/branch instructions (8 bytes) if the final
1453 address displacement is greater than 13 bits.
1455 ****************************************************************************/
1458 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1459 /* displacement as specified in source instruction */
1461 /* "COBR" or "CTRL" (for use in error message) */
1463 /* Instruction needing the displacement */
1465 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1467 /* 1 if varying length code fragment should be emitted;
1468 * 0 if an address fix should be emitted.
1471 /* 1 if callj relocation should be done; else 0 */
1474 expressionS e; /* Parsed expression */
1475 fixS *fixP; /* Structure describing needed address fix */
1476 char *outP; /* Where instruction binary is output to */
1480 parse_expr (dispP, &e);
1484 as_bad ("expression syntax error");
1487 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1488 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1492 outP = frag_more (8); /* Allocate worst-case storage */
1493 md_number_to_chars (outP, instr, 4);
1494 frag_variant (rs_machine_dependent, 4, 4, 1,
1495 adds (e), offs (e), outP);
1499 /* Set up a new fix structure, so address can be updated
1500 * when all symbol values are known.
1502 outP = emit (instr);
1503 fixP = fix_new (frag_now,
1504 outP - frag_now->fr_literal,
1511 fixP->fx_tcbit = callj;
1513 /* We want to modify a bit field when the address is
1514 * known. But we don't need all the garbage in the
1515 * bit_fix structure. So we're going to lie and store
1516 * the number of bits affected instead of a pointer.
1518 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1522 as_bad ("attempt to branch into different segment");
1526 as_bad ("target of %s instruction must be a label", ifmtP);
1532 /*****************************************************************************
1533 get_ispec: parse a memory operand for an index specification
1535 Here, an "index specification" is taken to be anything surrounded
1536 by square brackets and NOT followed by anything else.
1538 If it's found, detach it from the input string, remove the surrounding
1539 square brackets, and return a pointer to it. Otherwise, return NULL.
1541 *************************************************************************** */
1545 /* Pointer to memory operand from source instruction, no white space. */
1548 /* Points to start of index specification. */
1550 /* Points to end of index specification. */
1553 /* Find opening square bracket, if any. */
1554 start = strchr (textP, '[');
1559 /* Eliminate '[', detach from rest of operand */
1562 end = strchr (start, ']');
1566 as_bad ("unmatched '['");
1571 /* Eliminate ']' and make sure it was the last thing
1575 if (*(end + 1) != '\0')
1577 as_bad ("garbage after index spec ignored");
1584 /*****************************************************************************
1587 Look up a (suspected) register name in the register table and return the
1588 associated register number (or -1 if not found).
1590 *************************************************************************** */
1593 get_regnum (regname)
1594 char *regname; /* Suspected register name */
1598 rP = (int *) hash_find (reg_hash, regname);
1599 return (rP == NULL) ? -1 : *rP;
1603 /*****************************************************************************
1604 i_scan: perform lexical scan of ascii assembler instruction.
1607 - input string is an i80960 instruction (not a pseudo-op)
1608 - all comments and labels have been removed
1609 - all strings of whitespace have been collapsed to a single blank.
1612 args[0] points to opcode, other entries point to operands. All strings:
1613 - are NULL-terminated
1614 - contain no whitespace
1615 - have character constants ('x') replaced with a decimal number
1618 Number of operands (0,1,2, or 3) or -1 on error.
1620 *************************************************************************** */
1623 /* Pointer to ascii instruction; MUCKED BY US. */
1625 /* Output arg: pointers to opcode and operands placed here. MUST
1626 ACCOMMODATE 4 ENTRIES. */
1630 /* Isolate opcode */
1634 } /* Skip lead space, if any */
1636 for (; *iP != ' '; iP++)
1640 /* There are no operands */
1643 /* We never moved: there was no opcode either! */
1644 as_bad ("missing opcode");
1650 *iP++ = '\0'; /* Terminate opcode */
1651 return (get_args (iP, args));
1655 /*****************************************************************************
1656 mem_fmt: generate a MEMA- or MEMB-format instruction
1658 *************************************************************************** */
1660 mem_fmt (args, oP, callx)
1661 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1662 struct i960_opcode *oP; /* Pointer to description of instruction */
1663 int callx; /* Is this a callx opcode */
1665 int i; /* Loop counter */
1666 struct regop regop; /* Description of register operand */
1667 char opdesc; /* Operand descriptor byte */
1668 memS instr; /* Description of binary to be output */
1669 char *outP; /* Where the binary was output to */
1670 expressionS expr; /* Parsed expression */
1671 /* ->description of deferred address fixup */
1675 /* COFF support isn't in place yet for callx relaxing. */
1679 memset (&instr, '\0', sizeof (memS));
1680 instr.opcode = oP->opcode;
1682 /* Process operands. */
1683 for (i = 1; i <= oP->num_ops; i++)
1685 opdesc = oP->operand[i - 1];
1689 parse_memop (&instr, args[i], oP->format);
1693 parse_regop (®op, args[i], opdesc);
1694 instr.opcode |= regop.n << 19;
1699 outP = emit (instr.opcode);
1701 if (instr.disp == 0)
1706 /* Parse and process the displacement */
1707 parse_expr (instr.e, &expr);
1711 as_bad ("expression syntax error");
1715 if (instr.disp == 32)
1717 (void) emit (offs (expr)); /* Output displacement */
1721 /* 12-bit displacement */
1722 if (offs (expr) & ~0xfff)
1724 /* Won't fit in 12 bits: convert already-output
1725 * instruction to MEMB format, output
1728 mema_to_memb (outP);
1729 (void) emit (offs (expr));
1733 /* WILL fit in 12 bits: OR into opcode and
1734 * overwrite the binary we already put out
1736 instr.opcode |= offs (expr);
1737 md_number_to_chars (outP, instr.opcode, 4);
1743 if (instr.disp == 12)
1745 /* Displacement is dependent on a symbol, whose value
1746 * may change at link time. We HAVE to reserve 32 bits.
1747 * Convert already-output opcode to MEMB format.
1749 mema_to_memb (outP);
1752 /* Output 0 displacement and set up address fixup for when
1753 * this symbol's value becomes known.
1755 outP = emit ((long) 0);
1756 fixP = fix_new_exp (frag_now,
1757 outP - frag_now->fr_literal,
1762 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1763 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1764 being in the instruction stream, specifically as part of a callx
1766 fixP->fx_bsr = callx;
1772 /*****************************************************************************
1773 mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1775 There are 2 possible MEMA formats:
1777 - displacement + abase
1779 They are distinguished by the setting of the MEMA_ABASE bit.
1781 *************************************************************************** */
1783 mema_to_memb (opcodeP)
1784 char *opcodeP; /* Where to find the opcode, in target byte order */
1786 long opcode; /* Opcode in host byte order */
1787 long mode; /* Mode bits for MEMB instruction */
1789 opcode = md_chars_to_number (opcodeP, 4);
1790 know (!(opcode & MEMB_BIT));
1792 mode = MEMB_BIT | D_BIT;
1793 if (opcode & MEMA_ABASE)
1798 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1799 opcode |= mode; /* Set MEMB mode bits */
1801 md_number_to_chars (opcodeP, opcode, 4);
1802 } /* mema_to_memb() */
1805 /*****************************************************************************
1806 parse_expr: parse an expression
1808 Use base assembler's expression parser to parse an expression.
1809 It, unfortunately, runs off a global which we have to save/restore
1810 in order to make it work for us.
1812 An empty expression string is treated as an absolute 0.
1814 Sets O_illegal regardless of expression evaluation if entire input
1815 string is not consumed in the evaluation -- tolerate no dangling junk!
1817 *************************************************************************** */
1819 parse_expr (textP, expP)
1820 char *textP; /* Text of expression to be parsed */
1821 expressionS *expP; /* Where to put the results of parsing */
1823 char *save_in; /* Save global here */
1830 /* Treat empty string as absolute 0 */
1831 expP->X_add_symbol = expP->X_op_symbol = NULL;
1832 expP->X_add_number = 0;
1833 expP->X_op = O_constant;
1837 save_in = input_line_pointer; /* Save global */
1838 input_line_pointer = textP; /* Make parser work for us */
1840 (void) expression (expP);
1841 if (input_line_pointer - textP != strlen (textP))
1843 /* Did not consume all of the input */
1844 expP->X_op = O_illegal;
1846 symP = expP->X_add_symbol;
1847 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1849 /* Register name in an expression */
1850 /* FIXME: this isn't much of a check any more. */
1851 expP->X_op = O_illegal;
1854 input_line_pointer = save_in; /* Restore global */
1859 /*****************************************************************************
1861 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1864 Assumes the input consists of:
1865 arg[0] opcode mnemonic ('ldconst')
1866 arg[1] first operand (constant)
1867 arg[2] name of register to be loaded
1869 Replaces opcode and/or operands as appropriate.
1871 Returns the new number of arguments, or -1 on failure.
1873 *************************************************************************** */
1877 char *arg[]; /* See above */
1879 int n; /* Constant to be loaded */
1880 int shift; /* Shift count for "shlo" instruction */
1881 static char buf[5]; /* Literal for first operand */
1882 static char buf2[5]; /* Literal for second operand */
1883 expressionS e; /* Parsed expression */
1886 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1888 parse_expr (arg[1], &e);
1892 /* We're dependent on one or more symbols -- use "lda" */
1897 /* Try the following mappings:
1898 * ldconst 0,<reg> ->mov 0,<reg>
1899 * ldconst 31,<reg> ->mov 31,<reg>
1900 * ldconst 32,<reg> ->addo 1,31,<reg>
1901 * ldconst 62,<reg> ->addo 31,31,<reg>
1902 * ldconst 64,<reg> ->shlo 8,3,<reg>
1903 * ldconst -1,<reg> ->subo 1,0,<reg>
1904 * ldconst -31,<reg>->subo 31,0,<reg>
1906 * anthing else becomes:
1910 if ((0 <= n) && (n <= 31))
1915 else if ((-31 <= n) && (n <= -1))
1919 sprintf (buf, "%d", -n);
1924 else if ((32 <= n) && (n <= 62))
1929 sprintf (buf, "%d", n - 31);
1933 else if ((shift = shift_ok (n)) != 0)
1937 sprintf (buf, "%d", shift);
1939 sprintf (buf2, "%d", n >> shift);
1950 as_bad ("invalid constant");
1954 return (arg[3] == 0) ? 2 : 3;
1957 /*****************************************************************************
1958 parse_memop: parse a memory operand
1960 This routine is based on the observation that the 4 mode bits of the
1961 MEMB format, taken individually, have fairly consistent meaning:
1963 M3 (bit 13): 1 if displacement is present (D_BIT)
1964 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1965 M1 (bit 11): 1 if index is present (I_BIT)
1966 M0 (bit 10): 1 if abase is present (A_BIT)
1968 So we parse the memory operand and set bits in the mode as we find
1969 things. Then at the end, if we go to MEMB format, we need only set
1970 the MEMB bit (M2) and our mode is built for us.
1972 Unfortunately, I said "fairly consistent". The exceptions:
1975 0100 Would seem illegal, but means "abase-only".
1977 0101 Would seem to mean "abase-only" -- it means IP-relative.
1978 Must be converted to 0100.
1980 0110 Would seem to mean "index-only", but is reserved.
1981 We turn on the D bit and provide a 0 displacement.
1983 The other thing to observe is that we parse from the right, peeling
1984 things * off as we go: first any index spec, then any abase, then
1987 *************************************************************************** */
1990 parse_memop (memP, argP, optype)
1991 memS *memP; /* Where to put the results */
1992 char *argP; /* Text of the operand to be parsed */
1993 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1995 char *indexP; /* Pointer to index specification with "[]" removed */
1996 char *p; /* Temp char pointer */
1997 char iprel_flag; /* True if this is an IP-relative operand */
1998 int regnum; /* Register number */
1999 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
2000 (0,1,2,3,4 respectively). */
2002 int mode; /* MEMB mode bits */
2003 int *intP; /* Pointer to register number */
2005 /* The following table contains the default scale factors for each
2006 type of memory instruction. It is accessed using (optype-MEM1)
2007 as an index -- thus it assumes the 'optype' constants are
2008 assigned consecutive values, in the order they appear in this
2010 static const int def_scale[] =
2016 -1, /* MEM12 -- no valid default */
2021 iprel_flag = mode = 0;
2023 /* Any index present? */
2024 indexP = get_ispec (argP);
2027 p = strchr (indexP, '*');
2030 /* No explicit scale -- use default for this instruction
2031 type and assembler mode. */
2035 /* GNU960 compatibility */
2036 scale = def_scale[optype - MEM1];
2040 *p++ = '\0'; /* Eliminate '*' */
2042 /* Now indexP->a '\0'-terminated register name,
2043 * and p->a scale factor.
2046 if (!strcmp (p, "16"))
2050 else if (strchr ("1248", *p) && (p[1] == '\0'))
2060 regnum = get_regnum (indexP); /* Get index reg. # */
2061 if (!IS_RG_REG (regnum))
2063 as_bad ("invalid index register");
2067 /* Convert scale to its binary encoding */
2086 as_bad ("invalid scale factor");
2090 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2091 mode |= I_BIT; /* Found a valid index spec */
2094 /* Any abase (Register Indirect) specification present? */
2095 if ((p = strrchr (argP, '(')) != NULL)
2097 /* "(" is there -- does it start a legal abase spec? If not, it
2098 could be part of a displacement expression. */
2099 intP = (int *) hash_find (areg_hash, p);
2102 /* Got an abase here */
2104 *p = '\0'; /* discard register spec */
2105 if (regnum == IPREL)
2107 /* We have to specialcase ip-rel mode */
2112 memP->opcode |= regnum << 14;
2118 /* Any expression present? */
2125 /* Special-case ip-relative addressing */
2134 memP->opcode |= 5 << 10; /* IP-relative mode */
2140 /* Handle all other modes */
2144 /* Go with MEMA instruction format for now (grow to MEMB later
2145 if 12 bits is not enough for the displacement). MEMA format
2146 has a single mode bit: set it to indicate that abase is
2148 memP->opcode |= MEMA_ABASE;
2153 /* Go with MEMA instruction format for now (grow to MEMB later
2154 if 12 bits is not enough for the displacement). */
2159 /* For some reason, the bit string for this mode is not
2160 consistent: it should be 0 (exclusive of the MEMB bit), so we
2161 set it "by hand" here. */
2162 memP->opcode |= MEMB_BIT;
2166 /* set MEMB bit in mode, and OR in mode bits */
2167 memP->opcode |= mode | MEMB_BIT;
2171 /* Treat missing displacement as displacement of 0. */
2173 /* Fall into next case. */
2174 case D_BIT | A_BIT | I_BIT:
2176 /* set MEMB bit in mode, and OR in mode bits */
2177 memP->opcode |= mode | MEMB_BIT;
2187 /*****************************************************************************
2188 parse_po: parse machine-dependent pseudo-op
2190 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2191 up the rest of the input line, breaks out the individual arguments,
2192 and dispatches them to the correct handler.
2193 *************************************************************************** */
2197 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2199 /* Pointers operands, with no embedded whitespace.
2200 arg[0] unused, arg[1-3]->operands */
2202 int n_ops; /* Number of operands */
2203 char *p; /* Pointer to beginning of unparsed argument string */
2204 char eol; /* Character that indicated end of line */
2206 extern char is_end_of_line[];
2208 /* Advance input pointer to end of line. */
2209 p = input_line_pointer;
2210 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2212 input_line_pointer++;
2214 eol = *input_line_pointer; /* Save end-of-line char */
2215 *input_line_pointer = '\0'; /* Terminate argument list */
2217 /* Parse out operands */
2218 n_ops = get_args (p, args);
2224 /* Dispatch to correct handler */
2228 s_sysproc (n_ops, args);
2231 s_leafproc (n_ops, args);
2238 /* Restore eol, so line numbers get updated correctly. Base
2239 assembler assumes we leave input pointer pointing at char
2240 following the eol. */
2241 *input_line_pointer++ = eol;
2244 /*****************************************************************************
2245 parse_regop: parse a register operand.
2247 In case of illegal operand, issue a message and return some valid
2248 information so instruction processing can continue.
2249 *************************************************************************** */
2252 parse_regop (regopP, optext, opdesc)
2253 struct regop *regopP; /* Where to put description of register operand */
2254 char *optext; /* Text of operand */
2255 char opdesc; /* Descriptor byte: what's legal for this operand */
2257 int n; /* Register number */
2258 expressionS e; /* Parsed expression */
2260 /* See if operand is a register */
2261 n = get_regnum (optext);
2266 /* global or local register */
2267 if (!REG_ALIGN (opdesc, n))
2269 as_bad ("unaligned register");
2273 regopP->special = 0;
2276 else if (IS_FP_REG (n) && FP_OK (opdesc))
2278 /* Floating point register, and it's allowed */
2279 regopP->n = n - FP0;
2281 regopP->special = 0;
2284 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2286 /* Special-function register, and it's allowed */
2287 regopP->n = n - SF0;
2289 regopP->special = 1;
2290 if (!targ_has_sfr (regopP->n))
2292 as_bad ("no such sfr in this architecture");
2297 else if (LIT_OK (opdesc))
2299 /* How about a literal? */
2301 regopP->special = 0;
2303 { /* floating point literal acceptable */
2304 /* Skip over 0f, 0d, or 0e prefix */
2305 if ((optext[0] == '0')
2306 && (optext[1] >= 'd')
2307 && (optext[1] <= 'f'))
2312 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2317 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2325 { /* fixed point literal acceptable */
2326 parse_expr (optext, &e);
2327 if (e.X_op != O_constant
2328 || (offs (e) < 0) || (offs (e) > 31))
2330 as_bad ("illegal literal");
2333 regopP->n = offs (e);
2338 /* Nothing worked */
2340 regopP->mode = 0; /* Register r0 is always a good one */
2342 regopP->special = 0;
2343 } /* parse_regop() */
2345 /*****************************************************************************
2346 reg_fmt: generate a REG-format instruction
2348 *************************************************************************** */
2351 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2352 struct i960_opcode *oP; /* Pointer to description of instruction */
2354 long instr; /* Binary to be output */
2355 struct regop regop; /* Description of register operand */
2356 int n_ops; /* Number of operands */
2360 n_ops = oP->num_ops;
2364 parse_regop (®op, args[1], oP->operand[0]);
2366 if ((n_ops == 1) && !(instr & M3))
2368 /* 1-operand instruction in which the dst field should
2369 * be used (instead of src1).
2374 regop.mode = regop.special;
2381 /* regop.n goes in bit 0, needs no shifting */
2383 regop.special <<= 5;
2385 instr |= regop.n | regop.mode | regop.special;
2390 parse_regop (®op, args[2], oP->operand[1]);
2392 if ((n_ops == 2) && !(instr & M3))
2394 /* 2-operand instruction in which the dst field should
2395 * be used instead of src2).
2400 regop.mode = regop.special;
2409 regop.special <<= 6;
2411 instr |= regop.n | regop.mode | regop.special;
2415 parse_regop (®op, args[3], oP->operand[2]);
2418 regop.mode = regop.special;
2420 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2426 /*****************************************************************************
2428 Replace cobr instruction in a code fragment with equivalent branch and
2429 compare instructions, so it can reach beyond a 13-bit displacement.
2430 Set up an address fix/relocation for the new branch instruction.
2432 *************************************************************************** */
2434 /* This "conditional jump" table maps cobr instructions into
2435 equivalent compare and branch opcodes. */
2444 { /* COBR OPCODE: */
2445 { CHKBIT, BNO }, /* 0x30 - bbc */
2446 { CMPO, BG }, /* 0x31 - cmpobg */
2447 { CMPO, BE }, /* 0x32 - cmpobe */
2448 { CMPO, BGE }, /* 0x33 - cmpobge */
2449 { CMPO, BL }, /* 0x34 - cmpobl */
2450 { CMPO, BNE }, /* 0x35 - cmpobne */
2451 { CMPO, BLE }, /* 0x36 - cmpoble */
2452 { CHKBIT, BO }, /* 0x37 - bbs */
2453 { CMPI, BNO }, /* 0x38 - cmpibno */
2454 { CMPI, BG }, /* 0x39 - cmpibg */
2455 { CMPI, BE }, /* 0x3a - cmpibe */
2456 { CMPI, BGE }, /* 0x3b - cmpibge */
2457 { CMPI, BL }, /* 0x3c - cmpibl */
2458 { CMPI, BNE }, /* 0x3d - cmpibne */
2459 { CMPI, BLE }, /* 0x3e - cmpible */
2460 { CMPI, BO }, /* 0x3f - cmpibo */
2466 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2467 * the cobr instruction, which comes at the
2468 * end of the code fragment.
2471 int opcode, src1, src2, m1, s2;
2472 /* Bit fields from cobr instruction */
2473 long bp_bits; /* Branch prediction bits from cobr instruction */
2474 long instr; /* A single i960 instruction */
2475 /* ->instruction to be replaced */
2477 fixS *fixP; /* Relocation that can be done at assembly time */
2479 /* PICK UP & PARSE COBR INSTRUCTION */
2480 iP = fragP->fr_opcode;
2481 instr = md_chars_to_number (iP, 4);
2482 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2483 src1 = (instr >> 19) & 0x1f;
2484 m1 = (instr >> 13) & 1;
2486 src2 = (instr >> 14) & 0x1f;
2487 bp_bits = instr & BP_MASK;
2489 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2490 instr = coj[opcode].compare
2491 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2492 md_number_to_chars (iP, instr, 4);
2494 /* OUTPUT BRANCH INSTRUCTION */
2495 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2497 /* SET UP ADDRESS FIXUP/RELOCATION */
2498 fixP = fix_new (fragP,
2499 iP + 4 - fragP->fr_literal,
2506 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2513 /*****************************************************************************
2514 reloc_callj: Relocate a 'callj' instruction
2516 This is a "non-(GNU)-standard" machine-dependent hook. The base
2517 assembler calls it when it decides it can relocate an address at
2518 assembly time instead of emitting a relocation directive.
2520 Check to see if the relocation involves a 'callj' instruction to a:
2521 sysproc: Replace the default 'call' instruction with a 'calls'
2522 leafproc: Replace the default 'call' instruction with a 'bal'.
2523 other proc: Do nothing.
2525 See b.out.h for details on the 'n_other' field in a symbol structure.
2528 Assumes the caller has already figured out, in the case of a leafproc,
2529 to use the 'bal' entry point, and has substituted that symbol into the
2530 passed fixup structure.
2532 *************************************************************************** */
2535 /* Relocation that can be done at assembly time */
2538 /* Points to the binary for the instruction being relocated. */
2541 if (!fixP->fx_tcbit)
2543 /* This wasn't a callj instruction in the first place */
2547 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2549 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2551 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2552 procedure number is (other-1). */
2553 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2555 /* Nothing else needs to be done for this instruction. Make
2556 sure 'md_number_to_field()' will perform a no-op. */
2557 fixP->fx_bit_fixP = (bit_fixS *) 1;
2560 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2562 /* Should not happen: see block comment above */
2563 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy));
2565 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2567 /* Replace 'call' with 'bal'; both instructions have the same
2568 format, so calling code should complete relocation as if
2569 nothing happened here. */
2570 md_number_to_chars (where, BAL, 4);
2572 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2574 as_bad ("Looks like a proc, but can't tell what kind.\n");
2575 } /* switch on proc type */
2577 /* else Symbol is neither a sysproc nor a leafproc */
2581 /*****************************************************************************
2582 s_leafproc: process .leafproc pseudo-op
2584 .leafproc takes two arguments, the second one is optional:
2585 arg[1]: name of 'call' entry point to leaf procedure
2586 arg[2]: name of 'bal' entry point to leaf procedure
2588 If the two arguments are identical, or if the second one is missing,
2589 the first argument is taken to be the 'bal' entry point.
2591 If there are 2 distinct arguments, we must make sure that the 'bal'
2592 entry point immediately follows the 'call' entry point in the linked
2595 *************************************************************************** */
2597 s_leafproc (n_ops, args)
2598 int n_ops; /* Number of operands */
2599 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2601 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2602 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2604 if ((n_ops != 1) && (n_ops != 2))
2606 as_bad ("should have 1 or 2 operands");
2608 } /* Check number of arguments */
2610 /* Find or create symbol for 'call' entry point. */
2611 callP = symbol_find_or_make (args[1]);
2613 if (TC_S_IS_CALLNAME (callP))
2615 as_warn ("Redefining leafproc %s", S_GET_NAME (callP));
2618 /* If that was the only argument, use it as the 'bal' entry point.
2619 * Otherwise, mark it as the 'call' entry point and find or create
2620 * another symbol for the 'bal' entry point.
2622 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2624 TC_S_FORCE_TO_BALNAME (callP);
2629 TC_S_FORCE_TO_CALLNAME (callP);
2631 balP = symbol_find_or_make (args[2]);
2632 if (TC_S_IS_CALLNAME (balP))
2634 as_warn ("Redefining leafproc %s", S_GET_NAME (balP));
2636 TC_S_FORCE_TO_BALNAME (balP);
2638 tc_set_bal_of_call (callP, balP);
2639 } /* if only one arg, or the args are the same */
2644 s_sysproc: process .sysproc pseudo-op
2646 .sysproc takes two arguments:
2647 arg[1]: name of entry point to system procedure
2648 arg[2]: 'entry_num' (index) of system procedure in the range
2651 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2652 the symbol. Since that entry is normally 0, we bias 'entrynum'
2653 by adding 1 to it. It must be unbiased before it is used. */
2655 s_sysproc (n_ops, args)
2656 int n_ops; /* Number of operands */
2657 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2664 as_bad ("should have two operands");
2666 } /* bad arg count */
2668 /* Parse "entry_num" argument and check it for validity. */
2669 parse_expr (args[2], &exp);
2670 if (exp.X_op != O_constant
2672 || (offs (exp) > 31))
2674 as_bad ("'entry_num' must be absolute number in [0,31]");
2678 /* Find/make symbol and stick entry number (biased by +1) into it */
2679 symP = symbol_find_or_make (args[1]);
2681 if (TC_S_IS_SYSPROC (symP))
2683 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP));
2686 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2687 TC_S_FORCE_TO_SYSPROC (symP);
2691 /*****************************************************************************
2693 Determine if a "shlo" instruction can be used to implement a "ldconst".
2694 This means that some number X < 32 can be shifted left to produce the
2695 constant of interest.
2697 Return the shift count, or 0 if we can't do it.
2698 Caller calculates X by shifting original constant right 'shift' places.
2700 *************************************************************************** */
2704 int n; /* The constant of interest */
2706 int shift; /* The shift count */
2710 /* Can't do it for negative numbers */
2714 /* Shift 'n' right until a 1 is about to be lost */
2715 for (shift = 0; (n & 1) == 0; shift++)
2728 /* syntax: issue syntax error */
2733 as_bad ("syntax error");
2739 Return TRUE iff the target architecture supports the specified
2740 special-function register (sfr). */
2745 int n; /* Number (0-31) of sfr */
2747 switch (architecture)
2756 return ((0 <= n) && (n <= 2));
2763 Return TRUE iff the target architecture supports the indicated
2764 class of instructions. */
2767 targ_has_iclass (ic)
2768 /* Instruction class; one of:
2769 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2774 iclasses_seen |= ic;
2775 switch (architecture)
2778 return ic & (I_BASE | I_KX);
2780 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2782 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2784 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2786 return ic & (I_BASE | I_CX2 | I_XL);
2788 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2789 && (iclasses_seen & (I_CX | I_CX2)))
2791 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2792 iclasses_seen &= ~ic;
2798 /* Handle the MRI .endian pseudo-op. */
2807 name = input_line_pointer;
2808 c = get_symbol_end ();
2809 if (strcasecmp (name, "little") == 0)
2811 else if (strcasecmp (name, "big") == 0)
2812 as_bad ("big endian mode is not supported");
2814 as_warn ("ignoring unrecognized .endian type `%s'", name);
2816 *input_line_pointer = c;
2818 demand_empty_rest_of_line ();
2821 /* We have no need to default values of symbols. */
2825 md_undefined_symbol (name)
2831 /* Exactly what point is a PC-relative offset relative TO?
2832 On the i960, they're relative to the address of the instruction,
2833 which we have set up as the address of the fixup too. */
2835 md_pcrel_from (fixP)
2838 return fixP->fx_where + fixP->fx_frag->fr_address;
2842 md_apply_fix (fixP, val)
2846 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2848 if (!fixP->fx_bit_fixP)
2849 switch (fixP->fx_im_disp)
2852 /* For callx, we always want to write out zero, and emit a
2853 symbolic relocation. */
2857 fixP->fx_addnumber = val;
2858 md_number_to_imm (place, val, fixP->fx_size, fixP);
2861 md_number_to_disp (place,
2863 ? val + fixP->fx_pcrel_adjust
2867 case 2: /* fix requested for .long .word etc */
2868 md_number_to_chars (place, val, fixP->fx_size);
2871 as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
2875 md_number_to_field (place, val, fixP->fx_bit_fixP);
2878 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2880 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2883 relax_addressT segment_address_in_file;
2885 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2886 struct relocation_info ri;
2889 memset ((char *) &ri, '\0', sizeof (ri));
2890 symbolP = fixP->fx_addsy;
2891 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2892 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2893 /* These two 'cuz of NS32K */
2894 ri.r_callj = fixP->fx_tcbit;
2895 if (fixP->fx_bit_fixP)
2898 ri.r_length = nbytes_r_length[fixP->fx_size];
2899 ri.r_pcrel = fixP->fx_pcrel;
2900 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2902 if (fixP->fx_r_type != NO_RELOC)
2904 switch (fixP->fx_r_type)
2909 ri.r_length = fixP->fx_size - 1;
2923 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2926 ri.r_index = symbolP->sy_number;
2931 ri.r_index = S_GET_TYPE (symbolP);
2934 /* Output the relocation information in machine-dependent form. */
2935 md_ri_to_chars (where, &ri);
2938 #endif /* OBJ_AOUT or OBJ_BOUT */
2940 #if defined (OBJ_COFF) && defined (BFD)
2942 tc_coff_fix2rtype (fixP)
2948 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2951 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2958 tc_coff_sizemachdep (frag)
2962 return frag->fr_next->fr_address - frag->fr_address;
2968 /* Align an address by rounding it up to the specified boundary. */
2970 md_section_align (seg, addr)
2972 valueT addr; /* Address to be rounded up */
2974 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2975 } /* md_section_align() */
2979 tc_headers_hook (headers)
2980 object_headers *headers;
2982 if (iclasses_seen == I_BASE)
2984 headers->filehdr.f_flags |= F_I960CORE;
2986 else if (iclasses_seen & I_CX)
2988 headers->filehdr.f_flags |= F_I960CA;
2990 else if (iclasses_seen & I_XL)
2991 headers->filehdr.f_flags |= F_I960XL;
2992 else if (iclasses_seen & I_CX2)
2994 headers->filehdr.f_flags |= F_I960CA;
2996 else if (iclasses_seen & I_MIL)
2998 headers->filehdr.f_flags |= F_I960MC;
3000 else if (iclasses_seen & (I_DEC | I_FP))
3002 headers->filehdr.f_flags |= F_I960KB;
3006 headers->filehdr.f_flags |= F_I960KA;
3007 } /* set arch flag */
3009 if (flag_readonly_data_in_text)
3011 headers->filehdr.f_magic = I960RWMAGIC;
3012 headers->aouthdr.magic = OMAGIC;
3016 headers->filehdr.f_magic = I960ROMAGIC;
3017 headers->aouthdr.magic = NMAGIC;
3018 } /* set magic numbers */
3021 #endif /* OBJ_COFF */
3023 /* Things going on here:
3025 For bout, We need to assure a couple of simplifying
3026 assumptions about leafprocs for the linker: the leafproc
3027 entry symbols will be defined in the same assembly in
3028 which they're declared with the '.leafproc' directive;
3029 and if a leafproc has both 'call' and 'bal' entry points
3030 they are both global or both local.
3032 For coff, the call symbol has a second aux entry that
3033 contains the bal entry point. The bal symbol becomes a
3036 For coff representation, the call symbol has a second aux entry that
3037 contains the bal entry point. The bal symbol becomes a label. */
3040 tc_crawl_symbol_chain (headers)
3041 object_headers *headers;
3045 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3048 if (TC_S_IS_SYSPROC (symbolP))
3050 /* second aux entry already contains the sysproc number */
3051 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3052 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3053 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3055 } /* rewrite sysproc */
3056 #endif /* OBJ_COFF */
3058 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3061 } /* Not a leafproc symbol */
3063 if (!S_IS_DEFINED (symbolP))
3065 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP));
3066 } /* undefined leaf */
3068 if (TC_S_IS_CALLNAME (symbolP))
3070 symbolS *balP = tc_get_bal_of_call (symbolP);
3071 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3073 S_SET_EXTERNAL (symbolP);
3074 S_SET_EXTERNAL (balP);
3075 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3076 S_GET_NAME (symbolP), S_GET_NAME (balP));
3077 } /* externality mismatch */
3079 } /* walk the symbol chain */
3082 /* For aout or bout, the bal immediately follows the call.
3084 For coff, we cheat and store a pointer to the bal symbol in the
3085 second aux entry of the call. */
3096 tc_set_bal_of_call (callP, balP)
3100 know (TC_S_IS_CALLNAME (callP));
3101 know (TC_S_IS_BALNAME (balP));
3105 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
3106 S_SET_NUMBER_AUXILIARY (callP, 2);
3108 #else /* ! OBJ_COFF */
3111 /* If the 'bal' entry doesn't immediately follow the 'call'
3112 * symbol, unlink it from the symbol list and re-insert it.
3114 if (symbol_next (callP) != balP)
3116 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3117 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3118 } /* if not in order */
3120 #else /* ! OBJ_ABOUT */
3121 (as yet unwritten.);
3122 #endif /* ! OBJ_ABOUT */
3123 #endif /* ! OBJ_COFF */
3127 _tc_get_bal_of_call (callP)
3132 know (TC_S_IS_CALLNAME (callP));
3135 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
3138 retval = symbol_next (callP);
3140 (as yet unwritten.);
3141 #endif /* ! OBJ_ABOUT */
3142 #endif /* ! OBJ_COFF */
3144 know (TC_S_IS_BALNAME (retval));
3145 return ((char *) retval);
3146 } /* _tc_get_bal_of_call() */
3149 tc_coff_symbol_emit_hook (symbolP)
3152 if (TC_S_IS_CALLNAME (symbolP))
3155 symbolS *balP = tc_get_bal_of_call (symbolP);
3158 /* second aux entry contains the bal entry point */
3159 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3161 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3162 S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT));
3163 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3164 /* fix up the bal symbol */
3165 S_SET_STORAGE_CLASS (balP, C_LABEL);
3166 #endif /* OBJ_COFF */
3167 } /* only on calls */
3171 i960_handle_align (fragp)
3181 as_bad ("option --link-relax is only supported in b.out format");
3187 /* The text section "ends" with another alignment reloc, to which we
3188 aren't adding padding. */
3189 if (fragp->fr_next == text_last_frag
3190 || fragp->fr_next == data_last_frag)
3193 /* alignment directive */
3194 fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3195 (int) fragp->fr_type);
3196 #endif /* OBJ_BOUT */
3200 i960_validate_fix (fixP, this_segment_type, add_symbolPP)
3202 segT this_segment_type;
3203 symbolS **add_symbolPP;
3205 #define add_symbolP (*add_symbolPP)
3206 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
3208 /* Relocation should be done via the associated 'bal'
3209 entry point symbol. */
3211 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
3213 as_bad ("No 'bal' entry point for leafproc %s",
3214 S_GET_NAME (add_symbolP));
3217 fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
3220 /* Still have to work out other conditions for these tests. */
3224 as_bad ("callj to difference of two symbols");
3228 if ((int) fixP->fx_bit_fixP == 13)
3230 /* This is a COBR instruction. They have only a 13-bit
3231 displacement and are only to be used for local branches:
3232 flag as error, don't generate relocation. */
3233 as_bad ("can't use COBR format with external label");
3234 fixP->fx_addsy = NULL; /* No relocations please. */
3243 /* end of tc-i960.c */