1 /* tc-i860.c -- Assembler for the Intel i860 architecture.
2 Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002,
3 2003, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
5 Brought back from the dead and completely reworked
6 by Jason Eckhardt <jle@cygnus.com>.
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License along
21 with GAS; see the file COPYING. If not, write to the Free Software
22 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "safe-ctype.h"
27 #include "opcode/i860.h"
31 /* The opcode hash table. */
32 static struct hash_control *op_hash = NULL;
34 /* These characters always start a comment. */
35 const char comment_chars[] = "#!/";
37 /* These characters start a comment at the beginning of a line. */
38 const char line_comment_chars[] = "#/";
40 const char line_separator_chars[] = ";";
42 /* Characters that can be used to separate the mantissa from the exponent
43 in floating point numbers. */
44 const char EXP_CHARS[] = "eE";
46 /* Characters that indicate this number is a floating point constant.
47 As in 0f12.456 or 0d1.2345e12. */
48 const char FLT_CHARS[] = "rRsSfFdDxXpP";
50 /* Register prefix (depends on syntax). */
51 static char reg_prefix;
59 enum expand_type expand;
63 bfd_reloc_code_real_type reloc;
69 /* The current fixup count. */
72 static char *expr_end;
74 /* Indicates error if a pseudo operation was expanded after a branch. */
75 static char last_expand;
77 /* If true, then warn if any pseudo operations were expanded. */
78 static int target_warn_expand = 0;
80 /* If true, then XP support is enabled. */
81 static int target_xp = 0;
83 /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */
84 static int target_intel_syntax = 0;
88 static void i860_process_insn (char *);
89 static void s_dual (int);
90 static void s_enddual (int);
91 static void s_atmp (int);
92 static void s_align_wrapper (int);
93 static int i860_get_expression (char *);
94 static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
96 static void print_insn (struct i860_it *);
99 const pseudo_typeS md_pseudo_table[] =
101 {"align", s_align_wrapper, 0},
103 {"enddual", s_enddual, 0},
108 /* Dual-instruction mode handling. */
111 DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT,
113 static enum dual dual_mode = DUAL_OFF;
115 /* Handle ".dual" directive. */
117 s_dual (int ignore ATTRIBUTE_UNUSED)
119 if (target_intel_syntax)
122 as_bad (_("Directive .dual available only with -mintel-syntax option"));
125 /* Handle ".enddual" directive. */
127 s_enddual (int ignore ATTRIBUTE_UNUSED)
129 if (target_intel_syntax)
130 dual_mode = DUAL_OFF;
132 as_bad (_("Directive .enddual available only with -mintel-syntax option"));
135 /* Temporary register used when expanding assembler pseudo operations. */
136 static int atmp = 31;
139 s_atmp (int ignore ATTRIBUTE_UNUSED)
143 if (! target_intel_syntax)
145 as_bad (_("Directive .atmp available only with -mintel-syntax option"));
146 demand_empty_rest_of_line ();
150 if (strncmp (input_line_pointer, "sp", 2) == 0)
152 input_line_pointer += 2;
155 else if (strncmp (input_line_pointer, "fp", 2) == 0)
157 input_line_pointer += 2;
160 else if (strncmp (input_line_pointer, "r", 1) == 0)
162 input_line_pointer += 1;
163 temp = get_absolute_expression ();
164 if (temp >= 0 && temp <= 31)
167 as_bad (_("Unknown temporary pseudo register"));
171 as_bad (_("Unknown temporary pseudo register"));
173 demand_empty_rest_of_line ();
176 /* Handle ".align" directive depending on syntax mode.
177 AT&T/SVR4 syntax uses the standard align directive. However,
178 the Intel syntax additionally allows keywords for the alignment
179 parameter: ".align type", where type is one of {.short, .long,
180 .quad, .single, .double} representing alignments of 2, 4,
181 16, 4, and 8, respectively. */
183 s_align_wrapper (int arg)
185 char *parm = input_line_pointer;
187 if (target_intel_syntax)
189 /* Replace a keyword with the equivalent integer so the
190 standard align routine can parse the directive. */
191 if (strncmp (parm, ".short", 6) == 0)
192 strncpy (parm, " 2", 6);
193 else if (strncmp (parm, ".long", 5) == 0)
194 strncpy (parm, " 4", 5);
195 else if (strncmp (parm, ".quad", 5) == 0)
196 strncpy (parm, " 16", 5);
197 else if (strncmp (parm, ".single", 7) == 0)
198 strncpy (parm, " 4", 7);
199 else if (strncmp (parm, ".double", 7) == 0)
200 strncpy (parm, " 8", 7);
202 while (*input_line_pointer == ' ')
203 ++input_line_pointer;
209 /* This function is called once, at assembler startup time. It should
210 set up all the tables and data structures that the MD part of the
211 assembler will need. */
215 const char *retval = NULL;
219 op_hash = hash_new ();
221 while (i860_opcodes[i].name != NULL)
223 const char *name = i860_opcodes[i].name;
224 retval = hash_insert (op_hash, name, (void *) &i860_opcodes[i]);
227 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
228 i860_opcodes[i].name, retval);
233 if (i860_opcodes[i].match & i860_opcodes[i].lose)
236 _("internal error: losing opcode: `%s' \"%s\"\n"),
237 i860_opcodes[i].name, i860_opcodes[i].args);
242 while (i860_opcodes[i].name != NULL
243 && strcmp (i860_opcodes[i].name, name) == 0);
247 as_fatal (_("Defective assembler. No assembly attempted."));
249 /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */
250 reg_prefix = target_intel_syntax ? 0 : '%';
253 /* This is the core of the machine-dependent assembler. STR points to a
254 machine dependent instruction. This function emits the frags/bytes
257 md_assemble (char *str)
262 struct i860_it pseudo[3];
267 /* Assemble the instruction. */
268 i860_process_insn (str);
270 /* Check for expandable flag to produce pseudo-instructions. This
271 is an undesirable feature that should be avoided. */
272 if (the_insn.expand != 0 && the_insn.expand != XP_ONLY
273 && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
274 | OP_SEL_GOTOFF | OP_SEL_PLT)))
276 for (i = 0; i < 3; i++)
277 pseudo[i] = the_insn;
280 switch (the_insn.expand)
288 if (the_insn.fi[0].exp.X_add_symbol == NULL
289 && the_insn.fi[0].exp.X_op_symbol == NULL
290 && (the_insn.fi[0].exp.X_add_number < (1 << 15)
291 && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
294 /* Emit "or l%const,r0,ireg_dest". */
295 pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000;
296 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
298 /* Emit "orh h%const,ireg_dest,ireg_dest". */
299 pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000
300 | ((the_insn.opcode & 0x001f0000) << 5);
301 pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
307 if (the_insn.fi[0].exp.X_add_symbol == NULL
308 && the_insn.fi[0].exp.X_op_symbol == NULL
309 && (the_insn.fi[0].exp.X_add_number < (1 << 15)
310 && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
313 /* Emit "orh ha%addr_expr,ireg_src2,r31". */
314 pseudo[0].opcode = 0xec000000 | (the_insn.opcode & 0x03e00000)
316 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA);
318 /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup
319 information from the original instruction. */
320 pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21);
321 pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L;
327 if (the_insn.fi[0].exp.X_add_symbol == NULL
328 && the_insn.fi[0].exp.X_op_symbol == NULL
329 && (the_insn.fi[0].exp.X_add_number < (1 << 16)
330 && the_insn.fi[0].exp.X_add_number >= 0))
333 /* Emit "$(opcode)h h%const,ireg_src2,r31". */
334 pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000
336 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
338 /* Emit "$(opcode) l%const,r31,ireg_dest". */
339 pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000
341 pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
347 if (the_insn.fi[0].exp.X_add_symbol == NULL
348 && the_insn.fi[0].exp.X_op_symbol == NULL
349 && (the_insn.fi[0].exp.X_add_number < (1 << 16)
350 && the_insn.fi[0].exp.X_add_number >= 0))
353 /* Emit "andnot h%const,ireg_src2,r31". */
354 pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000
356 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
357 pseudo[0].fi[0].exp.X_add_number =
358 -1 - the_insn.fi[0].exp.X_add_number;
360 /* Emit "andnot l%const,r31,ireg_dest". */
361 pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000
363 pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
364 pseudo[1].fi[0].exp.X_add_number =
365 -1 - the_insn.fi[0].exp.X_add_number;
371 if (the_insn.fi[0].exp.X_add_symbol == NULL
372 && the_insn.fi[0].exp.X_op_symbol == NULL
373 && (the_insn.fi[0].exp.X_add_number < (1 << 15)
374 && the_insn.fi[0].exp.X_add_number >= -(1 << 15)))
377 /* Emit "orh h%const,r0,r31". */
378 pseudo[0].opcode = 0xec000000 | (atmp << 16);
379 pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H);
381 /* Emit "or l%const,r31,r31". */
382 pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16);
383 pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L);
385 /* Emit "r31,ireg_src2,ireg_dest". */
386 pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11);
387 pseudo[2].fi[0].fup = OP_IMM_S16;
393 as_fatal (_("failed sanity check."));
396 the_insn = pseudo[0];
398 /* Warn if an opcode is expanded after a delayed branch. */
399 if (num_opcodes > 1 && last_expand == 1)
400 as_warn (_("Expanded opcode after delayed branch: `%s'"), str);
402 /* Warn if an opcode is expanded in dual mode. */
403 if (num_opcodes > 1 && dual_mode != DUAL_OFF)
404 as_warn (_("Expanded opcode in dual mode: `%s'"), str);
406 /* Notify if any expansions happen. */
407 if (target_warn_expand && num_opcodes > 1)
408 as_warn (_("An instruction was expanded (%s)"), str);
411 dwarf2_emit_insn (0);
417 /* Output the opcode. Note that the i860 always reads instructions
418 as little-endian data. */
419 destp = frag_more (4);
420 number_to_chars_littleendian (destp, the_insn.opcode, 4);
422 /* Check for expanded opcode after branch or in dual mode. */
423 last_expand = the_insn.fi[0].pcrel;
425 /* Output the symbol-dependent stuff. Only btne and bte will ever
426 loop more than once here, since only they (possibly) have more
428 for (tmp = 0; tmp < fc; tmp++)
430 if (the_insn.fi[tmp].fup != OP_NONE)
433 fix = fix_new_exp (frag_now,
434 destp - frag_now->fr_literal,
436 &the_insn.fi[tmp].exp,
437 the_insn.fi[tmp].pcrel,
438 the_insn.fi[tmp].reloc);
440 /* Despite the odd name, this is a scratch field. We use
441 it to encode operand type information. */
442 fix->fx_addnumber = the_insn.fi[tmp].fup;
445 the_insn = pseudo[++i];
447 while (--num_opcodes > 0);
451 /* Assemble the instruction pointed to by STR. */
453 i860_process_insn (char *str)
458 struct i860_opcode *insn;
460 unsigned long opcode;
465 #if 1 /* For compiler warnings. */
472 for (s = str; ISLOWER (*s) || *s == '.' || *s == '3'
473 || *s == '2' || *s == '1'; ++s)
491 as_fatal (_("Unknown opcode: `%s'"), str);
494 /* Check for dual mode ("d.") opcode prefix. */
495 if (strncmp (str, "d.", 2) == 0)
497 if (dual_mode == DUAL_ON)
498 dual_mode = DUAL_ONDDOT;
500 dual_mode = DUAL_DDOT;
504 if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL)
506 if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT)
508 as_bad (_("Unknown opcode: `%s'"), str);
519 opcode = insn->match;
520 memset (&the_insn, '\0', sizeof (the_insn));
522 for (t = 0; t < MAX_FIXUPS; t++)
524 the_insn.fi[t].reloc = BFD_RELOC_NONE;
525 the_insn.fi[t].pcrel = 0;
526 the_insn.fi[t].fup = OP_NONE;
529 /* Build the opcode, checking as we go that the operands match. */
530 for (args = insn->args; ; ++args)
544 /* These must match exactly. */
554 /* Must be at least one digit. */
564 /* Next operand must be a register. */
568 /* Check for register prefix if necessary. */
569 if (reg_prefix && *s != reg_prefix)
596 /* Any register r0..r31. */
599 if (!ISDIGIT (c = *s++))
605 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
613 /* Not this opcode. */
618 /* Obtained the register, now place it in the opcode. */
622 opcode |= mask << 11;
626 opcode |= mask << 21;
630 opcode |= mask << 16;
636 /* Next operand is a floating point register. */
640 /* Check for register prefix if necessary. */
641 if (reg_prefix && *s != reg_prefix)
646 if (*s++ == 'f' && ISDIGIT (*s))
651 mask = 10 * (mask - '0') + (*s++ - '0');
664 opcode |= mask << 11;
668 opcode |= mask << 21;
672 opcode |= mask << 16;
673 if ((opcode & (1 << 10)) && mask != 0
674 && (mask == ((opcode >> 11) & 0x1f)))
675 as_warn (_("Pipelined instruction: fsrc1 = fdest"));
681 /* Next operand must be a control register. */
683 /* Check for register prefix if necessary. */
684 if (reg_prefix && *s != reg_prefix)
689 if (strncmp (s, "fir", 3) == 0)
695 if (strncmp (s, "psr", 3) == 0)
701 if (strncmp (s, "dirbase", 7) == 0)
707 if (strncmp (s, "db", 2) == 0)
713 if (strncmp (s, "fsr", 3) == 0)
719 if (strncmp (s, "epsr", 4) == 0)
725 /* The remaining control registers are XP only. */
726 if (target_xp && strncmp (s, "bear", 4) == 0)
732 if (target_xp && strncmp (s, "ccr", 3) == 0)
738 if (target_xp && strncmp (s, "p0", 2) == 0)
744 if (target_xp && strncmp (s, "p1", 2) == 0)
750 if (target_xp && strncmp (s, "p2", 2) == 0)
756 if (target_xp && strncmp (s, "p3", 2) == 0)
764 /* 5-bit immediate in src1. */
766 if (! i860_get_expression (s))
769 the_insn.fi[fc].fup |= OP_IMM_U5;
775 /* 26-bit immediate, relative branch (lbroff). */
777 the_insn.fi[fc].pcrel = 1;
778 the_insn.fi[fc].fup |= OP_IMM_BR26;
781 /* 16-bit split immediate, relative branch (sbroff). */
783 the_insn.fi[fc].pcrel = 1;
784 the_insn.fi[fc].fup |= OP_IMM_BR16;
787 /* 16-bit split immediate. */
789 the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
792 /* 16-bit split immediate, byte aligned (st.b). */
794 the_insn.fi[fc].fup |= OP_IMM_SPLIT16;
797 /* 16-bit split immediate, half-word aligned (st.s). */
799 the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2);
802 /* 16-bit split immediate, word aligned (st.l). */
804 the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4);
807 /* 16-bit immediate. */
809 the_insn.fi[fc].fup |= OP_IMM_S16;
812 /* 16-bit immediate, byte aligned (ld.b). */
814 the_insn.fi[fc].fup |= OP_IMM_S16;
817 /* 16-bit immediate, half-word aligned (ld.s). */
819 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2);
822 /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */
824 if (insn->name[0] == 'l')
825 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4);
827 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4);
830 /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */
832 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8);
835 /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */
837 the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16);
841 /* Handle the immediate for either the Intel syntax or
842 SVR4 syntax. The Intel syntax is "ha%immediate"
843 whereas SVR4 syntax is "[immediate]@ha". */
845 if (target_intel_syntax == 0)
847 /* AT&T/SVR4 syntax. */
851 /* Note that if i860_get_expression() fails, we will still
852 have created U entries in the symbol table for the
853 'symbols' in the input string. Try not to create U
854 symbols for registers, etc. */
855 if (! i860_get_expression (s))
860 if (strncmp (s, "@ha", 3) == 0)
862 the_insn.fi[fc].fup |= OP_SEL_HA;
865 else if (strncmp (s, "@h", 2) == 0)
867 the_insn.fi[fc].fup |= OP_SEL_H;
870 else if (strncmp (s, "@l", 2) == 0)
872 the_insn.fi[fc].fup |= OP_SEL_L;
875 else if (strncmp (s, "@gotoff", 7) == 0
876 || strncmp (s, "@GOTOFF", 7) == 0)
878 as_bad (_("Assembler does not yet support PIC"));
879 the_insn.fi[fc].fup |= OP_SEL_GOTOFF;
882 else if (strncmp (s, "@got", 4) == 0
883 || strncmp (s, "@GOT", 4) == 0)
885 as_bad (_("Assembler does not yet support PIC"));
886 the_insn.fi[fc].fup |= OP_SEL_GOT;
889 else if (strncmp (s, "@plt", 4) == 0
890 || strncmp (s, "@PLT", 4) == 0)
892 as_bad (_("Assembler does not yet support PIC"));
893 the_insn.fi[fc].fup |= OP_SEL_PLT;
897 the_insn.expand = insn->expand;
907 if (strncmp (s, "ha%", 3) == 0)
909 the_insn.fi[fc].fup |= OP_SEL_HA;
912 else if (strncmp (s, "h%", 2) == 0)
914 the_insn.fi[fc].fup |= OP_SEL_H;
917 else if (strncmp (s, "l%", 2) == 0)
919 the_insn.fi[fc].fup |= OP_SEL_L;
922 the_insn.expand = insn->expand;
924 /* Note that if i860_get_expression() fails, we will still
925 have created U entries in the symbol table for the
926 'symbols' in the input string. Try not to create U
927 symbols for registers, etc. */
928 if (! i860_get_expression (s))
939 as_fatal (_("failed sanity check."));
946 /* Args don't match. */
947 if (insn[1].name != NULL
948 && ! strcmp (insn->name, insn[1].name))
956 as_bad (_("Illegal operands for %s"), insn->name);
963 /* Set the dual bit on this instruction if necessary. */
964 if (dual_mode != DUAL_OFF)
966 if ((opcode & 0xfc000000) == 0x48000000 || opcode == 0xb0000000)
968 /* The instruction is a flop or a fnop, so set its dual bit
969 (but check that it is 8-byte aligned). */
970 if (((frag_now->fr_address + frag_now_fix_octets ()) & 7) == 0)
973 as_bad (_("'d.%s' must be 8-byte aligned"), insn->name);
975 if (dual_mode == DUAL_DDOT)
976 dual_mode = DUAL_OFF;
977 else if (dual_mode == DUAL_ONDDOT)
980 else if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT)
981 as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn->name);
984 the_insn.opcode = opcode;
986 /* Only recognize XP instructions when the user has requested it. */
987 if (insn->expand == XP_ONLY && ! target_xp)
988 as_bad (_("Unknown opcode: `%s'"), insn->name);
992 i860_get_expression (char *str)
997 save_in = input_line_pointer;
998 input_line_pointer = str;
999 seg = expression (&the_insn.fi[fc].exp);
1000 if (seg != absolute_section
1001 && seg != undefined_section
1002 && ! SEG_NORMAL (seg))
1004 the_insn.error = _("bad segment");
1005 expr_end = input_line_pointer;
1006 input_line_pointer = save_in;
1009 expr_end = input_line_pointer;
1010 input_line_pointer = save_in;
1015 md_atof (int type, char *litP, int *sizeP)
1017 return ieee_md_atof (type, litP, sizeP, TRUE);
1020 /* Write out in current endian mode. */
1022 md_number_to_chars (char *buf, valueT val, int n)
1024 if (target_big_endian)
1025 number_to_chars_bigendian (buf, val, n);
1027 number_to_chars_littleendian (buf, val, n);
1030 /* This should never be called for i860. */
1032 md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED,
1033 segT segtype ATTRIBUTE_UNUSED)
1035 as_fatal (_("relaxation not supported\n"));
1040 print_insn (struct i860_it *insn)
1043 fprintf (stderr, "ERROR: %s\n", insn->error);
1045 fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode);
1046 fprintf (stderr, "expand = 0x%x\t", insn->expand);
1047 fprintf (stderr, "reloc = %s\t\n",
1048 bfd_get_reloc_code_name (insn->reloc));
1049 fprintf (stderr, "exp = {\n");
1050 fprintf (stderr, "\t\tX_add_symbol = %s\n",
1051 insn->exp.X_add_symbol ?
1052 (S_GET_NAME (insn->exp.X_add_symbol) ?
1053 S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0");
1054 fprintf (stderr, "\t\tX_op_symbol = %s\n",
1055 insn->exp.X_op_symbol ?
1056 (S_GET_NAME (insn->exp.X_op_symbol) ?
1057 S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0");
1058 fprintf (stderr, "\t\tX_add_number = %lx\n",
1059 insn->exp.X_add_number);
1060 fprintf (stderr, "}\n");
1062 #endif /* DEBUG_I860 */
1066 const char *md_shortopts = "VQ:";
1068 const char *md_shortopts = "";
1071 #define OPTION_EB (OPTION_MD_BASE + 0)
1072 #define OPTION_EL (OPTION_MD_BASE + 1)
1073 #define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2)
1074 #define OPTION_XP (OPTION_MD_BASE + 3)
1075 #define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4)
1077 struct option md_longopts[] = {
1078 { "EB", no_argument, NULL, OPTION_EB },
1079 { "EL", no_argument, NULL, OPTION_EL },
1080 { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
1081 { "mxp", no_argument, NULL, OPTION_XP },
1082 { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX },
1083 { NULL, no_argument, NULL, 0 }
1085 size_t md_longopts_size = sizeof (md_longopts);
1088 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
1093 target_big_endian = 1;
1097 target_big_endian = 0;
1100 case OPTION_WARN_EXPAND:
1101 target_warn_expand = 1;
1108 case OPTION_INTEL_SYNTAX:
1109 target_intel_syntax = 1;
1113 /* SVR4 argument compatibility (-V): print version ID. */
1115 print_version_id ();
1118 /* SVR4 argument compatibility (-Qy, -Qn): controls whether
1119 a .comment section should be emitted or not (ignored). */
1132 md_show_usage (FILE *stream)
1134 fprintf (stream, _("\
1135 -EL generate code for little endian mode (default)\n\
1136 -EB generate code for big endian mode\n\
1137 -mwarn-expand warn if pseudo operations are expanded\n\
1138 -mxp enable i860XP support (disabled by default)\n\
1139 -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n"));
1141 /* SVR4 compatibility flags. */
1142 fprintf (stream, _("\
1143 -V print assembler version number\n\
1144 -Qy, -Qn ignored\n"));
1149 /* We have no need to default values of symbols. */
1151 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1156 /* The i860 denotes auto-increment with '++'. */
1158 md_operand (expressionS *exp)
1162 for (s = input_line_pointer; *s; s++)
1164 if (s[0] == '+' && s[1] == '+')
1166 input_line_pointer += 2;
1167 exp->X_op = O_register;
1173 /* Round up a section size to the appropriate boundary. */
1175 md_section_align (segT segment ATTRIBUTE_UNUSED,
1176 valueT size ATTRIBUTE_UNUSED)
1178 /* Byte alignment is fine. */
1182 /* On the i860, a PC-relative offset is relative to the address of the
1183 offset plus its size. */
1185 md_pcrel_from (fixS *fixP)
1187 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
1190 /* Determine the relocation needed for non PC-relative 16-bit immediates.
1191 Also adjust the given immediate as necessary. Finally, check that
1192 all constraints (such as alignment) are satisfied. */
1193 static bfd_reloc_code_real_type
1194 obtain_reloc_for_imm16 (fixS *fix, long *val)
1196 valueT fup = fix->fx_addnumber;
1197 bfd_reloc_code_real_type reloc;
1202 /* Check alignment restrictions. */
1203 if ((fup & OP_ALIGN2) && (*val & 0x1))
1204 as_bad_where (fix->fx_file, fix->fx_line,
1205 _("This immediate requires 0 MOD 2 alignment"));
1206 else if ((fup & OP_ALIGN4) && (*val & 0x3))
1207 as_bad_where (fix->fx_file, fix->fx_line,
1208 _("This immediate requires 0 MOD 4 alignment"));
1209 else if ((fup & OP_ALIGN8) && (*val & 0x7))
1210 as_bad_where (fix->fx_file, fix->fx_line,
1211 _("This immediate requires 0 MOD 8 alignment"));
1212 else if ((fup & OP_ALIGN16) && (*val & 0xf))
1213 as_bad_where (fix->fx_file, fix->fx_line,
1214 _("This immediate requires 0 MOD 16 alignment"));
1216 if (fup & OP_SEL_HA)
1218 *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0);
1219 reloc = BFD_RELOC_860_HIGHADJ;
1221 else if (fup & OP_SEL_H)
1224 reloc = BFD_RELOC_860_HIGH;
1226 else if (fup & OP_SEL_L)
1229 if (fup & OP_IMM_SPLIT16)
1231 if (fup & OP_ENCODE1)
1234 reloc = BFD_RELOC_860_SPLIT1;
1236 else if (fup & OP_ENCODE2)
1239 reloc = BFD_RELOC_860_SPLIT2;
1244 reloc = BFD_RELOC_860_SPLIT0;
1249 if (fup & OP_ENCODE1)
1252 reloc = BFD_RELOC_860_LOW1;
1254 else if (fup & OP_ENCODE2)
1257 reloc = BFD_RELOC_860_LOW2;
1259 else if (fup & OP_ENCODE3)
1262 reloc = BFD_RELOC_860_LOW3;
1267 reloc = BFD_RELOC_860_LOW0;
1271 /* Preserve size encode bits. */
1272 *val &= ~((1 << num_encode) - 1);
1276 /* No selector. What reloc do we generate (???)? */
1277 reloc = BFD_RELOC_32;
1283 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
1284 has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
1285 we will have to generate a reloc entry. */
1288 md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1295 buf = fix->fx_frag->fr_literal + fix->fx_where;
1297 /* Recall that earlier we stored the opcode little-endian. */
1298 insn = bfd_getl32 (buf);
1300 /* We stored a fix-up in this oddly-named scratch field. */
1301 fup = fix->fx_addnumber;
1303 /* Determine the necessary relocations as well as inserting an
1304 immediate into the instruction. */
1305 if (fup & OP_IMM_U5)
1308 as_bad_where (fix->fx_file, fix->fx_line,
1309 _("5-bit immediate too large"));
1311 as_bad_where (fix->fx_file, fix->fx_line,
1312 _("5-bit field must be absolute"));
1314 insn |= (val & 0x1f) << 11;
1315 bfd_putl32 (insn, buf);
1316 fix->fx_r_type = BFD_RELOC_NONE;
1319 else if (fup & OP_IMM_S16)
1321 fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1323 /* Insert the immediate. */
1328 insn |= val & 0xffff;
1329 bfd_putl32 (insn, buf);
1330 fix->fx_r_type = BFD_RELOC_NONE;
1334 else if (fup & OP_IMM_U16)
1337 else if (fup & OP_IMM_SPLIT16)
1339 fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val);
1341 /* Insert the immediate. */
1346 insn |= val & 0x7ff;
1347 insn |= (val & 0xf800) << 5;
1348 bfd_putl32 (insn, buf);
1349 fix->fx_r_type = BFD_RELOC_NONE;
1353 else if (fup & OP_IMM_BR16)
1356 as_bad_where (fix->fx_file, fix->fx_line,
1357 _("A branch offset requires 0 MOD 4 alignment"));
1361 /* Insert the immediate. */
1365 fix->fx_r_type = BFD_RELOC_860_PC16;
1369 insn |= (val & 0x7ff);
1370 insn |= ((val & 0xf800) << 5);
1371 bfd_putl32 (insn, buf);
1372 fix->fx_r_type = BFD_RELOC_NONE;
1376 else if (fup & OP_IMM_BR26)
1379 as_bad_where (fix->fx_file, fix->fx_line,
1380 _("A branch offset requires 0 MOD 4 alignment"));
1384 /* Insert the immediate. */
1387 fix->fx_r_type = BFD_RELOC_860_PC26;
1392 insn |= (val & 0x3ffffff);
1393 bfd_putl32 (insn, buf);
1394 fix->fx_r_type = BFD_RELOC_NONE;
1398 else if (fup != OP_NONE)
1400 as_bad_where (fix->fx_file, fix->fx_line,
1401 _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup);
1406 /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000"
1407 reach here (???). */
1410 fix->fx_r_type = BFD_RELOC_32;
1415 insn |= (val & 0xffffffff);
1416 bfd_putl32 (insn, buf);
1417 fix->fx_r_type = BFD_RELOC_NONE;
1423 /* Generate a machine dependent reloc from a fixup. */
1425 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
1430 reloc = xmalloc (sizeof (*reloc));
1431 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1432 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1433 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1434 reloc->addend = fixp->fx_offset;
1435 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1439 as_bad_where (fixp->fx_file, fixp->fx_line,
1440 "Cannot represent %s relocation in object file",
1441 bfd_get_reloc_code_name (fixp->fx_r_type));
1446 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
1447 of an rs_align_code fragment. */
1450 i860_handle_align (fragS *fragp)
1452 /* Instructions are always stored little-endian on the i860. */
1453 static const unsigned char le_nop[] = { 0x00, 0x00, 0x00, 0xA0 };
1458 if (fragp->fr_type != rs_align_code)
1461 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
1462 p = fragp->fr_literal + fragp->fr_fix;
1464 /* Make sure we are on a 4-byte boundary, in case someone has been
1465 putting data into a text section. */
1468 int fix = bytes & 3;
1471 fragp->fr_fix += fix;
1474 memcpy (p, le_nop, 4);
1478 /* This is called after a user-defined label is seen. We check
1479 if the label has a double colon (valid in Intel syntax mode only),
1480 in which case it should be externalized. */
1483 i860_check_label (symbolS *labelsym)
1485 /* At this point, the current line pointer is sitting on the character
1486 just after the first colon on the label. */
1487 if (target_intel_syntax && *input_line_pointer == ':')
1489 S_SET_EXTERNAL (labelsym);
1490 input_line_pointer++;