1 /* tc-i386.h -- Header file for tc-i386.c
2 Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 1999
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #ifdef ANSI_PROTOTYPES
29 #define TARGET_BYTES_BIG_ENDIAN 0
32 #define TARGET_FORMAT "coff-i386-lynx"
36 /* This is used to determine relocation types in tc-i386.c. The first
37 parameter is the current relocation type, the second one is the desired
38 type. The idea is that if the original type is already some kind of PIC
39 relocation, we leave it alone, otherwise we give it the desired type */
41 #define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \
42 (X) != BFD_RELOC_386_GOTOFF && \
43 (X) != BFD_RELOC_386_GOT32 && \
44 (X) != BFD_RELOC_386_GOTPC) ? Y : X)
46 #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
47 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
49 /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
50 * It comes up in complicated expressions such as
51 * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
52 * the regular expressions. The fixup specified here when used at runtime
53 * implies that we should add the address of the GOT to the specified location,
54 * and as a result we have simplified the expression into something we can use.
56 #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
58 /* This expression evaluates to false if the relocation is for a local object
59 for which we still want to do the relocation at runtime. True if we
60 are willing to perform this relocation while building the .o file.
61 This is only used for pcrel relocations, so GOTOFF does not need to be
62 checked here. I am not sure if some of the others are ever used with
63 pcrel, but it is easier to be safe than sorry. */
65 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
66 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
67 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
68 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
69 && ((FIX)->fx_addsy == NULL \
70 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
71 && ! S_IS_WEAK ((FIX)->fx_addsy) \
72 && S_IS_DEFINED ((FIX)->fx_addsy) \
73 && ! S_IS_COMMON ((FIX)->fx_addsy))))
75 #define TARGET_ARCH bfd_arch_i386
79 #define TARGET_FORMAT "a.out-i386-netbsd"
82 #define TARGET_FORMAT "a.out-i386-bsd"
85 #define TARGET_FORMAT "a.out-i386-linux"
88 #define TARGET_FORMAT "a.out-mach3"
91 #define TARGET_FORMAT "a.out-i386-dynix"
94 #define TARGET_FORMAT "a.out-i386"
99 #define TARGET_FORMAT "elf32-i386"
103 #ifdef OBJ_MAYBE_COFF
104 extern const char *i386_target_format PARAMS ((void));
105 #define TARGET_FORMAT i386_target_format ()
109 #else /* ! BFD_ASSEMBLER */
113 #define COFF_MAGIC I386MAGIC
114 #define BFD_ARCH bfd_arch_i386
115 #define COFF_FLAGS F_AR32WR
116 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
117 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
118 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
119 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
120 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
121 #define SUB_SEGMENT_ALIGN(SEG) 2
122 #define TC_RVA_RELOC 7
123 /* Need this for PIC relocations */
124 #define NEED_FX_R_TYPE
128 /* The BSDI linker apparently rejects objects with a machine type of
130 #define AOUT_MACHTYPE 0
132 #define AOUT_MACHTYPE 100
135 #undef REVERSE_SORT_RELOCS
137 #endif /* ! BFD_ASSEMBLER */
139 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
140 extern int tc_i386_force_relocation PARAMS ((struct fix *));
143 #define NO_RELOC BFD_RELOC_NONE
147 #define tc_coff_symbol_emit_hook(a) ; /* not used */
149 #ifndef BFD_ASSEMBLER
153 /* Local labels starts with .L */
154 #define LOCAL_LABEL(name) (name[0] == '.' \
155 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
161 #define LOCAL_LABELS_FB 1
163 #define tc_aout_pre_write_hook(x) {;} /* not used */
164 #define tc_crawl_symbol_chain(a) {;} /* not used */
165 #define tc_headers_hook(a) {;} /* not used */
167 extern const char extra_symbol_chars[];
168 #define tc_symbol_chars extra_symbol_chars
170 #define MAX_OPERANDS 3 /* max operands per insn */
171 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
172 #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
174 /* Prefixes will be emitted in the order defined below.
175 WAIT_PREFIX must be the first prefix since FWAIT is really is an
176 instruction, and so must come before any prefixes. */
177 #define WAIT_PREFIX 0
178 #define LOCKREP_PREFIX 1
179 #define ADDR_PREFIX 2
180 #define DATA_PREFIX 3
182 #define MAX_PREFIXES 5 /* max prefixes per opcode */
184 /* we define the syntax here (modulo base,index,scale syntax) */
185 #define REGISTER_PREFIX '%'
186 #define IMMEDIATE_PREFIX '$'
187 #define ABSOLUTE_PREFIX '*'
189 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
190 #define NOP_OPCODE (char) 0x90
192 /* register numbers */
193 #define EBP_REG_NUM 5
194 #define ESP_REG_NUM 4
196 /* modrm_byte.regmem for twobyte escape */
197 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
198 /* index_base_byte.index for no index register addressing */
199 #define NO_INDEX_REGISTER ESP_REG_NUM
200 /* index_base_byte.base for no base register addressing */
201 #define NO_BASE_REGISTER EBP_REG_NUM
202 #define NO_BASE_REGISTER_16 6
204 /* these are the instruction mnemonic suffixes. */
205 #define DWORD_MNEM_SUFFIX 'l'
206 #define WORD_MNEM_SUFFIX 'w'
207 #define BYTE_MNEM_SUFFIX 'b'
208 #define SHORT_MNEM_SUFFIX 's'
209 #define LONG_MNEM_SUFFIX 'l'
211 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
213 #define INTEL_DWORD_MNEM_SUFFIX 'd'
215 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
216 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
217 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
219 #define END_OF_INSN '\0'
222 /* Values 0-4 map onto scale factor */
229 #define OFFSET_FLAT 6
233 When an operand is read in it is classified by its type. This type includes
234 all the possible ways an operand can be used. Thus, '%eax' is both 'register
235 # 0' and 'The Accumulator'. In our language this is expressed by OR'ing
236 'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
237 Operands are classified so that we can match given operand types with
238 the opcode table in opcode/i386.h.
241 #define Reg8 0x1 /* 8 bit reg */
242 #define Reg16 0x2 /* 16 bit reg */
243 #define Reg32 0x4 /* 32 bit reg */
245 #define Imm8 0x8 /* 8 bit immediate */
246 #define Imm8S 0x10 /* 8 bit immediate sign extended */
247 #define Imm16 0x20 /* 16 bit immediate */
248 #define Imm32 0x40 /* 32 bit immediate */
249 #define Imm1 0x80 /* 1 bit immediate */
251 #define BaseIndex 0x100
252 /* Disp8,16,32 are used in different ways, depending on the
253 instruction. For jumps, they specify the size of the PC relative
254 displacement, for baseindex type instructions, they specify the
255 size of the offset relative to the base register, and for memory
256 offset instructions such as `mov 1234,%al' they specify the size of
257 the offset relative to the segment base. */
258 #define Disp8 0x200 /* 8 bit displacement */
259 #define Disp16 0x400 /* 16 bit displacement */
260 #define Disp32 0x800 /* 32 bit displacement */
262 #define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
263 #define ShiftCount 0x2000 /* register to hold shift cound = cl */
264 #define Control 0x4000 /* Control register */
265 #define Debug 0x8000 /* Debug register */
266 #define Test 0x10000 /* Test register */
267 #define FloatReg 0x20000 /* Float register */
268 #define FloatAcc 0x40000 /* Float stack top %st(0) */
269 #define SReg2 0x80000 /* 2 bit segment register */
270 #define SReg3 0x100000 /* 3 bit segment register */
271 #define Acc 0x200000 /* Accumulator %al or %ax or %eax */
272 #define JumpAbsolute 0x400000
273 #define RegMMX 0x800000 /* MMX register */
274 #define RegXMM 0x1000000 /* XMM registers in PIII */
275 #define EsSeg 0x2000000 /* String insn operand with fixed es segment */
276 /* InvMem is for instructions with a modrm byte that only allow a
277 general register encoding in the i.tm.mode and i.tm.regmem fields,
278 eg. control reg moves. They really ought to support a memory form,
279 but don't, so we add an InvMem flag to the register operand to
280 indicate that it should be encoded in the i.tm.regmem field. */
281 #define InvMem 0x4000000
283 #define Reg (Reg8|Reg16|Reg32) /* gen'l register */
284 #define WordReg (Reg16|Reg32)
285 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
286 #define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
287 #define Disp (Disp8|Disp16|Disp32) /* General displacement */
288 #define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
289 /* The following aliases are defined because the opcode table
290 carefully specifies the allowed memory types for each instruction.
291 At the moment we can only tell a memory reference size by the
292 instruction suffix, so there's not much point in defining Mem8,
293 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
294 the suffix directly to check memory operands. */
295 #define LLongMem AnyMem /* 64 bits (or more) */
296 #define LongMem AnyMem /* 32 bit memory ref */
297 #define ShortMem AnyMem /* 16 bit memory ref */
298 #define WordMem AnyMem /* 16 or 32 bit memory ref */
299 #define ByteMem AnyMem /* 8 bit memory ref */
301 #define SMALLEST_DISP_TYPE(num) \
302 (fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)
306 /* instruction name sans width suffix ("mov" for movl insns) */
309 /* how many operands */
310 unsigned int operands;
312 /* base_opcode is the fundamental opcode byte without optional
314 unsigned int base_opcode;
316 /* extension_opcode is the 3 bit extension for group <n> insns.
317 This field is also used to store the 8-bit opcode suffix for the
318 AMD 3DNow! instructions.
319 If this template has no extension opcode (the usual case) use None */
320 unsigned int extension_opcode;
321 #define None 0xffff /* If no extension_opcode is possible. */
323 /* the bits in opcode_modifier are used to generate the final opcode from
324 the base_opcode. These bits also are used to detect alternate forms of
325 the same instruction */
326 unsigned int opcode_modifier;
328 /* opcode_modifier bits: */
329 #define W 0x1 /* set if operands can be words or dwords
330 encoded the canonical way */
331 #define D 0x2 /* D = 0 if Reg --> Regmem;
332 D = 1 if Regmem --> Reg: MUST BE 0x2 */
334 #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
335 #define ShortForm 0x10 /* register is in low 3 bits of opcode */
336 #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
337 #define Jump 0x40 /* special case for jump insns. */
338 #define JumpDword 0x80 /* call and jump */
339 #define JumpByte 0x100 /* loop and jecxz */
340 #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
341 #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
342 #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
343 #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
344 #define Size16 0x2000 /* needs size prefix if in 32-bit mode */
345 #define Size32 0x4000 /* needs size prefix if in 16-bit mode */
346 #define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
347 #define No_bSuf 0x10000 /* b suffix on instruction illegal */
348 #define No_wSuf 0x20000 /* w suffix on instruction illegal */
349 #define No_lSuf 0x40000 /* l suffix on instruction illegal */
350 #define No_sSuf 0x80000 /* s suffix on instruction illegal */
351 #define No_dSuf 0x100000 /* d suffix on instruction illegal */
352 #define No_xSuf 0x200000 /* x suffix on instruction illegal */
353 #define FWait 0x400000 /* instruction needs FWAIT */
354 #define IsString 0x800000 /* quick test for string instructions */
355 #define regKludge 0x1000000 /* fake an extra reg operand for clr, imul */
356 #define IsPrefix 0x2000000 /* opcode is a prefix */
357 #define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */
358 #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
360 /* operand_types[i] describes the type of operand i. This is made
361 by OR'ing together all of the possible type masks. (e.g.
362 'operand_types[i] = Reg|Imm' specifies that operand i can be
363 either a register or an immediate operand */
364 unsigned int operand_types[3];
369 'templates' is for grouping together 'template' structures for opcodes
370 of the same name. This is only used for storing the insns in the grand
371 ole hash table of insns.
372 The templates themselves start at START and range up to (but not including)
377 const template *start;
381 /* these are for register name --> number & type hash lookup */
385 unsigned int reg_type;
386 unsigned int reg_num;
393 unsigned int seg_prefix;
397 /* 386 operand encoding bytes: see 386 book for details of this. */
400 unsigned int regmem; /* codes register or memory operand */
401 unsigned int reg; /* codes register operand (or extended opcode) */
402 unsigned int mode; /* how to interpret regmem & reg */
406 /* 386 opcode byte to code indirect addressing. */
415 /* The name of the global offset table generated by the compiler. Allow
416 this to be overridden if need be. */
417 #ifndef GLOBAL_OFFSET_TABLE_NAME
418 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
422 void i386_validate_fix PARAMS ((struct fix *));
423 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
428 #define md_operand(x)
430 extern const struct relax_type md_relax_table[];
431 #define TC_GENERIC_RELAX_TABLE md_relax_table
434 extern int flag_16bit_code;
436 #define md_do_align(n, fill, len, max, around) \
437 if ((n) && !need_pass_2 \
438 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
439 && subseg_text_p (now_seg)) \
442 p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
443 (symbolS *) 0, (offsetT) (n), (char *) 0); \
448 extern void i386_align_code PARAMS ((fragS *, int));
450 #define HANDLE_ALIGN(fragP) \
451 if (fragP->fr_type == rs_align_code) \
452 i386_align_code (fragP, (fragP->fr_next->fr_address \
453 - fragP->fr_address \
456 /* call md_apply_fix3 with segment instead of md_apply_fix */
457 #define MD_APPLY_FIX3
459 void i386_print_statistics PARAMS ((FILE *));
460 #define tc_print_statistics i386_print_statistics
462 #define md_number_to_chars number_to_chars_littleendian
465 #define tc_init_after_args() sco_id ()
466 extern void sco_id PARAMS ((void));
469 #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
471 /* end of tc-i386.h */