1 /* tc-i386.h -- Header file for tc-i386.c
2 Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #ifdef ANSI_PROTOTYPES
29 #define TARGET_BYTES_BIG_ENDIAN 0
32 #define TARGET_FORMAT "coff-i386-lynx"
36 /* This is used to determine relocation types in tc-i386.c. The first
37 parameter is the current relocation type, the second one is the desired
38 type. The idea is that if the original type is already some kind of PIC
39 relocation, we leave it alone, otherwise we give it the desired type */
41 #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
42 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
44 /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
45 * It comes up in complicated expressions such as
46 * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
47 * the regular expressions. The fixup specified here when used at runtime
48 * implies that we should add the address of the GOT to the specified location,
49 * and as a result we have simplified the expression into something we can use.
51 #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
53 /* This expression evaluates to false if the relocation is for a local object
54 for which we still want to do the relocation at runtime. True if we
55 are willing to perform this relocation while building the .o file.
56 This is only used for pcrel relocations, so GOTOFF does not need to be
57 checked here. I am not sure if some of the others are ever used with
58 pcrel, but it is easier to be safe than sorry. */
60 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
61 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
62 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
63 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
64 && ((FIX)->fx_addsy == NULL \
65 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
66 && ! S_IS_WEAK ((FIX)->fx_addsy) \
67 && S_IS_DEFINED ((FIX)->fx_addsy) \
68 && ! S_IS_COMMON ((FIX)->fx_addsy))))
70 #define TARGET_ARCH bfd_arch_i386
73 #define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
76 #define AOUT_TARGET_FORMAT "a.out-i386-bsd"
79 #define AOUT_TARGET_FORMAT "a.out-i386-linux"
82 #define AOUT_TARGET_FORMAT "a.out-mach3"
85 #define AOUT_TARGET_FORMAT "a.out-i386-dynix"
87 #ifndef AOUT_TARGET_FORMAT
88 #define AOUT_TARGET_FORMAT "a.out-i386"
91 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
92 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
93 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
94 extern const char *i386_target_format PARAMS ((void));
95 #define TARGET_FORMAT i386_target_format ()
98 #define TARGET_FORMAT "elf32-i386"
101 #define TARGET_FORMAT AOUT_TARGET_FORMAT
105 #else /* ! BFD_ASSEMBLER */
109 #define COFF_MAGIC I386MAGIC
110 #define BFD_ARCH bfd_arch_i386
111 #define COFF_FLAGS F_AR32WR
112 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
113 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
114 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
115 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
116 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
119 /* DJGPP now expects some sections to be 2**4 aligned. */
120 #define SUB_SEGMENT_ALIGN(SEG) \
121 ((strcmp (obj_segment_name (SEG), ".text") == 0 \
122 || strcmp (obj_segment_name (SEG), ".data") == 0 \
123 || strcmp (obj_segment_name (SEG), ".bss") == 0 \
124 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
125 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
126 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
130 #define SUB_SEGMENT_ALIGN(SEG) 2
133 #define TC_RVA_RELOC 7
134 /* Need this for PIC relocations */
135 #define NEED_FX_R_TYPE
139 /* The BSDI linker apparently rejects objects with a machine type of
141 #define AOUT_MACHTYPE 0
143 #define AOUT_MACHTYPE 100
146 #undef REVERSE_SORT_RELOCS
148 #endif /* ! BFD_ASSEMBLER */
150 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
151 extern int tc_i386_force_relocation PARAMS ((struct fix *));
154 #define NO_RELOC BFD_RELOC_NONE
158 #define tc_coff_symbol_emit_hook(a) ; /* not used */
160 #ifndef BFD_ASSEMBLER
164 /* Local labels starts with .L */
165 #define LOCAL_LABEL(name) (name[0] == '.' \
166 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
172 #define LOCAL_LABELS_FB 1
174 #define tc_aout_pre_write_hook(x) {;} /* not used */
175 #define tc_crawl_symbol_chain(a) {;} /* not used */
176 #define tc_headers_hook(a) {;} /* not used */
178 extern const char extra_symbol_chars[];
179 #define tc_symbol_chars extra_symbol_chars
181 #define MAX_OPERANDS 3 /* max operands per insn */
182 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
183 #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
185 /* Prefixes will be emitted in the order defined below.
186 WAIT_PREFIX must be the first prefix since FWAIT is really is an
187 instruction, and so must come before any prefixes. */
188 #define WAIT_PREFIX 0
189 #define LOCKREP_PREFIX 1
190 #define ADDR_PREFIX 2
191 #define DATA_PREFIX 3
193 #define MAX_PREFIXES 5 /* max prefixes per opcode */
195 /* we define the syntax here (modulo base,index,scale syntax) */
196 #define REGISTER_PREFIX '%'
197 #define IMMEDIATE_PREFIX '$'
198 #define ABSOLUTE_PREFIX '*'
200 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
201 #define NOP_OPCODE (char) 0x90
203 /* register numbers */
204 #define EBP_REG_NUM 5
205 #define ESP_REG_NUM 4
207 /* modrm_byte.regmem for twobyte escape */
208 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
209 /* index_base_byte.index for no index register addressing */
210 #define NO_INDEX_REGISTER ESP_REG_NUM
211 /* index_base_byte.base for no base register addressing */
212 #define NO_BASE_REGISTER EBP_REG_NUM
213 #define NO_BASE_REGISTER_16 6
215 /* these are the instruction mnemonic suffixes. */
216 #define WORD_MNEM_SUFFIX 'w'
217 #define BYTE_MNEM_SUFFIX 'b'
218 #define SHORT_MNEM_SUFFIX 's'
219 #define LONG_MNEM_SUFFIX 'l'
221 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
223 #define DWORD_MNEM_SUFFIX 'd'
225 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
226 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
227 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
229 #define END_OF_INSN '\0'
232 /* Values 0-4 map onto scale factor */
239 #define OFFSET_FLAT 6
246 /* instruction name sans width suffix ("mov" for movl insns) */
249 /* how many operands */
250 unsigned int operands;
252 /* base_opcode is the fundamental opcode byte without optional
254 unsigned int base_opcode;
256 /* extension_opcode is the 3 bit extension for group <n> insns.
257 This field is also used to store the 8-bit opcode suffix for the
258 AMD 3DNow! instructions.
259 If this template has no extension opcode (the usual case) use None */
260 unsigned int extension_opcode;
261 #define None 0xffff /* If no extension_opcode is possible. */
263 /* cpu feature flags */
264 unsigned int cpu_flags;
265 #define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
266 #define Cpu186 0x2 /* i186 or better required */
267 #define Cpu286 0x4 /* i286 or better required */
268 #define Cpu386 0x8 /* i386 or better required */
269 #define Cpu486 0x10 /* i486 or better required */
270 #define Cpu586 0x20 /* i585 or better required */
271 #define Cpu686 0x40 /* i686 or better required */
272 #define CpuMMX 0x80 /* MMX support required */
273 #define CpuSSE 0x100 /* Streaming SIMD extensions required */
274 #define Cpu3dnow 0x200 /* 3dnow! support required */
276 /* the bits in opcode_modifier are used to generate the final opcode from
277 the base_opcode. These bits also are used to detect alternate forms of
278 the same instruction */
279 unsigned int opcode_modifier;
281 /* opcode_modifier bits: */
282 #define W 0x1 /* set if operands can be words or dwords
283 encoded the canonical way */
284 #define D 0x2 /* D = 0 if Reg --> Regmem;
285 D = 1 if Regmem --> Reg: MUST BE 0x2 */
287 #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
288 #define ShortForm 0x10 /* register is in low 3 bits of opcode */
289 #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
290 #define Jump 0x40 /* special case for jump insns. */
291 #define JumpDword 0x80 /* call and jump */
292 #define JumpByte 0x100 /* loop and jecxz */
293 #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
294 #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
295 #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
296 #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
297 #define Size16 0x2000 /* needs size prefix if in 32-bit mode */
298 #define Size32 0x4000 /* needs size prefix if in 16-bit mode */
299 #define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
300 #define DefaultSize 0x10000 /* default insn size depends on mode */
301 #define No_bSuf 0x20000 /* b suffix on instruction illegal */
302 #define No_wSuf 0x40000 /* w suffix on instruction illegal */
303 #define No_lSuf 0x80000 /* l suffix on instruction illegal */
304 #define No_sSuf 0x100000 /* s suffix on instruction illegal */
305 #define No_dSuf 0x200000 /* d suffix on instruction illegal */
306 #define No_xSuf 0x400000 /* x suffix on instruction illegal */
307 #define FWait 0x800000 /* instruction needs FWAIT */
308 #define IsString 0x1000000 /* quick test for string instructions */
309 #define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
310 #define IsPrefix 0x4000000 /* opcode is a prefix */
311 #define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
312 #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
314 /* operand_types[i] describes the type of operand i. This is made
315 by OR'ing together all of the possible type masks. (e.g.
316 'operand_types[i] = Reg|Imm' specifies that operand i can be
317 either a register or an immediate operand. */
318 unsigned int operand_types[3];
320 /* operand_types[i] bits */
322 #define Reg8 0x1 /* 8 bit reg */
323 #define Reg16 0x2 /* 16 bit reg */
324 #define Reg32 0x4 /* 32 bit reg */
326 #define Imm8 0x8 /* 8 bit immediate */
327 #define Imm8S 0x10 /* 8 bit immediate sign extended */
328 #define Imm16 0x20 /* 16 bit immediate */
329 #define Imm32 0x40 /* 32 bit immediate */
330 #define Imm1 0x80 /* 1 bit immediate */
332 #define BaseIndex 0x100
333 /* Disp8,16,32 are used in different ways, depending on the
334 instruction. For jumps, they specify the size of the PC relative
335 displacement, for baseindex type instructions, they specify the
336 size of the offset relative to the base register, and for memory
337 offset instructions such as `mov 1234,%al' they specify the size of
338 the offset relative to the segment base. */
339 #define Disp8 0x200 /* 8 bit displacement */
340 #define Disp16 0x400 /* 16 bit displacement */
341 #define Disp32 0x800 /* 32 bit displacement */
343 #define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
344 #define ShiftCount 0x2000 /* register to hold shift cound = cl */
345 #define Control 0x4000 /* Control register */
346 #define Debug 0x8000 /* Debug register */
347 #define Test 0x10000 /* Test register */
348 #define FloatReg 0x20000 /* Float register */
349 #define FloatAcc 0x40000 /* Float stack top %st(0) */
350 #define SReg2 0x80000 /* 2 bit segment register */
351 #define SReg3 0x100000 /* 3 bit segment register */
352 #define Acc 0x200000 /* Accumulator %al or %ax or %eax */
353 #define JumpAbsolute 0x400000
354 #define RegMMX 0x800000 /* MMX register */
355 #define RegXMM 0x1000000 /* XMM registers in PIII */
356 #define EsSeg 0x2000000 /* String insn operand with fixed es segment */
357 /* InvMem is for instructions with a modrm byte that only allow a
358 general register encoding in the i.tm.mode and i.tm.regmem fields,
359 eg. control reg moves. They really ought to support a memory form,
360 but don't, so we add an InvMem flag to the register operand to
361 indicate that it should be encoded in the i.tm.regmem field. */
362 #define InvMem 0x4000000
364 #define Reg (Reg8|Reg16|Reg32) /* gen'l register */
365 #define WordReg (Reg16|Reg32)
366 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
367 #define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
368 #define Disp (Disp8|Disp16|Disp32) /* General displacement */
369 #define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
370 /* The following aliases are defined because the opcode table
371 carefully specifies the allowed memory types for each instruction.
372 At the moment we can only tell a memory reference size by the
373 instruction suffix, so there's not much point in defining Mem8,
374 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
375 the suffix directly to check memory operands. */
376 #define LLongMem AnyMem /* 64 bits (or more) */
377 #define LongMem AnyMem /* 32 bit memory ref */
378 #define ShortMem AnyMem /* 16 bit memory ref */
379 #define WordMem AnyMem /* 16 or 32 bit memory ref */
380 #define ByteMem AnyMem /* 8 bit memory ref */
385 'templates' is for grouping together 'template' structures for opcodes
386 of the same name. This is only used for storing the insns in the grand
387 ole hash table of insns.
388 The templates themselves start at START and range up to (but not including)
393 const template *start;
398 /* these are for register name --> number & type hash lookup */
402 unsigned int reg_type;
403 unsigned int reg_num;
410 unsigned int seg_prefix;
414 /* 386 operand encoding bytes: see 386 book for details of this. */
417 unsigned int regmem; /* codes register or memory operand */
418 unsigned int reg; /* codes register operand (or extended opcode) */
419 unsigned int mode; /* how to interpret regmem & reg */
423 /* 386 opcode byte to code indirect addressing. */
432 /* x86 arch names and features */
435 const char *name; /* arch name */
436 unsigned int flags; /* cpu feature flags */
440 /* The name of the global offset table generated by the compiler. Allow
441 this to be overridden if need be. */
442 #ifndef GLOBAL_OFFSET_TABLE_NAME
443 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
447 void i386_validate_fix PARAMS ((struct fix *));
448 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
453 #define md_operand(x)
455 extern const struct relax_type md_relax_table[];
456 #define TC_GENERIC_RELAX_TABLE md_relax_table
458 #define md_do_align(n, fill, len, max, around) \
459 if ((n) && !need_pass_2 \
460 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
461 && subseg_text_p (now_seg)) \
464 p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
465 (symbolS *) 0, (offsetT) (n), (char *) 0); \
470 extern void i386_align_code PARAMS ((fragS *, int));
472 #define HANDLE_ALIGN(fragP) \
473 if (fragP->fr_type == rs_align_code) \
474 i386_align_code (fragP, (fragP->fr_next->fr_address \
475 - fragP->fr_address \
478 /* call md_apply_fix3 with segment instead of md_apply_fix */
479 #define MD_APPLY_FIX3
481 void i386_print_statistics PARAMS ((FILE *));
482 #define tc_print_statistics i386_print_statistics
484 #define md_number_to_chars number_to_chars_littleendian
487 #define tc_init_after_args() sco_id ()
488 extern void sco_id PARAMS ((void));
491 #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
493 /* end of tc-i386.h */