1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
35 #include "opcode/i386.h"
38 #define TC_RELOC(X,Y) (Y)
41 static unsigned long mode_from_disp_size PARAMS ((unsigned long));
42 static int fits_in_signed_byte PARAMS ((long));
43 static int fits_in_unsigned_byte PARAMS ((long));
44 static int fits_in_unsigned_word PARAMS ((long));
45 static int fits_in_signed_word PARAMS ((long));
46 static int smallest_imm_type PARAMS ((long));
47 static void set_16bit_code_flag PARAMS ((int));
49 static bfd_reloc_code_real_type reloc
50 PARAMS ((int, int, bfd_reloc_code_real_type));
53 /* 'md_assemble ()' gathers together information and puts it into a
58 /* TM holds the template for the insn were currently assembling. */
60 /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */
62 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
64 /* OPERANDS gives the number of given operands. */
65 unsigned int operands;
67 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
68 of given register, displacement, memory operands and immediate
70 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
72 /* TYPES [i] is the type (see above #defines) which tells us how to
73 search through DISPS [i] & IMMS [i] & REGS [i] for the required
75 unsigned int types[MAX_OPERANDS];
77 /* Displacements (if given) for each operand. */
78 expressionS *disps[MAX_OPERANDS];
80 /* Relocation type for operand */
82 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
84 int disp_reloc[MAX_OPERANDS];
87 /* Immediate operands (if given) for each operand. */
88 expressionS *imms[MAX_OPERANDS];
90 /* Register operands (if given) for each operand. */
91 reg_entry *regs[MAX_OPERANDS];
93 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
94 the base index byte below. */
97 unsigned int log2_scale_factor;
99 /* SEG gives the seg_entry of this insn. It is equal to zero unless
100 an explicit segment override is given. */
101 const seg_entry *seg; /* segment for memory operands (if given) */
103 /* PREFIX holds all the given prefix opcodes (usually null).
104 PREFIXES is the size of PREFIX. */
105 /* richfix: really unsigned? */
106 unsigned char prefix[MAX_PREFIXES];
107 unsigned int prefixes;
109 /* RM and IB are the modrm byte and the base index byte where the
110 addressing modes of this insn are encoded. */
116 typedef struct _i386_insn i386_insn;
118 /* This array holds the chars that always start a comment. If the
119 pre-processor is disabled, these aren't very useful */
120 #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
121 const char comment_chars[] = "#/";
123 const char comment_chars[] = "#";
126 /* This array holds the chars that only start a comment at the beginning of
127 a line. If the line seems to have the form '# 123 filename'
128 .line and .file directives will appear in the pre-processed output */
129 /* Note that input_file.c hand checks for '#' at the beginning of the
130 first line of the input file. This is because the compiler outputs
131 #NO_APP at the beginning of its output. */
132 /* Also note that comments started like this one will always work if
133 '/' isn't otherwise defined. */
134 #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
135 const char line_comment_chars[] = "";
137 const char line_comment_chars[] = "/";
139 const char line_separator_chars[] = "";
141 /* Chars that can be used to separate mant from exp in floating point nums */
142 const char EXP_CHARS[] = "eE";
144 /* Chars that mean this number is a floating point constant */
147 const char FLT_CHARS[] = "fFdDxX";
149 /* tables for lexical analysis */
150 static char opcode_chars[256];
151 static char register_chars[256];
152 static char operand_chars[256];
153 static char space_chars[256];
154 static char identifier_chars[256];
155 static char digit_chars[256];
158 #define is_opcode_char(x) (opcode_chars[(unsigned char) x])
159 #define is_operand_char(x) (operand_chars[(unsigned char) x])
160 #define is_register_char(x) (register_chars[(unsigned char) x])
161 #define is_space_char(x) (space_chars[(unsigned char) x])
162 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
163 #define is_digit_char(x) (digit_chars[(unsigned char) x])
165 /* put here all non-digit non-letter charcters that may occur in an operand */
166 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
168 static char *ordinal_names[] = {"first", "second", "third"}; /* for printfs */
170 /* md_assemble() always leaves the strings it's passed unaltered. To
171 effect this we maintain a stack of saved characters that we've smashed
172 with '\0's (indicating end of strings for various sub-fields of the
173 assembler instruction). */
174 static char save_stack[32];
175 static char *save_stack_p; /* stack pointer */
176 #define END_STRING_AND_SAVE(s) *save_stack_p++ = *s; *s = '\0'
177 #define RESTORE_END_STRING(s) *s = *--save_stack_p
179 /* The instruction we're assembling. */
182 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
183 static expressionS disp_expressions[2], im_expressions[2];
185 /* pointers to ebp & esp entries in reg_hash hash table */
186 static reg_entry *ebp, *esp;
188 static int this_operand; /* current operand we are working on */
190 static int flag_do_long_jump; /* FIXME what does this do? */
192 static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */
194 /* Interface to relax_segment.
195 There are 2 relax states for 386 jump insns: one for conditional &
196 one for unconditional jumps. This is because the these two types
197 of jumps add different sizes to frags when we're figuring out what
198 sort of jump to choose to reach a given label. */
201 #define COND_JUMP 1 /* conditional jump */
202 #define UNCOND_JUMP 2 /* unconditional jump */
207 #define UNKNOWN_SIZE 3
211 #define INLINE __inline__
217 #define ENCODE_RELAX_STATE(type,size) \
218 ((relax_substateT)((type<<2) | (size)))
219 #define SIZE_FROM_RELAX_STATE(s) \
220 ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) )
222 const relax_typeS md_relax_table[] =
225 1) most positive reach of this state,
226 2) most negative reach of this state,
227 3) how many bytes this mode will add to the size of the current frag
228 4) which index into the table to try if we can't fit into this one.
235 /* For now we don't use word displacement jumps; they may be
237 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
238 /* word conditionals add 3 bytes to frag:
239 2 opcode prefix; 1 displacement bytes */
240 {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
241 /* dword conditionals adds 4 bytes to frag:
242 1 opcode prefix; 3 displacement bytes */
246 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
247 /* word jmp adds 2 bytes to frag:
248 1 opcode prefix; 1 displacement bytes */
249 {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
250 /* dword jmp adds 3 bytes to frag:
251 0 opcode prefix; 3 displacement bytes */
259 i386_align_code (fragP, count)
263 /* Various efficient no-op patterns for aligning code labels. */
264 /* Note: Don't try to assemble the instructions in the comments. */
265 /* 0L and 0w are not legal */
266 static const char f32_1[] =
268 static const char f32_2[] =
269 {0x89,0xf6}; /* movl %esi,%esi */
270 static const char f32_3[] =
271 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
272 static const char f32_4[] =
273 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
274 static const char f32_5[] =
276 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
277 static const char f32_6[] =
278 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
279 static const char f32_7[] =
280 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
281 static const char f32_8[] =
283 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
284 static const char f32_9[] =
285 {0x89,0xf6, /* movl %esi,%esi */
286 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
287 static const char f32_10[] =
288 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
289 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
290 static const char f32_11[] =
291 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
292 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
293 static const char f32_12[] =
294 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
295 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
296 static const char f32_13[] =
297 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
298 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
299 static const char f32_14[] =
300 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
301 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
302 static const char f32_15[] =
303 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
304 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
305 static const char f16_4[] =
306 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
307 static const char f16_5[] =
309 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
310 static const char f16_6[] =
311 {0x89,0xf6, /* mov %si,%si */
312 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
313 static const char f16_7[] =
314 {0x8d,0x74,0x00, /* lea 0(%si),%si */
315 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
316 static const char f16_8[] =
317 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
318 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
319 static const char *const f32_patt[] = {
320 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
321 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
323 static const char *const f16_patt[] = {
324 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
325 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
328 if (count > 0 && count <= 15)
332 memcpy(fragP->fr_literal + fragP->fr_fix,
333 f16_patt[count - 1], count);
334 if (count > 8) /* adjust jump offset */
335 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
338 memcpy(fragP->fr_literal + fragP->fr_fix,
339 f32_patt[count - 1], count);
340 fragP->fr_var = count;
344 static char *output_invalid PARAMS ((int c));
345 static int i386_operand PARAMS ((char *operand_string));
346 static reg_entry *parse_register PARAMS ((char *reg_string));
348 static void s_bss PARAMS ((int));
351 symbolS *GOT_symbol; /* Pre-defined "__GLOBAL_OFFSET_TABLE" */
353 static INLINE unsigned long
354 mode_from_disp_size (t)
357 return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0;
362 /* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */
364 static INLINE unsigned long
365 opcode_suffix_to_type (s)
368 return (s == BYTE_OPCODE_SUFFIX
369 ? Byte : (s == WORD_OPCODE_SUFFIX
371 } /* opcode_suffix_to_type() */
375 fits_in_signed_byte (num)
378 return (num >= -128) && (num <= 127);
379 } /* fits_in_signed_byte() */
382 fits_in_unsigned_byte (num)
385 return (num & 0xff) == num;
386 } /* fits_in_unsigned_byte() */
389 fits_in_unsigned_word (num)
392 return (num & 0xffff) == num;
393 } /* fits_in_unsigned_word() */
396 fits_in_signed_word (num)
399 return (-32768 <= num) && (num <= 32767);
400 } /* fits_in_signed_word() */
403 smallest_imm_type (num)
407 /* This code is disabled because all the Imm1 forms in the opcode table
408 are slower on the i486, and they're the versions with the implicitly
409 specified single-position displacement, which has another syntax if
410 you really want to use that form. If you really prefer to have the
411 one-byte-shorter Imm1 form despite these problems, re-enable this
414 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
416 return (fits_in_signed_byte (num)
417 ? (Imm8S | Imm8 | Imm16 | Imm32)
418 : fits_in_unsigned_byte (num)
419 ? (Imm8 | Imm16 | Imm32)
420 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
423 } /* smallest_imm_type() */
426 set_16bit_code_flag (new_16bit_code_flag)
427 int new_16bit_code_flag;
429 flag_16bit_code = new_16bit_code_flag;
432 const pseudo_typeS md_pseudo_table[] =
437 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
438 {"align", s_align_bytes, 0},
440 {"align", s_align_ptwo, 0},
442 {"ffloat", float_cons, 'f'},
443 {"dfloat", float_cons, 'd'},
444 {"tfloat", float_cons, 'x'},
446 {"noopt", s_ignore, 0},
447 {"optim", s_ignore, 0},
448 {"code16", set_16bit_code_flag, 1},
449 {"code32", set_16bit_code_flag, 0},
453 /* for interface with expression () */
454 extern char *input_line_pointer;
456 /* obstack for constructing various things in md_begin */
459 /* hash table for opcode lookup */
460 static struct hash_control *op_hash;
461 /* hash table for register lookup */
462 static struct hash_control *reg_hash;
463 /* hash table for prefix lookup */
464 static struct hash_control *prefix_hash;
470 const char *hash_err;
472 obstack_begin (&o, 4096);
474 /* initialize op_hash hash table */
475 op_hash = hash_new ();
478 register const template *optab;
479 register templates *core_optab;
482 optab = i386_optab; /* setup for loop */
483 prev_name = optab->name;
484 obstack_grow (&o, optab, sizeof (template));
485 core_optab = (templates *) xmalloc (sizeof (templates));
487 for (optab++; optab < i386_optab_end; optab++)
489 if (!strcmp (optab->name, prev_name))
491 /* same name as before --> append to current template list */
492 obstack_grow (&o, optab, sizeof (template));
496 /* different name --> ship out current template list;
497 add to hash table; & begin anew */
498 /* Note: end must be set before start! since obstack_next_free
499 changes upon opstack_finish */
500 core_optab->end = (template *) obstack_next_free (&o);
501 core_optab->start = (template *) obstack_finish (&o);
502 hash_err = hash_insert (op_hash, prev_name, (char *) core_optab);
506 as_fatal ("Internal Error: Can't hash %s: %s", prev_name,
509 prev_name = optab->name;
510 core_optab = (templates *) xmalloc (sizeof (templates));
511 obstack_grow (&o, optab, sizeof (template));
516 /* initialize reg_hash hash table */
517 reg_hash = hash_new ();
519 register const reg_entry *regtab;
521 for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++)
523 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
529 esp = (reg_entry *) hash_find (reg_hash, "esp");
530 ebp = (reg_entry *) hash_find (reg_hash, "ebp");
532 /* initialize reg_hash hash table */
533 prefix_hash = hash_new ();
535 register const prefix_entry *prefixtab;
537 for (prefixtab = i386_prefixtab;
538 prefixtab < i386_prefixtab_end; prefixtab++)
540 hash_err = hash_insert (prefix_hash, prefixtab->prefix_name,
547 /* fill in lexical tables: opcode_chars, operand_chars, space_chars */
552 for (c = 0; c < 256; c++)
554 if (islower (c) || isdigit (c))
557 register_chars[c] = c;
559 else if (isupper (c))
561 opcode_chars[c] = tolower (c);
562 register_chars[c] = opcode_chars[c];
564 else if (c == PREFIX_SEPERATOR)
568 else if (c == ')' || c == '(')
570 register_chars[c] = c;
573 if (isupper (c) || islower (c) || isdigit (c))
574 operand_chars[c] = c;
576 if (isdigit (c) || c == '-')
579 if (isalpha (c) || c == '_' || c == '.' || isdigit (c))
580 identifier_chars[c] = c;
583 identifier_chars['@'] = '@';
586 if (c == ' ' || c == '\t')
590 for (p = operand_special_chars; *p != '\0'; p++)
591 operand_chars[(unsigned char) *p] = *p;
594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
595 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
597 record_alignment (text_section, 2);
598 record_alignment (data_section, 2);
599 record_alignment (bss_section, 2);
605 i386_print_statistics (file)
608 hash_print_statistics (file, "i386 opcode", op_hash);
609 hash_print_statistics (file, "i386 register", reg_hash);
610 hash_print_statistics (file, "i386 prefix", prefix_hash);
616 /* debugging routines for md_assemble */
617 static void pi PARAMS ((char *, i386_insn *));
618 static void pte PARAMS ((template *));
619 static void pt PARAMS ((unsigned int));
620 static void pe PARAMS ((expressionS *));
621 static void ps PARAMS ((symbolS *));
628 register template *p;
631 fprintf (stdout, "%s: template ", line);
633 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
634 x->rm.mode, x->rm.reg, x->rm.regmem);
635 fprintf (stdout, " base %x index %x scale %x\n",
636 x->bi.base, x->bi.index, x->bi.scale);
637 for (i = 0; i < x->operands; i++)
639 fprintf (stdout, " #%d: ", i + 1);
641 fprintf (stdout, "\n");
643 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX))
644 fprintf (stdout, "%s\n", x->regs[i]->reg_name);
645 if (x->types[i] & Imm)
647 if (x->types[i] & (Disp | Abs))
657 fprintf (stdout, " %d operands ", t->operands);
658 fprintf (stdout, "opcode %x ",
660 if (t->extension_opcode != None)
661 fprintf (stdout, "ext %x ", t->extension_opcode);
662 if (t->opcode_modifier & D)
663 fprintf (stdout, "D");
664 if (t->opcode_modifier & W)
665 fprintf (stdout, "W");
666 fprintf (stdout, "\n");
667 for (i = 0; i < t->operands; i++)
669 fprintf (stdout, " #%d type ", i + 1);
670 pt (t->operand_types[i]);
671 fprintf (stdout, "\n");
679 fprintf (stdout, " operation %d\n", e->X_op);
680 fprintf (stdout, " add_number %d (%x)\n",
681 e->X_add_number, e->X_add_number);
684 fprintf (stdout, " add_symbol ");
685 ps (e->X_add_symbol);
686 fprintf (stdout, "\n");
690 fprintf (stdout, " op_symbol ");
692 fprintf (stdout, "\n");
700 fprintf (stdout, "%s type %s%s",
702 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
703 segment_name (S_GET_SEGMENT (s)));
724 { BaseIndex, "BaseIndex" },
734 { InOutPortReg, "InOutPortReg" },
735 { ShiftCount, "ShiftCount" },
737 { Control, "control reg" },
738 { Test, "test reg" },
739 { FloatReg, "FReg" },
740 { FloatAcc, "FAcc" },
741 { JumpAbsolute, "Jump Absolute" },
750 register struct type_name *ty;
754 fprintf (stdout, "Unknown");
758 for (ty = type_names; ty->mask; ty++)
760 fprintf (stdout, "%s, ", ty->tname);
765 #endif /* DEBUG386 */
768 static bfd_reloc_code_real_type
769 reloc (size, pcrel, other)
772 bfd_reloc_code_real_type other;
774 if (other != NO_RELOC) return other;
779 case 1: return BFD_RELOC_8_PCREL;
780 case 2: return BFD_RELOC_16_PCREL;
781 case 4: return BFD_RELOC_32_PCREL;
786 case 1: return BFD_RELOC_8;
787 case 2: return BFD_RELOC_16;
788 case 4: return BFD_RELOC_32;
791 as_bad ("Can not do %d byte %srelocation", size,
792 pcrel ? "pc-relative " : "");
793 return BFD_RELOC_NONE;
797 * Here we decide which fixups can be adjusted to make them relative to
798 * the beginning of the section instead of the symbol. Basically we need
799 * to make sure that the dynamic relocations are done correctly, so in
800 * some cases we force the original symbol to be used.
803 tc_i386_fix_adjustable(fixP)
807 /* Prevent all adjustments to global symbols. */
808 if (S_IS_EXTERN (fixP->fx_addsy))
810 if (S_IS_WEAK (fixP->fx_addsy))
812 #endif /* ! defined (OBJ_AOUT) */
813 /* adjust_reloc_syms doesn't know about the GOT */
814 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
815 || fixP->fx_r_type == BFD_RELOC_386_PLT32
816 || fixP->fx_r_type == BFD_RELOC_386_GOT32)
821 #define reloc(SIZE,PCREL,OTHER) 0
822 #define BFD_RELOC_32 0
823 #define BFD_RELOC_32_PCREL 0
824 #define BFD_RELOC_386_PLT32 0
825 #define BFD_RELOC_386_GOT32 0
826 #define BFD_RELOC_386_GOTOFF 0
829 /* This is the guts of the machine-dependent assembler. LINE points to a
830 machine dependent instruction. This function is supposed to emit
831 the frags/bytes it assembles to. */
837 /* Holds template once we've found it. */
840 /* Count the size of the instruction generated. */
843 /* Possible templates for current insn */
844 templates *current_templates = (templates *) 0;
848 /* Initialize globals. */
849 memset (&i, '\0', sizeof (i));
850 for (j = 0; j < MAX_OPERANDS; j++)
851 i.disp_reloc[j] = NO_RELOC;
852 memset (disp_expressions, '\0', sizeof (disp_expressions));
853 memset (im_expressions, '\0', sizeof (im_expressions));
854 save_stack_p = save_stack; /* reset stack pointer */
856 /* Fist parse an opcode & call i386_operand for the operands.
857 We assume that the scrubber has arranged it so that line[0] is the valid
858 start of a (possibly prefixed) opcode. */
862 /* 1 if operand is pending after ','. */
863 unsigned int expecting_operand = 0;
864 /* 1 if we found a prefix only acceptable with string insns. */
865 unsigned int expecting_string_instruction = 0;
866 /* Non-zero if operand parens not balanced. */
867 unsigned int paren_not_balanced;
868 char *token_start = l;
870 while (!is_space_char (*l) && *l != END_OF_INSN)
872 if (!is_opcode_char (*l))
874 as_bad ("invalid character %s in opcode", output_invalid (*l));
877 else if (*l != PREFIX_SEPERATOR)
879 *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */
884 /* This opcode's got a prefix. */
886 prefix_entry *prefix;
888 if (l == token_start)
890 as_bad ("expecting prefix; got nothing");
893 END_STRING_AND_SAVE (l);
894 prefix = (prefix_entry *) hash_find (prefix_hash, token_start);
897 as_bad ("no such opcode prefix ('%s')", token_start);
900 RESTORE_END_STRING (l);
901 /* check for repeated prefix */
902 for (q = 0; q < i.prefixes; q++)
903 if (i.prefix[q] == prefix->prefix_code)
905 as_bad ("same prefix used twice; you don't really want this!");
908 if (i.prefixes == MAX_PREFIXES)
910 as_bad ("too many opcode prefixes");
913 i.prefix[i.prefixes++] = prefix->prefix_code;
914 if (prefix->prefix_code == REPE || prefix->prefix_code == REPNE)
915 expecting_string_instruction = 1;
916 /* skip past PREFIX_SEPERATOR and reset token_start */
920 END_STRING_AND_SAVE (l);
921 if (token_start == l)
923 as_bad ("expecting opcode; got nothing");
927 /* Lookup insn in hash; try intel & att naming conventions if appropriate;
928 that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */
929 current_templates = (templates *) hash_find (op_hash, token_start);
930 if (!current_templates)
932 int last_index = strlen (token_start) - 1;
933 char last_char = token_start[last_index];
936 case DWORD_OPCODE_SUFFIX:
937 case WORD_OPCODE_SUFFIX:
938 case BYTE_OPCODE_SUFFIX:
939 token_start[last_index] = '\0';
940 current_templates = (templates *) hash_find (op_hash, token_start);
941 token_start[last_index] = last_char;
942 i.suffix = last_char;
944 if (!current_templates)
946 as_bad ("no such 386 instruction: `%s'", token_start);
950 RESTORE_END_STRING (l);
952 /* check for rep/repne without a string instruction */
953 if (expecting_string_instruction &&
954 !IS_STRING_INSTRUCTION (current_templates->
957 as_bad ("expecting string instruction after rep/repne");
961 /* There may be operands to parse. */
962 if (*l != END_OF_INSN &&
963 /* For string instructions, we ignore any operands if given. This
964 kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where
965 the operands are always going to be the same, and are not really
966 encoded in machine code. */
967 !IS_STRING_INSTRUCTION (current_templates->
973 /* skip optional white space before operand */
974 while (!is_operand_char (*l) && *l != END_OF_INSN)
976 if (!is_space_char (*l))
978 as_bad ("invalid character %s before %s operand",
980 ordinal_names[i.operands]);
985 token_start = l; /* after white space */
986 paren_not_balanced = 0;
987 while (paren_not_balanced || *l != ',')
989 if (*l == END_OF_INSN)
991 if (paren_not_balanced)
993 as_bad ("unbalanced parenthesis in %s operand.",
994 ordinal_names[i.operands]);
998 break; /* we are done */
1000 else if (!is_operand_char (*l) && !is_space_char (*l))
1002 as_bad ("invalid character %s in %s operand",
1003 output_invalid (*l),
1004 ordinal_names[i.operands]);
1008 ++paren_not_balanced;
1010 --paren_not_balanced;
1013 if (l != token_start)
1014 { /* yes, we've read in another operand */
1015 unsigned int operand_ok;
1016 this_operand = i.operands++;
1017 if (i.operands > MAX_OPERANDS)
1019 as_bad ("spurious operands; (%d operands/instruction max)",
1023 /* now parse operand adding info to 'i' as we go along */
1024 END_STRING_AND_SAVE (l);
1025 operand_ok = i386_operand (token_start);
1026 RESTORE_END_STRING (l); /* restore old contents */
1032 if (expecting_operand)
1034 expecting_operand_after_comma:
1035 as_bad ("expecting operand after ','; got nothing");
1040 as_bad ("expecting operand before ','; got nothing");
1045 /* now *l must be either ',' or END_OF_INSN */
1048 if (*++l == END_OF_INSN)
1049 { /* just skip it, if it's \n complain */
1050 goto expecting_operand_after_comma;
1052 expecting_operand = 1;
1055 while (*l != END_OF_INSN); /* until we get end of insn */
1059 /* Now we've parsed the opcode into a set of templates, and have the
1062 Next, we find a template that matches the given insn,
1063 making sure the overlap of the given operands types is consistent
1064 with the template operand types. */
1066 #define MATCH(overlap,given_type) \
1068 (((overlap & (JumpAbsolute|BaseIndex|Mem8)) \
1069 == (given_type & (JumpAbsolute|BaseIndex|Mem8))) \
1070 || (overlap == InOutPortReg)))
1073 /* If m0 and m1 are register matches they must be consistent
1074 with the expected operand types t0 and t1.
1075 That is, if both m0 & m1 are register matches
1076 i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ?
1077 then, either 1. or 2. must be true:
1078 1. the expected operand type register overlap is null:
1079 (t0 & t1 & Reg) == 0
1081 the given register overlap is null:
1082 (m0 & m1 & Reg) == 0
1083 2. the expected operand type register overlap == the given
1084 operand type overlap: (t0 & t1 & m0 & m1 & Reg).
1086 #define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \
1087 ( ((m0 & (Reg)) && (m1 & (Reg))) ? \
1088 ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \
1089 ((t0 & t1) & (m0 & m1) & (Reg)) \
1092 register unsigned int overlap0, overlap1;
1094 unsigned int overlap2;
1095 unsigned int found_reverse_match;
1097 overlap0 = overlap1 = overlap2 = found_reverse_match = 0;
1098 for (t = current_templates->start;
1099 t < current_templates->end;
1102 /* must have right number of operands */
1103 if (i.operands != t->operands)
1105 else if (!t->operands)
1106 break; /* 0 operands always matches */
1108 overlap0 = i.types[0] & t->operand_types[0];
1109 switch (t->operands)
1112 if (!MATCH (overlap0, i.types[0]))
1117 overlap1 = i.types[1] & t->operand_types[1];
1118 if (!MATCH (overlap0, i.types[0]) ||
1119 !MATCH (overlap1, i.types[1]) ||
1120 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1121 t->operand_types[0],
1122 t->operand_types[1]))
1125 /* check if other direction is valid ... */
1126 if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS))
1129 /* try reversing direction of operands */
1130 overlap0 = i.types[0] & t->operand_types[1];
1131 overlap1 = i.types[1] & t->operand_types[0];
1132 if (!MATCH (overlap0, i.types[0]) ||
1133 !MATCH (overlap1, i.types[1]) ||
1134 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1135 t->operand_types[0],
1136 t->operand_types[1]))
1138 /* does not match either direction */
1141 /* found a reverse match here -- slip through */
1142 /* found_reverse_match holds which of D or FloatD we've found */
1143 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1144 } /* endif: not forward match */
1145 /* found either forward/reverse 2 operand match here */
1146 if (t->operands == 3)
1148 overlap2 = i.types[2] & t->operand_types[2];
1149 if (!MATCH (overlap2, i.types[2]) ||
1150 !CONSISTENT_REGISTER_MATCH (overlap0, overlap2,
1151 t->operand_types[0],
1152 t->operand_types[2]) ||
1153 !CONSISTENT_REGISTER_MATCH (overlap1, overlap2,
1154 t->operand_types[1],
1155 t->operand_types[2]))
1158 /* found either forward/reverse 2 or 3 operand match here:
1159 slip through to break */
1161 break; /* we've found a match; break out of loop */
1162 } /* for (t = ... */
1163 if (t == current_templates->end)
1164 { /* we found no match */
1165 as_bad ("operands given don't match any known 386 instruction");
1169 /* Copy the template we found (we may change it!). */
1171 t = &i.tm; /* alter new copy of template */
1173 /* If the matched instruction specifies an explicit opcode suffix,
1174 use it - and make sure none has already been specified. */
1175 if (t->opcode_modifier & (Data16|Data32))
1179 as_bad ("extraneous opcode suffix given");
1182 if (t->opcode_modifier & Data16)
1183 i.suffix = WORD_OPCODE_SUFFIX;
1185 i.suffix = DWORD_OPCODE_SUFFIX;
1188 /* If there's no opcode suffix we try to invent one based on register
1190 if (!i.suffix && i.reg_operands)
1192 /* We take i.suffix from the LAST register operand specified. This
1193 assumes that the last register operands is the destination register
1196 for (op = 0; op < MAX_OPERANDS; op++)
1197 if (i.types[op] & Reg)
1199 i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX :
1200 (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX :
1201 DWORD_OPCODE_SUFFIX);
1204 else if (i.suffix != 0
1205 && i.reg_operands != 0
1206 && (i.types[i.operands - 1] & Reg) != 0)
1210 /* If the last operand is a register, make sure it is
1211 compatible with the suffix. */
1218 case BYTE_OPCODE_SUFFIX:
1219 /* If this is an eight bit register, it's OK. If it's the
1220 16 or 32 bit version of an eight bit register, we will
1221 just use the low portion, and that's OK too. */
1222 if ((i.types[i.operands - 1] & Reg8) == 0
1223 && i.regs[i.operands - 1]->reg_num >= 4)
1226 case WORD_OPCODE_SUFFIX:
1227 case DWORD_OPCODE_SUFFIX:
1228 /* We don't insist on the presence or absence of the e
1229 prefix on the register, but we reject eight bit
1231 if ((i.types[i.operands - 1] & Reg8) != 0)
1235 as_bad ("register does not match opcode suffix");
1238 /* Make still unresolved immediate matches conform to size of immediate
1239 given in i.suffix. Note: overlap2 cannot be an immediate!
1241 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1242 && overlap0 != Imm8 && overlap0 != Imm8S
1243 && overlap0 != Imm16 && overlap0 != Imm32)
1247 as_bad ("no opcode suffix given; can't determine immediate size");
1250 overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1251 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1253 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1254 && overlap1 != Imm8 && overlap1 != Imm8S
1255 && overlap1 != Imm16 && overlap1 != Imm32)
1259 as_bad ("no opcode suffix given; can't determine immediate size");
1262 overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1263 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1266 i.types[0] = overlap0;
1267 i.types[1] = overlap1;
1268 i.types[2] = overlap2;
1270 if (overlap0 & ImplicitRegister)
1272 if (overlap1 & ImplicitRegister)
1274 if (overlap2 & ImplicitRegister)
1276 if (overlap0 & Imm1)
1277 i.imm_operands = 0; /* kludge for shift insns */
1279 if (found_reverse_match)
1282 save = t->operand_types[0];
1283 t->operand_types[0] = t->operand_types[1];
1284 t->operand_types[1] = save;
1287 /* Finalize opcode. First, we change the opcode based on the operand
1288 size given by i.suffix: we never have to change things for byte insns,
1289 or when no opcode suffix is need to size the operands. */
1291 if (!i.suffix && (t->opcode_modifier & W))
1293 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1297 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1299 /* Select between byte and word/dword operations. */
1300 if (t->opcode_modifier & W)
1301 t->base_opcode |= W;
1302 /* Now select between word & dword operations via the
1303 operand size prefix. */
1304 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1306 if (i.prefixes == MAX_PREFIXES)
1308 as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes",
1312 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1316 /* For insns with operands there are more diddles to do to the opcode. */
1319 /* Default segment register this instruction will use
1320 for memory accesses. 0 means unknown.
1321 This is only for optimizing out unnecessary segment overrides. */
1322 const seg_entry *default_seg = 0;
1324 /* True if this instruction uses a memory addressing mode,
1325 and therefore may need an address-size prefix. */
1326 int uses_mem_addrmode = 0;
1329 /* If we found a reverse match we must alter the opcode direction bit
1330 found_reverse_match holds bit to set (different for int &
1333 if (found_reverse_match)
1335 t->base_opcode |= found_reverse_match;
1338 /* The imul $imm, %reg instruction is converted into
1339 imul $imm, %reg, %reg. */
1340 if (t->opcode_modifier & imulKludge)
1342 /* Pretend we saw the 3 operand case. */
1343 i.regs[2] = i.regs[1];
1347 /* The clr %reg instruction is converted into xor %reg, %reg. */
1348 if (t->opcode_modifier & iclrKludge)
1350 i.regs[1] = i.regs[0];
1354 /* Certain instructions expect the destination to be in the i.rm.reg
1355 field. This is by far the exceptional case. For these
1356 instructions, if the source operand is a register, we must reverse
1357 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1358 that the two register operands were given in the reverse order. */
1359 if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
1361 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1362 unsigned int second_reg_operand = first_reg_operand + 1;
1363 reg_entry *tmp = i.regs[first_reg_operand];
1364 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1365 i.regs[second_reg_operand] = tmp;
1368 if (t->opcode_modifier & ShortForm)
1370 /* The register or float register operand is in operand 0 or 1. */
1371 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1372 /* Register goes in low 3 bits of opcode. */
1373 t->base_opcode |= i.regs[op]->reg_num;
1375 else if (t->opcode_modifier & ShortFormW)
1377 /* Short form with 0x8 width bit. Register is always dest. operand */
1378 t->base_opcode |= i.regs[1]->reg_num;
1379 if (i.suffix == WORD_OPCODE_SUFFIX ||
1380 i.suffix == DWORD_OPCODE_SUFFIX)
1381 t->base_opcode |= 0x8;
1383 else if (t->opcode_modifier & Seg2ShortForm)
1385 if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
1387 as_bad ("you can't 'pop cs' on the 386.");
1390 t->base_opcode |= (i.regs[0]->reg_num << 3);
1392 else if (t->opcode_modifier & Seg3ShortForm)
1394 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1395 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1396 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1397 to change the opcode. */
1398 if (i.regs[0]->reg_num == 5)
1399 t->base_opcode |= 0x08;
1401 else if ((t->base_opcode & ~DW) == MOV_AX_DISP32)
1403 /* This is a special non-modrm instruction
1404 that addresses memory with a 32-bit displacement mode anyway,
1405 and thus requires an address-size prefix if in 16-bit mode. */
1406 uses_mem_addrmode = 1;
1409 else if (t->opcode_modifier & Modrm)
1411 /* The opcode is completed (modulo t->extension_opcode which must
1412 be put into the modrm byte.
1413 Now, we make the modrm & index base bytes based on all the info
1416 /* i.reg_operands MUST be the number of real register operands;
1417 implicit registers do not count. */
1418 if (i.reg_operands == 2)
1420 unsigned int source, dest;
1421 source = ((i.types[0]
1432 /* We must be careful to make sure that all
1433 segment/control/test/debug/MMX registers go into
1434 the i.rm.reg field (despite the whether they are
1435 source or destination operands). */
1436 if (i.regs[dest]->reg_type
1437 & (SReg2 | SReg3 | Control | Debug | Test | RegMMX))
1439 i.rm.reg = i.regs[dest]->reg_num;
1440 i.rm.regmem = i.regs[source]->reg_num;
1444 i.rm.reg = i.regs[source]->reg_num;
1445 i.rm.regmem = i.regs[dest]->reg_num;
1449 { /* if it's not 2 reg operands... */
1452 unsigned int fake_zero_displacement = 0;
1453 unsigned int op = (i.types[0] & Mem) ? 0 : ((i.types[1] & Mem) ? 1 : 2);
1455 /* Encode memory operand into modrm byte and base index
1458 if (i.base_reg == esp && !i.index_reg)
1460 /* <disp>(%esp) becomes two byte modrm with no index
1462 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1463 i.rm.mode = mode_from_disp_size (i.types[op]);
1464 i.bi.base = ESP_REG_NUM;
1465 i.bi.index = NO_INDEX_REGISTER;
1466 i.bi.scale = 0; /* Must be zero! */
1468 else if (i.base_reg == ebp && !i.index_reg)
1470 if (!(i.types[op] & Disp))
1472 /* Must fake a zero byte displacement. There is
1473 no direct way to code '(%ebp)' directly. */
1474 fake_zero_displacement = 1;
1475 /* fake_zero_displacement code does not set this. */
1476 i.types[op] |= Disp8;
1478 i.rm.mode = mode_from_disp_size (i.types[op]);
1479 i.rm.regmem = EBP_REG_NUM;
1481 else if (!i.base_reg && (i.types[op] & BaseIndex))
1483 /* There are three cases here.
1484 Case 1: '<32bit disp>(,1)' -- indirect absolute.
1485 (Same as cases 2 & 3 with NO index register)
1486 Case 2: <32bit disp> (,<index>) -- no base register with disp
1487 Case 3: (, <index>) --- no base register;
1488 no disp (must add 32bit 0 disp). */
1489 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1490 i.rm.mode = 0; /* 32bit mode */
1491 i.bi.base = NO_BASE_REGISTER;
1492 i.types[op] &= ~Disp;
1493 i.types[op] |= Disp32; /* Must be 32bit! */
1495 { /* case 2 or case 3 */
1496 i.bi.index = i.index_reg->reg_num;
1497 i.bi.scale = i.log2_scale_factor;
1498 if (i.disp_operands == 0)
1499 fake_zero_displacement = 1; /* case 3 */
1503 i.bi.index = NO_INDEX_REGISTER;
1507 else if (i.disp_operands && !i.base_reg && !i.index_reg)
1509 /* Operand is just <32bit disp> */
1510 i.rm.regmem = EBP_REG_NUM;
1512 i.types[op] &= ~Disp;
1513 i.types[op] |= Disp32;
1517 /* It's not a special case; rev'em up. */
1518 i.rm.regmem = i.base_reg->reg_num;
1519 i.rm.mode = mode_from_disp_size (i.types[op]);
1522 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1523 i.bi.base = i.base_reg->reg_num;
1524 i.bi.index = i.index_reg->reg_num;
1525 i.bi.scale = i.log2_scale_factor;
1526 if (i.base_reg == ebp && i.disp_operands == 0)
1528 fake_zero_displacement = 1;
1529 i.types[op] |= Disp8;
1530 i.rm.mode = mode_from_disp_size (i.types[op]);
1534 if (fake_zero_displacement)
1536 /* Fakes a zero displacement assuming that i.types[op]
1537 holds the correct displacement size. */
1538 exp = &disp_expressions[i.disp_operands++];
1540 exp->X_op = O_constant;
1541 exp->X_add_number = 0;
1542 exp->X_add_symbol = (symbolS *) 0;
1543 exp->X_op_symbol = (symbolS *) 0;
1546 /* Find the default segment for the memory
1547 operand. Used to optimize out explicit segment
1549 if (i.seg && (t->opcode_modifier & LinearAddress) == 0)
1551 unsigned int seg_index;
1553 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING)
1555 seg_index = (i.rm.mode << 3) | i.bi.base;
1556 default_seg = two_byte_segment_defaults[seg_index];
1560 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1561 default_seg = one_byte_segment_defaults[seg_index];
1566 /* Fill in i.rm.reg or i.rm.regmem field with register
1567 operand (if any) based on
1568 t->extension_opcode. Again, we must be careful to
1569 make sure that segment/control/debug/test/MMX
1570 registers are coded into the i.rm.reg field. */
1575 & (Reg | SReg2 | SReg3 | Control | Debug
1579 & (Reg | SReg2 | SReg3 | Control | Debug
1583 /* If there is an extension opcode to put here, the
1584 register number must be put into the regmem field. */
1585 if (t->extension_opcode != None)
1586 i.rm.regmem = i.regs[op]->reg_num;
1588 i.rm.reg = i.regs[op]->reg_num;
1590 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1591 we must set it to 3 to indicate this is a register
1592 operand int the regmem field */
1593 if (!i.mem_operands)
1597 /* Fill in i.rm.reg field with extension opcode (if any). */
1598 if (t->extension_opcode != None)
1599 i.rm.reg = t->extension_opcode;
1603 uses_mem_addrmode = 1;
1606 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1607 so if we're writing 16-bit code and using a memory addressing mode,
1608 always spew out an address size prefix. */
1609 if (uses_mem_addrmode && flag_16bit_code)
1611 if (i.prefixes == MAX_PREFIXES)
1613 as_bad ("%d prefixes given and address size override gives too many prefixes",
1617 i.prefix[i.prefixes++] = ADDR_PREFIX_OPCODE;
1620 /* If a segment was explicitly specified,
1621 and the specified segment is not the default,
1622 use an opcode prefix to select it.
1623 If we never figured out what the default segment is,
1624 then default_seg will be zero at this point,
1625 and the specified segment prefix will always be used. */
1626 if ((i.seg) && (i.seg != default_seg))
1628 if (i.prefixes == MAX_PREFIXES)
1630 as_bad ("%d prefixes given and %s segment override gives too many prefixes",
1631 MAX_PREFIXES, i.seg->seg_name);
1634 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1639 /* Handle conversion of 'int $3' --> special int3 insn. */
1640 if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
1642 t->base_opcode = INT3_OPCODE;
1646 /* We are ready to output the insn. */
1651 if (t->opcode_modifier & Jump)
1653 unsigned long n = i.disps[0]->X_add_number;
1655 if (i.disps[0]->X_op == O_constant)
1657 if (fits_in_signed_byte (n))
1661 p[0] = t->base_opcode;
1665 { /* It's an absolute word/dword displacement. */
1667 /* Use only 16-bit jumps for 16-bit code,
1668 because text segments are limited to 64K anyway;
1669 use only 32-bit jumps for 32-bit code,
1670 because they're faster. */
1671 int jmp_size = flag_16bit_code ? 2 : 4;
1672 if (flag_16bit_code && !fits_in_signed_word (n))
1674 as_bad ("16-bit jump out of range");
1678 if (t->base_opcode == JUMP_PC_RELATIVE)
1680 /* unconditional jump */
1681 p = frag_more (1 + jmp_size);
1682 insn_size += 1 + jmp_size;
1684 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1688 /* conditional jump */
1689 p = frag_more (2 + jmp_size);
1690 insn_size += 2 + jmp_size;
1691 p[0] = TWO_BYTE_OPCODE_ESCAPE;
1692 p[1] = t->base_opcode + 0x10;
1693 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1699 if (flag_16bit_code)
1701 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1705 /* It's a symbol; end frag & setup for relax.
1706 Make sure there are more than 6 chars left in the current frag;
1707 if not we'll have to start a new one. */
1711 p[0] = t->base_opcode;
1712 frag_var (rs_machine_dependent,
1713 6, /* 2 opcode/prefix + 4 displacement */
1715 ((unsigned char) *p == JUMP_PC_RELATIVE
1716 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1717 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1718 i.disps[0]->X_add_symbol,
1722 else if (t->opcode_modifier & (JumpByte | JumpDword))
1724 int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
1725 unsigned long n = i.disps[0]->X_add_number;
1728 /* The jcx/jecx instruction might need a data size prefix. */
1729 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1731 if (*q == WORD_PREFIX_OPCODE)
1733 /* The jcxz/jecxz instructions are marked with Data16
1734 and Data32, which means that they may get
1735 WORD_PREFIX_OPCODE added to the list of prefixes.
1736 However, the are correctly distinguished using
1737 ADDR_PREFIX_OPCODE. Here we look for
1738 WORD_PREFIX_OPCODE, and actually emit
1739 ADDR_PREFIX_OPCODE. This is a hack, but, then, so
1740 is the instruction itself.
1742 If an explicit suffix is used for the loop
1743 instruction, that actually controls whether we use
1744 cx vs. ecx. This is also controlled by
1747 I don't know if there is any valid case in which we
1748 want to emit WORD_PREFIX_OPCODE, but I am keeping
1749 the old behaviour for safety. */
1751 if (IS_JUMP_ON_CX_ZERO (t->base_opcode)
1752 || IS_LOOP_ECX_TIMES (t->base_opcode))
1753 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
1755 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1761 if ((size == 4) && (flag_16bit_code))
1763 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1767 if (fits_in_unsigned_byte (t->base_opcode))
1769 FRAG_APPEND_1_CHAR (t->base_opcode);
1774 p = frag_more (2); /* opcode can be at most two bytes */
1776 /* put out high byte first: can't use md_number_to_chars! */
1777 *p++ = (t->base_opcode >> 8) & 0xff;
1778 *p = t->base_opcode & 0xff;
1781 p = frag_more (size);
1783 if (i.disps[0]->X_op == O_constant)
1785 md_number_to_chars (p, (valueT) n, size);
1786 if (size == 1 && !fits_in_signed_byte (n))
1788 as_bad ("loop/jecx only takes byte displacement; %lu shortened to %d",
1794 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1795 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1799 else if (t->opcode_modifier & JumpInterSegment)
1801 if (flag_16bit_code)
1803 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1807 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1808 insn_size += 1 + 2 + 4;
1809 p[0] = t->base_opcode;
1810 if (i.imms[1]->X_op == O_constant)
1811 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1813 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1814 i.imms[1], 0, BFD_RELOC_32);
1815 if (i.imms[0]->X_op != O_constant)
1816 as_bad ("can't handle non absolute segment in long call/jmp");
1817 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1821 /* Output normal instructions here. */
1824 /* First the prefix bytes. */
1825 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1829 md_number_to_chars (p, (valueT) *q, 1);
1832 /* Now the opcode; be careful about word order here! */
1833 if (fits_in_unsigned_byte (t->base_opcode))
1835 FRAG_APPEND_1_CHAR (t->base_opcode);
1838 else if (fits_in_unsigned_word (t->base_opcode))
1842 /* put out high byte first: can't use md_number_to_chars! */
1843 *p++ = (t->base_opcode >> 8) & 0xff;
1844 *p = t->base_opcode & 0xff;
1847 { /* opcode is either 3 or 4 bytes */
1848 if (t->base_opcode & 0xff000000)
1852 *p++ = (t->base_opcode >> 24) & 0xff;
1859 *p++ = (t->base_opcode >> 16) & 0xff;
1860 *p++ = (t->base_opcode >> 8) & 0xff;
1861 *p = (t->base_opcode) & 0xff;
1864 /* Now the modrm byte and base index byte (if present). */
1865 if (t->opcode_modifier & Modrm)
1869 /* md_number_to_chars (p, i.rm, 1); */
1870 md_number_to_chars (p,
1871 (valueT) (i.rm.regmem << 0
1875 /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode)
1876 ==> need second modrm byte. */
1877 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3)
1881 /* md_number_to_chars (p, i.bi, 1); */
1882 md_number_to_chars (p, (valueT) (i.bi.base << 0
1889 if (i.disp_operands)
1891 register unsigned int n;
1893 for (n = 0; n < i.operands; n++)
1897 if (i.disps[n]->X_op == O_constant)
1899 if (i.types[n] & (Disp8 | Abs8))
1903 md_number_to_chars (p,
1904 (valueT) i.disps[n]->X_add_number,
1907 else if (i.types[n] & (Disp16 | Abs16))
1911 md_number_to_chars (p,
1912 (valueT) i.disps[n]->X_add_number,
1916 { /* Disp32|Abs32 */
1919 md_number_to_chars (p,
1920 (valueT) i.disps[n]->X_add_number,
1925 { /* not absolute_section */
1926 /* need a 32-bit fixup (don't support 8bit non-absolute disps) */
1929 fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
1931 TC_RELOC(i.disp_reloc[n], BFD_RELOC_32));
1935 } /* end displacement output */
1937 /* output immediate */
1940 register unsigned int n;
1942 for (n = 0; n < i.operands; n++)
1946 if (i.imms[n]->X_op == O_constant)
1948 if (i.types[n] & (Imm8 | Imm8S))
1952 md_number_to_chars (p,
1953 (valueT) i.imms[n]->X_add_number,
1956 else if (i.types[n] & Imm16)
1960 md_number_to_chars (p,
1961 (valueT) i.imms[n]->X_add_number,
1968 md_number_to_chars (p,
1969 (valueT) i.imms[n]->X_add_number,
1974 { /* not absolute_section */
1975 /* Need a 32-bit fixup (don't support 8bit
1976 non-absolute ims). Try to support other
1982 if (i.types[n] & (Imm8 | Imm8S))
1984 else if (i.types[n] & Imm16)
1988 r_type = reloc (size, 0, i.disp_reloc[0]);
1989 p = frag_more (size);
1991 #ifdef BFD_ASSEMBLER
1992 if (r_type == BFD_RELOC_32
1994 && GOT_symbol == i.imms[n]->X_add_symbol
1995 && (i.imms[n]->X_op == O_symbol
1996 || (i.imms[n]->X_op == O_add
1997 && (i.imms[n]->X_op_symbol->sy_value.X_op
2000 r_type = BFD_RELOC_386_GOTPC;
2001 i.imms[n]->X_add_number += 3;
2004 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2005 i.imms[n], pcrel, r_type);
2009 } /* end immediate output */
2017 #endif /* DEBUG386 */
2021 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
2025 i386_operand (operand_string)
2026 char *operand_string;
2028 register char *op_string = operand_string;
2030 /* Address of '\0' at end of operand_string. */
2031 char *end_of_operand_string = operand_string + strlen (operand_string);
2033 /* Start and end of displacement string expression (if found). */
2034 char *displacement_string_start = NULL;
2035 char *displacement_string_end = NULL;
2037 /* We check for an absolute prefix (differentiating,
2038 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
2039 if (*op_string == ABSOLUTE_PREFIX)
2042 i.types[this_operand] |= JumpAbsolute;
2045 /* Check if operand is a register. */
2046 if (*op_string == REGISTER_PREFIX)
2048 register reg_entry *r;
2049 if (!(r = parse_register (op_string)))
2051 as_bad ("bad register name ('%s')", op_string);
2054 /* Check for segment override, rather than segment register by
2055 searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */
2056 if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':')
2061 i.seg = (seg_entry *) & es;
2064 i.seg = (seg_entry *) & cs;
2067 i.seg = (seg_entry *) & ss;
2070 i.seg = (seg_entry *) & ds;
2073 i.seg = (seg_entry *) & fs;
2076 i.seg = (seg_entry *) & gs;
2079 op_string += 4; /* skip % <x> s : */
2080 operand_string = op_string; /* Pretend given string starts here. */
2081 if (!is_digit_char (*op_string) && !is_identifier_char (*op_string)
2082 && *op_string != '(' && *op_string != ABSOLUTE_PREFIX)
2084 as_bad ("bad memory operand after segment override");
2087 /* Handle case of %es:*foo. */
2088 if (*op_string == ABSOLUTE_PREFIX)
2091 i.types[this_operand] |= JumpAbsolute;
2093 goto do_memory_reference;
2095 i.types[this_operand] |= r->reg_type;
2096 i.regs[this_operand] = r;
2099 else if (*op_string == IMMEDIATE_PREFIX)
2100 { /* ... or an immediate */
2101 char *save_input_line_pointer;
2105 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2107 as_bad ("only 1 or 2 immediate operands are allowed");
2111 exp = &im_expressions[i.imm_operands++];
2112 i.imms[this_operand] = exp;
2113 save_input_line_pointer = input_line_pointer;
2114 input_line_pointer = ++op_string; /* must advance op_string! */
2116 exp_seg = expression (exp);
2117 if (*input_line_pointer != '\0')
2119 /* This should be as_bad, but some versions of gcc, up to
2120 about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx)
2121 in certain cases. Oddly, the code in question turns out
2122 to work correctly anyhow, so we make this just a warning
2123 until those versions of gcc are obsolete. */
2124 as_warn ("warning: unrecognized characters `%s' in expression",
2125 input_line_pointer);
2127 input_line_pointer = save_input_line_pointer;
2129 if (exp->X_op == O_absent)
2131 /* missing or bad expr becomes absolute 0 */
2132 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2134 exp->X_op = O_constant;
2135 exp->X_add_number = 0;
2136 exp->X_add_symbol = (symbolS *) 0;
2137 exp->X_op_symbol = (symbolS *) 0;
2138 i.types[this_operand] |= Imm;
2140 else if (exp->X_op == O_constant)
2142 i.types[this_operand] |=
2143 smallest_imm_type ((unsigned long) exp->X_add_number);
2146 else if (exp_seg != text_section
2147 && exp_seg != data_section
2148 && exp_seg != bss_section
2149 && exp_seg != undefined_section
2150 #ifdef BFD_ASSEMBLER
2151 && ! bfd_is_com_section (exp_seg)
2156 as_bad ("Unimplemented segment type %d in parse_operand", exp_seg);
2162 /* this is an address ==> 32bit */
2163 i.types[this_operand] |= Imm32;
2165 /* shorten this type of this operand if the instruction wants
2166 * fewer bits than are present in the immediate. The bit field
2167 * code can put out 'andb $0xffffff, %al', for example. pace
2168 * also 'movw $foo,(%eax)'
2172 case WORD_OPCODE_SUFFIX:
2173 i.types[this_operand] |= Imm16;
2175 case BYTE_OPCODE_SUFFIX:
2176 i.types[this_operand] |= Imm16 | Imm8 | Imm8S;
2180 else if (is_digit_char (*op_string) || is_identifier_char (*op_string)
2181 || *op_string == '(')
2183 /* This is a memory reference of some sort. */
2184 register char *base_string;
2185 unsigned int found_base_index_form;
2187 do_memory_reference:
2188 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2190 as_bad ("more than 1 memory reference in instruction");
2195 /* Determine type of memory operand from opcode_suffix;
2196 no opcode suffix implies general memory references. */
2199 case BYTE_OPCODE_SUFFIX:
2200 i.types[this_operand] |= Mem8;
2202 case WORD_OPCODE_SUFFIX:
2203 i.types[this_operand] |= Mem16;
2205 case DWORD_OPCODE_SUFFIX:
2207 i.types[this_operand] |= Mem32;
2210 /* Check for base index form. We detect the base index form by
2211 looking for an ')' at the end of the operand, searching
2212 for the '(' matching it, and finding a REGISTER_PREFIX or ','
2214 base_string = end_of_operand_string - 1;
2215 found_base_index_form = 0;
2216 if (*base_string == ')')
2218 unsigned int parens_balanced = 1;
2219 /* We've already checked that the number of left & right ()'s are
2220 equal, so this loop will not be infinite. */
2224 if (*base_string == ')')
2226 if (*base_string == '(')
2229 while (parens_balanced);
2230 base_string++; /* Skip past '('. */
2231 if (*base_string == REGISTER_PREFIX || *base_string == ',')
2232 found_base_index_form = 1;
2235 /* If we can't parse a base index register expression, we've found
2236 a pure displacement expression. We set up displacement_string_start
2237 and displacement_string_end for the code below. */
2238 if (!found_base_index_form)
2240 displacement_string_start = op_string;
2241 displacement_string_end = end_of_operand_string;
2245 char *base_reg_name, *index_reg_name, *num_string;
2248 i.types[this_operand] |= BaseIndex;
2250 /* If there is a displacement set-up for it to be parsed later. */
2251 if (base_string != op_string + 1)
2253 displacement_string_start = op_string;
2254 displacement_string_end = base_string - 1;
2257 /* Find base register (if any). */
2258 if (*base_string != ',')
2260 base_reg_name = base_string++;
2261 /* skip past register name & parse it */
2262 while (isalpha (*base_string))
2264 if (base_string == base_reg_name + 1)
2266 as_bad ("can't find base register name after '(%c'",
2270 END_STRING_AND_SAVE (base_string);
2271 if (!(i.base_reg = parse_register (base_reg_name)))
2273 as_bad ("bad base register name ('%s')", base_reg_name);
2276 RESTORE_END_STRING (base_string);
2279 /* Now check seperator; must be ',' ==> index reg
2280 OR num ==> no index reg. just scale factor
2281 OR ')' ==> end. (scale factor = 1) */
2282 if (*base_string != ',' && *base_string != ')')
2284 as_bad ("expecting ',' or ')' after base register in `%s'",
2289 /* There may index reg here; and there may be a scale factor. */
2290 if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX)
2292 index_reg_name = ++base_string;
2293 while (isalpha (*++base_string));
2294 END_STRING_AND_SAVE (base_string);
2295 if (!(i.index_reg = parse_register (index_reg_name)))
2297 as_bad ("bad index register name ('%s')", index_reg_name);
2300 RESTORE_END_STRING (base_string);
2303 /* Check for scale factor. */
2304 if (*base_string == ',' && isdigit (*(base_string + 1)))
2306 num_string = ++base_string;
2307 while (is_digit_char (*base_string))
2309 if (base_string == num_string)
2311 as_bad ("can't find a scale factor after ','");
2314 END_STRING_AND_SAVE (base_string);
2315 /* We've got a scale factor. */
2316 if (!sscanf (num_string, "%d", &num))
2318 as_bad ("can't parse scale factor from '%s'", num_string);
2321 RESTORE_END_STRING (base_string);
2323 { /* must be 1 digit scale */
2325 i.log2_scale_factor = 0;
2328 i.log2_scale_factor = 1;
2331 i.log2_scale_factor = 2;
2334 i.log2_scale_factor = 3;
2337 as_bad ("expecting scale factor of 1, 2, 4, 8; got %d", num);
2343 if (!i.index_reg && *base_string == ',')
2345 as_bad ("expecting index register or scale factor after ','; got '%c'",
2346 *(base_string + 1));
2352 /* If there's an expression begining the operand, parse it,
2353 assuming displacement_string_start and displacement_string_end
2355 if (displacement_string_start)
2357 register expressionS *exp;
2359 char *save_input_line_pointer;
2360 exp = &disp_expressions[i.disp_operands];
2361 i.disps[this_operand] = exp;
2362 i.disp_reloc[this_operand] = NO_RELOC;
2364 save_input_line_pointer = input_line_pointer;
2365 input_line_pointer = displacement_string_start;
2366 END_STRING_AND_SAVE (displacement_string_end);
2371 * We can have operands of the form
2372 * <symbol>@GOTOFF+<nnn>
2373 * Take the easy way out here and copy everything
2374 * into a temporary buffer...
2378 cp = strchr (input_line_pointer, '@');
2383 if (GOT_symbol == NULL)
2384 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2386 tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20);
2388 if (strncmp (cp + 1, "PLT", 3) == 0)
2390 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2392 strcpy (tmpbuf, input_line_pointer);
2393 strcat (tmpbuf, cp + 1 + 3);
2396 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2398 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2400 strcpy (tmpbuf, input_line_pointer);
2401 strcat (tmpbuf, cp + 1 + 6);
2404 else if (strncmp (cp + 1, "GOT", 3) == 0)
2406 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2408 strcpy (tmpbuf, input_line_pointer);
2409 strcat (tmpbuf, cp + 1 + 3);
2413 as_bad ("Bad reloc specifier '%s' in expression", cp + 1);
2415 input_line_pointer = tmpbuf;
2420 exp_seg = expression (exp);
2422 #ifdef BFD_ASSEMBLER
2423 /* We do this to make sure that the section symbol is in
2424 the symbol table. We will ultimately change the relocation
2425 to be relative to the beginning of the section */
2426 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2428 if (S_IS_LOCAL(exp->X_add_symbol)
2429 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2430 section_symbol(exp->X_add_symbol->bsym->section);
2431 assert (exp->X_op == O_symbol);
2432 exp->X_op = O_subtract;
2433 exp->X_op_symbol = GOT_symbol;
2434 i.disp_reloc[this_operand] = BFD_RELOC_32;
2438 if (*input_line_pointer)
2439 as_bad ("Ignoring junk '%s' after expression", input_line_pointer);
2440 RESTORE_END_STRING (displacement_string_end);
2441 input_line_pointer = save_input_line_pointer;
2442 if (exp->X_op == O_absent)
2444 /* missing expr becomes absolute 0 */
2445 as_bad ("missing or invalid displacement '%s' taken as 0",
2447 i.types[this_operand] |= (Disp | Abs);
2448 exp->X_op = O_constant;
2449 exp->X_add_number = 0;
2450 exp->X_add_symbol = (symbolS *) 0;
2451 exp->X_op_symbol = (symbolS *) 0;
2453 else if (exp->X_op == O_constant)
2455 i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number);
2457 else if (exp_seg == text_section
2458 || exp_seg == data_section
2459 || exp_seg == bss_section
2460 || exp_seg == undefined_section)
2462 i.types[this_operand] |= Disp32;
2467 i.types[this_operand] |= Disp32;
2469 goto seg_unimplemented;
2474 /* Make sure the memory operand we've been dealt is valid. */
2475 if (i.base_reg && i.index_reg &&
2476 !(i.base_reg->reg_type & i.index_reg->reg_type & Reg))
2478 as_bad ("register size mismatch in (base,index,scale) expression");
2482 * special case for (%dx) while doing input/output op
2485 (i.base_reg->reg_type == (Reg16 | InOutPortReg)) &&
2486 (i.index_reg == 0)))
2488 i.types[this_operand] |= InOutPortReg;
2491 if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) ||
2492 (i.index_reg && (i.index_reg->reg_type & Reg32) == 0))
2494 as_bad ("base/index register must be 32 bit register");
2497 if (i.index_reg && i.index_reg == esp)
2499 as_bad ("%s may not be used as an index register", esp->reg_name);
2504 { /* it's not a memory operand; argh! */
2505 as_bad ("invalid char %s begining %s operand '%s'",
2506 output_invalid (*op_string), ordinal_names[this_operand],
2510 return 1; /* normal return */
2514 * md_estimate_size_before_relax()
2516 * Called just before relax().
2517 * Any symbol that is now undefined will not become defined.
2518 * Return the correct fr_subtype in the frag.
2519 * Return the initial "guess for fr_var" to caller.
2520 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
2521 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
2522 * Although it may not be explicit in the frag, pretend fr_var starts with a
2526 md_estimate_size_before_relax (fragP, segment)
2527 register fragS *fragP;
2528 register segT segment;
2530 register unsigned char *opcode;
2531 register int old_fr_fix;
2533 old_fr_fix = fragP->fr_fix;
2534 opcode = (unsigned char *) fragP->fr_opcode;
2535 /* We've already got fragP->fr_subtype right; all we have to do is check
2536 for un-relaxable symbols. */
2537 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
2539 /* symbol is undefined in this segment */
2542 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
2543 opcode[0] = 0xe9; /* dword disp jmp */
2545 fix_new (fragP, old_fr_fix, 4,
2547 fragP->fr_offset, 1,
2548 (GOT_symbol && /* Not quite right - we should switch on
2549 presence of @PLT, but I cannot see how
2550 to get to that from here. We should have
2551 done this in md_assemble to really
2552 get it right all of the time, but I
2553 think it does not matter that much, as
2554 this will be right most of the time. ERY*/
2555 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2556 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2560 /* This changes the byte-displacement jump 0x7N -->
2561 the dword-displacement jump 0x0f8N */
2562 opcode[1] = opcode[0] + 0x10;
2563 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */
2564 fragP->fr_fix += 1 + 4; /* we've added an opcode byte */
2565 fix_new (fragP, old_fr_fix + 1, 4,
2567 fragP->fr_offset, 1,
2568 (GOT_symbol && /* Not quite right - we should switch on
2569 presence of @PLT, but I cannot see how
2570 to get to that from here. ERY */
2571 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2572 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2577 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
2578 } /* md_estimate_size_before_relax() */
2581 * md_convert_frag();
2583 * Called after relax() is finished.
2584 * In: Address of frag.
2585 * fr_type == rs_machine_dependent.
2586 * fr_subtype is what the address relaxed to.
2588 * Out: Any fixSs and constants are set up.
2589 * Caller will turn frag into a ".space 0".
2591 #ifndef BFD_ASSEMBLER
2593 md_convert_frag (headers, sec, fragP)
2594 object_headers *headers;
2596 register fragS *fragP;
2599 md_convert_frag (abfd, sec, fragP)
2602 register fragS *fragP;
2605 register unsigned char *opcode;
2606 unsigned char *where_to_put_displacement = NULL;
2607 unsigned int target_address;
2608 unsigned int opcode_address;
2609 unsigned int extension = 0;
2610 int displacement_from_opcode_start;
2612 opcode = (unsigned char *) fragP->fr_opcode;
2614 /* Address we want to reach in file space. */
2615 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
2616 #ifdef BFD_ASSEMBLER /* not needed otherwise? */
2617 target_address += fragP->fr_symbol->sy_frag->fr_address;
2620 /* Address opcode resides at in file space. */
2621 opcode_address = fragP->fr_address + fragP->fr_fix;
2623 /* Displacement from opcode start to fill into instruction. */
2624 displacement_from_opcode_start = target_address - opcode_address;
2626 switch (fragP->fr_subtype)
2628 case ENCODE_RELAX_STATE (COND_JUMP, BYTE):
2629 case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE):
2630 /* don't have to change opcode */
2631 extension = 1; /* 1 opcode + 1 displacement */
2632 where_to_put_displacement = &opcode[1];
2635 case ENCODE_RELAX_STATE (COND_JUMP, WORD):
2636 opcode[1] = TWO_BYTE_OPCODE_ESCAPE;
2637 opcode[2] = opcode[0] + 0x10;
2638 opcode[0] = WORD_PREFIX_OPCODE;
2639 extension = 4; /* 3 opcode + 2 displacement */
2640 where_to_put_displacement = &opcode[3];
2643 case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD):
2645 opcode[0] = WORD_PREFIX_OPCODE;
2646 extension = 3; /* 2 opcode + 2 displacement */
2647 where_to_put_displacement = &opcode[2];
2650 case ENCODE_RELAX_STATE (COND_JUMP, DWORD):
2651 opcode[1] = opcode[0] + 0x10;
2652 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
2653 extension = 5; /* 2 opcode + 4 displacement */
2654 where_to_put_displacement = &opcode[2];
2657 case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD):
2659 extension = 4; /* 1 opcode + 4 displacement */
2660 where_to_put_displacement = &opcode[1];
2664 BAD_CASE (fragP->fr_subtype);
2667 /* now put displacement after opcode */
2668 md_number_to_chars ((char *) where_to_put_displacement,
2669 (valueT) (displacement_from_opcode_start - extension),
2670 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
2671 fragP->fr_fix += extension;
2675 int md_short_jump_size = 2; /* size of byte displacement jmp */
2676 int md_long_jump_size = 5; /* size of dword displacement jmp */
2677 const int md_reloc_size = 8; /* Size of relocation record */
2680 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
2682 addressT from_addr, to_addr;
2688 offset = to_addr - (from_addr + 2);
2689 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
2690 md_number_to_chars (ptr + 1, (valueT) offset, 1);
2694 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
2696 addressT from_addr, to_addr;
2702 if (flag_do_long_jump)
2704 offset = to_addr - S_GET_VALUE (to_symbol);
2705 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
2706 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2707 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
2708 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
2712 offset = to_addr - (from_addr + 5);
2713 md_number_to_chars (ptr, (valueT) 0xe9, 1);
2714 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2718 /* Apply a fixup (fixS) to segment data, once it has been determined
2719 by our caller that we have all the info we need to fix it up.
2721 On the 386, immediates, displacements, and data pointers are all in
2722 the same (little-endian) format, so we don't need to care about which
2726 md_apply_fix3 (fixP, valp, seg)
2727 fixS *fixP; /* The fix we're to put in. */
2728 valueT *valp; /* Pointer to the value of the bits. */
2729 segT seg; /* Segment fix is from. */
2731 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2732 valueT value = *valp;
2734 if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel)
2735 fixP->fx_r_type = BFD_RELOC_32_PCREL;
2737 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2739 * This is a hack. There should be a better way to
2742 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2745 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2746 || OUTPUT_FLAVOR == bfd_target_coff_flavour)
2747 value += fixP->fx_where + fixP->fx_frag->fr_address;
2749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2750 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2751 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2752 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2754 /* Yes, we add the values in twice. This is because
2755 bfd_perform_relocation subtracts them out again. I think
2756 bfd_perform_relocation is broken, but I don't dare change
2758 value += fixP->fx_where + fixP->fx_frag->fr_address;
2761 #if defined (OBJ_COFF) && defined (TE_PE)
2762 /* For some reason, the PE format does not store a section
2763 address offset for a PC relative symbol. */
2764 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
2765 value += md_pcrel_from (fixP);
2769 /* Fix a few things - the dynamic linker expects certain values here,
2770 and we must not dissappoint it. */
2771 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2772 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2774 switch(fixP->fx_r_type) {
2775 case BFD_RELOC_386_PLT32:
2776 /* Make the jump instruction point to the address of the operand. At
2777 runtime we merely add the offset to the actual PLT entry. */
2780 case BFD_RELOC_386_GOTPC:
2782 * This is tough to explain. We end up with this one if we have
2783 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
2784 * here is to obtain the absolute address of the GOT, and it is strongly
2785 * preferable from a performance point of view to avoid using a runtime
2786 * relocation for this. The actual sequence of instructions often look
2792 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
2794 * The call and pop essentially return the absolute address of
2795 * the label .L66 and store it in %ebx. The linker itself will
2796 * ultimately change the first operand of the addl so that %ebx points to
2797 * the GOT, but to keep things simple, the .o file must have this operand
2798 * set so that it generates not the absolute address of .L66, but the
2799 * absolute address of itself. This allows the linker itself simply
2800 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
2801 * added in, and the addend of the relocation is stored in the operand
2802 * field for the instruction itself.
2804 * Our job here is to fix the operand so that it would add the correct
2805 * offset so that %ebx would point to itself. The thing that is tricky is
2806 * that .-.L66 will point to the beginning of the instruction, so we need
2807 * to further modify the operand so that it will point to itself.
2808 * There are other cases where you have something like:
2810 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
2812 * and here no correction would be required. Internally in the assembler
2813 * we treat operands of this form as not being pcrel since the '.' is
2814 * explicitly mentioned, and I wonder whether it would simplify matters
2815 * to do it this way. Who knows. In earlier versions of the PIC patches,
2816 * the pcrel_adjust field was used to store the correction, but since the
2817 * expression is not pcrel, I felt it would be confusing to do it this way.
2821 case BFD_RELOC_386_GOT32:
2822 value = 0; /* Fully resolved at runtime. No addend. */
2824 case BFD_RELOC_386_GOTOFF:
2833 md_number_to_chars (p, value, fixP->fx_size);
2839 /* This is never used. */
2840 long /* Knows about the byte order in a word. */
2841 md_chars_to_number (con, nbytes)
2842 unsigned char con[]; /* Low order byte 1st. */
2843 int nbytes; /* Number of bytes in the input. */
2846 for (retval = 0, con += nbytes - 1; nbytes--; con--)
2848 retval <<= BITS_PER_CHAR;
2856 #define MAX_LITTLENUMS 6
2858 /* Turn the string pointed to by litP into a floating point constant of type
2859 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
2860 is stored in *sizeP . An error message is returned, or NULL on OK. */
2862 md_atof (type, litP, sizeP)
2868 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2869 LITTLENUM_TYPE *wordP;
2891 return "Bad call to md_atof ()";
2893 t = atof_ieee (input_line_pointer, type, words);
2895 input_line_pointer = t;
2897 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2898 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
2899 the bigendian 386. */
2900 for (wordP = words + prec - 1; prec--;)
2902 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
2903 litP += sizeof (LITTLENUM_TYPE);
2908 char output_invalid_buf[8];
2915 sprintf (output_invalid_buf, "'%c'", c);
2917 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
2918 return output_invalid_buf;
2921 /* reg_string starts *before* REGISTER_PREFIX */
2923 parse_register (reg_string)
2926 register char *s = reg_string;
2928 char reg_name_given[MAX_REG_NAME_SIZE];
2930 s++; /* skip REGISTER_PREFIX */
2931 for (p = reg_name_given; is_register_char (*s); p++, s++)
2933 *p = register_chars[(unsigned char) *s];
2934 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
2935 return (reg_entry *) 0;
2938 return (reg_entry *) hash_find (reg_hash, reg_name_given);
2942 CONST char *md_shortopts = "kmVQ:";
2944 CONST char *md_shortopts = "m";
2946 struct option md_longopts[] = {
2947 {NULL, no_argument, NULL, 0}
2949 size_t md_longopts_size = sizeof(md_longopts);
2952 md_parse_option (c, arg)
2959 flag_do_long_jump = 1;
2962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2963 /* -k: Ignore for FreeBSD compatibility. */
2967 /* -V: SVR4 argument to print version ID. */
2969 print_version_id ();
2972 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
2973 should be emitted or not. FIXME: Not implemented. */
2985 md_show_usage (stream)
2989 -m do long jump\n");
2992 #ifdef BFD_ASSEMBLER
2993 #ifdef OBJ_MAYBE_ELF
2994 #ifdef OBJ_MAYBE_COFF
2996 /* Pick the target format to use. */
2999 i386_target_format ()
3001 switch (OUTPUT_FLAVOR)
3003 case bfd_target_coff_flavour:
3005 case bfd_target_elf_flavour:
3006 return "elf32-i386";
3013 #endif /* OBJ_MAYBE_COFF */
3014 #endif /* OBJ_MAYBE_ELF */
3015 #endif /* BFD_ASSEMBLER */
3019 md_undefined_symbol (name)
3022 if (*name == '_' && *(name+1) == 'G'
3023 && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0)
3027 if(symbol_find(name))
3028 as_bad("GOT already in symbol table");
3029 GOT_symbol = symbol_new (name, undefined_section,
3030 (valueT) 0, &zero_address_frag);
3037 /* Round up a section size to the appropriate boundary. */
3039 md_section_align (segment, size)
3044 #ifdef BFD_ASSEMBLER
3045 /* For a.out, force the section size to be aligned. If we don't do
3046 this, BFD will align it for us, but it will not write out the
3047 final bytes of the section. This may be a bug in BFD, but it is
3048 easier to fix it here since that is how the other a.out targets
3052 align = bfd_get_section_alignment (stdoutput, segment);
3053 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
3060 /* Exactly what point is a PC-relative offset relative TO? On the
3061 i386, they're relative to the address of the offset, plus its
3062 size. (??? Is this right? FIXME-SOON!) */
3064 md_pcrel_from (fixP)
3067 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3078 temp = get_absolute_expression ();
3079 subseg_set (bss_section, (subsegT) temp);
3080 demand_empty_rest_of_line ();
3086 #ifdef BFD_ASSEMBLER
3089 i386_validate_fix (fixp)
3092 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
3094 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
3099 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
3100 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
3103 tc_gen_reloc (section, fixp)
3108 bfd_reloc_code_real_type code;
3110 switch(fixp->fx_r_type)
3112 case BFD_RELOC_386_PLT32:
3113 case BFD_RELOC_386_GOT32:
3114 case BFD_RELOC_386_GOTOFF:
3115 case BFD_RELOC_386_GOTPC:
3117 code = fixp->fx_r_type;
3120 switch (F (fixp->fx_size, fixp->fx_pcrel))
3122 MAP (1, 0, BFD_RELOC_8);
3123 MAP (2, 0, BFD_RELOC_16);
3124 MAP (4, 0, BFD_RELOC_32);
3125 MAP (1, 1, BFD_RELOC_8_PCREL);
3126 MAP (2, 1, BFD_RELOC_16_PCREL);
3127 MAP (4, 1, BFD_RELOC_32_PCREL);
3129 as_bad ("Can not do %d byte %srelocation", fixp->fx_size,
3130 fixp->fx_pcrel ? "pc-relative " : "");
3136 if (code == BFD_RELOC_32
3138 && fixp->fx_addsy == GOT_symbol)
3139 code = BFD_RELOC_386_GOTPC;
3141 rel = (arelent *) xmalloc (sizeof (arelent));
3142 rel->sym_ptr_ptr = &fixp->fx_addsy->bsym;
3143 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3145 rel->addend = fixp->fx_addnumber;
3149 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
3150 if (rel->howto == NULL)
3152 as_bad_where (fixp->fx_file, fixp->fx_line,
3153 "Cannot represent relocation type %s",
3154 bfd_get_reloc_code_name (code));
3155 /* Set howto to a garbage value so that we can keep going. */
3156 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
3157 assert (rel->howto != NULL);
3163 #else /* ! BFD_ASSEMBLER */
3165 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
3167 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3170 relax_addressT segment_address_in_file;
3173 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3174 * Out: GNU LD relocation length code: 0, 1, or 2.
3177 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3180 know (fixP->fx_addsy != NULL);
3182 md_number_to_chars (where,
3183 (valueT) (fixP->fx_frag->fr_address
3184 + fixP->fx_where - segment_address_in_file),
3187 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3188 ? S_GET_TYPE (fixP->fx_addsy)
3189 : fixP->fx_addsy->sy_number);
3191 where[6] = (r_symbolnum >> 16) & 0x0ff;
3192 where[5] = (r_symbolnum >> 8) & 0x0ff;
3193 where[4] = r_symbolnum & 0x0ff;
3194 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
3195 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
3196 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
3199 #endif /* OBJ_AOUT or OBJ_BOUT */
3201 #if defined (I386COFF)
3204 tc_coff_fix2rtype (fixP)
3207 if (fixP->fx_r_type == R_IMAGEBASE)
3210 return (fixP->fx_pcrel ?
3211 (fixP->fx_size == 1 ? R_PCRBYTE :
3212 fixP->fx_size == 2 ? R_PCRWORD :
3214 (fixP->fx_size == 1 ? R_RELBYTE :
3215 fixP->fx_size == 2 ? R_RELWORD :
3220 tc_coff_sizemachdep (frag)
3224 return (frag->fr_next->fr_address - frag->fr_address);
3229 #endif /* I386COFF */
3231 #endif /* BFD_ASSEMBLER? */
3233 /* end of tc-i386.c */