1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg = 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg = 0;
422 /* Register prefix used for error message. */
423 static const char *register_prefix = "%";
425 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
426 leave, push, and pop instructions so that gcc has the same stack
427 frame as in 32 bit mode. */
428 static char stackop_size = '\0';
430 /* Non-zero to optimize code alignment. */
431 int optimize_align_code = 1;
433 /* Non-zero to quieten some warnings. */
434 static int quiet_warnings = 0;
437 static const char *cpu_arch_name = NULL;
438 static char *cpu_sub_arch_name = NULL;
440 /* CPU feature flags. */
441 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
443 /* If we have selected a cpu we are generating instructions for. */
444 static int cpu_arch_tune_set = 0;
446 /* Cpu we are generating instructions for. */
447 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
449 /* CPU feature flags of cpu we are generating instructions for. */
450 static i386_cpu_flags cpu_arch_tune_flags;
452 /* CPU instruction set architecture used. */
453 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
455 /* CPU feature flags of instruction set architecture used. */
456 static i386_cpu_flags cpu_arch_isa_flags;
458 /* If set, conditional jumps are not automatically promoted to handle
459 larger than a byte offset. */
460 static unsigned int no_cond_jump_promotion = 0;
462 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
463 static symbolS *GOT_symbol;
465 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
466 unsigned int x86_dwarf2_return_column;
468 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
469 int x86_cie_data_alignment;
471 /* Interface to relax_segment.
472 There are 3 major relax states for 386 jump insns because the
473 different types of jumps add different sizes to frags when we're
474 figuring out what sort of jump to choose to reach a given label. */
477 #define UNCOND_JUMP 0
479 #define COND_JUMP86 2
484 #define SMALL16 (SMALL | CODE16)
486 #define BIG16 (BIG | CODE16)
490 #define INLINE __inline__
496 #define ENCODE_RELAX_STATE(type, size) \
497 ((relax_substateT) (((type) << 2) | (size)))
498 #define TYPE_FROM_RELAX_STATE(s) \
500 #define DISP_SIZE_FROM_RELAX_STATE(s) \
501 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
503 /* This table is used by relax_frag to promote short jumps to long
504 ones where necessary. SMALL (short) jumps may be promoted to BIG
505 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
506 don't allow a short jump in a 32 bit code segment to be promoted to
507 a 16 bit offset jump because it's slower (requires data size
508 prefix), and doesn't work, unless the destination is in the bottom
509 64k of the code segment (The top 16 bits of eip are zeroed). */
511 const relax_typeS md_relax_table[] =
514 1) most positive reach of this state,
515 2) most negative reach of this state,
516 3) how many bytes this mode will have in the variable part of the frag
517 4) which index into the table to try if we can't fit into this one. */
519 /* UNCOND_JUMP states. */
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
521 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
522 /* dword jmp adds 4 bytes to frag:
523 0 extra opcode bytes, 4 displacement bytes. */
525 /* word jmp adds 2 byte2 to frag:
526 0 extra opcode bytes, 2 displacement bytes. */
529 /* COND_JUMP states. */
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
532 /* dword conditionals adds 5 bytes to frag:
533 1 extra opcode byte, 4 displacement bytes. */
535 /* word conditionals add 3 bytes to frag:
536 1 extra opcode byte, 2 displacement bytes. */
539 /* COND_JUMP86 states. */
540 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
542 /* dword conditionals adds 5 bytes to frag:
543 1 extra opcode byte, 4 displacement bytes. */
545 /* word conditionals add 4 bytes to frag:
546 1 displacement byte and a 3 byte long branch insn. */
550 static const arch_entry cpu_arch[] =
552 { "generic32", PROCESSOR_GENERIC32,
553 CPU_GENERIC32_FLAGS },
554 { "generic64", PROCESSOR_GENERIC64,
555 CPU_GENERIC64_FLAGS },
556 { "i8086", PROCESSOR_UNKNOWN,
558 { "i186", PROCESSOR_UNKNOWN,
560 { "i286", PROCESSOR_UNKNOWN,
562 { "i386", PROCESSOR_I386,
564 { "i486", PROCESSOR_I486,
566 { "i586", PROCESSOR_PENTIUM,
568 { "i686", PROCESSOR_PENTIUMPRO,
570 { "pentium", PROCESSOR_PENTIUM,
572 { "pentiumpro", PROCESSOR_PENTIUMPRO,
574 { "pentiumii", PROCESSOR_PENTIUMPRO,
576 { "pentiumiii",PROCESSOR_PENTIUMPRO,
578 { "pentium4", PROCESSOR_PENTIUM4,
580 { "prescott", PROCESSOR_NOCONA,
582 { "nocona", PROCESSOR_NOCONA,
584 { "yonah", PROCESSOR_CORE,
586 { "core", PROCESSOR_CORE,
588 { "merom", PROCESSOR_CORE2,
590 { "core2", PROCESSOR_CORE2,
592 { "k6", PROCESSOR_K6,
594 { "k6_2", PROCESSOR_K6,
596 { "athlon", PROCESSOR_ATHLON,
598 { "sledgehammer", PROCESSOR_K8,
600 { "opteron", PROCESSOR_K8,
602 { "k8", PROCESSOR_K8,
604 { "amdfam10", PROCESSOR_AMDFAM10,
605 CPU_AMDFAM10_FLAGS },
606 { ".mmx", PROCESSOR_UNKNOWN,
608 { ".sse", PROCESSOR_UNKNOWN,
610 { ".sse2", PROCESSOR_UNKNOWN,
612 { ".sse3", PROCESSOR_UNKNOWN,
614 { ".ssse3", PROCESSOR_UNKNOWN,
616 { ".sse4.1", PROCESSOR_UNKNOWN,
618 { ".sse4.2", PROCESSOR_UNKNOWN,
620 { ".sse4", PROCESSOR_UNKNOWN,
622 { ".vmx", PROCESSOR_UNKNOWN,
624 { ".smx", PROCESSOR_UNKNOWN,
626 { ".xsave", PROCESSOR_UNKNOWN,
628 { ".3dnow", PROCESSOR_UNKNOWN,
630 { ".3dnowa", PROCESSOR_UNKNOWN,
632 { ".padlock", PROCESSOR_UNKNOWN,
634 { ".pacifica", PROCESSOR_UNKNOWN,
636 { ".svme", PROCESSOR_UNKNOWN,
638 { ".sse4a", PROCESSOR_UNKNOWN,
640 { ".abm", PROCESSOR_UNKNOWN,
642 { ".sse5", PROCESSOR_UNKNOWN,
646 const pseudo_typeS md_pseudo_table[] =
648 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
649 {"align", s_align_bytes, 0},
651 {"align", s_align_ptwo, 0},
653 {"arch", set_cpu_arch, 0},
657 {"ffloat", float_cons, 'f'},
658 {"dfloat", float_cons, 'd'},
659 {"tfloat", float_cons, 'x'},
661 {"slong", signed_cons, 4},
662 {"noopt", s_ignore, 0},
663 {"optim", s_ignore, 0},
664 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
665 {"code16", set_code_flag, CODE_16BIT},
666 {"code32", set_code_flag, CODE_32BIT},
667 {"code64", set_code_flag, CODE_64BIT},
668 {"intel_syntax", set_intel_syntax, 1},
669 {"att_syntax", set_intel_syntax, 0},
670 {"intel_mnemonic", set_intel_mnemonic, 1},
671 {"att_mnemonic", set_intel_mnemonic, 0},
672 {"allow_index_reg", set_allow_index_reg, 1},
673 {"disallow_index_reg", set_allow_index_reg, 0},
674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
675 {"largecomm", handle_large_common, 0},
677 {"file", (void (*) (int)) dwarf2_directive_file, 0},
678 {"loc", dwarf2_directive_loc, 0},
679 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
682 {"secrel32", pe_directive_secrel, 0},
687 /* For interface with expression (). */
688 extern char *input_line_pointer;
690 /* Hash table for instruction mnemonic lookup. */
691 static struct hash_control *op_hash;
693 /* Hash table for register lookup. */
694 static struct hash_control *reg_hash;
697 i386_align_code (fragS *fragP, int count)
699 /* Various efficient no-op patterns for aligning code labels.
700 Note: Don't try to assemble the instructions in the comments.
701 0L and 0w are not legal. */
702 static const char f32_1[] =
704 static const char f32_2[] =
705 {0x66,0x90}; /* xchg %ax,%ax */
706 static const char f32_3[] =
707 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
708 static const char f32_4[] =
709 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
710 static const char f32_5[] =
712 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_6[] =
714 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
715 static const char f32_7[] =
716 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
717 static const char f32_8[] =
719 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_9[] =
721 {0x89,0xf6, /* movl %esi,%esi */
722 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
723 static const char f32_10[] =
724 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_11[] =
727 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_12[] =
730 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
731 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
732 static const char f32_13[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
735 static const char f32_14[] =
736 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f16_3[] =
739 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
740 static const char f16_4[] =
741 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
742 static const char f16_5[] =
744 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_6[] =
746 {0x89,0xf6, /* mov %si,%si */
747 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
748 static const char f16_7[] =
749 {0x8d,0x74,0x00, /* lea 0(%si),%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_8[] =
752 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char jump_31[] =
755 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
756 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
757 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
758 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
759 static const char *const f32_patt[] = {
760 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
761 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
763 static const char *const f16_patt[] = {
764 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
767 static const char alt_3[] =
769 /* nopl 0(%[re]ax) */
770 static const char alt_4[] =
771 {0x0f,0x1f,0x40,0x00};
772 /* nopl 0(%[re]ax,%[re]ax,1) */
773 static const char alt_5[] =
774 {0x0f,0x1f,0x44,0x00,0x00};
775 /* nopw 0(%[re]ax,%[re]ax,1) */
776 static const char alt_6[] =
777 {0x66,0x0f,0x1f,0x44,0x00,0x00};
778 /* nopl 0L(%[re]ax) */
779 static const char alt_7[] =
780 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
781 /* nopl 0L(%[re]ax,%[re]ax,1) */
782 static const char alt_8[] =
783 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
784 /* nopw 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_9[] =
786 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
788 static const char alt_10[] =
789 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
791 nopw %cs:0L(%[re]ax,%[re]ax,1) */
792 static const char alt_long_11[] =
794 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
797 nopw %cs:0L(%[re]ax,%[re]ax,1) */
798 static const char alt_long_12[] =
801 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
805 nopw %cs:0L(%[re]ax,%[re]ax,1) */
806 static const char alt_long_13[] =
810 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
815 nopw %cs:0L(%[re]ax,%[re]ax,1) */
816 static const char alt_long_14[] =
821 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
827 nopw %cs:0L(%[re]ax,%[re]ax,1) */
828 static const char alt_long_15[] =
834 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
835 /* nopl 0(%[re]ax,%[re]ax,1)
836 nopw 0(%[re]ax,%[re]ax,1) */
837 static const char alt_short_11[] =
838 {0x0f,0x1f,0x44,0x00,0x00,
839 0x66,0x0f,0x1f,0x44,0x00,0x00};
840 /* nopw 0(%[re]ax,%[re]ax,1)
841 nopw 0(%[re]ax,%[re]ax,1) */
842 static const char alt_short_12[] =
843 {0x66,0x0f,0x1f,0x44,0x00,0x00,
844 0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1)
847 static const char alt_short_13[] =
848 {0x66,0x0f,0x1f,0x44,0x00,0x00,
849 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
852 static const char alt_short_14[] =
853 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
854 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
856 nopl 0L(%[re]ax,%[re]ax,1) */
857 static const char alt_short_15[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
859 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 static const char *const alt_short_patt[] = {
861 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
862 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
863 alt_short_14, alt_short_15
865 static const char *const alt_long_patt[] = {
866 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
867 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
868 alt_long_14, alt_long_15
871 /* Only align for at least a positive non-zero boundary. */
872 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
875 /* We need to decide which NOP sequence to use for 32bit and
876 64bit. When -mtune= is used:
878 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
879 PROCESSOR_GENERIC32, f32_patt will be used.
880 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
881 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
882 alt_long_patt will be used.
883 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
884 PROCESSOR_AMDFAM10, alt_short_patt will be used.
886 When -mtune= isn't used, alt_long_patt will be used if
887 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
890 When -march= or .arch is used, we can't use anything beyond
891 cpu_arch_isa_flags. */
893 if (flag_code == CODE_16BIT)
897 memcpy (fragP->fr_literal + fragP->fr_fix,
899 /* Adjust jump offset. */
900 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
903 memcpy (fragP->fr_literal + fragP->fr_fix,
904 f16_patt[count - 1], count);
908 const char *const *patt = NULL;
910 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
912 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
913 switch (cpu_arch_tune)
915 case PROCESSOR_UNKNOWN:
916 /* We use cpu_arch_isa_flags to check if we SHOULD
917 optimize for Cpu686. */
918 if (cpu_arch_isa_flags.bitfield.cpui686)
919 patt = alt_long_patt;
923 case PROCESSOR_PENTIUMPRO:
924 case PROCESSOR_PENTIUM4:
925 case PROCESSOR_NOCONA:
927 case PROCESSOR_CORE2:
928 case PROCESSOR_GENERIC64:
929 patt = alt_long_patt;
932 case PROCESSOR_ATHLON:
934 case PROCESSOR_AMDFAM10:
935 patt = alt_short_patt;
939 case PROCESSOR_PENTIUM:
940 case PROCESSOR_GENERIC32:
947 switch (cpu_arch_tune)
949 case PROCESSOR_UNKNOWN:
950 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
951 PROCESSOR_UNKNOWN. */
957 case PROCESSOR_PENTIUM:
959 case PROCESSOR_ATHLON:
961 case PROCESSOR_AMDFAM10:
962 case PROCESSOR_GENERIC32:
963 /* We use cpu_arch_isa_flags to check if we CAN optimize
965 if (cpu_arch_isa_flags.bitfield.cpui686)
966 patt = alt_short_patt;
970 case PROCESSOR_PENTIUMPRO:
971 case PROCESSOR_PENTIUM4:
972 case PROCESSOR_NOCONA:
974 case PROCESSOR_CORE2:
975 if (cpu_arch_isa_flags.bitfield.cpui686)
976 patt = alt_long_patt;
980 case PROCESSOR_GENERIC64:
981 patt = alt_long_patt;
986 if (patt == f32_patt)
988 /* If the padding is less than 15 bytes, we use the normal
989 ones. Otherwise, we use a jump instruction and adjust
992 memcpy (fragP->fr_literal + fragP->fr_fix,
993 patt[count - 1], count);
996 memcpy (fragP->fr_literal + fragP->fr_fix,
998 /* Adjust jump offset. */
999 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1004 /* Maximum length of an instruction is 15 byte. If the
1005 padding is greater than 15 bytes and we don't use jump,
1006 we have to break it into smaller pieces. */
1007 int padding = count;
1008 while (padding > 15)
1011 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1016 memcpy (fragP->fr_literal + fragP->fr_fix,
1017 patt [padding - 1], padding);
1020 fragP->fr_var = count;
1024 uints_all_zero (const unsigned int *x, unsigned int size)
1042 uints_set (unsigned int *x, unsigned int v, unsigned int size)
1059 uints_equal (const unsigned int *x, const unsigned int *y,
1071 return x[0] == y [0];
1078 #define UINTS_ALL_ZERO(x) \
1079 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
1080 #define UINTS_SET(x, v) \
1081 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
1082 #define UINTS_CLEAR(x) \
1083 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
1084 #define UINTS_EQUAL(x, y) \
1085 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
1088 cpu_flags_check_cpu64 (i386_cpu_flags f)
1090 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1091 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1094 static INLINE i386_cpu_flags
1095 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1097 switch (ARRAY_SIZE (x.array))
1100 x.array [2] &= y.array [2];
1102 x.array [1] &= y.array [1];
1104 x.array [0] &= y.array [0];
1112 static INLINE i386_cpu_flags
1113 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1115 switch (ARRAY_SIZE (x.array))
1118 x.array [2] |= y.array [2];
1120 x.array [1] |= y.array [1];
1122 x.array [0] |= y.array [0];
1130 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1131 1 if compatible with arch, 0 if there is no match. */
1134 cpu_flags_match (i386_cpu_flags x)
1136 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1138 x.bitfield.cpu64 = 0;
1139 x.bitfield.cpuno64 = 0;
1141 if (UINTS_ALL_ZERO (x))
1145 i386_cpu_flags cpu = cpu_arch_flags;
1147 cpu.bitfield.cpu64 = 0;
1148 cpu.bitfield.cpuno64 = 0;
1149 cpu = cpu_flags_and (x, cpu);
1150 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1155 static INLINE i386_operand_type
1156 operand_type_and (i386_operand_type x, i386_operand_type y)
1158 switch (ARRAY_SIZE (x.array))
1161 x.array [2] &= y.array [2];
1163 x.array [1] &= y.array [1];
1165 x.array [0] &= y.array [0];
1173 static INLINE i386_operand_type
1174 operand_type_or (i386_operand_type x, i386_operand_type y)
1176 switch (ARRAY_SIZE (x.array))
1179 x.array [2] |= y.array [2];
1181 x.array [1] |= y.array [1];
1183 x.array [0] |= y.array [0];
1191 static INLINE i386_operand_type
1192 operand_type_xor (i386_operand_type x, i386_operand_type y)
1194 switch (ARRAY_SIZE (x.array))
1197 x.array [2] ^= y.array [2];
1199 x.array [1] ^= y.array [1];
1201 x.array [0] ^= y.array [0];
1209 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1210 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1211 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1212 static const i386_operand_type reg16_inoutportreg
1213 = OPERAND_TYPE_REG16_INOUTPORTREG;
1214 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1215 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1216 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1217 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1218 static const i386_operand_type anydisp
1219 = OPERAND_TYPE_ANYDISP;
1220 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1221 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1222 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1223 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1224 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1225 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1226 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1227 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1228 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1229 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1240 operand_type_check (i386_operand_type t, enum operand_type c)
1245 return (t.bitfield.reg8
1248 || t.bitfield.reg64);
1251 return (t.bitfield.imm8
1255 || t.bitfield.imm32s
1256 || t.bitfield.imm64);
1259 return (t.bitfield.disp8
1260 || t.bitfield.disp16
1261 || t.bitfield.disp32
1262 || t.bitfield.disp32s
1263 || t.bitfield.disp64);
1266 return (t.bitfield.disp8
1267 || t.bitfield.disp16
1268 || t.bitfield.disp32
1269 || t.bitfield.disp32s
1270 || t.bitfield.disp64
1271 || t.bitfield.baseindex);
1278 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1279 operand J for instruction template T. */
1282 match_reg_size (const template *t, unsigned int j)
1284 return !((i.types[j].bitfield.byte
1285 && !t->operand_types[j].bitfield.byte)
1286 || (i.types[j].bitfield.word
1287 && !t->operand_types[j].bitfield.word)
1288 || (i.types[j].bitfield.dword
1289 && !t->operand_types[j].bitfield.dword)
1290 || (i.types[j].bitfield.qword
1291 && !t->operand_types[j].bitfield.qword));
1294 /* Return 1 if there is no conflict in any size on operand J for
1295 instruction template T. */
1298 match_mem_size (const template *t, unsigned int j)
1300 return (match_reg_size (t, j)
1301 && !((i.types[j].bitfield.unspecified
1302 && !t->operand_types[j].bitfield.unspecified)
1303 || (i.types[j].bitfield.fword
1304 && !t->operand_types[j].bitfield.fword)
1305 || (i.types[j].bitfield.tbyte
1306 && !t->operand_types[j].bitfield.tbyte)
1307 || (i.types[j].bitfield.xmmword
1308 && !t->operand_types[j].bitfield.xmmword)));
1311 /* Return 1 if there is no size conflict on any operands for
1312 instruction template T. */
1315 operand_size_match (const template *t)
1320 /* Don't check jump instructions. */
1321 if (t->opcode_modifier.jump
1322 || t->opcode_modifier.jumpbyte
1323 || t->opcode_modifier.jumpdword
1324 || t->opcode_modifier.jumpintersegment)
1327 /* Check memory and accumulator operand size. */
1328 for (j = 0; j < i.operands; j++)
1330 if (t->operand_types[j].bitfield.anysize)
1333 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1339 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1347 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1350 /* Check reverse. */
1351 assert (i.operands == 2);
1354 for (j = 0; j < 2; j++)
1356 if (t->operand_types[j].bitfield.acc
1357 && !match_reg_size (t, j ? 0 : 1))
1363 if (i.types[j].bitfield.mem
1364 && !match_mem_size (t, j ? 0 : 1))
1375 operand_type_match (i386_operand_type overlap,
1376 i386_operand_type given)
1378 i386_operand_type temp = overlap;
1380 temp.bitfield.jumpabsolute = 0;
1381 temp.bitfield.unspecified = 0;
1382 temp.bitfield.byte = 0;
1383 temp.bitfield.word = 0;
1384 temp.bitfield.dword = 0;
1385 temp.bitfield.fword = 0;
1386 temp.bitfield.qword = 0;
1387 temp.bitfield.tbyte = 0;
1388 temp.bitfield.xmmword = 0;
1389 if (UINTS_ALL_ZERO (temp))
1392 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1393 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1396 /* If given types g0 and g1 are registers they must be of the same type
1397 unless the expected operand type register overlap is null.
1398 Note that Acc in a template matches every size of reg. */
1401 operand_type_register_match (i386_operand_type m0,
1402 i386_operand_type g0,
1403 i386_operand_type t0,
1404 i386_operand_type m1,
1405 i386_operand_type g1,
1406 i386_operand_type t1)
1408 if (!operand_type_check (g0, reg))
1411 if (!operand_type_check (g1, reg))
1414 if (g0.bitfield.reg8 == g1.bitfield.reg8
1415 && g0.bitfield.reg16 == g1.bitfield.reg16
1416 && g0.bitfield.reg32 == g1.bitfield.reg32
1417 && g0.bitfield.reg64 == g1.bitfield.reg64)
1420 if (m0.bitfield.acc)
1422 t0.bitfield.reg8 = 1;
1423 t0.bitfield.reg16 = 1;
1424 t0.bitfield.reg32 = 1;
1425 t0.bitfield.reg64 = 1;
1428 if (m1.bitfield.acc)
1430 t1.bitfield.reg8 = 1;
1431 t1.bitfield.reg16 = 1;
1432 t1.bitfield.reg32 = 1;
1433 t1.bitfield.reg64 = 1;
1436 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1437 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1438 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1439 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1442 static INLINE unsigned int
1443 mode_from_disp_size (i386_operand_type t)
1445 if (t.bitfield.disp8)
1447 else if (t.bitfield.disp16
1448 || t.bitfield.disp32
1449 || t.bitfield.disp32s)
1456 fits_in_signed_byte (offsetT num)
1458 return (num >= -128) && (num <= 127);
1462 fits_in_unsigned_byte (offsetT num)
1464 return (num & 0xff) == num;
1468 fits_in_unsigned_word (offsetT num)
1470 return (num & 0xffff) == num;
1474 fits_in_signed_word (offsetT num)
1476 return (-32768 <= num) && (num <= 32767);
1480 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1485 return (!(((offsetT) -1 << 31) & num)
1486 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1488 } /* fits_in_signed_long() */
1491 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1496 return (num & (((offsetT) 2 << 31) - 1)) == num;
1498 } /* fits_in_unsigned_long() */
1500 static i386_operand_type
1501 smallest_imm_type (offsetT num)
1503 i386_operand_type t;
1506 t.bitfield.imm64 = 1;
1508 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1510 /* This code is disabled on the 486 because all the Imm1 forms
1511 in the opcode table are slower on the i486. They're the
1512 versions with the implicitly specified single-position
1513 displacement, which has another syntax if you really want to
1515 t.bitfield.imm1 = 1;
1516 t.bitfield.imm8 = 1;
1517 t.bitfield.imm8s = 1;
1518 t.bitfield.imm16 = 1;
1519 t.bitfield.imm32 = 1;
1520 t.bitfield.imm32s = 1;
1522 else if (fits_in_signed_byte (num))
1524 t.bitfield.imm8 = 1;
1525 t.bitfield.imm8s = 1;
1526 t.bitfield.imm16 = 1;
1527 t.bitfield.imm32 = 1;
1528 t.bitfield.imm32s = 1;
1530 else if (fits_in_unsigned_byte (num))
1532 t.bitfield.imm8 = 1;
1533 t.bitfield.imm16 = 1;
1534 t.bitfield.imm32 = 1;
1535 t.bitfield.imm32s = 1;
1537 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1539 t.bitfield.imm16 = 1;
1540 t.bitfield.imm32 = 1;
1541 t.bitfield.imm32s = 1;
1543 else if (fits_in_signed_long (num))
1545 t.bitfield.imm32 = 1;
1546 t.bitfield.imm32s = 1;
1548 else if (fits_in_unsigned_long (num))
1549 t.bitfield.imm32 = 1;
1555 offset_in_range (offsetT val, int size)
1561 case 1: mask = ((addressT) 1 << 8) - 1; break;
1562 case 2: mask = ((addressT) 1 << 16) - 1; break;
1563 case 4: mask = ((addressT) 2 << 31) - 1; break;
1565 case 8: mask = ((addressT) 2 << 63) - 1; break;
1570 /* If BFD64, sign extend val. */
1571 if (!use_rela_relocations)
1572 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1573 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1575 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1577 char buf1[40], buf2[40];
1579 sprint_value (buf1, val);
1580 sprint_value (buf2, val & mask);
1581 as_warn (_("%s shortened to %s"), buf1, buf2);
1586 /* Returns 0 if attempting to add a prefix where one from the same
1587 class already exists, 1 if non rep/repne added, 2 if rep/repne
1590 add_prefix (unsigned int prefix)
1595 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1596 && flag_code == CODE_64BIT)
1598 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1599 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1600 && (prefix & (REX_R | REX_X | REX_B))))
1611 case CS_PREFIX_OPCODE:
1612 case DS_PREFIX_OPCODE:
1613 case ES_PREFIX_OPCODE:
1614 case FS_PREFIX_OPCODE:
1615 case GS_PREFIX_OPCODE:
1616 case SS_PREFIX_OPCODE:
1620 case REPNE_PREFIX_OPCODE:
1621 case REPE_PREFIX_OPCODE:
1624 case LOCK_PREFIX_OPCODE:
1632 case ADDR_PREFIX_OPCODE:
1636 case DATA_PREFIX_OPCODE:
1640 if (i.prefix[q] != 0)
1648 i.prefix[q] |= prefix;
1651 as_bad (_("same type of prefix used twice"));
1657 set_code_flag (int value)
1660 if (flag_code == CODE_64BIT)
1662 cpu_arch_flags.bitfield.cpu64 = 1;
1663 cpu_arch_flags.bitfield.cpuno64 = 0;
1667 cpu_arch_flags.bitfield.cpu64 = 0;
1668 cpu_arch_flags.bitfield.cpuno64 = 1;
1670 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1672 as_bad (_("64bit mode not supported on this CPU."));
1674 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1676 as_bad (_("32bit mode not supported on this CPU."));
1678 stackop_size = '\0';
1682 set_16bit_gcc_code_flag (int new_code_flag)
1684 flag_code = new_code_flag;
1685 if (flag_code != CODE_16BIT)
1687 cpu_arch_flags.bitfield.cpu64 = 0;
1688 cpu_arch_flags.bitfield.cpuno64 = 1;
1689 stackop_size = LONG_MNEM_SUFFIX;
1693 set_intel_syntax (int syntax_flag)
1695 /* Find out if register prefixing is specified. */
1696 int ask_naked_reg = 0;
1699 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1701 char *string = input_line_pointer;
1702 int e = get_symbol_end ();
1704 if (strcmp (string, "prefix") == 0)
1706 else if (strcmp (string, "noprefix") == 0)
1709 as_bad (_("bad argument to syntax directive."));
1710 *input_line_pointer = e;
1712 demand_empty_rest_of_line ();
1714 intel_syntax = syntax_flag;
1716 if (ask_naked_reg == 0)
1717 allow_naked_reg = (intel_syntax
1718 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1720 allow_naked_reg = (ask_naked_reg < 0);
1722 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1723 identifier_chars['$'] = intel_syntax ? '$' : 0;
1724 register_prefix = allow_naked_reg ? "" : "%";
1728 set_intel_mnemonic (int mnemonic_flag)
1730 intel_mnemonic = mnemonic_flag;
1734 set_allow_index_reg (int flag)
1736 allow_index_reg = flag;
1740 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1744 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1746 char *string = input_line_pointer;
1747 int e = get_symbol_end ();
1749 i386_cpu_flags flags;
1751 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1753 if (strcmp (string, cpu_arch[i].name) == 0)
1757 cpu_arch_name = cpu_arch[i].name;
1758 cpu_sub_arch_name = NULL;
1759 cpu_arch_flags = cpu_arch[i].flags;
1760 if (flag_code == CODE_64BIT)
1762 cpu_arch_flags.bitfield.cpu64 = 1;
1763 cpu_arch_flags.bitfield.cpuno64 = 0;
1767 cpu_arch_flags.bitfield.cpu64 = 0;
1768 cpu_arch_flags.bitfield.cpuno64 = 1;
1770 cpu_arch_isa = cpu_arch[i].type;
1771 cpu_arch_isa_flags = cpu_arch[i].flags;
1772 if (!cpu_arch_tune_set)
1774 cpu_arch_tune = cpu_arch_isa;
1775 cpu_arch_tune_flags = cpu_arch_isa_flags;
1780 flags = cpu_flags_or (cpu_arch_flags,
1782 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1784 if (cpu_sub_arch_name)
1786 char *name = cpu_sub_arch_name;
1787 cpu_sub_arch_name = concat (name,
1789 (const char *) NULL);
1793 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1794 cpu_arch_flags = flags;
1796 *input_line_pointer = e;
1797 demand_empty_rest_of_line ();
1801 if (i >= ARRAY_SIZE (cpu_arch))
1802 as_bad (_("no such architecture: `%s'"), string);
1804 *input_line_pointer = e;
1807 as_bad (_("missing cpu architecture"));
1809 no_cond_jump_promotion = 0;
1810 if (*input_line_pointer == ','
1811 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1813 char *string = ++input_line_pointer;
1814 int e = get_symbol_end ();
1816 if (strcmp (string, "nojumps") == 0)
1817 no_cond_jump_promotion = 1;
1818 else if (strcmp (string, "jumps") == 0)
1821 as_bad (_("no such architecture modifier: `%s'"), string);
1823 *input_line_pointer = e;
1826 demand_empty_rest_of_line ();
1832 if (!strcmp (default_arch, "x86_64"))
1833 return bfd_mach_x86_64;
1834 else if (!strcmp (default_arch, "i386"))
1835 return bfd_mach_i386_i386;
1837 as_fatal (_("Unknown architecture"));
1843 const char *hash_err;
1845 /* Initialize op_hash hash table. */
1846 op_hash = hash_new ();
1849 const template *optab;
1850 templates *core_optab;
1852 /* Setup for loop. */
1854 core_optab = (templates *) xmalloc (sizeof (templates));
1855 core_optab->start = optab;
1860 if (optab->name == NULL
1861 || strcmp (optab->name, (optab - 1)->name) != 0)
1863 /* different name --> ship out current template list;
1864 add to hash table; & begin anew. */
1865 core_optab->end = optab;
1866 hash_err = hash_insert (op_hash,
1871 as_fatal (_("Internal Error: Can't hash %s: %s"),
1875 if (optab->name == NULL)
1877 core_optab = (templates *) xmalloc (sizeof (templates));
1878 core_optab->start = optab;
1883 /* Initialize reg_hash hash table. */
1884 reg_hash = hash_new ();
1886 const reg_entry *regtab;
1887 unsigned int regtab_size = i386_regtab_size;
1889 for (regtab = i386_regtab; regtab_size--; regtab++)
1891 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1893 as_fatal (_("Internal Error: Can't hash %s: %s"),
1899 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1904 for (c = 0; c < 256; c++)
1909 mnemonic_chars[c] = c;
1910 register_chars[c] = c;
1911 operand_chars[c] = c;
1913 else if (ISLOWER (c))
1915 mnemonic_chars[c] = c;
1916 register_chars[c] = c;
1917 operand_chars[c] = c;
1919 else if (ISUPPER (c))
1921 mnemonic_chars[c] = TOLOWER (c);
1922 register_chars[c] = mnemonic_chars[c];
1923 operand_chars[c] = c;
1926 if (ISALPHA (c) || ISDIGIT (c))
1927 identifier_chars[c] = c;
1930 identifier_chars[c] = c;
1931 operand_chars[c] = c;
1936 identifier_chars['@'] = '@';
1939 identifier_chars['?'] = '?';
1940 operand_chars['?'] = '?';
1942 digit_chars['-'] = '-';
1943 mnemonic_chars['-'] = '-';
1944 mnemonic_chars['.'] = '.';
1945 identifier_chars['_'] = '_';
1946 identifier_chars['.'] = '.';
1948 for (p = operand_special_chars; *p != '\0'; p++)
1949 operand_chars[(unsigned char) *p] = *p;
1952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1955 record_alignment (text_section, 2);
1956 record_alignment (data_section, 2);
1957 record_alignment (bss_section, 2);
1961 if (flag_code == CODE_64BIT)
1963 x86_dwarf2_return_column = 16;
1964 x86_cie_data_alignment = -8;
1968 x86_dwarf2_return_column = 8;
1969 x86_cie_data_alignment = -4;
1974 i386_print_statistics (FILE *file)
1976 hash_print_statistics (file, "i386 opcode", op_hash);
1977 hash_print_statistics (file, "i386 register", reg_hash);
1982 /* Debugging routines for md_assemble. */
1983 static void pte (template *);
1984 static void pt (i386_operand_type);
1985 static void pe (expressionS *);
1986 static void ps (symbolS *);
1989 pi (char *line, i386_insn *x)
1993 fprintf (stdout, "%s: template ", line);
1995 fprintf (stdout, " address: base %s index %s scale %x\n",
1996 x->base_reg ? x->base_reg->reg_name : "none",
1997 x->index_reg ? x->index_reg->reg_name : "none",
1998 x->log2_scale_factor);
1999 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2000 x->rm.mode, x->rm.reg, x->rm.regmem);
2001 fprintf (stdout, " sib: base %x index %x scale %x\n",
2002 x->sib.base, x->sib.index, x->sib.scale);
2003 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2004 (x->rex & REX_W) != 0,
2005 (x->rex & REX_R) != 0,
2006 (x->rex & REX_X) != 0,
2007 (x->rex & REX_B) != 0);
2008 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2009 x->drex.reg, x->drex.rex);
2010 for (i = 0; i < x->operands; i++)
2012 fprintf (stdout, " #%d: ", i + 1);
2014 fprintf (stdout, "\n");
2015 if (x->types[i].bitfield.reg8
2016 || x->types[i].bitfield.reg16
2017 || x->types[i].bitfield.reg32
2018 || x->types[i].bitfield.reg64
2019 || x->types[i].bitfield.regmmx
2020 || x->types[i].bitfield.regxmm
2021 || x->types[i].bitfield.sreg2
2022 || x->types[i].bitfield.sreg3
2023 || x->types[i].bitfield.control
2024 || x->types[i].bitfield.debug
2025 || x->types[i].bitfield.test)
2026 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2027 if (operand_type_check (x->types[i], imm))
2029 if (operand_type_check (x->types[i], disp))
2030 pe (x->op[i].disps);
2038 fprintf (stdout, " %d operands ", t->operands);
2039 fprintf (stdout, "opcode %x ", t->base_opcode);
2040 if (t->extension_opcode != None)
2041 fprintf (stdout, "ext %x ", t->extension_opcode);
2042 if (t->opcode_modifier.d)
2043 fprintf (stdout, "D");
2044 if (t->opcode_modifier.w)
2045 fprintf (stdout, "W");
2046 fprintf (stdout, "\n");
2047 for (i = 0; i < t->operands; i++)
2049 fprintf (stdout, " #%d type ", i + 1);
2050 pt (t->operand_types[i]);
2051 fprintf (stdout, "\n");
2058 fprintf (stdout, " operation %d\n", e->X_op);
2059 fprintf (stdout, " add_number %ld (%lx)\n",
2060 (long) e->X_add_number, (long) e->X_add_number);
2061 if (e->X_add_symbol)
2063 fprintf (stdout, " add_symbol ");
2064 ps (e->X_add_symbol);
2065 fprintf (stdout, "\n");
2069 fprintf (stdout, " op_symbol ");
2070 ps (e->X_op_symbol);
2071 fprintf (stdout, "\n");
2078 fprintf (stdout, "%s type %s%s",
2080 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2081 segment_name (S_GET_SEGMENT (s)));
2084 static struct type_name
2086 i386_operand_type mask;
2089 const type_names[] =
2091 { OPERAND_TYPE_REG8, "r8" },
2092 { OPERAND_TYPE_REG16, "r16" },
2093 { OPERAND_TYPE_REG32, "r32" },
2094 { OPERAND_TYPE_REG64, "r64" },
2095 { OPERAND_TYPE_IMM8, "i8" },
2096 { OPERAND_TYPE_IMM8, "i8s" },
2097 { OPERAND_TYPE_IMM16, "i16" },
2098 { OPERAND_TYPE_IMM32, "i32" },
2099 { OPERAND_TYPE_IMM32S, "i32s" },
2100 { OPERAND_TYPE_IMM64, "i64" },
2101 { OPERAND_TYPE_IMM1, "i1" },
2102 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2103 { OPERAND_TYPE_DISP8, "d8" },
2104 { OPERAND_TYPE_DISP16, "d16" },
2105 { OPERAND_TYPE_DISP32, "d32" },
2106 { OPERAND_TYPE_DISP32S, "d32s" },
2107 { OPERAND_TYPE_DISP64, "d64" },
2108 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2109 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2110 { OPERAND_TYPE_CONTROL, "control reg" },
2111 { OPERAND_TYPE_TEST, "test reg" },
2112 { OPERAND_TYPE_DEBUG, "debug reg" },
2113 { OPERAND_TYPE_FLOATREG, "FReg" },
2114 { OPERAND_TYPE_FLOATACC, "FAcc" },
2115 { OPERAND_TYPE_SREG2, "SReg2" },
2116 { OPERAND_TYPE_SREG3, "SReg3" },
2117 { OPERAND_TYPE_ACC, "Acc" },
2118 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2119 { OPERAND_TYPE_REGMMX, "rMMX" },
2120 { OPERAND_TYPE_REGXMM, "rXMM" },
2121 { OPERAND_TYPE_ESSEG, "es" },
2125 pt (i386_operand_type t)
2128 i386_operand_type a;
2130 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2132 a = operand_type_and (t, type_names[j].mask);
2133 if (!UINTS_ALL_ZERO (a))
2134 fprintf (stdout, "%s, ", type_names[j].name);
2139 #endif /* DEBUG386 */
2141 static bfd_reloc_code_real_type
2142 reloc (unsigned int size,
2145 bfd_reloc_code_real_type other)
2147 if (other != NO_RELOC)
2149 reloc_howto_type *reloc;
2154 case BFD_RELOC_X86_64_GOT32:
2155 return BFD_RELOC_X86_64_GOT64;
2157 case BFD_RELOC_X86_64_PLTOFF64:
2158 return BFD_RELOC_X86_64_PLTOFF64;
2160 case BFD_RELOC_X86_64_GOTPC32:
2161 other = BFD_RELOC_X86_64_GOTPC64;
2163 case BFD_RELOC_X86_64_GOTPCREL:
2164 other = BFD_RELOC_X86_64_GOTPCREL64;
2166 case BFD_RELOC_X86_64_TPOFF32:
2167 other = BFD_RELOC_X86_64_TPOFF64;
2169 case BFD_RELOC_X86_64_DTPOFF32:
2170 other = BFD_RELOC_X86_64_DTPOFF64;
2176 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2177 if (size == 4 && flag_code != CODE_64BIT)
2180 reloc = bfd_reloc_type_lookup (stdoutput, other);
2182 as_bad (_("unknown relocation (%u)"), other);
2183 else if (size != bfd_get_reloc_size (reloc))
2184 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2185 bfd_get_reloc_size (reloc),
2187 else if (pcrel && !reloc->pc_relative)
2188 as_bad (_("non-pc-relative relocation for pc-relative field"));
2189 else if ((reloc->complain_on_overflow == complain_overflow_signed
2191 || (reloc->complain_on_overflow == complain_overflow_unsigned
2193 as_bad (_("relocated field and relocation type differ in signedness"));
2202 as_bad (_("there are no unsigned pc-relative relocations"));
2205 case 1: return BFD_RELOC_8_PCREL;
2206 case 2: return BFD_RELOC_16_PCREL;
2207 case 4: return BFD_RELOC_32_PCREL;
2208 case 8: return BFD_RELOC_64_PCREL;
2210 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2217 case 4: return BFD_RELOC_X86_64_32S;
2222 case 1: return BFD_RELOC_8;
2223 case 2: return BFD_RELOC_16;
2224 case 4: return BFD_RELOC_32;
2225 case 8: return BFD_RELOC_64;
2227 as_bad (_("cannot do %s %u byte relocation"),
2228 sign > 0 ? "signed" : "unsigned", size);
2232 return BFD_RELOC_NONE;
2235 /* Here we decide which fixups can be adjusted to make them relative to
2236 the beginning of the section instead of the symbol. Basically we need
2237 to make sure that the dynamic relocations are done correctly, so in
2238 some cases we force the original symbol to be used. */
2241 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2247 /* Don't adjust pc-relative references to merge sections in 64-bit
2249 if (use_rela_relocations
2250 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2254 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2255 and changed later by validate_fix. */
2256 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2257 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2260 /* adjust_reloc_syms doesn't know about the GOT. */
2261 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2262 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2263 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2264 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2265 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2266 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2267 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2268 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2269 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2270 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2271 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2272 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2273 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2274 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2275 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2276 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2277 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2278 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2279 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2280 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2281 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2282 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2283 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2284 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2285 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2286 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2287 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2288 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2295 intel_float_operand (const char *mnemonic)
2297 /* Note that the value returned is meaningful only for opcodes with (memory)
2298 operands, hence the code here is free to improperly handle opcodes that
2299 have no operands (for better performance and smaller code). */
2301 if (mnemonic[0] != 'f')
2302 return 0; /* non-math */
2304 switch (mnemonic[1])
2306 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2307 the fs segment override prefix not currently handled because no
2308 call path can make opcodes without operands get here */
2310 return 2 /* integer op */;
2312 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2313 return 3; /* fldcw/fldenv */
2316 if (mnemonic[2] != 'o' /* fnop */)
2317 return 3; /* non-waiting control op */
2320 if (mnemonic[2] == 's')
2321 return 3; /* frstor/frstpm */
2324 if (mnemonic[2] == 'a')
2325 return 3; /* fsave */
2326 if (mnemonic[2] == 't')
2328 switch (mnemonic[3])
2330 case 'c': /* fstcw */
2331 case 'd': /* fstdw */
2332 case 'e': /* fstenv */
2333 case 's': /* fsts[gw] */
2339 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2340 return 0; /* fxsave/fxrstor are not really math ops */
2347 /* This is the guts of the machine-dependent assembler. LINE points to a
2348 machine dependent instruction. This function is supposed to emit
2349 the frags/bytes it assembles to. */
2356 char mnemonic[MAX_MNEM_SIZE];
2358 /* Initialize globals. */
2359 memset (&i, '\0', sizeof (i));
2360 for (j = 0; j < MAX_OPERANDS; j++)
2361 i.reloc[j] = NO_RELOC;
2362 memset (disp_expressions, '\0', sizeof (disp_expressions));
2363 memset (im_expressions, '\0', sizeof (im_expressions));
2364 save_stack_p = save_stack;
2366 /* First parse an instruction mnemonic & call i386_operand for the operands.
2367 We assume that the scrubber has arranged it so that line[0] is the valid
2368 start of a (possibly prefixed) mnemonic. */
2370 line = parse_insn (line, mnemonic);
2374 line = parse_operands (line, mnemonic);
2378 /* Now we've parsed the mnemonic into a set of templates, and have the
2379 operands at hand. */
2381 /* All intel opcodes have reversed operands except for "bound" and
2382 "enter". We also don't reverse intersegment "jmp" and "call"
2383 instructions with 2 immediate operands so that the immediate segment
2384 precedes the offset, as it does when in AT&T mode. */
2387 && (strcmp (mnemonic, "bound") != 0)
2388 && (strcmp (mnemonic, "invlpga") != 0)
2389 && !(operand_type_check (i.types[0], imm)
2390 && operand_type_check (i.types[1], imm)))
2393 /* The order of the immediates should be reversed
2394 for 2 immediates extrq and insertq instructions */
2395 if (i.imm_operands == 2
2396 && (strcmp (mnemonic, "extrq") == 0
2397 || strcmp (mnemonic, "insertq") == 0))
2398 swap_2_operands (0, 1);
2403 /* Don't optimize displacement for movabs since it only takes 64bit
2406 && (flag_code != CODE_64BIT
2407 || strcmp (mnemonic, "movabs") != 0))
2410 /* Next, we find a template that matches the given insn,
2411 making sure the overlap of the given operands types is consistent
2412 with the template operand types. */
2414 if (!match_template ())
2417 /* Zap movzx and movsx suffix. The suffix has been set from
2418 "word ptr" or "byte ptr" on the source operand in Intel syntax
2419 or extracted from mnemonic in AT&T syntax. But we'll use
2420 the destination register to choose the suffix for encoding. */
2421 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2423 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2424 there is no suffix, the default will be byte extension. */
2425 if (i.reg_operands != 2
2428 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2433 if (i.tm.opcode_modifier.fwait)
2434 if (!add_prefix (FWAIT_OPCODE))
2437 /* Check string instruction segment overrides. */
2438 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2440 if (!check_string ())
2444 if (!process_suffix ())
2447 /* Make still unresolved immediate matches conform to size of immediate
2448 given in i.suffix. */
2449 if (!finalize_imm ())
2452 if (i.types[0].bitfield.imm1)
2453 i.imm_operands = 0; /* kludge for shift insns. */
2455 for (j = 0; j < 3; j++)
2456 if (i.types[j].bitfield.inoutportreg
2457 || i.types[j].bitfield.shiftcount
2458 || i.types[j].bitfield.acc
2459 || i.types[j].bitfield.floatacc)
2462 if (i.tm.opcode_modifier.immext)
2466 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2468 /* Streaming SIMD extensions 3 Instructions have the fixed
2469 operands with an opcode suffix which is coded in the same
2470 place as an 8-bit immediate field would be. Here we check
2471 those operands and remove them afterwards. */
2474 for (x = 0; x < i.operands; x++)
2475 if (i.op[x].regs->reg_num != x)
2476 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2478 i.op[x].regs->reg_name,
2484 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2485 opcode suffix which is coded in the same place as an 8-bit
2486 immediate field would be. Here we fake an 8-bit immediate
2487 operand from the opcode suffix stored in tm.extension_opcode.
2488 SSE5 also uses this encoding, for some of its 3 argument
2491 assert (i.imm_operands == 0
2493 || (i.tm.cpu_flags.bitfield.cpusse5
2494 && i.operands <= 3)));
2496 exp = &im_expressions[i.imm_operands++];
2497 i.op[i.operands].imms = exp;
2498 UINTS_CLEAR (i.types[i.operands]);
2499 i.types[i.operands].bitfield.imm8 = 1;
2501 exp->X_op = O_constant;
2502 exp->X_add_number = i.tm.extension_opcode;
2503 i.tm.extension_opcode = None;
2506 /* For insns with operands there are more diddles to do to the opcode. */
2509 if (!process_operands ())
2512 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2514 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2515 as_warn (_("translating to `%sp'"), i.tm.name);
2518 /* Handle conversion of 'int $3' --> special int3 insn. */
2519 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2521 i.tm.base_opcode = INT3_OPCODE;
2525 if ((i.tm.opcode_modifier.jump
2526 || i.tm.opcode_modifier.jumpbyte
2527 || i.tm.opcode_modifier.jumpdword)
2528 && i.op[0].disps->X_op == O_constant)
2530 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2531 the absolute address given by the constant. Since ix86 jumps and
2532 calls are pc relative, we need to generate a reloc. */
2533 i.op[0].disps->X_add_symbol = &abs_symbol;
2534 i.op[0].disps->X_op = O_symbol;
2537 if (i.tm.opcode_modifier.rex64)
2540 /* For 8 bit registers we need an empty rex prefix. Also if the
2541 instruction already has a prefix, we need to convert old
2542 registers to new ones. */
2544 if ((i.types[0].bitfield.reg8
2545 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2546 || (i.types[1].bitfield.reg8
2547 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2548 || ((i.types[0].bitfield.reg8
2549 || i.types[1].bitfield.reg8)
2554 i.rex |= REX_OPCODE;
2555 for (x = 0; x < 2; x++)
2557 /* Look for 8 bit operand that uses old registers. */
2558 if (i.types[x].bitfield.reg8
2559 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2561 /* In case it is "hi" register, give up. */
2562 if (i.op[x].regs->reg_num > 3)
2563 as_bad (_("can't encode register '%s%s' in an "
2564 "instruction requiring REX prefix."),
2565 register_prefix, i.op[x].regs->reg_name);
2567 /* Otherwise it is equivalent to the extended register.
2568 Since the encoding doesn't change this is merely
2569 cosmetic cleanup for debug output. */
2571 i.op[x].regs = i.op[x].regs + 8;
2576 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2578 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2583 else if (i.rex != 0)
2584 add_prefix (REX_OPCODE | i.rex);
2586 /* We are ready to output the insn. */
2591 parse_insn (char *line, char *mnemonic)
2594 char *token_start = l;
2599 /* Non-zero if we found a prefix only acceptable with string insns. */
2600 const char *expecting_string_instruction = NULL;
2605 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2608 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2610 as_bad (_("no such instruction: `%s'"), token_start);
2615 if (!is_space_char (*l)
2616 && *l != END_OF_INSN
2618 || (*l != PREFIX_SEPARATOR
2621 as_bad (_("invalid character %s in mnemonic"),
2622 output_invalid (*l));
2625 if (token_start == l)
2627 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2628 as_bad (_("expecting prefix; got nothing"));
2630 as_bad (_("expecting mnemonic; got nothing"));
2634 /* Look up instruction (or prefix) via hash table. */
2635 current_templates = hash_find (op_hash, mnemonic);
2637 if (*l != END_OF_INSN
2638 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2639 && current_templates
2640 && current_templates->start->opcode_modifier.isprefix)
2642 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2644 as_bad ((flag_code != CODE_64BIT
2645 ? _("`%s' is only supported in 64-bit mode")
2646 : _("`%s' is not supported in 64-bit mode")),
2647 current_templates->start->name);
2650 /* If we are in 16-bit mode, do not allow addr16 or data16.
2651 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2652 if ((current_templates->start->opcode_modifier.size16
2653 || current_templates->start->opcode_modifier.size32)
2654 && flag_code != CODE_64BIT
2655 && (current_templates->start->opcode_modifier.size32
2656 ^ (flag_code == CODE_16BIT)))
2658 as_bad (_("redundant %s prefix"),
2659 current_templates->start->name);
2662 /* Add prefix, checking for repeated prefixes. */
2663 switch (add_prefix (current_templates->start->base_opcode))
2668 expecting_string_instruction = current_templates->start->name;
2671 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2678 if (!current_templates)
2680 /* See if we can get a match by trimming off a suffix. */
2683 case WORD_MNEM_SUFFIX:
2684 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2685 i.suffix = SHORT_MNEM_SUFFIX;
2687 case BYTE_MNEM_SUFFIX:
2688 case QWORD_MNEM_SUFFIX:
2689 i.suffix = mnem_p[-1];
2691 current_templates = hash_find (op_hash, mnemonic);
2693 case SHORT_MNEM_SUFFIX:
2694 case LONG_MNEM_SUFFIX:
2697 i.suffix = mnem_p[-1];
2699 current_templates = hash_find (op_hash, mnemonic);
2707 if (intel_float_operand (mnemonic) == 1)
2708 i.suffix = SHORT_MNEM_SUFFIX;
2710 i.suffix = LONG_MNEM_SUFFIX;
2712 current_templates = hash_find (op_hash, mnemonic);
2716 if (!current_templates)
2718 as_bad (_("no such instruction: `%s'"), token_start);
2723 if (current_templates->start->opcode_modifier.jump
2724 || current_templates->start->opcode_modifier.jumpbyte)
2726 /* Check for a branch hint. We allow ",pt" and ",pn" for
2727 predict taken and predict not taken respectively.
2728 I'm not sure that branch hints actually do anything on loop
2729 and jcxz insns (JumpByte) for current Pentium4 chips. They
2730 may work in the future and it doesn't hurt to accept them
2732 if (l[0] == ',' && l[1] == 'p')
2736 if (!add_prefix (DS_PREFIX_OPCODE))
2740 else if (l[2] == 'n')
2742 if (!add_prefix (CS_PREFIX_OPCODE))
2748 /* Any other comma loses. */
2751 as_bad (_("invalid character %s in mnemonic"),
2752 output_invalid (*l));
2756 /* Check if instruction is supported on specified architecture. */
2758 for (t = current_templates->start; t < current_templates->end; ++t)
2760 supported |= cpu_flags_match (t->cpu_flags);
2765 if (!(supported & 2))
2767 as_bad (flag_code == CODE_64BIT
2768 ? _("`%s' is not supported in 64-bit mode")
2769 : _("`%s' is only supported in 64-bit mode"),
2770 current_templates->start->name);
2773 if (!(supported & 1))
2775 as_bad (_("`%s' is not supported on `%s%s'"),
2776 current_templates->start->name, cpu_arch_name,
2777 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2782 if (!cpu_arch_flags.bitfield.cpui386
2783 && (flag_code != CODE_16BIT))
2785 as_warn (_("use .code16 to ensure correct addressing mode"));
2788 /* Check for rep/repne without a string instruction. */
2789 if (expecting_string_instruction)
2791 static templates override;
2793 for (t = current_templates->start; t < current_templates->end; ++t)
2794 if (t->opcode_modifier.isstring)
2796 if (t >= current_templates->end)
2798 as_bad (_("expecting string instruction after `%s'"),
2799 expecting_string_instruction);
2802 for (override.start = t; t < current_templates->end; ++t)
2803 if (!t->opcode_modifier.isstring)
2806 current_templates = &override;
2813 parse_operands (char *l, const char *mnemonic)
2817 /* 1 if operand is pending after ','. */
2818 unsigned int expecting_operand = 0;
2820 /* Non-zero if operand parens not balanced. */
2821 unsigned int paren_not_balanced;
2823 while (*l != END_OF_INSN)
2825 /* Skip optional white space before operand. */
2826 if (is_space_char (*l))
2828 if (!is_operand_char (*l) && *l != END_OF_INSN)
2830 as_bad (_("invalid character %s before operand %d"),
2831 output_invalid (*l),
2835 token_start = l; /* after white space */
2836 paren_not_balanced = 0;
2837 while (paren_not_balanced || *l != ',')
2839 if (*l == END_OF_INSN)
2841 if (paren_not_balanced)
2844 as_bad (_("unbalanced parenthesis in operand %d."),
2847 as_bad (_("unbalanced brackets in operand %d."),
2852 break; /* we are done */
2854 else if (!is_operand_char (*l) && !is_space_char (*l))
2856 as_bad (_("invalid character %s in operand %d"),
2857 output_invalid (*l),
2864 ++paren_not_balanced;
2866 --paren_not_balanced;
2871 ++paren_not_balanced;
2873 --paren_not_balanced;
2877 if (l != token_start)
2878 { /* Yes, we've read in another operand. */
2879 unsigned int operand_ok;
2880 this_operand = i.operands++;
2881 i.types[this_operand].bitfield.unspecified = 1;
2882 if (i.operands > MAX_OPERANDS)
2884 as_bad (_("spurious operands; (%d operands/instruction max)"),
2888 /* Now parse operand adding info to 'i' as we go along. */
2889 END_STRING_AND_SAVE (l);
2893 i386_intel_operand (token_start,
2894 intel_float_operand (mnemonic));
2896 operand_ok = i386_att_operand (token_start);
2898 RESTORE_END_STRING (l);
2904 if (expecting_operand)
2906 expecting_operand_after_comma:
2907 as_bad (_("expecting operand after ','; got nothing"));
2912 as_bad (_("expecting operand before ','; got nothing"));
2917 /* Now *l must be either ',' or END_OF_INSN. */
2920 if (*++l == END_OF_INSN)
2922 /* Just skip it, if it's \n complain. */
2923 goto expecting_operand_after_comma;
2925 expecting_operand = 1;
2932 swap_2_operands (int xchg1, int xchg2)
2934 union i386_op temp_op;
2935 i386_operand_type temp_type;
2936 enum bfd_reloc_code_real temp_reloc;
2938 temp_type = i.types[xchg2];
2939 i.types[xchg2] = i.types[xchg1];
2940 i.types[xchg1] = temp_type;
2941 temp_op = i.op[xchg2];
2942 i.op[xchg2] = i.op[xchg1];
2943 i.op[xchg1] = temp_op;
2944 temp_reloc = i.reloc[xchg2];
2945 i.reloc[xchg2] = i.reloc[xchg1];
2946 i.reloc[xchg1] = temp_reloc;
2950 swap_operands (void)
2955 swap_2_operands (1, i.operands - 2);
2958 swap_2_operands (0, i.operands - 1);
2964 if (i.mem_operands == 2)
2966 const seg_entry *temp_seg;
2967 temp_seg = i.seg[0];
2968 i.seg[0] = i.seg[1];
2969 i.seg[1] = temp_seg;
2973 /* Try to ensure constant immediates are represented in the smallest
2978 char guess_suffix = 0;
2982 guess_suffix = i.suffix;
2983 else if (i.reg_operands)
2985 /* Figure out a suffix from the last register operand specified.
2986 We can't do this properly yet, ie. excluding InOutPortReg,
2987 but the following works for instructions with immediates.
2988 In any case, we can't set i.suffix yet. */
2989 for (op = i.operands; --op >= 0;)
2990 if (i.types[op].bitfield.reg8)
2992 guess_suffix = BYTE_MNEM_SUFFIX;
2995 else if (i.types[op].bitfield.reg16)
2997 guess_suffix = WORD_MNEM_SUFFIX;
3000 else if (i.types[op].bitfield.reg32)
3002 guess_suffix = LONG_MNEM_SUFFIX;
3005 else if (i.types[op].bitfield.reg64)
3007 guess_suffix = QWORD_MNEM_SUFFIX;
3011 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3012 guess_suffix = WORD_MNEM_SUFFIX;
3014 for (op = i.operands; --op >= 0;)
3015 if (operand_type_check (i.types[op], imm))
3017 switch (i.op[op].imms->X_op)
3020 /* If a suffix is given, this operand may be shortened. */
3021 switch (guess_suffix)
3023 case LONG_MNEM_SUFFIX:
3024 i.types[op].bitfield.imm32 = 1;
3025 i.types[op].bitfield.imm64 = 1;
3027 case WORD_MNEM_SUFFIX:
3028 i.types[op].bitfield.imm16 = 1;
3029 i.types[op].bitfield.imm32 = 1;
3030 i.types[op].bitfield.imm32s = 1;
3031 i.types[op].bitfield.imm64 = 1;
3033 case BYTE_MNEM_SUFFIX:
3034 i.types[op].bitfield.imm8 = 1;
3035 i.types[op].bitfield.imm8s = 1;
3036 i.types[op].bitfield.imm16 = 1;
3037 i.types[op].bitfield.imm32 = 1;
3038 i.types[op].bitfield.imm32s = 1;
3039 i.types[op].bitfield.imm64 = 1;
3043 /* If this operand is at most 16 bits, convert it
3044 to a signed 16 bit number before trying to see
3045 whether it will fit in an even smaller size.
3046 This allows a 16-bit operand such as $0xffe0 to
3047 be recognised as within Imm8S range. */
3048 if ((i.types[op].bitfield.imm16)
3049 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3051 i.op[op].imms->X_add_number =
3052 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3054 if ((i.types[op].bitfield.imm32)
3055 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3058 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3059 ^ ((offsetT) 1 << 31))
3060 - ((offsetT) 1 << 31));
3063 = operand_type_or (i.types[op],
3064 smallest_imm_type (i.op[op].imms->X_add_number));
3066 /* We must avoid matching of Imm32 templates when 64bit
3067 only immediate is available. */
3068 if (guess_suffix == QWORD_MNEM_SUFFIX)
3069 i.types[op].bitfield.imm32 = 0;
3076 /* Symbols and expressions. */
3078 /* Convert symbolic operand to proper sizes for matching, but don't
3079 prevent matching a set of insns that only supports sizes other
3080 than those matching the insn suffix. */
3082 i386_operand_type mask, allowed;
3086 UINTS_CLEAR (allowed);
3088 for (t = current_templates->start;
3089 t < current_templates->end;
3091 allowed = operand_type_or (allowed,
3092 t->operand_types[op]);
3093 switch (guess_suffix)
3095 case QWORD_MNEM_SUFFIX:
3096 mask.bitfield.imm64 = 1;
3097 mask.bitfield.imm32s = 1;
3099 case LONG_MNEM_SUFFIX:
3100 mask.bitfield.imm32 = 1;
3102 case WORD_MNEM_SUFFIX:
3103 mask.bitfield.imm16 = 1;
3105 case BYTE_MNEM_SUFFIX:
3106 mask.bitfield.imm8 = 1;
3111 allowed = operand_type_and (mask, allowed);
3112 if (!UINTS_ALL_ZERO (allowed))
3113 i.types[op] = operand_type_and (i.types[op], mask);
3120 /* Try to use the smallest displacement type too. */
3122 optimize_disp (void)
3126 for (op = i.operands; --op >= 0;)
3127 if (operand_type_check (i.types[op], disp))
3129 if (i.op[op].disps->X_op == O_constant)
3131 offsetT disp = i.op[op].disps->X_add_number;
3133 if (i.types[op].bitfield.disp16
3134 && (disp & ~(offsetT) 0xffff) == 0)
3136 /* If this operand is at most 16 bits, convert
3137 to a signed 16 bit number and don't use 64bit
3139 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3140 i.types[op].bitfield.disp64 = 0;
3142 if (i.types[op].bitfield.disp32
3143 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3145 /* If this operand is at most 32 bits, convert
3146 to a signed 32 bit number and don't use 64bit
3148 disp &= (((offsetT) 2 << 31) - 1);
3149 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3150 i.types[op].bitfield.disp64 = 0;
3152 if (!disp && i.types[op].bitfield.baseindex)
3154 i.types[op].bitfield.disp8 = 0;
3155 i.types[op].bitfield.disp16 = 0;
3156 i.types[op].bitfield.disp32 = 0;
3157 i.types[op].bitfield.disp32s = 0;
3158 i.types[op].bitfield.disp64 = 0;
3162 else if (flag_code == CODE_64BIT)
3164 if (fits_in_signed_long (disp))
3166 i.types[op].bitfield.disp64 = 0;
3167 i.types[op].bitfield.disp32s = 1;
3169 if (fits_in_unsigned_long (disp))
3170 i.types[op].bitfield.disp32 = 1;
3172 if ((i.types[op].bitfield.disp32
3173 || i.types[op].bitfield.disp32s
3174 || i.types[op].bitfield.disp16)
3175 && fits_in_signed_byte (disp))
3176 i.types[op].bitfield.disp8 = 1;
3178 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3179 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3181 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3182 i.op[op].disps, 0, i.reloc[op]);
3183 i.types[op].bitfield.disp8 = 0;
3184 i.types[op].bitfield.disp16 = 0;
3185 i.types[op].bitfield.disp32 = 0;
3186 i.types[op].bitfield.disp32s = 0;
3187 i.types[op].bitfield.disp64 = 0;
3190 /* We only support 64bit displacement on constants. */
3191 i.types[op].bitfield.disp64 = 0;
3196 match_template (void)
3198 /* Points to template once we've found it. */
3200 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3201 unsigned int found_reverse_match;
3202 i386_opcode_modifier suffix_check;
3203 i386_operand_type operand_types [MAX_OPERANDS];
3204 int addr_prefix_disp;
3206 unsigned int found_cpu_match;
3207 unsigned int check_register;
3209 #if MAX_OPERANDS != 4
3210 # error "MAX_OPERANDS must be 4."
3213 found_reverse_match = 0;
3214 addr_prefix_disp = -1;
3216 memset (&suffix_check, 0, sizeof (suffix_check));
3217 if (i.suffix == BYTE_MNEM_SUFFIX)
3218 suffix_check.no_bsuf = 1;
3219 else if (i.suffix == WORD_MNEM_SUFFIX)
3220 suffix_check.no_wsuf = 1;
3221 else if (i.suffix == SHORT_MNEM_SUFFIX)
3222 suffix_check.no_ssuf = 1;
3223 else if (i.suffix == LONG_MNEM_SUFFIX)
3224 suffix_check.no_lsuf = 1;
3225 else if (i.suffix == QWORD_MNEM_SUFFIX)
3226 suffix_check.no_qsuf = 1;
3227 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3228 suffix_check.no_ldsuf = 1;
3230 for (t = current_templates->start; t < current_templates->end; t++)
3232 addr_prefix_disp = -1;
3234 /* Must have right number of operands. */
3235 if (i.operands != t->operands)
3238 /* Check processor support. */
3239 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3240 if (!found_cpu_match)
3243 /* Check old gcc support. */
3244 if (!old_gcc && t->opcode_modifier.oldgcc)
3247 /* Check AT&T mnemonic. */
3248 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3251 /* Check AT&T syntax Intel syntax. */
3252 if ((intel_syntax && t->opcode_modifier.attsyntax)
3253 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3256 /* Check the suffix, except for some instructions in intel mode. */
3257 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3258 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3259 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3260 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3261 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3262 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3263 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3266 if (!operand_size_match (t))
3269 for (j = 0; j < MAX_OPERANDS; j++)
3270 operand_types[j] = t->operand_types[j];
3272 /* In general, don't allow 64-bit operands in 32-bit mode. */
3273 if (i.suffix == QWORD_MNEM_SUFFIX
3274 && flag_code != CODE_64BIT
3276 ? (!t->opcode_modifier.ignoresize
3277 && !intel_float_operand (t->name))
3278 : intel_float_operand (t->name) != 2)
3279 && ((!operand_types[0].bitfield.regmmx
3280 && !operand_types[0].bitfield.regxmm)
3281 || (!operand_types[t->operands > 1].bitfield.regmmx
3282 && !!operand_types[t->operands > 1].bitfield.regxmm))
3283 && (t->base_opcode != 0x0fc7
3284 || t->extension_opcode != 1 /* cmpxchg8b */))
3287 /* Do not verify operands when there are none. */
3291 /* We've found a match; break out of loop. */
3295 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3296 into Disp32/Disp16/Disp32 operand. */
3297 if (i.prefix[ADDR_PREFIX] != 0)
3299 /* There should be only one Disp operand. */
3303 for (j = 0; j < MAX_OPERANDS; j++)
3305 if (operand_types[j].bitfield.disp16)
3307 addr_prefix_disp = j;
3308 operand_types[j].bitfield.disp32 = 1;
3309 operand_types[j].bitfield.disp16 = 0;
3315 for (j = 0; j < MAX_OPERANDS; j++)
3317 if (operand_types[j].bitfield.disp32)
3319 addr_prefix_disp = j;
3320 operand_types[j].bitfield.disp32 = 0;
3321 operand_types[j].bitfield.disp16 = 1;
3327 for (j = 0; j < MAX_OPERANDS; j++)
3329 if (operand_types[j].bitfield.disp64)
3331 addr_prefix_disp = j;
3332 operand_types[j].bitfield.disp64 = 0;
3333 operand_types[j].bitfield.disp32 = 1;
3341 /* We check register size only if size of operands can be
3342 encoded the canonical way. */
3343 check_register = t->opcode_modifier.w;
3344 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3345 switch (t->operands)
3348 if (!operand_type_match (overlap0, i.types[0]))
3352 /* xchg %eax, %eax is a special case. It is an aliase for nop
3353 only in 32bit mode and we can use opcode 0x90. In 64bit
3354 mode, we can't use 0x90 for xchg %eax, %eax since it should
3355 zero-extend %eax to %rax. */
3356 if (flag_code == CODE_64BIT
3357 && t->base_opcode == 0x90
3358 && UINTS_EQUAL (i.types [0], acc32)
3359 && UINTS_EQUAL (i.types [1], acc32))
3363 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3364 if (!operand_type_match (overlap0, i.types[0])
3365 || !operand_type_match (overlap1, i.types[1])
3367 && !operand_type_register_match (overlap0, i.types[0],
3369 overlap1, i.types[1],
3372 /* Check if other direction is valid ... */
3373 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3376 /* Try reversing direction of operands. */
3377 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3378 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3379 if (!operand_type_match (overlap0, i.types[0])
3380 || !operand_type_match (overlap1, i.types[1])
3382 && !operand_type_register_match (overlap0,
3389 /* Does not match either direction. */
3392 /* found_reverse_match holds which of D or FloatDR
3394 if (t->opcode_modifier.d)
3395 found_reverse_match = Opcode_D;
3396 else if (t->opcode_modifier.floatd)
3397 found_reverse_match = Opcode_FloatD;
3399 found_reverse_match = 0;
3400 if (t->opcode_modifier.floatr)
3401 found_reverse_match |= Opcode_FloatR;
3405 /* Found a forward 2 operand match here. */
3406 switch (t->operands)
3409 overlap3 = operand_type_and (i.types[3],
3412 overlap2 = operand_type_and (i.types[2],
3417 switch (t->operands)
3420 if (!operand_type_match (overlap3, i.types[3])
3422 && !operand_type_register_match (overlap2,
3430 /* Here we make use of the fact that there are no
3431 reverse match 3 operand instructions, and all 3
3432 operand instructions only need to be checked for
3433 register consistency between operands 2 and 3. */
3434 if (!operand_type_match (overlap2, i.types[2])
3436 && !operand_type_register_match (overlap1,
3446 /* Found either forward/reverse 2, 3 or 4 operand match here:
3447 slip through to break. */
3449 if (!found_cpu_match)
3451 found_reverse_match = 0;
3454 /* We've found a match; break out of loop. */
3458 if (t == current_templates->end)
3460 /* We found no match. */
3461 as_bad (_("suffix or operands invalid for `%s'"),
3462 current_templates->start->name);
3466 if (!quiet_warnings)
3469 && (i.types[0].bitfield.jumpabsolute
3470 != operand_types[0].bitfield.jumpabsolute))
3472 as_warn (_("indirect %s without `*'"), t->name);
3475 if (t->opcode_modifier.isprefix
3476 && t->opcode_modifier.ignoresize)
3478 /* Warn them that a data or address size prefix doesn't
3479 affect assembly of the next line of code. */
3480 as_warn (_("stand-alone `%s' prefix"), t->name);
3484 /* Copy the template we found. */
3487 if (addr_prefix_disp != -1)
3488 i.tm.operand_types[addr_prefix_disp]
3489 = operand_types[addr_prefix_disp];
3491 if (found_reverse_match)
3493 /* If we found a reverse match we must alter the opcode
3494 direction bit. found_reverse_match holds bits to change
3495 (different for int & float insns). */
3497 i.tm.base_opcode ^= found_reverse_match;
3499 i.tm.operand_types[0] = operand_types[1];
3500 i.tm.operand_types[1] = operand_types[0];
3509 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3510 if (i.tm.operand_types[mem_op].bitfield.esseg)
3512 if (i.seg[0] != NULL && i.seg[0] != &es)
3514 as_bad (_("`%s' operand %d must use `%%es' segment"),
3519 /* There's only ever one segment override allowed per instruction.
3520 This instruction possibly has a legal segment override on the
3521 second operand, so copy the segment to where non-string
3522 instructions store it, allowing common code. */
3523 i.seg[0] = i.seg[1];
3525 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3527 if (i.seg[1] != NULL && i.seg[1] != &es)
3529 as_bad (_("`%s' operand %d must use `%%es' segment"),
3539 process_suffix (void)
3541 /* If matched instruction specifies an explicit instruction mnemonic
3543 if (i.tm.opcode_modifier.size16)
3544 i.suffix = WORD_MNEM_SUFFIX;
3545 else if (i.tm.opcode_modifier.size32)
3546 i.suffix = LONG_MNEM_SUFFIX;
3547 else if (i.tm.opcode_modifier.size64)
3548 i.suffix = QWORD_MNEM_SUFFIX;
3549 else if (i.reg_operands)
3551 /* If there's no instruction mnemonic suffix we try to invent one
3552 based on register operands. */
3555 /* We take i.suffix from the last register operand specified,
3556 Destination register type is more significant than source
3557 register type. crc32 in SSE4.2 prefers source register
3559 if (i.tm.base_opcode == 0xf20f38f1)
3561 if (i.types[0].bitfield.reg16)
3562 i.suffix = WORD_MNEM_SUFFIX;
3563 else if (i.types[0].bitfield.reg32)
3564 i.suffix = LONG_MNEM_SUFFIX;
3565 else if (i.types[0].bitfield.reg64)
3566 i.suffix = QWORD_MNEM_SUFFIX;
3568 else if (i.tm.base_opcode == 0xf20f38f0)
3570 if (i.types[0].bitfield.reg8)
3571 i.suffix = BYTE_MNEM_SUFFIX;
3578 if (i.tm.base_opcode == 0xf20f38f1
3579 || i.tm.base_opcode == 0xf20f38f0)
3581 /* We have to know the operand size for crc32. */
3582 as_bad (_("ambiguous memory operand size for `%s`"),
3587 for (op = i.operands; --op >= 0;)
3588 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3590 if (i.types[op].bitfield.reg8)
3592 i.suffix = BYTE_MNEM_SUFFIX;
3595 else if (i.types[op].bitfield.reg16)
3597 i.suffix = WORD_MNEM_SUFFIX;
3600 else if (i.types[op].bitfield.reg32)
3602 i.suffix = LONG_MNEM_SUFFIX;
3605 else if (i.types[op].bitfield.reg64)
3607 i.suffix = QWORD_MNEM_SUFFIX;
3613 else if (i.suffix == BYTE_MNEM_SUFFIX)
3615 if (!check_byte_reg ())
3618 else if (i.suffix == LONG_MNEM_SUFFIX)
3620 if (!check_long_reg ())
3623 else if (i.suffix == QWORD_MNEM_SUFFIX)
3626 && i.tm.opcode_modifier.ignoresize
3627 && i.tm.opcode_modifier.no_qsuf)
3629 else if (!check_qword_reg ())
3632 else if (i.suffix == WORD_MNEM_SUFFIX)
3634 if (!check_word_reg ())
3637 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3639 /* Skip if the instruction has x suffix. match_template
3640 should check if it is a valid suffix. */
3642 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3643 /* Do nothing if the instruction is going to ignore the prefix. */
3648 else if (i.tm.opcode_modifier.defaultsize
3650 /* exclude fldenv/frstor/fsave/fstenv */
3651 && i.tm.opcode_modifier.no_ssuf)
3653 i.suffix = stackop_size;
3655 else if (intel_syntax
3657 && (i.tm.operand_types[0].bitfield.jumpabsolute
3658 || i.tm.opcode_modifier.jumpbyte
3659 || i.tm.opcode_modifier.jumpintersegment
3660 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3661 && i.tm.extension_opcode <= 3)))
3666 if (!i.tm.opcode_modifier.no_qsuf)
3668 i.suffix = QWORD_MNEM_SUFFIX;
3672 if (!i.tm.opcode_modifier.no_lsuf)
3673 i.suffix = LONG_MNEM_SUFFIX;
3676 if (!i.tm.opcode_modifier.no_wsuf)
3677 i.suffix = WORD_MNEM_SUFFIX;
3686 if (i.tm.opcode_modifier.w)
3688 as_bad (_("no instruction mnemonic suffix given and "
3689 "no register operands; can't size instruction"));
3695 unsigned int suffixes;
3697 suffixes = !i.tm.opcode_modifier.no_bsuf;
3698 if (!i.tm.opcode_modifier.no_wsuf)
3700 if (!i.tm.opcode_modifier.no_lsuf)
3702 if (!i.tm.opcode_modifier.no_ldsuf)
3704 if (!i.tm.opcode_modifier.no_ssuf)
3706 if (!i.tm.opcode_modifier.no_qsuf)
3709 /* There are more than suffix matches. */
3710 if (i.tm.opcode_modifier.w
3711 || ((suffixes & (suffixes - 1))
3712 && !i.tm.opcode_modifier.defaultsize
3713 && !i.tm.opcode_modifier.ignoresize))
3715 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3721 /* Change the opcode based on the operand size given by i.suffix;
3722 We don't need to change things for byte insns. */
3725 && i.suffix != BYTE_MNEM_SUFFIX
3726 && i.suffix != XMMWORD_MNEM_SUFFIX)
3728 /* It's not a byte, select word/dword operation. */
3729 if (i.tm.opcode_modifier.w)
3731 if (i.tm.opcode_modifier.shortform)
3732 i.tm.base_opcode |= 8;
3734 i.tm.base_opcode |= 1;
3737 /* Now select between word & dword operations via the operand
3738 size prefix, except for instructions that will ignore this
3740 if (i.tm.opcode_modifier.addrprefixop0)
3742 /* The address size override prefix changes the size of the
3744 if ((flag_code == CODE_32BIT
3745 && i.op->regs[0].reg_type.bitfield.reg16)
3746 || (flag_code != CODE_32BIT
3747 && i.op->regs[0].reg_type.bitfield.reg32))
3748 if (!add_prefix (ADDR_PREFIX_OPCODE))
3751 else if (i.suffix != QWORD_MNEM_SUFFIX
3752 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3753 && !i.tm.opcode_modifier.ignoresize
3754 && !i.tm.opcode_modifier.floatmf
3755 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3756 || (flag_code == CODE_64BIT
3757 && i.tm.opcode_modifier.jumpbyte)))
3759 unsigned int prefix = DATA_PREFIX_OPCODE;
3761 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3762 prefix = ADDR_PREFIX_OPCODE;
3764 if (!add_prefix (prefix))
3768 /* Set mode64 for an operand. */
3769 if (i.suffix == QWORD_MNEM_SUFFIX
3770 && flag_code == CODE_64BIT
3771 && !i.tm.opcode_modifier.norex64)
3773 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3774 need rex64. cmpxchg8b is also a special case. */
3775 if (! (i.operands == 2
3776 && i.tm.base_opcode == 0x90
3777 && i.tm.extension_opcode == None
3778 && UINTS_EQUAL (i.types [0], acc64)
3779 && UINTS_EQUAL (i.types [1], acc64))
3780 && ! (i.operands == 1
3781 && i.tm.base_opcode == 0xfc7
3782 && i.tm.extension_opcode == 1
3783 && !operand_type_check (i.types [0], reg)
3784 && operand_type_check (i.types [0], anymem)))
3788 /* Size floating point instruction. */
3789 if (i.suffix == LONG_MNEM_SUFFIX)
3790 if (i.tm.opcode_modifier.floatmf)
3791 i.tm.base_opcode ^= 4;
3798 check_byte_reg (void)
3802 for (op = i.operands; --op >= 0;)
3804 /* If this is an eight bit register, it's OK. If it's the 16 or
3805 32 bit version of an eight bit register, we will just use the
3806 low portion, and that's OK too. */
3807 if (i.types[op].bitfield.reg8)
3810 /* Don't generate this warning if not needed. */
3811 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3814 /* crc32 doesn't generate this warning. */
3815 if (i.tm.base_opcode == 0xf20f38f0)
3818 if ((i.types[op].bitfield.reg16
3819 || i.types[op].bitfield.reg32
3820 || i.types[op].bitfield.reg64)
3821 && i.op[op].regs->reg_num < 4)
3823 /* Prohibit these changes in the 64bit mode, since the
3824 lowering is more complicated. */
3825 if (flag_code == CODE_64BIT
3826 && !i.tm.operand_types[op].bitfield.inoutportreg)
3828 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3829 register_prefix, i.op[op].regs->reg_name,
3833 #if REGISTER_WARNINGS
3835 && !i.tm.operand_types[op].bitfield.inoutportreg)
3836 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3838 (i.op[op].regs + (i.types[op].bitfield.reg16
3839 ? REGNAM_AL - REGNAM_AX
3840 : REGNAM_AL - REGNAM_EAX))->reg_name,
3842 i.op[op].regs->reg_name,
3847 /* Any other register is bad. */
3848 if (i.types[op].bitfield.reg16
3849 || i.types[op].bitfield.reg32
3850 || i.types[op].bitfield.reg64
3851 || i.types[op].bitfield.regmmx
3852 || i.types[op].bitfield.regxmm
3853 || i.types[op].bitfield.sreg2
3854 || i.types[op].bitfield.sreg3
3855 || i.types[op].bitfield.control
3856 || i.types[op].bitfield.debug
3857 || i.types[op].bitfield.test
3858 || i.types[op].bitfield.floatreg
3859 || i.types[op].bitfield.floatacc)
3861 as_bad (_("`%s%s' not allowed with `%s%c'"),
3863 i.op[op].regs->reg_name,
3873 check_long_reg (void)
3877 for (op = i.operands; --op >= 0;)
3878 /* Reject eight bit registers, except where the template requires
3879 them. (eg. movzb) */
3880 if (i.types[op].bitfield.reg8
3881 && (i.tm.operand_types[op].bitfield.reg16
3882 || i.tm.operand_types[op].bitfield.reg32
3883 || i.tm.operand_types[op].bitfield.acc))
3885 as_bad (_("`%s%s' not allowed with `%s%c'"),
3887 i.op[op].regs->reg_name,
3892 /* Warn if the e prefix on a general reg is missing. */
3893 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3894 && i.types[op].bitfield.reg16
3895 && (i.tm.operand_types[op].bitfield.reg32
3896 || i.tm.operand_types[op].bitfield.acc))
3898 /* Prohibit these changes in the 64bit mode, since the
3899 lowering is more complicated. */
3900 if (flag_code == CODE_64BIT)
3902 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3903 register_prefix, i.op[op].regs->reg_name,
3907 #if REGISTER_WARNINGS
3909 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3911 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3913 i.op[op].regs->reg_name,
3917 /* Warn if the r prefix on a general reg is missing. */
3918 else if (i.types[op].bitfield.reg64
3919 && (i.tm.operand_types[op].bitfield.reg32
3920 || i.tm.operand_types[op].bitfield.acc))
3923 && i.tm.opcode_modifier.toqword
3924 && !i.types[0].bitfield.regxmm)
3926 /* Convert to QWORD. We want REX byte. */
3927 i.suffix = QWORD_MNEM_SUFFIX;
3931 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3932 register_prefix, i.op[op].regs->reg_name,
3941 check_qword_reg (void)
3945 for (op = i.operands; --op >= 0; )
3946 /* Reject eight bit registers, except where the template requires
3947 them. (eg. movzb) */
3948 if (i.types[op].bitfield.reg8
3949 && (i.tm.operand_types[op].bitfield.reg16
3950 || i.tm.operand_types[op].bitfield.reg32
3951 || i.tm.operand_types[op].bitfield.acc))
3953 as_bad (_("`%s%s' not allowed with `%s%c'"),
3955 i.op[op].regs->reg_name,
3960 /* Warn if the e prefix on a general reg is missing. */
3961 else if ((i.types[op].bitfield.reg16
3962 || i.types[op].bitfield.reg32)
3963 && (i.tm.operand_types[op].bitfield.reg32
3964 || i.tm.operand_types[op].bitfield.acc))
3966 /* Prohibit these changes in the 64bit mode, since the
3967 lowering is more complicated. */
3969 && i.tm.opcode_modifier.todword
3970 && !i.types[0].bitfield.regxmm)
3972 /* Convert to DWORD. We don't want REX byte. */
3973 i.suffix = LONG_MNEM_SUFFIX;
3977 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3978 register_prefix, i.op[op].regs->reg_name,
3987 check_word_reg (void)
3990 for (op = i.operands; --op >= 0;)
3991 /* Reject eight bit registers, except where the template requires
3992 them. (eg. movzb) */
3993 if (i.types[op].bitfield.reg8
3994 && (i.tm.operand_types[op].bitfield.reg16
3995 || i.tm.operand_types[op].bitfield.reg32
3996 || i.tm.operand_types[op].bitfield.acc))
3998 as_bad (_("`%s%s' not allowed with `%s%c'"),
4000 i.op[op].regs->reg_name,
4005 /* Warn if the e prefix on a general reg is present. */
4006 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4007 && i.types[op].bitfield.reg32
4008 && (i.tm.operand_types[op].bitfield.reg16
4009 || i.tm.operand_types[op].bitfield.acc))
4011 /* Prohibit these changes in the 64bit mode, since the
4012 lowering is more complicated. */
4013 if (flag_code == CODE_64BIT)
4015 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4016 register_prefix, i.op[op].regs->reg_name,
4021 #if REGISTER_WARNINGS
4022 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4024 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4026 i.op[op].regs->reg_name,
4034 update_imm (unsigned int j)
4036 i386_operand_type overlap;
4038 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4039 if ((overlap.bitfield.imm8
4040 || overlap.bitfield.imm8s
4041 || overlap.bitfield.imm16
4042 || overlap.bitfield.imm32
4043 || overlap.bitfield.imm32s
4044 || overlap.bitfield.imm64)
4045 && !UINTS_EQUAL (overlap, imm8)
4046 && !UINTS_EQUAL (overlap, imm8s)
4047 && !UINTS_EQUAL (overlap, imm16)
4048 && !UINTS_EQUAL (overlap, imm32)
4049 && !UINTS_EQUAL (overlap, imm32s)
4050 && !UINTS_EQUAL (overlap, imm64))
4054 i386_operand_type temp;
4057 if (i.suffix == BYTE_MNEM_SUFFIX)
4059 temp.bitfield.imm8 = overlap.bitfield.imm8;
4060 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4062 else if (i.suffix == WORD_MNEM_SUFFIX)
4063 temp.bitfield.imm16 = overlap.bitfield.imm16;
4064 else if (i.suffix == QWORD_MNEM_SUFFIX)
4066 temp.bitfield.imm64 = overlap.bitfield.imm64;
4067 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4070 temp.bitfield.imm32 = overlap.bitfield.imm32;
4073 else if (UINTS_EQUAL (overlap, imm16_32_32s)
4074 || UINTS_EQUAL (overlap, imm16_32)
4075 || UINTS_EQUAL (overlap, imm16_32s))
4077 UINTS_CLEAR (overlap);
4078 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4079 overlap.bitfield.imm16 = 1;
4081 overlap.bitfield.imm32s = 1;
4083 if (!UINTS_EQUAL (overlap, imm8)
4084 && !UINTS_EQUAL (overlap, imm8s)
4085 && !UINTS_EQUAL (overlap, imm16)
4086 && !UINTS_EQUAL (overlap, imm32)
4087 && !UINTS_EQUAL (overlap, imm32s)
4088 && !UINTS_EQUAL (overlap, imm64))
4090 as_bad (_("no instruction mnemonic suffix given; "
4091 "can't determine immediate size"));
4095 i.types[j] = overlap;
4105 for (j = 0; j < 2; j++)
4106 if (update_imm (j) == 0)
4109 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4110 assert (operand_type_check (i.types[2], imm) == 0);
4118 i.drex.modrm_reg = 0;
4119 i.drex.modrm_regmem = 0;
4121 /* SSE5 4 operand instructions must have the destination the same as
4122 one of the inputs. Figure out the destination register and cache
4123 it away in the drex field, and remember which fields to use for
4125 if (i.tm.opcode_modifier.drex
4126 && i.tm.opcode_modifier.drexv
4129 i.tm.extension_opcode = None;
4131 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4132 if (i.types[0].bitfield.regxmm != 0
4133 && i.types[1].bitfield.regxmm != 0
4134 && i.types[2].bitfield.regxmm != 0
4135 && i.types[3].bitfield.regxmm != 0
4136 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4137 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4139 /* Clear the arguments that are stored in drex. */
4140 UINTS_CLEAR (i.types[0]);
4141 UINTS_CLEAR (i.types[3]);
4142 i.reg_operands -= 2;
4144 /* There are two different ways to encode a 4 operand
4145 instruction with all registers that uses OC1 set to
4146 0 or 1. Favor setting OC1 to 0 since this mimics the
4147 actions of other SSE5 assemblers. Use modrm encoding 2
4148 for register/register. Include the high order bit that
4149 is normally stored in the REX byte in the register
4151 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4152 i.drex.modrm_reg = 2;
4153 i.drex.modrm_regmem = 1;
4154 i.drex.reg = (i.op[3].regs->reg_num
4155 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4158 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4159 else if (i.types[0].bitfield.regxmm != 0
4160 && i.types[1].bitfield.regxmm != 0
4161 && (i.types[2].bitfield.regxmm
4162 || operand_type_check (i.types[2], anymem))
4163 && i.types[3].bitfield.regxmm != 0
4164 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4165 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4167 /* clear the arguments that are stored in drex */
4168 UINTS_CLEAR (i.types[0]);
4169 UINTS_CLEAR (i.types[3]);
4170 i.reg_operands -= 2;
4172 /* Specify the modrm encoding for memory addressing. Include
4173 the high order bit that is normally stored in the REX byte
4174 in the register field. */
4175 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4176 i.drex.modrm_reg = 1;
4177 i.drex.modrm_regmem = 2;
4178 i.drex.reg = (i.op[3].regs->reg_num
4179 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4182 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4183 else if (i.types[0].bitfield.regxmm != 0
4184 && operand_type_check (i.types[1], anymem) != 0
4185 && i.types[2].bitfield.regxmm != 0
4186 && i.types[3].bitfield.regxmm != 0
4187 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4188 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4190 /* Clear the arguments that are stored in drex. */
4191 UINTS_CLEAR (i.types[0]);
4192 UINTS_CLEAR (i.types[3]);
4193 i.reg_operands -= 2;
4195 /* Specify the modrm encoding for memory addressing. Include
4196 the high order bit that is normally stored in the REX byte
4197 in the register field. */
4198 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4199 i.drex.modrm_reg = 2;
4200 i.drex.modrm_regmem = 1;
4201 i.drex.reg = (i.op[3].regs->reg_num
4202 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4205 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4206 else if (i.types[0].bitfield.regxmm != 0
4207 && i.types[1].bitfield.regxmm != 0
4208 && i.types[2].bitfield.regxmm != 0
4209 && i.types[3].bitfield.regxmm != 0
4210 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4211 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4213 /* clear the arguments that are stored in drex */
4214 UINTS_CLEAR (i.types[2]);
4215 UINTS_CLEAR (i.types[3]);
4216 i.reg_operands -= 2;
4218 /* There are two different ways to encode a 4 operand
4219 instruction with all registers that uses OC1 set to
4220 0 or 1. Favor setting OC1 to 0 since this mimics the
4221 actions of other SSE5 assemblers. Use modrm encoding
4222 2 for register/register. Include the high order bit that
4223 is normally stored in the REX byte in the register
4225 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4226 i.drex.modrm_reg = 1;
4227 i.drex.modrm_regmem = 0;
4229 /* Remember the register, including the upper bits */
4230 i.drex.reg = (i.op[3].regs->reg_num
4231 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4234 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4235 else if (i.types[0].bitfield.regxmm != 0
4236 && (i.types[1].bitfield.regxmm
4237 || operand_type_check (i.types[1], anymem))
4238 && i.types[2].bitfield.regxmm != 0
4239 && i.types[3].bitfield.regxmm != 0
4240 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4241 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4243 /* Clear the arguments that are stored in drex. */
4244 UINTS_CLEAR (i.types[2]);
4245 UINTS_CLEAR (i.types[3]);
4246 i.reg_operands -= 2;
4248 /* Specify the modrm encoding and remember the register
4249 including the bits normally stored in the REX byte. */
4250 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4251 i.drex.modrm_reg = 0;
4252 i.drex.modrm_regmem = 1;
4253 i.drex.reg = (i.op[3].regs->reg_num
4254 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4257 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4258 else if (operand_type_check (i.types[0], anymem) != 0
4259 && i.types[1].bitfield.regxmm != 0
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0
4262 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4263 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4265 /* clear the arguments that are stored in drex */
4266 UINTS_CLEAR (i.types[2]);
4267 UINTS_CLEAR (i.types[3]);
4268 i.reg_operands -= 2;
4270 /* Specify the modrm encoding and remember the register
4271 including the bits normally stored in the REX byte. */
4272 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4273 i.drex.modrm_reg = 1;
4274 i.drex.modrm_regmem = 0;
4275 i.drex.reg = (i.op[3].regs->reg_num
4276 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4280 as_bad (_("Incorrect operands for the '%s' instruction"),
4284 /* SSE5 instructions with the DREX byte where the only memory operand
4285 is in the 2nd argument, and the first and last xmm register must
4286 match, and is encoded in the DREX byte. */
4287 else if (i.tm.opcode_modifier.drex
4288 && !i.tm.opcode_modifier.drexv
4291 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4292 if (i.types[0].bitfield.regxmm != 0
4293 && (i.types[1].bitfield.regxmm
4294 || operand_type_check(i.types[1], anymem))
4295 && i.types[2].bitfield.regxmm != 0
4296 && i.types[3].bitfield.regxmm != 0
4297 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4298 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4300 /* clear the arguments that are stored in drex */
4301 UINTS_CLEAR (i.types[0]);
4302 UINTS_CLEAR (i.types[3]);
4303 i.reg_operands -= 2;
4305 /* Specify the modrm encoding and remember the register
4306 including the high bit normally stored in the REX
4308 i.drex.modrm_reg = 2;
4309 i.drex.modrm_regmem = 1;
4310 i.drex.reg = (i.op[3].regs->reg_num
4311 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4315 as_bad (_("Incorrect operands for the '%s' instruction"),
4319 /* SSE5 3 operand instructions that the result is a register, being
4320 either operand can be a memory operand, using OC0 to note which
4321 one is the memory. */
4322 else if (i.tm.opcode_modifier.drex
4323 && i.tm.opcode_modifier.drexv
4326 i.tm.extension_opcode = None;
4328 /* Case 1: 3 operand insn, src1 = register. */
4329 if (i.types[0].bitfield.regxmm != 0
4330 && i.types[1].bitfield.regxmm != 0
4331 && i.types[2].bitfield.regxmm != 0)
4333 /* Clear the arguments that are stored in drex. */
4334 UINTS_CLEAR (i.types[2]);
4337 /* Specify the modrm encoding and remember the register
4338 including the high bit normally stored in the REX byte. */
4339 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4340 i.drex.modrm_reg = 1;
4341 i.drex.modrm_regmem = 0;
4342 i.drex.reg = (i.op[2].regs->reg_num
4343 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4346 /* Case 2: 3 operand insn, src1 = memory. */
4347 else if (operand_type_check (i.types[0], anymem) != 0
4348 && i.types[1].bitfield.regxmm != 0
4349 && i.types[2].bitfield.regxmm != 0)
4351 /* Clear the arguments that are stored in drex. */
4352 UINTS_CLEAR (i.types[2]);
4355 /* Specify the modrm encoding and remember the register
4356 including the high bit normally stored in the REX
4358 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4359 i.drex.modrm_reg = 1;
4360 i.drex.modrm_regmem = 0;
4361 i.drex.reg = (i.op[2].regs->reg_num
4362 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4365 /* Case 3: 3 operand insn, src2 = memory. */
4366 else if (i.types[0].bitfield.regxmm != 0
4367 && operand_type_check (i.types[1], anymem) != 0
4368 && i.types[2].bitfield.regxmm != 0)
4370 /* Clear the arguments that are stored in drex. */
4371 UINTS_CLEAR (i.types[2]);
4374 /* Specify the modrm encoding and remember the register
4375 including the high bit normally stored in the REX byte. */
4376 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4377 i.drex.modrm_reg = 0;
4378 i.drex.modrm_regmem = 1;
4379 i.drex.reg = (i.op[2].regs->reg_num
4380 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4384 as_bad (_("Incorrect operands for the '%s' instruction"),
4388 /* SSE5 4 operand instructions that are the comparison instructions
4389 where the first operand is the immediate value of the comparison
4391 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4393 /* Case 1: 4 operand insn, src1 = reg/memory. */
4394 if (operand_type_check (i.types[0], imm) != 0
4395 && (i.types[1].bitfield.regxmm
4396 || operand_type_check (i.types[1], anymem))
4397 && i.types[2].bitfield.regxmm != 0
4398 && i.types[3].bitfield.regxmm != 0)
4400 /* clear the arguments that are stored in drex */
4401 UINTS_CLEAR (i.types[3]);
4404 /* Specify the modrm encoding and remember the register
4405 including the high bit normally stored in the REX byte. */
4406 i.drex.modrm_reg = 2;
4407 i.drex.modrm_regmem = 1;
4408 i.drex.reg = (i.op[3].regs->reg_num
4409 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4412 /* Case 2: 3 operand insn with ImmExt that places the
4413 opcode_extension as an immediate argument. This is used for
4414 all of the varients of comparison that supplies the appropriate
4415 value as part of the instruction. */
4416 else if ((i.types[0].bitfield.regxmm
4417 || operand_type_check (i.types[0], anymem))
4418 && i.types[1].bitfield.regxmm != 0
4419 && i.types[2].bitfield.regxmm != 0
4420 && operand_type_check (i.types[3], imm) != 0)
4422 /* clear the arguments that are stored in drex */
4423 UINTS_CLEAR (i.types[2]);
4426 /* Specify the modrm encoding and remember the register
4427 including the high bit normally stored in the REX byte. */
4428 i.drex.modrm_reg = 1;
4429 i.drex.modrm_regmem = 0;
4430 i.drex.reg = (i.op[2].regs->reg_num
4431 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4435 as_bad (_("Incorrect operands for the '%s' instruction"),
4439 else if (i.tm.opcode_modifier.drex
4440 || i.tm.opcode_modifier.drexv
4441 || i.tm.opcode_modifier.drexc)
4442 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4446 process_operands (void)
4448 /* Default segment register this instruction will use for memory
4449 accesses. 0 means unknown. This is only for optimizing out
4450 unnecessary segment overrides. */
4451 const seg_entry *default_seg = 0;
4453 /* Handle all of the DREX munging that SSE5 needs. */
4454 if (i.tm.opcode_modifier.drex
4455 || i.tm.opcode_modifier.drexv
4456 || i.tm.opcode_modifier.drexc)
4459 if (i.tm.opcode_modifier.firstxmm0)
4463 /* The first operand is implicit and must be xmm0. */
4464 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4465 if (i.op[0].regs->reg_num != 0)
4468 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4469 i.tm.name, register_prefix);
4471 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4472 i.tm.name, register_prefix);
4476 for (j = 1; j < i.operands; j++)
4478 i.op[j - 1] = i.op[j];
4479 i.types[j - 1] = i.types[j];
4481 /* We need to adjust fields in i.tm since they are used by
4482 build_modrm_byte. */
4483 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4490 else if (i.tm.opcode_modifier.regkludge)
4492 /* The imul $imm, %reg instruction is converted into
4493 imul $imm, %reg, %reg, and the clr %reg instruction
4494 is converted into xor %reg, %reg. */
4496 unsigned int first_reg_op;
4498 if (operand_type_check (i.types[0], reg))
4502 /* Pretend we saw the extra register operand. */
4503 assert (i.reg_operands == 1
4504 && i.op[first_reg_op + 1].regs == 0);
4505 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4506 i.types[first_reg_op + 1] = i.types[first_reg_op];
4511 if (i.tm.opcode_modifier.shortform)
4513 if (i.types[0].bitfield.sreg2
4514 || i.types[0].bitfield.sreg3)
4516 if (i.tm.base_opcode == POP_SEG_SHORT
4517 && i.op[0].regs->reg_num == 1)
4519 as_bad (_("you can't `pop %%cs'"));
4522 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4523 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4528 /* The register or float register operand is in operand
4532 if (i.types[0].bitfield.floatreg
4533 || operand_type_check (i.types[0], reg))
4537 /* Register goes in low 3 bits of opcode. */
4538 i.tm.base_opcode |= i.op[op].regs->reg_num;
4539 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4541 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4543 /* Warn about some common errors, but press on regardless.
4544 The first case can be generated by gcc (<= 2.8.1). */
4545 if (i.operands == 2)
4547 /* Reversed arguments on faddp, fsubp, etc. */
4548 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4549 register_prefix, i.op[1].regs->reg_name,
4550 register_prefix, i.op[0].regs->reg_name);
4554 /* Extraneous `l' suffix on fp insn. */
4555 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4556 register_prefix, i.op[0].regs->reg_name);
4561 else if (i.tm.opcode_modifier.modrm)
4563 /* The opcode is completed (modulo i.tm.extension_opcode which
4564 must be put into the modrm byte). Now, we make the modrm and
4565 index base bytes based on all the info we've collected. */
4567 default_seg = build_modrm_byte ();
4569 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4573 else if (i.tm.opcode_modifier.isstring)
4575 /* For the string instructions that allow a segment override
4576 on one of their operands, the default segment is ds. */
4580 if (i.tm.base_opcode == 0x8d /* lea */
4583 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4585 /* If a segment was explicitly specified, and the specified segment
4586 is not the default, use an opcode prefix to select it. If we
4587 never figured out what the default segment is, then default_seg
4588 will be zero at this point, and the specified segment prefix will
4590 if ((i.seg[0]) && (i.seg[0] != default_seg))
4592 if (!add_prefix (i.seg[0]->seg_prefix))
4598 static const seg_entry *
4599 build_modrm_byte (void)
4601 const seg_entry *default_seg = 0;
4603 /* SSE5 4 operand instructions are encoded in such a way that one of
4604 the inputs must match the destination register. Process_drex hides
4605 the 3rd argument in the drex field, so that by the time we get
4606 here, it looks to GAS as if this is a 2 operand instruction. */
4607 if ((i.tm.opcode_modifier.drex
4608 || i.tm.opcode_modifier.drexv
4609 || i.tm.opcode_modifier.drexc)
4610 && i.reg_operands == 2)
4612 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4613 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4615 i.rm.reg = reg->reg_num;
4616 i.rm.regmem = regmem->reg_num;
4618 if ((reg->reg_flags & RegRex) != 0)
4620 if ((regmem->reg_flags & RegRex) != 0)
4624 /* i.reg_operands MUST be the number of real register operands;
4625 implicit registers do not count. */
4626 else if (i.reg_operands == 2)
4628 unsigned int source, dest;
4636 /* When there are 3 operands, one of them may be immediate,
4637 which may be the first or the last operand. Otherwise,
4638 the first operand must be shift count register (cl). */
4639 assert (i.imm_operands == 1
4640 || (i.imm_operands == 0
4641 && i.types[0].bitfield.shiftcount));
4642 if (operand_type_check (i.types[0], imm)
4643 || i.types[0].bitfield.shiftcount)
4649 /* When there are 4 operands, the first two must be 8bit
4650 immediate operands. The source operand will be the 3rd
4652 assert (i.imm_operands == 2
4653 && i.types[0].bitfield.imm8
4654 && i.types[1].bitfield.imm8);
4664 /* One of the register operands will be encoded in the i.tm.reg
4665 field, the other in the combined i.tm.mode and i.tm.regmem
4666 fields. If no form of this instruction supports a memory
4667 destination operand, then we assume the source operand may
4668 sometimes be a memory operand and so we need to store the
4669 destination in the i.rm.reg field. */
4670 if (!i.tm.operand_types[dest].bitfield.regmem
4671 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4673 i.rm.reg = i.op[dest].regs->reg_num;
4674 i.rm.regmem = i.op[source].regs->reg_num;
4675 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4677 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4682 i.rm.reg = i.op[source].regs->reg_num;
4683 i.rm.regmem = i.op[dest].regs->reg_num;
4684 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4686 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4689 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4691 if (!i.types[0].bitfield.control
4692 && !i.types[1].bitfield.control)
4694 i.rex &= ~(REX_R | REX_B);
4695 add_prefix (LOCK_PREFIX_OPCODE);
4699 { /* If it's not 2 reg operands... */
4702 unsigned int fake_zero_displacement = 0;
4705 /* This has been precalculated for SSE5 instructions
4706 that have a DREX field earlier in process_drex. */
4707 if (i.tm.opcode_modifier.drex
4708 || i.tm.opcode_modifier.drexv
4709 || i.tm.opcode_modifier.drexc)
4710 op = i.drex.modrm_regmem;
4713 for (op = 0; op < i.operands; op++)
4714 if (operand_type_check (i.types[op], anymem))
4716 assert (op < i.operands);
4721 if (i.base_reg == 0)
4724 if (!i.disp_operands)
4725 fake_zero_displacement = 1;
4726 if (i.index_reg == 0)
4728 /* Operand is just <disp> */
4729 if (flag_code == CODE_64BIT)
4731 /* 64bit mode overwrites the 32bit absolute
4732 addressing by RIP relative addressing and
4733 absolute addressing is encoded by one of the
4734 redundant SIB forms. */
4735 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4736 i.sib.base = NO_BASE_REGISTER;
4737 i.sib.index = NO_INDEX_REGISTER;
4738 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4739 ? disp32s : disp32);
4741 else if ((flag_code == CODE_16BIT)
4742 ^ (i.prefix[ADDR_PREFIX] != 0))
4744 i.rm.regmem = NO_BASE_REGISTER_16;
4745 i.types[op] = disp16;
4749 i.rm.regmem = NO_BASE_REGISTER;
4750 i.types[op] = disp32;
4753 else /* !i.base_reg && i.index_reg */
4755 if (i.index_reg->reg_num == RegEiz
4756 || i.index_reg->reg_num == RegRiz)
4757 i.sib.index = NO_INDEX_REGISTER;
4759 i.sib.index = i.index_reg->reg_num;
4760 i.sib.base = NO_BASE_REGISTER;
4761 i.sib.scale = i.log2_scale_factor;
4762 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4763 i.types[op].bitfield.disp8 = 0;
4764 i.types[op].bitfield.disp16 = 0;
4765 i.types[op].bitfield.disp64 = 0;
4766 if (flag_code != CODE_64BIT)
4768 /* Must be 32 bit */
4769 i.types[op].bitfield.disp32 = 1;
4770 i.types[op].bitfield.disp32s = 0;
4774 i.types[op].bitfield.disp32 = 0;
4775 i.types[op].bitfield.disp32s = 1;
4777 if ((i.index_reg->reg_flags & RegRex) != 0)
4781 /* RIP addressing for 64bit mode. */
4782 else if (i.base_reg->reg_num == RegRip ||
4783 i.base_reg->reg_num == RegEip)
4785 i.rm.regmem = NO_BASE_REGISTER;
4786 i.types[op].bitfield.disp8 = 0;
4787 i.types[op].bitfield.disp16 = 0;
4788 i.types[op].bitfield.disp32 = 0;
4789 i.types[op].bitfield.disp32s = 1;
4790 i.types[op].bitfield.disp64 = 0;
4791 i.flags[op] |= Operand_PCrel;
4792 if (! i.disp_operands)
4793 fake_zero_displacement = 1;
4795 else if (i.base_reg->reg_type.bitfield.reg16)
4797 switch (i.base_reg->reg_num)
4800 if (i.index_reg == 0)
4802 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4803 i.rm.regmem = i.index_reg->reg_num - 6;
4807 if (i.index_reg == 0)
4810 if (operand_type_check (i.types[op], disp) == 0)
4812 /* fake (%bp) into 0(%bp) */
4813 i.types[op].bitfield.disp8 = 1;
4814 fake_zero_displacement = 1;
4817 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4818 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4820 default: /* (%si) -> 4 or (%di) -> 5 */
4821 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4823 i.rm.mode = mode_from_disp_size (i.types[op]);
4825 else /* i.base_reg and 32/64 bit mode */
4827 if (flag_code == CODE_64BIT
4828 && operand_type_check (i.types[op], disp))
4830 i386_operand_type temp;
4832 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4834 if (i.prefix[ADDR_PREFIX] == 0)
4835 i.types[op].bitfield.disp32s = 1;
4837 i.types[op].bitfield.disp32 = 1;
4840 i.rm.regmem = i.base_reg->reg_num;
4841 if ((i.base_reg->reg_flags & RegRex) != 0)
4843 i.sib.base = i.base_reg->reg_num;
4844 /* x86-64 ignores REX prefix bit here to avoid decoder
4846 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4849 if (i.disp_operands == 0)
4851 fake_zero_displacement = 1;
4852 i.types[op].bitfield.disp8 = 1;
4855 else if (i.base_reg->reg_num == ESP_REG_NUM)
4859 i.sib.scale = i.log2_scale_factor;
4860 if (i.index_reg == 0)
4862 /* <disp>(%esp) becomes two byte modrm with no index
4863 register. We've already stored the code for esp
4864 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4865 Any base register besides %esp will not use the
4866 extra modrm byte. */
4867 i.sib.index = NO_INDEX_REGISTER;
4871 if (i.index_reg->reg_num == RegEiz
4872 || i.index_reg->reg_num == RegRiz)
4873 i.sib.index = NO_INDEX_REGISTER;
4875 i.sib.index = i.index_reg->reg_num;
4876 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4877 if ((i.index_reg->reg_flags & RegRex) != 0)
4882 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4883 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4886 i.rm.mode = mode_from_disp_size (i.types[op]);
4889 if (fake_zero_displacement)
4891 /* Fakes a zero displacement assuming that i.types[op]
4892 holds the correct displacement size. */
4895 assert (i.op[op].disps == 0);
4896 exp = &disp_expressions[i.disp_operands++];
4897 i.op[op].disps = exp;
4898 exp->X_op = O_constant;
4899 exp->X_add_number = 0;
4900 exp->X_add_symbol = (symbolS *) 0;
4901 exp->X_op_symbol = (symbolS *) 0;
4905 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4906 (if any) based on i.tm.extension_opcode. Again, we must be
4907 careful to make sure that segment/control/debug/test/MMX
4908 registers are coded into the i.rm.reg field. */
4913 /* This has been precalculated for SSE5 instructions
4914 that have a DREX field earlier in process_drex. */
4915 if (i.tm.opcode_modifier.drex
4916 || i.tm.opcode_modifier.drexv
4917 || i.tm.opcode_modifier.drexc)
4919 op = i.drex.modrm_reg;
4920 i.rm.reg = i.op[op].regs->reg_num;
4921 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4926 for (op = 0; op < i.operands; op++)
4927 if (i.types[op].bitfield.reg8
4928 || i.types[op].bitfield.reg16
4929 || i.types[op].bitfield.reg32
4930 || i.types[op].bitfield.reg64
4931 || i.types[op].bitfield.regmmx
4932 || i.types[op].bitfield.regxmm
4933 || i.types[op].bitfield.sreg2
4934 || i.types[op].bitfield.sreg3
4935 || i.types[op].bitfield.control
4936 || i.types[op].bitfield.debug
4937 || i.types[op].bitfield.test)
4940 assert (op < i.operands);
4942 /* If there is an extension opcode to put here, the
4943 register number must be put into the regmem field. */
4944 if (i.tm.extension_opcode != None)
4946 i.rm.regmem = i.op[op].regs->reg_num;
4947 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4952 i.rm.reg = i.op[op].regs->reg_num;
4953 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4958 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4959 must set it to 3 to indicate this is a register operand
4960 in the regmem field. */
4961 if (!i.mem_operands)
4965 /* Fill in i.rm.reg field with extension opcode (if any). */
4966 if (i.tm.extension_opcode != None
4967 && !(i.tm.opcode_modifier.drex
4968 || i.tm.opcode_modifier.drexv
4969 || i.tm.opcode_modifier.drexc))
4970 i.rm.reg = i.tm.extension_opcode;
4976 output_branch (void)
4981 relax_substateT subtype;
4986 if (flag_code == CODE_16BIT)
4990 if (i.prefix[DATA_PREFIX] != 0)
4996 /* Pentium4 branch hints. */
4997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5003 if (i.prefix[REX_PREFIX] != 0)
5009 if (i.prefixes != 0 && !intel_syntax)
5010 as_warn (_("skipping prefixes on this instruction"));
5012 /* It's always a symbol; End frag & setup for relax.
5013 Make sure there is enough room in this frag for the largest
5014 instruction we may generate in md_convert_frag. This is 2
5015 bytes for the opcode and room for the prefix and largest
5017 frag_grow (prefix + 2 + 4);
5018 /* Prefix and 1 opcode byte go in fr_fix. */
5019 p = frag_more (prefix + 1);
5020 if (i.prefix[DATA_PREFIX] != 0)
5021 *p++ = DATA_PREFIX_OPCODE;
5022 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5023 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5024 *p++ = i.prefix[SEG_PREFIX];
5025 if (i.prefix[REX_PREFIX] != 0)
5026 *p++ = i.prefix[REX_PREFIX];
5027 *p = i.tm.base_opcode;
5029 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5030 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5031 else if (cpu_arch_flags.bitfield.cpui386)
5032 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5034 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5037 sym = i.op[0].disps->X_add_symbol;
5038 off = i.op[0].disps->X_add_number;
5040 if (i.op[0].disps->X_op != O_constant
5041 && i.op[0].disps->X_op != O_symbol)
5043 /* Handle complex expressions. */
5044 sym = make_expr_symbol (i.op[0].disps);
5048 /* 1 possible extra opcode + 4 byte displacement go in var part.
5049 Pass reloc in fr_var. */
5050 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5060 if (i.tm.opcode_modifier.jumpbyte)
5062 /* This is a loop or jecxz type instruction. */
5064 if (i.prefix[ADDR_PREFIX] != 0)
5066 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5069 /* Pentium4 branch hints. */
5070 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5071 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5073 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5082 if (flag_code == CODE_16BIT)
5085 if (i.prefix[DATA_PREFIX] != 0)
5087 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5097 if (i.prefix[REX_PREFIX] != 0)
5099 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5103 if (i.prefixes != 0 && !intel_syntax)
5104 as_warn (_("skipping prefixes on this instruction"));
5106 p = frag_more (1 + size);
5107 *p++ = i.tm.base_opcode;
5109 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5110 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5112 /* All jumps handled here are signed, but don't use a signed limit
5113 check for 32 and 16 bit jumps as we want to allow wrap around at
5114 4G and 64k respectively. */
5116 fixP->fx_signed = 1;
5120 output_interseg_jump (void)
5128 if (flag_code == CODE_16BIT)
5132 if (i.prefix[DATA_PREFIX] != 0)
5138 if (i.prefix[REX_PREFIX] != 0)
5148 if (i.prefixes != 0 && !intel_syntax)
5149 as_warn (_("skipping prefixes on this instruction"));
5151 /* 1 opcode; 2 segment; offset */
5152 p = frag_more (prefix + 1 + 2 + size);
5154 if (i.prefix[DATA_PREFIX] != 0)
5155 *p++ = DATA_PREFIX_OPCODE;
5157 if (i.prefix[REX_PREFIX] != 0)
5158 *p++ = i.prefix[REX_PREFIX];
5160 *p++ = i.tm.base_opcode;
5161 if (i.op[1].imms->X_op == O_constant)
5163 offsetT n = i.op[1].imms->X_add_number;
5166 && !fits_in_unsigned_word (n)
5167 && !fits_in_signed_word (n))
5169 as_bad (_("16-bit jump out of range"));
5172 md_number_to_chars (p, n, size);
5175 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5176 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5177 if (i.op[0].imms->X_op != O_constant)
5178 as_bad (_("can't handle non absolute segment in `%s'"),
5180 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5186 fragS *insn_start_frag;
5187 offsetT insn_start_off;
5189 /* Tie dwarf2 debug info to the address at the start of the insn.
5190 We can't do this after the insn has been output as the current
5191 frag may have been closed off. eg. by frag_var. */
5192 dwarf2_emit_insn (0);
5194 insn_start_frag = frag_now;
5195 insn_start_off = frag_now_fix ();
5198 if (i.tm.opcode_modifier.jump)
5200 else if (i.tm.opcode_modifier.jumpbyte
5201 || i.tm.opcode_modifier.jumpdword)
5203 else if (i.tm.opcode_modifier.jumpintersegment)
5204 output_interseg_jump ();
5207 /* Output normal instructions here. */
5211 unsigned int prefix;
5213 switch (i.tm.opcode_length)
5216 if (i.tm.base_opcode & 0xff000000)
5218 prefix = (i.tm.base_opcode >> 24) & 0xff;
5223 if ((i.tm.base_opcode & 0xff0000) != 0)
5225 prefix = (i.tm.base_opcode >> 16) & 0xff;
5226 if (i.tm.cpu_flags.bitfield.cpupadlock)
5229 if (prefix != REPE_PREFIX_OPCODE
5230 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5231 add_prefix (prefix);
5234 add_prefix (prefix);
5243 /* The prefix bytes. */
5244 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5246 FRAG_APPEND_1_CHAR (*q);
5248 /* Now the opcode; be careful about word order here! */
5249 if (i.tm.opcode_length == 1)
5251 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5255 switch (i.tm.opcode_length)
5259 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5269 /* Put out high byte first: can't use md_number_to_chars! */
5270 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5271 *p = i.tm.base_opcode & 0xff;
5273 /* On SSE5, encode the OC1 bit in the DREX field if this
5274 encoding has multiple formats. */
5275 if (i.tm.opcode_modifier.drex
5276 && i.tm.opcode_modifier.drexv
5277 && DREX_OC1 (i.tm.extension_opcode))
5278 *p |= DREX_OC1_MASK;
5281 /* Now the modrm byte and sib byte (if present). */
5282 if (i.tm.opcode_modifier.modrm)
5284 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5287 /* If i.rm.regmem == ESP (4)
5288 && i.rm.mode != (Register mode)
5290 ==> need second modrm byte. */
5291 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5293 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5294 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5296 | i.sib.scale << 6));
5299 /* Write the DREX byte if needed. */
5300 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5303 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5305 /* Encode the OC0 bit if this encoding has multiple
5307 if ((i.tm.opcode_modifier.drex
5308 || i.tm.opcode_modifier.drexv)
5309 && DREX_OC0 (i.tm.extension_opcode))
5310 *p |= DREX_OC0_MASK;
5313 if (i.disp_operands)
5314 output_disp (insn_start_frag, insn_start_off);
5317 output_imm (insn_start_frag, insn_start_off);
5323 pi ("" /*line*/, &i);
5325 #endif /* DEBUG386 */
5328 /* Return the size of the displacement operand N. */
5331 disp_size (unsigned int n)
5334 if (i.types[n].bitfield.disp64)
5336 else if (i.types[n].bitfield.disp8)
5338 else if (i.types[n].bitfield.disp16)
5343 /* Return the size of the immediate operand N. */
5346 imm_size (unsigned int n)
5349 if (i.types[n].bitfield.imm64)
5351 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5353 else if (i.types[n].bitfield.imm16)
5359 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5364 for (n = 0; n < i.operands; n++)
5366 if (operand_type_check (i.types[n], disp))
5368 if (i.op[n].disps->X_op == O_constant)
5370 int size = disp_size (n);
5373 val = offset_in_range (i.op[n].disps->X_add_number,
5375 p = frag_more (size);
5376 md_number_to_chars (p, val, size);
5380 enum bfd_reloc_code_real reloc_type;
5381 int size = disp_size (n);
5382 int sign = i.types[n].bitfield.disp32s;
5383 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5385 /* We can't have 8 bit displacement here. */
5386 assert (!i.types[n].bitfield.disp8);
5388 /* The PC relative address is computed relative
5389 to the instruction boundary, so in case immediate
5390 fields follows, we need to adjust the value. */
5391 if (pcrel && i.imm_operands)
5396 for (n1 = 0; n1 < i.operands; n1++)
5397 if (operand_type_check (i.types[n1], imm))
5399 /* Only one immediate is allowed for PC
5400 relative address. */
5403 i.op[n].disps->X_add_number -= sz;
5405 /* We should find the immediate. */
5409 p = frag_more (size);
5410 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5412 && GOT_symbol == i.op[n].disps->X_add_symbol
5413 && (((reloc_type == BFD_RELOC_32
5414 || reloc_type == BFD_RELOC_X86_64_32S
5415 || (reloc_type == BFD_RELOC_64
5417 && (i.op[n].disps->X_op == O_symbol
5418 || (i.op[n].disps->X_op == O_add
5419 && ((symbol_get_value_expression
5420 (i.op[n].disps->X_op_symbol)->X_op)
5422 || reloc_type == BFD_RELOC_32_PCREL))
5426 if (insn_start_frag == frag_now)
5427 add = (p - frag_now->fr_literal) - insn_start_off;
5432 add = insn_start_frag->fr_fix - insn_start_off;
5433 for (fr = insn_start_frag->fr_next;
5434 fr && fr != frag_now; fr = fr->fr_next)
5436 add += p - frag_now->fr_literal;
5441 reloc_type = BFD_RELOC_386_GOTPC;
5442 i.op[n].imms->X_add_number += add;
5444 else if (reloc_type == BFD_RELOC_64)
5445 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5447 /* Don't do the adjustment for x86-64, as there
5448 the pcrel addressing is relative to the _next_
5449 insn, and that is taken care of in other code. */
5450 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5452 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5453 i.op[n].disps, pcrel, reloc_type);
5460 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5465 for (n = 0; n < i.operands; n++)
5467 if (operand_type_check (i.types[n], imm))
5469 if (i.op[n].imms->X_op == O_constant)
5471 int size = imm_size (n);
5474 val = offset_in_range (i.op[n].imms->X_add_number,
5476 p = frag_more (size);
5477 md_number_to_chars (p, val, size);
5481 /* Not absolute_section.
5482 Need a 32-bit fixup (don't support 8bit
5483 non-absolute imms). Try to support other
5485 enum bfd_reloc_code_real reloc_type;
5486 int size = imm_size (n);
5489 if (i.types[n].bitfield.imm32s
5490 && (i.suffix == QWORD_MNEM_SUFFIX
5491 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5496 p = frag_more (size);
5497 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5499 /* This is tough to explain. We end up with this one if we
5500 * have operands that look like
5501 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5502 * obtain the absolute address of the GOT, and it is strongly
5503 * preferable from a performance point of view to avoid using
5504 * a runtime relocation for this. The actual sequence of
5505 * instructions often look something like:
5510 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5512 * The call and pop essentially return the absolute address
5513 * of the label .L66 and store it in %ebx. The linker itself
5514 * will ultimately change the first operand of the addl so
5515 * that %ebx points to the GOT, but to keep things simple, the
5516 * .o file must have this operand set so that it generates not
5517 * the absolute address of .L66, but the absolute address of
5518 * itself. This allows the linker itself simply treat a GOTPC
5519 * relocation as asking for a pcrel offset to the GOT to be
5520 * added in, and the addend of the relocation is stored in the
5521 * operand field for the instruction itself.
5523 * Our job here is to fix the operand so that it would add
5524 * the correct offset so that %ebx would point to itself. The
5525 * thing that is tricky is that .-.L66 will point to the
5526 * beginning of the instruction, so we need to further modify
5527 * the operand so that it will point to itself. There are
5528 * other cases where you have something like:
5530 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5532 * and here no correction would be required. Internally in
5533 * the assembler we treat operands of this form as not being
5534 * pcrel since the '.' is explicitly mentioned, and I wonder
5535 * whether it would simplify matters to do it this way. Who
5536 * knows. In earlier versions of the PIC patches, the
5537 * pcrel_adjust field was used to store the correction, but
5538 * since the expression is not pcrel, I felt it would be
5539 * confusing to do it this way. */
5541 if ((reloc_type == BFD_RELOC_32
5542 || reloc_type == BFD_RELOC_X86_64_32S
5543 || reloc_type == BFD_RELOC_64)
5545 && GOT_symbol == i.op[n].imms->X_add_symbol
5546 && (i.op[n].imms->X_op == O_symbol
5547 || (i.op[n].imms->X_op == O_add
5548 && ((symbol_get_value_expression
5549 (i.op[n].imms->X_op_symbol)->X_op)
5554 if (insn_start_frag == frag_now)
5555 add = (p - frag_now->fr_literal) - insn_start_off;
5560 add = insn_start_frag->fr_fix - insn_start_off;
5561 for (fr = insn_start_frag->fr_next;
5562 fr && fr != frag_now; fr = fr->fr_next)
5564 add += p - frag_now->fr_literal;
5568 reloc_type = BFD_RELOC_386_GOTPC;
5570 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5572 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5573 i.op[n].imms->X_add_number += add;
5575 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5576 i.op[n].imms, 0, reloc_type);
5582 /* x86_cons_fix_new is called via the expression parsing code when a
5583 reloc is needed. We use this hook to get the correct .got reloc. */
5584 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5585 static int cons_sign = -1;
5588 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5591 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5593 got_reloc = NO_RELOC;
5596 if (exp->X_op == O_secrel)
5598 exp->X_op = O_symbol;
5599 r = BFD_RELOC_32_SECREL;
5603 fix_new_exp (frag, off, len, exp, 0, r);
5606 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5607 # define lex_got(reloc, adjust, types) NULL
5609 /* Parse operands of the form
5610 <symbol>@GOTOFF+<nnn>
5611 and similar .plt or .got references.
5613 If we find one, set up the correct relocation in RELOC and copy the
5614 input string, minus the `@GOTOFF' into a malloc'd buffer for
5615 parsing by the calling routine. Return this buffer, and if ADJUST
5616 is non-null set it to the length of the string we removed from the
5617 input line. Otherwise return NULL. */
5619 lex_got (enum bfd_reloc_code_real *reloc,
5621 i386_operand_type *types)
5623 /* Some of the relocations depend on the size of what field is to
5624 be relocated. But in our callers i386_immediate and i386_displacement
5625 we don't yet know the operand size (this will be set by insn
5626 matching). Hence we record the word32 relocation here,
5627 and adjust the reloc according to the real size in reloc(). */
5628 static const struct {
5630 const enum bfd_reloc_code_real rel[2];
5631 const i386_operand_type types64;
5634 BFD_RELOC_X86_64_PLTOFF64 },
5635 OPERAND_TYPE_IMM64 },
5636 { "PLT", { BFD_RELOC_386_PLT32,
5637 BFD_RELOC_X86_64_PLT32 },
5638 OPERAND_TYPE_IMM32_32S_DISP32 },
5640 BFD_RELOC_X86_64_GOTPLT64 },
5641 OPERAND_TYPE_IMM64_DISP64 },
5642 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5643 BFD_RELOC_X86_64_GOTOFF64 },
5644 OPERAND_TYPE_IMM64_DISP64 },
5646 BFD_RELOC_X86_64_GOTPCREL },
5647 OPERAND_TYPE_IMM32_32S_DISP32 },
5648 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5649 BFD_RELOC_X86_64_TLSGD },
5650 OPERAND_TYPE_IMM32_32S_DISP32 },
5651 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5653 OPERAND_TYPE_NONE },
5655 BFD_RELOC_X86_64_TLSLD },
5656 OPERAND_TYPE_IMM32_32S_DISP32 },
5657 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5658 BFD_RELOC_X86_64_GOTTPOFF },
5659 OPERAND_TYPE_IMM32_32S_DISP32 },
5660 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5661 BFD_RELOC_X86_64_TPOFF32 },
5662 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5663 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5665 OPERAND_TYPE_NONE },
5666 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5667 BFD_RELOC_X86_64_DTPOFF32 },
5669 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5670 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5672 OPERAND_TYPE_NONE },
5673 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5675 OPERAND_TYPE_NONE },
5676 { "GOT", { BFD_RELOC_386_GOT32,
5677 BFD_RELOC_X86_64_GOT32 },
5678 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5679 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5680 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5681 OPERAND_TYPE_IMM32_32S_DISP32 },
5682 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5683 BFD_RELOC_X86_64_TLSDESC_CALL },
5684 OPERAND_TYPE_IMM32_32S_DISP32 },
5692 for (cp = input_line_pointer; *cp != '@'; cp++)
5693 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5696 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5700 len = strlen (gotrel[j].str);
5701 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5703 if (gotrel[j].rel[object_64bit] != 0)
5706 char *tmpbuf, *past_reloc;
5708 *reloc = gotrel[j].rel[object_64bit];
5714 if (flag_code != CODE_64BIT)
5716 types->bitfield.imm32 = 1;
5717 types->bitfield.disp32 = 1;
5720 *types = gotrel[j].types64;
5723 if (GOT_symbol == NULL)
5724 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5726 /* The length of the first part of our input line. */
5727 first = cp - input_line_pointer;
5729 /* The second part goes from after the reloc token until
5730 (and including) an end_of_line char or comma. */
5731 past_reloc = cp + 1 + len;
5733 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5735 second = cp + 1 - past_reloc;
5737 /* Allocate and copy string. The trailing NUL shouldn't
5738 be necessary, but be safe. */
5739 tmpbuf = xmalloc (first + second + 2);
5740 memcpy (tmpbuf, input_line_pointer, first);
5741 if (second != 0 && *past_reloc != ' ')
5742 /* Replace the relocation token with ' ', so that
5743 errors like foo@GOTOFF1 will be detected. */
5744 tmpbuf[first++] = ' ';
5745 memcpy (tmpbuf + first, past_reloc, second);
5746 tmpbuf[first + second] = '\0';
5750 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5751 gotrel[j].str, 1 << (5 + object_64bit));
5756 /* Might be a symbol version string. Don't as_bad here. */
5761 x86_cons (expressionS *exp, int size)
5763 if (size == 4 || (object_64bit && size == 8))
5765 /* Handle @GOTOFF and the like in an expression. */
5767 char *gotfree_input_line;
5770 save = input_line_pointer;
5771 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5772 if (gotfree_input_line)
5773 input_line_pointer = gotfree_input_line;
5777 if (gotfree_input_line)
5779 /* expression () has merrily parsed up to the end of line,
5780 or a comma - in the wrong buffer. Transfer how far
5781 input_line_pointer has moved to the right buffer. */
5782 input_line_pointer = (save
5783 + (input_line_pointer - gotfree_input_line)
5785 free (gotfree_input_line);
5786 if (exp->X_op == O_constant
5787 || exp->X_op == O_absent
5788 || exp->X_op == O_illegal
5789 || exp->X_op == O_register
5790 || exp->X_op == O_big)
5792 char c = *input_line_pointer;
5793 *input_line_pointer = 0;
5794 as_bad (_("missing or invalid expression `%s'"), save);
5795 *input_line_pointer = c;
5804 static void signed_cons (int size)
5806 if (flag_code == CODE_64BIT)
5814 pe_directive_secrel (dummy)
5815 int dummy ATTRIBUTE_UNUSED;
5822 if (exp.X_op == O_symbol)
5823 exp.X_op = O_secrel;
5825 emit_expr (&exp, 4);
5827 while (*input_line_pointer++ == ',');
5829 input_line_pointer--;
5830 demand_empty_rest_of_line ();
5835 i386_immediate (char *imm_start)
5837 char *save_input_line_pointer;
5838 char *gotfree_input_line;
5841 i386_operand_type types;
5843 UINTS_SET (types, ~0);
5845 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5847 as_bad (_("at most %d immediate operands are allowed"),
5848 MAX_IMMEDIATE_OPERANDS);
5852 exp = &im_expressions[i.imm_operands++];
5853 i.op[this_operand].imms = exp;
5855 if (is_space_char (*imm_start))
5858 save_input_line_pointer = input_line_pointer;
5859 input_line_pointer = imm_start;
5861 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5862 if (gotfree_input_line)
5863 input_line_pointer = gotfree_input_line;
5865 exp_seg = expression (exp);
5868 if (*input_line_pointer)
5869 as_bad (_("junk `%s' after expression"), input_line_pointer);
5871 input_line_pointer = save_input_line_pointer;
5872 if (gotfree_input_line)
5873 free (gotfree_input_line);
5875 if (exp->X_op == O_absent
5876 || exp->X_op == O_illegal
5877 || exp->X_op == O_big
5878 || (gotfree_input_line
5879 && (exp->X_op == O_constant
5880 || exp->X_op == O_register)))
5882 as_bad (_("missing or invalid immediate expression `%s'"),
5886 else if (exp->X_op == O_constant)
5888 /* Size it properly later. */
5889 i.types[this_operand].bitfield.imm64 = 1;
5890 /* If BFD64, sign extend val. */
5891 if (!use_rela_relocations
5892 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5894 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5896 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5897 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5898 && exp_seg != absolute_section
5899 && exp_seg != text_section
5900 && exp_seg != data_section
5901 && exp_seg != bss_section
5902 && exp_seg != undefined_section
5903 && !bfd_is_com_section (exp_seg))
5905 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5909 else if (!intel_syntax && exp->X_op == O_register)
5911 as_bad (_("illegal immediate register operand %s"), imm_start);
5916 /* This is an address. The size of the address will be
5917 determined later, depending on destination register,
5918 suffix, or the default for the section. */
5919 i.types[this_operand].bitfield.imm8 = 1;
5920 i.types[this_operand].bitfield.imm16 = 1;
5921 i.types[this_operand].bitfield.imm32 = 1;
5922 i.types[this_operand].bitfield.imm32s = 1;
5923 i.types[this_operand].bitfield.imm64 = 1;
5924 i.types[this_operand] = operand_type_and (i.types[this_operand],
5932 i386_scale (char *scale)
5935 char *save = input_line_pointer;
5937 input_line_pointer = scale;
5938 val = get_absolute_expression ();
5943 i.log2_scale_factor = 0;
5946 i.log2_scale_factor = 1;
5949 i.log2_scale_factor = 2;
5952 i.log2_scale_factor = 3;
5956 char sep = *input_line_pointer;
5958 *input_line_pointer = '\0';
5959 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5961 *input_line_pointer = sep;
5962 input_line_pointer = save;
5966 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5968 as_warn (_("scale factor of %d without an index register"),
5969 1 << i.log2_scale_factor);
5970 i.log2_scale_factor = 0;
5972 scale = input_line_pointer;
5973 input_line_pointer = save;
5978 i386_displacement (char *disp_start, char *disp_end)
5982 char *save_input_line_pointer;
5983 char *gotfree_input_line;
5985 i386_operand_type bigdisp, types = anydisp;
5988 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5990 as_bad (_("at most %d displacement operands are allowed"),
5991 MAX_MEMORY_OPERANDS);
5995 UINTS_CLEAR (bigdisp);
5996 if ((i.types[this_operand].bitfield.jumpabsolute)
5997 || (!current_templates->start->opcode_modifier.jump
5998 && !current_templates->start->opcode_modifier.jumpdword))
6000 bigdisp.bitfield.disp32 = 1;
6001 override = (i.prefix[ADDR_PREFIX] != 0);
6002 if (flag_code == CODE_64BIT)
6006 bigdisp.bitfield.disp32s = 1;
6007 bigdisp.bitfield.disp64 = 1;
6010 else if ((flag_code == CODE_16BIT) ^ override)
6012 bigdisp.bitfield.disp32 = 0;
6013 bigdisp.bitfield.disp16 = 1;
6018 /* For PC-relative branches, the width of the displacement
6019 is dependent upon data size, not address size. */
6020 override = (i.prefix[DATA_PREFIX] != 0);
6021 if (flag_code == CODE_64BIT)
6023 if (override || i.suffix == WORD_MNEM_SUFFIX)
6024 bigdisp.bitfield.disp16 = 1;
6027 bigdisp.bitfield.disp32 = 1;
6028 bigdisp.bitfield.disp32s = 1;
6034 override = (i.suffix == (flag_code != CODE_16BIT
6036 : LONG_MNEM_SUFFIX));
6037 bigdisp.bitfield.disp32 = 1;
6038 if ((flag_code == CODE_16BIT) ^ override)
6040 bigdisp.bitfield.disp32 = 0;
6041 bigdisp.bitfield.disp16 = 1;
6045 i.types[this_operand] = operand_type_or (i.types[this_operand],
6048 exp = &disp_expressions[i.disp_operands];
6049 i.op[this_operand].disps = exp;
6051 save_input_line_pointer = input_line_pointer;
6052 input_line_pointer = disp_start;
6053 END_STRING_AND_SAVE (disp_end);
6055 #ifndef GCC_ASM_O_HACK
6056 #define GCC_ASM_O_HACK 0
6059 END_STRING_AND_SAVE (disp_end + 1);
6060 if (i.types[this_operand].bitfield.baseIndex
6061 && displacement_string_end[-1] == '+')
6063 /* This hack is to avoid a warning when using the "o"
6064 constraint within gcc asm statements.
6067 #define _set_tssldt_desc(n,addr,limit,type) \
6068 __asm__ __volatile__ ( \
6070 "movw %w1,2+%0\n\t" \
6072 "movb %b1,4+%0\n\t" \
6073 "movb %4,5+%0\n\t" \
6074 "movb $0,6+%0\n\t" \
6075 "movb %h1,7+%0\n\t" \
6077 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6079 This works great except that the output assembler ends
6080 up looking a bit weird if it turns out that there is
6081 no offset. You end up producing code that looks like:
6094 So here we provide the missing zero. */
6096 *displacement_string_end = '0';
6099 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6100 if (gotfree_input_line)
6101 input_line_pointer = gotfree_input_line;
6103 exp_seg = expression (exp);
6106 if (*input_line_pointer)
6107 as_bad (_("junk `%s' after expression"), input_line_pointer);
6109 RESTORE_END_STRING (disp_end + 1);
6111 input_line_pointer = save_input_line_pointer;
6112 if (gotfree_input_line)
6113 free (gotfree_input_line);
6116 /* We do this to make sure that the section symbol is in
6117 the symbol table. We will ultimately change the relocation
6118 to be relative to the beginning of the section. */
6119 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6120 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6121 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6123 if (exp->X_op != O_symbol)
6126 if (S_IS_LOCAL (exp->X_add_symbol)
6127 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6128 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6129 exp->X_op = O_subtract;
6130 exp->X_op_symbol = GOT_symbol;
6131 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6132 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6133 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6134 i.reloc[this_operand] = BFD_RELOC_64;
6136 i.reloc[this_operand] = BFD_RELOC_32;
6139 else if (exp->X_op == O_absent
6140 || exp->X_op == O_illegal
6141 || exp->X_op == O_big
6142 || (gotfree_input_line
6143 && (exp->X_op == O_constant
6144 || exp->X_op == O_register)))
6147 as_bad (_("missing or invalid displacement expression `%s'"),
6152 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6153 else if (exp->X_op != O_constant
6154 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6155 && exp_seg != absolute_section
6156 && exp_seg != text_section
6157 && exp_seg != data_section
6158 && exp_seg != bss_section
6159 && exp_seg != undefined_section
6160 && !bfd_is_com_section (exp_seg))
6162 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6167 RESTORE_END_STRING (disp_end);
6169 /* Check if this is a displacement only operand. */
6170 bigdisp = i.types[this_operand];
6171 bigdisp.bitfield.disp8 = 0;
6172 bigdisp.bitfield.disp16 = 0;
6173 bigdisp.bitfield.disp32 = 0;
6174 bigdisp.bitfield.disp32s = 0;
6175 bigdisp.bitfield.disp64 = 0;
6176 if (UINTS_ALL_ZERO (bigdisp))
6177 i.types[this_operand] = operand_type_and (i.types[this_operand],
6183 /* Make sure the memory operand we've been dealt is valid.
6184 Return 1 on success, 0 on a failure. */
6187 i386_index_check (const char *operand_string)
6190 #if INFER_ADDR_PREFIX
6196 if (flag_code == CODE_64BIT)
6199 && ((i.prefix[ADDR_PREFIX] == 0
6200 && !i.base_reg->reg_type.bitfield.reg64)
6201 || (i.prefix[ADDR_PREFIX]
6202 && !i.base_reg->reg_type.bitfield.reg32))
6204 || i.base_reg->reg_num !=
6205 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6207 && (!i.index_reg->reg_type.bitfield.baseindex
6208 || (i.prefix[ADDR_PREFIX] == 0
6209 && i.index_reg->reg_num != RegRiz
6210 && !i.index_reg->reg_type.bitfield.reg64
6212 || (i.prefix[ADDR_PREFIX]
6213 && i.index_reg->reg_num != RegEiz
6214 && !i.index_reg->reg_type.bitfield.reg32))))
6219 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6223 && (!i.base_reg->reg_type.bitfield.reg16
6224 || !i.base_reg->reg_type.bitfield.baseindex))
6226 && (!i.index_reg->reg_type.bitfield.reg16
6227 || !i.index_reg->reg_type.bitfield.baseindex
6229 && i.base_reg->reg_num < 6
6230 && i.index_reg->reg_num >= 6
6231 && i.log2_scale_factor == 0))))
6238 && !i.base_reg->reg_type.bitfield.reg32)
6240 && ((!i.index_reg->reg_type.bitfield.reg32
6241 && i.index_reg->reg_num != RegEiz)
6242 || !i.index_reg->reg_type.bitfield.baseindex)))
6248 #if INFER_ADDR_PREFIX
6249 if (i.prefix[ADDR_PREFIX] == 0)
6251 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6253 /* Change the size of any displacement too. At most one of
6254 Disp16 or Disp32 is set.
6255 FIXME. There doesn't seem to be any real need for separate
6256 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6257 Removing them would probably clean up the code quite a lot. */
6258 if (flag_code != CODE_64BIT
6259 && (i.types[this_operand].bitfield.disp16
6260 || i.types[this_operand].bitfield.disp32))
6261 i.types[this_operand]
6262 = operand_type_xor (i.types[this_operand], disp16_32);
6267 as_bad (_("`%s' is not a valid base/index expression"),
6271 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6273 flag_code_names[flag_code]);
6278 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6282 i386_att_operand (char *operand_string)
6286 char *op_string = operand_string;
6288 if (is_space_char (*op_string))
6291 /* We check for an absolute prefix (differentiating,
6292 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6293 if (*op_string == ABSOLUTE_PREFIX)
6296 if (is_space_char (*op_string))
6298 i.types[this_operand].bitfield.jumpabsolute = 1;
6301 /* Check if operand is a register. */
6302 if ((r = parse_register (op_string, &end_op)) != NULL)
6304 i386_operand_type temp;
6306 /* Check for a segment override by searching for ':' after a
6307 segment register. */
6309 if (is_space_char (*op_string))
6311 if (*op_string == ':'
6312 && (r->reg_type.bitfield.sreg2
6313 || r->reg_type.bitfield.sreg3))
6318 i.seg[i.mem_operands] = &es;
6321 i.seg[i.mem_operands] = &cs;
6324 i.seg[i.mem_operands] = &ss;
6327 i.seg[i.mem_operands] = &ds;
6330 i.seg[i.mem_operands] = &fs;
6333 i.seg[i.mem_operands] = &gs;
6337 /* Skip the ':' and whitespace. */
6339 if (is_space_char (*op_string))
6342 if (!is_digit_char (*op_string)
6343 && !is_identifier_char (*op_string)
6344 && *op_string != '('
6345 && *op_string != ABSOLUTE_PREFIX)
6347 as_bad (_("bad memory operand `%s'"), op_string);
6350 /* Handle case of %es:*foo. */
6351 if (*op_string == ABSOLUTE_PREFIX)
6354 if (is_space_char (*op_string))
6356 i.types[this_operand].bitfield.jumpabsolute = 1;
6358 goto do_memory_reference;
6362 as_bad (_("junk `%s' after register"), op_string);
6366 temp.bitfield.baseindex = 0;
6367 i.types[this_operand] = operand_type_or (i.types[this_operand],
6369 i.types[this_operand].bitfield.unspecified = 0;
6370 i.op[this_operand].regs = r;
6373 else if (*op_string == REGISTER_PREFIX)
6375 as_bad (_("bad register name `%s'"), op_string);
6378 else if (*op_string == IMMEDIATE_PREFIX)
6381 if (i.types[this_operand].bitfield.jumpabsolute)
6383 as_bad (_("immediate operand illegal with absolute jump"));
6386 if (!i386_immediate (op_string))
6389 else if (is_digit_char (*op_string)
6390 || is_identifier_char (*op_string)
6391 || *op_string == '(')
6393 /* This is a memory reference of some sort. */
6396 /* Start and end of displacement string expression (if found). */
6397 char *displacement_string_start;
6398 char *displacement_string_end;
6400 do_memory_reference:
6401 if ((i.mem_operands == 1
6402 && !current_templates->start->opcode_modifier.isstring)
6403 || i.mem_operands == 2)
6405 as_bad (_("too many memory references for `%s'"),
6406 current_templates->start->name);
6410 /* Check for base index form. We detect the base index form by
6411 looking for an ')' at the end of the operand, searching
6412 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6414 base_string = op_string + strlen (op_string);
6417 if (is_space_char (*base_string))
6420 /* If we only have a displacement, set-up for it to be parsed later. */
6421 displacement_string_start = op_string;
6422 displacement_string_end = base_string + 1;
6424 if (*base_string == ')')
6427 unsigned int parens_balanced = 1;
6428 /* We've already checked that the number of left & right ()'s are
6429 equal, so this loop will not be infinite. */
6433 if (*base_string == ')')
6435 if (*base_string == '(')
6438 while (parens_balanced);
6440 temp_string = base_string;
6442 /* Skip past '(' and whitespace. */
6444 if (is_space_char (*base_string))
6447 if (*base_string == ','
6448 || ((i.base_reg = parse_register (base_string, &end_op))
6451 displacement_string_end = temp_string;
6453 i.types[this_operand].bitfield.baseindex = 1;
6457 base_string = end_op;
6458 if (is_space_char (*base_string))
6462 /* There may be an index reg or scale factor here. */
6463 if (*base_string == ',')
6466 if (is_space_char (*base_string))
6469 if ((i.index_reg = parse_register (base_string, &end_op))
6472 base_string = end_op;
6473 if (is_space_char (*base_string))
6475 if (*base_string == ',')
6478 if (is_space_char (*base_string))
6481 else if (*base_string != ')')
6483 as_bad (_("expecting `,' or `)' "
6484 "after index register in `%s'"),
6489 else if (*base_string == REGISTER_PREFIX)
6491 as_bad (_("bad register name `%s'"), base_string);
6495 /* Check for scale factor. */
6496 if (*base_string != ')')
6498 char *end_scale = i386_scale (base_string);
6503 base_string = end_scale;
6504 if (is_space_char (*base_string))
6506 if (*base_string != ')')
6508 as_bad (_("expecting `)' "
6509 "after scale factor in `%s'"),
6514 else if (!i.index_reg)
6516 as_bad (_("expecting index register or scale factor "
6517 "after `,'; got '%c'"),
6522 else if (*base_string != ')')
6524 as_bad (_("expecting `,' or `)' "
6525 "after base register in `%s'"),
6530 else if (*base_string == REGISTER_PREFIX)
6532 as_bad (_("bad register name `%s'"), base_string);
6537 /* If there's an expression beginning the operand, parse it,
6538 assuming displacement_string_start and
6539 displacement_string_end are meaningful. */
6540 if (displacement_string_start != displacement_string_end)
6542 if (!i386_displacement (displacement_string_start,
6543 displacement_string_end))
6547 /* Special case for (%dx) while doing input/output op. */
6549 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6551 && i.log2_scale_factor == 0
6552 && i.seg[i.mem_operands] == 0
6553 && !operand_type_check (i.types[this_operand], disp))
6555 UINTS_CLEAR (i.types[this_operand]);
6556 i.types[this_operand].bitfield.inoutportreg = 1;
6560 if (i386_index_check (operand_string) == 0)
6562 i.types[this_operand].bitfield.mem = 1;
6567 /* It's not a memory operand; argh! */
6568 as_bad (_("invalid char %s beginning operand %d `%s'"),
6569 output_invalid (*op_string),
6574 return 1; /* Normal return. */
6577 /* md_estimate_size_before_relax()
6579 Called just before relax() for rs_machine_dependent frags. The x86
6580 assembler uses these frags to handle variable size jump
6583 Any symbol that is now undefined will not become defined.
6584 Return the correct fr_subtype in the frag.
6585 Return the initial "guess for variable size of frag" to caller.
6586 The guess is actually the growth beyond the fixed part. Whatever
6587 we do to grow the fixed or variable part contributes to our
6591 md_estimate_size_before_relax (fragP, segment)
6595 /* We've already got fragP->fr_subtype right; all we have to do is
6596 check for un-relaxable symbols. On an ELF system, we can't relax
6597 an externally visible symbol, because it may be overridden by a
6599 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6602 && (S_IS_EXTERNAL (fragP->fr_symbol)
6603 || S_IS_WEAK (fragP->fr_symbol)))
6607 /* Symbol is undefined in this segment, or we need to keep a
6608 reloc so that weak symbols can be overridden. */
6609 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6610 enum bfd_reloc_code_real reloc_type;
6611 unsigned char *opcode;
6614 if (fragP->fr_var != NO_RELOC)
6615 reloc_type = fragP->fr_var;
6617 reloc_type = BFD_RELOC_16_PCREL;
6619 reloc_type = BFD_RELOC_32_PCREL;
6621 old_fr_fix = fragP->fr_fix;
6622 opcode = (unsigned char *) fragP->fr_opcode;
6624 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6627 /* Make jmp (0xeb) a (d)word displacement jump. */
6629 fragP->fr_fix += size;
6630 fix_new (fragP, old_fr_fix, size,
6632 fragP->fr_offset, 1,
6638 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6640 /* Negate the condition, and branch past an
6641 unconditional jump. */
6644 /* Insert an unconditional jump. */
6646 /* We added two extra opcode bytes, and have a two byte
6648 fragP->fr_fix += 2 + 2;
6649 fix_new (fragP, old_fr_fix + 2, 2,
6651 fragP->fr_offset, 1,
6658 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6663 fixP = fix_new (fragP, old_fr_fix, 1,
6665 fragP->fr_offset, 1,
6667 fixP->fx_signed = 1;
6671 /* This changes the byte-displacement jump 0x7N
6672 to the (d)word-displacement jump 0x0f,0x8N. */
6673 opcode[1] = opcode[0] + 0x10;
6674 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6675 /* We've added an opcode byte. */
6676 fragP->fr_fix += 1 + size;
6677 fix_new (fragP, old_fr_fix + 1, size,
6679 fragP->fr_offset, 1,
6684 BAD_CASE (fragP->fr_subtype);
6688 return fragP->fr_fix - old_fr_fix;
6691 /* Guess size depending on current relax state. Initially the relax
6692 state will correspond to a short jump and we return 1, because
6693 the variable part of the frag (the branch offset) is one byte
6694 long. However, we can relax a section more than once and in that
6695 case we must either set fr_subtype back to the unrelaxed state,
6696 or return the value for the appropriate branch. */
6697 return md_relax_table[fragP->fr_subtype].rlx_length;
6700 /* Called after relax() is finished.
6702 In: Address of frag.
6703 fr_type == rs_machine_dependent.
6704 fr_subtype is what the address relaxed to.
6706 Out: Any fixSs and constants are set up.
6707 Caller will turn frag into a ".space 0". */
6710 md_convert_frag (abfd, sec, fragP)
6711 bfd *abfd ATTRIBUTE_UNUSED;
6712 segT sec ATTRIBUTE_UNUSED;
6715 unsigned char *opcode;
6716 unsigned char *where_to_put_displacement = NULL;
6717 offsetT target_address;
6718 offsetT opcode_address;
6719 unsigned int extension = 0;
6720 offsetT displacement_from_opcode_start;
6722 opcode = (unsigned char *) fragP->fr_opcode;
6724 /* Address we want to reach in file space. */
6725 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6727 /* Address opcode resides at in file space. */
6728 opcode_address = fragP->fr_address + fragP->fr_fix;
6730 /* Displacement from opcode start to fill into instruction. */
6731 displacement_from_opcode_start = target_address - opcode_address;
6733 if ((fragP->fr_subtype & BIG) == 0)
6735 /* Don't have to change opcode. */
6736 extension = 1; /* 1 opcode + 1 displacement */
6737 where_to_put_displacement = &opcode[1];
6741 if (no_cond_jump_promotion
6742 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6743 as_warn_where (fragP->fr_file, fragP->fr_line,
6744 _("long jump required"));
6746 switch (fragP->fr_subtype)
6748 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6749 extension = 4; /* 1 opcode + 4 displacement */
6751 where_to_put_displacement = &opcode[1];
6754 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6755 extension = 2; /* 1 opcode + 2 displacement */
6757 where_to_put_displacement = &opcode[1];
6760 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6761 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6762 extension = 5; /* 2 opcode + 4 displacement */
6763 opcode[1] = opcode[0] + 0x10;
6764 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6765 where_to_put_displacement = &opcode[2];
6768 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6769 extension = 3; /* 2 opcode + 2 displacement */
6770 opcode[1] = opcode[0] + 0x10;
6771 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6772 where_to_put_displacement = &opcode[2];
6775 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6780 where_to_put_displacement = &opcode[3];
6784 BAD_CASE (fragP->fr_subtype);
6789 /* If size if less then four we are sure that the operand fits,
6790 but if it's 4, then it could be that the displacement is larger
6792 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6794 && ((addressT) (displacement_from_opcode_start - extension
6795 + ((addressT) 1 << 31))
6796 > (((addressT) 2 << 31) - 1)))
6798 as_bad_where (fragP->fr_file, fragP->fr_line,
6799 _("jump target out of range"));
6800 /* Make us emit 0. */
6801 displacement_from_opcode_start = extension;
6803 /* Now put displacement after opcode. */
6804 md_number_to_chars ((char *) where_to_put_displacement,
6805 (valueT) (displacement_from_opcode_start - extension),
6806 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6807 fragP->fr_fix += extension;
6810 /* Apply a fixup (fixS) to segment data, once it has been determined
6811 by our caller that we have all the info we need to fix it up.
6813 On the 386, immediates, displacements, and data pointers are all in
6814 the same (little-endian) format, so we don't need to care about which
6818 md_apply_fix (fixP, valP, seg)
6819 /* The fix we're to put in. */
6821 /* Pointer to the value of the bits. */
6823 /* Segment fix is from. */
6824 segT seg ATTRIBUTE_UNUSED;
6826 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6827 valueT value = *valP;
6829 #if !defined (TE_Mach)
6832 switch (fixP->fx_r_type)
6838 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6841 case BFD_RELOC_X86_64_32S:
6842 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6845 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6848 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6853 if (fixP->fx_addsy != NULL
6854 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6855 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6856 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6857 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6858 && !use_rela_relocations)
6860 /* This is a hack. There should be a better way to handle this.
6861 This covers for the fact that bfd_install_relocation will
6862 subtract the current location (for partial_inplace, PC relative
6863 relocations); see more below. */
6867 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6870 value += fixP->fx_where + fixP->fx_frag->fr_address;
6872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6875 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6878 || (symbol_section_p (fixP->fx_addsy)
6879 && sym_seg != absolute_section))
6880 && !generic_force_reloc (fixP))
6882 /* Yes, we add the values in twice. This is because
6883 bfd_install_relocation subtracts them out again. I think
6884 bfd_install_relocation is broken, but I don't dare change
6886 value += fixP->fx_where + fixP->fx_frag->fr_address;
6890 #if defined (OBJ_COFF) && defined (TE_PE)
6891 /* For some reason, the PE format does not store a
6892 section address offset for a PC relative symbol. */
6893 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6894 || S_IS_WEAK (fixP->fx_addsy))
6895 value += md_pcrel_from (fixP);
6899 /* Fix a few things - the dynamic linker expects certain values here,
6900 and we must not disappoint it. */
6901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6902 if (IS_ELF && fixP->fx_addsy)
6903 switch (fixP->fx_r_type)
6905 case BFD_RELOC_386_PLT32:
6906 case BFD_RELOC_X86_64_PLT32:
6907 /* Make the jump instruction point to the address of the operand. At
6908 runtime we merely add the offset to the actual PLT entry. */
6912 case BFD_RELOC_386_TLS_GD:
6913 case BFD_RELOC_386_TLS_LDM:
6914 case BFD_RELOC_386_TLS_IE_32:
6915 case BFD_RELOC_386_TLS_IE:
6916 case BFD_RELOC_386_TLS_GOTIE:
6917 case BFD_RELOC_386_TLS_GOTDESC:
6918 case BFD_RELOC_X86_64_TLSGD:
6919 case BFD_RELOC_X86_64_TLSLD:
6920 case BFD_RELOC_X86_64_GOTTPOFF:
6921 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6922 value = 0; /* Fully resolved at runtime. No addend. */
6924 case BFD_RELOC_386_TLS_LE:
6925 case BFD_RELOC_386_TLS_LDO_32:
6926 case BFD_RELOC_386_TLS_LE_32:
6927 case BFD_RELOC_X86_64_DTPOFF32:
6928 case BFD_RELOC_X86_64_DTPOFF64:
6929 case BFD_RELOC_X86_64_TPOFF32:
6930 case BFD_RELOC_X86_64_TPOFF64:
6931 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6934 case BFD_RELOC_386_TLS_DESC_CALL:
6935 case BFD_RELOC_X86_64_TLSDESC_CALL:
6936 value = 0; /* Fully resolved at runtime. No addend. */
6937 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6941 case BFD_RELOC_386_GOT32:
6942 case BFD_RELOC_X86_64_GOT32:
6943 value = 0; /* Fully resolved at runtime. No addend. */
6946 case BFD_RELOC_VTABLE_INHERIT:
6947 case BFD_RELOC_VTABLE_ENTRY:
6954 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6956 #endif /* !defined (TE_Mach) */
6958 /* Are we finished with this relocation now? */
6959 if (fixP->fx_addsy == NULL)
6961 else if (use_rela_relocations)
6963 fixP->fx_no_overflow = 1;
6964 /* Remember value for tc_gen_reloc. */
6965 fixP->fx_addnumber = value;
6969 md_number_to_chars (p, value, fixP->fx_size);
6973 md_atof (int type, char *litP, int *sizeP)
6975 /* This outputs the LITTLENUMs in REVERSE order;
6976 in accord with the bigendian 386. */
6977 return ieee_md_atof (type, litP, sizeP, FALSE);
6980 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6983 output_invalid (int c)
6986 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6989 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6990 "(0x%x)", (unsigned char) c);
6991 return output_invalid_buf;
6994 /* REG_STRING starts *before* REGISTER_PREFIX. */
6996 static const reg_entry *
6997 parse_real_register (char *reg_string, char **end_op)
6999 char *s = reg_string;
7001 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7004 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7005 if (*s == REGISTER_PREFIX)
7008 if (is_space_char (*s))
7012 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7014 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7015 return (const reg_entry *) NULL;
7019 /* For naked regs, make sure that we are not dealing with an identifier.
7020 This prevents confusing an identifier like `eax_var' with register
7022 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7023 return (const reg_entry *) NULL;
7027 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7029 /* Handle floating point regs, allowing spaces in the (i) part. */
7030 if (r == i386_regtab /* %st is first entry of table */)
7032 if (is_space_char (*s))
7037 if (is_space_char (*s))
7039 if (*s >= '0' && *s <= '7')
7043 if (is_space_char (*s))
7048 r = hash_find (reg_hash, "st(0)");
7053 /* We have "%st(" then garbage. */
7054 return (const reg_entry *) NULL;
7058 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7061 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7062 return (const reg_entry *) NULL;
7065 && ((r->reg_flags & (RegRex64 | RegRex))
7066 || r->reg_type.bitfield.reg64)
7067 && (!cpu_arch_flags.bitfield.cpulm
7068 || !UINTS_EQUAL (r->reg_type, control))
7069 && flag_code != CODE_64BIT)
7070 return (const reg_entry *) NULL;
7075 /* REG_STRING starts *before* REGISTER_PREFIX. */
7077 static const reg_entry *
7078 parse_register (char *reg_string, char **end_op)
7082 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7083 r = parse_real_register (reg_string, end_op);
7088 char *save = input_line_pointer;
7092 input_line_pointer = reg_string;
7093 c = get_symbol_end ();
7094 symbolP = symbol_find (reg_string);
7095 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7097 const expressionS *e = symbol_get_value_expression (symbolP);
7099 know (e->X_op == O_register);
7100 know (e->X_add_number >= 0
7101 && (valueT) e->X_add_number < i386_regtab_size);
7102 r = i386_regtab + e->X_add_number;
7103 *end_op = input_line_pointer;
7105 *input_line_pointer = c;
7106 input_line_pointer = save;
7112 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7115 char *end = input_line_pointer;
7118 r = parse_register (name, &input_line_pointer);
7119 if (r && end <= input_line_pointer)
7121 *nextcharP = *input_line_pointer;
7122 *input_line_pointer = 0;
7123 e->X_op = O_register;
7124 e->X_add_number = r - i386_regtab;
7127 input_line_pointer = end;
7133 md_operand (expressionS *e)
7135 if (*input_line_pointer == REGISTER_PREFIX)
7138 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7142 e->X_op = O_register;
7143 e->X_add_number = r - i386_regtab;
7144 input_line_pointer = end;
7150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7151 const char *md_shortopts = "kVQ:sqn";
7153 const char *md_shortopts = "qn";
7156 #define OPTION_32 (OPTION_MD_BASE + 0)
7157 #define OPTION_64 (OPTION_MD_BASE + 1)
7158 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7159 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7160 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7161 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7162 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7163 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7164 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7165 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7167 struct option md_longopts[] =
7169 {"32", no_argument, NULL, OPTION_32},
7170 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7171 {"64", no_argument, NULL, OPTION_64},
7173 {"divide", no_argument, NULL, OPTION_DIVIDE},
7174 {"march", required_argument, NULL, OPTION_MARCH},
7175 {"mtune", required_argument, NULL, OPTION_MTUNE},
7176 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7177 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7178 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7179 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7180 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7181 {NULL, no_argument, NULL, 0}
7183 size_t md_longopts_size = sizeof (md_longopts);
7186 md_parse_option (int c, char *arg)
7194 optimize_align_code = 0;
7201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7202 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7203 should be emitted or not. FIXME: Not implemented. */
7207 /* -V: SVR4 argument to print version ID. */
7209 print_version_id ();
7212 /* -k: Ignore for FreeBSD compatibility. */
7217 /* -s: On i386 Solaris, this tells the native assembler to use
7218 .stab instead of .stab.excl. We always use .stab anyhow. */
7221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7224 const char **list, **l;
7226 list = bfd_target_list ();
7227 for (l = list; *l != NULL; l++)
7228 if (CONST_STRNEQ (*l, "elf64-x86-64")
7229 || strcmp (*l, "coff-x86-64") == 0
7230 || strcmp (*l, "pe-x86-64") == 0
7231 || strcmp (*l, "pei-x86-64") == 0)
7233 default_arch = "x86_64";
7237 as_fatal (_("No compiled in support for x86_64"));
7244 default_arch = "i386";
7248 #ifdef SVR4_COMMENT_CHARS
7253 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7255 for (s = i386_comment_chars; *s != '\0'; s++)
7259 i386_comment_chars = n;
7265 arch = xstrdup (arg);
7269 as_fatal (_("Invalid -march= option: `%s'"), arg);
7270 next = strchr (arch, '+');
7273 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7275 if (strcmp (arch, cpu_arch [i].name) == 0)
7278 cpu_arch_name = cpu_arch[i].name;
7279 cpu_sub_arch_name = NULL;
7280 cpu_arch_flags = cpu_arch[i].flags;
7281 cpu_arch_isa = cpu_arch[i].type;
7282 cpu_arch_isa_flags = cpu_arch[i].flags;
7283 if (!cpu_arch_tune_set)
7285 cpu_arch_tune = cpu_arch_isa;
7286 cpu_arch_tune_flags = cpu_arch_isa_flags;
7290 else if (*cpu_arch [i].name == '.'
7291 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7293 /* ISA entension. */
7294 i386_cpu_flags flags;
7295 flags = cpu_flags_or (cpu_arch_flags,
7297 if (!UINTS_EQUAL (flags, cpu_arch_flags))
7299 if (cpu_sub_arch_name)
7301 char *name = cpu_sub_arch_name;
7302 cpu_sub_arch_name = concat (name,
7304 (const char *) NULL);
7308 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7309 cpu_arch_flags = flags;
7315 if (i >= ARRAY_SIZE (cpu_arch))
7316 as_fatal (_("Invalid -march= option: `%s'"), arg);
7320 while (next != NULL );
7325 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7326 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7328 if (strcmp (arg, cpu_arch [i].name) == 0)
7330 cpu_arch_tune_set = 1;
7331 cpu_arch_tune = cpu_arch [i].type;
7332 cpu_arch_tune_flags = cpu_arch[i].flags;
7336 if (i >= ARRAY_SIZE (cpu_arch))
7337 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7340 case OPTION_MMNEMONIC:
7341 if (strcasecmp (arg, "att") == 0)
7343 else if (strcasecmp (arg, "intel") == 0)
7346 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7349 case OPTION_MSYNTAX:
7350 if (strcasecmp (arg, "att") == 0)
7352 else if (strcasecmp (arg, "intel") == 0)
7355 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7358 case OPTION_MINDEX_REG:
7359 allow_index_reg = 1;
7362 case OPTION_MNAKED_REG:
7363 allow_naked_reg = 1;
7366 case OPTION_MOLD_GCC:
7377 md_show_usage (stream)
7380 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7381 fprintf (stream, _("\
7383 -V print assembler version number\n\
7386 fprintf (stream, _("\
7387 -n Do not optimize code alignment\n\
7388 -q quieten some warnings\n"));
7389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7390 fprintf (stream, _("\
7393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7394 fprintf (stream, _("\
7395 --32/--64 generate 32bit/64bit code\n"));
7397 #ifdef SVR4_COMMENT_CHARS
7398 fprintf (stream, _("\
7399 --divide do not treat `/' as a comment character\n"));
7401 fprintf (stream, _("\
7402 --divide ignored\n"));
7404 fprintf (stream, _("\
7405 -march=CPU[,+EXTENSION...]\n\
7406 generate code for CPU and EXTENSION, CPU is one of:\n\
7407 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7408 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7409 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7410 generic32, generic64\n\
7411 EXTENSION is combination of:\n\
7412 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7413 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7415 fprintf (stream, _("\
7416 -mtune=CPU optimize for CPU, CPU is one of:\n\
7417 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7418 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7419 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7420 generic32, generic64\n"));
7421 fprintf (stream, _("\
7422 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7423 fprintf (stream, _("\
7424 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7425 fprintf (stream, _("\
7426 -mindex-reg support pseudo index registers\n"));
7427 fprintf (stream, _("\
7428 -mnaked-reg don't require `%%' prefix for registers\n"));
7429 fprintf (stream, _("\
7430 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7433 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7434 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7436 /* Pick the target format to use. */
7439 i386_target_format (void)
7441 if (!strcmp (default_arch, "x86_64"))
7443 set_code_flag (CODE_64BIT);
7444 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7446 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7447 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7448 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7449 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7450 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7451 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7452 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7453 cpu_arch_isa_flags.bitfield.cpummx= 1;
7454 cpu_arch_isa_flags.bitfield.cpusse = 1;
7455 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7457 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7459 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7460 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7461 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7462 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7463 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7464 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7465 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7466 cpu_arch_tune_flags.bitfield.cpummx= 1;
7467 cpu_arch_tune_flags.bitfield.cpusse = 1;
7468 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7471 else if (!strcmp (default_arch, "i386"))
7473 set_code_flag (CODE_32BIT);
7474 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7476 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7477 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7478 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7480 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7482 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7483 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7484 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7488 as_fatal (_("Unknown architecture"));
7489 switch (OUTPUT_FLAVOR)
7492 case bfd_target_coff_flavour:
7493 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7496 #ifdef OBJ_MAYBE_AOUT
7497 case bfd_target_aout_flavour:
7498 return AOUT_TARGET_FORMAT;
7500 #ifdef OBJ_MAYBE_COFF
7501 case bfd_target_coff_flavour:
7504 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7505 case bfd_target_elf_flavour:
7507 if (flag_code == CODE_64BIT)
7510 use_rela_relocations = 1;
7512 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7521 #endif /* OBJ_MAYBE_ more than one */
7523 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7525 i386_elf_emit_arch_note (void)
7527 if (IS_ELF && cpu_arch_name != NULL)
7530 asection *seg = now_seg;
7531 subsegT subseg = now_subseg;
7532 Elf_Internal_Note i_note;
7533 Elf_External_Note e_note;
7534 asection *note_secp;
7537 /* Create the .note section. */
7538 note_secp = subseg_new (".note", 0);
7539 bfd_set_section_flags (stdoutput,
7541 SEC_HAS_CONTENTS | SEC_READONLY);
7543 /* Process the arch string. */
7544 len = strlen (cpu_arch_name);
7546 i_note.namesz = len + 1;
7548 i_note.type = NT_ARCH;
7549 p = frag_more (sizeof (e_note.namesz));
7550 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7551 p = frag_more (sizeof (e_note.descsz));
7552 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7553 p = frag_more (sizeof (e_note.type));
7554 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7555 p = frag_more (len + 1);
7556 strcpy (p, cpu_arch_name);
7558 frag_align (2, 0, 0);
7560 subseg_set (seg, subseg);
7566 md_undefined_symbol (name)
7569 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7570 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7571 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7572 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7576 if (symbol_find (name))
7577 as_bad (_("GOT already in symbol table"));
7578 GOT_symbol = symbol_new (name, undefined_section,
7579 (valueT) 0, &zero_address_frag);
7586 /* Round up a section size to the appropriate boundary. */
7589 md_section_align (segment, size)
7590 segT segment ATTRIBUTE_UNUSED;
7593 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7594 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7596 /* For a.out, force the section size to be aligned. If we don't do
7597 this, BFD will align it for us, but it will not write out the
7598 final bytes of the section. This may be a bug in BFD, but it is
7599 easier to fix it here since that is how the other a.out targets
7603 align = bfd_get_section_alignment (stdoutput, segment);
7604 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7611 /* On the i386, PC-relative offsets are relative to the start of the
7612 next instruction. That is, the address of the offset, plus its
7613 size, since the offset is always the last part of the insn. */
7616 md_pcrel_from (fixS *fixP)
7618 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7624 s_bss (int ignore ATTRIBUTE_UNUSED)
7628 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7630 obj_elf_section_change_hook ();
7632 temp = get_absolute_expression ();
7633 subseg_set (bss_section, (subsegT) temp);
7634 demand_empty_rest_of_line ();
7640 i386_validate_fix (fixS *fixp)
7642 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7644 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7648 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7653 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7655 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7662 tc_gen_reloc (section, fixp)
7663 asection *section ATTRIBUTE_UNUSED;
7667 bfd_reloc_code_real_type code;
7669 switch (fixp->fx_r_type)
7671 case BFD_RELOC_X86_64_PLT32:
7672 case BFD_RELOC_X86_64_GOT32:
7673 case BFD_RELOC_X86_64_GOTPCREL:
7674 case BFD_RELOC_386_PLT32:
7675 case BFD_RELOC_386_GOT32:
7676 case BFD_RELOC_386_GOTOFF:
7677 case BFD_RELOC_386_GOTPC:
7678 case BFD_RELOC_386_TLS_GD:
7679 case BFD_RELOC_386_TLS_LDM:
7680 case BFD_RELOC_386_TLS_LDO_32:
7681 case BFD_RELOC_386_TLS_IE_32:
7682 case BFD_RELOC_386_TLS_IE:
7683 case BFD_RELOC_386_TLS_GOTIE:
7684 case BFD_RELOC_386_TLS_LE_32:
7685 case BFD_RELOC_386_TLS_LE:
7686 case BFD_RELOC_386_TLS_GOTDESC:
7687 case BFD_RELOC_386_TLS_DESC_CALL:
7688 case BFD_RELOC_X86_64_TLSGD:
7689 case BFD_RELOC_X86_64_TLSLD:
7690 case BFD_RELOC_X86_64_DTPOFF32:
7691 case BFD_RELOC_X86_64_DTPOFF64:
7692 case BFD_RELOC_X86_64_GOTTPOFF:
7693 case BFD_RELOC_X86_64_TPOFF32:
7694 case BFD_RELOC_X86_64_TPOFF64:
7695 case BFD_RELOC_X86_64_GOTOFF64:
7696 case BFD_RELOC_X86_64_GOTPC32:
7697 case BFD_RELOC_X86_64_GOT64:
7698 case BFD_RELOC_X86_64_GOTPCREL64:
7699 case BFD_RELOC_X86_64_GOTPC64:
7700 case BFD_RELOC_X86_64_GOTPLT64:
7701 case BFD_RELOC_X86_64_PLTOFF64:
7702 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7703 case BFD_RELOC_X86_64_TLSDESC_CALL:
7705 case BFD_RELOC_VTABLE_ENTRY:
7706 case BFD_RELOC_VTABLE_INHERIT:
7708 case BFD_RELOC_32_SECREL:
7710 code = fixp->fx_r_type;
7712 case BFD_RELOC_X86_64_32S:
7713 if (!fixp->fx_pcrel)
7715 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7716 code = fixp->fx_r_type;
7722 switch (fixp->fx_size)
7725 as_bad_where (fixp->fx_file, fixp->fx_line,
7726 _("can not do %d byte pc-relative relocation"),
7728 code = BFD_RELOC_32_PCREL;
7730 case 1: code = BFD_RELOC_8_PCREL; break;
7731 case 2: code = BFD_RELOC_16_PCREL; break;
7732 case 4: code = BFD_RELOC_32_PCREL; break;
7734 case 8: code = BFD_RELOC_64_PCREL; break;
7740 switch (fixp->fx_size)
7743 as_bad_where (fixp->fx_file, fixp->fx_line,
7744 _("can not do %d byte relocation"),
7746 code = BFD_RELOC_32;
7748 case 1: code = BFD_RELOC_8; break;
7749 case 2: code = BFD_RELOC_16; break;
7750 case 4: code = BFD_RELOC_32; break;
7752 case 8: code = BFD_RELOC_64; break;
7759 if ((code == BFD_RELOC_32
7760 || code == BFD_RELOC_32_PCREL
7761 || code == BFD_RELOC_X86_64_32S)
7763 && fixp->fx_addsy == GOT_symbol)
7766 code = BFD_RELOC_386_GOTPC;
7768 code = BFD_RELOC_X86_64_GOTPC32;
7770 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7772 && fixp->fx_addsy == GOT_symbol)
7774 code = BFD_RELOC_X86_64_GOTPC64;
7777 rel = (arelent *) xmalloc (sizeof (arelent));
7778 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7779 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7781 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7783 if (!use_rela_relocations)
7785 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7786 vtable entry to be used in the relocation's section offset. */
7787 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7788 rel->address = fixp->fx_offset;
7792 /* Use the rela in 64bit mode. */
7795 if (!fixp->fx_pcrel)
7796 rel->addend = fixp->fx_offset;
7800 case BFD_RELOC_X86_64_PLT32:
7801 case BFD_RELOC_X86_64_GOT32:
7802 case BFD_RELOC_X86_64_GOTPCREL:
7803 case BFD_RELOC_X86_64_TLSGD:
7804 case BFD_RELOC_X86_64_TLSLD:
7805 case BFD_RELOC_X86_64_GOTTPOFF:
7806 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7807 case BFD_RELOC_X86_64_TLSDESC_CALL:
7808 rel->addend = fixp->fx_offset - fixp->fx_size;
7811 rel->addend = (section->vma
7813 + fixp->fx_addnumber
7814 + md_pcrel_from (fixp));
7819 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7820 if (rel->howto == NULL)
7822 as_bad_where (fixp->fx_file, fixp->fx_line,
7823 _("cannot represent relocation type %s"),
7824 bfd_get_reloc_code_name (code));
7825 /* Set howto to a garbage value so that we can keep going. */
7826 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7827 assert (rel->howto != NULL);
7834 /* Parse operands using Intel syntax. This implements a recursive descent
7835 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7838 FIXME: We do not recognize the full operand grammar defined in the MASM
7839 documentation. In particular, all the structure/union and
7840 high-level macro operands are missing.
7842 Uppercase words are terminals, lower case words are non-terminals.
7843 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7844 bars '|' denote choices. Most grammar productions are implemented in
7845 functions called 'intel_<production>'.
7847 Initial production is 'expr'.
7853 binOp & | AND | \| | OR | ^ | XOR
7855 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7857 constant digits [[ radixOverride ]]
7859 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7897 => expr expr cmpOp e04
7900 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7901 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7903 hexdigit a | b | c | d | e | f
7904 | A | B | C | D | E | F
7910 mulOp * | / | % | MOD | << | SHL | >> | SHR
7914 register specialRegister
7918 segmentRegister CS | DS | ES | FS | GS | SS
7920 specialRegister CR0 | CR2 | CR3 | CR4
7921 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7922 | TR3 | TR4 | TR5 | TR6 | TR7
7924 We simplify the grammar in obvious places (e.g., register parsing is
7925 done by calling parse_register) and eliminate immediate left recursion
7926 to implement a recursive-descent parser.
7930 expr' cmpOp e04 expr'
7981 /* Parsing structure for the intel syntax parser. Used to implement the
7982 semantic actions for the operand grammar. */
7983 struct intel_parser_s
7985 char *op_string; /* The string being parsed. */
7986 int got_a_float; /* Whether the operand is a float. */
7987 int op_modifier; /* Operand modifier. */
7988 int is_mem; /* 1 if operand is memory reference. */
7989 int in_offset; /* >=1 if parsing operand of offset. */
7990 int in_bracket; /* >=1 if parsing operand in brackets. */
7991 const reg_entry *reg; /* Last register reference found. */
7992 char *disp; /* Displacement string being built. */
7993 char *next_operand; /* Resume point when splitting operands. */
7996 static struct intel_parser_s intel_parser;
7998 /* Token structure for parsing intel syntax. */
8001 int code; /* Token code. */
8002 const reg_entry *reg; /* Register entry for register tokens. */
8003 char *str; /* String representation. */
8006 static struct intel_token cur_token, prev_token;
8008 /* Token codes for the intel parser. Since T_SHORT is already used
8009 by COFF, undefine it first to prevent a warning. */
8028 /* Prototypes for intel parser functions. */
8029 static int intel_match_token (int);
8030 static void intel_putback_token (void);
8031 static void intel_get_token (void);
8032 static int intel_expr (void);
8033 static int intel_e04 (void);
8034 static int intel_e05 (void);
8035 static int intel_e06 (void);
8036 static int intel_e09 (void);
8037 static int intel_e10 (void);
8038 static int intel_e11 (void);
8041 i386_intel_operand (char *operand_string, int got_a_float)
8046 p = intel_parser.op_string = xstrdup (operand_string);
8047 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8051 /* Initialize token holders. */
8052 cur_token.code = prev_token.code = T_NIL;
8053 cur_token.reg = prev_token.reg = NULL;
8054 cur_token.str = prev_token.str = NULL;
8056 /* Initialize parser structure. */
8057 intel_parser.got_a_float = got_a_float;
8058 intel_parser.op_modifier = 0;
8059 intel_parser.is_mem = 0;
8060 intel_parser.in_offset = 0;
8061 intel_parser.in_bracket = 0;
8062 intel_parser.reg = NULL;
8063 intel_parser.disp[0] = '\0';
8064 intel_parser.next_operand = NULL;
8066 /* Read the first token and start the parser. */
8068 ret = intel_expr ();
8073 if (cur_token.code != T_NIL)
8075 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8076 current_templates->start->name, cur_token.str);
8079 /* If we found a memory reference, hand it over to i386_displacement
8080 to fill in the rest of the operand fields. */
8081 else if (intel_parser.is_mem)
8083 if ((i.mem_operands == 1
8084 && !current_templates->start->opcode_modifier.isstring)
8085 || i.mem_operands == 2)
8087 as_bad (_("too many memory references for '%s'"),
8088 current_templates->start->name);
8093 char *s = intel_parser.disp;
8094 i.types[this_operand].bitfield.mem = 1;
8097 if (!quiet_warnings && intel_parser.is_mem < 0)
8098 /* See the comments in intel_bracket_expr. */
8099 as_warn (_("Treating `%s' as memory reference"), operand_string);
8101 /* Add the displacement expression. */
8103 ret = i386_displacement (s, s + strlen (s));
8106 /* Swap base and index in 16-bit memory operands like
8107 [si+bx]. Since i386_index_check is also used in AT&T
8108 mode we have to do that here. */
8111 && i.base_reg->reg_type.bitfield.reg16
8112 && i.index_reg->reg_type.bitfield.reg16
8113 && i.base_reg->reg_num >= 6
8114 && i.index_reg->reg_num < 6)
8116 const reg_entry *base = i.index_reg;
8118 i.index_reg = i.base_reg;
8121 ret = i386_index_check (operand_string);
8126 /* Constant and OFFSET expressions are handled by i386_immediate. */
8127 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8128 || intel_parser.reg == NULL)
8129 ret = i386_immediate (intel_parser.disp);
8131 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8133 if (!ret || !intel_parser.next_operand)
8135 intel_parser.op_string = intel_parser.next_operand;
8136 this_operand = i.operands++;
8137 i.types[this_operand].bitfield.unspecified = 1;
8141 free (intel_parser.disp);
8146 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8150 expr' cmpOp e04 expr'
8155 /* XXX Implement the comparison operators. */
8156 return intel_e04 ();
8173 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8174 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8176 if (cur_token.code == '+')
8178 else if (cur_token.code == '-')
8179 nregs = NUM_ADDRESS_REGS;
8183 strcat (intel_parser.disp, cur_token.str);
8184 intel_match_token (cur_token.code);
8195 int nregs = ~NUM_ADDRESS_REGS;
8202 if (cur_token.code == '&'
8203 || cur_token.code == '|'
8204 || cur_token.code == '^')
8208 str[0] = cur_token.code;
8210 strcat (intel_parser.disp, str);
8215 intel_match_token (cur_token.code);
8220 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8221 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8232 int nregs = ~NUM_ADDRESS_REGS;
8239 if (cur_token.code == '*'
8240 || cur_token.code == '/'
8241 || cur_token.code == '%')
8245 str[0] = cur_token.code;
8247 strcat (intel_parser.disp, str);
8249 else if (cur_token.code == T_SHL)
8250 strcat (intel_parser.disp, "<<");
8251 else if (cur_token.code == T_SHR)
8252 strcat (intel_parser.disp, ">>");
8256 intel_match_token (cur_token.code);
8261 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8262 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8280 int nregs = ~NUM_ADDRESS_REGS;
8285 /* Don't consume constants here. */
8286 if (cur_token.code == '+' || cur_token.code == '-')
8288 /* Need to look one token ahead - if the next token
8289 is a constant, the current token is its sign. */
8292 intel_match_token (cur_token.code);
8293 next_code = cur_token.code;
8294 intel_putback_token ();
8295 if (next_code == T_CONST)
8299 /* e09 OFFSET e09 */
8300 if (cur_token.code == T_OFFSET)
8303 ++intel_parser.in_offset;
8307 else if (cur_token.code == T_SHORT)
8308 intel_parser.op_modifier |= 1 << T_SHORT;
8311 else if (cur_token.code == '+')
8312 strcat (intel_parser.disp, "+");
8317 else if (cur_token.code == '-' || cur_token.code == '~')
8323 str[0] = cur_token.code;
8325 strcat (intel_parser.disp, str);
8332 intel_match_token (cur_token.code);
8340 /* e09' PTR e10 e09' */
8341 if (cur_token.code == T_PTR)
8345 if (prev_token.code == T_BYTE)
8347 suffix = BYTE_MNEM_SUFFIX;
8348 i.types[this_operand].bitfield.byte = 1;
8351 else if (prev_token.code == T_WORD)
8353 if (current_templates->start->name[0] == 'l'
8354 && current_templates->start->name[2] == 's'
8355 && current_templates->start->name[3] == 0)
8356 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8357 else if (intel_parser.got_a_float == 2) /* "fi..." */
8358 suffix = SHORT_MNEM_SUFFIX;
8360 suffix = WORD_MNEM_SUFFIX;
8361 i.types[this_operand].bitfield.word = 1;
8364 else if (prev_token.code == T_DWORD)
8366 if (current_templates->start->name[0] == 'l'
8367 && current_templates->start->name[2] == 's'
8368 && current_templates->start->name[3] == 0)
8369 suffix = WORD_MNEM_SUFFIX;
8370 else if (flag_code == CODE_16BIT
8371 && (current_templates->start->opcode_modifier.jump
8372 || current_templates->start->opcode_modifier.jumpdword))
8373 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8374 else if (intel_parser.got_a_float == 1) /* "f..." */
8375 suffix = SHORT_MNEM_SUFFIX;
8377 suffix = LONG_MNEM_SUFFIX;
8378 i.types[this_operand].bitfield.dword = 1;
8381 else if (prev_token.code == T_FWORD)
8383 if (current_templates->start->name[0] == 'l'
8384 && current_templates->start->name[2] == 's'
8385 && current_templates->start->name[3] == 0)
8386 suffix = LONG_MNEM_SUFFIX;
8387 else if (!intel_parser.got_a_float)
8389 if (flag_code == CODE_16BIT)
8390 add_prefix (DATA_PREFIX_OPCODE);
8391 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8394 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8395 i.types[this_operand].bitfield.fword = 1;
8398 else if (prev_token.code == T_QWORD)
8400 if (intel_parser.got_a_float == 1) /* "f..." */
8401 suffix = LONG_MNEM_SUFFIX;
8403 suffix = QWORD_MNEM_SUFFIX;
8404 i.types[this_operand].bitfield.qword = 1;
8407 else if (prev_token.code == T_TBYTE)
8409 if (intel_parser.got_a_float == 1)
8410 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8412 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8415 else if (prev_token.code == T_XMMWORD)
8417 suffix = XMMWORD_MNEM_SUFFIX;
8418 i.types[this_operand].bitfield.xmmword = 1;
8423 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8427 i.types[this_operand].bitfield.unspecified = 0;
8429 /* Operands for jump/call using 'ptr' notation denote absolute
8431 if (current_templates->start->opcode_modifier.jump
8432 || current_templates->start->opcode_modifier.jumpdword)
8433 i.types[this_operand].bitfield.jumpabsolute = 1;
8435 if (current_templates->start->base_opcode == 0x8d /* lea */)
8439 else if (i.suffix != suffix)
8441 as_bad (_("Conflicting operand modifiers"));
8447 /* e09' : e10 e09' */
8448 else if (cur_token.code == ':')
8450 if (prev_token.code != T_REG)
8452 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8453 segment/group identifier (which we don't have), using comma
8454 as the operand separator there is even less consistent, since
8455 there all branches only have a single operand. */
8456 if (this_operand != 0
8457 || intel_parser.in_offset
8458 || intel_parser.in_bracket
8459 || (!current_templates->start->opcode_modifier.jump
8460 && !current_templates->start->opcode_modifier.jumpdword
8461 && !current_templates->start->opcode_modifier.jumpintersegment
8462 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8463 return intel_match_token (T_NIL);
8464 /* Remember the start of the 2nd operand and terminate 1st
8466 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8467 another expression), but it gets at least the simplest case
8468 (a plain number or symbol on the left side) right. */
8469 intel_parser.next_operand = intel_parser.op_string;
8470 *--intel_parser.op_string = '\0';
8471 return intel_match_token (':');
8479 intel_match_token (cur_token.code);
8485 --intel_parser.in_offset;
8488 if (NUM_ADDRESS_REGS > nregs)
8490 as_bad (_("Invalid operand to `OFFSET'"));
8493 intel_parser.op_modifier |= 1 << T_OFFSET;
8496 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8497 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8502 intel_bracket_expr (void)
8504 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8505 const char *start = intel_parser.op_string;
8508 if (i.op[this_operand].regs)
8509 return intel_match_token (T_NIL);
8511 intel_match_token ('[');
8513 /* Mark as a memory operand only if it's not already known to be an
8514 offset expression. If it's an offset expression, we need to keep
8516 if (!intel_parser.in_offset)
8518 ++intel_parser.in_bracket;
8520 /* Operands for jump/call inside brackets denote absolute addresses. */
8521 if (current_templates->start->opcode_modifier.jump
8522 || current_templates->start->opcode_modifier.jumpdword)
8523 i.types[this_operand].bitfield.jumpabsolute = 1;
8525 /* Unfortunately gas always diverged from MASM in a respect that can't
8526 be easily fixed without risking to break code sequences likely to be
8527 encountered (the testsuite even check for this): MASM doesn't consider
8528 an expression inside brackets unconditionally as a memory reference.
8529 When that is e.g. a constant, an offset expression, or the sum of the
8530 two, this is still taken as a constant load. gas, however, always
8531 treated these as memory references. As a compromise, we'll try to make
8532 offset expressions inside brackets work the MASM way (since that's
8533 less likely to be found in real world code), but make constants alone
8534 continue to work the traditional gas way. In either case, issue a
8536 intel_parser.op_modifier &= ~was_offset;
8539 strcat (intel_parser.disp, "[");
8541 /* Add a '+' to the displacement string if necessary. */
8542 if (*intel_parser.disp != '\0'
8543 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8544 strcat (intel_parser.disp, "+");
8547 && (len = intel_parser.op_string - start - 1,
8548 intel_match_token (']')))
8550 /* Preserve brackets when the operand is an offset expression. */
8551 if (intel_parser.in_offset)
8552 strcat (intel_parser.disp, "]");
8555 --intel_parser.in_bracket;
8556 if (i.base_reg || i.index_reg)
8557 intel_parser.is_mem = 1;
8558 if (!intel_parser.is_mem)
8560 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8561 /* Defer the warning until all of the operand was parsed. */
8562 intel_parser.is_mem = -1;
8563 else if (!quiet_warnings)
8564 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8565 len, start, len, start);
8568 intel_parser.op_modifier |= was_offset;
8585 while (cur_token.code == '[')
8587 if (!intel_bracket_expr ())
8612 switch (cur_token.code)
8616 intel_match_token ('(');
8617 strcat (intel_parser.disp, "(");
8619 if (intel_expr () && intel_match_token (')'))
8621 strcat (intel_parser.disp, ")");
8628 return intel_bracket_expr ();
8633 strcat (intel_parser.disp, cur_token.str);
8634 intel_match_token (cur_token.code);
8636 /* Mark as a memory operand only if it's not already known to be an
8637 offset expression. */
8638 if (!intel_parser.in_offset)
8639 intel_parser.is_mem = 1;
8646 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8648 intel_match_token (T_REG);
8650 /* Check for segment change. */
8651 if (cur_token.code == ':')
8653 if (!reg->reg_type.bitfield.sreg2
8654 && !reg->reg_type.bitfield.sreg3)
8656 as_bad (_("`%s' is not a valid segment register"),
8660 else if (i.seg[i.mem_operands])
8661 as_warn (_("Extra segment override ignored"));
8664 if (!intel_parser.in_offset)
8665 intel_parser.is_mem = 1;
8666 switch (reg->reg_num)
8669 i.seg[i.mem_operands] = &es;
8672 i.seg[i.mem_operands] = &cs;
8675 i.seg[i.mem_operands] = &ss;
8678 i.seg[i.mem_operands] = &ds;
8681 i.seg[i.mem_operands] = &fs;
8684 i.seg[i.mem_operands] = &gs;
8690 /* Not a segment register. Check for register scaling. */
8691 else if (cur_token.code == '*')
8693 if (!intel_parser.in_bracket)
8695 as_bad (_("Register scaling only allowed in memory operands"));
8699 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8700 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8701 else if (i.index_reg)
8702 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8704 /* What follows must be a valid scale. */
8705 intel_match_token ('*');
8707 i.types[this_operand].bitfield.baseindex = 1;
8709 /* Set the scale after setting the register (otherwise,
8710 i386_scale will complain) */
8711 if (cur_token.code == '+' || cur_token.code == '-')
8713 char *str, sign = cur_token.code;
8714 intel_match_token (cur_token.code);
8715 if (cur_token.code != T_CONST)
8717 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8721 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8722 strcpy (str + 1, cur_token.str);
8724 if (!i386_scale (str))
8728 else if (!i386_scale (cur_token.str))
8730 intel_match_token (cur_token.code);
8733 /* No scaling. If this is a memory operand, the register is either a
8734 base register (first occurrence) or an index register (second
8736 else if (intel_parser.in_bracket)
8741 else if (!i.index_reg)
8745 as_bad (_("Too many register references in memory operand"));
8749 i.types[this_operand].bitfield.baseindex = 1;
8752 /* It's neither base nor index. */
8753 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8755 i386_operand_type temp = reg->reg_type;
8756 temp.bitfield.baseindex = 0;
8757 i.types[this_operand] = operand_type_or (i.types[this_operand],
8759 i.types[this_operand].bitfield.unspecified = 0;
8760 i.op[this_operand].regs = reg;
8765 as_bad (_("Invalid use of register"));
8769 /* Since registers are not part of the displacement string (except
8770 when we're parsing offset operands), we may need to remove any
8771 preceding '+' from the displacement string. */
8772 if (*intel_parser.disp != '\0'
8773 && !intel_parser.in_offset)
8775 char *s = intel_parser.disp;
8776 s += strlen (s) - 1;
8799 intel_match_token (cur_token.code);
8801 if (cur_token.code == T_PTR)
8804 /* It must have been an identifier. */
8805 intel_putback_token ();
8806 cur_token.code = T_ID;
8812 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8816 /* The identifier represents a memory reference only if it's not
8817 preceded by an offset modifier and if it's not an equate. */
8818 symbolP = symbol_find(cur_token.str);
8819 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8820 intel_parser.is_mem = 1;
8828 char *save_str, sign = 0;
8830 /* Allow constants that start with `+' or `-'. */
8831 if (cur_token.code == '-' || cur_token.code == '+')
8833 sign = cur_token.code;
8834 intel_match_token (cur_token.code);
8835 if (cur_token.code != T_CONST)
8837 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8843 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8844 strcpy (save_str + !!sign, cur_token.str);
8848 /* Get the next token to check for register scaling. */
8849 intel_match_token (cur_token.code);
8851 /* Check if this constant is a scaling factor for an
8853 if (cur_token.code == '*')
8855 if (intel_match_token ('*') && cur_token.code == T_REG)
8857 const reg_entry *reg = cur_token.reg;
8859 if (!intel_parser.in_bracket)
8861 as_bad (_("Register scaling only allowed "
8862 "in memory operands"));
8866 /* Disallow things like [1*si].
8867 sp and esp are invalid as index. */
8868 if (reg->reg_type.bitfield.reg16)
8869 reg = i386_regtab + REGNAM_AX + 4;
8870 else if (i.index_reg)
8871 reg = i386_regtab + REGNAM_EAX + 4;
8873 /* The constant is followed by `* reg', so it must be
8876 i.types[this_operand].bitfield.baseindex = 1;
8878 /* Set the scale after setting the register (otherwise,
8879 i386_scale will complain) */
8880 if (!i386_scale (save_str))
8882 intel_match_token (T_REG);
8884 /* Since registers are not part of the displacement
8885 string, we may need to remove any preceding '+' from
8886 the displacement string. */
8887 if (*intel_parser.disp != '\0')
8889 char *s = intel_parser.disp;
8890 s += strlen (s) - 1;
8900 /* The constant was not used for register scaling. Since we have
8901 already consumed the token following `*' we now need to put it
8902 back in the stream. */
8903 intel_putback_token ();
8906 /* Add the constant to the displacement string. */
8907 strcat (intel_parser.disp, save_str);
8914 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8918 /* Match the given token against cur_token. If they match, read the next
8919 token from the operand string. */
8921 intel_match_token (int code)
8923 if (cur_token.code == code)
8930 as_bad (_("Unexpected token `%s'"), cur_token.str);
8935 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8937 intel_get_token (void)
8940 const reg_entry *reg;
8941 struct intel_token new_token;
8943 new_token.code = T_NIL;
8944 new_token.reg = NULL;
8945 new_token.str = NULL;
8947 /* Free the memory allocated to the previous token and move
8948 cur_token to prev_token. */
8950 free (prev_token.str);
8952 prev_token = cur_token;
8954 /* Skip whitespace. */
8955 while (is_space_char (*intel_parser.op_string))
8956 intel_parser.op_string++;
8958 /* Return an empty token if we find nothing else on the line. */
8959 if (*intel_parser.op_string == '\0')
8961 cur_token = new_token;
8965 /* The new token cannot be larger than the remainder of the operand
8967 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8968 new_token.str[0] = '\0';
8970 if (strchr ("0123456789", *intel_parser.op_string))
8972 char *p = new_token.str;
8973 char *q = intel_parser.op_string;
8974 new_token.code = T_CONST;
8976 /* Allow any kind of identifier char to encompass floating point and
8977 hexadecimal numbers. */
8978 while (is_identifier_char (*q))
8982 /* Recognize special symbol names [0-9][bf]. */
8983 if (strlen (intel_parser.op_string) == 2
8984 && (intel_parser.op_string[1] == 'b'
8985 || intel_parser.op_string[1] == 'f'))
8986 new_token.code = T_ID;
8989 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8991 size_t len = end_op - intel_parser.op_string;
8993 new_token.code = T_REG;
8994 new_token.reg = reg;
8996 memcpy (new_token.str, intel_parser.op_string, len);
8997 new_token.str[len] = '\0';
9000 else if (is_identifier_char (*intel_parser.op_string))
9002 char *p = new_token.str;
9003 char *q = intel_parser.op_string;
9005 /* A '.' or '$' followed by an identifier char is an identifier.
9006 Otherwise, it's operator '.' followed by an expression. */
9007 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9009 new_token.code = '.';
9010 new_token.str[0] = '.';
9011 new_token.str[1] = '\0';
9015 while (is_identifier_char (*q) || *q == '@')
9019 if (strcasecmp (new_token.str, "NOT") == 0)
9020 new_token.code = '~';
9022 else if (strcasecmp (new_token.str, "MOD") == 0)
9023 new_token.code = '%';
9025 else if (strcasecmp (new_token.str, "AND") == 0)
9026 new_token.code = '&';
9028 else if (strcasecmp (new_token.str, "OR") == 0)
9029 new_token.code = '|';
9031 else if (strcasecmp (new_token.str, "XOR") == 0)
9032 new_token.code = '^';
9034 else if (strcasecmp (new_token.str, "SHL") == 0)
9035 new_token.code = T_SHL;
9037 else if (strcasecmp (new_token.str, "SHR") == 0)
9038 new_token.code = T_SHR;
9040 else if (strcasecmp (new_token.str, "BYTE") == 0)
9041 new_token.code = T_BYTE;
9043 else if (strcasecmp (new_token.str, "WORD") == 0)
9044 new_token.code = T_WORD;
9046 else if (strcasecmp (new_token.str, "DWORD") == 0)
9047 new_token.code = T_DWORD;
9049 else if (strcasecmp (new_token.str, "FWORD") == 0)
9050 new_token.code = T_FWORD;
9052 else if (strcasecmp (new_token.str, "QWORD") == 0)
9053 new_token.code = T_QWORD;
9055 else if (strcasecmp (new_token.str, "TBYTE") == 0
9056 /* XXX remove (gcc still uses it) */
9057 || strcasecmp (new_token.str, "XWORD") == 0)
9058 new_token.code = T_TBYTE;
9060 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9061 || strcasecmp (new_token.str, "OWORD") == 0)
9062 new_token.code = T_XMMWORD;
9064 else if (strcasecmp (new_token.str, "PTR") == 0)
9065 new_token.code = T_PTR;
9067 else if (strcasecmp (new_token.str, "SHORT") == 0)
9068 new_token.code = T_SHORT;
9070 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9072 new_token.code = T_OFFSET;
9074 /* ??? This is not mentioned in the MASM grammar but gcc
9075 makes use of it with -mintel-syntax. OFFSET may be
9076 followed by FLAT: */
9077 if (strncasecmp (q, " FLAT:", 6) == 0)
9078 strcat (new_token.str, " FLAT:");
9081 /* ??? This is not mentioned in the MASM grammar. */
9082 else if (strcasecmp (new_token.str, "FLAT") == 0)
9084 new_token.code = T_OFFSET;
9086 strcat (new_token.str, ":");
9088 as_bad (_("`:' expected"));
9092 new_token.code = T_ID;
9096 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9098 new_token.code = *intel_parser.op_string;
9099 new_token.str[0] = *intel_parser.op_string;
9100 new_token.str[1] = '\0';
9103 else if (strchr ("<>", *intel_parser.op_string)
9104 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9106 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9107 new_token.str[0] = *intel_parser.op_string;
9108 new_token.str[1] = *intel_parser.op_string;
9109 new_token.str[2] = '\0';
9113 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9115 intel_parser.op_string += strlen (new_token.str);
9116 cur_token = new_token;
9119 /* Put cur_token back into the token stream and make cur_token point to
9122 intel_putback_token (void)
9124 if (cur_token.code != T_NIL)
9126 intel_parser.op_string -= strlen (cur_token.str);
9127 free (cur_token.str);
9129 cur_token = prev_token;
9131 /* Forget prev_token. */
9132 prev_token.code = T_NIL;
9133 prev_token.reg = NULL;
9134 prev_token.str = NULL;
9138 tc_x86_regname_to_dw2regnum (char *regname)
9140 unsigned int regnum;
9141 unsigned int regnames_count;
9142 static const char *const regnames_32[] =
9144 "eax", "ecx", "edx", "ebx",
9145 "esp", "ebp", "esi", "edi",
9146 "eip", "eflags", NULL,
9147 "st0", "st1", "st2", "st3",
9148 "st4", "st5", "st6", "st7",
9150 "xmm0", "xmm1", "xmm2", "xmm3",
9151 "xmm4", "xmm5", "xmm6", "xmm7",
9152 "mm0", "mm1", "mm2", "mm3",
9153 "mm4", "mm5", "mm6", "mm7",
9154 "fcw", "fsw", "mxcsr",
9155 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9158 static const char *const regnames_64[] =
9160 "rax", "rdx", "rcx", "rbx",
9161 "rsi", "rdi", "rbp", "rsp",
9162 "r8", "r9", "r10", "r11",
9163 "r12", "r13", "r14", "r15",
9165 "xmm0", "xmm1", "xmm2", "xmm3",
9166 "xmm4", "xmm5", "xmm6", "xmm7",
9167 "xmm8", "xmm9", "xmm10", "xmm11",
9168 "xmm12", "xmm13", "xmm14", "xmm15",
9169 "st0", "st1", "st2", "st3",
9170 "st4", "st5", "st6", "st7",
9171 "mm0", "mm1", "mm2", "mm3",
9172 "mm4", "mm5", "mm6", "mm7",
9174 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9175 "fs.base", "gs.base", NULL, NULL,
9177 "mxcsr", "fcw", "fsw"
9179 const char *const *regnames;
9181 if (flag_code == CODE_64BIT)
9183 regnames = regnames_64;
9184 regnames_count = ARRAY_SIZE (regnames_64);
9188 regnames = regnames_32;
9189 regnames_count = ARRAY_SIZE (regnames_32);
9192 for (regnum = 0; regnum < regnames_count; regnum++)
9193 if (regnames[regnum] != NULL
9194 && strcmp (regname, regnames[regnum]) == 0)
9201 tc_x86_frame_initial_instructions (void)
9203 static unsigned int sp_regno;
9206 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9209 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9210 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9214 i386_elf_section_type (const char *str, size_t len)
9216 if (flag_code == CODE_64BIT
9217 && len == sizeof ("unwind") - 1
9218 && strncmp (str, "unwind", 6) == 0)
9219 return SHT_X86_64_UNWIND;
9226 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9230 expr.X_op = O_secrel;
9231 expr.X_add_symbol = symbol;
9232 expr.X_add_number = 0;
9233 emit_expr (&expr, size);
9237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9238 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9241 x86_64_section_letter (int letter, char **ptr_msg)
9243 if (flag_code == CODE_64BIT)
9246 return SHF_X86_64_LARGE;
9248 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9251 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9256 x86_64_section_word (char *str, size_t len)
9258 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9259 return SHF_X86_64_LARGE;
9265 handle_large_common (int small ATTRIBUTE_UNUSED)
9267 if (flag_code != CODE_64BIT)
9269 s_comm_internal (0, elf_common_parse);
9270 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9274 static segT lbss_section;
9275 asection *saved_com_section_ptr = elf_com_section_ptr;
9276 asection *saved_bss_section = bss_section;
9278 if (lbss_section == NULL)
9280 flagword applicable;
9282 subsegT subseg = now_subseg;
9284 /* The .lbss section is for local .largecomm symbols. */
9285 lbss_section = subseg_new (".lbss", 0);
9286 applicable = bfd_applicable_section_flags (stdoutput);
9287 bfd_set_section_flags (stdoutput, lbss_section,
9288 applicable & SEC_ALLOC);
9289 seg_info (lbss_section)->bss = 1;
9291 subseg_set (seg, subseg);
9294 elf_com_section_ptr = &_bfd_elf_large_com_section;
9295 bss_section = lbss_section;
9297 s_comm_internal (0, elf_common_parse);
9299 elf_com_section_ptr = saved_com_section_ptr;
9300 bss_section = saved_bss_section;
9303 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */