1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
266 unsupported_with_intel_mnemonic,
269 invalid_vsib_address,
270 invalid_vector_register_set,
271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
276 mask_not_on_destination,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
285 /* TM holds the template for the insn were currently assembling. */
288 /* SUFFIX holds the instruction size suffix for byte, word, dword
289 or qword, if given. */
292 /* OPERANDS gives the number of given operands. */
293 unsigned int operands;
295 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
296 of given register, displacement, memory operands and immediate
298 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
300 /* TYPES [i] is the type (see above #defines) which tells us how to
301 use OP[i] for the corresponding operand. */
302 i386_operand_type types[MAX_OPERANDS];
304 /* Displacement expression, immediate expression, or register for each
306 union i386_op op[MAX_OPERANDS];
308 /* Flags for operands. */
309 unsigned int flags[MAX_OPERANDS];
310 #define Operand_PCrel 1
312 /* Relocation type for operand */
313 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
315 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
316 the base index byte below. */
317 const reg_entry *base_reg;
318 const reg_entry *index_reg;
319 unsigned int log2_scale_factor;
321 /* SEG gives the seg_entries of this insn. They are zero unless
322 explicit segment overrides are given. */
323 const seg_entry *seg[2];
325 /* Copied first memory operand string, for re-checking. */
328 /* PREFIX holds all the given prefix opcodes (usually null).
329 PREFIXES is the number of prefix opcodes. */
330 unsigned int prefixes;
331 unsigned char prefix[MAX_PREFIXES];
333 /* RM and SIB are the modrm byte and the sib byte where the
334 addressing modes of this insn are encoded. */
341 /* Masking attributes. */
342 struct Mask_Operation *mask;
344 /* Rounding control and SAE attributes. */
345 struct RC_Operation *rounding;
347 /* Broadcasting attributes. */
348 struct Broadcast_Operation *broadcast;
350 /* Compressed disp8*N attribute. */
351 unsigned int memshift;
353 /* Prefer load or store in encoding. */
356 dir_encoding_default = 0,
361 /* Prefer 8bit or 32bit displacement in encoding. */
364 disp_encoding_default = 0,
369 /* Prefer the REX byte in encoding. */
370 bfd_boolean rex_encoding;
372 /* Disable instruction size optimization. */
373 bfd_boolean no_optimize;
375 /* How to encode vector instructions. */
378 vex_encoding_default = 0,
385 const char *rep_prefix;
388 const char *hle_prefix;
390 /* Have BND prefix. */
391 const char *bnd_prefix;
393 /* Have NOTRACK prefix. */
394 const char *notrack_prefix;
397 enum i386_error error;
400 typedef struct _i386_insn i386_insn;
402 /* Link RC type with corresponding string, that'll be looked for in
411 static const struct RC_name RC_NamesTable[] =
413 { rne, STRING_COMMA_LEN ("rn-sae") },
414 { rd, STRING_COMMA_LEN ("rd-sae") },
415 { ru, STRING_COMMA_LEN ("ru-sae") },
416 { rz, STRING_COMMA_LEN ("rz-sae") },
417 { saeonly, STRING_COMMA_LEN ("sae") },
420 /* List of chars besides those in app.c:symbol_chars that can start an
421 operand. Used to prevent the scrubber eating vital white-space. */
422 const char extra_symbol_chars[] = "*%-([{}"
431 #if (defined (TE_I386AIX) \
432 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
433 && !defined (TE_GNU) \
434 && !defined (TE_LINUX) \
435 && !defined (TE_NACL) \
436 && !defined (TE_NETWARE) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars = "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars = "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars[] = "#/";
462 const char line_separator_chars[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars[256];
475 static char register_chars[256];
476 static char operand_chars[256];
477 static char identifier_chars[256];
478 static char digit_chars[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack[32];
496 static char *save_stack_p;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates *current_templates;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
510 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
512 /* Current operand we are working on. */
513 static int this_operand = -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code;
524 static unsigned int object_64bit;
525 static unsigned int disallow_64bit_reloc;
526 static int use_rela_relocations = 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi = I386_ABI;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj = 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared = 0;
553 /* 1 for intel syntax,
555 static int intel_syntax = 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic = !SYSV386_COMPAT;
565 /* 1 if support old (<= 2.8.1) versions of gcc. */
566 static int old_gcc = OLDGCC_COMPAT;
568 /* 1 if pseudo registers are permitted. */
569 static int allow_pseudo_reg = 0;
571 /* 1 if register prefix % not required. */
572 static int allow_naked_reg = 0;
574 /* 1 if the assembler should add BND prefix for all control-transferring
575 instructions supporting it, even if this prefix wasn't specified
577 static int add_bnd_prefix = 0;
579 /* 1 if pseudo index register, eiz/riz, is allowed . */
580 static int allow_index_reg = 0;
582 /* 1 if the assembler should ignore LOCK prefix, even if it was
583 specified explicitly. */
584 static int omit_lock_prefix = 0;
586 /* 1 if the assembler should encode lfence, mfence, and sfence as
587 "lock addl $0, (%{re}sp)". */
588 static int avoid_fence = 0;
590 /* 1 if the assembler should generate relax relocations. */
592 static int generate_relax_relocations
593 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
595 static enum check_kind
601 sse_check, operand_check = check_warning;
604 1. Clear the REX_W bit with register operand if possible.
605 2. Above plus use 128bit vector instruction to clear the full vector
608 static int optimize = 0;
611 1. Clear the REX_W bit with register operand if possible.
612 2. Above plus use 128bit vector instruction to clear the full vector
614 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
617 static int optimize_for_space = 0;
619 /* Register prefix used for error message. */
620 static const char *register_prefix = "%";
622 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
623 leave, push, and pop instructions so that gcc has the same stack
624 frame as in 32 bit mode. */
625 static char stackop_size = '\0';
627 /* Non-zero to optimize code alignment. */
628 int optimize_align_code = 1;
630 /* Non-zero to quieten some warnings. */
631 static int quiet_warnings = 0;
634 static const char *cpu_arch_name = NULL;
635 static char *cpu_sub_arch_name = NULL;
637 /* CPU feature flags. */
638 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
640 /* If we have selected a cpu we are generating instructions for. */
641 static int cpu_arch_tune_set = 0;
643 /* Cpu we are generating instructions for. */
644 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
646 /* CPU feature flags of cpu we are generating instructions for. */
647 static i386_cpu_flags cpu_arch_tune_flags;
649 /* CPU instruction set architecture used. */
650 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
652 /* CPU feature flags of instruction set architecture used. */
653 i386_cpu_flags cpu_arch_isa_flags;
655 /* If set, conditional jumps are not automatically promoted to handle
656 larger than a byte offset. */
657 static unsigned int no_cond_jump_promotion = 0;
659 /* Encode SSE instructions with VEX prefix. */
660 static unsigned int sse2avx;
662 /* Encode scalar AVX instructions with specific vector length. */
669 /* Encode scalar EVEX LIG instructions with specific vector length. */
677 /* Encode EVEX WIG instructions with specific evex.w. */
684 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
685 static enum rc_type evexrcig = rne;
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 static symbolS *GOT_symbol;
690 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
691 unsigned int x86_dwarf2_return_column;
693 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
694 int x86_cie_data_alignment;
696 /* Interface to relax_segment.
697 There are 3 major relax states for 386 jump insns because the
698 different types of jumps add different sizes to frags when we're
699 figuring out what sort of jump to choose to reach a given label. */
702 #define UNCOND_JUMP 0
704 #define COND_JUMP86 2
709 #define SMALL16 (SMALL | CODE16)
711 #define BIG16 (BIG | CODE16)
715 #define INLINE __inline__
721 #define ENCODE_RELAX_STATE(type, size) \
722 ((relax_substateT) (((type) << 2) | (size)))
723 #define TYPE_FROM_RELAX_STATE(s) \
725 #define DISP_SIZE_FROM_RELAX_STATE(s) \
726 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
728 /* This table is used by relax_frag to promote short jumps to long
729 ones where necessary. SMALL (short) jumps may be promoted to BIG
730 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
731 don't allow a short jump in a 32 bit code segment to be promoted to
732 a 16 bit offset jump because it's slower (requires data size
733 prefix), and doesn't work, unless the destination is in the bottom
734 64k of the code segment (The top 16 bits of eip are zeroed). */
736 const relax_typeS md_relax_table[] =
739 1) most positive reach of this state,
740 2) most negative reach of this state,
741 3) how many bytes this mode will have in the variable part of the frag
742 4) which index into the table to try if we can't fit into this one. */
744 /* UNCOND_JUMP states. */
745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
747 /* dword jmp adds 4 bytes to frag:
748 0 extra opcode bytes, 4 displacement bytes. */
750 /* word jmp adds 2 byte2 to frag:
751 0 extra opcode bytes, 2 displacement bytes. */
754 /* COND_JUMP states. */
755 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
756 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
757 /* dword conditionals adds 5 bytes to frag:
758 1 extra opcode byte, 4 displacement bytes. */
760 /* word conditionals add 3 bytes to frag:
761 1 extra opcode byte, 2 displacement bytes. */
764 /* COND_JUMP86 states. */
765 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
766 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
767 /* dword conditionals adds 5 bytes to frag:
768 1 extra opcode byte, 4 displacement bytes. */
770 /* word conditionals add 4 bytes to frag:
771 1 displacement byte and a 3 byte long branch insn. */
775 static const arch_entry cpu_arch[] =
777 /* Do not replace the first two entries - i386_target_format()
778 relies on them being there in this order. */
779 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
780 CPU_GENERIC32_FLAGS, 0 },
781 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
782 CPU_GENERIC64_FLAGS, 0 },
783 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
785 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
787 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
789 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
791 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
793 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
795 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
797 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
799 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
800 CPU_PENTIUMPRO_FLAGS, 0 },
801 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
803 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
805 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
807 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
809 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
810 CPU_NOCONA_FLAGS, 0 },
811 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
813 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
815 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
816 CPU_CORE2_FLAGS, 1 },
817 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
818 CPU_CORE2_FLAGS, 0 },
819 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
820 CPU_COREI7_FLAGS, 0 },
821 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
823 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
825 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
826 CPU_IAMCU_FLAGS, 0 },
827 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
829 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
831 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
832 CPU_ATHLON_FLAGS, 0 },
833 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
835 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
837 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
839 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
840 CPU_AMDFAM10_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
842 CPU_BDVER1_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
844 CPU_BDVER2_FLAGS, 0 },
845 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
846 CPU_BDVER3_FLAGS, 0 },
847 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
848 CPU_BDVER4_FLAGS, 0 },
849 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
850 CPU_ZNVER1_FLAGS, 0 },
851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
852 CPU_BTVER1_FLAGS, 0 },
853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
854 CPU_BTVER2_FLAGS, 0 },
855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
869 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
871 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
872 CPU_SSSE3_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_1_FLAGS, 0 },
875 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
876 CPU_SSE4_2_FLAGS, 0 },
877 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
878 CPU_SSE4_2_FLAGS, 0 },
879 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
881 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
883 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
884 CPU_AVX512F_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
886 CPU_AVX512CD_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
888 CPU_AVX512ER_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
890 CPU_AVX512PF_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
892 CPU_AVX512DQ_FLAGS, 0 },
893 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
894 CPU_AVX512BW_FLAGS, 0 },
895 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
896 CPU_AVX512VL_FLAGS, 0 },
897 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
900 CPU_VMFUNC_FLAGS, 0 },
901 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
903 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
904 CPU_XSAVE_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
906 CPU_XSAVEOPT_FLAGS, 0 },
907 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
908 CPU_XSAVEC_FLAGS, 0 },
909 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
910 CPU_XSAVES_FLAGS, 0 },
911 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
913 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
914 CPU_PCLMUL_FLAGS, 0 },
915 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
916 CPU_PCLMUL_FLAGS, 1 },
917 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
918 CPU_FSGSBASE_FLAGS, 0 },
919 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
920 CPU_RDRND_FLAGS, 0 },
921 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
931 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
934 CPU_MOVBE_FLAGS, 0 },
935 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
937 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
940 CPU_LZCNT_FLAGS, 0 },
941 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
943 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
945 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
946 CPU_INVPCID_FLAGS, 0 },
947 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
948 CPU_CLFLUSH_FLAGS, 0 },
949 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
951 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
952 CPU_SYSCALL_FLAGS, 0 },
953 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
954 CPU_RDTSCP_FLAGS, 0 },
955 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
956 CPU_3DNOW_FLAGS, 0 },
957 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
958 CPU_3DNOWA_FLAGS, 0 },
959 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
960 CPU_PADLOCK_FLAGS, 0 },
961 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
963 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
966 CPU_SSE4A_FLAGS, 0 },
967 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
973 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
975 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
976 CPU_RDSEED_FLAGS, 0 },
977 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
978 CPU_PRFCHW_FLAGS, 0 },
979 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
983 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
985 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
986 CPU_CLFLUSHOPT_FLAGS, 0 },
987 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
988 CPU_PREFETCHWT1_FLAGS, 0 },
989 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
991 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
993 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
994 CPU_AVX512IFMA_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
996 CPU_AVX512VBMI_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_4FMAPS_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_4VNNIW_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_VBMI2_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1006 CPU_AVX512_VNNI_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1008 CPU_AVX512_BITALG_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1010 CPU_CLZERO_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1012 CPU_MWAITX_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1014 CPU_OSPKE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1016 CPU_RDPID_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1018 CPU_PTWRITE_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1021 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1022 CPU_SHSTK_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1024 CPU_GFNI_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1026 CPU_VAES_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1028 CPU_VPCLMULQDQ_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1030 CPU_WBNOINVD_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1032 CPU_PCONFIG_FLAGS, 0 },
1035 static const noarch_entry cpu_noarch[] =
1037 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1038 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1039 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1040 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1041 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1042 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1043 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1048 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1049 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1050 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1066 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1067 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1071 /* Like s_lcomm_internal in gas/read.c but the alignment string
1072 is allowed to be optional. */
1075 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1082 && *input_line_pointer == ',')
1084 align = parse_align (needs_align - 1);
1086 if (align == (addressT) -1)
1101 bss_alloc (symbolP, size, align);
1106 pe_lcomm (int needs_align)
1108 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1112 const pseudo_typeS md_pseudo_table[] =
1114 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1115 {"align", s_align_bytes, 0},
1117 {"align", s_align_ptwo, 0},
1119 {"arch", set_cpu_arch, 0},
1123 {"lcomm", pe_lcomm, 1},
1125 {"ffloat", float_cons, 'f'},
1126 {"dfloat", float_cons, 'd'},
1127 {"tfloat", float_cons, 'x'},
1129 {"slong", signed_cons, 4},
1130 {"noopt", s_ignore, 0},
1131 {"optim", s_ignore, 0},
1132 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1133 {"code16", set_code_flag, CODE_16BIT},
1134 {"code32", set_code_flag, CODE_32BIT},
1136 {"code64", set_code_flag, CODE_64BIT},
1138 {"intel_syntax", set_intel_syntax, 1},
1139 {"att_syntax", set_intel_syntax, 0},
1140 {"intel_mnemonic", set_intel_mnemonic, 1},
1141 {"att_mnemonic", set_intel_mnemonic, 0},
1142 {"allow_index_reg", set_allow_index_reg, 1},
1143 {"disallow_index_reg", set_allow_index_reg, 0},
1144 {"sse_check", set_check, 0},
1145 {"operand_check", set_check, 1},
1146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1147 {"largecomm", handle_large_common, 0},
1149 {"file", dwarf2_directive_file, 0},
1150 {"loc", dwarf2_directive_loc, 0},
1151 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1154 {"secrel32", pe_directive_secrel, 0},
1159 /* For interface with expression (). */
1160 extern char *input_line_pointer;
1162 /* Hash table for instruction mnemonic lookup. */
1163 static struct hash_control *op_hash;
1165 /* Hash table for register lookup. */
1166 static struct hash_control *reg_hash;
1168 /* Various efficient no-op patterns for aligning code labels.
1169 Note: Don't try to assemble the instructions in the comments.
1170 0L and 0w are not legal. */
1171 static const unsigned char f32_1[] =
1173 static const unsigned char f32_2[] =
1174 {0x66,0x90}; /* xchg %ax,%ax */
1175 static const unsigned char f32_3[] =
1176 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1177 static const unsigned char f32_4[] =
1178 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1179 static const unsigned char f32_6[] =
1180 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1181 static const unsigned char f32_7[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1183 static const unsigned char f16_3[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1185 static const unsigned char f16_4[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1187 static const unsigned char jump_disp8[] =
1188 {0xeb}; /* jmp disp8 */
1189 static const unsigned char jump32_disp32[] =
1190 {0xe9}; /* jmp disp32 */
1191 static const unsigned char jump16_disp32[] =
1192 {0x66,0xe9}; /* jmp disp32 */
1193 /* 32-bit NOPs patterns. */
1194 static const unsigned char *const f32_patt[] = {
1195 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1197 /* 16-bit NOPs patterns. */
1198 static const unsigned char *const f16_patt[] = {
1199 f32_1, f32_2, f16_3, f16_4
1201 /* nopl (%[re]ax) */
1202 static const unsigned char alt_3[] =
1204 /* nopl 0(%[re]ax) */
1205 static const unsigned char alt_4[] =
1206 {0x0f,0x1f,0x40,0x00};
1207 /* nopl 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_5[] =
1209 {0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopw 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_6[] =
1212 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopl 0L(%[re]ax) */
1214 static const unsigned char alt_7[] =
1215 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1216 /* nopl 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_8[] =
1218 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_9[] =
1221 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_10[] =
1224 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* data16 nopw %cs:0L(%eax,%eax,1) */
1226 static const unsigned char alt_11[] =
1227 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* 32-bit and 64-bit NOPs patterns. */
1229 static const unsigned char *const alt_patt[] = {
1230 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1231 alt_9, alt_10, alt_11
1234 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1235 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1238 i386_output_nops (char *where, const unsigned char *const *patt,
1239 int count, int max_single_nop_size)
1242 /* Place the longer NOP first. */
1245 const unsigned char *nops = patt[max_single_nop_size - 1];
1247 /* Use the smaller one if the requsted one isn't available. */
1250 max_single_nop_size--;
1251 nops = patt[max_single_nop_size - 1];
1254 last = count % max_single_nop_size;
1257 for (offset = 0; offset < count; offset += max_single_nop_size)
1258 memcpy (where + offset, nops, max_single_nop_size);
1262 nops = patt[last - 1];
1265 /* Use the smaller one plus one-byte NOP if the needed one
1268 nops = patt[last - 1];
1269 memcpy (where + offset, nops, last);
1270 where[offset + last] = *patt[0];
1273 memcpy (where + offset, nops, last);
1278 fits_in_imm7 (offsetT num)
1280 return (num & 0x7f) == num;
1284 fits_in_imm31 (offsetT num)
1286 return (num & 0x7fffffff) == num;
1289 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1290 single NOP instruction LIMIT. */
1293 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1295 const unsigned char *const *patt = NULL;
1296 int max_single_nop_size;
1297 /* Maximum number of NOPs before switching to jump over NOPs. */
1298 int max_number_of_nops;
1300 switch (fragP->fr_type)
1309 /* We need to decide which NOP sequence to use for 32bit and
1310 64bit. When -mtune= is used:
1312 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1313 PROCESSOR_GENERIC32, f32_patt will be used.
1314 2. For the rest, alt_patt will be used.
1316 When -mtune= isn't used, alt_patt will be used if
1317 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1320 When -march= or .arch is used, we can't use anything beyond
1321 cpu_arch_isa_flags. */
1323 if (flag_code == CODE_16BIT)
1326 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1327 /* Limit number of NOPs to 2 in 16-bit mode. */
1328 max_number_of_nops = 2;
1332 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1334 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1335 switch (cpu_arch_tune)
1337 case PROCESSOR_UNKNOWN:
1338 /* We use cpu_arch_isa_flags to check if we SHOULD
1339 optimize with nops. */
1340 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
1348 case PROCESSOR_CORE2:
1349 case PROCESSOR_COREI7:
1350 case PROCESSOR_L1OM:
1351 case PROCESSOR_K1OM:
1352 case PROCESSOR_GENERIC64:
1354 case PROCESSOR_ATHLON:
1356 case PROCESSOR_AMDFAM10:
1358 case PROCESSOR_ZNVER:
1362 case PROCESSOR_I386:
1363 case PROCESSOR_I486:
1364 case PROCESSOR_PENTIUM:
1365 case PROCESSOR_PENTIUMPRO:
1366 case PROCESSOR_IAMCU:
1367 case PROCESSOR_GENERIC32:
1374 switch (fragP->tc_frag_data.tune)
1376 case PROCESSOR_UNKNOWN:
1377 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1378 PROCESSOR_UNKNOWN. */
1382 case PROCESSOR_I386:
1383 case PROCESSOR_I486:
1384 case PROCESSOR_PENTIUM:
1385 case PROCESSOR_IAMCU:
1387 case PROCESSOR_ATHLON:
1389 case PROCESSOR_AMDFAM10:
1391 case PROCESSOR_ZNVER:
1393 case PROCESSOR_GENERIC32:
1394 /* We use cpu_arch_isa_flags to check if we CAN optimize
1396 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1401 case PROCESSOR_PENTIUMPRO:
1402 case PROCESSOR_PENTIUM4:
1403 case PROCESSOR_NOCONA:
1404 case PROCESSOR_CORE:
1405 case PROCESSOR_CORE2:
1406 case PROCESSOR_COREI7:
1407 case PROCESSOR_L1OM:
1408 case PROCESSOR_K1OM:
1409 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1414 case PROCESSOR_GENERIC64:
1420 if (patt == f32_patt)
1422 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1423 /* Limit number of NOPs to 2 for older processors. */
1424 max_number_of_nops = 2;
1428 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1429 /* Limit number of NOPs to 7 for newer processors. */
1430 max_number_of_nops = 7;
1435 limit = max_single_nop_size;
1437 if (fragP->fr_type == rs_fill_nop)
1439 /* Output NOPs for .nop directive. */
1440 if (limit > max_single_nop_size)
1442 as_bad_where (fragP->fr_file, fragP->fr_line,
1443 _("invalid single nop size: %d "
1444 "(expect within [0, %d])"),
1445 limit, max_single_nop_size);
1450 fragP->fr_var = count;
1452 if ((count / max_single_nop_size) > max_number_of_nops)
1454 /* Generate jump over NOPs. */
1455 offsetT disp = count - 2;
1456 if (fits_in_imm7 (disp))
1458 /* Use "jmp disp8" if possible. */
1460 where[0] = jump_disp8[0];
1466 unsigned int size_of_jump;
1468 if (flag_code == CODE_16BIT)
1470 where[0] = jump16_disp32[0];
1471 where[1] = jump16_disp32[1];
1476 where[0] = jump32_disp32[0];
1480 count -= size_of_jump + 4;
1481 if (!fits_in_imm31 (count))
1483 as_bad_where (fragP->fr_file, fragP->fr_line,
1484 _("jump over nop padding out of range"));
1488 md_number_to_chars (where + size_of_jump, count, 4);
1489 where += size_of_jump + 4;
1493 /* Generate multiple NOPs. */
1494 i386_output_nops (where, patt, count, limit);
1498 operand_type_all_zero (const union i386_operand_type *x)
1500 switch (ARRAY_SIZE(x->array))
1511 return !x->array[0];
1518 operand_type_set (union i386_operand_type *x, unsigned int v)
1520 switch (ARRAY_SIZE(x->array))
1538 operand_type_equal (const union i386_operand_type *x,
1539 const union i386_operand_type *y)
1541 switch (ARRAY_SIZE(x->array))
1544 if (x->array[2] != y->array[2])
1548 if (x->array[1] != y->array[1])
1552 return x->array[0] == y->array[0];
1560 cpu_flags_all_zero (const union i386_cpu_flags *x)
1562 switch (ARRAY_SIZE(x->array))
1577 return !x->array[0];
1584 cpu_flags_equal (const union i386_cpu_flags *x,
1585 const union i386_cpu_flags *y)
1587 switch (ARRAY_SIZE(x->array))
1590 if (x->array[3] != y->array[3])
1594 if (x->array[2] != y->array[2])
1598 if (x->array[1] != y->array[1])
1602 return x->array[0] == y->array[0];
1610 cpu_flags_check_cpu64 (i386_cpu_flags f)
1612 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1613 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1616 static INLINE i386_cpu_flags
1617 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1619 switch (ARRAY_SIZE (x.array))
1622 x.array [3] &= y.array [3];
1625 x.array [2] &= y.array [2];
1628 x.array [1] &= y.array [1];
1631 x.array [0] &= y.array [0];
1639 static INLINE i386_cpu_flags
1640 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1642 switch (ARRAY_SIZE (x.array))
1645 x.array [3] |= y.array [3];
1648 x.array [2] |= y.array [2];
1651 x.array [1] |= y.array [1];
1654 x.array [0] |= y.array [0];
1662 static INLINE i386_cpu_flags
1663 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1665 switch (ARRAY_SIZE (x.array))
1668 x.array [3] &= ~y.array [3];
1671 x.array [2] &= ~y.array [2];
1674 x.array [1] &= ~y.array [1];
1677 x.array [0] &= ~y.array [0];
1685 #define CPU_FLAGS_ARCH_MATCH 0x1
1686 #define CPU_FLAGS_64BIT_MATCH 0x2
1688 #define CPU_FLAGS_PERFECT_MATCH \
1689 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1691 /* Return CPU flags match bits. */
1694 cpu_flags_match (const insn_template *t)
1696 i386_cpu_flags x = t->cpu_flags;
1697 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1699 x.bitfield.cpu64 = 0;
1700 x.bitfield.cpuno64 = 0;
1702 if (cpu_flags_all_zero (&x))
1704 /* This instruction is available on all archs. */
1705 match |= CPU_FLAGS_ARCH_MATCH;
1709 /* This instruction is available only on some archs. */
1710 i386_cpu_flags cpu = cpu_arch_flags;
1712 /* AVX512VL is no standalone feature - match it and then strip it. */
1713 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1715 x.bitfield.cpuavx512vl = 0;
1717 cpu = cpu_flags_and (x, cpu);
1718 if (!cpu_flags_all_zero (&cpu))
1720 if (x.bitfield.cpuavx)
1722 /* We need to check a few extra flags with AVX. */
1723 if (cpu.bitfield.cpuavx
1724 && (!t->opcode_modifier.sse2avx || sse2avx)
1725 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1726 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1727 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1728 match |= CPU_FLAGS_ARCH_MATCH;
1730 else if (x.bitfield.cpuavx512f)
1732 /* We need to check a few extra flags with AVX512F. */
1733 if (cpu.bitfield.cpuavx512f
1734 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1735 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1736 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1737 match |= CPU_FLAGS_ARCH_MATCH;
1740 match |= CPU_FLAGS_ARCH_MATCH;
1746 static INLINE i386_operand_type
1747 operand_type_and (i386_operand_type x, i386_operand_type y)
1749 switch (ARRAY_SIZE (x.array))
1752 x.array [2] &= y.array [2];
1755 x.array [1] &= y.array [1];
1758 x.array [0] &= y.array [0];
1766 static INLINE i386_operand_type
1767 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1769 switch (ARRAY_SIZE (x.array))
1772 x.array [2] &= ~y.array [2];
1775 x.array [1] &= ~y.array [1];
1778 x.array [0] &= ~y.array [0];
1786 static INLINE i386_operand_type
1787 operand_type_or (i386_operand_type x, i386_operand_type y)
1789 switch (ARRAY_SIZE (x.array))
1792 x.array [2] |= y.array [2];
1795 x.array [1] |= y.array [1];
1798 x.array [0] |= y.array [0];
1806 static INLINE i386_operand_type
1807 operand_type_xor (i386_operand_type x, i386_operand_type y)
1809 switch (ARRAY_SIZE (x.array))
1812 x.array [2] ^= y.array [2];
1815 x.array [1] ^= y.array [1];
1818 x.array [0] ^= y.array [0];
1826 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1827 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1828 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1829 static const i386_operand_type inoutportreg
1830 = OPERAND_TYPE_INOUTPORTREG;
1831 static const i386_operand_type reg16_inoutportreg
1832 = OPERAND_TYPE_REG16_INOUTPORTREG;
1833 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1834 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1835 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1836 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1837 static const i386_operand_type anydisp
1838 = OPERAND_TYPE_ANYDISP;
1839 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1840 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1841 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1842 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1843 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1844 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1845 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1846 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1847 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1848 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1849 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1850 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1861 operand_type_check (i386_operand_type t, enum operand_type c)
1866 return t.bitfield.reg;
1869 return (t.bitfield.imm8
1873 || t.bitfield.imm32s
1874 || t.bitfield.imm64);
1877 return (t.bitfield.disp8
1878 || t.bitfield.disp16
1879 || t.bitfield.disp32
1880 || t.bitfield.disp32s
1881 || t.bitfield.disp64);
1884 return (t.bitfield.disp8
1885 || t.bitfield.disp16
1886 || t.bitfield.disp32
1887 || t.bitfield.disp32s
1888 || t.bitfield.disp64
1889 || t.bitfield.baseindex);
1898 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1899 operand J for instruction template T. */
1902 match_reg_size (const insn_template *t, unsigned int j)
1904 return !((i.types[j].bitfield.byte
1905 && !t->operand_types[j].bitfield.byte)
1906 || (i.types[j].bitfield.word
1907 && !t->operand_types[j].bitfield.word)
1908 || (i.types[j].bitfield.dword
1909 && !t->operand_types[j].bitfield.dword)
1910 || (i.types[j].bitfield.qword
1911 && !t->operand_types[j].bitfield.qword)
1912 || (i.types[j].bitfield.tbyte
1913 && !t->operand_types[j].bitfield.tbyte));
1916 /* Return 1 if there is no conflict in SIMD register on
1917 operand J for instruction template T. */
1920 match_simd_size (const insn_template *t, unsigned int j)
1922 return !((i.types[j].bitfield.xmmword
1923 && !t->operand_types[j].bitfield.xmmword)
1924 || (i.types[j].bitfield.ymmword
1925 && !t->operand_types[j].bitfield.ymmword)
1926 || (i.types[j].bitfield.zmmword
1927 && !t->operand_types[j].bitfield.zmmword));
1930 /* Return 1 if there is no conflict in any size on operand J for
1931 instruction template T. */
1934 match_mem_size (const insn_template *t, unsigned int j)
1936 return (match_reg_size (t, j)
1937 && !((i.types[j].bitfield.unspecified
1939 && !t->operand_types[j].bitfield.unspecified)
1940 || (i.types[j].bitfield.fword
1941 && !t->operand_types[j].bitfield.fword)
1942 /* For scalar opcode templates to allow register and memory
1943 operands at the same time, some special casing is needed
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.dword
1948 || t->operand_types[j].bitfield.qword))
1949 ? (i.types[j].bitfield.xmmword
1950 || i.types[j].bitfield.ymmword
1951 || i.types[j].bitfield.zmmword)
1952 : !match_simd_size(t, j))));
1955 /* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1959 operand_size_match (const insn_template *t)
1964 /* Don't check jump instructions. */
1965 if (t->opcode_modifier.jump
1966 || t->opcode_modifier.jumpbyte
1967 || t->opcode_modifier.jumpdword
1968 || t->opcode_modifier.jumpintersegment)
1971 /* Check memory and accumulator operand size. */
1972 for (j = 0; j < i.operands; j++)
1974 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1975 && t->operand_types[j].bitfield.anysize)
1978 if (t->operand_types[j].bitfield.reg
1979 && !match_reg_size (t, j))
1985 if (t->operand_types[j].bitfield.regsimd
1986 && !match_simd_size (t, j))
1992 if (t->operand_types[j].bitfield.acc
1993 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1999 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2008 else if (!t->opcode_modifier.d)
2011 i.error = operand_size_mismatch;
2015 /* Check reverse. */
2016 gas_assert (i.operands == 2);
2019 for (j = 0; j < 2; j++)
2021 if ((t->operand_types[j].bitfield.reg
2022 || t->operand_types[j].bitfield.acc)
2023 && !match_reg_size (t, j ? 0 : 1))
2026 if (i.types[j].bitfield.mem
2027 && !match_mem_size (t, j ? 0 : 1))
2035 operand_type_match (i386_operand_type overlap,
2036 i386_operand_type given)
2038 i386_operand_type temp = overlap;
2040 temp.bitfield.jumpabsolute = 0;
2041 temp.bitfield.unspecified = 0;
2042 temp.bitfield.byte = 0;
2043 temp.bitfield.word = 0;
2044 temp.bitfield.dword = 0;
2045 temp.bitfield.fword = 0;
2046 temp.bitfield.qword = 0;
2047 temp.bitfield.tbyte = 0;
2048 temp.bitfield.xmmword = 0;
2049 temp.bitfield.ymmword = 0;
2050 temp.bitfield.zmmword = 0;
2051 if (operand_type_all_zero (&temp))
2054 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2055 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2059 i.error = operand_type_mismatch;
2063 /* If given types g0 and g1 are registers they must be of the same type
2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2069 operand_type_register_match (i386_operand_type g0,
2070 i386_operand_type t0,
2071 i386_operand_type g1,
2072 i386_operand_type t1)
2074 if (!g0.bitfield.reg
2075 && !g0.bitfield.regsimd
2076 && (!operand_type_check (g0, anymem)
2077 || g0.bitfield.unspecified
2078 || !t0.bitfield.regsimd))
2081 if (!g1.bitfield.reg
2082 && !g1.bitfield.regsimd
2083 && (!operand_type_check (g1, anymem)
2084 || g1.bitfield.unspecified
2085 || !t1.bitfield.regsimd))
2088 if (g0.bitfield.byte == g1.bitfield.byte
2089 && g0.bitfield.word == g1.bitfield.word
2090 && g0.bitfield.dword == g1.bitfield.dword
2091 && g0.bitfield.qword == g1.bitfield.qword
2092 && g0.bitfield.xmmword == g1.bitfield.xmmword
2093 && g0.bitfield.ymmword == g1.bitfield.ymmword
2094 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2097 if (!(t0.bitfield.byte & t1.bitfield.byte)
2098 && !(t0.bitfield.word & t1.bitfield.word)
2099 && !(t0.bitfield.dword & t1.bitfield.dword)
2100 && !(t0.bitfield.qword & t1.bitfield.qword)
2101 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2102 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2103 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2106 i.error = register_type_mismatch;
2111 static INLINE unsigned int
2112 register_number (const reg_entry *r)
2114 unsigned int nr = r->reg_num;
2116 if (r->reg_flags & RegRex)
2119 if (r->reg_flags & RegVRex)
2125 static INLINE unsigned int
2126 mode_from_disp_size (i386_operand_type t)
2128 if (t.bitfield.disp8)
2130 else if (t.bitfield.disp16
2131 || t.bitfield.disp32
2132 || t.bitfield.disp32s)
2139 fits_in_signed_byte (addressT num)
2141 return num + 0x80 <= 0xff;
2145 fits_in_unsigned_byte (addressT num)
2151 fits_in_unsigned_word (addressT num)
2153 return num <= 0xffff;
2157 fits_in_signed_word (addressT num)
2159 return num + 0x8000 <= 0xffff;
2163 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2168 return num + 0x80000000 <= 0xffffffff;
2170 } /* fits_in_signed_long() */
2173 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2178 return num <= 0xffffffff;
2180 } /* fits_in_unsigned_long() */
2183 fits_in_disp8 (offsetT num)
2185 int shift = i.memshift;
2191 mask = (1 << shift) - 1;
2193 /* Return 0 if NUM isn't properly aligned. */
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num >> shift);
2202 fits_in_imm4 (offsetT num)
2204 return (num & 0xf) == num;
2207 static i386_operand_type
2208 smallest_imm_type (offsetT num)
2210 i386_operand_type t;
2212 operand_type_set (&t, 0);
2213 t.bitfield.imm64 = 1;
2215 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2217 /* This code is disabled on the 486 because all the Imm1 forms
2218 in the opcode table are slower on the i486. They're the
2219 versions with the implicitly specified single-position
2220 displacement, which has another syntax if you really want to
2222 t.bitfield.imm1 = 1;
2223 t.bitfield.imm8 = 1;
2224 t.bitfield.imm8s = 1;
2225 t.bitfield.imm16 = 1;
2226 t.bitfield.imm32 = 1;
2227 t.bitfield.imm32s = 1;
2229 else if (fits_in_signed_byte (num))
2231 t.bitfield.imm8 = 1;
2232 t.bitfield.imm8s = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2237 else if (fits_in_unsigned_byte (num))
2239 t.bitfield.imm8 = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2244 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2246 t.bitfield.imm16 = 1;
2247 t.bitfield.imm32 = 1;
2248 t.bitfield.imm32s = 1;
2250 else if (fits_in_signed_long (num))
2252 t.bitfield.imm32 = 1;
2253 t.bitfield.imm32s = 1;
2255 else if (fits_in_unsigned_long (num))
2256 t.bitfield.imm32 = 1;
2262 offset_in_range (offsetT val, int size)
2268 case 1: mask = ((addressT) 1 << 8) - 1; break;
2269 case 2: mask = ((addressT) 1 << 16) - 1; break;
2270 case 4: mask = ((addressT) 2 << 31) - 1; break;
2272 case 8: mask = ((addressT) 2 << 63) - 1; break;
2278 /* If BFD64, sign extend val for 32bit address mode. */
2279 if (flag_code != CODE_64BIT
2280 || i.prefix[ADDR_PREFIX])
2281 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2282 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2285 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2287 char buf1[40], buf2[40];
2289 sprint_value (buf1, val);
2290 sprint_value (buf2, val & mask);
2291 as_warn (_("%s shortened to %s"), buf1, buf2);
2306 a. PREFIX_EXIST if attempting to add a prefix where one from the
2307 same class already exists.
2308 b. PREFIX_LOCK if lock prefix is added.
2309 c. PREFIX_REP if rep/repne prefix is added.
2310 d. PREFIX_DS if ds prefix is added.
2311 e. PREFIX_OTHER if other prefix is added.
2314 static enum PREFIX_GROUP
2315 add_prefix (unsigned int prefix)
2317 enum PREFIX_GROUP ret = PREFIX_OTHER;
2320 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2321 && flag_code == CODE_64BIT)
2323 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2324 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2325 && (prefix & (REX_R | REX_X | REX_B))))
2336 case DS_PREFIX_OPCODE:
2339 case CS_PREFIX_OPCODE:
2340 case ES_PREFIX_OPCODE:
2341 case FS_PREFIX_OPCODE:
2342 case GS_PREFIX_OPCODE:
2343 case SS_PREFIX_OPCODE:
2347 case REPNE_PREFIX_OPCODE:
2348 case REPE_PREFIX_OPCODE:
2353 case LOCK_PREFIX_OPCODE:
2362 case ADDR_PREFIX_OPCODE:
2366 case DATA_PREFIX_OPCODE:
2370 if (i.prefix[q] != 0)
2378 i.prefix[q] |= prefix;
2381 as_bad (_("same type of prefix used twice"));
2387 update_code_flag (int value, int check)
2389 PRINTF_LIKE ((*as_error));
2391 flag_code = (enum flag_code) value;
2392 if (flag_code == CODE_64BIT)
2394 cpu_arch_flags.bitfield.cpu64 = 1;
2395 cpu_arch_flags.bitfield.cpuno64 = 0;
2399 cpu_arch_flags.bitfield.cpu64 = 0;
2400 cpu_arch_flags.bitfield.cpuno64 = 1;
2402 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2405 as_error = as_fatal;
2408 (*as_error) (_("64bit mode not supported on `%s'."),
2409 cpu_arch_name ? cpu_arch_name : default_arch);
2411 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2414 as_error = as_fatal;
2417 (*as_error) (_("32bit mode not supported on `%s'."),
2418 cpu_arch_name ? cpu_arch_name : default_arch);
2420 stackop_size = '\0';
2424 set_code_flag (int value)
2426 update_code_flag (value, 0);
2430 set_16bit_gcc_code_flag (int new_code_flag)
2432 flag_code = (enum flag_code) new_code_flag;
2433 if (flag_code != CODE_16BIT)
2435 cpu_arch_flags.bitfield.cpu64 = 0;
2436 cpu_arch_flags.bitfield.cpuno64 = 1;
2437 stackop_size = LONG_MNEM_SUFFIX;
2441 set_intel_syntax (int syntax_flag)
2443 /* Find out if register prefixing is specified. */
2444 int ask_naked_reg = 0;
2447 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2450 int e = get_symbol_name (&string);
2452 if (strcmp (string, "prefix") == 0)
2454 else if (strcmp (string, "noprefix") == 0)
2457 as_bad (_("bad argument to syntax directive."));
2458 (void) restore_line_pointer (e);
2460 demand_empty_rest_of_line ();
2462 intel_syntax = syntax_flag;
2464 if (ask_naked_reg == 0)
2465 allow_naked_reg = (intel_syntax
2466 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2468 allow_naked_reg = (ask_naked_reg < 0);
2470 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2472 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2473 identifier_chars['$'] = intel_syntax ? '$' : 0;
2474 register_prefix = allow_naked_reg ? "" : "%";
2478 set_intel_mnemonic (int mnemonic_flag)
2480 intel_mnemonic = mnemonic_flag;
2484 set_allow_index_reg (int flag)
2486 allow_index_reg = flag;
2490 set_check (int what)
2492 enum check_kind *kind;
2497 kind = &operand_check;
2508 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2511 int e = get_symbol_name (&string);
2513 if (strcmp (string, "none") == 0)
2515 else if (strcmp (string, "warning") == 0)
2516 *kind = check_warning;
2517 else if (strcmp (string, "error") == 0)
2518 *kind = check_error;
2520 as_bad (_("bad argument to %s_check directive."), str);
2521 (void) restore_line_pointer (e);
2524 as_bad (_("missing argument for %s_check directive"), str);
2526 demand_empty_rest_of_line ();
2530 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2531 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2533 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2534 static const char *arch;
2536 /* Intel LIOM is only supported on ELF. */
2542 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2543 use default_arch. */
2544 arch = cpu_arch_name;
2546 arch = default_arch;
2549 /* If we are targeting Intel MCU, we must enable it. */
2550 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2551 || new_flag.bitfield.cpuiamcu)
2554 /* If we are targeting Intel L1OM, we must enable it. */
2555 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2556 || new_flag.bitfield.cpul1om)
2559 /* If we are targeting Intel K1OM, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2561 || new_flag.bitfield.cpuk1om)
2564 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2569 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2573 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2576 int e = get_symbol_name (&string);
2578 i386_cpu_flags flags;
2580 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2582 if (strcmp (string, cpu_arch[j].name) == 0)
2584 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2588 cpu_arch_name = cpu_arch[j].name;
2589 cpu_sub_arch_name = NULL;
2590 cpu_arch_flags = cpu_arch[j].flags;
2591 if (flag_code == CODE_64BIT)
2593 cpu_arch_flags.bitfield.cpu64 = 1;
2594 cpu_arch_flags.bitfield.cpuno64 = 0;
2598 cpu_arch_flags.bitfield.cpu64 = 0;
2599 cpu_arch_flags.bitfield.cpuno64 = 1;
2601 cpu_arch_isa = cpu_arch[j].type;
2602 cpu_arch_isa_flags = cpu_arch[j].flags;
2603 if (!cpu_arch_tune_set)
2605 cpu_arch_tune = cpu_arch_isa;
2606 cpu_arch_tune_flags = cpu_arch_isa_flags;
2611 flags = cpu_flags_or (cpu_arch_flags,
2614 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2616 if (cpu_sub_arch_name)
2618 char *name = cpu_sub_arch_name;
2619 cpu_sub_arch_name = concat (name,
2621 (const char *) NULL);
2625 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2626 cpu_arch_flags = flags;
2627 cpu_arch_isa_flags = flags;
2629 (void) restore_line_pointer (e);
2630 demand_empty_rest_of_line ();
2635 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2637 /* Disable an ISA extension. */
2638 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2639 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2641 flags = cpu_flags_and_not (cpu_arch_flags,
2642 cpu_noarch[j].flags);
2643 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2645 if (cpu_sub_arch_name)
2647 char *name = cpu_sub_arch_name;
2648 cpu_sub_arch_name = concat (name, string,
2649 (const char *) NULL);
2653 cpu_sub_arch_name = xstrdup (string);
2654 cpu_arch_flags = flags;
2655 cpu_arch_isa_flags = flags;
2657 (void) restore_line_pointer (e);
2658 demand_empty_rest_of_line ();
2662 j = ARRAY_SIZE (cpu_arch);
2665 if (j >= ARRAY_SIZE (cpu_arch))
2666 as_bad (_("no such architecture: `%s'"), string);
2668 *input_line_pointer = e;
2671 as_bad (_("missing cpu architecture"));
2673 no_cond_jump_promotion = 0;
2674 if (*input_line_pointer == ','
2675 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2680 ++input_line_pointer;
2681 e = get_symbol_name (&string);
2683 if (strcmp (string, "nojumps") == 0)
2684 no_cond_jump_promotion = 1;
2685 else if (strcmp (string, "jumps") == 0)
2688 as_bad (_("no such architecture modifier: `%s'"), string);
2690 (void) restore_line_pointer (e);
2693 demand_empty_rest_of_line ();
2696 enum bfd_architecture
2699 if (cpu_arch_isa == PROCESSOR_L1OM)
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om;
2706 else if (cpu_arch_isa == PROCESSOR_K1OM)
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code != CODE_64BIT)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om;
2713 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code == CODE_64BIT)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu;
2721 return bfd_arch_i386;
2727 if (!strncmp (default_arch, "x86_64", 6))
2729 if (cpu_arch_isa == PROCESSOR_L1OM)
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om;
2736 else if (cpu_arch_isa == PROCESSOR_K1OM)
2738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2739 || default_arch[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om;
2743 else if (default_arch[6] == '\0')
2744 return bfd_mach_x86_64;
2746 return bfd_mach_x64_32;
2748 else if (!strcmp (default_arch, "i386")
2749 || !strcmp (default_arch, "iamcu"))
2751 if (cpu_arch_isa == PROCESSOR_IAMCU)
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu;
2758 return bfd_mach_i386_i386;
2761 as_fatal (_("unknown architecture"));
2767 const char *hash_err;
2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type ['{'] = LEX_BEGIN_NAME;
2772 /* Initialize op_hash hash table. */
2773 op_hash = hash_new ();
2776 const insn_template *optab;
2777 templates *core_optab;
2779 /* Setup for loop. */
2781 core_optab = XNEW (templates);
2782 core_optab->start = optab;
2787 if (optab->name == NULL
2788 || strcmp (optab->name, (optab - 1)->name) != 0)
2790 /* different name --> ship out current template list;
2791 add to hash table; & begin anew. */
2792 core_optab->end = optab;
2793 hash_err = hash_insert (op_hash,
2795 (void *) core_optab);
2798 as_fatal (_("can't hash %s: %s"),
2802 if (optab->name == NULL)
2804 core_optab = XNEW (templates);
2805 core_optab->start = optab;
2810 /* Initialize reg_hash hash table. */
2811 reg_hash = hash_new ();
2813 const reg_entry *regtab;
2814 unsigned int regtab_size = i386_regtab_size;
2816 for (regtab = i386_regtab; regtab_size--; regtab++)
2818 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2820 as_fatal (_("can't hash %s: %s"),
2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2831 for (c = 0; c < 256; c++)
2836 mnemonic_chars[c] = c;
2837 register_chars[c] = c;
2838 operand_chars[c] = c;
2840 else if (ISLOWER (c))
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2846 else if (ISUPPER (c))
2848 mnemonic_chars[c] = TOLOWER (c);
2849 register_chars[c] = mnemonic_chars[c];
2850 operand_chars[c] = c;
2852 else if (c == '{' || c == '}')
2854 mnemonic_chars[c] = c;
2855 operand_chars[c] = c;
2858 if (ISALPHA (c) || ISDIGIT (c))
2859 identifier_chars[c] = c;
2862 identifier_chars[c] = c;
2863 operand_chars[c] = c;
2868 identifier_chars['@'] = '@';
2871 identifier_chars['?'] = '?';
2872 operand_chars['?'] = '?';
2874 digit_chars['-'] = '-';
2875 mnemonic_chars['_'] = '_';
2876 mnemonic_chars['-'] = '-';
2877 mnemonic_chars['.'] = '.';
2878 identifier_chars['_'] = '_';
2879 identifier_chars['.'] = '.';
2881 for (p = operand_special_chars; *p != '\0'; p++)
2882 operand_chars[(unsigned char) *p] = *p;
2885 if (flag_code == CODE_64BIT)
2887 #if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2891 x86_dwarf2_return_column = 16;
2893 x86_cie_data_alignment = -8;
2897 x86_dwarf2_return_column = 8;
2898 x86_cie_data_alignment = -4;
2903 i386_print_statistics (FILE *file)
2905 hash_print_statistics (file, "i386 opcode", op_hash);
2906 hash_print_statistics (file, "i386 register", reg_hash);
2911 /* Debugging routines for md_assemble. */
2912 static void pte (insn_template *);
2913 static void pt (i386_operand_type);
2914 static void pe (expressionS *);
2915 static void ps (symbolS *);
2918 pi (char *line, i386_insn *x)
2922 fprintf (stdout, "%s: template ", line);
2924 fprintf (stdout, " address: base %s index %s scale %x\n",
2925 x->base_reg ? x->base_reg->reg_name : "none",
2926 x->index_reg ? x->index_reg->reg_name : "none",
2927 x->log2_scale_factor);
2928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2929 x->rm.mode, x->rm.reg, x->rm.regmem);
2930 fprintf (stdout, " sib: base %x index %x scale %x\n",
2931 x->sib.base, x->sib.index, x->sib.scale);
2932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2933 (x->rex & REX_W) != 0,
2934 (x->rex & REX_R) != 0,
2935 (x->rex & REX_X) != 0,
2936 (x->rex & REX_B) != 0);
2937 for (j = 0; j < x->operands; j++)
2939 fprintf (stdout, " #%d: ", j + 1);
2941 fprintf (stdout, "\n");
2942 if (x->types[j].bitfield.reg
2943 || x->types[j].bitfield.regmmx
2944 || x->types[j].bitfield.regsimd
2945 || x->types[j].bitfield.sreg2
2946 || x->types[j].bitfield.sreg3
2947 || x->types[j].bitfield.control
2948 || x->types[j].bitfield.debug
2949 || x->types[j].bitfield.test)
2950 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2951 if (operand_type_check (x->types[j], imm))
2953 if (operand_type_check (x->types[j], disp))
2954 pe (x->op[j].disps);
2959 pte (insn_template *t)
2962 fprintf (stdout, " %d operands ", t->operands);
2963 fprintf (stdout, "opcode %x ", t->base_opcode);
2964 if (t->extension_opcode != None)
2965 fprintf (stdout, "ext %x ", t->extension_opcode);
2966 if (t->opcode_modifier.d)
2967 fprintf (stdout, "D");
2968 if (t->opcode_modifier.w)
2969 fprintf (stdout, "W");
2970 fprintf (stdout, "\n");
2971 for (j = 0; j < t->operands; j++)
2973 fprintf (stdout, " #%d type ", j + 1);
2974 pt (t->operand_types[j]);
2975 fprintf (stdout, "\n");
2982 fprintf (stdout, " operation %d\n", e->X_op);
2983 fprintf (stdout, " add_number %ld (%lx)\n",
2984 (long) e->X_add_number, (long) e->X_add_number);
2985 if (e->X_add_symbol)
2987 fprintf (stdout, " add_symbol ");
2988 ps (e->X_add_symbol);
2989 fprintf (stdout, "\n");
2993 fprintf (stdout, " op_symbol ");
2994 ps (e->X_op_symbol);
2995 fprintf (stdout, "\n");
3002 fprintf (stdout, "%s type %s%s",
3004 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s)));
3008 static struct type_name
3010 i386_operand_type mask;
3013 const type_names[] =
3015 { OPERAND_TYPE_REG8, "r8" },
3016 { OPERAND_TYPE_REG16, "r16" },
3017 { OPERAND_TYPE_REG32, "r32" },
3018 { OPERAND_TYPE_REG64, "r64" },
3019 { OPERAND_TYPE_IMM8, "i8" },
3020 { OPERAND_TYPE_IMM8, "i8s" },
3021 { OPERAND_TYPE_IMM16, "i16" },
3022 { OPERAND_TYPE_IMM32, "i32" },
3023 { OPERAND_TYPE_IMM32S, "i32s" },
3024 { OPERAND_TYPE_IMM64, "i64" },
3025 { OPERAND_TYPE_IMM1, "i1" },
3026 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8, "d8" },
3028 { OPERAND_TYPE_DISP16, "d16" },
3029 { OPERAND_TYPE_DISP32, "d32" },
3030 { OPERAND_TYPE_DISP32S, "d32s" },
3031 { OPERAND_TYPE_DISP64, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL, "control reg" },
3035 { OPERAND_TYPE_TEST, "test reg" },
3036 { OPERAND_TYPE_DEBUG, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG, "FReg" },
3038 { OPERAND_TYPE_FLOATACC, "FAcc" },
3039 { OPERAND_TYPE_SREG2, "SReg2" },
3040 { OPERAND_TYPE_SREG3, "SReg3" },
3041 { OPERAND_TYPE_ACC, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX, "rMMX" },
3044 { OPERAND_TYPE_REGXMM, "rXMM" },
3045 { OPERAND_TYPE_REGYMM, "rYMM" },
3046 { OPERAND_TYPE_REGZMM, "rZMM" },
3047 { OPERAND_TYPE_REGMASK, "Mask reg" },
3048 { OPERAND_TYPE_ESSEG, "es" },
3052 pt (i386_operand_type t)
3055 i386_operand_type a;
3057 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3059 a = operand_type_and (t, type_names[j].mask);
3060 if (!operand_type_all_zero (&a))
3061 fprintf (stdout, "%s, ", type_names[j].name);
3066 #endif /* DEBUG386 */
3068 static bfd_reloc_code_real_type
3069 reloc (unsigned int size,
3072 bfd_reloc_code_real_type other)
3074 if (other != NO_RELOC)
3076 reloc_howto_type *rel;
3081 case BFD_RELOC_X86_64_GOT32:
3082 return BFD_RELOC_X86_64_GOT64;
3084 case BFD_RELOC_X86_64_GOTPLT64:
3085 return BFD_RELOC_X86_64_GOTPLT64;
3087 case BFD_RELOC_X86_64_PLTOFF64:
3088 return BFD_RELOC_X86_64_PLTOFF64;
3090 case BFD_RELOC_X86_64_GOTPC32:
3091 other = BFD_RELOC_X86_64_GOTPC64;
3093 case BFD_RELOC_X86_64_GOTPCREL:
3094 other = BFD_RELOC_X86_64_GOTPCREL64;
3096 case BFD_RELOC_X86_64_TPOFF32:
3097 other = BFD_RELOC_X86_64_TPOFF64;
3099 case BFD_RELOC_X86_64_DTPOFF32:
3100 other = BFD_RELOC_X86_64_DTPOFF64;
3106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 if (other == BFD_RELOC_SIZE32)
3110 other = BFD_RELOC_SIZE64;
3113 as_bad (_("there are no pc-relative size relocations"));
3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3120 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3123 rel = bfd_reloc_type_lookup (stdoutput, other);
3125 as_bad (_("unknown relocation (%u)"), other);
3126 else if (size != bfd_get_reloc_size (rel))
3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3128 bfd_get_reloc_size (rel),
3130 else if (pcrel && !rel->pc_relative)
3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
3132 else if ((rel->complain_on_overflow == complain_overflow_signed
3134 || (rel->complain_on_overflow == complain_overflow_unsigned
3136 as_bad (_("relocated field and relocation type differ in signedness"));
3145 as_bad (_("there are no unsigned pc-relative relocations"));
3148 case 1: return BFD_RELOC_8_PCREL;
3149 case 2: return BFD_RELOC_16_PCREL;
3150 case 4: return BFD_RELOC_32_PCREL;
3151 case 8: return BFD_RELOC_64_PCREL;
3153 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3160 case 4: return BFD_RELOC_X86_64_32S;
3165 case 1: return BFD_RELOC_8;
3166 case 2: return BFD_RELOC_16;
3167 case 4: return BFD_RELOC_32;
3168 case 8: return BFD_RELOC_64;
3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign > 0 ? "signed" : "unsigned", size);
3177 /* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3183 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3199 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3205 || fixP->fx_r_type == BFD_RELOC_SIZE64
3206 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3207 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3209 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3243 intel_float_operand (const char *mnemonic)
3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3249 if (mnemonic[0] != 'f')
3250 return 0; /* non-math */
3252 switch (mnemonic[1])
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3258 return 2 /* integer op */;
3260 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3264 if (mnemonic[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3268 if (mnemonic[2] == 's')
3269 return 3; /* frstor/frstpm */
3272 if (mnemonic[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic[2] == 't')
3276 switch (mnemonic[3])
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3287 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3295 /* Build the VEX prefix. */
3298 build_vex_prefix (const insn_template *t)
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int vector_length;
3304 /* Check register specifier. */
3305 if (i.vex.register_specifier)
3307 register_specifier =
3308 ~register_number (i.vex.register_specifier) & 0xf;
3309 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3312 register_specifier = 0xf;
3314 /* Use 2-byte VEX prefix by swapping destination and source
3316 if (i.vec_encoding != vex_encoding_vex3
3317 && i.dir_encoding == dir_encoding_default
3318 && i.operands == i.reg_operands
3319 && i.tm.opcode_modifier.vexopcode == VEX0F
3320 && i.tm.opcode_modifier.load
3323 unsigned int xchg = i.operands - 1;
3324 union i386_op temp_op;
3325 i386_operand_type temp_type;
3327 temp_type = i.types[xchg];
3328 i.types[xchg] = i.types[0];
3329 i.types[0] = temp_type;
3330 temp_op = i.op[xchg];
3331 i.op[xchg] = i.op[0];
3334 gas_assert (i.rm.mode == 3);
3338 i.rm.regmem = i.rm.reg;
3341 /* Use the next insn. */
3345 if (i.tm.opcode_modifier.vex == VEXScalar)
3346 vector_length = avxscalar;
3347 else if (i.tm.opcode_modifier.vex == VEX256)
3354 for (op = 0; op < t->operands; ++op)
3355 if (t->operand_types[op].bitfield.xmmword
3356 && t->operand_types[op].bitfield.ymmword
3357 && i.types[op].bitfield.ymmword)
3364 switch ((i.tm.base_opcode >> 8) & 0xff)
3369 case DATA_PREFIX_OPCODE:
3372 case REPE_PREFIX_OPCODE:
3375 case REPNE_PREFIX_OPCODE:
3382 /* Use 2-byte VEX prefix if possible. */
3383 if (i.vec_encoding != vex_encoding_vex3
3384 && i.tm.opcode_modifier.vexopcode == VEX0F
3385 && i.tm.opcode_modifier.vexw != VEXW1
3386 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3388 /* 2-byte VEX prefix. */
3392 i.vex.bytes[0] = 0xc5;
3394 /* Check the REX.R bit. */
3395 r = (i.rex & REX_R) ? 0 : 1;
3396 i.vex.bytes[1] = (r << 7
3397 | register_specifier << 3
3398 | vector_length << 2
3403 /* 3-byte VEX prefix. */
3408 switch (i.tm.opcode_modifier.vexopcode)
3412 i.vex.bytes[0] = 0xc4;
3416 i.vex.bytes[0] = 0xc4;
3420 i.vex.bytes[0] = 0xc4;
3424 i.vex.bytes[0] = 0x8f;
3428 i.vex.bytes[0] = 0x8f;
3432 i.vex.bytes[0] = 0x8f;
3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3442 /* Check the REX.W bit. */
3443 w = (i.rex & REX_W) ? 1 : 0;
3444 if (i.tm.opcode_modifier.vexw == VEXW1)
3447 i.vex.bytes[2] = (w << 7
3448 | register_specifier << 3
3449 | vector_length << 2
3454 static INLINE bfd_boolean
3455 is_evex_encoding (const insn_template *t)
3457 return t->opcode_modifier.evex
3458 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3459 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3462 /* Build the EVEX prefix. */
3465 build_evex_prefix (void)
3467 unsigned int register_specifier;
3468 unsigned int implied_prefix;
3470 rex_byte vrex_used = 0;
3472 /* Check register specifier. */
3473 if (i.vex.register_specifier)
3475 gas_assert ((i.vrex & REX_X) == 0);
3477 register_specifier = i.vex.register_specifier->reg_num;
3478 if ((i.vex.register_specifier->reg_flags & RegRex))
3479 register_specifier += 8;
3480 /* The upper 16 registers are encoded in the fourth byte of the
3482 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3483 i.vex.bytes[3] = 0x8;
3484 register_specifier = ~register_specifier & 0xf;
3488 register_specifier = 0xf;
3490 /* Encode upper 16 vector index register in the fourth byte of
3492 if (!(i.vrex & REX_X))
3493 i.vex.bytes[3] = 0x8;
3498 switch ((i.tm.base_opcode >> 8) & 0xff)
3503 case DATA_PREFIX_OPCODE:
3506 case REPE_PREFIX_OPCODE:
3509 case REPNE_PREFIX_OPCODE:
3516 /* 4 byte EVEX prefix. */
3518 i.vex.bytes[0] = 0x62;
3521 switch (i.tm.opcode_modifier.vexopcode)
3537 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3539 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3541 /* The fifth bit of the second EVEX byte is 1's compliment of the
3542 REX_R bit in VREX. */
3543 if (!(i.vrex & REX_R))
3544 i.vex.bytes[1] |= 0x10;
3548 if ((i.reg_operands + i.imm_operands) == i.operands)
3550 /* When all operands are registers, the REX_X bit in REX is not
3551 used. We reuse it to encode the upper 16 registers, which is
3552 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3553 as 1's compliment. */
3554 if ((i.vrex & REX_B))
3557 i.vex.bytes[1] &= ~0x40;
3561 /* EVEX instructions shouldn't need the REX prefix. */
3562 i.vrex &= ~vrex_used;
3563 gas_assert (i.vrex == 0);
3565 /* Check the REX.W bit. */
3566 w = (i.rex & REX_W) ? 1 : 0;
3567 if (i.tm.opcode_modifier.vexw)
3569 if (i.tm.opcode_modifier.vexw == VEXW1)
3572 /* If w is not set it means we are dealing with WIG instruction. */
3575 if (evexwig == evexw1)
3579 /* Encode the U bit. */
3580 implied_prefix |= 0x4;
3582 /* The third byte of the EVEX prefix. */
3583 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3585 /* The fourth byte of the EVEX prefix. */
3586 /* The zeroing-masking bit. */
3587 if (i.mask && i.mask->zeroing)
3588 i.vex.bytes[3] |= 0x80;
3590 /* Don't always set the broadcast bit if there is no RC. */
3593 /* Encode the vector length. */
3594 unsigned int vec_length;
3596 if (!i.tm.opcode_modifier.evex
3597 || i.tm.opcode_modifier.evex == EVEXDYN)
3602 for (op = 0; op < i.tm.operands; ++op)
3603 if (i.tm.operand_types[op].bitfield.xmmword
3604 + i.tm.operand_types[op].bitfield.ymmword
3605 + i.tm.operand_types[op].bitfield.zmmword > 1)
3607 if (i.types[op].bitfield.zmmword)
3608 i.tm.opcode_modifier.evex = EVEX512;
3609 else if (i.types[op].bitfield.ymmword)
3610 i.tm.opcode_modifier.evex = EVEX256;
3611 else if (i.types[op].bitfield.xmmword)
3612 i.tm.opcode_modifier.evex = EVEX128;
3619 switch (i.tm.opcode_modifier.evex)
3621 case EVEXLIG: /* LL' is ignored */
3622 vec_length = evexlig << 5;
3625 vec_length = 0 << 5;
3628 vec_length = 1 << 5;
3631 vec_length = 2 << 5;
3637 i.vex.bytes[3] |= vec_length;
3638 /* Encode the broadcast bit. */
3640 i.vex.bytes[3] |= 0x10;
3644 if (i.rounding->type != saeonly)
3645 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3647 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3650 if (i.mask && i.mask->mask)
3651 i.vex.bytes[3] |= i.mask->mask->reg_num;
3655 process_immext (void)
3659 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3662 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3663 with an opcode suffix which is coded in the same place as an
3664 8-bit immediate field would be.
3665 Here we check those operands and remove them afterwards. */
3668 for (x = 0; x < i.operands; x++)
3669 if (register_number (i.op[x].regs) != x)
3670 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3671 register_prefix, i.op[x].regs->reg_name, x + 1,
3677 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3679 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3680 suffix which is coded in the same place as an 8-bit immediate
3682 Here we check those operands and remove them afterwards. */
3685 if (i.operands != 3)
3688 for (x = 0; x < 2; x++)
3689 if (register_number (i.op[x].regs) != x)
3690 goto bad_register_operand;
3692 /* Check for third operand for mwaitx/monitorx insn. */
3693 if (register_number (i.op[x].regs)
3694 != (x + (i.tm.extension_opcode == 0xfb)))
3696 bad_register_operand:
3697 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3698 register_prefix, i.op[x].regs->reg_name, x+1,
3705 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3706 which is coded in the same place as an 8-bit immediate field
3707 would be. Here we fake an 8-bit immediate operand from the
3708 opcode suffix stored in tm.extension_opcode.
3710 AVX instructions also use this encoding, for some of
3711 3 argument instructions. */
3713 gas_assert (i.imm_operands <= 1
3715 || ((i.tm.opcode_modifier.vex
3716 || i.tm.opcode_modifier.vexopcode
3717 || is_evex_encoding (&i.tm))
3718 && i.operands <= 4)));
3720 exp = &im_expressions[i.imm_operands++];
3721 i.op[i.operands].imms = exp;
3722 i.types[i.operands] = imm8;
3724 exp->X_op = O_constant;
3725 exp->X_add_number = i.tm.extension_opcode;
3726 i.tm.extension_opcode = None;
3733 switch (i.tm.opcode_modifier.hleprefixok)
3738 as_bad (_("invalid instruction `%s' after `%s'"),
3739 i.tm.name, i.hle_prefix);
3742 if (i.prefix[LOCK_PREFIX])
3744 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3748 case HLEPrefixRelease:
3749 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3751 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3755 if (i.mem_operands == 0
3756 || !operand_type_check (i.types[i.operands - 1], anymem))
3758 as_bad (_("memory destination needed for instruction `%s'"
3759 " after `xrelease'"), i.tm.name);
3766 /* Try the shortest encoding by shortening operand size. */
3769 optimize_encoding (void)
3773 if (optimize_for_space
3774 && i.reg_operands == 1
3775 && i.imm_operands == 1
3776 && !i.types[1].bitfield.byte
3777 && i.op[0].imms->X_op == O_constant
3778 && fits_in_imm7 (i.op[0].imms->X_add_number)
3779 && ((i.tm.base_opcode == 0xa8
3780 && i.tm.extension_opcode == None)
3781 || (i.tm.base_opcode == 0xf6
3782 && i.tm.extension_opcode == 0x0)))
3785 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3787 unsigned int base_regnum = i.op[1].regs->reg_num;
3788 if (flag_code == CODE_64BIT || base_regnum < 4)
3790 i.types[1].bitfield.byte = 1;
3791 /* Ignore the suffix. */
3793 if (base_regnum >= 4
3794 && !(i.op[1].regs->reg_flags & RegRex))
3796 /* Handle SP, BP, SI and DI registers. */
3797 if (i.types[1].bitfield.word)
3799 else if (i.types[1].bitfield.dword)
3807 else if (flag_code == CODE_64BIT
3808 && ((i.reg_operands == 1
3809 && i.imm_operands == 1
3810 && i.op[0].imms->X_op == O_constant
3811 && ((i.tm.base_opcode == 0xb0
3812 && i.tm.extension_opcode == None
3813 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3814 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3815 && (((i.tm.base_opcode == 0x24
3816 || i.tm.base_opcode == 0xa8)
3817 && i.tm.extension_opcode == None)
3818 || (i.tm.base_opcode == 0x80
3819 && i.tm.extension_opcode == 0x4)
3820 || ((i.tm.base_opcode == 0xf6
3821 || i.tm.base_opcode == 0xc6)
3822 && i.tm.extension_opcode == 0x0)))))
3823 || (i.reg_operands == 2
3824 && i.op[0].regs == i.op[1].regs
3825 && ((i.tm.base_opcode == 0x30
3826 || i.tm.base_opcode == 0x28)
3827 && i.tm.extension_opcode == None)))
3828 && i.types[1].bitfield.qword)
3831 andq $imm31, %r64 -> andl $imm31, %r32
3832 testq $imm31, %r64 -> testl $imm31, %r32
3833 xorq %r64, %r64 -> xorl %r32, %r32
3834 subq %r64, %r64 -> subl %r32, %r32
3835 movq $imm31, %r64 -> movl $imm31, %r32
3836 movq $imm32, %r64 -> movl $imm32, %r32
3838 i.tm.opcode_modifier.norex64 = 1;
3839 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3842 movq $imm31, %r64 -> movl $imm31, %r32
3843 movq $imm32, %r64 -> movl $imm32, %r32
3845 i.tm.operand_types[0].bitfield.imm32 = 1;
3846 i.tm.operand_types[0].bitfield.imm32s = 0;
3847 i.tm.operand_types[0].bitfield.imm64 = 0;
3848 i.types[0].bitfield.imm32 = 1;
3849 i.types[0].bitfield.imm32s = 0;
3850 i.types[0].bitfield.imm64 = 0;
3851 i.types[1].bitfield.dword = 1;
3852 i.types[1].bitfield.qword = 0;
3853 if (i.tm.base_opcode == 0xc6)
3856 movq $imm31, %r64 -> movl $imm31, %r32
3858 i.tm.base_opcode = 0xb0;
3859 i.tm.extension_opcode = None;
3860 i.tm.opcode_modifier.shortform = 1;
3861 i.tm.opcode_modifier.modrm = 0;
3865 else if (optimize > 1
3866 && i.reg_operands == 3
3867 && i.op[0].regs == i.op[1].regs
3868 && !i.types[2].bitfield.xmmword
3869 && (i.tm.opcode_modifier.vex
3872 && is_evex_encoding (&i.tm)
3873 && cpu_arch_flags.bitfield.cpuavx512vl))
3874 && ((i.tm.base_opcode == 0x55
3875 || i.tm.base_opcode == 0x6655
3876 || i.tm.base_opcode == 0x66df
3877 || i.tm.base_opcode == 0x57
3878 || i.tm.base_opcode == 0x6657
3879 || i.tm.base_opcode == 0x66ef
3880 || i.tm.base_opcode == 0x66f8
3881 || i.tm.base_opcode == 0x66f9
3882 || i.tm.base_opcode == 0x66fa
3883 || i.tm.base_opcode == 0x66fb)
3884 && i.tm.extension_opcode == None))
3887 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3889 EVEX VOP %zmmM, %zmmM, %zmmN
3890 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3891 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3892 EVEX VOP %ymmM, %ymmM, %ymmN
3893 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3894 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3895 VEX VOP %ymmM, %ymmM, %ymmN
3896 -> VEX VOP %xmmM, %xmmM, %xmmN
3897 VOP, one of vpandn and vpxor:
3898 VEX VOP %ymmM, %ymmM, %ymmN
3899 -> VEX VOP %xmmM, %xmmM, %xmmN
3900 VOP, one of vpandnd and vpandnq:
3901 EVEX VOP %zmmM, %zmmM, %zmmN
3902 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3904 EVEX VOP %ymmM, %ymmM, %ymmN
3905 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3906 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3907 VOP, one of vpxord and vpxorq:
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3915 if (is_evex_encoding (&i.tm))
3917 /* If only lower 16 vector registers are used, we can use
3919 for (j = 0; j < 3; j++)
3920 if (register_number (i.op[j].regs) > 15)
3924 i.tm.opcode_modifier.evex = EVEX128;
3927 i.tm.opcode_modifier.vex = VEX128;
3928 i.tm.opcode_modifier.vexw = VEXW0;
3929 i.tm.opcode_modifier.evex = 0;
3933 i.tm.opcode_modifier.vex = VEX128;
3935 if (i.tm.opcode_modifier.vex)
3936 for (j = 0; j < 3; j++)
3938 i.types[j].bitfield.xmmword = 1;
3939 i.types[j].bitfield.ymmword = 0;
3944 /* This is the guts of the machine-dependent assembler. LINE points to a
3945 machine dependent instruction. This function is supposed to emit
3946 the frags/bytes it assembles to. */
3949 md_assemble (char *line)
3952 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3953 const insn_template *t;
3955 /* Initialize globals. */
3956 memset (&i, '\0', sizeof (i));
3957 for (j = 0; j < MAX_OPERANDS; j++)
3958 i.reloc[j] = NO_RELOC;
3959 memset (disp_expressions, '\0', sizeof (disp_expressions));
3960 memset (im_expressions, '\0', sizeof (im_expressions));
3961 save_stack_p = save_stack;
3963 /* First parse an instruction mnemonic & call i386_operand for the operands.
3964 We assume that the scrubber has arranged it so that line[0] is the valid
3965 start of a (possibly prefixed) mnemonic. */
3967 line = parse_insn (line, mnemonic);
3970 mnem_suffix = i.suffix;
3972 line = parse_operands (line, mnemonic);
3974 xfree (i.memop1_string);
3975 i.memop1_string = NULL;
3979 /* Now we've parsed the mnemonic into a set of templates, and have the
3980 operands at hand. */
3982 /* All intel opcodes have reversed operands except for "bound" and
3983 "enter". We also don't reverse intersegment "jmp" and "call"
3984 instructions with 2 immediate operands so that the immediate segment
3985 precedes the offset, as it does when in AT&T mode. */
3988 && (strcmp (mnemonic, "bound") != 0)
3989 && (strcmp (mnemonic, "invlpga") != 0)
3990 && !(operand_type_check (i.types[0], imm)
3991 && operand_type_check (i.types[1], imm)))
3994 /* The order of the immediates should be reversed
3995 for 2 immediates extrq and insertq instructions */
3996 if (i.imm_operands == 2
3997 && (strcmp (mnemonic, "extrq") == 0
3998 || strcmp (mnemonic, "insertq") == 0))
3999 swap_2_operands (0, 1);
4004 /* Don't optimize displacement for movabs since it only takes 64bit
4007 && i.disp_encoding != disp_encoding_32bit
4008 && (flag_code != CODE_64BIT
4009 || strcmp (mnemonic, "movabs") != 0))
4012 /* Next, we find a template that matches the given insn,
4013 making sure the overlap of the given operands types is consistent
4014 with the template operand types. */
4016 if (!(t = match_template (mnem_suffix)))
4019 if (sse_check != check_none
4020 && !i.tm.opcode_modifier.noavx
4021 && !i.tm.cpu_flags.bitfield.cpuavx
4022 && (i.tm.cpu_flags.bitfield.cpusse
4023 || i.tm.cpu_flags.bitfield.cpusse2
4024 || i.tm.cpu_flags.bitfield.cpusse3
4025 || i.tm.cpu_flags.bitfield.cpussse3
4026 || i.tm.cpu_flags.bitfield.cpusse4_1
4027 || i.tm.cpu_flags.bitfield.cpusse4_2
4028 || i.tm.cpu_flags.bitfield.cpupclmul
4029 || i.tm.cpu_flags.bitfield.cpuaes
4030 || i.tm.cpu_flags.bitfield.cpugfni))
4032 (sse_check == check_warning
4034 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4037 /* Zap movzx and movsx suffix. The suffix has been set from
4038 "word ptr" or "byte ptr" on the source operand in Intel syntax
4039 or extracted from mnemonic in AT&T syntax. But we'll use
4040 the destination register to choose the suffix for encoding. */
4041 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4043 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4044 there is no suffix, the default will be byte extension. */
4045 if (i.reg_operands != 2
4048 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4053 if (i.tm.opcode_modifier.fwait)
4054 if (!add_prefix (FWAIT_OPCODE))
4057 /* Check if REP prefix is OK. */
4058 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4060 as_bad (_("invalid instruction `%s' after `%s'"),
4061 i.tm.name, i.rep_prefix);
4065 /* Check for lock without a lockable instruction. Destination operand
4066 must be memory unless it is xchg (0x86). */
4067 if (i.prefix[LOCK_PREFIX]
4068 && (!i.tm.opcode_modifier.islockable
4069 || i.mem_operands == 0
4070 || (i.tm.base_opcode != 0x86
4071 && !operand_type_check (i.types[i.operands - 1], anymem))))
4073 as_bad (_("expecting lockable instruction after `lock'"));
4077 /* Check if HLE prefix is OK. */
4078 if (i.hle_prefix && !check_hle ())
4081 /* Check BND prefix. */
4082 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4083 as_bad (_("expecting valid branch instruction after `bnd'"));
4085 /* Check NOTRACK prefix. */
4086 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4087 as_bad (_("expecting indirect branch instruction after `notrack'"));
4089 if (i.tm.cpu_flags.bitfield.cpumpx)
4091 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4092 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4093 else if (flag_code != CODE_16BIT
4094 ? i.prefix[ADDR_PREFIX]
4095 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4096 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4099 /* Insert BND prefix. */
4101 && i.tm.opcode_modifier.bndprefixok
4102 && !i.prefix[BND_PREFIX])
4103 add_prefix (BND_PREFIX_OPCODE);
4105 /* Check string instruction segment overrides. */
4106 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4108 if (!check_string ())
4110 i.disp_operands = 0;
4113 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4114 optimize_encoding ();
4116 if (!process_suffix ())
4119 /* Update operand types. */
4120 for (j = 0; j < i.operands; j++)
4121 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4123 /* Make still unresolved immediate matches conform to size of immediate
4124 given in i.suffix. */
4125 if (!finalize_imm ())
4128 if (i.types[0].bitfield.imm1)
4129 i.imm_operands = 0; /* kludge for shift insns. */
4131 /* We only need to check those implicit registers for instructions
4132 with 3 operands or less. */
4133 if (i.operands <= 3)
4134 for (j = 0; j < i.operands; j++)
4135 if (i.types[j].bitfield.inoutportreg
4136 || i.types[j].bitfield.shiftcount
4137 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4140 /* ImmExt should be processed after SSE2AVX. */
4141 if (!i.tm.opcode_modifier.sse2avx
4142 && i.tm.opcode_modifier.immext)
4145 /* For insns with operands there are more diddles to do to the opcode. */
4148 if (!process_operands ())
4151 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4153 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4154 as_warn (_("translating to `%sp'"), i.tm.name);
4157 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4158 || is_evex_encoding (&i.tm))
4160 if (flag_code == CODE_16BIT)
4162 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4167 if (i.tm.opcode_modifier.vex)
4168 build_vex_prefix (t);
4170 build_evex_prefix ();
4173 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4174 instructions may define INT_OPCODE as well, so avoid this corner
4175 case for those instructions that use MODRM. */
4176 if (i.tm.base_opcode == INT_OPCODE
4177 && !i.tm.opcode_modifier.modrm
4178 && i.op[0].imms->X_add_number == 3)
4180 i.tm.base_opcode = INT3_OPCODE;
4184 if ((i.tm.opcode_modifier.jump
4185 || i.tm.opcode_modifier.jumpbyte
4186 || i.tm.opcode_modifier.jumpdword)
4187 && i.op[0].disps->X_op == O_constant)
4189 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4190 the absolute address given by the constant. Since ix86 jumps and
4191 calls are pc relative, we need to generate a reloc. */
4192 i.op[0].disps->X_add_symbol = &abs_symbol;
4193 i.op[0].disps->X_op = O_symbol;
4196 if (i.tm.opcode_modifier.rex64)
4199 /* For 8 bit registers we need an empty rex prefix. Also if the
4200 instruction already has a prefix, we need to convert old
4201 registers to new ones. */
4203 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4204 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4205 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4206 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4207 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4208 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4213 i.rex |= REX_OPCODE;
4214 for (x = 0; x < 2; x++)
4216 /* Look for 8 bit operand that uses old registers. */
4217 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4218 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4220 /* In case it is "hi" register, give up. */
4221 if (i.op[x].regs->reg_num > 3)
4222 as_bad (_("can't encode register '%s%s' in an "
4223 "instruction requiring REX prefix."),
4224 register_prefix, i.op[x].regs->reg_name);
4226 /* Otherwise it is equivalent to the extended register.
4227 Since the encoding doesn't change this is merely
4228 cosmetic cleanup for debug output. */
4230 i.op[x].regs = i.op[x].regs + 8;
4235 if (i.rex == 0 && i.rex_encoding)
4237 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4238 that uses legacy register. If it is "hi" register, don't add
4239 the REX_OPCODE byte. */
4241 for (x = 0; x < 2; x++)
4242 if (i.types[x].bitfield.reg
4243 && i.types[x].bitfield.byte
4244 && (i.op[x].regs->reg_flags & RegRex64) == 0
4245 && i.op[x].regs->reg_num > 3)
4247 i.rex_encoding = FALSE;
4256 add_prefix (REX_OPCODE | i.rex);
4258 /* We are ready to output the insn. */
4263 parse_insn (char *line, char *mnemonic)
4266 char *token_start = l;
4269 const insn_template *t;
4275 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4280 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4282 as_bad (_("no such instruction: `%s'"), token_start);
4287 if (!is_space_char (*l)
4288 && *l != END_OF_INSN
4290 || (*l != PREFIX_SEPARATOR
4293 as_bad (_("invalid character %s in mnemonic"),
4294 output_invalid (*l));
4297 if (token_start == l)
4299 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4300 as_bad (_("expecting prefix; got nothing"));
4302 as_bad (_("expecting mnemonic; got nothing"));
4306 /* Look up instruction (or prefix) via hash table. */
4307 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4309 if (*l != END_OF_INSN
4310 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4311 && current_templates
4312 && current_templates->start->opcode_modifier.isprefix)
4314 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4316 as_bad ((flag_code != CODE_64BIT
4317 ? _("`%s' is only supported in 64-bit mode")
4318 : _("`%s' is not supported in 64-bit mode")),
4319 current_templates->start->name);
4322 /* If we are in 16-bit mode, do not allow addr16 or data16.
4323 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4324 if ((current_templates->start->opcode_modifier.size16
4325 || current_templates->start->opcode_modifier.size32)
4326 && flag_code != CODE_64BIT
4327 && (current_templates->start->opcode_modifier.size32
4328 ^ (flag_code == CODE_16BIT)))
4330 as_bad (_("redundant %s prefix"),
4331 current_templates->start->name);
4334 if (current_templates->start->opcode_length == 0)
4336 /* Handle pseudo prefixes. */
4337 switch (current_templates->start->base_opcode)
4341 i.disp_encoding = disp_encoding_8bit;
4345 i.disp_encoding = disp_encoding_32bit;
4349 i.dir_encoding = dir_encoding_load;
4353 i.dir_encoding = dir_encoding_store;
4357 i.vec_encoding = vex_encoding_vex2;
4361 i.vec_encoding = vex_encoding_vex3;
4365 i.vec_encoding = vex_encoding_evex;
4369 i.rex_encoding = TRUE;
4373 i.no_optimize = TRUE;
4381 /* Add prefix, checking for repeated prefixes. */
4382 switch (add_prefix (current_templates->start->base_opcode))
4387 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4388 i.notrack_prefix = current_templates->start->name;
4391 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4392 i.hle_prefix = current_templates->start->name;
4393 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4394 i.bnd_prefix = current_templates->start->name;
4396 i.rep_prefix = current_templates->start->name;
4402 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4409 if (!current_templates)
4411 /* Check if we should swap operand or force 32bit displacement in
4413 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4414 i.dir_encoding = dir_encoding_store;
4415 else if (mnem_p - 3 == dot_p
4418 i.disp_encoding = disp_encoding_8bit;
4419 else if (mnem_p - 4 == dot_p
4423 i.disp_encoding = disp_encoding_32bit;
4428 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4431 if (!current_templates)
4434 /* See if we can get a match by trimming off a suffix. */
4437 case WORD_MNEM_SUFFIX:
4438 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4439 i.suffix = SHORT_MNEM_SUFFIX;
4442 case BYTE_MNEM_SUFFIX:
4443 case QWORD_MNEM_SUFFIX:
4444 i.suffix = mnem_p[-1];
4446 current_templates = (const templates *) hash_find (op_hash,
4449 case SHORT_MNEM_SUFFIX:
4450 case LONG_MNEM_SUFFIX:
4453 i.suffix = mnem_p[-1];
4455 current_templates = (const templates *) hash_find (op_hash,
4464 if (intel_float_operand (mnemonic) == 1)
4465 i.suffix = SHORT_MNEM_SUFFIX;
4467 i.suffix = LONG_MNEM_SUFFIX;
4469 current_templates = (const templates *) hash_find (op_hash,
4474 if (!current_templates)
4476 as_bad (_("no such instruction: `%s'"), token_start);
4481 if (current_templates->start->opcode_modifier.jump
4482 || current_templates->start->opcode_modifier.jumpbyte)
4484 /* Check for a branch hint. We allow ",pt" and ",pn" for
4485 predict taken and predict not taken respectively.
4486 I'm not sure that branch hints actually do anything on loop
4487 and jcxz insns (JumpByte) for current Pentium4 chips. They
4488 may work in the future and it doesn't hurt to accept them
4490 if (l[0] == ',' && l[1] == 'p')
4494 if (!add_prefix (DS_PREFIX_OPCODE))
4498 else if (l[2] == 'n')
4500 if (!add_prefix (CS_PREFIX_OPCODE))
4506 /* Any other comma loses. */
4509 as_bad (_("invalid character %s in mnemonic"),
4510 output_invalid (*l));
4514 /* Check if instruction is supported on specified architecture. */
4516 for (t = current_templates->start; t < current_templates->end; ++t)
4518 supported |= cpu_flags_match (t);
4519 if (supported == CPU_FLAGS_PERFECT_MATCH)
4521 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4522 as_warn (_("use .code16 to ensure correct addressing mode"));
4528 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4529 as_bad (flag_code == CODE_64BIT
4530 ? _("`%s' is not supported in 64-bit mode")
4531 : _("`%s' is only supported in 64-bit mode"),
4532 current_templates->start->name);
4534 as_bad (_("`%s' is not supported on `%s%s'"),
4535 current_templates->start->name,
4536 cpu_arch_name ? cpu_arch_name : default_arch,
4537 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4543 parse_operands (char *l, const char *mnemonic)
4547 /* 1 if operand is pending after ','. */
4548 unsigned int expecting_operand = 0;
4550 /* Non-zero if operand parens not balanced. */
4551 unsigned int paren_not_balanced;
4553 while (*l != END_OF_INSN)
4555 /* Skip optional white space before operand. */
4556 if (is_space_char (*l))
4558 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4560 as_bad (_("invalid character %s before operand %d"),
4561 output_invalid (*l),
4565 token_start = l; /* After white space. */
4566 paren_not_balanced = 0;
4567 while (paren_not_balanced || *l != ',')
4569 if (*l == END_OF_INSN)
4571 if (paren_not_balanced)
4574 as_bad (_("unbalanced parenthesis in operand %d."),
4577 as_bad (_("unbalanced brackets in operand %d."),
4582 break; /* we are done */
4584 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4586 as_bad (_("invalid character %s in operand %d"),
4587 output_invalid (*l),
4594 ++paren_not_balanced;
4596 --paren_not_balanced;
4601 ++paren_not_balanced;
4603 --paren_not_balanced;
4607 if (l != token_start)
4608 { /* Yes, we've read in another operand. */
4609 unsigned int operand_ok;
4610 this_operand = i.operands++;
4611 if (i.operands > MAX_OPERANDS)
4613 as_bad (_("spurious operands; (%d operands/instruction max)"),
4617 i.types[this_operand].bitfield.unspecified = 1;
4618 /* Now parse operand adding info to 'i' as we go along. */
4619 END_STRING_AND_SAVE (l);
4623 i386_intel_operand (token_start,
4624 intel_float_operand (mnemonic));
4626 operand_ok = i386_att_operand (token_start);
4628 RESTORE_END_STRING (l);
4634 if (expecting_operand)
4636 expecting_operand_after_comma:
4637 as_bad (_("expecting operand after ','; got nothing"));
4642 as_bad (_("expecting operand before ','; got nothing"));
4647 /* Now *l must be either ',' or END_OF_INSN. */
4650 if (*++l == END_OF_INSN)
4652 /* Just skip it, if it's \n complain. */
4653 goto expecting_operand_after_comma;
4655 expecting_operand = 1;
4662 swap_2_operands (int xchg1, int xchg2)
4664 union i386_op temp_op;
4665 i386_operand_type temp_type;
4666 enum bfd_reloc_code_real temp_reloc;
4668 temp_type = i.types[xchg2];
4669 i.types[xchg2] = i.types[xchg1];
4670 i.types[xchg1] = temp_type;
4671 temp_op = i.op[xchg2];
4672 i.op[xchg2] = i.op[xchg1];
4673 i.op[xchg1] = temp_op;
4674 temp_reloc = i.reloc[xchg2];
4675 i.reloc[xchg2] = i.reloc[xchg1];
4676 i.reloc[xchg1] = temp_reloc;
4680 if (i.mask->operand == xchg1)
4681 i.mask->operand = xchg2;
4682 else if (i.mask->operand == xchg2)
4683 i.mask->operand = xchg1;
4687 if (i.broadcast->operand == xchg1)
4688 i.broadcast->operand = xchg2;
4689 else if (i.broadcast->operand == xchg2)
4690 i.broadcast->operand = xchg1;
4694 if (i.rounding->operand == xchg1)
4695 i.rounding->operand = xchg2;
4696 else if (i.rounding->operand == xchg2)
4697 i.rounding->operand = xchg1;
4702 swap_operands (void)
4708 swap_2_operands (1, i.operands - 2);
4712 swap_2_operands (0, i.operands - 1);
4718 if (i.mem_operands == 2)
4720 const seg_entry *temp_seg;
4721 temp_seg = i.seg[0];
4722 i.seg[0] = i.seg[1];
4723 i.seg[1] = temp_seg;
4727 /* Try to ensure constant immediates are represented in the smallest
4732 char guess_suffix = 0;
4736 guess_suffix = i.suffix;
4737 else if (i.reg_operands)
4739 /* Figure out a suffix from the last register operand specified.
4740 We can't do this properly yet, ie. excluding InOutPortReg,
4741 but the following works for instructions with immediates.
4742 In any case, we can't set i.suffix yet. */
4743 for (op = i.operands; --op >= 0;)
4744 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4746 guess_suffix = BYTE_MNEM_SUFFIX;
4749 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4751 guess_suffix = WORD_MNEM_SUFFIX;
4754 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4756 guess_suffix = LONG_MNEM_SUFFIX;
4759 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4761 guess_suffix = QWORD_MNEM_SUFFIX;
4765 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4766 guess_suffix = WORD_MNEM_SUFFIX;
4768 for (op = i.operands; --op >= 0;)
4769 if (operand_type_check (i.types[op], imm))
4771 switch (i.op[op].imms->X_op)
4774 /* If a suffix is given, this operand may be shortened. */
4775 switch (guess_suffix)
4777 case LONG_MNEM_SUFFIX:
4778 i.types[op].bitfield.imm32 = 1;
4779 i.types[op].bitfield.imm64 = 1;
4781 case WORD_MNEM_SUFFIX:
4782 i.types[op].bitfield.imm16 = 1;
4783 i.types[op].bitfield.imm32 = 1;
4784 i.types[op].bitfield.imm32s = 1;
4785 i.types[op].bitfield.imm64 = 1;
4787 case BYTE_MNEM_SUFFIX:
4788 i.types[op].bitfield.imm8 = 1;
4789 i.types[op].bitfield.imm8s = 1;
4790 i.types[op].bitfield.imm16 = 1;
4791 i.types[op].bitfield.imm32 = 1;
4792 i.types[op].bitfield.imm32s = 1;
4793 i.types[op].bitfield.imm64 = 1;
4797 /* If this operand is at most 16 bits, convert it
4798 to a signed 16 bit number before trying to see
4799 whether it will fit in an even smaller size.
4800 This allows a 16-bit operand such as $0xffe0 to
4801 be recognised as within Imm8S range. */
4802 if ((i.types[op].bitfield.imm16)
4803 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4805 i.op[op].imms->X_add_number =
4806 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4809 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4810 if ((i.types[op].bitfield.imm32)
4811 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4814 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4815 ^ ((offsetT) 1 << 31))
4816 - ((offsetT) 1 << 31));
4820 = operand_type_or (i.types[op],
4821 smallest_imm_type (i.op[op].imms->X_add_number));
4823 /* We must avoid matching of Imm32 templates when 64bit
4824 only immediate is available. */
4825 if (guess_suffix == QWORD_MNEM_SUFFIX)
4826 i.types[op].bitfield.imm32 = 0;
4833 /* Symbols and expressions. */
4835 /* Convert symbolic operand to proper sizes for matching, but don't
4836 prevent matching a set of insns that only supports sizes other
4837 than those matching the insn suffix. */
4839 i386_operand_type mask, allowed;
4840 const insn_template *t;
4842 operand_type_set (&mask, 0);
4843 operand_type_set (&allowed, 0);
4845 for (t = current_templates->start;
4846 t < current_templates->end;
4848 allowed = operand_type_or (allowed,
4849 t->operand_types[op]);
4850 switch (guess_suffix)
4852 case QWORD_MNEM_SUFFIX:
4853 mask.bitfield.imm64 = 1;
4854 mask.bitfield.imm32s = 1;
4856 case LONG_MNEM_SUFFIX:
4857 mask.bitfield.imm32 = 1;
4859 case WORD_MNEM_SUFFIX:
4860 mask.bitfield.imm16 = 1;
4862 case BYTE_MNEM_SUFFIX:
4863 mask.bitfield.imm8 = 1;
4868 allowed = operand_type_and (mask, allowed);
4869 if (!operand_type_all_zero (&allowed))
4870 i.types[op] = operand_type_and (i.types[op], mask);
4877 /* Try to use the smallest displacement type too. */
4879 optimize_disp (void)
4883 for (op = i.operands; --op >= 0;)
4884 if (operand_type_check (i.types[op], disp))
4886 if (i.op[op].disps->X_op == O_constant)
4888 offsetT op_disp = i.op[op].disps->X_add_number;
4890 if (i.types[op].bitfield.disp16
4891 && (op_disp & ~(offsetT) 0xffff) == 0)
4893 /* If this operand is at most 16 bits, convert
4894 to a signed 16 bit number and don't use 64bit
4896 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4897 i.types[op].bitfield.disp64 = 0;
4900 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4901 if (i.types[op].bitfield.disp32
4902 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4904 /* If this operand is at most 32 bits, convert
4905 to a signed 32 bit number and don't use 64bit
4907 op_disp &= (((offsetT) 2 << 31) - 1);
4908 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4909 i.types[op].bitfield.disp64 = 0;
4912 if (!op_disp && i.types[op].bitfield.baseindex)
4914 i.types[op].bitfield.disp8 = 0;
4915 i.types[op].bitfield.disp16 = 0;
4916 i.types[op].bitfield.disp32 = 0;
4917 i.types[op].bitfield.disp32s = 0;
4918 i.types[op].bitfield.disp64 = 0;
4922 else if (flag_code == CODE_64BIT)
4924 if (fits_in_signed_long (op_disp))
4926 i.types[op].bitfield.disp64 = 0;
4927 i.types[op].bitfield.disp32s = 1;
4929 if (i.prefix[ADDR_PREFIX]
4930 && fits_in_unsigned_long (op_disp))
4931 i.types[op].bitfield.disp32 = 1;
4933 if ((i.types[op].bitfield.disp32
4934 || i.types[op].bitfield.disp32s
4935 || i.types[op].bitfield.disp16)
4936 && fits_in_disp8 (op_disp))
4937 i.types[op].bitfield.disp8 = 1;
4939 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4940 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4942 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4943 i.op[op].disps, 0, i.reloc[op]);
4944 i.types[op].bitfield.disp8 = 0;
4945 i.types[op].bitfield.disp16 = 0;
4946 i.types[op].bitfield.disp32 = 0;
4947 i.types[op].bitfield.disp32s = 0;
4948 i.types[op].bitfield.disp64 = 0;
4951 /* We only support 64bit displacement on constants. */
4952 i.types[op].bitfield.disp64 = 0;
4956 /* Check if operands are valid for the instruction. */
4959 check_VecOperands (const insn_template *t)
4963 /* Without VSIB byte, we can't have a vector register for index. */
4964 if (!t->opcode_modifier.vecsib
4966 && (i.index_reg->reg_type.bitfield.xmmword
4967 || i.index_reg->reg_type.bitfield.ymmword
4968 || i.index_reg->reg_type.bitfield.zmmword))
4970 i.error = unsupported_vector_index_register;
4974 /* Check if default mask is allowed. */
4975 if (t->opcode_modifier.nodefmask
4976 && (!i.mask || i.mask->mask->reg_num == 0))
4978 i.error = no_default_mask;
4982 /* For VSIB byte, we need a vector register for index, and all vector
4983 registers must be distinct. */
4984 if (t->opcode_modifier.vecsib)
4987 || !((t->opcode_modifier.vecsib == VecSIB128
4988 && i.index_reg->reg_type.bitfield.xmmword)
4989 || (t->opcode_modifier.vecsib == VecSIB256
4990 && i.index_reg->reg_type.bitfield.ymmword)
4991 || (t->opcode_modifier.vecsib == VecSIB512
4992 && i.index_reg->reg_type.bitfield.zmmword)))
4994 i.error = invalid_vsib_address;
4998 gas_assert (i.reg_operands == 2 || i.mask);
4999 if (i.reg_operands == 2 && !i.mask)
5001 gas_assert (i.types[0].bitfield.regsimd);
5002 gas_assert (i.types[0].bitfield.xmmword
5003 || i.types[0].bitfield.ymmword);
5004 gas_assert (i.types[2].bitfield.regsimd);
5005 gas_assert (i.types[2].bitfield.xmmword
5006 || i.types[2].bitfield.ymmword);
5007 if (operand_check == check_none)
5009 if (register_number (i.op[0].regs)
5010 != register_number (i.index_reg)
5011 && register_number (i.op[2].regs)
5012 != register_number (i.index_reg)
5013 && register_number (i.op[0].regs)
5014 != register_number (i.op[2].regs))
5016 if (operand_check == check_error)
5018 i.error = invalid_vector_register_set;
5021 as_warn (_("mask, index, and destination registers should be distinct"));
5023 else if (i.reg_operands == 1 && i.mask)
5025 if (i.types[1].bitfield.regsimd
5026 && (i.types[1].bitfield.xmmword
5027 || i.types[1].bitfield.ymmword
5028 || i.types[1].bitfield.zmmword)
5029 && (register_number (i.op[1].regs)
5030 == register_number (i.index_reg)))
5032 if (operand_check == check_error)
5034 i.error = invalid_vector_register_set;
5037 if (operand_check != check_none)
5038 as_warn (_("index and destination registers should be distinct"));
5043 /* Check if broadcast is supported by the instruction and is applied
5044 to the memory operand. */
5047 int broadcasted_opnd_size;
5049 /* Check if specified broadcast is supported in this instruction,
5050 and it's applied to memory operand of DWORD or QWORD type,
5051 depending on VecESize. */
5052 if (i.broadcast->type != t->opcode_modifier.broadcast
5053 || !i.types[i.broadcast->operand].bitfield.mem
5054 || (t->opcode_modifier.vecesize == 0
5055 && !i.types[i.broadcast->operand].bitfield.dword
5056 && !i.types[i.broadcast->operand].bitfield.unspecified)
5057 || (t->opcode_modifier.vecesize == 1
5058 && !i.types[i.broadcast->operand].bitfield.qword
5059 && !i.types[i.broadcast->operand].bitfield.unspecified))
5062 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5063 if (i.broadcast->type == BROADCAST_1TO16)
5064 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5065 else if (i.broadcast->type == BROADCAST_1TO8)
5066 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5067 else if (i.broadcast->type == BROADCAST_1TO4)
5068 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5069 else if (i.broadcast->type == BROADCAST_1TO2)
5070 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5074 if ((broadcasted_opnd_size == 256
5075 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5076 || (broadcasted_opnd_size == 512
5077 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5080 i.error = unsupported_broadcast;
5084 /* If broadcast is supported in this instruction, we need to check if
5085 operand of one-element size isn't specified without broadcast. */
5086 else if (t->opcode_modifier.broadcast && i.mem_operands)
5088 /* Find memory operand. */
5089 for (op = 0; op < i.operands; op++)
5090 if (operand_type_check (i.types[op], anymem))
5092 gas_assert (op < i.operands);
5093 /* Check size of the memory operand. */
5094 if ((t->opcode_modifier.vecesize == 0
5095 && i.types[op].bitfield.dword)
5096 || (t->opcode_modifier.vecesize == 1
5097 && i.types[op].bitfield.qword))
5099 i.error = broadcast_needed;
5104 /* Check if requested masking is supported. */
5106 && (!t->opcode_modifier.masking
5108 && t->opcode_modifier.masking == MERGING_MASKING)))
5110 i.error = unsupported_masking;
5114 /* Check if masking is applied to dest operand. */
5115 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5117 i.error = mask_not_on_destination;
5124 if ((i.rounding->type != saeonly
5125 && !t->opcode_modifier.staticrounding)
5126 || (i.rounding->type == saeonly
5127 && (t->opcode_modifier.staticrounding
5128 || !t->opcode_modifier.sae)))
5130 i.error = unsupported_rc_sae;
5133 /* If the instruction has several immediate operands and one of
5134 them is rounding, the rounding operand should be the last
5135 immediate operand. */
5136 if (i.imm_operands > 1
5137 && i.rounding->operand != (int) (i.imm_operands - 1))
5139 i.error = rc_sae_operand_not_last_imm;
5144 /* Check vector Disp8 operand. */
5145 if (t->opcode_modifier.disp8memshift
5146 && i.disp_encoding != disp_encoding_32bit)
5149 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5151 i.memshift = t->opcode_modifier.disp8memshift;
5153 for (op = 0; op < i.operands; op++)
5154 if (operand_type_check (i.types[op], disp)
5155 && i.op[op].disps->X_op == O_constant)
5157 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5159 i.types[op].bitfield.disp8 = 1;
5162 i.types[op].bitfield.disp8 = 0;
5171 /* Check if operands are valid for the instruction. Update VEX
5175 VEX_check_operands (const insn_template *t)
5177 if (i.vec_encoding == vex_encoding_evex)
5179 /* This instruction must be encoded with EVEX prefix. */
5180 if (!is_evex_encoding (t))
5182 i.error = unsupported;
5188 if (!t->opcode_modifier.vex)
5190 /* This instruction template doesn't have VEX prefix. */
5191 if (i.vec_encoding != vex_encoding_default)
5193 i.error = unsupported;
5199 /* Only check VEX_Imm4, which must be the first operand. */
5200 if (t->operand_types[0].bitfield.vec_imm4)
5202 if (i.op[0].imms->X_op != O_constant
5203 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5209 /* Turn off Imm8 so that update_imm won't complain. */
5210 i.types[0] = vec_imm4;
5216 static const insn_template *
5217 match_template (char mnem_suffix)
5219 /* Points to template once we've found it. */
5220 const insn_template *t;
5221 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5222 i386_operand_type overlap4;
5223 unsigned int found_reverse_match;
5224 i386_opcode_modifier suffix_check, mnemsuf_check;
5225 i386_operand_type operand_types [MAX_OPERANDS];
5226 int addr_prefix_disp;
5228 unsigned int found_cpu_match;
5229 unsigned int check_register;
5230 enum i386_error specific_error = 0;
5232 #if MAX_OPERANDS != 5
5233 # error "MAX_OPERANDS must be 5."
5236 found_reverse_match = 0;
5237 addr_prefix_disp = -1;
5239 memset (&suffix_check, 0, sizeof (suffix_check));
5240 if (i.suffix == BYTE_MNEM_SUFFIX)
5241 suffix_check.no_bsuf = 1;
5242 else if (i.suffix == WORD_MNEM_SUFFIX)
5243 suffix_check.no_wsuf = 1;
5244 else if (i.suffix == SHORT_MNEM_SUFFIX)
5245 suffix_check.no_ssuf = 1;
5246 else if (i.suffix == LONG_MNEM_SUFFIX)
5247 suffix_check.no_lsuf = 1;
5248 else if (i.suffix == QWORD_MNEM_SUFFIX)
5249 suffix_check.no_qsuf = 1;
5250 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5251 suffix_check.no_ldsuf = 1;
5253 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5256 switch (mnem_suffix)
5258 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5259 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5260 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5261 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5262 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5266 /* Must have right number of operands. */
5267 i.error = number_of_operands_mismatch;
5269 for (t = current_templates->start; t < current_templates->end; t++)
5271 addr_prefix_disp = -1;
5273 if (i.operands != t->operands)
5276 /* Check processor support. */
5277 i.error = unsupported;
5278 found_cpu_match = (cpu_flags_match (t)
5279 == CPU_FLAGS_PERFECT_MATCH);
5280 if (!found_cpu_match)
5283 /* Check old gcc support. */
5284 i.error = old_gcc_only;
5285 if (!old_gcc && t->opcode_modifier.oldgcc)
5288 /* Check AT&T mnemonic. */
5289 i.error = unsupported_with_intel_mnemonic;
5290 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5293 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5294 i.error = unsupported_syntax;
5295 if ((intel_syntax && t->opcode_modifier.attsyntax)
5296 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5297 || (intel64 && t->opcode_modifier.amd64)
5298 || (!intel64 && t->opcode_modifier.intel64))
5301 /* Check the suffix, except for some instructions in intel mode. */
5302 i.error = invalid_instruction_suffix;
5303 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5304 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5305 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5306 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5307 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5308 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5309 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5311 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5312 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5313 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5314 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5315 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5316 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5317 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5320 if (!operand_size_match (t))
5323 for (j = 0; j < MAX_OPERANDS; j++)
5324 operand_types[j] = t->operand_types[j];
5326 /* In general, don't allow 64-bit operands in 32-bit mode. */
5327 if (i.suffix == QWORD_MNEM_SUFFIX
5328 && flag_code != CODE_64BIT
5330 ? (!t->opcode_modifier.ignoresize
5331 && !intel_float_operand (t->name))
5332 : intel_float_operand (t->name) != 2)
5333 && ((!operand_types[0].bitfield.regmmx
5334 && !operand_types[0].bitfield.regsimd)
5335 || (!operand_types[t->operands > 1].bitfield.regmmx
5336 && !operand_types[t->operands > 1].bitfield.regsimd))
5337 && (t->base_opcode != 0x0fc7
5338 || t->extension_opcode != 1 /* cmpxchg8b */))
5341 /* In general, don't allow 32-bit operands on pre-386. */
5342 else if (i.suffix == LONG_MNEM_SUFFIX
5343 && !cpu_arch_flags.bitfield.cpui386
5345 ? (!t->opcode_modifier.ignoresize
5346 && !intel_float_operand (t->name))
5347 : intel_float_operand (t->name) != 2)
5348 && ((!operand_types[0].bitfield.regmmx
5349 && !operand_types[0].bitfield.regsimd)
5350 || (!operand_types[t->operands > 1].bitfield.regmmx
5351 && !operand_types[t->operands > 1].bitfield.regsimd)))
5354 /* Do not verify operands when there are none. */
5358 /* We've found a match; break out of loop. */
5362 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5363 into Disp32/Disp16/Disp32 operand. */
5364 if (i.prefix[ADDR_PREFIX] != 0)
5366 /* There should be only one Disp operand. */
5370 for (j = 0; j < MAX_OPERANDS; j++)
5372 if (operand_types[j].bitfield.disp16)
5374 addr_prefix_disp = j;
5375 operand_types[j].bitfield.disp32 = 1;
5376 operand_types[j].bitfield.disp16 = 0;
5382 for (j = 0; j < MAX_OPERANDS; j++)
5384 if (operand_types[j].bitfield.disp32)
5386 addr_prefix_disp = j;
5387 operand_types[j].bitfield.disp32 = 0;
5388 operand_types[j].bitfield.disp16 = 1;
5394 for (j = 0; j < MAX_OPERANDS; j++)
5396 if (operand_types[j].bitfield.disp64)
5398 addr_prefix_disp = j;
5399 operand_types[j].bitfield.disp64 = 0;
5400 operand_types[j].bitfield.disp32 = 1;
5408 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5409 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5412 /* We check register size if needed. */
5413 check_register = t->opcode_modifier.checkregsize;
5414 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5415 switch (t->operands)
5418 if (!operand_type_match (overlap0, i.types[0]))
5422 /* xchg %eax, %eax is a special case. It is an alias for nop
5423 only in 32bit mode and we can use opcode 0x90. In 64bit
5424 mode, we can't use 0x90 for xchg %eax, %eax since it should
5425 zero-extend %eax to %rax. */
5426 if (flag_code == CODE_64BIT
5427 && t->base_opcode == 0x90
5428 && operand_type_equal (&i.types [0], &acc32)
5429 && operand_type_equal (&i.types [1], &acc32))
5431 /* If we want store form, we reverse direction of operands. */
5432 if (i.dir_encoding == dir_encoding_store
5433 && t->opcode_modifier.d)
5438 /* If we want store form, we skip the current load. */
5439 if (i.dir_encoding == dir_encoding_store
5440 && i.mem_operands == 0
5441 && t->opcode_modifier.load)
5446 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5447 if (!operand_type_match (overlap0, i.types[0])
5448 || !operand_type_match (overlap1, i.types[1])
5450 && !operand_type_register_match (i.types[0],
5455 /* Check if other direction is valid ... */
5456 if (!t->opcode_modifier.d)
5460 /* Try reversing direction of operands. */
5461 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5462 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5463 if (!operand_type_match (overlap0, i.types[0])
5464 || !operand_type_match (overlap1, i.types[1])
5466 && !operand_type_register_match (i.types[0],
5471 /* Does not match either direction. */
5474 /* found_reverse_match holds which of D or FloatR
5476 if (!t->opcode_modifier.d)
5477 found_reverse_match = 0;
5478 else if (operand_types[0].bitfield.tbyte)
5479 found_reverse_match = Opcode_FloatD;
5481 found_reverse_match = Opcode_D;
5482 if (t->opcode_modifier.floatr)
5483 found_reverse_match |= Opcode_FloatR;
5487 /* Found a forward 2 operand match here. */
5488 switch (t->operands)
5491 overlap4 = operand_type_and (i.types[4],
5495 overlap3 = operand_type_and (i.types[3],
5499 overlap2 = operand_type_and (i.types[2],
5504 switch (t->operands)
5507 if (!operand_type_match (overlap4, i.types[4])
5508 || !operand_type_register_match (i.types[3],
5515 if (!operand_type_match (overlap3, i.types[3])
5517 && !operand_type_register_match (i.types[2],
5524 /* Here we make use of the fact that there are no
5525 reverse match 3 operand instructions. */
5526 if (!operand_type_match (overlap2, i.types[2])
5528 && (!operand_type_register_match (i.types[0],
5532 || !operand_type_register_match (i.types[1],
5535 operand_types[2]))))
5540 /* Found either forward/reverse 2, 3 or 4 operand match here:
5541 slip through to break. */
5543 if (!found_cpu_match)
5545 found_reverse_match = 0;
5549 /* Check if vector and VEX operands are valid. */
5550 if (check_VecOperands (t) || VEX_check_operands (t))
5552 specific_error = i.error;
5556 /* We've found a match; break out of loop. */
5560 if (t == current_templates->end)
5562 /* We found no match. */
5563 const char *err_msg;
5564 switch (specific_error ? specific_error : i.error)
5568 case operand_size_mismatch:
5569 err_msg = _("operand size mismatch");
5571 case operand_type_mismatch:
5572 err_msg = _("operand type mismatch");
5574 case register_type_mismatch:
5575 err_msg = _("register type mismatch");
5577 case number_of_operands_mismatch:
5578 err_msg = _("number of operands mismatch");
5580 case invalid_instruction_suffix:
5581 err_msg = _("invalid instruction suffix");
5584 err_msg = _("constant doesn't fit in 4 bits");
5587 err_msg = _("only supported with old gcc");
5589 case unsupported_with_intel_mnemonic:
5590 err_msg = _("unsupported with Intel mnemonic");
5592 case unsupported_syntax:
5593 err_msg = _("unsupported syntax");
5596 as_bad (_("unsupported instruction `%s'"),
5597 current_templates->start->name);
5599 case invalid_vsib_address:
5600 err_msg = _("invalid VSIB address");
5602 case invalid_vector_register_set:
5603 err_msg = _("mask, index, and destination registers must be distinct");
5605 case unsupported_vector_index_register:
5606 err_msg = _("unsupported vector index register");
5608 case unsupported_broadcast:
5609 err_msg = _("unsupported broadcast");
5611 case broadcast_not_on_src_operand:
5612 err_msg = _("broadcast not on source memory operand");
5614 case broadcast_needed:
5615 err_msg = _("broadcast is needed for operand of such type");
5617 case unsupported_masking:
5618 err_msg = _("unsupported masking");
5620 case mask_not_on_destination:
5621 err_msg = _("mask not on destination operand");
5623 case no_default_mask:
5624 err_msg = _("default mask isn't allowed");
5626 case unsupported_rc_sae:
5627 err_msg = _("unsupported static rounding/sae");
5629 case rc_sae_operand_not_last_imm:
5631 err_msg = _("RC/SAE operand must precede immediate operands");
5633 err_msg = _("RC/SAE operand must follow immediate operands");
5635 case invalid_register_operand:
5636 err_msg = _("invalid register operand");
5639 as_bad (_("%s for `%s'"), err_msg,
5640 current_templates->start->name);
5644 if (!quiet_warnings)
5647 && (i.types[0].bitfield.jumpabsolute
5648 != operand_types[0].bitfield.jumpabsolute))
5650 as_warn (_("indirect %s without `*'"), t->name);
5653 if (t->opcode_modifier.isprefix
5654 && t->opcode_modifier.ignoresize)
5656 /* Warn them that a data or address size prefix doesn't
5657 affect assembly of the next line of code. */
5658 as_warn (_("stand-alone `%s' prefix"), t->name);
5662 /* Copy the template we found. */
5665 if (addr_prefix_disp != -1)
5666 i.tm.operand_types[addr_prefix_disp]
5667 = operand_types[addr_prefix_disp];
5669 if (found_reverse_match)
5671 /* If we found a reverse match we must alter the opcode
5672 direction bit. found_reverse_match holds bits to change
5673 (different for int & float insns). */
5675 i.tm.base_opcode ^= found_reverse_match;
5677 i.tm.operand_types[0] = operand_types[1];
5678 i.tm.operand_types[1] = operand_types[0];
5687 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5688 if (i.tm.operand_types[mem_op].bitfield.esseg)
5690 if (i.seg[0] != NULL && i.seg[0] != &es)
5692 as_bad (_("`%s' operand %d must use `%ses' segment"),
5698 /* There's only ever one segment override allowed per instruction.
5699 This instruction possibly has a legal segment override on the
5700 second operand, so copy the segment to where non-string
5701 instructions store it, allowing common code. */
5702 i.seg[0] = i.seg[1];
5704 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5706 if (i.seg[1] != NULL && i.seg[1] != &es)
5708 as_bad (_("`%s' operand %d must use `%ses' segment"),
5719 process_suffix (void)
5721 /* If matched instruction specifies an explicit instruction mnemonic
5723 if (i.tm.opcode_modifier.size16)
5724 i.suffix = WORD_MNEM_SUFFIX;
5725 else if (i.tm.opcode_modifier.size32)
5726 i.suffix = LONG_MNEM_SUFFIX;
5727 else if (i.tm.opcode_modifier.size64)
5728 i.suffix = QWORD_MNEM_SUFFIX;
5729 else if (i.reg_operands)
5731 /* If there's no instruction mnemonic suffix we try to invent one
5732 based on register operands. */
5735 /* We take i.suffix from the last register operand specified,
5736 Destination register type is more significant than source
5737 register type. crc32 in SSE4.2 prefers source register
5739 if (i.tm.base_opcode == 0xf20f38f1)
5741 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5742 i.suffix = WORD_MNEM_SUFFIX;
5743 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5744 i.suffix = LONG_MNEM_SUFFIX;
5745 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5746 i.suffix = QWORD_MNEM_SUFFIX;
5748 else if (i.tm.base_opcode == 0xf20f38f0)
5750 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5751 i.suffix = BYTE_MNEM_SUFFIX;
5758 if (i.tm.base_opcode == 0xf20f38f1
5759 || i.tm.base_opcode == 0xf20f38f0)
5761 /* We have to know the operand size for crc32. */
5762 as_bad (_("ambiguous memory operand size for `%s`"),
5767 for (op = i.operands; --op >= 0;)
5768 if (!i.tm.operand_types[op].bitfield.inoutportreg
5769 && !i.tm.operand_types[op].bitfield.shiftcount)
5771 if (!i.types[op].bitfield.reg)
5773 if (i.types[op].bitfield.byte)
5774 i.suffix = BYTE_MNEM_SUFFIX;
5775 else if (i.types[op].bitfield.word)
5776 i.suffix = WORD_MNEM_SUFFIX;
5777 else if (i.types[op].bitfield.dword)
5778 i.suffix = LONG_MNEM_SUFFIX;
5779 else if (i.types[op].bitfield.qword)
5780 i.suffix = QWORD_MNEM_SUFFIX;
5787 else if (i.suffix == BYTE_MNEM_SUFFIX)
5790 && i.tm.opcode_modifier.ignoresize
5791 && i.tm.opcode_modifier.no_bsuf)
5793 else if (!check_byte_reg ())
5796 else if (i.suffix == LONG_MNEM_SUFFIX)
5799 && i.tm.opcode_modifier.ignoresize
5800 && i.tm.opcode_modifier.no_lsuf)
5802 else if (!check_long_reg ())
5805 else if (i.suffix == QWORD_MNEM_SUFFIX)
5808 && i.tm.opcode_modifier.ignoresize
5809 && i.tm.opcode_modifier.no_qsuf)
5811 else if (!check_qword_reg ())
5814 else if (i.suffix == WORD_MNEM_SUFFIX)
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_wsuf)
5820 else if (!check_word_reg ())
5823 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5824 /* Do nothing if the instruction is going to ignore the prefix. */
5829 else if (i.tm.opcode_modifier.defaultsize
5831 /* exclude fldenv/frstor/fsave/fstenv */
5832 && i.tm.opcode_modifier.no_ssuf)
5834 i.suffix = stackop_size;
5836 else if (intel_syntax
5838 && (i.tm.operand_types[0].bitfield.jumpabsolute
5839 || i.tm.opcode_modifier.jumpbyte
5840 || i.tm.opcode_modifier.jumpintersegment
5841 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5842 && i.tm.extension_opcode <= 3)))
5847 if (!i.tm.opcode_modifier.no_qsuf)
5849 i.suffix = QWORD_MNEM_SUFFIX;
5854 if (!i.tm.opcode_modifier.no_lsuf)
5855 i.suffix = LONG_MNEM_SUFFIX;
5858 if (!i.tm.opcode_modifier.no_wsuf)
5859 i.suffix = WORD_MNEM_SUFFIX;
5868 if (i.tm.opcode_modifier.w)
5870 as_bad (_("no instruction mnemonic suffix given and "
5871 "no register operands; can't size instruction"));
5877 unsigned int suffixes;
5879 suffixes = !i.tm.opcode_modifier.no_bsuf;
5880 if (!i.tm.opcode_modifier.no_wsuf)
5882 if (!i.tm.opcode_modifier.no_lsuf)
5884 if (!i.tm.opcode_modifier.no_ldsuf)
5886 if (!i.tm.opcode_modifier.no_ssuf)
5888 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5891 /* There are more than suffix matches. */
5892 if (i.tm.opcode_modifier.w
5893 || ((suffixes & (suffixes - 1))
5894 && !i.tm.opcode_modifier.defaultsize
5895 && !i.tm.opcode_modifier.ignoresize))
5897 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5903 /* Change the opcode based on the operand size given by i.suffix. */
5906 /* Size floating point instruction. */
5907 case LONG_MNEM_SUFFIX:
5908 if (i.tm.opcode_modifier.floatmf)
5910 i.tm.base_opcode ^= 4;
5914 case WORD_MNEM_SUFFIX:
5915 case QWORD_MNEM_SUFFIX:
5916 /* It's not a byte, select word/dword operation. */
5917 if (i.tm.opcode_modifier.w)
5919 if (i.tm.opcode_modifier.shortform)
5920 i.tm.base_opcode |= 8;
5922 i.tm.base_opcode |= 1;
5925 case SHORT_MNEM_SUFFIX:
5926 /* Now select between word & dword operations via the operand
5927 size prefix, except for instructions that will ignore this
5929 if (i.tm.opcode_modifier.addrprefixop0)
5931 /* The address size override prefix changes the size of the
5933 if ((flag_code == CODE_32BIT
5934 && i.op->regs[0].reg_type.bitfield.word)
5935 || (flag_code != CODE_32BIT
5936 && i.op->regs[0].reg_type.bitfield.dword))
5937 if (!add_prefix (ADDR_PREFIX_OPCODE))
5940 else if (i.suffix != QWORD_MNEM_SUFFIX
5941 && !i.tm.opcode_modifier.ignoresize
5942 && !i.tm.opcode_modifier.floatmf
5943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5944 || (flag_code == CODE_64BIT
5945 && i.tm.opcode_modifier.jumpbyte)))
5947 unsigned int prefix = DATA_PREFIX_OPCODE;
5949 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5950 prefix = ADDR_PREFIX_OPCODE;
5952 if (!add_prefix (prefix))
5956 /* Set mode64 for an operand. */
5957 if (i.suffix == QWORD_MNEM_SUFFIX
5958 && flag_code == CODE_64BIT
5959 && !i.tm.opcode_modifier.norex64
5960 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5962 && ! (i.operands == 2
5963 && i.tm.base_opcode == 0x90
5964 && i.tm.extension_opcode == None
5965 && operand_type_equal (&i.types [0], &acc64)
5966 && operand_type_equal (&i.types [1], &acc64)))
5976 check_byte_reg (void)
5980 for (op = i.operands; --op >= 0;)
5982 /* Skip non-register operands. */
5983 if (!i.types[op].bitfield.reg)
5986 /* If this is an eight bit register, it's OK. If it's the 16 or
5987 32 bit version of an eight bit register, we will just use the
5988 low portion, and that's OK too. */
5989 if (i.types[op].bitfield.byte)
5992 /* I/O port address operands are OK too. */
5993 if (i.tm.operand_types[op].bitfield.inoutportreg)
5996 /* crc32 doesn't generate this warning. */
5997 if (i.tm.base_opcode == 0xf20f38f0)
6000 if ((i.types[op].bitfield.word
6001 || i.types[op].bitfield.dword
6002 || i.types[op].bitfield.qword)
6003 && i.op[op].regs->reg_num < 4
6004 /* Prohibit these changes in 64bit mode, since the lowering
6005 would be more complicated. */
6006 && flag_code != CODE_64BIT)
6008 #if REGISTER_WARNINGS
6009 if (!quiet_warnings)
6010 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6012 (i.op[op].regs + (i.types[op].bitfield.word
6013 ? REGNAM_AL - REGNAM_AX
6014 : REGNAM_AL - REGNAM_EAX))->reg_name,
6016 i.op[op].regs->reg_name,
6021 /* Any other register is bad. */
6022 if (i.types[op].bitfield.reg
6023 || i.types[op].bitfield.regmmx
6024 || i.types[op].bitfield.regsimd
6025 || i.types[op].bitfield.sreg2
6026 || i.types[op].bitfield.sreg3
6027 || i.types[op].bitfield.control
6028 || i.types[op].bitfield.debug
6029 || i.types[op].bitfield.test)
6031 as_bad (_("`%s%s' not allowed with `%s%c'"),
6033 i.op[op].regs->reg_name,
6043 check_long_reg (void)
6047 for (op = i.operands; --op >= 0;)
6048 /* Skip non-register operands. */
6049 if (!i.types[op].bitfield.reg)
6051 /* Reject eight bit registers, except where the template requires
6052 them. (eg. movzb) */
6053 else if (i.types[op].bitfield.byte
6054 && (i.tm.operand_types[op].bitfield.reg
6055 || i.tm.operand_types[op].bitfield.acc)
6056 && (i.tm.operand_types[op].bitfield.word
6057 || i.tm.operand_types[op].bitfield.dword))
6059 as_bad (_("`%s%s' not allowed with `%s%c'"),
6061 i.op[op].regs->reg_name,
6066 /* Warn if the e prefix on a general reg is missing. */
6067 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6068 && i.types[op].bitfield.word
6069 && (i.tm.operand_types[op].bitfield.reg
6070 || i.tm.operand_types[op].bitfield.acc)
6071 && i.tm.operand_types[op].bitfield.dword)
6073 /* Prohibit these changes in the 64bit mode, since the
6074 lowering is more complicated. */
6075 if (flag_code == CODE_64BIT)
6077 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6078 register_prefix, i.op[op].regs->reg_name,
6082 #if REGISTER_WARNINGS
6083 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6085 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6086 register_prefix, i.op[op].regs->reg_name, i.suffix);
6089 /* Warn if the r prefix on a general reg is present. */
6090 else if (i.types[op].bitfield.qword
6091 && (i.tm.operand_types[op].bitfield.reg
6092 || i.tm.operand_types[op].bitfield.acc)
6093 && i.tm.operand_types[op].bitfield.dword)
6096 && i.tm.opcode_modifier.toqword
6097 && !i.types[0].bitfield.regsimd)
6099 /* Convert to QWORD. We want REX byte. */
6100 i.suffix = QWORD_MNEM_SUFFIX;
6104 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6105 register_prefix, i.op[op].regs->reg_name,
6114 check_qword_reg (void)
6118 for (op = i.operands; --op >= 0; )
6119 /* Skip non-register operands. */
6120 if (!i.types[op].bitfield.reg)
6122 /* Reject eight bit registers, except where the template requires
6123 them. (eg. movzb) */
6124 else if (i.types[op].bitfield.byte
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && (i.tm.operand_types[op].bitfield.word
6128 || i.tm.operand_types[op].bitfield.dword))
6130 as_bad (_("`%s%s' not allowed with `%s%c'"),
6132 i.op[op].regs->reg_name,
6137 /* Warn if the r prefix on a general reg is missing. */
6138 else if ((i.types[op].bitfield.word
6139 || i.types[op].bitfield.dword)
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && i.tm.operand_types[op].bitfield.qword)
6144 /* Prohibit these changes in the 64bit mode, since the
6145 lowering is more complicated. */
6147 && i.tm.opcode_modifier.todword
6148 && !i.types[0].bitfield.regsimd)
6150 /* Convert to DWORD. We don't want REX byte. */
6151 i.suffix = LONG_MNEM_SUFFIX;
6155 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6156 register_prefix, i.op[op].regs->reg_name,
6165 check_word_reg (void)
6168 for (op = i.operands; --op >= 0;)
6169 /* Skip non-register operands. */
6170 if (!i.types[op].bitfield.reg)
6172 /* Reject eight bit registers, except where the template requires
6173 them. (eg. movzb) */
6174 else if (i.types[op].bitfield.byte
6175 && (i.tm.operand_types[op].bitfield.reg
6176 || i.tm.operand_types[op].bitfield.acc)
6177 && (i.tm.operand_types[op].bitfield.word
6178 || i.tm.operand_types[op].bitfield.dword))
6180 as_bad (_("`%s%s' not allowed with `%s%c'"),
6182 i.op[op].regs->reg_name,
6187 /* Warn if the e or r prefix on a general reg is present. */
6188 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6189 && (i.types[op].bitfield.dword
6190 || i.types[op].bitfield.qword)
6191 && (i.tm.operand_types[op].bitfield.reg
6192 || i.tm.operand_types[op].bitfield.acc)
6193 && i.tm.operand_types[op].bitfield.word)
6195 /* Prohibit these changes in the 64bit mode, since the
6196 lowering is more complicated. */
6197 if (flag_code == CODE_64BIT)
6199 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6200 register_prefix, i.op[op].regs->reg_name,
6204 #if REGISTER_WARNINGS
6205 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6207 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6208 register_prefix, i.op[op].regs->reg_name, i.suffix);
6215 update_imm (unsigned int j)
6217 i386_operand_type overlap = i.types[j];
6218 if ((overlap.bitfield.imm8
6219 || overlap.bitfield.imm8s
6220 || overlap.bitfield.imm16
6221 || overlap.bitfield.imm32
6222 || overlap.bitfield.imm32s
6223 || overlap.bitfield.imm64)
6224 && !operand_type_equal (&overlap, &imm8)
6225 && !operand_type_equal (&overlap, &imm8s)
6226 && !operand_type_equal (&overlap, &imm16)
6227 && !operand_type_equal (&overlap, &imm32)
6228 && !operand_type_equal (&overlap, &imm32s)
6229 && !operand_type_equal (&overlap, &imm64))
6233 i386_operand_type temp;
6235 operand_type_set (&temp, 0);
6236 if (i.suffix == BYTE_MNEM_SUFFIX)
6238 temp.bitfield.imm8 = overlap.bitfield.imm8;
6239 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6241 else if (i.suffix == WORD_MNEM_SUFFIX)
6242 temp.bitfield.imm16 = overlap.bitfield.imm16;
6243 else if (i.suffix == QWORD_MNEM_SUFFIX)
6245 temp.bitfield.imm64 = overlap.bitfield.imm64;
6246 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6249 temp.bitfield.imm32 = overlap.bitfield.imm32;
6252 else if (operand_type_equal (&overlap, &imm16_32_32s)
6253 || operand_type_equal (&overlap, &imm16_32)
6254 || operand_type_equal (&overlap, &imm16_32s))
6256 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6261 if (!operand_type_equal (&overlap, &imm8)
6262 && !operand_type_equal (&overlap, &imm8s)
6263 && !operand_type_equal (&overlap, &imm16)
6264 && !operand_type_equal (&overlap, &imm32)
6265 && !operand_type_equal (&overlap, &imm32s)
6266 && !operand_type_equal (&overlap, &imm64))
6268 as_bad (_("no instruction mnemonic suffix given; "
6269 "can't determine immediate size"));
6273 i.types[j] = overlap;
6283 /* Update the first 2 immediate operands. */
6284 n = i.operands > 2 ? 2 : i.operands;
6287 for (j = 0; j < n; j++)
6288 if (update_imm (j) == 0)
6291 /* The 3rd operand can't be immediate operand. */
6292 gas_assert (operand_type_check (i.types[2], imm) == 0);
6299 process_operands (void)
6301 /* Default segment register this instruction will use for memory
6302 accesses. 0 means unknown. This is only for optimizing out
6303 unnecessary segment overrides. */
6304 const seg_entry *default_seg = 0;
6306 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6308 unsigned int dupl = i.operands;
6309 unsigned int dest = dupl - 1;
6312 /* The destination must be an xmm register. */
6313 gas_assert (i.reg_operands
6314 && MAX_OPERANDS > dupl
6315 && operand_type_equal (&i.types[dest], ®xmm));
6317 if (i.tm.operand_types[0].bitfield.acc
6318 && i.tm.operand_types[0].bitfield.xmmword)
6320 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6322 /* Keep xmm0 for instructions with VEX prefix and 3
6324 i.tm.operand_types[0].bitfield.acc = 0;
6325 i.tm.operand_types[0].bitfield.regsimd = 1;
6330 /* We remove the first xmm0 and keep the number of
6331 operands unchanged, which in fact duplicates the
6333 for (j = 1; j < i.operands; j++)
6335 i.op[j - 1] = i.op[j];
6336 i.types[j - 1] = i.types[j];
6337 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6341 else if (i.tm.opcode_modifier.implicit1stxmm0)
6343 gas_assert ((MAX_OPERANDS - 1) > dupl
6344 && (i.tm.opcode_modifier.vexsources
6347 /* Add the implicit xmm0 for instructions with VEX prefix
6349 for (j = i.operands; j > 0; j--)
6351 i.op[j] = i.op[j - 1];
6352 i.types[j] = i.types[j - 1];
6353 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6356 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6357 i.types[0] = regxmm;
6358 i.tm.operand_types[0] = regxmm;
6361 i.reg_operands += 2;
6366 i.op[dupl] = i.op[dest];
6367 i.types[dupl] = i.types[dest];
6368 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6377 i.op[dupl] = i.op[dest];
6378 i.types[dupl] = i.types[dest];
6379 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6382 if (i.tm.opcode_modifier.immext)
6385 else if (i.tm.operand_types[0].bitfield.acc
6386 && i.tm.operand_types[0].bitfield.xmmword)
6390 for (j = 1; j < i.operands; j++)
6392 i.op[j - 1] = i.op[j];
6393 i.types[j - 1] = i.types[j];
6395 /* We need to adjust fields in i.tm since they are used by
6396 build_modrm_byte. */
6397 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6404 else if (i.tm.opcode_modifier.implicitquadgroup)
6406 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6408 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6409 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6410 regnum = register_number (i.op[1].regs);
6411 first_reg_in_group = regnum & ~3;
6412 last_reg_in_group = first_reg_in_group + 3;
6413 if (regnum != first_reg_in_group)
6414 as_warn (_("source register `%s%s' implicitly denotes"
6415 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6416 register_prefix, i.op[1].regs->reg_name,
6417 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6418 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6421 else if (i.tm.opcode_modifier.regkludge)
6423 /* The imul $imm, %reg instruction is converted into
6424 imul $imm, %reg, %reg, and the clr %reg instruction
6425 is converted into xor %reg, %reg. */
6427 unsigned int first_reg_op;
6429 if (operand_type_check (i.types[0], reg))
6433 /* Pretend we saw the extra register operand. */
6434 gas_assert (i.reg_operands == 1
6435 && i.op[first_reg_op + 1].regs == 0);
6436 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6437 i.types[first_reg_op + 1] = i.types[first_reg_op];
6442 if (i.tm.opcode_modifier.shortform)
6444 if (i.types[0].bitfield.sreg2
6445 || i.types[0].bitfield.sreg3)
6447 if (i.tm.base_opcode == POP_SEG_SHORT
6448 && i.op[0].regs->reg_num == 1)
6450 as_bad (_("you can't `pop %scs'"), register_prefix);
6453 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6454 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6459 /* The register or float register operand is in operand
6463 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6464 || operand_type_check (i.types[0], reg))
6468 /* Register goes in low 3 bits of opcode. */
6469 i.tm.base_opcode |= i.op[op].regs->reg_num;
6470 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6472 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6474 /* Warn about some common errors, but press on regardless.
6475 The first case can be generated by gcc (<= 2.8.1). */
6476 if (i.operands == 2)
6478 /* Reversed arguments on faddp, fsubp, etc. */
6479 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6480 register_prefix, i.op[!intel_syntax].regs->reg_name,
6481 register_prefix, i.op[intel_syntax].regs->reg_name);
6485 /* Extraneous `l' suffix on fp insn. */
6486 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6487 register_prefix, i.op[0].regs->reg_name);
6492 else if (i.tm.opcode_modifier.modrm)
6494 /* The opcode is completed (modulo i.tm.extension_opcode which
6495 must be put into the modrm byte). Now, we make the modrm and
6496 index base bytes based on all the info we've collected. */
6498 default_seg = build_modrm_byte ();
6500 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6504 else if (i.tm.opcode_modifier.isstring)
6506 /* For the string instructions that allow a segment override
6507 on one of their operands, the default segment is ds. */
6511 if (i.tm.base_opcode == 0x8d /* lea */
6514 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6516 /* If a segment was explicitly specified, and the specified segment
6517 is not the default, use an opcode prefix to select it. If we
6518 never figured out what the default segment is, then default_seg
6519 will be zero at this point, and the specified segment prefix will
6521 if ((i.seg[0]) && (i.seg[0] != default_seg))
6523 if (!add_prefix (i.seg[0]->seg_prefix))
6529 static const seg_entry *
6530 build_modrm_byte (void)
6532 const seg_entry *default_seg = 0;
6533 unsigned int source, dest;
6536 /* The first operand of instructions with VEX prefix and 3 sources
6537 must be VEX_Imm4. */
6538 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6541 unsigned int nds, reg_slot;
6544 if (i.tm.opcode_modifier.veximmext
6545 && i.tm.opcode_modifier.immext)
6547 dest = i.operands - 2;
6548 gas_assert (dest == 3);
6551 dest = i.operands - 1;
6554 /* There are 2 kinds of instructions:
6555 1. 5 operands: 4 register operands or 3 register operands
6556 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6557 VexW0 or VexW1. The destination must be either XMM, YMM or
6559 2. 4 operands: 4 register operands or 3 register operands
6560 plus 1 memory operand, VexXDS, and VexImmExt */
6561 gas_assert ((i.reg_operands == 4
6562 || (i.reg_operands == 3 && i.mem_operands == 1))
6563 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6564 && (i.tm.opcode_modifier.veximmext
6565 || (i.imm_operands == 1
6566 && i.types[0].bitfield.vec_imm4
6567 && (i.tm.opcode_modifier.vexw == VEXW0
6568 || i.tm.opcode_modifier.vexw == VEXW1)
6569 && i.tm.operand_types[dest].bitfield.regsimd)));
6571 if (i.imm_operands == 0)
6573 /* When there is no immediate operand, generate an 8bit
6574 immediate operand to encode the first operand. */
6575 exp = &im_expressions[i.imm_operands++];
6576 i.op[i.operands].imms = exp;
6577 i.types[i.operands] = imm8;
6579 /* If VexW1 is set, the first operand is the source and
6580 the second operand is encoded in the immediate operand. */
6581 if (i.tm.opcode_modifier.vexw == VEXW1)
6592 /* FMA swaps REG and NDS. */
6593 if (i.tm.cpu_flags.bitfield.cpufma)
6601 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6602 exp->X_op = O_constant;
6603 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6604 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6608 unsigned int imm_slot;
6610 if (i.tm.opcode_modifier.vexw == VEXW0)
6612 /* If VexW0 is set, the third operand is the source and
6613 the second operand is encoded in the immediate
6620 /* VexW1 is set, the second operand is the source and
6621 the third operand is encoded in the immediate
6627 if (i.tm.opcode_modifier.immext)
6629 /* When ImmExt is set, the immediate byte is the last
6631 imm_slot = i.operands - 1;
6639 /* Turn on Imm8 so that output_imm will generate it. */
6640 i.types[imm_slot].bitfield.imm8 = 1;
6643 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6644 i.op[imm_slot].imms->X_add_number
6645 |= register_number (i.op[reg_slot].regs) << 4;
6646 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6649 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6650 i.vex.register_specifier = i.op[nds].regs;
6655 /* i.reg_operands MUST be the number of real register operands;
6656 implicit registers do not count. If there are 3 register
6657 operands, it must be a instruction with VexNDS. For a
6658 instruction with VexNDD, the destination register is encoded
6659 in VEX prefix. If there are 4 register operands, it must be
6660 a instruction with VEX prefix and 3 sources. */
6661 if (i.mem_operands == 0
6662 && ((i.reg_operands == 2
6663 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6664 || (i.reg_operands == 3
6665 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6666 || (i.reg_operands == 4 && vex_3_sources)))
6674 /* When there are 3 operands, one of them may be immediate,
6675 which may be the first or the last operand. Otherwise,
6676 the first operand must be shift count register (cl) or it
6677 is an instruction with VexNDS. */
6678 gas_assert (i.imm_operands == 1
6679 || (i.imm_operands == 0
6680 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6681 || i.types[0].bitfield.shiftcount)));
6682 if (operand_type_check (i.types[0], imm)
6683 || i.types[0].bitfield.shiftcount)
6689 /* When there are 4 operands, the first two must be 8bit
6690 immediate operands. The source operand will be the 3rd
6693 For instructions with VexNDS, if the first operand
6694 an imm8, the source operand is the 2nd one. If the last
6695 operand is imm8, the source operand is the first one. */
6696 gas_assert ((i.imm_operands == 2
6697 && i.types[0].bitfield.imm8
6698 && i.types[1].bitfield.imm8)
6699 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6700 && i.imm_operands == 1
6701 && (i.types[0].bitfield.imm8
6702 || i.types[i.operands - 1].bitfield.imm8
6704 if (i.imm_operands == 2)
6708 if (i.types[0].bitfield.imm8)
6715 if (is_evex_encoding (&i.tm))
6717 /* For EVEX instructions, when there are 5 operands, the
6718 first one must be immediate operand. If the second one
6719 is immediate operand, the source operand is the 3th
6720 one. If the last one is immediate operand, the source
6721 operand is the 2nd one. */
6722 gas_assert (i.imm_operands == 2
6723 && i.tm.opcode_modifier.sae
6724 && operand_type_check (i.types[0], imm));
6725 if (operand_type_check (i.types[1], imm))
6727 else if (operand_type_check (i.types[4], imm))
6741 /* RC/SAE operand could be between DEST and SRC. That happens
6742 when one operand is GPR and the other one is XMM/YMM/ZMM
6744 if (i.rounding && i.rounding->operand == (int) dest)
6747 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6749 /* For instructions with VexNDS, the register-only source
6750 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6751 register. It is encoded in VEX prefix. We need to
6752 clear RegMem bit before calling operand_type_equal. */
6754 i386_operand_type op;
6757 /* Check register-only source operand when two source
6758 operands are swapped. */
6759 if (!i.tm.operand_types[source].bitfield.baseindex
6760 && i.tm.operand_types[dest].bitfield.baseindex)
6768 op = i.tm.operand_types[vvvv];
6769 op.bitfield.regmem = 0;
6770 if ((dest + 1) >= i.operands
6771 || ((!op.bitfield.reg
6772 || (!op.bitfield.dword && !op.bitfield.qword))
6773 && !op.bitfield.regsimd
6774 && !operand_type_equal (&op, ®mask)))
6776 i.vex.register_specifier = i.op[vvvv].regs;
6782 /* One of the register operands will be encoded in the i.tm.reg
6783 field, the other in the combined i.tm.mode and i.tm.regmem
6784 fields. If no form of this instruction supports a memory
6785 destination operand, then we assume the source operand may
6786 sometimes be a memory operand and so we need to store the
6787 destination in the i.rm.reg field. */
6788 if (!i.tm.operand_types[dest].bitfield.regmem
6789 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6791 i.rm.reg = i.op[dest].regs->reg_num;
6792 i.rm.regmem = i.op[source].regs->reg_num;
6793 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6795 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6797 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6799 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6804 i.rm.reg = i.op[source].regs->reg_num;
6805 i.rm.regmem = i.op[dest].regs->reg_num;
6806 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6808 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6810 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6812 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6815 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6817 if (!i.types[0].bitfield.control
6818 && !i.types[1].bitfield.control)
6820 i.rex &= ~(REX_R | REX_B);
6821 add_prefix (LOCK_PREFIX_OPCODE);
6825 { /* If it's not 2 reg operands... */
6830 unsigned int fake_zero_displacement = 0;
6833 for (op = 0; op < i.operands; op++)
6834 if (operand_type_check (i.types[op], anymem))
6836 gas_assert (op < i.operands);
6838 if (i.tm.opcode_modifier.vecsib)
6840 if (i.index_reg->reg_num == RegEiz
6841 || i.index_reg->reg_num == RegRiz)
6844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6847 i.sib.base = NO_BASE_REGISTER;
6848 i.sib.scale = i.log2_scale_factor;
6849 i.types[op].bitfield.disp8 = 0;
6850 i.types[op].bitfield.disp16 = 0;
6851 i.types[op].bitfield.disp64 = 0;
6852 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6854 /* Must be 32 bit */
6855 i.types[op].bitfield.disp32 = 1;
6856 i.types[op].bitfield.disp32s = 0;
6860 i.types[op].bitfield.disp32 = 0;
6861 i.types[op].bitfield.disp32s = 1;
6864 i.sib.index = i.index_reg->reg_num;
6865 if ((i.index_reg->reg_flags & RegRex) != 0)
6867 if ((i.index_reg->reg_flags & RegVRex) != 0)
6873 if (i.base_reg == 0)
6876 if (!i.disp_operands)
6877 fake_zero_displacement = 1;
6878 if (i.index_reg == 0)
6880 i386_operand_type newdisp;
6882 gas_assert (!i.tm.opcode_modifier.vecsib);
6883 /* Operand is just <disp> */
6884 if (flag_code == CODE_64BIT)
6886 /* 64bit mode overwrites the 32bit absolute
6887 addressing by RIP relative addressing and
6888 absolute addressing is encoded by one of the
6889 redundant SIB forms. */
6890 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6891 i.sib.base = NO_BASE_REGISTER;
6892 i.sib.index = NO_INDEX_REGISTER;
6893 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6895 else if ((flag_code == CODE_16BIT)
6896 ^ (i.prefix[ADDR_PREFIX] != 0))
6898 i.rm.regmem = NO_BASE_REGISTER_16;
6903 i.rm.regmem = NO_BASE_REGISTER;
6906 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6907 i.types[op] = operand_type_or (i.types[op], newdisp);
6909 else if (!i.tm.opcode_modifier.vecsib)
6911 /* !i.base_reg && i.index_reg */
6912 if (i.index_reg->reg_num == RegEiz
6913 || i.index_reg->reg_num == RegRiz)
6914 i.sib.index = NO_INDEX_REGISTER;
6916 i.sib.index = i.index_reg->reg_num;
6917 i.sib.base = NO_BASE_REGISTER;
6918 i.sib.scale = i.log2_scale_factor;
6919 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6920 i.types[op].bitfield.disp8 = 0;
6921 i.types[op].bitfield.disp16 = 0;
6922 i.types[op].bitfield.disp64 = 0;
6923 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6925 /* Must be 32 bit */
6926 i.types[op].bitfield.disp32 = 1;
6927 i.types[op].bitfield.disp32s = 0;
6931 i.types[op].bitfield.disp32 = 0;
6932 i.types[op].bitfield.disp32s = 1;
6934 if ((i.index_reg->reg_flags & RegRex) != 0)
6938 /* RIP addressing for 64bit mode. */
6939 else if (i.base_reg->reg_num == RegRip ||
6940 i.base_reg->reg_num == RegEip)
6942 gas_assert (!i.tm.opcode_modifier.vecsib);
6943 i.rm.regmem = NO_BASE_REGISTER;
6944 i.types[op].bitfield.disp8 = 0;
6945 i.types[op].bitfield.disp16 = 0;
6946 i.types[op].bitfield.disp32 = 0;
6947 i.types[op].bitfield.disp32s = 1;
6948 i.types[op].bitfield.disp64 = 0;
6949 i.flags[op] |= Operand_PCrel;
6950 if (! i.disp_operands)
6951 fake_zero_displacement = 1;
6953 else if (i.base_reg->reg_type.bitfield.word)
6955 gas_assert (!i.tm.opcode_modifier.vecsib);
6956 switch (i.base_reg->reg_num)
6959 if (i.index_reg == 0)
6961 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6962 i.rm.regmem = i.index_reg->reg_num - 6;
6966 if (i.index_reg == 0)
6969 if (operand_type_check (i.types[op], disp) == 0)
6971 /* fake (%bp) into 0(%bp) */
6972 i.types[op].bitfield.disp8 = 1;
6973 fake_zero_displacement = 1;
6976 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6977 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6979 default: /* (%si) -> 4 or (%di) -> 5 */
6980 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6982 i.rm.mode = mode_from_disp_size (i.types[op]);
6984 else /* i.base_reg and 32/64 bit mode */
6986 if (flag_code == CODE_64BIT
6987 && operand_type_check (i.types[op], disp))
6989 i.types[op].bitfield.disp16 = 0;
6990 i.types[op].bitfield.disp64 = 0;
6991 if (i.prefix[ADDR_PREFIX] == 0)
6993 i.types[op].bitfield.disp32 = 0;
6994 i.types[op].bitfield.disp32s = 1;
6998 i.types[op].bitfield.disp32 = 1;
6999 i.types[op].bitfield.disp32s = 0;
7003 if (!i.tm.opcode_modifier.vecsib)
7004 i.rm.regmem = i.base_reg->reg_num;
7005 if ((i.base_reg->reg_flags & RegRex) != 0)
7007 i.sib.base = i.base_reg->reg_num;
7008 /* x86-64 ignores REX prefix bit here to avoid decoder
7010 if (!(i.base_reg->reg_flags & RegRex)
7011 && (i.base_reg->reg_num == EBP_REG_NUM
7012 || i.base_reg->reg_num == ESP_REG_NUM))
7014 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7016 fake_zero_displacement = 1;
7017 i.types[op].bitfield.disp8 = 1;
7019 i.sib.scale = i.log2_scale_factor;
7020 if (i.index_reg == 0)
7022 gas_assert (!i.tm.opcode_modifier.vecsib);
7023 /* <disp>(%esp) becomes two byte modrm with no index
7024 register. We've already stored the code for esp
7025 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7026 Any base register besides %esp will not use the
7027 extra modrm byte. */
7028 i.sib.index = NO_INDEX_REGISTER;
7030 else if (!i.tm.opcode_modifier.vecsib)
7032 if (i.index_reg->reg_num == RegEiz
7033 || i.index_reg->reg_num == RegRiz)
7034 i.sib.index = NO_INDEX_REGISTER;
7036 i.sib.index = i.index_reg->reg_num;
7037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7038 if ((i.index_reg->reg_flags & RegRex) != 0)
7043 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7044 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7048 if (!fake_zero_displacement
7052 fake_zero_displacement = 1;
7053 if (i.disp_encoding == disp_encoding_8bit)
7054 i.types[op].bitfield.disp8 = 1;
7056 i.types[op].bitfield.disp32 = 1;
7058 i.rm.mode = mode_from_disp_size (i.types[op]);
7062 if (fake_zero_displacement)
7064 /* Fakes a zero displacement assuming that i.types[op]
7065 holds the correct displacement size. */
7068 gas_assert (i.op[op].disps == 0);
7069 exp = &disp_expressions[i.disp_operands++];
7070 i.op[op].disps = exp;
7071 exp->X_op = O_constant;
7072 exp->X_add_number = 0;
7073 exp->X_add_symbol = (symbolS *) 0;
7074 exp->X_op_symbol = (symbolS *) 0;
7082 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7084 if (operand_type_check (i.types[0], imm))
7085 i.vex.register_specifier = NULL;
7088 /* VEX.vvvv encodes one of the sources when the first
7089 operand is not an immediate. */
7090 if (i.tm.opcode_modifier.vexw == VEXW0)
7091 i.vex.register_specifier = i.op[0].regs;
7093 i.vex.register_specifier = i.op[1].regs;
7096 /* Destination is a XMM register encoded in the ModRM.reg
7098 i.rm.reg = i.op[2].regs->reg_num;
7099 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7102 /* ModRM.rm and VEX.B encodes the other source. */
7103 if (!i.mem_operands)
7107 if (i.tm.opcode_modifier.vexw == VEXW0)
7108 i.rm.regmem = i.op[1].regs->reg_num;
7110 i.rm.regmem = i.op[0].regs->reg_num;
7112 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7116 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7118 i.vex.register_specifier = i.op[2].regs;
7119 if (!i.mem_operands)
7122 i.rm.regmem = i.op[1].regs->reg_num;
7123 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7127 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7128 (if any) based on i.tm.extension_opcode. Again, we must be
7129 careful to make sure that segment/control/debug/test/MMX
7130 registers are coded into the i.rm.reg field. */
7131 else if (i.reg_operands)
7134 unsigned int vex_reg = ~0;
7136 for (op = 0; op < i.operands; op++)
7137 if (i.types[op].bitfield.reg
7138 || i.types[op].bitfield.regmmx
7139 || i.types[op].bitfield.regsimd
7140 || i.types[op].bitfield.regbnd
7141 || i.types[op].bitfield.regmask
7142 || i.types[op].bitfield.sreg2
7143 || i.types[op].bitfield.sreg3
7144 || i.types[op].bitfield.control
7145 || i.types[op].bitfield.debug
7146 || i.types[op].bitfield.test)
7151 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7153 /* For instructions with VexNDS, the register-only
7154 source operand is encoded in VEX prefix. */
7155 gas_assert (mem != (unsigned int) ~0);
7160 gas_assert (op < i.operands);
7164 /* Check register-only source operand when two source
7165 operands are swapped. */
7166 if (!i.tm.operand_types[op].bitfield.baseindex
7167 && i.tm.operand_types[op + 1].bitfield.baseindex)
7171 gas_assert (mem == (vex_reg + 1)
7172 && op < i.operands);
7177 gas_assert (vex_reg < i.operands);
7181 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7183 /* For instructions with VexNDD, the register destination
7184 is encoded in VEX prefix. */
7185 if (i.mem_operands == 0)
7187 /* There is no memory operand. */
7188 gas_assert ((op + 2) == i.operands);
7193 /* There are only 2 non-immediate operands. */
7194 gas_assert (op < i.imm_operands + 2
7195 && i.operands == i.imm_operands + 2);
7196 vex_reg = i.imm_operands + 1;
7200 gas_assert (op < i.operands);
7202 if (vex_reg != (unsigned int) ~0)
7204 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7206 if ((!type->bitfield.reg
7207 || (!type->bitfield.dword && !type->bitfield.qword))
7208 && !type->bitfield.regsimd
7209 && !operand_type_equal (type, ®mask))
7212 i.vex.register_specifier = i.op[vex_reg].regs;
7215 /* Don't set OP operand twice. */
7218 /* If there is an extension opcode to put here, the
7219 register number must be put into the regmem field. */
7220 if (i.tm.extension_opcode != None)
7222 i.rm.regmem = i.op[op].regs->reg_num;
7223 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7225 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7230 i.rm.reg = i.op[op].regs->reg_num;
7231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7233 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7238 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7239 must set it to 3 to indicate this is a register operand
7240 in the regmem field. */
7241 if (!i.mem_operands)
7245 /* Fill in i.rm.reg field with extension opcode (if any). */
7246 if (i.tm.extension_opcode != None)
7247 i.rm.reg = i.tm.extension_opcode;
7253 output_branch (void)
7259 relax_substateT subtype;
7263 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7264 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7267 if (i.prefix[DATA_PREFIX] != 0)
7273 /* Pentium4 branch hints. */
7274 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7275 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7280 if (i.prefix[REX_PREFIX] != 0)
7286 /* BND prefixed jump. */
7287 if (i.prefix[BND_PREFIX] != 0)
7289 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7293 if (i.prefixes != 0 && !intel_syntax)
7294 as_warn (_("skipping prefixes on this instruction"));
7296 /* It's always a symbol; End frag & setup for relax.
7297 Make sure there is enough room in this frag for the largest
7298 instruction we may generate in md_convert_frag. This is 2
7299 bytes for the opcode and room for the prefix and largest
7301 frag_grow (prefix + 2 + 4);
7302 /* Prefix and 1 opcode byte go in fr_fix. */
7303 p = frag_more (prefix + 1);
7304 if (i.prefix[DATA_PREFIX] != 0)
7305 *p++ = DATA_PREFIX_OPCODE;
7306 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7307 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7308 *p++ = i.prefix[SEG_PREFIX];
7309 if (i.prefix[REX_PREFIX] != 0)
7310 *p++ = i.prefix[REX_PREFIX];
7311 *p = i.tm.base_opcode;
7313 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7314 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7315 else if (cpu_arch_flags.bitfield.cpui386)
7316 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7318 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7321 sym = i.op[0].disps->X_add_symbol;
7322 off = i.op[0].disps->X_add_number;
7324 if (i.op[0].disps->X_op != O_constant
7325 && i.op[0].disps->X_op != O_symbol)
7327 /* Handle complex expressions. */
7328 sym = make_expr_symbol (i.op[0].disps);
7332 /* 1 possible extra opcode + 4 byte displacement go in var part.
7333 Pass reloc in fr_var. */
7334 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7338 /* Return TRUE iff PLT32 relocation should be used for branching to
7342 need_plt32_p (symbolS *s)
7344 /* PLT32 relocation is ELF only. */
7348 /* Since there is no need to prepare for PLT branch on x86-64, we
7349 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7350 be used as a marker for 32-bit PC-relative branches. */
7354 /* Weak or undefined symbol need PLT32 relocation. */
7355 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7358 /* Non-global symbol doesn't need PLT32 relocation. */
7359 if (! S_IS_EXTERNAL (s))
7362 /* Other global symbols need PLT32 relocation. NB: Symbol with
7363 non-default visibilities are treated as normal global symbol
7364 so that PLT32 relocation can be used as a marker for 32-bit
7365 PC-relative branches. It is useful for linker relaxation. */
7376 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7378 if (i.tm.opcode_modifier.jumpbyte)
7380 /* This is a loop or jecxz type instruction. */
7382 if (i.prefix[ADDR_PREFIX] != 0)
7384 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7387 /* Pentium4 branch hints. */
7388 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7389 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7391 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7400 if (flag_code == CODE_16BIT)
7403 if (i.prefix[DATA_PREFIX] != 0)
7405 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7415 if (i.prefix[REX_PREFIX] != 0)
7417 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7421 /* BND prefixed jump. */
7422 if (i.prefix[BND_PREFIX] != 0)
7424 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7428 if (i.prefixes != 0 && !intel_syntax)
7429 as_warn (_("skipping prefixes on this instruction"));
7431 p = frag_more (i.tm.opcode_length + size);
7432 switch (i.tm.opcode_length)
7435 *p++ = i.tm.base_opcode >> 8;
7438 *p++ = i.tm.base_opcode;
7444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7446 && jump_reloc == NO_RELOC
7447 && need_plt32_p (i.op[0].disps->X_add_symbol))
7448 jump_reloc = BFD_RELOC_X86_64_PLT32;
7451 jump_reloc = reloc (size, 1, 1, jump_reloc);
7453 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7454 i.op[0].disps, 1, jump_reloc);
7456 /* All jumps handled here are signed, but don't use a signed limit
7457 check for 32 and 16 bit jumps as we want to allow wrap around at
7458 4G and 64k respectively. */
7460 fixP->fx_signed = 1;
7464 output_interseg_jump (void)
7472 if (flag_code == CODE_16BIT)
7476 if (i.prefix[DATA_PREFIX] != 0)
7482 if (i.prefix[REX_PREFIX] != 0)
7492 if (i.prefixes != 0 && !intel_syntax)
7493 as_warn (_("skipping prefixes on this instruction"));
7495 /* 1 opcode; 2 segment; offset */
7496 p = frag_more (prefix + 1 + 2 + size);
7498 if (i.prefix[DATA_PREFIX] != 0)
7499 *p++ = DATA_PREFIX_OPCODE;
7501 if (i.prefix[REX_PREFIX] != 0)
7502 *p++ = i.prefix[REX_PREFIX];
7504 *p++ = i.tm.base_opcode;
7505 if (i.op[1].imms->X_op == O_constant)
7507 offsetT n = i.op[1].imms->X_add_number;
7510 && !fits_in_unsigned_word (n)
7511 && !fits_in_signed_word (n))
7513 as_bad (_("16-bit jump out of range"));
7516 md_number_to_chars (p, n, size);
7519 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7520 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7521 if (i.op[0].imms->X_op != O_constant)
7522 as_bad (_("can't handle non absolute segment in `%s'"),
7524 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7530 fragS *insn_start_frag;
7531 offsetT insn_start_off;
7533 /* Tie dwarf2 debug info to the address at the start of the insn.
7534 We can't do this after the insn has been output as the current
7535 frag may have been closed off. eg. by frag_var. */
7536 dwarf2_emit_insn (0);
7538 insn_start_frag = frag_now;
7539 insn_start_off = frag_now_fix ();
7542 if (i.tm.opcode_modifier.jump)
7544 else if (i.tm.opcode_modifier.jumpbyte
7545 || i.tm.opcode_modifier.jumpdword)
7547 else if (i.tm.opcode_modifier.jumpintersegment)
7548 output_interseg_jump ();
7551 /* Output normal instructions here. */
7555 unsigned int prefix;
7558 && i.tm.base_opcode == 0xfae
7560 && i.imm_operands == 1
7561 && (i.op[0].imms->X_add_number == 0xe8
7562 || i.op[0].imms->X_add_number == 0xf0
7563 || i.op[0].imms->X_add_number == 0xf8))
7565 /* Encode lfence, mfence, and sfence as
7566 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7567 offsetT val = 0x240483f0ULL;
7569 md_number_to_chars (p, val, 5);
7573 /* Some processors fail on LOCK prefix. This options makes
7574 assembler ignore LOCK prefix and serves as a workaround. */
7575 if (omit_lock_prefix)
7577 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7579 i.prefix[LOCK_PREFIX] = 0;
7582 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7583 don't need the explicit prefix. */
7584 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7586 switch (i.tm.opcode_length)
7589 if (i.tm.base_opcode & 0xff000000)
7591 prefix = (i.tm.base_opcode >> 24) & 0xff;
7596 if ((i.tm.base_opcode & 0xff0000) != 0)
7598 prefix = (i.tm.base_opcode >> 16) & 0xff;
7599 if (i.tm.cpu_flags.bitfield.cpupadlock)
7602 if (prefix != REPE_PREFIX_OPCODE
7603 || (i.prefix[REP_PREFIX]
7604 != REPE_PREFIX_OPCODE))
7605 add_prefix (prefix);
7608 add_prefix (prefix);
7614 /* Check for pseudo prefixes. */
7615 as_bad_where (insn_start_frag->fr_file,
7616 insn_start_frag->fr_line,
7617 _("pseudo prefix without instruction"));
7623 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7624 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7625 R_X86_64_GOTTPOFF relocation so that linker can safely
7626 perform IE->LE optimization. */
7627 if (x86_elf_abi == X86_64_X32_ABI
7629 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7630 && i.prefix[REX_PREFIX] == 0)
7631 add_prefix (REX_OPCODE);
7634 /* The prefix bytes. */
7635 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7637 FRAG_APPEND_1_CHAR (*q);
7641 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7646 /* REX byte is encoded in VEX prefix. */
7650 FRAG_APPEND_1_CHAR (*q);
7653 /* There should be no other prefixes for instructions
7658 /* For EVEX instructions i.vrex should become 0 after
7659 build_evex_prefix. For VEX instructions upper 16 registers
7660 aren't available, so VREX should be 0. */
7663 /* Now the VEX prefix. */
7664 p = frag_more (i.vex.length);
7665 for (j = 0; j < i.vex.length; j++)
7666 p[j] = i.vex.bytes[j];
7669 /* Now the opcode; be careful about word order here! */
7670 if (i.tm.opcode_length == 1)
7672 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7676 switch (i.tm.opcode_length)
7680 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7681 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7685 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7695 /* Put out high byte first: can't use md_number_to_chars! */
7696 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7697 *p = i.tm.base_opcode & 0xff;
7700 /* Now the modrm byte and sib byte (if present). */
7701 if (i.tm.opcode_modifier.modrm)
7703 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7706 /* If i.rm.regmem == ESP (4)
7707 && i.rm.mode != (Register mode)
7709 ==> need second modrm byte. */
7710 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7712 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7713 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7715 | i.sib.scale << 6));
7718 if (i.disp_operands)
7719 output_disp (insn_start_frag, insn_start_off);
7722 output_imm (insn_start_frag, insn_start_off);
7728 pi ("" /*line*/, &i);
7730 #endif /* DEBUG386 */
7733 /* Return the size of the displacement operand N. */
7736 disp_size (unsigned int n)
7740 if (i.types[n].bitfield.disp64)
7742 else if (i.types[n].bitfield.disp8)
7744 else if (i.types[n].bitfield.disp16)
7749 /* Return the size of the immediate operand N. */
7752 imm_size (unsigned int n)
7755 if (i.types[n].bitfield.imm64)
7757 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7759 else if (i.types[n].bitfield.imm16)
7765 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7770 for (n = 0; n < i.operands; n++)
7772 if (operand_type_check (i.types[n], disp))
7774 if (i.op[n].disps->X_op == O_constant)
7776 int size = disp_size (n);
7777 offsetT val = i.op[n].disps->X_add_number;
7779 val = offset_in_range (val >> i.memshift, size);
7780 p = frag_more (size);
7781 md_number_to_chars (p, val, size);
7785 enum bfd_reloc_code_real reloc_type;
7786 int size = disp_size (n);
7787 int sign = i.types[n].bitfield.disp32s;
7788 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7791 /* We can't have 8 bit displacement here. */
7792 gas_assert (!i.types[n].bitfield.disp8);
7794 /* The PC relative address is computed relative
7795 to the instruction boundary, so in case immediate
7796 fields follows, we need to adjust the value. */
7797 if (pcrel && i.imm_operands)
7802 for (n1 = 0; n1 < i.operands; n1++)
7803 if (operand_type_check (i.types[n1], imm))
7805 /* Only one immediate is allowed for PC
7806 relative address. */
7807 gas_assert (sz == 0);
7809 i.op[n].disps->X_add_number -= sz;
7811 /* We should find the immediate. */
7812 gas_assert (sz != 0);
7815 p = frag_more (size);
7816 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7818 && GOT_symbol == i.op[n].disps->X_add_symbol
7819 && (((reloc_type == BFD_RELOC_32
7820 || reloc_type == BFD_RELOC_X86_64_32S
7821 || (reloc_type == BFD_RELOC_64
7823 && (i.op[n].disps->X_op == O_symbol
7824 || (i.op[n].disps->X_op == O_add
7825 && ((symbol_get_value_expression
7826 (i.op[n].disps->X_op_symbol)->X_op)
7828 || reloc_type == BFD_RELOC_32_PCREL))
7832 if (insn_start_frag == frag_now)
7833 add = (p - frag_now->fr_literal) - insn_start_off;
7838 add = insn_start_frag->fr_fix - insn_start_off;
7839 for (fr = insn_start_frag->fr_next;
7840 fr && fr != frag_now; fr = fr->fr_next)
7842 add += p - frag_now->fr_literal;
7847 reloc_type = BFD_RELOC_386_GOTPC;
7848 i.op[n].imms->X_add_number += add;
7850 else if (reloc_type == BFD_RELOC_64)
7851 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7853 /* Don't do the adjustment for x86-64, as there
7854 the pcrel addressing is relative to the _next_
7855 insn, and that is taken care of in other code. */
7856 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7859 size, i.op[n].disps, pcrel,
7861 /* Check for "call/jmp *mem", "mov mem, %reg",
7862 "test %reg, mem" and "binop mem, %reg" where binop
7863 is one of adc, add, and, cmp, or, sbb, sub, xor
7864 instructions. Always generate R_386_GOT32X for
7865 "sym*GOT" operand in 32-bit mode. */
7866 if ((generate_relax_relocations
7869 && i.rm.regmem == 5))
7871 || (i.rm.mode == 0 && i.rm.regmem == 5))
7872 && ((i.operands == 1
7873 && i.tm.base_opcode == 0xff
7874 && (i.rm.reg == 2 || i.rm.reg == 4))
7876 && (i.tm.base_opcode == 0x8b
7877 || i.tm.base_opcode == 0x85
7878 || (i.tm.base_opcode & 0xc7) == 0x03))))
7882 fixP->fx_tcbit = i.rex != 0;
7884 && (i.base_reg->reg_num == RegRip
7885 || i.base_reg->reg_num == RegEip))
7886 fixP->fx_tcbit2 = 1;
7889 fixP->fx_tcbit2 = 1;
7897 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7902 for (n = 0; n < i.operands; n++)
7904 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7905 if (i.rounding && (int) n == i.rounding->operand)
7908 if (operand_type_check (i.types[n], imm))
7910 if (i.op[n].imms->X_op == O_constant)
7912 int size = imm_size (n);
7915 val = offset_in_range (i.op[n].imms->X_add_number,
7917 p = frag_more (size);
7918 md_number_to_chars (p, val, size);
7922 /* Not absolute_section.
7923 Need a 32-bit fixup (don't support 8bit
7924 non-absolute imms). Try to support other
7926 enum bfd_reloc_code_real reloc_type;
7927 int size = imm_size (n);
7930 if (i.types[n].bitfield.imm32s
7931 && (i.suffix == QWORD_MNEM_SUFFIX
7932 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7937 p = frag_more (size);
7938 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7940 /* This is tough to explain. We end up with this one if we
7941 * have operands that look like
7942 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7943 * obtain the absolute address of the GOT, and it is strongly
7944 * preferable from a performance point of view to avoid using
7945 * a runtime relocation for this. The actual sequence of
7946 * instructions often look something like:
7951 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7953 * The call and pop essentially return the absolute address
7954 * of the label .L66 and store it in %ebx. The linker itself
7955 * will ultimately change the first operand of the addl so
7956 * that %ebx points to the GOT, but to keep things simple, the
7957 * .o file must have this operand set so that it generates not
7958 * the absolute address of .L66, but the absolute address of
7959 * itself. This allows the linker itself simply treat a GOTPC
7960 * relocation as asking for a pcrel offset to the GOT to be
7961 * added in, and the addend of the relocation is stored in the
7962 * operand field for the instruction itself.
7964 * Our job here is to fix the operand so that it would add
7965 * the correct offset so that %ebx would point to itself. The
7966 * thing that is tricky is that .-.L66 will point to the
7967 * beginning of the instruction, so we need to further modify
7968 * the operand so that it will point to itself. There are
7969 * other cases where you have something like:
7971 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7973 * and here no correction would be required. Internally in
7974 * the assembler we treat operands of this form as not being
7975 * pcrel since the '.' is explicitly mentioned, and I wonder
7976 * whether it would simplify matters to do it this way. Who
7977 * knows. In earlier versions of the PIC patches, the
7978 * pcrel_adjust field was used to store the correction, but
7979 * since the expression is not pcrel, I felt it would be
7980 * confusing to do it this way. */
7982 if ((reloc_type == BFD_RELOC_32
7983 || reloc_type == BFD_RELOC_X86_64_32S
7984 || reloc_type == BFD_RELOC_64)
7986 && GOT_symbol == i.op[n].imms->X_add_symbol
7987 && (i.op[n].imms->X_op == O_symbol
7988 || (i.op[n].imms->X_op == O_add
7989 && ((symbol_get_value_expression
7990 (i.op[n].imms->X_op_symbol)->X_op)
7995 if (insn_start_frag == frag_now)
7996 add = (p - frag_now->fr_literal) - insn_start_off;
8001 add = insn_start_frag->fr_fix - insn_start_off;
8002 for (fr = insn_start_frag->fr_next;
8003 fr && fr != frag_now; fr = fr->fr_next)
8005 add += p - frag_now->fr_literal;
8009 reloc_type = BFD_RELOC_386_GOTPC;
8011 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8013 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8014 i.op[n].imms->X_add_number += add;
8016 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8017 i.op[n].imms, 0, reloc_type);
8023 /* x86_cons_fix_new is called via the expression parsing code when a
8024 reloc is needed. We use this hook to get the correct .got reloc. */
8025 static int cons_sign = -1;
8028 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8029 expressionS *exp, bfd_reloc_code_real_type r)
8031 r = reloc (len, 0, cons_sign, r);
8034 if (exp->X_op == O_secrel)
8036 exp->X_op = O_symbol;
8037 r = BFD_RELOC_32_SECREL;
8041 fix_new_exp (frag, off, len, exp, 0, r);
8044 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8045 purpose of the `.dc.a' internal pseudo-op. */
8048 x86_address_bytes (void)
8050 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8052 return stdoutput->arch_info->bits_per_address / 8;
8055 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8057 # define lex_got(reloc, adjust, types) NULL
8059 /* Parse operands of the form
8060 <symbol>@GOTOFF+<nnn>
8061 and similar .plt or .got references.
8063 If we find one, set up the correct relocation in RELOC and copy the
8064 input string, minus the `@GOTOFF' into a malloc'd buffer for
8065 parsing by the calling routine. Return this buffer, and if ADJUST
8066 is non-null set it to the length of the string we removed from the
8067 input line. Otherwise return NULL. */
8069 lex_got (enum bfd_reloc_code_real *rel,
8071 i386_operand_type *types)
8073 /* Some of the relocations depend on the size of what field is to
8074 be relocated. But in our callers i386_immediate and i386_displacement
8075 we don't yet know the operand size (this will be set by insn
8076 matching). Hence we record the word32 relocation here,
8077 and adjust the reloc according to the real size in reloc(). */
8078 static const struct {
8081 const enum bfd_reloc_code_real rel[2];
8082 const i386_operand_type types64;
8084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8085 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8087 OPERAND_TYPE_IMM32_64 },
8089 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8090 BFD_RELOC_X86_64_PLTOFF64 },
8091 OPERAND_TYPE_IMM64 },
8092 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8093 BFD_RELOC_X86_64_PLT32 },
8094 OPERAND_TYPE_IMM32_32S_DISP32 },
8095 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8096 BFD_RELOC_X86_64_GOTPLT64 },
8097 OPERAND_TYPE_IMM64_DISP64 },
8098 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8099 BFD_RELOC_X86_64_GOTOFF64 },
8100 OPERAND_TYPE_IMM64_DISP64 },
8101 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8102 BFD_RELOC_X86_64_GOTPCREL },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8105 BFD_RELOC_X86_64_TLSGD },
8106 OPERAND_TYPE_IMM32_32S_DISP32 },
8107 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8108 _dummy_first_bfd_reloc_code_real },
8109 OPERAND_TYPE_NONE },
8110 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8111 BFD_RELOC_X86_64_TLSLD },
8112 OPERAND_TYPE_IMM32_32S_DISP32 },
8113 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8114 BFD_RELOC_X86_64_GOTTPOFF },
8115 OPERAND_TYPE_IMM32_32S_DISP32 },
8116 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8117 BFD_RELOC_X86_64_TPOFF32 },
8118 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8119 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8120 _dummy_first_bfd_reloc_code_real },
8121 OPERAND_TYPE_NONE },
8122 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8123 BFD_RELOC_X86_64_DTPOFF32 },
8124 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8125 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8126 _dummy_first_bfd_reloc_code_real },
8127 OPERAND_TYPE_NONE },
8128 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8129 _dummy_first_bfd_reloc_code_real },
8130 OPERAND_TYPE_NONE },
8131 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8132 BFD_RELOC_X86_64_GOT32 },
8133 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8134 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8135 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8136 OPERAND_TYPE_IMM32_32S_DISP32 },
8137 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8138 BFD_RELOC_X86_64_TLSDESC_CALL },
8139 OPERAND_TYPE_IMM32_32S_DISP32 },
8144 #if defined (OBJ_MAYBE_ELF)
8149 for (cp = input_line_pointer; *cp != '@'; cp++)
8150 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8153 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8155 int len = gotrel[j].len;
8156 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8158 if (gotrel[j].rel[object_64bit] != 0)
8161 char *tmpbuf, *past_reloc;
8163 *rel = gotrel[j].rel[object_64bit];
8167 if (flag_code != CODE_64BIT)
8169 types->bitfield.imm32 = 1;
8170 types->bitfield.disp32 = 1;
8173 *types = gotrel[j].types64;
8176 if (j != 0 && GOT_symbol == NULL)
8177 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8179 /* The length of the first part of our input line. */
8180 first = cp - input_line_pointer;
8182 /* The second part goes from after the reloc token until
8183 (and including) an end_of_line char or comma. */
8184 past_reloc = cp + 1 + len;
8186 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8188 second = cp + 1 - past_reloc;
8190 /* Allocate and copy string. The trailing NUL shouldn't
8191 be necessary, but be safe. */
8192 tmpbuf = XNEWVEC (char, first + second + 2);
8193 memcpy (tmpbuf, input_line_pointer, first);
8194 if (second != 0 && *past_reloc != ' ')
8195 /* Replace the relocation token with ' ', so that
8196 errors like foo@GOTOFF1 will be detected. */
8197 tmpbuf[first++] = ' ';
8199 /* Increment length by 1 if the relocation token is
8204 memcpy (tmpbuf + first, past_reloc, second);
8205 tmpbuf[first + second] = '\0';
8209 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8210 gotrel[j].str, 1 << (5 + object_64bit));
8215 /* Might be a symbol version string. Don't as_bad here. */
8224 /* Parse operands of the form
8225 <symbol>@SECREL32+<nnn>
8227 If we find one, set up the correct relocation in RELOC and copy the
8228 input string, minus the `@SECREL32' into a malloc'd buffer for
8229 parsing by the calling routine. Return this buffer, and if ADJUST
8230 is non-null set it to the length of the string we removed from the
8231 input line. Otherwise return NULL.
8233 This function is copied from the ELF version above adjusted for PE targets. */
8236 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8237 int *adjust ATTRIBUTE_UNUSED,
8238 i386_operand_type *types)
8244 const enum bfd_reloc_code_real rel[2];
8245 const i386_operand_type types64;
8249 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8250 BFD_RELOC_32_SECREL },
8251 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8257 for (cp = input_line_pointer; *cp != '@'; cp++)
8258 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8261 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8263 int len = gotrel[j].len;
8265 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8267 if (gotrel[j].rel[object_64bit] != 0)
8270 char *tmpbuf, *past_reloc;
8272 *rel = gotrel[j].rel[object_64bit];
8278 if (flag_code != CODE_64BIT)
8280 types->bitfield.imm32 = 1;
8281 types->bitfield.disp32 = 1;
8284 *types = gotrel[j].types64;
8287 /* The length of the first part of our input line. */
8288 first = cp - input_line_pointer;
8290 /* The second part goes from after the reloc token until
8291 (and including) an end_of_line char or comma. */
8292 past_reloc = cp + 1 + len;
8294 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8296 second = cp + 1 - past_reloc;
8298 /* Allocate and copy string. The trailing NUL shouldn't
8299 be necessary, but be safe. */
8300 tmpbuf = XNEWVEC (char, first + second + 2);
8301 memcpy (tmpbuf, input_line_pointer, first);
8302 if (second != 0 && *past_reloc != ' ')
8303 /* Replace the relocation token with ' ', so that
8304 errors like foo@SECLREL321 will be detected. */
8305 tmpbuf[first++] = ' ';
8306 memcpy (tmpbuf + first, past_reloc, second);
8307 tmpbuf[first + second] = '\0';
8311 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8312 gotrel[j].str, 1 << (5 + object_64bit));
8317 /* Might be a symbol version string. Don't as_bad here. */
8323 bfd_reloc_code_real_type
8324 x86_cons (expressionS *exp, int size)
8326 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8328 intel_syntax = -intel_syntax;
8331 if (size == 4 || (object_64bit && size == 8))
8333 /* Handle @GOTOFF and the like in an expression. */
8335 char *gotfree_input_line;
8338 save = input_line_pointer;
8339 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8340 if (gotfree_input_line)
8341 input_line_pointer = gotfree_input_line;
8345 if (gotfree_input_line)
8347 /* expression () has merrily parsed up to the end of line,
8348 or a comma - in the wrong buffer. Transfer how far
8349 input_line_pointer has moved to the right buffer. */
8350 input_line_pointer = (save
8351 + (input_line_pointer - gotfree_input_line)
8353 free (gotfree_input_line);
8354 if (exp->X_op == O_constant
8355 || exp->X_op == O_absent
8356 || exp->X_op == O_illegal
8357 || exp->X_op == O_register
8358 || exp->X_op == O_big)
8360 char c = *input_line_pointer;
8361 *input_line_pointer = 0;
8362 as_bad (_("missing or invalid expression `%s'"), save);
8363 *input_line_pointer = c;
8370 intel_syntax = -intel_syntax;
8373 i386_intel_simplify (exp);
8379 signed_cons (int size)
8381 if (flag_code == CODE_64BIT)
8389 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8396 if (exp.X_op == O_symbol)
8397 exp.X_op = O_secrel;
8399 emit_expr (&exp, 4);
8401 while (*input_line_pointer++ == ',');
8403 input_line_pointer--;
8404 demand_empty_rest_of_line ();
8408 /* Handle Vector operations. */
8411 check_VecOperations (char *op_string, char *op_end)
8413 const reg_entry *mask;
8418 && (op_end == NULL || op_string < op_end))
8421 if (*op_string == '{')
8425 /* Check broadcasts. */
8426 if (strncmp (op_string, "1to", 3) == 0)
8431 goto duplicated_vec_op;
8434 if (*op_string == '8')
8435 bcst_type = BROADCAST_1TO8;
8436 else if (*op_string == '4')
8437 bcst_type = BROADCAST_1TO4;
8438 else if (*op_string == '2')
8439 bcst_type = BROADCAST_1TO2;
8440 else if (*op_string == '1'
8441 && *(op_string+1) == '6')
8443 bcst_type = BROADCAST_1TO16;
8448 as_bad (_("Unsupported broadcast: `%s'"), saved);
8453 broadcast_op.type = bcst_type;
8454 broadcast_op.operand = this_operand;
8455 i.broadcast = &broadcast_op;
8457 /* Check masking operation. */
8458 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8460 /* k0 can't be used for write mask. */
8461 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8463 as_bad (_("`%s%s' can't be used for write mask"),
8464 register_prefix, mask->reg_name);
8470 mask_op.mask = mask;
8471 mask_op.zeroing = 0;
8472 mask_op.operand = this_operand;
8478 goto duplicated_vec_op;
8480 i.mask->mask = mask;
8482 /* Only "{z}" is allowed here. No need to check
8483 zeroing mask explicitly. */
8484 if (i.mask->operand != this_operand)
8486 as_bad (_("invalid write mask `%s'"), saved);
8493 /* Check zeroing-flag for masking operation. */
8494 else if (*op_string == 'z')
8498 mask_op.mask = NULL;
8499 mask_op.zeroing = 1;
8500 mask_op.operand = this_operand;
8505 if (i.mask->zeroing)
8508 as_bad (_("duplicated `%s'"), saved);
8512 i.mask->zeroing = 1;
8514 /* Only "{%k}" is allowed here. No need to check mask
8515 register explicitly. */
8516 if (i.mask->operand != this_operand)
8518 as_bad (_("invalid zeroing-masking `%s'"),
8527 goto unknown_vec_op;
8529 if (*op_string != '}')
8531 as_bad (_("missing `}' in `%s'"), saved);
8538 /* We don't know this one. */
8539 as_bad (_("unknown vector operation: `%s'"), saved);
8543 if (i.mask && i.mask->zeroing && !i.mask->mask)
8545 as_bad (_("zeroing-masking only allowed with write mask"));
8553 i386_immediate (char *imm_start)
8555 char *save_input_line_pointer;
8556 char *gotfree_input_line;
8559 i386_operand_type types;
8561 operand_type_set (&types, ~0);
8563 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8565 as_bad (_("at most %d immediate operands are allowed"),
8566 MAX_IMMEDIATE_OPERANDS);
8570 exp = &im_expressions[i.imm_operands++];
8571 i.op[this_operand].imms = exp;
8573 if (is_space_char (*imm_start))
8576 save_input_line_pointer = input_line_pointer;
8577 input_line_pointer = imm_start;
8579 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8580 if (gotfree_input_line)
8581 input_line_pointer = gotfree_input_line;
8583 exp_seg = expression (exp);
8587 /* Handle vector operations. */
8588 if (*input_line_pointer == '{')
8590 input_line_pointer = check_VecOperations (input_line_pointer,
8592 if (input_line_pointer == NULL)
8596 if (*input_line_pointer)
8597 as_bad (_("junk `%s' after expression"), input_line_pointer);
8599 input_line_pointer = save_input_line_pointer;
8600 if (gotfree_input_line)
8602 free (gotfree_input_line);
8604 if (exp->X_op == O_constant || exp->X_op == O_register)
8605 exp->X_op = O_illegal;
8608 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8612 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8613 i386_operand_type types, const char *imm_start)
8615 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8618 as_bad (_("missing or invalid immediate expression `%s'"),
8622 else if (exp->X_op == O_constant)
8624 /* Size it properly later. */
8625 i.types[this_operand].bitfield.imm64 = 1;
8626 /* If not 64bit, sign extend val. */
8627 if (flag_code != CODE_64BIT
8628 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8630 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8632 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8633 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8634 && exp_seg != absolute_section
8635 && exp_seg != text_section
8636 && exp_seg != data_section
8637 && exp_seg != bss_section
8638 && exp_seg != undefined_section
8639 && !bfd_is_com_section (exp_seg))
8641 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8645 else if (!intel_syntax && exp_seg == reg_section)
8648 as_bad (_("illegal immediate register operand %s"), imm_start);
8653 /* This is an address. The size of the address will be
8654 determined later, depending on destination register,
8655 suffix, or the default for the section. */
8656 i.types[this_operand].bitfield.imm8 = 1;
8657 i.types[this_operand].bitfield.imm16 = 1;
8658 i.types[this_operand].bitfield.imm32 = 1;
8659 i.types[this_operand].bitfield.imm32s = 1;
8660 i.types[this_operand].bitfield.imm64 = 1;
8661 i.types[this_operand] = operand_type_and (i.types[this_operand],
8669 i386_scale (char *scale)
8672 char *save = input_line_pointer;
8674 input_line_pointer = scale;
8675 val = get_absolute_expression ();
8680 i.log2_scale_factor = 0;
8683 i.log2_scale_factor = 1;
8686 i.log2_scale_factor = 2;
8689 i.log2_scale_factor = 3;
8693 char sep = *input_line_pointer;
8695 *input_line_pointer = '\0';
8696 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8698 *input_line_pointer = sep;
8699 input_line_pointer = save;
8703 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8705 as_warn (_("scale factor of %d without an index register"),
8706 1 << i.log2_scale_factor);
8707 i.log2_scale_factor = 0;
8709 scale = input_line_pointer;
8710 input_line_pointer = save;
8715 i386_displacement (char *disp_start, char *disp_end)
8719 char *save_input_line_pointer;
8720 char *gotfree_input_line;
8722 i386_operand_type bigdisp, types = anydisp;
8725 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8727 as_bad (_("at most %d displacement operands are allowed"),
8728 MAX_MEMORY_OPERANDS);
8732 operand_type_set (&bigdisp, 0);
8733 if ((i.types[this_operand].bitfield.jumpabsolute)
8734 || (!current_templates->start->opcode_modifier.jump
8735 && !current_templates->start->opcode_modifier.jumpdword))
8737 bigdisp.bitfield.disp32 = 1;
8738 override = (i.prefix[ADDR_PREFIX] != 0);
8739 if (flag_code == CODE_64BIT)
8743 bigdisp.bitfield.disp32s = 1;
8744 bigdisp.bitfield.disp64 = 1;
8747 else if ((flag_code == CODE_16BIT) ^ override)
8749 bigdisp.bitfield.disp32 = 0;
8750 bigdisp.bitfield.disp16 = 1;
8755 /* For PC-relative branches, the width of the displacement
8756 is dependent upon data size, not address size. */
8757 override = (i.prefix[DATA_PREFIX] != 0);
8758 if (flag_code == CODE_64BIT)
8760 if (override || i.suffix == WORD_MNEM_SUFFIX)
8761 bigdisp.bitfield.disp16 = 1;
8764 bigdisp.bitfield.disp32 = 1;
8765 bigdisp.bitfield.disp32s = 1;
8771 override = (i.suffix == (flag_code != CODE_16BIT
8773 : LONG_MNEM_SUFFIX));
8774 bigdisp.bitfield.disp32 = 1;
8775 if ((flag_code == CODE_16BIT) ^ override)
8777 bigdisp.bitfield.disp32 = 0;
8778 bigdisp.bitfield.disp16 = 1;
8782 i.types[this_operand] = operand_type_or (i.types[this_operand],
8785 exp = &disp_expressions[i.disp_operands];
8786 i.op[this_operand].disps = exp;
8788 save_input_line_pointer = input_line_pointer;
8789 input_line_pointer = disp_start;
8790 END_STRING_AND_SAVE (disp_end);
8792 #ifndef GCC_ASM_O_HACK
8793 #define GCC_ASM_O_HACK 0
8796 END_STRING_AND_SAVE (disp_end + 1);
8797 if (i.types[this_operand].bitfield.baseIndex
8798 && displacement_string_end[-1] == '+')
8800 /* This hack is to avoid a warning when using the "o"
8801 constraint within gcc asm statements.
8804 #define _set_tssldt_desc(n,addr,limit,type) \
8805 __asm__ __volatile__ ( \
8807 "movw %w1,2+%0\n\t" \
8809 "movb %b1,4+%0\n\t" \
8810 "movb %4,5+%0\n\t" \
8811 "movb $0,6+%0\n\t" \
8812 "movb %h1,7+%0\n\t" \
8814 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8816 This works great except that the output assembler ends
8817 up looking a bit weird if it turns out that there is
8818 no offset. You end up producing code that looks like:
8831 So here we provide the missing zero. */
8833 *displacement_string_end = '0';
8836 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8837 if (gotfree_input_line)
8838 input_line_pointer = gotfree_input_line;
8840 exp_seg = expression (exp);
8843 if (*input_line_pointer)
8844 as_bad (_("junk `%s' after expression"), input_line_pointer);
8846 RESTORE_END_STRING (disp_end + 1);
8848 input_line_pointer = save_input_line_pointer;
8849 if (gotfree_input_line)
8851 free (gotfree_input_line);
8853 if (exp->X_op == O_constant || exp->X_op == O_register)
8854 exp->X_op = O_illegal;
8857 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8859 RESTORE_END_STRING (disp_end);
8865 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8866 i386_operand_type types, const char *disp_start)
8868 i386_operand_type bigdisp;
8871 /* We do this to make sure that the section symbol is in
8872 the symbol table. We will ultimately change the relocation
8873 to be relative to the beginning of the section. */
8874 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8875 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8876 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8878 if (exp->X_op != O_symbol)
8881 if (S_IS_LOCAL (exp->X_add_symbol)
8882 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8883 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8884 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8885 exp->X_op = O_subtract;
8886 exp->X_op_symbol = GOT_symbol;
8887 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8888 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8889 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8890 i.reloc[this_operand] = BFD_RELOC_64;
8892 i.reloc[this_operand] = BFD_RELOC_32;
8895 else if (exp->X_op == O_absent
8896 || exp->X_op == O_illegal
8897 || exp->X_op == O_big)
8900 as_bad (_("missing or invalid displacement expression `%s'"),
8905 else if (flag_code == CODE_64BIT
8906 && !i.prefix[ADDR_PREFIX]
8907 && exp->X_op == O_constant)
8909 /* Since displacement is signed extended to 64bit, don't allow
8910 disp32 and turn off disp32s if they are out of range. */
8911 i.types[this_operand].bitfield.disp32 = 0;
8912 if (!fits_in_signed_long (exp->X_add_number))
8914 i.types[this_operand].bitfield.disp32s = 0;
8915 if (i.types[this_operand].bitfield.baseindex)
8917 as_bad (_("0x%lx out range of signed 32bit displacement"),
8918 (long) exp->X_add_number);
8924 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8925 else if (exp->X_op != O_constant
8926 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8927 && exp_seg != absolute_section
8928 && exp_seg != text_section
8929 && exp_seg != data_section
8930 && exp_seg != bss_section
8931 && exp_seg != undefined_section
8932 && !bfd_is_com_section (exp_seg))
8934 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8939 /* Check if this is a displacement only operand. */
8940 bigdisp = i.types[this_operand];
8941 bigdisp.bitfield.disp8 = 0;
8942 bigdisp.bitfield.disp16 = 0;
8943 bigdisp.bitfield.disp32 = 0;
8944 bigdisp.bitfield.disp32s = 0;
8945 bigdisp.bitfield.disp64 = 0;
8946 if (operand_type_all_zero (&bigdisp))
8947 i.types[this_operand] = operand_type_and (i.types[this_operand],
8953 /* Return the active addressing mode, taking address override and
8954 registers forming the address into consideration. Update the
8955 address override prefix if necessary. */
8957 static enum flag_code
8958 i386_addressing_mode (void)
8960 enum flag_code addr_mode;
8962 if (i.prefix[ADDR_PREFIX])
8963 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8966 addr_mode = flag_code;
8968 #if INFER_ADDR_PREFIX
8969 if (i.mem_operands == 0)
8971 /* Infer address prefix from the first memory operand. */
8972 const reg_entry *addr_reg = i.base_reg;
8974 if (addr_reg == NULL)
8975 addr_reg = i.index_reg;
8979 if (addr_reg->reg_num == RegEip
8980 || addr_reg->reg_num == RegEiz
8981 || addr_reg->reg_type.bitfield.dword)
8982 addr_mode = CODE_32BIT;
8983 else if (flag_code != CODE_64BIT
8984 && addr_reg->reg_type.bitfield.word)
8985 addr_mode = CODE_16BIT;
8987 if (addr_mode != flag_code)
8989 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8991 /* Change the size of any displacement too. At most one
8992 of Disp16 or Disp32 is set.
8993 FIXME. There doesn't seem to be any real need for
8994 separate Disp16 and Disp32 flags. The same goes for
8995 Imm16 and Imm32. Removing them would probably clean
8996 up the code quite a lot. */
8997 if (flag_code != CODE_64BIT
8998 && (i.types[this_operand].bitfield.disp16
8999 || i.types[this_operand].bitfield.disp32))
9000 i.types[this_operand]
9001 = operand_type_xor (i.types[this_operand], disp16_32);
9011 /* Make sure the memory operand we've been dealt is valid.
9012 Return 1 on success, 0 on a failure. */
9015 i386_index_check (const char *operand_string)
9017 const char *kind = "base/index";
9018 enum flag_code addr_mode = i386_addressing_mode ();
9020 if (current_templates->start->opcode_modifier.isstring
9021 && !current_templates->start->opcode_modifier.immext
9022 && (current_templates->end[-1].opcode_modifier.isstring
9025 /* Memory operands of string insns are special in that they only allow
9026 a single register (rDI, rSI, or rBX) as their memory address. */
9027 const reg_entry *expected_reg;
9028 static const char *di_si[][2] =
9034 static const char *bx[] = { "ebx", "bx", "rbx" };
9036 kind = "string address";
9038 if (current_templates->start->opcode_modifier.repprefixok)
9040 i386_operand_type type = current_templates->end[-1].operand_types[0];
9042 if (!type.bitfield.baseindex
9043 || ((!i.mem_operands != !intel_syntax)
9044 && current_templates->end[-1].operand_types[1]
9045 .bitfield.baseindex))
9046 type = current_templates->end[-1].operand_types[1];
9047 expected_reg = hash_find (reg_hash,
9048 di_si[addr_mode][type.bitfield.esseg]);
9052 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9054 if (i.base_reg != expected_reg
9056 || operand_type_check (i.types[this_operand], disp))
9058 /* The second memory operand must have the same size as
9062 && !((addr_mode == CODE_64BIT
9063 && i.base_reg->reg_type.bitfield.qword)
9064 || (addr_mode == CODE_32BIT
9065 ? i.base_reg->reg_type.bitfield.dword
9066 : i.base_reg->reg_type.bitfield.word)))
9069 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9071 intel_syntax ? '[' : '(',
9073 expected_reg->reg_name,
9074 intel_syntax ? ']' : ')');
9081 as_bad (_("`%s' is not a valid %s expression"),
9082 operand_string, kind);
9087 if (addr_mode != CODE_16BIT)
9089 /* 32-bit/64-bit checks. */
9091 && (addr_mode == CODE_64BIT
9092 ? !i.base_reg->reg_type.bitfield.qword
9093 : !i.base_reg->reg_type.bitfield.dword)
9095 || (i.base_reg->reg_num
9096 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9098 && !i.index_reg->reg_type.bitfield.xmmword
9099 && !i.index_reg->reg_type.bitfield.ymmword
9100 && !i.index_reg->reg_type.bitfield.zmmword
9101 && ((addr_mode == CODE_64BIT
9102 ? !(i.index_reg->reg_type.bitfield.qword
9103 || i.index_reg->reg_num == RegRiz)
9104 : !(i.index_reg->reg_type.bitfield.dword
9105 || i.index_reg->reg_num == RegEiz))
9106 || !i.index_reg->reg_type.bitfield.baseindex)))
9109 /* bndmk, bndldx, and bndstx have special restrictions. */
9110 if (current_templates->start->base_opcode == 0xf30f1b
9111 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9113 /* They cannot use RIP-relative addressing. */
9114 if (i.base_reg && i.base_reg->reg_num == RegRip)
9116 as_bad (_("`%s' cannot be used here"), operand_string);
9120 /* bndldx and bndstx ignore their scale factor. */
9121 if (current_templates->start->base_opcode != 0xf30f1b
9122 && i.log2_scale_factor)
9123 as_warn (_("register scaling is being ignored here"));
9128 /* 16-bit checks. */
9130 && (!i.base_reg->reg_type.bitfield.word
9131 || !i.base_reg->reg_type.bitfield.baseindex))
9133 && (!i.index_reg->reg_type.bitfield.word
9134 || !i.index_reg->reg_type.bitfield.baseindex
9136 && i.base_reg->reg_num < 6
9137 && i.index_reg->reg_num >= 6
9138 && i.log2_scale_factor == 0))))
9145 /* Handle vector immediates. */
9148 RC_SAE_immediate (const char *imm_start)
9150 unsigned int match_found, j;
9151 const char *pstr = imm_start;
9159 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9161 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9165 rc_op.type = RC_NamesTable[j].type;
9166 rc_op.operand = this_operand;
9167 i.rounding = &rc_op;
9171 as_bad (_("duplicated `%s'"), imm_start);
9174 pstr += RC_NamesTable[j].len;
9184 as_bad (_("Missing '}': '%s'"), imm_start);
9187 /* RC/SAE immediate string should contain nothing more. */;
9190 as_bad (_("Junk after '}': '%s'"), imm_start);
9194 exp = &im_expressions[i.imm_operands++];
9195 i.op[this_operand].imms = exp;
9197 exp->X_op = O_constant;
9198 exp->X_add_number = 0;
9199 exp->X_add_symbol = (symbolS *) 0;
9200 exp->X_op_symbol = (symbolS *) 0;
9202 i.types[this_operand].bitfield.imm8 = 1;
9206 /* Only string instructions can have a second memory operand, so
9207 reduce current_templates to just those if it contains any. */
9209 maybe_adjust_templates (void)
9211 const insn_template *t;
9213 gas_assert (i.mem_operands == 1);
9215 for (t = current_templates->start; t < current_templates->end; ++t)
9216 if (t->opcode_modifier.isstring)
9219 if (t < current_templates->end)
9221 static templates aux_templates;
9222 bfd_boolean recheck;
9224 aux_templates.start = t;
9225 for (; t < current_templates->end; ++t)
9226 if (!t->opcode_modifier.isstring)
9228 aux_templates.end = t;
9230 /* Determine whether to re-check the first memory operand. */
9231 recheck = (aux_templates.start != current_templates->start
9232 || t != current_templates->end);
9234 current_templates = &aux_templates;
9239 if (i.memop1_string != NULL
9240 && i386_index_check (i.memop1_string) == 0)
9249 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9253 i386_att_operand (char *operand_string)
9257 char *op_string = operand_string;
9259 if (is_space_char (*op_string))
9262 /* We check for an absolute prefix (differentiating,
9263 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9264 if (*op_string == ABSOLUTE_PREFIX)
9267 if (is_space_char (*op_string))
9269 i.types[this_operand].bitfield.jumpabsolute = 1;
9272 /* Check if operand is a register. */
9273 if ((r = parse_register (op_string, &end_op)) != NULL)
9275 i386_operand_type temp;
9277 /* Check for a segment override by searching for ':' after a
9278 segment register. */
9280 if (is_space_char (*op_string))
9282 if (*op_string == ':'
9283 && (r->reg_type.bitfield.sreg2
9284 || r->reg_type.bitfield.sreg3))
9289 i.seg[i.mem_operands] = &es;
9292 i.seg[i.mem_operands] = &cs;
9295 i.seg[i.mem_operands] = &ss;
9298 i.seg[i.mem_operands] = &ds;
9301 i.seg[i.mem_operands] = &fs;
9304 i.seg[i.mem_operands] = &gs;
9308 /* Skip the ':' and whitespace. */
9310 if (is_space_char (*op_string))
9313 if (!is_digit_char (*op_string)
9314 && !is_identifier_char (*op_string)
9315 && *op_string != '('
9316 && *op_string != ABSOLUTE_PREFIX)
9318 as_bad (_("bad memory operand `%s'"), op_string);
9321 /* Handle case of %es:*foo. */
9322 if (*op_string == ABSOLUTE_PREFIX)
9325 if (is_space_char (*op_string))
9327 i.types[this_operand].bitfield.jumpabsolute = 1;
9329 goto do_memory_reference;
9332 /* Handle vector operations. */
9333 if (*op_string == '{')
9335 op_string = check_VecOperations (op_string, NULL);
9336 if (op_string == NULL)
9342 as_bad (_("junk `%s' after register"), op_string);
9346 temp.bitfield.baseindex = 0;
9347 i.types[this_operand] = operand_type_or (i.types[this_operand],
9349 i.types[this_operand].bitfield.unspecified = 0;
9350 i.op[this_operand].regs = r;
9353 else if (*op_string == REGISTER_PREFIX)
9355 as_bad (_("bad register name `%s'"), op_string);
9358 else if (*op_string == IMMEDIATE_PREFIX)
9361 if (i.types[this_operand].bitfield.jumpabsolute)
9363 as_bad (_("immediate operand illegal with absolute jump"));
9366 if (!i386_immediate (op_string))
9369 else if (RC_SAE_immediate (operand_string))
9371 /* If it is a RC or SAE immediate, do nothing. */
9374 else if (is_digit_char (*op_string)
9375 || is_identifier_char (*op_string)
9376 || *op_string == '"'
9377 || *op_string == '(')
9379 /* This is a memory reference of some sort. */
9382 /* Start and end of displacement string expression (if found). */
9383 char *displacement_string_start;
9384 char *displacement_string_end;
9387 do_memory_reference:
9388 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9390 if ((i.mem_operands == 1
9391 && !current_templates->start->opcode_modifier.isstring)
9392 || i.mem_operands == 2)
9394 as_bad (_("too many memory references for `%s'"),
9395 current_templates->start->name);
9399 /* Check for base index form. We detect the base index form by
9400 looking for an ')' at the end of the operand, searching
9401 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9403 base_string = op_string + strlen (op_string);
9405 /* Handle vector operations. */
9406 vop_start = strchr (op_string, '{');
9407 if (vop_start && vop_start < base_string)
9409 if (check_VecOperations (vop_start, base_string) == NULL)
9411 base_string = vop_start;
9415 if (is_space_char (*base_string))
9418 /* If we only have a displacement, set-up for it to be parsed later. */
9419 displacement_string_start = op_string;
9420 displacement_string_end = base_string + 1;
9422 if (*base_string == ')')
9425 unsigned int parens_balanced = 1;
9426 /* We've already checked that the number of left & right ()'s are
9427 equal, so this loop will not be infinite. */
9431 if (*base_string == ')')
9433 if (*base_string == '(')
9436 while (parens_balanced);
9438 temp_string = base_string;
9440 /* Skip past '(' and whitespace. */
9442 if (is_space_char (*base_string))
9445 if (*base_string == ','
9446 || ((i.base_reg = parse_register (base_string, &end_op))
9449 displacement_string_end = temp_string;
9451 i.types[this_operand].bitfield.baseindex = 1;
9455 base_string = end_op;
9456 if (is_space_char (*base_string))
9460 /* There may be an index reg or scale factor here. */
9461 if (*base_string == ',')
9464 if (is_space_char (*base_string))
9467 if ((i.index_reg = parse_register (base_string, &end_op))
9470 base_string = end_op;
9471 if (is_space_char (*base_string))
9473 if (*base_string == ',')
9476 if (is_space_char (*base_string))
9479 else if (*base_string != ')')
9481 as_bad (_("expecting `,' or `)' "
9482 "after index register in `%s'"),
9487 else if (*base_string == REGISTER_PREFIX)
9489 end_op = strchr (base_string, ',');
9492 as_bad (_("bad register name `%s'"), base_string);
9496 /* Check for scale factor. */
9497 if (*base_string != ')')
9499 char *end_scale = i386_scale (base_string);
9504 base_string = end_scale;
9505 if (is_space_char (*base_string))
9507 if (*base_string != ')')
9509 as_bad (_("expecting `)' "
9510 "after scale factor in `%s'"),
9515 else if (!i.index_reg)
9517 as_bad (_("expecting index register or scale factor "
9518 "after `,'; got '%c'"),
9523 else if (*base_string != ')')
9525 as_bad (_("expecting `,' or `)' "
9526 "after base register in `%s'"),
9531 else if (*base_string == REGISTER_PREFIX)
9533 end_op = strchr (base_string, ',');
9536 as_bad (_("bad register name `%s'"), base_string);
9541 /* If there's an expression beginning the operand, parse it,
9542 assuming displacement_string_start and
9543 displacement_string_end are meaningful. */
9544 if (displacement_string_start != displacement_string_end)
9546 if (!i386_displacement (displacement_string_start,
9547 displacement_string_end))
9551 /* Special case for (%dx) while doing input/output op. */
9553 && operand_type_equal (&i.base_reg->reg_type,
9554 ®16_inoutportreg)
9556 && i.log2_scale_factor == 0
9557 && i.seg[i.mem_operands] == 0
9558 && !operand_type_check (i.types[this_operand], disp))
9560 i.types[this_operand] = inoutportreg;
9564 if (i386_index_check (operand_string) == 0)
9566 i.types[this_operand].bitfield.mem = 1;
9567 if (i.mem_operands == 0)
9568 i.memop1_string = xstrdup (operand_string);
9573 /* It's not a memory operand; argh! */
9574 as_bad (_("invalid char %s beginning operand %d `%s'"),
9575 output_invalid (*op_string),
9580 return 1; /* Normal return. */
9583 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9584 that an rs_machine_dependent frag may reach. */
9587 i386_frag_max_var (fragS *frag)
9589 /* The only relaxable frags are for jumps.
9590 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9591 gas_assert (frag->fr_type == rs_machine_dependent);
9592 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9597 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9599 /* STT_GNU_IFUNC symbol must go through PLT. */
9600 if ((symbol_get_bfdsym (fr_symbol)->flags
9601 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9604 if (!S_IS_EXTERNAL (fr_symbol))
9605 /* Symbol may be weak or local. */
9606 return !S_IS_WEAK (fr_symbol);
9608 /* Global symbols with non-default visibility can't be preempted. */
9609 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9612 if (fr_var != NO_RELOC)
9613 switch ((enum bfd_reloc_code_real) fr_var)
9615 case BFD_RELOC_386_PLT32:
9616 case BFD_RELOC_X86_64_PLT32:
9617 /* Symbol with PLT relocation may be preempted. */
9623 /* Global symbols with default visibility in a shared library may be
9624 preempted by another definition. */
9629 /* md_estimate_size_before_relax()
9631 Called just before relax() for rs_machine_dependent frags. The x86
9632 assembler uses these frags to handle variable size jump
9635 Any symbol that is now undefined will not become defined.
9636 Return the correct fr_subtype in the frag.
9637 Return the initial "guess for variable size of frag" to caller.
9638 The guess is actually the growth beyond the fixed part. Whatever
9639 we do to grow the fixed or variable part contributes to our
9643 md_estimate_size_before_relax (fragS *fragP, segT segment)
9645 /* We've already got fragP->fr_subtype right; all we have to do is
9646 check for un-relaxable symbols. On an ELF system, we can't relax
9647 an externally visible symbol, because it may be overridden by a
9649 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9652 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9655 #if defined (OBJ_COFF) && defined (TE_PE)
9656 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9657 && S_IS_WEAK (fragP->fr_symbol))
9661 /* Symbol is undefined in this segment, or we need to keep a
9662 reloc so that weak symbols can be overridden. */
9663 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9664 enum bfd_reloc_code_real reloc_type;
9665 unsigned char *opcode;
9668 if (fragP->fr_var != NO_RELOC)
9669 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9671 reloc_type = BFD_RELOC_16_PCREL;
9672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9673 else if (need_plt32_p (fragP->fr_symbol))
9674 reloc_type = BFD_RELOC_X86_64_PLT32;
9677 reloc_type = BFD_RELOC_32_PCREL;
9679 old_fr_fix = fragP->fr_fix;
9680 opcode = (unsigned char *) fragP->fr_opcode;
9682 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9685 /* Make jmp (0xeb) a (d)word displacement jump. */
9687 fragP->fr_fix += size;
9688 fix_new (fragP, old_fr_fix, size,
9690 fragP->fr_offset, 1,
9696 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9698 /* Negate the condition, and branch past an
9699 unconditional jump. */
9702 /* Insert an unconditional jump. */
9704 /* We added two extra opcode bytes, and have a two byte
9706 fragP->fr_fix += 2 + 2;
9707 fix_new (fragP, old_fr_fix + 2, 2,
9709 fragP->fr_offset, 1,
9716 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9721 fixP = fix_new (fragP, old_fr_fix, 1,
9723 fragP->fr_offset, 1,
9725 fixP->fx_signed = 1;
9729 /* This changes the byte-displacement jump 0x7N
9730 to the (d)word-displacement jump 0x0f,0x8N. */
9731 opcode[1] = opcode[0] + 0x10;
9732 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9733 /* We've added an opcode byte. */
9734 fragP->fr_fix += 1 + size;
9735 fix_new (fragP, old_fr_fix + 1, size,
9737 fragP->fr_offset, 1,
9742 BAD_CASE (fragP->fr_subtype);
9746 return fragP->fr_fix - old_fr_fix;
9749 /* Guess size depending on current relax state. Initially the relax
9750 state will correspond to a short jump and we return 1, because
9751 the variable part of the frag (the branch offset) is one byte
9752 long. However, we can relax a section more than once and in that
9753 case we must either set fr_subtype back to the unrelaxed state,
9754 or return the value for the appropriate branch. */
9755 return md_relax_table[fragP->fr_subtype].rlx_length;
9758 /* Called after relax() is finished.
9760 In: Address of frag.
9761 fr_type == rs_machine_dependent.
9762 fr_subtype is what the address relaxed to.
9764 Out: Any fixSs and constants are set up.
9765 Caller will turn frag into a ".space 0". */
9768 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9771 unsigned char *opcode;
9772 unsigned char *where_to_put_displacement = NULL;
9773 offsetT target_address;
9774 offsetT opcode_address;
9775 unsigned int extension = 0;
9776 offsetT displacement_from_opcode_start;
9778 opcode = (unsigned char *) fragP->fr_opcode;
9780 /* Address we want to reach in file space. */
9781 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9783 /* Address opcode resides at in file space. */
9784 opcode_address = fragP->fr_address + fragP->fr_fix;
9786 /* Displacement from opcode start to fill into instruction. */
9787 displacement_from_opcode_start = target_address - opcode_address;
9789 if ((fragP->fr_subtype & BIG) == 0)
9791 /* Don't have to change opcode. */
9792 extension = 1; /* 1 opcode + 1 displacement */
9793 where_to_put_displacement = &opcode[1];
9797 if (no_cond_jump_promotion
9798 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9799 as_warn_where (fragP->fr_file, fragP->fr_line,
9800 _("long jump required"));
9802 switch (fragP->fr_subtype)
9804 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9805 extension = 4; /* 1 opcode + 4 displacement */
9807 where_to_put_displacement = &opcode[1];
9810 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9811 extension = 2; /* 1 opcode + 2 displacement */
9813 where_to_put_displacement = &opcode[1];
9816 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9817 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9818 extension = 5; /* 2 opcode + 4 displacement */
9819 opcode[1] = opcode[0] + 0x10;
9820 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9821 where_to_put_displacement = &opcode[2];
9824 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9825 extension = 3; /* 2 opcode + 2 displacement */
9826 opcode[1] = opcode[0] + 0x10;
9827 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9828 where_to_put_displacement = &opcode[2];
9831 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9836 where_to_put_displacement = &opcode[3];
9840 BAD_CASE (fragP->fr_subtype);
9845 /* If size if less then four we are sure that the operand fits,
9846 but if it's 4, then it could be that the displacement is larger
9848 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9850 && ((addressT) (displacement_from_opcode_start - extension
9851 + ((addressT) 1 << 31))
9852 > (((addressT) 2 << 31) - 1)))
9854 as_bad_where (fragP->fr_file, fragP->fr_line,
9855 _("jump target out of range"));
9856 /* Make us emit 0. */
9857 displacement_from_opcode_start = extension;
9859 /* Now put displacement after opcode. */
9860 md_number_to_chars ((char *) where_to_put_displacement,
9861 (valueT) (displacement_from_opcode_start - extension),
9862 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9863 fragP->fr_fix += extension;
9866 /* Apply a fixup (fixP) to segment data, once it has been determined
9867 by our caller that we have all the info we need to fix it up.
9869 Parameter valP is the pointer to the value of the bits.
9871 On the 386, immediates, displacements, and data pointers are all in
9872 the same (little-endian) format, so we don't need to care about which
9876 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9878 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9879 valueT value = *valP;
9881 #if !defined (TE_Mach)
9884 switch (fixP->fx_r_type)
9890 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9893 case BFD_RELOC_X86_64_32S:
9894 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9897 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9900 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9905 if (fixP->fx_addsy != NULL
9906 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9907 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9908 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9909 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9910 && !use_rela_relocations)
9912 /* This is a hack. There should be a better way to handle this.
9913 This covers for the fact that bfd_install_relocation will
9914 subtract the current location (for partial_inplace, PC relative
9915 relocations); see more below. */
9919 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9922 value += fixP->fx_where + fixP->fx_frag->fr_address;
9924 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9927 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9930 || (symbol_section_p (fixP->fx_addsy)
9931 && sym_seg != absolute_section))
9932 && !generic_force_reloc (fixP))
9934 /* Yes, we add the values in twice. This is because
9935 bfd_install_relocation subtracts them out again. I think
9936 bfd_install_relocation is broken, but I don't dare change
9938 value += fixP->fx_where + fixP->fx_frag->fr_address;
9942 #if defined (OBJ_COFF) && defined (TE_PE)
9943 /* For some reason, the PE format does not store a
9944 section address offset for a PC relative symbol. */
9945 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9946 || S_IS_WEAK (fixP->fx_addsy))
9947 value += md_pcrel_from (fixP);
9950 #if defined (OBJ_COFF) && defined (TE_PE)
9951 if (fixP->fx_addsy != NULL
9952 && S_IS_WEAK (fixP->fx_addsy)
9953 /* PR 16858: Do not modify weak function references. */
9954 && ! fixP->fx_pcrel)
9956 #if !defined (TE_PEP)
9957 /* For x86 PE weak function symbols are neither PC-relative
9958 nor do they set S_IS_FUNCTION. So the only reliable way
9959 to detect them is to check the flags of their containing
9961 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9962 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9966 value -= S_GET_VALUE (fixP->fx_addsy);
9970 /* Fix a few things - the dynamic linker expects certain values here,
9971 and we must not disappoint it. */
9972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9973 if (IS_ELF && fixP->fx_addsy)
9974 switch (fixP->fx_r_type)
9976 case BFD_RELOC_386_PLT32:
9977 case BFD_RELOC_X86_64_PLT32:
9978 /* Make the jump instruction point to the address of the operand. At
9979 runtime we merely add the offset to the actual PLT entry. */
9983 case BFD_RELOC_386_TLS_GD:
9984 case BFD_RELOC_386_TLS_LDM:
9985 case BFD_RELOC_386_TLS_IE_32:
9986 case BFD_RELOC_386_TLS_IE:
9987 case BFD_RELOC_386_TLS_GOTIE:
9988 case BFD_RELOC_386_TLS_GOTDESC:
9989 case BFD_RELOC_X86_64_TLSGD:
9990 case BFD_RELOC_X86_64_TLSLD:
9991 case BFD_RELOC_X86_64_GOTTPOFF:
9992 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9993 value = 0; /* Fully resolved at runtime. No addend. */
9995 case BFD_RELOC_386_TLS_LE:
9996 case BFD_RELOC_386_TLS_LDO_32:
9997 case BFD_RELOC_386_TLS_LE_32:
9998 case BFD_RELOC_X86_64_DTPOFF32:
9999 case BFD_RELOC_X86_64_DTPOFF64:
10000 case BFD_RELOC_X86_64_TPOFF32:
10001 case BFD_RELOC_X86_64_TPOFF64:
10002 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10005 case BFD_RELOC_386_TLS_DESC_CALL:
10006 case BFD_RELOC_X86_64_TLSDESC_CALL:
10007 value = 0; /* Fully resolved at runtime. No addend. */
10008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10012 case BFD_RELOC_VTABLE_INHERIT:
10013 case BFD_RELOC_VTABLE_ENTRY:
10020 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10022 #endif /* !defined (TE_Mach) */
10024 /* Are we finished with this relocation now? */
10025 if (fixP->fx_addsy == NULL)
10027 #if defined (OBJ_COFF) && defined (TE_PE)
10028 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10031 /* Remember value for tc_gen_reloc. */
10032 fixP->fx_addnumber = value;
10033 /* Clear out the frag for now. */
10037 else if (use_rela_relocations)
10039 fixP->fx_no_overflow = 1;
10040 /* Remember value for tc_gen_reloc. */
10041 fixP->fx_addnumber = value;
10045 md_number_to_chars (p, value, fixP->fx_size);
10049 md_atof (int type, char *litP, int *sizeP)
10051 /* This outputs the LITTLENUMs in REVERSE order;
10052 in accord with the bigendian 386. */
10053 return ieee_md_atof (type, litP, sizeP, FALSE);
10056 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10059 output_invalid (int c)
10062 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10065 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10066 "(0x%x)", (unsigned char) c);
10067 return output_invalid_buf;
10070 /* REG_STRING starts *before* REGISTER_PREFIX. */
10072 static const reg_entry *
10073 parse_real_register (char *reg_string, char **end_op)
10075 char *s = reg_string;
10077 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10078 const reg_entry *r;
10080 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10081 if (*s == REGISTER_PREFIX)
10084 if (is_space_char (*s))
10087 p = reg_name_given;
10088 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10090 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10091 return (const reg_entry *) NULL;
10095 /* For naked regs, make sure that we are not dealing with an identifier.
10096 This prevents confusing an identifier like `eax_var' with register
10098 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10099 return (const reg_entry *) NULL;
10103 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10105 /* Handle floating point regs, allowing spaces in the (i) part. */
10106 if (r == i386_regtab /* %st is first entry of table */)
10108 if (is_space_char (*s))
10113 if (is_space_char (*s))
10115 if (*s >= '0' && *s <= '7')
10117 int fpr = *s - '0';
10119 if (is_space_char (*s))
10124 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10129 /* We have "%st(" then garbage. */
10130 return (const reg_entry *) NULL;
10134 if (r == NULL || allow_pseudo_reg)
10137 if (operand_type_all_zero (&r->reg_type))
10138 return (const reg_entry *) NULL;
10140 if ((r->reg_type.bitfield.dword
10141 || r->reg_type.bitfield.sreg3
10142 || r->reg_type.bitfield.control
10143 || r->reg_type.bitfield.debug
10144 || r->reg_type.bitfield.test)
10145 && !cpu_arch_flags.bitfield.cpui386)
10146 return (const reg_entry *) NULL;
10148 if (r->reg_type.bitfield.tbyte
10149 && !cpu_arch_flags.bitfield.cpu8087
10150 && !cpu_arch_flags.bitfield.cpu287
10151 && !cpu_arch_flags.bitfield.cpu387)
10152 return (const reg_entry *) NULL;
10154 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10155 return (const reg_entry *) NULL;
10157 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10158 return (const reg_entry *) NULL;
10160 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10161 return (const reg_entry *) NULL;
10163 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10164 return (const reg_entry *) NULL;
10166 if (r->reg_type.bitfield.regmask
10167 && !cpu_arch_flags.bitfield.cpuregmask)
10168 return (const reg_entry *) NULL;
10170 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10171 if (!allow_index_reg
10172 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10173 return (const reg_entry *) NULL;
10175 /* Upper 16 vector register is only available with VREX in 64bit
10177 if ((r->reg_flags & RegVRex))
10179 if (i.vec_encoding == vex_encoding_default)
10180 i.vec_encoding = vex_encoding_evex;
10182 if (!cpu_arch_flags.bitfield.cpuvrex
10183 || i.vec_encoding != vex_encoding_evex
10184 || flag_code != CODE_64BIT)
10185 return (const reg_entry *) NULL;
10188 if (((r->reg_flags & (RegRex64 | RegRex))
10189 || r->reg_type.bitfield.qword)
10190 && (!cpu_arch_flags.bitfield.cpulm
10191 || !operand_type_equal (&r->reg_type, &control))
10192 && flag_code != CODE_64BIT)
10193 return (const reg_entry *) NULL;
10195 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10196 return (const reg_entry *) NULL;
10201 /* REG_STRING starts *before* REGISTER_PREFIX. */
10203 static const reg_entry *
10204 parse_register (char *reg_string, char **end_op)
10206 const reg_entry *r;
10208 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10209 r = parse_real_register (reg_string, end_op);
10214 char *save = input_line_pointer;
10218 input_line_pointer = reg_string;
10219 c = get_symbol_name (®_string);
10220 symbolP = symbol_find (reg_string);
10221 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10223 const expressionS *e = symbol_get_value_expression (symbolP);
10225 know (e->X_op == O_register);
10226 know (e->X_add_number >= 0
10227 && (valueT) e->X_add_number < i386_regtab_size);
10228 r = i386_regtab + e->X_add_number;
10229 if ((r->reg_flags & RegVRex))
10230 i.vec_encoding = vex_encoding_evex;
10231 *end_op = input_line_pointer;
10233 *input_line_pointer = c;
10234 input_line_pointer = save;
10240 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10242 const reg_entry *r;
10243 char *end = input_line_pointer;
10246 r = parse_register (name, &input_line_pointer);
10247 if (r && end <= input_line_pointer)
10249 *nextcharP = *input_line_pointer;
10250 *input_line_pointer = 0;
10251 e->X_op = O_register;
10252 e->X_add_number = r - i386_regtab;
10255 input_line_pointer = end;
10257 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10261 md_operand (expressionS *e)
10264 const reg_entry *r;
10266 switch (*input_line_pointer)
10268 case REGISTER_PREFIX:
10269 r = parse_real_register (input_line_pointer, &end);
10272 e->X_op = O_register;
10273 e->X_add_number = r - i386_regtab;
10274 input_line_pointer = end;
10279 gas_assert (intel_syntax);
10280 end = input_line_pointer++;
10282 if (*input_line_pointer == ']')
10284 ++input_line_pointer;
10285 e->X_op_symbol = make_expr_symbol (e);
10286 e->X_add_symbol = NULL;
10287 e->X_add_number = 0;
10292 e->X_op = O_absent;
10293 input_line_pointer = end;
10300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10301 const char *md_shortopts = "kVQ:sqnO::";
10303 const char *md_shortopts = "qnO::";
10306 #define OPTION_32 (OPTION_MD_BASE + 0)
10307 #define OPTION_64 (OPTION_MD_BASE + 1)
10308 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10309 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10310 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10311 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10312 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10313 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10314 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10315 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10316 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10317 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10318 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10319 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10320 #define OPTION_X32 (OPTION_MD_BASE + 14)
10321 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10322 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10323 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10324 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10325 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10326 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10327 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10328 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10329 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10330 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10331 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10333 struct option md_longopts[] =
10335 {"32", no_argument, NULL, OPTION_32},
10336 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10337 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10338 {"64", no_argument, NULL, OPTION_64},
10340 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10341 {"x32", no_argument, NULL, OPTION_X32},
10342 {"mshared", no_argument, NULL, OPTION_MSHARED},
10344 {"divide", no_argument, NULL, OPTION_DIVIDE},
10345 {"march", required_argument, NULL, OPTION_MARCH},
10346 {"mtune", required_argument, NULL, OPTION_MTUNE},
10347 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10348 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10349 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10350 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10351 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10352 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10353 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10354 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10355 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10356 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10357 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10358 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10359 # if defined (TE_PE) || defined (TE_PEP)
10360 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10362 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10363 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10364 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10365 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10366 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10367 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10368 {NULL, no_argument, NULL, 0}
10370 size_t md_longopts_size = sizeof (md_longopts);
10373 md_parse_option (int c, const char *arg)
10376 char *arch, *next, *saved;
10381 optimize_align_code = 0;
10385 quiet_warnings = 1;
10388 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10389 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10390 should be emitted or not. FIXME: Not implemented. */
10394 /* -V: SVR4 argument to print version ID. */
10396 print_version_id ();
10399 /* -k: Ignore for FreeBSD compatibility. */
10404 /* -s: On i386 Solaris, this tells the native assembler to use
10405 .stab instead of .stab.excl. We always use .stab anyhow. */
10408 case OPTION_MSHARED:
10412 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10413 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10416 const char **list, **l;
10418 list = bfd_target_list ();
10419 for (l = list; *l != NULL; l++)
10420 if (CONST_STRNEQ (*l, "elf64-x86-64")
10421 || strcmp (*l, "coff-x86-64") == 0
10422 || strcmp (*l, "pe-x86-64") == 0
10423 || strcmp (*l, "pei-x86-64") == 0
10424 || strcmp (*l, "mach-o-x86-64") == 0)
10426 default_arch = "x86_64";
10430 as_fatal (_("no compiled in support for x86_64"));
10436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10440 const char **list, **l;
10442 list = bfd_target_list ();
10443 for (l = list; *l != NULL; l++)
10444 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10446 default_arch = "x86_64:32";
10450 as_fatal (_("no compiled in support for 32bit x86_64"));
10454 as_fatal (_("32bit x86_64 is only supported for ELF"));
10459 default_arch = "i386";
10462 case OPTION_DIVIDE:
10463 #ifdef SVR4_COMMENT_CHARS
10468 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10470 for (s = i386_comment_chars; *s != '\0'; s++)
10474 i386_comment_chars = n;
10480 saved = xstrdup (arg);
10482 /* Allow -march=+nosse. */
10488 as_fatal (_("invalid -march= option: `%s'"), arg);
10489 next = strchr (arch, '+');
10492 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10494 if (strcmp (arch, cpu_arch [j].name) == 0)
10497 if (! cpu_arch[j].flags.bitfield.cpui386)
10500 cpu_arch_name = cpu_arch[j].name;
10501 cpu_sub_arch_name = NULL;
10502 cpu_arch_flags = cpu_arch[j].flags;
10503 cpu_arch_isa = cpu_arch[j].type;
10504 cpu_arch_isa_flags = cpu_arch[j].flags;
10505 if (!cpu_arch_tune_set)
10507 cpu_arch_tune = cpu_arch_isa;
10508 cpu_arch_tune_flags = cpu_arch_isa_flags;
10512 else if (*cpu_arch [j].name == '.'
10513 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10515 /* ISA extension. */
10516 i386_cpu_flags flags;
10518 flags = cpu_flags_or (cpu_arch_flags,
10519 cpu_arch[j].flags);
10521 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10523 if (cpu_sub_arch_name)
10525 char *name = cpu_sub_arch_name;
10526 cpu_sub_arch_name = concat (name,
10528 (const char *) NULL);
10532 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10533 cpu_arch_flags = flags;
10534 cpu_arch_isa_flags = flags;
10540 if (j >= ARRAY_SIZE (cpu_arch))
10542 /* Disable an ISA extension. */
10543 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10544 if (strcmp (arch, cpu_noarch [j].name) == 0)
10546 i386_cpu_flags flags;
10548 flags = cpu_flags_and_not (cpu_arch_flags,
10549 cpu_noarch[j].flags);
10550 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10552 if (cpu_sub_arch_name)
10554 char *name = cpu_sub_arch_name;
10555 cpu_sub_arch_name = concat (arch,
10556 (const char *) NULL);
10560 cpu_sub_arch_name = xstrdup (arch);
10561 cpu_arch_flags = flags;
10562 cpu_arch_isa_flags = flags;
10567 if (j >= ARRAY_SIZE (cpu_noarch))
10568 j = ARRAY_SIZE (cpu_arch);
10571 if (j >= ARRAY_SIZE (cpu_arch))
10572 as_fatal (_("invalid -march= option: `%s'"), arg);
10576 while (next != NULL);
10582 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10583 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10585 if (strcmp (arg, cpu_arch [j].name) == 0)
10587 cpu_arch_tune_set = 1;
10588 cpu_arch_tune = cpu_arch [j].type;
10589 cpu_arch_tune_flags = cpu_arch[j].flags;
10593 if (j >= ARRAY_SIZE (cpu_arch))
10594 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10597 case OPTION_MMNEMONIC:
10598 if (strcasecmp (arg, "att") == 0)
10599 intel_mnemonic = 0;
10600 else if (strcasecmp (arg, "intel") == 0)
10601 intel_mnemonic = 1;
10603 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10606 case OPTION_MSYNTAX:
10607 if (strcasecmp (arg, "att") == 0)
10609 else if (strcasecmp (arg, "intel") == 0)
10612 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10615 case OPTION_MINDEX_REG:
10616 allow_index_reg = 1;
10619 case OPTION_MNAKED_REG:
10620 allow_naked_reg = 1;
10623 case OPTION_MOLD_GCC:
10627 case OPTION_MSSE2AVX:
10631 case OPTION_MSSE_CHECK:
10632 if (strcasecmp (arg, "error") == 0)
10633 sse_check = check_error;
10634 else if (strcasecmp (arg, "warning") == 0)
10635 sse_check = check_warning;
10636 else if (strcasecmp (arg, "none") == 0)
10637 sse_check = check_none;
10639 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10642 case OPTION_MOPERAND_CHECK:
10643 if (strcasecmp (arg, "error") == 0)
10644 operand_check = check_error;
10645 else if (strcasecmp (arg, "warning") == 0)
10646 operand_check = check_warning;
10647 else if (strcasecmp (arg, "none") == 0)
10648 operand_check = check_none;
10650 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10653 case OPTION_MAVXSCALAR:
10654 if (strcasecmp (arg, "128") == 0)
10655 avxscalar = vex128;
10656 else if (strcasecmp (arg, "256") == 0)
10657 avxscalar = vex256;
10659 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10662 case OPTION_MADD_BND_PREFIX:
10663 add_bnd_prefix = 1;
10666 case OPTION_MEVEXLIG:
10667 if (strcmp (arg, "128") == 0)
10668 evexlig = evexl128;
10669 else if (strcmp (arg, "256") == 0)
10670 evexlig = evexl256;
10671 else if (strcmp (arg, "512") == 0)
10672 evexlig = evexl512;
10674 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10677 case OPTION_MEVEXRCIG:
10678 if (strcmp (arg, "rne") == 0)
10680 else if (strcmp (arg, "rd") == 0)
10682 else if (strcmp (arg, "ru") == 0)
10684 else if (strcmp (arg, "rz") == 0)
10687 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10690 case OPTION_MEVEXWIG:
10691 if (strcmp (arg, "0") == 0)
10693 else if (strcmp (arg, "1") == 0)
10696 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10699 # if defined (TE_PE) || defined (TE_PEP)
10700 case OPTION_MBIG_OBJ:
10705 case OPTION_MOMIT_LOCK_PREFIX:
10706 if (strcasecmp (arg, "yes") == 0)
10707 omit_lock_prefix = 1;
10708 else if (strcasecmp (arg, "no") == 0)
10709 omit_lock_prefix = 0;
10711 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10714 case OPTION_MFENCE_AS_LOCK_ADD:
10715 if (strcasecmp (arg, "yes") == 0)
10717 else if (strcasecmp (arg, "no") == 0)
10720 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10723 case OPTION_MRELAX_RELOCATIONS:
10724 if (strcasecmp (arg, "yes") == 0)
10725 generate_relax_relocations = 1;
10726 else if (strcasecmp (arg, "no") == 0)
10727 generate_relax_relocations = 0;
10729 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10732 case OPTION_MAMD64:
10736 case OPTION_MINTEL64:
10744 /* Turn off -Os. */
10745 optimize_for_space = 0;
10747 else if (*arg == 's')
10749 optimize_for_space = 1;
10750 /* Turn on all encoding optimizations. */
10755 optimize = atoi (arg);
10756 /* Turn off -Os. */
10757 optimize_for_space = 0;
10767 #define MESSAGE_TEMPLATE \
10771 output_message (FILE *stream, char *p, char *message, char *start,
10772 int *left_p, const char *name, int len)
10774 int size = sizeof (MESSAGE_TEMPLATE);
10775 int left = *left_p;
10777 /* Reserve 2 spaces for ", " or ",\0" */
10780 /* Check if there is any room. */
10788 p = mempcpy (p, name, len);
10792 /* Output the current message now and start a new one. */
10795 fprintf (stream, "%s\n", message);
10797 left = size - (start - message) - len - 2;
10799 gas_assert (left >= 0);
10801 p = mempcpy (p, name, len);
10809 show_arch (FILE *stream, int ext, int check)
10811 static char message[] = MESSAGE_TEMPLATE;
10812 char *start = message + 27;
10814 int size = sizeof (MESSAGE_TEMPLATE);
10821 left = size - (start - message);
10822 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10824 /* Should it be skipped? */
10825 if (cpu_arch [j].skip)
10828 name = cpu_arch [j].name;
10829 len = cpu_arch [j].len;
10832 /* It is an extension. Skip if we aren't asked to show it. */
10843 /* It is an processor. Skip if we show only extension. */
10846 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10848 /* It is an impossible processor - skip. */
10852 p = output_message (stream, p, message, start, &left, name, len);
10855 /* Display disabled extensions. */
10857 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10859 name = cpu_noarch [j].name;
10860 len = cpu_noarch [j].len;
10861 p = output_message (stream, p, message, start, &left, name,
10866 fprintf (stream, "%s\n", message);
10870 md_show_usage (FILE *stream)
10872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10873 fprintf (stream, _("\
10875 -V print assembler version number\n\
10878 fprintf (stream, _("\
10879 -n Do not optimize code alignment\n\
10880 -q quieten some warnings\n"));
10881 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10882 fprintf (stream, _("\
10885 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10886 || defined (TE_PE) || defined (TE_PEP))
10887 fprintf (stream, _("\
10888 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10890 #ifdef SVR4_COMMENT_CHARS
10891 fprintf (stream, _("\
10892 --divide do not treat `/' as a comment character\n"));
10894 fprintf (stream, _("\
10895 --divide ignored\n"));
10897 fprintf (stream, _("\
10898 -march=CPU[,+EXTENSION...]\n\
10899 generate code for CPU and EXTENSION, CPU is one of:\n"));
10900 show_arch (stream, 0, 1);
10901 fprintf (stream, _("\
10902 EXTENSION is combination of:\n"));
10903 show_arch (stream, 1, 0);
10904 fprintf (stream, _("\
10905 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10906 show_arch (stream, 0, 0);
10907 fprintf (stream, _("\
10908 -msse2avx encode SSE instructions with VEX prefix\n"));
10909 fprintf (stream, _("\
10910 -msse-check=[none|error|warning]\n\
10911 check SSE instructions\n"));
10912 fprintf (stream, _("\
10913 -moperand-check=[none|error|warning]\n\
10914 check operand combinations for validity\n"));
10915 fprintf (stream, _("\
10916 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10918 fprintf (stream, _("\
10919 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10921 fprintf (stream, _("\
10922 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10923 for EVEX.W bit ignored instructions\n"));
10924 fprintf (stream, _("\
10925 -mevexrcig=[rne|rd|ru|rz]\n\
10926 encode EVEX instructions with specific EVEX.RC value\n\
10927 for SAE-only ignored instructions\n"));
10928 fprintf (stream, _("\
10929 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10930 fprintf (stream, _("\
10931 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10932 fprintf (stream, _("\
10933 -mindex-reg support pseudo index registers\n"));
10934 fprintf (stream, _("\
10935 -mnaked-reg don't require `%%' prefix for registers\n"));
10936 fprintf (stream, _("\
10937 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10938 fprintf (stream, _("\
10939 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10940 fprintf (stream, _("\
10941 -mshared disable branch optimization for shared code\n"));
10942 # if defined (TE_PE) || defined (TE_PEP)
10943 fprintf (stream, _("\
10944 -mbig-obj generate big object files\n"));
10946 fprintf (stream, _("\
10947 -momit-lock-prefix=[no|yes]\n\
10948 strip all lock prefixes\n"));
10949 fprintf (stream, _("\
10950 -mfence-as-lock-add=[no|yes]\n\
10951 encode lfence, mfence and sfence as\n\
10952 lock addl $0x0, (%%{re}sp)\n"));
10953 fprintf (stream, _("\
10954 -mrelax-relocations=[no|yes]\n\
10955 generate relax relocations\n"));
10956 fprintf (stream, _("\
10957 -mamd64 accept only AMD64 ISA\n"));
10958 fprintf (stream, _("\
10959 -mintel64 accept only Intel64 ISA\n"));
10962 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10963 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10964 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10966 /* Pick the target format to use. */
10969 i386_target_format (void)
10971 if (!strncmp (default_arch, "x86_64", 6))
10973 update_code_flag (CODE_64BIT, 1);
10974 if (default_arch[6] == '\0')
10975 x86_elf_abi = X86_64_ABI;
10977 x86_elf_abi = X86_64_X32_ABI;
10979 else if (!strcmp (default_arch, "i386"))
10980 update_code_flag (CODE_32BIT, 1);
10981 else if (!strcmp (default_arch, "iamcu"))
10983 update_code_flag (CODE_32BIT, 1);
10984 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10986 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10987 cpu_arch_name = "iamcu";
10988 cpu_sub_arch_name = NULL;
10989 cpu_arch_flags = iamcu_flags;
10990 cpu_arch_isa = PROCESSOR_IAMCU;
10991 cpu_arch_isa_flags = iamcu_flags;
10992 if (!cpu_arch_tune_set)
10994 cpu_arch_tune = cpu_arch_isa;
10995 cpu_arch_tune_flags = cpu_arch_isa_flags;
10998 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10999 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11003 as_fatal (_("unknown architecture"));
11005 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11006 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11007 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11008 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11010 switch (OUTPUT_FLAVOR)
11012 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11013 case bfd_target_aout_flavour:
11014 return AOUT_TARGET_FORMAT;
11016 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11017 # if defined (TE_PE) || defined (TE_PEP)
11018 case bfd_target_coff_flavour:
11019 if (flag_code == CODE_64BIT)
11020 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11023 # elif defined (TE_GO32)
11024 case bfd_target_coff_flavour:
11025 return "coff-go32";
11027 case bfd_target_coff_flavour:
11028 return "coff-i386";
11031 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11032 case bfd_target_elf_flavour:
11034 const char *format;
11036 switch (x86_elf_abi)
11039 format = ELF_TARGET_FORMAT;
11042 use_rela_relocations = 1;
11044 format = ELF_TARGET_FORMAT64;
11046 case X86_64_X32_ABI:
11047 use_rela_relocations = 1;
11049 disallow_64bit_reloc = 1;
11050 format = ELF_TARGET_FORMAT32;
11053 if (cpu_arch_isa == PROCESSOR_L1OM)
11055 if (x86_elf_abi != X86_64_ABI)
11056 as_fatal (_("Intel L1OM is 64bit only"));
11057 return ELF_TARGET_L1OM_FORMAT;
11059 else if (cpu_arch_isa == PROCESSOR_K1OM)
11061 if (x86_elf_abi != X86_64_ABI)
11062 as_fatal (_("Intel K1OM is 64bit only"));
11063 return ELF_TARGET_K1OM_FORMAT;
11065 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11067 if (x86_elf_abi != I386_ABI)
11068 as_fatal (_("Intel MCU is 32bit only"));
11069 return ELF_TARGET_IAMCU_FORMAT;
11075 #if defined (OBJ_MACH_O)
11076 case bfd_target_mach_o_flavour:
11077 if (flag_code == CODE_64BIT)
11079 use_rela_relocations = 1;
11081 return "mach-o-x86-64";
11084 return "mach-o-i386";
11092 #endif /* OBJ_MAYBE_ more than one */
11095 md_undefined_symbol (char *name)
11097 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11098 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11099 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11100 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11104 if (symbol_find (name))
11105 as_bad (_("GOT already in symbol table"));
11106 GOT_symbol = symbol_new (name, undefined_section,
11107 (valueT) 0, &zero_address_frag);
11114 /* Round up a section size to the appropriate boundary. */
11117 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11119 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11120 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11122 /* For a.out, force the section size to be aligned. If we don't do
11123 this, BFD will align it for us, but it will not write out the
11124 final bytes of the section. This may be a bug in BFD, but it is
11125 easier to fix it here since that is how the other a.out targets
11129 align = bfd_get_section_alignment (stdoutput, segment);
11130 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11137 /* On the i386, PC-relative offsets are relative to the start of the
11138 next instruction. That is, the address of the offset, plus its
11139 size, since the offset is always the last part of the insn. */
11142 md_pcrel_from (fixS *fixP)
11144 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11150 s_bss (int ignore ATTRIBUTE_UNUSED)
11154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11156 obj_elf_section_change_hook ();
11158 temp = get_absolute_expression ();
11159 subseg_set (bss_section, (subsegT) temp);
11160 demand_empty_rest_of_line ();
11166 i386_validate_fix (fixS *fixp)
11168 if (fixp->fx_subsy)
11170 if (fixp->fx_subsy == GOT_symbol)
11172 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11176 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11177 if (fixp->fx_tcbit2)
11178 fixp->fx_r_type = (fixp->fx_tcbit
11179 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11180 : BFD_RELOC_X86_64_GOTPCRELX);
11183 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11188 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11190 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11192 fixp->fx_subsy = 0;
11195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11196 else if (!object_64bit)
11198 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11199 && fixp->fx_tcbit2)
11200 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11206 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11209 bfd_reloc_code_real_type code;
11211 switch (fixp->fx_r_type)
11213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11214 case BFD_RELOC_SIZE32:
11215 case BFD_RELOC_SIZE64:
11216 if (S_IS_DEFINED (fixp->fx_addsy)
11217 && !S_IS_EXTERNAL (fixp->fx_addsy))
11219 /* Resolve size relocation against local symbol to size of
11220 the symbol plus addend. */
11221 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11222 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11223 && !fits_in_unsigned_long (value))
11224 as_bad_where (fixp->fx_file, fixp->fx_line,
11225 _("symbol size computation overflow"));
11226 fixp->fx_addsy = NULL;
11227 fixp->fx_subsy = NULL;
11228 md_apply_fix (fixp, (valueT *) &value, NULL);
11232 /* Fall through. */
11234 case BFD_RELOC_X86_64_PLT32:
11235 case BFD_RELOC_X86_64_GOT32:
11236 case BFD_RELOC_X86_64_GOTPCREL:
11237 case BFD_RELOC_X86_64_GOTPCRELX:
11238 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11239 case BFD_RELOC_386_PLT32:
11240 case BFD_RELOC_386_GOT32:
11241 case BFD_RELOC_386_GOT32X:
11242 case BFD_RELOC_386_GOTOFF:
11243 case BFD_RELOC_386_GOTPC:
11244 case BFD_RELOC_386_TLS_GD:
11245 case BFD_RELOC_386_TLS_LDM:
11246 case BFD_RELOC_386_TLS_LDO_32:
11247 case BFD_RELOC_386_TLS_IE_32:
11248 case BFD_RELOC_386_TLS_IE:
11249 case BFD_RELOC_386_TLS_GOTIE:
11250 case BFD_RELOC_386_TLS_LE_32:
11251 case BFD_RELOC_386_TLS_LE:
11252 case BFD_RELOC_386_TLS_GOTDESC:
11253 case BFD_RELOC_386_TLS_DESC_CALL:
11254 case BFD_RELOC_X86_64_TLSGD:
11255 case BFD_RELOC_X86_64_TLSLD:
11256 case BFD_RELOC_X86_64_DTPOFF32:
11257 case BFD_RELOC_X86_64_DTPOFF64:
11258 case BFD_RELOC_X86_64_GOTTPOFF:
11259 case BFD_RELOC_X86_64_TPOFF32:
11260 case BFD_RELOC_X86_64_TPOFF64:
11261 case BFD_RELOC_X86_64_GOTOFF64:
11262 case BFD_RELOC_X86_64_GOTPC32:
11263 case BFD_RELOC_X86_64_GOT64:
11264 case BFD_RELOC_X86_64_GOTPCREL64:
11265 case BFD_RELOC_X86_64_GOTPC64:
11266 case BFD_RELOC_X86_64_GOTPLT64:
11267 case BFD_RELOC_X86_64_PLTOFF64:
11268 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11269 case BFD_RELOC_X86_64_TLSDESC_CALL:
11270 case BFD_RELOC_RVA:
11271 case BFD_RELOC_VTABLE_ENTRY:
11272 case BFD_RELOC_VTABLE_INHERIT:
11274 case BFD_RELOC_32_SECREL:
11276 code = fixp->fx_r_type;
11278 case BFD_RELOC_X86_64_32S:
11279 if (!fixp->fx_pcrel)
11281 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11282 code = fixp->fx_r_type;
11285 /* Fall through. */
11287 if (fixp->fx_pcrel)
11289 switch (fixp->fx_size)
11292 as_bad_where (fixp->fx_file, fixp->fx_line,
11293 _("can not do %d byte pc-relative relocation"),
11295 code = BFD_RELOC_32_PCREL;
11297 case 1: code = BFD_RELOC_8_PCREL; break;
11298 case 2: code = BFD_RELOC_16_PCREL; break;
11299 case 4: code = BFD_RELOC_32_PCREL; break;
11301 case 8: code = BFD_RELOC_64_PCREL; break;
11307 switch (fixp->fx_size)
11310 as_bad_where (fixp->fx_file, fixp->fx_line,
11311 _("can not do %d byte relocation"),
11313 code = BFD_RELOC_32;
11315 case 1: code = BFD_RELOC_8; break;
11316 case 2: code = BFD_RELOC_16; break;
11317 case 4: code = BFD_RELOC_32; break;
11319 case 8: code = BFD_RELOC_64; break;
11326 if ((code == BFD_RELOC_32
11327 || code == BFD_RELOC_32_PCREL
11328 || code == BFD_RELOC_X86_64_32S)
11330 && fixp->fx_addsy == GOT_symbol)
11333 code = BFD_RELOC_386_GOTPC;
11335 code = BFD_RELOC_X86_64_GOTPC32;
11337 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11339 && fixp->fx_addsy == GOT_symbol)
11341 code = BFD_RELOC_X86_64_GOTPC64;
11344 rel = XNEW (arelent);
11345 rel->sym_ptr_ptr = XNEW (asymbol *);
11346 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11348 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11350 if (!use_rela_relocations)
11352 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11353 vtable entry to be used in the relocation's section offset. */
11354 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11355 rel->address = fixp->fx_offset;
11356 #if defined (OBJ_COFF) && defined (TE_PE)
11357 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11358 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11363 /* Use the rela in 64bit mode. */
11366 if (disallow_64bit_reloc)
11369 case BFD_RELOC_X86_64_DTPOFF64:
11370 case BFD_RELOC_X86_64_TPOFF64:
11371 case BFD_RELOC_64_PCREL:
11372 case BFD_RELOC_X86_64_GOTOFF64:
11373 case BFD_RELOC_X86_64_GOT64:
11374 case BFD_RELOC_X86_64_GOTPCREL64:
11375 case BFD_RELOC_X86_64_GOTPC64:
11376 case BFD_RELOC_X86_64_GOTPLT64:
11377 case BFD_RELOC_X86_64_PLTOFF64:
11378 as_bad_where (fixp->fx_file, fixp->fx_line,
11379 _("cannot represent relocation type %s in x32 mode"),
11380 bfd_get_reloc_code_name (code));
11386 if (!fixp->fx_pcrel)
11387 rel->addend = fixp->fx_offset;
11391 case BFD_RELOC_X86_64_PLT32:
11392 case BFD_RELOC_X86_64_GOT32:
11393 case BFD_RELOC_X86_64_GOTPCREL:
11394 case BFD_RELOC_X86_64_GOTPCRELX:
11395 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11396 case BFD_RELOC_X86_64_TLSGD:
11397 case BFD_RELOC_X86_64_TLSLD:
11398 case BFD_RELOC_X86_64_GOTTPOFF:
11399 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11400 case BFD_RELOC_X86_64_TLSDESC_CALL:
11401 rel->addend = fixp->fx_offset - fixp->fx_size;
11404 rel->addend = (section->vma
11406 + fixp->fx_addnumber
11407 + md_pcrel_from (fixp));
11412 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11413 if (rel->howto == NULL)
11415 as_bad_where (fixp->fx_file, fixp->fx_line,
11416 _("cannot represent relocation type %s"),
11417 bfd_get_reloc_code_name (code));
11418 /* Set howto to a garbage value so that we can keep going. */
11419 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11420 gas_assert (rel->howto != NULL);
11426 #include "tc-i386-intel.c"
11429 tc_x86_parse_to_dw2regnum (expressionS *exp)
11431 int saved_naked_reg;
11432 char saved_register_dot;
11434 saved_naked_reg = allow_naked_reg;
11435 allow_naked_reg = 1;
11436 saved_register_dot = register_chars['.'];
11437 register_chars['.'] = '.';
11438 allow_pseudo_reg = 1;
11439 expression_and_evaluate (exp);
11440 allow_pseudo_reg = 0;
11441 register_chars['.'] = saved_register_dot;
11442 allow_naked_reg = saved_naked_reg;
11444 if (exp->X_op == O_register && exp->X_add_number >= 0)
11446 if ((addressT) exp->X_add_number < i386_regtab_size)
11448 exp->X_op = O_constant;
11449 exp->X_add_number = i386_regtab[exp->X_add_number]
11450 .dw2_regnum[flag_code >> 1];
11453 exp->X_op = O_illegal;
11458 tc_x86_frame_initial_instructions (void)
11460 static unsigned int sp_regno[2];
11462 if (!sp_regno[flag_code >> 1])
11464 char *saved_input = input_line_pointer;
11465 char sp[][4] = {"esp", "rsp"};
11468 input_line_pointer = sp[flag_code >> 1];
11469 tc_x86_parse_to_dw2regnum (&exp);
11470 gas_assert (exp.X_op == O_constant);
11471 sp_regno[flag_code >> 1] = exp.X_add_number;
11472 input_line_pointer = saved_input;
11475 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11476 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11480 x86_dwarf2_addr_size (void)
11482 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11483 if (x86_elf_abi == X86_64_X32_ABI)
11486 return bfd_arch_bits_per_address (stdoutput) / 8;
11490 i386_elf_section_type (const char *str, size_t len)
11492 if (flag_code == CODE_64BIT
11493 && len == sizeof ("unwind") - 1
11494 && strncmp (str, "unwind", 6) == 0)
11495 return SHT_X86_64_UNWIND;
11502 i386_solaris_fix_up_eh_frame (segT sec)
11504 if (flag_code == CODE_64BIT)
11505 elf_section_type (sec) = SHT_X86_64_UNWIND;
11511 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11515 exp.X_op = O_secrel;
11516 exp.X_add_symbol = symbol;
11517 exp.X_add_number = 0;
11518 emit_expr (&exp, size);
11522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11523 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11526 x86_64_section_letter (int letter, const char **ptr_msg)
11528 if (flag_code == CODE_64BIT)
11531 return SHF_X86_64_LARGE;
11533 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11536 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11541 x86_64_section_word (char *str, size_t len)
11543 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11544 return SHF_X86_64_LARGE;
11550 handle_large_common (int small ATTRIBUTE_UNUSED)
11552 if (flag_code != CODE_64BIT)
11554 s_comm_internal (0, elf_common_parse);
11555 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11559 static segT lbss_section;
11560 asection *saved_com_section_ptr = elf_com_section_ptr;
11561 asection *saved_bss_section = bss_section;
11563 if (lbss_section == NULL)
11565 flagword applicable;
11566 segT seg = now_seg;
11567 subsegT subseg = now_subseg;
11569 /* The .lbss section is for local .largecomm symbols. */
11570 lbss_section = subseg_new (".lbss", 0);
11571 applicable = bfd_applicable_section_flags (stdoutput);
11572 bfd_set_section_flags (stdoutput, lbss_section,
11573 applicable & SEC_ALLOC);
11574 seg_info (lbss_section)->bss = 1;
11576 subseg_set (seg, subseg);
11579 elf_com_section_ptr = &_bfd_elf_large_com_section;
11580 bss_section = lbss_section;
11582 s_comm_internal (0, elf_common_parse);
11584 elf_com_section_ptr = saved_com_section_ptr;
11585 bss_section = saved_bss_section;
11588 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */