1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry *parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_imm_operands (void);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry *build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS *, offsetT);
96 static void output_disp (fragS *, offsetT);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED);
104 static const char *default_arch = DEFAULT_ARCH;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry *regs;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 unsigned int types[MAX_OPERANDS];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op[MAX_OPERANDS];
141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry *seg[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars = "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars = "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars[] = "#/";
213 const char line_separator_chars[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars[256];
226 static char register_chars[256];
227 static char operand_chars[256];
228 static char identifier_chars[256];
229 static char digit_chars[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack[32];
247 static char *save_stack_p;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates *current_templates;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
263 /* Current operand we are working on. */
264 static int this_operand;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code;
276 static unsigned int object_64bit;
277 static int use_rela_relocations = 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names[] =
287 /* 1 for intel syntax,
289 static int intel_syntax = 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg = 0;
294 /* Register prefix used for error message. */
295 static const char *register_prefix = "%";
297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300 static char stackop_size = '\0';
302 /* Non-zero to optimize code alignment. */
303 int optimize_align_code = 1;
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings = 0;
309 static const char *cpu_arch_name = NULL;
310 static const char *cpu_sub_arch_name = NULL;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
315 /* If we have selected a cpu we are generating instructions for. */
316 static int cpu_arch_tune_set = 0;
318 /* Cpu we are generating instructions for. */
319 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321 /* CPU feature flags of cpu we are generating instructions for. */
322 static unsigned int cpu_arch_tune_flags = 0;
324 /* CPU instruction set architecture used. */
325 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of instruction set architecture used. */
328 static unsigned int cpu_arch_isa_flags = 0;
330 /* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332 static unsigned int no_cond_jump_promotion = 0;
334 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
335 static symbolS *GOT_symbol;
337 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
338 unsigned int x86_dwarf2_return_column;
340 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341 int x86_cie_data_alignment;
343 /* Interface to relax_segment.
344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
349 #define UNCOND_JUMP 0
351 #define COND_JUMP86 2
356 #define SMALL16 (SMALL | CODE16)
358 #define BIG16 (BIG | CODE16)
362 #define INLINE __inline__
368 #define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370 #define TYPE_FROM_RELAX_STATE(s) \
372 #define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
375 /* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
383 const relax_typeS md_relax_table[] =
386 1) most positive reach of this state,
387 2) most negative reach of this state,
388 3) how many bytes this mode will have in the variable part of the frag
389 4) which index into the table to try if we can't fit into this one. */
391 /* UNCOND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 3 bytes to frag:
408 1 extra opcode byte, 2 displacement bytes. */
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
422 static const arch_entry cpu_arch[] =
424 {"generic32", PROCESSOR_GENERIC32,
425 Cpu186|Cpu286|Cpu386},
426 {"generic64", PROCESSOR_GENERIC64,
427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
431 {"i186", PROCESSOR_UNKNOWN,
433 {"i286", PROCESSOR_UNKNOWN,
435 {"i386", PROCESSOR_GENERIC32,
436 Cpu186|Cpu286|Cpu386},
437 {"i486", PROCESSOR_I486,
438 Cpu186|Cpu286|Cpu386|Cpu486},
439 {"i586", PROCESSOR_PENTIUM,
440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
441 {"i686", PROCESSOR_PENTIUMPRO,
442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
443 {"pentium", PROCESSOR_PENTIUM,
444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
447 {"pentiumii", PROCESSOR_PENTIUMPRO,
448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
451 {"pentium4", PROCESSOR_PENTIUM4,
452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
460 {"yonah", PROCESSOR_CORE,
461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
463 {"core", PROCESSOR_CORE,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
474 {"k6_2", PROCESSOR_K6,
475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
476 {"athlon", PROCESSOR_ATHLON,
477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"amdfam10", PROCESSOR_AMDFAM10,
489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
492 {".mmx", PROCESSOR_UNKNOWN,
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
502 {".3dnow", PROCESSOR_UNKNOWN,
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
508 {".pacifica", PROCESSOR_UNKNOWN,
510 {".svme", PROCESSOR_UNKNOWN,
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
550 {"secrel32", pe_directive_secrel, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control *op_hash;
561 /* Hash table for register lookup. */
562 static struct hash_control *reg_hash;
565 i386_align_code (fragS *fragP, int count)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1[] =
572 static const char f32_2[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
629 static const char *const f16_patt[] = {
630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
634 static const char alt_3[] =
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
738 if (count <= 0 || count > 15)
741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code == CODE_16BIT)
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
776 for (i = 0; i < remains; i++)
778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
782 for (; i < nnops; i++)
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
791 const char *const *patt = NULL;
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
806 case PROCESSOR_CORE2:
807 patt = alt_long_patt;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
814 case PROCESSOR_ATHLON:
816 case PROCESSOR_GENERIC64:
817 case PROCESSOR_AMDFAM10:
818 patt = alt_short_patt;
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
829 switch (cpu_arch_tune)
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
844 case PROCESSOR_ATHLON:
846 case PROCESSOR_AMDFAM10:
847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
855 case PROCESSOR_CORE2:
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
867 memcpy (fragP->fr_literal + fragP->fr_fix,
868 patt[count - 1], count);
870 fragP->fr_var = count;
873 static INLINE unsigned int
874 mode_from_disp_size (unsigned int t)
876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
880 fits_in_signed_byte (offsetT num)
882 return (num >= -128) && (num <= 127);
886 fits_in_unsigned_byte (offsetT num)
888 return (num & 0xff) == num;
892 fits_in_unsigned_word (offsetT num)
894 return (num & 0xffff) == num;
898 fits_in_signed_word (offsetT num)
900 return (-32768 <= num) && (num <= 32767);
904 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
912 } /* fits_in_signed_long() */
915 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
922 } /* fits_in_unsigned_long() */
925 smallest_imm_type (offsetT num)
927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
937 return (fits_in_signed_byte (num)
938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
939 : fits_in_unsigned_byte (num)
940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
951 offset_in_range (offsetT val, int size)
957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
959 case 4: mask = ((addressT) 2 << 31) - 1; break;
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
966 /* If BFD64, sign extend val. */
967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
973 char buf1[40], buf2[40];
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
982 /* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
986 add_prefix (unsigned int prefix)
991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
994 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
995 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
996 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1020 case LOCK_PREFIX_OPCODE:
1028 case ADDR_PREFIX_OPCODE:
1032 case DATA_PREFIX_OPCODE:
1036 if (i.prefix[q] != 0)
1044 i.prefix[q] |= prefix;
1047 as_bad (_("same type of prefix used twice"));
1053 set_code_flag (int value)
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1060 as_bad (_("64bit mode not supported on this CPU."));
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1064 as_bad (_("32bit mode not supported on this CPU."));
1066 stackop_size = '\0';
1070 set_16bit_gcc_code_flag (int new_code_flag)
1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1075 stackop_size = LONG_MNEM_SUFFIX;
1079 set_intel_syntax (int syntax_flag)
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1090 if (strcmp (string, "prefix") == 0)
1092 else if (strcmp (string, "noprefix") == 0)
1095 as_bad (_("bad argument to syntax directive."));
1096 *input_line_pointer = e;
1098 demand_empty_rest_of_line ();
1100 intel_syntax = syntax_flag;
1102 if (ask_naked_reg == 0)
1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1106 allow_naked_reg = (ask_naked_reg < 0);
1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
1110 register_prefix = allow_naked_reg ? "" : "%";
1114 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
1133 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1134 cpu_arch_isa = cpu_arch[i].type;
1135 cpu_arch_isa_flags = cpu_arch[i].flags;
1136 if (!cpu_arch_tune_set)
1138 cpu_arch_tune = cpu_arch_isa;
1139 cpu_arch_tune_flags = cpu_arch_isa_flags;
1143 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1145 cpu_sub_arch_name = cpu_arch[i].name;
1146 cpu_arch_flags |= cpu_arch[i].flags;
1148 *input_line_pointer = e;
1149 demand_empty_rest_of_line ();
1153 if (i >= ARRAY_SIZE (cpu_arch))
1154 as_bad (_("no such architecture: `%s'"), string);
1156 *input_line_pointer = e;
1159 as_bad (_("missing cpu architecture"));
1161 no_cond_jump_promotion = 0;
1162 if (*input_line_pointer == ','
1163 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1165 char *string = ++input_line_pointer;
1166 int e = get_symbol_end ();
1168 if (strcmp (string, "nojumps") == 0)
1169 no_cond_jump_promotion = 1;
1170 else if (strcmp (string, "jumps") == 0)
1173 as_bad (_("no such architecture modifier: `%s'"), string);
1175 *input_line_pointer = e;
1178 demand_empty_rest_of_line ();
1184 if (!strcmp (default_arch, "x86_64"))
1185 return bfd_mach_x86_64;
1186 else if (!strcmp (default_arch, "i386"))
1187 return bfd_mach_i386_i386;
1189 as_fatal (_("Unknown architecture"));
1195 const char *hash_err;
1197 /* Initialize op_hash hash table. */
1198 op_hash = hash_new ();
1201 const template *optab;
1202 templates *core_optab;
1204 /* Setup for loop. */
1206 core_optab = (templates *) xmalloc (sizeof (templates));
1207 core_optab->start = optab;
1212 if (optab->name == NULL
1213 || strcmp (optab->name, (optab - 1)->name) != 0)
1215 /* different name --> ship out current template list;
1216 add to hash table; & begin anew. */
1217 core_optab->end = optab;
1218 hash_err = hash_insert (op_hash,
1223 as_fatal (_("Internal Error: Can't hash %s: %s"),
1227 if (optab->name == NULL)
1229 core_optab = (templates *) xmalloc (sizeof (templates));
1230 core_optab->start = optab;
1235 /* Initialize reg_hash hash table. */
1236 reg_hash = hash_new ();
1238 const reg_entry *regtab;
1240 for (regtab = i386_regtab;
1241 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1257 for (c = 0; c < 256; c++)
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1266 else if (ISLOWER (c))
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1272 else if (ISUPPER (c))
1274 mnemonic_chars[c] = TOLOWER (c);
1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1279 if (ISALPHA (c) || ISDIGIT (c))
1280 identifier_chars[c] = c;
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1289 identifier_chars['@'] = '@';
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
1295 digit_chars['-'] = '-';
1296 mnemonic_chars['-'] = '-';
1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1313 if (flag_code == CODE_64BIT)
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1326 i386_print_statistics (FILE *file)
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1334 /* Debugging routines for md_assemble. */
1335 static void pte (template *);
1336 static void pt (unsigned int);
1337 static void pe (expressionS *);
1338 static void ps (symbolS *);
1341 pi (char *line, i386_insn *x)
1345 fprintf (stdout, "%s: template ", line);
1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1352 x->rm.mode, x->rm.reg, x->rm.regmem);
1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1356 (x->rex & REX_MODE64) != 0,
1357 (x->rex & REX_EXTX) != 0,
1358 (x->rex & REX_EXTY) != 0,
1359 (x->rex & REX_EXTZ) != 0);
1360 for (i = 0; i < x->operands; i++)
1362 fprintf (stdout, " #%d: ", i + 1);
1364 fprintf (stdout, "\n");
1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1368 if (x->types[i] & Imm)
1370 if (x->types[i] & Disp)
1371 pe (x->op[i].disps);
1379 fprintf (stdout, " %d operands ", t->operands);
1380 fprintf (stdout, "opcode %x ", t->base_opcode);
1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1399 fprintf (stdout, " operation %d\n", e->X_op);
1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
1402 if (e->X_add_symbol)
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1419 fprintf (stdout, "%s type %s%s",
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1425 static struct type_name
1430 const type_names[] =
1443 { BaseIndex, "BaseIndex" },
1447 { Disp32S, "d32s" },
1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1459 { JumpAbsolute, "Jump Absolute" },
1470 const struct type_name *ty;
1472 for (ty = type_names; ty->mask; ty++)
1474 fprintf (stdout, "%s, ", ty->tname);
1478 #endif /* DEBUG386 */
1480 static bfd_reloc_code_real_type
1481 reloc (unsigned int size,
1484 bfd_reloc_code_real_type other)
1486 if (other != NO_RELOC)
1488 reloc_howto_type *reloc;
1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
1532 as_bad (_("relocated field and relocation type differ in signedness"));
1541 as_bad (_("there are no unsigned pc-relative relocations"));
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
1547 case 8: return BFD_RELOC_64_PCREL;
1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1556 case 4: return BFD_RELOC_X86_64_32S;
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
1571 return BFD_RELOC_NONE;
1574 /* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1580 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
1582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1599 /* adjust_reloc_syms doesn't know about the GOT. */
1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1634 intel_float_operand (const char *mnemonic)
1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1643 switch (mnemonic[1])
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1649 return 2 /* integer op */;
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1667 switch (mnemonic[3])
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1686 /* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1695 char mnemonic[MAX_MNEM_SIZE];
1697 /* Initialize globals. */
1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1700 i.reloc[j] = NO_RELOC;
1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
1703 save_stack_p = save_stack;
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
1707 start of a (possibly prefixed) mnemonic. */
1709 line = parse_insn (line, mnemonic);
1713 line = parse_operands (line, mnemonic);
1717 /* The order of the immediates should be reversed
1718 for 2 immediates extrq and insertq instructions */
1719 if ((i.imm_operands == 2) &&
1720 ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
1723 swap_imm_operands ();
1724 /* "extrq" and insertq" are the only two instructions whose operands
1725 have to be reversed even though they have two immediate operands.
1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
1737 precedes the offset, as it does when in AT&T mode. */
1738 if (intel_syntax && i.operands > 1
1739 && (strcmp (mnemonic, "bound") != 0)
1740 && (strcmp (mnemonic, "invlpga") != 0)
1741 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1747 /* Don't optimize displacement for movabs since it only takes 64bit
1750 && (flag_code != CODE_64BIT
1751 || strcmp (mnemonic, "movabs") != 0))
1754 /* Next, we find a template that matches the given insn,
1755 making sure the overlap of the given operands types is consistent
1756 with the template operand types. */
1758 if (!match_template ())
1763 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1765 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1766 i.tm.base_opcode ^= FloatR;
1768 /* Zap movzx and movsx suffix. The suffix may have been set from
1769 "word ptr" or "byte ptr" on the source operand, but we'll use
1770 the suffix later to choose the destination register. */
1771 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1773 if (i.reg_operands < 2
1775 && (~i.tm.opcode_modifier
1782 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1788 if (i.tm.opcode_modifier & FWait)
1789 if (!add_prefix (FWAIT_OPCODE))
1792 /* Check string instruction segment overrides. */
1793 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1795 if (!check_string ())
1799 if (!process_suffix ())
1802 /* Make still unresolved immediate matches conform to size of immediate
1803 given in i.suffix. */
1804 if (!finalize_imm ())
1807 if (i.types[0] & Imm1)
1808 i.imm_operands = 0; /* kludge for shift insns. */
1809 if (i.types[0] & ImplicitRegister)
1811 if (i.types[1] & ImplicitRegister)
1813 if (i.types[2] & ImplicitRegister)
1816 if (i.tm.opcode_modifier & ImmExt)
1820 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1822 /* Streaming SIMD extensions 3 Instructions have the fixed
1823 operands with an opcode suffix which is coded in the same
1824 place as an 8-bit immediate field would be. Here we check
1825 those operands and remove them afterwards. */
1828 for (x = 0; x < i.operands; x++)
1829 if (i.op[x].regs->reg_num != x)
1830 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1831 i.op[x].regs->reg_name, x + 1, i.tm.name);
1835 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1836 opcode suffix which is coded in the same place as an 8-bit
1837 immediate field would be. Here we fake an 8-bit immediate
1838 operand from the opcode suffix stored in tm.extension_opcode. */
1840 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1842 exp = &im_expressions[i.imm_operands++];
1843 i.op[i.operands].imms = exp;
1844 i.types[i.operands++] = Imm8;
1845 exp->X_op = O_constant;
1846 exp->X_add_number = i.tm.extension_opcode;
1847 i.tm.extension_opcode = None;
1850 /* For insns with operands there are more diddles to do to the opcode. */
1853 if (!process_operands ())
1856 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1858 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1859 as_warn (_("translating to `%sp'"), i.tm.name);
1862 /* Handle conversion of 'int $3' --> special int3 insn. */
1863 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1865 i.tm.base_opcode = INT3_OPCODE;
1869 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1870 && i.op[0].disps->X_op == O_constant)
1872 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1873 the absolute address given by the constant. Since ix86 jumps and
1874 calls are pc relative, we need to generate a reloc. */
1875 i.op[0].disps->X_add_symbol = &abs_symbol;
1876 i.op[0].disps->X_op = O_symbol;
1879 if ((i.tm.opcode_modifier & Rex64) != 0)
1880 i.rex |= REX_MODE64;
1882 /* For 8 bit registers we need an empty rex prefix. Also if the
1883 instruction already has a prefix, we need to convert old
1884 registers to new ones. */
1886 if (((i.types[0] & Reg8) != 0
1887 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1888 || ((i.types[1] & Reg8) != 0
1889 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1890 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1895 i.rex |= REX_OPCODE;
1896 for (x = 0; x < 2; x++)
1898 /* Look for 8 bit operand that uses old registers. */
1899 if ((i.types[x] & Reg8) != 0
1900 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1902 /* In case it is "hi" register, give up. */
1903 if (i.op[x].regs->reg_num > 3)
1904 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1905 i.op[x].regs->reg_name);
1907 /* Otherwise it is equivalent to the extended register.
1908 Since the encoding doesn't change this is merely
1909 cosmetic cleanup for debug output. */
1911 i.op[x].regs = i.op[x].regs + 8;
1917 add_prefix (REX_OPCODE | i.rex);
1919 /* We are ready to output the insn. */
1924 parse_insn (char *line, char *mnemonic)
1927 char *token_start = l;
1932 /* Non-zero if we found a prefix only acceptable with string insns. */
1933 const char *expecting_string_instruction = NULL;
1938 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1941 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1943 as_bad (_("no such instruction: `%s'"), token_start);
1948 if (!is_space_char (*l)
1949 && *l != END_OF_INSN
1951 || (*l != PREFIX_SEPARATOR
1954 as_bad (_("invalid character %s in mnemonic"),
1955 output_invalid (*l));
1958 if (token_start == l)
1960 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1961 as_bad (_("expecting prefix; got nothing"));
1963 as_bad (_("expecting mnemonic; got nothing"));
1967 /* Look up instruction (or prefix) via hash table. */
1968 current_templates = hash_find (op_hash, mnemonic);
1970 if (*l != END_OF_INSN
1971 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1972 && current_templates
1973 && (current_templates->start->opcode_modifier & IsPrefix))
1975 if (current_templates->start->cpu_flags
1976 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1978 as_bad ((flag_code != CODE_64BIT
1979 ? _("`%s' is only supported in 64-bit mode")
1980 : _("`%s' is not supported in 64-bit mode")),
1981 current_templates->start->name);
1984 /* If we are in 16-bit mode, do not allow addr16 or data16.
1985 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1986 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1987 && flag_code != CODE_64BIT
1988 && (((current_templates->start->opcode_modifier & Size32) != 0)
1989 ^ (flag_code == CODE_16BIT)))
1991 as_bad (_("redundant %s prefix"),
1992 current_templates->start->name);
1995 /* Add prefix, checking for repeated prefixes. */
1996 switch (add_prefix (current_templates->start->base_opcode))
2001 expecting_string_instruction = current_templates->start->name;
2004 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2011 if (!current_templates)
2013 /* See if we can get a match by trimming off a suffix. */
2016 case WORD_MNEM_SUFFIX:
2017 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2018 i.suffix = SHORT_MNEM_SUFFIX;
2020 case BYTE_MNEM_SUFFIX:
2021 case QWORD_MNEM_SUFFIX:
2022 i.suffix = mnem_p[-1];
2024 current_templates = hash_find (op_hash, mnemonic);
2026 case SHORT_MNEM_SUFFIX:
2027 case LONG_MNEM_SUFFIX:
2030 i.suffix = mnem_p[-1];
2032 current_templates = hash_find (op_hash, mnemonic);
2040 if (intel_float_operand (mnemonic) == 1)
2041 i.suffix = SHORT_MNEM_SUFFIX;
2043 i.suffix = LONG_MNEM_SUFFIX;
2045 current_templates = hash_find (op_hash, mnemonic);
2049 if (!current_templates)
2051 as_bad (_("no such instruction: `%s'"), token_start);
2056 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2058 /* Check for a branch hint. We allow ",pt" and ",pn" for
2059 predict taken and predict not taken respectively.
2060 I'm not sure that branch hints actually do anything on loop
2061 and jcxz insns (JumpByte) for current Pentium4 chips. They
2062 may work in the future and it doesn't hurt to accept them
2064 if (l[0] == ',' && l[1] == 'p')
2068 if (!add_prefix (DS_PREFIX_OPCODE))
2072 else if (l[2] == 'n')
2074 if (!add_prefix (CS_PREFIX_OPCODE))
2080 /* Any other comma loses. */
2083 as_bad (_("invalid character %s in mnemonic"),
2084 output_invalid (*l));
2088 /* Check if instruction is supported on specified architecture. */
2090 for (t = current_templates->start; t < current_templates->end; ++t)
2092 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2093 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2095 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2098 if (!(supported & 2))
2100 as_bad (flag_code == CODE_64BIT
2101 ? _("`%s' is not supported in 64-bit mode")
2102 : _("`%s' is only supported in 64-bit mode"),
2103 current_templates->start->name);
2106 if (!(supported & 1))
2108 as_warn (_("`%s' is not supported on `%s%s'"),
2109 current_templates->start->name,
2111 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2113 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2115 as_warn (_("use .code16 to ensure correct addressing mode"));
2118 /* Check for rep/repne without a string instruction. */
2119 if (expecting_string_instruction)
2121 static templates override;
2123 for (t = current_templates->start; t < current_templates->end; ++t)
2124 if (t->opcode_modifier & IsString)
2126 if (t >= current_templates->end)
2128 as_bad (_("expecting string instruction after `%s'"),
2129 expecting_string_instruction);
2132 for (override.start = t; t < current_templates->end; ++t)
2133 if (!(t->opcode_modifier & IsString))
2136 current_templates = &override;
2143 parse_operands (char *l, const char *mnemonic)
2147 /* 1 if operand is pending after ','. */
2148 unsigned int expecting_operand = 0;
2150 /* Non-zero if operand parens not balanced. */
2151 unsigned int paren_not_balanced;
2153 while (*l != END_OF_INSN)
2155 /* Skip optional white space before operand. */
2156 if (is_space_char (*l))
2158 if (!is_operand_char (*l) && *l != END_OF_INSN)
2160 as_bad (_("invalid character %s before operand %d"),
2161 output_invalid (*l),
2165 token_start = l; /* after white space */
2166 paren_not_balanced = 0;
2167 while (paren_not_balanced || *l != ',')
2169 if (*l == END_OF_INSN)
2171 if (paren_not_balanced)
2174 as_bad (_("unbalanced parenthesis in operand %d."),
2177 as_bad (_("unbalanced brackets in operand %d."),
2182 break; /* we are done */
2184 else if (!is_operand_char (*l) && !is_space_char (*l))
2186 as_bad (_("invalid character %s in operand %d"),
2187 output_invalid (*l),
2194 ++paren_not_balanced;
2196 --paren_not_balanced;
2201 ++paren_not_balanced;
2203 --paren_not_balanced;
2207 if (l != token_start)
2208 { /* Yes, we've read in another operand. */
2209 unsigned int operand_ok;
2210 this_operand = i.operands++;
2211 if (i.operands > MAX_OPERANDS)
2213 as_bad (_("spurious operands; (%d operands/instruction max)"),
2217 /* Now parse operand adding info to 'i' as we go along. */
2218 END_STRING_AND_SAVE (l);
2222 i386_intel_operand (token_start,
2223 intel_float_operand (mnemonic));
2225 operand_ok = i386_operand (token_start);
2227 RESTORE_END_STRING (l);
2233 if (expecting_operand)
2235 expecting_operand_after_comma:
2236 as_bad (_("expecting operand after ','; got nothing"));
2241 as_bad (_("expecting operand before ','; got nothing"));
2246 /* Now *l must be either ',' or END_OF_INSN. */
2249 if (*++l == END_OF_INSN)
2251 /* Just skip it, if it's \n complain. */
2252 goto expecting_operand_after_comma;
2254 expecting_operand = 1;
2261 swap_imm_operands (void)
2263 union i386_op temp_op;
2264 unsigned int temp_type;
2265 enum bfd_reloc_code_real temp_reloc;
2269 temp_type = i.types[xchg2];
2270 i.types[xchg2] = i.types[xchg1];
2271 i.types[xchg1] = temp_type;
2272 temp_op = i.op[xchg2];
2273 i.op[xchg2] = i.op[xchg1];
2274 i.op[xchg1] = temp_op;
2275 temp_reloc = i.reloc[xchg2];
2276 i.reloc[xchg2] = i.reloc[xchg1];
2277 i.reloc[xchg1] = temp_reloc;
2282 swap_operands (void)
2284 union i386_op temp_op;
2285 unsigned int temp_type;
2286 enum bfd_reloc_code_real temp_reloc;
2293 xchg2 = i.operands - 2;
2294 temp_type = i.types[xchg2];
2295 i.types[xchg2] = i.types[xchg1];
2296 i.types[xchg1] = temp_type;
2297 temp_op = i.op[xchg2];
2298 i.op[xchg2] = i.op[xchg1];
2299 i.op[xchg1] = temp_op;
2300 temp_reloc = i.reloc[xchg2];
2301 i.reloc[xchg2] = i.reloc[xchg1];
2302 i.reloc[xchg1] = temp_reloc;
2306 xchg2 = i.operands - 1;
2307 temp_type = i.types[xchg2];
2308 i.types[xchg2] = i.types[xchg1];
2309 i.types[xchg1] = temp_type;
2310 temp_op = i.op[xchg2];
2311 i.op[xchg2] = i.op[xchg1];
2312 i.op[xchg1] = temp_op;
2313 temp_reloc = i.reloc[xchg2];
2314 i.reloc[xchg2] = i.reloc[xchg1];
2315 i.reloc[xchg1] = temp_reloc;
2321 if (i.mem_operands == 2)
2323 const seg_entry *temp_seg;
2324 temp_seg = i.seg[0];
2325 i.seg[0] = i.seg[1];
2326 i.seg[1] = temp_seg;
2330 /* Try to ensure constant immediates are represented in the smallest
2335 char guess_suffix = 0;
2339 guess_suffix = i.suffix;
2340 else if (i.reg_operands)
2342 /* Figure out a suffix from the last register operand specified.
2343 We can't do this properly yet, ie. excluding InOutPortReg,
2344 but the following works for instructions with immediates.
2345 In any case, we can't set i.suffix yet. */
2346 for (op = i.operands; --op >= 0;)
2347 if (i.types[op] & Reg)
2349 if (i.types[op] & Reg8)
2350 guess_suffix = BYTE_MNEM_SUFFIX;
2351 else if (i.types[op] & Reg16)
2352 guess_suffix = WORD_MNEM_SUFFIX;
2353 else if (i.types[op] & Reg32)
2354 guess_suffix = LONG_MNEM_SUFFIX;
2355 else if (i.types[op] & Reg64)
2356 guess_suffix = QWORD_MNEM_SUFFIX;
2360 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2361 guess_suffix = WORD_MNEM_SUFFIX;
2363 for (op = i.operands; --op >= 0;)
2364 if (i.types[op] & Imm)
2366 switch (i.op[op].imms->X_op)
2369 /* If a suffix is given, this operand may be shortened. */
2370 switch (guess_suffix)
2372 case LONG_MNEM_SUFFIX:
2373 i.types[op] |= Imm32 | Imm64;
2375 case WORD_MNEM_SUFFIX:
2376 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2378 case BYTE_MNEM_SUFFIX:
2379 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2383 /* If this operand is at most 16 bits, convert it
2384 to a signed 16 bit number before trying to see
2385 whether it will fit in an even smaller size.
2386 This allows a 16-bit operand such as $0xffe0 to
2387 be recognised as within Imm8S range. */
2388 if ((i.types[op] & Imm16)
2389 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2391 i.op[op].imms->X_add_number =
2392 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2394 if ((i.types[op] & Imm32)
2395 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2398 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2399 ^ ((offsetT) 1 << 31))
2400 - ((offsetT) 1 << 31));
2402 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2404 /* We must avoid matching of Imm32 templates when 64bit
2405 only immediate is available. */
2406 if (guess_suffix == QWORD_MNEM_SUFFIX)
2407 i.types[op] &= ~Imm32;
2414 /* Symbols and expressions. */
2416 /* Convert symbolic operand to proper sizes for matching, but don't
2417 prevent matching a set of insns that only supports sizes other
2418 than those matching the insn suffix. */
2420 unsigned int mask, allowed = 0;
2423 for (t = current_templates->start; t < current_templates->end; ++t)
2424 allowed |= t->operand_types[op];
2425 switch (guess_suffix)
2427 case QWORD_MNEM_SUFFIX:
2428 mask = Imm64 | Imm32S;
2430 case LONG_MNEM_SUFFIX:
2433 case WORD_MNEM_SUFFIX:
2436 case BYTE_MNEM_SUFFIX:
2444 i.types[op] &= mask;
2451 /* Try to use the smallest displacement type too. */
2453 optimize_disp (void)
2457 for (op = i.operands; --op >= 0;)
2458 if (i.types[op] & Disp)
2460 if (i.op[op].disps->X_op == O_constant)
2462 offsetT disp = i.op[op].disps->X_add_number;
2464 if ((i.types[op] & Disp16)
2465 && (disp & ~(offsetT) 0xffff) == 0)
2467 /* If this operand is at most 16 bits, convert
2468 to a signed 16 bit number and don't use 64bit
2470 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2471 i.types[op] &= ~Disp64;
2473 if ((i.types[op] & Disp32)
2474 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2476 /* If this operand is at most 32 bits, convert
2477 to a signed 32 bit number and don't use 64bit
2479 disp &= (((offsetT) 2 << 31) - 1);
2480 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2481 i.types[op] &= ~Disp64;
2483 if (!disp && (i.types[op] & BaseIndex))
2485 i.types[op] &= ~Disp;
2489 else if (flag_code == CODE_64BIT)
2491 if (fits_in_signed_long (disp))
2493 i.types[op] &= ~Disp64;
2494 i.types[op] |= Disp32S;
2496 if (fits_in_unsigned_long (disp))
2497 i.types[op] |= Disp32;
2499 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2500 && fits_in_signed_byte (disp))
2501 i.types[op] |= Disp8;
2503 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2504 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2506 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2507 i.op[op].disps, 0, i.reloc[op]);
2508 i.types[op] &= ~Disp;
2511 /* We only support 64bit displacement on constants. */
2512 i.types[op] &= ~Disp64;
2517 match_template (void)
2519 /* Points to template once we've found it. */
2521 unsigned int overlap0, overlap1, overlap2, overlap3;
2522 unsigned int found_reverse_match;
2524 unsigned int operand_types [MAX_OPERANDS];
2525 int addr_prefix_disp;
2528 #if MAX_OPERANDS != 4
2529 # error "MAX_OPERANDS must be 4."
2532 #define MATCH(overlap, given, template) \
2533 ((overlap & ~JumpAbsolute) \
2534 && (((given) & (BaseIndex | JumpAbsolute)) \
2535 == ((overlap) & (BaseIndex | JumpAbsolute))))
2537 /* If given types r0 and r1 are registers they must be of the same type
2538 unless the expected operand type register overlap is null.
2539 Note that Acc in a template matches every size of reg. */
2540 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2541 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2542 || ((g0) & Reg) == ((g1) & Reg) \
2543 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2549 found_reverse_match = 0;
2550 for (j = 0; j < MAX_OPERANDS; j++)
2551 operand_types [j] = 0;
2552 addr_prefix_disp = -1;
2553 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2555 : (i.suffix == WORD_MNEM_SUFFIX
2557 : (i.suffix == SHORT_MNEM_SUFFIX
2559 : (i.suffix == LONG_MNEM_SUFFIX
2561 : (i.suffix == QWORD_MNEM_SUFFIX
2563 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2564 ? No_xSuf : 0))))));
2566 for (t = current_templates->start; t < current_templates->end; t++)
2568 addr_prefix_disp = -1;
2570 /* Must have right number of operands. */
2571 if (i.operands != t->operands)
2574 /* Check the suffix, except for some instructions in intel mode. */
2575 if ((t->opcode_modifier & suffix_check)
2577 && (t->opcode_modifier & IgnoreSize)))
2580 for (j = 0; j < MAX_OPERANDS; j++)
2581 operand_types [j] = t->operand_types [j];
2583 /* In general, don't allow 64-bit operands in 32-bit mode. */
2584 if (i.suffix == QWORD_MNEM_SUFFIX
2585 && flag_code != CODE_64BIT
2587 ? (!(t->opcode_modifier & IgnoreSize)
2588 && !intel_float_operand (t->name))
2589 : intel_float_operand (t->name) != 2)
2590 && (!(operand_types[0] & (RegMMX | RegXMM))
2591 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2592 && (t->base_opcode != 0x0fc7
2593 || t->extension_opcode != 1 /* cmpxchg8b */))
2596 /* Do not verify operands when there are none. */
2597 else if (!t->operands)
2599 if (t->cpu_flags & ~cpu_arch_flags)
2601 /* We've found a match; break out of loop. */
2605 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2606 into Disp32/Disp16/Disp32 operand. */
2607 if (i.prefix[ADDR_PREFIX] != 0)
2609 unsigned int DispOn = 0, DispOff = 0;
2627 for (j = 0; j < MAX_OPERANDS; j++)
2629 /* There should be only one Disp operand. */
2630 if ((operand_types[j] & DispOff))
2632 addr_prefix_disp = j;
2633 operand_types[j] |= DispOn;
2634 operand_types[j] &= ~DispOff;
2640 overlap0 = i.types[0] & operand_types[0];
2641 switch (t->operands)
2644 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2650 overlap1 = i.types[1] & operand_types[1];
2651 if (!MATCH (overlap0, i.types[0], operand_types[0])
2652 || !MATCH (overlap1, i.types[1], operand_types[1])
2653 /* monitor in SSE3 is a very special case. The first
2654 register and the second register may have different
2656 || !((t->base_opcode == 0x0f01
2657 && t->extension_opcode == 0xc8)
2658 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2660 overlap1, i.types[1],
2663 /* Check if other direction is valid ... */
2664 if ((t->opcode_modifier & (D | FloatD)) == 0)
2667 /* Try reversing direction of operands. */
2668 overlap0 = i.types[0] & operand_types[1];
2669 overlap1 = i.types[1] & operand_types[0];
2670 if (!MATCH (overlap0, i.types[0], operand_types[1])
2671 || !MATCH (overlap1, i.types[1], operand_types[0])
2672 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2674 overlap1, i.types[1],
2677 /* Does not match either direction. */
2680 /* found_reverse_match holds which of D or FloatDR
2682 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2686 /* Found a forward 2 operand match here. */
2687 switch (t->operands)
2690 overlap3 = i.types[3] & operand_types[3];
2692 overlap2 = i.types[2] & operand_types[2];
2696 switch (t->operands)
2699 if (!MATCH (overlap3, i.types[3], operand_types[3])
2700 || !CONSISTENT_REGISTER_MATCH (overlap2,
2708 /* Here we make use of the fact that there are no
2709 reverse match 3 operand instructions, and all 3
2710 operand instructions only need to be checked for
2711 register consistency between operands 2 and 3. */
2712 if (!MATCH (overlap2, i.types[2], operand_types[2])
2713 || !CONSISTENT_REGISTER_MATCH (overlap1,
2723 /* Found either forward/reverse 2, 3 or 4 operand match here:
2724 slip through to break. */
2726 if (t->cpu_flags & ~cpu_arch_flags)
2728 found_reverse_match = 0;
2731 /* We've found a match; break out of loop. */
2735 if (t == current_templates->end)
2737 /* We found no match. */
2738 as_bad (_("suffix or operands invalid for `%s'"),
2739 current_templates->start->name);
2743 if (!quiet_warnings)
2746 && ((i.types[0] & JumpAbsolute)
2747 != (operand_types[0] & JumpAbsolute)))
2749 as_warn (_("indirect %s without `*'"), t->name);
2752 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2753 == (IsPrefix | IgnoreSize))
2755 /* Warn them that a data or address size prefix doesn't
2756 affect assembly of the next line of code. */
2757 as_warn (_("stand-alone `%s' prefix"), t->name);
2761 /* Copy the template we found. */
2764 if (addr_prefix_disp != -1)
2765 i.tm.operand_types[addr_prefix_disp]
2766 = operand_types[addr_prefix_disp];
2768 if (found_reverse_match)
2770 /* If we found a reverse match we must alter the opcode
2771 direction bit. found_reverse_match holds bits to change
2772 (different for int & float insns). */
2774 i.tm.base_opcode ^= found_reverse_match;
2776 i.tm.operand_types[0] = operand_types[1];
2777 i.tm.operand_types[1] = operand_types[0];
2786 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2787 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2789 if (i.seg[0] != NULL && i.seg[0] != &es)
2791 as_bad (_("`%s' operand %d must use `%%es' segment"),
2796 /* There's only ever one segment override allowed per instruction.
2797 This instruction possibly has a legal segment override on the
2798 second operand, so copy the segment to where non-string
2799 instructions store it, allowing common code. */
2800 i.seg[0] = i.seg[1];
2802 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2804 if (i.seg[1] != NULL && i.seg[1] != &es)
2806 as_bad (_("`%s' operand %d must use `%%es' segment"),
2816 process_suffix (void)
2818 /* If matched instruction specifies an explicit instruction mnemonic
2820 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2822 if (i.tm.opcode_modifier & Size16)
2823 i.suffix = WORD_MNEM_SUFFIX;
2824 else if (i.tm.opcode_modifier & Size64)
2825 i.suffix = QWORD_MNEM_SUFFIX;
2827 i.suffix = LONG_MNEM_SUFFIX;
2829 else if (i.reg_operands)
2831 /* If there's no instruction mnemonic suffix we try to invent one
2832 based on register operands. */
2835 /* We take i.suffix from the last register operand specified,
2836 Destination register type is more significant than source
2840 for (op = i.operands; --op >= 0;)
2841 if ((i.types[op] & Reg)
2842 && !(i.tm.operand_types[op] & InOutPortReg))
2844 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2845 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2846 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2851 else if (i.suffix == BYTE_MNEM_SUFFIX)
2853 if (!check_byte_reg ())
2856 else if (i.suffix == LONG_MNEM_SUFFIX)
2858 if (!check_long_reg ())
2861 else if (i.suffix == QWORD_MNEM_SUFFIX)
2863 if (!check_qword_reg ())
2866 else if (i.suffix == WORD_MNEM_SUFFIX)
2868 if (!check_word_reg ())
2871 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2872 /* Do nothing if the instruction is going to ignore the prefix. */
2877 else if ((i.tm.opcode_modifier & DefaultSize)
2879 /* exclude fldenv/frstor/fsave/fstenv */
2880 && (i.tm.opcode_modifier & No_sSuf))
2882 i.suffix = stackop_size;
2884 else if (intel_syntax
2886 && ((i.tm.operand_types[0] & JumpAbsolute)
2887 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2888 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2889 && i.tm.extension_opcode <= 3)))
2894 if (!(i.tm.opcode_modifier & No_qSuf))
2896 i.suffix = QWORD_MNEM_SUFFIX;
2900 if (!(i.tm.opcode_modifier & No_lSuf))
2901 i.suffix = LONG_MNEM_SUFFIX;
2904 if (!(i.tm.opcode_modifier & No_wSuf))
2905 i.suffix = WORD_MNEM_SUFFIX;
2914 if (i.tm.opcode_modifier & W)
2916 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2922 unsigned int suffixes = (~i.tm.opcode_modifier
2930 if ((i.tm.opcode_modifier & W)
2931 || ((suffixes & (suffixes - 1))
2932 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2934 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2940 /* Change the opcode based on the operand size given by i.suffix;
2941 We don't need to change things for byte insns. */
2943 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2945 /* It's not a byte, select word/dword operation. */
2946 if (i.tm.opcode_modifier & W)
2948 if (i.tm.opcode_modifier & ShortForm)
2949 i.tm.base_opcode |= 8;
2951 i.tm.base_opcode |= 1;
2954 /* Now select between word & dword operations via the operand
2955 size prefix, except for instructions that will ignore this
2957 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2959 /* monitor in SSE3 is a very special case. The default size
2960 of AX is the size of mode. The address size override
2961 prefix will change the size of AX. */
2962 if (i.op->regs[0].reg_type &
2963 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2964 if (!add_prefix (ADDR_PREFIX_OPCODE))
2967 else if (i.suffix != QWORD_MNEM_SUFFIX
2968 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2969 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2970 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2971 || (flag_code == CODE_64BIT
2972 && (i.tm.opcode_modifier & JumpByte))))
2974 unsigned int prefix = DATA_PREFIX_OPCODE;
2976 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2977 prefix = ADDR_PREFIX_OPCODE;
2979 if (!add_prefix (prefix))
2983 /* Set mode64 for an operand. */
2984 if (i.suffix == QWORD_MNEM_SUFFIX
2985 && flag_code == CODE_64BIT
2986 && (i.tm.opcode_modifier & NoRex64) == 0)
2988 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2991 || i.types [0] != (Acc | Reg64)
2992 || i.types [1] != (Acc | Reg64)
2993 || strcmp (i.tm.name, "xchg") != 0)
2994 i.rex |= REX_MODE64;
2997 /* Size floating point instruction. */
2998 if (i.suffix == LONG_MNEM_SUFFIX)
2999 if (i.tm.opcode_modifier & FloatMF)
3000 i.tm.base_opcode ^= 4;
3007 check_byte_reg (void)
3011 for (op = i.operands; --op >= 0;)
3013 /* If this is an eight bit register, it's OK. If it's the 16 or
3014 32 bit version of an eight bit register, we will just use the
3015 low portion, and that's OK too. */
3016 if (i.types[op] & Reg8)
3019 /* movzx and movsx should not generate this warning. */
3021 && (i.tm.base_opcode == 0xfb7
3022 || i.tm.base_opcode == 0xfb6
3023 || i.tm.base_opcode == 0x63
3024 || i.tm.base_opcode == 0xfbe
3025 || i.tm.base_opcode == 0xfbf))
3028 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3030 /* Prohibit these changes in the 64bit mode, since the
3031 lowering is more complicated. */
3032 if (flag_code == CODE_64BIT
3033 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3035 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3036 register_prefix, i.op[op].regs->reg_name,
3040 #if REGISTER_WARNINGS
3042 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3043 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3044 (i.op[op].regs + (i.types[op] & Reg16
3045 ? REGNAM_AL - REGNAM_AX
3046 : REGNAM_AL - REGNAM_EAX))->reg_name,
3047 i.op[op].regs->reg_name,
3052 /* Any other register is bad. */
3053 if (i.types[op] & (Reg | RegMMX | RegXMM
3055 | Control | Debug | Test
3056 | FloatReg | FloatAcc))
3058 as_bad (_("`%%%s' not allowed with `%s%c'"),
3059 i.op[op].regs->reg_name,
3069 check_long_reg (void)
3073 for (op = i.operands; --op >= 0;)
3074 /* Reject eight bit registers, except where the template requires
3075 them. (eg. movzb) */
3076 if ((i.types[op] & Reg8) != 0
3077 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3079 as_bad (_("`%%%s' not allowed with `%s%c'"),
3080 i.op[op].regs->reg_name,
3085 /* Warn if the e prefix on a general reg is missing. */
3086 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3087 && (i.types[op] & Reg16) != 0
3088 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3090 /* Prohibit these changes in the 64bit mode, since the
3091 lowering is more complicated. */
3092 if (flag_code == CODE_64BIT)
3094 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3095 register_prefix, i.op[op].regs->reg_name,
3099 #if REGISTER_WARNINGS
3101 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3102 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3103 i.op[op].regs->reg_name,
3107 /* Warn if the r prefix on a general reg is missing. */
3108 else if ((i.types[op] & Reg64) != 0
3109 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3111 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3112 register_prefix, i.op[op].regs->reg_name,
3120 check_qword_reg (void)
3124 for (op = i.operands; --op >= 0; )
3125 /* Reject eight bit registers, except where the template requires
3126 them. (eg. movzb) */
3127 if ((i.types[op] & Reg8) != 0
3128 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3130 as_bad (_("`%%%s' not allowed with `%s%c'"),
3131 i.op[op].regs->reg_name,
3136 /* Warn if the e prefix on a general reg is missing. */
3137 else if (((i.types[op] & Reg16) != 0
3138 || (i.types[op] & Reg32) != 0)
3139 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3141 /* Prohibit these changes in the 64bit mode, since the
3142 lowering is more complicated. */
3143 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3144 register_prefix, i.op[op].regs->reg_name,
3152 check_word_reg (void)
3155 for (op = i.operands; --op >= 0;)
3156 /* Reject eight bit registers, except where the template requires
3157 them. (eg. movzb) */
3158 if ((i.types[op] & Reg8) != 0
3159 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3161 as_bad (_("`%%%s' not allowed with `%s%c'"),
3162 i.op[op].regs->reg_name,
3167 /* Warn if the e prefix on a general reg is present. */
3168 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3169 && (i.types[op] & Reg32) != 0
3170 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3172 /* Prohibit these changes in the 64bit mode, since the
3173 lowering is more complicated. */
3174 if (flag_code == CODE_64BIT)
3176 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3177 register_prefix, i.op[op].regs->reg_name,
3182 #if REGISTER_WARNINGS
3183 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3184 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3185 i.op[op].regs->reg_name,
3195 unsigned int overlap0, overlap1, overlap2;
3197 overlap0 = i.types[0] & i.tm.operand_types[0];
3198 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3199 && overlap0 != Imm8 && overlap0 != Imm8S
3200 && overlap0 != Imm16 && overlap0 != Imm32S
3201 && overlap0 != Imm32 && overlap0 != Imm64)
3205 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3207 : (i.suffix == WORD_MNEM_SUFFIX
3209 : (i.suffix == QWORD_MNEM_SUFFIX
3213 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3214 || overlap0 == (Imm16 | Imm32)
3215 || overlap0 == (Imm16 | Imm32S))
3217 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3220 if (overlap0 != Imm8 && overlap0 != Imm8S
3221 && overlap0 != Imm16 && overlap0 != Imm32S
3222 && overlap0 != Imm32 && overlap0 != Imm64)
3224 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3228 i.types[0] = overlap0;
3230 overlap1 = i.types[1] & i.tm.operand_types[1];
3231 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3232 && overlap1 != Imm8 && overlap1 != Imm8S
3233 && overlap1 != Imm16 && overlap1 != Imm32S
3234 && overlap1 != Imm32 && overlap1 != Imm64)
3238 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3240 : (i.suffix == WORD_MNEM_SUFFIX
3242 : (i.suffix == QWORD_MNEM_SUFFIX
3246 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3247 || overlap1 == (Imm16 | Imm32)
3248 || overlap1 == (Imm16 | Imm32S))
3250 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3253 if (overlap1 != Imm8 && overlap1 != Imm8S
3254 && overlap1 != Imm16 && overlap1 != Imm32S
3255 && overlap1 != Imm32 && overlap1 != Imm64)
3257 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3261 i.types[1] = overlap1;
3263 overlap2 = i.types[2] & i.tm.operand_types[2];
3264 assert ((overlap2 & Imm) == 0);
3265 i.types[2] = overlap2;
3271 process_operands (void)
3273 /* Default segment register this instruction will use for memory
3274 accesses. 0 means unknown. This is only for optimizing out
3275 unnecessary segment overrides. */
3276 const seg_entry *default_seg = 0;
3278 /* The imul $imm, %reg instruction is converted into
3279 imul $imm, %reg, %reg, and the clr %reg instruction
3280 is converted into xor %reg, %reg. */
3281 if (i.tm.opcode_modifier & regKludge)
3283 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3284 /* Pretend we saw the extra register operand. */
3285 assert (i.reg_operands == 1
3286 && i.op[first_reg_op + 1].regs == 0);
3287 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3288 i.types[first_reg_op + 1] = i.types[first_reg_op];
3293 if (i.tm.opcode_modifier & ShortForm)
3295 /* The register or float register operand is in operand 0 or 1. */
3296 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3297 /* Register goes in low 3 bits of opcode. */
3298 i.tm.base_opcode |= i.op[op].regs->reg_num;
3299 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3301 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3303 /* Warn about some common errors, but press on regardless.
3304 The first case can be generated by gcc (<= 2.8.1). */
3305 if (i.operands == 2)
3307 /* Reversed arguments on faddp, fsubp, etc. */
3308 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3309 i.op[1].regs->reg_name,
3310 i.op[0].regs->reg_name);
3314 /* Extraneous `l' suffix on fp insn. */
3315 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3316 i.op[0].regs->reg_name);
3320 else if (i.tm.opcode_modifier & Modrm)
3322 /* The opcode is completed (modulo i.tm.extension_opcode which
3323 must be put into the modrm byte). Now, we make the modrm and
3324 index base bytes based on all the info we've collected. */
3326 default_seg = build_modrm_byte ();
3328 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3330 if (i.tm.base_opcode == POP_SEG_SHORT
3331 && i.op[0].regs->reg_num == 1)
3333 as_bad (_("you can't `pop %%cs'"));
3336 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3337 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3340 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3344 else if ((i.tm.opcode_modifier & IsString) != 0)
3346 /* For the string instructions that allow a segment override
3347 on one of their operands, the default segment is ds. */
3351 if ((i.tm.base_opcode == 0x8d /* lea */
3352 || (i.tm.cpu_flags & CpuSVME))
3353 && i.seg[0] && !quiet_warnings)
3354 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3356 /* If a segment was explicitly specified, and the specified segment
3357 is not the default, use an opcode prefix to select it. If we
3358 never figured out what the default segment is, then default_seg
3359 will be zero at this point, and the specified segment prefix will
3361 if ((i.seg[0]) && (i.seg[0] != default_seg))
3363 if (!add_prefix (i.seg[0]->seg_prefix))
3369 static const seg_entry *
3370 build_modrm_byte (void)
3372 const seg_entry *default_seg = 0;
3374 /* i.reg_operands MUST be the number of real register operands;
3375 implicit registers do not count. */
3376 if (i.reg_operands == 2)
3378 unsigned int source, dest;
3386 /* When there are 3 operands, one of them may be immediate,
3387 which may be the first or the last operand. Otherwise,
3388 the first operand must be shift count register (cl). */
3389 assert (i.imm_operands == 1
3390 || (i.imm_operands == 0
3391 && (i.types[0] & ShiftCount)));
3392 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
3395 /* When there are 4 operands, the first two must be immediate
3396 operands. The source operand will be the 3rd one. */
3397 assert (i.imm_operands == 2
3398 && (i.types[0] & Imm)
3399 && (i.types[1] & Imm));
3409 /* One of the register operands will be encoded in the i.tm.reg
3410 field, the other in the combined i.tm.mode and i.tm.regmem
3411 fields. If no form of this instruction supports a memory
3412 destination operand, then we assume the source operand may
3413 sometimes be a memory operand and so we need to store the
3414 destination in the i.rm.reg field. */
3415 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3417 i.rm.reg = i.op[dest].regs->reg_num;
3418 i.rm.regmem = i.op[source].regs->reg_num;
3419 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3421 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3426 i.rm.reg = i.op[source].regs->reg_num;
3427 i.rm.regmem = i.op[dest].regs->reg_num;
3428 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3430 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3433 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3435 if (!((i.types[0] | i.types[1]) & Control))
3437 i.rex &= ~(REX_EXTX | REX_EXTZ);
3438 add_prefix (LOCK_PREFIX_OPCODE);
3442 { /* If it's not 2 reg operands... */
3445 unsigned int fake_zero_displacement = 0;
3446 unsigned int op = ((i.types[0] & AnyMem)
3448 : (i.types[1] & AnyMem) ? 1 : 2);
3452 if (i.base_reg == 0)
3455 if (!i.disp_operands)
3456 fake_zero_displacement = 1;
3457 if (i.index_reg == 0)
3459 /* Operand is just <disp> */
3460 if (flag_code == CODE_64BIT)
3462 /* 64bit mode overwrites the 32bit absolute
3463 addressing by RIP relative addressing and
3464 absolute addressing is encoded by one of the
3465 redundant SIB forms. */
3466 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3467 i.sib.base = NO_BASE_REGISTER;
3468 i.sib.index = NO_INDEX_REGISTER;
3469 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3470 ? Disp32S : Disp32);
3472 else if ((flag_code == CODE_16BIT)
3473 ^ (i.prefix[ADDR_PREFIX] != 0))
3475 i.rm.regmem = NO_BASE_REGISTER_16;
3476 i.types[op] = Disp16;
3480 i.rm.regmem = NO_BASE_REGISTER;
3481 i.types[op] = Disp32;
3484 else /* !i.base_reg && i.index_reg */
3486 i.sib.index = i.index_reg->reg_num;
3487 i.sib.base = NO_BASE_REGISTER;
3488 i.sib.scale = i.log2_scale_factor;
3489 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3490 i.types[op] &= ~Disp;
3491 if (flag_code != CODE_64BIT)
3492 i.types[op] |= Disp32; /* Must be 32 bit */
3494 i.types[op] |= Disp32S;
3495 if ((i.index_reg->reg_flags & RegRex) != 0)
3499 /* RIP addressing for 64bit mode. */
3500 else if (i.base_reg->reg_type == BaseIndex)
3502 i.rm.regmem = NO_BASE_REGISTER;
3503 i.types[op] &= ~ Disp;
3504 i.types[op] |= Disp32S;
3505 i.flags[op] |= Operand_PCrel;
3506 if (! i.disp_operands)
3507 fake_zero_displacement = 1;
3509 else if (i.base_reg->reg_type & Reg16)
3511 switch (i.base_reg->reg_num)
3514 if (i.index_reg == 0)
3516 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3517 i.rm.regmem = i.index_reg->reg_num - 6;
3521 if (i.index_reg == 0)
3524 if ((i.types[op] & Disp) == 0)
3526 /* fake (%bp) into 0(%bp) */
3527 i.types[op] |= Disp8;
3528 fake_zero_displacement = 1;
3531 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3532 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3534 default: /* (%si) -> 4 or (%di) -> 5 */
3535 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3537 i.rm.mode = mode_from_disp_size (i.types[op]);
3539 else /* i.base_reg and 32/64 bit mode */
3541 if (flag_code == CODE_64BIT
3542 && (i.types[op] & Disp))
3543 i.types[op] = ((i.types[op] & Disp8)
3544 | (i.prefix[ADDR_PREFIX] == 0
3545 ? Disp32S : Disp32));
3547 i.rm.regmem = i.base_reg->reg_num;
3548 if ((i.base_reg->reg_flags & RegRex) != 0)
3550 i.sib.base = i.base_reg->reg_num;
3551 /* x86-64 ignores REX prefix bit here to avoid decoder
3553 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3556 if (i.disp_operands == 0)
3558 fake_zero_displacement = 1;
3559 i.types[op] |= Disp8;
3562 else if (i.base_reg->reg_num == ESP_REG_NUM)
3566 i.sib.scale = i.log2_scale_factor;
3567 if (i.index_reg == 0)
3569 /* <disp>(%esp) becomes two byte modrm with no index
3570 register. We've already stored the code for esp
3571 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3572 Any base register besides %esp will not use the
3573 extra modrm byte. */
3574 i.sib.index = NO_INDEX_REGISTER;
3575 #if !SCALE1_WHEN_NO_INDEX
3576 /* Another case where we force the second modrm byte. */
3577 if (i.log2_scale_factor)
3578 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3583 i.sib.index = i.index_reg->reg_num;
3584 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3585 if ((i.index_reg->reg_flags & RegRex) != 0)
3590 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3591 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3594 i.rm.mode = mode_from_disp_size (i.types[op]);
3597 if (fake_zero_displacement)
3599 /* Fakes a zero displacement assuming that i.types[op]
3600 holds the correct displacement size. */
3603 assert (i.op[op].disps == 0);
3604 exp = &disp_expressions[i.disp_operands++];
3605 i.op[op].disps = exp;
3606 exp->X_op = O_constant;
3607 exp->X_add_number = 0;
3608 exp->X_add_symbol = (symbolS *) 0;
3609 exp->X_op_symbol = (symbolS *) 0;
3613 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3614 (if any) based on i.tm.extension_opcode. Again, we must be
3615 careful to make sure that segment/control/debug/test/MMX
3616 registers are coded into the i.rm.reg field. */
3621 & (Reg | RegMMX | RegXMM
3623 | Control | Debug | Test))
3626 & (Reg | RegMMX | RegXMM
3628 | Control | Debug | Test))
3631 /* If there is an extension opcode to put here, the register
3632 number must be put into the regmem field. */
3633 if (i.tm.extension_opcode != None)
3635 i.rm.regmem = i.op[op].regs->reg_num;
3636 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3641 i.rm.reg = i.op[op].regs->reg_num;
3642 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3646 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3647 must set it to 3 to indicate this is a register operand
3648 in the regmem field. */
3649 if (!i.mem_operands)
3653 /* Fill in i.rm.reg field with extension opcode (if any). */
3654 if (i.tm.extension_opcode != None)
3655 i.rm.reg = i.tm.extension_opcode;
3661 output_branch (void)
3666 relax_substateT subtype;
3671 if (flag_code == CODE_16BIT)
3675 if (i.prefix[DATA_PREFIX] != 0)
3681 /* Pentium4 branch hints. */
3682 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3683 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3688 if (i.prefix[REX_PREFIX] != 0)
3694 if (i.prefixes != 0 && !intel_syntax)
3695 as_warn (_("skipping prefixes on this instruction"));
3697 /* It's always a symbol; End frag & setup for relax.
3698 Make sure there is enough room in this frag for the largest
3699 instruction we may generate in md_convert_frag. This is 2
3700 bytes for the opcode and room for the prefix and largest
3702 frag_grow (prefix + 2 + 4);
3703 /* Prefix and 1 opcode byte go in fr_fix. */
3704 p = frag_more (prefix + 1);
3705 if (i.prefix[DATA_PREFIX] != 0)
3706 *p++ = DATA_PREFIX_OPCODE;
3707 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3708 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3709 *p++ = i.prefix[SEG_PREFIX];
3710 if (i.prefix[REX_PREFIX] != 0)
3711 *p++ = i.prefix[REX_PREFIX];
3712 *p = i.tm.base_opcode;
3714 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3715 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3716 else if ((cpu_arch_flags & Cpu386) != 0)
3717 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3719 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3722 sym = i.op[0].disps->X_add_symbol;
3723 off = i.op[0].disps->X_add_number;
3725 if (i.op[0].disps->X_op != O_constant
3726 && i.op[0].disps->X_op != O_symbol)
3728 /* Handle complex expressions. */
3729 sym = make_expr_symbol (i.op[0].disps);
3733 /* 1 possible extra opcode + 4 byte displacement go in var part.
3734 Pass reloc in fr_var. */
3735 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3745 if (i.tm.opcode_modifier & JumpByte)
3747 /* This is a loop or jecxz type instruction. */
3749 if (i.prefix[ADDR_PREFIX] != 0)
3751 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3754 /* Pentium4 branch hints. */
3755 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3756 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3758 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3767 if (flag_code == CODE_16BIT)
3770 if (i.prefix[DATA_PREFIX] != 0)
3772 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3782 if (i.prefix[REX_PREFIX] != 0)
3784 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3788 if (i.prefixes != 0 && !intel_syntax)
3789 as_warn (_("skipping prefixes on this instruction"));
3791 p = frag_more (1 + size);
3792 *p++ = i.tm.base_opcode;
3794 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3795 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3797 /* All jumps handled here are signed, but don't use a signed limit
3798 check for 32 and 16 bit jumps as we want to allow wrap around at
3799 4G and 64k respectively. */
3801 fixP->fx_signed = 1;
3805 output_interseg_jump (void)
3813 if (flag_code == CODE_16BIT)
3817 if (i.prefix[DATA_PREFIX] != 0)
3823 if (i.prefix[REX_PREFIX] != 0)
3833 if (i.prefixes != 0 && !intel_syntax)
3834 as_warn (_("skipping prefixes on this instruction"));
3836 /* 1 opcode; 2 segment; offset */
3837 p = frag_more (prefix + 1 + 2 + size);
3839 if (i.prefix[DATA_PREFIX] != 0)
3840 *p++ = DATA_PREFIX_OPCODE;
3842 if (i.prefix[REX_PREFIX] != 0)
3843 *p++ = i.prefix[REX_PREFIX];
3845 *p++ = i.tm.base_opcode;
3846 if (i.op[1].imms->X_op == O_constant)
3848 offsetT n = i.op[1].imms->X_add_number;
3851 && !fits_in_unsigned_word (n)
3852 && !fits_in_signed_word (n))
3854 as_bad (_("16-bit jump out of range"));
3857 md_number_to_chars (p, n, size);
3860 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3861 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3862 if (i.op[0].imms->X_op != O_constant)
3863 as_bad (_("can't handle non absolute segment in `%s'"),
3865 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3871 fragS *insn_start_frag;
3872 offsetT insn_start_off;
3874 /* Tie dwarf2 debug info to the address at the start of the insn.
3875 We can't do this after the insn has been output as the current
3876 frag may have been closed off. eg. by frag_var. */
3877 dwarf2_emit_insn (0);
3879 insn_start_frag = frag_now;
3880 insn_start_off = frag_now_fix ();
3883 if (i.tm.opcode_modifier & Jump)
3885 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3887 else if (i.tm.opcode_modifier & JumpInterSegment)
3888 output_interseg_jump ();
3891 /* Output normal instructions here. */
3894 unsigned int prefix;
3896 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3897 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3898 use one more higher byte to specify a prefix the instruction
3900 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3902 if (i.tm.base_opcode & 0xff000000)
3904 prefix = (i.tm.base_opcode >> 24) & 0xff;
3908 else if ((i.tm.base_opcode & 0xff0000) != 0)
3910 prefix = (i.tm.base_opcode >> 16) & 0xff;
3911 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3914 if (prefix != REPE_PREFIX_OPCODE
3915 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3916 add_prefix (prefix);
3919 add_prefix (prefix);
3922 /* The prefix bytes. */
3924 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3930 md_number_to_chars (p, (valueT) *q, 1);
3934 /* Now the opcode; be careful about word order here! */
3935 if (fits_in_unsigned_byte (i.tm.base_opcode))
3937 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3941 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3944 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3949 /* Put out high byte first: can't use md_number_to_chars! */
3950 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3951 *p = i.tm.base_opcode & 0xff;
3954 /* Now the modrm byte and sib byte (if present). */
3955 if (i.tm.opcode_modifier & Modrm)
3958 md_number_to_chars (p,
3959 (valueT) (i.rm.regmem << 0
3963 /* If i.rm.regmem == ESP (4)
3964 && i.rm.mode != (Register mode)
3966 ==> need second modrm byte. */
3967 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3969 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3972 md_number_to_chars (p,
3973 (valueT) (i.sib.base << 0
3975 | i.sib.scale << 6),
3980 if (i.disp_operands)
3981 output_disp (insn_start_frag, insn_start_off);
3984 output_imm (insn_start_frag, insn_start_off);
3990 pi ("" /*line*/, &i);
3992 #endif /* DEBUG386 */
3996 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
4001 for (n = 0; n < i.operands; n++)
4003 if (i.types[n] & Disp)
4005 if (i.op[n].disps->X_op == O_constant)
4011 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4014 if (i.types[n] & Disp8)
4016 if (i.types[n] & Disp64)
4019 val = offset_in_range (i.op[n].disps->X_add_number,
4021 p = frag_more (size);
4022 md_number_to_chars (p, val, size);
4026 enum bfd_reloc_code_real reloc_type;
4029 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4031 /* The PC relative address is computed relative
4032 to the instruction boundary, so in case immediate
4033 fields follows, we need to adjust the value. */
4034 if (pcrel && i.imm_operands)
4039 for (n1 = 0; n1 < i.operands; n1++)
4040 if (i.types[n1] & Imm)
4042 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4045 if (i.types[n1] & (Imm8 | Imm8S))
4047 if (i.types[n1] & Imm64)
4052 /* We should find the immediate. */
4053 if (n1 == i.operands)
4055 i.op[n].disps->X_add_number -= imm_size;
4058 if (i.types[n] & Disp32S)
4061 if (i.types[n] & (Disp16 | Disp64))
4064 if (i.types[n] & Disp64)
4068 p = frag_more (size);
4069 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4071 && GOT_symbol == i.op[n].disps->X_add_symbol
4072 && (((reloc_type == BFD_RELOC_32
4073 || reloc_type == BFD_RELOC_X86_64_32S
4074 || (reloc_type == BFD_RELOC_64
4076 && (i.op[n].disps->X_op == O_symbol
4077 || (i.op[n].disps->X_op == O_add
4078 && ((symbol_get_value_expression
4079 (i.op[n].disps->X_op_symbol)->X_op)
4081 || reloc_type == BFD_RELOC_32_PCREL))
4085 if (insn_start_frag == frag_now)
4086 add = (p - frag_now->fr_literal) - insn_start_off;
4091 add = insn_start_frag->fr_fix - insn_start_off;
4092 for (fr = insn_start_frag->fr_next;
4093 fr && fr != frag_now; fr = fr->fr_next)
4095 add += p - frag_now->fr_literal;
4100 reloc_type = BFD_RELOC_386_GOTPC;
4101 i.op[n].imms->X_add_number += add;
4103 else if (reloc_type == BFD_RELOC_64)
4104 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4106 /* Don't do the adjustment for x86-64, as there
4107 the pcrel addressing is relative to the _next_
4108 insn, and that is taken care of in other code. */
4109 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4111 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4112 i.op[n].disps, pcrel, reloc_type);
4119 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4124 for (n = 0; n < i.operands; n++)
4126 if (i.types[n] & Imm)
4128 if (i.op[n].imms->X_op == O_constant)
4134 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4137 if (i.types[n] & (Imm8 | Imm8S))
4139 else if (i.types[n] & Imm64)
4142 val = offset_in_range (i.op[n].imms->X_add_number,
4144 p = frag_more (size);
4145 md_number_to_chars (p, val, size);
4149 /* Not absolute_section.
4150 Need a 32-bit fixup (don't support 8bit
4151 non-absolute imms). Try to support other
4153 enum bfd_reloc_code_real reloc_type;
4157 if ((i.types[n] & (Imm32S))
4158 && (i.suffix == QWORD_MNEM_SUFFIX
4159 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4161 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4164 if (i.types[n] & (Imm8 | Imm8S))
4166 if (i.types[n] & Imm64)
4170 p = frag_more (size);
4171 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4173 /* This is tough to explain. We end up with this one if we
4174 * have operands that look like
4175 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4176 * obtain the absolute address of the GOT, and it is strongly
4177 * preferable from a performance point of view to avoid using
4178 * a runtime relocation for this. The actual sequence of
4179 * instructions often look something like:
4184 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4186 * The call and pop essentially return the absolute address
4187 * of the label .L66 and store it in %ebx. The linker itself
4188 * will ultimately change the first operand of the addl so
4189 * that %ebx points to the GOT, but to keep things simple, the
4190 * .o file must have this operand set so that it generates not
4191 * the absolute address of .L66, but the absolute address of
4192 * itself. This allows the linker itself simply treat a GOTPC
4193 * relocation as asking for a pcrel offset to the GOT to be
4194 * added in, and the addend of the relocation is stored in the
4195 * operand field for the instruction itself.
4197 * Our job here is to fix the operand so that it would add
4198 * the correct offset so that %ebx would point to itself. The
4199 * thing that is tricky is that .-.L66 will point to the
4200 * beginning of the instruction, so we need to further modify
4201 * the operand so that it will point to itself. There are
4202 * other cases where you have something like:
4204 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4206 * and here no correction would be required. Internally in
4207 * the assembler we treat operands of this form as not being
4208 * pcrel since the '.' is explicitly mentioned, and I wonder
4209 * whether it would simplify matters to do it this way. Who
4210 * knows. In earlier versions of the PIC patches, the
4211 * pcrel_adjust field was used to store the correction, but
4212 * since the expression is not pcrel, I felt it would be
4213 * confusing to do it this way. */
4215 if ((reloc_type == BFD_RELOC_32
4216 || reloc_type == BFD_RELOC_X86_64_32S
4217 || reloc_type == BFD_RELOC_64)
4219 && GOT_symbol == i.op[n].imms->X_add_symbol
4220 && (i.op[n].imms->X_op == O_symbol
4221 || (i.op[n].imms->X_op == O_add
4222 && ((symbol_get_value_expression
4223 (i.op[n].imms->X_op_symbol)->X_op)
4228 if (insn_start_frag == frag_now)
4229 add = (p - frag_now->fr_literal) - insn_start_off;
4234 add = insn_start_frag->fr_fix - insn_start_off;
4235 for (fr = insn_start_frag->fr_next;
4236 fr && fr != frag_now; fr = fr->fr_next)
4238 add += p - frag_now->fr_literal;
4242 reloc_type = BFD_RELOC_386_GOTPC;
4244 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4246 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4247 i.op[n].imms->X_add_number += add;
4249 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4250 i.op[n].imms, 0, reloc_type);
4256 /* x86_cons_fix_new is called via the expression parsing code when a
4257 reloc is needed. We use this hook to get the correct .got reloc. */
4258 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4259 static int cons_sign = -1;
4262 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
4265 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4267 got_reloc = NO_RELOC;
4270 if (exp->X_op == O_secrel)
4272 exp->X_op = O_symbol;
4273 r = BFD_RELOC_32_SECREL;
4277 fix_new_exp (frag, off, len, exp, 0, r);
4280 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4281 # define lex_got(reloc, adjust, types) NULL
4283 /* Parse operands of the form
4284 <symbol>@GOTOFF+<nnn>
4285 and similar .plt or .got references.
4287 If we find one, set up the correct relocation in RELOC and copy the
4288 input string, minus the `@GOTOFF' into a malloc'd buffer for
4289 parsing by the calling routine. Return this buffer, and if ADJUST
4290 is non-null set it to the length of the string we removed from the
4291 input line. Otherwise return NULL. */
4293 lex_got (enum bfd_reloc_code_real *reloc,
4295 unsigned int *types)
4297 /* Some of the relocations depend on the size of what field is to
4298 be relocated. But in our callers i386_immediate and i386_displacement
4299 we don't yet know the operand size (this will be set by insn
4300 matching). Hence we record the word32 relocation here,
4301 and adjust the reloc according to the real size in reloc(). */
4302 static const struct {
4304 const enum bfd_reloc_code_real rel[2];
4305 const unsigned int types64;
4307 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4308 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4309 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4310 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4311 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4312 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4313 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4314 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4315 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4316 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4317 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4318 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4319 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4320 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4321 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4322 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4323 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4331 for (cp = input_line_pointer; *cp != '@'; cp++)
4332 if (is_end_of_line[(unsigned char) *cp])
4335 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4339 len = strlen (gotrel[j].str);
4340 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4342 if (gotrel[j].rel[object_64bit] != 0)
4345 char *tmpbuf, *past_reloc;
4347 *reloc = gotrel[j].rel[object_64bit];
4353 if (flag_code != CODE_64BIT)
4354 *types = Imm32|Disp32;
4356 *types = gotrel[j].types64;
4359 if (GOT_symbol == NULL)
4360 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4362 /* Replace the relocation token with ' ', so that
4363 errors like foo@GOTOFF1 will be detected. */
4365 /* The length of the first part of our input line. */
4366 first = cp - input_line_pointer;
4368 /* The second part goes from after the reloc token until
4369 (and including) an end_of_line char. Don't use strlen
4370 here as the end_of_line char may not be a NUL. */
4371 past_reloc = cp + 1 + len;
4372 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4374 second = cp - past_reloc;
4376 /* Allocate and copy string. The trailing NUL shouldn't
4377 be necessary, but be safe. */
4378 tmpbuf = xmalloc (first + second + 2);
4379 memcpy (tmpbuf, input_line_pointer, first);
4380 tmpbuf[first] = ' ';
4381 memcpy (tmpbuf + first + 1, past_reloc, second);
4382 tmpbuf[first + second + 1] = '\0';
4386 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4387 gotrel[j].str, 1 << (5 + object_64bit));
4392 /* Might be a symbol version string. Don't as_bad here. */
4397 x86_cons (expressionS *exp, int size)
4399 if (size == 4 || (object_64bit && size == 8))
4401 /* Handle @GOTOFF and the like in an expression. */
4403 char *gotfree_input_line;
4406 save = input_line_pointer;
4407 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4408 if (gotfree_input_line)
4409 input_line_pointer = gotfree_input_line;
4413 if (gotfree_input_line)
4415 /* expression () has merrily parsed up to the end of line,
4416 or a comma - in the wrong buffer. Transfer how far
4417 input_line_pointer has moved to the right buffer. */
4418 input_line_pointer = (save
4419 + (input_line_pointer - gotfree_input_line)
4421 free (gotfree_input_line);
4429 static void signed_cons (int size)
4431 if (flag_code == CODE_64BIT)
4439 pe_directive_secrel (dummy)
4440 int dummy ATTRIBUTE_UNUSED;
4447 if (exp.X_op == O_symbol)
4448 exp.X_op = O_secrel;
4450 emit_expr (&exp, 4);
4452 while (*input_line_pointer++ == ',');
4454 input_line_pointer--;
4455 demand_empty_rest_of_line ();
4460 i386_immediate (char *imm_start)
4462 char *save_input_line_pointer;
4463 char *gotfree_input_line;
4466 unsigned int types = ~0U;
4468 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4470 as_bad (_("at most %d immediate operands are allowed"),
4471 MAX_IMMEDIATE_OPERANDS);
4475 exp = &im_expressions[i.imm_operands++];
4476 i.op[this_operand].imms = exp;
4478 if (is_space_char (*imm_start))
4481 save_input_line_pointer = input_line_pointer;
4482 input_line_pointer = imm_start;
4484 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4485 if (gotfree_input_line)
4486 input_line_pointer = gotfree_input_line;
4488 exp_seg = expression (exp);
4491 if (*input_line_pointer)
4492 as_bad (_("junk `%s' after expression"), input_line_pointer);
4494 input_line_pointer = save_input_line_pointer;
4495 if (gotfree_input_line)
4496 free (gotfree_input_line);
4498 if (exp->X_op == O_absent || exp->X_op == O_big)
4500 /* Missing or bad expr becomes absolute 0. */
4501 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4503 exp->X_op = O_constant;
4504 exp->X_add_number = 0;
4505 exp->X_add_symbol = (symbolS *) 0;
4506 exp->X_op_symbol = (symbolS *) 0;
4508 else if (exp->X_op == O_constant)
4510 /* Size it properly later. */
4511 i.types[this_operand] |= Imm64;
4512 /* If BFD64, sign extend val. */
4513 if (!use_rela_relocations)
4514 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4515 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4517 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4518 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4519 && exp_seg != absolute_section
4520 && exp_seg != text_section
4521 && exp_seg != data_section
4522 && exp_seg != bss_section
4523 && exp_seg != undefined_section
4524 && !bfd_is_com_section (exp_seg))
4526 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4530 else if (!intel_syntax && exp->X_op == O_register)
4532 as_bad (_("illegal immediate register operand %s"), imm_start);
4537 /* This is an address. The size of the address will be
4538 determined later, depending on destination register,
4539 suffix, or the default for the section. */
4540 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4541 i.types[this_operand] &= types;
4548 i386_scale (char *scale)
4551 char *save = input_line_pointer;
4553 input_line_pointer = scale;
4554 val = get_absolute_expression ();
4559 i.log2_scale_factor = 0;
4562 i.log2_scale_factor = 1;
4565 i.log2_scale_factor = 2;
4568 i.log2_scale_factor = 3;
4572 char sep = *input_line_pointer;
4574 *input_line_pointer = '\0';
4575 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4577 *input_line_pointer = sep;
4578 input_line_pointer = save;
4582 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4584 as_warn (_("scale factor of %d without an index register"),
4585 1 << i.log2_scale_factor);
4586 #if SCALE1_WHEN_NO_INDEX
4587 i.log2_scale_factor = 0;
4590 scale = input_line_pointer;
4591 input_line_pointer = save;
4596 i386_displacement (char *disp_start, char *disp_end)
4600 char *save_input_line_pointer;
4601 char *gotfree_input_line;
4602 int bigdisp, override;
4603 unsigned int types = Disp;
4605 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4607 as_bad (_("at most %d displacement operands are allowed"),
4608 MAX_MEMORY_OPERANDS);
4612 if ((i.types[this_operand] & JumpAbsolute)
4613 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4616 override = (i.prefix[ADDR_PREFIX] != 0);
4620 /* For PC-relative branches, the width of the displacement
4621 is dependent upon data size, not address size. */
4623 override = (i.prefix[DATA_PREFIX] != 0);
4625 if (flag_code == CODE_64BIT)
4628 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4630 : Disp32S | Disp32);
4632 bigdisp = Disp64 | Disp32S | Disp32;
4639 override = (i.suffix == (flag_code != CODE_16BIT
4641 : LONG_MNEM_SUFFIX));
4644 if ((flag_code == CODE_16BIT) ^ override)
4647 i.types[this_operand] |= bigdisp;
4649 exp = &disp_expressions[i.disp_operands];
4650 i.op[this_operand].disps = exp;
4652 save_input_line_pointer = input_line_pointer;
4653 input_line_pointer = disp_start;
4654 END_STRING_AND_SAVE (disp_end);
4656 #ifndef GCC_ASM_O_HACK
4657 #define GCC_ASM_O_HACK 0
4660 END_STRING_AND_SAVE (disp_end + 1);
4661 if ((i.types[this_operand] & BaseIndex) != 0
4662 && displacement_string_end[-1] == '+')
4664 /* This hack is to avoid a warning when using the "o"
4665 constraint within gcc asm statements.
4668 #define _set_tssldt_desc(n,addr,limit,type) \
4669 __asm__ __volatile__ ( \
4671 "movw %w1,2+%0\n\t" \
4673 "movb %b1,4+%0\n\t" \
4674 "movb %4,5+%0\n\t" \
4675 "movb $0,6+%0\n\t" \
4676 "movb %h1,7+%0\n\t" \
4678 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4680 This works great except that the output assembler ends
4681 up looking a bit weird if it turns out that there is
4682 no offset. You end up producing code that looks like:
4695 So here we provide the missing zero. */
4697 *displacement_string_end = '0';
4700 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4701 if (gotfree_input_line)
4702 input_line_pointer = gotfree_input_line;
4704 exp_seg = expression (exp);
4707 if (*input_line_pointer)
4708 as_bad (_("junk `%s' after expression"), input_line_pointer);
4710 RESTORE_END_STRING (disp_end + 1);
4712 RESTORE_END_STRING (disp_end);
4713 input_line_pointer = save_input_line_pointer;
4714 if (gotfree_input_line)
4715 free (gotfree_input_line);
4717 /* We do this to make sure that the section symbol is in
4718 the symbol table. We will ultimately change the relocation
4719 to be relative to the beginning of the section. */
4720 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4721 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4722 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4724 if (exp->X_op != O_symbol)
4726 as_bad (_("bad expression used with @%s"),
4727 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4733 if (S_IS_LOCAL (exp->X_add_symbol)
4734 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4735 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4736 exp->X_op = O_subtract;
4737 exp->X_op_symbol = GOT_symbol;
4738 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4739 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4740 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4741 i.reloc[this_operand] = BFD_RELOC_64;
4743 i.reloc[this_operand] = BFD_RELOC_32;
4746 if (exp->X_op == O_absent || exp->X_op == O_big)
4748 /* Missing or bad expr becomes absolute 0. */
4749 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4751 exp->X_op = O_constant;
4752 exp->X_add_number = 0;
4753 exp->X_add_symbol = (symbolS *) 0;
4754 exp->X_op_symbol = (symbolS *) 0;
4757 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4758 if (exp->X_op != O_constant
4759 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4760 && exp_seg != absolute_section
4761 && exp_seg != text_section
4762 && exp_seg != data_section
4763 && exp_seg != bss_section
4764 && exp_seg != undefined_section
4765 && !bfd_is_com_section (exp_seg))
4767 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4772 if (!(i.types[this_operand] & ~Disp))
4773 i.types[this_operand] &= types;
4778 /* Make sure the memory operand we've been dealt is valid.
4779 Return 1 on success, 0 on a failure. */
4782 i386_index_check (const char *operand_string)
4785 #if INFER_ADDR_PREFIX
4791 if ((current_templates->start->cpu_flags & CpuSVME)
4792 && current_templates->end[-1].operand_types[0] == AnyMem)
4794 /* Memory operands of SVME insns are special in that they only allow
4795 rAX as their memory address and ignore any segment override. */
4798 /* SKINIT is even more restrictive: it always requires EAX. */
4799 if (strcmp (current_templates->start->name, "skinit") == 0)
4801 else if (flag_code == CODE_64BIT)
4802 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4804 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4808 || !(i.base_reg->reg_type & Acc)
4809 || !(i.base_reg->reg_type & RegXX)
4811 || (i.types[0] & Disp))
4814 else if (flag_code == CODE_64BIT)
4816 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4819 && ((i.base_reg->reg_type & RegXX) == 0)
4820 && (i.base_reg->reg_type != BaseIndex
4823 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4824 != (RegXX | BaseIndex))))
4829 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4833 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4834 != (Reg16 | BaseIndex)))
4836 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4837 != (Reg16 | BaseIndex))
4839 && i.base_reg->reg_num < 6
4840 && i.index_reg->reg_num >= 6
4841 && i.log2_scale_factor == 0))))
4848 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4850 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4851 != (Reg32 | BaseIndex))))
4857 #if INFER_ADDR_PREFIX
4858 if (i.prefix[ADDR_PREFIX] == 0)
4860 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4862 /* Change the size of any displacement too. At most one of
4863 Disp16 or Disp32 is set.
4864 FIXME. There doesn't seem to be any real need for separate
4865 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4866 Removing them would probably clean up the code quite a lot. */
4867 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4868 i.types[this_operand] ^= (Disp16 | Disp32);
4873 as_bad (_("`%s' is not a valid base/index expression"),
4877 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4879 flag_code_names[flag_code]);
4884 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4888 i386_operand (char *operand_string)
4892 char *op_string = operand_string;
4894 if (is_space_char (*op_string))
4897 /* We check for an absolute prefix (differentiating,
4898 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4899 if (*op_string == ABSOLUTE_PREFIX)
4902 if (is_space_char (*op_string))
4904 i.types[this_operand] |= JumpAbsolute;
4907 /* Check if operand is a register. */
4908 if ((r = parse_register (op_string, &end_op)) != NULL)
4910 /* Check for a segment override by searching for ':' after a
4911 segment register. */
4913 if (is_space_char (*op_string))
4915 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4920 i.seg[i.mem_operands] = &es;
4923 i.seg[i.mem_operands] = &cs;
4926 i.seg[i.mem_operands] = &ss;
4929 i.seg[i.mem_operands] = &ds;
4932 i.seg[i.mem_operands] = &fs;
4935 i.seg[i.mem_operands] = &gs;
4939 /* Skip the ':' and whitespace. */
4941 if (is_space_char (*op_string))
4944 if (!is_digit_char (*op_string)
4945 && !is_identifier_char (*op_string)
4946 && *op_string != '('
4947 && *op_string != ABSOLUTE_PREFIX)
4949 as_bad (_("bad memory operand `%s'"), op_string);
4952 /* Handle case of %es:*foo. */
4953 if (*op_string == ABSOLUTE_PREFIX)
4956 if (is_space_char (*op_string))
4958 i.types[this_operand] |= JumpAbsolute;
4960 goto do_memory_reference;
4964 as_bad (_("junk `%s' after register"), op_string);
4967 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4968 i.op[this_operand].regs = r;
4971 else if (*op_string == REGISTER_PREFIX)
4973 as_bad (_("bad register name `%s'"), op_string);
4976 else if (*op_string == IMMEDIATE_PREFIX)
4979 if (i.types[this_operand] & JumpAbsolute)
4981 as_bad (_("immediate operand illegal with absolute jump"));
4984 if (!i386_immediate (op_string))
4987 else if (is_digit_char (*op_string)
4988 || is_identifier_char (*op_string)
4989 || *op_string == '(')
4991 /* This is a memory reference of some sort. */
4994 /* Start and end of displacement string expression (if found). */
4995 char *displacement_string_start;
4996 char *displacement_string_end;
4998 do_memory_reference:
4999 if ((i.mem_operands == 1
5000 && (current_templates->start->opcode_modifier & IsString) == 0)
5001 || i.mem_operands == 2)
5003 as_bad (_("too many memory references for `%s'"),
5004 current_templates->start->name);
5008 /* Check for base index form. We detect the base index form by
5009 looking for an ')' at the end of the operand, searching
5010 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5012 base_string = op_string + strlen (op_string);
5015 if (is_space_char (*base_string))
5018 /* If we only have a displacement, set-up for it to be parsed later. */
5019 displacement_string_start = op_string;
5020 displacement_string_end = base_string + 1;
5022 if (*base_string == ')')
5025 unsigned int parens_balanced = 1;
5026 /* We've already checked that the number of left & right ()'s are
5027 equal, so this loop will not be infinite. */
5031 if (*base_string == ')')
5033 if (*base_string == '(')
5036 while (parens_balanced);
5038 temp_string = base_string;
5040 /* Skip past '(' and whitespace. */
5042 if (is_space_char (*base_string))
5045 if (*base_string == ','
5046 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
5048 displacement_string_end = temp_string;
5050 i.types[this_operand] |= BaseIndex;
5054 base_string = end_op;
5055 if (is_space_char (*base_string))
5059 /* There may be an index reg or scale factor here. */
5060 if (*base_string == ',')
5063 if (is_space_char (*base_string))
5066 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5068 base_string = end_op;
5069 if (is_space_char (*base_string))
5071 if (*base_string == ',')
5074 if (is_space_char (*base_string))
5077 else if (*base_string != ')')
5079 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5084 else if (*base_string == REGISTER_PREFIX)
5086 as_bad (_("bad register name `%s'"), base_string);
5090 /* Check for scale factor. */
5091 if (*base_string != ')')
5093 char *end_scale = i386_scale (base_string);
5098 base_string = end_scale;
5099 if (is_space_char (*base_string))
5101 if (*base_string != ')')
5103 as_bad (_("expecting `)' after scale factor in `%s'"),
5108 else if (!i.index_reg)
5110 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5115 else if (*base_string != ')')
5117 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5122 else if (*base_string == REGISTER_PREFIX)
5124 as_bad (_("bad register name `%s'"), base_string);
5129 /* If there's an expression beginning the operand, parse it,
5130 assuming displacement_string_start and
5131 displacement_string_end are meaningful. */
5132 if (displacement_string_start != displacement_string_end)
5134 if (!i386_displacement (displacement_string_start,
5135 displacement_string_end))
5139 /* Special case for (%dx) while doing input/output op. */
5141 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5143 && i.log2_scale_factor == 0
5144 && i.seg[i.mem_operands] == 0
5145 && (i.types[this_operand] & Disp) == 0)
5147 i.types[this_operand] = InOutPortReg;
5151 if (i386_index_check (operand_string) == 0)
5157 /* It's not a memory operand; argh! */
5158 as_bad (_("invalid char %s beginning operand %d `%s'"),
5159 output_invalid (*op_string),
5164 return 1; /* Normal return. */
5167 /* md_estimate_size_before_relax()
5169 Called just before relax() for rs_machine_dependent frags. The x86
5170 assembler uses these frags to handle variable size jump
5173 Any symbol that is now undefined will not become defined.
5174 Return the correct fr_subtype in the frag.
5175 Return the initial "guess for variable size of frag" to caller.
5176 The guess is actually the growth beyond the fixed part. Whatever
5177 we do to grow the fixed or variable part contributes to our
5181 md_estimate_size_before_relax (fragP, segment)
5185 /* We've already got fragP->fr_subtype right; all we have to do is
5186 check for un-relaxable symbols. On an ELF system, we can't relax
5187 an externally visible symbol, because it may be overridden by a
5189 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5192 && (S_IS_EXTERNAL (fragP->fr_symbol)
5193 || S_IS_WEAK (fragP->fr_symbol)))
5197 /* Symbol is undefined in this segment, or we need to keep a
5198 reloc so that weak symbols can be overridden. */
5199 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5200 enum bfd_reloc_code_real reloc_type;
5201 unsigned char *opcode;
5204 if (fragP->fr_var != NO_RELOC)
5205 reloc_type = fragP->fr_var;
5207 reloc_type = BFD_RELOC_16_PCREL;
5209 reloc_type = BFD_RELOC_32_PCREL;
5211 old_fr_fix = fragP->fr_fix;
5212 opcode = (unsigned char *) fragP->fr_opcode;
5214 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5217 /* Make jmp (0xeb) a (d)word displacement jump. */
5219 fragP->fr_fix += size;
5220 fix_new (fragP, old_fr_fix, size,
5222 fragP->fr_offset, 1,
5228 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5230 /* Negate the condition, and branch past an
5231 unconditional jump. */
5234 /* Insert an unconditional jump. */
5236 /* We added two extra opcode bytes, and have a two byte
5238 fragP->fr_fix += 2 + 2;
5239 fix_new (fragP, old_fr_fix + 2, 2,
5241 fragP->fr_offset, 1,
5248 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5253 fixP = fix_new (fragP, old_fr_fix, 1,
5255 fragP->fr_offset, 1,
5257 fixP->fx_signed = 1;
5261 /* This changes the byte-displacement jump 0x7N
5262 to the (d)word-displacement jump 0x0f,0x8N. */
5263 opcode[1] = opcode[0] + 0x10;
5264 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5265 /* We've added an opcode byte. */
5266 fragP->fr_fix += 1 + size;
5267 fix_new (fragP, old_fr_fix + 1, size,
5269 fragP->fr_offset, 1,
5274 BAD_CASE (fragP->fr_subtype);
5278 return fragP->fr_fix - old_fr_fix;
5281 /* Guess size depending on current relax state. Initially the relax
5282 state will correspond to a short jump and we return 1, because
5283 the variable part of the frag (the branch offset) is one byte
5284 long. However, we can relax a section more than once and in that
5285 case we must either set fr_subtype back to the unrelaxed state,
5286 or return the value for the appropriate branch. */
5287 return md_relax_table[fragP->fr_subtype].rlx_length;
5290 /* Called after relax() is finished.
5292 In: Address of frag.
5293 fr_type == rs_machine_dependent.
5294 fr_subtype is what the address relaxed to.
5296 Out: Any fixSs and constants are set up.
5297 Caller will turn frag into a ".space 0". */
5300 md_convert_frag (abfd, sec, fragP)
5301 bfd *abfd ATTRIBUTE_UNUSED;
5302 segT sec ATTRIBUTE_UNUSED;
5305 unsigned char *opcode;
5306 unsigned char *where_to_put_displacement = NULL;
5307 offsetT target_address;
5308 offsetT opcode_address;
5309 unsigned int extension = 0;
5310 offsetT displacement_from_opcode_start;
5312 opcode = (unsigned char *) fragP->fr_opcode;
5314 /* Address we want to reach in file space. */
5315 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5317 /* Address opcode resides at in file space. */
5318 opcode_address = fragP->fr_address + fragP->fr_fix;
5320 /* Displacement from opcode start to fill into instruction. */
5321 displacement_from_opcode_start = target_address - opcode_address;
5323 if ((fragP->fr_subtype & BIG) == 0)
5325 /* Don't have to change opcode. */
5326 extension = 1; /* 1 opcode + 1 displacement */
5327 where_to_put_displacement = &opcode[1];
5331 if (no_cond_jump_promotion
5332 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5333 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5335 switch (fragP->fr_subtype)
5337 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5338 extension = 4; /* 1 opcode + 4 displacement */
5340 where_to_put_displacement = &opcode[1];
5343 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5344 extension = 2; /* 1 opcode + 2 displacement */
5346 where_to_put_displacement = &opcode[1];
5349 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5350 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5351 extension = 5; /* 2 opcode + 4 displacement */
5352 opcode[1] = opcode[0] + 0x10;
5353 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5354 where_to_put_displacement = &opcode[2];
5357 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5358 extension = 3; /* 2 opcode + 2 displacement */
5359 opcode[1] = opcode[0] + 0x10;
5360 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5361 where_to_put_displacement = &opcode[2];
5364 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5369 where_to_put_displacement = &opcode[3];
5373 BAD_CASE (fragP->fr_subtype);
5378 /* If size if less then four we are sure that the operand fits,
5379 but if it's 4, then it could be that the displacement is larger
5381 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5383 && ((addressT) (displacement_from_opcode_start - extension
5384 + ((addressT) 1 << 31))
5385 > (((addressT) 2 << 31) - 1)))
5387 as_bad_where (fragP->fr_file, fragP->fr_line,
5388 _("jump target out of range"));
5389 /* Make us emit 0. */
5390 displacement_from_opcode_start = extension;
5392 /* Now put displacement after opcode. */
5393 md_number_to_chars ((char *) where_to_put_displacement,
5394 (valueT) (displacement_from_opcode_start - extension),
5395 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5396 fragP->fr_fix += extension;
5399 /* Size of byte displacement jmp. */
5400 int md_short_jump_size = 2;
5402 /* Size of dword displacement jmp. */
5403 int md_long_jump_size = 5;
5406 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5408 addressT from_addr, to_addr;
5409 fragS *frag ATTRIBUTE_UNUSED;
5410 symbolS *to_symbol ATTRIBUTE_UNUSED;
5414 offset = to_addr - (from_addr + 2);
5415 /* Opcode for byte-disp jump. */
5416 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5417 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5421 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5423 addressT from_addr, to_addr;
5424 fragS *frag ATTRIBUTE_UNUSED;
5425 symbolS *to_symbol ATTRIBUTE_UNUSED;
5429 offset = to_addr - (from_addr + 5);
5430 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5431 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5434 /* Apply a fixup (fixS) to segment data, once it has been determined
5435 by our caller that we have all the info we need to fix it up.
5437 On the 386, immediates, displacements, and data pointers are all in
5438 the same (little-endian) format, so we don't need to care about which
5442 md_apply_fix (fixP, valP, seg)
5443 /* The fix we're to put in. */
5445 /* Pointer to the value of the bits. */
5447 /* Segment fix is from. */
5448 segT seg ATTRIBUTE_UNUSED;
5450 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5451 valueT value = *valP;
5453 #if !defined (TE_Mach)
5456 switch (fixP->fx_r_type)
5462 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5465 case BFD_RELOC_X86_64_32S:
5466 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5469 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5472 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5477 if (fixP->fx_addsy != NULL
5478 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5479 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5480 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5481 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5482 && !use_rela_relocations)
5484 /* This is a hack. There should be a better way to handle this.
5485 This covers for the fact that bfd_install_relocation will
5486 subtract the current location (for partial_inplace, PC relative
5487 relocations); see more below. */
5491 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5494 value += fixP->fx_where + fixP->fx_frag->fr_address;
5496 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5499 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5502 || (symbol_section_p (fixP->fx_addsy)
5503 && sym_seg != absolute_section))
5504 && !generic_force_reloc (fixP))
5506 /* Yes, we add the values in twice. This is because
5507 bfd_install_relocation subtracts them out again. I think
5508 bfd_install_relocation is broken, but I don't dare change
5510 value += fixP->fx_where + fixP->fx_frag->fr_address;
5514 #if defined (OBJ_COFF) && defined (TE_PE)
5515 /* For some reason, the PE format does not store a
5516 section address offset for a PC relative symbol. */
5517 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5518 || S_IS_WEAK (fixP->fx_addsy))
5519 value += md_pcrel_from (fixP);
5523 /* Fix a few things - the dynamic linker expects certain values here,
5524 and we must not disappoint it. */
5525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5526 if (IS_ELF && fixP->fx_addsy)
5527 switch (fixP->fx_r_type)
5529 case BFD_RELOC_386_PLT32:
5530 case BFD_RELOC_X86_64_PLT32:
5531 /* Make the jump instruction point to the address of the operand. At
5532 runtime we merely add the offset to the actual PLT entry. */
5536 case BFD_RELOC_386_TLS_GD:
5537 case BFD_RELOC_386_TLS_LDM:
5538 case BFD_RELOC_386_TLS_IE_32:
5539 case BFD_RELOC_386_TLS_IE:
5540 case BFD_RELOC_386_TLS_GOTIE:
5541 case BFD_RELOC_386_TLS_GOTDESC:
5542 case BFD_RELOC_X86_64_TLSGD:
5543 case BFD_RELOC_X86_64_TLSLD:
5544 case BFD_RELOC_X86_64_GOTTPOFF:
5545 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5546 value = 0; /* Fully resolved at runtime. No addend. */
5548 case BFD_RELOC_386_TLS_LE:
5549 case BFD_RELOC_386_TLS_LDO_32:
5550 case BFD_RELOC_386_TLS_LE_32:
5551 case BFD_RELOC_X86_64_DTPOFF32:
5552 case BFD_RELOC_X86_64_DTPOFF64:
5553 case BFD_RELOC_X86_64_TPOFF32:
5554 case BFD_RELOC_X86_64_TPOFF64:
5555 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5558 case BFD_RELOC_386_TLS_DESC_CALL:
5559 case BFD_RELOC_X86_64_TLSDESC_CALL:
5560 value = 0; /* Fully resolved at runtime. No addend. */
5561 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5565 case BFD_RELOC_386_GOT32:
5566 case BFD_RELOC_X86_64_GOT32:
5567 value = 0; /* Fully resolved at runtime. No addend. */
5570 case BFD_RELOC_VTABLE_INHERIT:
5571 case BFD_RELOC_VTABLE_ENTRY:
5578 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5580 #endif /* !defined (TE_Mach) */
5582 /* Are we finished with this relocation now? */
5583 if (fixP->fx_addsy == NULL)
5585 else if (use_rela_relocations)
5587 fixP->fx_no_overflow = 1;
5588 /* Remember value for tc_gen_reloc. */
5589 fixP->fx_addnumber = value;
5593 md_number_to_chars (p, value, fixP->fx_size);
5596 #define MAX_LITTLENUMS 6
5598 /* Turn the string pointed to by litP into a floating point constant
5599 of type TYPE, and emit the appropriate bytes. The number of
5600 LITTLENUMS emitted is stored in *SIZEP. An error message is
5601 returned, or NULL on OK. */
5604 md_atof (type, litP, sizeP)
5610 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5611 LITTLENUM_TYPE *wordP;
5633 return _("Bad call to md_atof ()");
5635 t = atof_ieee (input_line_pointer, type, words);
5637 input_line_pointer = t;
5639 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5640 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5641 the bigendian 386. */
5642 for (wordP = words + prec - 1; prec--;)
5644 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5645 litP += sizeof (LITTLENUM_TYPE);
5650 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5653 output_invalid (int c)
5656 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5659 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5660 "(0x%x)", (unsigned char) c);
5661 return output_invalid_buf;
5664 /* REG_STRING starts *before* REGISTER_PREFIX. */
5666 static const reg_entry *
5667 parse_real_register (char *reg_string, char **end_op)
5669 char *s = reg_string;
5671 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5674 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5675 if (*s == REGISTER_PREFIX)
5678 if (is_space_char (*s))
5682 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5684 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5685 return (const reg_entry *) NULL;
5689 /* For naked regs, make sure that we are not dealing with an identifier.
5690 This prevents confusing an identifier like `eax_var' with register
5692 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5693 return (const reg_entry *) NULL;
5697 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5699 /* Handle floating point regs, allowing spaces in the (i) part. */
5700 if (r == i386_regtab /* %st is first entry of table */)
5702 if (is_space_char (*s))
5707 if (is_space_char (*s))
5709 if (*s >= '0' && *s <= '7')
5711 r = &i386_float_regtab[*s - '0'];
5713 if (is_space_char (*s))
5721 /* We have "%st(" then garbage. */
5722 return (const reg_entry *) NULL;
5727 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5728 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5729 && flag_code != CODE_64BIT)
5730 return (const reg_entry *) NULL;
5735 /* REG_STRING starts *before* REGISTER_PREFIX. */
5737 static const reg_entry *
5738 parse_register (char *reg_string, char **end_op)
5742 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5743 r = parse_real_register (reg_string, end_op);
5748 char *save = input_line_pointer;
5752 input_line_pointer = reg_string;
5753 c = get_symbol_end ();
5754 symbolP = symbol_find (reg_string);
5755 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5757 const expressionS *e = symbol_get_value_expression (symbolP);
5759 know (e->X_op == O_register);
5760 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5761 r = i386_regtab + e->X_add_number;
5762 *end_op = input_line_pointer;
5764 *input_line_pointer = c;
5765 input_line_pointer = save;
5771 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5774 char *end = input_line_pointer;
5777 r = parse_register (name, &input_line_pointer);
5778 if (r && end <= input_line_pointer)
5780 *nextcharP = *input_line_pointer;
5781 *input_line_pointer = 0;
5782 e->X_op = O_register;
5783 e->X_add_number = r - i386_regtab;
5786 input_line_pointer = end;
5792 md_operand (expressionS *e)
5794 if (*input_line_pointer == REGISTER_PREFIX)
5797 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5801 e->X_op = O_register;
5802 e->X_add_number = r - i386_regtab;
5803 input_line_pointer = end;
5809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5810 const char *md_shortopts = "kVQ:sqn";
5812 const char *md_shortopts = "qn";
5815 #define OPTION_32 (OPTION_MD_BASE + 0)
5816 #define OPTION_64 (OPTION_MD_BASE + 1)
5817 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5818 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5819 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5821 struct option md_longopts[] =
5823 {"32", no_argument, NULL, OPTION_32},
5824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5825 {"64", no_argument, NULL, OPTION_64},
5827 {"divide", no_argument, NULL, OPTION_DIVIDE},
5828 {"march", required_argument, NULL, OPTION_MARCH},
5829 {"mtune", required_argument, NULL, OPTION_MTUNE},
5830 {NULL, no_argument, NULL, 0}
5832 size_t md_longopts_size = sizeof (md_longopts);
5835 md_parse_option (int c, char *arg)
5842 optimize_align_code = 0;
5849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5850 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5851 should be emitted or not. FIXME: Not implemented. */
5855 /* -V: SVR4 argument to print version ID. */
5857 print_version_id ();
5860 /* -k: Ignore for FreeBSD compatibility. */
5865 /* -s: On i386 Solaris, this tells the native assembler to use
5866 .stab instead of .stab.excl. We always use .stab anyhow. */
5869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5872 const char **list, **l;
5874 list = bfd_target_list ();
5875 for (l = list; *l != NULL; l++)
5876 if (CONST_STRNEQ (*l, "elf64-x86-64")
5877 || strcmp (*l, "coff-x86-64") == 0
5878 || strcmp (*l, "pe-x86-64") == 0
5879 || strcmp (*l, "pei-x86-64") == 0)
5881 default_arch = "x86_64";
5885 as_fatal (_("No compiled in support for x86_64"));
5892 default_arch = "i386";
5896 #ifdef SVR4_COMMENT_CHARS
5901 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5903 for (s = i386_comment_chars; *s != '\0'; s++)
5907 i386_comment_chars = n;
5914 as_fatal (_("Invalid -march= option: `%s'"), arg);
5915 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5917 if (strcmp (arg, cpu_arch [i].name) == 0)
5919 cpu_arch_isa = cpu_arch[i].type;
5920 cpu_arch_isa_flags = cpu_arch[i].flags;
5921 if (!cpu_arch_tune_set)
5923 cpu_arch_tune = cpu_arch_isa;
5924 cpu_arch_tune_flags = cpu_arch_isa_flags;
5929 if (i >= ARRAY_SIZE (cpu_arch))
5930 as_fatal (_("Invalid -march= option: `%s'"), arg);
5935 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5936 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5938 if (strcmp (arg, cpu_arch [i].name) == 0)
5940 cpu_arch_tune_set = 1;
5941 cpu_arch_tune = cpu_arch [i].type;
5942 cpu_arch_tune_flags = cpu_arch[i].flags;
5946 if (i >= ARRAY_SIZE (cpu_arch))
5947 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5957 md_show_usage (stream)
5960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5961 fprintf (stream, _("\
5963 -V print assembler version number\n\
5966 fprintf (stream, _("\
5967 -n Do not optimize code alignment\n\
5968 -q quieten some warnings\n"));
5969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5970 fprintf (stream, _("\
5973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5974 fprintf (stream, _("\
5975 --32/--64 generate 32bit/64bit code\n"));
5977 #ifdef SVR4_COMMENT_CHARS
5978 fprintf (stream, _("\
5979 --divide do not treat `/' as a comment character\n"));
5981 fprintf (stream, _("\
5982 --divide ignored\n"));
5984 fprintf (stream, _("\
5985 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5986 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5987 core, core2, k6, athlon, k8, generic32, generic64\n"));
5993 x86_64_target_format (void)
5995 if (strcmp (default_arch, "x86_64") == 0)
5997 set_code_flag (CODE_64BIT);
5998 return COFF_TARGET_FORMAT;
6000 else if (strcmp (default_arch, "i386") == 0)
6002 set_code_flag (CODE_32BIT);
6006 as_fatal (_("Unknown architecture"));
6011 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6012 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6014 /* Pick the target format to use. */
6017 i386_target_format (void)
6019 if (!strcmp (default_arch, "x86_64"))
6021 set_code_flag (CODE_64BIT);
6022 if (cpu_arch_isa_flags == 0)
6023 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6024 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6026 if (cpu_arch_tune_flags == 0)
6027 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6028 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6031 else if (!strcmp (default_arch, "i386"))
6033 set_code_flag (CODE_32BIT);
6034 if (cpu_arch_isa_flags == 0)
6035 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6036 if (cpu_arch_tune_flags == 0)
6037 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6040 as_fatal (_("Unknown architecture"));
6041 switch (OUTPUT_FLAVOR)
6043 #ifdef OBJ_MAYBE_AOUT
6044 case bfd_target_aout_flavour:
6045 return AOUT_TARGET_FORMAT;
6047 #ifdef OBJ_MAYBE_COFF
6048 case bfd_target_coff_flavour:
6051 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6052 case bfd_target_elf_flavour:
6054 if (flag_code == CODE_64BIT)
6057 use_rela_relocations = 1;
6059 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6068 #endif /* OBJ_MAYBE_ more than one */
6070 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6072 i386_elf_emit_arch_note (void)
6074 if (IS_ELF && cpu_arch_name != NULL)
6077 asection *seg = now_seg;
6078 subsegT subseg = now_subseg;
6079 Elf_Internal_Note i_note;
6080 Elf_External_Note e_note;
6081 asection *note_secp;
6084 /* Create the .note section. */
6085 note_secp = subseg_new (".note", 0);
6086 bfd_set_section_flags (stdoutput,
6088 SEC_HAS_CONTENTS | SEC_READONLY);
6090 /* Process the arch string. */
6091 len = strlen (cpu_arch_name);
6093 i_note.namesz = len + 1;
6095 i_note.type = NT_ARCH;
6096 p = frag_more (sizeof (e_note.namesz));
6097 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6098 p = frag_more (sizeof (e_note.descsz));
6099 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6100 p = frag_more (sizeof (e_note.type));
6101 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6102 p = frag_more (len + 1);
6103 strcpy (p, cpu_arch_name);
6105 frag_align (2, 0, 0);
6107 subseg_set (seg, subseg);
6113 md_undefined_symbol (name)
6116 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6117 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6118 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6119 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6123 if (symbol_find (name))
6124 as_bad (_("GOT already in symbol table"));
6125 GOT_symbol = symbol_new (name, undefined_section,
6126 (valueT) 0, &zero_address_frag);
6133 /* Round up a section size to the appropriate boundary. */
6136 md_section_align (segment, size)
6137 segT segment ATTRIBUTE_UNUSED;
6140 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6141 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6143 /* For a.out, force the section size to be aligned. If we don't do
6144 this, BFD will align it for us, but it will not write out the
6145 final bytes of the section. This may be a bug in BFD, but it is
6146 easier to fix it here since that is how the other a.out targets
6150 align = bfd_get_section_alignment (stdoutput, segment);
6151 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6158 /* On the i386, PC-relative offsets are relative to the start of the
6159 next instruction. That is, the address of the offset, plus its
6160 size, since the offset is always the last part of the insn. */
6163 md_pcrel_from (fixS *fixP)
6165 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6171 s_bss (int ignore ATTRIBUTE_UNUSED)
6175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6177 obj_elf_section_change_hook ();
6179 temp = get_absolute_expression ();
6180 subseg_set (bss_section, (subsegT) temp);
6181 demand_empty_rest_of_line ();
6187 i386_validate_fix (fixS *fixp)
6189 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6191 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6195 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6200 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6202 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6209 tc_gen_reloc (section, fixp)
6210 asection *section ATTRIBUTE_UNUSED;
6214 bfd_reloc_code_real_type code;
6216 switch (fixp->fx_r_type)
6218 case BFD_RELOC_X86_64_PLT32:
6219 case BFD_RELOC_X86_64_GOT32:
6220 case BFD_RELOC_X86_64_GOTPCREL:
6221 case BFD_RELOC_386_PLT32:
6222 case BFD_RELOC_386_GOT32:
6223 case BFD_RELOC_386_GOTOFF:
6224 case BFD_RELOC_386_GOTPC:
6225 case BFD_RELOC_386_TLS_GD:
6226 case BFD_RELOC_386_TLS_LDM:
6227 case BFD_RELOC_386_TLS_LDO_32:
6228 case BFD_RELOC_386_TLS_IE_32:
6229 case BFD_RELOC_386_TLS_IE:
6230 case BFD_RELOC_386_TLS_GOTIE:
6231 case BFD_RELOC_386_TLS_LE_32:
6232 case BFD_RELOC_386_TLS_LE:
6233 case BFD_RELOC_386_TLS_GOTDESC:
6234 case BFD_RELOC_386_TLS_DESC_CALL:
6235 case BFD_RELOC_X86_64_TLSGD:
6236 case BFD_RELOC_X86_64_TLSLD:
6237 case BFD_RELOC_X86_64_DTPOFF32:
6238 case BFD_RELOC_X86_64_DTPOFF64:
6239 case BFD_RELOC_X86_64_GOTTPOFF:
6240 case BFD_RELOC_X86_64_TPOFF32:
6241 case BFD_RELOC_X86_64_TPOFF64:
6242 case BFD_RELOC_X86_64_GOTOFF64:
6243 case BFD_RELOC_X86_64_GOTPC32:
6244 case BFD_RELOC_X86_64_GOT64:
6245 case BFD_RELOC_X86_64_GOTPCREL64:
6246 case BFD_RELOC_X86_64_GOTPC64:
6247 case BFD_RELOC_X86_64_GOTPLT64:
6248 case BFD_RELOC_X86_64_PLTOFF64:
6249 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6250 case BFD_RELOC_X86_64_TLSDESC_CALL:
6252 case BFD_RELOC_VTABLE_ENTRY:
6253 case BFD_RELOC_VTABLE_INHERIT:
6255 case BFD_RELOC_32_SECREL:
6257 code = fixp->fx_r_type;
6259 case BFD_RELOC_X86_64_32S:
6260 if (!fixp->fx_pcrel)
6262 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6263 code = fixp->fx_r_type;
6269 switch (fixp->fx_size)
6272 as_bad_where (fixp->fx_file, fixp->fx_line,
6273 _("can not do %d byte pc-relative relocation"),
6275 code = BFD_RELOC_32_PCREL;
6277 case 1: code = BFD_RELOC_8_PCREL; break;
6278 case 2: code = BFD_RELOC_16_PCREL; break;
6279 case 4: code = BFD_RELOC_32_PCREL; break;
6281 case 8: code = BFD_RELOC_64_PCREL; break;
6287 switch (fixp->fx_size)
6290 as_bad_where (fixp->fx_file, fixp->fx_line,
6291 _("can not do %d byte relocation"),
6293 code = BFD_RELOC_32;
6295 case 1: code = BFD_RELOC_8; break;
6296 case 2: code = BFD_RELOC_16; break;
6297 case 4: code = BFD_RELOC_32; break;
6299 case 8: code = BFD_RELOC_64; break;
6306 if ((code == BFD_RELOC_32
6307 || code == BFD_RELOC_32_PCREL
6308 || code == BFD_RELOC_X86_64_32S)
6310 && fixp->fx_addsy == GOT_symbol)
6313 code = BFD_RELOC_386_GOTPC;
6315 code = BFD_RELOC_X86_64_GOTPC32;
6317 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6319 && fixp->fx_addsy == GOT_symbol)
6321 code = BFD_RELOC_X86_64_GOTPC64;
6324 rel = (arelent *) xmalloc (sizeof (arelent));
6325 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6326 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6328 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6330 if (!use_rela_relocations)
6332 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6333 vtable entry to be used in the relocation's section offset. */
6334 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6335 rel->address = fixp->fx_offset;
6339 /* Use the rela in 64bit mode. */
6342 if (!fixp->fx_pcrel)
6343 rel->addend = fixp->fx_offset;
6347 case BFD_RELOC_X86_64_PLT32:
6348 case BFD_RELOC_X86_64_GOT32:
6349 case BFD_RELOC_X86_64_GOTPCREL:
6350 case BFD_RELOC_X86_64_TLSGD:
6351 case BFD_RELOC_X86_64_TLSLD:
6352 case BFD_RELOC_X86_64_GOTTPOFF:
6353 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6354 case BFD_RELOC_X86_64_TLSDESC_CALL:
6355 rel->addend = fixp->fx_offset - fixp->fx_size;
6358 rel->addend = (section->vma
6360 + fixp->fx_addnumber
6361 + md_pcrel_from (fixp));
6366 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6367 if (rel->howto == NULL)
6369 as_bad_where (fixp->fx_file, fixp->fx_line,
6370 _("cannot represent relocation type %s"),
6371 bfd_get_reloc_code_name (code));
6372 /* Set howto to a garbage value so that we can keep going. */
6373 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6374 assert (rel->howto != NULL);
6381 /* Parse operands using Intel syntax. This implements a recursive descent
6382 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6385 FIXME: We do not recognize the full operand grammar defined in the MASM
6386 documentation. In particular, all the structure/union and
6387 high-level macro operands are missing.
6389 Uppercase words are terminals, lower case words are non-terminals.
6390 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6391 bars '|' denote choices. Most grammar productions are implemented in
6392 functions called 'intel_<production>'.
6394 Initial production is 'expr'.
6400 binOp & | AND | \| | OR | ^ | XOR
6402 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6404 constant digits [[ radixOverride ]]
6406 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6444 => expr expr cmpOp e04
6447 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6448 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6450 hexdigit a | b | c | d | e | f
6451 | A | B | C | D | E | F
6457 mulOp * | / | % | MOD | << | SHL | >> | SHR
6461 register specialRegister
6465 segmentRegister CS | DS | ES | FS | GS | SS
6467 specialRegister CR0 | CR2 | CR3 | CR4
6468 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6469 | TR3 | TR4 | TR5 | TR6 | TR7
6471 We simplify the grammar in obvious places (e.g., register parsing is
6472 done by calling parse_register) and eliminate immediate left recursion
6473 to implement a recursive-descent parser.
6477 expr' cmpOp e04 expr'
6528 /* Parsing structure for the intel syntax parser. Used to implement the
6529 semantic actions for the operand grammar. */
6530 struct intel_parser_s
6532 char *op_string; /* The string being parsed. */
6533 int got_a_float; /* Whether the operand is a float. */
6534 int op_modifier; /* Operand modifier. */
6535 int is_mem; /* 1 if operand is memory reference. */
6536 int in_offset; /* >=1 if parsing operand of offset. */
6537 int in_bracket; /* >=1 if parsing operand in brackets. */
6538 const reg_entry *reg; /* Last register reference found. */
6539 char *disp; /* Displacement string being built. */
6540 char *next_operand; /* Resume point when splitting operands. */
6543 static struct intel_parser_s intel_parser;
6545 /* Token structure for parsing intel syntax. */
6548 int code; /* Token code. */
6549 const reg_entry *reg; /* Register entry for register tokens. */
6550 char *str; /* String representation. */
6553 static struct intel_token cur_token, prev_token;
6555 /* Token codes for the intel parser. Since T_SHORT is already used
6556 by COFF, undefine it first to prevent a warning. */
6575 /* Prototypes for intel parser functions. */
6576 static int intel_match_token (int);
6577 static void intel_putback_token (void);
6578 static void intel_get_token (void);
6579 static int intel_expr (void);
6580 static int intel_e04 (void);
6581 static int intel_e05 (void);
6582 static int intel_e06 (void);
6583 static int intel_e09 (void);
6584 static int intel_e10 (void);
6585 static int intel_e11 (void);
6588 i386_intel_operand (char *operand_string, int got_a_float)
6593 p = intel_parser.op_string = xstrdup (operand_string);
6594 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6598 /* Initialize token holders. */
6599 cur_token.code = prev_token.code = T_NIL;
6600 cur_token.reg = prev_token.reg = NULL;
6601 cur_token.str = prev_token.str = NULL;
6603 /* Initialize parser structure. */
6604 intel_parser.got_a_float = got_a_float;
6605 intel_parser.op_modifier = 0;
6606 intel_parser.is_mem = 0;
6607 intel_parser.in_offset = 0;
6608 intel_parser.in_bracket = 0;
6609 intel_parser.reg = NULL;
6610 intel_parser.disp[0] = '\0';
6611 intel_parser.next_operand = NULL;
6613 /* Read the first token and start the parser. */
6615 ret = intel_expr ();
6620 if (cur_token.code != T_NIL)
6622 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6623 current_templates->start->name, cur_token.str);
6626 /* If we found a memory reference, hand it over to i386_displacement
6627 to fill in the rest of the operand fields. */
6628 else if (intel_parser.is_mem)
6630 if ((i.mem_operands == 1
6631 && (current_templates->start->opcode_modifier & IsString) == 0)
6632 || i.mem_operands == 2)
6634 as_bad (_("too many memory references for '%s'"),
6635 current_templates->start->name);
6640 char *s = intel_parser.disp;
6643 if (!quiet_warnings && intel_parser.is_mem < 0)
6644 /* See the comments in intel_bracket_expr. */
6645 as_warn (_("Treating `%s' as memory reference"), operand_string);
6647 /* Add the displacement expression. */
6649 ret = i386_displacement (s, s + strlen (s));
6652 /* Swap base and index in 16-bit memory operands like
6653 [si+bx]. Since i386_index_check is also used in AT&T
6654 mode we have to do that here. */
6657 && (i.base_reg->reg_type & Reg16)
6658 && (i.index_reg->reg_type & Reg16)
6659 && i.base_reg->reg_num >= 6
6660 && i.index_reg->reg_num < 6)
6662 const reg_entry *base = i.index_reg;
6664 i.index_reg = i.base_reg;
6667 ret = i386_index_check (operand_string);
6672 /* Constant and OFFSET expressions are handled by i386_immediate. */
6673 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6674 || intel_parser.reg == NULL)
6675 ret = i386_immediate (intel_parser.disp);
6677 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6679 if (!ret || !intel_parser.next_operand)
6681 intel_parser.op_string = intel_parser.next_operand;
6682 this_operand = i.operands++;
6686 free (intel_parser.disp);
6691 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6695 expr' cmpOp e04 expr'
6700 /* XXX Implement the comparison operators. */
6701 return intel_e04 ();
6718 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6719 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6721 if (cur_token.code == '+')
6723 else if (cur_token.code == '-')
6724 nregs = NUM_ADDRESS_REGS;
6728 strcat (intel_parser.disp, cur_token.str);
6729 intel_match_token (cur_token.code);
6740 int nregs = ~NUM_ADDRESS_REGS;
6747 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6751 str[0] = cur_token.code;
6753 strcat (intel_parser.disp, str);
6758 intel_match_token (cur_token.code);
6763 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6764 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6775 int nregs = ~NUM_ADDRESS_REGS;
6782 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6786 str[0] = cur_token.code;
6788 strcat (intel_parser.disp, str);
6790 else if (cur_token.code == T_SHL)
6791 strcat (intel_parser.disp, "<<");
6792 else if (cur_token.code == T_SHR)
6793 strcat (intel_parser.disp, ">>");
6797 intel_match_token (cur_token.code);
6802 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6803 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6821 int nregs = ~NUM_ADDRESS_REGS;
6826 /* Don't consume constants here. */
6827 if (cur_token.code == '+' || cur_token.code == '-')
6829 /* Need to look one token ahead - if the next token
6830 is a constant, the current token is its sign. */
6833 intel_match_token (cur_token.code);
6834 next_code = cur_token.code;
6835 intel_putback_token ();
6836 if (next_code == T_CONST)
6840 /* e09 OFFSET e09 */
6841 if (cur_token.code == T_OFFSET)
6844 ++intel_parser.in_offset;
6848 else if (cur_token.code == T_SHORT)
6849 intel_parser.op_modifier |= 1 << T_SHORT;
6852 else if (cur_token.code == '+')
6853 strcat (intel_parser.disp, "+");
6858 else if (cur_token.code == '-' || cur_token.code == '~')
6864 str[0] = cur_token.code;
6866 strcat (intel_parser.disp, str);
6873 intel_match_token (cur_token.code);
6881 /* e09' PTR e10 e09' */
6882 if (cur_token.code == T_PTR)
6886 if (prev_token.code == T_BYTE)
6887 suffix = BYTE_MNEM_SUFFIX;
6889 else if (prev_token.code == T_WORD)
6891 if (current_templates->start->name[0] == 'l'
6892 && current_templates->start->name[2] == 's'
6893 && current_templates->start->name[3] == 0)
6894 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6895 else if (intel_parser.got_a_float == 2) /* "fi..." */
6896 suffix = SHORT_MNEM_SUFFIX;
6898 suffix = WORD_MNEM_SUFFIX;
6901 else if (prev_token.code == T_DWORD)
6903 if (current_templates->start->name[0] == 'l'
6904 && current_templates->start->name[2] == 's'
6905 && current_templates->start->name[3] == 0)
6906 suffix = WORD_MNEM_SUFFIX;
6907 else if (flag_code == CODE_16BIT
6908 && (current_templates->start->opcode_modifier
6909 & (Jump | JumpDword)))
6910 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6911 else if (intel_parser.got_a_float == 1) /* "f..." */
6912 suffix = SHORT_MNEM_SUFFIX;
6914 suffix = LONG_MNEM_SUFFIX;
6917 else if (prev_token.code == T_FWORD)
6919 if (current_templates->start->name[0] == 'l'
6920 && current_templates->start->name[2] == 's'
6921 && current_templates->start->name[3] == 0)
6922 suffix = LONG_MNEM_SUFFIX;
6923 else if (!intel_parser.got_a_float)
6925 if (flag_code == CODE_16BIT)
6926 add_prefix (DATA_PREFIX_OPCODE);
6927 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6930 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6933 else if (prev_token.code == T_QWORD)
6935 if (intel_parser.got_a_float == 1) /* "f..." */
6936 suffix = LONG_MNEM_SUFFIX;
6938 suffix = QWORD_MNEM_SUFFIX;
6941 else if (prev_token.code == T_TBYTE)
6943 if (intel_parser.got_a_float == 1)
6944 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6946 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6949 else if (prev_token.code == T_XMMWORD)
6951 /* XXX ignored for now, but accepted since gcc uses it */
6957 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6961 /* Operands for jump/call using 'ptr' notation denote absolute
6963 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6964 i.types[this_operand] |= JumpAbsolute;
6966 if (current_templates->start->base_opcode == 0x8d /* lea */)
6970 else if (i.suffix != suffix)
6972 as_bad (_("Conflicting operand modifiers"));
6978 /* e09' : e10 e09' */
6979 else if (cur_token.code == ':')
6981 if (prev_token.code != T_REG)
6983 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6984 segment/group identifier (which we don't have), using comma
6985 as the operand separator there is even less consistent, since
6986 there all branches only have a single operand. */
6987 if (this_operand != 0
6988 || intel_parser.in_offset
6989 || intel_parser.in_bracket
6990 || (!(current_templates->start->opcode_modifier
6991 & (Jump|JumpDword|JumpInterSegment))
6992 && !(current_templates->start->operand_types[0]
6994 return intel_match_token (T_NIL);
6995 /* Remember the start of the 2nd operand and terminate 1st
6997 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6998 another expression), but it gets at least the simplest case
6999 (a plain number or symbol on the left side) right. */
7000 intel_parser.next_operand = intel_parser.op_string;
7001 *--intel_parser.op_string = '\0';
7002 return intel_match_token (':');
7010 intel_match_token (cur_token.code);
7016 --intel_parser.in_offset;
7019 if (NUM_ADDRESS_REGS > nregs)
7021 as_bad (_("Invalid operand to `OFFSET'"));
7024 intel_parser.op_modifier |= 1 << T_OFFSET;
7027 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7028 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7033 intel_bracket_expr (void)
7035 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7036 const char *start = intel_parser.op_string;
7039 if (i.op[this_operand].regs)
7040 return intel_match_token (T_NIL);
7042 intel_match_token ('[');
7044 /* Mark as a memory operand only if it's not already known to be an
7045 offset expression. If it's an offset expression, we need to keep
7047 if (!intel_parser.in_offset)
7049 ++intel_parser.in_bracket;
7051 /* Operands for jump/call inside brackets denote absolute addresses. */
7052 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7053 i.types[this_operand] |= JumpAbsolute;
7055 /* Unfortunately gas always diverged from MASM in a respect that can't
7056 be easily fixed without risking to break code sequences likely to be
7057 encountered (the testsuite even check for this): MASM doesn't consider
7058 an expression inside brackets unconditionally as a memory reference.
7059 When that is e.g. a constant, an offset expression, or the sum of the
7060 two, this is still taken as a constant load. gas, however, always
7061 treated these as memory references. As a compromise, we'll try to make
7062 offset expressions inside brackets work the MASM way (since that's
7063 less likely to be found in real world code), but make constants alone
7064 continue to work the traditional gas way. In either case, issue a
7066 intel_parser.op_modifier &= ~was_offset;
7069 strcat (intel_parser.disp, "[");
7071 /* Add a '+' to the displacement string if necessary. */
7072 if (*intel_parser.disp != '\0'
7073 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7074 strcat (intel_parser.disp, "+");
7077 && (len = intel_parser.op_string - start - 1,
7078 intel_match_token (']')))
7080 /* Preserve brackets when the operand is an offset expression. */
7081 if (intel_parser.in_offset)
7082 strcat (intel_parser.disp, "]");
7085 --intel_parser.in_bracket;
7086 if (i.base_reg || i.index_reg)
7087 intel_parser.is_mem = 1;
7088 if (!intel_parser.is_mem)
7090 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7091 /* Defer the warning until all of the operand was parsed. */
7092 intel_parser.is_mem = -1;
7093 else if (!quiet_warnings)
7094 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7097 intel_parser.op_modifier |= was_offset;
7114 while (cur_token.code == '[')
7116 if (!intel_bracket_expr ())
7141 switch (cur_token.code)
7145 intel_match_token ('(');
7146 strcat (intel_parser.disp, "(");
7148 if (intel_expr () && intel_match_token (')'))
7150 strcat (intel_parser.disp, ")");
7157 return intel_bracket_expr ();
7162 strcat (intel_parser.disp, cur_token.str);
7163 intel_match_token (cur_token.code);
7165 /* Mark as a memory operand only if it's not already known to be an
7166 offset expression. */
7167 if (!intel_parser.in_offset)
7168 intel_parser.is_mem = 1;
7175 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7177 intel_match_token (T_REG);
7179 /* Check for segment change. */
7180 if (cur_token.code == ':')
7182 if (!(reg->reg_type & (SReg2 | SReg3)))
7184 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7187 else if (i.seg[i.mem_operands])
7188 as_warn (_("Extra segment override ignored"));
7191 if (!intel_parser.in_offset)
7192 intel_parser.is_mem = 1;
7193 switch (reg->reg_num)
7196 i.seg[i.mem_operands] = &es;
7199 i.seg[i.mem_operands] = &cs;
7202 i.seg[i.mem_operands] = &ss;
7205 i.seg[i.mem_operands] = &ds;
7208 i.seg[i.mem_operands] = &fs;
7211 i.seg[i.mem_operands] = &gs;
7217 /* Not a segment register. Check for register scaling. */
7218 else if (cur_token.code == '*')
7220 if (!intel_parser.in_bracket)
7222 as_bad (_("Register scaling only allowed in memory operands"));
7226 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7227 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7228 else if (i.index_reg)
7229 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7231 /* What follows must be a valid scale. */
7232 intel_match_token ('*');
7234 i.types[this_operand] |= BaseIndex;
7236 /* Set the scale after setting the register (otherwise,
7237 i386_scale will complain) */
7238 if (cur_token.code == '+' || cur_token.code == '-')
7240 char *str, sign = cur_token.code;
7241 intel_match_token (cur_token.code);
7242 if (cur_token.code != T_CONST)
7244 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7248 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7249 strcpy (str + 1, cur_token.str);
7251 if (!i386_scale (str))
7255 else if (!i386_scale (cur_token.str))
7257 intel_match_token (cur_token.code);
7260 /* No scaling. If this is a memory operand, the register is either a
7261 base register (first occurrence) or an index register (second
7263 else if (intel_parser.in_bracket)
7268 else if (!i.index_reg)
7272 as_bad (_("Too many register references in memory operand"));
7276 i.types[this_operand] |= BaseIndex;
7279 /* It's neither base nor index. */
7280 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7282 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7283 i.op[this_operand].regs = reg;
7288 as_bad (_("Invalid use of register"));
7292 /* Since registers are not part of the displacement string (except
7293 when we're parsing offset operands), we may need to remove any
7294 preceding '+' from the displacement string. */
7295 if (*intel_parser.disp != '\0'
7296 && !intel_parser.in_offset)
7298 char *s = intel_parser.disp;
7299 s += strlen (s) - 1;
7322 intel_match_token (cur_token.code);
7324 if (cur_token.code == T_PTR)
7327 /* It must have been an identifier. */
7328 intel_putback_token ();
7329 cur_token.code = T_ID;
7335 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7339 /* The identifier represents a memory reference only if it's not
7340 preceded by an offset modifier and if it's not an equate. */
7341 symbolP = symbol_find(cur_token.str);
7342 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7343 intel_parser.is_mem = 1;
7351 char *save_str, sign = 0;
7353 /* Allow constants that start with `+' or `-'. */
7354 if (cur_token.code == '-' || cur_token.code == '+')
7356 sign = cur_token.code;
7357 intel_match_token (cur_token.code);
7358 if (cur_token.code != T_CONST)
7360 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7366 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7367 strcpy (save_str + !!sign, cur_token.str);
7371 /* Get the next token to check for register scaling. */
7372 intel_match_token (cur_token.code);
7374 /* Check if this constant is a scaling factor for an index register. */
7375 if (cur_token.code == '*')
7377 if (intel_match_token ('*') && cur_token.code == T_REG)
7379 const reg_entry *reg = cur_token.reg;
7381 if (!intel_parser.in_bracket)
7383 as_bad (_("Register scaling only allowed in memory operands"));
7387 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7388 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7389 else if (i.index_reg)
7390 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7392 /* The constant is followed by `* reg', so it must be
7395 i.types[this_operand] |= BaseIndex;
7397 /* Set the scale after setting the register (otherwise,
7398 i386_scale will complain) */
7399 if (!i386_scale (save_str))
7401 intel_match_token (T_REG);
7403 /* Since registers are not part of the displacement
7404 string, we may need to remove any preceding '+' from
7405 the displacement string. */
7406 if (*intel_parser.disp != '\0')
7408 char *s = intel_parser.disp;
7409 s += strlen (s) - 1;
7419 /* The constant was not used for register scaling. Since we have
7420 already consumed the token following `*' we now need to put it
7421 back in the stream. */
7422 intel_putback_token ();
7425 /* Add the constant to the displacement string. */
7426 strcat (intel_parser.disp, save_str);
7433 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7437 /* Match the given token against cur_token. If they match, read the next
7438 token from the operand string. */
7440 intel_match_token (int code)
7442 if (cur_token.code == code)
7449 as_bad (_("Unexpected token `%s'"), cur_token.str);
7454 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7456 intel_get_token (void)
7459 const reg_entry *reg;
7460 struct intel_token new_token;
7462 new_token.code = T_NIL;
7463 new_token.reg = NULL;
7464 new_token.str = NULL;
7466 /* Free the memory allocated to the previous token and move
7467 cur_token to prev_token. */
7469 free (prev_token.str);
7471 prev_token = cur_token;
7473 /* Skip whitespace. */
7474 while (is_space_char (*intel_parser.op_string))
7475 intel_parser.op_string++;
7477 /* Return an empty token if we find nothing else on the line. */
7478 if (*intel_parser.op_string == '\0')
7480 cur_token = new_token;
7484 /* The new token cannot be larger than the remainder of the operand
7486 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7487 new_token.str[0] = '\0';
7489 if (strchr ("0123456789", *intel_parser.op_string))
7491 char *p = new_token.str;
7492 char *q = intel_parser.op_string;
7493 new_token.code = T_CONST;
7495 /* Allow any kind of identifier char to encompass floating point and
7496 hexadecimal numbers. */
7497 while (is_identifier_char (*q))
7501 /* Recognize special symbol names [0-9][bf]. */
7502 if (strlen (intel_parser.op_string) == 2
7503 && (intel_parser.op_string[1] == 'b'
7504 || intel_parser.op_string[1] == 'f'))
7505 new_token.code = T_ID;
7508 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7510 size_t len = end_op - intel_parser.op_string;
7512 new_token.code = T_REG;
7513 new_token.reg = reg;
7515 memcpy (new_token.str, intel_parser.op_string, len);
7516 new_token.str[len] = '\0';
7519 else if (is_identifier_char (*intel_parser.op_string))
7521 char *p = new_token.str;
7522 char *q = intel_parser.op_string;
7524 /* A '.' or '$' followed by an identifier char is an identifier.
7525 Otherwise, it's operator '.' followed by an expression. */
7526 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7528 new_token.code = '.';
7529 new_token.str[0] = '.';
7530 new_token.str[1] = '\0';
7534 while (is_identifier_char (*q) || *q == '@')
7538 if (strcasecmp (new_token.str, "NOT") == 0)
7539 new_token.code = '~';
7541 else if (strcasecmp (new_token.str, "MOD") == 0)
7542 new_token.code = '%';
7544 else if (strcasecmp (new_token.str, "AND") == 0)
7545 new_token.code = '&';
7547 else if (strcasecmp (new_token.str, "OR") == 0)
7548 new_token.code = '|';
7550 else if (strcasecmp (new_token.str, "XOR") == 0)
7551 new_token.code = '^';
7553 else if (strcasecmp (new_token.str, "SHL") == 0)
7554 new_token.code = T_SHL;
7556 else if (strcasecmp (new_token.str, "SHR") == 0)
7557 new_token.code = T_SHR;
7559 else if (strcasecmp (new_token.str, "BYTE") == 0)
7560 new_token.code = T_BYTE;
7562 else if (strcasecmp (new_token.str, "WORD") == 0)
7563 new_token.code = T_WORD;
7565 else if (strcasecmp (new_token.str, "DWORD") == 0)
7566 new_token.code = T_DWORD;
7568 else if (strcasecmp (new_token.str, "FWORD") == 0)
7569 new_token.code = T_FWORD;
7571 else if (strcasecmp (new_token.str, "QWORD") == 0)
7572 new_token.code = T_QWORD;
7574 else if (strcasecmp (new_token.str, "TBYTE") == 0
7575 /* XXX remove (gcc still uses it) */
7576 || strcasecmp (new_token.str, "XWORD") == 0)
7577 new_token.code = T_TBYTE;
7579 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7580 || strcasecmp (new_token.str, "OWORD") == 0)
7581 new_token.code = T_XMMWORD;
7583 else if (strcasecmp (new_token.str, "PTR") == 0)
7584 new_token.code = T_PTR;
7586 else if (strcasecmp (new_token.str, "SHORT") == 0)
7587 new_token.code = T_SHORT;
7589 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7591 new_token.code = T_OFFSET;
7593 /* ??? This is not mentioned in the MASM grammar but gcc
7594 makes use of it with -mintel-syntax. OFFSET may be
7595 followed by FLAT: */
7596 if (strncasecmp (q, " FLAT:", 6) == 0)
7597 strcat (new_token.str, " FLAT:");
7600 /* ??? This is not mentioned in the MASM grammar. */
7601 else if (strcasecmp (new_token.str, "FLAT") == 0)
7603 new_token.code = T_OFFSET;
7605 strcat (new_token.str, ":");
7607 as_bad (_("`:' expected"));
7611 new_token.code = T_ID;
7615 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7617 new_token.code = *intel_parser.op_string;
7618 new_token.str[0] = *intel_parser.op_string;
7619 new_token.str[1] = '\0';
7622 else if (strchr ("<>", *intel_parser.op_string)
7623 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7625 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7626 new_token.str[0] = *intel_parser.op_string;
7627 new_token.str[1] = *intel_parser.op_string;
7628 new_token.str[2] = '\0';
7632 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7634 intel_parser.op_string += strlen (new_token.str);
7635 cur_token = new_token;
7638 /* Put cur_token back into the token stream and make cur_token point to
7641 intel_putback_token (void)
7643 if (cur_token.code != T_NIL)
7645 intel_parser.op_string -= strlen (cur_token.str);
7646 free (cur_token.str);
7648 cur_token = prev_token;
7650 /* Forget prev_token. */
7651 prev_token.code = T_NIL;
7652 prev_token.reg = NULL;
7653 prev_token.str = NULL;
7657 tc_x86_regname_to_dw2regnum (char *regname)
7659 unsigned int regnum;
7660 unsigned int regnames_count;
7661 static const char *const regnames_32[] =
7663 "eax", "ecx", "edx", "ebx",
7664 "esp", "ebp", "esi", "edi",
7665 "eip", "eflags", NULL,
7666 "st0", "st1", "st2", "st3",
7667 "st4", "st5", "st6", "st7",
7669 "xmm0", "xmm1", "xmm2", "xmm3",
7670 "xmm4", "xmm5", "xmm6", "xmm7",
7671 "mm0", "mm1", "mm2", "mm3",
7672 "mm4", "mm5", "mm6", "mm7",
7673 "fcw", "fsw", "mxcsr",
7674 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7677 static const char *const regnames_64[] =
7679 "rax", "rdx", "rcx", "rbx",
7680 "rsi", "rdi", "rbp", "rsp",
7681 "r8", "r9", "r10", "r11",
7682 "r12", "r13", "r14", "r15",
7684 "xmm0", "xmm1", "xmm2", "xmm3",
7685 "xmm4", "xmm5", "xmm6", "xmm7",
7686 "xmm8", "xmm9", "xmm10", "xmm11",
7687 "xmm12", "xmm13", "xmm14", "xmm15",
7688 "st0", "st1", "st2", "st3",
7689 "st4", "st5", "st6", "st7",
7690 "mm0", "mm1", "mm2", "mm3",
7691 "mm4", "mm5", "mm6", "mm7",
7693 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7694 "fs.base", "gs.base", NULL, NULL,
7696 "mxcsr", "fcw", "fsw"
7698 const char *const *regnames;
7700 if (flag_code == CODE_64BIT)
7702 regnames = regnames_64;
7703 regnames_count = ARRAY_SIZE (regnames_64);
7707 regnames = regnames_32;
7708 regnames_count = ARRAY_SIZE (regnames_32);
7711 for (regnum = 0; regnum < regnames_count; regnum++)
7712 if (regnames[regnum] != NULL
7713 && strcmp (regname, regnames[regnum]) == 0)
7720 tc_x86_frame_initial_instructions (void)
7722 static unsigned int sp_regno;
7725 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7728 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7729 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7733 i386_elf_section_type (const char *str, size_t len)
7735 if (flag_code == CODE_64BIT
7736 && len == sizeof ("unwind") - 1
7737 && strncmp (str, "unwind", 6) == 0)
7738 return SHT_X86_64_UNWIND;
7745 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7749 expr.X_op = O_secrel;
7750 expr.X_add_symbol = symbol;
7751 expr.X_add_number = 0;
7752 emit_expr (&expr, size);
7756 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7757 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7760 x86_64_section_letter (int letter, char **ptr_msg)
7762 if (flag_code == CODE_64BIT)
7765 return SHF_X86_64_LARGE;
7767 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7770 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7775 x86_64_section_word (char *str, size_t len)
7777 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7778 return SHF_X86_64_LARGE;
7784 handle_large_common (int small ATTRIBUTE_UNUSED)
7786 if (flag_code != CODE_64BIT)
7788 s_comm_internal (0, elf_common_parse);
7789 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7793 static segT lbss_section;
7794 asection *saved_com_section_ptr = elf_com_section_ptr;
7795 asection *saved_bss_section = bss_section;
7797 if (lbss_section == NULL)
7799 flagword applicable;
7801 subsegT subseg = now_subseg;
7803 /* The .lbss section is for local .largecomm symbols. */
7804 lbss_section = subseg_new (".lbss", 0);
7805 applicable = bfd_applicable_section_flags (stdoutput);
7806 bfd_set_section_flags (stdoutput, lbss_section,
7807 applicable & SEC_ALLOC);
7808 seg_info (lbss_section)->bss = 1;
7810 subseg_set (seg, subseg);
7813 elf_com_section_ptr = &_bfd_elf_large_com_section;
7814 bss_section = lbss_section;
7816 s_comm_internal (0, elf_common_parse);
7818 elf_com_section_ptr = saved_com_section_ptr;
7819 bss_section = saved_bss_section;
7822 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */