1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c);
69 static int i386_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry *parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry *build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS *, offsetT);
91 static void output_disp (fragS *, offsetT);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED);
99 static const char *default_arch = DEFAULT_ARCH;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry *regs;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types[MAX_OPERANDS];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op[MAX_OPERANDS];
136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry *seg[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars = "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars = "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "#/";
210 const char line_separator_chars[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars[256];
223 static char register_chars[256];
224 static char operand_chars[256];
225 static char identifier_chars[256];
226 static char digit_chars[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack[32];
244 static char *save_stack_p;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates *current_templates;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
260 /* Current operand we are working on. */
261 static int this_operand;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code;
272 static unsigned int object_64bit;
273 static int use_rela_relocations = 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names[] =
283 /* 1 for intel syntax,
285 static int intel_syntax = 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic = !SYSV386_COMPAT;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc = OLDGCC_COMPAT;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg = 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix = "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code = 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings = 0;
315 static const char *cpu_arch_name = NULL;
316 static const char *cpu_sub_arch_name = NULL;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragS *fragP, int count)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1[] =
576 static const char f32_2[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
639 static const char alt_3[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code == CODE_16BIT)
769 memcpy (fragP->fr_literal + fragP->fr_fix,
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
780 const char *const *patt = NULL;
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags.bitfield.cpui686)
791 patt = alt_long_patt;
795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
804 case PROCESSOR_ATHLON:
806 case PROCESSOR_AMDFAM10:
807 patt = alt_short_patt;
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
819 switch (cpu_arch_tune)
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM:
831 case PROCESSOR_ATHLON:
833 case PROCESSOR_AMDFAM10:
834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags.bitfield.cpui686)
838 patt = alt_short_patt;
842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE2:
847 if (cpu_arch_isa_flags.bitfield.cpui686)
848 patt = alt_long_patt;
852 case PROCESSOR_GENERIC64:
853 patt = alt_long_patt;
858 if (patt == f32_patt)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
868 memcpy (fragP->fr_literal + fragP->fr_fix,
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
892 fragP->fr_var = count;
896 uints_all_zero (const unsigned int *x, unsigned int size)
914 uints_set (unsigned int *x, unsigned int v, unsigned int size)
931 uints_equal (const unsigned int *x, const unsigned int *y,
943 return x[0] == y [0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f)
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
969 switch (ARRAY_SIZE (x.array))
972 x.array [2] &= y.array [2];
974 x.array [1] &= y.array [1];
976 x.array [0] &= y.array [0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
987 switch (ARRAY_SIZE (x.array))
990 x.array [2] |= y.array [2];
992 x.array [1] |= y.array [1];
994 x.array [0] |= y.array [0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x)
1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1013 if (UINTS_ALL_ZERO (x))
1017 i386_cpu_flags cpu = cpu_arch_flags;
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x, i386_operand_type y)
1030 switch (ARRAY_SIZE (x.array))
1033 x.array [2] &= y.array [2];
1035 x.array [1] &= y.array [1];
1037 x.array [0] &= y.array [0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x, i386_operand_type y)
1048 switch (ARRAY_SIZE (x.array))
1051 x.array [2] |= y.array [2];
1053 x.array [1] |= y.array [1];
1055 x.array [0] |= y.array [0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x, i386_operand_type y)
1066 switch (ARRAY_SIZE (x.array))
1069 x.array [2] ^= y.array [2];
1071 x.array [1] ^= y.array [1];
1073 x.array [0] ^= y.array [0];
1081 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
1092 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1112 operand_type_check (i386_operand_type t, enum operand_type c)
1117 return (t.bitfield.reg8
1120 || t.bitfield.reg64);
1123 return (t.bitfield.imm8
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1151 operand_type_match (i386_operand_type overlap,
1152 i386_operand_type given)
1154 i386_operand_type temp = overlap;
1156 temp.bitfield.jumpabsolute = 0;
1157 if (UINTS_ALL_ZERO (temp))
1160 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1161 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1164 /* If given types r0 and r1 are registers they must be of the same type
1165 unless the expected operand type register overlap is null.
1166 Note that Acc in a template matches every size of reg. */
1169 operand_type_register_match (i386_operand_type m0,
1170 i386_operand_type g0,
1171 i386_operand_type t0,
1172 i386_operand_type m1,
1173 i386_operand_type g1,
1174 i386_operand_type t1)
1176 if (!operand_type_check (g0, reg))
1179 if (!operand_type_check (g1, reg))
1182 if (g0.bitfield.reg8 == g1.bitfield.reg8
1183 && g0.bitfield.reg16 == g1.bitfield.reg16
1184 && g0.bitfield.reg32 == g1.bitfield.reg32
1185 && g0.bitfield.reg64 == g1.bitfield.reg64)
1188 if (m0.bitfield.acc)
1190 t0.bitfield.reg8 = 1;
1191 t0.bitfield.reg16 = 1;
1192 t0.bitfield.reg32 = 1;
1193 t0.bitfield.reg64 = 1;
1196 if (m1.bitfield.acc)
1198 t1.bitfield.reg8 = 1;
1199 t1.bitfield.reg16 = 1;
1200 t1.bitfield.reg32 = 1;
1201 t1.bitfield.reg64 = 1;
1204 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1205 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1206 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1207 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1210 static INLINE unsigned int
1211 mode_from_disp_size (i386_operand_type t)
1213 if (t.bitfield.disp8)
1215 else if (t.bitfield.disp16
1216 || t.bitfield.disp32
1217 || t.bitfield.disp32s)
1224 fits_in_signed_byte (offsetT num)
1226 return (num >= -128) && (num <= 127);
1230 fits_in_unsigned_byte (offsetT num)
1232 return (num & 0xff) == num;
1236 fits_in_unsigned_word (offsetT num)
1238 return (num & 0xffff) == num;
1242 fits_in_signed_word (offsetT num)
1244 return (-32768 <= num) && (num <= 32767);
1248 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1253 return (!(((offsetT) -1 << 31) & num)
1254 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1256 } /* fits_in_signed_long() */
1259 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1264 return (num & (((offsetT) 2 << 31) - 1)) == num;
1266 } /* fits_in_unsigned_long() */
1268 static i386_operand_type
1269 smallest_imm_type (offsetT num)
1271 i386_operand_type t;
1274 t.bitfield.imm64 = 1;
1276 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1278 /* This code is disabled on the 486 because all the Imm1 forms
1279 in the opcode table are slower on the i486. They're the
1280 versions with the implicitly specified single-position
1281 displacement, which has another syntax if you really want to
1283 t.bitfield.imm1 = 1;
1284 t.bitfield.imm8 = 1;
1285 t.bitfield.imm8s = 1;
1286 t.bitfield.imm16 = 1;
1287 t.bitfield.imm32 = 1;
1288 t.bitfield.imm32s = 1;
1290 else if (fits_in_signed_byte (num))
1292 t.bitfield.imm8 = 1;
1293 t.bitfield.imm8s = 1;
1294 t.bitfield.imm16 = 1;
1295 t.bitfield.imm32 = 1;
1296 t.bitfield.imm32s = 1;
1298 else if (fits_in_unsigned_byte (num))
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1305 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1311 else if (fits_in_signed_long (num))
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1316 else if (fits_in_unsigned_long (num))
1317 t.bitfield.imm32 = 1;
1323 offset_in_range (offsetT val, int size)
1329 case 1: mask = ((addressT) 1 << 8) - 1; break;
1330 case 2: mask = ((addressT) 1 << 16) - 1; break;
1331 case 4: mask = ((addressT) 2 << 31) - 1; break;
1333 case 8: mask = ((addressT) 2 << 63) - 1; break;
1338 /* If BFD64, sign extend val. */
1339 if (!use_rela_relocations)
1340 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1341 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1343 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1345 char buf1[40], buf2[40];
1347 sprint_value (buf1, val);
1348 sprint_value (buf2, val & mask);
1349 as_warn (_("%s shortened to %s"), buf1, buf2);
1354 /* Returns 0 if attempting to add a prefix where one from the same
1355 class already exists, 1 if non rep/repne added, 2 if rep/repne
1358 add_prefix (unsigned int prefix)
1363 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1364 && flag_code == CODE_64BIT)
1366 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1367 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1368 && (prefix & (REX_R | REX_X | REX_B))))
1379 case CS_PREFIX_OPCODE:
1380 case DS_PREFIX_OPCODE:
1381 case ES_PREFIX_OPCODE:
1382 case FS_PREFIX_OPCODE:
1383 case GS_PREFIX_OPCODE:
1384 case SS_PREFIX_OPCODE:
1388 case REPNE_PREFIX_OPCODE:
1389 case REPE_PREFIX_OPCODE:
1392 case LOCK_PREFIX_OPCODE:
1400 case ADDR_PREFIX_OPCODE:
1404 case DATA_PREFIX_OPCODE:
1408 if (i.prefix[q] != 0)
1416 i.prefix[q] |= prefix;
1419 as_bad (_("same type of prefix used twice"));
1425 set_code_flag (int value)
1428 if (flag_code == CODE_64BIT)
1430 cpu_arch_flags.bitfield.cpu64 = 1;
1431 cpu_arch_flags.bitfield.cpuno64 = 0;
1435 cpu_arch_flags.bitfield.cpu64 = 0;
1436 cpu_arch_flags.bitfield.cpuno64 = 1;
1438 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1440 as_bad (_("64bit mode not supported on this CPU."));
1442 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1444 as_bad (_("32bit mode not supported on this CPU."));
1446 stackop_size = '\0';
1450 set_16bit_gcc_code_flag (int new_code_flag)
1452 flag_code = new_code_flag;
1453 if (flag_code != CODE_16BIT)
1455 cpu_arch_flags.bitfield.cpu64 = 0;
1456 cpu_arch_flags.bitfield.cpuno64 = 1;
1457 stackop_size = LONG_MNEM_SUFFIX;
1461 set_intel_syntax (int syntax_flag)
1463 /* Find out if register prefixing is specified. */
1464 int ask_naked_reg = 0;
1467 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1469 char *string = input_line_pointer;
1470 int e = get_symbol_end ();
1472 if (strcmp (string, "prefix") == 0)
1474 else if (strcmp (string, "noprefix") == 0)
1477 as_bad (_("bad argument to syntax directive."));
1478 *input_line_pointer = e;
1480 demand_empty_rest_of_line ();
1482 intel_syntax = syntax_flag;
1484 if (ask_naked_reg == 0)
1485 allow_naked_reg = (intel_syntax
1486 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1488 allow_naked_reg = (ask_naked_reg < 0);
1490 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1491 identifier_chars['$'] = intel_syntax ? '$' : 0;
1492 register_prefix = allow_naked_reg ? "" : "%";
1496 set_intel_mnemonic (int mnemonic_flag)
1498 intel_mnemonic = mnemonic_flag;
1502 set_allow_index_reg (int flag)
1504 allow_index_reg = flag;
1508 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1512 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1514 char *string = input_line_pointer;
1515 int e = get_symbol_end ();
1517 i386_cpu_flags flags;
1519 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1521 if (strcmp (string, cpu_arch[i].name) == 0)
1525 cpu_arch_name = cpu_arch[i].name;
1526 cpu_sub_arch_name = NULL;
1527 cpu_arch_flags = cpu_arch[i].flags;
1528 if (flag_code == CODE_64BIT)
1530 cpu_arch_flags.bitfield.cpu64 = 1;
1531 cpu_arch_flags.bitfield.cpuno64 = 0;
1535 cpu_arch_flags.bitfield.cpu64 = 0;
1536 cpu_arch_flags.bitfield.cpuno64 = 1;
1538 cpu_arch_isa = cpu_arch[i].type;
1539 cpu_arch_isa_flags = cpu_arch[i].flags;
1540 if (!cpu_arch_tune_set)
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1548 flags = cpu_flags_or (cpu_arch_flags,
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1552 cpu_sub_arch_name = cpu_arch[i].name;
1553 cpu_arch_flags = flags;
1555 *input_line_pointer = e;
1556 demand_empty_rest_of_line ();
1560 if (i >= ARRAY_SIZE (cpu_arch))
1561 as_bad (_("no such architecture: `%s'"), string);
1563 *input_line_pointer = e;
1566 as_bad (_("missing cpu architecture"));
1568 no_cond_jump_promotion = 0;
1569 if (*input_line_pointer == ','
1570 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1572 char *string = ++input_line_pointer;
1573 int e = get_symbol_end ();
1575 if (strcmp (string, "nojumps") == 0)
1576 no_cond_jump_promotion = 1;
1577 else if (strcmp (string, "jumps") == 0)
1580 as_bad (_("no such architecture modifier: `%s'"), string);
1582 *input_line_pointer = e;
1585 demand_empty_rest_of_line ();
1591 if (!strcmp (default_arch, "x86_64"))
1592 return bfd_mach_x86_64;
1593 else if (!strcmp (default_arch, "i386"))
1594 return bfd_mach_i386_i386;
1596 as_fatal (_("Unknown architecture"));
1602 const char *hash_err;
1604 /* Initialize op_hash hash table. */
1605 op_hash = hash_new ();
1608 const template *optab;
1609 templates *core_optab;
1611 /* Setup for loop. */
1613 core_optab = (templates *) xmalloc (sizeof (templates));
1614 core_optab->start = optab;
1619 if (optab->name == NULL
1620 || strcmp (optab->name, (optab - 1)->name) != 0)
1622 /* different name --> ship out current template list;
1623 add to hash table; & begin anew. */
1624 core_optab->end = optab;
1625 hash_err = hash_insert (op_hash,
1630 as_fatal (_("Internal Error: Can't hash %s: %s"),
1634 if (optab->name == NULL)
1636 core_optab = (templates *) xmalloc (sizeof (templates));
1637 core_optab->start = optab;
1642 /* Initialize reg_hash hash table. */
1643 reg_hash = hash_new ();
1645 const reg_entry *regtab;
1646 unsigned int regtab_size = i386_regtab_size;
1648 for (regtab = i386_regtab; regtab_size--; regtab++)
1650 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1652 as_fatal (_("Internal Error: Can't hash %s: %s"),
1658 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1663 for (c = 0; c < 256; c++)
1668 mnemonic_chars[c] = c;
1669 register_chars[c] = c;
1670 operand_chars[c] = c;
1672 else if (ISLOWER (c))
1674 mnemonic_chars[c] = c;
1675 register_chars[c] = c;
1676 operand_chars[c] = c;
1678 else if (ISUPPER (c))
1680 mnemonic_chars[c] = TOLOWER (c);
1681 register_chars[c] = mnemonic_chars[c];
1682 operand_chars[c] = c;
1685 if (ISALPHA (c) || ISDIGIT (c))
1686 identifier_chars[c] = c;
1689 identifier_chars[c] = c;
1690 operand_chars[c] = c;
1695 identifier_chars['@'] = '@';
1698 identifier_chars['?'] = '?';
1699 operand_chars['?'] = '?';
1701 digit_chars['-'] = '-';
1702 mnemonic_chars['-'] = '-';
1703 mnemonic_chars['.'] = '.';
1704 identifier_chars['_'] = '_';
1705 identifier_chars['.'] = '.';
1707 for (p = operand_special_chars; *p != '\0'; p++)
1708 operand_chars[(unsigned char) *p] = *p;
1711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1714 record_alignment (text_section, 2);
1715 record_alignment (data_section, 2);
1716 record_alignment (bss_section, 2);
1720 if (flag_code == CODE_64BIT)
1722 x86_dwarf2_return_column = 16;
1723 x86_cie_data_alignment = -8;
1727 x86_dwarf2_return_column = 8;
1728 x86_cie_data_alignment = -4;
1733 i386_print_statistics (FILE *file)
1735 hash_print_statistics (file, "i386 opcode", op_hash);
1736 hash_print_statistics (file, "i386 register", reg_hash);
1741 /* Debugging routines for md_assemble. */
1742 static void pte (template *);
1743 static void pt (i386_operand_type);
1744 static void pe (expressionS *);
1745 static void ps (symbolS *);
1748 pi (char *line, i386_insn *x)
1752 fprintf (stdout, "%s: template ", line);
1754 fprintf (stdout, " address: base %s index %s scale %x\n",
1755 x->base_reg ? x->base_reg->reg_name : "none",
1756 x->index_reg ? x->index_reg->reg_name : "none",
1757 x->log2_scale_factor);
1758 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1759 x->rm.mode, x->rm.reg, x->rm.regmem);
1760 fprintf (stdout, " sib: base %x index %x scale %x\n",
1761 x->sib.base, x->sib.index, x->sib.scale);
1762 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1763 (x->rex & REX_W) != 0,
1764 (x->rex & REX_R) != 0,
1765 (x->rex & REX_X) != 0,
1766 (x->rex & REX_B) != 0);
1767 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1768 x->drex.reg, x->drex.rex);
1769 for (i = 0; i < x->operands; i++)
1771 fprintf (stdout, " #%d: ", i + 1);
1773 fprintf (stdout, "\n");
1774 if (x->types[i].bitfield.reg8
1775 || x->types[i].bitfield.reg16
1776 || x->types[i].bitfield.reg32
1777 || x->types[i].bitfield.reg64
1778 || x->types[i].bitfield.regmmx
1779 || x->types[i].bitfield.regxmm
1780 || x->types[i].bitfield.sreg2
1781 || x->types[i].bitfield.sreg3
1782 || x->types[i].bitfield.control
1783 || x->types[i].bitfield.debug
1784 || x->types[i].bitfield.test)
1785 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1786 if (operand_type_check (x->types[i], imm))
1788 if (operand_type_check (x->types[i], disp))
1789 pe (x->op[i].disps);
1797 fprintf (stdout, " %d operands ", t->operands);
1798 fprintf (stdout, "opcode %x ", t->base_opcode);
1799 if (t->extension_opcode != None)
1800 fprintf (stdout, "ext %x ", t->extension_opcode);
1801 if (t->opcode_modifier.d)
1802 fprintf (stdout, "D");
1803 if (t->opcode_modifier.w)
1804 fprintf (stdout, "W");
1805 fprintf (stdout, "\n");
1806 for (i = 0; i < t->operands; i++)
1808 fprintf (stdout, " #%d type ", i + 1);
1809 pt (t->operand_types[i]);
1810 fprintf (stdout, "\n");
1817 fprintf (stdout, " operation %d\n", e->X_op);
1818 fprintf (stdout, " add_number %ld (%lx)\n",
1819 (long) e->X_add_number, (long) e->X_add_number);
1820 if (e->X_add_symbol)
1822 fprintf (stdout, " add_symbol ");
1823 ps (e->X_add_symbol);
1824 fprintf (stdout, "\n");
1828 fprintf (stdout, " op_symbol ");
1829 ps (e->X_op_symbol);
1830 fprintf (stdout, "\n");
1837 fprintf (stdout, "%s type %s%s",
1839 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1840 segment_name (S_GET_SEGMENT (s)));
1843 static struct type_name
1845 i386_operand_type mask;
1848 const type_names[] =
1850 { OPERAND_TYPE_REG8, "r8" },
1851 { OPERAND_TYPE_REG16, "r16" },
1852 { OPERAND_TYPE_REG32, "r32" },
1853 { OPERAND_TYPE_REG64, "r64" },
1854 { OPERAND_TYPE_IMM8, "i8" },
1855 { OPERAND_TYPE_IMM8, "i8s" },
1856 { OPERAND_TYPE_IMM16, "i16" },
1857 { OPERAND_TYPE_IMM32, "i32" },
1858 { OPERAND_TYPE_IMM32S, "i32s" },
1859 { OPERAND_TYPE_IMM64, "i64" },
1860 { OPERAND_TYPE_IMM1, "i1" },
1861 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1862 { OPERAND_TYPE_DISP8, "d8" },
1863 { OPERAND_TYPE_DISP16, "d16" },
1864 { OPERAND_TYPE_DISP32, "d32" },
1865 { OPERAND_TYPE_DISP32S, "d32s" },
1866 { OPERAND_TYPE_DISP64, "d64" },
1867 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1868 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1869 { OPERAND_TYPE_CONTROL, "control reg" },
1870 { OPERAND_TYPE_TEST, "test reg" },
1871 { OPERAND_TYPE_DEBUG, "debug reg" },
1872 { OPERAND_TYPE_FLOATREG, "FReg" },
1873 { OPERAND_TYPE_FLOATACC, "FAcc" },
1874 { OPERAND_TYPE_SREG2, "SReg2" },
1875 { OPERAND_TYPE_SREG3, "SReg3" },
1876 { OPERAND_TYPE_ACC, "Acc" },
1877 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1878 { OPERAND_TYPE_REGMMX, "rMMX" },
1879 { OPERAND_TYPE_REGXMM, "rXMM" },
1880 { OPERAND_TYPE_ESSEG, "es" },
1884 pt (i386_operand_type t)
1887 i386_operand_type a;
1889 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1891 a = operand_type_and (t, type_names[j].mask);
1892 if (!UINTS_ALL_ZERO (a))
1893 fprintf (stdout, "%s, ", type_names[j].name);
1898 #endif /* DEBUG386 */
1900 static bfd_reloc_code_real_type
1901 reloc (unsigned int size,
1904 bfd_reloc_code_real_type other)
1906 if (other != NO_RELOC)
1908 reloc_howto_type *reloc;
1913 case BFD_RELOC_X86_64_GOT32:
1914 return BFD_RELOC_X86_64_GOT64;
1916 case BFD_RELOC_X86_64_PLTOFF64:
1917 return BFD_RELOC_X86_64_PLTOFF64;
1919 case BFD_RELOC_X86_64_GOTPC32:
1920 other = BFD_RELOC_X86_64_GOTPC64;
1922 case BFD_RELOC_X86_64_GOTPCREL:
1923 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 case BFD_RELOC_X86_64_TPOFF32:
1926 other = BFD_RELOC_X86_64_TPOFF64;
1928 case BFD_RELOC_X86_64_DTPOFF32:
1929 other = BFD_RELOC_X86_64_DTPOFF64;
1935 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1936 if (size == 4 && flag_code != CODE_64BIT)
1939 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 as_bad (_("unknown relocation (%u)"), other);
1942 else if (size != bfd_get_reloc_size (reloc))
1943 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1944 bfd_get_reloc_size (reloc),
1946 else if (pcrel && !reloc->pc_relative)
1947 as_bad (_("non-pc-relative relocation for pc-relative field"));
1948 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 || (reloc->complain_on_overflow == complain_overflow_unsigned
1952 as_bad (_("relocated field and relocation type differ in signedness"));
1961 as_bad (_("there are no unsigned pc-relative relocations"));
1964 case 1: return BFD_RELOC_8_PCREL;
1965 case 2: return BFD_RELOC_16_PCREL;
1966 case 4: return BFD_RELOC_32_PCREL;
1967 case 8: return BFD_RELOC_64_PCREL;
1969 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1976 case 4: return BFD_RELOC_X86_64_32S;
1981 case 1: return BFD_RELOC_8;
1982 case 2: return BFD_RELOC_16;
1983 case 4: return BFD_RELOC_32;
1984 case 8: return BFD_RELOC_64;
1986 as_bad (_("cannot do %s %u byte relocation"),
1987 sign > 0 ? "signed" : "unsigned", size);
1991 return BFD_RELOC_NONE;
1994 /* Here we decide which fixups can be adjusted to make them relative to
1995 the beginning of the section instead of the symbol. Basically we need
1996 to make sure that the dynamic relocations are done correctly, so in
1997 some cases we force the original symbol to be used. */
2000 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2006 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 if (use_rela_relocations
2009 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2013 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2014 and changed later by validate_fix. */
2015 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2016 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2019 /* adjust_reloc_syms doesn't know about the GOT. */
2020 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2021 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2022 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2023 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2033 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2040 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2046 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2054 intel_float_operand (const char *mnemonic)
2056 /* Note that the value returned is meaningful only for opcodes with (memory)
2057 operands, hence the code here is free to improperly handle opcodes that
2058 have no operands (for better performance and smaller code). */
2060 if (mnemonic[0] != 'f')
2061 return 0; /* non-math */
2063 switch (mnemonic[1])
2065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2066 the fs segment override prefix not currently handled because no
2067 call path can make opcodes without operands get here */
2069 return 2 /* integer op */;
2071 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2072 return 3; /* fldcw/fldenv */
2075 if (mnemonic[2] != 'o' /* fnop */)
2076 return 3; /* non-waiting control op */
2079 if (mnemonic[2] == 's')
2080 return 3; /* frstor/frstpm */
2083 if (mnemonic[2] == 'a')
2084 return 3; /* fsave */
2085 if (mnemonic[2] == 't')
2087 switch (mnemonic[3])
2089 case 'c': /* fstcw */
2090 case 'd': /* fstdw */
2091 case 'e': /* fstenv */
2092 case 's': /* fsts[gw] */
2098 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2099 return 0; /* fxsave/fxrstor are not really math ops */
2106 /* This is the guts of the machine-dependent assembler. LINE points to a
2107 machine dependent instruction. This function is supposed to emit
2108 the frags/bytes it assembles to. */
2115 char mnemonic[MAX_MNEM_SIZE];
2117 /* Initialize globals. */
2118 memset (&i, '\0', sizeof (i));
2119 for (j = 0; j < MAX_OPERANDS; j++)
2120 i.reloc[j] = NO_RELOC;
2121 memset (disp_expressions, '\0', sizeof (disp_expressions));
2122 memset (im_expressions, '\0', sizeof (im_expressions));
2123 save_stack_p = save_stack;
2125 /* First parse an instruction mnemonic & call i386_operand for the operands.
2126 We assume that the scrubber has arranged it so that line[0] is the valid
2127 start of a (possibly prefixed) mnemonic. */
2129 line = parse_insn (line, mnemonic);
2133 line = parse_operands (line, mnemonic);
2137 /* Now we've parsed the mnemonic into a set of templates, and have the
2138 operands at hand. */
2140 /* All intel opcodes have reversed operands except for "bound" and
2141 "enter". We also don't reverse intersegment "jmp" and "call"
2142 instructions with 2 immediate operands so that the immediate segment
2143 precedes the offset, as it does when in AT&T mode. */
2146 && (strcmp (mnemonic, "bound") != 0)
2147 && (strcmp (mnemonic, "invlpga") != 0)
2148 && !(operand_type_check (i.types[0], imm)
2149 && operand_type_check (i.types[1], imm)))
2152 /* The order of the immediates should be reversed
2153 for 2 immediates extrq and insertq instructions */
2154 if (i.imm_operands == 2
2155 && (strcmp (mnemonic, "extrq") == 0
2156 || strcmp (mnemonic, "insertq") == 0))
2157 swap_2_operands (0, 1);
2162 /* Don't optimize displacement for movabs since it only takes 64bit
2165 && (flag_code != CODE_64BIT
2166 || strcmp (mnemonic, "movabs") != 0))
2169 /* Next, we find a template that matches the given insn,
2170 making sure the overlap of the given operands types is consistent
2171 with the template operand types. */
2173 if (!match_template ())
2178 /* Zap movzx and movsx suffix. The suffix may have been set from
2179 "word ptr" or "byte ptr" on the source operand, but we'll use
2180 the suffix later to choose the destination register. */
2181 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2183 if (i.reg_operands < 2
2185 && (!i.tm.opcode_modifier.no_bsuf
2186 || !i.tm.opcode_modifier.no_wsuf
2187 || !i.tm.opcode_modifier.no_lsuf
2188 || !i.tm.opcode_modifier.no_ssuf
2189 || !i.tm.opcode_modifier.no_ldsuf
2190 || !i.tm.opcode_modifier.no_qsuf))
2191 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2197 if (i.tm.opcode_modifier.fwait)
2198 if (!add_prefix (FWAIT_OPCODE))
2201 /* Check string instruction segment overrides. */
2202 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2204 if (!check_string ())
2208 if (!process_suffix ())
2211 /* Make still unresolved immediate matches conform to size of immediate
2212 given in i.suffix. */
2213 if (!finalize_imm ())
2216 if (i.types[0].bitfield.imm1)
2217 i.imm_operands = 0; /* kludge for shift insns. */
2219 for (j = 0; j < 3; j++)
2220 if (i.types[j].bitfield.inoutportreg
2221 || i.types[j].bitfield.shiftcount
2222 || i.types[j].bitfield.acc
2223 || i.types[j].bitfield.floatacc)
2226 if (i.tm.opcode_modifier.immext)
2230 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2232 /* Streaming SIMD extensions 3 Instructions have the fixed
2233 operands with an opcode suffix which is coded in the same
2234 place as an 8-bit immediate field would be. Here we check
2235 those operands and remove them afterwards. */
2238 for (x = 0; x < i.operands; x++)
2239 if (i.op[x].regs->reg_num != x)
2240 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2242 i.op[x].regs->reg_name,
2248 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2249 opcode suffix which is coded in the same place as an 8-bit
2250 immediate field would be. Here we fake an 8-bit immediate
2251 operand from the opcode suffix stored in tm.extension_opcode.
2252 SSE5 also uses this encoding, for some of its 3 argument
2255 assert (i.imm_operands == 0
2257 || (i.tm.cpu_flags.bitfield.cpusse5
2258 && i.operands <= 3)));
2260 exp = &im_expressions[i.imm_operands++];
2261 i.op[i.operands].imms = exp;
2262 UINTS_CLEAR (i.types[i.operands]);
2263 i.types[i.operands].bitfield.imm8 = 1;
2265 exp->X_op = O_constant;
2266 exp->X_add_number = i.tm.extension_opcode;
2267 i.tm.extension_opcode = None;
2270 /* For insns with operands there are more diddles to do to the opcode. */
2273 if (!process_operands ())
2276 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2278 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2279 as_warn (_("translating to `%sp'"), i.tm.name);
2282 /* Handle conversion of 'int $3' --> special int3 insn. */
2283 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2285 i.tm.base_opcode = INT3_OPCODE;
2289 if ((i.tm.opcode_modifier.jump
2290 || i.tm.opcode_modifier.jumpbyte
2291 || i.tm.opcode_modifier.jumpdword)
2292 && i.op[0].disps->X_op == O_constant)
2294 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2295 the absolute address given by the constant. Since ix86 jumps and
2296 calls are pc relative, we need to generate a reloc. */
2297 i.op[0].disps->X_add_symbol = &abs_symbol;
2298 i.op[0].disps->X_op = O_symbol;
2301 if (i.tm.opcode_modifier.rex64)
2304 /* For 8 bit registers we need an empty rex prefix. Also if the
2305 instruction already has a prefix, we need to convert old
2306 registers to new ones. */
2308 if ((i.types[0].bitfield.reg8
2309 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2310 || (i.types[1].bitfield.reg8
2311 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2312 || ((i.types[0].bitfield.reg8
2313 || i.types[1].bitfield.reg8)
2318 i.rex |= REX_OPCODE;
2319 for (x = 0; x < 2; x++)
2321 /* Look for 8 bit operand that uses old registers. */
2322 if (i.types[x].bitfield.reg8
2323 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2325 /* In case it is "hi" register, give up. */
2326 if (i.op[x].regs->reg_num > 3)
2327 as_bad (_("can't encode register '%s%s' in an "
2328 "instruction requiring REX prefix."),
2329 register_prefix, i.op[x].regs->reg_name);
2331 /* Otherwise it is equivalent to the extended register.
2332 Since the encoding doesn't change this is merely
2333 cosmetic cleanup for debug output. */
2335 i.op[x].regs = i.op[x].regs + 8;
2340 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2342 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2347 else if (i.rex != 0)
2348 add_prefix (REX_OPCODE | i.rex);
2350 /* We are ready to output the insn. */
2355 parse_insn (char *line, char *mnemonic)
2358 char *token_start = l;
2363 /* Non-zero if we found a prefix only acceptable with string insns. */
2364 const char *expecting_string_instruction = NULL;
2369 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2372 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2374 as_bad (_("no such instruction: `%s'"), token_start);
2379 if (!is_space_char (*l)
2380 && *l != END_OF_INSN
2382 || (*l != PREFIX_SEPARATOR
2385 as_bad (_("invalid character %s in mnemonic"),
2386 output_invalid (*l));
2389 if (token_start == l)
2391 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2392 as_bad (_("expecting prefix; got nothing"));
2394 as_bad (_("expecting mnemonic; got nothing"));
2398 /* Look up instruction (or prefix) via hash table. */
2399 current_templates = hash_find (op_hash, mnemonic);
2401 if (*l != END_OF_INSN
2402 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2403 && current_templates
2404 && current_templates->start->opcode_modifier.isprefix)
2406 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2408 as_bad ((flag_code != CODE_64BIT
2409 ? _("`%s' is only supported in 64-bit mode")
2410 : _("`%s' is not supported in 64-bit mode")),
2411 current_templates->start->name);
2414 /* If we are in 16-bit mode, do not allow addr16 or data16.
2415 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2416 if ((current_templates->start->opcode_modifier.size16
2417 || current_templates->start->opcode_modifier.size32)
2418 && flag_code != CODE_64BIT
2419 && (current_templates->start->opcode_modifier.size32
2420 ^ (flag_code == CODE_16BIT)))
2422 as_bad (_("redundant %s prefix"),
2423 current_templates->start->name);
2426 /* Add prefix, checking for repeated prefixes. */
2427 switch (add_prefix (current_templates->start->base_opcode))
2432 expecting_string_instruction = current_templates->start->name;
2435 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2442 if (!current_templates)
2444 /* See if we can get a match by trimming off a suffix. */
2447 case WORD_MNEM_SUFFIX:
2448 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2449 i.suffix = SHORT_MNEM_SUFFIX;
2451 case BYTE_MNEM_SUFFIX:
2452 case QWORD_MNEM_SUFFIX:
2453 i.suffix = mnem_p[-1];
2455 current_templates = hash_find (op_hash, mnemonic);
2457 case SHORT_MNEM_SUFFIX:
2458 case LONG_MNEM_SUFFIX:
2461 i.suffix = mnem_p[-1];
2463 current_templates = hash_find (op_hash, mnemonic);
2471 if (intel_float_operand (mnemonic) == 1)
2472 i.suffix = SHORT_MNEM_SUFFIX;
2474 i.suffix = LONG_MNEM_SUFFIX;
2476 current_templates = hash_find (op_hash, mnemonic);
2480 if (!current_templates)
2482 as_bad (_("no such instruction: `%s'"), token_start);
2487 if (current_templates->start->opcode_modifier.jump
2488 || current_templates->start->opcode_modifier.jumpbyte)
2490 /* Check for a branch hint. We allow ",pt" and ",pn" for
2491 predict taken and predict not taken respectively.
2492 I'm not sure that branch hints actually do anything on loop
2493 and jcxz insns (JumpByte) for current Pentium4 chips. They
2494 may work in the future and it doesn't hurt to accept them
2496 if (l[0] == ',' && l[1] == 'p')
2500 if (!add_prefix (DS_PREFIX_OPCODE))
2504 else if (l[2] == 'n')
2506 if (!add_prefix (CS_PREFIX_OPCODE))
2512 /* Any other comma loses. */
2515 as_bad (_("invalid character %s in mnemonic"),
2516 output_invalid (*l));
2520 /* Check if instruction is supported on specified architecture. */
2522 for (t = current_templates->start; t < current_templates->end; ++t)
2524 supported |= cpu_flags_match (t->cpu_flags);
2529 if (!(supported & 2))
2531 as_bad (flag_code == CODE_64BIT
2532 ? _("`%s' is not supported in 64-bit mode")
2533 : _("`%s' is only supported in 64-bit mode"),
2534 current_templates->start->name);
2537 if (!(supported & 1))
2539 as_bad (_("`%s' is not supported on `%s%s'"),
2540 current_templates->start->name, cpu_arch_name,
2541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2546 if (!cpu_arch_flags.bitfield.cpui386
2547 && (flag_code != CODE_16BIT))
2549 as_warn (_("use .code16 to ensure correct addressing mode"));
2552 /* Check for rep/repne without a string instruction. */
2553 if (expecting_string_instruction)
2555 static templates override;
2557 for (t = current_templates->start; t < current_templates->end; ++t)
2558 if (t->opcode_modifier.isstring)
2560 if (t >= current_templates->end)
2562 as_bad (_("expecting string instruction after `%s'"),
2563 expecting_string_instruction);
2566 for (override.start = t; t < current_templates->end; ++t)
2567 if (!t->opcode_modifier.isstring)
2570 current_templates = &override;
2577 parse_operands (char *l, const char *mnemonic)
2581 /* 1 if operand is pending after ','. */
2582 unsigned int expecting_operand = 0;
2584 /* Non-zero if operand parens not balanced. */
2585 unsigned int paren_not_balanced;
2587 while (*l != END_OF_INSN)
2589 /* Skip optional white space before operand. */
2590 if (is_space_char (*l))
2592 if (!is_operand_char (*l) && *l != END_OF_INSN)
2594 as_bad (_("invalid character %s before operand %d"),
2595 output_invalid (*l),
2599 token_start = l; /* after white space */
2600 paren_not_balanced = 0;
2601 while (paren_not_balanced || *l != ',')
2603 if (*l == END_OF_INSN)
2605 if (paren_not_balanced)
2608 as_bad (_("unbalanced parenthesis in operand %d."),
2611 as_bad (_("unbalanced brackets in operand %d."),
2616 break; /* we are done */
2618 else if (!is_operand_char (*l) && !is_space_char (*l))
2620 as_bad (_("invalid character %s in operand %d"),
2621 output_invalid (*l),
2628 ++paren_not_balanced;
2630 --paren_not_balanced;
2635 ++paren_not_balanced;
2637 --paren_not_balanced;
2641 if (l != token_start)
2642 { /* Yes, we've read in another operand. */
2643 unsigned int operand_ok;
2644 this_operand = i.operands++;
2645 if (i.operands > MAX_OPERANDS)
2647 as_bad (_("spurious operands; (%d operands/instruction max)"),
2651 /* Now parse operand adding info to 'i' as we go along. */
2652 END_STRING_AND_SAVE (l);
2656 i386_intel_operand (token_start,
2657 intel_float_operand (mnemonic));
2659 operand_ok = i386_operand (token_start);
2661 RESTORE_END_STRING (l);
2667 if (expecting_operand)
2669 expecting_operand_after_comma:
2670 as_bad (_("expecting operand after ','; got nothing"));
2675 as_bad (_("expecting operand before ','; got nothing"));
2680 /* Now *l must be either ',' or END_OF_INSN. */
2683 if (*++l == END_OF_INSN)
2685 /* Just skip it, if it's \n complain. */
2686 goto expecting_operand_after_comma;
2688 expecting_operand = 1;
2695 swap_2_operands (int xchg1, int xchg2)
2697 union i386_op temp_op;
2698 i386_operand_type temp_type;
2699 enum bfd_reloc_code_real temp_reloc;
2701 temp_type = i.types[xchg2];
2702 i.types[xchg2] = i.types[xchg1];
2703 i.types[xchg1] = temp_type;
2704 temp_op = i.op[xchg2];
2705 i.op[xchg2] = i.op[xchg1];
2706 i.op[xchg1] = temp_op;
2707 temp_reloc = i.reloc[xchg2];
2708 i.reloc[xchg2] = i.reloc[xchg1];
2709 i.reloc[xchg1] = temp_reloc;
2713 swap_operands (void)
2718 swap_2_operands (1, i.operands - 2);
2721 swap_2_operands (0, i.operands - 1);
2727 if (i.mem_operands == 2)
2729 const seg_entry *temp_seg;
2730 temp_seg = i.seg[0];
2731 i.seg[0] = i.seg[1];
2732 i.seg[1] = temp_seg;
2736 /* Try to ensure constant immediates are represented in the smallest
2741 char guess_suffix = 0;
2745 guess_suffix = i.suffix;
2746 else if (i.reg_operands)
2748 /* Figure out a suffix from the last register operand specified.
2749 We can't do this properly yet, ie. excluding InOutPortReg,
2750 but the following works for instructions with immediates.
2751 In any case, we can't set i.suffix yet. */
2752 for (op = i.operands; --op >= 0;)
2753 if (i.types[op].bitfield.reg8)
2755 guess_suffix = BYTE_MNEM_SUFFIX;
2758 else if (i.types[op].bitfield.reg16)
2760 guess_suffix = WORD_MNEM_SUFFIX;
2763 else if (i.types[op].bitfield.reg32)
2765 guess_suffix = LONG_MNEM_SUFFIX;
2768 else if (i.types[op].bitfield.reg64)
2770 guess_suffix = QWORD_MNEM_SUFFIX;
2774 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2775 guess_suffix = WORD_MNEM_SUFFIX;
2777 for (op = i.operands; --op >= 0;)
2778 if (operand_type_check (i.types[op], imm))
2780 switch (i.op[op].imms->X_op)
2783 /* If a suffix is given, this operand may be shortened. */
2784 switch (guess_suffix)
2786 case LONG_MNEM_SUFFIX:
2787 i.types[op].bitfield.imm32 = 1;
2788 i.types[op].bitfield.imm64 = 1;
2790 case WORD_MNEM_SUFFIX:
2791 i.types[op].bitfield.imm16 = 1;
2792 i.types[op].bitfield.imm32 = 1;
2793 i.types[op].bitfield.imm32s = 1;
2794 i.types[op].bitfield.imm64 = 1;
2796 case BYTE_MNEM_SUFFIX:
2797 i.types[op].bitfield.imm8 = 1;
2798 i.types[op].bitfield.imm8s = 1;
2799 i.types[op].bitfield.imm16 = 1;
2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm32s = 1;
2802 i.types[op].bitfield.imm64 = 1;
2806 /* If this operand is at most 16 bits, convert it
2807 to a signed 16 bit number before trying to see
2808 whether it will fit in an even smaller size.
2809 This allows a 16-bit operand such as $0xffe0 to
2810 be recognised as within Imm8S range. */
2811 if ((i.types[op].bitfield.imm16)
2812 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2814 i.op[op].imms->X_add_number =
2815 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2817 if ((i.types[op].bitfield.imm32)
2818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2822 ^ ((offsetT) 1 << 31))
2823 - ((offsetT) 1 << 31));
2826 = operand_type_or (i.types[op],
2827 smallest_imm_type (i.op[op].imms->X_add_number));
2829 /* We must avoid matching of Imm32 templates when 64bit
2830 only immediate is available. */
2831 if (guess_suffix == QWORD_MNEM_SUFFIX)
2832 i.types[op].bitfield.imm32 = 0;
2839 /* Symbols and expressions. */
2841 /* Convert symbolic operand to proper sizes for matching, but don't
2842 prevent matching a set of insns that only supports sizes other
2843 than those matching the insn suffix. */
2845 i386_operand_type mask, allowed;
2849 UINTS_CLEAR (allowed);
2851 for (t = current_templates->start;
2852 t < current_templates->end;
2854 allowed = operand_type_or (allowed,
2855 t->operand_types[op]);
2856 switch (guess_suffix)
2858 case QWORD_MNEM_SUFFIX:
2859 mask.bitfield.imm64 = 1;
2860 mask.bitfield.imm32s = 1;
2862 case LONG_MNEM_SUFFIX:
2863 mask.bitfield.imm32 = 1;
2865 case WORD_MNEM_SUFFIX:
2866 mask.bitfield.imm16 = 1;
2868 case BYTE_MNEM_SUFFIX:
2869 mask.bitfield.imm8 = 1;
2874 allowed = operand_type_and (mask, allowed);
2875 if (!UINTS_ALL_ZERO (allowed))
2876 i.types[op] = operand_type_and (i.types[op], mask);
2883 /* Try to use the smallest displacement type too. */
2885 optimize_disp (void)
2889 for (op = i.operands; --op >= 0;)
2890 if (operand_type_check (i.types[op], disp))
2892 if (i.op[op].disps->X_op == O_constant)
2894 offsetT disp = i.op[op].disps->X_add_number;
2896 if (i.types[op].bitfield.disp16
2897 && (disp & ~(offsetT) 0xffff) == 0)
2899 /* If this operand is at most 16 bits, convert
2900 to a signed 16 bit number and don't use 64bit
2902 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2903 i.types[op].bitfield.disp64 = 0;
2905 if (i.types[op].bitfield.disp32
2906 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2908 /* If this operand is at most 32 bits, convert
2909 to a signed 32 bit number and don't use 64bit
2911 disp &= (((offsetT) 2 << 31) - 1);
2912 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2913 i.types[op].bitfield.disp64 = 0;
2915 if (!disp && i.types[op].bitfield.baseindex)
2917 i.types[op].bitfield.disp8 = 0;
2918 i.types[op].bitfield.disp16 = 0;
2919 i.types[op].bitfield.disp32 = 0;
2920 i.types[op].bitfield.disp32s = 0;
2921 i.types[op].bitfield.disp64 = 0;
2925 else if (flag_code == CODE_64BIT)
2927 if (fits_in_signed_long (disp))
2929 i.types[op].bitfield.disp64 = 0;
2930 i.types[op].bitfield.disp32s = 1;
2932 if (fits_in_unsigned_long (disp))
2933 i.types[op].bitfield.disp32 = 1;
2935 if ((i.types[op].bitfield.disp32
2936 || i.types[op].bitfield.disp32s
2937 || i.types[op].bitfield.disp16)
2938 && fits_in_signed_byte (disp))
2939 i.types[op].bitfield.disp8 = 1;
2941 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2942 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2944 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2945 i.op[op].disps, 0, i.reloc[op]);
2946 i.types[op].bitfield.disp8 = 0;
2947 i.types[op].bitfield.disp16 = 0;
2948 i.types[op].bitfield.disp32 = 0;
2949 i.types[op].bitfield.disp32s = 0;
2950 i.types[op].bitfield.disp64 = 0;
2953 /* We only support 64bit displacement on constants. */
2954 i.types[op].bitfield.disp64 = 0;
2959 match_template (void)
2961 /* Points to template once we've found it. */
2963 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2964 unsigned int found_reverse_match;
2965 i386_opcode_modifier suffix_check;
2966 i386_operand_type operand_types [MAX_OPERANDS];
2967 int addr_prefix_disp;
2969 unsigned int found_cpu_match;
2971 #if MAX_OPERANDS != 4
2972 # error "MAX_OPERANDS must be 4."
2975 found_reverse_match = 0;
2976 addr_prefix_disp = -1;
2978 memset (&suffix_check, 0, sizeof (suffix_check));
2979 if (i.suffix == BYTE_MNEM_SUFFIX)
2980 suffix_check.no_bsuf = 1;
2981 else if (i.suffix == WORD_MNEM_SUFFIX)
2982 suffix_check.no_wsuf = 1;
2983 else if (i.suffix == SHORT_MNEM_SUFFIX)
2984 suffix_check.no_ssuf = 1;
2985 else if (i.suffix == LONG_MNEM_SUFFIX)
2986 suffix_check.no_lsuf = 1;
2987 else if (i.suffix == QWORD_MNEM_SUFFIX)
2988 suffix_check.no_qsuf = 1;
2989 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2990 suffix_check.no_ldsuf = 1;
2991 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
2992 suffix_check.xmmword = 1;
2994 for (t = current_templates->start; t < current_templates->end; t++)
2996 addr_prefix_disp = -1;
2998 /* Must have right number of operands. */
2999 if (i.operands != t->operands)
3002 /* Check old gcc support. */
3003 if (!old_gcc && t->opcode_modifier.oldgcc)
3006 /* Check AT&T mnemonic. */
3007 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3010 /* Check Intel syntax. */
3011 if (intel_syntax && t->opcode_modifier.attsyntax)
3014 /* Check the suffix, except for some instructions in intel mode. */
3015 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3016 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3017 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3018 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3019 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3020 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3021 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3024 /* Check the memory size in Intel mode when it is provided if
3028 && t->opcode_modifier.checksize
3029 && (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
3030 && (!t->opcode_modifier.word || !suffix_check.no_wsuf)
3031 && (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
3032 && (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
3033 && (!t->opcode_modifier.xmmword || !suffix_check.xmmword))
3036 for (j = 0; j < MAX_OPERANDS; j++)
3037 operand_types [j] = t->operand_types [j];
3039 /* In general, don't allow 64-bit operands in 32-bit mode. */
3040 if (i.suffix == QWORD_MNEM_SUFFIX
3041 && flag_code != CODE_64BIT
3043 ? (!t->opcode_modifier.ignoresize
3044 && !intel_float_operand (t->name))
3045 : intel_float_operand (t->name) != 2)
3046 && ((!operand_types[0].bitfield.regmmx
3047 && !operand_types[0].bitfield.regxmm)
3048 || (!operand_types[t->operands > 1].bitfield.regmmx
3049 && !!operand_types[t->operands > 1].bitfield.regxmm))
3050 && (t->base_opcode != 0x0fc7
3051 || t->extension_opcode != 1 /* cmpxchg8b */))
3054 /* Do not verify operands when there are none. */
3057 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3060 if (!found_cpu_match)
3062 /* We've found a match; break out of loop. */
3067 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3068 into Disp32/Disp16/Disp32 operand. */
3069 if (i.prefix[ADDR_PREFIX] != 0)
3071 /* There should be only one Disp operand. */
3075 for (j = 0; j < MAX_OPERANDS; j++)
3077 if (operand_types[j].bitfield.disp16)
3079 addr_prefix_disp = j;
3080 operand_types[j].bitfield.disp32 = 1;
3081 operand_types[j].bitfield.disp16 = 0;
3087 for (j = 0; j < MAX_OPERANDS; j++)
3089 if (operand_types[j].bitfield.disp32)
3091 addr_prefix_disp = j;
3092 operand_types[j].bitfield.disp32 = 0;
3093 operand_types[j].bitfield.disp16 = 1;
3099 for (j = 0; j < MAX_OPERANDS; j++)
3101 if (operand_types[j].bitfield.disp64)
3103 addr_prefix_disp = j;
3104 operand_types[j].bitfield.disp64 = 0;
3105 operand_types[j].bitfield.disp32 = 1;
3113 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3114 switch (t->operands)
3117 if (!operand_type_match (overlap0, i.types[0]))
3121 /* xchg %eax, %eax is a special case. It is an aliase for nop
3122 only in 32bit mode and we can use opcode 0x90. In 64bit
3123 mode, we can't use 0x90 for xchg %eax, %eax since it should
3124 zero-extend %eax to %rax. */
3125 if (flag_code == CODE_64BIT
3126 && t->base_opcode == 0x90
3127 && UINTS_EQUAL (i.types [0], acc32)
3128 && UINTS_EQUAL (i.types [1], acc32))
3132 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3133 if (!operand_type_match (overlap0, i.types[0])
3134 || !operand_type_match (overlap1, i.types[1])
3135 /* monitor in SSE3 is a very special case. The first
3136 register and the second register may have different
3137 sizes. The same applies to crc32 in SSE4.2. It is
3138 also true for invlpga, vmload, vmrun and vmsave in
3140 || !((t->base_opcode == 0x0f01
3141 && (t->extension_opcode == 0xc8
3142 || t->extension_opcode == 0xd8
3143 || t->extension_opcode == 0xda
3144 || t->extension_opcode == 0xdb
3145 || t->extension_opcode == 0xdf))
3146 || t->base_opcode == 0xf20f38f1
3147 || operand_type_register_match (overlap0, i.types[0],
3149 overlap1, i.types[1],
3152 /* Check if other direction is valid ... */
3153 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3156 /* Try reversing direction of operands. */
3157 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3158 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3159 if (!operand_type_match (overlap0, i.types[0])
3160 || !operand_type_match (overlap1, i.types[1])
3161 || !operand_type_register_match (overlap0, i.types[0],
3163 overlap1, i.types[1],
3166 /* Does not match either direction. */
3169 /* found_reverse_match holds which of D or FloatDR
3171 if (t->opcode_modifier.d)
3172 found_reverse_match = Opcode_D;
3173 else if (t->opcode_modifier.floatd)
3174 found_reverse_match = Opcode_FloatD;
3176 found_reverse_match = 0;
3177 if (t->opcode_modifier.floatr)
3178 found_reverse_match |= Opcode_FloatR;
3182 /* Found a forward 2 operand match here. */
3183 switch (t->operands)
3186 overlap3 = operand_type_and (i.types[3],
3189 overlap2 = operand_type_and (i.types[2],
3194 switch (t->operands)
3197 if (!operand_type_match (overlap3, i.types[3])
3198 || !operand_type_register_match (overlap2,
3206 /* Here we make use of the fact that there are no
3207 reverse match 3 operand instructions, and all 3
3208 operand instructions only need to be checked for
3209 register consistency between operands 2 and 3. */
3210 if (!operand_type_match (overlap2, i.types[2])
3211 || !operand_type_register_match (overlap1,
3221 /* Found either forward/reverse 2, 3 or 4 operand match here:
3222 slip through to break. */
3224 if (!found_cpu_match)
3226 found_reverse_match = 0;
3229 /* We've found a match; break out of loop. */
3233 if (t == current_templates->end)
3235 /* We found no match. */
3236 as_bad (_("suffix or operands invalid for `%s'"),
3237 current_templates->start->name);
3241 if (!quiet_warnings)
3244 && (i.types[0].bitfield.jumpabsolute
3245 != operand_types[0].bitfield.jumpabsolute))
3247 as_warn (_("indirect %s without `*'"), t->name);
3250 if (t->opcode_modifier.isprefix
3251 && t->opcode_modifier.ignoresize)
3253 /* Warn them that a data or address size prefix doesn't
3254 affect assembly of the next line of code. */
3255 as_warn (_("stand-alone `%s' prefix"), t->name);
3259 /* Copy the template we found. */
3262 if (addr_prefix_disp != -1)
3263 i.tm.operand_types[addr_prefix_disp]
3264 = operand_types[addr_prefix_disp];
3266 if (found_reverse_match)
3268 /* If we found a reverse match we must alter the opcode
3269 direction bit. found_reverse_match holds bits to change
3270 (different for int & float insns). */
3272 i.tm.base_opcode ^= found_reverse_match;
3274 i.tm.operand_types[0] = operand_types[1];
3275 i.tm.operand_types[1] = operand_types[0];
3284 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3285 if (i.tm.operand_types[mem_op].bitfield.esseg)
3287 if (i.seg[0] != NULL && i.seg[0] != &es)
3289 as_bad (_("`%s' operand %d must use `%%es' segment"),
3294 /* There's only ever one segment override allowed per instruction.
3295 This instruction possibly has a legal segment override on the
3296 second operand, so copy the segment to where non-string
3297 instructions store it, allowing common code. */
3298 i.seg[0] = i.seg[1];
3300 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3302 if (i.seg[1] != NULL && i.seg[1] != &es)
3304 as_bad (_("`%s' operand %d must use `%%es' segment"),
3314 process_suffix (void)
3316 /* If matched instruction specifies an explicit instruction mnemonic
3318 if (i.tm.opcode_modifier.size16)
3319 i.suffix = WORD_MNEM_SUFFIX;
3320 else if (i.tm.opcode_modifier.size32)
3321 i.suffix = LONG_MNEM_SUFFIX;
3322 else if (i.tm.opcode_modifier.size64)
3323 i.suffix = QWORD_MNEM_SUFFIX;
3324 else if (i.reg_operands)
3326 /* If there's no instruction mnemonic suffix we try to invent one
3327 based on register operands. */
3330 /* We take i.suffix from the last register operand specified,
3331 Destination register type is more significant than source
3332 register type. crc32 in SSE4.2 prefers source register
3334 if (i.tm.base_opcode == 0xf20f38f1)
3336 if (i.types[0].bitfield.reg16)
3337 i.suffix = WORD_MNEM_SUFFIX;
3338 else if (i.types[0].bitfield.reg32)
3339 i.suffix = LONG_MNEM_SUFFIX;
3340 else if (i.types[0].bitfield.reg64)
3341 i.suffix = QWORD_MNEM_SUFFIX;
3343 else if (i.tm.base_opcode == 0xf20f38f0)
3345 if (i.types[0].bitfield.reg8)
3346 i.suffix = BYTE_MNEM_SUFFIX;
3353 if (i.tm.base_opcode == 0xf20f38f1
3354 || i.tm.base_opcode == 0xf20f38f0)
3356 /* We have to know the operand size for crc32. */
3357 as_bad (_("ambiguous memory operand size for `%s`"),
3362 for (op = i.operands; --op >= 0;)
3363 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3365 if (i.types[op].bitfield.reg8)
3367 i.suffix = BYTE_MNEM_SUFFIX;
3370 else if (i.types[op].bitfield.reg16)
3372 i.suffix = WORD_MNEM_SUFFIX;
3375 else if (i.types[op].bitfield.reg32)
3377 i.suffix = LONG_MNEM_SUFFIX;
3380 else if (i.types[op].bitfield.reg64)
3382 i.suffix = QWORD_MNEM_SUFFIX;
3388 else if (i.suffix == BYTE_MNEM_SUFFIX)
3390 if (!check_byte_reg ())
3393 else if (i.suffix == LONG_MNEM_SUFFIX)
3395 if (!check_long_reg ())
3398 else if (i.suffix == QWORD_MNEM_SUFFIX)
3401 && i.tm.opcode_modifier.ignoresize
3402 && i.tm.opcode_modifier.no_qsuf)
3404 else if (!check_qword_reg ())
3407 else if (i.suffix == WORD_MNEM_SUFFIX)
3409 if (!check_word_reg ())
3412 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3414 /* Skip if the instruction has x suffix. match_template
3415 should check if it is a valid suffix. */
3417 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3418 /* Do nothing if the instruction is going to ignore the prefix. */
3423 else if (i.tm.opcode_modifier.defaultsize
3425 /* exclude fldenv/frstor/fsave/fstenv */
3426 && i.tm.opcode_modifier.no_ssuf)
3428 i.suffix = stackop_size;
3430 else if (intel_syntax
3432 && (i.tm.operand_types[0].bitfield.jumpabsolute
3433 || i.tm.opcode_modifier.jumpbyte
3434 || i.tm.opcode_modifier.jumpintersegment
3435 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3436 && i.tm.extension_opcode <= 3)))
3441 if (!i.tm.opcode_modifier.no_qsuf)
3443 i.suffix = QWORD_MNEM_SUFFIX;
3447 if (!i.tm.opcode_modifier.no_lsuf)
3448 i.suffix = LONG_MNEM_SUFFIX;
3451 if (!i.tm.opcode_modifier.no_wsuf)
3452 i.suffix = WORD_MNEM_SUFFIX;
3461 if (i.tm.opcode_modifier.w)
3463 as_bad (_("no instruction mnemonic suffix given and "
3464 "no register operands; can't size instruction"));
3470 unsigned int suffixes;
3472 suffixes = !i.tm.opcode_modifier.no_bsuf;
3473 if (!i.tm.opcode_modifier.no_wsuf)
3475 if (!i.tm.opcode_modifier.no_lsuf)
3477 if (!i.tm.opcode_modifier.no_ldsuf)
3479 if (!i.tm.opcode_modifier.no_ssuf)
3481 if (!i.tm.opcode_modifier.no_qsuf)
3484 /* There are more than suffix matches. */
3485 if (i.tm.opcode_modifier.w
3486 || ((suffixes & (suffixes - 1))
3487 && !i.tm.opcode_modifier.defaultsize
3488 && !i.tm.opcode_modifier.ignoresize))
3490 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3496 /* Change the opcode based on the operand size given by i.suffix;
3497 We don't need to change things for byte insns. */
3500 && i.suffix != BYTE_MNEM_SUFFIX
3501 && i.suffix != XMMWORD_MNEM_SUFFIX)
3503 /* It's not a byte, select word/dword operation. */
3504 if (i.tm.opcode_modifier.w)
3506 if (i.tm.opcode_modifier.shortform)
3507 i.tm.base_opcode |= 8;
3509 i.tm.base_opcode |= 1;
3512 /* Now select between word & dword operations via the operand
3513 size prefix, except for instructions that will ignore this
3515 if (i.tm.opcode_modifier.addrprefixop0)
3517 /* The address size override prefix changes the size of the
3519 if ((flag_code == CODE_32BIT
3520 && i.op->regs[0].reg_type.bitfield.reg16)
3521 || (flag_code != CODE_32BIT
3522 && i.op->regs[0].reg_type.bitfield.reg32))
3523 if (!add_prefix (ADDR_PREFIX_OPCODE))
3526 else if (i.suffix != QWORD_MNEM_SUFFIX
3527 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3528 && !i.tm.opcode_modifier.ignoresize
3529 && !i.tm.opcode_modifier.floatmf
3530 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3531 || (flag_code == CODE_64BIT
3532 && i.tm.opcode_modifier.jumpbyte)))
3534 unsigned int prefix = DATA_PREFIX_OPCODE;
3536 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3537 prefix = ADDR_PREFIX_OPCODE;
3539 if (!add_prefix (prefix))
3543 /* Set mode64 for an operand. */
3544 if (i.suffix == QWORD_MNEM_SUFFIX
3545 && flag_code == CODE_64BIT
3546 && !i.tm.opcode_modifier.norex64)
3548 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3549 need rex64. cmpxchg8b is also a special case. */
3550 if (! (i.operands == 2
3551 && i.tm.base_opcode == 0x90
3552 && i.tm.extension_opcode == None
3553 && UINTS_EQUAL (i.types [0], acc64)
3554 && UINTS_EQUAL (i.types [1], acc64))
3555 && ! (i.operands == 1
3556 && i.tm.base_opcode == 0xfc7
3557 && i.tm.extension_opcode == 1
3558 && !operand_type_check (i.types [0], reg)
3559 && operand_type_check (i.types [0], anymem)))
3563 /* Size floating point instruction. */
3564 if (i.suffix == LONG_MNEM_SUFFIX)
3565 if (i.tm.opcode_modifier.floatmf)
3566 i.tm.base_opcode ^= 4;
3573 check_byte_reg (void)
3577 for (op = i.operands; --op >= 0;)
3579 /* If this is an eight bit register, it's OK. If it's the 16 or
3580 32 bit version of an eight bit register, we will just use the
3581 low portion, and that's OK too. */
3582 if (i.types[op].bitfield.reg8)
3585 /* Don't generate this warning if not needed. */
3586 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3589 /* crc32 doesn't generate this warning. */
3590 if (i.tm.base_opcode == 0xf20f38f0)
3593 if ((i.types[op].bitfield.reg16
3594 || i.types[op].bitfield.reg32
3595 || i.types[op].bitfield.reg64)
3596 && i.op[op].regs->reg_num < 4)
3598 /* Prohibit these changes in the 64bit mode, since the
3599 lowering is more complicated. */
3600 if (flag_code == CODE_64BIT
3601 && !i.tm.operand_types[op].bitfield.inoutportreg)
3603 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3604 register_prefix, i.op[op].regs->reg_name,
3608 #if REGISTER_WARNINGS
3610 && !i.tm.operand_types[op].bitfield.inoutportreg)
3611 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3613 (i.op[op].regs + (i.types[op].bitfield.reg16
3614 ? REGNAM_AL - REGNAM_AX
3615 : REGNAM_AL - REGNAM_EAX))->reg_name,
3617 i.op[op].regs->reg_name,
3622 /* Any other register is bad. */
3623 if (i.types[op].bitfield.reg16
3624 || i.types[op].bitfield.reg32
3625 || i.types[op].bitfield.reg64
3626 || i.types[op].bitfield.regmmx
3627 || i.types[op].bitfield.regxmm
3628 || i.types[op].bitfield.sreg2
3629 || i.types[op].bitfield.sreg3
3630 || i.types[op].bitfield.control
3631 || i.types[op].bitfield.debug
3632 || i.types[op].bitfield.test
3633 || i.types[op].bitfield.floatreg
3634 || i.types[op].bitfield.floatacc)
3636 as_bad (_("`%s%s' not allowed with `%s%c'"),
3638 i.op[op].regs->reg_name,
3648 check_long_reg (void)
3652 for (op = i.operands; --op >= 0;)
3653 /* Reject eight bit registers, except where the template requires
3654 them. (eg. movzb) */
3655 if (i.types[op].bitfield.reg8
3656 && (i.tm.operand_types[op].bitfield.reg16
3657 || i.tm.operand_types[op].bitfield.reg32
3658 || i.tm.operand_types[op].bitfield.acc))
3660 as_bad (_("`%s%s' not allowed with `%s%c'"),
3662 i.op[op].regs->reg_name,
3667 /* Warn if the e prefix on a general reg is missing. */
3668 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3669 && i.types[op].bitfield.reg16
3670 && (i.tm.operand_types[op].bitfield.reg32
3671 || i.tm.operand_types[op].bitfield.acc))
3673 /* Prohibit these changes in the 64bit mode, since the
3674 lowering is more complicated. */
3675 if (flag_code == CODE_64BIT)
3677 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3678 register_prefix, i.op[op].regs->reg_name,
3682 #if REGISTER_WARNINGS
3684 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3686 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3688 i.op[op].regs->reg_name,
3692 /* Warn if the r prefix on a general reg is missing. */
3693 else if (i.types[op].bitfield.reg64
3694 && (i.tm.operand_types[op].bitfield.reg32
3695 || i.tm.operand_types[op].bitfield.acc))
3698 && i.tm.opcode_modifier.toqword
3699 && !i.types[0].bitfield.regxmm)
3701 /* Convert to QWORD. We want REX byte. */
3702 i.suffix = QWORD_MNEM_SUFFIX;
3706 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3707 register_prefix, i.op[op].regs->reg_name,
3716 check_qword_reg (void)
3720 for (op = i.operands; --op >= 0; )
3721 /* Reject eight bit registers, except where the template requires
3722 them. (eg. movzb) */
3723 if (i.types[op].bitfield.reg8
3724 && (i.tm.operand_types[op].bitfield.reg16
3725 || i.tm.operand_types[op].bitfield.reg32
3726 || i.tm.operand_types[op].bitfield.acc))
3728 as_bad (_("`%s%s' not allowed with `%s%c'"),
3730 i.op[op].regs->reg_name,
3735 /* Warn if the e prefix on a general reg is missing. */
3736 else if ((i.types[op].bitfield.reg16
3737 || i.types[op].bitfield.reg32)
3738 && (i.tm.operand_types[op].bitfield.reg32
3739 || i.tm.operand_types[op].bitfield.acc))
3741 /* Prohibit these changes in the 64bit mode, since the
3742 lowering is more complicated. */
3744 && i.tm.opcode_modifier.todword
3745 && !i.types[0].bitfield.regxmm)
3747 /* Convert to DWORD. We don't want REX byte. */
3748 i.suffix = LONG_MNEM_SUFFIX;
3752 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3753 register_prefix, i.op[op].regs->reg_name,
3762 check_word_reg (void)
3765 for (op = i.operands; --op >= 0;)
3766 /* Reject eight bit registers, except where the template requires
3767 them. (eg. movzb) */
3768 if (i.types[op].bitfield.reg8
3769 && (i.tm.operand_types[op].bitfield.reg16
3770 || i.tm.operand_types[op].bitfield.reg32
3771 || i.tm.operand_types[op].bitfield.acc))
3773 as_bad (_("`%s%s' not allowed with `%s%c'"),
3775 i.op[op].regs->reg_name,
3780 /* Warn if the e prefix on a general reg is present. */
3781 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3782 && i.types[op].bitfield.reg32
3783 && (i.tm.operand_types[op].bitfield.reg16
3784 || i.tm.operand_types[op].bitfield.acc))
3786 /* Prohibit these changes in the 64bit mode, since the
3787 lowering is more complicated. */
3788 if (flag_code == CODE_64BIT)
3790 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3791 register_prefix, i.op[op].regs->reg_name,
3796 #if REGISTER_WARNINGS
3797 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3799 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3801 i.op[op].regs->reg_name,
3809 update_imm (unsigned int j)
3811 i386_operand_type overlap;
3813 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3814 if ((overlap.bitfield.imm8
3815 || overlap.bitfield.imm8s
3816 || overlap.bitfield.imm16
3817 || overlap.bitfield.imm32
3818 || overlap.bitfield.imm32s
3819 || overlap.bitfield.imm64)
3820 && !UINTS_EQUAL (overlap, imm8)
3821 && !UINTS_EQUAL (overlap, imm8s)
3822 && !UINTS_EQUAL (overlap, imm16)
3823 && !UINTS_EQUAL (overlap, imm32)
3824 && !UINTS_EQUAL (overlap, imm32s)
3825 && !UINTS_EQUAL (overlap, imm64))
3829 i386_operand_type temp;
3832 if (i.suffix == BYTE_MNEM_SUFFIX)
3834 temp.bitfield.imm8 = overlap.bitfield.imm8;
3835 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3837 else if (i.suffix == WORD_MNEM_SUFFIX)
3838 temp.bitfield.imm16 = overlap.bitfield.imm16;
3839 else if (i.suffix == QWORD_MNEM_SUFFIX)
3841 temp.bitfield.imm64 = overlap.bitfield.imm64;
3842 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3845 temp.bitfield.imm32 = overlap.bitfield.imm32;
3848 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3849 || UINTS_EQUAL (overlap, imm16_32)
3850 || UINTS_EQUAL (overlap, imm16_32s))
3852 UINTS_CLEAR (overlap);
3853 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3854 overlap.bitfield.imm16 = 1;
3856 overlap.bitfield.imm32s = 1;
3858 if (!UINTS_EQUAL (overlap, imm8)
3859 && !UINTS_EQUAL (overlap, imm8s)
3860 && !UINTS_EQUAL (overlap, imm16)
3861 && !UINTS_EQUAL (overlap, imm32)
3862 && !UINTS_EQUAL (overlap, imm32s)
3863 && !UINTS_EQUAL (overlap, imm64))
3865 as_bad (_("no instruction mnemonic suffix given; "
3866 "can't determine immediate size"));
3870 i.types[j] = overlap;
3880 for (j = 0; j < 2; j++)
3881 if (update_imm (j) == 0)
3884 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3885 assert (operand_type_check (i.types[2], imm) == 0);
3893 i.drex.modrm_reg = 0;
3894 i.drex.modrm_regmem = 0;
3896 /* SSE5 4 operand instructions must have the destination the same as
3897 one of the inputs. Figure out the destination register and cache
3898 it away in the drex field, and remember which fields to use for
3900 if (i.tm.opcode_modifier.drex
3901 && i.tm.opcode_modifier.drexv
3904 i.tm.extension_opcode = None;
3906 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3907 if (i.types[0].bitfield.regxmm != 0
3908 && i.types[1].bitfield.regxmm != 0
3909 && i.types[2].bitfield.regxmm != 0
3910 && i.types[3].bitfield.regxmm != 0
3911 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3912 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3914 /* Clear the arguments that are stored in drex. */
3915 UINTS_CLEAR (i.types[0]);
3916 UINTS_CLEAR (i.types[3]);
3917 i.reg_operands -= 2;
3919 /* There are two different ways to encode a 4 operand
3920 instruction with all registers that uses OC1 set to
3921 0 or 1. Favor setting OC1 to 0 since this mimics the
3922 actions of other SSE5 assemblers. Use modrm encoding 2
3923 for register/register. Include the high order bit that
3924 is normally stored in the REX byte in the register
3926 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3927 i.drex.modrm_reg = 2;
3928 i.drex.modrm_regmem = 1;
3929 i.drex.reg = (i.op[3].regs->reg_num
3930 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3933 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3934 else if (i.types[0].bitfield.regxmm != 0
3935 && i.types[1].bitfield.regxmm != 0
3936 && (i.types[2].bitfield.regxmm
3937 || operand_type_check (i.types[2], anymem))
3938 && i.types[3].bitfield.regxmm != 0
3939 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3940 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3942 /* clear the arguments that are stored in drex */
3943 UINTS_CLEAR (i.types[0]);
3944 UINTS_CLEAR (i.types[3]);
3945 i.reg_operands -= 2;
3947 /* Specify the modrm encoding for memory addressing. Include
3948 the high order bit that is normally stored in the REX byte
3949 in the register field. */
3950 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3951 i.drex.modrm_reg = 1;
3952 i.drex.modrm_regmem = 2;
3953 i.drex.reg = (i.op[3].regs->reg_num
3954 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3957 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3958 else if (i.types[0].bitfield.regxmm != 0
3959 && operand_type_check (i.types[1], anymem) != 0
3960 && i.types[2].bitfield.regxmm != 0
3961 && i.types[3].bitfield.regxmm != 0
3962 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3963 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3965 /* Clear the arguments that are stored in drex. */
3966 UINTS_CLEAR (i.types[0]);
3967 UINTS_CLEAR (i.types[3]);
3968 i.reg_operands -= 2;
3970 /* Specify the modrm encoding for memory addressing. Include
3971 the high order bit that is normally stored in the REX byte
3972 in the register field. */
3973 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3974 i.drex.modrm_reg = 2;
3975 i.drex.modrm_regmem = 1;
3976 i.drex.reg = (i.op[3].regs->reg_num
3977 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3980 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3981 else if (i.types[0].bitfield.regxmm != 0
3982 && i.types[1].bitfield.regxmm != 0
3983 && i.types[2].bitfield.regxmm != 0
3984 && i.types[3].bitfield.regxmm != 0
3985 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3986 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3988 /* clear the arguments that are stored in drex */
3989 UINTS_CLEAR (i.types[2]);
3990 UINTS_CLEAR (i.types[3]);
3991 i.reg_operands -= 2;
3993 /* There are two different ways to encode a 4 operand
3994 instruction with all registers that uses OC1 set to
3995 0 or 1. Favor setting OC1 to 0 since this mimics the
3996 actions of other SSE5 assemblers. Use modrm encoding
3997 2 for register/register. Include the high order bit that
3998 is normally stored in the REX byte in the register
4000 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4001 i.drex.modrm_reg = 1;
4002 i.drex.modrm_regmem = 0;
4004 /* Remember the register, including the upper bits */
4005 i.drex.reg = (i.op[3].regs->reg_num
4006 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4009 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4010 else if (i.types[0].bitfield.regxmm != 0
4011 && (i.types[1].bitfield.regxmm
4012 || operand_type_check (i.types[1], anymem))
4013 && i.types[2].bitfield.regxmm != 0
4014 && i.types[3].bitfield.regxmm != 0
4015 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4016 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4018 /* Clear the arguments that are stored in drex. */
4019 UINTS_CLEAR (i.types[2]);
4020 UINTS_CLEAR (i.types[3]);
4021 i.reg_operands -= 2;
4023 /* Specify the modrm encoding and remember the register
4024 including the bits normally stored in the REX byte. */
4025 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4026 i.drex.modrm_reg = 0;
4027 i.drex.modrm_regmem = 1;
4028 i.drex.reg = (i.op[3].regs->reg_num
4029 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4032 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4033 else if (operand_type_check (i.types[0], anymem) != 0
4034 && i.types[1].bitfield.regxmm != 0
4035 && i.types[2].bitfield.regxmm != 0
4036 && i.types[3].bitfield.regxmm != 0
4037 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4038 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4040 /* clear the arguments that are stored in drex */
4041 UINTS_CLEAR (i.types[2]);
4042 UINTS_CLEAR (i.types[3]);
4043 i.reg_operands -= 2;
4045 /* Specify the modrm encoding and remember the register
4046 including the bits normally stored in the REX byte. */
4047 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4048 i.drex.modrm_reg = 1;
4049 i.drex.modrm_regmem = 0;
4050 i.drex.reg = (i.op[3].regs->reg_num
4051 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4055 as_bad (_("Incorrect operands for the '%s' instruction"),
4059 /* SSE5 instructions with the DREX byte where the only memory operand
4060 is in the 2nd argument, and the first and last xmm register must
4061 match, and is encoded in the DREX byte. */
4062 else if (i.tm.opcode_modifier.drex
4063 && !i.tm.opcode_modifier.drexv
4066 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4067 if (i.types[0].bitfield.regxmm != 0
4068 && (i.types[1].bitfield.regxmm
4069 || operand_type_check(i.types[1], anymem))
4070 && i.types[2].bitfield.regxmm != 0
4071 && i.types[3].bitfield.regxmm != 0
4072 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4073 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4075 /* clear the arguments that are stored in drex */
4076 UINTS_CLEAR (i.types[0]);
4077 UINTS_CLEAR (i.types[3]);
4078 i.reg_operands -= 2;
4080 /* Specify the modrm encoding and remember the register
4081 including the high bit normally stored in the REX
4083 i.drex.modrm_reg = 2;
4084 i.drex.modrm_regmem = 1;
4085 i.drex.reg = (i.op[3].regs->reg_num
4086 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4090 as_bad (_("Incorrect operands for the '%s' instruction"),
4094 /* SSE5 3 operand instructions that the result is a register, being
4095 either operand can be a memory operand, using OC0 to note which
4096 one is the memory. */
4097 else if (i.tm.opcode_modifier.drex
4098 && i.tm.opcode_modifier.drexv
4101 i.tm.extension_opcode = None;
4103 /* Case 1: 3 operand insn, src1 = register. */
4104 if (i.types[0].bitfield.regxmm != 0
4105 && i.types[1].bitfield.regxmm != 0
4106 && i.types[2].bitfield.regxmm != 0)
4108 /* Clear the arguments that are stored in drex. */
4109 UINTS_CLEAR (i.types[2]);
4112 /* Specify the modrm encoding and remember the register
4113 including the high bit normally stored in the REX byte. */
4114 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4115 i.drex.modrm_reg = 1;
4116 i.drex.modrm_regmem = 0;
4117 i.drex.reg = (i.op[2].regs->reg_num
4118 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4121 /* Case 2: 3 operand insn, src1 = memory. */
4122 else if (operand_type_check (i.types[0], anymem) != 0
4123 && i.types[1].bitfield.regxmm != 0
4124 && i.types[2].bitfield.regxmm != 0)
4126 /* Clear the arguments that are stored in drex. */
4127 UINTS_CLEAR (i.types[2]);
4130 /* Specify the modrm encoding and remember the register
4131 including the high bit normally stored in the REX
4133 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4134 i.drex.modrm_reg = 1;
4135 i.drex.modrm_regmem = 0;
4136 i.drex.reg = (i.op[2].regs->reg_num
4137 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4140 /* Case 3: 3 operand insn, src2 = memory. */
4141 else if (i.types[0].bitfield.regxmm != 0
4142 && operand_type_check (i.types[1], anymem) != 0
4143 && i.types[2].bitfield.regxmm != 0)
4145 /* Clear the arguments that are stored in drex. */
4146 UINTS_CLEAR (i.types[2]);
4149 /* Specify the modrm encoding and remember the register
4150 including the high bit normally stored in the REX byte. */
4151 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4152 i.drex.modrm_reg = 0;
4153 i.drex.modrm_regmem = 1;
4154 i.drex.reg = (i.op[2].regs->reg_num
4155 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4159 as_bad (_("Incorrect operands for the '%s' instruction"),
4163 /* SSE5 4 operand instructions that are the comparison instructions
4164 where the first operand is the immediate value of the comparison
4166 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4168 /* Case 1: 4 operand insn, src1 = reg/memory. */
4169 if (operand_type_check (i.types[0], imm) != 0
4170 && (i.types[1].bitfield.regxmm
4171 || operand_type_check (i.types[1], anymem))
4172 && i.types[2].bitfield.regxmm != 0
4173 && i.types[3].bitfield.regxmm != 0)
4175 /* clear the arguments that are stored in drex */
4176 UINTS_CLEAR (i.types[3]);
4179 /* Specify the modrm encoding and remember the register
4180 including the high bit normally stored in the REX byte. */
4181 i.drex.modrm_reg = 2;
4182 i.drex.modrm_regmem = 1;
4183 i.drex.reg = (i.op[3].regs->reg_num
4184 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4187 /* Case 2: 3 operand insn with ImmExt that places the
4188 opcode_extension as an immediate argument. This is used for
4189 all of the varients of comparison that supplies the appropriate
4190 value as part of the instruction. */
4191 else if ((i.types[0].bitfield.regxmm
4192 || operand_type_check (i.types[0], anymem))
4193 && i.types[1].bitfield.regxmm != 0
4194 && i.types[2].bitfield.regxmm != 0
4195 && operand_type_check (i.types[3], imm) != 0)
4197 /* clear the arguments that are stored in drex */
4198 UINTS_CLEAR (i.types[2]);
4201 /* Specify the modrm encoding and remember the register
4202 including the high bit normally stored in the REX byte. */
4203 i.drex.modrm_reg = 1;
4204 i.drex.modrm_regmem = 0;
4205 i.drex.reg = (i.op[2].regs->reg_num
4206 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4210 as_bad (_("Incorrect operands for the '%s' instruction"),
4214 else if (i.tm.opcode_modifier.drex
4215 || i.tm.opcode_modifier.drexv
4216 || i.tm.opcode_modifier.drexc)
4217 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4221 process_operands (void)
4223 /* Default segment register this instruction will use for memory
4224 accesses. 0 means unknown. This is only for optimizing out
4225 unnecessary segment overrides. */
4226 const seg_entry *default_seg = 0;
4228 /* Handle all of the DREX munging that SSE5 needs. */
4229 if (i.tm.opcode_modifier.drex
4230 || i.tm.opcode_modifier.drexv
4231 || i.tm.opcode_modifier.drexc)
4234 if (i.tm.opcode_modifier.firstxmm0)
4238 /* The first operand is implicit and must be xmm0. */
4239 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4240 if (i.op[0].regs->reg_num != 0)
4243 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4244 i.tm.name, register_prefix);
4246 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4247 i.tm.name, register_prefix);
4251 for (j = 1; j < i.operands; j++)
4253 i.op[j - 1] = i.op[j];
4254 i.types[j - 1] = i.types[j];
4256 /* We need to adjust fields in i.tm since they are used by
4257 build_modrm_byte. */
4258 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4265 else if (i.tm.opcode_modifier.regkludge)
4267 /* The imul $imm, %reg instruction is converted into
4268 imul $imm, %reg, %reg, and the clr %reg instruction
4269 is converted into xor %reg, %reg. */
4271 unsigned int first_reg_op;
4273 if (operand_type_check (i.types[0], reg))
4277 /* Pretend we saw the extra register operand. */
4278 assert (i.reg_operands == 1
4279 && i.op[first_reg_op + 1].regs == 0);
4280 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4281 i.types[first_reg_op + 1] = i.types[first_reg_op];
4286 if (i.tm.opcode_modifier.shortform)
4288 if (i.types[0].bitfield.sreg2
4289 || i.types[0].bitfield.sreg3)
4291 if (i.tm.base_opcode == POP_SEG_SHORT
4292 && i.op[0].regs->reg_num == 1)
4294 as_bad (_("you can't `pop %%cs'"));
4297 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4298 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4303 /* The register or float register operand is in operand
4307 if (i.types[0].bitfield.floatreg
4308 || operand_type_check (i.types[0], reg))
4312 /* Register goes in low 3 bits of opcode. */
4313 i.tm.base_opcode |= i.op[op].regs->reg_num;
4314 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4316 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4318 /* Warn about some common errors, but press on regardless.
4319 The first case can be generated by gcc (<= 2.8.1). */
4320 if (i.operands == 2)
4322 /* Reversed arguments on faddp, fsubp, etc. */
4323 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4324 register_prefix, i.op[1].regs->reg_name,
4325 register_prefix, i.op[0].regs->reg_name);
4329 /* Extraneous `l' suffix on fp insn. */
4330 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4331 register_prefix, i.op[0].regs->reg_name);
4336 else if (i.tm.opcode_modifier.modrm)
4338 /* The opcode is completed (modulo i.tm.extension_opcode which
4339 must be put into the modrm byte). Now, we make the modrm and
4340 index base bytes based on all the info we've collected. */
4342 default_seg = build_modrm_byte ();
4344 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4348 else if (i.tm.opcode_modifier.isstring)
4350 /* For the string instructions that allow a segment override
4351 on one of their operands, the default segment is ds. */
4355 if (i.tm.base_opcode == 0x8d /* lea */
4358 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4360 /* If a segment was explicitly specified, and the specified segment
4361 is not the default, use an opcode prefix to select it. If we
4362 never figured out what the default segment is, then default_seg
4363 will be zero at this point, and the specified segment prefix will
4365 if ((i.seg[0]) && (i.seg[0] != default_seg))
4367 if (!add_prefix (i.seg[0]->seg_prefix))
4373 static const seg_entry *
4374 build_modrm_byte (void)
4376 const seg_entry *default_seg = 0;
4378 /* SSE5 4 operand instructions are encoded in such a way that one of
4379 the inputs must match the destination register. Process_drex hides
4380 the 3rd argument in the drex field, so that by the time we get
4381 here, it looks to GAS as if this is a 2 operand instruction. */
4382 if ((i.tm.opcode_modifier.drex
4383 || i.tm.opcode_modifier.drexv
4384 || i.tm.opcode_modifier.drexc)
4385 && i.reg_operands == 2)
4387 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4388 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4390 i.rm.reg = reg->reg_num;
4391 i.rm.regmem = regmem->reg_num;
4393 if ((reg->reg_flags & RegRex) != 0)
4395 if ((regmem->reg_flags & RegRex) != 0)
4399 /* i.reg_operands MUST be the number of real register operands;
4400 implicit registers do not count. */
4401 else if (i.reg_operands == 2)
4403 unsigned int source, dest;
4411 /* When there are 3 operands, one of them may be immediate,
4412 which may be the first or the last operand. Otherwise,
4413 the first operand must be shift count register (cl). */
4414 assert (i.imm_operands == 1
4415 || (i.imm_operands == 0
4416 && i.types[0].bitfield.shiftcount));
4417 if (operand_type_check (i.types[0], imm)
4418 || i.types[0].bitfield.shiftcount)
4424 /* When there are 4 operands, the first two must be 8bit
4425 immediate operands. The source operand will be the 3rd
4427 assert (i.imm_operands == 2
4428 && i.types[0].bitfield.imm8
4429 && i.types[1].bitfield.imm8);
4439 /* One of the register operands will be encoded in the i.tm.reg
4440 field, the other in the combined i.tm.mode and i.tm.regmem
4441 fields. If no form of this instruction supports a memory
4442 destination operand, then we assume the source operand may
4443 sometimes be a memory operand and so we need to store the
4444 destination in the i.rm.reg field. */
4445 if (!i.tm.operand_types[dest].bitfield.regmem
4446 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4448 i.rm.reg = i.op[dest].regs->reg_num;
4449 i.rm.regmem = i.op[source].regs->reg_num;
4450 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4452 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4457 i.rm.reg = i.op[source].regs->reg_num;
4458 i.rm.regmem = i.op[dest].regs->reg_num;
4459 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4461 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4464 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4466 if (!i.types[0].bitfield.control
4467 && !i.types[1].bitfield.control)
4469 i.rex &= ~(REX_R | REX_B);
4470 add_prefix (LOCK_PREFIX_OPCODE);
4474 { /* If it's not 2 reg operands... */
4477 unsigned int fake_zero_displacement = 0;
4480 /* This has been precalculated for SSE5 instructions
4481 that have a DREX field earlier in process_drex. */
4482 if (i.tm.opcode_modifier.drex
4483 || i.tm.opcode_modifier.drexv
4484 || i.tm.opcode_modifier.drexc)
4485 op = i.drex.modrm_regmem;
4488 for (op = 0; op < i.operands; op++)
4489 if (operand_type_check (i.types[op], anymem))
4491 assert (op < i.operands);
4496 if (i.base_reg == 0)
4499 if (!i.disp_operands)
4500 fake_zero_displacement = 1;
4501 if (i.index_reg == 0)
4503 /* Operand is just <disp> */
4504 if (flag_code == CODE_64BIT)
4506 /* 64bit mode overwrites the 32bit absolute
4507 addressing by RIP relative addressing and
4508 absolute addressing is encoded by one of the
4509 redundant SIB forms. */
4510 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4511 i.sib.base = NO_BASE_REGISTER;
4512 i.sib.index = NO_INDEX_REGISTER;
4513 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4514 ? disp32s : disp32);
4516 else if ((flag_code == CODE_16BIT)
4517 ^ (i.prefix[ADDR_PREFIX] != 0))
4519 i.rm.regmem = NO_BASE_REGISTER_16;
4520 i.types[op] = disp16;
4524 i.rm.regmem = NO_BASE_REGISTER;
4525 i.types[op] = disp32;
4528 else /* !i.base_reg && i.index_reg */
4530 if (i.index_reg->reg_num == RegEiz
4531 || i.index_reg->reg_num == RegRiz)
4532 i.sib.index = NO_INDEX_REGISTER;
4534 i.sib.index = i.index_reg->reg_num;
4535 i.sib.base = NO_BASE_REGISTER;
4536 i.sib.scale = i.log2_scale_factor;
4537 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4538 i.types[op].bitfield.disp8 = 0;
4539 i.types[op].bitfield.disp16 = 0;
4540 i.types[op].bitfield.disp64 = 0;
4541 if (flag_code != CODE_64BIT)
4543 /* Must be 32 bit */
4544 i.types[op].bitfield.disp32 = 1;
4545 i.types[op].bitfield.disp32s = 0;
4549 i.types[op].bitfield.disp32 = 0;
4550 i.types[op].bitfield.disp32s = 1;
4552 if ((i.index_reg->reg_flags & RegRex) != 0)
4556 /* RIP addressing for 64bit mode. */
4557 else if (i.base_reg->reg_num == RegRip ||
4558 i.base_reg->reg_num == RegEip)
4560 i.rm.regmem = NO_BASE_REGISTER;
4561 i.types[op].bitfield.disp8 = 0;
4562 i.types[op].bitfield.disp16 = 0;
4563 i.types[op].bitfield.disp32 = 0;
4564 i.types[op].bitfield.disp32s = 1;
4565 i.types[op].bitfield.disp64 = 0;
4566 i.flags[op] |= Operand_PCrel;
4567 if (! i.disp_operands)
4568 fake_zero_displacement = 1;
4570 else if (i.base_reg->reg_type.bitfield.reg16)
4572 switch (i.base_reg->reg_num)
4575 if (i.index_reg == 0)
4577 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4578 i.rm.regmem = i.index_reg->reg_num - 6;
4582 if (i.index_reg == 0)
4585 if (operand_type_check (i.types[op], disp) == 0)
4587 /* fake (%bp) into 0(%bp) */
4588 i.types[op].bitfield.disp8 = 1;
4589 fake_zero_displacement = 1;
4592 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4593 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4595 default: /* (%si) -> 4 or (%di) -> 5 */
4596 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4598 i.rm.mode = mode_from_disp_size (i.types[op]);
4600 else /* i.base_reg and 32/64 bit mode */
4602 if (flag_code == CODE_64BIT
4603 && operand_type_check (i.types[op], disp))
4605 i386_operand_type temp;
4607 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4609 if (i.prefix[ADDR_PREFIX] == 0)
4610 i.types[op].bitfield.disp32s = 1;
4612 i.types[op].bitfield.disp32 = 1;
4615 i.rm.regmem = i.base_reg->reg_num;
4616 if ((i.base_reg->reg_flags & RegRex) != 0)
4618 i.sib.base = i.base_reg->reg_num;
4619 /* x86-64 ignores REX prefix bit here to avoid decoder
4621 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4624 if (i.disp_operands == 0)
4626 fake_zero_displacement = 1;
4627 i.types[op].bitfield.disp8 = 1;
4630 else if (i.base_reg->reg_num == ESP_REG_NUM)
4634 i.sib.scale = i.log2_scale_factor;
4635 if (i.index_reg == 0)
4637 /* <disp>(%esp) becomes two byte modrm with no index
4638 register. We've already stored the code for esp
4639 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4640 Any base register besides %esp will not use the
4641 extra modrm byte. */
4642 i.sib.index = NO_INDEX_REGISTER;
4646 if (i.index_reg->reg_num == RegEiz
4647 || i.index_reg->reg_num == RegRiz)
4648 i.sib.index = NO_INDEX_REGISTER;
4650 i.sib.index = i.index_reg->reg_num;
4651 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4652 if ((i.index_reg->reg_flags & RegRex) != 0)
4657 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4658 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4661 i.rm.mode = mode_from_disp_size (i.types[op]);
4664 if (fake_zero_displacement)
4666 /* Fakes a zero displacement assuming that i.types[op]
4667 holds the correct displacement size. */
4670 assert (i.op[op].disps == 0);
4671 exp = &disp_expressions[i.disp_operands++];
4672 i.op[op].disps = exp;
4673 exp->X_op = O_constant;
4674 exp->X_add_number = 0;
4675 exp->X_add_symbol = (symbolS *) 0;
4676 exp->X_op_symbol = (symbolS *) 0;
4680 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4681 (if any) based on i.tm.extension_opcode. Again, we must be
4682 careful to make sure that segment/control/debug/test/MMX
4683 registers are coded into the i.rm.reg field. */
4688 /* This has been precalculated for SSE5 instructions
4689 that have a DREX field earlier in process_drex. */
4690 if (i.tm.opcode_modifier.drex
4691 || i.tm.opcode_modifier.drexv
4692 || i.tm.opcode_modifier.drexc)
4694 op = i.drex.modrm_reg;
4695 i.rm.reg = i.op[op].regs->reg_num;
4696 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4701 for (op = 0; op < i.operands; op++)
4702 if (i.types[op].bitfield.reg8
4703 || i.types[op].bitfield.reg16
4704 || i.types[op].bitfield.reg32
4705 || i.types[op].bitfield.reg64
4706 || i.types[op].bitfield.regmmx
4707 || i.types[op].bitfield.regxmm
4708 || i.types[op].bitfield.sreg2
4709 || i.types[op].bitfield.sreg3
4710 || i.types[op].bitfield.control
4711 || i.types[op].bitfield.debug
4712 || i.types[op].bitfield.test)
4715 assert (op < i.operands);
4717 /* If there is an extension opcode to put here, the
4718 register number must be put into the regmem field. */
4719 if (i.tm.extension_opcode != None)
4721 i.rm.regmem = i.op[op].regs->reg_num;
4722 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4727 i.rm.reg = i.op[op].regs->reg_num;
4728 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4733 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4734 must set it to 3 to indicate this is a register operand
4735 in the regmem field. */
4736 if (!i.mem_operands)
4740 /* Fill in i.rm.reg field with extension opcode (if any). */
4741 if (i.tm.extension_opcode != None
4742 && !(i.tm.opcode_modifier.drex
4743 || i.tm.opcode_modifier.drexv
4744 || i.tm.opcode_modifier.drexc))
4745 i.rm.reg = i.tm.extension_opcode;
4751 output_branch (void)
4756 relax_substateT subtype;
4761 if (flag_code == CODE_16BIT)
4765 if (i.prefix[DATA_PREFIX] != 0)
4771 /* Pentium4 branch hints. */
4772 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4773 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4778 if (i.prefix[REX_PREFIX] != 0)
4784 if (i.prefixes != 0 && !intel_syntax)
4785 as_warn (_("skipping prefixes on this instruction"));
4787 /* It's always a symbol; End frag & setup for relax.
4788 Make sure there is enough room in this frag for the largest
4789 instruction we may generate in md_convert_frag. This is 2
4790 bytes for the opcode and room for the prefix and largest
4792 frag_grow (prefix + 2 + 4);
4793 /* Prefix and 1 opcode byte go in fr_fix. */
4794 p = frag_more (prefix + 1);
4795 if (i.prefix[DATA_PREFIX] != 0)
4796 *p++ = DATA_PREFIX_OPCODE;
4797 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4798 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4799 *p++ = i.prefix[SEG_PREFIX];
4800 if (i.prefix[REX_PREFIX] != 0)
4801 *p++ = i.prefix[REX_PREFIX];
4802 *p = i.tm.base_opcode;
4804 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4805 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4806 else if (cpu_arch_flags.bitfield.cpui386)
4807 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4809 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4812 sym = i.op[0].disps->X_add_symbol;
4813 off = i.op[0].disps->X_add_number;
4815 if (i.op[0].disps->X_op != O_constant
4816 && i.op[0].disps->X_op != O_symbol)
4818 /* Handle complex expressions. */
4819 sym = make_expr_symbol (i.op[0].disps);
4823 /* 1 possible extra opcode + 4 byte displacement go in var part.
4824 Pass reloc in fr_var. */
4825 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4835 if (i.tm.opcode_modifier.jumpbyte)
4837 /* This is a loop or jecxz type instruction. */
4839 if (i.prefix[ADDR_PREFIX] != 0)
4841 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4844 /* Pentium4 branch hints. */
4845 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4846 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4848 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4857 if (flag_code == CODE_16BIT)
4860 if (i.prefix[DATA_PREFIX] != 0)
4862 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4872 if (i.prefix[REX_PREFIX] != 0)
4874 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4878 if (i.prefixes != 0 && !intel_syntax)
4879 as_warn (_("skipping prefixes on this instruction"));
4881 p = frag_more (1 + size);
4882 *p++ = i.tm.base_opcode;
4884 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4885 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4887 /* All jumps handled here are signed, but don't use a signed limit
4888 check for 32 and 16 bit jumps as we want to allow wrap around at
4889 4G and 64k respectively. */
4891 fixP->fx_signed = 1;
4895 output_interseg_jump (void)
4903 if (flag_code == CODE_16BIT)
4907 if (i.prefix[DATA_PREFIX] != 0)
4913 if (i.prefix[REX_PREFIX] != 0)
4923 if (i.prefixes != 0 && !intel_syntax)
4924 as_warn (_("skipping prefixes on this instruction"));
4926 /* 1 opcode; 2 segment; offset */
4927 p = frag_more (prefix + 1 + 2 + size);
4929 if (i.prefix[DATA_PREFIX] != 0)
4930 *p++ = DATA_PREFIX_OPCODE;
4932 if (i.prefix[REX_PREFIX] != 0)
4933 *p++ = i.prefix[REX_PREFIX];
4935 *p++ = i.tm.base_opcode;
4936 if (i.op[1].imms->X_op == O_constant)
4938 offsetT n = i.op[1].imms->X_add_number;
4941 && !fits_in_unsigned_word (n)
4942 && !fits_in_signed_word (n))
4944 as_bad (_("16-bit jump out of range"));
4947 md_number_to_chars (p, n, size);
4950 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4951 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4952 if (i.op[0].imms->X_op != O_constant)
4953 as_bad (_("can't handle non absolute segment in `%s'"),
4955 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4961 fragS *insn_start_frag;
4962 offsetT insn_start_off;
4964 /* Tie dwarf2 debug info to the address at the start of the insn.
4965 We can't do this after the insn has been output as the current
4966 frag may have been closed off. eg. by frag_var. */
4967 dwarf2_emit_insn (0);
4969 insn_start_frag = frag_now;
4970 insn_start_off = frag_now_fix ();
4973 if (i.tm.opcode_modifier.jump)
4975 else if (i.tm.opcode_modifier.jumpbyte
4976 || i.tm.opcode_modifier.jumpdword)
4978 else if (i.tm.opcode_modifier.jumpintersegment)
4979 output_interseg_jump ();
4982 /* Output normal instructions here. */
4986 unsigned int prefix;
4988 switch (i.tm.opcode_length)
4991 if (i.tm.base_opcode & 0xff000000)
4993 prefix = (i.tm.base_opcode >> 24) & 0xff;
4998 if ((i.tm.base_opcode & 0xff0000) != 0)
5000 prefix = (i.tm.base_opcode >> 16) & 0xff;
5001 if (i.tm.cpu_flags.bitfield.cpupadlock)
5004 if (prefix != REPE_PREFIX_OPCODE
5005 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5006 add_prefix (prefix);
5009 add_prefix (prefix);
5018 /* The prefix bytes. */
5019 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5021 FRAG_APPEND_1_CHAR (*q);
5023 /* Now the opcode; be careful about word order here! */
5024 if (i.tm.opcode_length == 1)
5026 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5030 switch (i.tm.opcode_length)
5034 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5044 /* Put out high byte first: can't use md_number_to_chars! */
5045 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5046 *p = i.tm.base_opcode & 0xff;
5048 /* On SSE5, encode the OC1 bit in the DREX field if this
5049 encoding has multiple formats. */
5050 if (i.tm.opcode_modifier.drex
5051 && i.tm.opcode_modifier.drexv
5052 && DREX_OC1 (i.tm.extension_opcode))
5053 *p |= DREX_OC1_MASK;
5056 /* Now the modrm byte and sib byte (if present). */
5057 if (i.tm.opcode_modifier.modrm)
5059 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5062 /* If i.rm.regmem == ESP (4)
5063 && i.rm.mode != (Register mode)
5065 ==> need second modrm byte. */
5066 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5068 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5069 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5071 | i.sib.scale << 6));
5074 /* Write the DREX byte if needed. */
5075 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5078 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5080 /* Encode the OC0 bit if this encoding has multiple
5082 if ((i.tm.opcode_modifier.drex
5083 || i.tm.opcode_modifier.drexv)
5084 && DREX_OC0 (i.tm.extension_opcode))
5085 *p |= DREX_OC0_MASK;
5088 if (i.disp_operands)
5089 output_disp (insn_start_frag, insn_start_off);
5092 output_imm (insn_start_frag, insn_start_off);
5098 pi ("" /*line*/, &i);
5100 #endif /* DEBUG386 */
5103 /* Return the size of the displacement operand N. */
5106 disp_size (unsigned int n)
5109 if (i.types[n].bitfield.disp64)
5111 else if (i.types[n].bitfield.disp8)
5113 else if (i.types[n].bitfield.disp16)
5118 /* Return the size of the immediate operand N. */
5121 imm_size (unsigned int n)
5124 if (i.types[n].bitfield.imm64)
5126 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5128 else if (i.types[n].bitfield.imm16)
5134 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5139 for (n = 0; n < i.operands; n++)
5141 if (operand_type_check (i.types[n], disp))
5143 if (i.op[n].disps->X_op == O_constant)
5145 int size = disp_size (n);
5148 val = offset_in_range (i.op[n].disps->X_add_number,
5150 p = frag_more (size);
5151 md_number_to_chars (p, val, size);
5155 enum bfd_reloc_code_real reloc_type;
5156 int size = disp_size (n);
5157 int sign = i.types[n].bitfield.disp32s;
5158 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5160 /* We can't have 8 bit displacement here. */
5161 assert (!i.types[n].bitfield.disp8);
5163 /* The PC relative address is computed relative
5164 to the instruction boundary, so in case immediate
5165 fields follows, we need to adjust the value. */
5166 if (pcrel && i.imm_operands)
5171 for (n1 = 0; n1 < i.operands; n1++)
5172 if (operand_type_check (i.types[n1], imm))
5174 /* Only one immediate is allowed for PC
5175 relative address. */
5178 i.op[n].disps->X_add_number -= sz;
5180 /* We should find the immediate. */
5184 p = frag_more (size);
5185 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5187 && GOT_symbol == i.op[n].disps->X_add_symbol
5188 && (((reloc_type == BFD_RELOC_32
5189 || reloc_type == BFD_RELOC_X86_64_32S
5190 || (reloc_type == BFD_RELOC_64
5192 && (i.op[n].disps->X_op == O_symbol
5193 || (i.op[n].disps->X_op == O_add
5194 && ((symbol_get_value_expression
5195 (i.op[n].disps->X_op_symbol)->X_op)
5197 || reloc_type == BFD_RELOC_32_PCREL))
5201 if (insn_start_frag == frag_now)
5202 add = (p - frag_now->fr_literal) - insn_start_off;
5207 add = insn_start_frag->fr_fix - insn_start_off;
5208 for (fr = insn_start_frag->fr_next;
5209 fr && fr != frag_now; fr = fr->fr_next)
5211 add += p - frag_now->fr_literal;
5216 reloc_type = BFD_RELOC_386_GOTPC;
5217 i.op[n].imms->X_add_number += add;
5219 else if (reloc_type == BFD_RELOC_64)
5220 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5222 /* Don't do the adjustment for x86-64, as there
5223 the pcrel addressing is relative to the _next_
5224 insn, and that is taken care of in other code. */
5225 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5227 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5228 i.op[n].disps, pcrel, reloc_type);
5235 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5240 for (n = 0; n < i.operands; n++)
5242 if (operand_type_check (i.types[n], imm))
5244 if (i.op[n].imms->X_op == O_constant)
5246 int size = imm_size (n);
5249 val = offset_in_range (i.op[n].imms->X_add_number,
5251 p = frag_more (size);
5252 md_number_to_chars (p, val, size);
5256 /* Not absolute_section.
5257 Need a 32-bit fixup (don't support 8bit
5258 non-absolute imms). Try to support other
5260 enum bfd_reloc_code_real reloc_type;
5261 int size = imm_size (n);
5264 if (i.types[n].bitfield.imm32s
5265 && (i.suffix == QWORD_MNEM_SUFFIX
5266 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5271 p = frag_more (size);
5272 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5274 /* This is tough to explain. We end up with this one if we
5275 * have operands that look like
5276 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5277 * obtain the absolute address of the GOT, and it is strongly
5278 * preferable from a performance point of view to avoid using
5279 * a runtime relocation for this. The actual sequence of
5280 * instructions often look something like:
5285 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5287 * The call and pop essentially return the absolute address
5288 * of the label .L66 and store it in %ebx. The linker itself
5289 * will ultimately change the first operand of the addl so
5290 * that %ebx points to the GOT, but to keep things simple, the
5291 * .o file must have this operand set so that it generates not
5292 * the absolute address of .L66, but the absolute address of
5293 * itself. This allows the linker itself simply treat a GOTPC
5294 * relocation as asking for a pcrel offset to the GOT to be
5295 * added in, and the addend of the relocation is stored in the
5296 * operand field for the instruction itself.
5298 * Our job here is to fix the operand so that it would add
5299 * the correct offset so that %ebx would point to itself. The
5300 * thing that is tricky is that .-.L66 will point to the
5301 * beginning of the instruction, so we need to further modify
5302 * the operand so that it will point to itself. There are
5303 * other cases where you have something like:
5305 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5307 * and here no correction would be required. Internally in
5308 * the assembler we treat operands of this form as not being
5309 * pcrel since the '.' is explicitly mentioned, and I wonder
5310 * whether it would simplify matters to do it this way. Who
5311 * knows. In earlier versions of the PIC patches, the
5312 * pcrel_adjust field was used to store the correction, but
5313 * since the expression is not pcrel, I felt it would be
5314 * confusing to do it this way. */
5316 if ((reloc_type == BFD_RELOC_32
5317 || reloc_type == BFD_RELOC_X86_64_32S
5318 || reloc_type == BFD_RELOC_64)
5320 && GOT_symbol == i.op[n].imms->X_add_symbol
5321 && (i.op[n].imms->X_op == O_symbol
5322 || (i.op[n].imms->X_op == O_add
5323 && ((symbol_get_value_expression
5324 (i.op[n].imms->X_op_symbol)->X_op)
5329 if (insn_start_frag == frag_now)
5330 add = (p - frag_now->fr_literal) - insn_start_off;
5335 add = insn_start_frag->fr_fix - insn_start_off;
5336 for (fr = insn_start_frag->fr_next;
5337 fr && fr != frag_now; fr = fr->fr_next)
5339 add += p - frag_now->fr_literal;
5343 reloc_type = BFD_RELOC_386_GOTPC;
5345 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5347 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5348 i.op[n].imms->X_add_number += add;
5350 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5351 i.op[n].imms, 0, reloc_type);
5357 /* x86_cons_fix_new is called via the expression parsing code when a
5358 reloc is needed. We use this hook to get the correct .got reloc. */
5359 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5360 static int cons_sign = -1;
5363 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5366 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5368 got_reloc = NO_RELOC;
5371 if (exp->X_op == O_secrel)
5373 exp->X_op = O_symbol;
5374 r = BFD_RELOC_32_SECREL;
5378 fix_new_exp (frag, off, len, exp, 0, r);
5381 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5382 # define lex_got(reloc, adjust, types) NULL
5384 /* Parse operands of the form
5385 <symbol>@GOTOFF+<nnn>
5386 and similar .plt or .got references.
5388 If we find one, set up the correct relocation in RELOC and copy the
5389 input string, minus the `@GOTOFF' into a malloc'd buffer for
5390 parsing by the calling routine. Return this buffer, and if ADJUST
5391 is non-null set it to the length of the string we removed from the
5392 input line. Otherwise return NULL. */
5394 lex_got (enum bfd_reloc_code_real *reloc,
5396 i386_operand_type *types)
5398 /* Some of the relocations depend on the size of what field is to
5399 be relocated. But in our callers i386_immediate and i386_displacement
5400 we don't yet know the operand size (this will be set by insn
5401 matching). Hence we record the word32 relocation here,
5402 and adjust the reloc according to the real size in reloc(). */
5403 static const struct {
5405 const enum bfd_reloc_code_real rel[2];
5406 const i386_operand_type types64;
5409 BFD_RELOC_X86_64_PLTOFF64 },
5410 OPERAND_TYPE_IMM64 },
5411 { "PLT", { BFD_RELOC_386_PLT32,
5412 BFD_RELOC_X86_64_PLT32 },
5413 OPERAND_TYPE_IMM32_32S_DISP32 },
5415 BFD_RELOC_X86_64_GOTPLT64 },
5416 OPERAND_TYPE_IMM64_DISP64 },
5417 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5418 BFD_RELOC_X86_64_GOTOFF64 },
5419 OPERAND_TYPE_IMM64_DISP64 },
5421 BFD_RELOC_X86_64_GOTPCREL },
5422 OPERAND_TYPE_IMM32_32S_DISP32 },
5423 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5424 BFD_RELOC_X86_64_TLSGD },
5425 OPERAND_TYPE_IMM32_32S_DISP32 },
5426 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5428 OPERAND_TYPE_NONE },
5430 BFD_RELOC_X86_64_TLSLD },
5431 OPERAND_TYPE_IMM32_32S_DISP32 },
5432 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5433 BFD_RELOC_X86_64_GOTTPOFF },
5434 OPERAND_TYPE_IMM32_32S_DISP32 },
5435 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5436 BFD_RELOC_X86_64_TPOFF32 },
5437 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5438 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5440 OPERAND_TYPE_NONE },
5441 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5442 BFD_RELOC_X86_64_DTPOFF32 },
5444 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5445 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5447 OPERAND_TYPE_NONE },
5448 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5450 OPERAND_TYPE_NONE },
5451 { "GOT", { BFD_RELOC_386_GOT32,
5452 BFD_RELOC_X86_64_GOT32 },
5453 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5454 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5455 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5456 OPERAND_TYPE_IMM32_32S_DISP32 },
5457 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5458 BFD_RELOC_X86_64_TLSDESC_CALL },
5459 OPERAND_TYPE_IMM32_32S_DISP32 },
5467 for (cp = input_line_pointer; *cp != '@'; cp++)
5468 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5471 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5475 len = strlen (gotrel[j].str);
5476 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5478 if (gotrel[j].rel[object_64bit] != 0)
5481 char *tmpbuf, *past_reloc;
5483 *reloc = gotrel[j].rel[object_64bit];
5489 if (flag_code != CODE_64BIT)
5491 types->bitfield.imm32 = 1;
5492 types->bitfield.disp32 = 1;
5495 *types = gotrel[j].types64;
5498 if (GOT_symbol == NULL)
5499 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5501 /* The length of the first part of our input line. */
5502 first = cp - input_line_pointer;
5504 /* The second part goes from after the reloc token until
5505 (and including) an end_of_line char or comma. */
5506 past_reloc = cp + 1 + len;
5508 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5510 second = cp + 1 - past_reloc;
5512 /* Allocate and copy string. The trailing NUL shouldn't
5513 be necessary, but be safe. */
5514 tmpbuf = xmalloc (first + second + 2);
5515 memcpy (tmpbuf, input_line_pointer, first);
5516 if (second != 0 && *past_reloc != ' ')
5517 /* Replace the relocation token with ' ', so that
5518 errors like foo@GOTOFF1 will be detected. */
5519 tmpbuf[first++] = ' ';
5520 memcpy (tmpbuf + first, past_reloc, second);
5521 tmpbuf[first + second] = '\0';
5525 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5526 gotrel[j].str, 1 << (5 + object_64bit));
5531 /* Might be a symbol version string. Don't as_bad here. */
5536 x86_cons (expressionS *exp, int size)
5538 if (size == 4 || (object_64bit && size == 8))
5540 /* Handle @GOTOFF and the like in an expression. */
5542 char *gotfree_input_line;
5545 save = input_line_pointer;
5546 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5547 if (gotfree_input_line)
5548 input_line_pointer = gotfree_input_line;
5552 if (gotfree_input_line)
5554 /* expression () has merrily parsed up to the end of line,
5555 or a comma - in the wrong buffer. Transfer how far
5556 input_line_pointer has moved to the right buffer. */
5557 input_line_pointer = (save
5558 + (input_line_pointer - gotfree_input_line)
5560 free (gotfree_input_line);
5561 if (exp->X_op == O_constant
5562 || exp->X_op == O_absent
5563 || exp->X_op == O_illegal
5564 || exp->X_op == O_register
5565 || exp->X_op == O_big)
5567 char c = *input_line_pointer;
5568 *input_line_pointer = 0;
5569 as_bad (_("missing or invalid expression `%s'"), save);
5570 *input_line_pointer = c;
5579 static void signed_cons (int size)
5581 if (flag_code == CODE_64BIT)
5589 pe_directive_secrel (dummy)
5590 int dummy ATTRIBUTE_UNUSED;
5597 if (exp.X_op == O_symbol)
5598 exp.X_op = O_secrel;
5600 emit_expr (&exp, 4);
5602 while (*input_line_pointer++ == ',');
5604 input_line_pointer--;
5605 demand_empty_rest_of_line ();
5610 i386_immediate (char *imm_start)
5612 char *save_input_line_pointer;
5613 char *gotfree_input_line;
5616 i386_operand_type types;
5618 UINTS_SET (types, ~0);
5620 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5622 as_bad (_("at most %d immediate operands are allowed"),
5623 MAX_IMMEDIATE_OPERANDS);
5627 exp = &im_expressions[i.imm_operands++];
5628 i.op[this_operand].imms = exp;
5630 if (is_space_char (*imm_start))
5633 save_input_line_pointer = input_line_pointer;
5634 input_line_pointer = imm_start;
5636 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5637 if (gotfree_input_line)
5638 input_line_pointer = gotfree_input_line;
5640 exp_seg = expression (exp);
5643 if (*input_line_pointer)
5644 as_bad (_("junk `%s' after expression"), input_line_pointer);
5646 input_line_pointer = save_input_line_pointer;
5647 if (gotfree_input_line)
5648 free (gotfree_input_line);
5650 if (exp->X_op == O_absent
5651 || exp->X_op == O_illegal
5652 || exp->X_op == O_big
5653 || (gotfree_input_line
5654 && (exp->X_op == O_constant
5655 || exp->X_op == O_register)))
5657 as_bad (_("missing or invalid immediate expression `%s'"),
5661 else if (exp->X_op == O_constant)
5663 /* Size it properly later. */
5664 i.types[this_operand].bitfield.imm64 = 1;
5665 /* If BFD64, sign extend val. */
5666 if (!use_rela_relocations
5667 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5669 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5671 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5672 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5673 && exp_seg != absolute_section
5674 && exp_seg != text_section
5675 && exp_seg != data_section
5676 && exp_seg != bss_section
5677 && exp_seg != undefined_section
5678 && !bfd_is_com_section (exp_seg))
5680 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5684 else if (!intel_syntax && exp->X_op == O_register)
5686 as_bad (_("illegal immediate register operand %s"), imm_start);
5691 /* This is an address. The size of the address will be
5692 determined later, depending on destination register,
5693 suffix, or the default for the section. */
5694 i.types[this_operand].bitfield.imm8 = 1;
5695 i.types[this_operand].bitfield.imm16 = 1;
5696 i.types[this_operand].bitfield.imm32 = 1;
5697 i.types[this_operand].bitfield.imm32s = 1;
5698 i.types[this_operand].bitfield.imm64 = 1;
5699 i.types[this_operand] = operand_type_and (i.types[this_operand],
5707 i386_scale (char *scale)
5710 char *save = input_line_pointer;
5712 input_line_pointer = scale;
5713 val = get_absolute_expression ();
5718 i.log2_scale_factor = 0;
5721 i.log2_scale_factor = 1;
5724 i.log2_scale_factor = 2;
5727 i.log2_scale_factor = 3;
5731 char sep = *input_line_pointer;
5733 *input_line_pointer = '\0';
5734 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5736 *input_line_pointer = sep;
5737 input_line_pointer = save;
5741 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5743 as_warn (_("scale factor of %d without an index register"),
5744 1 << i.log2_scale_factor);
5745 i.log2_scale_factor = 0;
5747 scale = input_line_pointer;
5748 input_line_pointer = save;
5753 i386_displacement (char *disp_start, char *disp_end)
5757 char *save_input_line_pointer;
5758 char *gotfree_input_line;
5760 i386_operand_type bigdisp, types = anydisp;
5763 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5765 as_bad (_("at most %d displacement operands are allowed"),
5766 MAX_MEMORY_OPERANDS);
5770 UINTS_CLEAR (bigdisp);
5771 if ((i.types[this_operand].bitfield.jumpabsolute)
5772 || (!current_templates->start->opcode_modifier.jump
5773 && !current_templates->start->opcode_modifier.jumpdword))
5775 bigdisp.bitfield.disp32 = 1;
5776 override = (i.prefix[ADDR_PREFIX] != 0);
5777 if (flag_code == CODE_64BIT)
5781 bigdisp.bitfield.disp32s = 1;
5782 bigdisp.bitfield.disp64 = 1;
5785 else if ((flag_code == CODE_16BIT) ^ override)
5787 bigdisp.bitfield.disp32 = 0;
5788 bigdisp.bitfield.disp16 = 1;
5793 /* For PC-relative branches, the width of the displacement
5794 is dependent upon data size, not address size. */
5795 override = (i.prefix[DATA_PREFIX] != 0);
5796 if (flag_code == CODE_64BIT)
5798 if (override || i.suffix == WORD_MNEM_SUFFIX)
5799 bigdisp.bitfield.disp16 = 1;
5802 bigdisp.bitfield.disp32 = 1;
5803 bigdisp.bitfield.disp32s = 1;
5809 override = (i.suffix == (flag_code != CODE_16BIT
5811 : LONG_MNEM_SUFFIX));
5812 bigdisp.bitfield.disp32 = 1;
5813 if ((flag_code == CODE_16BIT) ^ override)
5815 bigdisp.bitfield.disp32 = 0;
5816 bigdisp.bitfield.disp16 = 1;
5820 i.types[this_operand] = operand_type_or (i.types[this_operand],
5823 exp = &disp_expressions[i.disp_operands];
5824 i.op[this_operand].disps = exp;
5826 save_input_line_pointer = input_line_pointer;
5827 input_line_pointer = disp_start;
5828 END_STRING_AND_SAVE (disp_end);
5830 #ifndef GCC_ASM_O_HACK
5831 #define GCC_ASM_O_HACK 0
5834 END_STRING_AND_SAVE (disp_end + 1);
5835 if (i.types[this_operand].bitfield.baseIndex
5836 && displacement_string_end[-1] == '+')
5838 /* This hack is to avoid a warning when using the "o"
5839 constraint within gcc asm statements.
5842 #define _set_tssldt_desc(n,addr,limit,type) \
5843 __asm__ __volatile__ ( \
5845 "movw %w1,2+%0\n\t" \
5847 "movb %b1,4+%0\n\t" \
5848 "movb %4,5+%0\n\t" \
5849 "movb $0,6+%0\n\t" \
5850 "movb %h1,7+%0\n\t" \
5852 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5854 This works great except that the output assembler ends
5855 up looking a bit weird if it turns out that there is
5856 no offset. You end up producing code that looks like:
5869 So here we provide the missing zero. */
5871 *displacement_string_end = '0';
5874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5875 if (gotfree_input_line)
5876 input_line_pointer = gotfree_input_line;
5878 exp_seg = expression (exp);
5881 if (*input_line_pointer)
5882 as_bad (_("junk `%s' after expression"), input_line_pointer);
5884 RESTORE_END_STRING (disp_end + 1);
5886 input_line_pointer = save_input_line_pointer;
5887 if (gotfree_input_line)
5888 free (gotfree_input_line);
5891 /* We do this to make sure that the section symbol is in
5892 the symbol table. We will ultimately change the relocation
5893 to be relative to the beginning of the section. */
5894 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5895 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5898 if (exp->X_op != O_symbol)
5901 if (S_IS_LOCAL (exp->X_add_symbol)
5902 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5903 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5904 exp->X_op = O_subtract;
5905 exp->X_op_symbol = GOT_symbol;
5906 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5907 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5908 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5909 i.reloc[this_operand] = BFD_RELOC_64;
5911 i.reloc[this_operand] = BFD_RELOC_32;
5914 else if (exp->X_op == O_absent
5915 || exp->X_op == O_illegal
5916 || exp->X_op == O_big
5917 || (gotfree_input_line
5918 && (exp->X_op == O_constant
5919 || exp->X_op == O_register)))
5922 as_bad (_("missing or invalid displacement expression `%s'"),
5927 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5928 else if (exp->X_op != O_constant
5929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5930 && exp_seg != absolute_section
5931 && exp_seg != text_section
5932 && exp_seg != data_section
5933 && exp_seg != bss_section
5934 && exp_seg != undefined_section
5935 && !bfd_is_com_section (exp_seg))
5937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5942 RESTORE_END_STRING (disp_end);
5944 /* Check if this is a displacement only operand. */
5945 bigdisp = i.types[this_operand];
5946 bigdisp.bitfield.disp8 = 0;
5947 bigdisp.bitfield.disp16 = 0;
5948 bigdisp.bitfield.disp32 = 0;
5949 bigdisp.bitfield.disp32s = 0;
5950 bigdisp.bitfield.disp64 = 0;
5951 if (UINTS_ALL_ZERO (bigdisp))
5952 i.types[this_operand] = operand_type_and (i.types[this_operand],
5958 /* Make sure the memory operand we've been dealt is valid.
5959 Return 1 on success, 0 on a failure. */
5962 i386_index_check (const char *operand_string)
5965 #if INFER_ADDR_PREFIX
5971 if (flag_code == CODE_64BIT)
5974 && ((i.prefix[ADDR_PREFIX] == 0
5975 && !i.base_reg->reg_type.bitfield.reg64)
5976 || (i.prefix[ADDR_PREFIX]
5977 && !i.base_reg->reg_type.bitfield.reg32))
5979 || i.base_reg->reg_num !=
5980 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
5982 && (!i.index_reg->reg_type.bitfield.baseindex
5983 || (i.prefix[ADDR_PREFIX] == 0
5984 && i.index_reg->reg_num != RegRiz
5985 && !i.index_reg->reg_type.bitfield.reg64
5987 || (i.prefix[ADDR_PREFIX]
5988 && i.index_reg->reg_num != RegEiz
5989 && !i.index_reg->reg_type.bitfield.reg32))))
5994 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5998 && (!i.base_reg->reg_type.bitfield.reg16
5999 || !i.base_reg->reg_type.bitfield.baseindex))
6001 && (!i.index_reg->reg_type.bitfield.reg16
6002 || !i.index_reg->reg_type.bitfield.baseindex
6004 && i.base_reg->reg_num < 6
6005 && i.index_reg->reg_num >= 6
6006 && i.log2_scale_factor == 0))))
6013 && !i.base_reg->reg_type.bitfield.reg32)
6015 && ((!i.index_reg->reg_type.bitfield.reg32
6016 && i.index_reg->reg_num != RegEiz)
6017 || !i.index_reg->reg_type.bitfield.baseindex)))
6023 #if INFER_ADDR_PREFIX
6024 if (i.prefix[ADDR_PREFIX] == 0)
6026 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6028 /* Change the size of any displacement too. At most one of
6029 Disp16 or Disp32 is set.
6030 FIXME. There doesn't seem to be any real need for separate
6031 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6032 Removing them would probably clean up the code quite a lot. */
6033 if (flag_code != CODE_64BIT
6034 && (i.types[this_operand].bitfield.disp16
6035 || i.types[this_operand].bitfield.disp32))
6036 i.types[this_operand]
6037 = operand_type_xor (i.types[this_operand], disp16_32);
6042 as_bad (_("`%s' is not a valid base/index expression"),
6046 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6048 flag_code_names[flag_code]);
6053 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6057 i386_operand (char *operand_string)
6061 char *op_string = operand_string;
6063 if (is_space_char (*op_string))
6066 /* We check for an absolute prefix (differentiating,
6067 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6068 if (*op_string == ABSOLUTE_PREFIX)
6071 if (is_space_char (*op_string))
6073 i.types[this_operand].bitfield.jumpabsolute = 1;
6076 /* Check if operand is a register. */
6077 if ((r = parse_register (op_string, &end_op)) != NULL)
6079 i386_operand_type temp;
6081 /* Check for a segment override by searching for ':' after a
6082 segment register. */
6084 if (is_space_char (*op_string))
6086 if (*op_string == ':'
6087 && (r->reg_type.bitfield.sreg2
6088 || r->reg_type.bitfield.sreg3))
6093 i.seg[i.mem_operands] = &es;
6096 i.seg[i.mem_operands] = &cs;
6099 i.seg[i.mem_operands] = &ss;
6102 i.seg[i.mem_operands] = &ds;
6105 i.seg[i.mem_operands] = &fs;
6108 i.seg[i.mem_operands] = &gs;
6112 /* Skip the ':' and whitespace. */
6114 if (is_space_char (*op_string))
6117 if (!is_digit_char (*op_string)
6118 && !is_identifier_char (*op_string)
6119 && *op_string != '('
6120 && *op_string != ABSOLUTE_PREFIX)
6122 as_bad (_("bad memory operand `%s'"), op_string);
6125 /* Handle case of %es:*foo. */
6126 if (*op_string == ABSOLUTE_PREFIX)
6129 if (is_space_char (*op_string))
6131 i.types[this_operand].bitfield.jumpabsolute = 1;
6133 goto do_memory_reference;
6137 as_bad (_("junk `%s' after register"), op_string);
6141 temp.bitfield.baseindex = 0;
6142 i.types[this_operand] = operand_type_or (i.types[this_operand],
6144 i.op[this_operand].regs = r;
6147 else if (*op_string == REGISTER_PREFIX)
6149 as_bad (_("bad register name `%s'"), op_string);
6152 else if (*op_string == IMMEDIATE_PREFIX)
6155 if (i.types[this_operand].bitfield.jumpabsolute)
6157 as_bad (_("immediate operand illegal with absolute jump"));
6160 if (!i386_immediate (op_string))
6163 else if (is_digit_char (*op_string)
6164 || is_identifier_char (*op_string)
6165 || *op_string == '(')
6167 /* This is a memory reference of some sort. */
6170 /* Start and end of displacement string expression (if found). */
6171 char *displacement_string_start;
6172 char *displacement_string_end;
6174 do_memory_reference:
6175 if ((i.mem_operands == 1
6176 && !current_templates->start->opcode_modifier.isstring)
6177 || i.mem_operands == 2)
6179 as_bad (_("too many memory references for `%s'"),
6180 current_templates->start->name);
6184 /* Check for base index form. We detect the base index form by
6185 looking for an ')' at the end of the operand, searching
6186 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6188 base_string = op_string + strlen (op_string);
6191 if (is_space_char (*base_string))
6194 /* If we only have a displacement, set-up for it to be parsed later. */
6195 displacement_string_start = op_string;
6196 displacement_string_end = base_string + 1;
6198 if (*base_string == ')')
6201 unsigned int parens_balanced = 1;
6202 /* We've already checked that the number of left & right ()'s are
6203 equal, so this loop will not be infinite. */
6207 if (*base_string == ')')
6209 if (*base_string == '(')
6212 while (parens_balanced);
6214 temp_string = base_string;
6216 /* Skip past '(' and whitespace. */
6218 if (is_space_char (*base_string))
6221 if (*base_string == ','
6222 || ((i.base_reg = parse_register (base_string, &end_op))
6225 displacement_string_end = temp_string;
6227 i.types[this_operand].bitfield.baseindex = 1;
6231 base_string = end_op;
6232 if (is_space_char (*base_string))
6236 /* There may be an index reg or scale factor here. */
6237 if (*base_string == ',')
6240 if (is_space_char (*base_string))
6243 if ((i.index_reg = parse_register (base_string, &end_op))
6246 base_string = end_op;
6247 if (is_space_char (*base_string))
6249 if (*base_string == ',')
6252 if (is_space_char (*base_string))
6255 else if (*base_string != ')')
6257 as_bad (_("expecting `,' or `)' "
6258 "after index register in `%s'"),
6263 else if (*base_string == REGISTER_PREFIX)
6265 as_bad (_("bad register name `%s'"), base_string);
6269 /* Check for scale factor. */
6270 if (*base_string != ')')
6272 char *end_scale = i386_scale (base_string);
6277 base_string = end_scale;
6278 if (is_space_char (*base_string))
6280 if (*base_string != ')')
6282 as_bad (_("expecting `)' "
6283 "after scale factor in `%s'"),
6288 else if (!i.index_reg)
6290 as_bad (_("expecting index register or scale factor "
6291 "after `,'; got '%c'"),
6296 else if (*base_string != ')')
6298 as_bad (_("expecting `,' or `)' "
6299 "after base register in `%s'"),
6304 else if (*base_string == REGISTER_PREFIX)
6306 as_bad (_("bad register name `%s'"), base_string);
6311 /* If there's an expression beginning the operand, parse it,
6312 assuming displacement_string_start and
6313 displacement_string_end are meaningful. */
6314 if (displacement_string_start != displacement_string_end)
6316 if (!i386_displacement (displacement_string_start,
6317 displacement_string_end))
6321 /* Special case for (%dx) while doing input/output op. */
6323 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6325 && i.log2_scale_factor == 0
6326 && i.seg[i.mem_operands] == 0
6327 && !operand_type_check (i.types[this_operand], disp))
6329 UINTS_CLEAR (i.types[this_operand]);
6330 i.types[this_operand].bitfield.inoutportreg = 1;
6334 if (i386_index_check (operand_string) == 0)
6340 /* It's not a memory operand; argh! */
6341 as_bad (_("invalid char %s beginning operand %d `%s'"),
6342 output_invalid (*op_string),
6347 return 1; /* Normal return. */
6350 /* md_estimate_size_before_relax()
6352 Called just before relax() for rs_machine_dependent frags. The x86
6353 assembler uses these frags to handle variable size jump
6356 Any symbol that is now undefined will not become defined.
6357 Return the correct fr_subtype in the frag.
6358 Return the initial "guess for variable size of frag" to caller.
6359 The guess is actually the growth beyond the fixed part. Whatever
6360 we do to grow the fixed or variable part contributes to our
6364 md_estimate_size_before_relax (fragP, segment)
6368 /* We've already got fragP->fr_subtype right; all we have to do is
6369 check for un-relaxable symbols. On an ELF system, we can't relax
6370 an externally visible symbol, because it may be overridden by a
6372 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6375 && (S_IS_EXTERNAL (fragP->fr_symbol)
6376 || S_IS_WEAK (fragP->fr_symbol)))
6380 /* Symbol is undefined in this segment, or we need to keep a
6381 reloc so that weak symbols can be overridden. */
6382 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6383 enum bfd_reloc_code_real reloc_type;
6384 unsigned char *opcode;
6387 if (fragP->fr_var != NO_RELOC)
6388 reloc_type = fragP->fr_var;
6390 reloc_type = BFD_RELOC_16_PCREL;
6392 reloc_type = BFD_RELOC_32_PCREL;
6394 old_fr_fix = fragP->fr_fix;
6395 opcode = (unsigned char *) fragP->fr_opcode;
6397 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6400 /* Make jmp (0xeb) a (d)word displacement jump. */
6402 fragP->fr_fix += size;
6403 fix_new (fragP, old_fr_fix, size,
6405 fragP->fr_offset, 1,
6411 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6413 /* Negate the condition, and branch past an
6414 unconditional jump. */
6417 /* Insert an unconditional jump. */
6419 /* We added two extra opcode bytes, and have a two byte
6421 fragP->fr_fix += 2 + 2;
6422 fix_new (fragP, old_fr_fix + 2, 2,
6424 fragP->fr_offset, 1,
6431 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6436 fixP = fix_new (fragP, old_fr_fix, 1,
6438 fragP->fr_offset, 1,
6440 fixP->fx_signed = 1;
6444 /* This changes the byte-displacement jump 0x7N
6445 to the (d)word-displacement jump 0x0f,0x8N. */
6446 opcode[1] = opcode[0] + 0x10;
6447 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6448 /* We've added an opcode byte. */
6449 fragP->fr_fix += 1 + size;
6450 fix_new (fragP, old_fr_fix + 1, size,
6452 fragP->fr_offset, 1,
6457 BAD_CASE (fragP->fr_subtype);
6461 return fragP->fr_fix - old_fr_fix;
6464 /* Guess size depending on current relax state. Initially the relax
6465 state will correspond to a short jump and we return 1, because
6466 the variable part of the frag (the branch offset) is one byte
6467 long. However, we can relax a section more than once and in that
6468 case we must either set fr_subtype back to the unrelaxed state,
6469 or return the value for the appropriate branch. */
6470 return md_relax_table[fragP->fr_subtype].rlx_length;
6473 /* Called after relax() is finished.
6475 In: Address of frag.
6476 fr_type == rs_machine_dependent.
6477 fr_subtype is what the address relaxed to.
6479 Out: Any fixSs and constants are set up.
6480 Caller will turn frag into a ".space 0". */
6483 md_convert_frag (abfd, sec, fragP)
6484 bfd *abfd ATTRIBUTE_UNUSED;
6485 segT sec ATTRIBUTE_UNUSED;
6488 unsigned char *opcode;
6489 unsigned char *where_to_put_displacement = NULL;
6490 offsetT target_address;
6491 offsetT opcode_address;
6492 unsigned int extension = 0;
6493 offsetT displacement_from_opcode_start;
6495 opcode = (unsigned char *) fragP->fr_opcode;
6497 /* Address we want to reach in file space. */
6498 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6500 /* Address opcode resides at in file space. */
6501 opcode_address = fragP->fr_address + fragP->fr_fix;
6503 /* Displacement from opcode start to fill into instruction. */
6504 displacement_from_opcode_start = target_address - opcode_address;
6506 if ((fragP->fr_subtype & BIG) == 0)
6508 /* Don't have to change opcode. */
6509 extension = 1; /* 1 opcode + 1 displacement */
6510 where_to_put_displacement = &opcode[1];
6514 if (no_cond_jump_promotion
6515 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6516 as_warn_where (fragP->fr_file, fragP->fr_line,
6517 _("long jump required"));
6519 switch (fragP->fr_subtype)
6521 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6522 extension = 4; /* 1 opcode + 4 displacement */
6524 where_to_put_displacement = &opcode[1];
6527 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6528 extension = 2; /* 1 opcode + 2 displacement */
6530 where_to_put_displacement = &opcode[1];
6533 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6534 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6535 extension = 5; /* 2 opcode + 4 displacement */
6536 opcode[1] = opcode[0] + 0x10;
6537 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6538 where_to_put_displacement = &opcode[2];
6541 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6542 extension = 3; /* 2 opcode + 2 displacement */
6543 opcode[1] = opcode[0] + 0x10;
6544 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6545 where_to_put_displacement = &opcode[2];
6548 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6553 where_to_put_displacement = &opcode[3];
6557 BAD_CASE (fragP->fr_subtype);
6562 /* If size if less then four we are sure that the operand fits,
6563 but if it's 4, then it could be that the displacement is larger
6565 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6567 && ((addressT) (displacement_from_opcode_start - extension
6568 + ((addressT) 1 << 31))
6569 > (((addressT) 2 << 31) - 1)))
6571 as_bad_where (fragP->fr_file, fragP->fr_line,
6572 _("jump target out of range"));
6573 /* Make us emit 0. */
6574 displacement_from_opcode_start = extension;
6576 /* Now put displacement after opcode. */
6577 md_number_to_chars ((char *) where_to_put_displacement,
6578 (valueT) (displacement_from_opcode_start - extension),
6579 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6580 fragP->fr_fix += extension;
6583 /* Apply a fixup (fixS) to segment data, once it has been determined
6584 by our caller that we have all the info we need to fix it up.
6586 On the 386, immediates, displacements, and data pointers are all in
6587 the same (little-endian) format, so we don't need to care about which
6591 md_apply_fix (fixP, valP, seg)
6592 /* The fix we're to put in. */
6594 /* Pointer to the value of the bits. */
6596 /* Segment fix is from. */
6597 segT seg ATTRIBUTE_UNUSED;
6599 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6600 valueT value = *valP;
6602 #if !defined (TE_Mach)
6605 switch (fixP->fx_r_type)
6611 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6614 case BFD_RELOC_X86_64_32S:
6615 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6618 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6621 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6626 if (fixP->fx_addsy != NULL
6627 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6628 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6629 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6630 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6631 && !use_rela_relocations)
6633 /* This is a hack. There should be a better way to handle this.
6634 This covers for the fact that bfd_install_relocation will
6635 subtract the current location (for partial_inplace, PC relative
6636 relocations); see more below. */
6640 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6643 value += fixP->fx_where + fixP->fx_frag->fr_address;
6645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6648 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6651 || (symbol_section_p (fixP->fx_addsy)
6652 && sym_seg != absolute_section))
6653 && !generic_force_reloc (fixP))
6655 /* Yes, we add the values in twice. This is because
6656 bfd_install_relocation subtracts them out again. I think
6657 bfd_install_relocation is broken, but I don't dare change
6659 value += fixP->fx_where + fixP->fx_frag->fr_address;
6663 #if defined (OBJ_COFF) && defined (TE_PE)
6664 /* For some reason, the PE format does not store a
6665 section address offset for a PC relative symbol. */
6666 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6667 || S_IS_WEAK (fixP->fx_addsy))
6668 value += md_pcrel_from (fixP);
6672 /* Fix a few things - the dynamic linker expects certain values here,
6673 and we must not disappoint it. */
6674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6675 if (IS_ELF && fixP->fx_addsy)
6676 switch (fixP->fx_r_type)
6678 case BFD_RELOC_386_PLT32:
6679 case BFD_RELOC_X86_64_PLT32:
6680 /* Make the jump instruction point to the address of the operand. At
6681 runtime we merely add the offset to the actual PLT entry. */
6685 case BFD_RELOC_386_TLS_GD:
6686 case BFD_RELOC_386_TLS_LDM:
6687 case BFD_RELOC_386_TLS_IE_32:
6688 case BFD_RELOC_386_TLS_IE:
6689 case BFD_RELOC_386_TLS_GOTIE:
6690 case BFD_RELOC_386_TLS_GOTDESC:
6691 case BFD_RELOC_X86_64_TLSGD:
6692 case BFD_RELOC_X86_64_TLSLD:
6693 case BFD_RELOC_X86_64_GOTTPOFF:
6694 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6695 value = 0; /* Fully resolved at runtime. No addend. */
6697 case BFD_RELOC_386_TLS_LE:
6698 case BFD_RELOC_386_TLS_LDO_32:
6699 case BFD_RELOC_386_TLS_LE_32:
6700 case BFD_RELOC_X86_64_DTPOFF32:
6701 case BFD_RELOC_X86_64_DTPOFF64:
6702 case BFD_RELOC_X86_64_TPOFF32:
6703 case BFD_RELOC_X86_64_TPOFF64:
6704 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6707 case BFD_RELOC_386_TLS_DESC_CALL:
6708 case BFD_RELOC_X86_64_TLSDESC_CALL:
6709 value = 0; /* Fully resolved at runtime. No addend. */
6710 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6714 case BFD_RELOC_386_GOT32:
6715 case BFD_RELOC_X86_64_GOT32:
6716 value = 0; /* Fully resolved at runtime. No addend. */
6719 case BFD_RELOC_VTABLE_INHERIT:
6720 case BFD_RELOC_VTABLE_ENTRY:
6727 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6729 #endif /* !defined (TE_Mach) */
6731 /* Are we finished with this relocation now? */
6732 if (fixP->fx_addsy == NULL)
6734 else if (use_rela_relocations)
6736 fixP->fx_no_overflow = 1;
6737 /* Remember value for tc_gen_reloc. */
6738 fixP->fx_addnumber = value;
6742 md_number_to_chars (p, value, fixP->fx_size);
6746 md_atof (int type, char *litP, int *sizeP)
6748 /* This outputs the LITTLENUMs in REVERSE order;
6749 in accord with the bigendian 386. */
6750 return ieee_md_atof (type, litP, sizeP, FALSE);
6753 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6756 output_invalid (int c)
6759 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6762 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6763 "(0x%x)", (unsigned char) c);
6764 return output_invalid_buf;
6767 /* REG_STRING starts *before* REGISTER_PREFIX. */
6769 static const reg_entry *
6770 parse_real_register (char *reg_string, char **end_op)
6772 char *s = reg_string;
6774 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6777 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6778 if (*s == REGISTER_PREFIX)
6781 if (is_space_char (*s))
6785 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6787 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6788 return (const reg_entry *) NULL;
6792 /* For naked regs, make sure that we are not dealing with an identifier.
6793 This prevents confusing an identifier like `eax_var' with register
6795 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6796 return (const reg_entry *) NULL;
6800 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6802 /* Handle floating point regs, allowing spaces in the (i) part. */
6803 if (r == i386_regtab /* %st is first entry of table */)
6805 if (is_space_char (*s))
6810 if (is_space_char (*s))
6812 if (*s >= '0' && *s <= '7')
6816 if (is_space_char (*s))
6821 r = hash_find (reg_hash, "st(0)");
6826 /* We have "%st(" then garbage. */
6827 return (const reg_entry *) NULL;
6831 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6834 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6835 return (const reg_entry *) NULL;
6838 && ((r->reg_flags & (RegRex64 | RegRex))
6839 || r->reg_type.bitfield.reg64)
6840 && (!cpu_arch_flags.bitfield.cpulm
6841 || !UINTS_EQUAL (r->reg_type, control))
6842 && flag_code != CODE_64BIT)
6843 return (const reg_entry *) NULL;
6848 /* REG_STRING starts *before* REGISTER_PREFIX. */
6850 static const reg_entry *
6851 parse_register (char *reg_string, char **end_op)
6855 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6856 r = parse_real_register (reg_string, end_op);
6861 char *save = input_line_pointer;
6865 input_line_pointer = reg_string;
6866 c = get_symbol_end ();
6867 symbolP = symbol_find (reg_string);
6868 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6870 const expressionS *e = symbol_get_value_expression (symbolP);
6872 know (e->X_op == O_register);
6873 know (e->X_add_number >= 0
6874 && (valueT) e->X_add_number < i386_regtab_size);
6875 r = i386_regtab + e->X_add_number;
6876 *end_op = input_line_pointer;
6878 *input_line_pointer = c;
6879 input_line_pointer = save;
6885 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6888 char *end = input_line_pointer;
6891 r = parse_register (name, &input_line_pointer);
6892 if (r && end <= input_line_pointer)
6894 *nextcharP = *input_line_pointer;
6895 *input_line_pointer = 0;
6896 e->X_op = O_register;
6897 e->X_add_number = r - i386_regtab;
6900 input_line_pointer = end;
6906 md_operand (expressionS *e)
6908 if (*input_line_pointer == REGISTER_PREFIX)
6911 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6915 e->X_op = O_register;
6916 e->X_add_number = r - i386_regtab;
6917 input_line_pointer = end;
6923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6924 const char *md_shortopts = "kVQ:sqn";
6926 const char *md_shortopts = "qn";
6929 #define OPTION_32 (OPTION_MD_BASE + 0)
6930 #define OPTION_64 (OPTION_MD_BASE + 1)
6931 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6932 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6933 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6934 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6935 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6936 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6937 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6938 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6940 struct option md_longopts[] =
6942 {"32", no_argument, NULL, OPTION_32},
6943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6944 {"64", no_argument, NULL, OPTION_64},
6946 {"divide", no_argument, NULL, OPTION_DIVIDE},
6947 {"march", required_argument, NULL, OPTION_MARCH},
6948 {"mtune", required_argument, NULL, OPTION_MTUNE},
6949 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6950 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6951 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6952 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6953 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
6954 {NULL, no_argument, NULL, 0}
6956 size_t md_longopts_size = sizeof (md_longopts);
6959 md_parse_option (int c, char *arg)
6966 optimize_align_code = 0;
6973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6974 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6975 should be emitted or not. FIXME: Not implemented. */
6979 /* -V: SVR4 argument to print version ID. */
6981 print_version_id ();
6984 /* -k: Ignore for FreeBSD compatibility. */
6989 /* -s: On i386 Solaris, this tells the native assembler to use
6990 .stab instead of .stab.excl. We always use .stab anyhow. */
6993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6996 const char **list, **l;
6998 list = bfd_target_list ();
6999 for (l = list; *l != NULL; l++)
7000 if (CONST_STRNEQ (*l, "elf64-x86-64")
7001 || strcmp (*l, "coff-x86-64") == 0
7002 || strcmp (*l, "pe-x86-64") == 0
7003 || strcmp (*l, "pei-x86-64") == 0)
7005 default_arch = "x86_64";
7009 as_fatal (_("No compiled in support for x86_64"));
7016 default_arch = "i386";
7020 #ifdef SVR4_COMMENT_CHARS
7025 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7027 for (s = i386_comment_chars; *s != '\0'; s++)
7031 i386_comment_chars = n;
7038 as_fatal (_("Invalid -march= option: `%s'"), arg);
7039 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7041 if (strcmp (arg, cpu_arch [i].name) == 0)
7043 cpu_arch_isa = cpu_arch[i].type;
7044 cpu_arch_isa_flags = cpu_arch[i].flags;
7045 if (!cpu_arch_tune_set)
7047 cpu_arch_tune = cpu_arch_isa;
7048 cpu_arch_tune_flags = cpu_arch_isa_flags;
7053 if (i >= ARRAY_SIZE (cpu_arch))
7054 as_fatal (_("Invalid -march= option: `%s'"), arg);
7059 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7060 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7062 if (strcmp (arg, cpu_arch [i].name) == 0)
7064 cpu_arch_tune_set = 1;
7065 cpu_arch_tune = cpu_arch [i].type;
7066 cpu_arch_tune_flags = cpu_arch[i].flags;
7070 if (i >= ARRAY_SIZE (cpu_arch))
7071 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7074 case OPTION_MMNEMONIC:
7075 if (strcasecmp (arg, "att") == 0)
7077 else if (strcasecmp (arg, "intel") == 0)
7080 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7083 case OPTION_MSYNTAX:
7084 if (strcasecmp (arg, "att") == 0)
7086 else if (strcasecmp (arg, "intel") == 0)
7089 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7092 case OPTION_MINDEX_REG:
7093 allow_index_reg = 1;
7096 case OPTION_MNAKED_REG:
7097 allow_naked_reg = 1;
7100 case OPTION_MOLD_GCC:
7111 md_show_usage (stream)
7114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7115 fprintf (stream, _("\
7117 -V print assembler version number\n\
7120 fprintf (stream, _("\
7121 -n Do not optimize code alignment\n\
7122 -q quieten some warnings\n"));
7123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7124 fprintf (stream, _("\
7127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7128 fprintf (stream, _("\
7129 --32/--64 generate 32bit/64bit code\n"));
7131 #ifdef SVR4_COMMENT_CHARS
7132 fprintf (stream, _("\
7133 --divide do not treat `/' as a comment character\n"));
7135 fprintf (stream, _("\
7136 --divide ignored\n"));
7138 fprintf (stream, _("\
7139 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7140 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7141 core, core2, k6, athlon, k8, generic32, generic64\n"));
7142 fprintf (stream, _("\
7143 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7144 fprintf (stream, _("\
7145 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7146 fprintf (stream, _("\
7147 -mindex-reg support pseudo index registers\n"));
7148 fprintf (stream, _("\
7149 -mnaked-reg don't require `%%' prefix for registers\n"));
7150 fprintf (stream, _("\
7151 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7154 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7155 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7157 /* Pick the target format to use. */
7160 i386_target_format (void)
7162 if (!strcmp (default_arch, "x86_64"))
7164 set_code_flag (CODE_64BIT);
7165 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7167 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7168 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7169 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7170 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7171 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7172 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7173 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7174 cpu_arch_isa_flags.bitfield.cpummx= 1;
7175 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7176 cpu_arch_isa_flags.bitfield.cpusse = 1;
7177 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7179 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7181 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7182 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7183 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7184 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7185 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7186 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7187 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7188 cpu_arch_tune_flags.bitfield.cpummx= 1;
7189 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7190 cpu_arch_tune_flags.bitfield.cpusse = 1;
7191 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7194 else if (!strcmp (default_arch, "i386"))
7196 set_code_flag (CODE_32BIT);
7197 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7199 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7201 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7203 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7205 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7207 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7211 as_fatal (_("Unknown architecture"));
7212 switch (OUTPUT_FLAVOR)
7215 case bfd_target_coff_flavour:
7216 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7219 #ifdef OBJ_MAYBE_AOUT
7220 case bfd_target_aout_flavour:
7221 return AOUT_TARGET_FORMAT;
7223 #ifdef OBJ_MAYBE_COFF
7224 case bfd_target_coff_flavour:
7227 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7228 case bfd_target_elf_flavour:
7230 if (flag_code == CODE_64BIT)
7233 use_rela_relocations = 1;
7235 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7244 #endif /* OBJ_MAYBE_ more than one */
7246 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7248 i386_elf_emit_arch_note (void)
7250 if (IS_ELF && cpu_arch_name != NULL)
7253 asection *seg = now_seg;
7254 subsegT subseg = now_subseg;
7255 Elf_Internal_Note i_note;
7256 Elf_External_Note e_note;
7257 asection *note_secp;
7260 /* Create the .note section. */
7261 note_secp = subseg_new (".note", 0);
7262 bfd_set_section_flags (stdoutput,
7264 SEC_HAS_CONTENTS | SEC_READONLY);
7266 /* Process the arch string. */
7267 len = strlen (cpu_arch_name);
7269 i_note.namesz = len + 1;
7271 i_note.type = NT_ARCH;
7272 p = frag_more (sizeof (e_note.namesz));
7273 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7274 p = frag_more (sizeof (e_note.descsz));
7275 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7276 p = frag_more (sizeof (e_note.type));
7277 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7278 p = frag_more (len + 1);
7279 strcpy (p, cpu_arch_name);
7281 frag_align (2, 0, 0);
7283 subseg_set (seg, subseg);
7289 md_undefined_symbol (name)
7292 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7293 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7294 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7295 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7299 if (symbol_find (name))
7300 as_bad (_("GOT already in symbol table"));
7301 GOT_symbol = symbol_new (name, undefined_section,
7302 (valueT) 0, &zero_address_frag);
7309 /* Round up a section size to the appropriate boundary. */
7312 md_section_align (segment, size)
7313 segT segment ATTRIBUTE_UNUSED;
7316 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7317 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7319 /* For a.out, force the section size to be aligned. If we don't do
7320 this, BFD will align it for us, but it will not write out the
7321 final bytes of the section. This may be a bug in BFD, but it is
7322 easier to fix it here since that is how the other a.out targets
7326 align = bfd_get_section_alignment (stdoutput, segment);
7327 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7334 /* On the i386, PC-relative offsets are relative to the start of the
7335 next instruction. That is, the address of the offset, plus its
7336 size, since the offset is always the last part of the insn. */
7339 md_pcrel_from (fixS *fixP)
7341 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7347 s_bss (int ignore ATTRIBUTE_UNUSED)
7351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7353 obj_elf_section_change_hook ();
7355 temp = get_absolute_expression ();
7356 subseg_set (bss_section, (subsegT) temp);
7357 demand_empty_rest_of_line ();
7363 i386_validate_fix (fixS *fixp)
7365 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7367 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7371 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7376 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7378 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7385 tc_gen_reloc (section, fixp)
7386 asection *section ATTRIBUTE_UNUSED;
7390 bfd_reloc_code_real_type code;
7392 switch (fixp->fx_r_type)
7394 case BFD_RELOC_X86_64_PLT32:
7395 case BFD_RELOC_X86_64_GOT32:
7396 case BFD_RELOC_X86_64_GOTPCREL:
7397 case BFD_RELOC_386_PLT32:
7398 case BFD_RELOC_386_GOT32:
7399 case BFD_RELOC_386_GOTOFF:
7400 case BFD_RELOC_386_GOTPC:
7401 case BFD_RELOC_386_TLS_GD:
7402 case BFD_RELOC_386_TLS_LDM:
7403 case BFD_RELOC_386_TLS_LDO_32:
7404 case BFD_RELOC_386_TLS_IE_32:
7405 case BFD_RELOC_386_TLS_IE:
7406 case BFD_RELOC_386_TLS_GOTIE:
7407 case BFD_RELOC_386_TLS_LE_32:
7408 case BFD_RELOC_386_TLS_LE:
7409 case BFD_RELOC_386_TLS_GOTDESC:
7410 case BFD_RELOC_386_TLS_DESC_CALL:
7411 case BFD_RELOC_X86_64_TLSGD:
7412 case BFD_RELOC_X86_64_TLSLD:
7413 case BFD_RELOC_X86_64_DTPOFF32:
7414 case BFD_RELOC_X86_64_DTPOFF64:
7415 case BFD_RELOC_X86_64_GOTTPOFF:
7416 case BFD_RELOC_X86_64_TPOFF32:
7417 case BFD_RELOC_X86_64_TPOFF64:
7418 case BFD_RELOC_X86_64_GOTOFF64:
7419 case BFD_RELOC_X86_64_GOTPC32:
7420 case BFD_RELOC_X86_64_GOT64:
7421 case BFD_RELOC_X86_64_GOTPCREL64:
7422 case BFD_RELOC_X86_64_GOTPC64:
7423 case BFD_RELOC_X86_64_GOTPLT64:
7424 case BFD_RELOC_X86_64_PLTOFF64:
7425 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7426 case BFD_RELOC_X86_64_TLSDESC_CALL:
7428 case BFD_RELOC_VTABLE_ENTRY:
7429 case BFD_RELOC_VTABLE_INHERIT:
7431 case BFD_RELOC_32_SECREL:
7433 code = fixp->fx_r_type;
7435 case BFD_RELOC_X86_64_32S:
7436 if (!fixp->fx_pcrel)
7438 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7439 code = fixp->fx_r_type;
7445 switch (fixp->fx_size)
7448 as_bad_where (fixp->fx_file, fixp->fx_line,
7449 _("can not do %d byte pc-relative relocation"),
7451 code = BFD_RELOC_32_PCREL;
7453 case 1: code = BFD_RELOC_8_PCREL; break;
7454 case 2: code = BFD_RELOC_16_PCREL; break;
7455 case 4: code = BFD_RELOC_32_PCREL; break;
7457 case 8: code = BFD_RELOC_64_PCREL; break;
7463 switch (fixp->fx_size)
7466 as_bad_where (fixp->fx_file, fixp->fx_line,
7467 _("can not do %d byte relocation"),
7469 code = BFD_RELOC_32;
7471 case 1: code = BFD_RELOC_8; break;
7472 case 2: code = BFD_RELOC_16; break;
7473 case 4: code = BFD_RELOC_32; break;
7475 case 8: code = BFD_RELOC_64; break;
7482 if ((code == BFD_RELOC_32
7483 || code == BFD_RELOC_32_PCREL
7484 || code == BFD_RELOC_X86_64_32S)
7486 && fixp->fx_addsy == GOT_symbol)
7489 code = BFD_RELOC_386_GOTPC;
7491 code = BFD_RELOC_X86_64_GOTPC32;
7493 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7495 && fixp->fx_addsy == GOT_symbol)
7497 code = BFD_RELOC_X86_64_GOTPC64;
7500 rel = (arelent *) xmalloc (sizeof (arelent));
7501 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7502 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7504 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7506 if (!use_rela_relocations)
7508 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7509 vtable entry to be used in the relocation's section offset. */
7510 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7511 rel->address = fixp->fx_offset;
7515 /* Use the rela in 64bit mode. */
7518 if (!fixp->fx_pcrel)
7519 rel->addend = fixp->fx_offset;
7523 case BFD_RELOC_X86_64_PLT32:
7524 case BFD_RELOC_X86_64_GOT32:
7525 case BFD_RELOC_X86_64_GOTPCREL:
7526 case BFD_RELOC_X86_64_TLSGD:
7527 case BFD_RELOC_X86_64_TLSLD:
7528 case BFD_RELOC_X86_64_GOTTPOFF:
7529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7530 case BFD_RELOC_X86_64_TLSDESC_CALL:
7531 rel->addend = fixp->fx_offset - fixp->fx_size;
7534 rel->addend = (section->vma
7536 + fixp->fx_addnumber
7537 + md_pcrel_from (fixp));
7542 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7543 if (rel->howto == NULL)
7545 as_bad_where (fixp->fx_file, fixp->fx_line,
7546 _("cannot represent relocation type %s"),
7547 bfd_get_reloc_code_name (code));
7548 /* Set howto to a garbage value so that we can keep going. */
7549 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7550 assert (rel->howto != NULL);
7557 /* Parse operands using Intel syntax. This implements a recursive descent
7558 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7561 FIXME: We do not recognize the full operand grammar defined in the MASM
7562 documentation. In particular, all the structure/union and
7563 high-level macro operands are missing.
7565 Uppercase words are terminals, lower case words are non-terminals.
7566 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7567 bars '|' denote choices. Most grammar productions are implemented in
7568 functions called 'intel_<production>'.
7570 Initial production is 'expr'.
7576 binOp & | AND | \| | OR | ^ | XOR
7578 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7580 constant digits [[ radixOverride ]]
7582 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7620 => expr expr cmpOp e04
7623 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7624 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7626 hexdigit a | b | c | d | e | f
7627 | A | B | C | D | E | F
7633 mulOp * | / | % | MOD | << | SHL | >> | SHR
7637 register specialRegister
7641 segmentRegister CS | DS | ES | FS | GS | SS
7643 specialRegister CR0 | CR2 | CR3 | CR4
7644 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7645 | TR3 | TR4 | TR5 | TR6 | TR7
7647 We simplify the grammar in obvious places (e.g., register parsing is
7648 done by calling parse_register) and eliminate immediate left recursion
7649 to implement a recursive-descent parser.
7653 expr' cmpOp e04 expr'
7704 /* Parsing structure for the intel syntax parser. Used to implement the
7705 semantic actions for the operand grammar. */
7706 struct intel_parser_s
7708 char *op_string; /* The string being parsed. */
7709 int got_a_float; /* Whether the operand is a float. */
7710 int op_modifier; /* Operand modifier. */
7711 int is_mem; /* 1 if operand is memory reference. */
7712 int in_offset; /* >=1 if parsing operand of offset. */
7713 int in_bracket; /* >=1 if parsing operand in brackets. */
7714 const reg_entry *reg; /* Last register reference found. */
7715 char *disp; /* Displacement string being built. */
7716 char *next_operand; /* Resume point when splitting operands. */
7719 static struct intel_parser_s intel_parser;
7721 /* Token structure for parsing intel syntax. */
7724 int code; /* Token code. */
7725 const reg_entry *reg; /* Register entry for register tokens. */
7726 char *str; /* String representation. */
7729 static struct intel_token cur_token, prev_token;
7731 /* Token codes for the intel parser. Since T_SHORT is already used
7732 by COFF, undefine it first to prevent a warning. */
7751 /* Prototypes for intel parser functions. */
7752 static int intel_match_token (int);
7753 static void intel_putback_token (void);
7754 static void intel_get_token (void);
7755 static int intel_expr (void);
7756 static int intel_e04 (void);
7757 static int intel_e05 (void);
7758 static int intel_e06 (void);
7759 static int intel_e09 (void);
7760 static int intel_e10 (void);
7761 static int intel_e11 (void);
7764 i386_intel_operand (char *operand_string, int got_a_float)
7769 p = intel_parser.op_string = xstrdup (operand_string);
7770 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7774 /* Initialize token holders. */
7775 cur_token.code = prev_token.code = T_NIL;
7776 cur_token.reg = prev_token.reg = NULL;
7777 cur_token.str = prev_token.str = NULL;
7779 /* Initialize parser structure. */
7780 intel_parser.got_a_float = got_a_float;
7781 intel_parser.op_modifier = 0;
7782 intel_parser.is_mem = 0;
7783 intel_parser.in_offset = 0;
7784 intel_parser.in_bracket = 0;
7785 intel_parser.reg = NULL;
7786 intel_parser.disp[0] = '\0';
7787 intel_parser.next_operand = NULL;
7789 /* Read the first token and start the parser. */
7791 ret = intel_expr ();
7796 if (cur_token.code != T_NIL)
7798 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7799 current_templates->start->name, cur_token.str);
7802 /* If we found a memory reference, hand it over to i386_displacement
7803 to fill in the rest of the operand fields. */
7804 else if (intel_parser.is_mem)
7806 if ((i.mem_operands == 1
7807 && !current_templates->start->opcode_modifier.isstring)
7808 || i.mem_operands == 2)
7810 as_bad (_("too many memory references for '%s'"),
7811 current_templates->start->name);
7816 char *s = intel_parser.disp;
7819 if (!quiet_warnings && intel_parser.is_mem < 0)
7820 /* See the comments in intel_bracket_expr. */
7821 as_warn (_("Treating `%s' as memory reference"), operand_string);
7823 /* Add the displacement expression. */
7825 ret = i386_displacement (s, s + strlen (s));
7828 /* Swap base and index in 16-bit memory operands like
7829 [si+bx]. Since i386_index_check is also used in AT&T
7830 mode we have to do that here. */
7833 && i.base_reg->reg_type.bitfield.reg16
7834 && i.index_reg->reg_type.bitfield.reg16
7835 && i.base_reg->reg_num >= 6
7836 && i.index_reg->reg_num < 6)
7838 const reg_entry *base = i.index_reg;
7840 i.index_reg = i.base_reg;
7843 ret = i386_index_check (operand_string);
7848 /* Constant and OFFSET expressions are handled by i386_immediate. */
7849 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7850 || intel_parser.reg == NULL)
7851 ret = i386_immediate (intel_parser.disp);
7853 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7855 if (!ret || !intel_parser.next_operand)
7857 intel_parser.op_string = intel_parser.next_operand;
7858 this_operand = i.operands++;
7862 free (intel_parser.disp);
7867 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7871 expr' cmpOp e04 expr'
7876 /* XXX Implement the comparison operators. */
7877 return intel_e04 ();
7894 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7895 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7897 if (cur_token.code == '+')
7899 else if (cur_token.code == '-')
7900 nregs = NUM_ADDRESS_REGS;
7904 strcat (intel_parser.disp, cur_token.str);
7905 intel_match_token (cur_token.code);
7916 int nregs = ~NUM_ADDRESS_REGS;
7923 if (cur_token.code == '&'
7924 || cur_token.code == '|'
7925 || cur_token.code == '^')
7929 str[0] = cur_token.code;
7931 strcat (intel_parser.disp, str);
7936 intel_match_token (cur_token.code);
7941 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7942 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7953 int nregs = ~NUM_ADDRESS_REGS;
7960 if (cur_token.code == '*'
7961 || cur_token.code == '/'
7962 || cur_token.code == '%')
7966 str[0] = cur_token.code;
7968 strcat (intel_parser.disp, str);
7970 else if (cur_token.code == T_SHL)
7971 strcat (intel_parser.disp, "<<");
7972 else if (cur_token.code == T_SHR)
7973 strcat (intel_parser.disp, ">>");
7977 intel_match_token (cur_token.code);
7982 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7983 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8001 int nregs = ~NUM_ADDRESS_REGS;
8006 /* Don't consume constants here. */
8007 if (cur_token.code == '+' || cur_token.code == '-')
8009 /* Need to look one token ahead - if the next token
8010 is a constant, the current token is its sign. */
8013 intel_match_token (cur_token.code);
8014 next_code = cur_token.code;
8015 intel_putback_token ();
8016 if (next_code == T_CONST)
8020 /* e09 OFFSET e09 */
8021 if (cur_token.code == T_OFFSET)
8024 ++intel_parser.in_offset;
8028 else if (cur_token.code == T_SHORT)
8029 intel_parser.op_modifier |= 1 << T_SHORT;
8032 else if (cur_token.code == '+')
8033 strcat (intel_parser.disp, "+");
8038 else if (cur_token.code == '-' || cur_token.code == '~')
8044 str[0] = cur_token.code;
8046 strcat (intel_parser.disp, str);
8053 intel_match_token (cur_token.code);
8061 /* e09' PTR e10 e09' */
8062 if (cur_token.code == T_PTR)
8066 if (prev_token.code == T_BYTE)
8067 suffix = BYTE_MNEM_SUFFIX;
8069 else if (prev_token.code == T_WORD)
8071 if (current_templates->start->name[0] == 'l'
8072 && current_templates->start->name[2] == 's'
8073 && current_templates->start->name[3] == 0)
8074 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8075 else if (intel_parser.got_a_float == 2) /* "fi..." */
8076 suffix = SHORT_MNEM_SUFFIX;
8078 suffix = WORD_MNEM_SUFFIX;
8081 else if (prev_token.code == T_DWORD)
8083 if (current_templates->start->name[0] == 'l'
8084 && current_templates->start->name[2] == 's'
8085 && current_templates->start->name[3] == 0)
8086 suffix = WORD_MNEM_SUFFIX;
8087 else if (flag_code == CODE_16BIT
8088 && (current_templates->start->opcode_modifier.jump
8089 || current_templates->start->opcode_modifier.jumpdword))
8090 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8091 else if (intel_parser.got_a_float == 1) /* "f..." */
8092 suffix = SHORT_MNEM_SUFFIX;
8094 suffix = LONG_MNEM_SUFFIX;
8097 else if (prev_token.code == T_FWORD)
8099 if (current_templates->start->name[0] == 'l'
8100 && current_templates->start->name[2] == 's'
8101 && current_templates->start->name[3] == 0)
8102 suffix = LONG_MNEM_SUFFIX;
8103 else if (!intel_parser.got_a_float)
8105 if (flag_code == CODE_16BIT)
8106 add_prefix (DATA_PREFIX_OPCODE);
8107 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8110 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8113 else if (prev_token.code == T_QWORD)
8115 if (intel_parser.got_a_float == 1) /* "f..." */
8116 suffix = LONG_MNEM_SUFFIX;
8118 suffix = QWORD_MNEM_SUFFIX;
8121 else if (prev_token.code == T_TBYTE)
8123 if (intel_parser.got_a_float == 1)
8124 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8126 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8129 else if (prev_token.code == T_XMMWORD)
8131 suffix = XMMWORD_MNEM_SUFFIX;
8136 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8140 /* Operands for jump/call using 'ptr' notation denote absolute
8142 if (current_templates->start->opcode_modifier.jump
8143 || current_templates->start->opcode_modifier.jumpdword)
8144 i.types[this_operand].bitfield.jumpabsolute = 1;
8146 if (current_templates->start->base_opcode == 0x8d /* lea */)
8150 else if (i.suffix != suffix)
8152 as_bad (_("Conflicting operand modifiers"));
8158 /* e09' : e10 e09' */
8159 else if (cur_token.code == ':')
8161 if (prev_token.code != T_REG)
8163 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8164 segment/group identifier (which we don't have), using comma
8165 as the operand separator there is even less consistent, since
8166 there all branches only have a single operand. */
8167 if (this_operand != 0
8168 || intel_parser.in_offset
8169 || intel_parser.in_bracket
8170 || (!current_templates->start->opcode_modifier.jump
8171 && !current_templates->start->opcode_modifier.jumpdword
8172 && !current_templates->start->opcode_modifier.jumpintersegment
8173 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8174 return intel_match_token (T_NIL);
8175 /* Remember the start of the 2nd operand and terminate 1st
8177 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8178 another expression), but it gets at least the simplest case
8179 (a plain number or symbol on the left side) right. */
8180 intel_parser.next_operand = intel_parser.op_string;
8181 *--intel_parser.op_string = '\0';
8182 return intel_match_token (':');
8190 intel_match_token (cur_token.code);
8196 --intel_parser.in_offset;
8199 if (NUM_ADDRESS_REGS > nregs)
8201 as_bad (_("Invalid operand to `OFFSET'"));
8204 intel_parser.op_modifier |= 1 << T_OFFSET;
8207 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8208 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8213 intel_bracket_expr (void)
8215 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8216 const char *start = intel_parser.op_string;
8219 if (i.op[this_operand].regs)
8220 return intel_match_token (T_NIL);
8222 intel_match_token ('[');
8224 /* Mark as a memory operand only if it's not already known to be an
8225 offset expression. If it's an offset expression, we need to keep
8227 if (!intel_parser.in_offset)
8229 ++intel_parser.in_bracket;
8231 /* Operands for jump/call inside brackets denote absolute addresses. */
8232 if (current_templates->start->opcode_modifier.jump
8233 || current_templates->start->opcode_modifier.jumpdword)
8234 i.types[this_operand].bitfield.jumpabsolute = 1;
8236 /* Unfortunately gas always diverged from MASM in a respect that can't
8237 be easily fixed without risking to break code sequences likely to be
8238 encountered (the testsuite even check for this): MASM doesn't consider
8239 an expression inside brackets unconditionally as a memory reference.
8240 When that is e.g. a constant, an offset expression, or the sum of the
8241 two, this is still taken as a constant load. gas, however, always
8242 treated these as memory references. As a compromise, we'll try to make
8243 offset expressions inside brackets work the MASM way (since that's
8244 less likely to be found in real world code), but make constants alone
8245 continue to work the traditional gas way. In either case, issue a
8247 intel_parser.op_modifier &= ~was_offset;
8250 strcat (intel_parser.disp, "[");
8252 /* Add a '+' to the displacement string if necessary. */
8253 if (*intel_parser.disp != '\0'
8254 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8255 strcat (intel_parser.disp, "+");
8258 && (len = intel_parser.op_string - start - 1,
8259 intel_match_token (']')))
8261 /* Preserve brackets when the operand is an offset expression. */
8262 if (intel_parser.in_offset)
8263 strcat (intel_parser.disp, "]");
8266 --intel_parser.in_bracket;
8267 if (i.base_reg || i.index_reg)
8268 intel_parser.is_mem = 1;
8269 if (!intel_parser.is_mem)
8271 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8272 /* Defer the warning until all of the operand was parsed. */
8273 intel_parser.is_mem = -1;
8274 else if (!quiet_warnings)
8275 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8276 len, start, len, start);
8279 intel_parser.op_modifier |= was_offset;
8296 while (cur_token.code == '[')
8298 if (!intel_bracket_expr ())
8323 switch (cur_token.code)
8327 intel_match_token ('(');
8328 strcat (intel_parser.disp, "(");
8330 if (intel_expr () && intel_match_token (')'))
8332 strcat (intel_parser.disp, ")");
8339 return intel_bracket_expr ();
8344 strcat (intel_parser.disp, cur_token.str);
8345 intel_match_token (cur_token.code);
8347 /* Mark as a memory operand only if it's not already known to be an
8348 offset expression. */
8349 if (!intel_parser.in_offset)
8350 intel_parser.is_mem = 1;
8357 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8359 intel_match_token (T_REG);
8361 /* Check for segment change. */
8362 if (cur_token.code == ':')
8364 if (!reg->reg_type.bitfield.sreg2
8365 && !reg->reg_type.bitfield.sreg3)
8367 as_bad (_("`%s' is not a valid segment register"),
8371 else if (i.seg[i.mem_operands])
8372 as_warn (_("Extra segment override ignored"));
8375 if (!intel_parser.in_offset)
8376 intel_parser.is_mem = 1;
8377 switch (reg->reg_num)
8380 i.seg[i.mem_operands] = &es;
8383 i.seg[i.mem_operands] = &cs;
8386 i.seg[i.mem_operands] = &ss;
8389 i.seg[i.mem_operands] = &ds;
8392 i.seg[i.mem_operands] = &fs;
8395 i.seg[i.mem_operands] = &gs;
8401 /* Not a segment register. Check for register scaling. */
8402 else if (cur_token.code == '*')
8404 if (!intel_parser.in_bracket)
8406 as_bad (_("Register scaling only allowed in memory operands"));
8410 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8411 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8412 else if (i.index_reg)
8413 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8415 /* What follows must be a valid scale. */
8416 intel_match_token ('*');
8418 i.types[this_operand].bitfield.baseindex = 1;
8420 /* Set the scale after setting the register (otherwise,
8421 i386_scale will complain) */
8422 if (cur_token.code == '+' || cur_token.code == '-')
8424 char *str, sign = cur_token.code;
8425 intel_match_token (cur_token.code);
8426 if (cur_token.code != T_CONST)
8428 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8432 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8433 strcpy (str + 1, cur_token.str);
8435 if (!i386_scale (str))
8439 else if (!i386_scale (cur_token.str))
8441 intel_match_token (cur_token.code);
8444 /* No scaling. If this is a memory operand, the register is either a
8445 base register (first occurrence) or an index register (second
8447 else if (intel_parser.in_bracket)
8452 else if (!i.index_reg)
8456 as_bad (_("Too many register references in memory operand"));
8460 i.types[this_operand].bitfield.baseindex = 1;
8463 /* It's neither base nor index. */
8464 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8466 i386_operand_type temp = reg->reg_type;
8467 temp.bitfield.baseindex = 0;
8468 i.types[this_operand] = operand_type_or (i.types[this_operand],
8470 i.op[this_operand].regs = reg;
8475 as_bad (_("Invalid use of register"));
8479 /* Since registers are not part of the displacement string (except
8480 when we're parsing offset operands), we may need to remove any
8481 preceding '+' from the displacement string. */
8482 if (*intel_parser.disp != '\0'
8483 && !intel_parser.in_offset)
8485 char *s = intel_parser.disp;
8486 s += strlen (s) - 1;
8509 intel_match_token (cur_token.code);
8511 if (cur_token.code == T_PTR)
8514 /* It must have been an identifier. */
8515 intel_putback_token ();
8516 cur_token.code = T_ID;
8522 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8526 /* The identifier represents a memory reference only if it's not
8527 preceded by an offset modifier and if it's not an equate. */
8528 symbolP = symbol_find(cur_token.str);
8529 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8530 intel_parser.is_mem = 1;
8538 char *save_str, sign = 0;
8540 /* Allow constants that start with `+' or `-'. */
8541 if (cur_token.code == '-' || cur_token.code == '+')
8543 sign = cur_token.code;
8544 intel_match_token (cur_token.code);
8545 if (cur_token.code != T_CONST)
8547 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8553 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8554 strcpy (save_str + !!sign, cur_token.str);
8558 /* Get the next token to check for register scaling. */
8559 intel_match_token (cur_token.code);
8561 /* Check if this constant is a scaling factor for an
8563 if (cur_token.code == '*')
8565 if (intel_match_token ('*') && cur_token.code == T_REG)
8567 const reg_entry *reg = cur_token.reg;
8569 if (!intel_parser.in_bracket)
8571 as_bad (_("Register scaling only allowed "
8572 "in memory operands"));
8576 /* Disallow things like [1*si].
8577 sp and esp are invalid as index. */
8578 if (reg->reg_type.bitfield.reg16)
8579 reg = i386_regtab + REGNAM_AX + 4;
8580 else if (i.index_reg)
8581 reg = i386_regtab + REGNAM_EAX + 4;
8583 /* The constant is followed by `* reg', so it must be
8586 i.types[this_operand].bitfield.baseindex = 1;
8588 /* Set the scale after setting the register (otherwise,
8589 i386_scale will complain) */
8590 if (!i386_scale (save_str))
8592 intel_match_token (T_REG);
8594 /* Since registers are not part of the displacement
8595 string, we may need to remove any preceding '+' from
8596 the displacement string. */
8597 if (*intel_parser.disp != '\0')
8599 char *s = intel_parser.disp;
8600 s += strlen (s) - 1;
8610 /* The constant was not used for register scaling. Since we have
8611 already consumed the token following `*' we now need to put it
8612 back in the stream. */
8613 intel_putback_token ();
8616 /* Add the constant to the displacement string. */
8617 strcat (intel_parser.disp, save_str);
8624 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8628 /* Match the given token against cur_token. If they match, read the next
8629 token from the operand string. */
8631 intel_match_token (int code)
8633 if (cur_token.code == code)
8640 as_bad (_("Unexpected token `%s'"), cur_token.str);
8645 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8647 intel_get_token (void)
8650 const reg_entry *reg;
8651 struct intel_token new_token;
8653 new_token.code = T_NIL;
8654 new_token.reg = NULL;
8655 new_token.str = NULL;
8657 /* Free the memory allocated to the previous token and move
8658 cur_token to prev_token. */
8660 free (prev_token.str);
8662 prev_token = cur_token;
8664 /* Skip whitespace. */
8665 while (is_space_char (*intel_parser.op_string))
8666 intel_parser.op_string++;
8668 /* Return an empty token if we find nothing else on the line. */
8669 if (*intel_parser.op_string == '\0')
8671 cur_token = new_token;
8675 /* The new token cannot be larger than the remainder of the operand
8677 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8678 new_token.str[0] = '\0';
8680 if (strchr ("0123456789", *intel_parser.op_string))
8682 char *p = new_token.str;
8683 char *q = intel_parser.op_string;
8684 new_token.code = T_CONST;
8686 /* Allow any kind of identifier char to encompass floating point and
8687 hexadecimal numbers. */
8688 while (is_identifier_char (*q))
8692 /* Recognize special symbol names [0-9][bf]. */
8693 if (strlen (intel_parser.op_string) == 2
8694 && (intel_parser.op_string[1] == 'b'
8695 || intel_parser.op_string[1] == 'f'))
8696 new_token.code = T_ID;
8699 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8701 size_t len = end_op - intel_parser.op_string;
8703 new_token.code = T_REG;
8704 new_token.reg = reg;
8706 memcpy (new_token.str, intel_parser.op_string, len);
8707 new_token.str[len] = '\0';
8710 else if (is_identifier_char (*intel_parser.op_string))
8712 char *p = new_token.str;
8713 char *q = intel_parser.op_string;
8715 /* A '.' or '$' followed by an identifier char is an identifier.
8716 Otherwise, it's operator '.' followed by an expression. */
8717 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8719 new_token.code = '.';
8720 new_token.str[0] = '.';
8721 new_token.str[1] = '\0';
8725 while (is_identifier_char (*q) || *q == '@')
8729 if (strcasecmp (new_token.str, "NOT") == 0)
8730 new_token.code = '~';
8732 else if (strcasecmp (new_token.str, "MOD") == 0)
8733 new_token.code = '%';
8735 else if (strcasecmp (new_token.str, "AND") == 0)
8736 new_token.code = '&';
8738 else if (strcasecmp (new_token.str, "OR") == 0)
8739 new_token.code = '|';
8741 else if (strcasecmp (new_token.str, "XOR") == 0)
8742 new_token.code = '^';
8744 else if (strcasecmp (new_token.str, "SHL") == 0)
8745 new_token.code = T_SHL;
8747 else if (strcasecmp (new_token.str, "SHR") == 0)
8748 new_token.code = T_SHR;
8750 else if (strcasecmp (new_token.str, "BYTE") == 0)
8751 new_token.code = T_BYTE;
8753 else if (strcasecmp (new_token.str, "WORD") == 0)
8754 new_token.code = T_WORD;
8756 else if (strcasecmp (new_token.str, "DWORD") == 0)
8757 new_token.code = T_DWORD;
8759 else if (strcasecmp (new_token.str, "FWORD") == 0)
8760 new_token.code = T_FWORD;
8762 else if (strcasecmp (new_token.str, "QWORD") == 0)
8763 new_token.code = T_QWORD;
8765 else if (strcasecmp (new_token.str, "TBYTE") == 0
8766 /* XXX remove (gcc still uses it) */
8767 || strcasecmp (new_token.str, "XWORD") == 0)
8768 new_token.code = T_TBYTE;
8770 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8771 || strcasecmp (new_token.str, "OWORD") == 0)
8772 new_token.code = T_XMMWORD;
8774 else if (strcasecmp (new_token.str, "PTR") == 0)
8775 new_token.code = T_PTR;
8777 else if (strcasecmp (new_token.str, "SHORT") == 0)
8778 new_token.code = T_SHORT;
8780 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8782 new_token.code = T_OFFSET;
8784 /* ??? This is not mentioned in the MASM grammar but gcc
8785 makes use of it with -mintel-syntax. OFFSET may be
8786 followed by FLAT: */
8787 if (strncasecmp (q, " FLAT:", 6) == 0)
8788 strcat (new_token.str, " FLAT:");
8791 /* ??? This is not mentioned in the MASM grammar. */
8792 else if (strcasecmp (new_token.str, "FLAT") == 0)
8794 new_token.code = T_OFFSET;
8796 strcat (new_token.str, ":");
8798 as_bad (_("`:' expected"));
8802 new_token.code = T_ID;
8806 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8808 new_token.code = *intel_parser.op_string;
8809 new_token.str[0] = *intel_parser.op_string;
8810 new_token.str[1] = '\0';
8813 else if (strchr ("<>", *intel_parser.op_string)
8814 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8816 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8817 new_token.str[0] = *intel_parser.op_string;
8818 new_token.str[1] = *intel_parser.op_string;
8819 new_token.str[2] = '\0';
8823 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8825 intel_parser.op_string += strlen (new_token.str);
8826 cur_token = new_token;
8829 /* Put cur_token back into the token stream and make cur_token point to
8832 intel_putback_token (void)
8834 if (cur_token.code != T_NIL)
8836 intel_parser.op_string -= strlen (cur_token.str);
8837 free (cur_token.str);
8839 cur_token = prev_token;
8841 /* Forget prev_token. */
8842 prev_token.code = T_NIL;
8843 prev_token.reg = NULL;
8844 prev_token.str = NULL;
8848 tc_x86_regname_to_dw2regnum (char *regname)
8850 unsigned int regnum;
8851 unsigned int regnames_count;
8852 static const char *const regnames_32[] =
8854 "eax", "ecx", "edx", "ebx",
8855 "esp", "ebp", "esi", "edi",
8856 "eip", "eflags", NULL,
8857 "st0", "st1", "st2", "st3",
8858 "st4", "st5", "st6", "st7",
8860 "xmm0", "xmm1", "xmm2", "xmm3",
8861 "xmm4", "xmm5", "xmm6", "xmm7",
8862 "mm0", "mm1", "mm2", "mm3",
8863 "mm4", "mm5", "mm6", "mm7",
8864 "fcw", "fsw", "mxcsr",
8865 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8868 static const char *const regnames_64[] =
8870 "rax", "rdx", "rcx", "rbx",
8871 "rsi", "rdi", "rbp", "rsp",
8872 "r8", "r9", "r10", "r11",
8873 "r12", "r13", "r14", "r15",
8875 "xmm0", "xmm1", "xmm2", "xmm3",
8876 "xmm4", "xmm5", "xmm6", "xmm7",
8877 "xmm8", "xmm9", "xmm10", "xmm11",
8878 "xmm12", "xmm13", "xmm14", "xmm15",
8879 "st0", "st1", "st2", "st3",
8880 "st4", "st5", "st6", "st7",
8881 "mm0", "mm1", "mm2", "mm3",
8882 "mm4", "mm5", "mm6", "mm7",
8884 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8885 "fs.base", "gs.base", NULL, NULL,
8887 "mxcsr", "fcw", "fsw"
8889 const char *const *regnames;
8891 if (flag_code == CODE_64BIT)
8893 regnames = regnames_64;
8894 regnames_count = ARRAY_SIZE (regnames_64);
8898 regnames = regnames_32;
8899 regnames_count = ARRAY_SIZE (regnames_32);
8902 for (regnum = 0; regnum < regnames_count; regnum++)
8903 if (regnames[regnum] != NULL
8904 && strcmp (regname, regnames[regnum]) == 0)
8911 tc_x86_frame_initial_instructions (void)
8913 static unsigned int sp_regno;
8916 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8919 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8920 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8924 i386_elf_section_type (const char *str, size_t len)
8926 if (flag_code == CODE_64BIT
8927 && len == sizeof ("unwind") - 1
8928 && strncmp (str, "unwind", 6) == 0)
8929 return SHT_X86_64_UNWIND;
8936 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8940 expr.X_op = O_secrel;
8941 expr.X_add_symbol = symbol;
8942 expr.X_add_number = 0;
8943 emit_expr (&expr, size);
8947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8948 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8951 x86_64_section_letter (int letter, char **ptr_msg)
8953 if (flag_code == CODE_64BIT)
8956 return SHF_X86_64_LARGE;
8958 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8961 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8966 x86_64_section_word (char *str, size_t len)
8968 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8969 return SHF_X86_64_LARGE;
8975 handle_large_common (int small ATTRIBUTE_UNUSED)
8977 if (flag_code != CODE_64BIT)
8979 s_comm_internal (0, elf_common_parse);
8980 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8984 static segT lbss_section;
8985 asection *saved_com_section_ptr = elf_com_section_ptr;
8986 asection *saved_bss_section = bss_section;
8988 if (lbss_section == NULL)
8990 flagword applicable;
8992 subsegT subseg = now_subseg;
8994 /* The .lbss section is for local .largecomm symbols. */
8995 lbss_section = subseg_new (".lbss", 0);
8996 applicable = bfd_applicable_section_flags (stdoutput);
8997 bfd_set_section_flags (stdoutput, lbss_section,
8998 applicable & SEC_ALLOC);
8999 seg_info (lbss_section)->bss = 1;
9001 subseg_set (seg, subseg);
9004 elf_com_section_ptr = &_bfd_elf_large_com_section;
9005 bss_section = lbss_section;
9007 s_comm_internal (0, elf_common_parse);
9009 elf_com_section_ptr = saved_com_section_ptr;
9010 bss_section = saved_bss_section;
9013 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */