1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
461 const char line_separator_chars[] = ";";
463 /* Chars that can be used to separate mant from exp in floating point
465 const char EXP_CHARS[] = "eE";
467 /* Chars that mean this number is a floating point constant
470 const char FLT_CHARS[] = "fFdDxX";
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
501 /* The instruction we're assembling. */
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
511 /* Current operand we are working on. */
512 static int this_operand = -1;
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531 /* The ELF ABI to use. */
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
552 /* 1 for intel syntax,
554 static int intel_syntax = 0;
556 /* 1 for Intel64 ISA,
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
573 static int add_bnd_prefix = 0;
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
586 /* 1 if the assembler should generate relax relocations. */
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591 static enum check_kind
597 sse_check, operand_check = check_warning;
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
604 static int optimize = 0;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
613 static int optimize_for_space = 0;
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
658 /* Encode scalar AVX instructions with specific vector length. */
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 /* Encode EVEX WIG instructions with specific evex.w. */
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
698 #define UNCOND_JUMP 0
700 #define COND_JUMP86 2
705 #define SMALL16 (SMALL | CODE16)
707 #define BIG16 (BIG | CODE16)
711 #define INLINE __inline__
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
732 const relax_typeS md_relax_table[] =
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
771 static const arch_entry cpu_arch[] =
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1030 CPU_WAITPKG_FLAGS, 0 },
1033 static const noarch_entry cpu_noarch[] =
1035 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1036 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1037 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1038 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1039 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1040 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1041 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1042 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1043 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1047 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1048 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1064 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1065 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1069 /* Like s_lcomm_internal in gas/read.c but the alignment string
1070 is allowed to be optional. */
1073 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1080 && *input_line_pointer == ',')
1082 align = parse_align (needs_align - 1);
1084 if (align == (addressT) -1)
1099 bss_alloc (symbolP, size, align);
1104 pe_lcomm (int needs_align)
1106 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1110 const pseudo_typeS md_pseudo_table[] =
1112 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1113 {"align", s_align_bytes, 0},
1115 {"align", s_align_ptwo, 0},
1117 {"arch", set_cpu_arch, 0},
1121 {"lcomm", pe_lcomm, 1},
1123 {"ffloat", float_cons, 'f'},
1124 {"dfloat", float_cons, 'd'},
1125 {"tfloat", float_cons, 'x'},
1127 {"slong", signed_cons, 4},
1128 {"noopt", s_ignore, 0},
1129 {"optim", s_ignore, 0},
1130 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1131 {"code16", set_code_flag, CODE_16BIT},
1132 {"code32", set_code_flag, CODE_32BIT},
1134 {"code64", set_code_flag, CODE_64BIT},
1136 {"intel_syntax", set_intel_syntax, 1},
1137 {"att_syntax", set_intel_syntax, 0},
1138 {"intel_mnemonic", set_intel_mnemonic, 1},
1139 {"att_mnemonic", set_intel_mnemonic, 0},
1140 {"allow_index_reg", set_allow_index_reg, 1},
1141 {"disallow_index_reg", set_allow_index_reg, 0},
1142 {"sse_check", set_check, 0},
1143 {"operand_check", set_check, 1},
1144 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1145 {"largecomm", handle_large_common, 0},
1147 {"file", dwarf2_directive_file, 0},
1148 {"loc", dwarf2_directive_loc, 0},
1149 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1152 {"secrel32", pe_directive_secrel, 0},
1157 /* For interface with expression (). */
1158 extern char *input_line_pointer;
1160 /* Hash table for instruction mnemonic lookup. */
1161 static struct hash_control *op_hash;
1163 /* Hash table for register lookup. */
1164 static struct hash_control *reg_hash;
1166 /* Various efficient no-op patterns for aligning code labels.
1167 Note: Don't try to assemble the instructions in the comments.
1168 0L and 0w are not legal. */
1169 static const unsigned char f32_1[] =
1171 static const unsigned char f32_2[] =
1172 {0x66,0x90}; /* xchg %ax,%ax */
1173 static const unsigned char f32_3[] =
1174 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1175 static const unsigned char f32_4[] =
1176 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1177 static const unsigned char f32_6[] =
1178 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1179 static const unsigned char f32_7[] =
1180 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1181 static const unsigned char f16_3[] =
1182 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1183 static const unsigned char f16_4[] =
1184 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1185 static const unsigned char jump_disp8[] =
1186 {0xeb}; /* jmp disp8 */
1187 static const unsigned char jump32_disp32[] =
1188 {0xe9}; /* jmp disp32 */
1189 static const unsigned char jump16_disp32[] =
1190 {0x66,0xe9}; /* jmp disp32 */
1191 /* 32-bit NOPs patterns. */
1192 static const unsigned char *const f32_patt[] = {
1193 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1195 /* 16-bit NOPs patterns. */
1196 static const unsigned char *const f16_patt[] = {
1197 f32_1, f32_2, f16_3, f16_4
1199 /* nopl (%[re]ax) */
1200 static const unsigned char alt_3[] =
1202 /* nopl 0(%[re]ax) */
1203 static const unsigned char alt_4[] =
1204 {0x0f,0x1f,0x40,0x00};
1205 /* nopl 0(%[re]ax,%[re]ax,1) */
1206 static const unsigned char alt_5[] =
1207 {0x0f,0x1f,0x44,0x00,0x00};
1208 /* nopw 0(%[re]ax,%[re]ax,1) */
1209 static const unsigned char alt_6[] =
1210 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1211 /* nopl 0L(%[re]ax) */
1212 static const unsigned char alt_7[] =
1213 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1214 /* nopl 0L(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_8[] =
1216 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1217 /* nopw 0L(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_9[] =
1219 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1220 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1221 static const unsigned char alt_10[] =
1222 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1223 /* data16 nopw %cs:0L(%eax,%eax,1) */
1224 static const unsigned char alt_11[] =
1225 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* 32-bit and 64-bit NOPs patterns. */
1227 static const unsigned char *const alt_patt[] = {
1228 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1229 alt_9, alt_10, alt_11
1232 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1233 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1236 i386_output_nops (char *where, const unsigned char *const *patt,
1237 int count, int max_single_nop_size)
1240 /* Place the longer NOP first. */
1243 const unsigned char *nops = patt[max_single_nop_size - 1];
1245 /* Use the smaller one if the requsted one isn't available. */
1248 max_single_nop_size--;
1249 nops = patt[max_single_nop_size - 1];
1252 last = count % max_single_nop_size;
1255 for (offset = 0; offset < count; offset += max_single_nop_size)
1256 memcpy (where + offset, nops, max_single_nop_size);
1260 nops = patt[last - 1];
1263 /* Use the smaller one plus one-byte NOP if the needed one
1266 nops = patt[last - 1];
1267 memcpy (where + offset, nops, last);
1268 where[offset + last] = *patt[0];
1271 memcpy (where + offset, nops, last);
1276 fits_in_imm7 (offsetT num)
1278 return (num & 0x7f) == num;
1282 fits_in_imm31 (offsetT num)
1284 return (num & 0x7fffffff) == num;
1287 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1288 single NOP instruction LIMIT. */
1291 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1293 const unsigned char *const *patt = NULL;
1294 int max_single_nop_size;
1295 /* Maximum number of NOPs before switching to jump over NOPs. */
1296 int max_number_of_nops;
1298 switch (fragP->fr_type)
1307 /* We need to decide which NOP sequence to use for 32bit and
1308 64bit. When -mtune= is used:
1310 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1311 PROCESSOR_GENERIC32, f32_patt will be used.
1312 2. For the rest, alt_patt will be used.
1314 When -mtune= isn't used, alt_patt will be used if
1315 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1318 When -march= or .arch is used, we can't use anything beyond
1319 cpu_arch_isa_flags. */
1321 if (flag_code == CODE_16BIT)
1324 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1325 /* Limit number of NOPs to 2 in 16-bit mode. */
1326 max_number_of_nops = 2;
1330 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1332 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1333 switch (cpu_arch_tune)
1335 case PROCESSOR_UNKNOWN:
1336 /* We use cpu_arch_isa_flags to check if we SHOULD
1337 optimize with nops. */
1338 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1343 case PROCESSOR_PENTIUM4:
1344 case PROCESSOR_NOCONA:
1345 case PROCESSOR_CORE:
1346 case PROCESSOR_CORE2:
1347 case PROCESSOR_COREI7:
1348 case PROCESSOR_L1OM:
1349 case PROCESSOR_K1OM:
1350 case PROCESSOR_GENERIC64:
1352 case PROCESSOR_ATHLON:
1354 case PROCESSOR_AMDFAM10:
1356 case PROCESSOR_ZNVER:
1360 case PROCESSOR_I386:
1361 case PROCESSOR_I486:
1362 case PROCESSOR_PENTIUM:
1363 case PROCESSOR_PENTIUMPRO:
1364 case PROCESSOR_IAMCU:
1365 case PROCESSOR_GENERIC32:
1372 switch (fragP->tc_frag_data.tune)
1374 case PROCESSOR_UNKNOWN:
1375 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1376 PROCESSOR_UNKNOWN. */
1380 case PROCESSOR_I386:
1381 case PROCESSOR_I486:
1382 case PROCESSOR_PENTIUM:
1383 case PROCESSOR_IAMCU:
1385 case PROCESSOR_ATHLON:
1387 case PROCESSOR_AMDFAM10:
1389 case PROCESSOR_ZNVER:
1391 case PROCESSOR_GENERIC32:
1392 /* We use cpu_arch_isa_flags to check if we CAN optimize
1394 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1399 case PROCESSOR_PENTIUMPRO:
1400 case PROCESSOR_PENTIUM4:
1401 case PROCESSOR_NOCONA:
1402 case PROCESSOR_CORE:
1403 case PROCESSOR_CORE2:
1404 case PROCESSOR_COREI7:
1405 case PROCESSOR_L1OM:
1406 case PROCESSOR_K1OM:
1407 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1412 case PROCESSOR_GENERIC64:
1418 if (patt == f32_patt)
1420 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1421 /* Limit number of NOPs to 2 for older processors. */
1422 max_number_of_nops = 2;
1426 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1427 /* Limit number of NOPs to 7 for newer processors. */
1428 max_number_of_nops = 7;
1433 limit = max_single_nop_size;
1435 if (fragP->fr_type == rs_fill_nop)
1437 /* Output NOPs for .nop directive. */
1438 if (limit > max_single_nop_size)
1440 as_bad_where (fragP->fr_file, fragP->fr_line,
1441 _("invalid single nop size: %d "
1442 "(expect within [0, %d])"),
1443 limit, max_single_nop_size);
1448 fragP->fr_var = count;
1450 if ((count / max_single_nop_size) > max_number_of_nops)
1452 /* Generate jump over NOPs. */
1453 offsetT disp = count - 2;
1454 if (fits_in_imm7 (disp))
1456 /* Use "jmp disp8" if possible. */
1458 where[0] = jump_disp8[0];
1464 unsigned int size_of_jump;
1466 if (flag_code == CODE_16BIT)
1468 where[0] = jump16_disp32[0];
1469 where[1] = jump16_disp32[1];
1474 where[0] = jump32_disp32[0];
1478 count -= size_of_jump + 4;
1479 if (!fits_in_imm31 (count))
1481 as_bad_where (fragP->fr_file, fragP->fr_line,
1482 _("jump over nop padding out of range"));
1486 md_number_to_chars (where + size_of_jump, count, 4);
1487 where += size_of_jump + 4;
1491 /* Generate multiple NOPs. */
1492 i386_output_nops (where, patt, count, limit);
1496 operand_type_all_zero (const union i386_operand_type *x)
1498 switch (ARRAY_SIZE(x->array))
1509 return !x->array[0];
1516 operand_type_set (union i386_operand_type *x, unsigned int v)
1518 switch (ARRAY_SIZE(x->array))
1536 operand_type_equal (const union i386_operand_type *x,
1537 const union i386_operand_type *y)
1539 switch (ARRAY_SIZE(x->array))
1542 if (x->array[2] != y->array[2])
1546 if (x->array[1] != y->array[1])
1550 return x->array[0] == y->array[0];
1558 cpu_flags_all_zero (const union i386_cpu_flags *x)
1560 switch (ARRAY_SIZE(x->array))
1575 return !x->array[0];
1582 cpu_flags_equal (const union i386_cpu_flags *x,
1583 const union i386_cpu_flags *y)
1585 switch (ARRAY_SIZE(x->array))
1588 if (x->array[3] != y->array[3])
1592 if (x->array[2] != y->array[2])
1596 if (x->array[1] != y->array[1])
1600 return x->array[0] == y->array[0];
1608 cpu_flags_check_cpu64 (i386_cpu_flags f)
1610 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1611 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1614 static INLINE i386_cpu_flags
1615 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1617 switch (ARRAY_SIZE (x.array))
1620 x.array [3] &= y.array [3];
1623 x.array [2] &= y.array [2];
1626 x.array [1] &= y.array [1];
1629 x.array [0] &= y.array [0];
1637 static INLINE i386_cpu_flags
1638 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1640 switch (ARRAY_SIZE (x.array))
1643 x.array [3] |= y.array [3];
1646 x.array [2] |= y.array [2];
1649 x.array [1] |= y.array [1];
1652 x.array [0] |= y.array [0];
1660 static INLINE i386_cpu_flags
1661 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1663 switch (ARRAY_SIZE (x.array))
1666 x.array [3] &= ~y.array [3];
1669 x.array [2] &= ~y.array [2];
1672 x.array [1] &= ~y.array [1];
1675 x.array [0] &= ~y.array [0];
1683 #define CPU_FLAGS_ARCH_MATCH 0x1
1684 #define CPU_FLAGS_64BIT_MATCH 0x2
1686 #define CPU_FLAGS_PERFECT_MATCH \
1687 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1689 /* Return CPU flags match bits. */
1692 cpu_flags_match (const insn_template *t)
1694 i386_cpu_flags x = t->cpu_flags;
1695 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1697 x.bitfield.cpu64 = 0;
1698 x.bitfield.cpuno64 = 0;
1700 if (cpu_flags_all_zero (&x))
1702 /* This instruction is available on all archs. */
1703 match |= CPU_FLAGS_ARCH_MATCH;
1707 /* This instruction is available only on some archs. */
1708 i386_cpu_flags cpu = cpu_arch_flags;
1710 /* AVX512VL is no standalone feature - match it and then strip it. */
1711 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1713 x.bitfield.cpuavx512vl = 0;
1715 cpu = cpu_flags_and (x, cpu);
1716 if (!cpu_flags_all_zero (&cpu))
1718 if (x.bitfield.cpuavx)
1720 /* We need to check a few extra flags with AVX. */
1721 if (cpu.bitfield.cpuavx
1722 && (!t->opcode_modifier.sse2avx || sse2avx)
1723 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1724 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1725 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1726 match |= CPU_FLAGS_ARCH_MATCH;
1728 else if (x.bitfield.cpuavx512f)
1730 /* We need to check a few extra flags with AVX512F. */
1731 if (cpu.bitfield.cpuavx512f
1732 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1733 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1734 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1738 match |= CPU_FLAGS_ARCH_MATCH;
1744 static INLINE i386_operand_type
1745 operand_type_and (i386_operand_type x, i386_operand_type y)
1747 switch (ARRAY_SIZE (x.array))
1750 x.array [2] &= y.array [2];
1753 x.array [1] &= y.array [1];
1756 x.array [0] &= y.array [0];
1764 static INLINE i386_operand_type
1765 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1767 switch (ARRAY_SIZE (x.array))
1770 x.array [2] &= ~y.array [2];
1773 x.array [1] &= ~y.array [1];
1776 x.array [0] &= ~y.array [0];
1784 static INLINE i386_operand_type
1785 operand_type_or (i386_operand_type x, i386_operand_type y)
1787 switch (ARRAY_SIZE (x.array))
1790 x.array [2] |= y.array [2];
1793 x.array [1] |= y.array [1];
1796 x.array [0] |= y.array [0];
1804 static INLINE i386_operand_type
1805 operand_type_xor (i386_operand_type x, i386_operand_type y)
1807 switch (ARRAY_SIZE (x.array))
1810 x.array [2] ^= y.array [2];
1813 x.array [1] ^= y.array [1];
1816 x.array [0] ^= y.array [0];
1824 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1825 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1826 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1827 static const i386_operand_type inoutportreg
1828 = OPERAND_TYPE_INOUTPORTREG;
1829 static const i386_operand_type reg16_inoutportreg
1830 = OPERAND_TYPE_REG16_INOUTPORTREG;
1831 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1832 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1833 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1834 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1835 static const i386_operand_type anydisp
1836 = OPERAND_TYPE_ANYDISP;
1837 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1838 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1839 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1840 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1841 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1842 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1843 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1844 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1845 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1846 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1847 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1848 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1859 operand_type_check (i386_operand_type t, enum operand_type c)
1864 return t.bitfield.reg;
1867 return (t.bitfield.imm8
1871 || t.bitfield.imm32s
1872 || t.bitfield.imm64);
1875 return (t.bitfield.disp8
1876 || t.bitfield.disp16
1877 || t.bitfield.disp32
1878 || t.bitfield.disp32s
1879 || t.bitfield.disp64);
1882 return (t.bitfield.disp8
1883 || t.bitfield.disp16
1884 || t.bitfield.disp32
1885 || t.bitfield.disp32s
1886 || t.bitfield.disp64
1887 || t.bitfield.baseindex);
1896 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1897 operand J for instruction template T. */
1900 match_reg_size (const insn_template *t, unsigned int j)
1902 return !((i.types[j].bitfield.byte
1903 && !t->operand_types[j].bitfield.byte)
1904 || (i.types[j].bitfield.word
1905 && !t->operand_types[j].bitfield.word)
1906 || (i.types[j].bitfield.dword
1907 && !t->operand_types[j].bitfield.dword)
1908 || (i.types[j].bitfield.qword
1909 && !t->operand_types[j].bitfield.qword)
1910 || (i.types[j].bitfield.tbyte
1911 && !t->operand_types[j].bitfield.tbyte));
1914 /* Return 1 if there is no conflict in SIMD register on
1915 operand J for instruction template T. */
1918 match_simd_size (const insn_template *t, unsigned int j)
1920 return !((i.types[j].bitfield.xmmword
1921 && !t->operand_types[j].bitfield.xmmword)
1922 || (i.types[j].bitfield.ymmword
1923 && !t->operand_types[j].bitfield.ymmword)
1924 || (i.types[j].bitfield.zmmword
1925 && !t->operand_types[j].bitfield.zmmword));
1928 /* Return 1 if there is no conflict in any size on operand J for
1929 instruction template T. */
1932 match_mem_size (const insn_template *t, unsigned int j)
1934 return (match_reg_size (t, j)
1935 && !((i.types[j].bitfield.unspecified
1937 && !t->operand_types[j].bitfield.unspecified)
1938 || (i.types[j].bitfield.fword
1939 && !t->operand_types[j].bitfield.fword)
1940 /* For scalar opcode templates to allow register and memory
1941 operands at the same time, some special casing is needed
1942 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1943 down-conversion vpmov*. */
1944 || ((t->operand_types[j].bitfield.regsimd
1945 && !t->opcode_modifier.broadcast
1946 && (t->operand_types[j].bitfield.byte
1947 || t->operand_types[j].bitfield.word
1948 || t->operand_types[j].bitfield.dword
1949 || t->operand_types[j].bitfield.qword))
1950 ? (i.types[j].bitfield.xmmword
1951 || i.types[j].bitfield.ymmword
1952 || i.types[j].bitfield.zmmword)
1953 : !match_simd_size(t, j))));
1956 /* Return 1 if there is no size conflict on any operands for
1957 instruction template T. */
1960 operand_size_match (const insn_template *t)
1965 /* Don't check jump instructions. */
1966 if (t->opcode_modifier.jump
1967 || t->opcode_modifier.jumpbyte
1968 || t->opcode_modifier.jumpdword
1969 || t->opcode_modifier.jumpintersegment)
1972 /* Check memory and accumulator operand size. */
1973 for (j = 0; j < i.operands; j++)
1975 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1976 && t->operand_types[j].bitfield.anysize)
1979 if (t->operand_types[j].bitfield.reg
1980 && !match_reg_size (t, j))
1986 if (t->operand_types[j].bitfield.regsimd
1987 && !match_simd_size (t, j))
1993 if (t->operand_types[j].bitfield.acc
1994 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2000 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2009 else if (!t->opcode_modifier.d)
2012 i.error = operand_size_mismatch;
2016 /* Check reverse. */
2017 gas_assert (i.operands == 2);
2020 for (j = 0; j < 2; j++)
2022 if ((t->operand_types[j].bitfield.reg
2023 || t->operand_types[j].bitfield.acc)
2024 && !match_reg_size (t, j ? 0 : 1))
2027 if (i.types[j].bitfield.mem
2028 && !match_mem_size (t, j ? 0 : 1))
2036 operand_type_match (i386_operand_type overlap,
2037 i386_operand_type given)
2039 i386_operand_type temp = overlap;
2041 temp.bitfield.jumpabsolute = 0;
2042 temp.bitfield.unspecified = 0;
2043 temp.bitfield.byte = 0;
2044 temp.bitfield.word = 0;
2045 temp.bitfield.dword = 0;
2046 temp.bitfield.fword = 0;
2047 temp.bitfield.qword = 0;
2048 temp.bitfield.tbyte = 0;
2049 temp.bitfield.xmmword = 0;
2050 temp.bitfield.ymmword = 0;
2051 temp.bitfield.zmmword = 0;
2052 if (operand_type_all_zero (&temp))
2055 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2056 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2060 i.error = operand_type_mismatch;
2064 /* If given types g0 and g1 are registers they must be of the same type
2065 unless the expected operand type register overlap is null.
2066 Memory operand size of certain SIMD instructions is also being checked
2070 operand_type_register_match (i386_operand_type g0,
2071 i386_operand_type t0,
2072 i386_operand_type g1,
2073 i386_operand_type t1)
2075 if (!g0.bitfield.reg
2076 && !g0.bitfield.regsimd
2077 && (!operand_type_check (g0, anymem)
2078 || g0.bitfield.unspecified
2079 || !t0.bitfield.regsimd))
2082 if (!g1.bitfield.reg
2083 && !g1.bitfield.regsimd
2084 && (!operand_type_check (g1, anymem)
2085 || g1.bitfield.unspecified
2086 || !t1.bitfield.regsimd))
2089 if (g0.bitfield.byte == g1.bitfield.byte
2090 && g0.bitfield.word == g1.bitfield.word
2091 && g0.bitfield.dword == g1.bitfield.dword
2092 && g0.bitfield.qword == g1.bitfield.qword
2093 && g0.bitfield.xmmword == g1.bitfield.xmmword
2094 && g0.bitfield.ymmword == g1.bitfield.ymmword
2095 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2098 if (!(t0.bitfield.byte & t1.bitfield.byte)
2099 && !(t0.bitfield.word & t1.bitfield.word)
2100 && !(t0.bitfield.dword & t1.bitfield.dword)
2101 && !(t0.bitfield.qword & t1.bitfield.qword)
2102 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2103 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2104 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2107 i.error = register_type_mismatch;
2112 static INLINE unsigned int
2113 register_number (const reg_entry *r)
2115 unsigned int nr = r->reg_num;
2117 if (r->reg_flags & RegRex)
2120 if (r->reg_flags & RegVRex)
2126 static INLINE unsigned int
2127 mode_from_disp_size (i386_operand_type t)
2129 if (t.bitfield.disp8)
2131 else if (t.bitfield.disp16
2132 || t.bitfield.disp32
2133 || t.bitfield.disp32s)
2140 fits_in_signed_byte (addressT num)
2142 return num + 0x80 <= 0xff;
2146 fits_in_unsigned_byte (addressT num)
2152 fits_in_unsigned_word (addressT num)
2154 return num <= 0xffff;
2158 fits_in_signed_word (addressT num)
2160 return num + 0x8000 <= 0xffff;
2164 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2169 return num + 0x80000000 <= 0xffffffff;
2171 } /* fits_in_signed_long() */
2174 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2179 return num <= 0xffffffff;
2181 } /* fits_in_unsigned_long() */
2184 fits_in_disp8 (offsetT num)
2186 int shift = i.memshift;
2192 mask = (1 << shift) - 1;
2194 /* Return 0 if NUM isn't properly aligned. */
2198 /* Check if NUM will fit in 8bit after shift. */
2199 return fits_in_signed_byte (num >> shift);
2203 fits_in_imm4 (offsetT num)
2205 return (num & 0xf) == num;
2208 static i386_operand_type
2209 smallest_imm_type (offsetT num)
2211 i386_operand_type t;
2213 operand_type_set (&t, 0);
2214 t.bitfield.imm64 = 1;
2216 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2218 /* This code is disabled on the 486 because all the Imm1 forms
2219 in the opcode table are slower on the i486. They're the
2220 versions with the implicitly specified single-position
2221 displacement, which has another syntax if you really want to
2223 t.bitfield.imm1 = 1;
2224 t.bitfield.imm8 = 1;
2225 t.bitfield.imm8s = 1;
2226 t.bitfield.imm16 = 1;
2227 t.bitfield.imm32 = 1;
2228 t.bitfield.imm32s = 1;
2230 else if (fits_in_signed_byte (num))
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm8s = 1;
2234 t.bitfield.imm16 = 1;
2235 t.bitfield.imm32 = 1;
2236 t.bitfield.imm32s = 1;
2238 else if (fits_in_unsigned_byte (num))
2240 t.bitfield.imm8 = 1;
2241 t.bitfield.imm16 = 1;
2242 t.bitfield.imm32 = 1;
2243 t.bitfield.imm32s = 1;
2245 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2251 else if (fits_in_signed_long (num))
2253 t.bitfield.imm32 = 1;
2254 t.bitfield.imm32s = 1;
2256 else if (fits_in_unsigned_long (num))
2257 t.bitfield.imm32 = 1;
2263 offset_in_range (offsetT val, int size)
2269 case 1: mask = ((addressT) 1 << 8) - 1; break;
2270 case 2: mask = ((addressT) 1 << 16) - 1; break;
2271 case 4: mask = ((addressT) 2 << 31) - 1; break;
2273 case 8: mask = ((addressT) 2 << 63) - 1; break;
2279 /* If BFD64, sign extend val for 32bit address mode. */
2280 if (flag_code != CODE_64BIT
2281 || i.prefix[ADDR_PREFIX])
2282 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2283 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2286 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2288 char buf1[40], buf2[40];
2290 sprint_value (buf1, val);
2291 sprint_value (buf2, val & mask);
2292 as_warn (_("%s shortened to %s"), buf1, buf2);
2307 a. PREFIX_EXIST if attempting to add a prefix where one from the
2308 same class already exists.
2309 b. PREFIX_LOCK if lock prefix is added.
2310 c. PREFIX_REP if rep/repne prefix is added.
2311 d. PREFIX_DS if ds prefix is added.
2312 e. PREFIX_OTHER if other prefix is added.
2315 static enum PREFIX_GROUP
2316 add_prefix (unsigned int prefix)
2318 enum PREFIX_GROUP ret = PREFIX_OTHER;
2321 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2322 && flag_code == CODE_64BIT)
2324 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2325 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2326 && (prefix & (REX_R | REX_X | REX_B))))
2337 case DS_PREFIX_OPCODE:
2340 case CS_PREFIX_OPCODE:
2341 case ES_PREFIX_OPCODE:
2342 case FS_PREFIX_OPCODE:
2343 case GS_PREFIX_OPCODE:
2344 case SS_PREFIX_OPCODE:
2348 case REPNE_PREFIX_OPCODE:
2349 case REPE_PREFIX_OPCODE:
2354 case LOCK_PREFIX_OPCODE:
2363 case ADDR_PREFIX_OPCODE:
2367 case DATA_PREFIX_OPCODE:
2371 if (i.prefix[q] != 0)
2379 i.prefix[q] |= prefix;
2382 as_bad (_("same type of prefix used twice"));
2388 update_code_flag (int value, int check)
2390 PRINTF_LIKE ((*as_error));
2392 flag_code = (enum flag_code) value;
2393 if (flag_code == CODE_64BIT)
2395 cpu_arch_flags.bitfield.cpu64 = 1;
2396 cpu_arch_flags.bitfield.cpuno64 = 0;
2400 cpu_arch_flags.bitfield.cpu64 = 0;
2401 cpu_arch_flags.bitfield.cpuno64 = 1;
2403 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2406 as_error = as_fatal;
2409 (*as_error) (_("64bit mode not supported on `%s'."),
2410 cpu_arch_name ? cpu_arch_name : default_arch);
2412 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2415 as_error = as_fatal;
2418 (*as_error) (_("32bit mode not supported on `%s'."),
2419 cpu_arch_name ? cpu_arch_name : default_arch);
2421 stackop_size = '\0';
2425 set_code_flag (int value)
2427 update_code_flag (value, 0);
2431 set_16bit_gcc_code_flag (int new_code_flag)
2433 flag_code = (enum flag_code) new_code_flag;
2434 if (flag_code != CODE_16BIT)
2436 cpu_arch_flags.bitfield.cpu64 = 0;
2437 cpu_arch_flags.bitfield.cpuno64 = 1;
2438 stackop_size = LONG_MNEM_SUFFIX;
2442 set_intel_syntax (int syntax_flag)
2444 /* Find out if register prefixing is specified. */
2445 int ask_naked_reg = 0;
2448 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2451 int e = get_symbol_name (&string);
2453 if (strcmp (string, "prefix") == 0)
2455 else if (strcmp (string, "noprefix") == 0)
2458 as_bad (_("bad argument to syntax directive."));
2459 (void) restore_line_pointer (e);
2461 demand_empty_rest_of_line ();
2463 intel_syntax = syntax_flag;
2465 if (ask_naked_reg == 0)
2466 allow_naked_reg = (intel_syntax
2467 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2469 allow_naked_reg = (ask_naked_reg < 0);
2471 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2473 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2474 identifier_chars['$'] = intel_syntax ? '$' : 0;
2475 register_prefix = allow_naked_reg ? "" : "%";
2479 set_intel_mnemonic (int mnemonic_flag)
2481 intel_mnemonic = mnemonic_flag;
2485 set_allow_index_reg (int flag)
2487 allow_index_reg = flag;
2491 set_check (int what)
2493 enum check_kind *kind;
2498 kind = &operand_check;
2509 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2512 int e = get_symbol_name (&string);
2514 if (strcmp (string, "none") == 0)
2516 else if (strcmp (string, "warning") == 0)
2517 *kind = check_warning;
2518 else if (strcmp (string, "error") == 0)
2519 *kind = check_error;
2521 as_bad (_("bad argument to %s_check directive."), str);
2522 (void) restore_line_pointer (e);
2525 as_bad (_("missing argument for %s_check directive"), str);
2527 demand_empty_rest_of_line ();
2531 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2532 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2535 static const char *arch;
2537 /* Intel LIOM is only supported on ELF. */
2543 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2544 use default_arch. */
2545 arch = cpu_arch_name;
2547 arch = default_arch;
2550 /* If we are targeting Intel MCU, we must enable it. */
2551 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2552 || new_flag.bitfield.cpuiamcu)
2555 /* If we are targeting Intel L1OM, we must enable it. */
2556 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2557 || new_flag.bitfield.cpul1om)
2560 /* If we are targeting Intel K1OM, we must enable it. */
2561 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2562 || new_flag.bitfield.cpuk1om)
2565 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2570 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2574 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2577 int e = get_symbol_name (&string);
2579 i386_cpu_flags flags;
2581 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2583 if (strcmp (string, cpu_arch[j].name) == 0)
2585 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2589 cpu_arch_name = cpu_arch[j].name;
2590 cpu_sub_arch_name = NULL;
2591 cpu_arch_flags = cpu_arch[j].flags;
2592 if (flag_code == CODE_64BIT)
2594 cpu_arch_flags.bitfield.cpu64 = 1;
2595 cpu_arch_flags.bitfield.cpuno64 = 0;
2599 cpu_arch_flags.bitfield.cpu64 = 0;
2600 cpu_arch_flags.bitfield.cpuno64 = 1;
2602 cpu_arch_isa = cpu_arch[j].type;
2603 cpu_arch_isa_flags = cpu_arch[j].flags;
2604 if (!cpu_arch_tune_set)
2606 cpu_arch_tune = cpu_arch_isa;
2607 cpu_arch_tune_flags = cpu_arch_isa_flags;
2612 flags = cpu_flags_or (cpu_arch_flags,
2615 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2617 if (cpu_sub_arch_name)
2619 char *name = cpu_sub_arch_name;
2620 cpu_sub_arch_name = concat (name,
2622 (const char *) NULL);
2626 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2627 cpu_arch_flags = flags;
2628 cpu_arch_isa_flags = flags;
2632 = cpu_flags_or (cpu_arch_isa_flags,
2634 (void) restore_line_pointer (e);
2635 demand_empty_rest_of_line ();
2640 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2642 /* Disable an ISA extension. */
2643 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2644 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2646 flags = cpu_flags_and_not (cpu_arch_flags,
2647 cpu_noarch[j].flags);
2648 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2650 if (cpu_sub_arch_name)
2652 char *name = cpu_sub_arch_name;
2653 cpu_sub_arch_name = concat (name, string,
2654 (const char *) NULL);
2658 cpu_sub_arch_name = xstrdup (string);
2659 cpu_arch_flags = flags;
2660 cpu_arch_isa_flags = flags;
2662 (void) restore_line_pointer (e);
2663 demand_empty_rest_of_line ();
2667 j = ARRAY_SIZE (cpu_arch);
2670 if (j >= ARRAY_SIZE (cpu_arch))
2671 as_bad (_("no such architecture: `%s'"), string);
2673 *input_line_pointer = e;
2676 as_bad (_("missing cpu architecture"));
2678 no_cond_jump_promotion = 0;
2679 if (*input_line_pointer == ','
2680 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2685 ++input_line_pointer;
2686 e = get_symbol_name (&string);
2688 if (strcmp (string, "nojumps") == 0)
2689 no_cond_jump_promotion = 1;
2690 else if (strcmp (string, "jumps") == 0)
2693 as_bad (_("no such architecture modifier: `%s'"), string);
2695 (void) restore_line_pointer (e);
2698 demand_empty_rest_of_line ();
2701 enum bfd_architecture
2704 if (cpu_arch_isa == PROCESSOR_L1OM)
2706 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2707 || flag_code != CODE_64BIT)
2708 as_fatal (_("Intel L1OM is 64bit ELF only"));
2709 return bfd_arch_l1om;
2711 else if (cpu_arch_isa == PROCESSOR_K1OM)
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel K1OM is 64bit ELF only"));
2716 return bfd_arch_k1om;
2718 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code == CODE_64BIT)
2722 as_fatal (_("Intel MCU is 32bit ELF only"));
2723 return bfd_arch_iamcu;
2726 return bfd_arch_i386;
2732 if (!strncmp (default_arch, "x86_64", 6))
2734 if (cpu_arch_isa == PROCESSOR_L1OM)
2736 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2737 || default_arch[6] != '\0')
2738 as_fatal (_("Intel L1OM is 64bit ELF only"));
2739 return bfd_mach_l1om;
2741 else if (cpu_arch_isa == PROCESSOR_K1OM)
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel K1OM is 64bit ELF only"));
2746 return bfd_mach_k1om;
2748 else if (default_arch[6] == '\0')
2749 return bfd_mach_x86_64;
2751 return bfd_mach_x64_32;
2753 else if (!strcmp (default_arch, "i386")
2754 || !strcmp (default_arch, "iamcu"))
2756 if (cpu_arch_isa == PROCESSOR_IAMCU)
2758 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2759 as_fatal (_("Intel MCU is 32bit ELF only"));
2760 return bfd_mach_i386_iamcu;
2763 return bfd_mach_i386_i386;
2766 as_fatal (_("unknown architecture"));
2772 const char *hash_err;
2774 /* Support pseudo prefixes like {disp32}. */
2775 lex_type ['{'] = LEX_BEGIN_NAME;
2777 /* Initialize op_hash hash table. */
2778 op_hash = hash_new ();
2781 const insn_template *optab;
2782 templates *core_optab;
2784 /* Setup for loop. */
2786 core_optab = XNEW (templates);
2787 core_optab->start = optab;
2792 if (optab->name == NULL
2793 || strcmp (optab->name, (optab - 1)->name) != 0)
2795 /* different name --> ship out current template list;
2796 add to hash table; & begin anew. */
2797 core_optab->end = optab;
2798 hash_err = hash_insert (op_hash,
2800 (void *) core_optab);
2803 as_fatal (_("can't hash %s: %s"),
2807 if (optab->name == NULL)
2809 core_optab = XNEW (templates);
2810 core_optab->start = optab;
2815 /* Initialize reg_hash hash table. */
2816 reg_hash = hash_new ();
2818 const reg_entry *regtab;
2819 unsigned int regtab_size = i386_regtab_size;
2821 for (regtab = i386_regtab; regtab_size--; regtab++)
2823 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2825 as_fatal (_("can't hash %s: %s"),
2831 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2836 for (c = 0; c < 256; c++)
2841 mnemonic_chars[c] = c;
2842 register_chars[c] = c;
2843 operand_chars[c] = c;
2845 else if (ISLOWER (c))
2847 mnemonic_chars[c] = c;
2848 register_chars[c] = c;
2849 operand_chars[c] = c;
2851 else if (ISUPPER (c))
2853 mnemonic_chars[c] = TOLOWER (c);
2854 register_chars[c] = mnemonic_chars[c];
2855 operand_chars[c] = c;
2857 else if (c == '{' || c == '}')
2859 mnemonic_chars[c] = c;
2860 operand_chars[c] = c;
2863 if (ISALPHA (c) || ISDIGIT (c))
2864 identifier_chars[c] = c;
2867 identifier_chars[c] = c;
2868 operand_chars[c] = c;
2873 identifier_chars['@'] = '@';
2876 identifier_chars['?'] = '?';
2877 operand_chars['?'] = '?';
2879 digit_chars['-'] = '-';
2880 mnemonic_chars['_'] = '_';
2881 mnemonic_chars['-'] = '-';
2882 mnemonic_chars['.'] = '.';
2883 identifier_chars['_'] = '_';
2884 identifier_chars['.'] = '.';
2886 for (p = operand_special_chars; *p != '\0'; p++)
2887 operand_chars[(unsigned char) *p] = *p;
2890 if (flag_code == CODE_64BIT)
2892 #if defined (OBJ_COFF) && defined (TE_PE)
2893 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2896 x86_dwarf2_return_column = 16;
2898 x86_cie_data_alignment = -8;
2902 x86_dwarf2_return_column = 8;
2903 x86_cie_data_alignment = -4;
2908 i386_print_statistics (FILE *file)
2910 hash_print_statistics (file, "i386 opcode", op_hash);
2911 hash_print_statistics (file, "i386 register", reg_hash);
2916 /* Debugging routines for md_assemble. */
2917 static void pte (insn_template *);
2918 static void pt (i386_operand_type);
2919 static void pe (expressionS *);
2920 static void ps (symbolS *);
2923 pi (char *line, i386_insn *x)
2927 fprintf (stdout, "%s: template ", line);
2929 fprintf (stdout, " address: base %s index %s scale %x\n",
2930 x->base_reg ? x->base_reg->reg_name : "none",
2931 x->index_reg ? x->index_reg->reg_name : "none",
2932 x->log2_scale_factor);
2933 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2934 x->rm.mode, x->rm.reg, x->rm.regmem);
2935 fprintf (stdout, " sib: base %x index %x scale %x\n",
2936 x->sib.base, x->sib.index, x->sib.scale);
2937 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2938 (x->rex & REX_W) != 0,
2939 (x->rex & REX_R) != 0,
2940 (x->rex & REX_X) != 0,
2941 (x->rex & REX_B) != 0);
2942 for (j = 0; j < x->operands; j++)
2944 fprintf (stdout, " #%d: ", j + 1);
2946 fprintf (stdout, "\n");
2947 if (x->types[j].bitfield.reg
2948 || x->types[j].bitfield.regmmx
2949 || x->types[j].bitfield.regsimd
2950 || x->types[j].bitfield.sreg2
2951 || x->types[j].bitfield.sreg3
2952 || x->types[j].bitfield.control
2953 || x->types[j].bitfield.debug
2954 || x->types[j].bitfield.test)
2955 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2956 if (operand_type_check (x->types[j], imm))
2958 if (operand_type_check (x->types[j], disp))
2959 pe (x->op[j].disps);
2964 pte (insn_template *t)
2967 fprintf (stdout, " %d operands ", t->operands);
2968 fprintf (stdout, "opcode %x ", t->base_opcode);
2969 if (t->extension_opcode != None)
2970 fprintf (stdout, "ext %x ", t->extension_opcode);
2971 if (t->opcode_modifier.d)
2972 fprintf (stdout, "D");
2973 if (t->opcode_modifier.w)
2974 fprintf (stdout, "W");
2975 fprintf (stdout, "\n");
2976 for (j = 0; j < t->operands; j++)
2978 fprintf (stdout, " #%d type ", j + 1);
2979 pt (t->operand_types[j]);
2980 fprintf (stdout, "\n");
2987 fprintf (stdout, " operation %d\n", e->X_op);
2988 fprintf (stdout, " add_number %ld (%lx)\n",
2989 (long) e->X_add_number, (long) e->X_add_number);
2990 if (e->X_add_symbol)
2992 fprintf (stdout, " add_symbol ");
2993 ps (e->X_add_symbol);
2994 fprintf (stdout, "\n");
2998 fprintf (stdout, " op_symbol ");
2999 ps (e->X_op_symbol);
3000 fprintf (stdout, "\n");
3007 fprintf (stdout, "%s type %s%s",
3009 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3010 segment_name (S_GET_SEGMENT (s)));
3013 static struct type_name
3015 i386_operand_type mask;
3018 const type_names[] =
3020 { OPERAND_TYPE_REG8, "r8" },
3021 { OPERAND_TYPE_REG16, "r16" },
3022 { OPERAND_TYPE_REG32, "r32" },
3023 { OPERAND_TYPE_REG64, "r64" },
3024 { OPERAND_TYPE_IMM8, "i8" },
3025 { OPERAND_TYPE_IMM8, "i8s" },
3026 { OPERAND_TYPE_IMM16, "i16" },
3027 { OPERAND_TYPE_IMM32, "i32" },
3028 { OPERAND_TYPE_IMM32S, "i32s" },
3029 { OPERAND_TYPE_IMM64, "i64" },
3030 { OPERAND_TYPE_IMM1, "i1" },
3031 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3032 { OPERAND_TYPE_DISP8, "d8" },
3033 { OPERAND_TYPE_DISP16, "d16" },
3034 { OPERAND_TYPE_DISP32, "d32" },
3035 { OPERAND_TYPE_DISP32S, "d32s" },
3036 { OPERAND_TYPE_DISP64, "d64" },
3037 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3038 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3039 { OPERAND_TYPE_CONTROL, "control reg" },
3040 { OPERAND_TYPE_TEST, "test reg" },
3041 { OPERAND_TYPE_DEBUG, "debug reg" },
3042 { OPERAND_TYPE_FLOATREG, "FReg" },
3043 { OPERAND_TYPE_FLOATACC, "FAcc" },
3044 { OPERAND_TYPE_SREG2, "SReg2" },
3045 { OPERAND_TYPE_SREG3, "SReg3" },
3046 { OPERAND_TYPE_ACC, "Acc" },
3047 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3048 { OPERAND_TYPE_REGMMX, "rMMX" },
3049 { OPERAND_TYPE_REGXMM, "rXMM" },
3050 { OPERAND_TYPE_REGYMM, "rYMM" },
3051 { OPERAND_TYPE_REGZMM, "rZMM" },
3052 { OPERAND_TYPE_REGMASK, "Mask reg" },
3053 { OPERAND_TYPE_ESSEG, "es" },
3057 pt (i386_operand_type t)
3060 i386_operand_type a;
3062 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3064 a = operand_type_and (t, type_names[j].mask);
3065 if (!operand_type_all_zero (&a))
3066 fprintf (stdout, "%s, ", type_names[j].name);
3071 #endif /* DEBUG386 */
3073 static bfd_reloc_code_real_type
3074 reloc (unsigned int size,
3077 bfd_reloc_code_real_type other)
3079 if (other != NO_RELOC)
3081 reloc_howto_type *rel;
3086 case BFD_RELOC_X86_64_GOT32:
3087 return BFD_RELOC_X86_64_GOT64;
3089 case BFD_RELOC_X86_64_GOTPLT64:
3090 return BFD_RELOC_X86_64_GOTPLT64;
3092 case BFD_RELOC_X86_64_PLTOFF64:
3093 return BFD_RELOC_X86_64_PLTOFF64;
3095 case BFD_RELOC_X86_64_GOTPC32:
3096 other = BFD_RELOC_X86_64_GOTPC64;
3098 case BFD_RELOC_X86_64_GOTPCREL:
3099 other = BFD_RELOC_X86_64_GOTPCREL64;
3101 case BFD_RELOC_X86_64_TPOFF32:
3102 other = BFD_RELOC_X86_64_TPOFF64;
3104 case BFD_RELOC_X86_64_DTPOFF32:
3105 other = BFD_RELOC_X86_64_DTPOFF64;
3111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3112 if (other == BFD_RELOC_SIZE32)
3115 other = BFD_RELOC_SIZE64;
3118 as_bad (_("there are no pc-relative size relocations"));
3124 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3125 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3128 rel = bfd_reloc_type_lookup (stdoutput, other);
3130 as_bad (_("unknown relocation (%u)"), other);
3131 else if (size != bfd_get_reloc_size (rel))
3132 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3133 bfd_get_reloc_size (rel),
3135 else if (pcrel && !rel->pc_relative)
3136 as_bad (_("non-pc-relative relocation for pc-relative field"));
3137 else if ((rel->complain_on_overflow == complain_overflow_signed
3139 || (rel->complain_on_overflow == complain_overflow_unsigned
3141 as_bad (_("relocated field and relocation type differ in signedness"));
3150 as_bad (_("there are no unsigned pc-relative relocations"));
3153 case 1: return BFD_RELOC_8_PCREL;
3154 case 2: return BFD_RELOC_16_PCREL;
3155 case 4: return BFD_RELOC_32_PCREL;
3156 case 8: return BFD_RELOC_64_PCREL;
3158 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3165 case 4: return BFD_RELOC_X86_64_32S;
3170 case 1: return BFD_RELOC_8;
3171 case 2: return BFD_RELOC_16;
3172 case 4: return BFD_RELOC_32;
3173 case 8: return BFD_RELOC_64;
3175 as_bad (_("cannot do %s %u byte relocation"),
3176 sign > 0 ? "signed" : "unsigned", size);
3182 /* Here we decide which fixups can be adjusted to make them relative to
3183 the beginning of the section instead of the symbol. Basically we need
3184 to make sure that the dynamic relocations are done correctly, so in
3185 some cases we force the original symbol to be used. */
3188 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3194 /* Don't adjust pc-relative references to merge sections in 64-bit
3196 if (use_rela_relocations
3197 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3201 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3202 and changed later by validate_fix. */
3203 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3204 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3207 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3208 for size relocations. */
3209 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3210 || fixP->fx_r_type == BFD_RELOC_SIZE64
3211 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3212 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3213 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3214 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3240 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3241 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3248 intel_float_operand (const char *mnemonic)
3250 /* Note that the value returned is meaningful only for opcodes with (memory)
3251 operands, hence the code here is free to improperly handle opcodes that
3252 have no operands (for better performance and smaller code). */
3254 if (mnemonic[0] != 'f')
3255 return 0; /* non-math */
3257 switch (mnemonic[1])
3259 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3260 the fs segment override prefix not currently handled because no
3261 call path can make opcodes without operands get here */
3263 return 2 /* integer op */;
3265 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3266 return 3; /* fldcw/fldenv */
3269 if (mnemonic[2] != 'o' /* fnop */)
3270 return 3; /* non-waiting control op */
3273 if (mnemonic[2] == 's')
3274 return 3; /* frstor/frstpm */
3277 if (mnemonic[2] == 'a')
3278 return 3; /* fsave */
3279 if (mnemonic[2] == 't')
3281 switch (mnemonic[3])
3283 case 'c': /* fstcw */
3284 case 'd': /* fstdw */
3285 case 'e': /* fstenv */
3286 case 's': /* fsts[gw] */
3292 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3293 return 0; /* fxsave/fxrstor are not really math ops */
3300 /* Build the VEX prefix. */
3303 build_vex_prefix (const insn_template *t)
3305 unsigned int register_specifier;
3306 unsigned int implied_prefix;
3307 unsigned int vector_length;
3309 /* Check register specifier. */
3310 if (i.vex.register_specifier)
3312 register_specifier =
3313 ~register_number (i.vex.register_specifier) & 0xf;
3314 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3317 register_specifier = 0xf;
3319 /* Use 2-byte VEX prefix by swapping destination and source
3321 if (i.vec_encoding != vex_encoding_vex3
3322 && i.dir_encoding == dir_encoding_default
3323 && i.operands == i.reg_operands
3324 && i.tm.opcode_modifier.vexopcode == VEX0F
3325 && i.tm.opcode_modifier.load
3328 unsigned int xchg = i.operands - 1;
3329 union i386_op temp_op;
3330 i386_operand_type temp_type;
3332 temp_type = i.types[xchg];
3333 i.types[xchg] = i.types[0];
3334 i.types[0] = temp_type;
3335 temp_op = i.op[xchg];
3336 i.op[xchg] = i.op[0];
3339 gas_assert (i.rm.mode == 3);
3343 i.rm.regmem = i.rm.reg;
3346 /* Use the next insn. */
3350 if (i.tm.opcode_modifier.vex == VEXScalar)
3351 vector_length = avxscalar;
3352 else if (i.tm.opcode_modifier.vex == VEX256)
3359 for (op = 0; op < t->operands; ++op)
3360 if (t->operand_types[op].bitfield.xmmword
3361 && t->operand_types[op].bitfield.ymmword
3362 && i.types[op].bitfield.ymmword)
3369 switch ((i.tm.base_opcode >> 8) & 0xff)
3374 case DATA_PREFIX_OPCODE:
3377 case REPE_PREFIX_OPCODE:
3380 case REPNE_PREFIX_OPCODE:
3387 /* Use 2-byte VEX prefix if possible. */
3388 if (i.vec_encoding != vex_encoding_vex3
3389 && i.tm.opcode_modifier.vexopcode == VEX0F
3390 && i.tm.opcode_modifier.vexw != VEXW1
3391 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3393 /* 2-byte VEX prefix. */
3397 i.vex.bytes[0] = 0xc5;
3399 /* Check the REX.R bit. */
3400 r = (i.rex & REX_R) ? 0 : 1;
3401 i.vex.bytes[1] = (r << 7
3402 | register_specifier << 3
3403 | vector_length << 2
3408 /* 3-byte VEX prefix. */
3413 switch (i.tm.opcode_modifier.vexopcode)
3417 i.vex.bytes[0] = 0xc4;
3421 i.vex.bytes[0] = 0xc4;
3425 i.vex.bytes[0] = 0xc4;
3429 i.vex.bytes[0] = 0x8f;
3433 i.vex.bytes[0] = 0x8f;
3437 i.vex.bytes[0] = 0x8f;
3443 /* The high 3 bits of the second VEX byte are 1's compliment
3444 of RXB bits from REX. */
3445 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3447 /* Check the REX.W bit. */
3448 w = (i.rex & REX_W) ? 1 : 0;
3449 if (i.tm.opcode_modifier.vexw == VEXW1)
3452 i.vex.bytes[2] = (w << 7
3453 | register_specifier << 3
3454 | vector_length << 2
3459 static INLINE bfd_boolean
3460 is_evex_encoding (const insn_template *t)
3462 return t->opcode_modifier.evex
3463 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3464 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3467 /* Build the EVEX prefix. */
3470 build_evex_prefix (void)
3472 unsigned int register_specifier;
3473 unsigned int implied_prefix;
3475 rex_byte vrex_used = 0;
3477 /* Check register specifier. */
3478 if (i.vex.register_specifier)
3480 gas_assert ((i.vrex & REX_X) == 0);
3482 register_specifier = i.vex.register_specifier->reg_num;
3483 if ((i.vex.register_specifier->reg_flags & RegRex))
3484 register_specifier += 8;
3485 /* The upper 16 registers are encoded in the fourth byte of the
3487 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3488 i.vex.bytes[3] = 0x8;
3489 register_specifier = ~register_specifier & 0xf;
3493 register_specifier = 0xf;
3495 /* Encode upper 16 vector index register in the fourth byte of
3497 if (!(i.vrex & REX_X))
3498 i.vex.bytes[3] = 0x8;
3503 switch ((i.tm.base_opcode >> 8) & 0xff)
3508 case DATA_PREFIX_OPCODE:
3511 case REPE_PREFIX_OPCODE:
3514 case REPNE_PREFIX_OPCODE:
3521 /* 4 byte EVEX prefix. */
3523 i.vex.bytes[0] = 0x62;
3526 switch (i.tm.opcode_modifier.vexopcode)
3542 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3544 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3546 /* The fifth bit of the second EVEX byte is 1's compliment of the
3547 REX_R bit in VREX. */
3548 if (!(i.vrex & REX_R))
3549 i.vex.bytes[1] |= 0x10;
3553 if ((i.reg_operands + i.imm_operands) == i.operands)
3555 /* When all operands are registers, the REX_X bit in REX is not
3556 used. We reuse it to encode the upper 16 registers, which is
3557 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3558 as 1's compliment. */
3559 if ((i.vrex & REX_B))
3562 i.vex.bytes[1] &= ~0x40;
3566 /* EVEX instructions shouldn't need the REX prefix. */
3567 i.vrex &= ~vrex_used;
3568 gas_assert (i.vrex == 0);
3570 /* Check the REX.W bit. */
3571 w = (i.rex & REX_W) ? 1 : 0;
3572 if (i.tm.opcode_modifier.vexw)
3574 if (i.tm.opcode_modifier.vexw == VEXW1)
3577 /* If w is not set it means we are dealing with WIG instruction. */
3580 if (evexwig == evexw1)
3584 /* Encode the U bit. */
3585 implied_prefix |= 0x4;
3587 /* The third byte of the EVEX prefix. */
3588 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3590 /* The fourth byte of the EVEX prefix. */
3591 /* The zeroing-masking bit. */
3592 if (i.mask && i.mask->zeroing)
3593 i.vex.bytes[3] |= 0x80;
3595 /* Don't always set the broadcast bit if there is no RC. */
3598 /* Encode the vector length. */
3599 unsigned int vec_length;
3601 if (!i.tm.opcode_modifier.evex
3602 || i.tm.opcode_modifier.evex == EVEXDYN)
3607 for (op = 0; op < i.tm.operands; ++op)
3608 if (i.tm.operand_types[op].bitfield.xmmword
3609 + i.tm.operand_types[op].bitfield.ymmword
3610 + i.tm.operand_types[op].bitfield.zmmword > 1)
3612 if (i.types[op].bitfield.zmmword)
3613 i.tm.opcode_modifier.evex = EVEX512;
3614 else if (i.types[op].bitfield.ymmword)
3615 i.tm.opcode_modifier.evex = EVEX256;
3616 else if (i.types[op].bitfield.xmmword)
3617 i.tm.opcode_modifier.evex = EVEX128;
3624 switch (i.tm.opcode_modifier.evex)
3626 case EVEXLIG: /* LL' is ignored */
3627 vec_length = evexlig << 5;
3630 vec_length = 0 << 5;
3633 vec_length = 1 << 5;
3636 vec_length = 2 << 5;
3642 i.vex.bytes[3] |= vec_length;
3643 /* Encode the broadcast bit. */
3645 i.vex.bytes[3] |= 0x10;
3649 if (i.rounding->type != saeonly)
3650 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3652 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3655 if (i.mask && i.mask->mask)
3656 i.vex.bytes[3] |= i.mask->mask->reg_num;
3660 process_immext (void)
3664 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3667 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3668 with an opcode suffix which is coded in the same place as an
3669 8-bit immediate field would be.
3670 Here we check those operands and remove them afterwards. */
3673 for (x = 0; x < i.operands; x++)
3674 if (register_number (i.op[x].regs) != x)
3675 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3676 register_prefix, i.op[x].regs->reg_name, x + 1,
3682 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3684 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3685 suffix which is coded in the same place as an 8-bit immediate
3687 Here we check those operands and remove them afterwards. */
3690 if (i.operands != 3)
3693 for (x = 0; x < 2; x++)
3694 if (register_number (i.op[x].regs) != x)
3695 goto bad_register_operand;
3697 /* Check for third operand for mwaitx/monitorx insn. */
3698 if (register_number (i.op[x].regs)
3699 != (x + (i.tm.extension_opcode == 0xfb)))
3701 bad_register_operand:
3702 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3703 register_prefix, i.op[x].regs->reg_name, x+1,
3710 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3711 which is coded in the same place as an 8-bit immediate field
3712 would be. Here we fake an 8-bit immediate operand from the
3713 opcode suffix stored in tm.extension_opcode.
3715 AVX instructions also use this encoding, for some of
3716 3 argument instructions. */
3718 gas_assert (i.imm_operands <= 1
3720 || ((i.tm.opcode_modifier.vex
3721 || i.tm.opcode_modifier.vexopcode
3722 || is_evex_encoding (&i.tm))
3723 && i.operands <= 4)));
3725 exp = &im_expressions[i.imm_operands++];
3726 i.op[i.operands].imms = exp;
3727 i.types[i.operands] = imm8;
3729 exp->X_op = O_constant;
3730 exp->X_add_number = i.tm.extension_opcode;
3731 i.tm.extension_opcode = None;
3738 switch (i.tm.opcode_modifier.hleprefixok)
3743 as_bad (_("invalid instruction `%s' after `%s'"),
3744 i.tm.name, i.hle_prefix);
3747 if (i.prefix[LOCK_PREFIX])
3749 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3753 case HLEPrefixRelease:
3754 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3756 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3760 if (i.mem_operands == 0
3761 || !operand_type_check (i.types[i.operands - 1], anymem))
3763 as_bad (_("memory destination needed for instruction `%s'"
3764 " after `xrelease'"), i.tm.name);
3771 /* Try the shortest encoding by shortening operand size. */
3774 optimize_encoding (void)
3778 if (optimize_for_space
3779 && i.reg_operands == 1
3780 && i.imm_operands == 1
3781 && !i.types[1].bitfield.byte
3782 && i.op[0].imms->X_op == O_constant
3783 && fits_in_imm7 (i.op[0].imms->X_add_number)
3784 && ((i.tm.base_opcode == 0xa8
3785 && i.tm.extension_opcode == None)
3786 || (i.tm.base_opcode == 0xf6
3787 && i.tm.extension_opcode == 0x0)))
3790 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3792 unsigned int base_regnum = i.op[1].regs->reg_num;
3793 if (flag_code == CODE_64BIT || base_regnum < 4)
3795 i.types[1].bitfield.byte = 1;
3796 /* Ignore the suffix. */
3798 if (base_regnum >= 4
3799 && !(i.op[1].regs->reg_flags & RegRex))
3801 /* Handle SP, BP, SI and DI registers. */
3802 if (i.types[1].bitfield.word)
3804 else if (i.types[1].bitfield.dword)
3812 else if (flag_code == CODE_64BIT
3813 && ((i.types[1].bitfield.qword
3814 && i.reg_operands == 1
3815 && i.imm_operands == 1
3816 && i.op[0].imms->X_op == O_constant
3817 && ((i.tm.base_opcode == 0xb0
3818 && i.tm.extension_opcode == None
3819 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3820 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3821 && (((i.tm.base_opcode == 0x24
3822 || i.tm.base_opcode == 0xa8)
3823 && i.tm.extension_opcode == None)
3824 || (i.tm.base_opcode == 0x80
3825 && i.tm.extension_opcode == 0x4)
3826 || ((i.tm.base_opcode == 0xf6
3827 || i.tm.base_opcode == 0xc6)
3828 && i.tm.extension_opcode == 0x0)))))
3829 || (i.types[0].bitfield.qword
3830 && ((i.reg_operands == 2
3831 && i.op[0].regs == i.op[1].regs
3832 && ((i.tm.base_opcode == 0x30
3833 || i.tm.base_opcode == 0x28)
3834 && i.tm.extension_opcode == None))
3835 || (i.reg_operands == 1
3837 && i.tm.base_opcode == 0x30
3838 && i.tm.extension_opcode == None)))))
3841 andq $imm31, %r64 -> andl $imm31, %r32
3842 testq $imm31, %r64 -> testl $imm31, %r32
3843 xorq %r64, %r64 -> xorl %r32, %r32
3844 subq %r64, %r64 -> subl %r32, %r32
3845 movq $imm31, %r64 -> movl $imm31, %r32
3846 movq $imm32, %r64 -> movl $imm32, %r32
3848 i.tm.opcode_modifier.norex64 = 1;
3849 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3855 i.tm.operand_types[0].bitfield.imm32 = 1;
3856 i.tm.operand_types[0].bitfield.imm32s = 0;
3857 i.tm.operand_types[0].bitfield.imm64 = 0;
3858 i.types[0].bitfield.imm32 = 1;
3859 i.types[0].bitfield.imm32s = 0;
3860 i.types[0].bitfield.imm64 = 0;
3861 i.types[1].bitfield.dword = 1;
3862 i.types[1].bitfield.qword = 0;
3863 if (i.tm.base_opcode == 0xc6)
3866 movq $imm31, %r64 -> movl $imm31, %r32
3868 i.tm.base_opcode = 0xb0;
3869 i.tm.extension_opcode = None;
3870 i.tm.opcode_modifier.shortform = 1;
3871 i.tm.opcode_modifier.modrm = 0;
3875 else if (optimize > 1
3876 && i.reg_operands == 3
3877 && i.op[0].regs == i.op[1].regs
3878 && !i.types[2].bitfield.xmmword
3879 && (i.tm.opcode_modifier.vex
3882 && is_evex_encoding (&i.tm)
3883 && (i.vec_encoding != vex_encoding_evex
3884 || i.tm.cpu_flags.bitfield.cpuavx512vl
3885 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3886 && ((i.tm.base_opcode == 0x55
3887 || i.tm.base_opcode == 0x6655
3888 || i.tm.base_opcode == 0x66df
3889 || i.tm.base_opcode == 0x57
3890 || i.tm.base_opcode == 0x6657
3891 || i.tm.base_opcode == 0x66ef
3892 || i.tm.base_opcode == 0x66f8
3893 || i.tm.base_opcode == 0x66f9
3894 || i.tm.base_opcode == 0x66fa
3895 || i.tm.base_opcode == 0x66fb)
3896 && i.tm.extension_opcode == None))
3899 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3901 EVEX VOP %zmmM, %zmmM, %zmmN
3902 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3904 EVEX VOP %ymmM, %ymmM, %ymmN
3905 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3906 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3907 VEX VOP %ymmM, %ymmM, %ymmN
3908 -> VEX VOP %xmmM, %xmmM, %xmmN
3909 VOP, one of vpandn and vpxor:
3910 VEX VOP %ymmM, %ymmM, %ymmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN
3912 VOP, one of vpandnd and vpandnq:
3913 EVEX VOP %zmmM, %zmmM, %zmmN
3914 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 EVEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3918 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3919 VOP, one of vpxord and vpxorq:
3920 EVEX VOP %zmmM, %zmmM, %zmmN
3921 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3922 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3923 EVEX VOP %ymmM, %ymmM, %ymmN
3924 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3925 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3927 if (is_evex_encoding (&i.tm))
3929 if (i.vec_encoding == vex_encoding_evex)
3930 i.tm.opcode_modifier.evex = EVEX128;
3933 i.tm.opcode_modifier.vex = VEX128;
3934 i.tm.opcode_modifier.vexw = VEXW0;
3935 i.tm.opcode_modifier.evex = 0;
3939 i.tm.opcode_modifier.vex = VEX128;
3941 if (i.tm.opcode_modifier.vex)
3942 for (j = 0; j < 3; j++)
3944 i.types[j].bitfield.xmmword = 1;
3945 i.types[j].bitfield.ymmword = 0;
3950 /* This is the guts of the machine-dependent assembler. LINE points to a
3951 machine dependent instruction. This function is supposed to emit
3952 the frags/bytes it assembles to. */
3955 md_assemble (char *line)
3958 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3959 const insn_template *t;
3961 /* Initialize globals. */
3962 memset (&i, '\0', sizeof (i));
3963 for (j = 0; j < MAX_OPERANDS; j++)
3964 i.reloc[j] = NO_RELOC;
3965 memset (disp_expressions, '\0', sizeof (disp_expressions));
3966 memset (im_expressions, '\0', sizeof (im_expressions));
3967 save_stack_p = save_stack;
3969 /* First parse an instruction mnemonic & call i386_operand for the operands.
3970 We assume that the scrubber has arranged it so that line[0] is the valid
3971 start of a (possibly prefixed) mnemonic. */
3973 line = parse_insn (line, mnemonic);
3976 mnem_suffix = i.suffix;
3978 line = parse_operands (line, mnemonic);
3980 xfree (i.memop1_string);
3981 i.memop1_string = NULL;
3985 /* Now we've parsed the mnemonic into a set of templates, and have the
3986 operands at hand. */
3988 /* All intel opcodes have reversed operands except for "bound" and
3989 "enter". We also don't reverse intersegment "jmp" and "call"
3990 instructions with 2 immediate operands so that the immediate segment
3991 precedes the offset, as it does when in AT&T mode. */
3994 && (strcmp (mnemonic, "bound") != 0)
3995 && (strcmp (mnemonic, "invlpga") != 0)
3996 && !(operand_type_check (i.types[0], imm)
3997 && operand_type_check (i.types[1], imm)))
4000 /* The order of the immediates should be reversed
4001 for 2 immediates extrq and insertq instructions */
4002 if (i.imm_operands == 2
4003 && (strcmp (mnemonic, "extrq") == 0
4004 || strcmp (mnemonic, "insertq") == 0))
4005 swap_2_operands (0, 1);
4010 /* Don't optimize displacement for movabs since it only takes 64bit
4013 && i.disp_encoding != disp_encoding_32bit
4014 && (flag_code != CODE_64BIT
4015 || strcmp (mnemonic, "movabs") != 0))
4018 /* Next, we find a template that matches the given insn,
4019 making sure the overlap of the given operands types is consistent
4020 with the template operand types. */
4022 if (!(t = match_template (mnem_suffix)))
4025 if (sse_check != check_none
4026 && !i.tm.opcode_modifier.noavx
4027 && !i.tm.cpu_flags.bitfield.cpuavx
4028 && (i.tm.cpu_flags.bitfield.cpusse
4029 || i.tm.cpu_flags.bitfield.cpusse2
4030 || i.tm.cpu_flags.bitfield.cpusse3
4031 || i.tm.cpu_flags.bitfield.cpussse3
4032 || i.tm.cpu_flags.bitfield.cpusse4_1
4033 || i.tm.cpu_flags.bitfield.cpusse4_2
4034 || i.tm.cpu_flags.bitfield.cpupclmul
4035 || i.tm.cpu_flags.bitfield.cpuaes
4036 || i.tm.cpu_flags.bitfield.cpugfni))
4038 (sse_check == check_warning
4040 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4043 /* Zap movzx and movsx suffix. The suffix has been set from
4044 "word ptr" or "byte ptr" on the source operand in Intel syntax
4045 or extracted from mnemonic in AT&T syntax. But we'll use
4046 the destination register to choose the suffix for encoding. */
4047 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4049 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4050 there is no suffix, the default will be byte extension. */
4051 if (i.reg_operands != 2
4054 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4059 if (i.tm.opcode_modifier.fwait)
4060 if (!add_prefix (FWAIT_OPCODE))
4063 /* Check if REP prefix is OK. */
4064 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4066 as_bad (_("invalid instruction `%s' after `%s'"),
4067 i.tm.name, i.rep_prefix);
4071 /* Check for lock without a lockable instruction. Destination operand
4072 must be memory unless it is xchg (0x86). */
4073 if (i.prefix[LOCK_PREFIX]
4074 && (!i.tm.opcode_modifier.islockable
4075 || i.mem_operands == 0
4076 || (i.tm.base_opcode != 0x86
4077 && !operand_type_check (i.types[i.operands - 1], anymem))))
4079 as_bad (_("expecting lockable instruction after `lock'"));
4083 /* Check if HLE prefix is OK. */
4084 if (i.hle_prefix && !check_hle ())
4087 /* Check BND prefix. */
4088 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4089 as_bad (_("expecting valid branch instruction after `bnd'"));
4091 /* Check NOTRACK prefix. */
4092 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4093 as_bad (_("expecting indirect branch instruction after `notrack'"));
4095 if (i.tm.cpu_flags.bitfield.cpumpx)
4097 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4098 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4099 else if (flag_code != CODE_16BIT
4100 ? i.prefix[ADDR_PREFIX]
4101 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4102 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4105 /* Insert BND prefix. */
4107 && i.tm.opcode_modifier.bndprefixok
4108 && !i.prefix[BND_PREFIX])
4109 add_prefix (BND_PREFIX_OPCODE);
4111 /* Check string instruction segment overrides. */
4112 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4114 if (!check_string ())
4116 i.disp_operands = 0;
4119 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4120 optimize_encoding ();
4122 if (!process_suffix ())
4125 /* Update operand types. */
4126 for (j = 0; j < i.operands; j++)
4127 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4129 /* Make still unresolved immediate matches conform to size of immediate
4130 given in i.suffix. */
4131 if (!finalize_imm ())
4134 if (i.types[0].bitfield.imm1)
4135 i.imm_operands = 0; /* kludge for shift insns. */
4137 /* We only need to check those implicit registers for instructions
4138 with 3 operands or less. */
4139 if (i.operands <= 3)
4140 for (j = 0; j < i.operands; j++)
4141 if (i.types[j].bitfield.inoutportreg
4142 || i.types[j].bitfield.shiftcount
4143 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4146 /* ImmExt should be processed after SSE2AVX. */
4147 if (!i.tm.opcode_modifier.sse2avx
4148 && i.tm.opcode_modifier.immext)
4151 /* For insns with operands there are more diddles to do to the opcode. */
4154 if (!process_operands ())
4157 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4159 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4160 as_warn (_("translating to `%sp'"), i.tm.name);
4163 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4164 || is_evex_encoding (&i.tm))
4166 if (flag_code == CODE_16BIT)
4168 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4173 if (i.tm.opcode_modifier.vex)
4174 build_vex_prefix (t);
4176 build_evex_prefix ();
4179 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4180 instructions may define INT_OPCODE as well, so avoid this corner
4181 case for those instructions that use MODRM. */
4182 if (i.tm.base_opcode == INT_OPCODE
4183 && !i.tm.opcode_modifier.modrm
4184 && i.op[0].imms->X_add_number == 3)
4186 i.tm.base_opcode = INT3_OPCODE;
4190 if ((i.tm.opcode_modifier.jump
4191 || i.tm.opcode_modifier.jumpbyte
4192 || i.tm.opcode_modifier.jumpdword)
4193 && i.op[0].disps->X_op == O_constant)
4195 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4196 the absolute address given by the constant. Since ix86 jumps and
4197 calls are pc relative, we need to generate a reloc. */
4198 i.op[0].disps->X_add_symbol = &abs_symbol;
4199 i.op[0].disps->X_op = O_symbol;
4202 if (i.tm.opcode_modifier.rex64)
4205 /* For 8 bit registers we need an empty rex prefix. Also if the
4206 instruction already has a prefix, we need to convert old
4207 registers to new ones. */
4209 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4210 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4211 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4212 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4213 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4214 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4219 i.rex |= REX_OPCODE;
4220 for (x = 0; x < 2; x++)
4222 /* Look for 8 bit operand that uses old registers. */
4223 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4224 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4226 /* In case it is "hi" register, give up. */
4227 if (i.op[x].regs->reg_num > 3)
4228 as_bad (_("can't encode register '%s%s' in an "
4229 "instruction requiring REX prefix."),
4230 register_prefix, i.op[x].regs->reg_name);
4232 /* Otherwise it is equivalent to the extended register.
4233 Since the encoding doesn't change this is merely
4234 cosmetic cleanup for debug output. */
4236 i.op[x].regs = i.op[x].regs + 8;
4241 if (i.rex == 0 && i.rex_encoding)
4243 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4244 that uses legacy register. If it is "hi" register, don't add
4245 the REX_OPCODE byte. */
4247 for (x = 0; x < 2; x++)
4248 if (i.types[x].bitfield.reg
4249 && i.types[x].bitfield.byte
4250 && (i.op[x].regs->reg_flags & RegRex64) == 0
4251 && i.op[x].regs->reg_num > 3)
4253 i.rex_encoding = FALSE;
4262 add_prefix (REX_OPCODE | i.rex);
4264 /* We are ready to output the insn. */
4269 parse_insn (char *line, char *mnemonic)
4272 char *token_start = l;
4275 const insn_template *t;
4281 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4286 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4288 as_bad (_("no such instruction: `%s'"), token_start);
4293 if (!is_space_char (*l)
4294 && *l != END_OF_INSN
4296 || (*l != PREFIX_SEPARATOR
4299 as_bad (_("invalid character %s in mnemonic"),
4300 output_invalid (*l));
4303 if (token_start == l)
4305 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4306 as_bad (_("expecting prefix; got nothing"));
4308 as_bad (_("expecting mnemonic; got nothing"));
4312 /* Look up instruction (or prefix) via hash table. */
4313 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4315 if (*l != END_OF_INSN
4316 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4317 && current_templates
4318 && current_templates->start->opcode_modifier.isprefix)
4320 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4322 as_bad ((flag_code != CODE_64BIT
4323 ? _("`%s' is only supported in 64-bit mode")
4324 : _("`%s' is not supported in 64-bit mode")),
4325 current_templates->start->name);
4328 /* If we are in 16-bit mode, do not allow addr16 or data16.
4329 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4330 if ((current_templates->start->opcode_modifier.size16
4331 || current_templates->start->opcode_modifier.size32)
4332 && flag_code != CODE_64BIT
4333 && (current_templates->start->opcode_modifier.size32
4334 ^ (flag_code == CODE_16BIT)))
4336 as_bad (_("redundant %s prefix"),
4337 current_templates->start->name);
4340 if (current_templates->start->opcode_length == 0)
4342 /* Handle pseudo prefixes. */
4343 switch (current_templates->start->base_opcode)
4347 i.disp_encoding = disp_encoding_8bit;
4351 i.disp_encoding = disp_encoding_32bit;
4355 i.dir_encoding = dir_encoding_load;
4359 i.dir_encoding = dir_encoding_store;
4363 i.vec_encoding = vex_encoding_vex2;
4367 i.vec_encoding = vex_encoding_vex3;
4371 i.vec_encoding = vex_encoding_evex;
4375 i.rex_encoding = TRUE;
4379 i.no_optimize = TRUE;
4387 /* Add prefix, checking for repeated prefixes. */
4388 switch (add_prefix (current_templates->start->base_opcode))
4393 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4394 i.notrack_prefix = current_templates->start->name;
4397 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4398 i.hle_prefix = current_templates->start->name;
4399 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4400 i.bnd_prefix = current_templates->start->name;
4402 i.rep_prefix = current_templates->start->name;
4408 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4415 if (!current_templates)
4417 /* Check if we should swap operand or force 32bit displacement in
4419 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4420 i.dir_encoding = dir_encoding_store;
4421 else if (mnem_p - 3 == dot_p
4424 i.disp_encoding = disp_encoding_8bit;
4425 else if (mnem_p - 4 == dot_p
4429 i.disp_encoding = disp_encoding_32bit;
4434 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4437 if (!current_templates)
4440 /* See if we can get a match by trimming off a suffix. */
4443 case WORD_MNEM_SUFFIX:
4444 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4445 i.suffix = SHORT_MNEM_SUFFIX;
4448 case BYTE_MNEM_SUFFIX:
4449 case QWORD_MNEM_SUFFIX:
4450 i.suffix = mnem_p[-1];
4452 current_templates = (const templates *) hash_find (op_hash,
4455 case SHORT_MNEM_SUFFIX:
4456 case LONG_MNEM_SUFFIX:
4459 i.suffix = mnem_p[-1];
4461 current_templates = (const templates *) hash_find (op_hash,
4470 if (intel_float_operand (mnemonic) == 1)
4471 i.suffix = SHORT_MNEM_SUFFIX;
4473 i.suffix = LONG_MNEM_SUFFIX;
4475 current_templates = (const templates *) hash_find (op_hash,
4480 if (!current_templates)
4482 as_bad (_("no such instruction: `%s'"), token_start);
4487 if (current_templates->start->opcode_modifier.jump
4488 || current_templates->start->opcode_modifier.jumpbyte)
4490 /* Check for a branch hint. We allow ",pt" and ",pn" for
4491 predict taken and predict not taken respectively.
4492 I'm not sure that branch hints actually do anything on loop
4493 and jcxz insns (JumpByte) for current Pentium4 chips. They
4494 may work in the future and it doesn't hurt to accept them
4496 if (l[0] == ',' && l[1] == 'p')
4500 if (!add_prefix (DS_PREFIX_OPCODE))
4504 else if (l[2] == 'n')
4506 if (!add_prefix (CS_PREFIX_OPCODE))
4512 /* Any other comma loses. */
4515 as_bad (_("invalid character %s in mnemonic"),
4516 output_invalid (*l));
4520 /* Check if instruction is supported on specified architecture. */
4522 for (t = current_templates->start; t < current_templates->end; ++t)
4524 supported |= cpu_flags_match (t);
4525 if (supported == CPU_FLAGS_PERFECT_MATCH)
4527 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4528 as_warn (_("use .code16 to ensure correct addressing mode"));
4534 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4535 as_bad (flag_code == CODE_64BIT
4536 ? _("`%s' is not supported in 64-bit mode")
4537 : _("`%s' is only supported in 64-bit mode"),
4538 current_templates->start->name);
4540 as_bad (_("`%s' is not supported on `%s%s'"),
4541 current_templates->start->name,
4542 cpu_arch_name ? cpu_arch_name : default_arch,
4543 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4549 parse_operands (char *l, const char *mnemonic)
4553 /* 1 if operand is pending after ','. */
4554 unsigned int expecting_operand = 0;
4556 /* Non-zero if operand parens not balanced. */
4557 unsigned int paren_not_balanced;
4559 while (*l != END_OF_INSN)
4561 /* Skip optional white space before operand. */
4562 if (is_space_char (*l))
4564 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4566 as_bad (_("invalid character %s before operand %d"),
4567 output_invalid (*l),
4571 token_start = l; /* After white space. */
4572 paren_not_balanced = 0;
4573 while (paren_not_balanced || *l != ',')
4575 if (*l == END_OF_INSN)
4577 if (paren_not_balanced)
4580 as_bad (_("unbalanced parenthesis in operand %d."),
4583 as_bad (_("unbalanced brackets in operand %d."),
4588 break; /* we are done */
4590 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4592 as_bad (_("invalid character %s in operand %d"),
4593 output_invalid (*l),
4600 ++paren_not_balanced;
4602 --paren_not_balanced;
4607 ++paren_not_balanced;
4609 --paren_not_balanced;
4613 if (l != token_start)
4614 { /* Yes, we've read in another operand. */
4615 unsigned int operand_ok;
4616 this_operand = i.operands++;
4617 if (i.operands > MAX_OPERANDS)
4619 as_bad (_("spurious operands; (%d operands/instruction max)"),
4623 i.types[this_operand].bitfield.unspecified = 1;
4624 /* Now parse operand adding info to 'i' as we go along. */
4625 END_STRING_AND_SAVE (l);
4629 i386_intel_operand (token_start,
4630 intel_float_operand (mnemonic));
4632 operand_ok = i386_att_operand (token_start);
4634 RESTORE_END_STRING (l);
4640 if (expecting_operand)
4642 expecting_operand_after_comma:
4643 as_bad (_("expecting operand after ','; got nothing"));
4648 as_bad (_("expecting operand before ','; got nothing"));
4653 /* Now *l must be either ',' or END_OF_INSN. */
4656 if (*++l == END_OF_INSN)
4658 /* Just skip it, if it's \n complain. */
4659 goto expecting_operand_after_comma;
4661 expecting_operand = 1;
4668 swap_2_operands (int xchg1, int xchg2)
4670 union i386_op temp_op;
4671 i386_operand_type temp_type;
4672 enum bfd_reloc_code_real temp_reloc;
4674 temp_type = i.types[xchg2];
4675 i.types[xchg2] = i.types[xchg1];
4676 i.types[xchg1] = temp_type;
4677 temp_op = i.op[xchg2];
4678 i.op[xchg2] = i.op[xchg1];
4679 i.op[xchg1] = temp_op;
4680 temp_reloc = i.reloc[xchg2];
4681 i.reloc[xchg2] = i.reloc[xchg1];
4682 i.reloc[xchg1] = temp_reloc;
4686 if (i.mask->operand == xchg1)
4687 i.mask->operand = xchg2;
4688 else if (i.mask->operand == xchg2)
4689 i.mask->operand = xchg1;
4693 if (i.broadcast->operand == xchg1)
4694 i.broadcast->operand = xchg2;
4695 else if (i.broadcast->operand == xchg2)
4696 i.broadcast->operand = xchg1;
4700 if (i.rounding->operand == xchg1)
4701 i.rounding->operand = xchg2;
4702 else if (i.rounding->operand == xchg2)
4703 i.rounding->operand = xchg1;
4708 swap_operands (void)
4714 swap_2_operands (1, i.operands - 2);
4718 swap_2_operands (0, i.operands - 1);
4724 if (i.mem_operands == 2)
4726 const seg_entry *temp_seg;
4727 temp_seg = i.seg[0];
4728 i.seg[0] = i.seg[1];
4729 i.seg[1] = temp_seg;
4733 /* Try to ensure constant immediates are represented in the smallest
4738 char guess_suffix = 0;
4742 guess_suffix = i.suffix;
4743 else if (i.reg_operands)
4745 /* Figure out a suffix from the last register operand specified.
4746 We can't do this properly yet, ie. excluding InOutPortReg,
4747 but the following works for instructions with immediates.
4748 In any case, we can't set i.suffix yet. */
4749 for (op = i.operands; --op >= 0;)
4750 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4752 guess_suffix = BYTE_MNEM_SUFFIX;
4755 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4757 guess_suffix = WORD_MNEM_SUFFIX;
4760 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4762 guess_suffix = LONG_MNEM_SUFFIX;
4765 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4767 guess_suffix = QWORD_MNEM_SUFFIX;
4771 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4772 guess_suffix = WORD_MNEM_SUFFIX;
4774 for (op = i.operands; --op >= 0;)
4775 if (operand_type_check (i.types[op], imm))
4777 switch (i.op[op].imms->X_op)
4780 /* If a suffix is given, this operand may be shortened. */
4781 switch (guess_suffix)
4783 case LONG_MNEM_SUFFIX:
4784 i.types[op].bitfield.imm32 = 1;
4785 i.types[op].bitfield.imm64 = 1;
4787 case WORD_MNEM_SUFFIX:
4788 i.types[op].bitfield.imm16 = 1;
4789 i.types[op].bitfield.imm32 = 1;
4790 i.types[op].bitfield.imm32s = 1;
4791 i.types[op].bitfield.imm64 = 1;
4793 case BYTE_MNEM_SUFFIX:
4794 i.types[op].bitfield.imm8 = 1;
4795 i.types[op].bitfield.imm8s = 1;
4796 i.types[op].bitfield.imm16 = 1;
4797 i.types[op].bitfield.imm32 = 1;
4798 i.types[op].bitfield.imm32s = 1;
4799 i.types[op].bitfield.imm64 = 1;
4803 /* If this operand is at most 16 bits, convert it
4804 to a signed 16 bit number before trying to see
4805 whether it will fit in an even smaller size.
4806 This allows a 16-bit operand such as $0xffe0 to
4807 be recognised as within Imm8S range. */
4808 if ((i.types[op].bitfield.imm16)
4809 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4811 i.op[op].imms->X_add_number =
4812 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4815 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4816 if ((i.types[op].bitfield.imm32)
4817 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4820 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4821 ^ ((offsetT) 1 << 31))
4822 - ((offsetT) 1 << 31));
4826 = operand_type_or (i.types[op],
4827 smallest_imm_type (i.op[op].imms->X_add_number));
4829 /* We must avoid matching of Imm32 templates when 64bit
4830 only immediate is available. */
4831 if (guess_suffix == QWORD_MNEM_SUFFIX)
4832 i.types[op].bitfield.imm32 = 0;
4839 /* Symbols and expressions. */
4841 /* Convert symbolic operand to proper sizes for matching, but don't
4842 prevent matching a set of insns that only supports sizes other
4843 than those matching the insn suffix. */
4845 i386_operand_type mask, allowed;
4846 const insn_template *t;
4848 operand_type_set (&mask, 0);
4849 operand_type_set (&allowed, 0);
4851 for (t = current_templates->start;
4852 t < current_templates->end;
4854 allowed = operand_type_or (allowed,
4855 t->operand_types[op]);
4856 switch (guess_suffix)
4858 case QWORD_MNEM_SUFFIX:
4859 mask.bitfield.imm64 = 1;
4860 mask.bitfield.imm32s = 1;
4862 case LONG_MNEM_SUFFIX:
4863 mask.bitfield.imm32 = 1;
4865 case WORD_MNEM_SUFFIX:
4866 mask.bitfield.imm16 = 1;
4868 case BYTE_MNEM_SUFFIX:
4869 mask.bitfield.imm8 = 1;
4874 allowed = operand_type_and (mask, allowed);
4875 if (!operand_type_all_zero (&allowed))
4876 i.types[op] = operand_type_and (i.types[op], mask);
4883 /* Try to use the smallest displacement type too. */
4885 optimize_disp (void)
4889 for (op = i.operands; --op >= 0;)
4890 if (operand_type_check (i.types[op], disp))
4892 if (i.op[op].disps->X_op == O_constant)
4894 offsetT op_disp = i.op[op].disps->X_add_number;
4896 if (i.types[op].bitfield.disp16
4897 && (op_disp & ~(offsetT) 0xffff) == 0)
4899 /* If this operand is at most 16 bits, convert
4900 to a signed 16 bit number and don't use 64bit
4902 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4903 i.types[op].bitfield.disp64 = 0;
4906 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4907 if (i.types[op].bitfield.disp32
4908 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4910 /* If this operand is at most 32 bits, convert
4911 to a signed 32 bit number and don't use 64bit
4913 op_disp &= (((offsetT) 2 << 31) - 1);
4914 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4915 i.types[op].bitfield.disp64 = 0;
4918 if (!op_disp && i.types[op].bitfield.baseindex)
4920 i.types[op].bitfield.disp8 = 0;
4921 i.types[op].bitfield.disp16 = 0;
4922 i.types[op].bitfield.disp32 = 0;
4923 i.types[op].bitfield.disp32s = 0;
4924 i.types[op].bitfield.disp64 = 0;
4928 else if (flag_code == CODE_64BIT)
4930 if (fits_in_signed_long (op_disp))
4932 i.types[op].bitfield.disp64 = 0;
4933 i.types[op].bitfield.disp32s = 1;
4935 if (i.prefix[ADDR_PREFIX]
4936 && fits_in_unsigned_long (op_disp))
4937 i.types[op].bitfield.disp32 = 1;
4939 if ((i.types[op].bitfield.disp32
4940 || i.types[op].bitfield.disp32s
4941 || i.types[op].bitfield.disp16)
4942 && fits_in_disp8 (op_disp))
4943 i.types[op].bitfield.disp8 = 1;
4945 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4946 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4948 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4949 i.op[op].disps, 0, i.reloc[op]);
4950 i.types[op].bitfield.disp8 = 0;
4951 i.types[op].bitfield.disp16 = 0;
4952 i.types[op].bitfield.disp32 = 0;
4953 i.types[op].bitfield.disp32s = 0;
4954 i.types[op].bitfield.disp64 = 0;
4957 /* We only support 64bit displacement on constants. */
4958 i.types[op].bitfield.disp64 = 0;
4962 /* Check if operands are valid for the instruction. */
4965 check_VecOperands (const insn_template *t)
4969 /* Without VSIB byte, we can't have a vector register for index. */
4970 if (!t->opcode_modifier.vecsib
4972 && (i.index_reg->reg_type.bitfield.xmmword
4973 || i.index_reg->reg_type.bitfield.ymmword
4974 || i.index_reg->reg_type.bitfield.zmmword))
4976 i.error = unsupported_vector_index_register;
4980 /* Check if default mask is allowed. */
4981 if (t->opcode_modifier.nodefmask
4982 && (!i.mask || i.mask->mask->reg_num == 0))
4984 i.error = no_default_mask;
4988 /* For VSIB byte, we need a vector register for index, and all vector
4989 registers must be distinct. */
4990 if (t->opcode_modifier.vecsib)
4993 || !((t->opcode_modifier.vecsib == VecSIB128
4994 && i.index_reg->reg_type.bitfield.xmmword)
4995 || (t->opcode_modifier.vecsib == VecSIB256
4996 && i.index_reg->reg_type.bitfield.ymmword)
4997 || (t->opcode_modifier.vecsib == VecSIB512
4998 && i.index_reg->reg_type.bitfield.zmmword)))
5000 i.error = invalid_vsib_address;
5004 gas_assert (i.reg_operands == 2 || i.mask);
5005 if (i.reg_operands == 2 && !i.mask)
5007 gas_assert (i.types[0].bitfield.regsimd);
5008 gas_assert (i.types[0].bitfield.xmmword
5009 || i.types[0].bitfield.ymmword);
5010 gas_assert (i.types[2].bitfield.regsimd);
5011 gas_assert (i.types[2].bitfield.xmmword
5012 || i.types[2].bitfield.ymmword);
5013 if (operand_check == check_none)
5015 if (register_number (i.op[0].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[2].regs)
5018 != register_number (i.index_reg)
5019 && register_number (i.op[0].regs)
5020 != register_number (i.op[2].regs))
5022 if (operand_check == check_error)
5024 i.error = invalid_vector_register_set;
5027 as_warn (_("mask, index, and destination registers should be distinct"));
5029 else if (i.reg_operands == 1 && i.mask)
5031 if (i.types[1].bitfield.regsimd
5032 && (i.types[1].bitfield.xmmword
5033 || i.types[1].bitfield.ymmword
5034 || i.types[1].bitfield.zmmword)
5035 && (register_number (i.op[1].regs)
5036 == register_number (i.index_reg)))
5038 if (operand_check == check_error)
5040 i.error = invalid_vector_register_set;
5043 if (operand_check != check_none)
5044 as_warn (_("index and destination registers should be distinct"));
5049 /* Check if broadcast is supported by the instruction and is applied
5050 to the memory operand. */
5053 i386_operand_type type, overlap;
5055 /* Check if specified broadcast is supported in this instruction,
5056 and it's applied to memory operand of DWORD or QWORD type. */
5057 op = i.broadcast->operand;
5058 if (!t->opcode_modifier.broadcast
5059 || !i.types[op].bitfield.mem
5060 || (!i.types[op].bitfield.unspecified
5061 && (t->operand_types[op].bitfield.dword
5062 ? !i.types[op].bitfield.dword
5063 : !i.types[op].bitfield.qword)))
5066 i.error = unsupported_broadcast;
5070 operand_type_set (&type, 0);
5071 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5074 type.bitfield.qword = 1;
5077 type.bitfield.xmmword = 1;
5080 type.bitfield.ymmword = 1;
5083 type.bitfield.zmmword = 1;
5089 overlap = operand_type_and (type, t->operand_types[op]);
5090 if (operand_type_all_zero (&overlap))
5093 if (t->opcode_modifier.checkregsize)
5097 for (j = 0; j < i.operands; ++j)
5100 && !operand_type_register_match(i.types[j],
5101 t->operand_types[j],
5103 t->operand_types[op]))
5108 /* If broadcast is supported in this instruction, we need to check if
5109 operand of one-element size isn't specified without broadcast. */
5110 else if (t->opcode_modifier.broadcast && i.mem_operands)
5112 /* Find memory operand. */
5113 for (op = 0; op < i.operands; op++)
5114 if (operand_type_check (i.types[op], anymem))
5116 gas_assert (op < i.operands);
5117 /* Check size of the memory operand. */
5118 if (t->operand_types[op].bitfield.dword
5119 ? i.types[op].bitfield.dword
5120 : i.types[op].bitfield.qword)
5122 i.error = broadcast_needed;
5127 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5129 /* Check if requested masking is supported. */
5131 && (!t->opcode_modifier.masking
5133 && t->opcode_modifier.masking == MERGING_MASKING)))
5135 i.error = unsupported_masking;
5139 /* Check if masking is applied to dest operand. */
5140 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5142 i.error = mask_not_on_destination;
5149 if ((i.rounding->type != saeonly
5150 && !t->opcode_modifier.staticrounding)
5151 || (i.rounding->type == saeonly
5152 && (t->opcode_modifier.staticrounding
5153 || !t->opcode_modifier.sae)))
5155 i.error = unsupported_rc_sae;
5158 /* If the instruction has several immediate operands and one of
5159 them is rounding, the rounding operand should be the last
5160 immediate operand. */
5161 if (i.imm_operands > 1
5162 && i.rounding->operand != (int) (i.imm_operands - 1))
5164 i.error = rc_sae_operand_not_last_imm;
5169 /* Check vector Disp8 operand. */
5170 if (t->opcode_modifier.disp8memshift
5171 && i.disp_encoding != disp_encoding_32bit)
5174 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5176 i.memshift = t->opcode_modifier.disp8memshift;
5178 for (op = 0; op < i.operands; op++)
5179 if (operand_type_check (i.types[op], disp)
5180 && i.op[op].disps->X_op == O_constant)
5182 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5184 i.types[op].bitfield.disp8 = 1;
5187 i.types[op].bitfield.disp8 = 0;
5196 /* Check if operands are valid for the instruction. Update VEX
5200 VEX_check_operands (const insn_template *t)
5202 if (i.vec_encoding == vex_encoding_evex)
5204 /* This instruction must be encoded with EVEX prefix. */
5205 if (!is_evex_encoding (t))
5207 i.error = unsupported;
5213 if (!t->opcode_modifier.vex)
5215 /* This instruction template doesn't have VEX prefix. */
5216 if (i.vec_encoding != vex_encoding_default)
5218 i.error = unsupported;
5224 /* Only check VEX_Imm4, which must be the first operand. */
5225 if (t->operand_types[0].bitfield.vec_imm4)
5227 if (i.op[0].imms->X_op != O_constant
5228 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5234 /* Turn off Imm8 so that update_imm won't complain. */
5235 i.types[0] = vec_imm4;
5241 static const insn_template *
5242 match_template (char mnem_suffix)
5244 /* Points to template once we've found it. */
5245 const insn_template *t;
5246 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5247 i386_operand_type overlap4;
5248 unsigned int found_reverse_match;
5249 i386_opcode_modifier suffix_check, mnemsuf_check;
5250 i386_operand_type operand_types [MAX_OPERANDS];
5251 int addr_prefix_disp;
5253 unsigned int found_cpu_match;
5254 unsigned int check_register;
5255 enum i386_error specific_error = 0;
5257 #if MAX_OPERANDS != 5
5258 # error "MAX_OPERANDS must be 5."
5261 found_reverse_match = 0;
5262 addr_prefix_disp = -1;
5264 memset (&suffix_check, 0, sizeof (suffix_check));
5265 if (i.suffix == BYTE_MNEM_SUFFIX)
5266 suffix_check.no_bsuf = 1;
5267 else if (i.suffix == WORD_MNEM_SUFFIX)
5268 suffix_check.no_wsuf = 1;
5269 else if (i.suffix == SHORT_MNEM_SUFFIX)
5270 suffix_check.no_ssuf = 1;
5271 else if (i.suffix == LONG_MNEM_SUFFIX)
5272 suffix_check.no_lsuf = 1;
5273 else if (i.suffix == QWORD_MNEM_SUFFIX)
5274 suffix_check.no_qsuf = 1;
5275 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5276 suffix_check.no_ldsuf = 1;
5278 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5281 switch (mnem_suffix)
5283 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5284 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5285 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5286 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5287 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5291 /* Must have right number of operands. */
5292 i.error = number_of_operands_mismatch;
5294 for (t = current_templates->start; t < current_templates->end; t++)
5296 addr_prefix_disp = -1;
5298 if (i.operands != t->operands)
5301 /* Check processor support. */
5302 i.error = unsupported;
5303 found_cpu_match = (cpu_flags_match (t)
5304 == CPU_FLAGS_PERFECT_MATCH);
5305 if (!found_cpu_match)
5308 /* Check AT&T mnemonic. */
5309 i.error = unsupported_with_intel_mnemonic;
5310 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5313 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5314 i.error = unsupported_syntax;
5315 if ((intel_syntax && t->opcode_modifier.attsyntax)
5316 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5317 || (intel64 && t->opcode_modifier.amd64)
5318 || (!intel64 && t->opcode_modifier.intel64))
5321 /* Check the suffix, except for some instructions in intel mode. */
5322 i.error = invalid_instruction_suffix;
5323 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5324 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5325 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5326 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5327 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5328 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5329 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5331 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5332 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5333 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5334 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5335 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5336 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5337 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5340 if (!operand_size_match (t))
5343 for (j = 0; j < MAX_OPERANDS; j++)
5344 operand_types[j] = t->operand_types[j];
5346 /* In general, don't allow 64-bit operands in 32-bit mode. */
5347 if (i.suffix == QWORD_MNEM_SUFFIX
5348 && flag_code != CODE_64BIT
5350 ? (!t->opcode_modifier.ignoresize
5351 && !intel_float_operand (t->name))
5352 : intel_float_operand (t->name) != 2)
5353 && ((!operand_types[0].bitfield.regmmx
5354 && !operand_types[0].bitfield.regsimd)
5355 || (!operand_types[t->operands > 1].bitfield.regmmx
5356 && !operand_types[t->operands > 1].bitfield.regsimd))
5357 && (t->base_opcode != 0x0fc7
5358 || t->extension_opcode != 1 /* cmpxchg8b */))
5361 /* In general, don't allow 32-bit operands on pre-386. */
5362 else if (i.suffix == LONG_MNEM_SUFFIX
5363 && !cpu_arch_flags.bitfield.cpui386
5365 ? (!t->opcode_modifier.ignoresize
5366 && !intel_float_operand (t->name))
5367 : intel_float_operand (t->name) != 2)
5368 && ((!operand_types[0].bitfield.regmmx
5369 && !operand_types[0].bitfield.regsimd)
5370 || (!operand_types[t->operands > 1].bitfield.regmmx
5371 && !operand_types[t->operands > 1].bitfield.regsimd)))
5374 /* Do not verify operands when there are none. */
5378 /* We've found a match; break out of loop. */
5382 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5383 into Disp32/Disp16/Disp32 operand. */
5384 if (i.prefix[ADDR_PREFIX] != 0)
5386 /* There should be only one Disp operand. */
5390 for (j = 0; j < MAX_OPERANDS; j++)
5392 if (operand_types[j].bitfield.disp16)
5394 addr_prefix_disp = j;
5395 operand_types[j].bitfield.disp32 = 1;
5396 operand_types[j].bitfield.disp16 = 0;
5402 for (j = 0; j < MAX_OPERANDS; j++)
5404 if (operand_types[j].bitfield.disp32)
5406 addr_prefix_disp = j;
5407 operand_types[j].bitfield.disp32 = 0;
5408 operand_types[j].bitfield.disp16 = 1;
5414 for (j = 0; j < MAX_OPERANDS; j++)
5416 if (operand_types[j].bitfield.disp64)
5418 addr_prefix_disp = j;
5419 operand_types[j].bitfield.disp64 = 0;
5420 operand_types[j].bitfield.disp32 = 1;
5428 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5429 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5432 /* We check register size if needed. */
5433 check_register = t->opcode_modifier.checkregsize;
5434 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5435 switch (t->operands)
5438 if (!operand_type_match (overlap0, i.types[0]))
5442 /* xchg %eax, %eax is a special case. It is an alias for nop
5443 only in 32bit mode and we can use opcode 0x90. In 64bit
5444 mode, we can't use 0x90 for xchg %eax, %eax since it should
5445 zero-extend %eax to %rax. */
5446 if (flag_code == CODE_64BIT
5447 && t->base_opcode == 0x90
5448 && operand_type_equal (&i.types [0], &acc32)
5449 && operand_type_equal (&i.types [1], &acc32))
5451 /* xrelease mov %eax, <disp> is another special case. It must not
5452 match the accumulator-only encoding of mov. */
5453 if (flag_code != CODE_64BIT
5455 && t->base_opcode == 0xa0
5456 && i.types[0].bitfield.acc
5457 && operand_type_check (i.types[1], anymem))
5459 /* If we want store form, we reverse direction of operands. */
5460 if (i.dir_encoding == dir_encoding_store
5461 && t->opcode_modifier.d)
5466 /* If we want store form, we skip the current load. */
5467 if (i.dir_encoding == dir_encoding_store
5468 && i.mem_operands == 0
5469 && t->opcode_modifier.load)
5474 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5475 if (!operand_type_match (overlap0, i.types[0])
5476 || !operand_type_match (overlap1, i.types[1])
5478 && !operand_type_register_match (i.types[0],
5483 /* Check if other direction is valid ... */
5484 if (!t->opcode_modifier.d)
5488 /* Try reversing direction of operands. */
5489 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5490 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5491 if (!operand_type_match (overlap0, i.types[0])
5492 || !operand_type_match (overlap1, i.types[1])
5494 && !operand_type_register_match (i.types[0],
5499 /* Does not match either direction. */
5502 /* found_reverse_match holds which of D or FloatR
5504 if (!t->opcode_modifier.d)
5505 found_reverse_match = 0;
5506 else if (operand_types[0].bitfield.tbyte)
5507 found_reverse_match = Opcode_FloatD;
5509 found_reverse_match = Opcode_D;
5510 if (t->opcode_modifier.floatr)
5511 found_reverse_match |= Opcode_FloatR;
5515 /* Found a forward 2 operand match here. */
5516 switch (t->operands)
5519 overlap4 = operand_type_and (i.types[4],
5523 overlap3 = operand_type_and (i.types[3],
5527 overlap2 = operand_type_and (i.types[2],
5532 switch (t->operands)
5535 if (!operand_type_match (overlap4, i.types[4])
5536 || !operand_type_register_match (i.types[3],
5543 if (!operand_type_match (overlap3, i.types[3])
5545 && (!operand_type_register_match (i.types[1],
5549 || !operand_type_register_match (i.types[2],
5552 operand_types[3]))))
5556 /* Here we make use of the fact that there are no
5557 reverse match 3 operand instructions. */
5558 if (!operand_type_match (overlap2, i.types[2])
5560 && (!operand_type_register_match (i.types[0],
5564 || !operand_type_register_match (i.types[1],
5567 operand_types[2]))))
5572 /* Found either forward/reverse 2, 3 or 4 operand match here:
5573 slip through to break. */
5575 if (!found_cpu_match)
5577 found_reverse_match = 0;
5581 /* Check if vector and VEX operands are valid. */
5582 if (check_VecOperands (t) || VEX_check_operands (t))
5584 specific_error = i.error;
5588 /* We've found a match; break out of loop. */
5592 if (t == current_templates->end)
5594 /* We found no match. */
5595 const char *err_msg;
5596 switch (specific_error ? specific_error : i.error)
5600 case operand_size_mismatch:
5601 err_msg = _("operand size mismatch");
5603 case operand_type_mismatch:
5604 err_msg = _("operand type mismatch");
5606 case register_type_mismatch:
5607 err_msg = _("register type mismatch");
5609 case number_of_operands_mismatch:
5610 err_msg = _("number of operands mismatch");
5612 case invalid_instruction_suffix:
5613 err_msg = _("invalid instruction suffix");
5616 err_msg = _("constant doesn't fit in 4 bits");
5618 case unsupported_with_intel_mnemonic:
5619 err_msg = _("unsupported with Intel mnemonic");
5621 case unsupported_syntax:
5622 err_msg = _("unsupported syntax");
5625 as_bad (_("unsupported instruction `%s'"),
5626 current_templates->start->name);
5628 case invalid_vsib_address:
5629 err_msg = _("invalid VSIB address");
5631 case invalid_vector_register_set:
5632 err_msg = _("mask, index, and destination registers must be distinct");
5634 case unsupported_vector_index_register:
5635 err_msg = _("unsupported vector index register");
5637 case unsupported_broadcast:
5638 err_msg = _("unsupported broadcast");
5640 case broadcast_not_on_src_operand:
5641 err_msg = _("broadcast not on source memory operand");
5643 case broadcast_needed:
5644 err_msg = _("broadcast is needed for operand of such type");
5646 case unsupported_masking:
5647 err_msg = _("unsupported masking");
5649 case mask_not_on_destination:
5650 err_msg = _("mask not on destination operand");
5652 case no_default_mask:
5653 err_msg = _("default mask isn't allowed");
5655 case unsupported_rc_sae:
5656 err_msg = _("unsupported static rounding/sae");
5658 case rc_sae_operand_not_last_imm:
5660 err_msg = _("RC/SAE operand must precede immediate operands");
5662 err_msg = _("RC/SAE operand must follow immediate operands");
5664 case invalid_register_operand:
5665 err_msg = _("invalid register operand");
5668 as_bad (_("%s for `%s'"), err_msg,
5669 current_templates->start->name);
5673 if (!quiet_warnings)
5676 && (i.types[0].bitfield.jumpabsolute
5677 != operand_types[0].bitfield.jumpabsolute))
5679 as_warn (_("indirect %s without `*'"), t->name);
5682 if (t->opcode_modifier.isprefix
5683 && t->opcode_modifier.ignoresize)
5685 /* Warn them that a data or address size prefix doesn't
5686 affect assembly of the next line of code. */
5687 as_warn (_("stand-alone `%s' prefix"), t->name);
5691 /* Copy the template we found. */
5694 if (addr_prefix_disp != -1)
5695 i.tm.operand_types[addr_prefix_disp]
5696 = operand_types[addr_prefix_disp];
5698 if (found_reverse_match)
5700 /* If we found a reverse match we must alter the opcode
5701 direction bit. found_reverse_match holds bits to change
5702 (different for int & float insns). */
5704 i.tm.base_opcode ^= found_reverse_match;
5706 i.tm.operand_types[0] = operand_types[1];
5707 i.tm.operand_types[1] = operand_types[0];
5716 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5717 if (i.tm.operand_types[mem_op].bitfield.esseg)
5719 if (i.seg[0] != NULL && i.seg[0] != &es)
5721 as_bad (_("`%s' operand %d must use `%ses' segment"),
5727 /* There's only ever one segment override allowed per instruction.
5728 This instruction possibly has a legal segment override on the
5729 second operand, so copy the segment to where non-string
5730 instructions store it, allowing common code. */
5731 i.seg[0] = i.seg[1];
5733 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5735 if (i.seg[1] != NULL && i.seg[1] != &es)
5737 as_bad (_("`%s' operand %d must use `%ses' segment"),
5748 process_suffix (void)
5750 /* If matched instruction specifies an explicit instruction mnemonic
5752 if (i.tm.opcode_modifier.size16)
5753 i.suffix = WORD_MNEM_SUFFIX;
5754 else if (i.tm.opcode_modifier.size32)
5755 i.suffix = LONG_MNEM_SUFFIX;
5756 else if (i.tm.opcode_modifier.size64)
5757 i.suffix = QWORD_MNEM_SUFFIX;
5758 else if (i.reg_operands)
5760 /* If there's no instruction mnemonic suffix we try to invent one
5761 based on register operands. */
5764 /* We take i.suffix from the last register operand specified,
5765 Destination register type is more significant than source
5766 register type. crc32 in SSE4.2 prefers source register
5768 if (i.tm.base_opcode == 0xf20f38f1)
5770 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5771 i.suffix = WORD_MNEM_SUFFIX;
5772 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5773 i.suffix = LONG_MNEM_SUFFIX;
5774 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5775 i.suffix = QWORD_MNEM_SUFFIX;
5777 else if (i.tm.base_opcode == 0xf20f38f0)
5779 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5780 i.suffix = BYTE_MNEM_SUFFIX;
5787 if (i.tm.base_opcode == 0xf20f38f1
5788 || i.tm.base_opcode == 0xf20f38f0)
5790 /* We have to know the operand size for crc32. */
5791 as_bad (_("ambiguous memory operand size for `%s`"),
5796 for (op = i.operands; --op >= 0;)
5797 if (!i.tm.operand_types[op].bitfield.inoutportreg
5798 && !i.tm.operand_types[op].bitfield.shiftcount)
5800 if (!i.types[op].bitfield.reg)
5802 if (i.types[op].bitfield.byte)
5803 i.suffix = BYTE_MNEM_SUFFIX;
5804 else if (i.types[op].bitfield.word)
5805 i.suffix = WORD_MNEM_SUFFIX;
5806 else if (i.types[op].bitfield.dword)
5807 i.suffix = LONG_MNEM_SUFFIX;
5808 else if (i.types[op].bitfield.qword)
5809 i.suffix = QWORD_MNEM_SUFFIX;
5816 else if (i.suffix == BYTE_MNEM_SUFFIX)
5819 && i.tm.opcode_modifier.ignoresize
5820 && i.tm.opcode_modifier.no_bsuf)
5822 else if (!check_byte_reg ())
5825 else if (i.suffix == LONG_MNEM_SUFFIX)
5828 && i.tm.opcode_modifier.ignoresize
5829 && i.tm.opcode_modifier.no_lsuf
5830 && !i.tm.opcode_modifier.todword
5831 && !i.tm.opcode_modifier.toqword)
5833 else if (!check_long_reg ())
5836 else if (i.suffix == QWORD_MNEM_SUFFIX)
5839 && i.tm.opcode_modifier.ignoresize
5840 && i.tm.opcode_modifier.no_qsuf
5841 && !i.tm.opcode_modifier.todword
5842 && !i.tm.opcode_modifier.toqword)
5844 else if (!check_qword_reg ())
5847 else if (i.suffix == WORD_MNEM_SUFFIX)
5850 && i.tm.opcode_modifier.ignoresize
5851 && i.tm.opcode_modifier.no_wsuf)
5853 else if (!check_word_reg ())
5856 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5857 /* Do nothing if the instruction is going to ignore the prefix. */
5862 else if (i.tm.opcode_modifier.defaultsize
5864 /* exclude fldenv/frstor/fsave/fstenv */
5865 && i.tm.opcode_modifier.no_ssuf)
5867 i.suffix = stackop_size;
5869 else if (intel_syntax
5871 && (i.tm.operand_types[0].bitfield.jumpabsolute
5872 || i.tm.opcode_modifier.jumpbyte
5873 || i.tm.opcode_modifier.jumpintersegment
5874 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5875 && i.tm.extension_opcode <= 3)))
5880 if (!i.tm.opcode_modifier.no_qsuf)
5882 i.suffix = QWORD_MNEM_SUFFIX;
5887 if (!i.tm.opcode_modifier.no_lsuf)
5888 i.suffix = LONG_MNEM_SUFFIX;
5891 if (!i.tm.opcode_modifier.no_wsuf)
5892 i.suffix = WORD_MNEM_SUFFIX;
5901 if (i.tm.opcode_modifier.w)
5903 as_bad (_("no instruction mnemonic suffix given and "
5904 "no register operands; can't size instruction"));
5910 unsigned int suffixes;
5912 suffixes = !i.tm.opcode_modifier.no_bsuf;
5913 if (!i.tm.opcode_modifier.no_wsuf)
5915 if (!i.tm.opcode_modifier.no_lsuf)
5917 if (!i.tm.opcode_modifier.no_ldsuf)
5919 if (!i.tm.opcode_modifier.no_ssuf)
5921 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5924 /* There are more than suffix matches. */
5925 if (i.tm.opcode_modifier.w
5926 || ((suffixes & (suffixes - 1))
5927 && !i.tm.opcode_modifier.defaultsize
5928 && !i.tm.opcode_modifier.ignoresize))
5930 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5936 /* Change the opcode based on the operand size given by i.suffix. */
5939 /* Size floating point instruction. */
5940 case LONG_MNEM_SUFFIX:
5941 if (i.tm.opcode_modifier.floatmf)
5943 i.tm.base_opcode ^= 4;
5947 case WORD_MNEM_SUFFIX:
5948 case QWORD_MNEM_SUFFIX:
5949 /* It's not a byte, select word/dword operation. */
5950 if (i.tm.opcode_modifier.w)
5952 if (i.tm.opcode_modifier.shortform)
5953 i.tm.base_opcode |= 8;
5955 i.tm.base_opcode |= 1;
5958 case SHORT_MNEM_SUFFIX:
5959 /* Now select between word & dword operations via the operand
5960 size prefix, except for instructions that will ignore this
5962 if (i.tm.opcode_modifier.addrprefixop0)
5964 /* The address size override prefix changes the size of the
5966 if ((flag_code == CODE_32BIT
5967 && i.op->regs[0].reg_type.bitfield.word)
5968 || (flag_code != CODE_32BIT
5969 && i.op->regs[0].reg_type.bitfield.dword))
5970 if (!add_prefix (ADDR_PREFIX_OPCODE))
5973 else if (i.suffix != QWORD_MNEM_SUFFIX
5974 && !i.tm.opcode_modifier.ignoresize
5975 && !i.tm.opcode_modifier.floatmf
5976 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5977 || (flag_code == CODE_64BIT
5978 && i.tm.opcode_modifier.jumpbyte)))
5980 unsigned int prefix = DATA_PREFIX_OPCODE;
5982 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5983 prefix = ADDR_PREFIX_OPCODE;
5985 if (!add_prefix (prefix))
5989 /* Set mode64 for an operand. */
5990 if (i.suffix == QWORD_MNEM_SUFFIX
5991 && flag_code == CODE_64BIT
5992 && !i.tm.opcode_modifier.norex64
5993 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5995 && ! (i.operands == 2
5996 && i.tm.base_opcode == 0x90
5997 && i.tm.extension_opcode == None
5998 && operand_type_equal (&i.types [0], &acc64)
5999 && operand_type_equal (&i.types [1], &acc64)))
6009 check_byte_reg (void)
6013 for (op = i.operands; --op >= 0;)
6015 /* Skip non-register operands. */
6016 if (!i.types[op].bitfield.reg)
6019 /* If this is an eight bit register, it's OK. If it's the 16 or
6020 32 bit version of an eight bit register, we will just use the
6021 low portion, and that's OK too. */
6022 if (i.types[op].bitfield.byte)
6025 /* I/O port address operands are OK too. */
6026 if (i.tm.operand_types[op].bitfield.inoutportreg)
6029 /* crc32 doesn't generate this warning. */
6030 if (i.tm.base_opcode == 0xf20f38f0)
6033 if ((i.types[op].bitfield.word
6034 || i.types[op].bitfield.dword
6035 || i.types[op].bitfield.qword)
6036 && i.op[op].regs->reg_num < 4
6037 /* Prohibit these changes in 64bit mode, since the lowering
6038 would be more complicated. */
6039 && flag_code != CODE_64BIT)
6041 #if REGISTER_WARNINGS
6042 if (!quiet_warnings)
6043 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6045 (i.op[op].regs + (i.types[op].bitfield.word
6046 ? REGNAM_AL - REGNAM_AX
6047 : REGNAM_AL - REGNAM_EAX))->reg_name,
6049 i.op[op].regs->reg_name,
6054 /* Any other register is bad. */
6055 if (i.types[op].bitfield.reg
6056 || i.types[op].bitfield.regmmx
6057 || i.types[op].bitfield.regsimd
6058 || i.types[op].bitfield.sreg2
6059 || i.types[op].bitfield.sreg3
6060 || i.types[op].bitfield.control
6061 || i.types[op].bitfield.debug
6062 || i.types[op].bitfield.test)
6064 as_bad (_("`%s%s' not allowed with `%s%c'"),
6066 i.op[op].regs->reg_name,
6076 check_long_reg (void)
6080 for (op = i.operands; --op >= 0;)
6081 /* Skip non-register operands. */
6082 if (!i.types[op].bitfield.reg)
6084 /* Reject eight bit registers, except where the template requires
6085 them. (eg. movzb) */
6086 else if (i.types[op].bitfield.byte
6087 && (i.tm.operand_types[op].bitfield.reg
6088 || i.tm.operand_types[op].bitfield.acc)
6089 && (i.tm.operand_types[op].bitfield.word
6090 || i.tm.operand_types[op].bitfield.dword))
6092 as_bad (_("`%s%s' not allowed with `%s%c'"),
6094 i.op[op].regs->reg_name,
6099 /* Warn if the e prefix on a general reg is missing. */
6100 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6101 && i.types[op].bitfield.word
6102 && (i.tm.operand_types[op].bitfield.reg
6103 || i.tm.operand_types[op].bitfield.acc)
6104 && i.tm.operand_types[op].bitfield.dword)
6106 /* Prohibit these changes in the 64bit mode, since the
6107 lowering is more complicated. */
6108 if (flag_code == CODE_64BIT)
6110 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6111 register_prefix, i.op[op].regs->reg_name,
6115 #if REGISTER_WARNINGS
6116 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6118 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6119 register_prefix, i.op[op].regs->reg_name, i.suffix);
6122 /* Warn if the r prefix on a general reg is present. */
6123 else if (i.types[op].bitfield.qword
6124 && (i.tm.operand_types[op].bitfield.reg
6125 || i.tm.operand_types[op].bitfield.acc)
6126 && i.tm.operand_types[op].bitfield.dword)
6129 && i.tm.opcode_modifier.toqword
6130 && !i.types[0].bitfield.regsimd)
6132 /* Convert to QWORD. We want REX byte. */
6133 i.suffix = QWORD_MNEM_SUFFIX;
6137 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6138 register_prefix, i.op[op].regs->reg_name,
6147 check_qword_reg (void)
6151 for (op = i.operands; --op >= 0; )
6152 /* Skip non-register operands. */
6153 if (!i.types[op].bitfield.reg)
6155 /* Reject eight bit registers, except where the template requires
6156 them. (eg. movzb) */
6157 else if (i.types[op].bitfield.byte
6158 && (i.tm.operand_types[op].bitfield.reg
6159 || i.tm.operand_types[op].bitfield.acc)
6160 && (i.tm.operand_types[op].bitfield.word
6161 || i.tm.operand_types[op].bitfield.dword))
6163 as_bad (_("`%s%s' not allowed with `%s%c'"),
6165 i.op[op].regs->reg_name,
6170 /* Warn if the r prefix on a general reg is missing. */
6171 else if ((i.types[op].bitfield.word
6172 || i.types[op].bitfield.dword)
6173 && (i.tm.operand_types[op].bitfield.reg
6174 || i.tm.operand_types[op].bitfield.acc)
6175 && i.tm.operand_types[op].bitfield.qword)
6177 /* Prohibit these changes in the 64bit mode, since the
6178 lowering is more complicated. */
6180 && i.tm.opcode_modifier.todword
6181 && !i.types[0].bitfield.regsimd)
6183 /* Convert to DWORD. We don't want REX byte. */
6184 i.suffix = LONG_MNEM_SUFFIX;
6188 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6189 register_prefix, i.op[op].regs->reg_name,
6198 check_word_reg (void)
6201 for (op = i.operands; --op >= 0;)
6202 /* Skip non-register operands. */
6203 if (!i.types[op].bitfield.reg)
6205 /* Reject eight bit registers, except where the template requires
6206 them. (eg. movzb) */
6207 else if (i.types[op].bitfield.byte
6208 && (i.tm.operand_types[op].bitfield.reg
6209 || i.tm.operand_types[op].bitfield.acc)
6210 && (i.tm.operand_types[op].bitfield.word
6211 || i.tm.operand_types[op].bitfield.dword))
6213 as_bad (_("`%s%s' not allowed with `%s%c'"),
6215 i.op[op].regs->reg_name,
6220 /* Warn if the e or r prefix on a general reg is present. */
6221 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6222 && (i.types[op].bitfield.dword
6223 || i.types[op].bitfield.qword)
6224 && (i.tm.operand_types[op].bitfield.reg
6225 || i.tm.operand_types[op].bitfield.acc)
6226 && i.tm.operand_types[op].bitfield.word)
6228 /* Prohibit these changes in the 64bit mode, since the
6229 lowering is more complicated. */
6230 if (flag_code == CODE_64BIT)
6232 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6233 register_prefix, i.op[op].regs->reg_name,
6237 #if REGISTER_WARNINGS
6238 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6240 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6241 register_prefix, i.op[op].regs->reg_name, i.suffix);
6248 update_imm (unsigned int j)
6250 i386_operand_type overlap = i.types[j];
6251 if ((overlap.bitfield.imm8
6252 || overlap.bitfield.imm8s
6253 || overlap.bitfield.imm16
6254 || overlap.bitfield.imm32
6255 || overlap.bitfield.imm32s
6256 || overlap.bitfield.imm64)
6257 && !operand_type_equal (&overlap, &imm8)
6258 && !operand_type_equal (&overlap, &imm8s)
6259 && !operand_type_equal (&overlap, &imm16)
6260 && !operand_type_equal (&overlap, &imm32)
6261 && !operand_type_equal (&overlap, &imm32s)
6262 && !operand_type_equal (&overlap, &imm64))
6266 i386_operand_type temp;
6268 operand_type_set (&temp, 0);
6269 if (i.suffix == BYTE_MNEM_SUFFIX)
6271 temp.bitfield.imm8 = overlap.bitfield.imm8;
6272 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6274 else if (i.suffix == WORD_MNEM_SUFFIX)
6275 temp.bitfield.imm16 = overlap.bitfield.imm16;
6276 else if (i.suffix == QWORD_MNEM_SUFFIX)
6278 temp.bitfield.imm64 = overlap.bitfield.imm64;
6279 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6282 temp.bitfield.imm32 = overlap.bitfield.imm32;
6285 else if (operand_type_equal (&overlap, &imm16_32_32s)
6286 || operand_type_equal (&overlap, &imm16_32)
6287 || operand_type_equal (&overlap, &imm16_32s))
6289 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6294 if (!operand_type_equal (&overlap, &imm8)
6295 && !operand_type_equal (&overlap, &imm8s)
6296 && !operand_type_equal (&overlap, &imm16)
6297 && !operand_type_equal (&overlap, &imm32)
6298 && !operand_type_equal (&overlap, &imm32s)
6299 && !operand_type_equal (&overlap, &imm64))
6301 as_bad (_("no instruction mnemonic suffix given; "
6302 "can't determine immediate size"));
6306 i.types[j] = overlap;
6316 /* Update the first 2 immediate operands. */
6317 n = i.operands > 2 ? 2 : i.operands;
6320 for (j = 0; j < n; j++)
6321 if (update_imm (j) == 0)
6324 /* The 3rd operand can't be immediate operand. */
6325 gas_assert (operand_type_check (i.types[2], imm) == 0);
6332 process_operands (void)
6334 /* Default segment register this instruction will use for memory
6335 accesses. 0 means unknown. This is only for optimizing out
6336 unnecessary segment overrides. */
6337 const seg_entry *default_seg = 0;
6339 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6341 unsigned int dupl = i.operands;
6342 unsigned int dest = dupl - 1;
6345 /* The destination must be an xmm register. */
6346 gas_assert (i.reg_operands
6347 && MAX_OPERANDS > dupl
6348 && operand_type_equal (&i.types[dest], ®xmm));
6350 if (i.tm.operand_types[0].bitfield.acc
6351 && i.tm.operand_types[0].bitfield.xmmword)
6353 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6355 /* Keep xmm0 for instructions with VEX prefix and 3
6357 i.tm.operand_types[0].bitfield.acc = 0;
6358 i.tm.operand_types[0].bitfield.regsimd = 1;
6363 /* We remove the first xmm0 and keep the number of
6364 operands unchanged, which in fact duplicates the
6366 for (j = 1; j < i.operands; j++)
6368 i.op[j - 1] = i.op[j];
6369 i.types[j - 1] = i.types[j];
6370 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6374 else if (i.tm.opcode_modifier.implicit1stxmm0)
6376 gas_assert ((MAX_OPERANDS - 1) > dupl
6377 && (i.tm.opcode_modifier.vexsources
6380 /* Add the implicit xmm0 for instructions with VEX prefix
6382 for (j = i.operands; j > 0; j--)
6384 i.op[j] = i.op[j - 1];
6385 i.types[j] = i.types[j - 1];
6386 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6389 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6390 i.types[0] = regxmm;
6391 i.tm.operand_types[0] = regxmm;
6394 i.reg_operands += 2;
6399 i.op[dupl] = i.op[dest];
6400 i.types[dupl] = i.types[dest];
6401 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6410 i.op[dupl] = i.op[dest];
6411 i.types[dupl] = i.types[dest];
6412 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6415 if (i.tm.opcode_modifier.immext)
6418 else if (i.tm.operand_types[0].bitfield.acc
6419 && i.tm.operand_types[0].bitfield.xmmword)
6423 for (j = 1; j < i.operands; j++)
6425 i.op[j - 1] = i.op[j];
6426 i.types[j - 1] = i.types[j];
6428 /* We need to adjust fields in i.tm since they are used by
6429 build_modrm_byte. */
6430 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6437 else if (i.tm.opcode_modifier.implicitquadgroup)
6439 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6441 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6442 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6443 regnum = register_number (i.op[1].regs);
6444 first_reg_in_group = regnum & ~3;
6445 last_reg_in_group = first_reg_in_group + 3;
6446 if (regnum != first_reg_in_group)
6447 as_warn (_("source register `%s%s' implicitly denotes"
6448 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6449 register_prefix, i.op[1].regs->reg_name,
6450 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6451 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6454 else if (i.tm.opcode_modifier.regkludge)
6456 /* The imul $imm, %reg instruction is converted into
6457 imul $imm, %reg, %reg, and the clr %reg instruction
6458 is converted into xor %reg, %reg. */
6460 unsigned int first_reg_op;
6462 if (operand_type_check (i.types[0], reg))
6466 /* Pretend we saw the extra register operand. */
6467 gas_assert (i.reg_operands == 1
6468 && i.op[first_reg_op + 1].regs == 0);
6469 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6470 i.types[first_reg_op + 1] = i.types[first_reg_op];
6475 if (i.tm.opcode_modifier.shortform)
6477 if (i.types[0].bitfield.sreg2
6478 || i.types[0].bitfield.sreg3)
6480 if (i.tm.base_opcode == POP_SEG_SHORT
6481 && i.op[0].regs->reg_num == 1)
6483 as_bad (_("you can't `pop %scs'"), register_prefix);
6486 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6487 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6492 /* The register or float register operand is in operand
6496 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6497 || operand_type_check (i.types[0], reg))
6501 /* Register goes in low 3 bits of opcode. */
6502 i.tm.base_opcode |= i.op[op].regs->reg_num;
6503 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6505 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6507 /* Warn about some common errors, but press on regardless.
6508 The first case can be generated by gcc (<= 2.8.1). */
6509 if (i.operands == 2)
6511 /* Reversed arguments on faddp, fsubp, etc. */
6512 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6513 register_prefix, i.op[!intel_syntax].regs->reg_name,
6514 register_prefix, i.op[intel_syntax].regs->reg_name);
6518 /* Extraneous `l' suffix on fp insn. */
6519 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6520 register_prefix, i.op[0].regs->reg_name);
6525 else if (i.tm.opcode_modifier.modrm)
6527 /* The opcode is completed (modulo i.tm.extension_opcode which
6528 must be put into the modrm byte). Now, we make the modrm and
6529 index base bytes based on all the info we've collected. */
6531 default_seg = build_modrm_byte ();
6533 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6537 else if (i.tm.opcode_modifier.isstring)
6539 /* For the string instructions that allow a segment override
6540 on one of their operands, the default segment is ds. */
6544 if (i.tm.base_opcode == 0x8d /* lea */
6547 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6549 /* If a segment was explicitly specified, and the specified segment
6550 is not the default, use an opcode prefix to select it. If we
6551 never figured out what the default segment is, then default_seg
6552 will be zero at this point, and the specified segment prefix will
6554 if ((i.seg[0]) && (i.seg[0] != default_seg))
6556 if (!add_prefix (i.seg[0]->seg_prefix))
6562 static const seg_entry *
6563 build_modrm_byte (void)
6565 const seg_entry *default_seg = 0;
6566 unsigned int source, dest;
6569 /* The first operand of instructions with VEX prefix and 3 sources
6570 must be VEX_Imm4. */
6571 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6574 unsigned int nds, reg_slot;
6577 if (i.tm.opcode_modifier.veximmext
6578 && i.tm.opcode_modifier.immext)
6580 dest = i.operands - 2;
6581 gas_assert (dest == 3);
6584 dest = i.operands - 1;
6587 /* There are 2 kinds of instructions:
6588 1. 5 operands: 4 register operands or 3 register operands
6589 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6590 VexW0 or VexW1. The destination must be either XMM, YMM or
6592 2. 4 operands: 4 register operands or 3 register operands
6593 plus 1 memory operand, VexXDS, and VexImmExt */
6594 gas_assert ((i.reg_operands == 4
6595 || (i.reg_operands == 3 && i.mem_operands == 1))
6596 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6597 && (i.tm.opcode_modifier.veximmext
6598 || (i.imm_operands == 1
6599 && i.types[0].bitfield.vec_imm4
6600 && (i.tm.opcode_modifier.vexw == VEXW0
6601 || i.tm.opcode_modifier.vexw == VEXW1)
6602 && i.tm.operand_types[dest].bitfield.regsimd)));
6604 if (i.imm_operands == 0)
6606 /* When there is no immediate operand, generate an 8bit
6607 immediate operand to encode the first operand. */
6608 exp = &im_expressions[i.imm_operands++];
6609 i.op[i.operands].imms = exp;
6610 i.types[i.operands] = imm8;
6612 /* If VexW1 is set, the first operand is the source and
6613 the second operand is encoded in the immediate operand. */
6614 if (i.tm.opcode_modifier.vexw == VEXW1)
6625 /* FMA swaps REG and NDS. */
6626 if (i.tm.cpu_flags.bitfield.cpufma)
6634 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6635 exp->X_op = O_constant;
6636 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6637 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6641 unsigned int imm_slot;
6643 if (i.tm.opcode_modifier.vexw == VEXW0)
6645 /* If VexW0 is set, the third operand is the source and
6646 the second operand is encoded in the immediate
6653 /* VexW1 is set, the second operand is the source and
6654 the third operand is encoded in the immediate
6660 if (i.tm.opcode_modifier.immext)
6662 /* When ImmExt is set, the immediate byte is the last
6664 imm_slot = i.operands - 1;
6672 /* Turn on Imm8 so that output_imm will generate it. */
6673 i.types[imm_slot].bitfield.imm8 = 1;
6676 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6677 i.op[imm_slot].imms->X_add_number
6678 |= register_number (i.op[reg_slot].regs) << 4;
6679 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6682 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6683 i.vex.register_specifier = i.op[nds].regs;
6688 /* i.reg_operands MUST be the number of real register operands;
6689 implicit registers do not count. If there are 3 register
6690 operands, it must be a instruction with VexNDS. For a
6691 instruction with VexNDD, the destination register is encoded
6692 in VEX prefix. If there are 4 register operands, it must be
6693 a instruction with VEX prefix and 3 sources. */
6694 if (i.mem_operands == 0
6695 && ((i.reg_operands == 2
6696 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6697 || (i.reg_operands == 3
6698 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6699 || (i.reg_operands == 4 && vex_3_sources)))
6707 /* When there are 3 operands, one of them may be immediate,
6708 which may be the first or the last operand. Otherwise,
6709 the first operand must be shift count register (cl) or it
6710 is an instruction with VexNDS. */
6711 gas_assert (i.imm_operands == 1
6712 || (i.imm_operands == 0
6713 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6714 || i.types[0].bitfield.shiftcount)));
6715 if (operand_type_check (i.types[0], imm)
6716 || i.types[0].bitfield.shiftcount)
6722 /* When there are 4 operands, the first two must be 8bit
6723 immediate operands. The source operand will be the 3rd
6726 For instructions with VexNDS, if the first operand
6727 an imm8, the source operand is the 2nd one. If the last
6728 operand is imm8, the source operand is the first one. */
6729 gas_assert ((i.imm_operands == 2
6730 && i.types[0].bitfield.imm8
6731 && i.types[1].bitfield.imm8)
6732 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6733 && i.imm_operands == 1
6734 && (i.types[0].bitfield.imm8
6735 || i.types[i.operands - 1].bitfield.imm8
6737 if (i.imm_operands == 2)
6741 if (i.types[0].bitfield.imm8)
6748 if (is_evex_encoding (&i.tm))
6750 /* For EVEX instructions, when there are 5 operands, the
6751 first one must be immediate operand. If the second one
6752 is immediate operand, the source operand is the 3th
6753 one. If the last one is immediate operand, the source
6754 operand is the 2nd one. */
6755 gas_assert (i.imm_operands == 2
6756 && i.tm.opcode_modifier.sae
6757 && operand_type_check (i.types[0], imm));
6758 if (operand_type_check (i.types[1], imm))
6760 else if (operand_type_check (i.types[4], imm))
6774 /* RC/SAE operand could be between DEST and SRC. That happens
6775 when one operand is GPR and the other one is XMM/YMM/ZMM
6777 if (i.rounding && i.rounding->operand == (int) dest)
6780 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6782 /* For instructions with VexNDS, the register-only source
6783 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6784 register. It is encoded in VEX prefix. We need to
6785 clear RegMem bit before calling operand_type_equal. */
6787 i386_operand_type op;
6790 /* Check register-only source operand when two source
6791 operands are swapped. */
6792 if (!i.tm.operand_types[source].bitfield.baseindex
6793 && i.tm.operand_types[dest].bitfield.baseindex)
6801 op = i.tm.operand_types[vvvv];
6802 op.bitfield.regmem = 0;
6803 if ((dest + 1) >= i.operands
6804 || ((!op.bitfield.reg
6805 || (!op.bitfield.dword && !op.bitfield.qword))
6806 && !op.bitfield.regsimd
6807 && !operand_type_equal (&op, ®mask)))
6809 i.vex.register_specifier = i.op[vvvv].regs;
6815 /* One of the register operands will be encoded in the i.tm.reg
6816 field, the other in the combined i.tm.mode and i.tm.regmem
6817 fields. If no form of this instruction supports a memory
6818 destination operand, then we assume the source operand may
6819 sometimes be a memory operand and so we need to store the
6820 destination in the i.rm.reg field. */
6821 if (!i.tm.operand_types[dest].bitfield.regmem
6822 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6824 i.rm.reg = i.op[dest].regs->reg_num;
6825 i.rm.regmem = i.op[source].regs->reg_num;
6826 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6828 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6830 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6832 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6837 i.rm.reg = i.op[source].regs->reg_num;
6838 i.rm.regmem = i.op[dest].regs->reg_num;
6839 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6841 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6843 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6845 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6848 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6850 if (!i.types[0].bitfield.control
6851 && !i.types[1].bitfield.control)
6853 i.rex &= ~(REX_R | REX_B);
6854 add_prefix (LOCK_PREFIX_OPCODE);
6858 { /* If it's not 2 reg operands... */
6863 unsigned int fake_zero_displacement = 0;
6866 for (op = 0; op < i.operands; op++)
6867 if (operand_type_check (i.types[op], anymem))
6869 gas_assert (op < i.operands);
6871 if (i.tm.opcode_modifier.vecsib)
6873 if (i.index_reg->reg_num == RegEiz
6874 || i.index_reg->reg_num == RegRiz)
6877 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6880 i.sib.base = NO_BASE_REGISTER;
6881 i.sib.scale = i.log2_scale_factor;
6882 i.types[op].bitfield.disp8 = 0;
6883 i.types[op].bitfield.disp16 = 0;
6884 i.types[op].bitfield.disp64 = 0;
6885 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6887 /* Must be 32 bit */
6888 i.types[op].bitfield.disp32 = 1;
6889 i.types[op].bitfield.disp32s = 0;
6893 i.types[op].bitfield.disp32 = 0;
6894 i.types[op].bitfield.disp32s = 1;
6897 i.sib.index = i.index_reg->reg_num;
6898 if ((i.index_reg->reg_flags & RegRex) != 0)
6900 if ((i.index_reg->reg_flags & RegVRex) != 0)
6906 if (i.base_reg == 0)
6909 if (!i.disp_operands)
6910 fake_zero_displacement = 1;
6911 if (i.index_reg == 0)
6913 i386_operand_type newdisp;
6915 gas_assert (!i.tm.opcode_modifier.vecsib);
6916 /* Operand is just <disp> */
6917 if (flag_code == CODE_64BIT)
6919 /* 64bit mode overwrites the 32bit absolute
6920 addressing by RIP relative addressing and
6921 absolute addressing is encoded by one of the
6922 redundant SIB forms. */
6923 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6924 i.sib.base = NO_BASE_REGISTER;
6925 i.sib.index = NO_INDEX_REGISTER;
6926 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6928 else if ((flag_code == CODE_16BIT)
6929 ^ (i.prefix[ADDR_PREFIX] != 0))
6931 i.rm.regmem = NO_BASE_REGISTER_16;
6936 i.rm.regmem = NO_BASE_REGISTER;
6939 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6940 i.types[op] = operand_type_or (i.types[op], newdisp);
6942 else if (!i.tm.opcode_modifier.vecsib)
6944 /* !i.base_reg && i.index_reg */
6945 if (i.index_reg->reg_num == RegEiz
6946 || i.index_reg->reg_num == RegRiz)
6947 i.sib.index = NO_INDEX_REGISTER;
6949 i.sib.index = i.index_reg->reg_num;
6950 i.sib.base = NO_BASE_REGISTER;
6951 i.sib.scale = i.log2_scale_factor;
6952 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6953 i.types[op].bitfield.disp8 = 0;
6954 i.types[op].bitfield.disp16 = 0;
6955 i.types[op].bitfield.disp64 = 0;
6956 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6958 /* Must be 32 bit */
6959 i.types[op].bitfield.disp32 = 1;
6960 i.types[op].bitfield.disp32s = 0;
6964 i.types[op].bitfield.disp32 = 0;
6965 i.types[op].bitfield.disp32s = 1;
6967 if ((i.index_reg->reg_flags & RegRex) != 0)
6971 /* RIP addressing for 64bit mode. */
6972 else if (i.base_reg->reg_num == RegRip ||
6973 i.base_reg->reg_num == RegEip)
6975 gas_assert (!i.tm.opcode_modifier.vecsib);
6976 i.rm.regmem = NO_BASE_REGISTER;
6977 i.types[op].bitfield.disp8 = 0;
6978 i.types[op].bitfield.disp16 = 0;
6979 i.types[op].bitfield.disp32 = 0;
6980 i.types[op].bitfield.disp32s = 1;
6981 i.types[op].bitfield.disp64 = 0;
6982 i.flags[op] |= Operand_PCrel;
6983 if (! i.disp_operands)
6984 fake_zero_displacement = 1;
6986 else if (i.base_reg->reg_type.bitfield.word)
6988 gas_assert (!i.tm.opcode_modifier.vecsib);
6989 switch (i.base_reg->reg_num)
6992 if (i.index_reg == 0)
6994 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6995 i.rm.regmem = i.index_reg->reg_num - 6;
6999 if (i.index_reg == 0)
7002 if (operand_type_check (i.types[op], disp) == 0)
7004 /* fake (%bp) into 0(%bp) */
7005 i.types[op].bitfield.disp8 = 1;
7006 fake_zero_displacement = 1;
7009 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7010 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7012 default: /* (%si) -> 4 or (%di) -> 5 */
7013 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7015 i.rm.mode = mode_from_disp_size (i.types[op]);
7017 else /* i.base_reg and 32/64 bit mode */
7019 if (flag_code == CODE_64BIT
7020 && operand_type_check (i.types[op], disp))
7022 i.types[op].bitfield.disp16 = 0;
7023 i.types[op].bitfield.disp64 = 0;
7024 if (i.prefix[ADDR_PREFIX] == 0)
7026 i.types[op].bitfield.disp32 = 0;
7027 i.types[op].bitfield.disp32s = 1;
7031 i.types[op].bitfield.disp32 = 1;
7032 i.types[op].bitfield.disp32s = 0;
7036 if (!i.tm.opcode_modifier.vecsib)
7037 i.rm.regmem = i.base_reg->reg_num;
7038 if ((i.base_reg->reg_flags & RegRex) != 0)
7040 i.sib.base = i.base_reg->reg_num;
7041 /* x86-64 ignores REX prefix bit here to avoid decoder
7043 if (!(i.base_reg->reg_flags & RegRex)
7044 && (i.base_reg->reg_num == EBP_REG_NUM
7045 || i.base_reg->reg_num == ESP_REG_NUM))
7047 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7049 fake_zero_displacement = 1;
7050 i.types[op].bitfield.disp8 = 1;
7052 i.sib.scale = i.log2_scale_factor;
7053 if (i.index_reg == 0)
7055 gas_assert (!i.tm.opcode_modifier.vecsib);
7056 /* <disp>(%esp) becomes two byte modrm with no index
7057 register. We've already stored the code for esp
7058 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7059 Any base register besides %esp will not use the
7060 extra modrm byte. */
7061 i.sib.index = NO_INDEX_REGISTER;
7063 else if (!i.tm.opcode_modifier.vecsib)
7065 if (i.index_reg->reg_num == RegEiz
7066 || i.index_reg->reg_num == RegRiz)
7067 i.sib.index = NO_INDEX_REGISTER;
7069 i.sib.index = i.index_reg->reg_num;
7070 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7071 if ((i.index_reg->reg_flags & RegRex) != 0)
7076 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7077 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7081 if (!fake_zero_displacement
7085 fake_zero_displacement = 1;
7086 if (i.disp_encoding == disp_encoding_8bit)
7087 i.types[op].bitfield.disp8 = 1;
7089 i.types[op].bitfield.disp32 = 1;
7091 i.rm.mode = mode_from_disp_size (i.types[op]);
7095 if (fake_zero_displacement)
7097 /* Fakes a zero displacement assuming that i.types[op]
7098 holds the correct displacement size. */
7101 gas_assert (i.op[op].disps == 0);
7102 exp = &disp_expressions[i.disp_operands++];
7103 i.op[op].disps = exp;
7104 exp->X_op = O_constant;
7105 exp->X_add_number = 0;
7106 exp->X_add_symbol = (symbolS *) 0;
7107 exp->X_op_symbol = (symbolS *) 0;
7115 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7117 if (operand_type_check (i.types[0], imm))
7118 i.vex.register_specifier = NULL;
7121 /* VEX.vvvv encodes one of the sources when the first
7122 operand is not an immediate. */
7123 if (i.tm.opcode_modifier.vexw == VEXW0)
7124 i.vex.register_specifier = i.op[0].regs;
7126 i.vex.register_specifier = i.op[1].regs;
7129 /* Destination is a XMM register encoded in the ModRM.reg
7131 i.rm.reg = i.op[2].regs->reg_num;
7132 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7135 /* ModRM.rm and VEX.B encodes the other source. */
7136 if (!i.mem_operands)
7140 if (i.tm.opcode_modifier.vexw == VEXW0)
7141 i.rm.regmem = i.op[1].regs->reg_num;
7143 i.rm.regmem = i.op[0].regs->reg_num;
7145 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7149 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7151 i.vex.register_specifier = i.op[2].regs;
7152 if (!i.mem_operands)
7155 i.rm.regmem = i.op[1].regs->reg_num;
7156 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7160 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7161 (if any) based on i.tm.extension_opcode. Again, we must be
7162 careful to make sure that segment/control/debug/test/MMX
7163 registers are coded into the i.rm.reg field. */
7164 else if (i.reg_operands)
7167 unsigned int vex_reg = ~0;
7169 for (op = 0; op < i.operands; op++)
7170 if (i.types[op].bitfield.reg
7171 || i.types[op].bitfield.regmmx
7172 || i.types[op].bitfield.regsimd
7173 || i.types[op].bitfield.regbnd
7174 || i.types[op].bitfield.regmask
7175 || i.types[op].bitfield.sreg2
7176 || i.types[op].bitfield.sreg3
7177 || i.types[op].bitfield.control
7178 || i.types[op].bitfield.debug
7179 || i.types[op].bitfield.test)
7184 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7186 /* For instructions with VexNDS, the register-only
7187 source operand is encoded in VEX prefix. */
7188 gas_assert (mem != (unsigned int) ~0);
7193 gas_assert (op < i.operands);
7197 /* Check register-only source operand when two source
7198 operands are swapped. */
7199 if (!i.tm.operand_types[op].bitfield.baseindex
7200 && i.tm.operand_types[op + 1].bitfield.baseindex)
7204 gas_assert (mem == (vex_reg + 1)
7205 && op < i.operands);
7210 gas_assert (vex_reg < i.operands);
7214 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7216 /* For instructions with VexNDD, the register destination
7217 is encoded in VEX prefix. */
7218 if (i.mem_operands == 0)
7220 /* There is no memory operand. */
7221 gas_assert ((op + 2) == i.operands);
7226 /* There are only 2 non-immediate operands. */
7227 gas_assert (op < i.imm_operands + 2
7228 && i.operands == i.imm_operands + 2);
7229 vex_reg = i.imm_operands + 1;
7233 gas_assert (op < i.operands);
7235 if (vex_reg != (unsigned int) ~0)
7237 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7239 if ((!type->bitfield.reg
7240 || (!type->bitfield.dword && !type->bitfield.qword))
7241 && !type->bitfield.regsimd
7242 && !operand_type_equal (type, ®mask))
7245 i.vex.register_specifier = i.op[vex_reg].regs;
7248 /* Don't set OP operand twice. */
7251 /* If there is an extension opcode to put here, the
7252 register number must be put into the regmem field. */
7253 if (i.tm.extension_opcode != None)
7255 i.rm.regmem = i.op[op].regs->reg_num;
7256 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7258 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7263 i.rm.reg = i.op[op].regs->reg_num;
7264 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7266 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7271 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7272 must set it to 3 to indicate this is a register operand
7273 in the regmem field. */
7274 if (!i.mem_operands)
7278 /* Fill in i.rm.reg field with extension opcode (if any). */
7279 if (i.tm.extension_opcode != None)
7280 i.rm.reg = i.tm.extension_opcode;
7286 output_branch (void)
7292 relax_substateT subtype;
7296 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7297 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7300 if (i.prefix[DATA_PREFIX] != 0)
7306 /* Pentium4 branch hints. */
7307 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7308 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7313 if (i.prefix[REX_PREFIX] != 0)
7319 /* BND prefixed jump. */
7320 if (i.prefix[BND_PREFIX] != 0)
7322 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7326 if (i.prefixes != 0 && !intel_syntax)
7327 as_warn (_("skipping prefixes on this instruction"));
7329 /* It's always a symbol; End frag & setup for relax.
7330 Make sure there is enough room in this frag for the largest
7331 instruction we may generate in md_convert_frag. This is 2
7332 bytes for the opcode and room for the prefix and largest
7334 frag_grow (prefix + 2 + 4);
7335 /* Prefix and 1 opcode byte go in fr_fix. */
7336 p = frag_more (prefix + 1);
7337 if (i.prefix[DATA_PREFIX] != 0)
7338 *p++ = DATA_PREFIX_OPCODE;
7339 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7340 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7341 *p++ = i.prefix[SEG_PREFIX];
7342 if (i.prefix[REX_PREFIX] != 0)
7343 *p++ = i.prefix[REX_PREFIX];
7344 *p = i.tm.base_opcode;
7346 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7347 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7348 else if (cpu_arch_flags.bitfield.cpui386)
7349 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7351 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7354 sym = i.op[0].disps->X_add_symbol;
7355 off = i.op[0].disps->X_add_number;
7357 if (i.op[0].disps->X_op != O_constant
7358 && i.op[0].disps->X_op != O_symbol)
7360 /* Handle complex expressions. */
7361 sym = make_expr_symbol (i.op[0].disps);
7365 /* 1 possible extra opcode + 4 byte displacement go in var part.
7366 Pass reloc in fr_var. */
7367 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7370 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7371 /* Return TRUE iff PLT32 relocation should be used for branching to
7375 need_plt32_p (symbolS *s)
7377 /* PLT32 relocation is ELF only. */
7381 /* Since there is no need to prepare for PLT branch on x86-64, we
7382 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7383 be used as a marker for 32-bit PC-relative branches. */
7387 /* Weak or undefined symbol need PLT32 relocation. */
7388 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7391 /* Non-global symbol doesn't need PLT32 relocation. */
7392 if (! S_IS_EXTERNAL (s))
7395 /* Other global symbols need PLT32 relocation. NB: Symbol with
7396 non-default visibilities are treated as normal global symbol
7397 so that PLT32 relocation can be used as a marker for 32-bit
7398 PC-relative branches. It is useful for linker relaxation. */
7409 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7411 if (i.tm.opcode_modifier.jumpbyte)
7413 /* This is a loop or jecxz type instruction. */
7415 if (i.prefix[ADDR_PREFIX] != 0)
7417 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7420 /* Pentium4 branch hints. */
7421 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7422 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7424 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7433 if (flag_code == CODE_16BIT)
7436 if (i.prefix[DATA_PREFIX] != 0)
7438 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7448 if (i.prefix[REX_PREFIX] != 0)
7450 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7454 /* BND prefixed jump. */
7455 if (i.prefix[BND_PREFIX] != 0)
7457 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7461 if (i.prefixes != 0 && !intel_syntax)
7462 as_warn (_("skipping prefixes on this instruction"));
7464 p = frag_more (i.tm.opcode_length + size);
7465 switch (i.tm.opcode_length)
7468 *p++ = i.tm.base_opcode >> 8;
7471 *p++ = i.tm.base_opcode;
7477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7479 && jump_reloc == NO_RELOC
7480 && need_plt32_p (i.op[0].disps->X_add_symbol))
7481 jump_reloc = BFD_RELOC_X86_64_PLT32;
7484 jump_reloc = reloc (size, 1, 1, jump_reloc);
7486 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7487 i.op[0].disps, 1, jump_reloc);
7489 /* All jumps handled here are signed, but don't use a signed limit
7490 check for 32 and 16 bit jumps as we want to allow wrap around at
7491 4G and 64k respectively. */
7493 fixP->fx_signed = 1;
7497 output_interseg_jump (void)
7505 if (flag_code == CODE_16BIT)
7509 if (i.prefix[DATA_PREFIX] != 0)
7515 if (i.prefix[REX_PREFIX] != 0)
7525 if (i.prefixes != 0 && !intel_syntax)
7526 as_warn (_("skipping prefixes on this instruction"));
7528 /* 1 opcode; 2 segment; offset */
7529 p = frag_more (prefix + 1 + 2 + size);
7531 if (i.prefix[DATA_PREFIX] != 0)
7532 *p++ = DATA_PREFIX_OPCODE;
7534 if (i.prefix[REX_PREFIX] != 0)
7535 *p++ = i.prefix[REX_PREFIX];
7537 *p++ = i.tm.base_opcode;
7538 if (i.op[1].imms->X_op == O_constant)
7540 offsetT n = i.op[1].imms->X_add_number;
7543 && !fits_in_unsigned_word (n)
7544 && !fits_in_signed_word (n))
7546 as_bad (_("16-bit jump out of range"));
7549 md_number_to_chars (p, n, size);
7552 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7553 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7554 if (i.op[0].imms->X_op != O_constant)
7555 as_bad (_("can't handle non absolute segment in `%s'"),
7557 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7563 fragS *insn_start_frag;
7564 offsetT insn_start_off;
7566 /* Tie dwarf2 debug info to the address at the start of the insn.
7567 We can't do this after the insn has been output as the current
7568 frag may have been closed off. eg. by frag_var. */
7569 dwarf2_emit_insn (0);
7571 insn_start_frag = frag_now;
7572 insn_start_off = frag_now_fix ();
7575 if (i.tm.opcode_modifier.jump)
7577 else if (i.tm.opcode_modifier.jumpbyte
7578 || i.tm.opcode_modifier.jumpdword)
7580 else if (i.tm.opcode_modifier.jumpintersegment)
7581 output_interseg_jump ();
7584 /* Output normal instructions here. */
7588 unsigned int prefix;
7591 && i.tm.base_opcode == 0xfae
7593 && i.imm_operands == 1
7594 && (i.op[0].imms->X_add_number == 0xe8
7595 || i.op[0].imms->X_add_number == 0xf0
7596 || i.op[0].imms->X_add_number == 0xf8))
7598 /* Encode lfence, mfence, and sfence as
7599 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7600 offsetT val = 0x240483f0ULL;
7602 md_number_to_chars (p, val, 5);
7606 /* Some processors fail on LOCK prefix. This options makes
7607 assembler ignore LOCK prefix and serves as a workaround. */
7608 if (omit_lock_prefix)
7610 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7612 i.prefix[LOCK_PREFIX] = 0;
7615 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7616 don't need the explicit prefix. */
7617 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7619 switch (i.tm.opcode_length)
7622 if (i.tm.base_opcode & 0xff000000)
7624 prefix = (i.tm.base_opcode >> 24) & 0xff;
7629 if ((i.tm.base_opcode & 0xff0000) != 0)
7631 prefix = (i.tm.base_opcode >> 16) & 0xff;
7632 if (i.tm.cpu_flags.bitfield.cpupadlock)
7635 if (prefix != REPE_PREFIX_OPCODE
7636 || (i.prefix[REP_PREFIX]
7637 != REPE_PREFIX_OPCODE))
7638 add_prefix (prefix);
7641 add_prefix (prefix);
7647 /* Check for pseudo prefixes. */
7648 as_bad_where (insn_start_frag->fr_file,
7649 insn_start_frag->fr_line,
7650 _("pseudo prefix without instruction"));
7656 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7657 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7658 R_X86_64_GOTTPOFF relocation so that linker can safely
7659 perform IE->LE optimization. */
7660 if (x86_elf_abi == X86_64_X32_ABI
7662 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7663 && i.prefix[REX_PREFIX] == 0)
7664 add_prefix (REX_OPCODE);
7667 /* The prefix bytes. */
7668 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7670 FRAG_APPEND_1_CHAR (*q);
7674 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7679 /* REX byte is encoded in VEX prefix. */
7683 FRAG_APPEND_1_CHAR (*q);
7686 /* There should be no other prefixes for instructions
7691 /* For EVEX instructions i.vrex should become 0 after
7692 build_evex_prefix. For VEX instructions upper 16 registers
7693 aren't available, so VREX should be 0. */
7696 /* Now the VEX prefix. */
7697 p = frag_more (i.vex.length);
7698 for (j = 0; j < i.vex.length; j++)
7699 p[j] = i.vex.bytes[j];
7702 /* Now the opcode; be careful about word order here! */
7703 if (i.tm.opcode_length == 1)
7705 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7709 switch (i.tm.opcode_length)
7713 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7714 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7718 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7728 /* Put out high byte first: can't use md_number_to_chars! */
7729 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7730 *p = i.tm.base_opcode & 0xff;
7733 /* Now the modrm byte and sib byte (if present). */
7734 if (i.tm.opcode_modifier.modrm)
7736 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7739 /* If i.rm.regmem == ESP (4)
7740 && i.rm.mode != (Register mode)
7742 ==> need second modrm byte. */
7743 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7745 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7746 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7748 | i.sib.scale << 6));
7751 if (i.disp_operands)
7752 output_disp (insn_start_frag, insn_start_off);
7755 output_imm (insn_start_frag, insn_start_off);
7761 pi ("" /*line*/, &i);
7763 #endif /* DEBUG386 */
7766 /* Return the size of the displacement operand N. */
7769 disp_size (unsigned int n)
7773 if (i.types[n].bitfield.disp64)
7775 else if (i.types[n].bitfield.disp8)
7777 else if (i.types[n].bitfield.disp16)
7782 /* Return the size of the immediate operand N. */
7785 imm_size (unsigned int n)
7788 if (i.types[n].bitfield.imm64)
7790 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7792 else if (i.types[n].bitfield.imm16)
7798 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7803 for (n = 0; n < i.operands; n++)
7805 if (operand_type_check (i.types[n], disp))
7807 if (i.op[n].disps->X_op == O_constant)
7809 int size = disp_size (n);
7810 offsetT val = i.op[n].disps->X_add_number;
7812 val = offset_in_range (val >> i.memshift, size);
7813 p = frag_more (size);
7814 md_number_to_chars (p, val, size);
7818 enum bfd_reloc_code_real reloc_type;
7819 int size = disp_size (n);
7820 int sign = i.types[n].bitfield.disp32s;
7821 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7824 /* We can't have 8 bit displacement here. */
7825 gas_assert (!i.types[n].bitfield.disp8);
7827 /* The PC relative address is computed relative
7828 to the instruction boundary, so in case immediate
7829 fields follows, we need to adjust the value. */
7830 if (pcrel && i.imm_operands)
7835 for (n1 = 0; n1 < i.operands; n1++)
7836 if (operand_type_check (i.types[n1], imm))
7838 /* Only one immediate is allowed for PC
7839 relative address. */
7840 gas_assert (sz == 0);
7842 i.op[n].disps->X_add_number -= sz;
7844 /* We should find the immediate. */
7845 gas_assert (sz != 0);
7848 p = frag_more (size);
7849 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7851 && GOT_symbol == i.op[n].disps->X_add_symbol
7852 && (((reloc_type == BFD_RELOC_32
7853 || reloc_type == BFD_RELOC_X86_64_32S
7854 || (reloc_type == BFD_RELOC_64
7856 && (i.op[n].disps->X_op == O_symbol
7857 || (i.op[n].disps->X_op == O_add
7858 && ((symbol_get_value_expression
7859 (i.op[n].disps->X_op_symbol)->X_op)
7861 || reloc_type == BFD_RELOC_32_PCREL))
7865 if (insn_start_frag == frag_now)
7866 add = (p - frag_now->fr_literal) - insn_start_off;
7871 add = insn_start_frag->fr_fix - insn_start_off;
7872 for (fr = insn_start_frag->fr_next;
7873 fr && fr != frag_now; fr = fr->fr_next)
7875 add += p - frag_now->fr_literal;
7880 reloc_type = BFD_RELOC_386_GOTPC;
7881 i.op[n].imms->X_add_number += add;
7883 else if (reloc_type == BFD_RELOC_64)
7884 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7886 /* Don't do the adjustment for x86-64, as there
7887 the pcrel addressing is relative to the _next_
7888 insn, and that is taken care of in other code. */
7889 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7891 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7892 size, i.op[n].disps, pcrel,
7894 /* Check for "call/jmp *mem", "mov mem, %reg",
7895 "test %reg, mem" and "binop mem, %reg" where binop
7896 is one of adc, add, and, cmp, or, sbb, sub, xor
7897 instructions. Always generate R_386_GOT32X for
7898 "sym*GOT" operand in 32-bit mode. */
7899 if ((generate_relax_relocations
7902 && i.rm.regmem == 5))
7904 || (i.rm.mode == 0 && i.rm.regmem == 5))
7905 && ((i.operands == 1
7906 && i.tm.base_opcode == 0xff
7907 && (i.rm.reg == 2 || i.rm.reg == 4))
7909 && (i.tm.base_opcode == 0x8b
7910 || i.tm.base_opcode == 0x85
7911 || (i.tm.base_opcode & 0xc7) == 0x03))))
7915 fixP->fx_tcbit = i.rex != 0;
7917 && (i.base_reg->reg_num == RegRip
7918 || i.base_reg->reg_num == RegEip))
7919 fixP->fx_tcbit2 = 1;
7922 fixP->fx_tcbit2 = 1;
7930 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7935 for (n = 0; n < i.operands; n++)
7937 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7938 if (i.rounding && (int) n == i.rounding->operand)
7941 if (operand_type_check (i.types[n], imm))
7943 if (i.op[n].imms->X_op == O_constant)
7945 int size = imm_size (n);
7948 val = offset_in_range (i.op[n].imms->X_add_number,
7950 p = frag_more (size);
7951 md_number_to_chars (p, val, size);
7955 /* Not absolute_section.
7956 Need a 32-bit fixup (don't support 8bit
7957 non-absolute imms). Try to support other
7959 enum bfd_reloc_code_real reloc_type;
7960 int size = imm_size (n);
7963 if (i.types[n].bitfield.imm32s
7964 && (i.suffix == QWORD_MNEM_SUFFIX
7965 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7970 p = frag_more (size);
7971 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7973 /* This is tough to explain. We end up with this one if we
7974 * have operands that look like
7975 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7976 * obtain the absolute address of the GOT, and it is strongly
7977 * preferable from a performance point of view to avoid using
7978 * a runtime relocation for this. The actual sequence of
7979 * instructions often look something like:
7984 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7986 * The call and pop essentially return the absolute address
7987 * of the label .L66 and store it in %ebx. The linker itself
7988 * will ultimately change the first operand of the addl so
7989 * that %ebx points to the GOT, but to keep things simple, the
7990 * .o file must have this operand set so that it generates not
7991 * the absolute address of .L66, but the absolute address of
7992 * itself. This allows the linker itself simply treat a GOTPC
7993 * relocation as asking for a pcrel offset to the GOT to be
7994 * added in, and the addend of the relocation is stored in the
7995 * operand field for the instruction itself.
7997 * Our job here is to fix the operand so that it would add
7998 * the correct offset so that %ebx would point to itself. The
7999 * thing that is tricky is that .-.L66 will point to the
8000 * beginning of the instruction, so we need to further modify
8001 * the operand so that it will point to itself. There are
8002 * other cases where you have something like:
8004 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8006 * and here no correction would be required. Internally in
8007 * the assembler we treat operands of this form as not being
8008 * pcrel since the '.' is explicitly mentioned, and I wonder
8009 * whether it would simplify matters to do it this way. Who
8010 * knows. In earlier versions of the PIC patches, the
8011 * pcrel_adjust field was used to store the correction, but
8012 * since the expression is not pcrel, I felt it would be
8013 * confusing to do it this way. */
8015 if ((reloc_type == BFD_RELOC_32
8016 || reloc_type == BFD_RELOC_X86_64_32S
8017 || reloc_type == BFD_RELOC_64)
8019 && GOT_symbol == i.op[n].imms->X_add_symbol
8020 && (i.op[n].imms->X_op == O_symbol
8021 || (i.op[n].imms->X_op == O_add
8022 && ((symbol_get_value_expression
8023 (i.op[n].imms->X_op_symbol)->X_op)
8028 if (insn_start_frag == frag_now)
8029 add = (p - frag_now->fr_literal) - insn_start_off;
8034 add = insn_start_frag->fr_fix - insn_start_off;
8035 for (fr = insn_start_frag->fr_next;
8036 fr && fr != frag_now; fr = fr->fr_next)
8038 add += p - frag_now->fr_literal;
8042 reloc_type = BFD_RELOC_386_GOTPC;
8044 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8046 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8047 i.op[n].imms->X_add_number += add;
8049 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8050 i.op[n].imms, 0, reloc_type);
8056 /* x86_cons_fix_new is called via the expression parsing code when a
8057 reloc is needed. We use this hook to get the correct .got reloc. */
8058 static int cons_sign = -1;
8061 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8062 expressionS *exp, bfd_reloc_code_real_type r)
8064 r = reloc (len, 0, cons_sign, r);
8067 if (exp->X_op == O_secrel)
8069 exp->X_op = O_symbol;
8070 r = BFD_RELOC_32_SECREL;
8074 fix_new_exp (frag, off, len, exp, 0, r);
8077 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8078 purpose of the `.dc.a' internal pseudo-op. */
8081 x86_address_bytes (void)
8083 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8085 return stdoutput->arch_info->bits_per_address / 8;
8088 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8090 # define lex_got(reloc, adjust, types) NULL
8092 /* Parse operands of the form
8093 <symbol>@GOTOFF+<nnn>
8094 and similar .plt or .got references.
8096 If we find one, set up the correct relocation in RELOC and copy the
8097 input string, minus the `@GOTOFF' into a malloc'd buffer for
8098 parsing by the calling routine. Return this buffer, and if ADJUST
8099 is non-null set it to the length of the string we removed from the
8100 input line. Otherwise return NULL. */
8102 lex_got (enum bfd_reloc_code_real *rel,
8104 i386_operand_type *types)
8106 /* Some of the relocations depend on the size of what field is to
8107 be relocated. But in our callers i386_immediate and i386_displacement
8108 we don't yet know the operand size (this will be set by insn
8109 matching). Hence we record the word32 relocation here,
8110 and adjust the reloc according to the real size in reloc(). */
8111 static const struct {
8114 const enum bfd_reloc_code_real rel[2];
8115 const i386_operand_type types64;
8117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8118 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8120 OPERAND_TYPE_IMM32_64 },
8122 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8123 BFD_RELOC_X86_64_PLTOFF64 },
8124 OPERAND_TYPE_IMM64 },
8125 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8126 BFD_RELOC_X86_64_PLT32 },
8127 OPERAND_TYPE_IMM32_32S_DISP32 },
8128 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8129 BFD_RELOC_X86_64_GOTPLT64 },
8130 OPERAND_TYPE_IMM64_DISP64 },
8131 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8132 BFD_RELOC_X86_64_GOTOFF64 },
8133 OPERAND_TYPE_IMM64_DISP64 },
8134 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8135 BFD_RELOC_X86_64_GOTPCREL },
8136 OPERAND_TYPE_IMM32_32S_DISP32 },
8137 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8138 BFD_RELOC_X86_64_TLSGD },
8139 OPERAND_TYPE_IMM32_32S_DISP32 },
8140 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8141 _dummy_first_bfd_reloc_code_real },
8142 OPERAND_TYPE_NONE },
8143 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8144 BFD_RELOC_X86_64_TLSLD },
8145 OPERAND_TYPE_IMM32_32S_DISP32 },
8146 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8147 BFD_RELOC_X86_64_GOTTPOFF },
8148 OPERAND_TYPE_IMM32_32S_DISP32 },
8149 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8150 BFD_RELOC_X86_64_TPOFF32 },
8151 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8152 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8153 _dummy_first_bfd_reloc_code_real },
8154 OPERAND_TYPE_NONE },
8155 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8156 BFD_RELOC_X86_64_DTPOFF32 },
8157 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8158 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8159 _dummy_first_bfd_reloc_code_real },
8160 OPERAND_TYPE_NONE },
8161 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8162 _dummy_first_bfd_reloc_code_real },
8163 OPERAND_TYPE_NONE },
8164 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8165 BFD_RELOC_X86_64_GOT32 },
8166 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8167 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8168 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8169 OPERAND_TYPE_IMM32_32S_DISP32 },
8170 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8171 BFD_RELOC_X86_64_TLSDESC_CALL },
8172 OPERAND_TYPE_IMM32_32S_DISP32 },
8177 #if defined (OBJ_MAYBE_ELF)
8182 for (cp = input_line_pointer; *cp != '@'; cp++)
8183 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8186 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8188 int len = gotrel[j].len;
8189 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8191 if (gotrel[j].rel[object_64bit] != 0)
8194 char *tmpbuf, *past_reloc;
8196 *rel = gotrel[j].rel[object_64bit];
8200 if (flag_code != CODE_64BIT)
8202 types->bitfield.imm32 = 1;
8203 types->bitfield.disp32 = 1;
8206 *types = gotrel[j].types64;
8209 if (j != 0 && GOT_symbol == NULL)
8210 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8212 /* The length of the first part of our input line. */
8213 first = cp - input_line_pointer;
8215 /* The second part goes from after the reloc token until
8216 (and including) an end_of_line char or comma. */
8217 past_reloc = cp + 1 + len;
8219 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8221 second = cp + 1 - past_reloc;
8223 /* Allocate and copy string. The trailing NUL shouldn't
8224 be necessary, but be safe. */
8225 tmpbuf = XNEWVEC (char, first + second + 2);
8226 memcpy (tmpbuf, input_line_pointer, first);
8227 if (second != 0 && *past_reloc != ' ')
8228 /* Replace the relocation token with ' ', so that
8229 errors like foo@GOTOFF1 will be detected. */
8230 tmpbuf[first++] = ' ';
8232 /* Increment length by 1 if the relocation token is
8237 memcpy (tmpbuf + first, past_reloc, second);
8238 tmpbuf[first + second] = '\0';
8242 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8243 gotrel[j].str, 1 << (5 + object_64bit));
8248 /* Might be a symbol version string. Don't as_bad here. */
8257 /* Parse operands of the form
8258 <symbol>@SECREL32+<nnn>
8260 If we find one, set up the correct relocation in RELOC and copy the
8261 input string, minus the `@SECREL32' into a malloc'd buffer for
8262 parsing by the calling routine. Return this buffer, and if ADJUST
8263 is non-null set it to the length of the string we removed from the
8264 input line. Otherwise return NULL.
8266 This function is copied from the ELF version above adjusted for PE targets. */
8269 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8270 int *adjust ATTRIBUTE_UNUSED,
8271 i386_operand_type *types)
8277 const enum bfd_reloc_code_real rel[2];
8278 const i386_operand_type types64;
8282 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8283 BFD_RELOC_32_SECREL },
8284 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8290 for (cp = input_line_pointer; *cp != '@'; cp++)
8291 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8294 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8296 int len = gotrel[j].len;
8298 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8300 if (gotrel[j].rel[object_64bit] != 0)
8303 char *tmpbuf, *past_reloc;
8305 *rel = gotrel[j].rel[object_64bit];
8311 if (flag_code != CODE_64BIT)
8313 types->bitfield.imm32 = 1;
8314 types->bitfield.disp32 = 1;
8317 *types = gotrel[j].types64;
8320 /* The length of the first part of our input line. */
8321 first = cp - input_line_pointer;
8323 /* The second part goes from after the reloc token until
8324 (and including) an end_of_line char or comma. */
8325 past_reloc = cp + 1 + len;
8327 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8329 second = cp + 1 - past_reloc;
8331 /* Allocate and copy string. The trailing NUL shouldn't
8332 be necessary, but be safe. */
8333 tmpbuf = XNEWVEC (char, first + second + 2);
8334 memcpy (tmpbuf, input_line_pointer, first);
8335 if (second != 0 && *past_reloc != ' ')
8336 /* Replace the relocation token with ' ', so that
8337 errors like foo@SECLREL321 will be detected. */
8338 tmpbuf[first++] = ' ';
8339 memcpy (tmpbuf + first, past_reloc, second);
8340 tmpbuf[first + second] = '\0';
8344 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8345 gotrel[j].str, 1 << (5 + object_64bit));
8350 /* Might be a symbol version string. Don't as_bad here. */
8356 bfd_reloc_code_real_type
8357 x86_cons (expressionS *exp, int size)
8359 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8361 intel_syntax = -intel_syntax;
8364 if (size == 4 || (object_64bit && size == 8))
8366 /* Handle @GOTOFF and the like in an expression. */
8368 char *gotfree_input_line;
8371 save = input_line_pointer;
8372 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8373 if (gotfree_input_line)
8374 input_line_pointer = gotfree_input_line;
8378 if (gotfree_input_line)
8380 /* expression () has merrily parsed up to the end of line,
8381 or a comma - in the wrong buffer. Transfer how far
8382 input_line_pointer has moved to the right buffer. */
8383 input_line_pointer = (save
8384 + (input_line_pointer - gotfree_input_line)
8386 free (gotfree_input_line);
8387 if (exp->X_op == O_constant
8388 || exp->X_op == O_absent
8389 || exp->X_op == O_illegal
8390 || exp->X_op == O_register
8391 || exp->X_op == O_big)
8393 char c = *input_line_pointer;
8394 *input_line_pointer = 0;
8395 as_bad (_("missing or invalid expression `%s'"), save);
8396 *input_line_pointer = c;
8403 intel_syntax = -intel_syntax;
8406 i386_intel_simplify (exp);
8412 signed_cons (int size)
8414 if (flag_code == CODE_64BIT)
8422 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8429 if (exp.X_op == O_symbol)
8430 exp.X_op = O_secrel;
8432 emit_expr (&exp, 4);
8434 while (*input_line_pointer++ == ',');
8436 input_line_pointer--;
8437 demand_empty_rest_of_line ();
8441 /* Handle Vector operations. */
8444 check_VecOperations (char *op_string, char *op_end)
8446 const reg_entry *mask;
8451 && (op_end == NULL || op_string < op_end))
8454 if (*op_string == '{')
8458 /* Check broadcasts. */
8459 if (strncmp (op_string, "1to", 3) == 0)
8464 goto duplicated_vec_op;
8467 if (*op_string == '8')
8469 else if (*op_string == '4')
8471 else if (*op_string == '2')
8473 else if (*op_string == '1'
8474 && *(op_string+1) == '6')
8481 as_bad (_("Unsupported broadcast: `%s'"), saved);
8486 broadcast_op.type = bcst_type;
8487 broadcast_op.operand = this_operand;
8488 i.broadcast = &broadcast_op;
8490 /* Check masking operation. */
8491 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8493 /* k0 can't be used for write mask. */
8494 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8496 as_bad (_("`%s%s' can't be used for write mask"),
8497 register_prefix, mask->reg_name);
8503 mask_op.mask = mask;
8504 mask_op.zeroing = 0;
8505 mask_op.operand = this_operand;
8511 goto duplicated_vec_op;
8513 i.mask->mask = mask;
8515 /* Only "{z}" is allowed here. No need to check
8516 zeroing mask explicitly. */
8517 if (i.mask->operand != this_operand)
8519 as_bad (_("invalid write mask `%s'"), saved);
8526 /* Check zeroing-flag for masking operation. */
8527 else if (*op_string == 'z')
8531 mask_op.mask = NULL;
8532 mask_op.zeroing = 1;
8533 mask_op.operand = this_operand;
8538 if (i.mask->zeroing)
8541 as_bad (_("duplicated `%s'"), saved);
8545 i.mask->zeroing = 1;
8547 /* Only "{%k}" is allowed here. No need to check mask
8548 register explicitly. */
8549 if (i.mask->operand != this_operand)
8551 as_bad (_("invalid zeroing-masking `%s'"),
8560 goto unknown_vec_op;
8562 if (*op_string != '}')
8564 as_bad (_("missing `}' in `%s'"), saved);
8569 /* Strip whitespace since the addition of pseudo prefixes
8570 changed how the scrubber treats '{'. */
8571 if (is_space_char (*op_string))
8577 /* We don't know this one. */
8578 as_bad (_("unknown vector operation: `%s'"), saved);
8582 if (i.mask && i.mask->zeroing && !i.mask->mask)
8584 as_bad (_("zeroing-masking only allowed with write mask"));
8592 i386_immediate (char *imm_start)
8594 char *save_input_line_pointer;
8595 char *gotfree_input_line;
8598 i386_operand_type types;
8600 operand_type_set (&types, ~0);
8602 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8604 as_bad (_("at most %d immediate operands are allowed"),
8605 MAX_IMMEDIATE_OPERANDS);
8609 exp = &im_expressions[i.imm_operands++];
8610 i.op[this_operand].imms = exp;
8612 if (is_space_char (*imm_start))
8615 save_input_line_pointer = input_line_pointer;
8616 input_line_pointer = imm_start;
8618 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8619 if (gotfree_input_line)
8620 input_line_pointer = gotfree_input_line;
8622 exp_seg = expression (exp);
8626 /* Handle vector operations. */
8627 if (*input_line_pointer == '{')
8629 input_line_pointer = check_VecOperations (input_line_pointer,
8631 if (input_line_pointer == NULL)
8635 if (*input_line_pointer)
8636 as_bad (_("junk `%s' after expression"), input_line_pointer);
8638 input_line_pointer = save_input_line_pointer;
8639 if (gotfree_input_line)
8641 free (gotfree_input_line);
8643 if (exp->X_op == O_constant || exp->X_op == O_register)
8644 exp->X_op = O_illegal;
8647 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8651 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8652 i386_operand_type types, const char *imm_start)
8654 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8657 as_bad (_("missing or invalid immediate expression `%s'"),
8661 else if (exp->X_op == O_constant)
8663 /* Size it properly later. */
8664 i.types[this_operand].bitfield.imm64 = 1;
8665 /* If not 64bit, sign extend val. */
8666 if (flag_code != CODE_64BIT
8667 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8669 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8671 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8672 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8673 && exp_seg != absolute_section
8674 && exp_seg != text_section
8675 && exp_seg != data_section
8676 && exp_seg != bss_section
8677 && exp_seg != undefined_section
8678 && !bfd_is_com_section (exp_seg))
8680 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8684 else if (!intel_syntax && exp_seg == reg_section)
8687 as_bad (_("illegal immediate register operand %s"), imm_start);
8692 /* This is an address. The size of the address will be
8693 determined later, depending on destination register,
8694 suffix, or the default for the section. */
8695 i.types[this_operand].bitfield.imm8 = 1;
8696 i.types[this_operand].bitfield.imm16 = 1;
8697 i.types[this_operand].bitfield.imm32 = 1;
8698 i.types[this_operand].bitfield.imm32s = 1;
8699 i.types[this_operand].bitfield.imm64 = 1;
8700 i.types[this_operand] = operand_type_and (i.types[this_operand],
8708 i386_scale (char *scale)
8711 char *save = input_line_pointer;
8713 input_line_pointer = scale;
8714 val = get_absolute_expression ();
8719 i.log2_scale_factor = 0;
8722 i.log2_scale_factor = 1;
8725 i.log2_scale_factor = 2;
8728 i.log2_scale_factor = 3;
8732 char sep = *input_line_pointer;
8734 *input_line_pointer = '\0';
8735 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8737 *input_line_pointer = sep;
8738 input_line_pointer = save;
8742 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8744 as_warn (_("scale factor of %d without an index register"),
8745 1 << i.log2_scale_factor);
8746 i.log2_scale_factor = 0;
8748 scale = input_line_pointer;
8749 input_line_pointer = save;
8754 i386_displacement (char *disp_start, char *disp_end)
8758 char *save_input_line_pointer;
8759 char *gotfree_input_line;
8761 i386_operand_type bigdisp, types = anydisp;
8764 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8766 as_bad (_("at most %d displacement operands are allowed"),
8767 MAX_MEMORY_OPERANDS);
8771 operand_type_set (&bigdisp, 0);
8772 if ((i.types[this_operand].bitfield.jumpabsolute)
8773 || (!current_templates->start->opcode_modifier.jump
8774 && !current_templates->start->opcode_modifier.jumpdword))
8776 bigdisp.bitfield.disp32 = 1;
8777 override = (i.prefix[ADDR_PREFIX] != 0);
8778 if (flag_code == CODE_64BIT)
8782 bigdisp.bitfield.disp32s = 1;
8783 bigdisp.bitfield.disp64 = 1;
8786 else if ((flag_code == CODE_16BIT) ^ override)
8788 bigdisp.bitfield.disp32 = 0;
8789 bigdisp.bitfield.disp16 = 1;
8794 /* For PC-relative branches, the width of the displacement
8795 is dependent upon data size, not address size. */
8796 override = (i.prefix[DATA_PREFIX] != 0);
8797 if (flag_code == CODE_64BIT)
8799 if (override || i.suffix == WORD_MNEM_SUFFIX)
8800 bigdisp.bitfield.disp16 = 1;
8803 bigdisp.bitfield.disp32 = 1;
8804 bigdisp.bitfield.disp32s = 1;
8810 override = (i.suffix == (flag_code != CODE_16BIT
8812 : LONG_MNEM_SUFFIX));
8813 bigdisp.bitfield.disp32 = 1;
8814 if ((flag_code == CODE_16BIT) ^ override)
8816 bigdisp.bitfield.disp32 = 0;
8817 bigdisp.bitfield.disp16 = 1;
8821 i.types[this_operand] = operand_type_or (i.types[this_operand],
8824 exp = &disp_expressions[i.disp_operands];
8825 i.op[this_operand].disps = exp;
8827 save_input_line_pointer = input_line_pointer;
8828 input_line_pointer = disp_start;
8829 END_STRING_AND_SAVE (disp_end);
8831 #ifndef GCC_ASM_O_HACK
8832 #define GCC_ASM_O_HACK 0
8835 END_STRING_AND_SAVE (disp_end + 1);
8836 if (i.types[this_operand].bitfield.baseIndex
8837 && displacement_string_end[-1] == '+')
8839 /* This hack is to avoid a warning when using the "o"
8840 constraint within gcc asm statements.
8843 #define _set_tssldt_desc(n,addr,limit,type) \
8844 __asm__ __volatile__ ( \
8846 "movw %w1,2+%0\n\t" \
8848 "movb %b1,4+%0\n\t" \
8849 "movb %4,5+%0\n\t" \
8850 "movb $0,6+%0\n\t" \
8851 "movb %h1,7+%0\n\t" \
8853 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8855 This works great except that the output assembler ends
8856 up looking a bit weird if it turns out that there is
8857 no offset. You end up producing code that looks like:
8870 So here we provide the missing zero. */
8872 *displacement_string_end = '0';
8875 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8876 if (gotfree_input_line)
8877 input_line_pointer = gotfree_input_line;
8879 exp_seg = expression (exp);
8882 if (*input_line_pointer)
8883 as_bad (_("junk `%s' after expression"), input_line_pointer);
8885 RESTORE_END_STRING (disp_end + 1);
8887 input_line_pointer = save_input_line_pointer;
8888 if (gotfree_input_line)
8890 free (gotfree_input_line);
8892 if (exp->X_op == O_constant || exp->X_op == O_register)
8893 exp->X_op = O_illegal;
8896 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8898 RESTORE_END_STRING (disp_end);
8904 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8905 i386_operand_type types, const char *disp_start)
8907 i386_operand_type bigdisp;
8910 /* We do this to make sure that the section symbol is in
8911 the symbol table. We will ultimately change the relocation
8912 to be relative to the beginning of the section. */
8913 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8914 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8915 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8917 if (exp->X_op != O_symbol)
8920 if (S_IS_LOCAL (exp->X_add_symbol)
8921 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8922 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8923 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8924 exp->X_op = O_subtract;
8925 exp->X_op_symbol = GOT_symbol;
8926 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8927 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8928 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8929 i.reloc[this_operand] = BFD_RELOC_64;
8931 i.reloc[this_operand] = BFD_RELOC_32;
8934 else if (exp->X_op == O_absent
8935 || exp->X_op == O_illegal
8936 || exp->X_op == O_big)
8939 as_bad (_("missing or invalid displacement expression `%s'"),
8944 else if (flag_code == CODE_64BIT
8945 && !i.prefix[ADDR_PREFIX]
8946 && exp->X_op == O_constant)
8948 /* Since displacement is signed extended to 64bit, don't allow
8949 disp32 and turn off disp32s if they are out of range. */
8950 i.types[this_operand].bitfield.disp32 = 0;
8951 if (!fits_in_signed_long (exp->X_add_number))
8953 i.types[this_operand].bitfield.disp32s = 0;
8954 if (i.types[this_operand].bitfield.baseindex)
8956 as_bad (_("0x%lx out range of signed 32bit displacement"),
8957 (long) exp->X_add_number);
8963 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8964 else if (exp->X_op != O_constant
8965 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8966 && exp_seg != absolute_section
8967 && exp_seg != text_section
8968 && exp_seg != data_section
8969 && exp_seg != bss_section
8970 && exp_seg != undefined_section
8971 && !bfd_is_com_section (exp_seg))
8973 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8978 /* Check if this is a displacement only operand. */
8979 bigdisp = i.types[this_operand];
8980 bigdisp.bitfield.disp8 = 0;
8981 bigdisp.bitfield.disp16 = 0;
8982 bigdisp.bitfield.disp32 = 0;
8983 bigdisp.bitfield.disp32s = 0;
8984 bigdisp.bitfield.disp64 = 0;
8985 if (operand_type_all_zero (&bigdisp))
8986 i.types[this_operand] = operand_type_and (i.types[this_operand],
8992 /* Return the active addressing mode, taking address override and
8993 registers forming the address into consideration. Update the
8994 address override prefix if necessary. */
8996 static enum flag_code
8997 i386_addressing_mode (void)
8999 enum flag_code addr_mode;
9001 if (i.prefix[ADDR_PREFIX])
9002 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9005 addr_mode = flag_code;
9007 #if INFER_ADDR_PREFIX
9008 if (i.mem_operands == 0)
9010 /* Infer address prefix from the first memory operand. */
9011 const reg_entry *addr_reg = i.base_reg;
9013 if (addr_reg == NULL)
9014 addr_reg = i.index_reg;
9018 if (addr_reg->reg_num == RegEip
9019 || addr_reg->reg_num == RegEiz
9020 || addr_reg->reg_type.bitfield.dword)
9021 addr_mode = CODE_32BIT;
9022 else if (flag_code != CODE_64BIT
9023 && addr_reg->reg_type.bitfield.word)
9024 addr_mode = CODE_16BIT;
9026 if (addr_mode != flag_code)
9028 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9030 /* Change the size of any displacement too. At most one
9031 of Disp16 or Disp32 is set.
9032 FIXME. There doesn't seem to be any real need for
9033 separate Disp16 and Disp32 flags. The same goes for
9034 Imm16 and Imm32. Removing them would probably clean
9035 up the code quite a lot. */
9036 if (flag_code != CODE_64BIT
9037 && (i.types[this_operand].bitfield.disp16
9038 || i.types[this_operand].bitfield.disp32))
9039 i.types[this_operand]
9040 = operand_type_xor (i.types[this_operand], disp16_32);
9050 /* Make sure the memory operand we've been dealt is valid.
9051 Return 1 on success, 0 on a failure. */
9054 i386_index_check (const char *operand_string)
9056 const char *kind = "base/index";
9057 enum flag_code addr_mode = i386_addressing_mode ();
9059 if (current_templates->start->opcode_modifier.isstring
9060 && !current_templates->start->opcode_modifier.immext
9061 && (current_templates->end[-1].opcode_modifier.isstring
9064 /* Memory operands of string insns are special in that they only allow
9065 a single register (rDI, rSI, or rBX) as their memory address. */
9066 const reg_entry *expected_reg;
9067 static const char *di_si[][2] =
9073 static const char *bx[] = { "ebx", "bx", "rbx" };
9075 kind = "string address";
9077 if (current_templates->start->opcode_modifier.repprefixok)
9079 i386_operand_type type = current_templates->end[-1].operand_types[0];
9081 if (!type.bitfield.baseindex
9082 || ((!i.mem_operands != !intel_syntax)
9083 && current_templates->end[-1].operand_types[1]
9084 .bitfield.baseindex))
9085 type = current_templates->end[-1].operand_types[1];
9086 expected_reg = hash_find (reg_hash,
9087 di_si[addr_mode][type.bitfield.esseg]);
9091 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9093 if (i.base_reg != expected_reg
9095 || operand_type_check (i.types[this_operand], disp))
9097 /* The second memory operand must have the same size as
9101 && !((addr_mode == CODE_64BIT
9102 && i.base_reg->reg_type.bitfield.qword)
9103 || (addr_mode == CODE_32BIT
9104 ? i.base_reg->reg_type.bitfield.dword
9105 : i.base_reg->reg_type.bitfield.word)))
9108 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9110 intel_syntax ? '[' : '(',
9112 expected_reg->reg_name,
9113 intel_syntax ? ']' : ')');
9120 as_bad (_("`%s' is not a valid %s expression"),
9121 operand_string, kind);
9126 if (addr_mode != CODE_16BIT)
9128 /* 32-bit/64-bit checks. */
9130 && (addr_mode == CODE_64BIT
9131 ? !i.base_reg->reg_type.bitfield.qword
9132 : !i.base_reg->reg_type.bitfield.dword)
9134 || (i.base_reg->reg_num
9135 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9137 && !i.index_reg->reg_type.bitfield.xmmword
9138 && !i.index_reg->reg_type.bitfield.ymmword
9139 && !i.index_reg->reg_type.bitfield.zmmword
9140 && ((addr_mode == CODE_64BIT
9141 ? !(i.index_reg->reg_type.bitfield.qword
9142 || i.index_reg->reg_num == RegRiz)
9143 : !(i.index_reg->reg_type.bitfield.dword
9144 || i.index_reg->reg_num == RegEiz))
9145 || !i.index_reg->reg_type.bitfield.baseindex)))
9148 /* bndmk, bndldx, and bndstx have special restrictions. */
9149 if (current_templates->start->base_opcode == 0xf30f1b
9150 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9152 /* They cannot use RIP-relative addressing. */
9153 if (i.base_reg && i.base_reg->reg_num == RegRip)
9155 as_bad (_("`%s' cannot be used here"), operand_string);
9159 /* bndldx and bndstx ignore their scale factor. */
9160 if (current_templates->start->base_opcode != 0xf30f1b
9161 && i.log2_scale_factor)
9162 as_warn (_("register scaling is being ignored here"));
9167 /* 16-bit checks. */
9169 && (!i.base_reg->reg_type.bitfield.word
9170 || !i.base_reg->reg_type.bitfield.baseindex))
9172 && (!i.index_reg->reg_type.bitfield.word
9173 || !i.index_reg->reg_type.bitfield.baseindex
9175 && i.base_reg->reg_num < 6
9176 && i.index_reg->reg_num >= 6
9177 && i.log2_scale_factor == 0))))
9184 /* Handle vector immediates. */
9187 RC_SAE_immediate (const char *imm_start)
9189 unsigned int match_found, j;
9190 const char *pstr = imm_start;
9198 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9200 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9204 rc_op.type = RC_NamesTable[j].type;
9205 rc_op.operand = this_operand;
9206 i.rounding = &rc_op;
9210 as_bad (_("duplicated `%s'"), imm_start);
9213 pstr += RC_NamesTable[j].len;
9223 as_bad (_("Missing '}': '%s'"), imm_start);
9226 /* RC/SAE immediate string should contain nothing more. */;
9229 as_bad (_("Junk after '}': '%s'"), imm_start);
9233 exp = &im_expressions[i.imm_operands++];
9234 i.op[this_operand].imms = exp;
9236 exp->X_op = O_constant;
9237 exp->X_add_number = 0;
9238 exp->X_add_symbol = (symbolS *) 0;
9239 exp->X_op_symbol = (symbolS *) 0;
9241 i.types[this_operand].bitfield.imm8 = 1;
9245 /* Only string instructions can have a second memory operand, so
9246 reduce current_templates to just those if it contains any. */
9248 maybe_adjust_templates (void)
9250 const insn_template *t;
9252 gas_assert (i.mem_operands == 1);
9254 for (t = current_templates->start; t < current_templates->end; ++t)
9255 if (t->opcode_modifier.isstring)
9258 if (t < current_templates->end)
9260 static templates aux_templates;
9261 bfd_boolean recheck;
9263 aux_templates.start = t;
9264 for (; t < current_templates->end; ++t)
9265 if (!t->opcode_modifier.isstring)
9267 aux_templates.end = t;
9269 /* Determine whether to re-check the first memory operand. */
9270 recheck = (aux_templates.start != current_templates->start
9271 || t != current_templates->end);
9273 current_templates = &aux_templates;
9278 if (i.memop1_string != NULL
9279 && i386_index_check (i.memop1_string) == 0)
9288 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9292 i386_att_operand (char *operand_string)
9296 char *op_string = operand_string;
9298 if (is_space_char (*op_string))
9301 /* We check for an absolute prefix (differentiating,
9302 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9303 if (*op_string == ABSOLUTE_PREFIX)
9306 if (is_space_char (*op_string))
9308 i.types[this_operand].bitfield.jumpabsolute = 1;
9311 /* Check if operand is a register. */
9312 if ((r = parse_register (op_string, &end_op)) != NULL)
9314 i386_operand_type temp;
9316 /* Check for a segment override by searching for ':' after a
9317 segment register. */
9319 if (is_space_char (*op_string))
9321 if (*op_string == ':'
9322 && (r->reg_type.bitfield.sreg2
9323 || r->reg_type.bitfield.sreg3))
9328 i.seg[i.mem_operands] = &es;
9331 i.seg[i.mem_operands] = &cs;
9334 i.seg[i.mem_operands] = &ss;
9337 i.seg[i.mem_operands] = &ds;
9340 i.seg[i.mem_operands] = &fs;
9343 i.seg[i.mem_operands] = &gs;
9347 /* Skip the ':' and whitespace. */
9349 if (is_space_char (*op_string))
9352 if (!is_digit_char (*op_string)
9353 && !is_identifier_char (*op_string)
9354 && *op_string != '('
9355 && *op_string != ABSOLUTE_PREFIX)
9357 as_bad (_("bad memory operand `%s'"), op_string);
9360 /* Handle case of %es:*foo. */
9361 if (*op_string == ABSOLUTE_PREFIX)
9364 if (is_space_char (*op_string))
9366 i.types[this_operand].bitfield.jumpabsolute = 1;
9368 goto do_memory_reference;
9371 /* Handle vector operations. */
9372 if (*op_string == '{')
9374 op_string = check_VecOperations (op_string, NULL);
9375 if (op_string == NULL)
9381 as_bad (_("junk `%s' after register"), op_string);
9385 temp.bitfield.baseindex = 0;
9386 i.types[this_operand] = operand_type_or (i.types[this_operand],
9388 i.types[this_operand].bitfield.unspecified = 0;
9389 i.op[this_operand].regs = r;
9392 else if (*op_string == REGISTER_PREFIX)
9394 as_bad (_("bad register name `%s'"), op_string);
9397 else if (*op_string == IMMEDIATE_PREFIX)
9400 if (i.types[this_operand].bitfield.jumpabsolute)
9402 as_bad (_("immediate operand illegal with absolute jump"));
9405 if (!i386_immediate (op_string))
9408 else if (RC_SAE_immediate (operand_string))
9410 /* If it is a RC or SAE immediate, do nothing. */
9413 else if (is_digit_char (*op_string)
9414 || is_identifier_char (*op_string)
9415 || *op_string == '"'
9416 || *op_string == '(')
9418 /* This is a memory reference of some sort. */
9421 /* Start and end of displacement string expression (if found). */
9422 char *displacement_string_start;
9423 char *displacement_string_end;
9426 do_memory_reference:
9427 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9429 if ((i.mem_operands == 1
9430 && !current_templates->start->opcode_modifier.isstring)
9431 || i.mem_operands == 2)
9433 as_bad (_("too many memory references for `%s'"),
9434 current_templates->start->name);
9438 /* Check for base index form. We detect the base index form by
9439 looking for an ')' at the end of the operand, searching
9440 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9442 base_string = op_string + strlen (op_string);
9444 /* Handle vector operations. */
9445 vop_start = strchr (op_string, '{');
9446 if (vop_start && vop_start < base_string)
9448 if (check_VecOperations (vop_start, base_string) == NULL)
9450 base_string = vop_start;
9454 if (is_space_char (*base_string))
9457 /* If we only have a displacement, set-up for it to be parsed later. */
9458 displacement_string_start = op_string;
9459 displacement_string_end = base_string + 1;
9461 if (*base_string == ')')
9464 unsigned int parens_balanced = 1;
9465 /* We've already checked that the number of left & right ()'s are
9466 equal, so this loop will not be infinite. */
9470 if (*base_string == ')')
9472 if (*base_string == '(')
9475 while (parens_balanced);
9477 temp_string = base_string;
9479 /* Skip past '(' and whitespace. */
9481 if (is_space_char (*base_string))
9484 if (*base_string == ','
9485 || ((i.base_reg = parse_register (base_string, &end_op))
9488 displacement_string_end = temp_string;
9490 i.types[this_operand].bitfield.baseindex = 1;
9494 base_string = end_op;
9495 if (is_space_char (*base_string))
9499 /* There may be an index reg or scale factor here. */
9500 if (*base_string == ',')
9503 if (is_space_char (*base_string))
9506 if ((i.index_reg = parse_register (base_string, &end_op))
9509 base_string = end_op;
9510 if (is_space_char (*base_string))
9512 if (*base_string == ',')
9515 if (is_space_char (*base_string))
9518 else if (*base_string != ')')
9520 as_bad (_("expecting `,' or `)' "
9521 "after index register in `%s'"),
9526 else if (*base_string == REGISTER_PREFIX)
9528 end_op = strchr (base_string, ',');
9531 as_bad (_("bad register name `%s'"), base_string);
9535 /* Check for scale factor. */
9536 if (*base_string != ')')
9538 char *end_scale = i386_scale (base_string);
9543 base_string = end_scale;
9544 if (is_space_char (*base_string))
9546 if (*base_string != ')')
9548 as_bad (_("expecting `)' "
9549 "after scale factor in `%s'"),
9554 else if (!i.index_reg)
9556 as_bad (_("expecting index register or scale factor "
9557 "after `,'; got '%c'"),
9562 else if (*base_string != ')')
9564 as_bad (_("expecting `,' or `)' "
9565 "after base register in `%s'"),
9570 else if (*base_string == REGISTER_PREFIX)
9572 end_op = strchr (base_string, ',');
9575 as_bad (_("bad register name `%s'"), base_string);
9580 /* If there's an expression beginning the operand, parse it,
9581 assuming displacement_string_start and
9582 displacement_string_end are meaningful. */
9583 if (displacement_string_start != displacement_string_end)
9585 if (!i386_displacement (displacement_string_start,
9586 displacement_string_end))
9590 /* Special case for (%dx) while doing input/output op. */
9592 && operand_type_equal (&i.base_reg->reg_type,
9593 ®16_inoutportreg)
9595 && i.log2_scale_factor == 0
9596 && i.seg[i.mem_operands] == 0
9597 && !operand_type_check (i.types[this_operand], disp))
9599 i.types[this_operand] = inoutportreg;
9603 if (i386_index_check (operand_string) == 0)
9605 i.types[this_operand].bitfield.mem = 1;
9606 if (i.mem_operands == 0)
9607 i.memop1_string = xstrdup (operand_string);
9612 /* It's not a memory operand; argh! */
9613 as_bad (_("invalid char %s beginning operand %d `%s'"),
9614 output_invalid (*op_string),
9619 return 1; /* Normal return. */
9622 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9623 that an rs_machine_dependent frag may reach. */
9626 i386_frag_max_var (fragS *frag)
9628 /* The only relaxable frags are for jumps.
9629 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9630 gas_assert (frag->fr_type == rs_machine_dependent);
9631 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9634 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9636 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9638 /* STT_GNU_IFUNC symbol must go through PLT. */
9639 if ((symbol_get_bfdsym (fr_symbol)->flags
9640 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9643 if (!S_IS_EXTERNAL (fr_symbol))
9644 /* Symbol may be weak or local. */
9645 return !S_IS_WEAK (fr_symbol);
9647 /* Global symbols with non-default visibility can't be preempted. */
9648 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9651 if (fr_var != NO_RELOC)
9652 switch ((enum bfd_reloc_code_real) fr_var)
9654 case BFD_RELOC_386_PLT32:
9655 case BFD_RELOC_X86_64_PLT32:
9656 /* Symbol with PLT relocation may be preempted. */
9662 /* Global symbols with default visibility in a shared library may be
9663 preempted by another definition. */
9668 /* md_estimate_size_before_relax()
9670 Called just before relax() for rs_machine_dependent frags. The x86
9671 assembler uses these frags to handle variable size jump
9674 Any symbol that is now undefined will not become defined.
9675 Return the correct fr_subtype in the frag.
9676 Return the initial "guess for variable size of frag" to caller.
9677 The guess is actually the growth beyond the fixed part. Whatever
9678 we do to grow the fixed or variable part contributes to our
9682 md_estimate_size_before_relax (fragS *fragP, segT segment)
9684 /* We've already got fragP->fr_subtype right; all we have to do is
9685 check for un-relaxable symbols. On an ELF system, we can't relax
9686 an externally visible symbol, because it may be overridden by a
9688 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9691 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9694 #if defined (OBJ_COFF) && defined (TE_PE)
9695 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9696 && S_IS_WEAK (fragP->fr_symbol))
9700 /* Symbol is undefined in this segment, or we need to keep a
9701 reloc so that weak symbols can be overridden. */
9702 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9703 enum bfd_reloc_code_real reloc_type;
9704 unsigned char *opcode;
9707 if (fragP->fr_var != NO_RELOC)
9708 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9710 reloc_type = BFD_RELOC_16_PCREL;
9711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9712 else if (need_plt32_p (fragP->fr_symbol))
9713 reloc_type = BFD_RELOC_X86_64_PLT32;
9716 reloc_type = BFD_RELOC_32_PCREL;
9718 old_fr_fix = fragP->fr_fix;
9719 opcode = (unsigned char *) fragP->fr_opcode;
9721 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9724 /* Make jmp (0xeb) a (d)word displacement jump. */
9726 fragP->fr_fix += size;
9727 fix_new (fragP, old_fr_fix, size,
9729 fragP->fr_offset, 1,
9735 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9737 /* Negate the condition, and branch past an
9738 unconditional jump. */
9741 /* Insert an unconditional jump. */
9743 /* We added two extra opcode bytes, and have a two byte
9745 fragP->fr_fix += 2 + 2;
9746 fix_new (fragP, old_fr_fix + 2, 2,
9748 fragP->fr_offset, 1,
9755 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9760 fixP = fix_new (fragP, old_fr_fix, 1,
9762 fragP->fr_offset, 1,
9764 fixP->fx_signed = 1;
9768 /* This changes the byte-displacement jump 0x7N
9769 to the (d)word-displacement jump 0x0f,0x8N. */
9770 opcode[1] = opcode[0] + 0x10;
9771 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9772 /* We've added an opcode byte. */
9773 fragP->fr_fix += 1 + size;
9774 fix_new (fragP, old_fr_fix + 1, size,
9776 fragP->fr_offset, 1,
9781 BAD_CASE (fragP->fr_subtype);
9785 return fragP->fr_fix - old_fr_fix;
9788 /* Guess size depending on current relax state. Initially the relax
9789 state will correspond to a short jump and we return 1, because
9790 the variable part of the frag (the branch offset) is one byte
9791 long. However, we can relax a section more than once and in that
9792 case we must either set fr_subtype back to the unrelaxed state,
9793 or return the value for the appropriate branch. */
9794 return md_relax_table[fragP->fr_subtype].rlx_length;
9797 /* Called after relax() is finished.
9799 In: Address of frag.
9800 fr_type == rs_machine_dependent.
9801 fr_subtype is what the address relaxed to.
9803 Out: Any fixSs and constants are set up.
9804 Caller will turn frag into a ".space 0". */
9807 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9810 unsigned char *opcode;
9811 unsigned char *where_to_put_displacement = NULL;
9812 offsetT target_address;
9813 offsetT opcode_address;
9814 unsigned int extension = 0;
9815 offsetT displacement_from_opcode_start;
9817 opcode = (unsigned char *) fragP->fr_opcode;
9819 /* Address we want to reach in file space. */
9820 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9822 /* Address opcode resides at in file space. */
9823 opcode_address = fragP->fr_address + fragP->fr_fix;
9825 /* Displacement from opcode start to fill into instruction. */
9826 displacement_from_opcode_start = target_address - opcode_address;
9828 if ((fragP->fr_subtype & BIG) == 0)
9830 /* Don't have to change opcode. */
9831 extension = 1; /* 1 opcode + 1 displacement */
9832 where_to_put_displacement = &opcode[1];
9836 if (no_cond_jump_promotion
9837 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9838 as_warn_where (fragP->fr_file, fragP->fr_line,
9839 _("long jump required"));
9841 switch (fragP->fr_subtype)
9843 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9844 extension = 4; /* 1 opcode + 4 displacement */
9846 where_to_put_displacement = &opcode[1];
9849 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9850 extension = 2; /* 1 opcode + 2 displacement */
9852 where_to_put_displacement = &opcode[1];
9855 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9856 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9857 extension = 5; /* 2 opcode + 4 displacement */
9858 opcode[1] = opcode[0] + 0x10;
9859 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9860 where_to_put_displacement = &opcode[2];
9863 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9864 extension = 3; /* 2 opcode + 2 displacement */
9865 opcode[1] = opcode[0] + 0x10;
9866 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9867 where_to_put_displacement = &opcode[2];
9870 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9875 where_to_put_displacement = &opcode[3];
9879 BAD_CASE (fragP->fr_subtype);
9884 /* If size if less then four we are sure that the operand fits,
9885 but if it's 4, then it could be that the displacement is larger
9887 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9889 && ((addressT) (displacement_from_opcode_start - extension
9890 + ((addressT) 1 << 31))
9891 > (((addressT) 2 << 31) - 1)))
9893 as_bad_where (fragP->fr_file, fragP->fr_line,
9894 _("jump target out of range"));
9895 /* Make us emit 0. */
9896 displacement_from_opcode_start = extension;
9898 /* Now put displacement after opcode. */
9899 md_number_to_chars ((char *) where_to_put_displacement,
9900 (valueT) (displacement_from_opcode_start - extension),
9901 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9902 fragP->fr_fix += extension;
9905 /* Apply a fixup (fixP) to segment data, once it has been determined
9906 by our caller that we have all the info we need to fix it up.
9908 Parameter valP is the pointer to the value of the bits.
9910 On the 386, immediates, displacements, and data pointers are all in
9911 the same (little-endian) format, so we don't need to care about which
9915 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9917 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9918 valueT value = *valP;
9920 #if !defined (TE_Mach)
9923 switch (fixP->fx_r_type)
9929 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9932 case BFD_RELOC_X86_64_32S:
9933 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9936 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9939 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9944 if (fixP->fx_addsy != NULL
9945 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9946 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9947 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9948 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9949 && !use_rela_relocations)
9951 /* This is a hack. There should be a better way to handle this.
9952 This covers for the fact that bfd_install_relocation will
9953 subtract the current location (for partial_inplace, PC relative
9954 relocations); see more below. */
9958 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9961 value += fixP->fx_where + fixP->fx_frag->fr_address;
9963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9966 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9969 || (symbol_section_p (fixP->fx_addsy)
9970 && sym_seg != absolute_section))
9971 && !generic_force_reloc (fixP))
9973 /* Yes, we add the values in twice. This is because
9974 bfd_install_relocation subtracts them out again. I think
9975 bfd_install_relocation is broken, but I don't dare change
9977 value += fixP->fx_where + fixP->fx_frag->fr_address;
9981 #if defined (OBJ_COFF) && defined (TE_PE)
9982 /* For some reason, the PE format does not store a
9983 section address offset for a PC relative symbol. */
9984 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9985 || S_IS_WEAK (fixP->fx_addsy))
9986 value += md_pcrel_from (fixP);
9989 #if defined (OBJ_COFF) && defined (TE_PE)
9990 if (fixP->fx_addsy != NULL
9991 && S_IS_WEAK (fixP->fx_addsy)
9992 /* PR 16858: Do not modify weak function references. */
9993 && ! fixP->fx_pcrel)
9995 #if !defined (TE_PEP)
9996 /* For x86 PE weak function symbols are neither PC-relative
9997 nor do they set S_IS_FUNCTION. So the only reliable way
9998 to detect them is to check the flags of their containing
10000 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10001 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10005 value -= S_GET_VALUE (fixP->fx_addsy);
10009 /* Fix a few things - the dynamic linker expects certain values here,
10010 and we must not disappoint it. */
10011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10012 if (IS_ELF && fixP->fx_addsy)
10013 switch (fixP->fx_r_type)
10015 case BFD_RELOC_386_PLT32:
10016 case BFD_RELOC_X86_64_PLT32:
10017 /* Make the jump instruction point to the address of the operand. At
10018 runtime we merely add the offset to the actual PLT entry. */
10022 case BFD_RELOC_386_TLS_GD:
10023 case BFD_RELOC_386_TLS_LDM:
10024 case BFD_RELOC_386_TLS_IE_32:
10025 case BFD_RELOC_386_TLS_IE:
10026 case BFD_RELOC_386_TLS_GOTIE:
10027 case BFD_RELOC_386_TLS_GOTDESC:
10028 case BFD_RELOC_X86_64_TLSGD:
10029 case BFD_RELOC_X86_64_TLSLD:
10030 case BFD_RELOC_X86_64_GOTTPOFF:
10031 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10032 value = 0; /* Fully resolved at runtime. No addend. */
10034 case BFD_RELOC_386_TLS_LE:
10035 case BFD_RELOC_386_TLS_LDO_32:
10036 case BFD_RELOC_386_TLS_LE_32:
10037 case BFD_RELOC_X86_64_DTPOFF32:
10038 case BFD_RELOC_X86_64_DTPOFF64:
10039 case BFD_RELOC_X86_64_TPOFF32:
10040 case BFD_RELOC_X86_64_TPOFF64:
10041 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10044 case BFD_RELOC_386_TLS_DESC_CALL:
10045 case BFD_RELOC_X86_64_TLSDESC_CALL:
10046 value = 0; /* Fully resolved at runtime. No addend. */
10047 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10051 case BFD_RELOC_VTABLE_INHERIT:
10052 case BFD_RELOC_VTABLE_ENTRY:
10059 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10061 #endif /* !defined (TE_Mach) */
10063 /* Are we finished with this relocation now? */
10064 if (fixP->fx_addsy == NULL)
10066 #if defined (OBJ_COFF) && defined (TE_PE)
10067 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10070 /* Remember value for tc_gen_reloc. */
10071 fixP->fx_addnumber = value;
10072 /* Clear out the frag for now. */
10076 else if (use_rela_relocations)
10078 fixP->fx_no_overflow = 1;
10079 /* Remember value for tc_gen_reloc. */
10080 fixP->fx_addnumber = value;
10084 md_number_to_chars (p, value, fixP->fx_size);
10088 md_atof (int type, char *litP, int *sizeP)
10090 /* This outputs the LITTLENUMs in REVERSE order;
10091 in accord with the bigendian 386. */
10092 return ieee_md_atof (type, litP, sizeP, FALSE);
10095 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10098 output_invalid (int c)
10101 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10104 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10105 "(0x%x)", (unsigned char) c);
10106 return output_invalid_buf;
10109 /* REG_STRING starts *before* REGISTER_PREFIX. */
10111 static const reg_entry *
10112 parse_real_register (char *reg_string, char **end_op)
10114 char *s = reg_string;
10116 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10117 const reg_entry *r;
10119 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10120 if (*s == REGISTER_PREFIX)
10123 if (is_space_char (*s))
10126 p = reg_name_given;
10127 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10129 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10130 return (const reg_entry *) NULL;
10134 /* For naked regs, make sure that we are not dealing with an identifier.
10135 This prevents confusing an identifier like `eax_var' with register
10137 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10138 return (const reg_entry *) NULL;
10142 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10144 /* Handle floating point regs, allowing spaces in the (i) part. */
10145 if (r == i386_regtab /* %st is first entry of table */)
10147 if (is_space_char (*s))
10152 if (is_space_char (*s))
10154 if (*s >= '0' && *s <= '7')
10156 int fpr = *s - '0';
10158 if (is_space_char (*s))
10163 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10168 /* We have "%st(" then garbage. */
10169 return (const reg_entry *) NULL;
10173 if (r == NULL || allow_pseudo_reg)
10176 if (operand_type_all_zero (&r->reg_type))
10177 return (const reg_entry *) NULL;
10179 if ((r->reg_type.bitfield.dword
10180 || r->reg_type.bitfield.sreg3
10181 || r->reg_type.bitfield.control
10182 || r->reg_type.bitfield.debug
10183 || r->reg_type.bitfield.test)
10184 && !cpu_arch_flags.bitfield.cpui386)
10185 return (const reg_entry *) NULL;
10187 if (r->reg_type.bitfield.tbyte
10188 && !cpu_arch_flags.bitfield.cpu8087
10189 && !cpu_arch_flags.bitfield.cpu287
10190 && !cpu_arch_flags.bitfield.cpu387)
10191 return (const reg_entry *) NULL;
10193 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10194 return (const reg_entry *) NULL;
10196 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10197 return (const reg_entry *) NULL;
10199 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10200 return (const reg_entry *) NULL;
10202 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10203 return (const reg_entry *) NULL;
10205 if (r->reg_type.bitfield.regmask
10206 && !cpu_arch_flags.bitfield.cpuregmask)
10207 return (const reg_entry *) NULL;
10209 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10210 if (!allow_index_reg
10211 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10212 return (const reg_entry *) NULL;
10214 /* Upper 16 vector register is only available with VREX in 64bit
10216 if ((r->reg_flags & RegVRex))
10218 if (i.vec_encoding == vex_encoding_default)
10219 i.vec_encoding = vex_encoding_evex;
10221 if (!cpu_arch_flags.bitfield.cpuvrex
10222 || i.vec_encoding != vex_encoding_evex
10223 || flag_code != CODE_64BIT)
10224 return (const reg_entry *) NULL;
10227 if (((r->reg_flags & (RegRex64 | RegRex))
10228 || r->reg_type.bitfield.qword)
10229 && (!cpu_arch_flags.bitfield.cpulm
10230 || !operand_type_equal (&r->reg_type, &control))
10231 && flag_code != CODE_64BIT)
10232 return (const reg_entry *) NULL;
10234 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10235 return (const reg_entry *) NULL;
10240 /* REG_STRING starts *before* REGISTER_PREFIX. */
10242 static const reg_entry *
10243 parse_register (char *reg_string, char **end_op)
10245 const reg_entry *r;
10247 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10248 r = parse_real_register (reg_string, end_op);
10253 char *save = input_line_pointer;
10257 input_line_pointer = reg_string;
10258 c = get_symbol_name (®_string);
10259 symbolP = symbol_find (reg_string);
10260 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10262 const expressionS *e = symbol_get_value_expression (symbolP);
10264 know (e->X_op == O_register);
10265 know (e->X_add_number >= 0
10266 && (valueT) e->X_add_number < i386_regtab_size);
10267 r = i386_regtab + e->X_add_number;
10268 if ((r->reg_flags & RegVRex))
10269 i.vec_encoding = vex_encoding_evex;
10270 *end_op = input_line_pointer;
10272 *input_line_pointer = c;
10273 input_line_pointer = save;
10279 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10281 const reg_entry *r;
10282 char *end = input_line_pointer;
10285 r = parse_register (name, &input_line_pointer);
10286 if (r && end <= input_line_pointer)
10288 *nextcharP = *input_line_pointer;
10289 *input_line_pointer = 0;
10290 e->X_op = O_register;
10291 e->X_add_number = r - i386_regtab;
10294 input_line_pointer = end;
10296 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10300 md_operand (expressionS *e)
10303 const reg_entry *r;
10305 switch (*input_line_pointer)
10307 case REGISTER_PREFIX:
10308 r = parse_real_register (input_line_pointer, &end);
10311 e->X_op = O_register;
10312 e->X_add_number = r - i386_regtab;
10313 input_line_pointer = end;
10318 gas_assert (intel_syntax);
10319 end = input_line_pointer++;
10321 if (*input_line_pointer == ']')
10323 ++input_line_pointer;
10324 e->X_op_symbol = make_expr_symbol (e);
10325 e->X_add_symbol = NULL;
10326 e->X_add_number = 0;
10331 e->X_op = O_absent;
10332 input_line_pointer = end;
10339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10340 const char *md_shortopts = "kVQ:sqnO::";
10342 const char *md_shortopts = "qnO::";
10345 #define OPTION_32 (OPTION_MD_BASE + 0)
10346 #define OPTION_64 (OPTION_MD_BASE + 1)
10347 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10348 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10349 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10350 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10351 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10352 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10353 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10354 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10355 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10356 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10357 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10358 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10359 #define OPTION_X32 (OPTION_MD_BASE + 14)
10360 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10361 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10362 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10363 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10364 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10365 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10366 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10367 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10368 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10369 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10371 struct option md_longopts[] =
10373 {"32", no_argument, NULL, OPTION_32},
10374 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10375 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10376 {"64", no_argument, NULL, OPTION_64},
10378 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10379 {"x32", no_argument, NULL, OPTION_X32},
10380 {"mshared", no_argument, NULL, OPTION_MSHARED},
10382 {"divide", no_argument, NULL, OPTION_DIVIDE},
10383 {"march", required_argument, NULL, OPTION_MARCH},
10384 {"mtune", required_argument, NULL, OPTION_MTUNE},
10385 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10386 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10387 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10388 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10389 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10390 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10391 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10392 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10393 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10394 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10395 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10396 # if defined (TE_PE) || defined (TE_PEP)
10397 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10399 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10400 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10401 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10402 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10403 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10404 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10405 {NULL, no_argument, NULL, 0}
10407 size_t md_longopts_size = sizeof (md_longopts);
10410 md_parse_option (int c, const char *arg)
10413 char *arch, *next, *saved;
10418 optimize_align_code = 0;
10422 quiet_warnings = 1;
10425 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10426 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10427 should be emitted or not. FIXME: Not implemented. */
10431 /* -V: SVR4 argument to print version ID. */
10433 print_version_id ();
10436 /* -k: Ignore for FreeBSD compatibility. */
10441 /* -s: On i386 Solaris, this tells the native assembler to use
10442 .stab instead of .stab.excl. We always use .stab anyhow. */
10445 case OPTION_MSHARED:
10449 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10450 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10453 const char **list, **l;
10455 list = bfd_target_list ();
10456 for (l = list; *l != NULL; l++)
10457 if (CONST_STRNEQ (*l, "elf64-x86-64")
10458 || strcmp (*l, "coff-x86-64") == 0
10459 || strcmp (*l, "pe-x86-64") == 0
10460 || strcmp (*l, "pei-x86-64") == 0
10461 || strcmp (*l, "mach-o-x86-64") == 0)
10463 default_arch = "x86_64";
10467 as_fatal (_("no compiled in support for x86_64"));
10473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10477 const char **list, **l;
10479 list = bfd_target_list ();
10480 for (l = list; *l != NULL; l++)
10481 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10483 default_arch = "x86_64:32";
10487 as_fatal (_("no compiled in support for 32bit x86_64"));
10491 as_fatal (_("32bit x86_64 is only supported for ELF"));
10496 default_arch = "i386";
10499 case OPTION_DIVIDE:
10500 #ifdef SVR4_COMMENT_CHARS
10505 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10507 for (s = i386_comment_chars; *s != '\0'; s++)
10511 i386_comment_chars = n;
10517 saved = xstrdup (arg);
10519 /* Allow -march=+nosse. */
10525 as_fatal (_("invalid -march= option: `%s'"), arg);
10526 next = strchr (arch, '+');
10529 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10531 if (strcmp (arch, cpu_arch [j].name) == 0)
10534 if (! cpu_arch[j].flags.bitfield.cpui386)
10537 cpu_arch_name = cpu_arch[j].name;
10538 cpu_sub_arch_name = NULL;
10539 cpu_arch_flags = cpu_arch[j].flags;
10540 cpu_arch_isa = cpu_arch[j].type;
10541 cpu_arch_isa_flags = cpu_arch[j].flags;
10542 if (!cpu_arch_tune_set)
10544 cpu_arch_tune = cpu_arch_isa;
10545 cpu_arch_tune_flags = cpu_arch_isa_flags;
10549 else if (*cpu_arch [j].name == '.'
10550 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10552 /* ISA extension. */
10553 i386_cpu_flags flags;
10555 flags = cpu_flags_or (cpu_arch_flags,
10556 cpu_arch[j].flags);
10558 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10560 if (cpu_sub_arch_name)
10562 char *name = cpu_sub_arch_name;
10563 cpu_sub_arch_name = concat (name,
10565 (const char *) NULL);
10569 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10570 cpu_arch_flags = flags;
10571 cpu_arch_isa_flags = flags;
10575 = cpu_flags_or (cpu_arch_isa_flags,
10576 cpu_arch[j].flags);
10581 if (j >= ARRAY_SIZE (cpu_arch))
10583 /* Disable an ISA extension. */
10584 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10585 if (strcmp (arch, cpu_noarch [j].name) == 0)
10587 i386_cpu_flags flags;
10589 flags = cpu_flags_and_not (cpu_arch_flags,
10590 cpu_noarch[j].flags);
10591 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10593 if (cpu_sub_arch_name)
10595 char *name = cpu_sub_arch_name;
10596 cpu_sub_arch_name = concat (arch,
10597 (const char *) NULL);
10601 cpu_sub_arch_name = xstrdup (arch);
10602 cpu_arch_flags = flags;
10603 cpu_arch_isa_flags = flags;
10608 if (j >= ARRAY_SIZE (cpu_noarch))
10609 j = ARRAY_SIZE (cpu_arch);
10612 if (j >= ARRAY_SIZE (cpu_arch))
10613 as_fatal (_("invalid -march= option: `%s'"), arg);
10617 while (next != NULL);
10623 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10624 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10626 if (strcmp (arg, cpu_arch [j].name) == 0)
10628 cpu_arch_tune_set = 1;
10629 cpu_arch_tune = cpu_arch [j].type;
10630 cpu_arch_tune_flags = cpu_arch[j].flags;
10634 if (j >= ARRAY_SIZE (cpu_arch))
10635 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10638 case OPTION_MMNEMONIC:
10639 if (strcasecmp (arg, "att") == 0)
10640 intel_mnemonic = 0;
10641 else if (strcasecmp (arg, "intel") == 0)
10642 intel_mnemonic = 1;
10644 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10647 case OPTION_MSYNTAX:
10648 if (strcasecmp (arg, "att") == 0)
10650 else if (strcasecmp (arg, "intel") == 0)
10653 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10656 case OPTION_MINDEX_REG:
10657 allow_index_reg = 1;
10660 case OPTION_MNAKED_REG:
10661 allow_naked_reg = 1;
10664 case OPTION_MSSE2AVX:
10668 case OPTION_MSSE_CHECK:
10669 if (strcasecmp (arg, "error") == 0)
10670 sse_check = check_error;
10671 else if (strcasecmp (arg, "warning") == 0)
10672 sse_check = check_warning;
10673 else if (strcasecmp (arg, "none") == 0)
10674 sse_check = check_none;
10676 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10679 case OPTION_MOPERAND_CHECK:
10680 if (strcasecmp (arg, "error") == 0)
10681 operand_check = check_error;
10682 else if (strcasecmp (arg, "warning") == 0)
10683 operand_check = check_warning;
10684 else if (strcasecmp (arg, "none") == 0)
10685 operand_check = check_none;
10687 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10690 case OPTION_MAVXSCALAR:
10691 if (strcasecmp (arg, "128") == 0)
10692 avxscalar = vex128;
10693 else if (strcasecmp (arg, "256") == 0)
10694 avxscalar = vex256;
10696 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10699 case OPTION_MADD_BND_PREFIX:
10700 add_bnd_prefix = 1;
10703 case OPTION_MEVEXLIG:
10704 if (strcmp (arg, "128") == 0)
10705 evexlig = evexl128;
10706 else if (strcmp (arg, "256") == 0)
10707 evexlig = evexl256;
10708 else if (strcmp (arg, "512") == 0)
10709 evexlig = evexl512;
10711 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10714 case OPTION_MEVEXRCIG:
10715 if (strcmp (arg, "rne") == 0)
10717 else if (strcmp (arg, "rd") == 0)
10719 else if (strcmp (arg, "ru") == 0)
10721 else if (strcmp (arg, "rz") == 0)
10724 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10727 case OPTION_MEVEXWIG:
10728 if (strcmp (arg, "0") == 0)
10730 else if (strcmp (arg, "1") == 0)
10733 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10736 # if defined (TE_PE) || defined (TE_PEP)
10737 case OPTION_MBIG_OBJ:
10742 case OPTION_MOMIT_LOCK_PREFIX:
10743 if (strcasecmp (arg, "yes") == 0)
10744 omit_lock_prefix = 1;
10745 else if (strcasecmp (arg, "no") == 0)
10746 omit_lock_prefix = 0;
10748 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10751 case OPTION_MFENCE_AS_LOCK_ADD:
10752 if (strcasecmp (arg, "yes") == 0)
10754 else if (strcasecmp (arg, "no") == 0)
10757 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10760 case OPTION_MRELAX_RELOCATIONS:
10761 if (strcasecmp (arg, "yes") == 0)
10762 generate_relax_relocations = 1;
10763 else if (strcasecmp (arg, "no") == 0)
10764 generate_relax_relocations = 0;
10766 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10769 case OPTION_MAMD64:
10773 case OPTION_MINTEL64:
10781 /* Turn off -Os. */
10782 optimize_for_space = 0;
10784 else if (*arg == 's')
10786 optimize_for_space = 1;
10787 /* Turn on all encoding optimizations. */
10792 optimize = atoi (arg);
10793 /* Turn off -Os. */
10794 optimize_for_space = 0;
10804 #define MESSAGE_TEMPLATE \
10808 output_message (FILE *stream, char *p, char *message, char *start,
10809 int *left_p, const char *name, int len)
10811 int size = sizeof (MESSAGE_TEMPLATE);
10812 int left = *left_p;
10814 /* Reserve 2 spaces for ", " or ",\0" */
10817 /* Check if there is any room. */
10825 p = mempcpy (p, name, len);
10829 /* Output the current message now and start a new one. */
10832 fprintf (stream, "%s\n", message);
10834 left = size - (start - message) - len - 2;
10836 gas_assert (left >= 0);
10838 p = mempcpy (p, name, len);
10846 show_arch (FILE *stream, int ext, int check)
10848 static char message[] = MESSAGE_TEMPLATE;
10849 char *start = message + 27;
10851 int size = sizeof (MESSAGE_TEMPLATE);
10858 left = size - (start - message);
10859 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10861 /* Should it be skipped? */
10862 if (cpu_arch [j].skip)
10865 name = cpu_arch [j].name;
10866 len = cpu_arch [j].len;
10869 /* It is an extension. Skip if we aren't asked to show it. */
10880 /* It is an processor. Skip if we show only extension. */
10883 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10885 /* It is an impossible processor - skip. */
10889 p = output_message (stream, p, message, start, &left, name, len);
10892 /* Display disabled extensions. */
10894 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10896 name = cpu_noarch [j].name;
10897 len = cpu_noarch [j].len;
10898 p = output_message (stream, p, message, start, &left, name,
10903 fprintf (stream, "%s\n", message);
10907 md_show_usage (FILE *stream)
10909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10910 fprintf (stream, _("\
10912 -V print assembler version number\n\
10915 fprintf (stream, _("\
10916 -n Do not optimize code alignment\n\
10917 -q quieten some warnings\n"));
10918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10919 fprintf (stream, _("\
10922 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10923 || defined (TE_PE) || defined (TE_PEP))
10924 fprintf (stream, _("\
10925 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10927 #ifdef SVR4_COMMENT_CHARS
10928 fprintf (stream, _("\
10929 --divide do not treat `/' as a comment character\n"));
10931 fprintf (stream, _("\
10932 --divide ignored\n"));
10934 fprintf (stream, _("\
10935 -march=CPU[,+EXTENSION...]\n\
10936 generate code for CPU and EXTENSION, CPU is one of:\n"));
10937 show_arch (stream, 0, 1);
10938 fprintf (stream, _("\
10939 EXTENSION is combination of:\n"));
10940 show_arch (stream, 1, 0);
10941 fprintf (stream, _("\
10942 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10943 show_arch (stream, 0, 0);
10944 fprintf (stream, _("\
10945 -msse2avx encode SSE instructions with VEX prefix\n"));
10946 fprintf (stream, _("\
10947 -msse-check=[none|error|warning]\n\
10948 check SSE instructions\n"));
10949 fprintf (stream, _("\
10950 -moperand-check=[none|error|warning]\n\
10951 check operand combinations for validity\n"));
10952 fprintf (stream, _("\
10953 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10955 fprintf (stream, _("\
10956 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10958 fprintf (stream, _("\
10959 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10960 for EVEX.W bit ignored instructions\n"));
10961 fprintf (stream, _("\
10962 -mevexrcig=[rne|rd|ru|rz]\n\
10963 encode EVEX instructions with specific EVEX.RC value\n\
10964 for SAE-only ignored instructions\n"));
10965 fprintf (stream, _("\
10966 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10967 fprintf (stream, _("\
10968 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10969 fprintf (stream, _("\
10970 -mindex-reg support pseudo index registers\n"));
10971 fprintf (stream, _("\
10972 -mnaked-reg don't require `%%' prefix for registers\n"));
10973 fprintf (stream, _("\
10974 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10975 fprintf (stream, _("\
10976 -mshared disable branch optimization for shared code\n"));
10977 # if defined (TE_PE) || defined (TE_PEP)
10978 fprintf (stream, _("\
10979 -mbig-obj generate big object files\n"));
10981 fprintf (stream, _("\
10982 -momit-lock-prefix=[no|yes]\n\
10983 strip all lock prefixes\n"));
10984 fprintf (stream, _("\
10985 -mfence-as-lock-add=[no|yes]\n\
10986 encode lfence, mfence and sfence as\n\
10987 lock addl $0x0, (%%{re}sp)\n"));
10988 fprintf (stream, _("\
10989 -mrelax-relocations=[no|yes]\n\
10990 generate relax relocations\n"));
10991 fprintf (stream, _("\
10992 -mamd64 accept only AMD64 ISA\n"));
10993 fprintf (stream, _("\
10994 -mintel64 accept only Intel64 ISA\n"));
10997 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10998 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10999 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11001 /* Pick the target format to use. */
11004 i386_target_format (void)
11006 if (!strncmp (default_arch, "x86_64", 6))
11008 update_code_flag (CODE_64BIT, 1);
11009 if (default_arch[6] == '\0')
11010 x86_elf_abi = X86_64_ABI;
11012 x86_elf_abi = X86_64_X32_ABI;
11014 else if (!strcmp (default_arch, "i386"))
11015 update_code_flag (CODE_32BIT, 1);
11016 else if (!strcmp (default_arch, "iamcu"))
11018 update_code_flag (CODE_32BIT, 1);
11019 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11021 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11022 cpu_arch_name = "iamcu";
11023 cpu_sub_arch_name = NULL;
11024 cpu_arch_flags = iamcu_flags;
11025 cpu_arch_isa = PROCESSOR_IAMCU;
11026 cpu_arch_isa_flags = iamcu_flags;
11027 if (!cpu_arch_tune_set)
11029 cpu_arch_tune = cpu_arch_isa;
11030 cpu_arch_tune_flags = cpu_arch_isa_flags;
11033 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11034 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11038 as_fatal (_("unknown architecture"));
11040 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11041 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11042 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11043 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11045 switch (OUTPUT_FLAVOR)
11047 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11048 case bfd_target_aout_flavour:
11049 return AOUT_TARGET_FORMAT;
11051 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11052 # if defined (TE_PE) || defined (TE_PEP)
11053 case bfd_target_coff_flavour:
11054 if (flag_code == CODE_64BIT)
11055 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11058 # elif defined (TE_GO32)
11059 case bfd_target_coff_flavour:
11060 return "coff-go32";
11062 case bfd_target_coff_flavour:
11063 return "coff-i386";
11066 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11067 case bfd_target_elf_flavour:
11069 const char *format;
11071 switch (x86_elf_abi)
11074 format = ELF_TARGET_FORMAT;
11077 use_rela_relocations = 1;
11079 format = ELF_TARGET_FORMAT64;
11081 case X86_64_X32_ABI:
11082 use_rela_relocations = 1;
11084 disallow_64bit_reloc = 1;
11085 format = ELF_TARGET_FORMAT32;
11088 if (cpu_arch_isa == PROCESSOR_L1OM)
11090 if (x86_elf_abi != X86_64_ABI)
11091 as_fatal (_("Intel L1OM is 64bit only"));
11092 return ELF_TARGET_L1OM_FORMAT;
11094 else if (cpu_arch_isa == PROCESSOR_K1OM)
11096 if (x86_elf_abi != X86_64_ABI)
11097 as_fatal (_("Intel K1OM is 64bit only"));
11098 return ELF_TARGET_K1OM_FORMAT;
11100 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11102 if (x86_elf_abi != I386_ABI)
11103 as_fatal (_("Intel MCU is 32bit only"));
11104 return ELF_TARGET_IAMCU_FORMAT;
11110 #if defined (OBJ_MACH_O)
11111 case bfd_target_mach_o_flavour:
11112 if (flag_code == CODE_64BIT)
11114 use_rela_relocations = 1;
11116 return "mach-o-x86-64";
11119 return "mach-o-i386";
11127 #endif /* OBJ_MAYBE_ more than one */
11130 md_undefined_symbol (char *name)
11132 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11133 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11134 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11135 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11139 if (symbol_find (name))
11140 as_bad (_("GOT already in symbol table"));
11141 GOT_symbol = symbol_new (name, undefined_section,
11142 (valueT) 0, &zero_address_frag);
11149 /* Round up a section size to the appropriate boundary. */
11152 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11154 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11155 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11157 /* For a.out, force the section size to be aligned. If we don't do
11158 this, BFD will align it for us, but it will not write out the
11159 final bytes of the section. This may be a bug in BFD, but it is
11160 easier to fix it here since that is how the other a.out targets
11164 align = bfd_get_section_alignment (stdoutput, segment);
11165 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11172 /* On the i386, PC-relative offsets are relative to the start of the
11173 next instruction. That is, the address of the offset, plus its
11174 size, since the offset is always the last part of the insn. */
11177 md_pcrel_from (fixS *fixP)
11179 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11185 s_bss (int ignore ATTRIBUTE_UNUSED)
11189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11191 obj_elf_section_change_hook ();
11193 temp = get_absolute_expression ();
11194 subseg_set (bss_section, (subsegT) temp);
11195 demand_empty_rest_of_line ();
11201 i386_validate_fix (fixS *fixp)
11203 if (fixp->fx_subsy)
11205 if (fixp->fx_subsy == GOT_symbol)
11207 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11212 if (fixp->fx_tcbit2)
11213 fixp->fx_r_type = (fixp->fx_tcbit
11214 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11215 : BFD_RELOC_X86_64_GOTPCRELX);
11218 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11223 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11225 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11227 fixp->fx_subsy = 0;
11230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11231 else if (!object_64bit)
11233 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11234 && fixp->fx_tcbit2)
11235 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11241 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11244 bfd_reloc_code_real_type code;
11246 switch (fixp->fx_r_type)
11248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11249 case BFD_RELOC_SIZE32:
11250 case BFD_RELOC_SIZE64:
11251 if (S_IS_DEFINED (fixp->fx_addsy)
11252 && !S_IS_EXTERNAL (fixp->fx_addsy))
11254 /* Resolve size relocation against local symbol to size of
11255 the symbol plus addend. */
11256 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11257 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11258 && !fits_in_unsigned_long (value))
11259 as_bad_where (fixp->fx_file, fixp->fx_line,
11260 _("symbol size computation overflow"));
11261 fixp->fx_addsy = NULL;
11262 fixp->fx_subsy = NULL;
11263 md_apply_fix (fixp, (valueT *) &value, NULL);
11267 /* Fall through. */
11269 case BFD_RELOC_X86_64_PLT32:
11270 case BFD_RELOC_X86_64_GOT32:
11271 case BFD_RELOC_X86_64_GOTPCREL:
11272 case BFD_RELOC_X86_64_GOTPCRELX:
11273 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11274 case BFD_RELOC_386_PLT32:
11275 case BFD_RELOC_386_GOT32:
11276 case BFD_RELOC_386_GOT32X:
11277 case BFD_RELOC_386_GOTOFF:
11278 case BFD_RELOC_386_GOTPC:
11279 case BFD_RELOC_386_TLS_GD:
11280 case BFD_RELOC_386_TLS_LDM:
11281 case BFD_RELOC_386_TLS_LDO_32:
11282 case BFD_RELOC_386_TLS_IE_32:
11283 case BFD_RELOC_386_TLS_IE:
11284 case BFD_RELOC_386_TLS_GOTIE:
11285 case BFD_RELOC_386_TLS_LE_32:
11286 case BFD_RELOC_386_TLS_LE:
11287 case BFD_RELOC_386_TLS_GOTDESC:
11288 case BFD_RELOC_386_TLS_DESC_CALL:
11289 case BFD_RELOC_X86_64_TLSGD:
11290 case BFD_RELOC_X86_64_TLSLD:
11291 case BFD_RELOC_X86_64_DTPOFF32:
11292 case BFD_RELOC_X86_64_DTPOFF64:
11293 case BFD_RELOC_X86_64_GOTTPOFF:
11294 case BFD_RELOC_X86_64_TPOFF32:
11295 case BFD_RELOC_X86_64_TPOFF64:
11296 case BFD_RELOC_X86_64_GOTOFF64:
11297 case BFD_RELOC_X86_64_GOTPC32:
11298 case BFD_RELOC_X86_64_GOT64:
11299 case BFD_RELOC_X86_64_GOTPCREL64:
11300 case BFD_RELOC_X86_64_GOTPC64:
11301 case BFD_RELOC_X86_64_GOTPLT64:
11302 case BFD_RELOC_X86_64_PLTOFF64:
11303 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11304 case BFD_RELOC_X86_64_TLSDESC_CALL:
11305 case BFD_RELOC_RVA:
11306 case BFD_RELOC_VTABLE_ENTRY:
11307 case BFD_RELOC_VTABLE_INHERIT:
11309 case BFD_RELOC_32_SECREL:
11311 code = fixp->fx_r_type;
11313 case BFD_RELOC_X86_64_32S:
11314 if (!fixp->fx_pcrel)
11316 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11317 code = fixp->fx_r_type;
11320 /* Fall through. */
11322 if (fixp->fx_pcrel)
11324 switch (fixp->fx_size)
11327 as_bad_where (fixp->fx_file, fixp->fx_line,
11328 _("can not do %d byte pc-relative relocation"),
11330 code = BFD_RELOC_32_PCREL;
11332 case 1: code = BFD_RELOC_8_PCREL; break;
11333 case 2: code = BFD_RELOC_16_PCREL; break;
11334 case 4: code = BFD_RELOC_32_PCREL; break;
11336 case 8: code = BFD_RELOC_64_PCREL; break;
11342 switch (fixp->fx_size)
11345 as_bad_where (fixp->fx_file, fixp->fx_line,
11346 _("can not do %d byte relocation"),
11348 code = BFD_RELOC_32;
11350 case 1: code = BFD_RELOC_8; break;
11351 case 2: code = BFD_RELOC_16; break;
11352 case 4: code = BFD_RELOC_32; break;
11354 case 8: code = BFD_RELOC_64; break;
11361 if ((code == BFD_RELOC_32
11362 || code == BFD_RELOC_32_PCREL
11363 || code == BFD_RELOC_X86_64_32S)
11365 && fixp->fx_addsy == GOT_symbol)
11368 code = BFD_RELOC_386_GOTPC;
11370 code = BFD_RELOC_X86_64_GOTPC32;
11372 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11374 && fixp->fx_addsy == GOT_symbol)
11376 code = BFD_RELOC_X86_64_GOTPC64;
11379 rel = XNEW (arelent);
11380 rel->sym_ptr_ptr = XNEW (asymbol *);
11381 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11383 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11385 if (!use_rela_relocations)
11387 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11388 vtable entry to be used in the relocation's section offset. */
11389 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11390 rel->address = fixp->fx_offset;
11391 #if defined (OBJ_COFF) && defined (TE_PE)
11392 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11393 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11398 /* Use the rela in 64bit mode. */
11401 if (disallow_64bit_reloc)
11404 case BFD_RELOC_X86_64_DTPOFF64:
11405 case BFD_RELOC_X86_64_TPOFF64:
11406 case BFD_RELOC_64_PCREL:
11407 case BFD_RELOC_X86_64_GOTOFF64:
11408 case BFD_RELOC_X86_64_GOT64:
11409 case BFD_RELOC_X86_64_GOTPCREL64:
11410 case BFD_RELOC_X86_64_GOTPC64:
11411 case BFD_RELOC_X86_64_GOTPLT64:
11412 case BFD_RELOC_X86_64_PLTOFF64:
11413 as_bad_where (fixp->fx_file, fixp->fx_line,
11414 _("cannot represent relocation type %s in x32 mode"),
11415 bfd_get_reloc_code_name (code));
11421 if (!fixp->fx_pcrel)
11422 rel->addend = fixp->fx_offset;
11426 case BFD_RELOC_X86_64_PLT32:
11427 case BFD_RELOC_X86_64_GOT32:
11428 case BFD_RELOC_X86_64_GOTPCREL:
11429 case BFD_RELOC_X86_64_GOTPCRELX:
11430 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11431 case BFD_RELOC_X86_64_TLSGD:
11432 case BFD_RELOC_X86_64_TLSLD:
11433 case BFD_RELOC_X86_64_GOTTPOFF:
11434 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11435 case BFD_RELOC_X86_64_TLSDESC_CALL:
11436 rel->addend = fixp->fx_offset - fixp->fx_size;
11439 rel->addend = (section->vma
11441 + fixp->fx_addnumber
11442 + md_pcrel_from (fixp));
11447 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11448 if (rel->howto == NULL)
11450 as_bad_where (fixp->fx_file, fixp->fx_line,
11451 _("cannot represent relocation type %s"),
11452 bfd_get_reloc_code_name (code));
11453 /* Set howto to a garbage value so that we can keep going. */
11454 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11455 gas_assert (rel->howto != NULL);
11461 #include "tc-i386-intel.c"
11464 tc_x86_parse_to_dw2regnum (expressionS *exp)
11466 int saved_naked_reg;
11467 char saved_register_dot;
11469 saved_naked_reg = allow_naked_reg;
11470 allow_naked_reg = 1;
11471 saved_register_dot = register_chars['.'];
11472 register_chars['.'] = '.';
11473 allow_pseudo_reg = 1;
11474 expression_and_evaluate (exp);
11475 allow_pseudo_reg = 0;
11476 register_chars['.'] = saved_register_dot;
11477 allow_naked_reg = saved_naked_reg;
11479 if (exp->X_op == O_register && exp->X_add_number >= 0)
11481 if ((addressT) exp->X_add_number < i386_regtab_size)
11483 exp->X_op = O_constant;
11484 exp->X_add_number = i386_regtab[exp->X_add_number]
11485 .dw2_regnum[flag_code >> 1];
11488 exp->X_op = O_illegal;
11493 tc_x86_frame_initial_instructions (void)
11495 static unsigned int sp_regno[2];
11497 if (!sp_regno[flag_code >> 1])
11499 char *saved_input = input_line_pointer;
11500 char sp[][4] = {"esp", "rsp"};
11503 input_line_pointer = sp[flag_code >> 1];
11504 tc_x86_parse_to_dw2regnum (&exp);
11505 gas_assert (exp.X_op == O_constant);
11506 sp_regno[flag_code >> 1] = exp.X_add_number;
11507 input_line_pointer = saved_input;
11510 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11511 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11515 x86_dwarf2_addr_size (void)
11517 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11518 if (x86_elf_abi == X86_64_X32_ABI)
11521 return bfd_arch_bits_per_address (stdoutput) / 8;
11525 i386_elf_section_type (const char *str, size_t len)
11527 if (flag_code == CODE_64BIT
11528 && len == sizeof ("unwind") - 1
11529 && strncmp (str, "unwind", 6) == 0)
11530 return SHT_X86_64_UNWIND;
11537 i386_solaris_fix_up_eh_frame (segT sec)
11539 if (flag_code == CODE_64BIT)
11540 elf_section_type (sec) = SHT_X86_64_UNWIND;
11546 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11550 exp.X_op = O_secrel;
11551 exp.X_add_symbol = symbol;
11552 exp.X_add_number = 0;
11553 emit_expr (&exp, size);
11557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11558 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11561 x86_64_section_letter (int letter, const char **ptr_msg)
11563 if (flag_code == CODE_64BIT)
11566 return SHF_X86_64_LARGE;
11568 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11571 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11576 x86_64_section_word (char *str, size_t len)
11578 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11579 return SHF_X86_64_LARGE;
11585 handle_large_common (int small ATTRIBUTE_UNUSED)
11587 if (flag_code != CODE_64BIT)
11589 s_comm_internal (0, elf_common_parse);
11590 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11594 static segT lbss_section;
11595 asection *saved_com_section_ptr = elf_com_section_ptr;
11596 asection *saved_bss_section = bss_section;
11598 if (lbss_section == NULL)
11600 flagword applicable;
11601 segT seg = now_seg;
11602 subsegT subseg = now_subseg;
11604 /* The .lbss section is for local .largecomm symbols. */
11605 lbss_section = subseg_new (".lbss", 0);
11606 applicable = bfd_applicable_section_flags (stdoutput);
11607 bfd_set_section_flags (stdoutput, lbss_section,
11608 applicable & SEC_ALLOC);
11609 seg_info (lbss_section)->bss = 1;
11611 subseg_set (seg, subseg);
11614 elf_com_section_ptr = &_bfd_elf_large_com_section;
11615 bss_section = lbss_section;
11617 s_comm_internal (0, elf_common_parse);
11619 elf_com_section_ptr = saved_com_section_ptr;
11620 bss_section = saved_bss_section;
11623 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */