1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
849 CPU_BTVER1_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
851 CPU_BTVER2_FLAGS, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
869 CPU_SSSE3_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_1_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
881 CPU_AVX512F_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
883 CPU_AVX512CD_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
885 CPU_AVX512ER_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
887 CPU_AVX512PF_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
889 CPU_AVX512DQ_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
891 CPU_AVX512BW_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
893 CPU_AVX512VL_FLAGS, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
897 CPU_VMFUNC_FLAGS, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
901 CPU_XSAVE_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEOPT_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEC_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
907 CPU_XSAVES_FLAGS, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
915 CPU_FSGSBASE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
917 CPU_RDRND_FLAGS, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
931 CPU_MOVBE_FLAGS, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
937 CPU_LZCNT_FLAGS, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
943 CPU_INVPCID_FLAGS, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
945 CPU_CLFLUSH_FLAGS, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
949 CPU_SYSCALL_FLAGS, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
951 CPU_RDTSCP_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
953 CPU_3DNOW_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
955 CPU_3DNOWA_FLAGS, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
957 CPU_PADLOCK_FLAGS, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
963 CPU_SSE4A_FLAGS, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
973 CPU_RDSEED_FLAGS, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
975 CPU_PRFCHW_FLAGS, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
983 CPU_CLFLUSHOPT_FLAGS, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
985 CPU_PREFETCHWT1_FLAGS, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
991 CPU_AVX512IFMA_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
993 CPU_AVX512VBMI_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1007 CPU_CLZERO_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1009 CPU_MWAITX_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1011 CPU_OSPKE_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1013 CPU_RDPID_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
1040 static const noarch_entry cpu_noarch[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1089 && *input_line_pointer == ',')
1091 align = parse_align (needs_align - 1);
1093 if (align == (addressT) -1)
1108 bss_alloc (symbolP, size, align);
1113 pe_lcomm (int needs_align)
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1119 const pseudo_typeS md_pseudo_table[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1124 {"align", s_align_ptwo, 0},
1126 {"arch", set_cpu_arch, 0},
1130 {"lcomm", pe_lcomm, 1},
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1136 {"slong", signed_cons, 4},
1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
1143 {"code64", set_code_flag, CODE_64BIT},
1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
1156 {"file", dwarf2_directive_file, 0},
1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1161 {"secrel32", pe_directive_secrel, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control *op_hash;
1172 /* Hash table for register lookup. */
1173 static struct hash_control *reg_hash;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1[] =
1180 static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt[] = {
1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt[] = {
1206 f32_1, f32_2, f16_3, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1238 alt_9, alt_10, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
1261 last = count % max_single_nop_size;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1269 nops = patt[last - 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1280 memcpy (where + offset, nops, last);
1285 fits_in_imm7 (offsetT num)
1287 return (num & 0x7f) == num;
1291 fits_in_imm31 (offsetT num)
1293 return (num & 0x7fffffff) == num;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1302 const unsigned char *const *patt = NULL;
1303 int max_single_nop_size;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
1307 switch (fragP->fr_type)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code == CODE_16BIT)
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
1354 case PROCESSOR_CORE:
1355 case PROCESSOR_CORE2:
1356 case PROCESSOR_COREI7:
1357 case PROCESSOR_L1OM:
1358 case PROCESSOR_K1OM:
1359 case PROCESSOR_GENERIC64:
1361 case PROCESSOR_ATHLON:
1363 case PROCESSOR_AMDFAM10:
1365 case PROCESSOR_ZNVER:
1369 case PROCESSOR_I386:
1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
1372 case PROCESSOR_PENTIUMPRO:
1373 case PROCESSOR_IAMCU:
1374 case PROCESSOR_GENERIC32:
1381 switch (fragP->tc_frag_data.tune)
1383 case PROCESSOR_UNKNOWN:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386:
1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
1392 case PROCESSOR_IAMCU:
1394 case PROCESSOR_ATHLON:
1396 case PROCESSOR_AMDFAM10:
1398 case PROCESSOR_ZNVER:
1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
1412 case PROCESSOR_CORE2:
1413 case PROCESSOR_COREI7:
1414 case PROCESSOR_L1OM:
1415 case PROCESSOR_K1OM:
1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1421 case PROCESSOR_GENERIC64:
1427 if (patt == f32_patt)
1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1442 limit = max_single_nop_size;
1444 if (fragP->fr_type == rs_fill_nop)
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1457 fragP->fr_var = count;
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1465 /* Use "jmp disp8" if possible. */
1467 where[0] = jump_disp8[0];
1473 unsigned int size_of_jump;
1475 if (flag_code == CODE_16BIT)
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1483 where[0] = jump32_disp32[0];
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
1505 operand_type_all_zero (const union i386_operand_type *x)
1507 switch (ARRAY_SIZE(x->array))
1518 return !x->array[0];
1525 operand_type_set (union i386_operand_type *x, unsigned int v)
1527 switch (ARRAY_SIZE(x->array))
1545 operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
1548 switch (ARRAY_SIZE(x->array))
1551 if (x->array[2] != y->array[2])
1555 if (x->array[1] != y->array[1])
1559 return x->array[0] == y->array[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags *x)
1569 switch (ARRAY_SIZE(x->array))
1584 return !x->array[0];
1591 cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1594 switch (ARRAY_SIZE(x->array))
1597 if (x->array[3] != y->array[3])
1601 if (x->array[2] != y->array[2])
1605 if (x->array[1] != y->array[1])
1609 return x->array[0] == y->array[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f)
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1626 switch (ARRAY_SIZE (x.array))
1629 x.array [3] &= y.array [3];
1632 x.array [2] &= y.array [2];
1635 x.array [1] &= y.array [1];
1638 x.array [0] &= y.array [0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1649 switch (ARRAY_SIZE (x.array))
1652 x.array [3] |= y.array [3];
1655 x.array [2] |= y.array [2];
1658 x.array [1] |= y.array [1];
1661 x.array [0] |= y.array [0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1672 switch (ARRAY_SIZE (x.array))
1675 x.array [3] &= ~y.array [3];
1678 x.array [2] &= ~y.array [2];
1681 x.array [1] &= ~y.array [1];
1684 x.array [0] &= ~y.array [0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template *t)
1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1709 if (cpu_flags_all_zero (&x))
1711 /* This instruction is available on all archs. */
1712 match |= CPU_FLAGS_ARCH_MATCH;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu = cpu_arch_flags;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1722 x.bitfield.cpuavx512vl = 0;
1724 cpu = cpu_flags_and (x, cpu);
1725 if (!cpu_flags_all_zero (&cpu))
1727 if (x.bitfield.cpuavx)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1737 else if (x.bitfield.cpuavx512f)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1747 match |= CPU_FLAGS_ARCH_MATCH;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x, i386_operand_type y)
1756 switch (ARRAY_SIZE (x.array))
1759 x.array [2] &= y.array [2];
1762 x.array [1] &= y.array [1];
1765 x.array [0] &= y.array [0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1776 switch (ARRAY_SIZE (x.array))
1779 x.array [2] &= ~y.array [2];
1782 x.array [1] &= ~y.array [1];
1785 x.array [0] &= ~y.array [0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x, i386_operand_type y)
1796 switch (ARRAY_SIZE (x.array))
1799 x.array [2] |= y.array [2];
1802 x.array [1] |= y.array [1];
1805 x.array [0] |= y.array [0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x, i386_operand_type y)
1816 switch (ARRAY_SIZE (x.array))
1819 x.array [2] ^= y.array [2];
1822 x.array [1] ^= y.array [1];
1825 x.array [0] ^= y.array [0];
1833 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1835 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
1841 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1842 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1843 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1852 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1863 operand_type_check (i386_operand_type t, enum operand_type c)
1868 return t.bitfield.reg;
1871 return (t.bitfield.imm8
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1901 between operand GIVEN and opeand WANTED for instruction template T. */
1904 match_operand_size (const insn_template *t, unsigned int wanted,
1907 return !((i.types[given].bitfield.byte
1908 && !t->operand_types[wanted].bitfield.byte)
1909 || (i.types[given].bitfield.word
1910 && !t->operand_types[wanted].bitfield.word)
1911 || (i.types[given].bitfield.dword
1912 && !t->operand_types[wanted].bitfield.dword)
1913 || (i.types[given].bitfield.qword
1914 && !t->operand_types[wanted].bitfield.qword)
1915 || (i.types[given].bitfield.tbyte
1916 && !t->operand_types[wanted].bitfield.tbyte));
1919 /* Return 1 if there is no conflict in SIMD register between operand
1920 GIVEN and opeand WANTED for instruction template T. */
1923 match_simd_size (const insn_template *t, unsigned int wanted,
1926 return !((i.types[given].bitfield.xmmword
1927 && !t->operand_types[wanted].bitfield.xmmword)
1928 || (i.types[given].bitfield.ymmword
1929 && !t->operand_types[wanted].bitfield.ymmword)
1930 || (i.types[given].bitfield.zmmword
1931 && !t->operand_types[wanted].bitfield.zmmword));
1934 /* Return 1 if there is no conflict in any size between operand GIVEN
1935 and opeand WANTED for instruction template T. */
1938 match_mem_size (const insn_template *t, unsigned int wanted,
1941 return (match_operand_size (t, wanted, given)
1942 && !((i.types[given].bitfield.unspecified
1944 && !t->operand_types[wanted].bitfield.unspecified)
1945 || (i.types[given].bitfield.fword
1946 && !t->operand_types[wanted].bitfield.fword)
1947 /* For scalar opcode templates to allow register and memory
1948 operands at the same time, some special casing is needed
1949 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1950 down-conversion vpmov*. */
1951 || ((t->operand_types[wanted].bitfield.regsimd
1952 && !t->opcode_modifier.broadcast
1953 && (t->operand_types[wanted].bitfield.byte
1954 || t->operand_types[wanted].bitfield.word
1955 || t->operand_types[wanted].bitfield.dword
1956 || t->operand_types[wanted].bitfield.qword))
1957 ? (i.types[given].bitfield.xmmword
1958 || i.types[given].bitfield.ymmword
1959 || i.types[given].bitfield.zmmword)
1960 : !match_simd_size(t, wanted, given))));
1963 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1964 operands for instruction template T, and it has MATCH_REVERSE set if there
1965 is no size conflict on any operands for the template with operands reversed
1966 (and the template allows for reversing in the first place). */
1968 #define MATCH_STRAIGHT 1
1969 #define MATCH_REVERSE 2
1971 static INLINE unsigned int
1972 operand_size_match (const insn_template *t)
1974 unsigned int j, match = MATCH_STRAIGHT;
1976 /* Don't check jump instructions. */
1977 if (t->opcode_modifier.jump
1978 || t->opcode_modifier.jumpbyte
1979 || t->opcode_modifier.jumpdword
1980 || t->opcode_modifier.jumpintersegment)
1983 /* Check memory and accumulator operand size. */
1984 for (j = 0; j < i.operands; j++)
1986 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1987 && t->operand_types[j].bitfield.anysize)
1990 if (t->operand_types[j].bitfield.reg
1991 && !match_operand_size (t, j, j))
1997 if (t->operand_types[j].bitfield.regsimd
1998 && !match_simd_size (t, j, j))
2004 if (t->operand_types[j].bitfield.acc
2005 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2011 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2018 if (!t->opcode_modifier.d)
2022 i.error = operand_size_mismatch;
2026 /* Check reverse. */
2027 gas_assert (i.operands == 2);
2029 for (j = 0; j < 2; j++)
2031 if ((t->operand_types[j].bitfield.reg
2032 || t->operand_types[j].bitfield.acc)
2033 && !match_operand_size (t, j, !j))
2036 if (i.types[!j].bitfield.mem
2037 && !match_mem_size (t, j, !j))
2041 return match | MATCH_REVERSE;
2045 operand_type_match (i386_operand_type overlap,
2046 i386_operand_type given)
2048 i386_operand_type temp = overlap;
2050 temp.bitfield.jumpabsolute = 0;
2051 temp.bitfield.unspecified = 0;
2052 temp.bitfield.byte = 0;
2053 temp.bitfield.word = 0;
2054 temp.bitfield.dword = 0;
2055 temp.bitfield.fword = 0;
2056 temp.bitfield.qword = 0;
2057 temp.bitfield.tbyte = 0;
2058 temp.bitfield.xmmword = 0;
2059 temp.bitfield.ymmword = 0;
2060 temp.bitfield.zmmword = 0;
2061 if (operand_type_all_zero (&temp))
2064 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2065 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2069 i.error = operand_type_mismatch;
2073 /* If given types g0 and g1 are registers they must be of the same type
2074 unless the expected operand type register overlap is null.
2075 Memory operand size of certain SIMD instructions is also being checked
2079 operand_type_register_match (i386_operand_type g0,
2080 i386_operand_type t0,
2081 i386_operand_type g1,
2082 i386_operand_type t1)
2084 if (!g0.bitfield.reg
2085 && !g0.bitfield.regsimd
2086 && (!operand_type_check (g0, anymem)
2087 || g0.bitfield.unspecified
2088 || !t0.bitfield.regsimd))
2091 if (!g1.bitfield.reg
2092 && !g1.bitfield.regsimd
2093 && (!operand_type_check (g1, anymem)
2094 || g1.bitfield.unspecified
2095 || !t1.bitfield.regsimd))
2098 if (g0.bitfield.byte == g1.bitfield.byte
2099 && g0.bitfield.word == g1.bitfield.word
2100 && g0.bitfield.dword == g1.bitfield.dword
2101 && g0.bitfield.qword == g1.bitfield.qword
2102 && g0.bitfield.xmmword == g1.bitfield.xmmword
2103 && g0.bitfield.ymmword == g1.bitfield.ymmword
2104 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2107 if (!(t0.bitfield.byte & t1.bitfield.byte)
2108 && !(t0.bitfield.word & t1.bitfield.word)
2109 && !(t0.bitfield.dword & t1.bitfield.dword)
2110 && !(t0.bitfield.qword & t1.bitfield.qword)
2111 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2112 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2113 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2116 i.error = register_type_mismatch;
2121 static INLINE unsigned int
2122 register_number (const reg_entry *r)
2124 unsigned int nr = r->reg_num;
2126 if (r->reg_flags & RegRex)
2129 if (r->reg_flags & RegVRex)
2135 static INLINE unsigned int
2136 mode_from_disp_size (i386_operand_type t)
2138 if (t.bitfield.disp8)
2140 else if (t.bitfield.disp16
2141 || t.bitfield.disp32
2142 || t.bitfield.disp32s)
2149 fits_in_signed_byte (addressT num)
2151 return num + 0x80 <= 0xff;
2155 fits_in_unsigned_byte (addressT num)
2161 fits_in_unsigned_word (addressT num)
2163 return num <= 0xffff;
2167 fits_in_signed_word (addressT num)
2169 return num + 0x8000 <= 0xffff;
2173 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2178 return num + 0x80000000 <= 0xffffffff;
2180 } /* fits_in_signed_long() */
2183 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2188 return num <= 0xffffffff;
2190 } /* fits_in_unsigned_long() */
2193 fits_in_disp8 (offsetT num)
2195 int shift = i.memshift;
2201 mask = (1 << shift) - 1;
2203 /* Return 0 if NUM isn't properly aligned. */
2207 /* Check if NUM will fit in 8bit after shift. */
2208 return fits_in_signed_byte (num >> shift);
2212 fits_in_imm4 (offsetT num)
2214 return (num & 0xf) == num;
2217 static i386_operand_type
2218 smallest_imm_type (offsetT num)
2220 i386_operand_type t;
2222 operand_type_set (&t, 0);
2223 t.bitfield.imm64 = 1;
2225 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2227 /* This code is disabled on the 486 because all the Imm1 forms
2228 in the opcode table are slower on the i486. They're the
2229 versions with the implicitly specified single-position
2230 displacement, which has another syntax if you really want to
2232 t.bitfield.imm1 = 1;
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2239 else if (fits_in_signed_byte (num))
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm8s = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2247 else if (fits_in_unsigned_byte (num))
2249 t.bitfield.imm8 = 1;
2250 t.bitfield.imm16 = 1;
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2254 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2256 t.bitfield.imm16 = 1;
2257 t.bitfield.imm32 = 1;
2258 t.bitfield.imm32s = 1;
2260 else if (fits_in_signed_long (num))
2262 t.bitfield.imm32 = 1;
2263 t.bitfield.imm32s = 1;
2265 else if (fits_in_unsigned_long (num))
2266 t.bitfield.imm32 = 1;
2272 offset_in_range (offsetT val, int size)
2278 case 1: mask = ((addressT) 1 << 8) - 1; break;
2279 case 2: mask = ((addressT) 1 << 16) - 1; break;
2280 case 4: mask = ((addressT) 2 << 31) - 1; break;
2282 case 8: mask = ((addressT) 2 << 63) - 1; break;
2288 /* If BFD64, sign extend val for 32bit address mode. */
2289 if (flag_code != CODE_64BIT
2290 || i.prefix[ADDR_PREFIX])
2291 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2292 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2295 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2297 char buf1[40], buf2[40];
2299 sprint_value (buf1, val);
2300 sprint_value (buf2, val & mask);
2301 as_warn (_("%s shortened to %s"), buf1, buf2);
2316 a. PREFIX_EXIST if attempting to add a prefix where one from the
2317 same class already exists.
2318 b. PREFIX_LOCK if lock prefix is added.
2319 c. PREFIX_REP if rep/repne prefix is added.
2320 d. PREFIX_DS if ds prefix is added.
2321 e. PREFIX_OTHER if other prefix is added.
2324 static enum PREFIX_GROUP
2325 add_prefix (unsigned int prefix)
2327 enum PREFIX_GROUP ret = PREFIX_OTHER;
2330 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2331 && flag_code == CODE_64BIT)
2333 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2334 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2335 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2336 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2347 case DS_PREFIX_OPCODE:
2350 case CS_PREFIX_OPCODE:
2351 case ES_PREFIX_OPCODE:
2352 case FS_PREFIX_OPCODE:
2353 case GS_PREFIX_OPCODE:
2354 case SS_PREFIX_OPCODE:
2358 case REPNE_PREFIX_OPCODE:
2359 case REPE_PREFIX_OPCODE:
2364 case LOCK_PREFIX_OPCODE:
2373 case ADDR_PREFIX_OPCODE:
2377 case DATA_PREFIX_OPCODE:
2381 if (i.prefix[q] != 0)
2389 i.prefix[q] |= prefix;
2392 as_bad (_("same type of prefix used twice"));
2398 update_code_flag (int value, int check)
2400 PRINTF_LIKE ((*as_error));
2402 flag_code = (enum flag_code) value;
2403 if (flag_code == CODE_64BIT)
2405 cpu_arch_flags.bitfield.cpu64 = 1;
2406 cpu_arch_flags.bitfield.cpuno64 = 0;
2410 cpu_arch_flags.bitfield.cpu64 = 0;
2411 cpu_arch_flags.bitfield.cpuno64 = 1;
2413 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2416 as_error = as_fatal;
2419 (*as_error) (_("64bit mode not supported on `%s'."),
2420 cpu_arch_name ? cpu_arch_name : default_arch);
2422 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2425 as_error = as_fatal;
2428 (*as_error) (_("32bit mode not supported on `%s'."),
2429 cpu_arch_name ? cpu_arch_name : default_arch);
2431 stackop_size = '\0';
2435 set_code_flag (int value)
2437 update_code_flag (value, 0);
2441 set_16bit_gcc_code_flag (int new_code_flag)
2443 flag_code = (enum flag_code) new_code_flag;
2444 if (flag_code != CODE_16BIT)
2446 cpu_arch_flags.bitfield.cpu64 = 0;
2447 cpu_arch_flags.bitfield.cpuno64 = 1;
2448 stackop_size = LONG_MNEM_SUFFIX;
2452 set_intel_syntax (int syntax_flag)
2454 /* Find out if register prefixing is specified. */
2455 int ask_naked_reg = 0;
2458 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2461 int e = get_symbol_name (&string);
2463 if (strcmp (string, "prefix") == 0)
2465 else if (strcmp (string, "noprefix") == 0)
2468 as_bad (_("bad argument to syntax directive."));
2469 (void) restore_line_pointer (e);
2471 demand_empty_rest_of_line ();
2473 intel_syntax = syntax_flag;
2475 if (ask_naked_reg == 0)
2476 allow_naked_reg = (intel_syntax
2477 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2479 allow_naked_reg = (ask_naked_reg < 0);
2481 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2483 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2484 identifier_chars['$'] = intel_syntax ? '$' : 0;
2485 register_prefix = allow_naked_reg ? "" : "%";
2489 set_intel_mnemonic (int mnemonic_flag)
2491 intel_mnemonic = mnemonic_flag;
2495 set_allow_index_reg (int flag)
2497 allow_index_reg = flag;
2501 set_check (int what)
2503 enum check_kind *kind;
2508 kind = &operand_check;
2519 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2522 int e = get_symbol_name (&string);
2524 if (strcmp (string, "none") == 0)
2526 else if (strcmp (string, "warning") == 0)
2527 *kind = check_warning;
2528 else if (strcmp (string, "error") == 0)
2529 *kind = check_error;
2531 as_bad (_("bad argument to %s_check directive."), str);
2532 (void) restore_line_pointer (e);
2535 as_bad (_("missing argument for %s_check directive"), str);
2537 demand_empty_rest_of_line ();
2541 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2542 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2545 static const char *arch;
2547 /* Intel LIOM is only supported on ELF. */
2553 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2554 use default_arch. */
2555 arch = cpu_arch_name;
2557 arch = default_arch;
2560 /* If we are targeting Intel MCU, we must enable it. */
2561 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2562 || new_flag.bitfield.cpuiamcu)
2565 /* If we are targeting Intel L1OM, we must enable it. */
2566 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2567 || new_flag.bitfield.cpul1om)
2570 /* If we are targeting Intel K1OM, we must enable it. */
2571 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2572 || new_flag.bitfield.cpuk1om)
2575 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2580 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2584 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2587 int e = get_symbol_name (&string);
2589 i386_cpu_flags flags;
2591 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2593 if (strcmp (string, cpu_arch[j].name) == 0)
2595 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2599 cpu_arch_name = cpu_arch[j].name;
2600 cpu_sub_arch_name = NULL;
2601 cpu_arch_flags = cpu_arch[j].flags;
2602 if (flag_code == CODE_64BIT)
2604 cpu_arch_flags.bitfield.cpu64 = 1;
2605 cpu_arch_flags.bitfield.cpuno64 = 0;
2609 cpu_arch_flags.bitfield.cpu64 = 0;
2610 cpu_arch_flags.bitfield.cpuno64 = 1;
2612 cpu_arch_isa = cpu_arch[j].type;
2613 cpu_arch_isa_flags = cpu_arch[j].flags;
2614 if (!cpu_arch_tune_set)
2616 cpu_arch_tune = cpu_arch_isa;
2617 cpu_arch_tune_flags = cpu_arch_isa_flags;
2622 flags = cpu_flags_or (cpu_arch_flags,
2625 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2627 if (cpu_sub_arch_name)
2629 char *name = cpu_sub_arch_name;
2630 cpu_sub_arch_name = concat (name,
2632 (const char *) NULL);
2636 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2637 cpu_arch_flags = flags;
2638 cpu_arch_isa_flags = flags;
2642 = cpu_flags_or (cpu_arch_isa_flags,
2644 (void) restore_line_pointer (e);
2645 demand_empty_rest_of_line ();
2650 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2652 /* Disable an ISA extension. */
2653 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2654 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2656 flags = cpu_flags_and_not (cpu_arch_flags,
2657 cpu_noarch[j].flags);
2658 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2660 if (cpu_sub_arch_name)
2662 char *name = cpu_sub_arch_name;
2663 cpu_sub_arch_name = concat (name, string,
2664 (const char *) NULL);
2668 cpu_sub_arch_name = xstrdup (string);
2669 cpu_arch_flags = flags;
2670 cpu_arch_isa_flags = flags;
2672 (void) restore_line_pointer (e);
2673 demand_empty_rest_of_line ();
2677 j = ARRAY_SIZE (cpu_arch);
2680 if (j >= ARRAY_SIZE (cpu_arch))
2681 as_bad (_("no such architecture: `%s'"), string);
2683 *input_line_pointer = e;
2686 as_bad (_("missing cpu architecture"));
2688 no_cond_jump_promotion = 0;
2689 if (*input_line_pointer == ','
2690 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2695 ++input_line_pointer;
2696 e = get_symbol_name (&string);
2698 if (strcmp (string, "nojumps") == 0)
2699 no_cond_jump_promotion = 1;
2700 else if (strcmp (string, "jumps") == 0)
2703 as_bad (_("no such architecture modifier: `%s'"), string);
2705 (void) restore_line_pointer (e);
2708 demand_empty_rest_of_line ();
2711 enum bfd_architecture
2714 if (cpu_arch_isa == PROCESSOR_L1OM)
2716 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2717 || flag_code != CODE_64BIT)
2718 as_fatal (_("Intel L1OM is 64bit ELF only"));
2719 return bfd_arch_l1om;
2721 else if (cpu_arch_isa == PROCESSOR_K1OM)
2723 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2724 || flag_code != CODE_64BIT)
2725 as_fatal (_("Intel K1OM is 64bit ELF only"));
2726 return bfd_arch_k1om;
2728 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2730 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2731 || flag_code == CODE_64BIT)
2732 as_fatal (_("Intel MCU is 32bit ELF only"));
2733 return bfd_arch_iamcu;
2736 return bfd_arch_i386;
2742 if (!strncmp (default_arch, "x86_64", 6))
2744 if (cpu_arch_isa == PROCESSOR_L1OM)
2746 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2747 || default_arch[6] != '\0')
2748 as_fatal (_("Intel L1OM is 64bit ELF only"));
2749 return bfd_mach_l1om;
2751 else if (cpu_arch_isa == PROCESSOR_K1OM)
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2754 || default_arch[6] != '\0')
2755 as_fatal (_("Intel K1OM is 64bit ELF only"));
2756 return bfd_mach_k1om;
2758 else if (default_arch[6] == '\0')
2759 return bfd_mach_x86_64;
2761 return bfd_mach_x64_32;
2763 else if (!strcmp (default_arch, "i386")
2764 || !strcmp (default_arch, "iamcu"))
2766 if (cpu_arch_isa == PROCESSOR_IAMCU)
2768 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2769 as_fatal (_("Intel MCU is 32bit ELF only"));
2770 return bfd_mach_i386_iamcu;
2773 return bfd_mach_i386_i386;
2776 as_fatal (_("unknown architecture"));
2782 const char *hash_err;
2784 /* Support pseudo prefixes like {disp32}. */
2785 lex_type ['{'] = LEX_BEGIN_NAME;
2787 /* Initialize op_hash hash table. */
2788 op_hash = hash_new ();
2791 const insn_template *optab;
2792 templates *core_optab;
2794 /* Setup for loop. */
2796 core_optab = XNEW (templates);
2797 core_optab->start = optab;
2802 if (optab->name == NULL
2803 || strcmp (optab->name, (optab - 1)->name) != 0)
2805 /* different name --> ship out current template list;
2806 add to hash table; & begin anew. */
2807 core_optab->end = optab;
2808 hash_err = hash_insert (op_hash,
2810 (void *) core_optab);
2813 as_fatal (_("can't hash %s: %s"),
2817 if (optab->name == NULL)
2819 core_optab = XNEW (templates);
2820 core_optab->start = optab;
2825 /* Initialize reg_hash hash table. */
2826 reg_hash = hash_new ();
2828 const reg_entry *regtab;
2829 unsigned int regtab_size = i386_regtab_size;
2831 for (regtab = i386_regtab; regtab_size--; regtab++)
2833 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2835 as_fatal (_("can't hash %s: %s"),
2841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2846 for (c = 0; c < 256; c++)
2851 mnemonic_chars[c] = c;
2852 register_chars[c] = c;
2853 operand_chars[c] = c;
2855 else if (ISLOWER (c))
2857 mnemonic_chars[c] = c;
2858 register_chars[c] = c;
2859 operand_chars[c] = c;
2861 else if (ISUPPER (c))
2863 mnemonic_chars[c] = TOLOWER (c);
2864 register_chars[c] = mnemonic_chars[c];
2865 operand_chars[c] = c;
2867 else if (c == '{' || c == '}')
2869 mnemonic_chars[c] = c;
2870 operand_chars[c] = c;
2873 if (ISALPHA (c) || ISDIGIT (c))
2874 identifier_chars[c] = c;
2877 identifier_chars[c] = c;
2878 operand_chars[c] = c;
2883 identifier_chars['@'] = '@';
2886 identifier_chars['?'] = '?';
2887 operand_chars['?'] = '?';
2889 digit_chars['-'] = '-';
2890 mnemonic_chars['_'] = '_';
2891 mnemonic_chars['-'] = '-';
2892 mnemonic_chars['.'] = '.';
2893 identifier_chars['_'] = '_';
2894 identifier_chars['.'] = '.';
2896 for (p = operand_special_chars; *p != '\0'; p++)
2897 operand_chars[(unsigned char) *p] = *p;
2900 if (flag_code == CODE_64BIT)
2902 #if defined (OBJ_COFF) && defined (TE_PE)
2903 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2906 x86_dwarf2_return_column = 16;
2908 x86_cie_data_alignment = -8;
2912 x86_dwarf2_return_column = 8;
2913 x86_cie_data_alignment = -4;
2918 i386_print_statistics (FILE *file)
2920 hash_print_statistics (file, "i386 opcode", op_hash);
2921 hash_print_statistics (file, "i386 register", reg_hash);
2926 /* Debugging routines for md_assemble. */
2927 static void pte (insn_template *);
2928 static void pt (i386_operand_type);
2929 static void pe (expressionS *);
2930 static void ps (symbolS *);
2933 pi (char *line, i386_insn *x)
2937 fprintf (stdout, "%s: template ", line);
2939 fprintf (stdout, " address: base %s index %s scale %x\n",
2940 x->base_reg ? x->base_reg->reg_name : "none",
2941 x->index_reg ? x->index_reg->reg_name : "none",
2942 x->log2_scale_factor);
2943 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2944 x->rm.mode, x->rm.reg, x->rm.regmem);
2945 fprintf (stdout, " sib: base %x index %x scale %x\n",
2946 x->sib.base, x->sib.index, x->sib.scale);
2947 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2948 (x->rex & REX_W) != 0,
2949 (x->rex & REX_R) != 0,
2950 (x->rex & REX_X) != 0,
2951 (x->rex & REX_B) != 0);
2952 for (j = 0; j < x->operands; j++)
2954 fprintf (stdout, " #%d: ", j + 1);
2956 fprintf (stdout, "\n");
2957 if (x->types[j].bitfield.reg
2958 || x->types[j].bitfield.regmmx
2959 || x->types[j].bitfield.regsimd
2960 || x->types[j].bitfield.sreg2
2961 || x->types[j].bitfield.sreg3
2962 || x->types[j].bitfield.control
2963 || x->types[j].bitfield.debug
2964 || x->types[j].bitfield.test)
2965 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2966 if (operand_type_check (x->types[j], imm))
2968 if (operand_type_check (x->types[j], disp))
2969 pe (x->op[j].disps);
2974 pte (insn_template *t)
2977 fprintf (stdout, " %d operands ", t->operands);
2978 fprintf (stdout, "opcode %x ", t->base_opcode);
2979 if (t->extension_opcode != None)
2980 fprintf (stdout, "ext %x ", t->extension_opcode);
2981 if (t->opcode_modifier.d)
2982 fprintf (stdout, "D");
2983 if (t->opcode_modifier.w)
2984 fprintf (stdout, "W");
2985 fprintf (stdout, "\n");
2986 for (j = 0; j < t->operands; j++)
2988 fprintf (stdout, " #%d type ", j + 1);
2989 pt (t->operand_types[j]);
2990 fprintf (stdout, "\n");
2997 fprintf (stdout, " operation %d\n", e->X_op);
2998 fprintf (stdout, " add_number %ld (%lx)\n",
2999 (long) e->X_add_number, (long) e->X_add_number);
3000 if (e->X_add_symbol)
3002 fprintf (stdout, " add_symbol ");
3003 ps (e->X_add_symbol);
3004 fprintf (stdout, "\n");
3008 fprintf (stdout, " op_symbol ");
3009 ps (e->X_op_symbol);
3010 fprintf (stdout, "\n");
3017 fprintf (stdout, "%s type %s%s",
3019 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3020 segment_name (S_GET_SEGMENT (s)));
3023 static struct type_name
3025 i386_operand_type mask;
3028 const type_names[] =
3030 { OPERAND_TYPE_REG8, "r8" },
3031 { OPERAND_TYPE_REG16, "r16" },
3032 { OPERAND_TYPE_REG32, "r32" },
3033 { OPERAND_TYPE_REG64, "r64" },
3034 { OPERAND_TYPE_IMM8, "i8" },
3035 { OPERAND_TYPE_IMM8, "i8s" },
3036 { OPERAND_TYPE_IMM16, "i16" },
3037 { OPERAND_TYPE_IMM32, "i32" },
3038 { OPERAND_TYPE_IMM32S, "i32s" },
3039 { OPERAND_TYPE_IMM64, "i64" },
3040 { OPERAND_TYPE_IMM1, "i1" },
3041 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3042 { OPERAND_TYPE_DISP8, "d8" },
3043 { OPERAND_TYPE_DISP16, "d16" },
3044 { OPERAND_TYPE_DISP32, "d32" },
3045 { OPERAND_TYPE_DISP32S, "d32s" },
3046 { OPERAND_TYPE_DISP64, "d64" },
3047 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3048 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3049 { OPERAND_TYPE_CONTROL, "control reg" },
3050 { OPERAND_TYPE_TEST, "test reg" },
3051 { OPERAND_TYPE_DEBUG, "debug reg" },
3052 { OPERAND_TYPE_FLOATREG, "FReg" },
3053 { OPERAND_TYPE_FLOATACC, "FAcc" },
3054 { OPERAND_TYPE_SREG2, "SReg2" },
3055 { OPERAND_TYPE_SREG3, "SReg3" },
3056 { OPERAND_TYPE_ACC, "Acc" },
3057 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3058 { OPERAND_TYPE_REGMMX, "rMMX" },
3059 { OPERAND_TYPE_REGXMM, "rXMM" },
3060 { OPERAND_TYPE_REGYMM, "rYMM" },
3061 { OPERAND_TYPE_REGZMM, "rZMM" },
3062 { OPERAND_TYPE_REGMASK, "Mask reg" },
3063 { OPERAND_TYPE_ESSEG, "es" },
3067 pt (i386_operand_type t)
3070 i386_operand_type a;
3072 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3074 a = operand_type_and (t, type_names[j].mask);
3075 if (!operand_type_all_zero (&a))
3076 fprintf (stdout, "%s, ", type_names[j].name);
3081 #endif /* DEBUG386 */
3083 static bfd_reloc_code_real_type
3084 reloc (unsigned int size,
3087 bfd_reloc_code_real_type other)
3089 if (other != NO_RELOC)
3091 reloc_howto_type *rel;
3096 case BFD_RELOC_X86_64_GOT32:
3097 return BFD_RELOC_X86_64_GOT64;
3099 case BFD_RELOC_X86_64_GOTPLT64:
3100 return BFD_RELOC_X86_64_GOTPLT64;
3102 case BFD_RELOC_X86_64_PLTOFF64:
3103 return BFD_RELOC_X86_64_PLTOFF64;
3105 case BFD_RELOC_X86_64_GOTPC32:
3106 other = BFD_RELOC_X86_64_GOTPC64;
3108 case BFD_RELOC_X86_64_GOTPCREL:
3109 other = BFD_RELOC_X86_64_GOTPCREL64;
3111 case BFD_RELOC_X86_64_TPOFF32:
3112 other = BFD_RELOC_X86_64_TPOFF64;
3114 case BFD_RELOC_X86_64_DTPOFF32:
3115 other = BFD_RELOC_X86_64_DTPOFF64;
3121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3122 if (other == BFD_RELOC_SIZE32)
3125 other = BFD_RELOC_SIZE64;
3128 as_bad (_("there are no pc-relative size relocations"));
3134 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3135 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3138 rel = bfd_reloc_type_lookup (stdoutput, other);
3140 as_bad (_("unknown relocation (%u)"), other);
3141 else if (size != bfd_get_reloc_size (rel))
3142 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3143 bfd_get_reloc_size (rel),
3145 else if (pcrel && !rel->pc_relative)
3146 as_bad (_("non-pc-relative relocation for pc-relative field"));
3147 else if ((rel->complain_on_overflow == complain_overflow_signed
3149 || (rel->complain_on_overflow == complain_overflow_unsigned
3151 as_bad (_("relocated field and relocation type differ in signedness"));
3160 as_bad (_("there are no unsigned pc-relative relocations"));
3163 case 1: return BFD_RELOC_8_PCREL;
3164 case 2: return BFD_RELOC_16_PCREL;
3165 case 4: return BFD_RELOC_32_PCREL;
3166 case 8: return BFD_RELOC_64_PCREL;
3168 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3175 case 4: return BFD_RELOC_X86_64_32S;
3180 case 1: return BFD_RELOC_8;
3181 case 2: return BFD_RELOC_16;
3182 case 4: return BFD_RELOC_32;
3183 case 8: return BFD_RELOC_64;
3185 as_bad (_("cannot do %s %u byte relocation"),
3186 sign > 0 ? "signed" : "unsigned", size);
3192 /* Here we decide which fixups can be adjusted to make them relative to
3193 the beginning of the section instead of the symbol. Basically we need
3194 to make sure that the dynamic relocations are done correctly, so in
3195 some cases we force the original symbol to be used. */
3198 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3204 /* Don't adjust pc-relative references to merge sections in 64-bit
3206 if (use_rela_relocations
3207 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3211 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3212 and changed later by validate_fix. */
3213 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3214 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3217 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3218 for size relocations. */
3219 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3220 || fixP->fx_r_type == BFD_RELOC_SIZE64
3221 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3222 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3223 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3224 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3234 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3249 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3250 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3251 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3258 intel_float_operand (const char *mnemonic)
3260 /* Note that the value returned is meaningful only for opcodes with (memory)
3261 operands, hence the code here is free to improperly handle opcodes that
3262 have no operands (for better performance and smaller code). */
3264 if (mnemonic[0] != 'f')
3265 return 0; /* non-math */
3267 switch (mnemonic[1])
3269 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3270 the fs segment override prefix not currently handled because no
3271 call path can make opcodes without operands get here */
3273 return 2 /* integer op */;
3275 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3276 return 3; /* fldcw/fldenv */
3279 if (mnemonic[2] != 'o' /* fnop */)
3280 return 3; /* non-waiting control op */
3283 if (mnemonic[2] == 's')
3284 return 3; /* frstor/frstpm */
3287 if (mnemonic[2] == 'a')
3288 return 3; /* fsave */
3289 if (mnemonic[2] == 't')
3291 switch (mnemonic[3])
3293 case 'c': /* fstcw */
3294 case 'd': /* fstdw */
3295 case 'e': /* fstenv */
3296 case 's': /* fsts[gw] */
3302 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3303 return 0; /* fxsave/fxrstor are not really math ops */
3310 /* Build the VEX prefix. */
3313 build_vex_prefix (const insn_template *t)
3315 unsigned int register_specifier;
3316 unsigned int implied_prefix;
3317 unsigned int vector_length;
3319 /* Check register specifier. */
3320 if (i.vex.register_specifier)
3322 register_specifier =
3323 ~register_number (i.vex.register_specifier) & 0xf;
3324 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3327 register_specifier = 0xf;
3329 /* Use 2-byte VEX prefix by swapping destination and source
3331 if (i.vec_encoding != vex_encoding_vex3
3332 && i.dir_encoding == dir_encoding_default
3333 && i.operands == i.reg_operands
3334 && i.tm.opcode_modifier.vexopcode == VEX0F
3335 && i.tm.opcode_modifier.load
3338 unsigned int xchg = i.operands - 1;
3339 union i386_op temp_op;
3340 i386_operand_type temp_type;
3342 temp_type = i.types[xchg];
3343 i.types[xchg] = i.types[0];
3344 i.types[0] = temp_type;
3345 temp_op = i.op[xchg];
3346 i.op[xchg] = i.op[0];
3349 gas_assert (i.rm.mode == 3);
3353 i.rm.regmem = i.rm.reg;
3356 /* Use the next insn. */
3360 if (i.tm.opcode_modifier.vex == VEXScalar)
3361 vector_length = avxscalar;
3362 else if (i.tm.opcode_modifier.vex == VEX256)
3369 for (op = 0; op < t->operands; ++op)
3370 if (t->operand_types[op].bitfield.xmmword
3371 && t->operand_types[op].bitfield.ymmword
3372 && i.types[op].bitfield.ymmword)
3379 switch ((i.tm.base_opcode >> 8) & 0xff)
3384 case DATA_PREFIX_OPCODE:
3387 case REPE_PREFIX_OPCODE:
3390 case REPNE_PREFIX_OPCODE:
3397 /* Use 2-byte VEX prefix if possible. */
3398 if (i.vec_encoding != vex_encoding_vex3
3399 && i.tm.opcode_modifier.vexopcode == VEX0F
3400 && i.tm.opcode_modifier.vexw != VEXW1
3401 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3403 /* 2-byte VEX prefix. */
3407 i.vex.bytes[0] = 0xc5;
3409 /* Check the REX.R bit. */
3410 r = (i.rex & REX_R) ? 0 : 1;
3411 i.vex.bytes[1] = (r << 7
3412 | register_specifier << 3
3413 | vector_length << 2
3418 /* 3-byte VEX prefix. */
3423 switch (i.tm.opcode_modifier.vexopcode)
3427 i.vex.bytes[0] = 0xc4;
3431 i.vex.bytes[0] = 0xc4;
3435 i.vex.bytes[0] = 0xc4;
3439 i.vex.bytes[0] = 0x8f;
3443 i.vex.bytes[0] = 0x8f;
3447 i.vex.bytes[0] = 0x8f;
3453 /* The high 3 bits of the second VEX byte are 1's compliment
3454 of RXB bits from REX. */
3455 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3457 /* Check the REX.W bit. */
3458 w = (i.rex & REX_W) ? 1 : 0;
3459 if (i.tm.opcode_modifier.vexw == VEXW1)
3462 i.vex.bytes[2] = (w << 7
3463 | register_specifier << 3
3464 | vector_length << 2
3469 static INLINE bfd_boolean
3470 is_evex_encoding (const insn_template *t)
3472 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3473 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3474 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3477 /* Build the EVEX prefix. */
3480 build_evex_prefix (void)
3482 unsigned int register_specifier;
3483 unsigned int implied_prefix;
3485 rex_byte vrex_used = 0;
3487 /* Check register specifier. */
3488 if (i.vex.register_specifier)
3490 gas_assert ((i.vrex & REX_X) == 0);
3492 register_specifier = i.vex.register_specifier->reg_num;
3493 if ((i.vex.register_specifier->reg_flags & RegRex))
3494 register_specifier += 8;
3495 /* The upper 16 registers are encoded in the fourth byte of the
3497 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3498 i.vex.bytes[3] = 0x8;
3499 register_specifier = ~register_specifier & 0xf;
3503 register_specifier = 0xf;
3505 /* Encode upper 16 vector index register in the fourth byte of
3507 if (!(i.vrex & REX_X))
3508 i.vex.bytes[3] = 0x8;
3513 switch ((i.tm.base_opcode >> 8) & 0xff)
3518 case DATA_PREFIX_OPCODE:
3521 case REPE_PREFIX_OPCODE:
3524 case REPNE_PREFIX_OPCODE:
3531 /* 4 byte EVEX prefix. */
3533 i.vex.bytes[0] = 0x62;
3536 switch (i.tm.opcode_modifier.vexopcode)
3552 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3554 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3556 /* The fifth bit of the second EVEX byte is 1's compliment of the
3557 REX_R bit in VREX. */
3558 if (!(i.vrex & REX_R))
3559 i.vex.bytes[1] |= 0x10;
3563 if ((i.reg_operands + i.imm_operands) == i.operands)
3565 /* When all operands are registers, the REX_X bit in REX is not
3566 used. We reuse it to encode the upper 16 registers, which is
3567 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3568 as 1's compliment. */
3569 if ((i.vrex & REX_B))
3572 i.vex.bytes[1] &= ~0x40;
3576 /* EVEX instructions shouldn't need the REX prefix. */
3577 i.vrex &= ~vrex_used;
3578 gas_assert (i.vrex == 0);
3580 /* Check the REX.W bit. */
3581 w = (i.rex & REX_W) ? 1 : 0;
3582 if (i.tm.opcode_modifier.vexw)
3584 if (i.tm.opcode_modifier.vexw == VEXW1)
3587 /* If w is not set it means we are dealing with WIG instruction. */
3590 if (evexwig == evexw1)
3594 /* Encode the U bit. */
3595 implied_prefix |= 0x4;
3597 /* The third byte of the EVEX prefix. */
3598 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3600 /* The fourth byte of the EVEX prefix. */
3601 /* The zeroing-masking bit. */
3602 if (i.mask && i.mask->zeroing)
3603 i.vex.bytes[3] |= 0x80;
3605 /* Don't always set the broadcast bit if there is no RC. */
3608 /* Encode the vector length. */
3609 unsigned int vec_length;
3611 if (!i.tm.opcode_modifier.evex
3612 || i.tm.opcode_modifier.evex == EVEXDYN)
3617 for (op = 0; op < i.tm.operands; ++op)
3618 if (i.tm.operand_types[op].bitfield.xmmword
3619 + i.tm.operand_types[op].bitfield.ymmword
3620 + i.tm.operand_types[op].bitfield.zmmword > 1)
3622 if (i.types[op].bitfield.zmmword)
3623 i.tm.opcode_modifier.evex = EVEX512;
3624 else if (i.types[op].bitfield.ymmword)
3625 i.tm.opcode_modifier.evex = EVEX256;
3626 else if (i.types[op].bitfield.xmmword)
3627 i.tm.opcode_modifier.evex = EVEX128;
3628 else if (i.broadcast && (int) op == i.broadcast->operand)
3630 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3631 * i.broadcast->type)
3634 i.tm.opcode_modifier.evex = EVEX512;
3637 i.tm.opcode_modifier.evex = EVEX256;
3640 i.tm.opcode_modifier.evex = EVEX128;
3651 switch (i.tm.opcode_modifier.evex)
3653 case EVEXLIG: /* LL' is ignored */
3654 vec_length = evexlig << 5;
3657 vec_length = 0 << 5;
3660 vec_length = 1 << 5;
3663 vec_length = 2 << 5;
3669 i.vex.bytes[3] |= vec_length;
3670 /* Encode the broadcast bit. */
3672 i.vex.bytes[3] |= 0x10;
3676 if (i.rounding->type != saeonly)
3677 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3679 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3682 if (i.mask && i.mask->mask)
3683 i.vex.bytes[3] |= i.mask->mask->reg_num;
3687 process_immext (void)
3691 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3694 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3695 with an opcode suffix which is coded in the same place as an
3696 8-bit immediate field would be.
3697 Here we check those operands and remove them afterwards. */
3700 for (x = 0; x < i.operands; x++)
3701 if (register_number (i.op[x].regs) != x)
3702 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3703 register_prefix, i.op[x].regs->reg_name, x + 1,
3709 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3711 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3712 suffix which is coded in the same place as an 8-bit immediate
3714 Here we check those operands and remove them afterwards. */
3717 if (i.operands != 3)
3720 for (x = 0; x < 2; x++)
3721 if (register_number (i.op[x].regs) != x)
3722 goto bad_register_operand;
3724 /* Check for third operand for mwaitx/monitorx insn. */
3725 if (register_number (i.op[x].regs)
3726 != (x + (i.tm.extension_opcode == 0xfb)))
3728 bad_register_operand:
3729 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3730 register_prefix, i.op[x].regs->reg_name, x+1,
3737 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3738 which is coded in the same place as an 8-bit immediate field
3739 would be. Here we fake an 8-bit immediate operand from the
3740 opcode suffix stored in tm.extension_opcode.
3742 AVX instructions also use this encoding, for some of
3743 3 argument instructions. */
3745 gas_assert (i.imm_operands <= 1
3747 || ((i.tm.opcode_modifier.vex
3748 || i.tm.opcode_modifier.vexopcode
3749 || is_evex_encoding (&i.tm))
3750 && i.operands <= 4)));
3752 exp = &im_expressions[i.imm_operands++];
3753 i.op[i.operands].imms = exp;
3754 i.types[i.operands] = imm8;
3756 exp->X_op = O_constant;
3757 exp->X_add_number = i.tm.extension_opcode;
3758 i.tm.extension_opcode = None;
3765 switch (i.tm.opcode_modifier.hleprefixok)
3770 as_bad (_("invalid instruction `%s' after `%s'"),
3771 i.tm.name, i.hle_prefix);
3774 if (i.prefix[LOCK_PREFIX])
3776 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3780 case HLEPrefixRelease:
3781 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3783 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3787 if (i.mem_operands == 0
3788 || !operand_type_check (i.types[i.operands - 1], anymem))
3790 as_bad (_("memory destination needed for instruction `%s'"
3791 " after `xrelease'"), i.tm.name);
3798 /* Try the shortest encoding by shortening operand size. */
3801 optimize_encoding (void)
3805 if (optimize_for_space
3806 && i.reg_operands == 1
3807 && i.imm_operands == 1
3808 && !i.types[1].bitfield.byte
3809 && i.op[0].imms->X_op == O_constant
3810 && fits_in_imm7 (i.op[0].imms->X_add_number)
3811 && ((i.tm.base_opcode == 0xa8
3812 && i.tm.extension_opcode == None)
3813 || (i.tm.base_opcode == 0xf6
3814 && i.tm.extension_opcode == 0x0)))
3817 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3819 unsigned int base_regnum = i.op[1].regs->reg_num;
3820 if (flag_code == CODE_64BIT || base_regnum < 4)
3822 i.types[1].bitfield.byte = 1;
3823 /* Ignore the suffix. */
3825 if (base_regnum >= 4
3826 && !(i.op[1].regs->reg_flags & RegRex))
3828 /* Handle SP, BP, SI and DI registers. */
3829 if (i.types[1].bitfield.word)
3831 else if (i.types[1].bitfield.dword)
3839 else if (flag_code == CODE_64BIT
3840 && ((i.types[1].bitfield.qword
3841 && i.reg_operands == 1
3842 && i.imm_operands == 1
3843 && i.op[0].imms->X_op == O_constant
3844 && ((i.tm.base_opcode == 0xb0
3845 && i.tm.extension_opcode == None
3846 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3847 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3848 && (((i.tm.base_opcode == 0x24
3849 || i.tm.base_opcode == 0xa8)
3850 && i.tm.extension_opcode == None)
3851 || (i.tm.base_opcode == 0x80
3852 && i.tm.extension_opcode == 0x4)
3853 || ((i.tm.base_opcode == 0xf6
3854 || i.tm.base_opcode == 0xc6)
3855 && i.tm.extension_opcode == 0x0)))))
3856 || (i.types[0].bitfield.qword
3857 && ((i.reg_operands == 2
3858 && i.op[0].regs == i.op[1].regs
3859 && ((i.tm.base_opcode == 0x30
3860 || i.tm.base_opcode == 0x28)
3861 && i.tm.extension_opcode == None))
3862 || (i.reg_operands == 1
3864 && i.tm.base_opcode == 0x30
3865 && i.tm.extension_opcode == None)))))
3868 andq $imm31, %r64 -> andl $imm31, %r32
3869 testq $imm31, %r64 -> testl $imm31, %r32
3870 xorq %r64, %r64 -> xorl %r32, %r32
3871 subq %r64, %r64 -> subl %r32, %r32
3872 movq $imm31, %r64 -> movl $imm31, %r32
3873 movq $imm32, %r64 -> movl $imm32, %r32
3875 i.tm.opcode_modifier.norex64 = 1;
3876 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3879 movq $imm31, %r64 -> movl $imm31, %r32
3880 movq $imm32, %r64 -> movl $imm32, %r32
3882 i.tm.operand_types[0].bitfield.imm32 = 1;
3883 i.tm.operand_types[0].bitfield.imm32s = 0;
3884 i.tm.operand_types[0].bitfield.imm64 = 0;
3885 i.types[0].bitfield.imm32 = 1;
3886 i.types[0].bitfield.imm32s = 0;
3887 i.types[0].bitfield.imm64 = 0;
3888 i.types[1].bitfield.dword = 1;
3889 i.types[1].bitfield.qword = 0;
3890 if (i.tm.base_opcode == 0xc6)
3893 movq $imm31, %r64 -> movl $imm31, %r32
3895 i.tm.base_opcode = 0xb0;
3896 i.tm.extension_opcode = None;
3897 i.tm.opcode_modifier.shortform = 1;
3898 i.tm.opcode_modifier.modrm = 0;
3902 else if (optimize > 1
3903 && i.reg_operands == 3
3904 && i.op[0].regs == i.op[1].regs
3905 && !i.types[2].bitfield.xmmword
3906 && (i.tm.opcode_modifier.vex
3907 || ((!i.mask || i.mask->zeroing)
3909 && is_evex_encoding (&i.tm)
3910 && (i.vec_encoding != vex_encoding_evex
3911 || i.tm.cpu_flags.bitfield.cpuavx512vl
3912 || (i.tm.operand_types[2].bitfield.zmmword
3913 && i.types[2].bitfield.ymmword)
3914 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3915 && ((i.tm.base_opcode == 0x55
3916 || i.tm.base_opcode == 0x6655
3917 || i.tm.base_opcode == 0x66df
3918 || i.tm.base_opcode == 0x57
3919 || i.tm.base_opcode == 0x6657
3920 || i.tm.base_opcode == 0x66ef
3921 || i.tm.base_opcode == 0x66f8
3922 || i.tm.base_opcode == 0x66f9
3923 || i.tm.base_opcode == 0x66fa
3924 || i.tm.base_opcode == 0x66fb)
3925 && i.tm.extension_opcode == None))
3928 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3930 EVEX VOP %zmmM, %zmmM, %zmmN
3931 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3933 EVEX VOP %ymmM, %ymmM, %ymmN
3934 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3935 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3936 VEX VOP %ymmM, %ymmM, %ymmN
3937 -> VEX VOP %xmmM, %xmmM, %xmmN
3938 VOP, one of vpandn and vpxor:
3939 VEX VOP %ymmM, %ymmM, %ymmN
3940 -> VEX VOP %xmmM, %xmmM, %xmmN
3941 VOP, one of vpandnd and vpandnq:
3942 EVEX VOP %zmmM, %zmmM, %zmmN
3943 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3944 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3945 EVEX VOP %ymmM, %ymmM, %ymmN
3946 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3947 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3948 VOP, one of vpxord and vpxorq:
3949 EVEX VOP %zmmM, %zmmM, %zmmN
3950 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3951 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3952 EVEX VOP %ymmM, %ymmM, %ymmN
3953 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3954 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3956 if (is_evex_encoding (&i.tm))
3958 if (i.vec_encoding == vex_encoding_evex)
3959 i.tm.opcode_modifier.evex = EVEX128;
3962 i.tm.opcode_modifier.vex = VEX128;
3963 i.tm.opcode_modifier.vexw = VEXW0;
3964 i.tm.opcode_modifier.evex = 0;
3968 i.tm.opcode_modifier.vex = VEX128;
3970 if (i.tm.opcode_modifier.vex)
3971 for (j = 0; j < 3; j++)
3973 i.types[j].bitfield.xmmword = 1;
3974 i.types[j].bitfield.ymmword = 0;
3979 /* This is the guts of the machine-dependent assembler. LINE points to a
3980 machine dependent instruction. This function is supposed to emit
3981 the frags/bytes it assembles to. */
3984 md_assemble (char *line)
3987 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3988 const insn_template *t;
3990 /* Initialize globals. */
3991 memset (&i, '\0', sizeof (i));
3992 for (j = 0; j < MAX_OPERANDS; j++)
3993 i.reloc[j] = NO_RELOC;
3994 memset (disp_expressions, '\0', sizeof (disp_expressions));
3995 memset (im_expressions, '\0', sizeof (im_expressions));
3996 save_stack_p = save_stack;
3998 /* First parse an instruction mnemonic & call i386_operand for the operands.
3999 We assume that the scrubber has arranged it so that line[0] is the valid
4000 start of a (possibly prefixed) mnemonic. */
4002 line = parse_insn (line, mnemonic);
4005 mnem_suffix = i.suffix;
4007 line = parse_operands (line, mnemonic);
4009 xfree (i.memop1_string);
4010 i.memop1_string = NULL;
4014 /* Now we've parsed the mnemonic into a set of templates, and have the
4015 operands at hand. */
4017 /* All intel opcodes have reversed operands except for "bound" and
4018 "enter". We also don't reverse intersegment "jmp" and "call"
4019 instructions with 2 immediate operands so that the immediate segment
4020 precedes the offset, as it does when in AT&T mode. */
4023 && (strcmp (mnemonic, "bound") != 0)
4024 && (strcmp (mnemonic, "invlpga") != 0)
4025 && !(operand_type_check (i.types[0], imm)
4026 && operand_type_check (i.types[1], imm)))
4029 /* The order of the immediates should be reversed
4030 for 2 immediates extrq and insertq instructions */
4031 if (i.imm_operands == 2
4032 && (strcmp (mnemonic, "extrq") == 0
4033 || strcmp (mnemonic, "insertq") == 0))
4034 swap_2_operands (0, 1);
4039 /* Don't optimize displacement for movabs since it only takes 64bit
4042 && i.disp_encoding != disp_encoding_32bit
4043 && (flag_code != CODE_64BIT
4044 || strcmp (mnemonic, "movabs") != 0))
4047 /* Next, we find a template that matches the given insn,
4048 making sure the overlap of the given operands types is consistent
4049 with the template operand types. */
4051 if (!(t = match_template (mnem_suffix)))
4054 if (sse_check != check_none
4055 && !i.tm.opcode_modifier.noavx
4056 && !i.tm.cpu_flags.bitfield.cpuavx
4057 && (i.tm.cpu_flags.bitfield.cpusse
4058 || i.tm.cpu_flags.bitfield.cpusse2
4059 || i.tm.cpu_flags.bitfield.cpusse3
4060 || i.tm.cpu_flags.bitfield.cpussse3
4061 || i.tm.cpu_flags.bitfield.cpusse4_1
4062 || i.tm.cpu_flags.bitfield.cpusse4_2
4063 || i.tm.cpu_flags.bitfield.cpupclmul
4064 || i.tm.cpu_flags.bitfield.cpuaes
4065 || i.tm.cpu_flags.bitfield.cpugfni))
4067 (sse_check == check_warning
4069 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4072 /* Zap movzx and movsx suffix. The suffix has been set from
4073 "word ptr" or "byte ptr" on the source operand in Intel syntax
4074 or extracted from mnemonic in AT&T syntax. But we'll use
4075 the destination register to choose the suffix for encoding. */
4076 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4078 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4079 there is no suffix, the default will be byte extension. */
4080 if (i.reg_operands != 2
4083 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4088 if (i.tm.opcode_modifier.fwait)
4089 if (!add_prefix (FWAIT_OPCODE))
4092 /* Check if REP prefix is OK. */
4093 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4095 as_bad (_("invalid instruction `%s' after `%s'"),
4096 i.tm.name, i.rep_prefix);
4100 /* Check for lock without a lockable instruction. Destination operand
4101 must be memory unless it is xchg (0x86). */
4102 if (i.prefix[LOCK_PREFIX]
4103 && (!i.tm.opcode_modifier.islockable
4104 || i.mem_operands == 0
4105 || (i.tm.base_opcode != 0x86
4106 && !operand_type_check (i.types[i.operands - 1], anymem))))
4108 as_bad (_("expecting lockable instruction after `lock'"));
4112 /* Check if HLE prefix is OK. */
4113 if (i.hle_prefix && !check_hle ())
4116 /* Check BND prefix. */
4117 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4118 as_bad (_("expecting valid branch instruction after `bnd'"));
4120 /* Check NOTRACK prefix. */
4121 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4122 as_bad (_("expecting indirect branch instruction after `notrack'"));
4124 if (i.tm.cpu_flags.bitfield.cpumpx)
4126 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4127 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4128 else if (flag_code != CODE_16BIT
4129 ? i.prefix[ADDR_PREFIX]
4130 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4131 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4134 /* Insert BND prefix. */
4135 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4137 if (!i.prefix[BND_PREFIX])
4138 add_prefix (BND_PREFIX_OPCODE);
4139 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4141 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4142 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4146 /* Check string instruction segment overrides. */
4147 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4149 if (!check_string ())
4151 i.disp_operands = 0;
4154 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4155 optimize_encoding ();
4157 if (!process_suffix ())
4160 /* Update operand types. */
4161 for (j = 0; j < i.operands; j++)
4162 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4164 /* Make still unresolved immediate matches conform to size of immediate
4165 given in i.suffix. */
4166 if (!finalize_imm ())
4169 if (i.types[0].bitfield.imm1)
4170 i.imm_operands = 0; /* kludge for shift insns. */
4172 /* We only need to check those implicit registers for instructions
4173 with 3 operands or less. */
4174 if (i.operands <= 3)
4175 for (j = 0; j < i.operands; j++)
4176 if (i.types[j].bitfield.inoutportreg
4177 || i.types[j].bitfield.shiftcount
4178 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4181 /* ImmExt should be processed after SSE2AVX. */
4182 if (!i.tm.opcode_modifier.sse2avx
4183 && i.tm.opcode_modifier.immext)
4186 /* For insns with operands there are more diddles to do to the opcode. */
4189 if (!process_operands ())
4192 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4194 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4195 as_warn (_("translating to `%sp'"), i.tm.name);
4198 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4199 || is_evex_encoding (&i.tm))
4201 if (flag_code == CODE_16BIT)
4203 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4208 if (i.tm.opcode_modifier.vex)
4209 build_vex_prefix (t);
4211 build_evex_prefix ();
4214 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4215 instructions may define INT_OPCODE as well, so avoid this corner
4216 case for those instructions that use MODRM. */
4217 if (i.tm.base_opcode == INT_OPCODE
4218 && !i.tm.opcode_modifier.modrm
4219 && i.op[0].imms->X_add_number == 3)
4221 i.tm.base_opcode = INT3_OPCODE;
4225 if ((i.tm.opcode_modifier.jump
4226 || i.tm.opcode_modifier.jumpbyte
4227 || i.tm.opcode_modifier.jumpdword)
4228 && i.op[0].disps->X_op == O_constant)
4230 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4231 the absolute address given by the constant. Since ix86 jumps and
4232 calls are pc relative, we need to generate a reloc. */
4233 i.op[0].disps->X_add_symbol = &abs_symbol;
4234 i.op[0].disps->X_op = O_symbol;
4237 if (i.tm.opcode_modifier.rex64)
4240 /* For 8 bit registers we need an empty rex prefix. Also if the
4241 instruction already has a prefix, we need to convert old
4242 registers to new ones. */
4244 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4245 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4246 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4247 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4248 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4249 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4254 i.rex |= REX_OPCODE;
4255 for (x = 0; x < 2; x++)
4257 /* Look for 8 bit operand that uses old registers. */
4258 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4259 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4261 /* In case it is "hi" register, give up. */
4262 if (i.op[x].regs->reg_num > 3)
4263 as_bad (_("can't encode register '%s%s' in an "
4264 "instruction requiring REX prefix."),
4265 register_prefix, i.op[x].regs->reg_name);
4267 /* Otherwise it is equivalent to the extended register.
4268 Since the encoding doesn't change this is merely
4269 cosmetic cleanup for debug output. */
4271 i.op[x].regs = i.op[x].regs + 8;
4276 if (i.rex == 0 && i.rex_encoding)
4278 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4279 that uses legacy register. If it is "hi" register, don't add
4280 the REX_OPCODE byte. */
4282 for (x = 0; x < 2; x++)
4283 if (i.types[x].bitfield.reg
4284 && i.types[x].bitfield.byte
4285 && (i.op[x].regs->reg_flags & RegRex64) == 0
4286 && i.op[x].regs->reg_num > 3)
4288 i.rex_encoding = FALSE;
4297 add_prefix (REX_OPCODE | i.rex);
4299 /* We are ready to output the insn. */
4304 parse_insn (char *line, char *mnemonic)
4307 char *token_start = l;
4310 const insn_template *t;
4316 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4321 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4323 as_bad (_("no such instruction: `%s'"), token_start);
4328 if (!is_space_char (*l)
4329 && *l != END_OF_INSN
4331 || (*l != PREFIX_SEPARATOR
4334 as_bad (_("invalid character %s in mnemonic"),
4335 output_invalid (*l));
4338 if (token_start == l)
4340 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4341 as_bad (_("expecting prefix; got nothing"));
4343 as_bad (_("expecting mnemonic; got nothing"));
4347 /* Look up instruction (or prefix) via hash table. */
4348 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4350 if (*l != END_OF_INSN
4351 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4352 && current_templates
4353 && current_templates->start->opcode_modifier.isprefix)
4355 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4357 as_bad ((flag_code != CODE_64BIT
4358 ? _("`%s' is only supported in 64-bit mode")
4359 : _("`%s' is not supported in 64-bit mode")),
4360 current_templates->start->name);
4363 /* If we are in 16-bit mode, do not allow addr16 or data16.
4364 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4365 if ((current_templates->start->opcode_modifier.size16
4366 || current_templates->start->opcode_modifier.size32)
4367 && flag_code != CODE_64BIT
4368 && (current_templates->start->opcode_modifier.size32
4369 ^ (flag_code == CODE_16BIT)))
4371 as_bad (_("redundant %s prefix"),
4372 current_templates->start->name);
4375 if (current_templates->start->opcode_length == 0)
4377 /* Handle pseudo prefixes. */
4378 switch (current_templates->start->base_opcode)
4382 i.disp_encoding = disp_encoding_8bit;
4386 i.disp_encoding = disp_encoding_32bit;
4390 i.dir_encoding = dir_encoding_load;
4394 i.dir_encoding = dir_encoding_store;
4398 i.vec_encoding = vex_encoding_vex2;
4402 i.vec_encoding = vex_encoding_vex3;
4406 i.vec_encoding = vex_encoding_evex;
4410 i.rex_encoding = TRUE;
4414 i.no_optimize = TRUE;
4422 /* Add prefix, checking for repeated prefixes. */
4423 switch (add_prefix (current_templates->start->base_opcode))
4428 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4429 i.notrack_prefix = current_templates->start->name;
4432 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4433 i.hle_prefix = current_templates->start->name;
4434 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4435 i.bnd_prefix = current_templates->start->name;
4437 i.rep_prefix = current_templates->start->name;
4443 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4450 if (!current_templates)
4452 /* Check if we should swap operand or force 32bit displacement in
4454 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4455 i.dir_encoding = dir_encoding_store;
4456 else if (mnem_p - 3 == dot_p
4459 i.disp_encoding = disp_encoding_8bit;
4460 else if (mnem_p - 4 == dot_p
4464 i.disp_encoding = disp_encoding_32bit;
4469 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4472 if (!current_templates)
4475 /* See if we can get a match by trimming off a suffix. */
4478 case WORD_MNEM_SUFFIX:
4479 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4480 i.suffix = SHORT_MNEM_SUFFIX;
4483 case BYTE_MNEM_SUFFIX:
4484 case QWORD_MNEM_SUFFIX:
4485 i.suffix = mnem_p[-1];
4487 current_templates = (const templates *) hash_find (op_hash,
4490 case SHORT_MNEM_SUFFIX:
4491 case LONG_MNEM_SUFFIX:
4494 i.suffix = mnem_p[-1];
4496 current_templates = (const templates *) hash_find (op_hash,
4505 if (intel_float_operand (mnemonic) == 1)
4506 i.suffix = SHORT_MNEM_SUFFIX;
4508 i.suffix = LONG_MNEM_SUFFIX;
4510 current_templates = (const templates *) hash_find (op_hash,
4515 if (!current_templates)
4517 as_bad (_("no such instruction: `%s'"), token_start);
4522 if (current_templates->start->opcode_modifier.jump
4523 || current_templates->start->opcode_modifier.jumpbyte)
4525 /* Check for a branch hint. We allow ",pt" and ",pn" for
4526 predict taken and predict not taken respectively.
4527 I'm not sure that branch hints actually do anything on loop
4528 and jcxz insns (JumpByte) for current Pentium4 chips. They
4529 may work in the future and it doesn't hurt to accept them
4531 if (l[0] == ',' && l[1] == 'p')
4535 if (!add_prefix (DS_PREFIX_OPCODE))
4539 else if (l[2] == 'n')
4541 if (!add_prefix (CS_PREFIX_OPCODE))
4547 /* Any other comma loses. */
4550 as_bad (_("invalid character %s in mnemonic"),
4551 output_invalid (*l));
4555 /* Check if instruction is supported on specified architecture. */
4557 for (t = current_templates->start; t < current_templates->end; ++t)
4559 supported |= cpu_flags_match (t);
4560 if (supported == CPU_FLAGS_PERFECT_MATCH)
4562 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4563 as_warn (_("use .code16 to ensure correct addressing mode"));
4569 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4570 as_bad (flag_code == CODE_64BIT
4571 ? _("`%s' is not supported in 64-bit mode")
4572 : _("`%s' is only supported in 64-bit mode"),
4573 current_templates->start->name);
4575 as_bad (_("`%s' is not supported on `%s%s'"),
4576 current_templates->start->name,
4577 cpu_arch_name ? cpu_arch_name : default_arch,
4578 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4584 parse_operands (char *l, const char *mnemonic)
4588 /* 1 if operand is pending after ','. */
4589 unsigned int expecting_operand = 0;
4591 /* Non-zero if operand parens not balanced. */
4592 unsigned int paren_not_balanced;
4594 while (*l != END_OF_INSN)
4596 /* Skip optional white space before operand. */
4597 if (is_space_char (*l))
4599 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4601 as_bad (_("invalid character %s before operand %d"),
4602 output_invalid (*l),
4606 token_start = l; /* After white space. */
4607 paren_not_balanced = 0;
4608 while (paren_not_balanced || *l != ',')
4610 if (*l == END_OF_INSN)
4612 if (paren_not_balanced)
4615 as_bad (_("unbalanced parenthesis in operand %d."),
4618 as_bad (_("unbalanced brackets in operand %d."),
4623 break; /* we are done */
4625 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4627 as_bad (_("invalid character %s in operand %d"),
4628 output_invalid (*l),
4635 ++paren_not_balanced;
4637 --paren_not_balanced;
4642 ++paren_not_balanced;
4644 --paren_not_balanced;
4648 if (l != token_start)
4649 { /* Yes, we've read in another operand. */
4650 unsigned int operand_ok;
4651 this_operand = i.operands++;
4652 if (i.operands > MAX_OPERANDS)
4654 as_bad (_("spurious operands; (%d operands/instruction max)"),
4658 i.types[this_operand].bitfield.unspecified = 1;
4659 /* Now parse operand adding info to 'i' as we go along. */
4660 END_STRING_AND_SAVE (l);
4664 i386_intel_operand (token_start,
4665 intel_float_operand (mnemonic));
4667 operand_ok = i386_att_operand (token_start);
4669 RESTORE_END_STRING (l);
4675 if (expecting_operand)
4677 expecting_operand_after_comma:
4678 as_bad (_("expecting operand after ','; got nothing"));
4683 as_bad (_("expecting operand before ','; got nothing"));
4688 /* Now *l must be either ',' or END_OF_INSN. */
4691 if (*++l == END_OF_INSN)
4693 /* Just skip it, if it's \n complain. */
4694 goto expecting_operand_after_comma;
4696 expecting_operand = 1;
4703 swap_2_operands (int xchg1, int xchg2)
4705 union i386_op temp_op;
4706 i386_operand_type temp_type;
4707 enum bfd_reloc_code_real temp_reloc;
4709 temp_type = i.types[xchg2];
4710 i.types[xchg2] = i.types[xchg1];
4711 i.types[xchg1] = temp_type;
4712 temp_op = i.op[xchg2];
4713 i.op[xchg2] = i.op[xchg1];
4714 i.op[xchg1] = temp_op;
4715 temp_reloc = i.reloc[xchg2];
4716 i.reloc[xchg2] = i.reloc[xchg1];
4717 i.reloc[xchg1] = temp_reloc;
4721 if (i.mask->operand == xchg1)
4722 i.mask->operand = xchg2;
4723 else if (i.mask->operand == xchg2)
4724 i.mask->operand = xchg1;
4728 if (i.broadcast->operand == xchg1)
4729 i.broadcast->operand = xchg2;
4730 else if (i.broadcast->operand == xchg2)
4731 i.broadcast->operand = xchg1;
4735 if (i.rounding->operand == xchg1)
4736 i.rounding->operand = xchg2;
4737 else if (i.rounding->operand == xchg2)
4738 i.rounding->operand = xchg1;
4743 swap_operands (void)
4749 swap_2_operands (1, i.operands - 2);
4753 swap_2_operands (0, i.operands - 1);
4759 if (i.mem_operands == 2)
4761 const seg_entry *temp_seg;
4762 temp_seg = i.seg[0];
4763 i.seg[0] = i.seg[1];
4764 i.seg[1] = temp_seg;
4768 /* Try to ensure constant immediates are represented in the smallest
4773 char guess_suffix = 0;
4777 guess_suffix = i.suffix;
4778 else if (i.reg_operands)
4780 /* Figure out a suffix from the last register operand specified.
4781 We can't do this properly yet, ie. excluding InOutPortReg,
4782 but the following works for instructions with immediates.
4783 In any case, we can't set i.suffix yet. */
4784 for (op = i.operands; --op >= 0;)
4785 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4787 guess_suffix = BYTE_MNEM_SUFFIX;
4790 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4792 guess_suffix = WORD_MNEM_SUFFIX;
4795 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4797 guess_suffix = LONG_MNEM_SUFFIX;
4800 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4802 guess_suffix = QWORD_MNEM_SUFFIX;
4806 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4807 guess_suffix = WORD_MNEM_SUFFIX;
4809 for (op = i.operands; --op >= 0;)
4810 if (operand_type_check (i.types[op], imm))
4812 switch (i.op[op].imms->X_op)
4815 /* If a suffix is given, this operand may be shortened. */
4816 switch (guess_suffix)
4818 case LONG_MNEM_SUFFIX:
4819 i.types[op].bitfield.imm32 = 1;
4820 i.types[op].bitfield.imm64 = 1;
4822 case WORD_MNEM_SUFFIX:
4823 i.types[op].bitfield.imm16 = 1;
4824 i.types[op].bitfield.imm32 = 1;
4825 i.types[op].bitfield.imm32s = 1;
4826 i.types[op].bitfield.imm64 = 1;
4828 case BYTE_MNEM_SUFFIX:
4829 i.types[op].bitfield.imm8 = 1;
4830 i.types[op].bitfield.imm8s = 1;
4831 i.types[op].bitfield.imm16 = 1;
4832 i.types[op].bitfield.imm32 = 1;
4833 i.types[op].bitfield.imm32s = 1;
4834 i.types[op].bitfield.imm64 = 1;
4838 /* If this operand is at most 16 bits, convert it
4839 to a signed 16 bit number before trying to see
4840 whether it will fit in an even smaller size.
4841 This allows a 16-bit operand such as $0xffe0 to
4842 be recognised as within Imm8S range. */
4843 if ((i.types[op].bitfield.imm16)
4844 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4846 i.op[op].imms->X_add_number =
4847 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4850 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4851 if ((i.types[op].bitfield.imm32)
4852 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4855 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4856 ^ ((offsetT) 1 << 31))
4857 - ((offsetT) 1 << 31));
4861 = operand_type_or (i.types[op],
4862 smallest_imm_type (i.op[op].imms->X_add_number));
4864 /* We must avoid matching of Imm32 templates when 64bit
4865 only immediate is available. */
4866 if (guess_suffix == QWORD_MNEM_SUFFIX)
4867 i.types[op].bitfield.imm32 = 0;
4874 /* Symbols and expressions. */
4876 /* Convert symbolic operand to proper sizes for matching, but don't
4877 prevent matching a set of insns that only supports sizes other
4878 than those matching the insn suffix. */
4880 i386_operand_type mask, allowed;
4881 const insn_template *t;
4883 operand_type_set (&mask, 0);
4884 operand_type_set (&allowed, 0);
4886 for (t = current_templates->start;
4887 t < current_templates->end;
4889 allowed = operand_type_or (allowed,
4890 t->operand_types[op]);
4891 switch (guess_suffix)
4893 case QWORD_MNEM_SUFFIX:
4894 mask.bitfield.imm64 = 1;
4895 mask.bitfield.imm32s = 1;
4897 case LONG_MNEM_SUFFIX:
4898 mask.bitfield.imm32 = 1;
4900 case WORD_MNEM_SUFFIX:
4901 mask.bitfield.imm16 = 1;
4903 case BYTE_MNEM_SUFFIX:
4904 mask.bitfield.imm8 = 1;
4909 allowed = operand_type_and (mask, allowed);
4910 if (!operand_type_all_zero (&allowed))
4911 i.types[op] = operand_type_and (i.types[op], mask);
4918 /* Try to use the smallest displacement type too. */
4920 optimize_disp (void)
4924 for (op = i.operands; --op >= 0;)
4925 if (operand_type_check (i.types[op], disp))
4927 if (i.op[op].disps->X_op == O_constant)
4929 offsetT op_disp = i.op[op].disps->X_add_number;
4931 if (i.types[op].bitfield.disp16
4932 && (op_disp & ~(offsetT) 0xffff) == 0)
4934 /* If this operand is at most 16 bits, convert
4935 to a signed 16 bit number and don't use 64bit
4937 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4938 i.types[op].bitfield.disp64 = 0;
4941 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4942 if (i.types[op].bitfield.disp32
4943 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4945 /* If this operand is at most 32 bits, convert
4946 to a signed 32 bit number and don't use 64bit
4948 op_disp &= (((offsetT) 2 << 31) - 1);
4949 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4950 i.types[op].bitfield.disp64 = 0;
4953 if (!op_disp && i.types[op].bitfield.baseindex)
4955 i.types[op].bitfield.disp8 = 0;
4956 i.types[op].bitfield.disp16 = 0;
4957 i.types[op].bitfield.disp32 = 0;
4958 i.types[op].bitfield.disp32s = 0;
4959 i.types[op].bitfield.disp64 = 0;
4963 else if (flag_code == CODE_64BIT)
4965 if (fits_in_signed_long (op_disp))
4967 i.types[op].bitfield.disp64 = 0;
4968 i.types[op].bitfield.disp32s = 1;
4970 if (i.prefix[ADDR_PREFIX]
4971 && fits_in_unsigned_long (op_disp))
4972 i.types[op].bitfield.disp32 = 1;
4974 if ((i.types[op].bitfield.disp32
4975 || i.types[op].bitfield.disp32s
4976 || i.types[op].bitfield.disp16)
4977 && fits_in_disp8 (op_disp))
4978 i.types[op].bitfield.disp8 = 1;
4980 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4981 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4983 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4984 i.op[op].disps, 0, i.reloc[op]);
4985 i.types[op].bitfield.disp8 = 0;
4986 i.types[op].bitfield.disp16 = 0;
4987 i.types[op].bitfield.disp32 = 0;
4988 i.types[op].bitfield.disp32s = 0;
4989 i.types[op].bitfield.disp64 = 0;
4992 /* We only support 64bit displacement on constants. */
4993 i.types[op].bitfield.disp64 = 0;
4997 /* Check if operands are valid for the instruction. */
5000 check_VecOperands (const insn_template *t)
5004 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5006 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5007 any one operand are implicity requiring AVX512VL support if the actual
5008 operand size is YMMword or XMMword. Since this function runs after
5009 template matching, there's no need to check for YMMword/XMMword in
5011 cpu = cpu_flags_and (t->cpu_flags, avx512);
5012 if (!cpu_flags_all_zero (&cpu)
5013 && !t->cpu_flags.bitfield.cpuavx512vl
5014 && !cpu_arch_flags.bitfield.cpuavx512vl)
5016 for (op = 0; op < t->operands; ++op)
5018 if (t->operand_types[op].bitfield.zmmword
5019 && (i.types[op].bitfield.ymmword
5020 || i.types[op].bitfield.xmmword))
5022 i.error = unsupported;
5028 /* Without VSIB byte, we can't have a vector register for index. */
5029 if (!t->opcode_modifier.vecsib
5031 && (i.index_reg->reg_type.bitfield.xmmword
5032 || i.index_reg->reg_type.bitfield.ymmword
5033 || i.index_reg->reg_type.bitfield.zmmword))
5035 i.error = unsupported_vector_index_register;
5039 /* Check if default mask is allowed. */
5040 if (t->opcode_modifier.nodefmask
5041 && (!i.mask || i.mask->mask->reg_num == 0))
5043 i.error = no_default_mask;
5047 /* For VSIB byte, we need a vector register for index, and all vector
5048 registers must be distinct. */
5049 if (t->opcode_modifier.vecsib)
5052 || !((t->opcode_modifier.vecsib == VecSIB128
5053 && i.index_reg->reg_type.bitfield.xmmword)
5054 || (t->opcode_modifier.vecsib == VecSIB256
5055 && i.index_reg->reg_type.bitfield.ymmword)
5056 || (t->opcode_modifier.vecsib == VecSIB512
5057 && i.index_reg->reg_type.bitfield.zmmword)))
5059 i.error = invalid_vsib_address;
5063 gas_assert (i.reg_operands == 2 || i.mask);
5064 if (i.reg_operands == 2 && !i.mask)
5066 gas_assert (i.types[0].bitfield.regsimd);
5067 gas_assert (i.types[0].bitfield.xmmword
5068 || i.types[0].bitfield.ymmword);
5069 gas_assert (i.types[2].bitfield.regsimd);
5070 gas_assert (i.types[2].bitfield.xmmword
5071 || i.types[2].bitfield.ymmword);
5072 if (operand_check == check_none)
5074 if (register_number (i.op[0].regs)
5075 != register_number (i.index_reg)
5076 && register_number (i.op[2].regs)
5077 != register_number (i.index_reg)
5078 && register_number (i.op[0].regs)
5079 != register_number (i.op[2].regs))
5081 if (operand_check == check_error)
5083 i.error = invalid_vector_register_set;
5086 as_warn (_("mask, index, and destination registers should be distinct"));
5088 else if (i.reg_operands == 1 && i.mask)
5090 if (i.types[1].bitfield.regsimd
5091 && (i.types[1].bitfield.xmmword
5092 || i.types[1].bitfield.ymmword
5093 || i.types[1].bitfield.zmmword)
5094 && (register_number (i.op[1].regs)
5095 == register_number (i.index_reg)))
5097 if (operand_check == check_error)
5099 i.error = invalid_vector_register_set;
5102 if (operand_check != check_none)
5103 as_warn (_("index and destination registers should be distinct"));
5108 /* Check if broadcast is supported by the instruction and is applied
5109 to the memory operand. */
5112 i386_operand_type type, overlap;
5114 /* Check if specified broadcast is supported in this instruction,
5115 and it's applied to memory operand of DWORD or QWORD type. */
5116 op = i.broadcast->operand;
5117 if (!t->opcode_modifier.broadcast
5118 || !i.types[op].bitfield.mem
5119 || (!i.types[op].bitfield.unspecified
5120 && (t->operand_types[op].bitfield.dword
5121 ? !i.types[op].bitfield.dword
5122 : !i.types[op].bitfield.qword)))
5125 i.error = unsupported_broadcast;
5129 operand_type_set (&type, 0);
5130 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5133 type.bitfield.qword = 1;
5136 type.bitfield.xmmword = 1;
5139 type.bitfield.ymmword = 1;
5142 type.bitfield.zmmword = 1;
5148 overlap = operand_type_and (type, t->operand_types[op]);
5149 if (operand_type_all_zero (&overlap))
5152 if (t->opcode_modifier.checkregsize)
5156 type.bitfield.baseindex = 1;
5157 for (j = 0; j < i.operands; ++j)
5160 && !operand_type_register_match(i.types[j],
5161 t->operand_types[j],
5163 t->operand_types[op]))
5168 /* If broadcast is supported in this instruction, we need to check if
5169 operand of one-element size isn't specified without broadcast. */
5170 else if (t->opcode_modifier.broadcast && i.mem_operands)
5172 /* Find memory operand. */
5173 for (op = 0; op < i.operands; op++)
5174 if (operand_type_check (i.types[op], anymem))
5176 gas_assert (op < i.operands);
5177 /* Check size of the memory operand. */
5178 if (t->operand_types[op].bitfield.dword
5179 ? i.types[op].bitfield.dword
5180 : i.types[op].bitfield.qword)
5182 i.error = broadcast_needed;
5187 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5189 /* Check if requested masking is supported. */
5191 && (!t->opcode_modifier.masking
5193 && t->opcode_modifier.masking == MERGING_MASKING)))
5195 i.error = unsupported_masking;
5199 /* Check if masking is applied to dest operand. */
5200 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5202 i.error = mask_not_on_destination;
5209 if ((i.rounding->type != saeonly
5210 && !t->opcode_modifier.staticrounding)
5211 || (i.rounding->type == saeonly
5212 && (t->opcode_modifier.staticrounding
5213 || !t->opcode_modifier.sae)))
5215 i.error = unsupported_rc_sae;
5218 /* If the instruction has several immediate operands and one of
5219 them is rounding, the rounding operand should be the last
5220 immediate operand. */
5221 if (i.imm_operands > 1
5222 && i.rounding->operand != (int) (i.imm_operands - 1))
5224 i.error = rc_sae_operand_not_last_imm;
5229 /* Check vector Disp8 operand. */
5230 if (t->opcode_modifier.disp8memshift
5231 && i.disp_encoding != disp_encoding_32bit)
5234 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5235 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5236 i.memshift = t->opcode_modifier.disp8memshift;
5239 const i386_operand_type *type = NULL;
5242 for (op = 0; op < i.operands; op++)
5243 if (operand_type_check (i.types[op], anymem))
5245 if (t->operand_types[op].bitfield.xmmword
5246 + t->operand_types[op].bitfield.ymmword
5247 + t->operand_types[op].bitfield.zmmword <= 1)
5248 type = &t->operand_types[op];
5249 else if (!i.types[op].bitfield.unspecified)
5250 type = &i.types[op];
5252 else if (i.types[op].bitfield.regsimd)
5254 if (i.types[op].bitfield.zmmword)
5256 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5258 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5264 if (type->bitfield.zmmword)
5266 else if (type->bitfield.ymmword)
5268 else if (type->bitfield.xmmword)
5272 /* For the check in fits_in_disp8(). */
5273 if (i.memshift == 0)
5277 for (op = 0; op < i.operands; op++)
5278 if (operand_type_check (i.types[op], disp)
5279 && i.op[op].disps->X_op == O_constant)
5281 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5283 i.types[op].bitfield.disp8 = 1;
5286 i.types[op].bitfield.disp8 = 0;
5295 /* Check if operands are valid for the instruction. Update VEX
5299 VEX_check_operands (const insn_template *t)
5301 if (i.vec_encoding == vex_encoding_evex)
5303 /* This instruction must be encoded with EVEX prefix. */
5304 if (!is_evex_encoding (t))
5306 i.error = unsupported;
5312 if (!t->opcode_modifier.vex)
5314 /* This instruction template doesn't have VEX prefix. */
5315 if (i.vec_encoding != vex_encoding_default)
5317 i.error = unsupported;
5323 /* Only check VEX_Imm4, which must be the first operand. */
5324 if (t->operand_types[0].bitfield.vec_imm4)
5326 if (i.op[0].imms->X_op != O_constant
5327 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5333 /* Turn off Imm8 so that update_imm won't complain. */
5334 i.types[0] = vec_imm4;
5340 static const insn_template *
5341 match_template (char mnem_suffix)
5343 /* Points to template once we've found it. */
5344 const insn_template *t;
5345 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5346 i386_operand_type overlap4;
5347 unsigned int found_reverse_match;
5348 i386_opcode_modifier suffix_check, mnemsuf_check;
5349 i386_operand_type operand_types [MAX_OPERANDS];
5350 int addr_prefix_disp;
5352 unsigned int found_cpu_match, size_match;
5353 unsigned int check_register;
5354 enum i386_error specific_error = 0;
5356 #if MAX_OPERANDS != 5
5357 # error "MAX_OPERANDS must be 5."
5360 found_reverse_match = 0;
5361 addr_prefix_disp = -1;
5363 memset (&suffix_check, 0, sizeof (suffix_check));
5364 if (intel_syntax && i.broadcast)
5366 else if (i.suffix == BYTE_MNEM_SUFFIX)
5367 suffix_check.no_bsuf = 1;
5368 else if (i.suffix == WORD_MNEM_SUFFIX)
5369 suffix_check.no_wsuf = 1;
5370 else if (i.suffix == SHORT_MNEM_SUFFIX)
5371 suffix_check.no_ssuf = 1;
5372 else if (i.suffix == LONG_MNEM_SUFFIX)
5373 suffix_check.no_lsuf = 1;
5374 else if (i.suffix == QWORD_MNEM_SUFFIX)
5375 suffix_check.no_qsuf = 1;
5376 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5377 suffix_check.no_ldsuf = 1;
5379 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5382 switch (mnem_suffix)
5384 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5385 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5386 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5387 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5388 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5392 /* Must have right number of operands. */
5393 i.error = number_of_operands_mismatch;
5395 for (t = current_templates->start; t < current_templates->end; t++)
5397 addr_prefix_disp = -1;
5399 if (i.operands != t->operands)
5402 /* Check processor support. */
5403 i.error = unsupported;
5404 found_cpu_match = (cpu_flags_match (t)
5405 == CPU_FLAGS_PERFECT_MATCH);
5406 if (!found_cpu_match)
5409 /* Check AT&T mnemonic. */
5410 i.error = unsupported_with_intel_mnemonic;
5411 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5414 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5415 i.error = unsupported_syntax;
5416 if ((intel_syntax && t->opcode_modifier.attsyntax)
5417 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5418 || (intel64 && t->opcode_modifier.amd64)
5419 || (!intel64 && t->opcode_modifier.intel64))
5422 /* Check the suffix, except for some instructions in intel mode. */
5423 i.error = invalid_instruction_suffix;
5424 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5425 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5426 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5427 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5428 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5429 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5430 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5432 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5433 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5434 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5435 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5436 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5437 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5438 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5441 size_match = operand_size_match (t);
5445 for (j = 0; j < MAX_OPERANDS; j++)
5446 operand_types[j] = t->operand_types[j];
5448 /* In general, don't allow 64-bit operands in 32-bit mode. */
5449 if (i.suffix == QWORD_MNEM_SUFFIX
5450 && flag_code != CODE_64BIT
5452 ? (!t->opcode_modifier.ignoresize
5453 && !t->opcode_modifier.broadcast
5454 && !intel_float_operand (t->name))
5455 : intel_float_operand (t->name) != 2)
5456 && ((!operand_types[0].bitfield.regmmx
5457 && !operand_types[0].bitfield.regsimd)
5458 || (!operand_types[t->operands > 1].bitfield.regmmx
5459 && !operand_types[t->operands > 1].bitfield.regsimd))
5460 && (t->base_opcode != 0x0fc7
5461 || t->extension_opcode != 1 /* cmpxchg8b */))
5464 /* In general, don't allow 32-bit operands on pre-386. */
5465 else if (i.suffix == LONG_MNEM_SUFFIX
5466 && !cpu_arch_flags.bitfield.cpui386
5468 ? (!t->opcode_modifier.ignoresize
5469 && !intel_float_operand (t->name))
5470 : intel_float_operand (t->name) != 2)
5471 && ((!operand_types[0].bitfield.regmmx
5472 && !operand_types[0].bitfield.regsimd)
5473 || (!operand_types[t->operands > 1].bitfield.regmmx
5474 && !operand_types[t->operands > 1].bitfield.regsimd)))
5477 /* Do not verify operands when there are none. */
5481 /* We've found a match; break out of loop. */
5485 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5486 into Disp32/Disp16/Disp32 operand. */
5487 if (i.prefix[ADDR_PREFIX] != 0)
5489 /* There should be only one Disp operand. */
5493 for (j = 0; j < MAX_OPERANDS; j++)
5495 if (operand_types[j].bitfield.disp16)
5497 addr_prefix_disp = j;
5498 operand_types[j].bitfield.disp32 = 1;
5499 operand_types[j].bitfield.disp16 = 0;
5505 for (j = 0; j < MAX_OPERANDS; j++)
5507 if (operand_types[j].bitfield.disp32)
5509 addr_prefix_disp = j;
5510 operand_types[j].bitfield.disp32 = 0;
5511 operand_types[j].bitfield.disp16 = 1;
5517 for (j = 0; j < MAX_OPERANDS; j++)
5519 if (operand_types[j].bitfield.disp64)
5521 addr_prefix_disp = j;
5522 operand_types[j].bitfield.disp64 = 0;
5523 operand_types[j].bitfield.disp32 = 1;
5531 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5532 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5535 /* We check register size if needed. */
5536 if (t->opcode_modifier.checkregsize)
5538 check_register = (1 << t->operands) - 1;
5540 check_register &= ~(1 << i.broadcast->operand);
5545 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5546 switch (t->operands)
5549 if (!operand_type_match (overlap0, i.types[0]))
5553 /* xchg %eax, %eax is a special case. It is an alias for nop
5554 only in 32bit mode and we can use opcode 0x90. In 64bit
5555 mode, we can't use 0x90 for xchg %eax, %eax since it should
5556 zero-extend %eax to %rax. */
5557 if (flag_code == CODE_64BIT
5558 && t->base_opcode == 0x90
5559 && operand_type_equal (&i.types [0], &acc32)
5560 && operand_type_equal (&i.types [1], &acc32))
5562 /* xrelease mov %eax, <disp> is another special case. It must not
5563 match the accumulator-only encoding of mov. */
5564 if (flag_code != CODE_64BIT
5566 && t->base_opcode == 0xa0
5567 && i.types[0].bitfield.acc
5568 && operand_type_check (i.types[1], anymem))
5570 if (!(size_match & MATCH_STRAIGHT))
5572 /* If we want store form, we reverse direction of operands. */
5573 if (i.dir_encoding == dir_encoding_store
5574 && t->opcode_modifier.d)
5579 /* If we want store form, we skip the current load. */
5580 if (i.dir_encoding == dir_encoding_store
5581 && i.mem_operands == 0
5582 && t->opcode_modifier.load)
5587 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5588 if (!operand_type_match (overlap0, i.types[0])
5589 || !operand_type_match (overlap1, i.types[1])
5590 || ((check_register & 3) == 3
5591 && !operand_type_register_match (i.types[0],
5596 /* Check if other direction is valid ... */
5597 if (!t->opcode_modifier.d)
5601 if (!(size_match & MATCH_REVERSE))
5603 /* Try reversing direction of operands. */
5604 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5605 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5606 if (!operand_type_match (overlap0, i.types[0])
5607 || !operand_type_match (overlap1, i.types[1])
5609 && !operand_type_register_match (i.types[0],
5614 /* Does not match either direction. */
5617 /* found_reverse_match holds which of D or FloatR
5619 if (!t->opcode_modifier.d)
5620 found_reverse_match = 0;
5621 else if (operand_types[0].bitfield.tbyte)
5622 found_reverse_match = Opcode_FloatD;
5624 found_reverse_match = Opcode_D;
5625 if (t->opcode_modifier.floatr)
5626 found_reverse_match |= Opcode_FloatR;
5630 /* Found a forward 2 operand match here. */
5631 switch (t->operands)
5634 overlap4 = operand_type_and (i.types[4],
5638 overlap3 = operand_type_and (i.types[3],
5642 overlap2 = operand_type_and (i.types[2],
5647 switch (t->operands)
5650 if (!operand_type_match (overlap4, i.types[4])
5651 || !operand_type_register_match (i.types[3],
5658 if (!operand_type_match (overlap3, i.types[3])
5659 || ((check_register & 0xa) == 0xa
5660 && !operand_type_register_match (i.types[1],
5664 || ((check_register & 0xc) == 0xc
5665 && !operand_type_register_match (i.types[2],
5672 /* Here we make use of the fact that there are no
5673 reverse match 3 operand instructions. */
5674 if (!operand_type_match (overlap2, i.types[2])
5675 || ((check_register & 5) == 5
5676 && !operand_type_register_match (i.types[0],
5680 || ((check_register & 6) == 6
5681 && !operand_type_register_match (i.types[1],
5689 /* Found either forward/reverse 2, 3 or 4 operand match here:
5690 slip through to break. */
5692 if (!found_cpu_match)
5694 found_reverse_match = 0;
5698 /* Check if vector and VEX operands are valid. */
5699 if (check_VecOperands (t) || VEX_check_operands (t))
5701 specific_error = i.error;
5705 /* We've found a match; break out of loop. */
5709 if (t == current_templates->end)
5711 /* We found no match. */
5712 const char *err_msg;
5713 switch (specific_error ? specific_error : i.error)
5717 case operand_size_mismatch:
5718 err_msg = _("operand size mismatch");
5720 case operand_type_mismatch:
5721 err_msg = _("operand type mismatch");
5723 case register_type_mismatch:
5724 err_msg = _("register type mismatch");
5726 case number_of_operands_mismatch:
5727 err_msg = _("number of operands mismatch");
5729 case invalid_instruction_suffix:
5730 err_msg = _("invalid instruction suffix");
5733 err_msg = _("constant doesn't fit in 4 bits");
5735 case unsupported_with_intel_mnemonic:
5736 err_msg = _("unsupported with Intel mnemonic");
5738 case unsupported_syntax:
5739 err_msg = _("unsupported syntax");
5742 as_bad (_("unsupported instruction `%s'"),
5743 current_templates->start->name);
5745 case invalid_vsib_address:
5746 err_msg = _("invalid VSIB address");
5748 case invalid_vector_register_set:
5749 err_msg = _("mask, index, and destination registers must be distinct");
5751 case unsupported_vector_index_register:
5752 err_msg = _("unsupported vector index register");
5754 case unsupported_broadcast:
5755 err_msg = _("unsupported broadcast");
5757 case broadcast_not_on_src_operand:
5758 err_msg = _("broadcast not on source memory operand");
5760 case broadcast_needed:
5761 err_msg = _("broadcast is needed for operand of such type");
5763 case unsupported_masking:
5764 err_msg = _("unsupported masking");
5766 case mask_not_on_destination:
5767 err_msg = _("mask not on destination operand");
5769 case no_default_mask:
5770 err_msg = _("default mask isn't allowed");
5772 case unsupported_rc_sae:
5773 err_msg = _("unsupported static rounding/sae");
5775 case rc_sae_operand_not_last_imm:
5777 err_msg = _("RC/SAE operand must precede immediate operands");
5779 err_msg = _("RC/SAE operand must follow immediate operands");
5781 case invalid_register_operand:
5782 err_msg = _("invalid register operand");
5785 as_bad (_("%s for `%s'"), err_msg,
5786 current_templates->start->name);
5790 if (!quiet_warnings)
5793 && (i.types[0].bitfield.jumpabsolute
5794 != operand_types[0].bitfield.jumpabsolute))
5796 as_warn (_("indirect %s without `*'"), t->name);
5799 if (t->opcode_modifier.isprefix
5800 && t->opcode_modifier.ignoresize)
5802 /* Warn them that a data or address size prefix doesn't
5803 affect assembly of the next line of code. */
5804 as_warn (_("stand-alone `%s' prefix"), t->name);
5808 /* Copy the template we found. */
5811 if (addr_prefix_disp != -1)
5812 i.tm.operand_types[addr_prefix_disp]
5813 = operand_types[addr_prefix_disp];
5815 if (found_reverse_match)
5817 /* If we found a reverse match we must alter the opcode
5818 direction bit. found_reverse_match holds bits to change
5819 (different for int & float insns). */
5821 i.tm.base_opcode ^= found_reverse_match;
5823 i.tm.operand_types[0] = operand_types[1];
5824 i.tm.operand_types[1] = operand_types[0];
5833 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5834 if (i.tm.operand_types[mem_op].bitfield.esseg)
5836 if (i.seg[0] != NULL && i.seg[0] != &es)
5838 as_bad (_("`%s' operand %d must use `%ses' segment"),
5844 /* There's only ever one segment override allowed per instruction.
5845 This instruction possibly has a legal segment override on the
5846 second operand, so copy the segment to where non-string
5847 instructions store it, allowing common code. */
5848 i.seg[0] = i.seg[1];
5850 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5852 if (i.seg[1] != NULL && i.seg[1] != &es)
5854 as_bad (_("`%s' operand %d must use `%ses' segment"),
5865 process_suffix (void)
5867 /* If matched instruction specifies an explicit instruction mnemonic
5869 if (i.tm.opcode_modifier.size16)
5870 i.suffix = WORD_MNEM_SUFFIX;
5871 else if (i.tm.opcode_modifier.size32)
5872 i.suffix = LONG_MNEM_SUFFIX;
5873 else if (i.tm.opcode_modifier.size64)
5874 i.suffix = QWORD_MNEM_SUFFIX;
5875 else if (i.reg_operands)
5877 /* If there's no instruction mnemonic suffix we try to invent one
5878 based on register operands. */
5881 /* We take i.suffix from the last register operand specified,
5882 Destination register type is more significant than source
5883 register type. crc32 in SSE4.2 prefers source register
5885 if (i.tm.base_opcode == 0xf20f38f1)
5887 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5888 i.suffix = WORD_MNEM_SUFFIX;
5889 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5890 i.suffix = LONG_MNEM_SUFFIX;
5891 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5892 i.suffix = QWORD_MNEM_SUFFIX;
5894 else if (i.tm.base_opcode == 0xf20f38f0)
5896 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5897 i.suffix = BYTE_MNEM_SUFFIX;
5904 if (i.tm.base_opcode == 0xf20f38f1
5905 || i.tm.base_opcode == 0xf20f38f0)
5907 /* We have to know the operand size for crc32. */
5908 as_bad (_("ambiguous memory operand size for `%s`"),
5913 for (op = i.operands; --op >= 0;)
5914 if (!i.tm.operand_types[op].bitfield.inoutportreg
5915 && !i.tm.operand_types[op].bitfield.shiftcount)
5917 if (!i.types[op].bitfield.reg)
5919 if (i.types[op].bitfield.byte)
5920 i.suffix = BYTE_MNEM_SUFFIX;
5921 else if (i.types[op].bitfield.word)
5922 i.suffix = WORD_MNEM_SUFFIX;
5923 else if (i.types[op].bitfield.dword)
5924 i.suffix = LONG_MNEM_SUFFIX;
5925 else if (i.types[op].bitfield.qword)
5926 i.suffix = QWORD_MNEM_SUFFIX;
5933 else if (i.suffix == BYTE_MNEM_SUFFIX)
5936 && i.tm.opcode_modifier.ignoresize
5937 && i.tm.opcode_modifier.no_bsuf)
5939 else if (!check_byte_reg ())
5942 else if (i.suffix == LONG_MNEM_SUFFIX)
5945 && i.tm.opcode_modifier.ignoresize
5946 && i.tm.opcode_modifier.no_lsuf
5947 && !i.tm.opcode_modifier.todword
5948 && !i.tm.opcode_modifier.toqword)
5950 else if (!check_long_reg ())
5953 else if (i.suffix == QWORD_MNEM_SUFFIX)
5956 && i.tm.opcode_modifier.ignoresize
5957 && i.tm.opcode_modifier.no_qsuf
5958 && !i.tm.opcode_modifier.todword
5959 && !i.tm.opcode_modifier.toqword)
5961 else if (!check_qword_reg ())
5964 else if (i.suffix == WORD_MNEM_SUFFIX)
5967 && i.tm.opcode_modifier.ignoresize
5968 && i.tm.opcode_modifier.no_wsuf)
5970 else if (!check_word_reg ())
5973 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5974 /* Do nothing if the instruction is going to ignore the prefix. */
5979 else if (i.tm.opcode_modifier.defaultsize
5981 /* exclude fldenv/frstor/fsave/fstenv */
5982 && i.tm.opcode_modifier.no_ssuf)
5984 i.suffix = stackop_size;
5986 else if (intel_syntax
5988 && (i.tm.operand_types[0].bitfield.jumpabsolute
5989 || i.tm.opcode_modifier.jumpbyte
5990 || i.tm.opcode_modifier.jumpintersegment
5991 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5992 && i.tm.extension_opcode <= 3)))
5997 if (!i.tm.opcode_modifier.no_qsuf)
5999 i.suffix = QWORD_MNEM_SUFFIX;
6004 if (!i.tm.opcode_modifier.no_lsuf)
6005 i.suffix = LONG_MNEM_SUFFIX;
6008 if (!i.tm.opcode_modifier.no_wsuf)
6009 i.suffix = WORD_MNEM_SUFFIX;
6018 if (i.tm.opcode_modifier.w)
6020 as_bad (_("no instruction mnemonic suffix given and "
6021 "no register operands; can't size instruction"));
6027 unsigned int suffixes;
6029 suffixes = !i.tm.opcode_modifier.no_bsuf;
6030 if (!i.tm.opcode_modifier.no_wsuf)
6032 if (!i.tm.opcode_modifier.no_lsuf)
6034 if (!i.tm.opcode_modifier.no_ldsuf)
6036 if (!i.tm.opcode_modifier.no_ssuf)
6038 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6041 /* There are more than suffix matches. */
6042 if (i.tm.opcode_modifier.w
6043 || ((suffixes & (suffixes - 1))
6044 && !i.tm.opcode_modifier.defaultsize
6045 && !i.tm.opcode_modifier.ignoresize))
6047 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6053 /* Change the opcode based on the operand size given by i.suffix. */
6056 /* Size floating point instruction. */
6057 case LONG_MNEM_SUFFIX:
6058 if (i.tm.opcode_modifier.floatmf)
6060 i.tm.base_opcode ^= 4;
6064 case WORD_MNEM_SUFFIX:
6065 case QWORD_MNEM_SUFFIX:
6066 /* It's not a byte, select word/dword operation. */
6067 if (i.tm.opcode_modifier.w)
6069 if (i.tm.opcode_modifier.shortform)
6070 i.tm.base_opcode |= 8;
6072 i.tm.base_opcode |= 1;
6075 case SHORT_MNEM_SUFFIX:
6076 /* Now select between word & dword operations via the operand
6077 size prefix, except for instructions that will ignore this
6079 if (i.reg_operands > 0
6080 && i.types[0].bitfield.reg
6081 && i.tm.opcode_modifier.addrprefixopreg
6082 && (i.tm.opcode_modifier.immext
6083 || i.operands == 1))
6085 /* The address size override prefix changes the size of the
6087 if ((flag_code == CODE_32BIT
6088 && i.op[0].regs->reg_type.bitfield.word)
6089 || (flag_code != CODE_32BIT
6090 && i.op[0].regs->reg_type.bitfield.dword))
6091 if (!add_prefix (ADDR_PREFIX_OPCODE))
6094 else if (i.suffix != QWORD_MNEM_SUFFIX
6095 && !i.tm.opcode_modifier.ignoresize
6096 && !i.tm.opcode_modifier.floatmf
6097 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6098 || (flag_code == CODE_64BIT
6099 && i.tm.opcode_modifier.jumpbyte)))
6101 unsigned int prefix = DATA_PREFIX_OPCODE;
6103 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6104 prefix = ADDR_PREFIX_OPCODE;
6106 if (!add_prefix (prefix))
6110 /* Set mode64 for an operand. */
6111 if (i.suffix == QWORD_MNEM_SUFFIX
6112 && flag_code == CODE_64BIT
6113 && !i.tm.opcode_modifier.norex64
6114 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6116 && ! (i.operands == 2
6117 && i.tm.base_opcode == 0x90
6118 && i.tm.extension_opcode == None
6119 && operand_type_equal (&i.types [0], &acc64)
6120 && operand_type_equal (&i.types [1], &acc64)))
6126 if (i.reg_operands != 0
6128 && i.tm.opcode_modifier.addrprefixopreg
6129 && !i.tm.opcode_modifier.immext)
6131 /* Check invalid register operand when the address size override
6132 prefix changes the size of register operands. */
6134 enum { need_word, need_dword, need_qword } need;
6136 if (flag_code == CODE_32BIT)
6137 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6140 if (i.prefix[ADDR_PREFIX])
6143 need = flag_code == CODE_64BIT ? need_qword : need_word;
6146 for (op = 0; op < i.operands; op++)
6147 if (i.types[op].bitfield.reg
6148 && ((need == need_word
6149 && !i.op[op].regs->reg_type.bitfield.word)
6150 || (need == need_dword
6151 && !i.op[op].regs->reg_type.bitfield.dword)
6152 || (need == need_qword
6153 && !i.op[op].regs->reg_type.bitfield.qword)))
6155 as_bad (_("invalid register operand size for `%s'"),
6165 check_byte_reg (void)
6169 for (op = i.operands; --op >= 0;)
6171 /* Skip non-register operands. */
6172 if (!i.types[op].bitfield.reg)
6175 /* If this is an eight bit register, it's OK. If it's the 16 or
6176 32 bit version of an eight bit register, we will just use the
6177 low portion, and that's OK too. */
6178 if (i.types[op].bitfield.byte)
6181 /* I/O port address operands are OK too. */
6182 if (i.tm.operand_types[op].bitfield.inoutportreg)
6185 /* crc32 doesn't generate this warning. */
6186 if (i.tm.base_opcode == 0xf20f38f0)
6189 if ((i.types[op].bitfield.word
6190 || i.types[op].bitfield.dword
6191 || i.types[op].bitfield.qword)
6192 && i.op[op].regs->reg_num < 4
6193 /* Prohibit these changes in 64bit mode, since the lowering
6194 would be more complicated. */
6195 && flag_code != CODE_64BIT)
6197 #if REGISTER_WARNINGS
6198 if (!quiet_warnings)
6199 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6201 (i.op[op].regs + (i.types[op].bitfield.word
6202 ? REGNAM_AL - REGNAM_AX
6203 : REGNAM_AL - REGNAM_EAX))->reg_name,
6205 i.op[op].regs->reg_name,
6210 /* Any other register is bad. */
6211 if (i.types[op].bitfield.reg
6212 || i.types[op].bitfield.regmmx
6213 || i.types[op].bitfield.regsimd
6214 || i.types[op].bitfield.sreg2
6215 || i.types[op].bitfield.sreg3
6216 || i.types[op].bitfield.control
6217 || i.types[op].bitfield.debug
6218 || i.types[op].bitfield.test)
6220 as_bad (_("`%s%s' not allowed with `%s%c'"),
6222 i.op[op].regs->reg_name,
6232 check_long_reg (void)
6236 for (op = i.operands; --op >= 0;)
6237 /* Skip non-register operands. */
6238 if (!i.types[op].bitfield.reg)
6240 /* Reject eight bit registers, except where the template requires
6241 them. (eg. movzb) */
6242 else if (i.types[op].bitfield.byte
6243 && (i.tm.operand_types[op].bitfield.reg
6244 || i.tm.operand_types[op].bitfield.acc)
6245 && (i.tm.operand_types[op].bitfield.word
6246 || i.tm.operand_types[op].bitfield.dword))
6248 as_bad (_("`%s%s' not allowed with `%s%c'"),
6250 i.op[op].regs->reg_name,
6255 /* Warn if the e prefix on a general reg is missing. */
6256 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6257 && i.types[op].bitfield.word
6258 && (i.tm.operand_types[op].bitfield.reg
6259 || i.tm.operand_types[op].bitfield.acc)
6260 && i.tm.operand_types[op].bitfield.dword)
6262 /* Prohibit these changes in the 64bit mode, since the
6263 lowering is more complicated. */
6264 if (flag_code == CODE_64BIT)
6266 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6267 register_prefix, i.op[op].regs->reg_name,
6271 #if REGISTER_WARNINGS
6272 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6274 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6275 register_prefix, i.op[op].regs->reg_name, i.suffix);
6278 /* Warn if the r prefix on a general reg is present. */
6279 else if (i.types[op].bitfield.qword
6280 && (i.tm.operand_types[op].bitfield.reg
6281 || i.tm.operand_types[op].bitfield.acc)
6282 && i.tm.operand_types[op].bitfield.dword)
6285 && i.tm.opcode_modifier.toqword
6286 && !i.types[0].bitfield.regsimd)
6288 /* Convert to QWORD. We want REX byte. */
6289 i.suffix = QWORD_MNEM_SUFFIX;
6293 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6294 register_prefix, i.op[op].regs->reg_name,
6303 check_qword_reg (void)
6307 for (op = i.operands; --op >= 0; )
6308 /* Skip non-register operands. */
6309 if (!i.types[op].bitfield.reg)
6311 /* Reject eight bit registers, except where the template requires
6312 them. (eg. movzb) */
6313 else if (i.types[op].bitfield.byte
6314 && (i.tm.operand_types[op].bitfield.reg
6315 || i.tm.operand_types[op].bitfield.acc)
6316 && (i.tm.operand_types[op].bitfield.word
6317 || i.tm.operand_types[op].bitfield.dword))
6319 as_bad (_("`%s%s' not allowed with `%s%c'"),
6321 i.op[op].regs->reg_name,
6326 /* Warn if the r prefix on a general reg is missing. */
6327 else if ((i.types[op].bitfield.word
6328 || i.types[op].bitfield.dword)
6329 && (i.tm.operand_types[op].bitfield.reg
6330 || i.tm.operand_types[op].bitfield.acc)
6331 && i.tm.operand_types[op].bitfield.qword)
6333 /* Prohibit these changes in the 64bit mode, since the
6334 lowering is more complicated. */
6336 && i.tm.opcode_modifier.todword
6337 && !i.types[0].bitfield.regsimd)
6339 /* Convert to DWORD. We don't want REX byte. */
6340 i.suffix = LONG_MNEM_SUFFIX;
6344 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6345 register_prefix, i.op[op].regs->reg_name,
6354 check_word_reg (void)
6357 for (op = i.operands; --op >= 0;)
6358 /* Skip non-register operands. */
6359 if (!i.types[op].bitfield.reg)
6361 /* Reject eight bit registers, except where the template requires
6362 them. (eg. movzb) */
6363 else if (i.types[op].bitfield.byte
6364 && (i.tm.operand_types[op].bitfield.reg
6365 || i.tm.operand_types[op].bitfield.acc)
6366 && (i.tm.operand_types[op].bitfield.word
6367 || i.tm.operand_types[op].bitfield.dword))
6369 as_bad (_("`%s%s' not allowed with `%s%c'"),
6371 i.op[op].regs->reg_name,
6376 /* Warn if the e or r prefix on a general reg is present. */
6377 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6378 && (i.types[op].bitfield.dword
6379 || i.types[op].bitfield.qword)
6380 && (i.tm.operand_types[op].bitfield.reg
6381 || i.tm.operand_types[op].bitfield.acc)
6382 && i.tm.operand_types[op].bitfield.word)
6384 /* Prohibit these changes in the 64bit mode, since the
6385 lowering is more complicated. */
6386 if (flag_code == CODE_64BIT)
6388 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6389 register_prefix, i.op[op].regs->reg_name,
6393 #if REGISTER_WARNINGS
6394 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6396 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6397 register_prefix, i.op[op].regs->reg_name, i.suffix);
6404 update_imm (unsigned int j)
6406 i386_operand_type overlap = i.types[j];
6407 if ((overlap.bitfield.imm8
6408 || overlap.bitfield.imm8s
6409 || overlap.bitfield.imm16
6410 || overlap.bitfield.imm32
6411 || overlap.bitfield.imm32s
6412 || overlap.bitfield.imm64)
6413 && !operand_type_equal (&overlap, &imm8)
6414 && !operand_type_equal (&overlap, &imm8s)
6415 && !operand_type_equal (&overlap, &imm16)
6416 && !operand_type_equal (&overlap, &imm32)
6417 && !operand_type_equal (&overlap, &imm32s)
6418 && !operand_type_equal (&overlap, &imm64))
6422 i386_operand_type temp;
6424 operand_type_set (&temp, 0);
6425 if (i.suffix == BYTE_MNEM_SUFFIX)
6427 temp.bitfield.imm8 = overlap.bitfield.imm8;
6428 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6430 else if (i.suffix == WORD_MNEM_SUFFIX)
6431 temp.bitfield.imm16 = overlap.bitfield.imm16;
6432 else if (i.suffix == QWORD_MNEM_SUFFIX)
6434 temp.bitfield.imm64 = overlap.bitfield.imm64;
6435 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6438 temp.bitfield.imm32 = overlap.bitfield.imm32;
6441 else if (operand_type_equal (&overlap, &imm16_32_32s)
6442 || operand_type_equal (&overlap, &imm16_32)
6443 || operand_type_equal (&overlap, &imm16_32s))
6445 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6450 if (!operand_type_equal (&overlap, &imm8)
6451 && !operand_type_equal (&overlap, &imm8s)
6452 && !operand_type_equal (&overlap, &imm16)
6453 && !operand_type_equal (&overlap, &imm32)
6454 && !operand_type_equal (&overlap, &imm32s)
6455 && !operand_type_equal (&overlap, &imm64))
6457 as_bad (_("no instruction mnemonic suffix given; "
6458 "can't determine immediate size"));
6462 i.types[j] = overlap;
6472 /* Update the first 2 immediate operands. */
6473 n = i.operands > 2 ? 2 : i.operands;
6476 for (j = 0; j < n; j++)
6477 if (update_imm (j) == 0)
6480 /* The 3rd operand can't be immediate operand. */
6481 gas_assert (operand_type_check (i.types[2], imm) == 0);
6488 process_operands (void)
6490 /* Default segment register this instruction will use for memory
6491 accesses. 0 means unknown. This is only for optimizing out
6492 unnecessary segment overrides. */
6493 const seg_entry *default_seg = 0;
6495 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6497 unsigned int dupl = i.operands;
6498 unsigned int dest = dupl - 1;
6501 /* The destination must be an xmm register. */
6502 gas_assert (i.reg_operands
6503 && MAX_OPERANDS > dupl
6504 && operand_type_equal (&i.types[dest], ®xmm));
6506 if (i.tm.operand_types[0].bitfield.acc
6507 && i.tm.operand_types[0].bitfield.xmmword)
6509 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6511 /* Keep xmm0 for instructions with VEX prefix and 3
6513 i.tm.operand_types[0].bitfield.acc = 0;
6514 i.tm.operand_types[0].bitfield.regsimd = 1;
6519 /* We remove the first xmm0 and keep the number of
6520 operands unchanged, which in fact duplicates the
6522 for (j = 1; j < i.operands; j++)
6524 i.op[j - 1] = i.op[j];
6525 i.types[j - 1] = i.types[j];
6526 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6530 else if (i.tm.opcode_modifier.implicit1stxmm0)
6532 gas_assert ((MAX_OPERANDS - 1) > dupl
6533 && (i.tm.opcode_modifier.vexsources
6536 /* Add the implicit xmm0 for instructions with VEX prefix
6538 for (j = i.operands; j > 0; j--)
6540 i.op[j] = i.op[j - 1];
6541 i.types[j] = i.types[j - 1];
6542 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6545 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6546 i.types[0] = regxmm;
6547 i.tm.operand_types[0] = regxmm;
6550 i.reg_operands += 2;
6555 i.op[dupl] = i.op[dest];
6556 i.types[dupl] = i.types[dest];
6557 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6566 i.op[dupl] = i.op[dest];
6567 i.types[dupl] = i.types[dest];
6568 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6571 if (i.tm.opcode_modifier.immext)
6574 else if (i.tm.operand_types[0].bitfield.acc
6575 && i.tm.operand_types[0].bitfield.xmmword)
6579 for (j = 1; j < i.operands; j++)
6581 i.op[j - 1] = i.op[j];
6582 i.types[j - 1] = i.types[j];
6584 /* We need to adjust fields in i.tm since they are used by
6585 build_modrm_byte. */
6586 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6593 else if (i.tm.opcode_modifier.implicitquadgroup)
6595 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6597 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6598 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6599 regnum = register_number (i.op[1].regs);
6600 first_reg_in_group = regnum & ~3;
6601 last_reg_in_group = first_reg_in_group + 3;
6602 if (regnum != first_reg_in_group)
6603 as_warn (_("source register `%s%s' implicitly denotes"
6604 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6605 register_prefix, i.op[1].regs->reg_name,
6606 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6607 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6610 else if (i.tm.opcode_modifier.regkludge)
6612 /* The imul $imm, %reg instruction is converted into
6613 imul $imm, %reg, %reg, and the clr %reg instruction
6614 is converted into xor %reg, %reg. */
6616 unsigned int first_reg_op;
6618 if (operand_type_check (i.types[0], reg))
6622 /* Pretend we saw the extra register operand. */
6623 gas_assert (i.reg_operands == 1
6624 && i.op[first_reg_op + 1].regs == 0);
6625 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6626 i.types[first_reg_op + 1] = i.types[first_reg_op];
6631 if (i.tm.opcode_modifier.shortform)
6633 if (i.types[0].bitfield.sreg2
6634 || i.types[0].bitfield.sreg3)
6636 if (i.tm.base_opcode == POP_SEG_SHORT
6637 && i.op[0].regs->reg_num == 1)
6639 as_bad (_("you can't `pop %scs'"), register_prefix);
6642 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6643 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6648 /* The register or float register operand is in operand
6652 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6653 || operand_type_check (i.types[0], reg))
6657 /* Register goes in low 3 bits of opcode. */
6658 i.tm.base_opcode |= i.op[op].regs->reg_num;
6659 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6661 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6663 /* Warn about some common errors, but press on regardless.
6664 The first case can be generated by gcc (<= 2.8.1). */
6665 if (i.operands == 2)
6667 /* Reversed arguments on faddp, fsubp, etc. */
6668 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6669 register_prefix, i.op[!intel_syntax].regs->reg_name,
6670 register_prefix, i.op[intel_syntax].regs->reg_name);
6674 /* Extraneous `l' suffix on fp insn. */
6675 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6676 register_prefix, i.op[0].regs->reg_name);
6681 else if (i.tm.opcode_modifier.modrm)
6683 /* The opcode is completed (modulo i.tm.extension_opcode which
6684 must be put into the modrm byte). Now, we make the modrm and
6685 index base bytes based on all the info we've collected. */
6687 default_seg = build_modrm_byte ();
6689 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6693 else if (i.tm.opcode_modifier.isstring)
6695 /* For the string instructions that allow a segment override
6696 on one of their operands, the default segment is ds. */
6700 if (i.tm.base_opcode == 0x8d /* lea */
6703 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6705 /* If a segment was explicitly specified, and the specified segment
6706 is not the default, use an opcode prefix to select it. If we
6707 never figured out what the default segment is, then default_seg
6708 will be zero at this point, and the specified segment prefix will
6710 if ((i.seg[0]) && (i.seg[0] != default_seg))
6712 if (!add_prefix (i.seg[0]->seg_prefix))
6718 static const seg_entry *
6719 build_modrm_byte (void)
6721 const seg_entry *default_seg = 0;
6722 unsigned int source, dest;
6725 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6728 unsigned int nds, reg_slot;
6731 dest = i.operands - 1;
6734 /* There are 2 kinds of instructions:
6735 1. 5 operands: 4 register operands or 3 register operands
6736 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6737 VexW0 or VexW1. The destination must be either XMM, YMM or
6739 2. 4 operands: 4 register operands or 3 register operands
6740 plus 1 memory operand, with VexXDS. */
6741 gas_assert ((i.reg_operands == 4
6742 || (i.reg_operands == 3 && i.mem_operands == 1))
6743 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6744 && i.tm.opcode_modifier.vexw
6745 && i.tm.operand_types[dest].bitfield.regsimd);
6747 /* If VexW1 is set, the first non-immediate operand is the source and
6748 the second non-immediate one is encoded in the immediate operand. */
6749 if (i.tm.opcode_modifier.vexw == VEXW1)
6751 source = i.imm_operands;
6752 reg_slot = i.imm_operands + 1;
6756 source = i.imm_operands + 1;
6757 reg_slot = i.imm_operands;
6760 if (i.imm_operands == 0)
6762 /* When there is no immediate operand, generate an 8bit
6763 immediate operand to encode the first operand. */
6764 exp = &im_expressions[i.imm_operands++];
6765 i.op[i.operands].imms = exp;
6766 i.types[i.operands] = imm8;
6769 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6770 exp->X_op = O_constant;
6771 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6772 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6776 unsigned int imm_slot;
6778 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6780 if (i.tm.opcode_modifier.immext)
6782 /* When ImmExt is set, the immediate byte is the last
6784 imm_slot = i.operands - 1;
6792 /* Turn on Imm8 so that output_imm will generate it. */
6793 i.types[imm_slot].bitfield.imm8 = 1;
6796 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6797 i.op[imm_slot].imms->X_add_number
6798 |= register_number (i.op[reg_slot].regs) << 4;
6799 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6802 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6803 i.vex.register_specifier = i.op[nds].regs;
6808 /* i.reg_operands MUST be the number of real register operands;
6809 implicit registers do not count. If there are 3 register
6810 operands, it must be a instruction with VexNDS. For a
6811 instruction with VexNDD, the destination register is encoded
6812 in VEX prefix. If there are 4 register operands, it must be
6813 a instruction with VEX prefix and 3 sources. */
6814 if (i.mem_operands == 0
6815 && ((i.reg_operands == 2
6816 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6817 || (i.reg_operands == 3
6818 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6819 || (i.reg_operands == 4 && vex_3_sources)))
6827 /* When there are 3 operands, one of them may be immediate,
6828 which may be the first or the last operand. Otherwise,
6829 the first operand must be shift count register (cl) or it
6830 is an instruction with VexNDS. */
6831 gas_assert (i.imm_operands == 1
6832 || (i.imm_operands == 0
6833 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6834 || i.types[0].bitfield.shiftcount)));
6835 if (operand_type_check (i.types[0], imm)
6836 || i.types[0].bitfield.shiftcount)
6842 /* When there are 4 operands, the first two must be 8bit
6843 immediate operands. The source operand will be the 3rd
6846 For instructions with VexNDS, if the first operand
6847 an imm8, the source operand is the 2nd one. If the last
6848 operand is imm8, the source operand is the first one. */
6849 gas_assert ((i.imm_operands == 2
6850 && i.types[0].bitfield.imm8
6851 && i.types[1].bitfield.imm8)
6852 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6853 && i.imm_operands == 1
6854 && (i.types[0].bitfield.imm8
6855 || i.types[i.operands - 1].bitfield.imm8
6857 if (i.imm_operands == 2)
6861 if (i.types[0].bitfield.imm8)
6868 if (is_evex_encoding (&i.tm))
6870 /* For EVEX instructions, when there are 5 operands, the
6871 first one must be immediate operand. If the second one
6872 is immediate operand, the source operand is the 3th
6873 one. If the last one is immediate operand, the source
6874 operand is the 2nd one. */
6875 gas_assert (i.imm_operands == 2
6876 && i.tm.opcode_modifier.sae
6877 && operand_type_check (i.types[0], imm));
6878 if (operand_type_check (i.types[1], imm))
6880 else if (operand_type_check (i.types[4], imm))
6894 /* RC/SAE operand could be between DEST and SRC. That happens
6895 when one operand is GPR and the other one is XMM/YMM/ZMM
6897 if (i.rounding && i.rounding->operand == (int) dest)
6900 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6902 /* For instructions with VexNDS, the register-only source
6903 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6904 register. It is encoded in VEX prefix. We need to
6905 clear RegMem bit before calling operand_type_equal. */
6907 i386_operand_type op;
6910 /* Check register-only source operand when two source
6911 operands are swapped. */
6912 if (!i.tm.operand_types[source].bitfield.baseindex
6913 && i.tm.operand_types[dest].bitfield.baseindex)
6921 op = i.tm.operand_types[vvvv];
6922 op.bitfield.regmem = 0;
6923 if ((dest + 1) >= i.operands
6924 || ((!op.bitfield.reg
6925 || (!op.bitfield.dword && !op.bitfield.qword))
6926 && !op.bitfield.regsimd
6927 && !operand_type_equal (&op, ®mask)))
6929 i.vex.register_specifier = i.op[vvvv].regs;
6935 /* One of the register operands will be encoded in the i.tm.reg
6936 field, the other in the combined i.tm.mode and i.tm.regmem
6937 fields. If no form of this instruction supports a memory
6938 destination operand, then we assume the source operand may
6939 sometimes be a memory operand and so we need to store the
6940 destination in the i.rm.reg field. */
6941 if (!i.tm.operand_types[dest].bitfield.regmem
6942 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6944 i.rm.reg = i.op[dest].regs->reg_num;
6945 i.rm.regmem = i.op[source].regs->reg_num;
6946 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6948 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6950 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6952 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6957 i.rm.reg = i.op[source].regs->reg_num;
6958 i.rm.regmem = i.op[dest].regs->reg_num;
6959 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6961 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6963 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6965 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6968 if (flag_code != CODE_64BIT && (i.rex & REX_R))
6970 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
6973 add_prefix (LOCK_PREFIX_OPCODE);
6977 { /* If it's not 2 reg operands... */
6982 unsigned int fake_zero_displacement = 0;
6985 for (op = 0; op < i.operands; op++)
6986 if (operand_type_check (i.types[op], anymem))
6988 gas_assert (op < i.operands);
6990 if (i.tm.opcode_modifier.vecsib)
6992 if (i.index_reg->reg_num == RegEiz
6993 || i.index_reg->reg_num == RegRiz)
6996 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6999 i.sib.base = NO_BASE_REGISTER;
7000 i.sib.scale = i.log2_scale_factor;
7001 i.types[op].bitfield.disp8 = 0;
7002 i.types[op].bitfield.disp16 = 0;
7003 i.types[op].bitfield.disp64 = 0;
7004 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7006 /* Must be 32 bit */
7007 i.types[op].bitfield.disp32 = 1;
7008 i.types[op].bitfield.disp32s = 0;
7012 i.types[op].bitfield.disp32 = 0;
7013 i.types[op].bitfield.disp32s = 1;
7016 i.sib.index = i.index_reg->reg_num;
7017 if ((i.index_reg->reg_flags & RegRex) != 0)
7019 if ((i.index_reg->reg_flags & RegVRex) != 0)
7025 if (i.base_reg == 0)
7028 if (!i.disp_operands)
7029 fake_zero_displacement = 1;
7030 if (i.index_reg == 0)
7032 i386_operand_type newdisp;
7034 gas_assert (!i.tm.opcode_modifier.vecsib);
7035 /* Operand is just <disp> */
7036 if (flag_code == CODE_64BIT)
7038 /* 64bit mode overwrites the 32bit absolute
7039 addressing by RIP relative addressing and
7040 absolute addressing is encoded by one of the
7041 redundant SIB forms. */
7042 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7043 i.sib.base = NO_BASE_REGISTER;
7044 i.sib.index = NO_INDEX_REGISTER;
7045 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7047 else if ((flag_code == CODE_16BIT)
7048 ^ (i.prefix[ADDR_PREFIX] != 0))
7050 i.rm.regmem = NO_BASE_REGISTER_16;
7055 i.rm.regmem = NO_BASE_REGISTER;
7058 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7059 i.types[op] = operand_type_or (i.types[op], newdisp);
7061 else if (!i.tm.opcode_modifier.vecsib)
7063 /* !i.base_reg && i.index_reg */
7064 if (i.index_reg->reg_num == RegEiz
7065 || i.index_reg->reg_num == RegRiz)
7066 i.sib.index = NO_INDEX_REGISTER;
7068 i.sib.index = i.index_reg->reg_num;
7069 i.sib.base = NO_BASE_REGISTER;
7070 i.sib.scale = i.log2_scale_factor;
7071 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7072 i.types[op].bitfield.disp8 = 0;
7073 i.types[op].bitfield.disp16 = 0;
7074 i.types[op].bitfield.disp64 = 0;
7075 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7077 /* Must be 32 bit */
7078 i.types[op].bitfield.disp32 = 1;
7079 i.types[op].bitfield.disp32s = 0;
7083 i.types[op].bitfield.disp32 = 0;
7084 i.types[op].bitfield.disp32s = 1;
7086 if ((i.index_reg->reg_flags & RegRex) != 0)
7090 /* RIP addressing for 64bit mode. */
7091 else if (i.base_reg->reg_num == RegRip ||
7092 i.base_reg->reg_num == RegEip)
7094 gas_assert (!i.tm.opcode_modifier.vecsib);
7095 i.rm.regmem = NO_BASE_REGISTER;
7096 i.types[op].bitfield.disp8 = 0;
7097 i.types[op].bitfield.disp16 = 0;
7098 i.types[op].bitfield.disp32 = 0;
7099 i.types[op].bitfield.disp32s = 1;
7100 i.types[op].bitfield.disp64 = 0;
7101 i.flags[op] |= Operand_PCrel;
7102 if (! i.disp_operands)
7103 fake_zero_displacement = 1;
7105 else if (i.base_reg->reg_type.bitfield.word)
7107 gas_assert (!i.tm.opcode_modifier.vecsib);
7108 switch (i.base_reg->reg_num)
7111 if (i.index_reg == 0)
7113 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7114 i.rm.regmem = i.index_reg->reg_num - 6;
7118 if (i.index_reg == 0)
7121 if (operand_type_check (i.types[op], disp) == 0)
7123 /* fake (%bp) into 0(%bp) */
7124 i.types[op].bitfield.disp8 = 1;
7125 fake_zero_displacement = 1;
7128 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7129 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7131 default: /* (%si) -> 4 or (%di) -> 5 */
7132 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7134 i.rm.mode = mode_from_disp_size (i.types[op]);
7136 else /* i.base_reg and 32/64 bit mode */
7138 if (flag_code == CODE_64BIT
7139 && operand_type_check (i.types[op], disp))
7141 i.types[op].bitfield.disp16 = 0;
7142 i.types[op].bitfield.disp64 = 0;
7143 if (i.prefix[ADDR_PREFIX] == 0)
7145 i.types[op].bitfield.disp32 = 0;
7146 i.types[op].bitfield.disp32s = 1;
7150 i.types[op].bitfield.disp32 = 1;
7151 i.types[op].bitfield.disp32s = 0;
7155 if (!i.tm.opcode_modifier.vecsib)
7156 i.rm.regmem = i.base_reg->reg_num;
7157 if ((i.base_reg->reg_flags & RegRex) != 0)
7159 i.sib.base = i.base_reg->reg_num;
7160 /* x86-64 ignores REX prefix bit here to avoid decoder
7162 if (!(i.base_reg->reg_flags & RegRex)
7163 && (i.base_reg->reg_num == EBP_REG_NUM
7164 || i.base_reg->reg_num == ESP_REG_NUM))
7166 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7168 fake_zero_displacement = 1;
7169 i.types[op].bitfield.disp8 = 1;
7171 i.sib.scale = i.log2_scale_factor;
7172 if (i.index_reg == 0)
7174 gas_assert (!i.tm.opcode_modifier.vecsib);
7175 /* <disp>(%esp) becomes two byte modrm with no index
7176 register. We've already stored the code for esp
7177 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7178 Any base register besides %esp will not use the
7179 extra modrm byte. */
7180 i.sib.index = NO_INDEX_REGISTER;
7182 else if (!i.tm.opcode_modifier.vecsib)
7184 if (i.index_reg->reg_num == RegEiz
7185 || i.index_reg->reg_num == RegRiz)
7186 i.sib.index = NO_INDEX_REGISTER;
7188 i.sib.index = i.index_reg->reg_num;
7189 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7190 if ((i.index_reg->reg_flags & RegRex) != 0)
7195 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7196 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7200 if (!fake_zero_displacement
7204 fake_zero_displacement = 1;
7205 if (i.disp_encoding == disp_encoding_8bit)
7206 i.types[op].bitfield.disp8 = 1;
7208 i.types[op].bitfield.disp32 = 1;
7210 i.rm.mode = mode_from_disp_size (i.types[op]);
7214 if (fake_zero_displacement)
7216 /* Fakes a zero displacement assuming that i.types[op]
7217 holds the correct displacement size. */
7220 gas_assert (i.op[op].disps == 0);
7221 exp = &disp_expressions[i.disp_operands++];
7222 i.op[op].disps = exp;
7223 exp->X_op = O_constant;
7224 exp->X_add_number = 0;
7225 exp->X_add_symbol = (symbolS *) 0;
7226 exp->X_op_symbol = (symbolS *) 0;
7234 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7236 if (operand_type_check (i.types[0], imm))
7237 i.vex.register_specifier = NULL;
7240 /* VEX.vvvv encodes one of the sources when the first
7241 operand is not an immediate. */
7242 if (i.tm.opcode_modifier.vexw == VEXW0)
7243 i.vex.register_specifier = i.op[0].regs;
7245 i.vex.register_specifier = i.op[1].regs;
7248 /* Destination is a XMM register encoded in the ModRM.reg
7250 i.rm.reg = i.op[2].regs->reg_num;
7251 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7254 /* ModRM.rm and VEX.B encodes the other source. */
7255 if (!i.mem_operands)
7259 if (i.tm.opcode_modifier.vexw == VEXW0)
7260 i.rm.regmem = i.op[1].regs->reg_num;
7262 i.rm.regmem = i.op[0].regs->reg_num;
7264 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7268 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7270 i.vex.register_specifier = i.op[2].regs;
7271 if (!i.mem_operands)
7274 i.rm.regmem = i.op[1].regs->reg_num;
7275 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7279 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7280 (if any) based on i.tm.extension_opcode. Again, we must be
7281 careful to make sure that segment/control/debug/test/MMX
7282 registers are coded into the i.rm.reg field. */
7283 else if (i.reg_operands)
7286 unsigned int vex_reg = ~0;
7288 for (op = 0; op < i.operands; op++)
7289 if (i.types[op].bitfield.reg
7290 || i.types[op].bitfield.regmmx
7291 || i.types[op].bitfield.regsimd
7292 || i.types[op].bitfield.regbnd
7293 || i.types[op].bitfield.regmask
7294 || i.types[op].bitfield.sreg2
7295 || i.types[op].bitfield.sreg3
7296 || i.types[op].bitfield.control
7297 || i.types[op].bitfield.debug
7298 || i.types[op].bitfield.test)
7303 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7305 /* For instructions with VexNDS, the register-only
7306 source operand is encoded in VEX prefix. */
7307 gas_assert (mem != (unsigned int) ~0);
7312 gas_assert (op < i.operands);
7316 /* Check register-only source operand when two source
7317 operands are swapped. */
7318 if (!i.tm.operand_types[op].bitfield.baseindex
7319 && i.tm.operand_types[op + 1].bitfield.baseindex)
7323 gas_assert (mem == (vex_reg + 1)
7324 && op < i.operands);
7329 gas_assert (vex_reg < i.operands);
7333 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7335 /* For instructions with VexNDD, the register destination
7336 is encoded in VEX prefix. */
7337 if (i.mem_operands == 0)
7339 /* There is no memory operand. */
7340 gas_assert ((op + 2) == i.operands);
7345 /* There are only 2 non-immediate operands. */
7346 gas_assert (op < i.imm_operands + 2
7347 && i.operands == i.imm_operands + 2);
7348 vex_reg = i.imm_operands + 1;
7352 gas_assert (op < i.operands);
7354 if (vex_reg != (unsigned int) ~0)
7356 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7358 if ((!type->bitfield.reg
7359 || (!type->bitfield.dword && !type->bitfield.qword))
7360 && !type->bitfield.regsimd
7361 && !operand_type_equal (type, ®mask))
7364 i.vex.register_specifier = i.op[vex_reg].regs;
7367 /* Don't set OP operand twice. */
7370 /* If there is an extension opcode to put here, the
7371 register number must be put into the regmem field. */
7372 if (i.tm.extension_opcode != None)
7374 i.rm.regmem = i.op[op].regs->reg_num;
7375 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7377 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7382 i.rm.reg = i.op[op].regs->reg_num;
7383 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7385 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7390 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7391 must set it to 3 to indicate this is a register operand
7392 in the regmem field. */
7393 if (!i.mem_operands)
7397 /* Fill in i.rm.reg field with extension opcode (if any). */
7398 if (i.tm.extension_opcode != None)
7399 i.rm.reg = i.tm.extension_opcode;
7405 output_branch (void)
7411 relax_substateT subtype;
7415 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7416 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7419 if (i.prefix[DATA_PREFIX] != 0)
7425 /* Pentium4 branch hints. */
7426 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7427 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7432 if (i.prefix[REX_PREFIX] != 0)
7438 /* BND prefixed jump. */
7439 if (i.prefix[BND_PREFIX] != 0)
7441 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7445 if (i.prefixes != 0 && !intel_syntax)
7446 as_warn (_("skipping prefixes on this instruction"));
7448 /* It's always a symbol; End frag & setup for relax.
7449 Make sure there is enough room in this frag for the largest
7450 instruction we may generate in md_convert_frag. This is 2
7451 bytes for the opcode and room for the prefix and largest
7453 frag_grow (prefix + 2 + 4);
7454 /* Prefix and 1 opcode byte go in fr_fix. */
7455 p = frag_more (prefix + 1);
7456 if (i.prefix[DATA_PREFIX] != 0)
7457 *p++ = DATA_PREFIX_OPCODE;
7458 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7459 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7460 *p++ = i.prefix[SEG_PREFIX];
7461 if (i.prefix[REX_PREFIX] != 0)
7462 *p++ = i.prefix[REX_PREFIX];
7463 *p = i.tm.base_opcode;
7465 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7466 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7467 else if (cpu_arch_flags.bitfield.cpui386)
7468 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7470 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7473 sym = i.op[0].disps->X_add_symbol;
7474 off = i.op[0].disps->X_add_number;
7476 if (i.op[0].disps->X_op != O_constant
7477 && i.op[0].disps->X_op != O_symbol)
7479 /* Handle complex expressions. */
7480 sym = make_expr_symbol (i.op[0].disps);
7484 /* 1 possible extra opcode + 4 byte displacement go in var part.
7485 Pass reloc in fr_var. */
7486 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7490 /* Return TRUE iff PLT32 relocation should be used for branching to
7494 need_plt32_p (symbolS *s)
7496 /* PLT32 relocation is ELF only. */
7500 /* Since there is no need to prepare for PLT branch on x86-64, we
7501 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7502 be used as a marker for 32-bit PC-relative branches. */
7506 /* Weak or undefined symbol need PLT32 relocation. */
7507 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7510 /* Non-global symbol doesn't need PLT32 relocation. */
7511 if (! S_IS_EXTERNAL (s))
7514 /* Other global symbols need PLT32 relocation. NB: Symbol with
7515 non-default visibilities are treated as normal global symbol
7516 so that PLT32 relocation can be used as a marker for 32-bit
7517 PC-relative branches. It is useful for linker relaxation. */
7528 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7530 if (i.tm.opcode_modifier.jumpbyte)
7532 /* This is a loop or jecxz type instruction. */
7534 if (i.prefix[ADDR_PREFIX] != 0)
7536 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7539 /* Pentium4 branch hints. */
7540 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7541 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7543 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7552 if (flag_code == CODE_16BIT)
7555 if (i.prefix[DATA_PREFIX] != 0)
7557 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7567 if (i.prefix[REX_PREFIX] != 0)
7569 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7573 /* BND prefixed jump. */
7574 if (i.prefix[BND_PREFIX] != 0)
7576 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7580 if (i.prefixes != 0 && !intel_syntax)
7581 as_warn (_("skipping prefixes on this instruction"));
7583 p = frag_more (i.tm.opcode_length + size);
7584 switch (i.tm.opcode_length)
7587 *p++ = i.tm.base_opcode >> 8;
7590 *p++ = i.tm.base_opcode;
7596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7598 && jump_reloc == NO_RELOC
7599 && need_plt32_p (i.op[0].disps->X_add_symbol))
7600 jump_reloc = BFD_RELOC_X86_64_PLT32;
7603 jump_reloc = reloc (size, 1, 1, jump_reloc);
7605 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7606 i.op[0].disps, 1, jump_reloc);
7608 /* All jumps handled here are signed, but don't use a signed limit
7609 check for 32 and 16 bit jumps as we want to allow wrap around at
7610 4G and 64k respectively. */
7612 fixP->fx_signed = 1;
7616 output_interseg_jump (void)
7624 if (flag_code == CODE_16BIT)
7628 if (i.prefix[DATA_PREFIX] != 0)
7634 if (i.prefix[REX_PREFIX] != 0)
7644 if (i.prefixes != 0 && !intel_syntax)
7645 as_warn (_("skipping prefixes on this instruction"));
7647 /* 1 opcode; 2 segment; offset */
7648 p = frag_more (prefix + 1 + 2 + size);
7650 if (i.prefix[DATA_PREFIX] != 0)
7651 *p++ = DATA_PREFIX_OPCODE;
7653 if (i.prefix[REX_PREFIX] != 0)
7654 *p++ = i.prefix[REX_PREFIX];
7656 *p++ = i.tm.base_opcode;
7657 if (i.op[1].imms->X_op == O_constant)
7659 offsetT n = i.op[1].imms->X_add_number;
7662 && !fits_in_unsigned_word (n)
7663 && !fits_in_signed_word (n))
7665 as_bad (_("16-bit jump out of range"));
7668 md_number_to_chars (p, n, size);
7671 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7672 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7673 if (i.op[0].imms->X_op != O_constant)
7674 as_bad (_("can't handle non absolute segment in `%s'"),
7676 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7682 fragS *insn_start_frag;
7683 offsetT insn_start_off;
7685 /* Tie dwarf2 debug info to the address at the start of the insn.
7686 We can't do this after the insn has been output as the current
7687 frag may have been closed off. eg. by frag_var. */
7688 dwarf2_emit_insn (0);
7690 insn_start_frag = frag_now;
7691 insn_start_off = frag_now_fix ();
7694 if (i.tm.opcode_modifier.jump)
7696 else if (i.tm.opcode_modifier.jumpbyte
7697 || i.tm.opcode_modifier.jumpdword)
7699 else if (i.tm.opcode_modifier.jumpintersegment)
7700 output_interseg_jump ();
7703 /* Output normal instructions here. */
7707 unsigned int prefix;
7710 && i.tm.base_opcode == 0xfae
7712 && i.imm_operands == 1
7713 && (i.op[0].imms->X_add_number == 0xe8
7714 || i.op[0].imms->X_add_number == 0xf0
7715 || i.op[0].imms->X_add_number == 0xf8))
7717 /* Encode lfence, mfence, and sfence as
7718 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7719 offsetT val = 0x240483f0ULL;
7721 md_number_to_chars (p, val, 5);
7725 /* Some processors fail on LOCK prefix. This options makes
7726 assembler ignore LOCK prefix and serves as a workaround. */
7727 if (omit_lock_prefix)
7729 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7731 i.prefix[LOCK_PREFIX] = 0;
7734 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7735 don't need the explicit prefix. */
7736 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7738 switch (i.tm.opcode_length)
7741 if (i.tm.base_opcode & 0xff000000)
7743 prefix = (i.tm.base_opcode >> 24) & 0xff;
7744 add_prefix (prefix);
7748 if ((i.tm.base_opcode & 0xff0000) != 0)
7750 prefix = (i.tm.base_opcode >> 16) & 0xff;
7751 if (!i.tm.cpu_flags.bitfield.cpupadlock
7752 || prefix != REPE_PREFIX_OPCODE
7753 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7754 add_prefix (prefix);
7760 /* Check for pseudo prefixes. */
7761 as_bad_where (insn_start_frag->fr_file,
7762 insn_start_frag->fr_line,
7763 _("pseudo prefix without instruction"));
7769 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7770 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7771 R_X86_64_GOTTPOFF relocation so that linker can safely
7772 perform IE->LE optimization. */
7773 if (x86_elf_abi == X86_64_X32_ABI
7775 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7776 && i.prefix[REX_PREFIX] == 0)
7777 add_prefix (REX_OPCODE);
7780 /* The prefix bytes. */
7781 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7783 FRAG_APPEND_1_CHAR (*q);
7787 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7792 /* REX byte is encoded in VEX prefix. */
7796 FRAG_APPEND_1_CHAR (*q);
7799 /* There should be no other prefixes for instructions
7804 /* For EVEX instructions i.vrex should become 0 after
7805 build_evex_prefix. For VEX instructions upper 16 registers
7806 aren't available, so VREX should be 0. */
7809 /* Now the VEX prefix. */
7810 p = frag_more (i.vex.length);
7811 for (j = 0; j < i.vex.length; j++)
7812 p[j] = i.vex.bytes[j];
7815 /* Now the opcode; be careful about word order here! */
7816 if (i.tm.opcode_length == 1)
7818 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7822 switch (i.tm.opcode_length)
7826 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7827 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7831 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7841 /* Put out high byte first: can't use md_number_to_chars! */
7842 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7843 *p = i.tm.base_opcode & 0xff;
7846 /* Now the modrm byte and sib byte (if present). */
7847 if (i.tm.opcode_modifier.modrm)
7849 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7852 /* If i.rm.regmem == ESP (4)
7853 && i.rm.mode != (Register mode)
7855 ==> need second modrm byte. */
7856 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7858 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7859 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7861 | i.sib.scale << 6));
7864 if (i.disp_operands)
7865 output_disp (insn_start_frag, insn_start_off);
7868 output_imm (insn_start_frag, insn_start_off);
7874 pi ("" /*line*/, &i);
7876 #endif /* DEBUG386 */
7879 /* Return the size of the displacement operand N. */
7882 disp_size (unsigned int n)
7886 if (i.types[n].bitfield.disp64)
7888 else if (i.types[n].bitfield.disp8)
7890 else if (i.types[n].bitfield.disp16)
7895 /* Return the size of the immediate operand N. */
7898 imm_size (unsigned int n)
7901 if (i.types[n].bitfield.imm64)
7903 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7905 else if (i.types[n].bitfield.imm16)
7911 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7916 for (n = 0; n < i.operands; n++)
7918 if (operand_type_check (i.types[n], disp))
7920 if (i.op[n].disps->X_op == O_constant)
7922 int size = disp_size (n);
7923 offsetT val = i.op[n].disps->X_add_number;
7925 val = offset_in_range (val >> i.memshift, size);
7926 p = frag_more (size);
7927 md_number_to_chars (p, val, size);
7931 enum bfd_reloc_code_real reloc_type;
7932 int size = disp_size (n);
7933 int sign = i.types[n].bitfield.disp32s;
7934 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7937 /* We can't have 8 bit displacement here. */
7938 gas_assert (!i.types[n].bitfield.disp8);
7940 /* The PC relative address is computed relative
7941 to the instruction boundary, so in case immediate
7942 fields follows, we need to adjust the value. */
7943 if (pcrel && i.imm_operands)
7948 for (n1 = 0; n1 < i.operands; n1++)
7949 if (operand_type_check (i.types[n1], imm))
7951 /* Only one immediate is allowed for PC
7952 relative address. */
7953 gas_assert (sz == 0);
7955 i.op[n].disps->X_add_number -= sz;
7957 /* We should find the immediate. */
7958 gas_assert (sz != 0);
7961 p = frag_more (size);
7962 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7964 && GOT_symbol == i.op[n].disps->X_add_symbol
7965 && (((reloc_type == BFD_RELOC_32
7966 || reloc_type == BFD_RELOC_X86_64_32S
7967 || (reloc_type == BFD_RELOC_64
7969 && (i.op[n].disps->X_op == O_symbol
7970 || (i.op[n].disps->X_op == O_add
7971 && ((symbol_get_value_expression
7972 (i.op[n].disps->X_op_symbol)->X_op)
7974 || reloc_type == BFD_RELOC_32_PCREL))
7978 if (insn_start_frag == frag_now)
7979 add = (p - frag_now->fr_literal) - insn_start_off;
7984 add = insn_start_frag->fr_fix - insn_start_off;
7985 for (fr = insn_start_frag->fr_next;
7986 fr && fr != frag_now; fr = fr->fr_next)
7988 add += p - frag_now->fr_literal;
7993 reloc_type = BFD_RELOC_386_GOTPC;
7994 i.op[n].imms->X_add_number += add;
7996 else if (reloc_type == BFD_RELOC_64)
7997 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7999 /* Don't do the adjustment for x86-64, as there
8000 the pcrel addressing is relative to the _next_
8001 insn, and that is taken care of in other code. */
8002 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8004 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8005 size, i.op[n].disps, pcrel,
8007 /* Check for "call/jmp *mem", "mov mem, %reg",
8008 "test %reg, mem" and "binop mem, %reg" where binop
8009 is one of adc, add, and, cmp, or, sbb, sub, xor
8010 instructions. Always generate R_386_GOT32X for
8011 "sym*GOT" operand in 32-bit mode. */
8012 if ((generate_relax_relocations
8015 && i.rm.regmem == 5))
8017 || (i.rm.mode == 0 && i.rm.regmem == 5))
8018 && ((i.operands == 1
8019 && i.tm.base_opcode == 0xff
8020 && (i.rm.reg == 2 || i.rm.reg == 4))
8022 && (i.tm.base_opcode == 0x8b
8023 || i.tm.base_opcode == 0x85
8024 || (i.tm.base_opcode & 0xc7) == 0x03))))
8028 fixP->fx_tcbit = i.rex != 0;
8030 && (i.base_reg->reg_num == RegRip
8031 || i.base_reg->reg_num == RegEip))
8032 fixP->fx_tcbit2 = 1;
8035 fixP->fx_tcbit2 = 1;
8043 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8048 for (n = 0; n < i.operands; n++)
8050 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8051 if (i.rounding && (int) n == i.rounding->operand)
8054 if (operand_type_check (i.types[n], imm))
8056 if (i.op[n].imms->X_op == O_constant)
8058 int size = imm_size (n);
8061 val = offset_in_range (i.op[n].imms->X_add_number,
8063 p = frag_more (size);
8064 md_number_to_chars (p, val, size);
8068 /* Not absolute_section.
8069 Need a 32-bit fixup (don't support 8bit
8070 non-absolute imms). Try to support other
8072 enum bfd_reloc_code_real reloc_type;
8073 int size = imm_size (n);
8076 if (i.types[n].bitfield.imm32s
8077 && (i.suffix == QWORD_MNEM_SUFFIX
8078 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8083 p = frag_more (size);
8084 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8086 /* This is tough to explain. We end up with this one if we
8087 * have operands that look like
8088 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8089 * obtain the absolute address of the GOT, and it is strongly
8090 * preferable from a performance point of view to avoid using
8091 * a runtime relocation for this. The actual sequence of
8092 * instructions often look something like:
8097 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8099 * The call and pop essentially return the absolute address
8100 * of the label .L66 and store it in %ebx. The linker itself
8101 * will ultimately change the first operand of the addl so
8102 * that %ebx points to the GOT, but to keep things simple, the
8103 * .o file must have this operand set so that it generates not
8104 * the absolute address of .L66, but the absolute address of
8105 * itself. This allows the linker itself simply treat a GOTPC
8106 * relocation as asking for a pcrel offset to the GOT to be
8107 * added in, and the addend of the relocation is stored in the
8108 * operand field for the instruction itself.
8110 * Our job here is to fix the operand so that it would add
8111 * the correct offset so that %ebx would point to itself. The
8112 * thing that is tricky is that .-.L66 will point to the
8113 * beginning of the instruction, so we need to further modify
8114 * the operand so that it will point to itself. There are
8115 * other cases where you have something like:
8117 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8119 * and here no correction would be required. Internally in
8120 * the assembler we treat operands of this form as not being
8121 * pcrel since the '.' is explicitly mentioned, and I wonder
8122 * whether it would simplify matters to do it this way. Who
8123 * knows. In earlier versions of the PIC patches, the
8124 * pcrel_adjust field was used to store the correction, but
8125 * since the expression is not pcrel, I felt it would be
8126 * confusing to do it this way. */
8128 if ((reloc_type == BFD_RELOC_32
8129 || reloc_type == BFD_RELOC_X86_64_32S
8130 || reloc_type == BFD_RELOC_64)
8132 && GOT_symbol == i.op[n].imms->X_add_symbol
8133 && (i.op[n].imms->X_op == O_symbol
8134 || (i.op[n].imms->X_op == O_add
8135 && ((symbol_get_value_expression
8136 (i.op[n].imms->X_op_symbol)->X_op)
8141 if (insn_start_frag == frag_now)
8142 add = (p - frag_now->fr_literal) - insn_start_off;
8147 add = insn_start_frag->fr_fix - insn_start_off;
8148 for (fr = insn_start_frag->fr_next;
8149 fr && fr != frag_now; fr = fr->fr_next)
8151 add += p - frag_now->fr_literal;
8155 reloc_type = BFD_RELOC_386_GOTPC;
8157 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8159 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8160 i.op[n].imms->X_add_number += add;
8162 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8163 i.op[n].imms, 0, reloc_type);
8169 /* x86_cons_fix_new is called via the expression parsing code when a
8170 reloc is needed. We use this hook to get the correct .got reloc. */
8171 static int cons_sign = -1;
8174 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8175 expressionS *exp, bfd_reloc_code_real_type r)
8177 r = reloc (len, 0, cons_sign, r);
8180 if (exp->X_op == O_secrel)
8182 exp->X_op = O_symbol;
8183 r = BFD_RELOC_32_SECREL;
8187 fix_new_exp (frag, off, len, exp, 0, r);
8190 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8191 purpose of the `.dc.a' internal pseudo-op. */
8194 x86_address_bytes (void)
8196 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8198 return stdoutput->arch_info->bits_per_address / 8;
8201 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8203 # define lex_got(reloc, adjust, types) NULL
8205 /* Parse operands of the form
8206 <symbol>@GOTOFF+<nnn>
8207 and similar .plt or .got references.
8209 If we find one, set up the correct relocation in RELOC and copy the
8210 input string, minus the `@GOTOFF' into a malloc'd buffer for
8211 parsing by the calling routine. Return this buffer, and if ADJUST
8212 is non-null set it to the length of the string we removed from the
8213 input line. Otherwise return NULL. */
8215 lex_got (enum bfd_reloc_code_real *rel,
8217 i386_operand_type *types)
8219 /* Some of the relocations depend on the size of what field is to
8220 be relocated. But in our callers i386_immediate and i386_displacement
8221 we don't yet know the operand size (this will be set by insn
8222 matching). Hence we record the word32 relocation here,
8223 and adjust the reloc according to the real size in reloc(). */
8224 static const struct {
8227 const enum bfd_reloc_code_real rel[2];
8228 const i386_operand_type types64;
8230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8231 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8233 OPERAND_TYPE_IMM32_64 },
8235 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8236 BFD_RELOC_X86_64_PLTOFF64 },
8237 OPERAND_TYPE_IMM64 },
8238 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8239 BFD_RELOC_X86_64_PLT32 },
8240 OPERAND_TYPE_IMM32_32S_DISP32 },
8241 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8242 BFD_RELOC_X86_64_GOTPLT64 },
8243 OPERAND_TYPE_IMM64_DISP64 },
8244 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8245 BFD_RELOC_X86_64_GOTOFF64 },
8246 OPERAND_TYPE_IMM64_DISP64 },
8247 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8248 BFD_RELOC_X86_64_GOTPCREL },
8249 OPERAND_TYPE_IMM32_32S_DISP32 },
8250 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8251 BFD_RELOC_X86_64_TLSGD },
8252 OPERAND_TYPE_IMM32_32S_DISP32 },
8253 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8254 _dummy_first_bfd_reloc_code_real },
8255 OPERAND_TYPE_NONE },
8256 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8257 BFD_RELOC_X86_64_TLSLD },
8258 OPERAND_TYPE_IMM32_32S_DISP32 },
8259 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8260 BFD_RELOC_X86_64_GOTTPOFF },
8261 OPERAND_TYPE_IMM32_32S_DISP32 },
8262 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8263 BFD_RELOC_X86_64_TPOFF32 },
8264 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8265 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8266 _dummy_first_bfd_reloc_code_real },
8267 OPERAND_TYPE_NONE },
8268 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8269 BFD_RELOC_X86_64_DTPOFF32 },
8270 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8271 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8272 _dummy_first_bfd_reloc_code_real },
8273 OPERAND_TYPE_NONE },
8274 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8275 _dummy_first_bfd_reloc_code_real },
8276 OPERAND_TYPE_NONE },
8277 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8278 BFD_RELOC_X86_64_GOT32 },
8279 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8280 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8281 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8282 OPERAND_TYPE_IMM32_32S_DISP32 },
8283 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8284 BFD_RELOC_X86_64_TLSDESC_CALL },
8285 OPERAND_TYPE_IMM32_32S_DISP32 },
8290 #if defined (OBJ_MAYBE_ELF)
8295 for (cp = input_line_pointer; *cp != '@'; cp++)
8296 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8299 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8301 int len = gotrel[j].len;
8302 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8304 if (gotrel[j].rel[object_64bit] != 0)
8307 char *tmpbuf, *past_reloc;
8309 *rel = gotrel[j].rel[object_64bit];
8313 if (flag_code != CODE_64BIT)
8315 types->bitfield.imm32 = 1;
8316 types->bitfield.disp32 = 1;
8319 *types = gotrel[j].types64;
8322 if (j != 0 && GOT_symbol == NULL)
8323 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8325 /* The length of the first part of our input line. */
8326 first = cp - input_line_pointer;
8328 /* The second part goes from after the reloc token until
8329 (and including) an end_of_line char or comma. */
8330 past_reloc = cp + 1 + len;
8332 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8334 second = cp + 1 - past_reloc;
8336 /* Allocate and copy string. The trailing NUL shouldn't
8337 be necessary, but be safe. */
8338 tmpbuf = XNEWVEC (char, first + second + 2);
8339 memcpy (tmpbuf, input_line_pointer, first);
8340 if (second != 0 && *past_reloc != ' ')
8341 /* Replace the relocation token with ' ', so that
8342 errors like foo@GOTOFF1 will be detected. */
8343 tmpbuf[first++] = ' ';
8345 /* Increment length by 1 if the relocation token is
8350 memcpy (tmpbuf + first, past_reloc, second);
8351 tmpbuf[first + second] = '\0';
8355 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8356 gotrel[j].str, 1 << (5 + object_64bit));
8361 /* Might be a symbol version string. Don't as_bad here. */
8370 /* Parse operands of the form
8371 <symbol>@SECREL32+<nnn>
8373 If we find one, set up the correct relocation in RELOC and copy the
8374 input string, minus the `@SECREL32' into a malloc'd buffer for
8375 parsing by the calling routine. Return this buffer, and if ADJUST
8376 is non-null set it to the length of the string we removed from the
8377 input line. Otherwise return NULL.
8379 This function is copied from the ELF version above adjusted for PE targets. */
8382 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8383 int *adjust ATTRIBUTE_UNUSED,
8384 i386_operand_type *types)
8390 const enum bfd_reloc_code_real rel[2];
8391 const i386_operand_type types64;
8395 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8396 BFD_RELOC_32_SECREL },
8397 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8403 for (cp = input_line_pointer; *cp != '@'; cp++)
8404 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8407 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8409 int len = gotrel[j].len;
8411 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8413 if (gotrel[j].rel[object_64bit] != 0)
8416 char *tmpbuf, *past_reloc;
8418 *rel = gotrel[j].rel[object_64bit];
8424 if (flag_code != CODE_64BIT)
8426 types->bitfield.imm32 = 1;
8427 types->bitfield.disp32 = 1;
8430 *types = gotrel[j].types64;
8433 /* The length of the first part of our input line. */
8434 first = cp - input_line_pointer;
8436 /* The second part goes from after the reloc token until
8437 (and including) an end_of_line char or comma. */
8438 past_reloc = cp + 1 + len;
8440 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8442 second = cp + 1 - past_reloc;
8444 /* Allocate and copy string. The trailing NUL shouldn't
8445 be necessary, but be safe. */
8446 tmpbuf = XNEWVEC (char, first + second + 2);
8447 memcpy (tmpbuf, input_line_pointer, first);
8448 if (second != 0 && *past_reloc != ' ')
8449 /* Replace the relocation token with ' ', so that
8450 errors like foo@SECLREL321 will be detected. */
8451 tmpbuf[first++] = ' ';
8452 memcpy (tmpbuf + first, past_reloc, second);
8453 tmpbuf[first + second] = '\0';
8457 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8458 gotrel[j].str, 1 << (5 + object_64bit));
8463 /* Might be a symbol version string. Don't as_bad here. */
8469 bfd_reloc_code_real_type
8470 x86_cons (expressionS *exp, int size)
8472 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8474 intel_syntax = -intel_syntax;
8477 if (size == 4 || (object_64bit && size == 8))
8479 /* Handle @GOTOFF and the like in an expression. */
8481 char *gotfree_input_line;
8484 save = input_line_pointer;
8485 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8486 if (gotfree_input_line)
8487 input_line_pointer = gotfree_input_line;
8491 if (gotfree_input_line)
8493 /* expression () has merrily parsed up to the end of line,
8494 or a comma - in the wrong buffer. Transfer how far
8495 input_line_pointer has moved to the right buffer. */
8496 input_line_pointer = (save
8497 + (input_line_pointer - gotfree_input_line)
8499 free (gotfree_input_line);
8500 if (exp->X_op == O_constant
8501 || exp->X_op == O_absent
8502 || exp->X_op == O_illegal
8503 || exp->X_op == O_register
8504 || exp->X_op == O_big)
8506 char c = *input_line_pointer;
8507 *input_line_pointer = 0;
8508 as_bad (_("missing or invalid expression `%s'"), save);
8509 *input_line_pointer = c;
8516 intel_syntax = -intel_syntax;
8519 i386_intel_simplify (exp);
8525 signed_cons (int size)
8527 if (flag_code == CODE_64BIT)
8535 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8542 if (exp.X_op == O_symbol)
8543 exp.X_op = O_secrel;
8545 emit_expr (&exp, 4);
8547 while (*input_line_pointer++ == ',');
8549 input_line_pointer--;
8550 demand_empty_rest_of_line ();
8554 /* Handle Vector operations. */
8557 check_VecOperations (char *op_string, char *op_end)
8559 const reg_entry *mask;
8564 && (op_end == NULL || op_string < op_end))
8567 if (*op_string == '{')
8571 /* Check broadcasts. */
8572 if (strncmp (op_string, "1to", 3) == 0)
8577 goto duplicated_vec_op;
8580 if (*op_string == '8')
8582 else if (*op_string == '4')
8584 else if (*op_string == '2')
8586 else if (*op_string == '1'
8587 && *(op_string+1) == '6')
8594 as_bad (_("Unsupported broadcast: `%s'"), saved);
8599 broadcast_op.type = bcst_type;
8600 broadcast_op.operand = this_operand;
8601 i.broadcast = &broadcast_op;
8603 /* Check masking operation. */
8604 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8606 /* k0 can't be used for write mask. */
8607 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8609 as_bad (_("`%s%s' can't be used for write mask"),
8610 register_prefix, mask->reg_name);
8616 mask_op.mask = mask;
8617 mask_op.zeroing = 0;
8618 mask_op.operand = this_operand;
8624 goto duplicated_vec_op;
8626 i.mask->mask = mask;
8628 /* Only "{z}" is allowed here. No need to check
8629 zeroing mask explicitly. */
8630 if (i.mask->operand != this_operand)
8632 as_bad (_("invalid write mask `%s'"), saved);
8639 /* Check zeroing-flag for masking operation. */
8640 else if (*op_string == 'z')
8644 mask_op.mask = NULL;
8645 mask_op.zeroing = 1;
8646 mask_op.operand = this_operand;
8651 if (i.mask->zeroing)
8654 as_bad (_("duplicated `%s'"), saved);
8658 i.mask->zeroing = 1;
8660 /* Only "{%k}" is allowed here. No need to check mask
8661 register explicitly. */
8662 if (i.mask->operand != this_operand)
8664 as_bad (_("invalid zeroing-masking `%s'"),
8673 goto unknown_vec_op;
8675 if (*op_string != '}')
8677 as_bad (_("missing `}' in `%s'"), saved);
8682 /* Strip whitespace since the addition of pseudo prefixes
8683 changed how the scrubber treats '{'. */
8684 if (is_space_char (*op_string))
8690 /* We don't know this one. */
8691 as_bad (_("unknown vector operation: `%s'"), saved);
8695 if (i.mask && i.mask->zeroing && !i.mask->mask)
8697 as_bad (_("zeroing-masking only allowed with write mask"));
8705 i386_immediate (char *imm_start)
8707 char *save_input_line_pointer;
8708 char *gotfree_input_line;
8711 i386_operand_type types;
8713 operand_type_set (&types, ~0);
8715 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8717 as_bad (_("at most %d immediate operands are allowed"),
8718 MAX_IMMEDIATE_OPERANDS);
8722 exp = &im_expressions[i.imm_operands++];
8723 i.op[this_operand].imms = exp;
8725 if (is_space_char (*imm_start))
8728 save_input_line_pointer = input_line_pointer;
8729 input_line_pointer = imm_start;
8731 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8732 if (gotfree_input_line)
8733 input_line_pointer = gotfree_input_line;
8735 exp_seg = expression (exp);
8739 /* Handle vector operations. */
8740 if (*input_line_pointer == '{')
8742 input_line_pointer = check_VecOperations (input_line_pointer,
8744 if (input_line_pointer == NULL)
8748 if (*input_line_pointer)
8749 as_bad (_("junk `%s' after expression"), input_line_pointer);
8751 input_line_pointer = save_input_line_pointer;
8752 if (gotfree_input_line)
8754 free (gotfree_input_line);
8756 if (exp->X_op == O_constant || exp->X_op == O_register)
8757 exp->X_op = O_illegal;
8760 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8764 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8765 i386_operand_type types, const char *imm_start)
8767 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8770 as_bad (_("missing or invalid immediate expression `%s'"),
8774 else if (exp->X_op == O_constant)
8776 /* Size it properly later. */
8777 i.types[this_operand].bitfield.imm64 = 1;
8778 /* If not 64bit, sign extend val. */
8779 if (flag_code != CODE_64BIT
8780 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8782 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8784 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8785 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8786 && exp_seg != absolute_section
8787 && exp_seg != text_section
8788 && exp_seg != data_section
8789 && exp_seg != bss_section
8790 && exp_seg != undefined_section
8791 && !bfd_is_com_section (exp_seg))
8793 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8797 else if (!intel_syntax && exp_seg == reg_section)
8800 as_bad (_("illegal immediate register operand %s"), imm_start);
8805 /* This is an address. The size of the address will be
8806 determined later, depending on destination register,
8807 suffix, or the default for the section. */
8808 i.types[this_operand].bitfield.imm8 = 1;
8809 i.types[this_operand].bitfield.imm16 = 1;
8810 i.types[this_operand].bitfield.imm32 = 1;
8811 i.types[this_operand].bitfield.imm32s = 1;
8812 i.types[this_operand].bitfield.imm64 = 1;
8813 i.types[this_operand] = operand_type_and (i.types[this_operand],
8821 i386_scale (char *scale)
8824 char *save = input_line_pointer;
8826 input_line_pointer = scale;
8827 val = get_absolute_expression ();
8832 i.log2_scale_factor = 0;
8835 i.log2_scale_factor = 1;
8838 i.log2_scale_factor = 2;
8841 i.log2_scale_factor = 3;
8845 char sep = *input_line_pointer;
8847 *input_line_pointer = '\0';
8848 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8850 *input_line_pointer = sep;
8851 input_line_pointer = save;
8855 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8857 as_warn (_("scale factor of %d without an index register"),
8858 1 << i.log2_scale_factor);
8859 i.log2_scale_factor = 0;
8861 scale = input_line_pointer;
8862 input_line_pointer = save;
8867 i386_displacement (char *disp_start, char *disp_end)
8871 char *save_input_line_pointer;
8872 char *gotfree_input_line;
8874 i386_operand_type bigdisp, types = anydisp;
8877 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8879 as_bad (_("at most %d displacement operands are allowed"),
8880 MAX_MEMORY_OPERANDS);
8884 operand_type_set (&bigdisp, 0);
8885 if ((i.types[this_operand].bitfield.jumpabsolute)
8886 || (!current_templates->start->opcode_modifier.jump
8887 && !current_templates->start->opcode_modifier.jumpdword))
8889 bigdisp.bitfield.disp32 = 1;
8890 override = (i.prefix[ADDR_PREFIX] != 0);
8891 if (flag_code == CODE_64BIT)
8895 bigdisp.bitfield.disp32s = 1;
8896 bigdisp.bitfield.disp64 = 1;
8899 else if ((flag_code == CODE_16BIT) ^ override)
8901 bigdisp.bitfield.disp32 = 0;
8902 bigdisp.bitfield.disp16 = 1;
8907 /* For PC-relative branches, the width of the displacement
8908 is dependent upon data size, not address size. */
8909 override = (i.prefix[DATA_PREFIX] != 0);
8910 if (flag_code == CODE_64BIT)
8912 if (override || i.suffix == WORD_MNEM_SUFFIX)
8913 bigdisp.bitfield.disp16 = 1;
8916 bigdisp.bitfield.disp32 = 1;
8917 bigdisp.bitfield.disp32s = 1;
8923 override = (i.suffix == (flag_code != CODE_16BIT
8925 : LONG_MNEM_SUFFIX));
8926 bigdisp.bitfield.disp32 = 1;
8927 if ((flag_code == CODE_16BIT) ^ override)
8929 bigdisp.bitfield.disp32 = 0;
8930 bigdisp.bitfield.disp16 = 1;
8934 i.types[this_operand] = operand_type_or (i.types[this_operand],
8937 exp = &disp_expressions[i.disp_operands];
8938 i.op[this_operand].disps = exp;
8940 save_input_line_pointer = input_line_pointer;
8941 input_line_pointer = disp_start;
8942 END_STRING_AND_SAVE (disp_end);
8944 #ifndef GCC_ASM_O_HACK
8945 #define GCC_ASM_O_HACK 0
8948 END_STRING_AND_SAVE (disp_end + 1);
8949 if (i.types[this_operand].bitfield.baseIndex
8950 && displacement_string_end[-1] == '+')
8952 /* This hack is to avoid a warning when using the "o"
8953 constraint within gcc asm statements.
8956 #define _set_tssldt_desc(n,addr,limit,type) \
8957 __asm__ __volatile__ ( \
8959 "movw %w1,2+%0\n\t" \
8961 "movb %b1,4+%0\n\t" \
8962 "movb %4,5+%0\n\t" \
8963 "movb $0,6+%0\n\t" \
8964 "movb %h1,7+%0\n\t" \
8966 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8968 This works great except that the output assembler ends
8969 up looking a bit weird if it turns out that there is
8970 no offset. You end up producing code that looks like:
8983 So here we provide the missing zero. */
8985 *displacement_string_end = '0';
8988 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8989 if (gotfree_input_line)
8990 input_line_pointer = gotfree_input_line;
8992 exp_seg = expression (exp);
8995 if (*input_line_pointer)
8996 as_bad (_("junk `%s' after expression"), input_line_pointer);
8998 RESTORE_END_STRING (disp_end + 1);
9000 input_line_pointer = save_input_line_pointer;
9001 if (gotfree_input_line)
9003 free (gotfree_input_line);
9005 if (exp->X_op == O_constant || exp->X_op == O_register)
9006 exp->X_op = O_illegal;
9009 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9011 RESTORE_END_STRING (disp_end);
9017 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9018 i386_operand_type types, const char *disp_start)
9020 i386_operand_type bigdisp;
9023 /* We do this to make sure that the section symbol is in
9024 the symbol table. We will ultimately change the relocation
9025 to be relative to the beginning of the section. */
9026 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9027 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9028 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9030 if (exp->X_op != O_symbol)
9033 if (S_IS_LOCAL (exp->X_add_symbol)
9034 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9035 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9036 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9037 exp->X_op = O_subtract;
9038 exp->X_op_symbol = GOT_symbol;
9039 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9040 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9041 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9042 i.reloc[this_operand] = BFD_RELOC_64;
9044 i.reloc[this_operand] = BFD_RELOC_32;
9047 else if (exp->X_op == O_absent
9048 || exp->X_op == O_illegal
9049 || exp->X_op == O_big)
9052 as_bad (_("missing or invalid displacement expression `%s'"),
9057 else if (flag_code == CODE_64BIT
9058 && !i.prefix[ADDR_PREFIX]
9059 && exp->X_op == O_constant)
9061 /* Since displacement is signed extended to 64bit, don't allow
9062 disp32 and turn off disp32s if they are out of range. */
9063 i.types[this_operand].bitfield.disp32 = 0;
9064 if (!fits_in_signed_long (exp->X_add_number))
9066 i.types[this_operand].bitfield.disp32s = 0;
9067 if (i.types[this_operand].bitfield.baseindex)
9069 as_bad (_("0x%lx out range of signed 32bit displacement"),
9070 (long) exp->X_add_number);
9076 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9077 else if (exp->X_op != O_constant
9078 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9079 && exp_seg != absolute_section
9080 && exp_seg != text_section
9081 && exp_seg != data_section
9082 && exp_seg != bss_section
9083 && exp_seg != undefined_section
9084 && !bfd_is_com_section (exp_seg))
9086 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9091 /* Check if this is a displacement only operand. */
9092 bigdisp = i.types[this_operand];
9093 bigdisp.bitfield.disp8 = 0;
9094 bigdisp.bitfield.disp16 = 0;
9095 bigdisp.bitfield.disp32 = 0;
9096 bigdisp.bitfield.disp32s = 0;
9097 bigdisp.bitfield.disp64 = 0;
9098 if (operand_type_all_zero (&bigdisp))
9099 i.types[this_operand] = operand_type_and (i.types[this_operand],
9105 /* Return the active addressing mode, taking address override and
9106 registers forming the address into consideration. Update the
9107 address override prefix if necessary. */
9109 static enum flag_code
9110 i386_addressing_mode (void)
9112 enum flag_code addr_mode;
9114 if (i.prefix[ADDR_PREFIX])
9115 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9118 addr_mode = flag_code;
9120 #if INFER_ADDR_PREFIX
9121 if (i.mem_operands == 0)
9123 /* Infer address prefix from the first memory operand. */
9124 const reg_entry *addr_reg = i.base_reg;
9126 if (addr_reg == NULL)
9127 addr_reg = i.index_reg;
9131 if (addr_reg->reg_num == RegEip
9132 || addr_reg->reg_num == RegEiz
9133 || addr_reg->reg_type.bitfield.dword)
9134 addr_mode = CODE_32BIT;
9135 else if (flag_code != CODE_64BIT
9136 && addr_reg->reg_type.bitfield.word)
9137 addr_mode = CODE_16BIT;
9139 if (addr_mode != flag_code)
9141 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9143 /* Change the size of any displacement too. At most one
9144 of Disp16 or Disp32 is set.
9145 FIXME. There doesn't seem to be any real need for
9146 separate Disp16 and Disp32 flags. The same goes for
9147 Imm16 and Imm32. Removing them would probably clean
9148 up the code quite a lot. */
9149 if (flag_code != CODE_64BIT
9150 && (i.types[this_operand].bitfield.disp16
9151 || i.types[this_operand].bitfield.disp32))
9152 i.types[this_operand]
9153 = operand_type_xor (i.types[this_operand], disp16_32);
9163 /* Make sure the memory operand we've been dealt is valid.
9164 Return 1 on success, 0 on a failure. */
9167 i386_index_check (const char *operand_string)
9169 const char *kind = "base/index";
9170 enum flag_code addr_mode = i386_addressing_mode ();
9172 if (current_templates->start->opcode_modifier.isstring
9173 && !current_templates->start->opcode_modifier.immext
9174 && (current_templates->end[-1].opcode_modifier.isstring
9177 /* Memory operands of string insns are special in that they only allow
9178 a single register (rDI, rSI, or rBX) as their memory address. */
9179 const reg_entry *expected_reg;
9180 static const char *di_si[][2] =
9186 static const char *bx[] = { "ebx", "bx", "rbx" };
9188 kind = "string address";
9190 if (current_templates->start->opcode_modifier.repprefixok)
9192 i386_operand_type type = current_templates->end[-1].operand_types[0];
9194 if (!type.bitfield.baseindex
9195 || ((!i.mem_operands != !intel_syntax)
9196 && current_templates->end[-1].operand_types[1]
9197 .bitfield.baseindex))
9198 type = current_templates->end[-1].operand_types[1];
9199 expected_reg = hash_find (reg_hash,
9200 di_si[addr_mode][type.bitfield.esseg]);
9204 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9206 if (i.base_reg != expected_reg
9208 || operand_type_check (i.types[this_operand], disp))
9210 /* The second memory operand must have the same size as
9214 && !((addr_mode == CODE_64BIT
9215 && i.base_reg->reg_type.bitfield.qword)
9216 || (addr_mode == CODE_32BIT
9217 ? i.base_reg->reg_type.bitfield.dword
9218 : i.base_reg->reg_type.bitfield.word)))
9221 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9223 intel_syntax ? '[' : '(',
9225 expected_reg->reg_name,
9226 intel_syntax ? ']' : ')');
9233 as_bad (_("`%s' is not a valid %s expression"),
9234 operand_string, kind);
9239 if (addr_mode != CODE_16BIT)
9241 /* 32-bit/64-bit checks. */
9243 && (addr_mode == CODE_64BIT
9244 ? !i.base_reg->reg_type.bitfield.qword
9245 : !i.base_reg->reg_type.bitfield.dword)
9247 || (i.base_reg->reg_num
9248 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9250 && !i.index_reg->reg_type.bitfield.xmmword
9251 && !i.index_reg->reg_type.bitfield.ymmword
9252 && !i.index_reg->reg_type.bitfield.zmmword
9253 && ((addr_mode == CODE_64BIT
9254 ? !(i.index_reg->reg_type.bitfield.qword
9255 || i.index_reg->reg_num == RegRiz)
9256 : !(i.index_reg->reg_type.bitfield.dword
9257 || i.index_reg->reg_num == RegEiz))
9258 || !i.index_reg->reg_type.bitfield.baseindex)))
9261 /* bndmk, bndldx, and bndstx have special restrictions. */
9262 if (current_templates->start->base_opcode == 0xf30f1b
9263 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9265 /* They cannot use RIP-relative addressing. */
9266 if (i.base_reg && i.base_reg->reg_num == RegRip)
9268 as_bad (_("`%s' cannot be used here"), operand_string);
9272 /* bndldx and bndstx ignore their scale factor. */
9273 if (current_templates->start->base_opcode != 0xf30f1b
9274 && i.log2_scale_factor)
9275 as_warn (_("register scaling is being ignored here"));
9280 /* 16-bit checks. */
9282 && (!i.base_reg->reg_type.bitfield.word
9283 || !i.base_reg->reg_type.bitfield.baseindex))
9285 && (!i.index_reg->reg_type.bitfield.word
9286 || !i.index_reg->reg_type.bitfield.baseindex
9288 && i.base_reg->reg_num < 6
9289 && i.index_reg->reg_num >= 6
9290 && i.log2_scale_factor == 0))))
9297 /* Handle vector immediates. */
9300 RC_SAE_immediate (const char *imm_start)
9302 unsigned int match_found, j;
9303 const char *pstr = imm_start;
9311 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9313 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9317 rc_op.type = RC_NamesTable[j].type;
9318 rc_op.operand = this_operand;
9319 i.rounding = &rc_op;
9323 as_bad (_("duplicated `%s'"), imm_start);
9326 pstr += RC_NamesTable[j].len;
9336 as_bad (_("Missing '}': '%s'"), imm_start);
9339 /* RC/SAE immediate string should contain nothing more. */;
9342 as_bad (_("Junk after '}': '%s'"), imm_start);
9346 exp = &im_expressions[i.imm_operands++];
9347 i.op[this_operand].imms = exp;
9349 exp->X_op = O_constant;
9350 exp->X_add_number = 0;
9351 exp->X_add_symbol = (symbolS *) 0;
9352 exp->X_op_symbol = (symbolS *) 0;
9354 i.types[this_operand].bitfield.imm8 = 1;
9358 /* Only string instructions can have a second memory operand, so
9359 reduce current_templates to just those if it contains any. */
9361 maybe_adjust_templates (void)
9363 const insn_template *t;
9365 gas_assert (i.mem_operands == 1);
9367 for (t = current_templates->start; t < current_templates->end; ++t)
9368 if (t->opcode_modifier.isstring)
9371 if (t < current_templates->end)
9373 static templates aux_templates;
9374 bfd_boolean recheck;
9376 aux_templates.start = t;
9377 for (; t < current_templates->end; ++t)
9378 if (!t->opcode_modifier.isstring)
9380 aux_templates.end = t;
9382 /* Determine whether to re-check the first memory operand. */
9383 recheck = (aux_templates.start != current_templates->start
9384 || t != current_templates->end);
9386 current_templates = &aux_templates;
9391 if (i.memop1_string != NULL
9392 && i386_index_check (i.memop1_string) == 0)
9401 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9405 i386_att_operand (char *operand_string)
9409 char *op_string = operand_string;
9411 if (is_space_char (*op_string))
9414 /* We check for an absolute prefix (differentiating,
9415 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9416 if (*op_string == ABSOLUTE_PREFIX)
9419 if (is_space_char (*op_string))
9421 i.types[this_operand].bitfield.jumpabsolute = 1;
9424 /* Check if operand is a register. */
9425 if ((r = parse_register (op_string, &end_op)) != NULL)
9427 i386_operand_type temp;
9429 /* Check for a segment override by searching for ':' after a
9430 segment register. */
9432 if (is_space_char (*op_string))
9434 if (*op_string == ':'
9435 && (r->reg_type.bitfield.sreg2
9436 || r->reg_type.bitfield.sreg3))
9441 i.seg[i.mem_operands] = &es;
9444 i.seg[i.mem_operands] = &cs;
9447 i.seg[i.mem_operands] = &ss;
9450 i.seg[i.mem_operands] = &ds;
9453 i.seg[i.mem_operands] = &fs;
9456 i.seg[i.mem_operands] = &gs;
9460 /* Skip the ':' and whitespace. */
9462 if (is_space_char (*op_string))
9465 if (!is_digit_char (*op_string)
9466 && !is_identifier_char (*op_string)
9467 && *op_string != '('
9468 && *op_string != ABSOLUTE_PREFIX)
9470 as_bad (_("bad memory operand `%s'"), op_string);
9473 /* Handle case of %es:*foo. */
9474 if (*op_string == ABSOLUTE_PREFIX)
9477 if (is_space_char (*op_string))
9479 i.types[this_operand].bitfield.jumpabsolute = 1;
9481 goto do_memory_reference;
9484 /* Handle vector operations. */
9485 if (*op_string == '{')
9487 op_string = check_VecOperations (op_string, NULL);
9488 if (op_string == NULL)
9494 as_bad (_("junk `%s' after register"), op_string);
9498 temp.bitfield.baseindex = 0;
9499 i.types[this_operand] = operand_type_or (i.types[this_operand],
9501 i.types[this_operand].bitfield.unspecified = 0;
9502 i.op[this_operand].regs = r;
9505 else if (*op_string == REGISTER_PREFIX)
9507 as_bad (_("bad register name `%s'"), op_string);
9510 else if (*op_string == IMMEDIATE_PREFIX)
9513 if (i.types[this_operand].bitfield.jumpabsolute)
9515 as_bad (_("immediate operand illegal with absolute jump"));
9518 if (!i386_immediate (op_string))
9521 else if (RC_SAE_immediate (operand_string))
9523 /* If it is a RC or SAE immediate, do nothing. */
9526 else if (is_digit_char (*op_string)
9527 || is_identifier_char (*op_string)
9528 || *op_string == '"'
9529 || *op_string == '(')
9531 /* This is a memory reference of some sort. */
9534 /* Start and end of displacement string expression (if found). */
9535 char *displacement_string_start;
9536 char *displacement_string_end;
9539 do_memory_reference:
9540 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9542 if ((i.mem_operands == 1
9543 && !current_templates->start->opcode_modifier.isstring)
9544 || i.mem_operands == 2)
9546 as_bad (_("too many memory references for `%s'"),
9547 current_templates->start->name);
9551 /* Check for base index form. We detect the base index form by
9552 looking for an ')' at the end of the operand, searching
9553 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9555 base_string = op_string + strlen (op_string);
9557 /* Handle vector operations. */
9558 vop_start = strchr (op_string, '{');
9559 if (vop_start && vop_start < base_string)
9561 if (check_VecOperations (vop_start, base_string) == NULL)
9563 base_string = vop_start;
9567 if (is_space_char (*base_string))
9570 /* If we only have a displacement, set-up for it to be parsed later. */
9571 displacement_string_start = op_string;
9572 displacement_string_end = base_string + 1;
9574 if (*base_string == ')')
9577 unsigned int parens_balanced = 1;
9578 /* We've already checked that the number of left & right ()'s are
9579 equal, so this loop will not be infinite. */
9583 if (*base_string == ')')
9585 if (*base_string == '(')
9588 while (parens_balanced);
9590 temp_string = base_string;
9592 /* Skip past '(' and whitespace. */
9594 if (is_space_char (*base_string))
9597 if (*base_string == ','
9598 || ((i.base_reg = parse_register (base_string, &end_op))
9601 displacement_string_end = temp_string;
9603 i.types[this_operand].bitfield.baseindex = 1;
9607 base_string = end_op;
9608 if (is_space_char (*base_string))
9612 /* There may be an index reg or scale factor here. */
9613 if (*base_string == ',')
9616 if (is_space_char (*base_string))
9619 if ((i.index_reg = parse_register (base_string, &end_op))
9622 base_string = end_op;
9623 if (is_space_char (*base_string))
9625 if (*base_string == ',')
9628 if (is_space_char (*base_string))
9631 else if (*base_string != ')')
9633 as_bad (_("expecting `,' or `)' "
9634 "after index register in `%s'"),
9639 else if (*base_string == REGISTER_PREFIX)
9641 end_op = strchr (base_string, ',');
9644 as_bad (_("bad register name `%s'"), base_string);
9648 /* Check for scale factor. */
9649 if (*base_string != ')')
9651 char *end_scale = i386_scale (base_string);
9656 base_string = end_scale;
9657 if (is_space_char (*base_string))
9659 if (*base_string != ')')
9661 as_bad (_("expecting `)' "
9662 "after scale factor in `%s'"),
9667 else if (!i.index_reg)
9669 as_bad (_("expecting index register or scale factor "
9670 "after `,'; got '%c'"),
9675 else if (*base_string != ')')
9677 as_bad (_("expecting `,' or `)' "
9678 "after base register in `%s'"),
9683 else if (*base_string == REGISTER_PREFIX)
9685 end_op = strchr (base_string, ',');
9688 as_bad (_("bad register name `%s'"), base_string);
9693 /* If there's an expression beginning the operand, parse it,
9694 assuming displacement_string_start and
9695 displacement_string_end are meaningful. */
9696 if (displacement_string_start != displacement_string_end)
9698 if (!i386_displacement (displacement_string_start,
9699 displacement_string_end))
9703 /* Special case for (%dx) while doing input/output op. */
9705 && i.base_reg->reg_type.bitfield.inoutportreg
9707 && i.log2_scale_factor == 0
9708 && i.seg[i.mem_operands] == 0
9709 && !operand_type_check (i.types[this_operand], disp))
9711 i.types[this_operand] = i.base_reg->reg_type;
9715 if (i386_index_check (operand_string) == 0)
9717 i.types[this_operand].bitfield.mem = 1;
9718 if (i.mem_operands == 0)
9719 i.memop1_string = xstrdup (operand_string);
9724 /* It's not a memory operand; argh! */
9725 as_bad (_("invalid char %s beginning operand %d `%s'"),
9726 output_invalid (*op_string),
9731 return 1; /* Normal return. */
9734 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9735 that an rs_machine_dependent frag may reach. */
9738 i386_frag_max_var (fragS *frag)
9740 /* The only relaxable frags are for jumps.
9741 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9742 gas_assert (frag->fr_type == rs_machine_dependent);
9743 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9746 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9748 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9750 /* STT_GNU_IFUNC symbol must go through PLT. */
9751 if ((symbol_get_bfdsym (fr_symbol)->flags
9752 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9755 if (!S_IS_EXTERNAL (fr_symbol))
9756 /* Symbol may be weak or local. */
9757 return !S_IS_WEAK (fr_symbol);
9759 /* Global symbols with non-default visibility can't be preempted. */
9760 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9763 if (fr_var != NO_RELOC)
9764 switch ((enum bfd_reloc_code_real) fr_var)
9766 case BFD_RELOC_386_PLT32:
9767 case BFD_RELOC_X86_64_PLT32:
9768 /* Symbol with PLT relocation may be preempted. */
9774 /* Global symbols with default visibility in a shared library may be
9775 preempted by another definition. */
9780 /* md_estimate_size_before_relax()
9782 Called just before relax() for rs_machine_dependent frags. The x86
9783 assembler uses these frags to handle variable size jump
9786 Any symbol that is now undefined will not become defined.
9787 Return the correct fr_subtype in the frag.
9788 Return the initial "guess for variable size of frag" to caller.
9789 The guess is actually the growth beyond the fixed part. Whatever
9790 we do to grow the fixed or variable part contributes to our
9794 md_estimate_size_before_relax (fragS *fragP, segT segment)
9796 /* We've already got fragP->fr_subtype right; all we have to do is
9797 check for un-relaxable symbols. On an ELF system, we can't relax
9798 an externally visible symbol, because it may be overridden by a
9800 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9801 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9803 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9806 #if defined (OBJ_COFF) && defined (TE_PE)
9807 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9808 && S_IS_WEAK (fragP->fr_symbol))
9812 /* Symbol is undefined in this segment, or we need to keep a
9813 reloc so that weak symbols can be overridden. */
9814 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9815 enum bfd_reloc_code_real reloc_type;
9816 unsigned char *opcode;
9819 if (fragP->fr_var != NO_RELOC)
9820 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9822 reloc_type = BFD_RELOC_16_PCREL;
9823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9824 else if (need_plt32_p (fragP->fr_symbol))
9825 reloc_type = BFD_RELOC_X86_64_PLT32;
9828 reloc_type = BFD_RELOC_32_PCREL;
9830 old_fr_fix = fragP->fr_fix;
9831 opcode = (unsigned char *) fragP->fr_opcode;
9833 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9836 /* Make jmp (0xeb) a (d)word displacement jump. */
9838 fragP->fr_fix += size;
9839 fix_new (fragP, old_fr_fix, size,
9841 fragP->fr_offset, 1,
9847 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9849 /* Negate the condition, and branch past an
9850 unconditional jump. */
9853 /* Insert an unconditional jump. */
9855 /* We added two extra opcode bytes, and have a two byte
9857 fragP->fr_fix += 2 + 2;
9858 fix_new (fragP, old_fr_fix + 2, 2,
9860 fragP->fr_offset, 1,
9867 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9872 fixP = fix_new (fragP, old_fr_fix, 1,
9874 fragP->fr_offset, 1,
9876 fixP->fx_signed = 1;
9880 /* This changes the byte-displacement jump 0x7N
9881 to the (d)word-displacement jump 0x0f,0x8N. */
9882 opcode[1] = opcode[0] + 0x10;
9883 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9884 /* We've added an opcode byte. */
9885 fragP->fr_fix += 1 + size;
9886 fix_new (fragP, old_fr_fix + 1, size,
9888 fragP->fr_offset, 1,
9893 BAD_CASE (fragP->fr_subtype);
9897 return fragP->fr_fix - old_fr_fix;
9900 /* Guess size depending on current relax state. Initially the relax
9901 state will correspond to a short jump and we return 1, because
9902 the variable part of the frag (the branch offset) is one byte
9903 long. However, we can relax a section more than once and in that
9904 case we must either set fr_subtype back to the unrelaxed state,
9905 or return the value for the appropriate branch. */
9906 return md_relax_table[fragP->fr_subtype].rlx_length;
9909 /* Called after relax() is finished.
9911 In: Address of frag.
9912 fr_type == rs_machine_dependent.
9913 fr_subtype is what the address relaxed to.
9915 Out: Any fixSs and constants are set up.
9916 Caller will turn frag into a ".space 0". */
9919 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9922 unsigned char *opcode;
9923 unsigned char *where_to_put_displacement = NULL;
9924 offsetT target_address;
9925 offsetT opcode_address;
9926 unsigned int extension = 0;
9927 offsetT displacement_from_opcode_start;
9929 opcode = (unsigned char *) fragP->fr_opcode;
9931 /* Address we want to reach in file space. */
9932 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9934 /* Address opcode resides at in file space. */
9935 opcode_address = fragP->fr_address + fragP->fr_fix;
9937 /* Displacement from opcode start to fill into instruction. */
9938 displacement_from_opcode_start = target_address - opcode_address;
9940 if ((fragP->fr_subtype & BIG) == 0)
9942 /* Don't have to change opcode. */
9943 extension = 1; /* 1 opcode + 1 displacement */
9944 where_to_put_displacement = &opcode[1];
9948 if (no_cond_jump_promotion
9949 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9950 as_warn_where (fragP->fr_file, fragP->fr_line,
9951 _("long jump required"));
9953 switch (fragP->fr_subtype)
9955 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9956 extension = 4; /* 1 opcode + 4 displacement */
9958 where_to_put_displacement = &opcode[1];
9961 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9962 extension = 2; /* 1 opcode + 2 displacement */
9964 where_to_put_displacement = &opcode[1];
9967 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9968 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9969 extension = 5; /* 2 opcode + 4 displacement */
9970 opcode[1] = opcode[0] + 0x10;
9971 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9972 where_to_put_displacement = &opcode[2];
9975 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9976 extension = 3; /* 2 opcode + 2 displacement */
9977 opcode[1] = opcode[0] + 0x10;
9978 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9979 where_to_put_displacement = &opcode[2];
9982 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9987 where_to_put_displacement = &opcode[3];
9991 BAD_CASE (fragP->fr_subtype);
9996 /* If size if less then four we are sure that the operand fits,
9997 but if it's 4, then it could be that the displacement is larger
9999 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10001 && ((addressT) (displacement_from_opcode_start - extension
10002 + ((addressT) 1 << 31))
10003 > (((addressT) 2 << 31) - 1)))
10005 as_bad_where (fragP->fr_file, fragP->fr_line,
10006 _("jump target out of range"));
10007 /* Make us emit 0. */
10008 displacement_from_opcode_start = extension;
10010 /* Now put displacement after opcode. */
10011 md_number_to_chars ((char *) where_to_put_displacement,
10012 (valueT) (displacement_from_opcode_start - extension),
10013 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10014 fragP->fr_fix += extension;
10017 /* Apply a fixup (fixP) to segment data, once it has been determined
10018 by our caller that we have all the info we need to fix it up.
10020 Parameter valP is the pointer to the value of the bits.
10022 On the 386, immediates, displacements, and data pointers are all in
10023 the same (little-endian) format, so we don't need to care about which
10024 we are handling. */
10027 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10029 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10030 valueT value = *valP;
10032 #if !defined (TE_Mach)
10033 if (fixP->fx_pcrel)
10035 switch (fixP->fx_r_type)
10041 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10044 case BFD_RELOC_X86_64_32S:
10045 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10048 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10051 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10056 if (fixP->fx_addsy != NULL
10057 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10058 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10059 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10060 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10061 && !use_rela_relocations)
10063 /* This is a hack. There should be a better way to handle this.
10064 This covers for the fact that bfd_install_relocation will
10065 subtract the current location (for partial_inplace, PC relative
10066 relocations); see more below. */
10070 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10073 value += fixP->fx_where + fixP->fx_frag->fr_address;
10075 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10080 if ((sym_seg == seg
10081 || (symbol_section_p (fixP->fx_addsy)
10082 && sym_seg != absolute_section))
10083 && !generic_force_reloc (fixP))
10085 /* Yes, we add the values in twice. This is because
10086 bfd_install_relocation subtracts them out again. I think
10087 bfd_install_relocation is broken, but I don't dare change
10089 value += fixP->fx_where + fixP->fx_frag->fr_address;
10093 #if defined (OBJ_COFF) && defined (TE_PE)
10094 /* For some reason, the PE format does not store a
10095 section address offset for a PC relative symbol. */
10096 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10097 || S_IS_WEAK (fixP->fx_addsy))
10098 value += md_pcrel_from (fixP);
10101 #if defined (OBJ_COFF) && defined (TE_PE)
10102 if (fixP->fx_addsy != NULL
10103 && S_IS_WEAK (fixP->fx_addsy)
10104 /* PR 16858: Do not modify weak function references. */
10105 && ! fixP->fx_pcrel)
10107 #if !defined (TE_PEP)
10108 /* For x86 PE weak function symbols are neither PC-relative
10109 nor do they set S_IS_FUNCTION. So the only reliable way
10110 to detect them is to check the flags of their containing
10112 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10113 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10117 value -= S_GET_VALUE (fixP->fx_addsy);
10121 /* Fix a few things - the dynamic linker expects certain values here,
10122 and we must not disappoint it. */
10123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10124 if (IS_ELF && fixP->fx_addsy)
10125 switch (fixP->fx_r_type)
10127 case BFD_RELOC_386_PLT32:
10128 case BFD_RELOC_X86_64_PLT32:
10129 /* Make the jump instruction point to the address of the operand. At
10130 runtime we merely add the offset to the actual PLT entry. */
10134 case BFD_RELOC_386_TLS_GD:
10135 case BFD_RELOC_386_TLS_LDM:
10136 case BFD_RELOC_386_TLS_IE_32:
10137 case BFD_RELOC_386_TLS_IE:
10138 case BFD_RELOC_386_TLS_GOTIE:
10139 case BFD_RELOC_386_TLS_GOTDESC:
10140 case BFD_RELOC_X86_64_TLSGD:
10141 case BFD_RELOC_X86_64_TLSLD:
10142 case BFD_RELOC_X86_64_GOTTPOFF:
10143 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10144 value = 0; /* Fully resolved at runtime. No addend. */
10146 case BFD_RELOC_386_TLS_LE:
10147 case BFD_RELOC_386_TLS_LDO_32:
10148 case BFD_RELOC_386_TLS_LE_32:
10149 case BFD_RELOC_X86_64_DTPOFF32:
10150 case BFD_RELOC_X86_64_DTPOFF64:
10151 case BFD_RELOC_X86_64_TPOFF32:
10152 case BFD_RELOC_X86_64_TPOFF64:
10153 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10156 case BFD_RELOC_386_TLS_DESC_CALL:
10157 case BFD_RELOC_X86_64_TLSDESC_CALL:
10158 value = 0; /* Fully resolved at runtime. No addend. */
10159 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10163 case BFD_RELOC_VTABLE_INHERIT:
10164 case BFD_RELOC_VTABLE_ENTRY:
10171 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10173 #endif /* !defined (TE_Mach) */
10175 /* Are we finished with this relocation now? */
10176 if (fixP->fx_addsy == NULL)
10178 #if defined (OBJ_COFF) && defined (TE_PE)
10179 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10182 /* Remember value for tc_gen_reloc. */
10183 fixP->fx_addnumber = value;
10184 /* Clear out the frag for now. */
10188 else if (use_rela_relocations)
10190 fixP->fx_no_overflow = 1;
10191 /* Remember value for tc_gen_reloc. */
10192 fixP->fx_addnumber = value;
10196 md_number_to_chars (p, value, fixP->fx_size);
10200 md_atof (int type, char *litP, int *sizeP)
10202 /* This outputs the LITTLENUMs in REVERSE order;
10203 in accord with the bigendian 386. */
10204 return ieee_md_atof (type, litP, sizeP, FALSE);
10207 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10210 output_invalid (int c)
10213 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10216 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10217 "(0x%x)", (unsigned char) c);
10218 return output_invalid_buf;
10221 /* REG_STRING starts *before* REGISTER_PREFIX. */
10223 static const reg_entry *
10224 parse_real_register (char *reg_string, char **end_op)
10226 char *s = reg_string;
10228 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10229 const reg_entry *r;
10231 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10232 if (*s == REGISTER_PREFIX)
10235 if (is_space_char (*s))
10238 p = reg_name_given;
10239 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10241 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10242 return (const reg_entry *) NULL;
10246 /* For naked regs, make sure that we are not dealing with an identifier.
10247 This prevents confusing an identifier like `eax_var' with register
10249 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10250 return (const reg_entry *) NULL;
10254 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10256 /* Handle floating point regs, allowing spaces in the (i) part. */
10257 if (r == i386_regtab /* %st is first entry of table */)
10259 if (!cpu_arch_flags.bitfield.cpu8087
10260 && !cpu_arch_flags.bitfield.cpu287
10261 && !cpu_arch_flags.bitfield.cpu387)
10262 return (const reg_entry *) NULL;
10264 if (is_space_char (*s))
10269 if (is_space_char (*s))
10271 if (*s >= '0' && *s <= '7')
10273 int fpr = *s - '0';
10275 if (is_space_char (*s))
10280 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10285 /* We have "%st(" then garbage. */
10286 return (const reg_entry *) NULL;
10290 if (r == NULL || allow_pseudo_reg)
10293 if (operand_type_all_zero (&r->reg_type))
10294 return (const reg_entry *) NULL;
10296 if ((r->reg_type.bitfield.dword
10297 || r->reg_type.bitfield.sreg3
10298 || r->reg_type.bitfield.control
10299 || r->reg_type.bitfield.debug
10300 || r->reg_type.bitfield.test)
10301 && !cpu_arch_flags.bitfield.cpui386)
10302 return (const reg_entry *) NULL;
10304 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10305 return (const reg_entry *) NULL;
10307 if (!cpu_arch_flags.bitfield.cpuavx512f)
10309 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10310 return (const reg_entry *) NULL;
10312 if (!cpu_arch_flags.bitfield.cpuavx)
10314 if (r->reg_type.bitfield.ymmword)
10315 return (const reg_entry *) NULL;
10317 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10318 return (const reg_entry *) NULL;
10322 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10323 return (const reg_entry *) NULL;
10325 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10326 if (!allow_index_reg
10327 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10328 return (const reg_entry *) NULL;
10330 /* Upper 16 vector registers are only available with VREX in 64bit
10331 mode, and require EVEX encoding. */
10332 if (r->reg_flags & RegVRex)
10334 if (!cpu_arch_flags.bitfield.cpuvrex
10335 || flag_code != CODE_64BIT)
10336 return (const reg_entry *) NULL;
10338 i.vec_encoding = vex_encoding_evex;
10341 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10342 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10343 && flag_code != CODE_64BIT)
10344 return (const reg_entry *) NULL;
10346 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10347 return (const reg_entry *) NULL;
10352 /* REG_STRING starts *before* REGISTER_PREFIX. */
10354 static const reg_entry *
10355 parse_register (char *reg_string, char **end_op)
10357 const reg_entry *r;
10359 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10360 r = parse_real_register (reg_string, end_op);
10365 char *save = input_line_pointer;
10369 input_line_pointer = reg_string;
10370 c = get_symbol_name (®_string);
10371 symbolP = symbol_find (reg_string);
10372 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10374 const expressionS *e = symbol_get_value_expression (symbolP);
10376 know (e->X_op == O_register);
10377 know (e->X_add_number >= 0
10378 && (valueT) e->X_add_number < i386_regtab_size);
10379 r = i386_regtab + e->X_add_number;
10380 if ((r->reg_flags & RegVRex))
10381 i.vec_encoding = vex_encoding_evex;
10382 *end_op = input_line_pointer;
10384 *input_line_pointer = c;
10385 input_line_pointer = save;
10391 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10393 const reg_entry *r;
10394 char *end = input_line_pointer;
10397 r = parse_register (name, &input_line_pointer);
10398 if (r && end <= input_line_pointer)
10400 *nextcharP = *input_line_pointer;
10401 *input_line_pointer = 0;
10402 e->X_op = O_register;
10403 e->X_add_number = r - i386_regtab;
10406 input_line_pointer = end;
10408 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10412 md_operand (expressionS *e)
10415 const reg_entry *r;
10417 switch (*input_line_pointer)
10419 case REGISTER_PREFIX:
10420 r = parse_real_register (input_line_pointer, &end);
10423 e->X_op = O_register;
10424 e->X_add_number = r - i386_regtab;
10425 input_line_pointer = end;
10430 gas_assert (intel_syntax);
10431 end = input_line_pointer++;
10433 if (*input_line_pointer == ']')
10435 ++input_line_pointer;
10436 e->X_op_symbol = make_expr_symbol (e);
10437 e->X_add_symbol = NULL;
10438 e->X_add_number = 0;
10443 e->X_op = O_absent;
10444 input_line_pointer = end;
10451 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10452 const char *md_shortopts = "kVQ:sqnO::";
10454 const char *md_shortopts = "qnO::";
10457 #define OPTION_32 (OPTION_MD_BASE + 0)
10458 #define OPTION_64 (OPTION_MD_BASE + 1)
10459 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10460 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10461 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10462 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10463 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10464 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10465 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10466 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10467 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10468 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10469 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10470 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10471 #define OPTION_X32 (OPTION_MD_BASE + 14)
10472 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10473 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10474 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10475 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10476 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10477 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10478 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10479 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10480 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10481 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10483 struct option md_longopts[] =
10485 {"32", no_argument, NULL, OPTION_32},
10486 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10487 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10488 {"64", no_argument, NULL, OPTION_64},
10490 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10491 {"x32", no_argument, NULL, OPTION_X32},
10492 {"mshared", no_argument, NULL, OPTION_MSHARED},
10494 {"divide", no_argument, NULL, OPTION_DIVIDE},
10495 {"march", required_argument, NULL, OPTION_MARCH},
10496 {"mtune", required_argument, NULL, OPTION_MTUNE},
10497 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10498 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10499 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10500 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10501 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10502 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10503 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10504 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10505 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10506 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10507 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10508 # if defined (TE_PE) || defined (TE_PEP)
10509 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10511 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10512 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10513 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10514 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10515 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10516 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10517 {NULL, no_argument, NULL, 0}
10519 size_t md_longopts_size = sizeof (md_longopts);
10522 md_parse_option (int c, const char *arg)
10525 char *arch, *next, *saved;
10530 optimize_align_code = 0;
10534 quiet_warnings = 1;
10537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10538 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10539 should be emitted or not. FIXME: Not implemented. */
10543 /* -V: SVR4 argument to print version ID. */
10545 print_version_id ();
10548 /* -k: Ignore for FreeBSD compatibility. */
10553 /* -s: On i386 Solaris, this tells the native assembler to use
10554 .stab instead of .stab.excl. We always use .stab anyhow. */
10557 case OPTION_MSHARED:
10561 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10565 const char **list, **l;
10567 list = bfd_target_list ();
10568 for (l = list; *l != NULL; l++)
10569 if (CONST_STRNEQ (*l, "elf64-x86-64")
10570 || strcmp (*l, "coff-x86-64") == 0
10571 || strcmp (*l, "pe-x86-64") == 0
10572 || strcmp (*l, "pei-x86-64") == 0
10573 || strcmp (*l, "mach-o-x86-64") == 0)
10575 default_arch = "x86_64";
10579 as_fatal (_("no compiled in support for x86_64"));
10585 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10589 const char **list, **l;
10591 list = bfd_target_list ();
10592 for (l = list; *l != NULL; l++)
10593 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10595 default_arch = "x86_64:32";
10599 as_fatal (_("no compiled in support for 32bit x86_64"));
10603 as_fatal (_("32bit x86_64 is only supported for ELF"));
10608 default_arch = "i386";
10611 case OPTION_DIVIDE:
10612 #ifdef SVR4_COMMENT_CHARS
10617 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10619 for (s = i386_comment_chars; *s != '\0'; s++)
10623 i386_comment_chars = n;
10629 saved = xstrdup (arg);
10631 /* Allow -march=+nosse. */
10637 as_fatal (_("invalid -march= option: `%s'"), arg);
10638 next = strchr (arch, '+');
10641 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10643 if (strcmp (arch, cpu_arch [j].name) == 0)
10646 if (! cpu_arch[j].flags.bitfield.cpui386)
10649 cpu_arch_name = cpu_arch[j].name;
10650 cpu_sub_arch_name = NULL;
10651 cpu_arch_flags = cpu_arch[j].flags;
10652 cpu_arch_isa = cpu_arch[j].type;
10653 cpu_arch_isa_flags = cpu_arch[j].flags;
10654 if (!cpu_arch_tune_set)
10656 cpu_arch_tune = cpu_arch_isa;
10657 cpu_arch_tune_flags = cpu_arch_isa_flags;
10661 else if (*cpu_arch [j].name == '.'
10662 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10664 /* ISA extension. */
10665 i386_cpu_flags flags;
10667 flags = cpu_flags_or (cpu_arch_flags,
10668 cpu_arch[j].flags);
10670 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10672 if (cpu_sub_arch_name)
10674 char *name = cpu_sub_arch_name;
10675 cpu_sub_arch_name = concat (name,
10677 (const char *) NULL);
10681 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10682 cpu_arch_flags = flags;
10683 cpu_arch_isa_flags = flags;
10687 = cpu_flags_or (cpu_arch_isa_flags,
10688 cpu_arch[j].flags);
10693 if (j >= ARRAY_SIZE (cpu_arch))
10695 /* Disable an ISA extension. */
10696 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10697 if (strcmp (arch, cpu_noarch [j].name) == 0)
10699 i386_cpu_flags flags;
10701 flags = cpu_flags_and_not (cpu_arch_flags,
10702 cpu_noarch[j].flags);
10703 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10705 if (cpu_sub_arch_name)
10707 char *name = cpu_sub_arch_name;
10708 cpu_sub_arch_name = concat (arch,
10709 (const char *) NULL);
10713 cpu_sub_arch_name = xstrdup (arch);
10714 cpu_arch_flags = flags;
10715 cpu_arch_isa_flags = flags;
10720 if (j >= ARRAY_SIZE (cpu_noarch))
10721 j = ARRAY_SIZE (cpu_arch);
10724 if (j >= ARRAY_SIZE (cpu_arch))
10725 as_fatal (_("invalid -march= option: `%s'"), arg);
10729 while (next != NULL);
10735 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10736 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10738 if (strcmp (arg, cpu_arch [j].name) == 0)
10740 cpu_arch_tune_set = 1;
10741 cpu_arch_tune = cpu_arch [j].type;
10742 cpu_arch_tune_flags = cpu_arch[j].flags;
10746 if (j >= ARRAY_SIZE (cpu_arch))
10747 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10750 case OPTION_MMNEMONIC:
10751 if (strcasecmp (arg, "att") == 0)
10752 intel_mnemonic = 0;
10753 else if (strcasecmp (arg, "intel") == 0)
10754 intel_mnemonic = 1;
10756 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10759 case OPTION_MSYNTAX:
10760 if (strcasecmp (arg, "att") == 0)
10762 else if (strcasecmp (arg, "intel") == 0)
10765 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10768 case OPTION_MINDEX_REG:
10769 allow_index_reg = 1;
10772 case OPTION_MNAKED_REG:
10773 allow_naked_reg = 1;
10776 case OPTION_MSSE2AVX:
10780 case OPTION_MSSE_CHECK:
10781 if (strcasecmp (arg, "error") == 0)
10782 sse_check = check_error;
10783 else if (strcasecmp (arg, "warning") == 0)
10784 sse_check = check_warning;
10785 else if (strcasecmp (arg, "none") == 0)
10786 sse_check = check_none;
10788 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10791 case OPTION_MOPERAND_CHECK:
10792 if (strcasecmp (arg, "error") == 0)
10793 operand_check = check_error;
10794 else if (strcasecmp (arg, "warning") == 0)
10795 operand_check = check_warning;
10796 else if (strcasecmp (arg, "none") == 0)
10797 operand_check = check_none;
10799 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10802 case OPTION_MAVXSCALAR:
10803 if (strcasecmp (arg, "128") == 0)
10804 avxscalar = vex128;
10805 else if (strcasecmp (arg, "256") == 0)
10806 avxscalar = vex256;
10808 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10811 case OPTION_MADD_BND_PREFIX:
10812 add_bnd_prefix = 1;
10815 case OPTION_MEVEXLIG:
10816 if (strcmp (arg, "128") == 0)
10817 evexlig = evexl128;
10818 else if (strcmp (arg, "256") == 0)
10819 evexlig = evexl256;
10820 else if (strcmp (arg, "512") == 0)
10821 evexlig = evexl512;
10823 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10826 case OPTION_MEVEXRCIG:
10827 if (strcmp (arg, "rne") == 0)
10829 else if (strcmp (arg, "rd") == 0)
10831 else if (strcmp (arg, "ru") == 0)
10833 else if (strcmp (arg, "rz") == 0)
10836 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10839 case OPTION_MEVEXWIG:
10840 if (strcmp (arg, "0") == 0)
10842 else if (strcmp (arg, "1") == 0)
10845 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10848 # if defined (TE_PE) || defined (TE_PEP)
10849 case OPTION_MBIG_OBJ:
10854 case OPTION_MOMIT_LOCK_PREFIX:
10855 if (strcasecmp (arg, "yes") == 0)
10856 omit_lock_prefix = 1;
10857 else if (strcasecmp (arg, "no") == 0)
10858 omit_lock_prefix = 0;
10860 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10863 case OPTION_MFENCE_AS_LOCK_ADD:
10864 if (strcasecmp (arg, "yes") == 0)
10866 else if (strcasecmp (arg, "no") == 0)
10869 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10872 case OPTION_MRELAX_RELOCATIONS:
10873 if (strcasecmp (arg, "yes") == 0)
10874 generate_relax_relocations = 1;
10875 else if (strcasecmp (arg, "no") == 0)
10876 generate_relax_relocations = 0;
10878 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10881 case OPTION_MAMD64:
10885 case OPTION_MINTEL64:
10893 /* Turn off -Os. */
10894 optimize_for_space = 0;
10896 else if (*arg == 's')
10898 optimize_for_space = 1;
10899 /* Turn on all encoding optimizations. */
10904 optimize = atoi (arg);
10905 /* Turn off -Os. */
10906 optimize_for_space = 0;
10916 #define MESSAGE_TEMPLATE \
10920 output_message (FILE *stream, char *p, char *message, char *start,
10921 int *left_p, const char *name, int len)
10923 int size = sizeof (MESSAGE_TEMPLATE);
10924 int left = *left_p;
10926 /* Reserve 2 spaces for ", " or ",\0" */
10929 /* Check if there is any room. */
10937 p = mempcpy (p, name, len);
10941 /* Output the current message now and start a new one. */
10944 fprintf (stream, "%s\n", message);
10946 left = size - (start - message) - len - 2;
10948 gas_assert (left >= 0);
10950 p = mempcpy (p, name, len);
10958 show_arch (FILE *stream, int ext, int check)
10960 static char message[] = MESSAGE_TEMPLATE;
10961 char *start = message + 27;
10963 int size = sizeof (MESSAGE_TEMPLATE);
10970 left = size - (start - message);
10971 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10973 /* Should it be skipped? */
10974 if (cpu_arch [j].skip)
10977 name = cpu_arch [j].name;
10978 len = cpu_arch [j].len;
10981 /* It is an extension. Skip if we aren't asked to show it. */
10992 /* It is an processor. Skip if we show only extension. */
10995 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10997 /* It is an impossible processor - skip. */
11001 p = output_message (stream, p, message, start, &left, name, len);
11004 /* Display disabled extensions. */
11006 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11008 name = cpu_noarch [j].name;
11009 len = cpu_noarch [j].len;
11010 p = output_message (stream, p, message, start, &left, name,
11015 fprintf (stream, "%s\n", message);
11019 md_show_usage (FILE *stream)
11021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11022 fprintf (stream, _("\
11024 -V print assembler version number\n\
11027 fprintf (stream, _("\
11028 -n Do not optimize code alignment\n\
11029 -q quieten some warnings\n"));
11030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11031 fprintf (stream, _("\
11034 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11035 || defined (TE_PE) || defined (TE_PEP))
11036 fprintf (stream, _("\
11037 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11039 #ifdef SVR4_COMMENT_CHARS
11040 fprintf (stream, _("\
11041 --divide do not treat `/' as a comment character\n"));
11043 fprintf (stream, _("\
11044 --divide ignored\n"));
11046 fprintf (stream, _("\
11047 -march=CPU[,+EXTENSION...]\n\
11048 generate code for CPU and EXTENSION, CPU is one of:\n"));
11049 show_arch (stream, 0, 1);
11050 fprintf (stream, _("\
11051 EXTENSION is combination of:\n"));
11052 show_arch (stream, 1, 0);
11053 fprintf (stream, _("\
11054 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11055 show_arch (stream, 0, 0);
11056 fprintf (stream, _("\
11057 -msse2avx encode SSE instructions with VEX prefix\n"));
11058 fprintf (stream, _("\
11059 -msse-check=[none|error|warning]\n\
11060 check SSE instructions\n"));
11061 fprintf (stream, _("\
11062 -moperand-check=[none|error|warning]\n\
11063 check operand combinations for validity\n"));
11064 fprintf (stream, _("\
11065 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11067 fprintf (stream, _("\
11068 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11070 fprintf (stream, _("\
11071 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11072 for EVEX.W bit ignored instructions\n"));
11073 fprintf (stream, _("\
11074 -mevexrcig=[rne|rd|ru|rz]\n\
11075 encode EVEX instructions with specific EVEX.RC value\n\
11076 for SAE-only ignored instructions\n"));
11077 fprintf (stream, _("\
11078 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11079 fprintf (stream, _("\
11080 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11081 fprintf (stream, _("\
11082 -mindex-reg support pseudo index registers\n"));
11083 fprintf (stream, _("\
11084 -mnaked-reg don't require `%%' prefix for registers\n"));
11085 fprintf (stream, _("\
11086 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11087 fprintf (stream, _("\
11088 -mshared disable branch optimization for shared code\n"));
11089 # if defined (TE_PE) || defined (TE_PEP)
11090 fprintf (stream, _("\
11091 -mbig-obj generate big object files\n"));
11093 fprintf (stream, _("\
11094 -momit-lock-prefix=[no|yes]\n\
11095 strip all lock prefixes\n"));
11096 fprintf (stream, _("\
11097 -mfence-as-lock-add=[no|yes]\n\
11098 encode lfence, mfence and sfence as\n\
11099 lock addl $0x0, (%%{re}sp)\n"));
11100 fprintf (stream, _("\
11101 -mrelax-relocations=[no|yes]\n\
11102 generate relax relocations\n"));
11103 fprintf (stream, _("\
11104 -mamd64 accept only AMD64 ISA\n"));
11105 fprintf (stream, _("\
11106 -mintel64 accept only Intel64 ISA\n"));
11109 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11110 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11111 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11113 /* Pick the target format to use. */
11116 i386_target_format (void)
11118 if (!strncmp (default_arch, "x86_64", 6))
11120 update_code_flag (CODE_64BIT, 1);
11121 if (default_arch[6] == '\0')
11122 x86_elf_abi = X86_64_ABI;
11124 x86_elf_abi = X86_64_X32_ABI;
11126 else if (!strcmp (default_arch, "i386"))
11127 update_code_flag (CODE_32BIT, 1);
11128 else if (!strcmp (default_arch, "iamcu"))
11130 update_code_flag (CODE_32BIT, 1);
11131 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11133 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11134 cpu_arch_name = "iamcu";
11135 cpu_sub_arch_name = NULL;
11136 cpu_arch_flags = iamcu_flags;
11137 cpu_arch_isa = PROCESSOR_IAMCU;
11138 cpu_arch_isa_flags = iamcu_flags;
11139 if (!cpu_arch_tune_set)
11141 cpu_arch_tune = cpu_arch_isa;
11142 cpu_arch_tune_flags = cpu_arch_isa_flags;
11145 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11146 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11150 as_fatal (_("unknown architecture"));
11152 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11153 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11154 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11155 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11157 switch (OUTPUT_FLAVOR)
11159 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11160 case bfd_target_aout_flavour:
11161 return AOUT_TARGET_FORMAT;
11163 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11164 # if defined (TE_PE) || defined (TE_PEP)
11165 case bfd_target_coff_flavour:
11166 if (flag_code == CODE_64BIT)
11167 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11170 # elif defined (TE_GO32)
11171 case bfd_target_coff_flavour:
11172 return "coff-go32";
11174 case bfd_target_coff_flavour:
11175 return "coff-i386";
11178 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11179 case bfd_target_elf_flavour:
11181 const char *format;
11183 switch (x86_elf_abi)
11186 format = ELF_TARGET_FORMAT;
11189 use_rela_relocations = 1;
11191 format = ELF_TARGET_FORMAT64;
11193 case X86_64_X32_ABI:
11194 use_rela_relocations = 1;
11196 disallow_64bit_reloc = 1;
11197 format = ELF_TARGET_FORMAT32;
11200 if (cpu_arch_isa == PROCESSOR_L1OM)
11202 if (x86_elf_abi != X86_64_ABI)
11203 as_fatal (_("Intel L1OM is 64bit only"));
11204 return ELF_TARGET_L1OM_FORMAT;
11206 else if (cpu_arch_isa == PROCESSOR_K1OM)
11208 if (x86_elf_abi != X86_64_ABI)
11209 as_fatal (_("Intel K1OM is 64bit only"));
11210 return ELF_TARGET_K1OM_FORMAT;
11212 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11214 if (x86_elf_abi != I386_ABI)
11215 as_fatal (_("Intel MCU is 32bit only"));
11216 return ELF_TARGET_IAMCU_FORMAT;
11222 #if defined (OBJ_MACH_O)
11223 case bfd_target_mach_o_flavour:
11224 if (flag_code == CODE_64BIT)
11226 use_rela_relocations = 1;
11228 return "mach-o-x86-64";
11231 return "mach-o-i386";
11239 #endif /* OBJ_MAYBE_ more than one */
11242 md_undefined_symbol (char *name)
11244 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11245 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11246 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11247 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11251 if (symbol_find (name))
11252 as_bad (_("GOT already in symbol table"));
11253 GOT_symbol = symbol_new (name, undefined_section,
11254 (valueT) 0, &zero_address_frag);
11261 /* Round up a section size to the appropriate boundary. */
11264 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11266 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11267 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11269 /* For a.out, force the section size to be aligned. If we don't do
11270 this, BFD will align it for us, but it will not write out the
11271 final bytes of the section. This may be a bug in BFD, but it is
11272 easier to fix it here since that is how the other a.out targets
11276 align = bfd_get_section_alignment (stdoutput, segment);
11277 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11284 /* On the i386, PC-relative offsets are relative to the start of the
11285 next instruction. That is, the address of the offset, plus its
11286 size, since the offset is always the last part of the insn. */
11289 md_pcrel_from (fixS *fixP)
11291 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11297 s_bss (int ignore ATTRIBUTE_UNUSED)
11301 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11303 obj_elf_section_change_hook ();
11305 temp = get_absolute_expression ();
11306 subseg_set (bss_section, (subsegT) temp);
11307 demand_empty_rest_of_line ();
11313 i386_validate_fix (fixS *fixp)
11315 if (fixp->fx_subsy)
11317 if (fixp->fx_subsy == GOT_symbol)
11319 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11323 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11324 if (fixp->fx_tcbit2)
11325 fixp->fx_r_type = (fixp->fx_tcbit
11326 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11327 : BFD_RELOC_X86_64_GOTPCRELX);
11330 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11335 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11337 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11339 fixp->fx_subsy = 0;
11342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11343 else if (!object_64bit)
11345 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11346 && fixp->fx_tcbit2)
11347 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11353 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11356 bfd_reloc_code_real_type code;
11358 switch (fixp->fx_r_type)
11360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11361 case BFD_RELOC_SIZE32:
11362 case BFD_RELOC_SIZE64:
11363 if (S_IS_DEFINED (fixp->fx_addsy)
11364 && !S_IS_EXTERNAL (fixp->fx_addsy))
11366 /* Resolve size relocation against local symbol to size of
11367 the symbol plus addend. */
11368 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11369 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11370 && !fits_in_unsigned_long (value))
11371 as_bad_where (fixp->fx_file, fixp->fx_line,
11372 _("symbol size computation overflow"));
11373 fixp->fx_addsy = NULL;
11374 fixp->fx_subsy = NULL;
11375 md_apply_fix (fixp, (valueT *) &value, NULL);
11379 /* Fall through. */
11381 case BFD_RELOC_X86_64_PLT32:
11382 case BFD_RELOC_X86_64_GOT32:
11383 case BFD_RELOC_X86_64_GOTPCREL:
11384 case BFD_RELOC_X86_64_GOTPCRELX:
11385 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11386 case BFD_RELOC_386_PLT32:
11387 case BFD_RELOC_386_GOT32:
11388 case BFD_RELOC_386_GOT32X:
11389 case BFD_RELOC_386_GOTOFF:
11390 case BFD_RELOC_386_GOTPC:
11391 case BFD_RELOC_386_TLS_GD:
11392 case BFD_RELOC_386_TLS_LDM:
11393 case BFD_RELOC_386_TLS_LDO_32:
11394 case BFD_RELOC_386_TLS_IE_32:
11395 case BFD_RELOC_386_TLS_IE:
11396 case BFD_RELOC_386_TLS_GOTIE:
11397 case BFD_RELOC_386_TLS_LE_32:
11398 case BFD_RELOC_386_TLS_LE:
11399 case BFD_RELOC_386_TLS_GOTDESC:
11400 case BFD_RELOC_386_TLS_DESC_CALL:
11401 case BFD_RELOC_X86_64_TLSGD:
11402 case BFD_RELOC_X86_64_TLSLD:
11403 case BFD_RELOC_X86_64_DTPOFF32:
11404 case BFD_RELOC_X86_64_DTPOFF64:
11405 case BFD_RELOC_X86_64_GOTTPOFF:
11406 case BFD_RELOC_X86_64_TPOFF32:
11407 case BFD_RELOC_X86_64_TPOFF64:
11408 case BFD_RELOC_X86_64_GOTOFF64:
11409 case BFD_RELOC_X86_64_GOTPC32:
11410 case BFD_RELOC_X86_64_GOT64:
11411 case BFD_RELOC_X86_64_GOTPCREL64:
11412 case BFD_RELOC_X86_64_GOTPC64:
11413 case BFD_RELOC_X86_64_GOTPLT64:
11414 case BFD_RELOC_X86_64_PLTOFF64:
11415 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11416 case BFD_RELOC_X86_64_TLSDESC_CALL:
11417 case BFD_RELOC_RVA:
11418 case BFD_RELOC_VTABLE_ENTRY:
11419 case BFD_RELOC_VTABLE_INHERIT:
11421 case BFD_RELOC_32_SECREL:
11423 code = fixp->fx_r_type;
11425 case BFD_RELOC_X86_64_32S:
11426 if (!fixp->fx_pcrel)
11428 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11429 code = fixp->fx_r_type;
11432 /* Fall through. */
11434 if (fixp->fx_pcrel)
11436 switch (fixp->fx_size)
11439 as_bad_where (fixp->fx_file, fixp->fx_line,
11440 _("can not do %d byte pc-relative relocation"),
11442 code = BFD_RELOC_32_PCREL;
11444 case 1: code = BFD_RELOC_8_PCREL; break;
11445 case 2: code = BFD_RELOC_16_PCREL; break;
11446 case 4: code = BFD_RELOC_32_PCREL; break;
11448 case 8: code = BFD_RELOC_64_PCREL; break;
11454 switch (fixp->fx_size)
11457 as_bad_where (fixp->fx_file, fixp->fx_line,
11458 _("can not do %d byte relocation"),
11460 code = BFD_RELOC_32;
11462 case 1: code = BFD_RELOC_8; break;
11463 case 2: code = BFD_RELOC_16; break;
11464 case 4: code = BFD_RELOC_32; break;
11466 case 8: code = BFD_RELOC_64; break;
11473 if ((code == BFD_RELOC_32
11474 || code == BFD_RELOC_32_PCREL
11475 || code == BFD_RELOC_X86_64_32S)
11477 && fixp->fx_addsy == GOT_symbol)
11480 code = BFD_RELOC_386_GOTPC;
11482 code = BFD_RELOC_X86_64_GOTPC32;
11484 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11486 && fixp->fx_addsy == GOT_symbol)
11488 code = BFD_RELOC_X86_64_GOTPC64;
11491 rel = XNEW (arelent);
11492 rel->sym_ptr_ptr = XNEW (asymbol *);
11493 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11495 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11497 if (!use_rela_relocations)
11499 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11500 vtable entry to be used in the relocation's section offset. */
11501 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11502 rel->address = fixp->fx_offset;
11503 #if defined (OBJ_COFF) && defined (TE_PE)
11504 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11505 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11510 /* Use the rela in 64bit mode. */
11513 if (disallow_64bit_reloc)
11516 case BFD_RELOC_X86_64_DTPOFF64:
11517 case BFD_RELOC_X86_64_TPOFF64:
11518 case BFD_RELOC_64_PCREL:
11519 case BFD_RELOC_X86_64_GOTOFF64:
11520 case BFD_RELOC_X86_64_GOT64:
11521 case BFD_RELOC_X86_64_GOTPCREL64:
11522 case BFD_RELOC_X86_64_GOTPC64:
11523 case BFD_RELOC_X86_64_GOTPLT64:
11524 case BFD_RELOC_X86_64_PLTOFF64:
11525 as_bad_where (fixp->fx_file, fixp->fx_line,
11526 _("cannot represent relocation type %s in x32 mode"),
11527 bfd_get_reloc_code_name (code));
11533 if (!fixp->fx_pcrel)
11534 rel->addend = fixp->fx_offset;
11538 case BFD_RELOC_X86_64_PLT32:
11539 case BFD_RELOC_X86_64_GOT32:
11540 case BFD_RELOC_X86_64_GOTPCREL:
11541 case BFD_RELOC_X86_64_GOTPCRELX:
11542 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11543 case BFD_RELOC_X86_64_TLSGD:
11544 case BFD_RELOC_X86_64_TLSLD:
11545 case BFD_RELOC_X86_64_GOTTPOFF:
11546 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11547 case BFD_RELOC_X86_64_TLSDESC_CALL:
11548 rel->addend = fixp->fx_offset - fixp->fx_size;
11551 rel->addend = (section->vma
11553 + fixp->fx_addnumber
11554 + md_pcrel_from (fixp));
11559 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11560 if (rel->howto == NULL)
11562 as_bad_where (fixp->fx_file, fixp->fx_line,
11563 _("cannot represent relocation type %s"),
11564 bfd_get_reloc_code_name (code));
11565 /* Set howto to a garbage value so that we can keep going. */
11566 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11567 gas_assert (rel->howto != NULL);
11573 #include "tc-i386-intel.c"
11576 tc_x86_parse_to_dw2regnum (expressionS *exp)
11578 int saved_naked_reg;
11579 char saved_register_dot;
11581 saved_naked_reg = allow_naked_reg;
11582 allow_naked_reg = 1;
11583 saved_register_dot = register_chars['.'];
11584 register_chars['.'] = '.';
11585 allow_pseudo_reg = 1;
11586 expression_and_evaluate (exp);
11587 allow_pseudo_reg = 0;
11588 register_chars['.'] = saved_register_dot;
11589 allow_naked_reg = saved_naked_reg;
11591 if (exp->X_op == O_register && exp->X_add_number >= 0)
11593 if ((addressT) exp->X_add_number < i386_regtab_size)
11595 exp->X_op = O_constant;
11596 exp->X_add_number = i386_regtab[exp->X_add_number]
11597 .dw2_regnum[flag_code >> 1];
11600 exp->X_op = O_illegal;
11605 tc_x86_frame_initial_instructions (void)
11607 static unsigned int sp_regno[2];
11609 if (!sp_regno[flag_code >> 1])
11611 char *saved_input = input_line_pointer;
11612 char sp[][4] = {"esp", "rsp"};
11615 input_line_pointer = sp[flag_code >> 1];
11616 tc_x86_parse_to_dw2regnum (&exp);
11617 gas_assert (exp.X_op == O_constant);
11618 sp_regno[flag_code >> 1] = exp.X_add_number;
11619 input_line_pointer = saved_input;
11622 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11623 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11627 x86_dwarf2_addr_size (void)
11629 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11630 if (x86_elf_abi == X86_64_X32_ABI)
11633 return bfd_arch_bits_per_address (stdoutput) / 8;
11637 i386_elf_section_type (const char *str, size_t len)
11639 if (flag_code == CODE_64BIT
11640 && len == sizeof ("unwind") - 1
11641 && strncmp (str, "unwind", 6) == 0)
11642 return SHT_X86_64_UNWIND;
11649 i386_solaris_fix_up_eh_frame (segT sec)
11651 if (flag_code == CODE_64BIT)
11652 elf_section_type (sec) = SHT_X86_64_UNWIND;
11658 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11662 exp.X_op = O_secrel;
11663 exp.X_add_symbol = symbol;
11664 exp.X_add_number = 0;
11665 emit_expr (&exp, size);
11669 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11670 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11673 x86_64_section_letter (int letter, const char **ptr_msg)
11675 if (flag_code == CODE_64BIT)
11678 return SHF_X86_64_LARGE;
11680 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11683 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11688 x86_64_section_word (char *str, size_t len)
11690 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11691 return SHF_X86_64_LARGE;
11697 handle_large_common (int small ATTRIBUTE_UNUSED)
11699 if (flag_code != CODE_64BIT)
11701 s_comm_internal (0, elf_common_parse);
11702 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11706 static segT lbss_section;
11707 asection *saved_com_section_ptr = elf_com_section_ptr;
11708 asection *saved_bss_section = bss_section;
11710 if (lbss_section == NULL)
11712 flagword applicable;
11713 segT seg = now_seg;
11714 subsegT subseg = now_subseg;
11716 /* The .lbss section is for local .largecomm symbols. */
11717 lbss_section = subseg_new (".lbss", 0);
11718 applicable = bfd_applicable_section_flags (stdoutput);
11719 bfd_set_section_flags (stdoutput, lbss_section,
11720 applicable & SEC_ALLOC);
11721 seg_info (lbss_section)->bss = 1;
11723 subseg_set (seg, subseg);
11726 elf_com_section_ptr = &_bfd_elf_large_com_section;
11727 bss_section = lbss_section;
11729 s_comm_internal (0, elf_common_parse);
11731 elf_com_section_ptr = saved_com_section_ptr;
11732 bss_section = saved_bss_section;
11735 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */