1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
196 static const char *default_arch = DEFAULT_ARCH;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
269 unsupported_with_intel_mnemonic,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
279 mask_not_on_destination,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op[MAX_OPERANDS];
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default = 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default = 0,
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
378 /* How to encode vector instructions. */
381 vex_encoding_default = 0,
388 const char *rep_prefix;
391 const char *hle_prefix;
393 /* Have BND prefix. */
394 const char *bnd_prefix;
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
400 enum i386_error error;
403 typedef struct _i386_insn i386_insn;
405 /* Link RC type with corresponding string, that'll be looked for in
414 static const struct RC_name RC_NamesTable[] =
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
465 const char line_separator_chars[] = ";";
467 /* Chars that can be used to separate mant from exp in floating point
469 const char EXP_CHARS[] = "eE";
471 /* Chars that mean this number is a floating point constant
474 const char FLT_CHARS[] = "fFdDxX";
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
505 /* The instruction we're assembling. */
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
515 /* Current operand we are working on. */
516 static int this_operand = -1;
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
535 /* The ELF ABI to use. */
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
556 /* 1 for intel syntax,
558 static int intel_syntax = 0;
560 /* 1 for Intel64 ISA,
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
580 static int add_bnd_prefix = 0;
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
593 /* 1 if the assembler should generate relax relocations. */
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
598 static enum check_kind
604 sse_check, operand_check = check_warning;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
611 static int optimize = 0;
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
620 static int optimize_for_space = 0;
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
665 /* Encode scalar AVX instructions with specific vector length. */
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
680 /* Encode EVEX WIG instructions with specific evex.w. */
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
705 #define UNCOND_JUMP 0
707 #define COND_JUMP86 2
712 #define SMALL16 (SMALL | CODE16)
714 #define BIG16 (BIG | CODE16)
718 #define INLINE __inline__
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
739 const relax_typeS md_relax_table[] =
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
778 static const arch_entry cpu_arch[] =
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1038 static const noarch_entry cpu_noarch[] =
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1085 && *input_line_pointer == ',')
1087 align = parse_align (needs_align - 1);
1089 if (align == (addressT) -1)
1104 bss_alloc (symbolP, size, align);
1109 pe_lcomm (int needs_align)
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1115 const pseudo_typeS md_pseudo_table[] =
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1120 {"align", s_align_ptwo, 0},
1122 {"arch", set_cpu_arch, 0},
1126 {"lcomm", pe_lcomm, 1},
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1139 {"code64", set_code_flag, CODE_64BIT},
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1157 {"secrel32", pe_directive_secrel, 0},
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1234 alt_9, alt_10, alt_11
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1241 i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1245 /* Place the longer NOP first. */
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1250 /* Use the smaller one if the requsted one isn't available. */
1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
1257 last = count % max_single_nop_size;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1265 nops = patt[last - 1];
1268 /* Use the smaller one plus one-byte NOP if the needed one
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1276 memcpy (where + offset, nops, last);
1281 fits_in_imm7 (offsetT num)
1283 return (num & 0x7f) == num;
1287 fits_in_imm31 (offsetT num)
1289 return (num & 0x7fffffff) == num;
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1296 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1298 const unsigned char *const *patt = NULL;
1299 int max_single_nop_size;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
1303 switch (fragP->fr_type)
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1326 if (flag_code == CODE_16BIT)
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
1350 case PROCESSOR_CORE:
1351 case PROCESSOR_CORE2:
1352 case PROCESSOR_COREI7:
1353 case PROCESSOR_L1OM:
1354 case PROCESSOR_K1OM:
1355 case PROCESSOR_GENERIC64:
1357 case PROCESSOR_ATHLON:
1359 case PROCESSOR_AMDFAM10:
1361 case PROCESSOR_ZNVER:
1365 case PROCESSOR_I386:
1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
1368 case PROCESSOR_PENTIUMPRO:
1369 case PROCESSOR_IAMCU:
1370 case PROCESSOR_GENERIC32:
1377 switch (fragP->tc_frag_data.tune)
1379 case PROCESSOR_UNKNOWN:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1385 case PROCESSOR_I386:
1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
1388 case PROCESSOR_IAMCU:
1390 case PROCESSOR_ATHLON:
1392 case PROCESSOR_AMDFAM10:
1394 case PROCESSOR_ZNVER:
1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
1408 case PROCESSOR_CORE2:
1409 case PROCESSOR_COREI7:
1410 case PROCESSOR_L1OM:
1411 case PROCESSOR_K1OM:
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1417 case PROCESSOR_GENERIC64:
1423 if (patt == f32_patt)
1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1438 limit = max_single_nop_size;
1440 if (fragP->fr_type == rs_fill_nop)
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1453 fragP->fr_var = count;
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1461 /* Use "jmp disp8" if possible. */
1463 where[0] = jump_disp8[0];
1469 unsigned int size_of_jump;
1471 if (flag_code == CODE_16BIT)
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1479 where[0] = jump32_disp32[0];
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
1501 operand_type_all_zero (const union i386_operand_type *x)
1503 switch (ARRAY_SIZE(x->array))
1514 return !x->array[0];
1521 operand_type_set (union i386_operand_type *x, unsigned int v)
1523 switch (ARRAY_SIZE(x->array))
1541 operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
1544 switch (ARRAY_SIZE(x->array))
1547 if (x->array[2] != y->array[2])
1551 if (x->array[1] != y->array[1])
1555 return x->array[0] == y->array[0];
1563 cpu_flags_all_zero (const union i386_cpu_flags *x)
1565 switch (ARRAY_SIZE(x->array))
1580 return !x->array[0];
1587 cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1590 switch (ARRAY_SIZE(x->array))
1593 if (x->array[3] != y->array[3])
1597 if (x->array[2] != y->array[2])
1601 if (x->array[1] != y->array[1])
1605 return x->array[0] == y->array[0];
1613 cpu_flags_check_cpu64 (i386_cpu_flags f)
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1622 switch (ARRAY_SIZE (x.array))
1625 x.array [3] &= y.array [3];
1628 x.array [2] &= y.array [2];
1631 x.array [1] &= y.array [1];
1634 x.array [0] &= y.array [0];
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1645 switch (ARRAY_SIZE (x.array))
1648 x.array [3] |= y.array [3];
1651 x.array [2] |= y.array [2];
1654 x.array [1] |= y.array [1];
1657 x.array [0] |= y.array [0];
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1668 switch (ARRAY_SIZE (x.array))
1671 x.array [3] &= ~y.array [3];
1674 x.array [2] &= ~y.array [2];
1677 x.array [1] &= ~y.array [1];
1680 x.array [0] &= ~y.array [0];
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1691 #define CPU_FLAGS_PERFECT_MATCH \
1692 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1694 /* Return CPU flags match bits. */
1697 cpu_flags_match (const insn_template *t)
1699 i386_cpu_flags x = t->cpu_flags;
1700 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1702 x.bitfield.cpu64 = 0;
1703 x.bitfield.cpuno64 = 0;
1705 if (cpu_flags_all_zero (&x))
1707 /* This instruction is available on all archs. */
1708 match |= CPU_FLAGS_ARCH_MATCH;
1712 /* This instruction is available only on some archs. */
1713 i386_cpu_flags cpu = cpu_arch_flags;
1715 cpu = cpu_flags_and (x, cpu);
1716 if (!cpu_flags_all_zero (&cpu))
1718 if (x.bitfield.cpuavx)
1720 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1721 if (cpu.bitfield.cpuavx
1722 && (!t->opcode_modifier.sse2avx || sse2avx)
1723 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1724 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1725 match |= CPU_FLAGS_ARCH_MATCH;
1727 else if (x.bitfield.cpuavx512vl)
1729 /* Match AVX512VL. */
1730 if (cpu.bitfield.cpuavx512vl)
1732 /* Need another match. */
1733 cpu.bitfield.cpuavx512vl = 0;
1734 if (!cpu_flags_all_zero (&cpu))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1739 match |= CPU_FLAGS_ARCH_MATCH;
1745 static INLINE i386_operand_type
1746 operand_type_and (i386_operand_type x, i386_operand_type y)
1748 switch (ARRAY_SIZE (x.array))
1751 x.array [2] &= y.array [2];
1754 x.array [1] &= y.array [1];
1757 x.array [0] &= y.array [0];
1765 static INLINE i386_operand_type
1766 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1768 switch (ARRAY_SIZE (x.array))
1771 x.array [2] &= ~y.array [2];
1774 x.array [1] &= ~y.array [1];
1777 x.array [0] &= ~y.array [0];
1785 static INLINE i386_operand_type
1786 operand_type_or (i386_operand_type x, i386_operand_type y)
1788 switch (ARRAY_SIZE (x.array))
1791 x.array [2] |= y.array [2];
1794 x.array [1] |= y.array [1];
1797 x.array [0] |= y.array [0];
1805 static INLINE i386_operand_type
1806 operand_type_xor (i386_operand_type x, i386_operand_type y)
1808 switch (ARRAY_SIZE (x.array))
1811 x.array [2] ^= y.array [2];
1814 x.array [1] ^= y.array [1];
1817 x.array [0] ^= y.array [0];
1825 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1826 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1827 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1828 static const i386_operand_type inoutportreg
1829 = OPERAND_TYPE_INOUTPORTREG;
1830 static const i386_operand_type reg16_inoutportreg
1831 = OPERAND_TYPE_REG16_INOUTPORTREG;
1832 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1833 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1834 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1835 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1836 static const i386_operand_type anydisp
1837 = OPERAND_TYPE_ANYDISP;
1838 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1839 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1840 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1841 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1842 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1843 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1844 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1845 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1846 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1847 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1848 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1849 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1860 operand_type_check (i386_operand_type t, enum operand_type c)
1865 return t.bitfield.reg;
1868 return (t.bitfield.imm8
1872 || t.bitfield.imm32s
1873 || t.bitfield.imm64);
1876 return (t.bitfield.disp8
1877 || t.bitfield.disp16
1878 || t.bitfield.disp32
1879 || t.bitfield.disp32s
1880 || t.bitfield.disp64);
1883 return (t.bitfield.disp8
1884 || t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s
1887 || t.bitfield.disp64
1888 || t.bitfield.baseindex);
1897 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1898 operand J for instruction template T. */
1901 match_reg_size (const insn_template *t, unsigned int j)
1903 return !((i.types[j].bitfield.byte
1904 && !t->operand_types[j].bitfield.byte)
1905 || (i.types[j].bitfield.word
1906 && !t->operand_types[j].bitfield.word)
1907 || (i.types[j].bitfield.dword
1908 && !t->operand_types[j].bitfield.dword)
1909 || (i.types[j].bitfield.qword
1910 && !t->operand_types[j].bitfield.qword)
1911 || (i.types[j].bitfield.tbyte
1912 && !t->operand_types[j].bitfield.tbyte));
1915 /* Return 1 if there is no conflict in SIMD register on
1916 operand J for instruction template T. */
1919 match_simd_size (const insn_template *t, unsigned int j)
1921 return !((i.types[j].bitfield.xmmword
1922 && !t->operand_types[j].bitfield.xmmword)
1923 || (i.types[j].bitfield.ymmword
1924 && !t->operand_types[j].bitfield.ymmword)
1925 || (i.types[j].bitfield.zmmword
1926 && !t->operand_types[j].bitfield.zmmword));
1929 /* Return 1 if there is no conflict in any size on operand J for
1930 instruction template T. */
1933 match_mem_size (const insn_template *t, unsigned int j)
1935 return (match_reg_size (t, j)
1936 && !((i.types[j].bitfield.unspecified
1938 && !t->operand_types[j].bitfield.unspecified)
1939 || (i.types[j].bitfield.fword
1940 && !t->operand_types[j].bitfield.fword)
1941 /* For scalar opcode templates to allow register and memory
1942 operands at the same time, some special casing is needed
1944 || ((t->operand_types[j].bitfield.regsimd
1945 && !t->opcode_modifier.broadcast
1946 && (t->operand_types[j].bitfield.dword
1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
1954 /* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1958 operand_size_match (const insn_template *t)
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
1977 if (t->operand_types[j].bitfield.reg
1978 && !match_reg_size (t, j))
1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2007 else if (!t->opcode_modifier.d)
2010 i.error = operand_size_mismatch;
2014 /* Check reverse. */
2015 gas_assert (i.operands == 2);
2018 for (j = 0; j < 2; j++)
2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
2022 && !match_reg_size (t, j ? 0 : 1))
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
2034 operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2037 i386_operand_type temp = overlap;
2039 temp.bitfield.jumpabsolute = 0;
2040 temp.bitfield.unspecified = 0;
2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
2048 temp.bitfield.ymmword = 0;
2049 temp.bitfield.zmmword = 0;
2050 if (operand_type_all_zero (&temp))
2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2058 i.error = operand_type_mismatch;
2062 /* If given types g0 and g1 are registers they must be of the same type
2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2068 operand_type_register_match (i386_operand_type g0,
2069 i386_operand_type t0,
2070 i386_operand_type g1,
2071 i386_operand_type t1)
2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2105 i.error = register_type_mismatch;
2110 static INLINE unsigned int
2111 register_number (const reg_entry *r)
2113 unsigned int nr = r->reg_num;
2115 if (r->reg_flags & RegRex)
2118 if (r->reg_flags & RegVRex)
2124 static INLINE unsigned int
2125 mode_from_disp_size (i386_operand_type t)
2127 if (t.bitfield.disp8)
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2138 fits_in_signed_byte (addressT num)
2140 return num + 0x80 <= 0xff;
2144 fits_in_unsigned_byte (addressT num)
2150 fits_in_unsigned_word (addressT num)
2152 return num <= 0xffff;
2156 fits_in_signed_word (addressT num)
2158 return num + 0x8000 <= 0xffff;
2162 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2167 return num + 0x80000000 <= 0xffffffff;
2169 } /* fits_in_signed_long() */
2172 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2177 return num <= 0xffffffff;
2179 } /* fits_in_unsigned_long() */
2182 fits_in_disp8 (offsetT num)
2184 int shift = i.memshift;
2190 mask = (1 << shift) - 1;
2192 /* Return 0 if NUM isn't properly aligned. */
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2201 fits_in_imm4 (offsetT num)
2203 return (num & 0xf) == num;
2206 static i386_operand_type
2207 smallest_imm_type (offsetT num)
2209 i386_operand_type t;
2211 operand_type_set (&t, 0);
2212 t.bitfield.imm64 = 1;
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2228 else if (fits_in_signed_byte (num))
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2236 else if (fits_in_unsigned_byte (num))
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2249 else if (fits_in_signed_long (num))
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2261 offset_in_range (offsetT val, int size)
2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2286 char buf1[40], buf2[40];
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
2313 static enum PREFIX_GROUP
2314 add_prefix (unsigned int prefix)
2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
2335 case DS_PREFIX_OPCODE:
2338 case CS_PREFIX_OPCODE:
2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
2352 case LOCK_PREFIX_OPCODE:
2361 case ADDR_PREFIX_OPCODE:
2365 case DATA_PREFIX_OPCODE:
2369 if (i.prefix[q] != 0)
2377 i.prefix[q] |= prefix;
2380 as_bad (_("same type of prefix used twice"));
2386 update_code_flag (int value, int check)
2388 PRINTF_LIKE ((*as_error));
2390 flag_code = (enum flag_code) value;
2391 if (flag_code == CODE_64BIT)
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2404 as_error = as_fatal;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2413 as_error = as_fatal;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 stackop_size = '\0';
2423 set_code_flag (int value)
2425 update_code_flag (value, 0);
2429 set_16bit_gcc_code_flag (int new_code_flag)
2431 flag_code = (enum flag_code) new_code_flag;
2432 if (flag_code != CODE_16BIT)
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
2436 stackop_size = LONG_MNEM_SUFFIX;
2440 set_intel_syntax (int syntax_flag)
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2449 int e = get_symbol_name (&string);
2451 if (strcmp (string, "prefix") == 0)
2453 else if (strcmp (string, "noprefix") == 0)
2456 as_bad (_("bad argument to syntax directive."));
2457 (void) restore_line_pointer (e);
2459 demand_empty_rest_of_line ();
2461 intel_syntax = syntax_flag;
2463 if (ask_naked_reg == 0)
2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2467 allow_naked_reg = (ask_naked_reg < 0);
2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
2473 register_prefix = allow_naked_reg ? "" : "%";
2477 set_intel_mnemonic (int mnemonic_flag)
2479 intel_mnemonic = mnemonic_flag;
2483 set_allow_index_reg (int flag)
2485 allow_index_reg = flag;
2489 set_check (int what)
2491 enum check_kind *kind;
2496 kind = &operand_check;
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2510 int e = get_symbol_name (&string);
2512 if (strcmp (string, "none") == 0)
2514 else if (strcmp (string, "warning") == 0)
2515 *kind = check_warning;
2516 else if (strcmp (string, "error") == 0)
2517 *kind = check_error;
2519 as_bad (_("bad argument to %s_check directive."), str);
2520 (void) restore_line_pointer (e);
2523 as_bad (_("missing argument for %s_check directive"), str);
2525 demand_empty_rest_of_line ();
2529 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2535 /* Intel LIOM is only supported on ELF. */
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2545 arch = default_arch;
2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2553 /* If we are targeting Intel L1OM, we must enable it. */
2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2555 || new_flag.bitfield.cpul1om)
2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2568 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2575 int e = get_symbol_name (&string);
2577 i386_cpu_flags flags;
2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2581 if (strcmp (string, cpu_arch[j].name) == 0)
2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2587 cpu_arch_name = cpu_arch[j].name;
2588 cpu_sub_arch_name = NULL;
2589 cpu_arch_flags = cpu_arch[j].flags;
2590 if (flag_code == CODE_64BIT)
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
2602 if (!cpu_arch_tune_set)
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2610 flags = cpu_flags_or (cpu_arch_flags,
2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2615 if (cpu_sub_arch_name)
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
2620 (const char *) NULL);
2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2625 cpu_arch_flags = flags;
2626 cpu_arch_isa_flags = flags;
2628 (void) restore_line_pointer (e);
2629 demand_empty_rest_of_line ();
2634 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2636 /* Disable an ISA extension. */
2637 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2638 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2640 flags = cpu_flags_and_not (cpu_arch_flags,
2641 cpu_noarch[j].flags);
2642 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2644 if (cpu_sub_arch_name)
2646 char *name = cpu_sub_arch_name;
2647 cpu_sub_arch_name = concat (name, string,
2648 (const char *) NULL);
2652 cpu_sub_arch_name = xstrdup (string);
2653 cpu_arch_flags = flags;
2654 cpu_arch_isa_flags = flags;
2656 (void) restore_line_pointer (e);
2657 demand_empty_rest_of_line ();
2661 j = ARRAY_SIZE (cpu_arch);
2664 if (j >= ARRAY_SIZE (cpu_arch))
2665 as_bad (_("no such architecture: `%s'"), string);
2667 *input_line_pointer = e;
2670 as_bad (_("missing cpu architecture"));
2672 no_cond_jump_promotion = 0;
2673 if (*input_line_pointer == ','
2674 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2679 ++input_line_pointer;
2680 e = get_symbol_name (&string);
2682 if (strcmp (string, "nojumps") == 0)
2683 no_cond_jump_promotion = 1;
2684 else if (strcmp (string, "jumps") == 0)
2687 as_bad (_("no such architecture modifier: `%s'"), string);
2689 (void) restore_line_pointer (e);
2692 demand_empty_rest_of_line ();
2695 enum bfd_architecture
2698 if (cpu_arch_isa == PROCESSOR_L1OM)
2700 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2701 || flag_code != CODE_64BIT)
2702 as_fatal (_("Intel L1OM is 64bit ELF only"));
2703 return bfd_arch_l1om;
2705 else if (cpu_arch_isa == PROCESSOR_K1OM)
2707 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2708 || flag_code != CODE_64BIT)
2709 as_fatal (_("Intel K1OM is 64bit ELF only"));
2710 return bfd_arch_k1om;
2712 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2715 || flag_code == CODE_64BIT)
2716 as_fatal (_("Intel MCU is 32bit ELF only"));
2717 return bfd_arch_iamcu;
2720 return bfd_arch_i386;
2726 if (!strncmp (default_arch, "x86_64", 6))
2728 if (cpu_arch_isa == PROCESSOR_L1OM)
2730 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2731 || default_arch[6] != '\0')
2732 as_fatal (_("Intel L1OM is 64bit ELF only"));
2733 return bfd_mach_l1om;
2735 else if (cpu_arch_isa == PROCESSOR_K1OM)
2737 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2738 || default_arch[6] != '\0')
2739 as_fatal (_("Intel K1OM is 64bit ELF only"));
2740 return bfd_mach_k1om;
2742 else if (default_arch[6] == '\0')
2743 return bfd_mach_x86_64;
2745 return bfd_mach_x64_32;
2747 else if (!strcmp (default_arch, "i386")
2748 || !strcmp (default_arch, "iamcu"))
2750 if (cpu_arch_isa == PROCESSOR_IAMCU)
2752 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2753 as_fatal (_("Intel MCU is 32bit ELF only"));
2754 return bfd_mach_i386_iamcu;
2757 return bfd_mach_i386_i386;
2760 as_fatal (_("unknown architecture"));
2766 const char *hash_err;
2768 /* Support pseudo prefixes like {disp32}. */
2769 lex_type ['{'] = LEX_BEGIN_NAME;
2771 /* Initialize op_hash hash table. */
2772 op_hash = hash_new ();
2775 const insn_template *optab;
2776 templates *core_optab;
2778 /* Setup for loop. */
2780 core_optab = XNEW (templates);
2781 core_optab->start = optab;
2786 if (optab->name == NULL
2787 || strcmp (optab->name, (optab - 1)->name) != 0)
2789 /* different name --> ship out current template list;
2790 add to hash table; & begin anew. */
2791 core_optab->end = optab;
2792 hash_err = hash_insert (op_hash,
2794 (void *) core_optab);
2797 as_fatal (_("can't hash %s: %s"),
2801 if (optab->name == NULL)
2803 core_optab = XNEW (templates);
2804 core_optab->start = optab;
2809 /* Initialize reg_hash hash table. */
2810 reg_hash = hash_new ();
2812 const reg_entry *regtab;
2813 unsigned int regtab_size = i386_regtab_size;
2815 for (regtab = i386_regtab; regtab_size--; regtab++)
2817 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2819 as_fatal (_("can't hash %s: %s"),
2825 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2830 for (c = 0; c < 256; c++)
2835 mnemonic_chars[c] = c;
2836 register_chars[c] = c;
2837 operand_chars[c] = c;
2839 else if (ISLOWER (c))
2841 mnemonic_chars[c] = c;
2842 register_chars[c] = c;
2843 operand_chars[c] = c;
2845 else if (ISUPPER (c))
2847 mnemonic_chars[c] = TOLOWER (c);
2848 register_chars[c] = mnemonic_chars[c];
2849 operand_chars[c] = c;
2851 else if (c == '{' || c == '}')
2853 mnemonic_chars[c] = c;
2854 operand_chars[c] = c;
2857 if (ISALPHA (c) || ISDIGIT (c))
2858 identifier_chars[c] = c;
2861 identifier_chars[c] = c;
2862 operand_chars[c] = c;
2867 identifier_chars['@'] = '@';
2870 identifier_chars['?'] = '?';
2871 operand_chars['?'] = '?';
2873 digit_chars['-'] = '-';
2874 mnemonic_chars['_'] = '_';
2875 mnemonic_chars['-'] = '-';
2876 mnemonic_chars['.'] = '.';
2877 identifier_chars['_'] = '_';
2878 identifier_chars['.'] = '.';
2880 for (p = operand_special_chars; *p != '\0'; p++)
2881 operand_chars[(unsigned char) *p] = *p;
2884 if (flag_code == CODE_64BIT)
2886 #if defined (OBJ_COFF) && defined (TE_PE)
2887 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2890 x86_dwarf2_return_column = 16;
2892 x86_cie_data_alignment = -8;
2896 x86_dwarf2_return_column = 8;
2897 x86_cie_data_alignment = -4;
2902 i386_print_statistics (FILE *file)
2904 hash_print_statistics (file, "i386 opcode", op_hash);
2905 hash_print_statistics (file, "i386 register", reg_hash);
2910 /* Debugging routines for md_assemble. */
2911 static void pte (insn_template *);
2912 static void pt (i386_operand_type);
2913 static void pe (expressionS *);
2914 static void ps (symbolS *);
2917 pi (char *line, i386_insn *x)
2921 fprintf (stdout, "%s: template ", line);
2923 fprintf (stdout, " address: base %s index %s scale %x\n",
2924 x->base_reg ? x->base_reg->reg_name : "none",
2925 x->index_reg ? x->index_reg->reg_name : "none",
2926 x->log2_scale_factor);
2927 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2928 x->rm.mode, x->rm.reg, x->rm.regmem);
2929 fprintf (stdout, " sib: base %x index %x scale %x\n",
2930 x->sib.base, x->sib.index, x->sib.scale);
2931 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2932 (x->rex & REX_W) != 0,
2933 (x->rex & REX_R) != 0,
2934 (x->rex & REX_X) != 0,
2935 (x->rex & REX_B) != 0);
2936 for (j = 0; j < x->operands; j++)
2938 fprintf (stdout, " #%d: ", j + 1);
2940 fprintf (stdout, "\n");
2941 if (x->types[j].bitfield.reg
2942 || x->types[j].bitfield.regmmx
2943 || x->types[j].bitfield.regsimd
2944 || x->types[j].bitfield.sreg2
2945 || x->types[j].bitfield.sreg3
2946 || x->types[j].bitfield.control
2947 || x->types[j].bitfield.debug
2948 || x->types[j].bitfield.test)
2949 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2950 if (operand_type_check (x->types[j], imm))
2952 if (operand_type_check (x->types[j], disp))
2953 pe (x->op[j].disps);
2958 pte (insn_template *t)
2961 fprintf (stdout, " %d operands ", t->operands);
2962 fprintf (stdout, "opcode %x ", t->base_opcode);
2963 if (t->extension_opcode != None)
2964 fprintf (stdout, "ext %x ", t->extension_opcode);
2965 if (t->opcode_modifier.d)
2966 fprintf (stdout, "D");
2967 if (t->opcode_modifier.w)
2968 fprintf (stdout, "W");
2969 fprintf (stdout, "\n");
2970 for (j = 0; j < t->operands; j++)
2972 fprintf (stdout, " #%d type ", j + 1);
2973 pt (t->operand_types[j]);
2974 fprintf (stdout, "\n");
2981 fprintf (stdout, " operation %d\n", e->X_op);
2982 fprintf (stdout, " add_number %ld (%lx)\n",
2983 (long) e->X_add_number, (long) e->X_add_number);
2984 if (e->X_add_symbol)
2986 fprintf (stdout, " add_symbol ");
2987 ps (e->X_add_symbol);
2988 fprintf (stdout, "\n");
2992 fprintf (stdout, " op_symbol ");
2993 ps (e->X_op_symbol);
2994 fprintf (stdout, "\n");
3001 fprintf (stdout, "%s type %s%s",
3003 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3004 segment_name (S_GET_SEGMENT (s)));
3007 static struct type_name
3009 i386_operand_type mask;
3012 const type_names[] =
3014 { OPERAND_TYPE_REG8, "r8" },
3015 { OPERAND_TYPE_REG16, "r16" },
3016 { OPERAND_TYPE_REG32, "r32" },
3017 { OPERAND_TYPE_REG64, "r64" },
3018 { OPERAND_TYPE_IMM8, "i8" },
3019 { OPERAND_TYPE_IMM8, "i8s" },
3020 { OPERAND_TYPE_IMM16, "i16" },
3021 { OPERAND_TYPE_IMM32, "i32" },
3022 { OPERAND_TYPE_IMM32S, "i32s" },
3023 { OPERAND_TYPE_IMM64, "i64" },
3024 { OPERAND_TYPE_IMM1, "i1" },
3025 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3026 { OPERAND_TYPE_DISP8, "d8" },
3027 { OPERAND_TYPE_DISP16, "d16" },
3028 { OPERAND_TYPE_DISP32, "d32" },
3029 { OPERAND_TYPE_DISP32S, "d32s" },
3030 { OPERAND_TYPE_DISP64, "d64" },
3031 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3032 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3033 { OPERAND_TYPE_CONTROL, "control reg" },
3034 { OPERAND_TYPE_TEST, "test reg" },
3035 { OPERAND_TYPE_DEBUG, "debug reg" },
3036 { OPERAND_TYPE_FLOATREG, "FReg" },
3037 { OPERAND_TYPE_FLOATACC, "FAcc" },
3038 { OPERAND_TYPE_SREG2, "SReg2" },
3039 { OPERAND_TYPE_SREG3, "SReg3" },
3040 { OPERAND_TYPE_ACC, "Acc" },
3041 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3042 { OPERAND_TYPE_REGMMX, "rMMX" },
3043 { OPERAND_TYPE_REGXMM, "rXMM" },
3044 { OPERAND_TYPE_REGYMM, "rYMM" },
3045 { OPERAND_TYPE_REGZMM, "rZMM" },
3046 { OPERAND_TYPE_REGMASK, "Mask reg" },
3047 { OPERAND_TYPE_ESSEG, "es" },
3051 pt (i386_operand_type t)
3054 i386_operand_type a;
3056 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3058 a = operand_type_and (t, type_names[j].mask);
3059 if (!operand_type_all_zero (&a))
3060 fprintf (stdout, "%s, ", type_names[j].name);
3065 #endif /* DEBUG386 */
3067 static bfd_reloc_code_real_type
3068 reloc (unsigned int size,
3071 bfd_reloc_code_real_type other)
3073 if (other != NO_RELOC)
3075 reloc_howto_type *rel;
3080 case BFD_RELOC_X86_64_GOT32:
3081 return BFD_RELOC_X86_64_GOT64;
3083 case BFD_RELOC_X86_64_GOTPLT64:
3084 return BFD_RELOC_X86_64_GOTPLT64;
3086 case BFD_RELOC_X86_64_PLTOFF64:
3087 return BFD_RELOC_X86_64_PLTOFF64;
3089 case BFD_RELOC_X86_64_GOTPC32:
3090 other = BFD_RELOC_X86_64_GOTPC64;
3092 case BFD_RELOC_X86_64_GOTPCREL:
3093 other = BFD_RELOC_X86_64_GOTPCREL64;
3095 case BFD_RELOC_X86_64_TPOFF32:
3096 other = BFD_RELOC_X86_64_TPOFF64;
3098 case BFD_RELOC_X86_64_DTPOFF32:
3099 other = BFD_RELOC_X86_64_DTPOFF64;
3105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3106 if (other == BFD_RELOC_SIZE32)
3109 other = BFD_RELOC_SIZE64;
3112 as_bad (_("there are no pc-relative size relocations"));
3118 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3119 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3122 rel = bfd_reloc_type_lookup (stdoutput, other);
3124 as_bad (_("unknown relocation (%u)"), other);
3125 else if (size != bfd_get_reloc_size (rel))
3126 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3127 bfd_get_reloc_size (rel),
3129 else if (pcrel && !rel->pc_relative)
3130 as_bad (_("non-pc-relative relocation for pc-relative field"));
3131 else if ((rel->complain_on_overflow == complain_overflow_signed
3133 || (rel->complain_on_overflow == complain_overflow_unsigned
3135 as_bad (_("relocated field and relocation type differ in signedness"));
3144 as_bad (_("there are no unsigned pc-relative relocations"));
3147 case 1: return BFD_RELOC_8_PCREL;
3148 case 2: return BFD_RELOC_16_PCREL;
3149 case 4: return BFD_RELOC_32_PCREL;
3150 case 8: return BFD_RELOC_64_PCREL;
3152 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3159 case 4: return BFD_RELOC_X86_64_32S;
3164 case 1: return BFD_RELOC_8;
3165 case 2: return BFD_RELOC_16;
3166 case 4: return BFD_RELOC_32;
3167 case 8: return BFD_RELOC_64;
3169 as_bad (_("cannot do %s %u byte relocation"),
3170 sign > 0 ? "signed" : "unsigned", size);
3176 /* Here we decide which fixups can be adjusted to make them relative to
3177 the beginning of the section instead of the symbol. Basically we need
3178 to make sure that the dynamic relocations are done correctly, so in
3179 some cases we force the original symbol to be used. */
3182 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3188 /* Don't adjust pc-relative references to merge sections in 64-bit
3190 if (use_rela_relocations
3191 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3195 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3196 and changed later by validate_fix. */
3197 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3198 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3201 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3202 for size relocations. */
3203 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3204 || fixP->fx_r_type == BFD_RELOC_SIZE64
3205 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3206 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3207 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3209 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3219 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3234 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3242 intel_float_operand (const char *mnemonic)
3244 /* Note that the value returned is meaningful only for opcodes with (memory)
3245 operands, hence the code here is free to improperly handle opcodes that
3246 have no operands (for better performance and smaller code). */
3248 if (mnemonic[0] != 'f')
3249 return 0; /* non-math */
3251 switch (mnemonic[1])
3253 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3254 the fs segment override prefix not currently handled because no
3255 call path can make opcodes without operands get here */
3257 return 2 /* integer op */;
3259 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3260 return 3; /* fldcw/fldenv */
3263 if (mnemonic[2] != 'o' /* fnop */)
3264 return 3; /* non-waiting control op */
3267 if (mnemonic[2] == 's')
3268 return 3; /* frstor/frstpm */
3271 if (mnemonic[2] == 'a')
3272 return 3; /* fsave */
3273 if (mnemonic[2] == 't')
3275 switch (mnemonic[3])
3277 case 'c': /* fstcw */
3278 case 'd': /* fstdw */
3279 case 'e': /* fstenv */
3280 case 's': /* fsts[gw] */
3286 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3287 return 0; /* fxsave/fxrstor are not really math ops */
3294 /* Build the VEX prefix. */
3297 build_vex_prefix (const insn_template *t)
3299 unsigned int register_specifier;
3300 unsigned int implied_prefix;
3301 unsigned int vector_length;
3303 /* Check register specifier. */
3304 if (i.vex.register_specifier)
3306 register_specifier =
3307 ~register_number (i.vex.register_specifier) & 0xf;
3308 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3311 register_specifier = 0xf;
3313 /* Use 2-byte VEX prefix by swapping destination and source
3315 if (i.vec_encoding != vex_encoding_vex3
3316 && i.dir_encoding == dir_encoding_default
3317 && i.operands == i.reg_operands
3318 && i.tm.opcode_modifier.vexopcode == VEX0F
3319 && i.tm.opcode_modifier.load
3322 unsigned int xchg = i.operands - 1;
3323 union i386_op temp_op;
3324 i386_operand_type temp_type;
3326 temp_type = i.types[xchg];
3327 i.types[xchg] = i.types[0];
3328 i.types[0] = temp_type;
3329 temp_op = i.op[xchg];
3330 i.op[xchg] = i.op[0];
3333 gas_assert (i.rm.mode == 3);
3337 i.rm.regmem = i.rm.reg;
3340 /* Use the next insn. */
3344 if (i.tm.opcode_modifier.vex == VEXScalar)
3345 vector_length = avxscalar;
3346 else if (i.tm.opcode_modifier.vex == VEX256)
3353 for (op = 0; op < t->operands; ++op)
3354 if (t->operand_types[op].bitfield.xmmword
3355 && t->operand_types[op].bitfield.ymmword
3356 && i.types[op].bitfield.ymmword)
3363 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 case DATA_PREFIX_OPCODE:
3371 case REPE_PREFIX_OPCODE:
3374 case REPNE_PREFIX_OPCODE:
3381 /* Use 2-byte VEX prefix if possible. */
3382 if (i.vec_encoding != vex_encoding_vex3
3383 && i.tm.opcode_modifier.vexopcode == VEX0F
3384 && i.tm.opcode_modifier.vexw != VEXW1
3385 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3387 /* 2-byte VEX prefix. */
3391 i.vex.bytes[0] = 0xc5;
3393 /* Check the REX.R bit. */
3394 r = (i.rex & REX_R) ? 0 : 1;
3395 i.vex.bytes[1] = (r << 7
3396 | register_specifier << 3
3397 | vector_length << 2
3402 /* 3-byte VEX prefix. */
3407 switch (i.tm.opcode_modifier.vexopcode)
3411 i.vex.bytes[0] = 0xc4;
3415 i.vex.bytes[0] = 0xc4;
3419 i.vex.bytes[0] = 0xc4;
3423 i.vex.bytes[0] = 0x8f;
3427 i.vex.bytes[0] = 0x8f;
3431 i.vex.bytes[0] = 0x8f;
3437 /* The high 3 bits of the second VEX byte are 1's compliment
3438 of RXB bits from REX. */
3439 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3441 /* Check the REX.W bit. */
3442 w = (i.rex & REX_W) ? 1 : 0;
3443 if (i.tm.opcode_modifier.vexw == VEXW1)
3446 i.vex.bytes[2] = (w << 7
3447 | register_specifier << 3
3448 | vector_length << 2
3453 /* Build the EVEX prefix. */
3456 build_evex_prefix (void)
3458 unsigned int register_specifier;
3459 unsigned int implied_prefix;
3461 rex_byte vrex_used = 0;
3463 /* Check register specifier. */
3464 if (i.vex.register_specifier)
3466 gas_assert ((i.vrex & REX_X) == 0);
3468 register_specifier = i.vex.register_specifier->reg_num;
3469 if ((i.vex.register_specifier->reg_flags & RegRex))
3470 register_specifier += 8;
3471 /* The upper 16 registers are encoded in the fourth byte of the
3473 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3474 i.vex.bytes[3] = 0x8;
3475 register_specifier = ~register_specifier & 0xf;
3479 register_specifier = 0xf;
3481 /* Encode upper 16 vector index register in the fourth byte of
3483 if (!(i.vrex & REX_X))
3484 i.vex.bytes[3] = 0x8;
3489 switch ((i.tm.base_opcode >> 8) & 0xff)
3494 case DATA_PREFIX_OPCODE:
3497 case REPE_PREFIX_OPCODE:
3500 case REPNE_PREFIX_OPCODE:
3507 /* 4 byte EVEX prefix. */
3509 i.vex.bytes[0] = 0x62;
3512 switch (i.tm.opcode_modifier.vexopcode)
3528 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3530 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3532 /* The fifth bit of the second EVEX byte is 1's compliment of the
3533 REX_R bit in VREX. */
3534 if (!(i.vrex & REX_R))
3535 i.vex.bytes[1] |= 0x10;
3539 if ((i.reg_operands + i.imm_operands) == i.operands)
3541 /* When all operands are registers, the REX_X bit in REX is not
3542 used. We reuse it to encode the upper 16 registers, which is
3543 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3544 as 1's compliment. */
3545 if ((i.vrex & REX_B))
3548 i.vex.bytes[1] &= ~0x40;
3552 /* EVEX instructions shouldn't need the REX prefix. */
3553 i.vrex &= ~vrex_used;
3554 gas_assert (i.vrex == 0);
3556 /* Check the REX.W bit. */
3557 w = (i.rex & REX_W) ? 1 : 0;
3558 if (i.tm.opcode_modifier.vexw)
3560 if (i.tm.opcode_modifier.vexw == VEXW1)
3563 /* If w is not set it means we are dealing with WIG instruction. */
3566 if (evexwig == evexw1)
3570 /* Encode the U bit. */
3571 implied_prefix |= 0x4;
3573 /* The third byte of the EVEX prefix. */
3574 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3576 /* The fourth byte of the EVEX prefix. */
3577 /* The zeroing-masking bit. */
3578 if (i.mask && i.mask->zeroing)
3579 i.vex.bytes[3] |= 0x80;
3581 /* Don't always set the broadcast bit if there is no RC. */
3584 /* Encode the vector length. */
3585 unsigned int vec_length;
3587 switch (i.tm.opcode_modifier.evex)
3589 case EVEXLIG: /* LL' is ignored */
3590 vec_length = evexlig << 5;
3593 vec_length = 0 << 5;
3596 vec_length = 1 << 5;
3599 vec_length = 2 << 5;
3605 i.vex.bytes[3] |= vec_length;
3606 /* Encode the broadcast bit. */
3608 i.vex.bytes[3] |= 0x10;
3612 if (i.rounding->type != saeonly)
3613 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3615 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3618 if (i.mask && i.mask->mask)
3619 i.vex.bytes[3] |= i.mask->mask->reg_num;
3623 process_immext (void)
3627 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3630 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3631 with an opcode suffix which is coded in the same place as an
3632 8-bit immediate field would be.
3633 Here we check those operands and remove them afterwards. */
3636 for (x = 0; x < i.operands; x++)
3637 if (register_number (i.op[x].regs) != x)
3638 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3639 register_prefix, i.op[x].regs->reg_name, x + 1,
3645 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3647 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3648 suffix which is coded in the same place as an 8-bit immediate
3650 Here we check those operands and remove them afterwards. */
3653 if (i.operands != 3)
3656 for (x = 0; x < 2; x++)
3657 if (register_number (i.op[x].regs) != x)
3658 goto bad_register_operand;
3660 /* Check for third operand for mwaitx/monitorx insn. */
3661 if (register_number (i.op[x].regs)
3662 != (x + (i.tm.extension_opcode == 0xfb)))
3664 bad_register_operand:
3665 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3666 register_prefix, i.op[x].regs->reg_name, x+1,
3673 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3674 which is coded in the same place as an 8-bit immediate field
3675 would be. Here we fake an 8-bit immediate operand from the
3676 opcode suffix stored in tm.extension_opcode.
3678 AVX instructions also use this encoding, for some of
3679 3 argument instructions. */
3681 gas_assert (i.imm_operands <= 1
3683 || ((i.tm.opcode_modifier.vex
3684 || i.tm.opcode_modifier.evex)
3685 && i.operands <= 4)));
3687 exp = &im_expressions[i.imm_operands++];
3688 i.op[i.operands].imms = exp;
3689 i.types[i.operands] = imm8;
3691 exp->X_op = O_constant;
3692 exp->X_add_number = i.tm.extension_opcode;
3693 i.tm.extension_opcode = None;
3700 switch (i.tm.opcode_modifier.hleprefixok)
3705 as_bad (_("invalid instruction `%s' after `%s'"),
3706 i.tm.name, i.hle_prefix);
3709 if (i.prefix[LOCK_PREFIX])
3711 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3715 case HLEPrefixRelease:
3716 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3718 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3722 if (i.mem_operands == 0
3723 || !operand_type_check (i.types[i.operands - 1], anymem))
3725 as_bad (_("memory destination needed for instruction `%s'"
3726 " after `xrelease'"), i.tm.name);
3733 /* Try the shortest encoding by shortening operand size. */
3736 optimize_encoding (void)
3740 if (optimize_for_space
3741 && i.reg_operands == 1
3742 && i.imm_operands == 1
3743 && !i.types[1].bitfield.byte
3744 && i.op[0].imms->X_op == O_constant
3745 && fits_in_imm7 (i.op[0].imms->X_add_number)
3746 && ((i.tm.base_opcode == 0xa8
3747 && i.tm.extension_opcode == None)
3748 || (i.tm.base_opcode == 0xf6
3749 && i.tm.extension_opcode == 0x0)))
3752 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3754 unsigned int base_regnum = i.op[1].regs->reg_num;
3755 if (flag_code == CODE_64BIT || base_regnum < 4)
3757 i.types[1].bitfield.byte = 1;
3758 /* Ignore the suffix. */
3760 if (base_regnum >= 4
3761 && !(i.op[1].regs->reg_flags & RegRex))
3763 /* Handle SP, BP, SI and DI registers. */
3764 if (i.types[1].bitfield.word)
3766 else if (i.types[1].bitfield.dword)
3774 else if (flag_code == CODE_64BIT
3775 && ((i.reg_operands == 1
3776 && i.imm_operands == 1
3777 && i.op[0].imms->X_op == O_constant
3778 && ((i.tm.base_opcode == 0xb0
3779 && i.tm.extension_opcode == None
3780 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3781 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3782 && (((i.tm.base_opcode == 0x24
3783 || i.tm.base_opcode == 0xa8)
3784 && i.tm.extension_opcode == None)
3785 || (i.tm.base_opcode == 0x80
3786 && i.tm.extension_opcode == 0x4)
3787 || ((i.tm.base_opcode == 0xf6
3788 || i.tm.base_opcode == 0xc6)
3789 && i.tm.extension_opcode == 0x0)))))
3790 || (i.reg_operands == 2
3791 && i.op[0].regs == i.op[1].regs
3792 && ((i.tm.base_opcode == 0x30
3793 || i.tm.base_opcode == 0x28)
3794 && i.tm.extension_opcode == None)))
3795 && i.types[1].bitfield.qword)
3798 andq $imm31, %r64 -> andl $imm31, %r32
3799 testq $imm31, %r64 -> testl $imm31, %r32
3800 xorq %r64, %r64 -> xorl %r32, %r32
3801 subq %r64, %r64 -> subl %r32, %r32
3802 movq $imm31, %r64 -> movl $imm31, %r32
3803 movq $imm32, %r64 -> movl $imm32, %r32
3805 i.tm.opcode_modifier.norex64 = 1;
3806 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3809 movq $imm31, %r64 -> movl $imm31, %r32
3810 movq $imm32, %r64 -> movl $imm32, %r32
3812 i.tm.operand_types[0].bitfield.imm32 = 1;
3813 i.tm.operand_types[0].bitfield.imm32s = 0;
3814 i.tm.operand_types[0].bitfield.imm64 = 0;
3815 i.types[0].bitfield.imm32 = 1;
3816 i.types[0].bitfield.imm32s = 0;
3817 i.types[0].bitfield.imm64 = 0;
3818 i.types[1].bitfield.dword = 1;
3819 i.types[1].bitfield.qword = 0;
3820 if (i.tm.base_opcode == 0xc6)
3823 movq $imm31, %r64 -> movl $imm31, %r32
3825 i.tm.base_opcode = 0xb0;
3826 i.tm.extension_opcode = None;
3827 i.tm.opcode_modifier.shortform = 1;
3828 i.tm.opcode_modifier.modrm = 0;
3832 else if (optimize > 1
3833 && i.reg_operands == 3
3834 && i.op[0].regs == i.op[1].regs
3835 && !i.types[2].bitfield.xmmword
3836 && (i.tm.opcode_modifier.vex
3839 && i.tm.opcode_modifier.evex
3840 && cpu_arch_flags.bitfield.cpuavx512vl))
3841 && ((i.tm.base_opcode == 0x55
3842 || i.tm.base_opcode == 0x6655
3843 || i.tm.base_opcode == 0x66df
3844 || i.tm.base_opcode == 0x57
3845 || i.tm.base_opcode == 0x6657
3846 || i.tm.base_opcode == 0x66ef
3847 || i.tm.base_opcode == 0x66f8
3848 || i.tm.base_opcode == 0x66f9
3849 || i.tm.base_opcode == 0x66fa
3850 || i.tm.base_opcode == 0x66fb)
3851 && i.tm.extension_opcode == None))
3854 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3856 EVEX VOP %zmmM, %zmmM, %zmmN
3857 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3858 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3859 EVEX VOP %ymmM, %ymmM, %ymmN
3860 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3861 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3862 VEX VOP %ymmM, %ymmM, %ymmN
3863 -> VEX VOP %xmmM, %xmmM, %xmmN
3864 VOP, one of vpandn and vpxor:
3865 VEX VOP %ymmM, %ymmM, %ymmN
3866 -> VEX VOP %xmmM, %xmmM, %xmmN
3867 VOP, one of vpandnd and vpandnq:
3868 EVEX VOP %zmmM, %zmmM, %zmmN
3869 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3870 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3871 EVEX VOP %ymmM, %ymmM, %ymmN
3872 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3873 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3874 VOP, one of vpxord and vpxorq:
3875 EVEX VOP %zmmM, %zmmM, %zmmN
3876 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3877 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3878 EVEX VOP %ymmM, %ymmM, %ymmN
3879 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3880 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 if (i.tm.opcode_modifier.evex)
3884 /* If only lower 16 vector registers are used, we can use
3886 for (j = 0; j < 3; j++)
3887 if (register_number (i.op[j].regs) > 15)
3891 i.tm.opcode_modifier.evex = EVEX128;
3894 i.tm.opcode_modifier.vex = VEX128;
3895 i.tm.opcode_modifier.vexw = VEXW0;
3896 i.tm.opcode_modifier.evex = 0;
3900 i.tm.opcode_modifier.vex = VEX128;
3902 if (i.tm.opcode_modifier.vex)
3903 for (j = 0; j < 3; j++)
3905 i.types[j].bitfield.xmmword = 1;
3906 i.types[j].bitfield.ymmword = 0;
3911 /* This is the guts of the machine-dependent assembler. LINE points to a
3912 machine dependent instruction. This function is supposed to emit
3913 the frags/bytes it assembles to. */
3916 md_assemble (char *line)
3919 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3920 const insn_template *t;
3922 /* Initialize globals. */
3923 memset (&i, '\0', sizeof (i));
3924 for (j = 0; j < MAX_OPERANDS; j++)
3925 i.reloc[j] = NO_RELOC;
3926 memset (disp_expressions, '\0', sizeof (disp_expressions));
3927 memset (im_expressions, '\0', sizeof (im_expressions));
3928 save_stack_p = save_stack;
3930 /* First parse an instruction mnemonic & call i386_operand for the operands.
3931 We assume that the scrubber has arranged it so that line[0] is the valid
3932 start of a (possibly prefixed) mnemonic. */
3934 line = parse_insn (line, mnemonic);
3937 mnem_suffix = i.suffix;
3939 line = parse_operands (line, mnemonic);
3941 xfree (i.memop1_string);
3942 i.memop1_string = NULL;
3946 /* Now we've parsed the mnemonic into a set of templates, and have the
3947 operands at hand. */
3949 /* All intel opcodes have reversed operands except for "bound" and
3950 "enter". We also don't reverse intersegment "jmp" and "call"
3951 instructions with 2 immediate operands so that the immediate segment
3952 precedes the offset, as it does when in AT&T mode. */
3955 && (strcmp (mnemonic, "bound") != 0)
3956 && (strcmp (mnemonic, "invlpga") != 0)
3957 && !(operand_type_check (i.types[0], imm)
3958 && operand_type_check (i.types[1], imm)))
3961 /* The order of the immediates should be reversed
3962 for 2 immediates extrq and insertq instructions */
3963 if (i.imm_operands == 2
3964 && (strcmp (mnemonic, "extrq") == 0
3965 || strcmp (mnemonic, "insertq") == 0))
3966 swap_2_operands (0, 1);
3971 /* Don't optimize displacement for movabs since it only takes 64bit
3974 && i.disp_encoding != disp_encoding_32bit
3975 && (flag_code != CODE_64BIT
3976 || strcmp (mnemonic, "movabs") != 0))
3979 /* Next, we find a template that matches the given insn,
3980 making sure the overlap of the given operands types is consistent
3981 with the template operand types. */
3983 if (!(t = match_template (mnem_suffix)))
3986 if (sse_check != check_none
3987 && !i.tm.opcode_modifier.noavx
3988 && !i.tm.cpu_flags.bitfield.cpuavx
3989 && (i.tm.cpu_flags.bitfield.cpusse
3990 || i.tm.cpu_flags.bitfield.cpusse2
3991 || i.tm.cpu_flags.bitfield.cpusse3
3992 || i.tm.cpu_flags.bitfield.cpussse3
3993 || i.tm.cpu_flags.bitfield.cpusse4_1
3994 || i.tm.cpu_flags.bitfield.cpusse4_2
3995 || i.tm.cpu_flags.bitfield.cpupclmul
3996 || i.tm.cpu_flags.bitfield.cpuaes
3997 || i.tm.cpu_flags.bitfield.cpugfni))
3999 (sse_check == check_warning
4001 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4004 /* Zap movzx and movsx suffix. The suffix has been set from
4005 "word ptr" or "byte ptr" on the source operand in Intel syntax
4006 or extracted from mnemonic in AT&T syntax. But we'll use
4007 the destination register to choose the suffix for encoding. */
4008 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4010 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4011 there is no suffix, the default will be byte extension. */
4012 if (i.reg_operands != 2
4015 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4020 if (i.tm.opcode_modifier.fwait)
4021 if (!add_prefix (FWAIT_OPCODE))
4024 /* Check if REP prefix is OK. */
4025 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4027 as_bad (_("invalid instruction `%s' after `%s'"),
4028 i.tm.name, i.rep_prefix);
4032 /* Check for lock without a lockable instruction. Destination operand
4033 must be memory unless it is xchg (0x86). */
4034 if (i.prefix[LOCK_PREFIX]
4035 && (!i.tm.opcode_modifier.islockable
4036 || i.mem_operands == 0
4037 || (i.tm.base_opcode != 0x86
4038 && !operand_type_check (i.types[i.operands - 1], anymem))))
4040 as_bad (_("expecting lockable instruction after `lock'"));
4044 /* Check if HLE prefix is OK. */
4045 if (i.hle_prefix && !check_hle ())
4048 /* Check BND prefix. */
4049 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4050 as_bad (_("expecting valid branch instruction after `bnd'"));
4052 /* Check NOTRACK prefix. */
4053 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4054 as_bad (_("expecting indirect branch instruction after `notrack'"));
4056 if (i.tm.cpu_flags.bitfield.cpumpx)
4058 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4059 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4060 else if (flag_code != CODE_16BIT
4061 ? i.prefix[ADDR_PREFIX]
4062 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4063 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4066 /* Insert BND prefix. */
4068 && i.tm.opcode_modifier.bndprefixok
4069 && !i.prefix[BND_PREFIX])
4070 add_prefix (BND_PREFIX_OPCODE);
4072 /* Check string instruction segment overrides. */
4073 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4075 if (!check_string ())
4077 i.disp_operands = 0;
4080 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4081 optimize_encoding ();
4083 if (!process_suffix ())
4086 /* Update operand types. */
4087 for (j = 0; j < i.operands; j++)
4088 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4090 /* Make still unresolved immediate matches conform to size of immediate
4091 given in i.suffix. */
4092 if (!finalize_imm ())
4095 if (i.types[0].bitfield.imm1)
4096 i.imm_operands = 0; /* kludge for shift insns. */
4098 /* We only need to check those implicit registers for instructions
4099 with 3 operands or less. */
4100 if (i.operands <= 3)
4101 for (j = 0; j < i.operands; j++)
4102 if (i.types[j].bitfield.inoutportreg
4103 || i.types[j].bitfield.shiftcount
4104 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4107 /* ImmExt should be processed after SSE2AVX. */
4108 if (!i.tm.opcode_modifier.sse2avx
4109 && i.tm.opcode_modifier.immext)
4112 /* For insns with operands there are more diddles to do to the opcode. */
4115 if (!process_operands ())
4118 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4120 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4121 as_warn (_("translating to `%sp'"), i.tm.name);
4124 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4126 if (flag_code == CODE_16BIT)
4128 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4133 if (i.tm.opcode_modifier.vex)
4134 build_vex_prefix (t);
4136 build_evex_prefix ();
4139 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4140 instructions may define INT_OPCODE as well, so avoid this corner
4141 case for those instructions that use MODRM. */
4142 if (i.tm.base_opcode == INT_OPCODE
4143 && !i.tm.opcode_modifier.modrm
4144 && i.op[0].imms->X_add_number == 3)
4146 i.tm.base_opcode = INT3_OPCODE;
4150 if ((i.tm.opcode_modifier.jump
4151 || i.tm.opcode_modifier.jumpbyte
4152 || i.tm.opcode_modifier.jumpdword)
4153 && i.op[0].disps->X_op == O_constant)
4155 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4156 the absolute address given by the constant. Since ix86 jumps and
4157 calls are pc relative, we need to generate a reloc. */
4158 i.op[0].disps->X_add_symbol = &abs_symbol;
4159 i.op[0].disps->X_op = O_symbol;
4162 if (i.tm.opcode_modifier.rex64)
4165 /* For 8 bit registers we need an empty rex prefix. Also if the
4166 instruction already has a prefix, we need to convert old
4167 registers to new ones. */
4169 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4170 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4171 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4172 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4173 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4174 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4179 i.rex |= REX_OPCODE;
4180 for (x = 0; x < 2; x++)
4182 /* Look for 8 bit operand that uses old registers. */
4183 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4184 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4186 /* In case it is "hi" register, give up. */
4187 if (i.op[x].regs->reg_num > 3)
4188 as_bad (_("can't encode register '%s%s' in an "
4189 "instruction requiring REX prefix."),
4190 register_prefix, i.op[x].regs->reg_name);
4192 /* Otherwise it is equivalent to the extended register.
4193 Since the encoding doesn't change this is merely
4194 cosmetic cleanup for debug output. */
4196 i.op[x].regs = i.op[x].regs + 8;
4201 if (i.rex == 0 && i.rex_encoding)
4203 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4204 that uses legacy register. If it is "hi" register, don't add
4205 the REX_OPCODE byte. */
4207 for (x = 0; x < 2; x++)
4208 if (i.types[x].bitfield.reg
4209 && i.types[x].bitfield.byte
4210 && (i.op[x].regs->reg_flags & RegRex64) == 0
4211 && i.op[x].regs->reg_num > 3)
4213 i.rex_encoding = FALSE;
4222 add_prefix (REX_OPCODE | i.rex);
4224 /* We are ready to output the insn. */
4229 parse_insn (char *line, char *mnemonic)
4232 char *token_start = l;
4235 const insn_template *t;
4241 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4246 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4248 as_bad (_("no such instruction: `%s'"), token_start);
4253 if (!is_space_char (*l)
4254 && *l != END_OF_INSN
4256 || (*l != PREFIX_SEPARATOR
4259 as_bad (_("invalid character %s in mnemonic"),
4260 output_invalid (*l));
4263 if (token_start == l)
4265 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4266 as_bad (_("expecting prefix; got nothing"));
4268 as_bad (_("expecting mnemonic; got nothing"));
4272 /* Look up instruction (or prefix) via hash table. */
4273 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4275 if (*l != END_OF_INSN
4276 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4277 && current_templates
4278 && current_templates->start->opcode_modifier.isprefix)
4280 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4282 as_bad ((flag_code != CODE_64BIT
4283 ? _("`%s' is only supported in 64-bit mode")
4284 : _("`%s' is not supported in 64-bit mode")),
4285 current_templates->start->name);
4288 /* If we are in 16-bit mode, do not allow addr16 or data16.
4289 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4290 if ((current_templates->start->opcode_modifier.size16
4291 || current_templates->start->opcode_modifier.size32)
4292 && flag_code != CODE_64BIT
4293 && (current_templates->start->opcode_modifier.size32
4294 ^ (flag_code == CODE_16BIT)))
4296 as_bad (_("redundant %s prefix"),
4297 current_templates->start->name);
4300 if (current_templates->start->opcode_length == 0)
4302 /* Handle pseudo prefixes. */
4303 switch (current_templates->start->base_opcode)
4307 i.disp_encoding = disp_encoding_8bit;
4311 i.disp_encoding = disp_encoding_32bit;
4315 i.dir_encoding = dir_encoding_load;
4319 i.dir_encoding = dir_encoding_store;
4323 i.vec_encoding = vex_encoding_vex2;
4327 i.vec_encoding = vex_encoding_vex3;
4331 i.vec_encoding = vex_encoding_evex;
4335 i.rex_encoding = TRUE;
4339 i.no_optimize = TRUE;
4347 /* Add prefix, checking for repeated prefixes. */
4348 switch (add_prefix (current_templates->start->base_opcode))
4353 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4354 i.notrack_prefix = current_templates->start->name;
4357 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4358 i.hle_prefix = current_templates->start->name;
4359 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4360 i.bnd_prefix = current_templates->start->name;
4362 i.rep_prefix = current_templates->start->name;
4368 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4375 if (!current_templates)
4377 /* Check if we should swap operand or force 32bit displacement in
4379 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4380 i.dir_encoding = dir_encoding_store;
4381 else if (mnem_p - 3 == dot_p
4384 i.disp_encoding = disp_encoding_8bit;
4385 else if (mnem_p - 4 == dot_p
4389 i.disp_encoding = disp_encoding_32bit;
4394 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4397 if (!current_templates)
4400 /* See if we can get a match by trimming off a suffix. */
4403 case WORD_MNEM_SUFFIX:
4404 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4405 i.suffix = SHORT_MNEM_SUFFIX;
4408 case BYTE_MNEM_SUFFIX:
4409 case QWORD_MNEM_SUFFIX:
4410 i.suffix = mnem_p[-1];
4412 current_templates = (const templates *) hash_find (op_hash,
4415 case SHORT_MNEM_SUFFIX:
4416 case LONG_MNEM_SUFFIX:
4419 i.suffix = mnem_p[-1];
4421 current_templates = (const templates *) hash_find (op_hash,
4430 if (intel_float_operand (mnemonic) == 1)
4431 i.suffix = SHORT_MNEM_SUFFIX;
4433 i.suffix = LONG_MNEM_SUFFIX;
4435 current_templates = (const templates *) hash_find (op_hash,
4440 if (!current_templates)
4442 as_bad (_("no such instruction: `%s'"), token_start);
4447 if (current_templates->start->opcode_modifier.jump
4448 || current_templates->start->opcode_modifier.jumpbyte)
4450 /* Check for a branch hint. We allow ",pt" and ",pn" for
4451 predict taken and predict not taken respectively.
4452 I'm not sure that branch hints actually do anything on loop
4453 and jcxz insns (JumpByte) for current Pentium4 chips. They
4454 may work in the future and it doesn't hurt to accept them
4456 if (l[0] == ',' && l[1] == 'p')
4460 if (!add_prefix (DS_PREFIX_OPCODE))
4464 else if (l[2] == 'n')
4466 if (!add_prefix (CS_PREFIX_OPCODE))
4472 /* Any other comma loses. */
4475 as_bad (_("invalid character %s in mnemonic"),
4476 output_invalid (*l));
4480 /* Check if instruction is supported on specified architecture. */
4482 for (t = current_templates->start; t < current_templates->end; ++t)
4484 supported |= cpu_flags_match (t);
4485 if (supported == CPU_FLAGS_PERFECT_MATCH)
4489 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4491 as_bad (flag_code == CODE_64BIT
4492 ? _("`%s' is not supported in 64-bit mode")
4493 : _("`%s' is only supported in 64-bit mode"),
4494 current_templates->start->name);
4497 if (supported != CPU_FLAGS_PERFECT_MATCH)
4499 as_bad (_("`%s' is not supported on `%s%s'"),
4500 current_templates->start->name,
4501 cpu_arch_name ? cpu_arch_name : default_arch,
4502 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4507 if (!cpu_arch_flags.bitfield.cpui386
4508 && (flag_code != CODE_16BIT))
4510 as_warn (_("use .code16 to ensure correct addressing mode"));
4517 parse_operands (char *l, const char *mnemonic)
4521 /* 1 if operand is pending after ','. */
4522 unsigned int expecting_operand = 0;
4524 /* Non-zero if operand parens not balanced. */
4525 unsigned int paren_not_balanced;
4527 while (*l != END_OF_INSN)
4529 /* Skip optional white space before operand. */
4530 if (is_space_char (*l))
4532 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4534 as_bad (_("invalid character %s before operand %d"),
4535 output_invalid (*l),
4539 token_start = l; /* After white space. */
4540 paren_not_balanced = 0;
4541 while (paren_not_balanced || *l != ',')
4543 if (*l == END_OF_INSN)
4545 if (paren_not_balanced)
4548 as_bad (_("unbalanced parenthesis in operand %d."),
4551 as_bad (_("unbalanced brackets in operand %d."),
4556 break; /* we are done */
4558 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4560 as_bad (_("invalid character %s in operand %d"),
4561 output_invalid (*l),
4568 ++paren_not_balanced;
4570 --paren_not_balanced;
4575 ++paren_not_balanced;
4577 --paren_not_balanced;
4581 if (l != token_start)
4582 { /* Yes, we've read in another operand. */
4583 unsigned int operand_ok;
4584 this_operand = i.operands++;
4585 if (i.operands > MAX_OPERANDS)
4587 as_bad (_("spurious operands; (%d operands/instruction max)"),
4591 i.types[this_operand].bitfield.unspecified = 1;
4592 /* Now parse operand adding info to 'i' as we go along. */
4593 END_STRING_AND_SAVE (l);
4597 i386_intel_operand (token_start,
4598 intel_float_operand (mnemonic));
4600 operand_ok = i386_att_operand (token_start);
4602 RESTORE_END_STRING (l);
4608 if (expecting_operand)
4610 expecting_operand_after_comma:
4611 as_bad (_("expecting operand after ','; got nothing"));
4616 as_bad (_("expecting operand before ','; got nothing"));
4621 /* Now *l must be either ',' or END_OF_INSN. */
4624 if (*++l == END_OF_INSN)
4626 /* Just skip it, if it's \n complain. */
4627 goto expecting_operand_after_comma;
4629 expecting_operand = 1;
4636 swap_2_operands (int xchg1, int xchg2)
4638 union i386_op temp_op;
4639 i386_operand_type temp_type;
4640 enum bfd_reloc_code_real temp_reloc;
4642 temp_type = i.types[xchg2];
4643 i.types[xchg2] = i.types[xchg1];
4644 i.types[xchg1] = temp_type;
4645 temp_op = i.op[xchg2];
4646 i.op[xchg2] = i.op[xchg1];
4647 i.op[xchg1] = temp_op;
4648 temp_reloc = i.reloc[xchg2];
4649 i.reloc[xchg2] = i.reloc[xchg1];
4650 i.reloc[xchg1] = temp_reloc;
4654 if (i.mask->operand == xchg1)
4655 i.mask->operand = xchg2;
4656 else if (i.mask->operand == xchg2)
4657 i.mask->operand = xchg1;
4661 if (i.broadcast->operand == xchg1)
4662 i.broadcast->operand = xchg2;
4663 else if (i.broadcast->operand == xchg2)
4664 i.broadcast->operand = xchg1;
4668 if (i.rounding->operand == xchg1)
4669 i.rounding->operand = xchg2;
4670 else if (i.rounding->operand == xchg2)
4671 i.rounding->operand = xchg1;
4676 swap_operands (void)
4682 swap_2_operands (1, i.operands - 2);
4686 swap_2_operands (0, i.operands - 1);
4692 if (i.mem_operands == 2)
4694 const seg_entry *temp_seg;
4695 temp_seg = i.seg[0];
4696 i.seg[0] = i.seg[1];
4697 i.seg[1] = temp_seg;
4701 /* Try to ensure constant immediates are represented in the smallest
4706 char guess_suffix = 0;
4710 guess_suffix = i.suffix;
4711 else if (i.reg_operands)
4713 /* Figure out a suffix from the last register operand specified.
4714 We can't do this properly yet, ie. excluding InOutPortReg,
4715 but the following works for instructions with immediates.
4716 In any case, we can't set i.suffix yet. */
4717 for (op = i.operands; --op >= 0;)
4718 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4720 guess_suffix = BYTE_MNEM_SUFFIX;
4723 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4725 guess_suffix = WORD_MNEM_SUFFIX;
4728 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4730 guess_suffix = LONG_MNEM_SUFFIX;
4733 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4735 guess_suffix = QWORD_MNEM_SUFFIX;
4739 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4740 guess_suffix = WORD_MNEM_SUFFIX;
4742 for (op = i.operands; --op >= 0;)
4743 if (operand_type_check (i.types[op], imm))
4745 switch (i.op[op].imms->X_op)
4748 /* If a suffix is given, this operand may be shortened. */
4749 switch (guess_suffix)
4751 case LONG_MNEM_SUFFIX:
4752 i.types[op].bitfield.imm32 = 1;
4753 i.types[op].bitfield.imm64 = 1;
4755 case WORD_MNEM_SUFFIX:
4756 i.types[op].bitfield.imm16 = 1;
4757 i.types[op].bitfield.imm32 = 1;
4758 i.types[op].bitfield.imm32s = 1;
4759 i.types[op].bitfield.imm64 = 1;
4761 case BYTE_MNEM_SUFFIX:
4762 i.types[op].bitfield.imm8 = 1;
4763 i.types[op].bitfield.imm8s = 1;
4764 i.types[op].bitfield.imm16 = 1;
4765 i.types[op].bitfield.imm32 = 1;
4766 i.types[op].bitfield.imm32s = 1;
4767 i.types[op].bitfield.imm64 = 1;
4771 /* If this operand is at most 16 bits, convert it
4772 to a signed 16 bit number before trying to see
4773 whether it will fit in an even smaller size.
4774 This allows a 16-bit operand such as $0xffe0 to
4775 be recognised as within Imm8S range. */
4776 if ((i.types[op].bitfield.imm16)
4777 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4779 i.op[op].imms->X_add_number =
4780 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4783 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4784 if ((i.types[op].bitfield.imm32)
4785 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4788 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4789 ^ ((offsetT) 1 << 31))
4790 - ((offsetT) 1 << 31));
4794 = operand_type_or (i.types[op],
4795 smallest_imm_type (i.op[op].imms->X_add_number));
4797 /* We must avoid matching of Imm32 templates when 64bit
4798 only immediate is available. */
4799 if (guess_suffix == QWORD_MNEM_SUFFIX)
4800 i.types[op].bitfield.imm32 = 0;
4807 /* Symbols and expressions. */
4809 /* Convert symbolic operand to proper sizes for matching, but don't
4810 prevent matching a set of insns that only supports sizes other
4811 than those matching the insn suffix. */
4813 i386_operand_type mask, allowed;
4814 const insn_template *t;
4816 operand_type_set (&mask, 0);
4817 operand_type_set (&allowed, 0);
4819 for (t = current_templates->start;
4820 t < current_templates->end;
4822 allowed = operand_type_or (allowed,
4823 t->operand_types[op]);
4824 switch (guess_suffix)
4826 case QWORD_MNEM_SUFFIX:
4827 mask.bitfield.imm64 = 1;
4828 mask.bitfield.imm32s = 1;
4830 case LONG_MNEM_SUFFIX:
4831 mask.bitfield.imm32 = 1;
4833 case WORD_MNEM_SUFFIX:
4834 mask.bitfield.imm16 = 1;
4836 case BYTE_MNEM_SUFFIX:
4837 mask.bitfield.imm8 = 1;
4842 allowed = operand_type_and (mask, allowed);
4843 if (!operand_type_all_zero (&allowed))
4844 i.types[op] = operand_type_and (i.types[op], mask);
4851 /* Try to use the smallest displacement type too. */
4853 optimize_disp (void)
4857 for (op = i.operands; --op >= 0;)
4858 if (operand_type_check (i.types[op], disp))
4860 if (i.op[op].disps->X_op == O_constant)
4862 offsetT op_disp = i.op[op].disps->X_add_number;
4864 if (i.types[op].bitfield.disp16
4865 && (op_disp & ~(offsetT) 0xffff) == 0)
4867 /* If this operand is at most 16 bits, convert
4868 to a signed 16 bit number and don't use 64bit
4870 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4871 i.types[op].bitfield.disp64 = 0;
4874 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4875 if (i.types[op].bitfield.disp32
4876 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4878 /* If this operand is at most 32 bits, convert
4879 to a signed 32 bit number and don't use 64bit
4881 op_disp &= (((offsetT) 2 << 31) - 1);
4882 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4883 i.types[op].bitfield.disp64 = 0;
4886 if (!op_disp && i.types[op].bitfield.baseindex)
4888 i.types[op].bitfield.disp8 = 0;
4889 i.types[op].bitfield.disp16 = 0;
4890 i.types[op].bitfield.disp32 = 0;
4891 i.types[op].bitfield.disp32s = 0;
4892 i.types[op].bitfield.disp64 = 0;
4896 else if (flag_code == CODE_64BIT)
4898 if (fits_in_signed_long (op_disp))
4900 i.types[op].bitfield.disp64 = 0;
4901 i.types[op].bitfield.disp32s = 1;
4903 if (i.prefix[ADDR_PREFIX]
4904 && fits_in_unsigned_long (op_disp))
4905 i.types[op].bitfield.disp32 = 1;
4907 if ((i.types[op].bitfield.disp32
4908 || i.types[op].bitfield.disp32s
4909 || i.types[op].bitfield.disp16)
4910 && fits_in_disp8 (op_disp))
4911 i.types[op].bitfield.disp8 = 1;
4913 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4914 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4916 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4917 i.op[op].disps, 0, i.reloc[op]);
4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
4925 /* We only support 64bit displacement on constants. */
4926 i.types[op].bitfield.disp64 = 0;
4930 /* Check if operands are valid for the instruction. */
4933 check_VecOperands (const insn_template *t)
4937 /* Without VSIB byte, we can't have a vector register for index. */
4938 if (!t->opcode_modifier.vecsib
4940 && (i.index_reg->reg_type.bitfield.xmmword
4941 || i.index_reg->reg_type.bitfield.ymmword
4942 || i.index_reg->reg_type.bitfield.zmmword))
4944 i.error = unsupported_vector_index_register;
4948 /* Check if default mask is allowed. */
4949 if (t->opcode_modifier.nodefmask
4950 && (!i.mask || i.mask->mask->reg_num == 0))
4952 i.error = no_default_mask;
4956 /* For VSIB byte, we need a vector register for index, and all vector
4957 registers must be distinct. */
4958 if (t->opcode_modifier.vecsib)
4961 || !((t->opcode_modifier.vecsib == VecSIB128
4962 && i.index_reg->reg_type.bitfield.xmmword)
4963 || (t->opcode_modifier.vecsib == VecSIB256
4964 && i.index_reg->reg_type.bitfield.ymmword)
4965 || (t->opcode_modifier.vecsib == VecSIB512
4966 && i.index_reg->reg_type.bitfield.zmmword)))
4968 i.error = invalid_vsib_address;
4972 gas_assert (i.reg_operands == 2 || i.mask);
4973 if (i.reg_operands == 2 && !i.mask)
4975 gas_assert (i.types[0].bitfield.regsimd);
4976 gas_assert (i.types[0].bitfield.xmmword
4977 || i.types[0].bitfield.ymmword);
4978 gas_assert (i.types[2].bitfield.regsimd);
4979 gas_assert (i.types[2].bitfield.xmmword
4980 || i.types[2].bitfield.ymmword);
4981 if (operand_check == check_none)
4983 if (register_number (i.op[0].regs)
4984 != register_number (i.index_reg)
4985 && register_number (i.op[2].regs)
4986 != register_number (i.index_reg)
4987 && register_number (i.op[0].regs)
4988 != register_number (i.op[2].regs))
4990 if (operand_check == check_error)
4992 i.error = invalid_vector_register_set;
4995 as_warn (_("mask, index, and destination registers should be distinct"));
4997 else if (i.reg_operands == 1 && i.mask)
4999 if (i.types[1].bitfield.regsimd
5000 && (i.types[1].bitfield.xmmword
5001 || i.types[1].bitfield.ymmword
5002 || i.types[1].bitfield.zmmword)
5003 && (register_number (i.op[1].regs)
5004 == register_number (i.index_reg)))
5006 if (operand_check == check_error)
5008 i.error = invalid_vector_register_set;
5011 if (operand_check != check_none)
5012 as_warn (_("index and destination registers should be distinct"));
5017 /* Check if broadcast is supported by the instruction and is applied
5018 to the memory operand. */
5021 int broadcasted_opnd_size;
5023 /* Check if specified broadcast is supported in this instruction,
5024 and it's applied to memory operand of DWORD or QWORD type,
5025 depending on VecESize. */
5026 if (i.broadcast->type != t->opcode_modifier.broadcast
5027 || !i.types[i.broadcast->operand].bitfield.mem
5028 || (t->opcode_modifier.vecesize == 0
5029 && !i.types[i.broadcast->operand].bitfield.dword
5030 && !i.types[i.broadcast->operand].bitfield.unspecified)
5031 || (t->opcode_modifier.vecesize == 1
5032 && !i.types[i.broadcast->operand].bitfield.qword
5033 && !i.types[i.broadcast->operand].bitfield.unspecified))
5036 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5037 if (i.broadcast->type == BROADCAST_1TO16)
5038 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5039 else if (i.broadcast->type == BROADCAST_1TO8)
5040 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5041 else if (i.broadcast->type == BROADCAST_1TO4)
5042 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5043 else if (i.broadcast->type == BROADCAST_1TO2)
5044 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5048 if ((broadcasted_opnd_size == 256
5049 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5050 || (broadcasted_opnd_size == 512
5051 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5054 i.error = unsupported_broadcast;
5058 /* If broadcast is supported in this instruction, we need to check if
5059 operand of one-element size isn't specified without broadcast. */
5060 else if (t->opcode_modifier.broadcast && i.mem_operands)
5062 /* Find memory operand. */
5063 for (op = 0; op < i.operands; op++)
5064 if (operand_type_check (i.types[op], anymem))
5066 gas_assert (op < i.operands);
5067 /* Check size of the memory operand. */
5068 if ((t->opcode_modifier.vecesize == 0
5069 && i.types[op].bitfield.dword)
5070 || (t->opcode_modifier.vecesize == 1
5071 && i.types[op].bitfield.qword))
5073 i.error = broadcast_needed;
5078 /* Check if requested masking is supported. */
5080 && (!t->opcode_modifier.masking
5082 && t->opcode_modifier.masking == MERGING_MASKING)))
5084 i.error = unsupported_masking;
5088 /* Check if masking is applied to dest operand. */
5089 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5091 i.error = mask_not_on_destination;
5098 if ((i.rounding->type != saeonly
5099 && !t->opcode_modifier.staticrounding)
5100 || (i.rounding->type == saeonly
5101 && (t->opcode_modifier.staticrounding
5102 || !t->opcode_modifier.sae)))
5104 i.error = unsupported_rc_sae;
5107 /* If the instruction has several immediate operands and one of
5108 them is rounding, the rounding operand should be the last
5109 immediate operand. */
5110 if (i.imm_operands > 1
5111 && i.rounding->operand != (int) (i.imm_operands - 1))
5113 i.error = rc_sae_operand_not_last_imm;
5118 /* Check vector Disp8 operand. */
5119 if (t->opcode_modifier.disp8memshift
5120 && i.disp_encoding != disp_encoding_32bit)
5123 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5125 i.memshift = t->opcode_modifier.disp8memshift;
5127 for (op = 0; op < i.operands; op++)
5128 if (operand_type_check (i.types[op], disp)
5129 && i.op[op].disps->X_op == O_constant)
5131 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5133 i.types[op].bitfield.disp8 = 1;
5136 i.types[op].bitfield.disp8 = 0;
5145 /* Check if operands are valid for the instruction. Update VEX
5149 VEX_check_operands (const insn_template *t)
5151 if (i.vec_encoding == vex_encoding_evex)
5153 /* This instruction must be encoded with EVEX prefix. */
5154 if (!t->opcode_modifier.evex)
5156 i.error = unsupported;
5162 if (!t->opcode_modifier.vex)
5164 /* This instruction template doesn't have VEX prefix. */
5165 if (i.vec_encoding != vex_encoding_default)
5167 i.error = unsupported;
5173 /* Only check VEX_Imm4, which must be the first operand. */
5174 if (t->operand_types[0].bitfield.vec_imm4)
5176 if (i.op[0].imms->X_op != O_constant
5177 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5183 /* Turn off Imm8 so that update_imm won't complain. */
5184 i.types[0] = vec_imm4;
5190 static const insn_template *
5191 match_template (char mnem_suffix)
5193 /* Points to template once we've found it. */
5194 const insn_template *t;
5195 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5196 i386_operand_type overlap4;
5197 unsigned int found_reverse_match;
5198 i386_opcode_modifier suffix_check, mnemsuf_check;
5199 i386_operand_type operand_types [MAX_OPERANDS];
5200 int addr_prefix_disp;
5202 unsigned int found_cpu_match;
5203 unsigned int check_register;
5204 enum i386_error specific_error = 0;
5206 #if MAX_OPERANDS != 5
5207 # error "MAX_OPERANDS must be 5."
5210 found_reverse_match = 0;
5211 addr_prefix_disp = -1;
5213 memset (&suffix_check, 0, sizeof (suffix_check));
5214 if (i.suffix == BYTE_MNEM_SUFFIX)
5215 suffix_check.no_bsuf = 1;
5216 else if (i.suffix == WORD_MNEM_SUFFIX)
5217 suffix_check.no_wsuf = 1;
5218 else if (i.suffix == SHORT_MNEM_SUFFIX)
5219 suffix_check.no_ssuf = 1;
5220 else if (i.suffix == LONG_MNEM_SUFFIX)
5221 suffix_check.no_lsuf = 1;
5222 else if (i.suffix == QWORD_MNEM_SUFFIX)
5223 suffix_check.no_qsuf = 1;
5224 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5225 suffix_check.no_ldsuf = 1;
5227 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5230 switch (mnem_suffix)
5232 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5233 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5234 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5235 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5236 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5240 /* Must have right number of operands. */
5241 i.error = number_of_operands_mismatch;
5243 for (t = current_templates->start; t < current_templates->end; t++)
5245 addr_prefix_disp = -1;
5247 if (i.operands != t->operands)
5250 /* Check processor support. */
5251 i.error = unsupported;
5252 found_cpu_match = (cpu_flags_match (t)
5253 == CPU_FLAGS_PERFECT_MATCH);
5254 if (!found_cpu_match)
5257 /* Check old gcc support. */
5258 i.error = old_gcc_only;
5259 if (!old_gcc && t->opcode_modifier.oldgcc)
5262 /* Check AT&T mnemonic. */
5263 i.error = unsupported_with_intel_mnemonic;
5264 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5267 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5268 i.error = unsupported_syntax;
5269 if ((intel_syntax && t->opcode_modifier.attsyntax)
5270 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5271 || (intel64 && t->opcode_modifier.amd64)
5272 || (!intel64 && t->opcode_modifier.intel64))
5275 /* Check the suffix, except for some instructions in intel mode. */
5276 i.error = invalid_instruction_suffix;
5277 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5278 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5279 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5280 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5281 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5282 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5283 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5285 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5286 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5287 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5288 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5289 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5290 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5291 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5294 if (!operand_size_match (t))
5297 for (j = 0; j < MAX_OPERANDS; j++)
5298 operand_types[j] = t->operand_types[j];
5300 /* In general, don't allow 64-bit operands in 32-bit mode. */
5301 if (i.suffix == QWORD_MNEM_SUFFIX
5302 && flag_code != CODE_64BIT
5304 ? (!t->opcode_modifier.ignoresize
5305 && !intel_float_operand (t->name))
5306 : intel_float_operand (t->name) != 2)
5307 && ((!operand_types[0].bitfield.regmmx
5308 && !operand_types[0].bitfield.regsimd)
5309 || (!operand_types[t->operands > 1].bitfield.regmmx
5310 && !operand_types[t->operands > 1].bitfield.regsimd))
5311 && (t->base_opcode != 0x0fc7
5312 || t->extension_opcode != 1 /* cmpxchg8b */))
5315 /* In general, don't allow 32-bit operands on pre-386. */
5316 else if (i.suffix == LONG_MNEM_SUFFIX
5317 && !cpu_arch_flags.bitfield.cpui386
5319 ? (!t->opcode_modifier.ignoresize
5320 && !intel_float_operand (t->name))
5321 : intel_float_operand (t->name) != 2)
5322 && ((!operand_types[0].bitfield.regmmx
5323 && !operand_types[0].bitfield.regsimd)
5324 || (!operand_types[t->operands > 1].bitfield.regmmx
5325 && !operand_types[t->operands > 1].bitfield.regsimd)))
5328 /* Do not verify operands when there are none. */
5332 /* We've found a match; break out of loop. */
5336 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5337 into Disp32/Disp16/Disp32 operand. */
5338 if (i.prefix[ADDR_PREFIX] != 0)
5340 /* There should be only one Disp operand. */
5344 for (j = 0; j < MAX_OPERANDS; j++)
5346 if (operand_types[j].bitfield.disp16)
5348 addr_prefix_disp = j;
5349 operand_types[j].bitfield.disp32 = 1;
5350 operand_types[j].bitfield.disp16 = 0;
5356 for (j = 0; j < MAX_OPERANDS; j++)
5358 if (operand_types[j].bitfield.disp32)
5360 addr_prefix_disp = j;
5361 operand_types[j].bitfield.disp32 = 0;
5362 operand_types[j].bitfield.disp16 = 1;
5368 for (j = 0; j < MAX_OPERANDS; j++)
5370 if (operand_types[j].bitfield.disp64)
5372 addr_prefix_disp = j;
5373 operand_types[j].bitfield.disp64 = 0;
5374 operand_types[j].bitfield.disp32 = 1;
5382 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5383 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5386 /* We check register size if needed. */
5387 check_register = t->opcode_modifier.checkregsize;
5388 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5389 switch (t->operands)
5392 if (!operand_type_match (overlap0, i.types[0]))
5396 /* xchg %eax, %eax is a special case. It is an alias for nop
5397 only in 32bit mode and we can use opcode 0x90. In 64bit
5398 mode, we can't use 0x90 for xchg %eax, %eax since it should
5399 zero-extend %eax to %rax. */
5400 if (flag_code == CODE_64BIT
5401 && t->base_opcode == 0x90
5402 && operand_type_equal (&i.types [0], &acc32)
5403 && operand_type_equal (&i.types [1], &acc32))
5405 /* If we want store form, we reverse direction of operands. */
5406 if (i.dir_encoding == dir_encoding_store
5407 && t->opcode_modifier.d)
5412 /* If we want store form, we skip the current load. */
5413 if (i.dir_encoding == dir_encoding_store
5414 && i.mem_operands == 0
5415 && t->opcode_modifier.load)
5420 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5421 if (!operand_type_match (overlap0, i.types[0])
5422 || !operand_type_match (overlap1, i.types[1])
5424 && !operand_type_register_match (i.types[0],
5429 /* Check if other direction is valid ... */
5430 if (!t->opcode_modifier.d)
5434 /* Try reversing direction of operands. */
5435 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5436 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5437 if (!operand_type_match (overlap0, i.types[0])
5438 || !operand_type_match (overlap1, i.types[1])
5440 && !operand_type_register_match (i.types[0],
5445 /* Does not match either direction. */
5448 /* found_reverse_match holds which of D or FloatR
5450 if (!t->opcode_modifier.d)
5451 found_reverse_match = 0;
5452 else if (operand_types[0].bitfield.tbyte)
5453 found_reverse_match = Opcode_FloatD;
5455 found_reverse_match = Opcode_D;
5456 if (t->opcode_modifier.floatr)
5457 found_reverse_match |= Opcode_FloatR;
5461 /* Found a forward 2 operand match here. */
5462 switch (t->operands)
5465 overlap4 = operand_type_and (i.types[4],
5469 overlap3 = operand_type_and (i.types[3],
5473 overlap2 = operand_type_and (i.types[2],
5478 switch (t->operands)
5481 if (!operand_type_match (overlap4, i.types[4])
5482 || !operand_type_register_match (i.types[3],
5489 if (!operand_type_match (overlap3, i.types[3])
5491 && !operand_type_register_match (i.types[2],
5498 /* Here we make use of the fact that there are no
5499 reverse match 3 operand instructions, and all 3
5500 operand instructions only need to be checked for
5501 register consistency between operands 2 and 3. */
5502 if (!operand_type_match (overlap2, i.types[2])
5504 && !operand_type_register_match (i.types[1],
5512 /* Found either forward/reverse 2, 3 or 4 operand match here:
5513 slip through to break. */
5515 if (!found_cpu_match)
5517 found_reverse_match = 0;
5521 /* Check if vector and VEX operands are valid. */
5522 if (check_VecOperands (t) || VEX_check_operands (t))
5524 specific_error = i.error;
5528 /* We've found a match; break out of loop. */
5532 if (t == current_templates->end)
5534 /* We found no match. */
5535 const char *err_msg;
5536 switch (specific_error ? specific_error : i.error)
5540 case operand_size_mismatch:
5541 err_msg = _("operand size mismatch");
5543 case operand_type_mismatch:
5544 err_msg = _("operand type mismatch");
5546 case register_type_mismatch:
5547 err_msg = _("register type mismatch");
5549 case number_of_operands_mismatch:
5550 err_msg = _("number of operands mismatch");
5552 case invalid_instruction_suffix:
5553 err_msg = _("invalid instruction suffix");
5556 err_msg = _("constant doesn't fit in 4 bits");
5559 err_msg = _("only supported with old gcc");
5561 case unsupported_with_intel_mnemonic:
5562 err_msg = _("unsupported with Intel mnemonic");
5564 case unsupported_syntax:
5565 err_msg = _("unsupported syntax");
5568 as_bad (_("unsupported instruction `%s'"),
5569 current_templates->start->name);
5571 case invalid_vsib_address:
5572 err_msg = _("invalid VSIB address");
5574 case invalid_vector_register_set:
5575 err_msg = _("mask, index, and destination registers must be distinct");
5577 case unsupported_vector_index_register:
5578 err_msg = _("unsupported vector index register");
5580 case unsupported_broadcast:
5581 err_msg = _("unsupported broadcast");
5583 case broadcast_not_on_src_operand:
5584 err_msg = _("broadcast not on source memory operand");
5586 case broadcast_needed:
5587 err_msg = _("broadcast is needed for operand of such type");
5589 case unsupported_masking:
5590 err_msg = _("unsupported masking");
5592 case mask_not_on_destination:
5593 err_msg = _("mask not on destination operand");
5595 case no_default_mask:
5596 err_msg = _("default mask isn't allowed");
5598 case unsupported_rc_sae:
5599 err_msg = _("unsupported static rounding/sae");
5601 case rc_sae_operand_not_last_imm:
5603 err_msg = _("RC/SAE operand must precede immediate operands");
5605 err_msg = _("RC/SAE operand must follow immediate operands");
5607 case invalid_register_operand:
5608 err_msg = _("invalid register operand");
5611 as_bad (_("%s for `%s'"), err_msg,
5612 current_templates->start->name);
5616 if (!quiet_warnings)
5619 && (i.types[0].bitfield.jumpabsolute
5620 != operand_types[0].bitfield.jumpabsolute))
5622 as_warn (_("indirect %s without `*'"), t->name);
5625 if (t->opcode_modifier.isprefix
5626 && t->opcode_modifier.ignoresize)
5628 /* Warn them that a data or address size prefix doesn't
5629 affect assembly of the next line of code. */
5630 as_warn (_("stand-alone `%s' prefix"), t->name);
5634 /* Copy the template we found. */
5637 if (addr_prefix_disp != -1)
5638 i.tm.operand_types[addr_prefix_disp]
5639 = operand_types[addr_prefix_disp];
5641 if (found_reverse_match)
5643 /* If we found a reverse match we must alter the opcode
5644 direction bit. found_reverse_match holds bits to change
5645 (different for int & float insns). */
5647 i.tm.base_opcode ^= found_reverse_match;
5649 i.tm.operand_types[0] = operand_types[1];
5650 i.tm.operand_types[1] = operand_types[0];
5659 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5660 if (i.tm.operand_types[mem_op].bitfield.esseg)
5662 if (i.seg[0] != NULL && i.seg[0] != &es)
5664 as_bad (_("`%s' operand %d must use `%ses' segment"),
5670 /* There's only ever one segment override allowed per instruction.
5671 This instruction possibly has a legal segment override on the
5672 second operand, so copy the segment to where non-string
5673 instructions store it, allowing common code. */
5674 i.seg[0] = i.seg[1];
5676 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5678 if (i.seg[1] != NULL && i.seg[1] != &es)
5680 as_bad (_("`%s' operand %d must use `%ses' segment"),
5691 process_suffix (void)
5693 /* If matched instruction specifies an explicit instruction mnemonic
5695 if (i.tm.opcode_modifier.size16)
5696 i.suffix = WORD_MNEM_SUFFIX;
5697 else if (i.tm.opcode_modifier.size32)
5698 i.suffix = LONG_MNEM_SUFFIX;
5699 else if (i.tm.opcode_modifier.size64)
5700 i.suffix = QWORD_MNEM_SUFFIX;
5701 else if (i.reg_operands)
5703 /* If there's no instruction mnemonic suffix we try to invent one
5704 based on register operands. */
5707 /* We take i.suffix from the last register operand specified,
5708 Destination register type is more significant than source
5709 register type. crc32 in SSE4.2 prefers source register
5711 if (i.tm.base_opcode == 0xf20f38f1)
5713 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5714 i.suffix = WORD_MNEM_SUFFIX;
5715 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5716 i.suffix = LONG_MNEM_SUFFIX;
5717 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5718 i.suffix = QWORD_MNEM_SUFFIX;
5720 else if (i.tm.base_opcode == 0xf20f38f0)
5722 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5723 i.suffix = BYTE_MNEM_SUFFIX;
5730 if (i.tm.base_opcode == 0xf20f38f1
5731 || i.tm.base_opcode == 0xf20f38f0)
5733 /* We have to know the operand size for crc32. */
5734 as_bad (_("ambiguous memory operand size for `%s`"),
5739 for (op = i.operands; --op >= 0;)
5740 if (!i.tm.operand_types[op].bitfield.inoutportreg
5741 && !i.tm.operand_types[op].bitfield.shiftcount)
5743 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5745 i.suffix = BYTE_MNEM_SUFFIX;
5748 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5750 i.suffix = WORD_MNEM_SUFFIX;
5753 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5755 i.suffix = LONG_MNEM_SUFFIX;
5758 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5760 i.suffix = QWORD_MNEM_SUFFIX;
5766 else if (i.suffix == BYTE_MNEM_SUFFIX)
5769 && i.tm.opcode_modifier.ignoresize
5770 && i.tm.opcode_modifier.no_bsuf)
5772 else if (!check_byte_reg ())
5775 else if (i.suffix == LONG_MNEM_SUFFIX)
5778 && i.tm.opcode_modifier.ignoresize
5779 && i.tm.opcode_modifier.no_lsuf)
5781 else if (!check_long_reg ())
5784 else if (i.suffix == QWORD_MNEM_SUFFIX)
5787 && i.tm.opcode_modifier.ignoresize
5788 && i.tm.opcode_modifier.no_qsuf)
5790 else if (!check_qword_reg ())
5793 else if (i.suffix == WORD_MNEM_SUFFIX)
5796 && i.tm.opcode_modifier.ignoresize
5797 && i.tm.opcode_modifier.no_wsuf)
5799 else if (!check_word_reg ())
5802 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5803 || i.suffix == YMMWORD_MNEM_SUFFIX
5804 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5806 /* Skip if the instruction has x/y/z suffix. match_template
5807 should check if it is a valid suffix. */
5809 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5810 /* Do nothing if the instruction is going to ignore the prefix. */
5815 else if (i.tm.opcode_modifier.defaultsize
5817 /* exclude fldenv/frstor/fsave/fstenv */
5818 && i.tm.opcode_modifier.no_ssuf)
5820 i.suffix = stackop_size;
5822 else if (intel_syntax
5824 && (i.tm.operand_types[0].bitfield.jumpabsolute
5825 || i.tm.opcode_modifier.jumpbyte
5826 || i.tm.opcode_modifier.jumpintersegment
5827 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5828 && i.tm.extension_opcode <= 3)))
5833 if (!i.tm.opcode_modifier.no_qsuf)
5835 i.suffix = QWORD_MNEM_SUFFIX;
5840 if (!i.tm.opcode_modifier.no_lsuf)
5841 i.suffix = LONG_MNEM_SUFFIX;
5844 if (!i.tm.opcode_modifier.no_wsuf)
5845 i.suffix = WORD_MNEM_SUFFIX;
5854 if (i.tm.opcode_modifier.w)
5856 as_bad (_("no instruction mnemonic suffix given and "
5857 "no register operands; can't size instruction"));
5863 unsigned int suffixes;
5865 suffixes = !i.tm.opcode_modifier.no_bsuf;
5866 if (!i.tm.opcode_modifier.no_wsuf)
5868 if (!i.tm.opcode_modifier.no_lsuf)
5870 if (!i.tm.opcode_modifier.no_ldsuf)
5872 if (!i.tm.opcode_modifier.no_ssuf)
5874 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5877 /* There are more than suffix matches. */
5878 if (i.tm.opcode_modifier.w
5879 || ((suffixes & (suffixes - 1))
5880 && !i.tm.opcode_modifier.defaultsize
5881 && !i.tm.opcode_modifier.ignoresize))
5883 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5889 /* Change the opcode based on the operand size given by i.suffix;
5890 We don't need to change things for byte insns. */
5893 && i.suffix != BYTE_MNEM_SUFFIX
5894 && i.suffix != XMMWORD_MNEM_SUFFIX
5895 && i.suffix != YMMWORD_MNEM_SUFFIX
5896 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5898 /* It's not a byte, select word/dword operation. */
5899 if (i.tm.opcode_modifier.w)
5901 if (i.tm.opcode_modifier.shortform)
5902 i.tm.base_opcode |= 8;
5904 i.tm.base_opcode |= 1;
5907 /* Now select between word & dword operations via the operand
5908 size prefix, except for instructions that will ignore this
5910 if (i.tm.opcode_modifier.addrprefixop0)
5912 /* The address size override prefix changes the size of the
5914 if ((flag_code == CODE_32BIT
5915 && i.op->regs[0].reg_type.bitfield.word)
5916 || (flag_code != CODE_32BIT
5917 && i.op->regs[0].reg_type.bitfield.dword))
5918 if (!add_prefix (ADDR_PREFIX_OPCODE))
5921 else if (i.suffix != QWORD_MNEM_SUFFIX
5922 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5923 && !i.tm.opcode_modifier.ignoresize
5924 && !i.tm.opcode_modifier.floatmf
5925 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5926 || (flag_code == CODE_64BIT
5927 && i.tm.opcode_modifier.jumpbyte)))
5929 unsigned int prefix = DATA_PREFIX_OPCODE;
5931 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5932 prefix = ADDR_PREFIX_OPCODE;
5934 if (!add_prefix (prefix))
5938 /* Set mode64 for an operand. */
5939 if (i.suffix == QWORD_MNEM_SUFFIX
5940 && flag_code == CODE_64BIT
5941 && !i.tm.opcode_modifier.norex64)
5943 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5944 need rex64. cmpxchg8b is also a special case. */
5945 if (! (i.operands == 2
5946 && i.tm.base_opcode == 0x90
5947 && i.tm.extension_opcode == None
5948 && operand_type_equal (&i.types [0], &acc64)
5949 && operand_type_equal (&i.types [1], &acc64))
5950 && ! (i.operands == 1
5951 && i.tm.base_opcode == 0xfc7
5952 && i.tm.extension_opcode == 1
5953 && !operand_type_check (i.types [0], reg)
5954 && operand_type_check (i.types [0], anymem)))
5958 /* Size floating point instruction. */
5959 if (i.suffix == LONG_MNEM_SUFFIX)
5960 if (i.tm.opcode_modifier.floatmf)
5961 i.tm.base_opcode ^= 4;
5968 check_byte_reg (void)
5972 for (op = i.operands; --op >= 0;)
5974 /* Skip non-register operands. */
5975 if (!i.types[op].bitfield.reg)
5978 /* If this is an eight bit register, it's OK. If it's the 16 or
5979 32 bit version of an eight bit register, we will just use the
5980 low portion, and that's OK too. */
5981 if (i.types[op].bitfield.byte)
5984 /* I/O port address operands are OK too. */
5985 if (i.tm.operand_types[op].bitfield.inoutportreg)
5988 /* crc32 doesn't generate this warning. */
5989 if (i.tm.base_opcode == 0xf20f38f0)
5992 if ((i.types[op].bitfield.word
5993 || i.types[op].bitfield.dword
5994 || i.types[op].bitfield.qword)
5995 && i.op[op].regs->reg_num < 4
5996 /* Prohibit these changes in 64bit mode, since the lowering
5997 would be more complicated. */
5998 && flag_code != CODE_64BIT)
6000 #if REGISTER_WARNINGS
6001 if (!quiet_warnings)
6002 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6004 (i.op[op].regs + (i.types[op].bitfield.word
6005 ? REGNAM_AL - REGNAM_AX
6006 : REGNAM_AL - REGNAM_EAX))->reg_name,
6008 i.op[op].regs->reg_name,
6013 /* Any other register is bad. */
6014 if (i.types[op].bitfield.reg
6015 || i.types[op].bitfield.regmmx
6016 || i.types[op].bitfield.regsimd
6017 || i.types[op].bitfield.sreg2
6018 || i.types[op].bitfield.sreg3
6019 || i.types[op].bitfield.control
6020 || i.types[op].bitfield.debug
6021 || i.types[op].bitfield.test)
6023 as_bad (_("`%s%s' not allowed with `%s%c'"),
6025 i.op[op].regs->reg_name,
6035 check_long_reg (void)
6039 for (op = i.operands; --op >= 0;)
6040 /* Skip non-register operands. */
6041 if (!i.types[op].bitfield.reg)
6043 /* Reject eight bit registers, except where the template requires
6044 them. (eg. movzb) */
6045 else if (i.types[op].bitfield.byte
6046 && (i.tm.operand_types[op].bitfield.reg
6047 || i.tm.operand_types[op].bitfield.acc)
6048 && (i.tm.operand_types[op].bitfield.word
6049 || i.tm.operand_types[op].bitfield.dword))
6051 as_bad (_("`%s%s' not allowed with `%s%c'"),
6053 i.op[op].regs->reg_name,
6058 /* Warn if the e prefix on a general reg is missing. */
6059 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6060 && i.types[op].bitfield.word
6061 && (i.tm.operand_types[op].bitfield.reg
6062 || i.tm.operand_types[op].bitfield.acc)
6063 && i.tm.operand_types[op].bitfield.dword)
6065 /* Prohibit these changes in the 64bit mode, since the
6066 lowering is more complicated. */
6067 if (flag_code == CODE_64BIT)
6069 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6070 register_prefix, i.op[op].regs->reg_name,
6074 #if REGISTER_WARNINGS
6075 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6077 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6078 register_prefix, i.op[op].regs->reg_name, i.suffix);
6081 /* Warn if the r prefix on a general reg is present. */
6082 else if (i.types[op].bitfield.qword
6083 && (i.tm.operand_types[op].bitfield.reg
6084 || i.tm.operand_types[op].bitfield.acc)
6085 && i.tm.operand_types[op].bitfield.dword)
6088 && i.tm.opcode_modifier.toqword
6089 && !i.types[0].bitfield.regsimd)
6091 /* Convert to QWORD. We want REX byte. */
6092 i.suffix = QWORD_MNEM_SUFFIX;
6096 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6097 register_prefix, i.op[op].regs->reg_name,
6106 check_qword_reg (void)
6110 for (op = i.operands; --op >= 0; )
6111 /* Skip non-register operands. */
6112 if (!i.types[op].bitfield.reg)
6114 /* Reject eight bit registers, except where the template requires
6115 them. (eg. movzb) */
6116 else if (i.types[op].bitfield.byte
6117 && (i.tm.operand_types[op].bitfield.reg
6118 || i.tm.operand_types[op].bitfield.acc)
6119 && (i.tm.operand_types[op].bitfield.word
6120 || i.tm.operand_types[op].bitfield.dword))
6122 as_bad (_("`%s%s' not allowed with `%s%c'"),
6124 i.op[op].regs->reg_name,
6129 /* Warn if the r prefix on a general reg is missing. */
6130 else if ((i.types[op].bitfield.word
6131 || i.types[op].bitfield.dword)
6132 && (i.tm.operand_types[op].bitfield.reg
6133 || i.tm.operand_types[op].bitfield.acc)
6134 && i.tm.operand_types[op].bitfield.qword)
6136 /* Prohibit these changes in the 64bit mode, since the
6137 lowering is more complicated. */
6139 && i.tm.opcode_modifier.todword
6140 && !i.types[0].bitfield.regsimd)
6142 /* Convert to DWORD. We don't want REX byte. */
6143 i.suffix = LONG_MNEM_SUFFIX;
6147 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6148 register_prefix, i.op[op].regs->reg_name,
6157 check_word_reg (void)
6160 for (op = i.operands; --op >= 0;)
6161 /* Skip non-register operands. */
6162 if (!i.types[op].bitfield.reg)
6164 /* Reject eight bit registers, except where the template requires
6165 them. (eg. movzb) */
6166 else if (i.types[op].bitfield.byte
6167 && (i.tm.operand_types[op].bitfield.reg
6168 || i.tm.operand_types[op].bitfield.acc)
6169 && (i.tm.operand_types[op].bitfield.word
6170 || i.tm.operand_types[op].bitfield.dword))
6172 as_bad (_("`%s%s' not allowed with `%s%c'"),
6174 i.op[op].regs->reg_name,
6179 /* Warn if the e or r prefix on a general reg is present. */
6180 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6181 && (i.types[op].bitfield.dword
6182 || i.types[op].bitfield.qword)
6183 && (i.tm.operand_types[op].bitfield.reg
6184 || i.tm.operand_types[op].bitfield.acc)
6185 && i.tm.operand_types[op].bitfield.word)
6187 /* Prohibit these changes in the 64bit mode, since the
6188 lowering is more complicated. */
6189 if (flag_code == CODE_64BIT)
6191 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6192 register_prefix, i.op[op].regs->reg_name,
6196 #if REGISTER_WARNINGS
6197 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6199 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6200 register_prefix, i.op[op].regs->reg_name, i.suffix);
6207 update_imm (unsigned int j)
6209 i386_operand_type overlap = i.types[j];
6210 if ((overlap.bitfield.imm8
6211 || overlap.bitfield.imm8s
6212 || overlap.bitfield.imm16
6213 || overlap.bitfield.imm32
6214 || overlap.bitfield.imm32s
6215 || overlap.bitfield.imm64)
6216 && !operand_type_equal (&overlap, &imm8)
6217 && !operand_type_equal (&overlap, &imm8s)
6218 && !operand_type_equal (&overlap, &imm16)
6219 && !operand_type_equal (&overlap, &imm32)
6220 && !operand_type_equal (&overlap, &imm32s)
6221 && !operand_type_equal (&overlap, &imm64))
6225 i386_operand_type temp;
6227 operand_type_set (&temp, 0);
6228 if (i.suffix == BYTE_MNEM_SUFFIX)
6230 temp.bitfield.imm8 = overlap.bitfield.imm8;
6231 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6233 else if (i.suffix == WORD_MNEM_SUFFIX)
6234 temp.bitfield.imm16 = overlap.bitfield.imm16;
6235 else if (i.suffix == QWORD_MNEM_SUFFIX)
6237 temp.bitfield.imm64 = overlap.bitfield.imm64;
6238 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6241 temp.bitfield.imm32 = overlap.bitfield.imm32;
6244 else if (operand_type_equal (&overlap, &imm16_32_32s)
6245 || operand_type_equal (&overlap, &imm16_32)
6246 || operand_type_equal (&overlap, &imm16_32s))
6248 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6253 if (!operand_type_equal (&overlap, &imm8)
6254 && !operand_type_equal (&overlap, &imm8s)
6255 && !operand_type_equal (&overlap, &imm16)
6256 && !operand_type_equal (&overlap, &imm32)
6257 && !operand_type_equal (&overlap, &imm32s)
6258 && !operand_type_equal (&overlap, &imm64))
6260 as_bad (_("no instruction mnemonic suffix given; "
6261 "can't determine immediate size"));
6265 i.types[j] = overlap;
6275 /* Update the first 2 immediate operands. */
6276 n = i.operands > 2 ? 2 : i.operands;
6279 for (j = 0; j < n; j++)
6280 if (update_imm (j) == 0)
6283 /* The 3rd operand can't be immediate operand. */
6284 gas_assert (operand_type_check (i.types[2], imm) == 0);
6291 process_operands (void)
6293 /* Default segment register this instruction will use for memory
6294 accesses. 0 means unknown. This is only for optimizing out
6295 unnecessary segment overrides. */
6296 const seg_entry *default_seg = 0;
6298 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6300 unsigned int dupl = i.operands;
6301 unsigned int dest = dupl - 1;
6304 /* The destination must be an xmm register. */
6305 gas_assert (i.reg_operands
6306 && MAX_OPERANDS > dupl
6307 && operand_type_equal (&i.types[dest], ®xmm));
6309 if (i.tm.operand_types[0].bitfield.acc
6310 && i.tm.operand_types[0].bitfield.xmmword)
6312 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6314 /* Keep xmm0 for instructions with VEX prefix and 3
6316 i.tm.operand_types[0].bitfield.acc = 0;
6317 i.tm.operand_types[0].bitfield.regsimd = 1;
6322 /* We remove the first xmm0 and keep the number of
6323 operands unchanged, which in fact duplicates the
6325 for (j = 1; j < i.operands; j++)
6327 i.op[j - 1] = i.op[j];
6328 i.types[j - 1] = i.types[j];
6329 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6333 else if (i.tm.opcode_modifier.implicit1stxmm0)
6335 gas_assert ((MAX_OPERANDS - 1) > dupl
6336 && (i.tm.opcode_modifier.vexsources
6339 /* Add the implicit xmm0 for instructions with VEX prefix
6341 for (j = i.operands; j > 0; j--)
6343 i.op[j] = i.op[j - 1];
6344 i.types[j] = i.types[j - 1];
6345 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6348 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6349 i.types[0] = regxmm;
6350 i.tm.operand_types[0] = regxmm;
6353 i.reg_operands += 2;
6358 i.op[dupl] = i.op[dest];
6359 i.types[dupl] = i.types[dest];
6360 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6369 i.op[dupl] = i.op[dest];
6370 i.types[dupl] = i.types[dest];
6371 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6374 if (i.tm.opcode_modifier.immext)
6377 else if (i.tm.operand_types[0].bitfield.acc
6378 && i.tm.operand_types[0].bitfield.xmmword)
6382 for (j = 1; j < i.operands; j++)
6384 i.op[j - 1] = i.op[j];
6385 i.types[j - 1] = i.types[j];
6387 /* We need to adjust fields in i.tm since they are used by
6388 build_modrm_byte. */
6389 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6396 else if (i.tm.opcode_modifier.implicitquadgroup)
6398 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6400 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6401 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6402 regnum = register_number (i.op[1].regs);
6403 first_reg_in_group = regnum & ~3;
6404 last_reg_in_group = first_reg_in_group + 3;
6405 if (regnum != first_reg_in_group)
6406 as_warn (_("source register `%s%s' implicitly denotes"
6407 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6408 register_prefix, i.op[1].regs->reg_name,
6409 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6410 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6413 else if (i.tm.opcode_modifier.regkludge)
6415 /* The imul $imm, %reg instruction is converted into
6416 imul $imm, %reg, %reg, and the clr %reg instruction
6417 is converted into xor %reg, %reg. */
6419 unsigned int first_reg_op;
6421 if (operand_type_check (i.types[0], reg))
6425 /* Pretend we saw the extra register operand. */
6426 gas_assert (i.reg_operands == 1
6427 && i.op[first_reg_op + 1].regs == 0);
6428 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6429 i.types[first_reg_op + 1] = i.types[first_reg_op];
6434 if (i.tm.opcode_modifier.shortform)
6436 if (i.types[0].bitfield.sreg2
6437 || i.types[0].bitfield.sreg3)
6439 if (i.tm.base_opcode == POP_SEG_SHORT
6440 && i.op[0].regs->reg_num == 1)
6442 as_bad (_("you can't `pop %scs'"), register_prefix);
6445 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6446 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6451 /* The register or float register operand is in operand
6455 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6456 || operand_type_check (i.types[0], reg))
6460 /* Register goes in low 3 bits of opcode. */
6461 i.tm.base_opcode |= i.op[op].regs->reg_num;
6462 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6464 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6466 /* Warn about some common errors, but press on regardless.
6467 The first case can be generated by gcc (<= 2.8.1). */
6468 if (i.operands == 2)
6470 /* Reversed arguments on faddp, fsubp, etc. */
6471 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6472 register_prefix, i.op[!intel_syntax].regs->reg_name,
6473 register_prefix, i.op[intel_syntax].regs->reg_name);
6477 /* Extraneous `l' suffix on fp insn. */
6478 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6479 register_prefix, i.op[0].regs->reg_name);
6484 else if (i.tm.opcode_modifier.modrm)
6486 /* The opcode is completed (modulo i.tm.extension_opcode which
6487 must be put into the modrm byte). Now, we make the modrm and
6488 index base bytes based on all the info we've collected. */
6490 default_seg = build_modrm_byte ();
6492 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6496 else if (i.tm.opcode_modifier.isstring)
6498 /* For the string instructions that allow a segment override
6499 on one of their operands, the default segment is ds. */
6503 if (i.tm.base_opcode == 0x8d /* lea */
6506 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6508 /* If a segment was explicitly specified, and the specified segment
6509 is not the default, use an opcode prefix to select it. If we
6510 never figured out what the default segment is, then default_seg
6511 will be zero at this point, and the specified segment prefix will
6513 if ((i.seg[0]) && (i.seg[0] != default_seg))
6515 if (!add_prefix (i.seg[0]->seg_prefix))
6521 static const seg_entry *
6522 build_modrm_byte (void)
6524 const seg_entry *default_seg = 0;
6525 unsigned int source, dest;
6528 /* The first operand of instructions with VEX prefix and 3 sources
6529 must be VEX_Imm4. */
6530 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6533 unsigned int nds, reg_slot;
6536 if (i.tm.opcode_modifier.veximmext
6537 && i.tm.opcode_modifier.immext)
6539 dest = i.operands - 2;
6540 gas_assert (dest == 3);
6543 dest = i.operands - 1;
6546 /* There are 2 kinds of instructions:
6547 1. 5 operands: 4 register operands or 3 register operands
6548 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6549 VexW0 or VexW1. The destination must be either XMM, YMM or
6551 2. 4 operands: 4 register operands or 3 register operands
6552 plus 1 memory operand, VexXDS, and VexImmExt */
6553 gas_assert ((i.reg_operands == 4
6554 || (i.reg_operands == 3 && i.mem_operands == 1))
6555 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6556 && (i.tm.opcode_modifier.veximmext
6557 || (i.imm_operands == 1
6558 && i.types[0].bitfield.vec_imm4
6559 && (i.tm.opcode_modifier.vexw == VEXW0
6560 || i.tm.opcode_modifier.vexw == VEXW1)
6561 && i.tm.operand_types[dest].bitfield.regsimd)));
6563 if (i.imm_operands == 0)
6565 /* When there is no immediate operand, generate an 8bit
6566 immediate operand to encode the first operand. */
6567 exp = &im_expressions[i.imm_operands++];
6568 i.op[i.operands].imms = exp;
6569 i.types[i.operands] = imm8;
6571 /* If VexW1 is set, the first operand is the source and
6572 the second operand is encoded in the immediate operand. */
6573 if (i.tm.opcode_modifier.vexw == VEXW1)
6584 /* FMA swaps REG and NDS. */
6585 if (i.tm.cpu_flags.bitfield.cpufma)
6593 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6594 exp->X_op = O_constant;
6595 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6596 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6600 unsigned int imm_slot;
6602 if (i.tm.opcode_modifier.vexw == VEXW0)
6604 /* If VexW0 is set, the third operand is the source and
6605 the second operand is encoded in the immediate
6612 /* VexW1 is set, the second operand is the source and
6613 the third operand is encoded in the immediate
6619 if (i.tm.opcode_modifier.immext)
6621 /* When ImmExt is set, the immediate byte is the last
6623 imm_slot = i.operands - 1;
6631 /* Turn on Imm8 so that output_imm will generate it. */
6632 i.types[imm_slot].bitfield.imm8 = 1;
6635 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6636 i.op[imm_slot].imms->X_add_number
6637 |= register_number (i.op[reg_slot].regs) << 4;
6638 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6641 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6642 i.vex.register_specifier = i.op[nds].regs;
6647 /* i.reg_operands MUST be the number of real register operands;
6648 implicit registers do not count. If there are 3 register
6649 operands, it must be a instruction with VexNDS. For a
6650 instruction with VexNDD, the destination register is encoded
6651 in VEX prefix. If there are 4 register operands, it must be
6652 a instruction with VEX prefix and 3 sources. */
6653 if (i.mem_operands == 0
6654 && ((i.reg_operands == 2
6655 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6656 || (i.reg_operands == 3
6657 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6658 || (i.reg_operands == 4 && vex_3_sources)))
6666 /* When there are 3 operands, one of them may be immediate,
6667 which may be the first or the last operand. Otherwise,
6668 the first operand must be shift count register (cl) or it
6669 is an instruction with VexNDS. */
6670 gas_assert (i.imm_operands == 1
6671 || (i.imm_operands == 0
6672 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6673 || i.types[0].bitfield.shiftcount)));
6674 if (operand_type_check (i.types[0], imm)
6675 || i.types[0].bitfield.shiftcount)
6681 /* When there are 4 operands, the first two must be 8bit
6682 immediate operands. The source operand will be the 3rd
6685 For instructions with VexNDS, if the first operand
6686 an imm8, the source operand is the 2nd one. If the last
6687 operand is imm8, the source operand is the first one. */
6688 gas_assert ((i.imm_operands == 2
6689 && i.types[0].bitfield.imm8
6690 && i.types[1].bitfield.imm8)
6691 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6692 && i.imm_operands == 1
6693 && (i.types[0].bitfield.imm8
6694 || i.types[i.operands - 1].bitfield.imm8
6696 if (i.imm_operands == 2)
6700 if (i.types[0].bitfield.imm8)
6707 if (i.tm.opcode_modifier.evex)
6709 /* For EVEX instructions, when there are 5 operands, the
6710 first one must be immediate operand. If the second one
6711 is immediate operand, the source operand is the 3th
6712 one. If the last one is immediate operand, the source
6713 operand is the 2nd one. */
6714 gas_assert (i.imm_operands == 2
6715 && i.tm.opcode_modifier.sae
6716 && operand_type_check (i.types[0], imm));
6717 if (operand_type_check (i.types[1], imm))
6719 else if (operand_type_check (i.types[4], imm))
6733 /* RC/SAE operand could be between DEST and SRC. That happens
6734 when one operand is GPR and the other one is XMM/YMM/ZMM
6736 if (i.rounding && i.rounding->operand == (int) dest)
6739 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6741 /* For instructions with VexNDS, the register-only source
6742 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6743 register. It is encoded in VEX prefix. We need to
6744 clear RegMem bit before calling operand_type_equal. */
6746 i386_operand_type op;
6749 /* Check register-only source operand when two source
6750 operands are swapped. */
6751 if (!i.tm.operand_types[source].bitfield.baseindex
6752 && i.tm.operand_types[dest].bitfield.baseindex)
6760 op = i.tm.operand_types[vvvv];
6761 op.bitfield.regmem = 0;
6762 if ((dest + 1) >= i.operands
6763 || ((!op.bitfield.reg
6764 || (!op.bitfield.dword && !op.bitfield.qword))
6765 && !op.bitfield.regsimd
6766 && !operand_type_equal (&op, ®mask)))
6768 i.vex.register_specifier = i.op[vvvv].regs;
6774 /* One of the register operands will be encoded in the i.tm.reg
6775 field, the other in the combined i.tm.mode and i.tm.regmem
6776 fields. If no form of this instruction supports a memory
6777 destination operand, then we assume the source operand may
6778 sometimes be a memory operand and so we need to store the
6779 destination in the i.rm.reg field. */
6780 if (!i.tm.operand_types[dest].bitfield.regmem
6781 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6783 i.rm.reg = i.op[dest].regs->reg_num;
6784 i.rm.regmem = i.op[source].regs->reg_num;
6785 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6787 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6789 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6791 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6796 i.rm.reg = i.op[source].regs->reg_num;
6797 i.rm.regmem = i.op[dest].regs->reg_num;
6798 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6800 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6802 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6804 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6807 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6809 if (!i.types[0].bitfield.control
6810 && !i.types[1].bitfield.control)
6812 i.rex &= ~(REX_R | REX_B);
6813 add_prefix (LOCK_PREFIX_OPCODE);
6817 { /* If it's not 2 reg operands... */
6822 unsigned int fake_zero_displacement = 0;
6825 for (op = 0; op < i.operands; op++)
6826 if (operand_type_check (i.types[op], anymem))
6828 gas_assert (op < i.operands);
6830 if (i.tm.opcode_modifier.vecsib)
6832 if (i.index_reg->reg_num == RegEiz
6833 || i.index_reg->reg_num == RegRiz)
6836 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6839 i.sib.base = NO_BASE_REGISTER;
6840 i.sib.scale = i.log2_scale_factor;
6841 i.types[op].bitfield.disp8 = 0;
6842 i.types[op].bitfield.disp16 = 0;
6843 i.types[op].bitfield.disp64 = 0;
6844 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6846 /* Must be 32 bit */
6847 i.types[op].bitfield.disp32 = 1;
6848 i.types[op].bitfield.disp32s = 0;
6852 i.types[op].bitfield.disp32 = 0;
6853 i.types[op].bitfield.disp32s = 1;
6856 i.sib.index = i.index_reg->reg_num;
6857 if ((i.index_reg->reg_flags & RegRex) != 0)
6859 if ((i.index_reg->reg_flags & RegVRex) != 0)
6865 if (i.base_reg == 0)
6868 if (!i.disp_operands)
6869 fake_zero_displacement = 1;
6870 if (i.index_reg == 0)
6872 i386_operand_type newdisp;
6874 gas_assert (!i.tm.opcode_modifier.vecsib);
6875 /* Operand is just <disp> */
6876 if (flag_code == CODE_64BIT)
6878 /* 64bit mode overwrites the 32bit absolute
6879 addressing by RIP relative addressing and
6880 absolute addressing is encoded by one of the
6881 redundant SIB forms. */
6882 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6883 i.sib.base = NO_BASE_REGISTER;
6884 i.sib.index = NO_INDEX_REGISTER;
6885 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6887 else if ((flag_code == CODE_16BIT)
6888 ^ (i.prefix[ADDR_PREFIX] != 0))
6890 i.rm.regmem = NO_BASE_REGISTER_16;
6895 i.rm.regmem = NO_BASE_REGISTER;
6898 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6899 i.types[op] = operand_type_or (i.types[op], newdisp);
6901 else if (!i.tm.opcode_modifier.vecsib)
6903 /* !i.base_reg && i.index_reg */
6904 if (i.index_reg->reg_num == RegEiz
6905 || i.index_reg->reg_num == RegRiz)
6906 i.sib.index = NO_INDEX_REGISTER;
6908 i.sib.index = i.index_reg->reg_num;
6909 i.sib.base = NO_BASE_REGISTER;
6910 i.sib.scale = i.log2_scale_factor;
6911 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6912 i.types[op].bitfield.disp8 = 0;
6913 i.types[op].bitfield.disp16 = 0;
6914 i.types[op].bitfield.disp64 = 0;
6915 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6917 /* Must be 32 bit */
6918 i.types[op].bitfield.disp32 = 1;
6919 i.types[op].bitfield.disp32s = 0;
6923 i.types[op].bitfield.disp32 = 0;
6924 i.types[op].bitfield.disp32s = 1;
6926 if ((i.index_reg->reg_flags & RegRex) != 0)
6930 /* RIP addressing for 64bit mode. */
6931 else if (i.base_reg->reg_num == RegRip ||
6932 i.base_reg->reg_num == RegEip)
6934 gas_assert (!i.tm.opcode_modifier.vecsib);
6935 i.rm.regmem = NO_BASE_REGISTER;
6936 i.types[op].bitfield.disp8 = 0;
6937 i.types[op].bitfield.disp16 = 0;
6938 i.types[op].bitfield.disp32 = 0;
6939 i.types[op].bitfield.disp32s = 1;
6940 i.types[op].bitfield.disp64 = 0;
6941 i.flags[op] |= Operand_PCrel;
6942 if (! i.disp_operands)
6943 fake_zero_displacement = 1;
6945 else if (i.base_reg->reg_type.bitfield.word)
6947 gas_assert (!i.tm.opcode_modifier.vecsib);
6948 switch (i.base_reg->reg_num)
6951 if (i.index_reg == 0)
6953 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6954 i.rm.regmem = i.index_reg->reg_num - 6;
6958 if (i.index_reg == 0)
6961 if (operand_type_check (i.types[op], disp) == 0)
6963 /* fake (%bp) into 0(%bp) */
6964 i.types[op].bitfield.disp8 = 1;
6965 fake_zero_displacement = 1;
6968 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6969 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6971 default: /* (%si) -> 4 or (%di) -> 5 */
6972 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6974 i.rm.mode = mode_from_disp_size (i.types[op]);
6976 else /* i.base_reg and 32/64 bit mode */
6978 if (flag_code == CODE_64BIT
6979 && operand_type_check (i.types[op], disp))
6981 i.types[op].bitfield.disp16 = 0;
6982 i.types[op].bitfield.disp64 = 0;
6983 if (i.prefix[ADDR_PREFIX] == 0)
6985 i.types[op].bitfield.disp32 = 0;
6986 i.types[op].bitfield.disp32s = 1;
6990 i.types[op].bitfield.disp32 = 1;
6991 i.types[op].bitfield.disp32s = 0;
6995 if (!i.tm.opcode_modifier.vecsib)
6996 i.rm.regmem = i.base_reg->reg_num;
6997 if ((i.base_reg->reg_flags & RegRex) != 0)
6999 i.sib.base = i.base_reg->reg_num;
7000 /* x86-64 ignores REX prefix bit here to avoid decoder
7002 if (!(i.base_reg->reg_flags & RegRex)
7003 && (i.base_reg->reg_num == EBP_REG_NUM
7004 || i.base_reg->reg_num == ESP_REG_NUM))
7006 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7008 fake_zero_displacement = 1;
7009 i.types[op].bitfield.disp8 = 1;
7011 i.sib.scale = i.log2_scale_factor;
7012 if (i.index_reg == 0)
7014 gas_assert (!i.tm.opcode_modifier.vecsib);
7015 /* <disp>(%esp) becomes two byte modrm with no index
7016 register. We've already stored the code for esp
7017 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7018 Any base register besides %esp will not use the
7019 extra modrm byte. */
7020 i.sib.index = NO_INDEX_REGISTER;
7022 else if (!i.tm.opcode_modifier.vecsib)
7024 if (i.index_reg->reg_num == RegEiz
7025 || i.index_reg->reg_num == RegRiz)
7026 i.sib.index = NO_INDEX_REGISTER;
7028 i.sib.index = i.index_reg->reg_num;
7029 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7030 if ((i.index_reg->reg_flags & RegRex) != 0)
7035 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7036 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7040 if (!fake_zero_displacement
7044 fake_zero_displacement = 1;
7045 if (i.disp_encoding == disp_encoding_8bit)
7046 i.types[op].bitfield.disp8 = 1;
7048 i.types[op].bitfield.disp32 = 1;
7050 i.rm.mode = mode_from_disp_size (i.types[op]);
7054 if (fake_zero_displacement)
7056 /* Fakes a zero displacement assuming that i.types[op]
7057 holds the correct displacement size. */
7060 gas_assert (i.op[op].disps == 0);
7061 exp = &disp_expressions[i.disp_operands++];
7062 i.op[op].disps = exp;
7063 exp->X_op = O_constant;
7064 exp->X_add_number = 0;
7065 exp->X_add_symbol = (symbolS *) 0;
7066 exp->X_op_symbol = (symbolS *) 0;
7074 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7076 if (operand_type_check (i.types[0], imm))
7077 i.vex.register_specifier = NULL;
7080 /* VEX.vvvv encodes one of the sources when the first
7081 operand is not an immediate. */
7082 if (i.tm.opcode_modifier.vexw == VEXW0)
7083 i.vex.register_specifier = i.op[0].regs;
7085 i.vex.register_specifier = i.op[1].regs;
7088 /* Destination is a XMM register encoded in the ModRM.reg
7090 i.rm.reg = i.op[2].regs->reg_num;
7091 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7094 /* ModRM.rm and VEX.B encodes the other source. */
7095 if (!i.mem_operands)
7099 if (i.tm.opcode_modifier.vexw == VEXW0)
7100 i.rm.regmem = i.op[1].regs->reg_num;
7102 i.rm.regmem = i.op[0].regs->reg_num;
7104 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7108 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7110 i.vex.register_specifier = i.op[2].regs;
7111 if (!i.mem_operands)
7114 i.rm.regmem = i.op[1].regs->reg_num;
7115 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7119 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7120 (if any) based on i.tm.extension_opcode. Again, we must be
7121 careful to make sure that segment/control/debug/test/MMX
7122 registers are coded into the i.rm.reg field. */
7123 else if (i.reg_operands)
7126 unsigned int vex_reg = ~0;
7128 for (op = 0; op < i.operands; op++)
7129 if (i.types[op].bitfield.reg
7130 || i.types[op].bitfield.regmmx
7131 || i.types[op].bitfield.regsimd
7132 || i.types[op].bitfield.regbnd
7133 || i.types[op].bitfield.regmask
7134 || i.types[op].bitfield.sreg2
7135 || i.types[op].bitfield.sreg3
7136 || i.types[op].bitfield.control
7137 || i.types[op].bitfield.debug
7138 || i.types[op].bitfield.test)
7143 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7145 /* For instructions with VexNDS, the register-only
7146 source operand is encoded in VEX prefix. */
7147 gas_assert (mem != (unsigned int) ~0);
7152 gas_assert (op < i.operands);
7156 /* Check register-only source operand when two source
7157 operands are swapped. */
7158 if (!i.tm.operand_types[op].bitfield.baseindex
7159 && i.tm.operand_types[op + 1].bitfield.baseindex)
7163 gas_assert (mem == (vex_reg + 1)
7164 && op < i.operands);
7169 gas_assert (vex_reg < i.operands);
7173 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7175 /* For instructions with VexNDD, the register destination
7176 is encoded in VEX prefix. */
7177 if (i.mem_operands == 0)
7179 /* There is no memory operand. */
7180 gas_assert ((op + 2) == i.operands);
7185 /* There are only 2 operands. */
7186 gas_assert (op < 2 && i.operands == 2);
7191 gas_assert (op < i.operands);
7193 if (vex_reg != (unsigned int) ~0)
7195 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7197 if ((!type->bitfield.reg
7198 || (!type->bitfield.dword && !type->bitfield.qword))
7199 && !type->bitfield.regsimd
7200 && !operand_type_equal (type, ®mask))
7203 i.vex.register_specifier = i.op[vex_reg].regs;
7206 /* Don't set OP operand twice. */
7209 /* If there is an extension opcode to put here, the
7210 register number must be put into the regmem field. */
7211 if (i.tm.extension_opcode != None)
7213 i.rm.regmem = i.op[op].regs->reg_num;
7214 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7216 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7221 i.rm.reg = i.op[op].regs->reg_num;
7222 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7224 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7229 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7230 must set it to 3 to indicate this is a register operand
7231 in the regmem field. */
7232 if (!i.mem_operands)
7236 /* Fill in i.rm.reg field with extension opcode (if any). */
7237 if (i.tm.extension_opcode != None)
7238 i.rm.reg = i.tm.extension_opcode;
7244 output_branch (void)
7250 relax_substateT subtype;
7254 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7255 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7258 if (i.prefix[DATA_PREFIX] != 0)
7264 /* Pentium4 branch hints. */
7265 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7266 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7271 if (i.prefix[REX_PREFIX] != 0)
7277 /* BND prefixed jump. */
7278 if (i.prefix[BND_PREFIX] != 0)
7280 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7284 if (i.prefixes != 0 && !intel_syntax)
7285 as_warn (_("skipping prefixes on this instruction"));
7287 /* It's always a symbol; End frag & setup for relax.
7288 Make sure there is enough room in this frag for the largest
7289 instruction we may generate in md_convert_frag. This is 2
7290 bytes for the opcode and room for the prefix and largest
7292 frag_grow (prefix + 2 + 4);
7293 /* Prefix and 1 opcode byte go in fr_fix. */
7294 p = frag_more (prefix + 1);
7295 if (i.prefix[DATA_PREFIX] != 0)
7296 *p++ = DATA_PREFIX_OPCODE;
7297 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7298 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7299 *p++ = i.prefix[SEG_PREFIX];
7300 if (i.prefix[REX_PREFIX] != 0)
7301 *p++ = i.prefix[REX_PREFIX];
7302 *p = i.tm.base_opcode;
7304 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7305 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7306 else if (cpu_arch_flags.bitfield.cpui386)
7307 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7309 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7312 sym = i.op[0].disps->X_add_symbol;
7313 off = i.op[0].disps->X_add_number;
7315 if (i.op[0].disps->X_op != O_constant
7316 && i.op[0].disps->X_op != O_symbol)
7318 /* Handle complex expressions. */
7319 sym = make_expr_symbol (i.op[0].disps);
7323 /* 1 possible extra opcode + 4 byte displacement go in var part.
7324 Pass reloc in fr_var. */
7325 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7329 /* Return TRUE iff PLT32 relocation should be used for branching to
7333 need_plt32_p (symbolS *s)
7335 /* PLT32 relocation is ELF only. */
7339 /* Since there is no need to prepare for PLT branch on x86-64, we
7340 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7341 be used as a marker for 32-bit PC-relative branches. */
7345 /* Weak or undefined symbol need PLT32 relocation. */
7346 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7349 /* Non-global symbol doesn't need PLT32 relocation. */
7350 if (! S_IS_EXTERNAL (s))
7353 /* Other global symbols need PLT32 relocation. NB: Symbol with
7354 non-default visibilities are treated as normal global symbol
7355 so that PLT32 relocation can be used as a marker for 32-bit
7356 PC-relative branches. It is useful for linker relaxation. */
7367 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7369 if (i.tm.opcode_modifier.jumpbyte)
7371 /* This is a loop or jecxz type instruction. */
7373 if (i.prefix[ADDR_PREFIX] != 0)
7375 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7378 /* Pentium4 branch hints. */
7379 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7380 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7382 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7391 if (flag_code == CODE_16BIT)
7394 if (i.prefix[DATA_PREFIX] != 0)
7396 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7406 if (i.prefix[REX_PREFIX] != 0)
7408 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7412 /* BND prefixed jump. */
7413 if (i.prefix[BND_PREFIX] != 0)
7415 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7419 if (i.prefixes != 0 && !intel_syntax)
7420 as_warn (_("skipping prefixes on this instruction"));
7422 p = frag_more (i.tm.opcode_length + size);
7423 switch (i.tm.opcode_length)
7426 *p++ = i.tm.base_opcode >> 8;
7429 *p++ = i.tm.base_opcode;
7435 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7437 && jump_reloc == NO_RELOC
7438 && need_plt32_p (i.op[0].disps->X_add_symbol))
7439 jump_reloc = BFD_RELOC_X86_64_PLT32;
7442 jump_reloc = reloc (size, 1, 1, jump_reloc);
7444 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7445 i.op[0].disps, 1, jump_reloc);
7447 /* All jumps handled here are signed, but don't use a signed limit
7448 check for 32 and 16 bit jumps as we want to allow wrap around at
7449 4G and 64k respectively. */
7451 fixP->fx_signed = 1;
7455 output_interseg_jump (void)
7463 if (flag_code == CODE_16BIT)
7467 if (i.prefix[DATA_PREFIX] != 0)
7473 if (i.prefix[REX_PREFIX] != 0)
7483 if (i.prefixes != 0 && !intel_syntax)
7484 as_warn (_("skipping prefixes on this instruction"));
7486 /* 1 opcode; 2 segment; offset */
7487 p = frag_more (prefix + 1 + 2 + size);
7489 if (i.prefix[DATA_PREFIX] != 0)
7490 *p++ = DATA_PREFIX_OPCODE;
7492 if (i.prefix[REX_PREFIX] != 0)
7493 *p++ = i.prefix[REX_PREFIX];
7495 *p++ = i.tm.base_opcode;
7496 if (i.op[1].imms->X_op == O_constant)
7498 offsetT n = i.op[1].imms->X_add_number;
7501 && !fits_in_unsigned_word (n)
7502 && !fits_in_signed_word (n))
7504 as_bad (_("16-bit jump out of range"));
7507 md_number_to_chars (p, n, size);
7510 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7511 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7512 if (i.op[0].imms->X_op != O_constant)
7513 as_bad (_("can't handle non absolute segment in `%s'"),
7515 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7521 fragS *insn_start_frag;
7522 offsetT insn_start_off;
7524 /* Tie dwarf2 debug info to the address at the start of the insn.
7525 We can't do this after the insn has been output as the current
7526 frag may have been closed off. eg. by frag_var. */
7527 dwarf2_emit_insn (0);
7529 insn_start_frag = frag_now;
7530 insn_start_off = frag_now_fix ();
7533 if (i.tm.opcode_modifier.jump)
7535 else if (i.tm.opcode_modifier.jumpbyte
7536 || i.tm.opcode_modifier.jumpdword)
7538 else if (i.tm.opcode_modifier.jumpintersegment)
7539 output_interseg_jump ();
7542 /* Output normal instructions here. */
7546 unsigned int prefix;
7549 && i.tm.base_opcode == 0xfae
7551 && i.imm_operands == 1
7552 && (i.op[0].imms->X_add_number == 0xe8
7553 || i.op[0].imms->X_add_number == 0xf0
7554 || i.op[0].imms->X_add_number == 0xf8))
7556 /* Encode lfence, mfence, and sfence as
7557 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7558 offsetT val = 0x240483f0ULL;
7560 md_number_to_chars (p, val, 5);
7564 /* Some processors fail on LOCK prefix. This options makes
7565 assembler ignore LOCK prefix and serves as a workaround. */
7566 if (omit_lock_prefix)
7568 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7570 i.prefix[LOCK_PREFIX] = 0;
7573 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7574 don't need the explicit prefix. */
7575 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7577 switch (i.tm.opcode_length)
7580 if (i.tm.base_opcode & 0xff000000)
7582 prefix = (i.tm.base_opcode >> 24) & 0xff;
7587 if ((i.tm.base_opcode & 0xff0000) != 0)
7589 prefix = (i.tm.base_opcode >> 16) & 0xff;
7590 if (i.tm.cpu_flags.bitfield.cpupadlock)
7593 if (prefix != REPE_PREFIX_OPCODE
7594 || (i.prefix[REP_PREFIX]
7595 != REPE_PREFIX_OPCODE))
7596 add_prefix (prefix);
7599 add_prefix (prefix);
7605 /* Check for pseudo prefixes. */
7606 as_bad_where (insn_start_frag->fr_file,
7607 insn_start_frag->fr_line,
7608 _("pseudo prefix without instruction"));
7614 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7615 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7616 R_X86_64_GOTTPOFF relocation so that linker can safely
7617 perform IE->LE optimization. */
7618 if (x86_elf_abi == X86_64_X32_ABI
7620 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7621 && i.prefix[REX_PREFIX] == 0)
7622 add_prefix (REX_OPCODE);
7625 /* The prefix bytes. */
7626 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7628 FRAG_APPEND_1_CHAR (*q);
7632 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7637 /* REX byte is encoded in VEX prefix. */
7641 FRAG_APPEND_1_CHAR (*q);
7644 /* There should be no other prefixes for instructions
7649 /* For EVEX instructions i.vrex should become 0 after
7650 build_evex_prefix. For VEX instructions upper 16 registers
7651 aren't available, so VREX should be 0. */
7654 /* Now the VEX prefix. */
7655 p = frag_more (i.vex.length);
7656 for (j = 0; j < i.vex.length; j++)
7657 p[j] = i.vex.bytes[j];
7660 /* Now the opcode; be careful about word order here! */
7661 if (i.tm.opcode_length == 1)
7663 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7667 switch (i.tm.opcode_length)
7671 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7672 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7676 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7686 /* Put out high byte first: can't use md_number_to_chars! */
7687 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7688 *p = i.tm.base_opcode & 0xff;
7691 /* Now the modrm byte and sib byte (if present). */
7692 if (i.tm.opcode_modifier.modrm)
7694 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7697 /* If i.rm.regmem == ESP (4)
7698 && i.rm.mode != (Register mode)
7700 ==> need second modrm byte. */
7701 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7703 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7704 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7706 | i.sib.scale << 6));
7709 if (i.disp_operands)
7710 output_disp (insn_start_frag, insn_start_off);
7713 output_imm (insn_start_frag, insn_start_off);
7719 pi ("" /*line*/, &i);
7721 #endif /* DEBUG386 */
7724 /* Return the size of the displacement operand N. */
7727 disp_size (unsigned int n)
7731 if (i.types[n].bitfield.disp64)
7733 else if (i.types[n].bitfield.disp8)
7735 else if (i.types[n].bitfield.disp16)
7740 /* Return the size of the immediate operand N. */
7743 imm_size (unsigned int n)
7746 if (i.types[n].bitfield.imm64)
7748 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7750 else if (i.types[n].bitfield.imm16)
7756 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7761 for (n = 0; n < i.operands; n++)
7763 if (operand_type_check (i.types[n], disp))
7765 if (i.op[n].disps->X_op == O_constant)
7767 int size = disp_size (n);
7768 offsetT val = i.op[n].disps->X_add_number;
7770 val = offset_in_range (val >> i.memshift, size);
7771 p = frag_more (size);
7772 md_number_to_chars (p, val, size);
7776 enum bfd_reloc_code_real reloc_type;
7777 int size = disp_size (n);
7778 int sign = i.types[n].bitfield.disp32s;
7779 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7782 /* We can't have 8 bit displacement here. */
7783 gas_assert (!i.types[n].bitfield.disp8);
7785 /* The PC relative address is computed relative
7786 to the instruction boundary, so in case immediate
7787 fields follows, we need to adjust the value. */
7788 if (pcrel && i.imm_operands)
7793 for (n1 = 0; n1 < i.operands; n1++)
7794 if (operand_type_check (i.types[n1], imm))
7796 /* Only one immediate is allowed for PC
7797 relative address. */
7798 gas_assert (sz == 0);
7800 i.op[n].disps->X_add_number -= sz;
7802 /* We should find the immediate. */
7803 gas_assert (sz != 0);
7806 p = frag_more (size);
7807 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7809 && GOT_symbol == i.op[n].disps->X_add_symbol
7810 && (((reloc_type == BFD_RELOC_32
7811 || reloc_type == BFD_RELOC_X86_64_32S
7812 || (reloc_type == BFD_RELOC_64
7814 && (i.op[n].disps->X_op == O_symbol
7815 || (i.op[n].disps->X_op == O_add
7816 && ((symbol_get_value_expression
7817 (i.op[n].disps->X_op_symbol)->X_op)
7819 || reloc_type == BFD_RELOC_32_PCREL))
7823 if (insn_start_frag == frag_now)
7824 add = (p - frag_now->fr_literal) - insn_start_off;
7829 add = insn_start_frag->fr_fix - insn_start_off;
7830 for (fr = insn_start_frag->fr_next;
7831 fr && fr != frag_now; fr = fr->fr_next)
7833 add += p - frag_now->fr_literal;
7838 reloc_type = BFD_RELOC_386_GOTPC;
7839 i.op[n].imms->X_add_number += add;
7841 else if (reloc_type == BFD_RELOC_64)
7842 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7844 /* Don't do the adjustment for x86-64, as there
7845 the pcrel addressing is relative to the _next_
7846 insn, and that is taken care of in other code. */
7847 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7849 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7850 size, i.op[n].disps, pcrel,
7852 /* Check for "call/jmp *mem", "mov mem, %reg",
7853 "test %reg, mem" and "binop mem, %reg" where binop
7854 is one of adc, add, and, cmp, or, sbb, sub, xor
7855 instructions. Always generate R_386_GOT32X for
7856 "sym*GOT" operand in 32-bit mode. */
7857 if ((generate_relax_relocations
7860 && i.rm.regmem == 5))
7862 || (i.rm.mode == 0 && i.rm.regmem == 5))
7863 && ((i.operands == 1
7864 && i.tm.base_opcode == 0xff
7865 && (i.rm.reg == 2 || i.rm.reg == 4))
7867 && (i.tm.base_opcode == 0x8b
7868 || i.tm.base_opcode == 0x85
7869 || (i.tm.base_opcode & 0xc7) == 0x03))))
7873 fixP->fx_tcbit = i.rex != 0;
7875 && (i.base_reg->reg_num == RegRip
7876 || i.base_reg->reg_num == RegEip))
7877 fixP->fx_tcbit2 = 1;
7880 fixP->fx_tcbit2 = 1;
7888 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7893 for (n = 0; n < i.operands; n++)
7895 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7896 if (i.rounding && (int) n == i.rounding->operand)
7899 if (operand_type_check (i.types[n], imm))
7901 if (i.op[n].imms->X_op == O_constant)
7903 int size = imm_size (n);
7906 val = offset_in_range (i.op[n].imms->X_add_number,
7908 p = frag_more (size);
7909 md_number_to_chars (p, val, size);
7913 /* Not absolute_section.
7914 Need a 32-bit fixup (don't support 8bit
7915 non-absolute imms). Try to support other
7917 enum bfd_reloc_code_real reloc_type;
7918 int size = imm_size (n);
7921 if (i.types[n].bitfield.imm32s
7922 && (i.suffix == QWORD_MNEM_SUFFIX
7923 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7928 p = frag_more (size);
7929 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7931 /* This is tough to explain. We end up with this one if we
7932 * have operands that look like
7933 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7934 * obtain the absolute address of the GOT, and it is strongly
7935 * preferable from a performance point of view to avoid using
7936 * a runtime relocation for this. The actual sequence of
7937 * instructions often look something like:
7942 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7944 * The call and pop essentially return the absolute address
7945 * of the label .L66 and store it in %ebx. The linker itself
7946 * will ultimately change the first operand of the addl so
7947 * that %ebx points to the GOT, but to keep things simple, the
7948 * .o file must have this operand set so that it generates not
7949 * the absolute address of .L66, but the absolute address of
7950 * itself. This allows the linker itself simply treat a GOTPC
7951 * relocation as asking for a pcrel offset to the GOT to be
7952 * added in, and the addend of the relocation is stored in the
7953 * operand field for the instruction itself.
7955 * Our job here is to fix the operand so that it would add
7956 * the correct offset so that %ebx would point to itself. The
7957 * thing that is tricky is that .-.L66 will point to the
7958 * beginning of the instruction, so we need to further modify
7959 * the operand so that it will point to itself. There are
7960 * other cases where you have something like:
7962 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7964 * and here no correction would be required. Internally in
7965 * the assembler we treat operands of this form as not being
7966 * pcrel since the '.' is explicitly mentioned, and I wonder
7967 * whether it would simplify matters to do it this way. Who
7968 * knows. In earlier versions of the PIC patches, the
7969 * pcrel_adjust field was used to store the correction, but
7970 * since the expression is not pcrel, I felt it would be
7971 * confusing to do it this way. */
7973 if ((reloc_type == BFD_RELOC_32
7974 || reloc_type == BFD_RELOC_X86_64_32S
7975 || reloc_type == BFD_RELOC_64)
7977 && GOT_symbol == i.op[n].imms->X_add_symbol
7978 && (i.op[n].imms->X_op == O_symbol
7979 || (i.op[n].imms->X_op == O_add
7980 && ((symbol_get_value_expression
7981 (i.op[n].imms->X_op_symbol)->X_op)
7986 if (insn_start_frag == frag_now)
7987 add = (p - frag_now->fr_literal) - insn_start_off;
7992 add = insn_start_frag->fr_fix - insn_start_off;
7993 for (fr = insn_start_frag->fr_next;
7994 fr && fr != frag_now; fr = fr->fr_next)
7996 add += p - frag_now->fr_literal;
8000 reloc_type = BFD_RELOC_386_GOTPC;
8002 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8004 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8005 i.op[n].imms->X_add_number += add;
8007 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8008 i.op[n].imms, 0, reloc_type);
8014 /* x86_cons_fix_new is called via the expression parsing code when a
8015 reloc is needed. We use this hook to get the correct .got reloc. */
8016 static int cons_sign = -1;
8019 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8020 expressionS *exp, bfd_reloc_code_real_type r)
8022 r = reloc (len, 0, cons_sign, r);
8025 if (exp->X_op == O_secrel)
8027 exp->X_op = O_symbol;
8028 r = BFD_RELOC_32_SECREL;
8032 fix_new_exp (frag, off, len, exp, 0, r);
8035 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8036 purpose of the `.dc.a' internal pseudo-op. */
8039 x86_address_bytes (void)
8041 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8043 return stdoutput->arch_info->bits_per_address / 8;
8046 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8048 # define lex_got(reloc, adjust, types) NULL
8050 /* Parse operands of the form
8051 <symbol>@GOTOFF+<nnn>
8052 and similar .plt or .got references.
8054 If we find one, set up the correct relocation in RELOC and copy the
8055 input string, minus the `@GOTOFF' into a malloc'd buffer for
8056 parsing by the calling routine. Return this buffer, and if ADJUST
8057 is non-null set it to the length of the string we removed from the
8058 input line. Otherwise return NULL. */
8060 lex_got (enum bfd_reloc_code_real *rel,
8062 i386_operand_type *types)
8064 /* Some of the relocations depend on the size of what field is to
8065 be relocated. But in our callers i386_immediate and i386_displacement
8066 we don't yet know the operand size (this will be set by insn
8067 matching). Hence we record the word32 relocation here,
8068 and adjust the reloc according to the real size in reloc(). */
8069 static const struct {
8072 const enum bfd_reloc_code_real rel[2];
8073 const i386_operand_type types64;
8075 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8076 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8078 OPERAND_TYPE_IMM32_64 },
8080 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8081 BFD_RELOC_X86_64_PLTOFF64 },
8082 OPERAND_TYPE_IMM64 },
8083 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8084 BFD_RELOC_X86_64_PLT32 },
8085 OPERAND_TYPE_IMM32_32S_DISP32 },
8086 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8087 BFD_RELOC_X86_64_GOTPLT64 },
8088 OPERAND_TYPE_IMM64_DISP64 },
8089 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8090 BFD_RELOC_X86_64_GOTOFF64 },
8091 OPERAND_TYPE_IMM64_DISP64 },
8092 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8093 BFD_RELOC_X86_64_GOTPCREL },
8094 OPERAND_TYPE_IMM32_32S_DISP32 },
8095 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8096 BFD_RELOC_X86_64_TLSGD },
8097 OPERAND_TYPE_IMM32_32S_DISP32 },
8098 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8099 _dummy_first_bfd_reloc_code_real },
8100 OPERAND_TYPE_NONE },
8101 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8102 BFD_RELOC_X86_64_TLSLD },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8105 BFD_RELOC_X86_64_GOTTPOFF },
8106 OPERAND_TYPE_IMM32_32S_DISP32 },
8107 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8108 BFD_RELOC_X86_64_TPOFF32 },
8109 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8110 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8111 _dummy_first_bfd_reloc_code_real },
8112 OPERAND_TYPE_NONE },
8113 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8114 BFD_RELOC_X86_64_DTPOFF32 },
8115 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8116 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8117 _dummy_first_bfd_reloc_code_real },
8118 OPERAND_TYPE_NONE },
8119 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8120 _dummy_first_bfd_reloc_code_real },
8121 OPERAND_TYPE_NONE },
8122 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8123 BFD_RELOC_X86_64_GOT32 },
8124 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8125 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8126 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8127 OPERAND_TYPE_IMM32_32S_DISP32 },
8128 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8129 BFD_RELOC_X86_64_TLSDESC_CALL },
8130 OPERAND_TYPE_IMM32_32S_DISP32 },
8135 #if defined (OBJ_MAYBE_ELF)
8140 for (cp = input_line_pointer; *cp != '@'; cp++)
8141 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8144 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8146 int len = gotrel[j].len;
8147 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8149 if (gotrel[j].rel[object_64bit] != 0)
8152 char *tmpbuf, *past_reloc;
8154 *rel = gotrel[j].rel[object_64bit];
8158 if (flag_code != CODE_64BIT)
8160 types->bitfield.imm32 = 1;
8161 types->bitfield.disp32 = 1;
8164 *types = gotrel[j].types64;
8167 if (j != 0 && GOT_symbol == NULL)
8168 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8170 /* The length of the first part of our input line. */
8171 first = cp - input_line_pointer;
8173 /* The second part goes from after the reloc token until
8174 (and including) an end_of_line char or comma. */
8175 past_reloc = cp + 1 + len;
8177 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8179 second = cp + 1 - past_reloc;
8181 /* Allocate and copy string. The trailing NUL shouldn't
8182 be necessary, but be safe. */
8183 tmpbuf = XNEWVEC (char, first + second + 2);
8184 memcpy (tmpbuf, input_line_pointer, first);
8185 if (second != 0 && *past_reloc != ' ')
8186 /* Replace the relocation token with ' ', so that
8187 errors like foo@GOTOFF1 will be detected. */
8188 tmpbuf[first++] = ' ';
8190 /* Increment length by 1 if the relocation token is
8195 memcpy (tmpbuf + first, past_reloc, second);
8196 tmpbuf[first + second] = '\0';
8200 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8201 gotrel[j].str, 1 << (5 + object_64bit));
8206 /* Might be a symbol version string. Don't as_bad here. */
8215 /* Parse operands of the form
8216 <symbol>@SECREL32+<nnn>
8218 If we find one, set up the correct relocation in RELOC and copy the
8219 input string, minus the `@SECREL32' into a malloc'd buffer for
8220 parsing by the calling routine. Return this buffer, and if ADJUST
8221 is non-null set it to the length of the string we removed from the
8222 input line. Otherwise return NULL.
8224 This function is copied from the ELF version above adjusted for PE targets. */
8227 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8228 int *adjust ATTRIBUTE_UNUSED,
8229 i386_operand_type *types)
8235 const enum bfd_reloc_code_real rel[2];
8236 const i386_operand_type types64;
8240 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8241 BFD_RELOC_32_SECREL },
8242 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8248 for (cp = input_line_pointer; *cp != '@'; cp++)
8249 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8252 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8254 int len = gotrel[j].len;
8256 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8258 if (gotrel[j].rel[object_64bit] != 0)
8261 char *tmpbuf, *past_reloc;
8263 *rel = gotrel[j].rel[object_64bit];
8269 if (flag_code != CODE_64BIT)
8271 types->bitfield.imm32 = 1;
8272 types->bitfield.disp32 = 1;
8275 *types = gotrel[j].types64;
8278 /* The length of the first part of our input line. */
8279 first = cp - input_line_pointer;
8281 /* The second part goes from after the reloc token until
8282 (and including) an end_of_line char or comma. */
8283 past_reloc = cp + 1 + len;
8285 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8287 second = cp + 1 - past_reloc;
8289 /* Allocate and copy string. The trailing NUL shouldn't
8290 be necessary, but be safe. */
8291 tmpbuf = XNEWVEC (char, first + second + 2);
8292 memcpy (tmpbuf, input_line_pointer, first);
8293 if (second != 0 && *past_reloc != ' ')
8294 /* Replace the relocation token with ' ', so that
8295 errors like foo@SECLREL321 will be detected. */
8296 tmpbuf[first++] = ' ';
8297 memcpy (tmpbuf + first, past_reloc, second);
8298 tmpbuf[first + second] = '\0';
8302 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8303 gotrel[j].str, 1 << (5 + object_64bit));
8308 /* Might be a symbol version string. Don't as_bad here. */
8314 bfd_reloc_code_real_type
8315 x86_cons (expressionS *exp, int size)
8317 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8319 intel_syntax = -intel_syntax;
8322 if (size == 4 || (object_64bit && size == 8))
8324 /* Handle @GOTOFF and the like in an expression. */
8326 char *gotfree_input_line;
8329 save = input_line_pointer;
8330 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8331 if (gotfree_input_line)
8332 input_line_pointer = gotfree_input_line;
8336 if (gotfree_input_line)
8338 /* expression () has merrily parsed up to the end of line,
8339 or a comma - in the wrong buffer. Transfer how far
8340 input_line_pointer has moved to the right buffer. */
8341 input_line_pointer = (save
8342 + (input_line_pointer - gotfree_input_line)
8344 free (gotfree_input_line);
8345 if (exp->X_op == O_constant
8346 || exp->X_op == O_absent
8347 || exp->X_op == O_illegal
8348 || exp->X_op == O_register
8349 || exp->X_op == O_big)
8351 char c = *input_line_pointer;
8352 *input_line_pointer = 0;
8353 as_bad (_("missing or invalid expression `%s'"), save);
8354 *input_line_pointer = c;
8361 intel_syntax = -intel_syntax;
8364 i386_intel_simplify (exp);
8370 signed_cons (int size)
8372 if (flag_code == CODE_64BIT)
8380 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8387 if (exp.X_op == O_symbol)
8388 exp.X_op = O_secrel;
8390 emit_expr (&exp, 4);
8392 while (*input_line_pointer++ == ',');
8394 input_line_pointer--;
8395 demand_empty_rest_of_line ();
8399 /* Handle Vector operations. */
8402 check_VecOperations (char *op_string, char *op_end)
8404 const reg_entry *mask;
8409 && (op_end == NULL || op_string < op_end))
8412 if (*op_string == '{')
8416 /* Check broadcasts. */
8417 if (strncmp (op_string, "1to", 3) == 0)
8422 goto duplicated_vec_op;
8425 if (*op_string == '8')
8426 bcst_type = BROADCAST_1TO8;
8427 else if (*op_string == '4')
8428 bcst_type = BROADCAST_1TO4;
8429 else if (*op_string == '2')
8430 bcst_type = BROADCAST_1TO2;
8431 else if (*op_string == '1'
8432 && *(op_string+1) == '6')
8434 bcst_type = BROADCAST_1TO16;
8439 as_bad (_("Unsupported broadcast: `%s'"), saved);
8444 broadcast_op.type = bcst_type;
8445 broadcast_op.operand = this_operand;
8446 i.broadcast = &broadcast_op;
8448 /* Check masking operation. */
8449 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8451 /* k0 can't be used for write mask. */
8452 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8454 as_bad (_("`%s%s' can't be used for write mask"),
8455 register_prefix, mask->reg_name);
8461 mask_op.mask = mask;
8462 mask_op.zeroing = 0;
8463 mask_op.operand = this_operand;
8469 goto duplicated_vec_op;
8471 i.mask->mask = mask;
8473 /* Only "{z}" is allowed here. No need to check
8474 zeroing mask explicitly. */
8475 if (i.mask->operand != this_operand)
8477 as_bad (_("invalid write mask `%s'"), saved);
8484 /* Check zeroing-flag for masking operation. */
8485 else if (*op_string == 'z')
8489 mask_op.mask = NULL;
8490 mask_op.zeroing = 1;
8491 mask_op.operand = this_operand;
8496 if (i.mask->zeroing)
8499 as_bad (_("duplicated `%s'"), saved);
8503 i.mask->zeroing = 1;
8505 /* Only "{%k}" is allowed here. No need to check mask
8506 register explicitly. */
8507 if (i.mask->operand != this_operand)
8509 as_bad (_("invalid zeroing-masking `%s'"),
8518 goto unknown_vec_op;
8520 if (*op_string != '}')
8522 as_bad (_("missing `}' in `%s'"), saved);
8529 /* We don't know this one. */
8530 as_bad (_("unknown vector operation: `%s'"), saved);
8534 if (i.mask && i.mask->zeroing && !i.mask->mask)
8536 as_bad (_("zeroing-masking only allowed with write mask"));
8544 i386_immediate (char *imm_start)
8546 char *save_input_line_pointer;
8547 char *gotfree_input_line;
8550 i386_operand_type types;
8552 operand_type_set (&types, ~0);
8554 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8556 as_bad (_("at most %d immediate operands are allowed"),
8557 MAX_IMMEDIATE_OPERANDS);
8561 exp = &im_expressions[i.imm_operands++];
8562 i.op[this_operand].imms = exp;
8564 if (is_space_char (*imm_start))
8567 save_input_line_pointer = input_line_pointer;
8568 input_line_pointer = imm_start;
8570 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8571 if (gotfree_input_line)
8572 input_line_pointer = gotfree_input_line;
8574 exp_seg = expression (exp);
8578 /* Handle vector operations. */
8579 if (*input_line_pointer == '{')
8581 input_line_pointer = check_VecOperations (input_line_pointer,
8583 if (input_line_pointer == NULL)
8587 if (*input_line_pointer)
8588 as_bad (_("junk `%s' after expression"), input_line_pointer);
8590 input_line_pointer = save_input_line_pointer;
8591 if (gotfree_input_line)
8593 free (gotfree_input_line);
8595 if (exp->X_op == O_constant || exp->X_op == O_register)
8596 exp->X_op = O_illegal;
8599 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8603 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8604 i386_operand_type types, const char *imm_start)
8606 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8609 as_bad (_("missing or invalid immediate expression `%s'"),
8613 else if (exp->X_op == O_constant)
8615 /* Size it properly later. */
8616 i.types[this_operand].bitfield.imm64 = 1;
8617 /* If not 64bit, sign extend val. */
8618 if (flag_code != CODE_64BIT
8619 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8621 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8623 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8624 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8625 && exp_seg != absolute_section
8626 && exp_seg != text_section
8627 && exp_seg != data_section
8628 && exp_seg != bss_section
8629 && exp_seg != undefined_section
8630 && !bfd_is_com_section (exp_seg))
8632 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8636 else if (!intel_syntax && exp_seg == reg_section)
8639 as_bad (_("illegal immediate register operand %s"), imm_start);
8644 /* This is an address. The size of the address will be
8645 determined later, depending on destination register,
8646 suffix, or the default for the section. */
8647 i.types[this_operand].bitfield.imm8 = 1;
8648 i.types[this_operand].bitfield.imm16 = 1;
8649 i.types[this_operand].bitfield.imm32 = 1;
8650 i.types[this_operand].bitfield.imm32s = 1;
8651 i.types[this_operand].bitfield.imm64 = 1;
8652 i.types[this_operand] = operand_type_and (i.types[this_operand],
8660 i386_scale (char *scale)
8663 char *save = input_line_pointer;
8665 input_line_pointer = scale;
8666 val = get_absolute_expression ();
8671 i.log2_scale_factor = 0;
8674 i.log2_scale_factor = 1;
8677 i.log2_scale_factor = 2;
8680 i.log2_scale_factor = 3;
8684 char sep = *input_line_pointer;
8686 *input_line_pointer = '\0';
8687 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8689 *input_line_pointer = sep;
8690 input_line_pointer = save;
8694 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8696 as_warn (_("scale factor of %d without an index register"),
8697 1 << i.log2_scale_factor);
8698 i.log2_scale_factor = 0;
8700 scale = input_line_pointer;
8701 input_line_pointer = save;
8706 i386_displacement (char *disp_start, char *disp_end)
8710 char *save_input_line_pointer;
8711 char *gotfree_input_line;
8713 i386_operand_type bigdisp, types = anydisp;
8716 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8718 as_bad (_("at most %d displacement operands are allowed"),
8719 MAX_MEMORY_OPERANDS);
8723 operand_type_set (&bigdisp, 0);
8724 if ((i.types[this_operand].bitfield.jumpabsolute)
8725 || (!current_templates->start->opcode_modifier.jump
8726 && !current_templates->start->opcode_modifier.jumpdword))
8728 bigdisp.bitfield.disp32 = 1;
8729 override = (i.prefix[ADDR_PREFIX] != 0);
8730 if (flag_code == CODE_64BIT)
8734 bigdisp.bitfield.disp32s = 1;
8735 bigdisp.bitfield.disp64 = 1;
8738 else if ((flag_code == CODE_16BIT) ^ override)
8740 bigdisp.bitfield.disp32 = 0;
8741 bigdisp.bitfield.disp16 = 1;
8746 /* For PC-relative branches, the width of the displacement
8747 is dependent upon data size, not address size. */
8748 override = (i.prefix[DATA_PREFIX] != 0);
8749 if (flag_code == CODE_64BIT)
8751 if (override || i.suffix == WORD_MNEM_SUFFIX)
8752 bigdisp.bitfield.disp16 = 1;
8755 bigdisp.bitfield.disp32 = 1;
8756 bigdisp.bitfield.disp32s = 1;
8762 override = (i.suffix == (flag_code != CODE_16BIT
8764 : LONG_MNEM_SUFFIX));
8765 bigdisp.bitfield.disp32 = 1;
8766 if ((flag_code == CODE_16BIT) ^ override)
8768 bigdisp.bitfield.disp32 = 0;
8769 bigdisp.bitfield.disp16 = 1;
8773 i.types[this_operand] = operand_type_or (i.types[this_operand],
8776 exp = &disp_expressions[i.disp_operands];
8777 i.op[this_operand].disps = exp;
8779 save_input_line_pointer = input_line_pointer;
8780 input_line_pointer = disp_start;
8781 END_STRING_AND_SAVE (disp_end);
8783 #ifndef GCC_ASM_O_HACK
8784 #define GCC_ASM_O_HACK 0
8787 END_STRING_AND_SAVE (disp_end + 1);
8788 if (i.types[this_operand].bitfield.baseIndex
8789 && displacement_string_end[-1] == '+')
8791 /* This hack is to avoid a warning when using the "o"
8792 constraint within gcc asm statements.
8795 #define _set_tssldt_desc(n,addr,limit,type) \
8796 __asm__ __volatile__ ( \
8798 "movw %w1,2+%0\n\t" \
8800 "movb %b1,4+%0\n\t" \
8801 "movb %4,5+%0\n\t" \
8802 "movb $0,6+%0\n\t" \
8803 "movb %h1,7+%0\n\t" \
8805 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8807 This works great except that the output assembler ends
8808 up looking a bit weird if it turns out that there is
8809 no offset. You end up producing code that looks like:
8822 So here we provide the missing zero. */
8824 *displacement_string_end = '0';
8827 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8828 if (gotfree_input_line)
8829 input_line_pointer = gotfree_input_line;
8831 exp_seg = expression (exp);
8834 if (*input_line_pointer)
8835 as_bad (_("junk `%s' after expression"), input_line_pointer);
8837 RESTORE_END_STRING (disp_end + 1);
8839 input_line_pointer = save_input_line_pointer;
8840 if (gotfree_input_line)
8842 free (gotfree_input_line);
8844 if (exp->X_op == O_constant || exp->X_op == O_register)
8845 exp->X_op = O_illegal;
8848 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8850 RESTORE_END_STRING (disp_end);
8856 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8857 i386_operand_type types, const char *disp_start)
8859 i386_operand_type bigdisp;
8862 /* We do this to make sure that the section symbol is in
8863 the symbol table. We will ultimately change the relocation
8864 to be relative to the beginning of the section. */
8865 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8866 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8867 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8869 if (exp->X_op != O_symbol)
8872 if (S_IS_LOCAL (exp->X_add_symbol)
8873 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8874 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8875 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8876 exp->X_op = O_subtract;
8877 exp->X_op_symbol = GOT_symbol;
8878 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8879 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8880 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8881 i.reloc[this_operand] = BFD_RELOC_64;
8883 i.reloc[this_operand] = BFD_RELOC_32;
8886 else if (exp->X_op == O_absent
8887 || exp->X_op == O_illegal
8888 || exp->X_op == O_big)
8891 as_bad (_("missing or invalid displacement expression `%s'"),
8896 else if (flag_code == CODE_64BIT
8897 && !i.prefix[ADDR_PREFIX]
8898 && exp->X_op == O_constant)
8900 /* Since displacement is signed extended to 64bit, don't allow
8901 disp32 and turn off disp32s if they are out of range. */
8902 i.types[this_operand].bitfield.disp32 = 0;
8903 if (!fits_in_signed_long (exp->X_add_number))
8905 i.types[this_operand].bitfield.disp32s = 0;
8906 if (i.types[this_operand].bitfield.baseindex)
8908 as_bad (_("0x%lx out range of signed 32bit displacement"),
8909 (long) exp->X_add_number);
8915 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8916 else if (exp->X_op != O_constant
8917 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8918 && exp_seg != absolute_section
8919 && exp_seg != text_section
8920 && exp_seg != data_section
8921 && exp_seg != bss_section
8922 && exp_seg != undefined_section
8923 && !bfd_is_com_section (exp_seg))
8925 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8930 /* Check if this is a displacement only operand. */
8931 bigdisp = i.types[this_operand];
8932 bigdisp.bitfield.disp8 = 0;
8933 bigdisp.bitfield.disp16 = 0;
8934 bigdisp.bitfield.disp32 = 0;
8935 bigdisp.bitfield.disp32s = 0;
8936 bigdisp.bitfield.disp64 = 0;
8937 if (operand_type_all_zero (&bigdisp))
8938 i.types[this_operand] = operand_type_and (i.types[this_operand],
8944 /* Return the active addressing mode, taking address override and
8945 registers forming the address into consideration. Update the
8946 address override prefix if necessary. */
8948 static enum flag_code
8949 i386_addressing_mode (void)
8951 enum flag_code addr_mode;
8953 if (i.prefix[ADDR_PREFIX])
8954 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8957 addr_mode = flag_code;
8959 #if INFER_ADDR_PREFIX
8960 if (i.mem_operands == 0)
8962 /* Infer address prefix from the first memory operand. */
8963 const reg_entry *addr_reg = i.base_reg;
8965 if (addr_reg == NULL)
8966 addr_reg = i.index_reg;
8970 if (addr_reg->reg_num == RegEip
8971 || addr_reg->reg_num == RegEiz
8972 || addr_reg->reg_type.bitfield.dword)
8973 addr_mode = CODE_32BIT;
8974 else if (flag_code != CODE_64BIT
8975 && addr_reg->reg_type.bitfield.word)
8976 addr_mode = CODE_16BIT;
8978 if (addr_mode != flag_code)
8980 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8982 /* Change the size of any displacement too. At most one
8983 of Disp16 or Disp32 is set.
8984 FIXME. There doesn't seem to be any real need for
8985 separate Disp16 and Disp32 flags. The same goes for
8986 Imm16 and Imm32. Removing them would probably clean
8987 up the code quite a lot. */
8988 if (flag_code != CODE_64BIT
8989 && (i.types[this_operand].bitfield.disp16
8990 || i.types[this_operand].bitfield.disp32))
8991 i.types[this_operand]
8992 = operand_type_xor (i.types[this_operand], disp16_32);
9002 /* Make sure the memory operand we've been dealt is valid.
9003 Return 1 on success, 0 on a failure. */
9006 i386_index_check (const char *operand_string)
9008 const char *kind = "base/index";
9009 enum flag_code addr_mode = i386_addressing_mode ();
9011 if (current_templates->start->opcode_modifier.isstring
9012 && !current_templates->start->opcode_modifier.immext
9013 && (current_templates->end[-1].opcode_modifier.isstring
9016 /* Memory operands of string insns are special in that they only allow
9017 a single register (rDI, rSI, or rBX) as their memory address. */
9018 const reg_entry *expected_reg;
9019 static const char *di_si[][2] =
9025 static const char *bx[] = { "ebx", "bx", "rbx" };
9027 kind = "string address";
9029 if (current_templates->start->opcode_modifier.repprefixok)
9031 i386_operand_type type = current_templates->end[-1].operand_types[0];
9033 if (!type.bitfield.baseindex
9034 || ((!i.mem_operands != !intel_syntax)
9035 && current_templates->end[-1].operand_types[1]
9036 .bitfield.baseindex))
9037 type = current_templates->end[-1].operand_types[1];
9038 expected_reg = hash_find (reg_hash,
9039 di_si[addr_mode][type.bitfield.esseg]);
9043 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9045 if (i.base_reg != expected_reg
9047 || operand_type_check (i.types[this_operand], disp))
9049 /* The second memory operand must have the same size as
9053 && !((addr_mode == CODE_64BIT
9054 && i.base_reg->reg_type.bitfield.qword)
9055 || (addr_mode == CODE_32BIT
9056 ? i.base_reg->reg_type.bitfield.dword
9057 : i.base_reg->reg_type.bitfield.word)))
9060 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9062 intel_syntax ? '[' : '(',
9064 expected_reg->reg_name,
9065 intel_syntax ? ']' : ')');
9072 as_bad (_("`%s' is not a valid %s expression"),
9073 operand_string, kind);
9078 if (addr_mode != CODE_16BIT)
9080 /* 32-bit/64-bit checks. */
9082 && (addr_mode == CODE_64BIT
9083 ? !i.base_reg->reg_type.bitfield.qword
9084 : !i.base_reg->reg_type.bitfield.dword)
9086 || (i.base_reg->reg_num
9087 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9089 && !i.index_reg->reg_type.bitfield.xmmword
9090 && !i.index_reg->reg_type.bitfield.ymmword
9091 && !i.index_reg->reg_type.bitfield.zmmword
9092 && ((addr_mode == CODE_64BIT
9093 ? !(i.index_reg->reg_type.bitfield.qword
9094 || i.index_reg->reg_num == RegRiz)
9095 : !(i.index_reg->reg_type.bitfield.dword
9096 || i.index_reg->reg_num == RegEiz))
9097 || !i.index_reg->reg_type.bitfield.baseindex)))
9100 /* bndmk, bndldx, and bndstx have special restrictions. */
9101 if (current_templates->start->base_opcode == 0xf30f1b
9102 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9104 /* They cannot use RIP-relative addressing. */
9105 if (i.base_reg && i.base_reg->reg_num == RegRip)
9107 as_bad (_("`%s' cannot be used here"), operand_string);
9111 /* bndldx and bndstx ignore their scale factor. */
9112 if (current_templates->start->base_opcode != 0xf30f1b
9113 && i.log2_scale_factor)
9114 as_warn (_("register scaling is being ignored here"));
9119 /* 16-bit checks. */
9121 && (!i.base_reg->reg_type.bitfield.word
9122 || !i.base_reg->reg_type.bitfield.baseindex))
9124 && (!i.index_reg->reg_type.bitfield.word
9125 || !i.index_reg->reg_type.bitfield.baseindex
9127 && i.base_reg->reg_num < 6
9128 && i.index_reg->reg_num >= 6
9129 && i.log2_scale_factor == 0))))
9136 /* Handle vector immediates. */
9139 RC_SAE_immediate (const char *imm_start)
9141 unsigned int match_found, j;
9142 const char *pstr = imm_start;
9150 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9152 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9156 rc_op.type = RC_NamesTable[j].type;
9157 rc_op.operand = this_operand;
9158 i.rounding = &rc_op;
9162 as_bad (_("duplicated `%s'"), imm_start);
9165 pstr += RC_NamesTable[j].len;
9175 as_bad (_("Missing '}': '%s'"), imm_start);
9178 /* RC/SAE immediate string should contain nothing more. */;
9181 as_bad (_("Junk after '}': '%s'"), imm_start);
9185 exp = &im_expressions[i.imm_operands++];
9186 i.op[this_operand].imms = exp;
9188 exp->X_op = O_constant;
9189 exp->X_add_number = 0;
9190 exp->X_add_symbol = (symbolS *) 0;
9191 exp->X_op_symbol = (symbolS *) 0;
9193 i.types[this_operand].bitfield.imm8 = 1;
9197 /* Only string instructions can have a second memory operand, so
9198 reduce current_templates to just those if it contains any. */
9200 maybe_adjust_templates (void)
9202 const insn_template *t;
9204 gas_assert (i.mem_operands == 1);
9206 for (t = current_templates->start; t < current_templates->end; ++t)
9207 if (t->opcode_modifier.isstring)
9210 if (t < current_templates->end)
9212 static templates aux_templates;
9213 bfd_boolean recheck;
9215 aux_templates.start = t;
9216 for (; t < current_templates->end; ++t)
9217 if (!t->opcode_modifier.isstring)
9219 aux_templates.end = t;
9221 /* Determine whether to re-check the first memory operand. */
9222 recheck = (aux_templates.start != current_templates->start
9223 || t != current_templates->end);
9225 current_templates = &aux_templates;
9230 if (i.memop1_string != NULL
9231 && i386_index_check (i.memop1_string) == 0)
9240 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9244 i386_att_operand (char *operand_string)
9248 char *op_string = operand_string;
9250 if (is_space_char (*op_string))
9253 /* We check for an absolute prefix (differentiating,
9254 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9255 if (*op_string == ABSOLUTE_PREFIX)
9258 if (is_space_char (*op_string))
9260 i.types[this_operand].bitfield.jumpabsolute = 1;
9263 /* Check if operand is a register. */
9264 if ((r = parse_register (op_string, &end_op)) != NULL)
9266 i386_operand_type temp;
9268 /* Check for a segment override by searching for ':' after a
9269 segment register. */
9271 if (is_space_char (*op_string))
9273 if (*op_string == ':'
9274 && (r->reg_type.bitfield.sreg2
9275 || r->reg_type.bitfield.sreg3))
9280 i.seg[i.mem_operands] = &es;
9283 i.seg[i.mem_operands] = &cs;
9286 i.seg[i.mem_operands] = &ss;
9289 i.seg[i.mem_operands] = &ds;
9292 i.seg[i.mem_operands] = &fs;
9295 i.seg[i.mem_operands] = &gs;
9299 /* Skip the ':' and whitespace. */
9301 if (is_space_char (*op_string))
9304 if (!is_digit_char (*op_string)
9305 && !is_identifier_char (*op_string)
9306 && *op_string != '('
9307 && *op_string != ABSOLUTE_PREFIX)
9309 as_bad (_("bad memory operand `%s'"), op_string);
9312 /* Handle case of %es:*foo. */
9313 if (*op_string == ABSOLUTE_PREFIX)
9316 if (is_space_char (*op_string))
9318 i.types[this_operand].bitfield.jumpabsolute = 1;
9320 goto do_memory_reference;
9323 /* Handle vector operations. */
9324 if (*op_string == '{')
9326 op_string = check_VecOperations (op_string, NULL);
9327 if (op_string == NULL)
9333 as_bad (_("junk `%s' after register"), op_string);
9337 temp.bitfield.baseindex = 0;
9338 i.types[this_operand] = operand_type_or (i.types[this_operand],
9340 i.types[this_operand].bitfield.unspecified = 0;
9341 i.op[this_operand].regs = r;
9344 else if (*op_string == REGISTER_PREFIX)
9346 as_bad (_("bad register name `%s'"), op_string);
9349 else if (*op_string == IMMEDIATE_PREFIX)
9352 if (i.types[this_operand].bitfield.jumpabsolute)
9354 as_bad (_("immediate operand illegal with absolute jump"));
9357 if (!i386_immediate (op_string))
9360 else if (RC_SAE_immediate (operand_string))
9362 /* If it is a RC or SAE immediate, do nothing. */
9365 else if (is_digit_char (*op_string)
9366 || is_identifier_char (*op_string)
9367 || *op_string == '"'
9368 || *op_string == '(')
9370 /* This is a memory reference of some sort. */
9373 /* Start and end of displacement string expression (if found). */
9374 char *displacement_string_start;
9375 char *displacement_string_end;
9378 do_memory_reference:
9379 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9381 if ((i.mem_operands == 1
9382 && !current_templates->start->opcode_modifier.isstring)
9383 || i.mem_operands == 2)
9385 as_bad (_("too many memory references for `%s'"),
9386 current_templates->start->name);
9390 /* Check for base index form. We detect the base index form by
9391 looking for an ')' at the end of the operand, searching
9392 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9394 base_string = op_string + strlen (op_string);
9396 /* Handle vector operations. */
9397 vop_start = strchr (op_string, '{');
9398 if (vop_start && vop_start < base_string)
9400 if (check_VecOperations (vop_start, base_string) == NULL)
9402 base_string = vop_start;
9406 if (is_space_char (*base_string))
9409 /* If we only have a displacement, set-up for it to be parsed later. */
9410 displacement_string_start = op_string;
9411 displacement_string_end = base_string + 1;
9413 if (*base_string == ')')
9416 unsigned int parens_balanced = 1;
9417 /* We've already checked that the number of left & right ()'s are
9418 equal, so this loop will not be infinite. */
9422 if (*base_string == ')')
9424 if (*base_string == '(')
9427 while (parens_balanced);
9429 temp_string = base_string;
9431 /* Skip past '(' and whitespace. */
9433 if (is_space_char (*base_string))
9436 if (*base_string == ','
9437 || ((i.base_reg = parse_register (base_string, &end_op))
9440 displacement_string_end = temp_string;
9442 i.types[this_operand].bitfield.baseindex = 1;
9446 base_string = end_op;
9447 if (is_space_char (*base_string))
9451 /* There may be an index reg or scale factor here. */
9452 if (*base_string == ',')
9455 if (is_space_char (*base_string))
9458 if ((i.index_reg = parse_register (base_string, &end_op))
9461 base_string = end_op;
9462 if (is_space_char (*base_string))
9464 if (*base_string == ',')
9467 if (is_space_char (*base_string))
9470 else if (*base_string != ')')
9472 as_bad (_("expecting `,' or `)' "
9473 "after index register in `%s'"),
9478 else if (*base_string == REGISTER_PREFIX)
9480 end_op = strchr (base_string, ',');
9483 as_bad (_("bad register name `%s'"), base_string);
9487 /* Check for scale factor. */
9488 if (*base_string != ')')
9490 char *end_scale = i386_scale (base_string);
9495 base_string = end_scale;
9496 if (is_space_char (*base_string))
9498 if (*base_string != ')')
9500 as_bad (_("expecting `)' "
9501 "after scale factor in `%s'"),
9506 else if (!i.index_reg)
9508 as_bad (_("expecting index register or scale factor "
9509 "after `,'; got '%c'"),
9514 else if (*base_string != ')')
9516 as_bad (_("expecting `,' or `)' "
9517 "after base register in `%s'"),
9522 else if (*base_string == REGISTER_PREFIX)
9524 end_op = strchr (base_string, ',');
9527 as_bad (_("bad register name `%s'"), base_string);
9532 /* If there's an expression beginning the operand, parse it,
9533 assuming displacement_string_start and
9534 displacement_string_end are meaningful. */
9535 if (displacement_string_start != displacement_string_end)
9537 if (!i386_displacement (displacement_string_start,
9538 displacement_string_end))
9542 /* Special case for (%dx) while doing input/output op. */
9544 && operand_type_equal (&i.base_reg->reg_type,
9545 ®16_inoutportreg)
9547 && i.log2_scale_factor == 0
9548 && i.seg[i.mem_operands] == 0
9549 && !operand_type_check (i.types[this_operand], disp))
9551 i.types[this_operand] = inoutportreg;
9555 if (i386_index_check (operand_string) == 0)
9557 i.types[this_operand].bitfield.mem = 1;
9558 if (i.mem_operands == 0)
9559 i.memop1_string = xstrdup (operand_string);
9564 /* It's not a memory operand; argh! */
9565 as_bad (_("invalid char %s beginning operand %d `%s'"),
9566 output_invalid (*op_string),
9571 return 1; /* Normal return. */
9574 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9575 that an rs_machine_dependent frag may reach. */
9578 i386_frag_max_var (fragS *frag)
9580 /* The only relaxable frags are for jumps.
9581 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9582 gas_assert (frag->fr_type == rs_machine_dependent);
9583 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9586 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9588 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9590 /* STT_GNU_IFUNC symbol must go through PLT. */
9591 if ((symbol_get_bfdsym (fr_symbol)->flags
9592 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9595 if (!S_IS_EXTERNAL (fr_symbol))
9596 /* Symbol may be weak or local. */
9597 return !S_IS_WEAK (fr_symbol);
9599 /* Global symbols with non-default visibility can't be preempted. */
9600 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9603 if (fr_var != NO_RELOC)
9604 switch ((enum bfd_reloc_code_real) fr_var)
9606 case BFD_RELOC_386_PLT32:
9607 case BFD_RELOC_X86_64_PLT32:
9608 /* Symbol with PLT relocation may be preempted. */
9614 /* Global symbols with default visibility in a shared library may be
9615 preempted by another definition. */
9620 /* md_estimate_size_before_relax()
9622 Called just before relax() for rs_machine_dependent frags. The x86
9623 assembler uses these frags to handle variable size jump
9626 Any symbol that is now undefined will not become defined.
9627 Return the correct fr_subtype in the frag.
9628 Return the initial "guess for variable size of frag" to caller.
9629 The guess is actually the growth beyond the fixed part. Whatever
9630 we do to grow the fixed or variable part contributes to our
9634 md_estimate_size_before_relax (fragS *fragP, segT segment)
9636 /* We've already got fragP->fr_subtype right; all we have to do is
9637 check for un-relaxable symbols. On an ELF system, we can't relax
9638 an externally visible symbol, because it may be overridden by a
9640 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9643 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9646 #if defined (OBJ_COFF) && defined (TE_PE)
9647 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9648 && S_IS_WEAK (fragP->fr_symbol))
9652 /* Symbol is undefined in this segment, or we need to keep a
9653 reloc so that weak symbols can be overridden. */
9654 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9655 enum bfd_reloc_code_real reloc_type;
9656 unsigned char *opcode;
9659 if (fragP->fr_var != NO_RELOC)
9660 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9662 reloc_type = BFD_RELOC_16_PCREL;
9663 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9664 else if (need_plt32_p (fragP->fr_symbol))
9665 reloc_type = BFD_RELOC_X86_64_PLT32;
9668 reloc_type = BFD_RELOC_32_PCREL;
9670 old_fr_fix = fragP->fr_fix;
9671 opcode = (unsigned char *) fragP->fr_opcode;
9673 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9676 /* Make jmp (0xeb) a (d)word displacement jump. */
9678 fragP->fr_fix += size;
9679 fix_new (fragP, old_fr_fix, size,
9681 fragP->fr_offset, 1,
9687 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9689 /* Negate the condition, and branch past an
9690 unconditional jump. */
9693 /* Insert an unconditional jump. */
9695 /* We added two extra opcode bytes, and have a two byte
9697 fragP->fr_fix += 2 + 2;
9698 fix_new (fragP, old_fr_fix + 2, 2,
9700 fragP->fr_offset, 1,
9707 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9712 fixP = fix_new (fragP, old_fr_fix, 1,
9714 fragP->fr_offset, 1,
9716 fixP->fx_signed = 1;
9720 /* This changes the byte-displacement jump 0x7N
9721 to the (d)word-displacement jump 0x0f,0x8N. */
9722 opcode[1] = opcode[0] + 0x10;
9723 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9724 /* We've added an opcode byte. */
9725 fragP->fr_fix += 1 + size;
9726 fix_new (fragP, old_fr_fix + 1, size,
9728 fragP->fr_offset, 1,
9733 BAD_CASE (fragP->fr_subtype);
9737 return fragP->fr_fix - old_fr_fix;
9740 /* Guess size depending on current relax state. Initially the relax
9741 state will correspond to a short jump and we return 1, because
9742 the variable part of the frag (the branch offset) is one byte
9743 long. However, we can relax a section more than once and in that
9744 case we must either set fr_subtype back to the unrelaxed state,
9745 or return the value for the appropriate branch. */
9746 return md_relax_table[fragP->fr_subtype].rlx_length;
9749 /* Called after relax() is finished.
9751 In: Address of frag.
9752 fr_type == rs_machine_dependent.
9753 fr_subtype is what the address relaxed to.
9755 Out: Any fixSs and constants are set up.
9756 Caller will turn frag into a ".space 0". */
9759 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9762 unsigned char *opcode;
9763 unsigned char *where_to_put_displacement = NULL;
9764 offsetT target_address;
9765 offsetT opcode_address;
9766 unsigned int extension = 0;
9767 offsetT displacement_from_opcode_start;
9769 opcode = (unsigned char *) fragP->fr_opcode;
9771 /* Address we want to reach in file space. */
9772 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9774 /* Address opcode resides at in file space. */
9775 opcode_address = fragP->fr_address + fragP->fr_fix;
9777 /* Displacement from opcode start to fill into instruction. */
9778 displacement_from_opcode_start = target_address - opcode_address;
9780 if ((fragP->fr_subtype & BIG) == 0)
9782 /* Don't have to change opcode. */
9783 extension = 1; /* 1 opcode + 1 displacement */
9784 where_to_put_displacement = &opcode[1];
9788 if (no_cond_jump_promotion
9789 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9790 as_warn_where (fragP->fr_file, fragP->fr_line,
9791 _("long jump required"));
9793 switch (fragP->fr_subtype)
9795 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9796 extension = 4; /* 1 opcode + 4 displacement */
9798 where_to_put_displacement = &opcode[1];
9801 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9802 extension = 2; /* 1 opcode + 2 displacement */
9804 where_to_put_displacement = &opcode[1];
9807 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9808 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9809 extension = 5; /* 2 opcode + 4 displacement */
9810 opcode[1] = opcode[0] + 0x10;
9811 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9812 where_to_put_displacement = &opcode[2];
9815 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9816 extension = 3; /* 2 opcode + 2 displacement */
9817 opcode[1] = opcode[0] + 0x10;
9818 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9819 where_to_put_displacement = &opcode[2];
9822 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9827 where_to_put_displacement = &opcode[3];
9831 BAD_CASE (fragP->fr_subtype);
9836 /* If size if less then four we are sure that the operand fits,
9837 but if it's 4, then it could be that the displacement is larger
9839 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9841 && ((addressT) (displacement_from_opcode_start - extension
9842 + ((addressT) 1 << 31))
9843 > (((addressT) 2 << 31) - 1)))
9845 as_bad_where (fragP->fr_file, fragP->fr_line,
9846 _("jump target out of range"));
9847 /* Make us emit 0. */
9848 displacement_from_opcode_start = extension;
9850 /* Now put displacement after opcode. */
9851 md_number_to_chars ((char *) where_to_put_displacement,
9852 (valueT) (displacement_from_opcode_start - extension),
9853 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9854 fragP->fr_fix += extension;
9857 /* Apply a fixup (fixP) to segment data, once it has been determined
9858 by our caller that we have all the info we need to fix it up.
9860 Parameter valP is the pointer to the value of the bits.
9862 On the 386, immediates, displacements, and data pointers are all in
9863 the same (little-endian) format, so we don't need to care about which
9867 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9869 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9870 valueT value = *valP;
9872 #if !defined (TE_Mach)
9875 switch (fixP->fx_r_type)
9881 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9884 case BFD_RELOC_X86_64_32S:
9885 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9888 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9891 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9896 if (fixP->fx_addsy != NULL
9897 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9898 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9899 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9900 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9901 && !use_rela_relocations)
9903 /* This is a hack. There should be a better way to handle this.
9904 This covers for the fact that bfd_install_relocation will
9905 subtract the current location (for partial_inplace, PC relative
9906 relocations); see more below. */
9910 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9913 value += fixP->fx_where + fixP->fx_frag->fr_address;
9915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9918 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9921 || (symbol_section_p (fixP->fx_addsy)
9922 && sym_seg != absolute_section))
9923 && !generic_force_reloc (fixP))
9925 /* Yes, we add the values in twice. This is because
9926 bfd_install_relocation subtracts them out again. I think
9927 bfd_install_relocation is broken, but I don't dare change
9929 value += fixP->fx_where + fixP->fx_frag->fr_address;
9933 #if defined (OBJ_COFF) && defined (TE_PE)
9934 /* For some reason, the PE format does not store a
9935 section address offset for a PC relative symbol. */
9936 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9937 || S_IS_WEAK (fixP->fx_addsy))
9938 value += md_pcrel_from (fixP);
9941 #if defined (OBJ_COFF) && defined (TE_PE)
9942 if (fixP->fx_addsy != NULL
9943 && S_IS_WEAK (fixP->fx_addsy)
9944 /* PR 16858: Do not modify weak function references. */
9945 && ! fixP->fx_pcrel)
9947 #if !defined (TE_PEP)
9948 /* For x86 PE weak function symbols are neither PC-relative
9949 nor do they set S_IS_FUNCTION. So the only reliable way
9950 to detect them is to check the flags of their containing
9952 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9953 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9957 value -= S_GET_VALUE (fixP->fx_addsy);
9961 /* Fix a few things - the dynamic linker expects certain values here,
9962 and we must not disappoint it. */
9963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9964 if (IS_ELF && fixP->fx_addsy)
9965 switch (fixP->fx_r_type)
9967 case BFD_RELOC_386_PLT32:
9968 case BFD_RELOC_X86_64_PLT32:
9969 /* Make the jump instruction point to the address of the operand. At
9970 runtime we merely add the offset to the actual PLT entry. */
9974 case BFD_RELOC_386_TLS_GD:
9975 case BFD_RELOC_386_TLS_LDM:
9976 case BFD_RELOC_386_TLS_IE_32:
9977 case BFD_RELOC_386_TLS_IE:
9978 case BFD_RELOC_386_TLS_GOTIE:
9979 case BFD_RELOC_386_TLS_GOTDESC:
9980 case BFD_RELOC_X86_64_TLSGD:
9981 case BFD_RELOC_X86_64_TLSLD:
9982 case BFD_RELOC_X86_64_GOTTPOFF:
9983 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9984 value = 0; /* Fully resolved at runtime. No addend. */
9986 case BFD_RELOC_386_TLS_LE:
9987 case BFD_RELOC_386_TLS_LDO_32:
9988 case BFD_RELOC_386_TLS_LE_32:
9989 case BFD_RELOC_X86_64_DTPOFF32:
9990 case BFD_RELOC_X86_64_DTPOFF64:
9991 case BFD_RELOC_X86_64_TPOFF32:
9992 case BFD_RELOC_X86_64_TPOFF64:
9993 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9996 case BFD_RELOC_386_TLS_DESC_CALL:
9997 case BFD_RELOC_X86_64_TLSDESC_CALL:
9998 value = 0; /* Fully resolved at runtime. No addend. */
9999 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10003 case BFD_RELOC_VTABLE_INHERIT:
10004 case BFD_RELOC_VTABLE_ENTRY:
10011 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10013 #endif /* !defined (TE_Mach) */
10015 /* Are we finished with this relocation now? */
10016 if (fixP->fx_addsy == NULL)
10018 #if defined (OBJ_COFF) && defined (TE_PE)
10019 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10022 /* Remember value for tc_gen_reloc. */
10023 fixP->fx_addnumber = value;
10024 /* Clear out the frag for now. */
10028 else if (use_rela_relocations)
10030 fixP->fx_no_overflow = 1;
10031 /* Remember value for tc_gen_reloc. */
10032 fixP->fx_addnumber = value;
10036 md_number_to_chars (p, value, fixP->fx_size);
10040 md_atof (int type, char *litP, int *sizeP)
10042 /* This outputs the LITTLENUMs in REVERSE order;
10043 in accord with the bigendian 386. */
10044 return ieee_md_atof (type, litP, sizeP, FALSE);
10047 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10050 output_invalid (int c)
10053 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10056 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10057 "(0x%x)", (unsigned char) c);
10058 return output_invalid_buf;
10061 /* REG_STRING starts *before* REGISTER_PREFIX. */
10063 static const reg_entry *
10064 parse_real_register (char *reg_string, char **end_op)
10066 char *s = reg_string;
10068 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10069 const reg_entry *r;
10071 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10072 if (*s == REGISTER_PREFIX)
10075 if (is_space_char (*s))
10078 p = reg_name_given;
10079 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10081 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10082 return (const reg_entry *) NULL;
10086 /* For naked regs, make sure that we are not dealing with an identifier.
10087 This prevents confusing an identifier like `eax_var' with register
10089 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10090 return (const reg_entry *) NULL;
10094 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10096 /* Handle floating point regs, allowing spaces in the (i) part. */
10097 if (r == i386_regtab /* %st is first entry of table */)
10099 if (is_space_char (*s))
10104 if (is_space_char (*s))
10106 if (*s >= '0' && *s <= '7')
10108 int fpr = *s - '0';
10110 if (is_space_char (*s))
10115 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10120 /* We have "%st(" then garbage. */
10121 return (const reg_entry *) NULL;
10125 if (r == NULL || allow_pseudo_reg)
10128 if (operand_type_all_zero (&r->reg_type))
10129 return (const reg_entry *) NULL;
10131 if ((r->reg_type.bitfield.dword
10132 || r->reg_type.bitfield.sreg3
10133 || r->reg_type.bitfield.control
10134 || r->reg_type.bitfield.debug
10135 || r->reg_type.bitfield.test)
10136 && !cpu_arch_flags.bitfield.cpui386)
10137 return (const reg_entry *) NULL;
10139 if (r->reg_type.bitfield.tbyte
10140 && !cpu_arch_flags.bitfield.cpu8087
10141 && !cpu_arch_flags.bitfield.cpu287
10142 && !cpu_arch_flags.bitfield.cpu387)
10143 return (const reg_entry *) NULL;
10145 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10146 return (const reg_entry *) NULL;
10148 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10149 return (const reg_entry *) NULL;
10151 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10152 return (const reg_entry *) NULL;
10154 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10155 return (const reg_entry *) NULL;
10157 if (r->reg_type.bitfield.regmask
10158 && !cpu_arch_flags.bitfield.cpuregmask)
10159 return (const reg_entry *) NULL;
10161 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10162 if (!allow_index_reg
10163 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10164 return (const reg_entry *) NULL;
10166 /* Upper 16 vector register is only available with VREX in 64bit
10168 if ((r->reg_flags & RegVRex))
10170 if (i.vec_encoding == vex_encoding_default)
10171 i.vec_encoding = vex_encoding_evex;
10173 if (!cpu_arch_flags.bitfield.cpuvrex
10174 || i.vec_encoding != vex_encoding_evex
10175 || flag_code != CODE_64BIT)
10176 return (const reg_entry *) NULL;
10179 if (((r->reg_flags & (RegRex64 | RegRex))
10180 || r->reg_type.bitfield.qword)
10181 && (!cpu_arch_flags.bitfield.cpulm
10182 || !operand_type_equal (&r->reg_type, &control))
10183 && flag_code != CODE_64BIT)
10184 return (const reg_entry *) NULL;
10186 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10187 return (const reg_entry *) NULL;
10192 /* REG_STRING starts *before* REGISTER_PREFIX. */
10194 static const reg_entry *
10195 parse_register (char *reg_string, char **end_op)
10197 const reg_entry *r;
10199 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10200 r = parse_real_register (reg_string, end_op);
10205 char *save = input_line_pointer;
10209 input_line_pointer = reg_string;
10210 c = get_symbol_name (®_string);
10211 symbolP = symbol_find (reg_string);
10212 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10214 const expressionS *e = symbol_get_value_expression (symbolP);
10216 know (e->X_op == O_register);
10217 know (e->X_add_number >= 0
10218 && (valueT) e->X_add_number < i386_regtab_size);
10219 r = i386_regtab + e->X_add_number;
10220 if ((r->reg_flags & RegVRex))
10221 i.vec_encoding = vex_encoding_evex;
10222 *end_op = input_line_pointer;
10224 *input_line_pointer = c;
10225 input_line_pointer = save;
10231 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10233 const reg_entry *r;
10234 char *end = input_line_pointer;
10237 r = parse_register (name, &input_line_pointer);
10238 if (r && end <= input_line_pointer)
10240 *nextcharP = *input_line_pointer;
10241 *input_line_pointer = 0;
10242 e->X_op = O_register;
10243 e->X_add_number = r - i386_regtab;
10246 input_line_pointer = end;
10248 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10252 md_operand (expressionS *e)
10255 const reg_entry *r;
10257 switch (*input_line_pointer)
10259 case REGISTER_PREFIX:
10260 r = parse_real_register (input_line_pointer, &end);
10263 e->X_op = O_register;
10264 e->X_add_number = r - i386_regtab;
10265 input_line_pointer = end;
10270 gas_assert (intel_syntax);
10271 end = input_line_pointer++;
10273 if (*input_line_pointer == ']')
10275 ++input_line_pointer;
10276 e->X_op_symbol = make_expr_symbol (e);
10277 e->X_add_symbol = NULL;
10278 e->X_add_number = 0;
10283 e->X_op = O_absent;
10284 input_line_pointer = end;
10291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10292 const char *md_shortopts = "kVQ:sqnO::";
10294 const char *md_shortopts = "qnO::";
10297 #define OPTION_32 (OPTION_MD_BASE + 0)
10298 #define OPTION_64 (OPTION_MD_BASE + 1)
10299 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10300 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10301 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10302 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10303 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10304 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10305 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10306 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10307 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10308 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10309 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10310 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10311 #define OPTION_X32 (OPTION_MD_BASE + 14)
10312 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10313 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10314 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10315 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10316 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10317 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10318 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10319 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10320 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10321 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10322 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10324 struct option md_longopts[] =
10326 {"32", no_argument, NULL, OPTION_32},
10327 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10328 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10329 {"64", no_argument, NULL, OPTION_64},
10331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10332 {"x32", no_argument, NULL, OPTION_X32},
10333 {"mshared", no_argument, NULL, OPTION_MSHARED},
10335 {"divide", no_argument, NULL, OPTION_DIVIDE},
10336 {"march", required_argument, NULL, OPTION_MARCH},
10337 {"mtune", required_argument, NULL, OPTION_MTUNE},
10338 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10339 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10340 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10341 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10342 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10343 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10344 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10345 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10346 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10347 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10348 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10349 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10350 # if defined (TE_PE) || defined (TE_PEP)
10351 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10353 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10354 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10355 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10356 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10357 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10358 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10359 {NULL, no_argument, NULL, 0}
10361 size_t md_longopts_size = sizeof (md_longopts);
10364 md_parse_option (int c, const char *arg)
10367 char *arch, *next, *saved;
10372 optimize_align_code = 0;
10376 quiet_warnings = 1;
10379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10380 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10381 should be emitted or not. FIXME: Not implemented. */
10385 /* -V: SVR4 argument to print version ID. */
10387 print_version_id ();
10390 /* -k: Ignore for FreeBSD compatibility. */
10395 /* -s: On i386 Solaris, this tells the native assembler to use
10396 .stab instead of .stab.excl. We always use .stab anyhow. */
10399 case OPTION_MSHARED:
10403 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10404 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10407 const char **list, **l;
10409 list = bfd_target_list ();
10410 for (l = list; *l != NULL; l++)
10411 if (CONST_STRNEQ (*l, "elf64-x86-64")
10412 || strcmp (*l, "coff-x86-64") == 0
10413 || strcmp (*l, "pe-x86-64") == 0
10414 || strcmp (*l, "pei-x86-64") == 0
10415 || strcmp (*l, "mach-o-x86-64") == 0)
10417 default_arch = "x86_64";
10421 as_fatal (_("no compiled in support for x86_64"));
10427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10431 const char **list, **l;
10433 list = bfd_target_list ();
10434 for (l = list; *l != NULL; l++)
10435 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10437 default_arch = "x86_64:32";
10441 as_fatal (_("no compiled in support for 32bit x86_64"));
10445 as_fatal (_("32bit x86_64 is only supported for ELF"));
10450 default_arch = "i386";
10453 case OPTION_DIVIDE:
10454 #ifdef SVR4_COMMENT_CHARS
10459 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10461 for (s = i386_comment_chars; *s != '\0'; s++)
10465 i386_comment_chars = n;
10471 saved = xstrdup (arg);
10473 /* Allow -march=+nosse. */
10479 as_fatal (_("invalid -march= option: `%s'"), arg);
10480 next = strchr (arch, '+');
10483 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10485 if (strcmp (arch, cpu_arch [j].name) == 0)
10488 if (! cpu_arch[j].flags.bitfield.cpui386)
10491 cpu_arch_name = cpu_arch[j].name;
10492 cpu_sub_arch_name = NULL;
10493 cpu_arch_flags = cpu_arch[j].flags;
10494 cpu_arch_isa = cpu_arch[j].type;
10495 cpu_arch_isa_flags = cpu_arch[j].flags;
10496 if (!cpu_arch_tune_set)
10498 cpu_arch_tune = cpu_arch_isa;
10499 cpu_arch_tune_flags = cpu_arch_isa_flags;
10503 else if (*cpu_arch [j].name == '.'
10504 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10506 /* ISA extension. */
10507 i386_cpu_flags flags;
10509 flags = cpu_flags_or (cpu_arch_flags,
10510 cpu_arch[j].flags);
10512 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10514 if (cpu_sub_arch_name)
10516 char *name = cpu_sub_arch_name;
10517 cpu_sub_arch_name = concat (name,
10519 (const char *) NULL);
10523 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10524 cpu_arch_flags = flags;
10525 cpu_arch_isa_flags = flags;
10531 if (j >= ARRAY_SIZE (cpu_arch))
10533 /* Disable an ISA extension. */
10534 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10535 if (strcmp (arch, cpu_noarch [j].name) == 0)
10537 i386_cpu_flags flags;
10539 flags = cpu_flags_and_not (cpu_arch_flags,
10540 cpu_noarch[j].flags);
10541 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10543 if (cpu_sub_arch_name)
10545 char *name = cpu_sub_arch_name;
10546 cpu_sub_arch_name = concat (arch,
10547 (const char *) NULL);
10551 cpu_sub_arch_name = xstrdup (arch);
10552 cpu_arch_flags = flags;
10553 cpu_arch_isa_flags = flags;
10558 if (j >= ARRAY_SIZE (cpu_noarch))
10559 j = ARRAY_SIZE (cpu_arch);
10562 if (j >= ARRAY_SIZE (cpu_arch))
10563 as_fatal (_("invalid -march= option: `%s'"), arg);
10567 while (next != NULL);
10573 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10574 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10576 if (strcmp (arg, cpu_arch [j].name) == 0)
10578 cpu_arch_tune_set = 1;
10579 cpu_arch_tune = cpu_arch [j].type;
10580 cpu_arch_tune_flags = cpu_arch[j].flags;
10584 if (j >= ARRAY_SIZE (cpu_arch))
10585 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10588 case OPTION_MMNEMONIC:
10589 if (strcasecmp (arg, "att") == 0)
10590 intel_mnemonic = 0;
10591 else if (strcasecmp (arg, "intel") == 0)
10592 intel_mnemonic = 1;
10594 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10597 case OPTION_MSYNTAX:
10598 if (strcasecmp (arg, "att") == 0)
10600 else if (strcasecmp (arg, "intel") == 0)
10603 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10606 case OPTION_MINDEX_REG:
10607 allow_index_reg = 1;
10610 case OPTION_MNAKED_REG:
10611 allow_naked_reg = 1;
10614 case OPTION_MOLD_GCC:
10618 case OPTION_MSSE2AVX:
10622 case OPTION_MSSE_CHECK:
10623 if (strcasecmp (arg, "error") == 0)
10624 sse_check = check_error;
10625 else if (strcasecmp (arg, "warning") == 0)
10626 sse_check = check_warning;
10627 else if (strcasecmp (arg, "none") == 0)
10628 sse_check = check_none;
10630 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10633 case OPTION_MOPERAND_CHECK:
10634 if (strcasecmp (arg, "error") == 0)
10635 operand_check = check_error;
10636 else if (strcasecmp (arg, "warning") == 0)
10637 operand_check = check_warning;
10638 else if (strcasecmp (arg, "none") == 0)
10639 operand_check = check_none;
10641 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10644 case OPTION_MAVXSCALAR:
10645 if (strcasecmp (arg, "128") == 0)
10646 avxscalar = vex128;
10647 else if (strcasecmp (arg, "256") == 0)
10648 avxscalar = vex256;
10650 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10653 case OPTION_MADD_BND_PREFIX:
10654 add_bnd_prefix = 1;
10657 case OPTION_MEVEXLIG:
10658 if (strcmp (arg, "128") == 0)
10659 evexlig = evexl128;
10660 else if (strcmp (arg, "256") == 0)
10661 evexlig = evexl256;
10662 else if (strcmp (arg, "512") == 0)
10663 evexlig = evexl512;
10665 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10668 case OPTION_MEVEXRCIG:
10669 if (strcmp (arg, "rne") == 0)
10671 else if (strcmp (arg, "rd") == 0)
10673 else if (strcmp (arg, "ru") == 0)
10675 else if (strcmp (arg, "rz") == 0)
10678 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10681 case OPTION_MEVEXWIG:
10682 if (strcmp (arg, "0") == 0)
10684 else if (strcmp (arg, "1") == 0)
10687 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10690 # if defined (TE_PE) || defined (TE_PEP)
10691 case OPTION_MBIG_OBJ:
10696 case OPTION_MOMIT_LOCK_PREFIX:
10697 if (strcasecmp (arg, "yes") == 0)
10698 omit_lock_prefix = 1;
10699 else if (strcasecmp (arg, "no") == 0)
10700 omit_lock_prefix = 0;
10702 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10705 case OPTION_MFENCE_AS_LOCK_ADD:
10706 if (strcasecmp (arg, "yes") == 0)
10708 else if (strcasecmp (arg, "no") == 0)
10711 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10714 case OPTION_MRELAX_RELOCATIONS:
10715 if (strcasecmp (arg, "yes") == 0)
10716 generate_relax_relocations = 1;
10717 else if (strcasecmp (arg, "no") == 0)
10718 generate_relax_relocations = 0;
10720 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10723 case OPTION_MAMD64:
10727 case OPTION_MINTEL64:
10735 /* Turn off -Os. */
10736 optimize_for_space = 0;
10738 else if (*arg == 's')
10740 optimize_for_space = 1;
10741 /* Turn on all encoding optimizations. */
10746 optimize = atoi (arg);
10747 /* Turn off -Os. */
10748 optimize_for_space = 0;
10758 #define MESSAGE_TEMPLATE \
10762 output_message (FILE *stream, char *p, char *message, char *start,
10763 int *left_p, const char *name, int len)
10765 int size = sizeof (MESSAGE_TEMPLATE);
10766 int left = *left_p;
10768 /* Reserve 2 spaces for ", " or ",\0" */
10771 /* Check if there is any room. */
10779 p = mempcpy (p, name, len);
10783 /* Output the current message now and start a new one. */
10786 fprintf (stream, "%s\n", message);
10788 left = size - (start - message) - len - 2;
10790 gas_assert (left >= 0);
10792 p = mempcpy (p, name, len);
10800 show_arch (FILE *stream, int ext, int check)
10802 static char message[] = MESSAGE_TEMPLATE;
10803 char *start = message + 27;
10805 int size = sizeof (MESSAGE_TEMPLATE);
10812 left = size - (start - message);
10813 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10815 /* Should it be skipped? */
10816 if (cpu_arch [j].skip)
10819 name = cpu_arch [j].name;
10820 len = cpu_arch [j].len;
10823 /* It is an extension. Skip if we aren't asked to show it. */
10834 /* It is an processor. Skip if we show only extension. */
10837 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10839 /* It is an impossible processor - skip. */
10843 p = output_message (stream, p, message, start, &left, name, len);
10846 /* Display disabled extensions. */
10848 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10850 name = cpu_noarch [j].name;
10851 len = cpu_noarch [j].len;
10852 p = output_message (stream, p, message, start, &left, name,
10857 fprintf (stream, "%s\n", message);
10861 md_show_usage (FILE *stream)
10863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10864 fprintf (stream, _("\
10866 -V print assembler version number\n\
10869 fprintf (stream, _("\
10870 -n Do not optimize code alignment\n\
10871 -q quieten some warnings\n"));
10872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10873 fprintf (stream, _("\
10876 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10877 || defined (TE_PE) || defined (TE_PEP))
10878 fprintf (stream, _("\
10879 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10881 #ifdef SVR4_COMMENT_CHARS
10882 fprintf (stream, _("\
10883 --divide do not treat `/' as a comment character\n"));
10885 fprintf (stream, _("\
10886 --divide ignored\n"));
10888 fprintf (stream, _("\
10889 -march=CPU[,+EXTENSION...]\n\
10890 generate code for CPU and EXTENSION, CPU is one of:\n"));
10891 show_arch (stream, 0, 1);
10892 fprintf (stream, _("\
10893 EXTENSION is combination of:\n"));
10894 show_arch (stream, 1, 0);
10895 fprintf (stream, _("\
10896 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10897 show_arch (stream, 0, 0);
10898 fprintf (stream, _("\
10899 -msse2avx encode SSE instructions with VEX prefix\n"));
10900 fprintf (stream, _("\
10901 -msse-check=[none|error|warning]\n\
10902 check SSE instructions\n"));
10903 fprintf (stream, _("\
10904 -moperand-check=[none|error|warning]\n\
10905 check operand combinations for validity\n"));
10906 fprintf (stream, _("\
10907 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10909 fprintf (stream, _("\
10910 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10912 fprintf (stream, _("\
10913 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10914 for EVEX.W bit ignored instructions\n"));
10915 fprintf (stream, _("\
10916 -mevexrcig=[rne|rd|ru|rz]\n\
10917 encode EVEX instructions with specific EVEX.RC value\n\
10918 for SAE-only ignored instructions\n"));
10919 fprintf (stream, _("\
10920 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10921 fprintf (stream, _("\
10922 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10923 fprintf (stream, _("\
10924 -mindex-reg support pseudo index registers\n"));
10925 fprintf (stream, _("\
10926 -mnaked-reg don't require `%%' prefix for registers\n"));
10927 fprintf (stream, _("\
10928 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10929 fprintf (stream, _("\
10930 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10931 fprintf (stream, _("\
10932 -mshared disable branch optimization for shared code\n"));
10933 # if defined (TE_PE) || defined (TE_PEP)
10934 fprintf (stream, _("\
10935 -mbig-obj generate big object files\n"));
10937 fprintf (stream, _("\
10938 -momit-lock-prefix=[no|yes]\n\
10939 strip all lock prefixes\n"));
10940 fprintf (stream, _("\
10941 -mfence-as-lock-add=[no|yes]\n\
10942 encode lfence, mfence and sfence as\n\
10943 lock addl $0x0, (%%{re}sp)\n"));
10944 fprintf (stream, _("\
10945 -mrelax-relocations=[no|yes]\n\
10946 generate relax relocations\n"));
10947 fprintf (stream, _("\
10948 -mamd64 accept only AMD64 ISA\n"));
10949 fprintf (stream, _("\
10950 -mintel64 accept only Intel64 ISA\n"));
10953 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10954 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10955 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10957 /* Pick the target format to use. */
10960 i386_target_format (void)
10962 if (!strncmp (default_arch, "x86_64", 6))
10964 update_code_flag (CODE_64BIT, 1);
10965 if (default_arch[6] == '\0')
10966 x86_elf_abi = X86_64_ABI;
10968 x86_elf_abi = X86_64_X32_ABI;
10970 else if (!strcmp (default_arch, "i386"))
10971 update_code_flag (CODE_32BIT, 1);
10972 else if (!strcmp (default_arch, "iamcu"))
10974 update_code_flag (CODE_32BIT, 1);
10975 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10977 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10978 cpu_arch_name = "iamcu";
10979 cpu_sub_arch_name = NULL;
10980 cpu_arch_flags = iamcu_flags;
10981 cpu_arch_isa = PROCESSOR_IAMCU;
10982 cpu_arch_isa_flags = iamcu_flags;
10983 if (!cpu_arch_tune_set)
10985 cpu_arch_tune = cpu_arch_isa;
10986 cpu_arch_tune_flags = cpu_arch_isa_flags;
10989 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10990 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10994 as_fatal (_("unknown architecture"));
10996 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10997 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10998 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10999 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11001 switch (OUTPUT_FLAVOR)
11003 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11004 case bfd_target_aout_flavour:
11005 return AOUT_TARGET_FORMAT;
11007 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11008 # if defined (TE_PE) || defined (TE_PEP)
11009 case bfd_target_coff_flavour:
11010 if (flag_code == CODE_64BIT)
11011 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11014 # elif defined (TE_GO32)
11015 case bfd_target_coff_flavour:
11016 return "coff-go32";
11018 case bfd_target_coff_flavour:
11019 return "coff-i386";
11022 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11023 case bfd_target_elf_flavour:
11025 const char *format;
11027 switch (x86_elf_abi)
11030 format = ELF_TARGET_FORMAT;
11033 use_rela_relocations = 1;
11035 format = ELF_TARGET_FORMAT64;
11037 case X86_64_X32_ABI:
11038 use_rela_relocations = 1;
11040 disallow_64bit_reloc = 1;
11041 format = ELF_TARGET_FORMAT32;
11044 if (cpu_arch_isa == PROCESSOR_L1OM)
11046 if (x86_elf_abi != X86_64_ABI)
11047 as_fatal (_("Intel L1OM is 64bit only"));
11048 return ELF_TARGET_L1OM_FORMAT;
11050 else if (cpu_arch_isa == PROCESSOR_K1OM)
11052 if (x86_elf_abi != X86_64_ABI)
11053 as_fatal (_("Intel K1OM is 64bit only"));
11054 return ELF_TARGET_K1OM_FORMAT;
11056 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11058 if (x86_elf_abi != I386_ABI)
11059 as_fatal (_("Intel MCU is 32bit only"));
11060 return ELF_TARGET_IAMCU_FORMAT;
11066 #if defined (OBJ_MACH_O)
11067 case bfd_target_mach_o_flavour:
11068 if (flag_code == CODE_64BIT)
11070 use_rela_relocations = 1;
11072 return "mach-o-x86-64";
11075 return "mach-o-i386";
11083 #endif /* OBJ_MAYBE_ more than one */
11086 md_undefined_symbol (char *name)
11088 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11089 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11090 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11091 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11095 if (symbol_find (name))
11096 as_bad (_("GOT already in symbol table"));
11097 GOT_symbol = symbol_new (name, undefined_section,
11098 (valueT) 0, &zero_address_frag);
11105 /* Round up a section size to the appropriate boundary. */
11108 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11110 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11111 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11113 /* For a.out, force the section size to be aligned. If we don't do
11114 this, BFD will align it for us, but it will not write out the
11115 final bytes of the section. This may be a bug in BFD, but it is
11116 easier to fix it here since that is how the other a.out targets
11120 align = bfd_get_section_alignment (stdoutput, segment);
11121 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11128 /* On the i386, PC-relative offsets are relative to the start of the
11129 next instruction. That is, the address of the offset, plus its
11130 size, since the offset is always the last part of the insn. */
11133 md_pcrel_from (fixS *fixP)
11135 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11141 s_bss (int ignore ATTRIBUTE_UNUSED)
11145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11147 obj_elf_section_change_hook ();
11149 temp = get_absolute_expression ();
11150 subseg_set (bss_section, (subsegT) temp);
11151 demand_empty_rest_of_line ();
11157 i386_validate_fix (fixS *fixp)
11159 if (fixp->fx_subsy)
11161 if (fixp->fx_subsy == GOT_symbol)
11163 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11168 if (fixp->fx_tcbit2)
11169 fixp->fx_r_type = (fixp->fx_tcbit
11170 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11171 : BFD_RELOC_X86_64_GOTPCRELX);
11174 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11179 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11181 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11183 fixp->fx_subsy = 0;
11186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11187 else if (!object_64bit)
11189 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11190 && fixp->fx_tcbit2)
11191 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11197 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11200 bfd_reloc_code_real_type code;
11202 switch (fixp->fx_r_type)
11204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11205 case BFD_RELOC_SIZE32:
11206 case BFD_RELOC_SIZE64:
11207 if (S_IS_DEFINED (fixp->fx_addsy)
11208 && !S_IS_EXTERNAL (fixp->fx_addsy))
11210 /* Resolve size relocation against local symbol to size of
11211 the symbol plus addend. */
11212 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11213 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11214 && !fits_in_unsigned_long (value))
11215 as_bad_where (fixp->fx_file, fixp->fx_line,
11216 _("symbol size computation overflow"));
11217 fixp->fx_addsy = NULL;
11218 fixp->fx_subsy = NULL;
11219 md_apply_fix (fixp, (valueT *) &value, NULL);
11223 /* Fall through. */
11225 case BFD_RELOC_X86_64_PLT32:
11226 case BFD_RELOC_X86_64_GOT32:
11227 case BFD_RELOC_X86_64_GOTPCREL:
11228 case BFD_RELOC_X86_64_GOTPCRELX:
11229 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11230 case BFD_RELOC_386_PLT32:
11231 case BFD_RELOC_386_GOT32:
11232 case BFD_RELOC_386_GOT32X:
11233 case BFD_RELOC_386_GOTOFF:
11234 case BFD_RELOC_386_GOTPC:
11235 case BFD_RELOC_386_TLS_GD:
11236 case BFD_RELOC_386_TLS_LDM:
11237 case BFD_RELOC_386_TLS_LDO_32:
11238 case BFD_RELOC_386_TLS_IE_32:
11239 case BFD_RELOC_386_TLS_IE:
11240 case BFD_RELOC_386_TLS_GOTIE:
11241 case BFD_RELOC_386_TLS_LE_32:
11242 case BFD_RELOC_386_TLS_LE:
11243 case BFD_RELOC_386_TLS_GOTDESC:
11244 case BFD_RELOC_386_TLS_DESC_CALL:
11245 case BFD_RELOC_X86_64_TLSGD:
11246 case BFD_RELOC_X86_64_TLSLD:
11247 case BFD_RELOC_X86_64_DTPOFF32:
11248 case BFD_RELOC_X86_64_DTPOFF64:
11249 case BFD_RELOC_X86_64_GOTTPOFF:
11250 case BFD_RELOC_X86_64_TPOFF32:
11251 case BFD_RELOC_X86_64_TPOFF64:
11252 case BFD_RELOC_X86_64_GOTOFF64:
11253 case BFD_RELOC_X86_64_GOTPC32:
11254 case BFD_RELOC_X86_64_GOT64:
11255 case BFD_RELOC_X86_64_GOTPCREL64:
11256 case BFD_RELOC_X86_64_GOTPC64:
11257 case BFD_RELOC_X86_64_GOTPLT64:
11258 case BFD_RELOC_X86_64_PLTOFF64:
11259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11260 case BFD_RELOC_X86_64_TLSDESC_CALL:
11261 case BFD_RELOC_RVA:
11262 case BFD_RELOC_VTABLE_ENTRY:
11263 case BFD_RELOC_VTABLE_INHERIT:
11265 case BFD_RELOC_32_SECREL:
11267 code = fixp->fx_r_type;
11269 case BFD_RELOC_X86_64_32S:
11270 if (!fixp->fx_pcrel)
11272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11273 code = fixp->fx_r_type;
11276 /* Fall through. */
11278 if (fixp->fx_pcrel)
11280 switch (fixp->fx_size)
11283 as_bad_where (fixp->fx_file, fixp->fx_line,
11284 _("can not do %d byte pc-relative relocation"),
11286 code = BFD_RELOC_32_PCREL;
11288 case 1: code = BFD_RELOC_8_PCREL; break;
11289 case 2: code = BFD_RELOC_16_PCREL; break;
11290 case 4: code = BFD_RELOC_32_PCREL; break;
11292 case 8: code = BFD_RELOC_64_PCREL; break;
11298 switch (fixp->fx_size)
11301 as_bad_where (fixp->fx_file, fixp->fx_line,
11302 _("can not do %d byte relocation"),
11304 code = BFD_RELOC_32;
11306 case 1: code = BFD_RELOC_8; break;
11307 case 2: code = BFD_RELOC_16; break;
11308 case 4: code = BFD_RELOC_32; break;
11310 case 8: code = BFD_RELOC_64; break;
11317 if ((code == BFD_RELOC_32
11318 || code == BFD_RELOC_32_PCREL
11319 || code == BFD_RELOC_X86_64_32S)
11321 && fixp->fx_addsy == GOT_symbol)
11324 code = BFD_RELOC_386_GOTPC;
11326 code = BFD_RELOC_X86_64_GOTPC32;
11328 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11330 && fixp->fx_addsy == GOT_symbol)
11332 code = BFD_RELOC_X86_64_GOTPC64;
11335 rel = XNEW (arelent);
11336 rel->sym_ptr_ptr = XNEW (asymbol *);
11337 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11339 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11341 if (!use_rela_relocations)
11343 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11344 vtable entry to be used in the relocation's section offset. */
11345 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11346 rel->address = fixp->fx_offset;
11347 #if defined (OBJ_COFF) && defined (TE_PE)
11348 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11349 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11354 /* Use the rela in 64bit mode. */
11357 if (disallow_64bit_reloc)
11360 case BFD_RELOC_X86_64_DTPOFF64:
11361 case BFD_RELOC_X86_64_TPOFF64:
11362 case BFD_RELOC_64_PCREL:
11363 case BFD_RELOC_X86_64_GOTOFF64:
11364 case BFD_RELOC_X86_64_GOT64:
11365 case BFD_RELOC_X86_64_GOTPCREL64:
11366 case BFD_RELOC_X86_64_GOTPC64:
11367 case BFD_RELOC_X86_64_GOTPLT64:
11368 case BFD_RELOC_X86_64_PLTOFF64:
11369 as_bad_where (fixp->fx_file, fixp->fx_line,
11370 _("cannot represent relocation type %s in x32 mode"),
11371 bfd_get_reloc_code_name (code));
11377 if (!fixp->fx_pcrel)
11378 rel->addend = fixp->fx_offset;
11382 case BFD_RELOC_X86_64_PLT32:
11383 case BFD_RELOC_X86_64_GOT32:
11384 case BFD_RELOC_X86_64_GOTPCREL:
11385 case BFD_RELOC_X86_64_GOTPCRELX:
11386 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11387 case BFD_RELOC_X86_64_TLSGD:
11388 case BFD_RELOC_X86_64_TLSLD:
11389 case BFD_RELOC_X86_64_GOTTPOFF:
11390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11391 case BFD_RELOC_X86_64_TLSDESC_CALL:
11392 rel->addend = fixp->fx_offset - fixp->fx_size;
11395 rel->addend = (section->vma
11397 + fixp->fx_addnumber
11398 + md_pcrel_from (fixp));
11403 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11404 if (rel->howto == NULL)
11406 as_bad_where (fixp->fx_file, fixp->fx_line,
11407 _("cannot represent relocation type %s"),
11408 bfd_get_reloc_code_name (code));
11409 /* Set howto to a garbage value so that we can keep going. */
11410 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11411 gas_assert (rel->howto != NULL);
11417 #include "tc-i386-intel.c"
11420 tc_x86_parse_to_dw2regnum (expressionS *exp)
11422 int saved_naked_reg;
11423 char saved_register_dot;
11425 saved_naked_reg = allow_naked_reg;
11426 allow_naked_reg = 1;
11427 saved_register_dot = register_chars['.'];
11428 register_chars['.'] = '.';
11429 allow_pseudo_reg = 1;
11430 expression_and_evaluate (exp);
11431 allow_pseudo_reg = 0;
11432 register_chars['.'] = saved_register_dot;
11433 allow_naked_reg = saved_naked_reg;
11435 if (exp->X_op == O_register && exp->X_add_number >= 0)
11437 if ((addressT) exp->X_add_number < i386_regtab_size)
11439 exp->X_op = O_constant;
11440 exp->X_add_number = i386_regtab[exp->X_add_number]
11441 .dw2_regnum[flag_code >> 1];
11444 exp->X_op = O_illegal;
11449 tc_x86_frame_initial_instructions (void)
11451 static unsigned int sp_regno[2];
11453 if (!sp_regno[flag_code >> 1])
11455 char *saved_input = input_line_pointer;
11456 char sp[][4] = {"esp", "rsp"};
11459 input_line_pointer = sp[flag_code >> 1];
11460 tc_x86_parse_to_dw2regnum (&exp);
11461 gas_assert (exp.X_op == O_constant);
11462 sp_regno[flag_code >> 1] = exp.X_add_number;
11463 input_line_pointer = saved_input;
11466 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11467 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11471 x86_dwarf2_addr_size (void)
11473 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11474 if (x86_elf_abi == X86_64_X32_ABI)
11477 return bfd_arch_bits_per_address (stdoutput) / 8;
11481 i386_elf_section_type (const char *str, size_t len)
11483 if (flag_code == CODE_64BIT
11484 && len == sizeof ("unwind") - 1
11485 && strncmp (str, "unwind", 6) == 0)
11486 return SHT_X86_64_UNWIND;
11493 i386_solaris_fix_up_eh_frame (segT sec)
11495 if (flag_code == CODE_64BIT)
11496 elf_section_type (sec) = SHT_X86_64_UNWIND;
11502 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11506 exp.X_op = O_secrel;
11507 exp.X_add_symbol = symbol;
11508 exp.X_add_number = 0;
11509 emit_expr (&exp, size);
11513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11514 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11517 x86_64_section_letter (int letter, const char **ptr_msg)
11519 if (flag_code == CODE_64BIT)
11522 return SHF_X86_64_LARGE;
11524 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11527 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11532 x86_64_section_word (char *str, size_t len)
11534 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11535 return SHF_X86_64_LARGE;
11541 handle_large_common (int small ATTRIBUTE_UNUSED)
11543 if (flag_code != CODE_64BIT)
11545 s_comm_internal (0, elf_common_parse);
11546 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11550 static segT lbss_section;
11551 asection *saved_com_section_ptr = elf_com_section_ptr;
11552 asection *saved_bss_section = bss_section;
11554 if (lbss_section == NULL)
11556 flagword applicable;
11557 segT seg = now_seg;
11558 subsegT subseg = now_subseg;
11560 /* The .lbss section is for local .largecomm symbols. */
11561 lbss_section = subseg_new (".lbss", 0);
11562 applicable = bfd_applicable_section_flags (stdoutput);
11563 bfd_set_section_flags (stdoutput, lbss_section,
11564 applicable & SEC_ALLOC);
11565 seg_info (lbss_section)->bss = 1;
11567 subseg_set (seg, subseg);
11570 elf_com_section_ptr = &_bfd_elf_large_com_section;
11571 bss_section = lbss_section;
11573 s_comm_internal (0, elf_common_parse);
11575 elf_com_section_ptr = saved_com_section_ptr;
11576 bss_section = saved_bss_section;
11579 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */