1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static char *output_invalid PARAMS ((int c));
84 static int i386_operand PARAMS ((char *operand_string));
85 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86 static const reg_entry *parse_register PARAMS ((char *reg_string,
88 static char *parse_insn PARAMS ((char *, char *));
89 static char *parse_operands PARAMS ((char *, const char *));
90 static void swap_operands PARAMS ((void));
91 static void optimize_imm PARAMS ((void));
92 static void optimize_disp PARAMS ((void));
93 static int match_template PARAMS ((void));
94 static int check_string PARAMS ((void));
95 static int process_suffix PARAMS ((void));
96 static int check_byte_reg PARAMS ((void));
97 static int check_long_reg PARAMS ((void));
98 static int check_qword_reg PARAMS ((void));
99 static int check_word_reg PARAMS ((void));
100 static int finalize_imm PARAMS ((void));
101 static int process_operands PARAMS ((void));
102 static const seg_entry *build_modrm_byte PARAMS ((void));
103 static void output_insn PARAMS ((void));
104 static void output_branch PARAMS ((void));
105 static void output_jump PARAMS ((void));
106 static void output_interseg_jump PARAMS ((void));
107 static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109 static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
112 static void s_bss PARAMS ((int));
115 static const char *default_arch = DEFAULT_ARCH;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry *regs;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types[MAX_OPERANDS];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op[MAX_OPERANDS];
152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry *seg[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars[] = "/#";
225 const char line_separator_chars[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars[256];
238 static char register_chars[256];
239 static char operand_chars[256];
240 static char identifier_chars[256];
241 static char digit_chars[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack[32];
259 static char *save_stack_p;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates *current_templates;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions[2], im_expressions[2];
274 /* Current operand we are working on. */
275 static int this_operand;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code;
287 static int use_rela_relocations = 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names[] =
297 /* 1 for intel syntax,
299 static int intel_syntax = 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg = 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size = '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code = 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings = 0;
316 static const char *cpu_arch_name = NULL;
317 static const char *cpu_sub_arch_name = NULL;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion = 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS *GOT_symbol;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch[] = {
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
433 {".sse", CpuMMX|CpuMMX2|CpuSSE },
434 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
435 {".3dnow", CpuMMX|Cpu3dnow },
436 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
437 {".padlock", CpuPadLock },
441 const pseudo_typeS md_pseudo_table[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes, 0},
446 {"align", s_align_ptwo, 0},
448 {"arch", set_cpu_arch, 0},
452 {"ffloat", float_cons, 'f'},
453 {"dfloat", float_cons, 'd'},
454 {"tfloat", float_cons, 'x'},
456 {"noopt", s_ignore, 0},
457 {"optim", s_ignore, 0},
458 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
459 {"code16", set_code_flag, CODE_16BIT},
460 {"code32", set_code_flag, CODE_32BIT},
461 {"code64", set_code_flag, CODE_64BIT},
462 {"intel_syntax", set_intel_syntax, 1},
463 {"att_syntax", set_intel_syntax, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
465 {"loc", dwarf2_directive_loc, 0},
467 {"secrel32", pe_directive_secrel, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control *op_hash;
478 /* Hash table for register lookup. */
479 static struct hash_control *reg_hash;
482 i386_align_code (fragP, count)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1[] =
491 static const char f32_2[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt[] = {
545 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
546 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
548 static const char *const f16_patt[] = {
549 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
550 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
553 if (count <= 0 || count > 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code == CODE_64BIT)
561 int nnops = (count + 3) / 4;
562 int len = count / nnops;
563 int remains = count - nnops * len;
566 for (i = 0; i < remains; i++)
568 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
569 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
572 for (; i < nnops; i++)
574 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
575 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
580 if (flag_code == CODE_16BIT)
582 memcpy (fragP->fr_literal + fragP->fr_fix,
583 f16_patt[count - 1], count);
585 /* Adjust jump offset. */
586 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
589 memcpy (fragP->fr_literal + fragP->fr_fix,
590 f32_patt[count - 1], count);
591 fragP->fr_var = count;
594 static INLINE unsigned int
595 mode_from_disp_size (t)
598 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
602 fits_in_signed_byte (num)
605 return (num >= -128) && (num <= 127);
609 fits_in_unsigned_byte (num)
612 return (num & 0xff) == num;
616 fits_in_unsigned_word (num)
619 return (num & 0xffff) == num;
623 fits_in_signed_word (num)
626 return (-32768 <= num) && (num <= 32767);
629 fits_in_signed_long (num)
630 offsetT num ATTRIBUTE_UNUSED;
635 return (!(((offsetT) -1 << 31) & num)
636 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
646 return (num & (((offsetT) 2 << 31) - 1)) == num;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num)
654 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
664 return (fits_in_signed_byte (num)
665 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
666 : fits_in_unsigned_byte (num)
667 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
668 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
669 ? (Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_signed_long (num)
671 ? (Imm32 | Imm32S | Imm64)
672 : fits_in_unsigned_long (num)
678 offset_in_range (val, size)
686 case 1: mask = ((addressT) 1 << 8) - 1; break;
687 case 2: mask = ((addressT) 1 << 16) - 1; break;
688 case 4: mask = ((addressT) 2 << 31) - 1; break;
690 case 8: mask = ((addressT) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations)
697 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
698 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
700 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
702 char buf1[40], buf2[40];
704 sprint_value (buf1, val);
705 sprint_value (buf2, val & mask);
706 as_warn (_("%s shortened to %s"), buf1, buf2);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
722 && flag_code == CODE_64BIT)
730 case CS_PREFIX_OPCODE:
731 case DS_PREFIX_OPCODE:
732 case ES_PREFIX_OPCODE:
733 case FS_PREFIX_OPCODE:
734 case GS_PREFIX_OPCODE:
735 case SS_PREFIX_OPCODE:
739 case REPNE_PREFIX_OPCODE:
740 case REPE_PREFIX_OPCODE:
743 case LOCK_PREFIX_OPCODE:
751 case ADDR_PREFIX_OPCODE:
755 case DATA_PREFIX_OPCODE:
760 if (i.prefix[q] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i.prefix[q] = prefix;
772 set_code_flag (value)
776 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
777 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag)
793 flag_code = new_code_flag;
794 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
795 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
796 stackop_size = LONG_MNEM_SUFFIX;
800 set_intel_syntax (syntax_flag)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg = 0;
807 if (!is_end_of_line[(unsigned char) *input_line_pointer])
809 char *string = input_line_pointer;
810 int e = get_symbol_end ();
812 if (strcmp (string, "prefix") == 0)
814 else if (strcmp (string, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer = e;
820 demand_empty_rest_of_line ();
822 intel_syntax = syntax_flag;
824 if (ask_naked_reg == 0)
825 allow_naked_reg = (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
828 allow_naked_reg = (ask_naked_reg < 0);
830 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
831 identifier_chars['$'] = intel_syntax ? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED;
840 if (!is_end_of_line[(unsigned char) *input_line_pointer])
842 char *string = input_line_pointer;
843 int e = get_symbol_end ();
846 for (i = 0; cpu_arch[i].name; i++)
848 if (strcmp (string, cpu_arch[i].name) == 0)
852 cpu_arch_name = cpu_arch[i].name;
853 cpu_sub_arch_name = NULL;
854 cpu_arch_flags = (cpu_arch[i].flags
855 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
858 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
860 cpu_sub_arch_name = cpu_arch[i].name;
861 cpu_arch_flags |= cpu_arch[i].flags;
863 *input_line_pointer = e;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch[i].name)
869 as_bad (_("no such architecture: `%s'"), string);
871 *input_line_pointer = e;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion = 0;
877 if (*input_line_pointer == ','
878 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
880 char *string = ++input_line_pointer;
881 int e = get_symbol_end ();
883 if (strcmp (string, "nojumps") == 0)
884 no_cond_jump_promotion = 1;
885 else if (strcmp (string, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string);
890 *input_line_pointer = e;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch, "x86_64"))
900 return bfd_mach_x86_64;
901 else if (!strcmp (default_arch, "i386"))
902 return bfd_mach_i386_i386;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err;
912 /* Initialize op_hash hash table. */
913 op_hash = hash_new ();
916 const template *optab;
917 templates *core_optab;
919 /* Setup for loop. */
921 core_optab = (templates *) xmalloc (sizeof (templates));
922 core_optab->start = optab;
927 if (optab->name == NULL
928 || strcmp (optab->name, (optab - 1)->name) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab->end = optab;
933 hash_err = hash_insert (op_hash,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab->name == NULL)
944 core_optab = (templates *) xmalloc (sizeof (templates));
945 core_optab->start = optab;
950 /* Initialize reg_hash hash table. */
951 reg_hash = hash_new ();
953 const reg_entry *regtab;
955 for (regtab = i386_regtab;
956 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
959 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c = 0; c < 256; c++)
977 mnemonic_chars[c] = c;
978 register_chars[c] = c;
979 operand_chars[c] = c;
981 else if (ISLOWER (c))
983 mnemonic_chars[c] = c;
984 register_chars[c] = c;
985 operand_chars[c] = c;
987 else if (ISUPPER (c))
989 mnemonic_chars[c] = TOLOWER (c);
990 register_chars[c] = mnemonic_chars[c];
991 operand_chars[c] = c;
994 if (ISALPHA (c) || ISDIGIT (c))
995 identifier_chars[c] = c;
998 identifier_chars[c] = c;
999 operand_chars[c] = c;
1004 identifier_chars['@'] = '@';
1007 identifier_chars['?'] = '?';
1008 operand_chars['?'] = '?';
1010 digit_chars['-'] = '-';
1011 mnemonic_chars['-'] = '-';
1012 identifier_chars['_'] = '_';
1013 identifier_chars['.'] = '.';
1015 for (p = operand_special_chars; *p != '\0'; p++)
1016 operand_chars[(unsigned char) *p] = *p;
1019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1022 record_alignment (text_section, 2);
1023 record_alignment (data_section, 2);
1024 record_alignment (bss_section, 2);
1028 if (flag_code == CODE_64BIT)
1030 x86_dwarf2_return_column = 16;
1031 x86_cie_data_alignment = -8;
1035 x86_dwarf2_return_column = 8;
1036 x86_cie_data_alignment = -4;
1041 i386_print_statistics (file)
1044 hash_print_statistics (file, "i386 opcode", op_hash);
1045 hash_print_statistics (file, "i386 register", reg_hash);
1050 /* Debugging routines for md_assemble. */
1051 static void pi PARAMS ((char *, i386_insn *));
1052 static void pte PARAMS ((template *));
1053 static void pt PARAMS ((unsigned int));
1054 static void pe PARAMS ((expressionS *));
1055 static void ps PARAMS ((symbolS *));
1064 fprintf (stdout, "%s: template ", line);
1066 fprintf (stdout, " address: base %s index %s scale %x\n",
1067 x->base_reg ? x->base_reg->reg_name : "none",
1068 x->index_reg ? x->index_reg->reg_name : "none",
1069 x->log2_scale_factor);
1070 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1071 x->rm.mode, x->rm.reg, x->rm.regmem);
1072 fprintf (stdout, " sib: base %x index %x scale %x\n",
1073 x->sib.base, x->sib.index, x->sib.scale);
1074 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1075 (x->rex & REX_MODE64) != 0,
1076 (x->rex & REX_EXTX) != 0,
1077 (x->rex & REX_EXTY) != 0,
1078 (x->rex & REX_EXTZ) != 0);
1079 for (i = 0; i < x->operands; i++)
1081 fprintf (stdout, " #%d: ", i + 1);
1083 fprintf (stdout, "\n");
1085 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1086 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1087 if (x->types[i] & Imm)
1089 if (x->types[i] & Disp)
1090 pe (x->op[i].disps);
1099 fprintf (stdout, " %d operands ", t->operands);
1100 fprintf (stdout, "opcode %x ", t->base_opcode);
1101 if (t->extension_opcode != None)
1102 fprintf (stdout, "ext %x ", t->extension_opcode);
1103 if (t->opcode_modifier & D)
1104 fprintf (stdout, "D");
1105 if (t->opcode_modifier & W)
1106 fprintf (stdout, "W");
1107 fprintf (stdout, "\n");
1108 for (i = 0; i < t->operands; i++)
1110 fprintf (stdout, " #%d type ", i + 1);
1111 pt (t->operand_types[i]);
1112 fprintf (stdout, "\n");
1120 fprintf (stdout, " operation %d\n", e->X_op);
1121 fprintf (stdout, " add_number %ld (%lx)\n",
1122 (long) e->X_add_number, (long) e->X_add_number);
1123 if (e->X_add_symbol)
1125 fprintf (stdout, " add_symbol ");
1126 ps (e->X_add_symbol);
1127 fprintf (stdout, "\n");
1131 fprintf (stdout, " op_symbol ");
1132 ps (e->X_op_symbol);
1133 fprintf (stdout, "\n");
1141 fprintf (stdout, "%s type %s%s",
1143 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s)));
1153 static const type_names[] =
1166 { BaseIndex, "BaseIndex" },
1170 { Disp32S, "d32s" },
1172 { InOutPortReg, "InOutPortReg" },
1173 { ShiftCount, "ShiftCount" },
1174 { Control, "control reg" },
1175 { Test, "test reg" },
1176 { Debug, "debug reg" },
1177 { FloatReg, "FReg" },
1178 { FloatAcc, "FAcc" },
1182 { JumpAbsolute, "Jump Absolute" },
1193 const struct type_name *ty;
1195 for (ty = type_names; ty->mask; ty++)
1197 fprintf (stdout, "%s, ", ty->tname);
1201 #endif /* DEBUG386 */
1203 static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1206 static bfd_reloc_code_real_type
1207 reloc (size, pcrel, sign, other)
1211 bfd_reloc_code_real_type other;
1213 if (other != NO_RELOC)
1219 as_bad (_("There are no unsigned pc-relative relocations"));
1222 case 1: return BFD_RELOC_8_PCREL;
1223 case 2: return BFD_RELOC_16_PCREL;
1224 case 4: return BFD_RELOC_32_PCREL;
1225 case 8: return BFD_RELOC_64_PCREL;
1227 as_bad (_("can not do %d byte pc-relative relocation"), size);
1234 case 4: return BFD_RELOC_X86_64_32S;
1239 case 1: return BFD_RELOC_8;
1240 case 2: return BFD_RELOC_16;
1241 case 4: return BFD_RELOC_32;
1242 case 8: return BFD_RELOC_64;
1244 as_bad (_("can not do %s %d byte relocation"),
1245 sign ? "signed" : "unsigned", size);
1249 return BFD_RELOC_NONE;
1252 /* Here we decide which fixups can be adjusted to make them relative to
1253 the beginning of the section instead of the symbol. Basically we need
1254 to make sure that the dynamic relocations are done correctly, so in
1255 some cases we force the original symbol to be used. */
1258 tc_i386_fix_adjustable (fixP)
1259 fixS *fixP ATTRIBUTE_UNUSED;
1261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1262 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1265 /* Don't adjust pc-relative references to merge sections in 64-bit
1267 if (use_rela_relocations
1268 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1272 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1273 and changed later by validate_fix. */
1274 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1275 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1278 /* adjust_reloc_syms doesn't know about the GOT. */
1279 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1280 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1281 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1282 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1283 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1284 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1285 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1288 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1289 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1290 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1291 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1292 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1293 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1296 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1297 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1298 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1299 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1300 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1301 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1302 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1308 static int intel_float_operand PARAMS ((const char *mnemonic));
1311 intel_float_operand (mnemonic)
1312 const char *mnemonic;
1314 /* Note that the value returned is meaningful only for opcodes with (memory)
1315 operands, hence the code here is free to improperly handle opcodes that
1316 have no operands (for better performance and smaller code). */
1318 if (mnemonic[0] != 'f')
1319 return 0; /* non-math */
1321 switch (mnemonic[1])
1323 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1324 the fs segment override prefix not currently handled because no
1325 call path can make opcodes without operands get here */
1327 return 2 /* integer op */;
1329 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1330 return 3; /* fldcw/fldenv */
1333 if (mnemonic[2] != 'o' /* fnop */)
1334 return 3; /* non-waiting control op */
1337 if (mnemonic[2] == 's')
1338 return 3; /* frstor/frstpm */
1341 if (mnemonic[2] == 'a')
1342 return 3; /* fsave */
1343 if (mnemonic[2] == 't')
1345 switch (mnemonic[3])
1347 case 'c': /* fstcw */
1348 case 'd': /* fstdw */
1349 case 'e': /* fstenv */
1350 case 's': /* fsts[gw] */
1356 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1357 return 0; /* fxsave/fxrstor are not really math ops */
1364 /* This is the guts of the machine-dependent assembler. LINE points to a
1365 machine dependent instruction. This function is supposed to emit
1366 the frags/bytes it assembles to. */
1373 char mnemonic[MAX_MNEM_SIZE];
1375 /* Initialize globals. */
1376 memset (&i, '\0', sizeof (i));
1377 for (j = 0; j < MAX_OPERANDS; j++)
1378 i.reloc[j] = NO_RELOC;
1379 memset (disp_expressions, '\0', sizeof (disp_expressions));
1380 memset (im_expressions, '\0', sizeof (im_expressions));
1381 save_stack_p = save_stack;
1383 /* First parse an instruction mnemonic & call i386_operand for the operands.
1384 We assume that the scrubber has arranged it so that line[0] is the valid
1385 start of a (possibly prefixed) mnemonic. */
1387 line = parse_insn (line, mnemonic);
1391 line = parse_operands (line, mnemonic);
1395 /* Now we've parsed the mnemonic into a set of templates, and have the
1396 operands at hand. */
1398 /* All intel opcodes have reversed operands except for "bound" and
1399 "enter". We also don't reverse intersegment "jmp" and "call"
1400 instructions with 2 immediate operands so that the immediate segment
1401 precedes the offset, as it does when in AT&T mode. "enter" and the
1402 intersegment "jmp" and "call" instructions are the only ones that
1403 have two immediate operands. */
1404 if (intel_syntax && i.operands > 1
1405 && (strcmp (mnemonic, "bound") != 0)
1406 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1412 if (i.disp_operands)
1415 /* Next, we find a template that matches the given insn,
1416 making sure the overlap of the given operands types is consistent
1417 with the template operand types. */
1419 if (!match_template ())
1424 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1426 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1427 i.tm.base_opcode ^= FloatR;
1429 /* Zap movzx and movsx suffix. The suffix may have been set from
1430 "word ptr" or "byte ptr" on the source operand, but we'll use
1431 the suffix later to choose the destination register. */
1432 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1434 if (i.reg_operands < 2
1436 && (~i.tm.opcode_modifier
1443 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1449 if (i.tm.opcode_modifier & FWait)
1450 if (!add_prefix (FWAIT_OPCODE))
1453 /* Check string instruction segment overrides. */
1454 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1456 if (!check_string ())
1460 if (!process_suffix ())
1463 /* Make still unresolved immediate matches conform to size of immediate
1464 given in i.suffix. */
1465 if (!finalize_imm ())
1468 if (i.types[0] & Imm1)
1469 i.imm_operands = 0; /* kludge for shift insns. */
1470 if (i.types[0] & ImplicitRegister)
1472 if (i.types[1] & ImplicitRegister)
1474 if (i.types[2] & ImplicitRegister)
1477 if (i.tm.opcode_modifier & ImmExt)
1481 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1483 /* These Intel Prescott New Instructions have the fixed
1484 operands with an opcode suffix which is coded in the same
1485 place as an 8-bit immediate field would be. Here we check
1486 those operands and remove them afterwards. */
1489 for (x = 0; x < i.operands; x++)
1490 if (i.op[x].regs->reg_num != x)
1491 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1492 i.op[x].regs->reg_name, x + 1, i.tm.name);
1496 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1497 opcode suffix which is coded in the same place as an 8-bit
1498 immediate field would be. Here we fake an 8-bit immediate
1499 operand from the opcode suffix stored in tm.extension_opcode. */
1501 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1503 exp = &im_expressions[i.imm_operands++];
1504 i.op[i.operands].imms = exp;
1505 i.types[i.operands++] = Imm8;
1506 exp->X_op = O_constant;
1507 exp->X_add_number = i.tm.extension_opcode;
1508 i.tm.extension_opcode = None;
1511 /* For insns with operands there are more diddles to do to the opcode. */
1514 if (!process_operands ())
1517 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1519 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1520 as_warn (_("translating to `%sp'"), i.tm.name);
1523 /* Handle conversion of 'int $3' --> special int3 insn. */
1524 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1526 i.tm.base_opcode = INT3_OPCODE;
1530 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1531 && i.op[0].disps->X_op == O_constant)
1533 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1534 the absolute address given by the constant. Since ix86 jumps and
1535 calls are pc relative, we need to generate a reloc. */
1536 i.op[0].disps->X_add_symbol = &abs_symbol;
1537 i.op[0].disps->X_op = O_symbol;
1540 if ((i.tm.opcode_modifier & Rex64) != 0)
1541 i.rex |= REX_MODE64;
1543 /* For 8 bit registers we need an empty rex prefix. Also if the
1544 instruction already has a prefix, we need to convert old
1545 registers to new ones. */
1547 if (((i.types[0] & Reg8) != 0
1548 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1549 || ((i.types[1] & Reg8) != 0
1550 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1551 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1556 i.rex |= REX_OPCODE;
1557 for (x = 0; x < 2; x++)
1559 /* Look for 8 bit operand that uses old registers. */
1560 if ((i.types[x] & Reg8) != 0
1561 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1563 /* In case it is "hi" register, give up. */
1564 if (i.op[x].regs->reg_num > 3)
1565 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1566 i.op[x].regs->reg_name);
1568 /* Otherwise it is equivalent to the extended register.
1569 Since the encoding doesn't change this is merely
1570 cosmetic cleanup for debug output. */
1572 i.op[x].regs = i.op[x].regs + 8;
1578 add_prefix (REX_OPCODE | i.rex);
1580 /* We are ready to output the insn. */
1585 parse_insn (line, mnemonic)
1590 char *token_start = l;
1595 /* Non-zero if we found a prefix only acceptable with string insns. */
1596 const char *expecting_string_instruction = NULL;
1601 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1604 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1606 as_bad (_("no such instruction: `%s'"), token_start);
1611 if (!is_space_char (*l)
1612 && *l != END_OF_INSN
1614 || (*l != PREFIX_SEPARATOR
1617 as_bad (_("invalid character %s in mnemonic"),
1618 output_invalid (*l));
1621 if (token_start == l)
1623 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1624 as_bad (_("expecting prefix; got nothing"));
1626 as_bad (_("expecting mnemonic; got nothing"));
1630 /* Look up instruction (or prefix) via hash table. */
1631 current_templates = hash_find (op_hash, mnemonic);
1633 if (*l != END_OF_INSN
1634 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1635 && current_templates
1636 && (current_templates->start->opcode_modifier & IsPrefix))
1638 /* If we are in 16-bit mode, do not allow addr16 or data16.
1639 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1640 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1641 && flag_code != CODE_64BIT
1642 && (((current_templates->start->opcode_modifier & Size32) != 0)
1643 ^ (flag_code == CODE_16BIT)))
1645 as_bad (_("redundant %s prefix"),
1646 current_templates->start->name);
1649 /* Add prefix, checking for repeated prefixes. */
1650 switch (add_prefix (current_templates->start->base_opcode))
1655 expecting_string_instruction = current_templates->start->name;
1658 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1665 if (!current_templates)
1667 /* See if we can get a match by trimming off a suffix. */
1670 case WORD_MNEM_SUFFIX:
1671 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1672 i.suffix = SHORT_MNEM_SUFFIX;
1674 case BYTE_MNEM_SUFFIX:
1675 case QWORD_MNEM_SUFFIX:
1676 i.suffix = mnem_p[-1];
1678 current_templates = hash_find (op_hash, mnemonic);
1680 case SHORT_MNEM_SUFFIX:
1681 case LONG_MNEM_SUFFIX:
1684 i.suffix = mnem_p[-1];
1686 current_templates = hash_find (op_hash, mnemonic);
1694 if (intel_float_operand (mnemonic) == 1)
1695 i.suffix = SHORT_MNEM_SUFFIX;
1697 i.suffix = LONG_MNEM_SUFFIX;
1699 current_templates = hash_find (op_hash, mnemonic);
1703 if (!current_templates)
1705 as_bad (_("no such instruction: `%s'"), token_start);
1710 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1712 /* Check for a branch hint. We allow ",pt" and ",pn" for
1713 predict taken and predict not taken respectively.
1714 I'm not sure that branch hints actually do anything on loop
1715 and jcxz insns (JumpByte) for current Pentium4 chips. They
1716 may work in the future and it doesn't hurt to accept them
1718 if (l[0] == ',' && l[1] == 'p')
1722 if (!add_prefix (DS_PREFIX_OPCODE))
1726 else if (l[2] == 'n')
1728 if (!add_prefix (CS_PREFIX_OPCODE))
1734 /* Any other comma loses. */
1737 as_bad (_("invalid character %s in mnemonic"),
1738 output_invalid (*l));
1742 /* Check if instruction is supported on specified architecture. */
1744 for (t = current_templates->start; t < current_templates->end; ++t)
1746 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1747 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1749 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1752 if (!(supported & 2))
1754 as_bad (flag_code == CODE_64BIT
1755 ? _("`%s' is not supported in 64-bit mode")
1756 : _("`%s' is only supported in 64-bit mode"),
1757 current_templates->start->name);
1760 if (!(supported & 1))
1762 as_warn (_("`%s' is not supported on `%s%s'"),
1763 current_templates->start->name,
1765 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1767 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1769 as_warn (_("use .code16 to ensure correct addressing mode"));
1772 /* Check for rep/repne without a string instruction. */
1773 if (expecting_string_instruction)
1775 static templates override;
1777 for (t = current_templates->start; t < current_templates->end; ++t)
1778 if (t->opcode_modifier & IsString)
1780 if (t >= current_templates->end)
1782 as_bad (_("expecting string instruction after `%s'"),
1783 expecting_string_instruction);
1786 for (override.start = t; t < current_templates->end; ++t)
1787 if (!(t->opcode_modifier & IsString))
1790 current_templates = &override;
1797 parse_operands (l, mnemonic)
1799 const char *mnemonic;
1803 /* 1 if operand is pending after ','. */
1804 unsigned int expecting_operand = 0;
1806 /* Non-zero if operand parens not balanced. */
1807 unsigned int paren_not_balanced;
1809 while (*l != END_OF_INSN)
1811 /* Skip optional white space before operand. */
1812 if (is_space_char (*l))
1814 if (!is_operand_char (*l) && *l != END_OF_INSN)
1816 as_bad (_("invalid character %s before operand %d"),
1817 output_invalid (*l),
1821 token_start = l; /* after white space */
1822 paren_not_balanced = 0;
1823 while (paren_not_balanced || *l != ',')
1825 if (*l == END_OF_INSN)
1827 if (paren_not_balanced)
1830 as_bad (_("unbalanced parenthesis in operand %d."),
1833 as_bad (_("unbalanced brackets in operand %d."),
1838 break; /* we are done */
1840 else if (!is_operand_char (*l) && !is_space_char (*l))
1842 as_bad (_("invalid character %s in operand %d"),
1843 output_invalid (*l),
1850 ++paren_not_balanced;
1852 --paren_not_balanced;
1857 ++paren_not_balanced;
1859 --paren_not_balanced;
1863 if (l != token_start)
1864 { /* Yes, we've read in another operand. */
1865 unsigned int operand_ok;
1866 this_operand = i.operands++;
1867 if (i.operands > MAX_OPERANDS)
1869 as_bad (_("spurious operands; (%d operands/instruction max)"),
1873 /* Now parse operand adding info to 'i' as we go along. */
1874 END_STRING_AND_SAVE (l);
1878 i386_intel_operand (token_start,
1879 intel_float_operand (mnemonic));
1881 operand_ok = i386_operand (token_start);
1883 RESTORE_END_STRING (l);
1889 if (expecting_operand)
1891 expecting_operand_after_comma:
1892 as_bad (_("expecting operand after ','; got nothing"));
1897 as_bad (_("expecting operand before ','; got nothing"));
1902 /* Now *l must be either ',' or END_OF_INSN. */
1905 if (*++l == END_OF_INSN)
1907 /* Just skip it, if it's \n complain. */
1908 goto expecting_operand_after_comma;
1910 expecting_operand = 1;
1919 union i386_op temp_op;
1920 unsigned int temp_type;
1921 enum bfd_reloc_code_real temp_reloc;
1925 if (i.operands == 2)
1930 else if (i.operands == 3)
1935 temp_type = i.types[xchg2];
1936 i.types[xchg2] = i.types[xchg1];
1937 i.types[xchg1] = temp_type;
1938 temp_op = i.op[xchg2];
1939 i.op[xchg2] = i.op[xchg1];
1940 i.op[xchg1] = temp_op;
1941 temp_reloc = i.reloc[xchg2];
1942 i.reloc[xchg2] = i.reloc[xchg1];
1943 i.reloc[xchg1] = temp_reloc;
1945 if (i.mem_operands == 2)
1947 const seg_entry *temp_seg;
1948 temp_seg = i.seg[0];
1949 i.seg[0] = i.seg[1];
1950 i.seg[1] = temp_seg;
1954 /* Try to ensure constant immediates are represented in the smallest
1959 char guess_suffix = 0;
1963 guess_suffix = i.suffix;
1964 else if (i.reg_operands)
1966 /* Figure out a suffix from the last register operand specified.
1967 We can't do this properly yet, ie. excluding InOutPortReg,
1968 but the following works for instructions with immediates.
1969 In any case, we can't set i.suffix yet. */
1970 for (op = i.operands; --op >= 0;)
1971 if (i.types[op] & Reg)
1973 if (i.types[op] & Reg8)
1974 guess_suffix = BYTE_MNEM_SUFFIX;
1975 else if (i.types[op] & Reg16)
1976 guess_suffix = WORD_MNEM_SUFFIX;
1977 else if (i.types[op] & Reg32)
1978 guess_suffix = LONG_MNEM_SUFFIX;
1979 else if (i.types[op] & Reg64)
1980 guess_suffix = QWORD_MNEM_SUFFIX;
1984 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1985 guess_suffix = WORD_MNEM_SUFFIX;
1987 for (op = i.operands; --op >= 0;)
1988 if (i.types[op] & Imm)
1990 switch (i.op[op].imms->X_op)
1993 /* If a suffix is given, this operand may be shortened. */
1994 switch (guess_suffix)
1996 case LONG_MNEM_SUFFIX:
1997 i.types[op] |= Imm32 | Imm64;
1999 case WORD_MNEM_SUFFIX:
2000 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2002 case BYTE_MNEM_SUFFIX:
2003 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2007 /* If this operand is at most 16 bits, convert it
2008 to a signed 16 bit number before trying to see
2009 whether it will fit in an even smaller size.
2010 This allows a 16-bit operand such as $0xffe0 to
2011 be recognised as within Imm8S range. */
2012 if ((i.types[op] & Imm16)
2013 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2015 i.op[op].imms->X_add_number =
2016 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2018 if ((i.types[op] & Imm32)
2019 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2022 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2023 ^ ((offsetT) 1 << 31))
2024 - ((offsetT) 1 << 31));
2026 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2028 /* We must avoid matching of Imm32 templates when 64bit
2029 only immediate is available. */
2030 if (guess_suffix == QWORD_MNEM_SUFFIX)
2031 i.types[op] &= ~Imm32;
2038 /* Symbols and expressions. */
2040 /* Convert symbolic operand to proper sizes for matching. */
2041 switch (guess_suffix)
2043 case QWORD_MNEM_SUFFIX:
2044 i.types[op] = Imm64 | Imm32S;
2046 case LONG_MNEM_SUFFIX:
2047 i.types[op] = Imm32;
2049 case WORD_MNEM_SUFFIX:
2050 i.types[op] = Imm16;
2052 case BYTE_MNEM_SUFFIX:
2053 i.types[op] = Imm8 | Imm8S;
2061 /* Try to use the smallest displacement type too. */
2067 for (op = i.operands; --op >= 0;)
2068 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
2070 offsetT disp = i.op[op].disps->X_add_number;
2072 if (i.types[op] & Disp16)
2074 /* We know this operand is at most 16 bits, so
2075 convert to a signed 16 bit number before trying
2076 to see whether it will fit in an even smaller
2079 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2081 else if (i.types[op] & Disp32)
2083 /* We know this operand is at most 32 bits, so convert to a
2084 signed 32 bit number before trying to see whether it will
2085 fit in an even smaller size. */
2086 disp &= (((offsetT) 2 << 31) - 1);
2087 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2089 if (!disp && (i.types[op] & BaseIndex))
2091 i.types[op] &= ~Disp;
2095 else if (flag_code == CODE_64BIT)
2097 if (fits_in_signed_long (disp))
2098 i.types[op] |= Disp32S;
2099 if (fits_in_unsigned_long (disp))
2100 i.types[op] |= Disp32;
2102 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2103 && fits_in_signed_byte (disp))
2104 i.types[op] |= Disp8;
2111 /* Points to template once we've found it. */
2113 unsigned int overlap0, overlap1, overlap2;
2114 unsigned int found_reverse_match;
2117 #define MATCH(overlap, given, template) \
2118 ((overlap & ~JumpAbsolute) \
2119 && (((given) & (BaseIndex | JumpAbsolute)) \
2120 == ((overlap) & (BaseIndex | JumpAbsolute))))
2122 /* If given types r0 and r1 are registers they must be of the same type
2123 unless the expected operand type register overlap is null.
2124 Note that Acc in a template matches every size of reg. */
2125 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2126 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2127 || ((g0) & Reg) == ((g1) & Reg) \
2128 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2133 found_reverse_match = 0;
2134 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2136 : (i.suffix == WORD_MNEM_SUFFIX
2138 : (i.suffix == SHORT_MNEM_SUFFIX
2140 : (i.suffix == LONG_MNEM_SUFFIX
2142 : (i.suffix == QWORD_MNEM_SUFFIX
2144 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2145 ? No_xSuf : 0))))));
2147 t = current_templates->start;
2148 if (i.suffix == QWORD_MNEM_SUFFIX
2149 && flag_code != CODE_64BIT
2151 ? !(t->opcode_modifier & IgnoreSize)
2152 && !intel_float_operand (t->name)
2153 : intel_float_operand (t->name) != 2)
2154 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2155 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2156 && (t->base_opcode != 0x0fc7
2157 || t->extension_opcode != 1 /* cmpxchg8b */))
2158 t = current_templates->end;
2159 for (; t < current_templates->end; t++)
2161 /* Must have right number of operands. */
2162 if (i.operands != t->operands)
2165 /* Check the suffix, except for some instructions in intel mode. */
2166 if ((t->opcode_modifier & suffix_check)
2168 && (t->opcode_modifier & IgnoreSize)))
2171 /* Do not verify operands when there are none. */
2172 else if (!t->operands)
2174 if (t->cpu_flags & ~cpu_arch_flags)
2176 /* We've found a match; break out of loop. */
2180 overlap0 = i.types[0] & t->operand_types[0];
2181 switch (t->operands)
2184 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2189 overlap1 = i.types[1] & t->operand_types[1];
2190 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2191 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2192 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2193 t->operand_types[0],
2194 overlap1, i.types[1],
2195 t->operand_types[1]))
2197 /* Check if other direction is valid ... */
2198 if ((t->opcode_modifier & (D | FloatD)) == 0)
2201 /* Try reversing direction of operands. */
2202 overlap0 = i.types[0] & t->operand_types[1];
2203 overlap1 = i.types[1] & t->operand_types[0];
2204 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2205 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2206 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2207 t->operand_types[1],
2208 overlap1, i.types[1],
2209 t->operand_types[0]))
2211 /* Does not match either direction. */
2214 /* found_reverse_match holds which of D or FloatDR
2216 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2218 /* Found a forward 2 operand match here. */
2219 else if (t->operands == 3)
2221 /* Here we make use of the fact that there are no
2222 reverse match 3 operand instructions, and all 3
2223 operand instructions only need to be checked for
2224 register consistency between operands 2 and 3. */
2225 overlap2 = i.types[2] & t->operand_types[2];
2226 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2227 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2228 t->operand_types[1],
2229 overlap2, i.types[2],
2230 t->operand_types[2]))
2234 /* Found either forward/reverse 2 or 3 operand match here:
2235 slip through to break. */
2237 if (t->cpu_flags & ~cpu_arch_flags)
2239 found_reverse_match = 0;
2242 /* We've found a match; break out of loop. */
2246 if (t == current_templates->end)
2248 /* We found no match. */
2249 as_bad (_("suffix or operands invalid for `%s'"),
2250 current_templates->start->name);
2254 if (!quiet_warnings)
2257 && ((i.types[0] & JumpAbsolute)
2258 != (t->operand_types[0] & JumpAbsolute)))
2260 as_warn (_("indirect %s without `*'"), t->name);
2263 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2264 == (IsPrefix | IgnoreSize))
2266 /* Warn them that a data or address size prefix doesn't
2267 affect assembly of the next line of code. */
2268 as_warn (_("stand-alone `%s' prefix"), t->name);
2272 /* Copy the template we found. */
2274 if (found_reverse_match)
2276 /* If we found a reverse match we must alter the opcode
2277 direction bit. found_reverse_match holds bits to change
2278 (different for int & float insns). */
2280 i.tm.base_opcode ^= found_reverse_match;
2282 i.tm.operand_types[0] = t->operand_types[1];
2283 i.tm.operand_types[1] = t->operand_types[0];
2292 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2293 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2295 if (i.seg[0] != NULL && i.seg[0] != &es)
2297 as_bad (_("`%s' operand %d must use `%%es' segment"),
2302 /* There's only ever one segment override allowed per instruction.
2303 This instruction possibly has a legal segment override on the
2304 second operand, so copy the segment to where non-string
2305 instructions store it, allowing common code. */
2306 i.seg[0] = i.seg[1];
2308 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2310 if (i.seg[1] != NULL && i.seg[1] != &es)
2312 as_bad (_("`%s' operand %d must use `%%es' segment"),
2322 process_suffix (void)
2324 /* If matched instruction specifies an explicit instruction mnemonic
2326 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2328 if (i.tm.opcode_modifier & Size16)
2329 i.suffix = WORD_MNEM_SUFFIX;
2330 else if (i.tm.opcode_modifier & Size64)
2331 i.suffix = QWORD_MNEM_SUFFIX;
2333 i.suffix = LONG_MNEM_SUFFIX;
2335 else if (i.reg_operands)
2337 /* If there's no instruction mnemonic suffix we try to invent one
2338 based on register operands. */
2341 /* We take i.suffix from the last register operand specified,
2342 Destination register type is more significant than source
2346 for (op = i.operands; --op >= 0;)
2347 if ((i.types[op] & Reg)
2348 && !(i.tm.operand_types[op] & InOutPortReg))
2350 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2351 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2352 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2357 else if (i.suffix == BYTE_MNEM_SUFFIX)
2359 if (!check_byte_reg ())
2362 else if (i.suffix == LONG_MNEM_SUFFIX)
2364 if (!check_long_reg ())
2367 else if (i.suffix == QWORD_MNEM_SUFFIX)
2369 if (!check_qword_reg ())
2372 else if (i.suffix == WORD_MNEM_SUFFIX)
2374 if (!check_word_reg ())
2377 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2378 /* Do nothing if the instruction is going to ignore the prefix. */
2383 else if ((i.tm.opcode_modifier & DefaultSize)
2385 /* exclude fldenv/frstor/fsave/fstenv */
2386 && (i.tm.opcode_modifier & No_sSuf))
2388 i.suffix = stackop_size;
2390 else if (intel_syntax
2392 && ((i.tm.operand_types[0] & JumpAbsolute)
2393 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2394 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2395 && i.tm.extension_opcode <= 3)))
2400 if (!(i.tm.opcode_modifier & No_qSuf))
2402 i.suffix = QWORD_MNEM_SUFFIX;
2406 if (!(i.tm.opcode_modifier & No_lSuf))
2407 i.suffix = LONG_MNEM_SUFFIX;
2410 if (!(i.tm.opcode_modifier & No_wSuf))
2411 i.suffix = WORD_MNEM_SUFFIX;
2420 if (i.tm.opcode_modifier & W)
2422 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2428 unsigned int suffixes = ~i.tm.opcode_modifier
2436 if ((i.tm.opcode_modifier & W)
2437 || ((suffixes & (suffixes - 1))
2438 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2440 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2446 /* Change the opcode based on the operand size given by i.suffix;
2447 We don't need to change things for byte insns. */
2449 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2451 /* It's not a byte, select word/dword operation. */
2452 if (i.tm.opcode_modifier & W)
2454 if (i.tm.opcode_modifier & ShortForm)
2455 i.tm.base_opcode |= 8;
2457 i.tm.base_opcode |= 1;
2460 /* Now select between word & dword operations via the operand
2461 size prefix, except for instructions that will ignore this
2463 if (i.suffix != QWORD_MNEM_SUFFIX
2464 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2465 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2466 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2467 || (flag_code == CODE_64BIT
2468 && (i.tm.opcode_modifier & JumpByte))))
2470 unsigned int prefix = DATA_PREFIX_OPCODE;
2472 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2473 prefix = ADDR_PREFIX_OPCODE;
2475 if (!add_prefix (prefix))
2479 /* Set mode64 for an operand. */
2480 if (i.suffix == QWORD_MNEM_SUFFIX
2481 && flag_code == CODE_64BIT
2482 && (i.tm.opcode_modifier & NoRex64) == 0)
2483 i.rex |= REX_MODE64;
2485 /* Size floating point instruction. */
2486 if (i.suffix == LONG_MNEM_SUFFIX)
2487 if (i.tm.opcode_modifier & FloatMF)
2488 i.tm.base_opcode ^= 4;
2495 check_byte_reg (void)
2499 for (op = i.operands; --op >= 0;)
2501 /* If this is an eight bit register, it's OK. If it's the 16 or
2502 32 bit version of an eight bit register, we will just use the
2503 low portion, and that's OK too. */
2504 if (i.types[op] & Reg8)
2507 /* movzx and movsx should not generate this warning. */
2509 && (i.tm.base_opcode == 0xfb7
2510 || i.tm.base_opcode == 0xfb6
2511 || i.tm.base_opcode == 0x63
2512 || i.tm.base_opcode == 0xfbe
2513 || i.tm.base_opcode == 0xfbf))
2516 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2518 /* Prohibit these changes in the 64bit mode, since the
2519 lowering is more complicated. */
2520 if (flag_code == CODE_64BIT
2521 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2523 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2524 i.op[op].regs->reg_name,
2528 #if REGISTER_WARNINGS
2530 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2531 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2532 (i.op[op].regs + (i.types[op] & Reg16
2533 ? REGNAM_AL - REGNAM_AX
2534 : REGNAM_AL - REGNAM_EAX))->reg_name,
2535 i.op[op].regs->reg_name,
2540 /* Any other register is bad. */
2541 if (i.types[op] & (Reg | RegMMX | RegXMM
2543 | Control | Debug | Test
2544 | FloatReg | FloatAcc))
2546 as_bad (_("`%%%s' not allowed with `%s%c'"),
2547 i.op[op].regs->reg_name,
2561 for (op = i.operands; --op >= 0;)
2562 /* Reject eight bit registers, except where the template requires
2563 them. (eg. movzb) */
2564 if ((i.types[op] & Reg8) != 0
2565 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2567 as_bad (_("`%%%s' not allowed with `%s%c'"),
2568 i.op[op].regs->reg_name,
2573 /* Warn if the e prefix on a general reg is missing. */
2574 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2575 && (i.types[op] & Reg16) != 0
2576 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2578 /* Prohibit these changes in the 64bit mode, since the
2579 lowering is more complicated. */
2580 if (flag_code == CODE_64BIT)
2582 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2583 i.op[op].regs->reg_name,
2587 #if REGISTER_WARNINGS
2589 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2590 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2591 i.op[op].regs->reg_name,
2595 /* Warn if the r prefix on a general reg is missing. */
2596 else if ((i.types[op] & Reg64) != 0
2597 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2599 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2600 i.op[op].regs->reg_name,
2612 for (op = i.operands; --op >= 0; )
2613 /* Reject eight bit registers, except where the template requires
2614 them. (eg. movzb) */
2615 if ((i.types[op] & Reg8) != 0
2616 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2618 as_bad (_("`%%%s' not allowed with `%s%c'"),
2619 i.op[op].regs->reg_name,
2624 /* Warn if the e prefix on a general reg is missing. */
2625 else if (((i.types[op] & Reg16) != 0
2626 || (i.types[op] & Reg32) != 0)
2627 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2629 /* Prohibit these changes in the 64bit mode, since the
2630 lowering is more complicated. */
2631 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2632 i.op[op].regs->reg_name,
2643 for (op = i.operands; --op >= 0;)
2644 /* Reject eight bit registers, except where the template requires
2645 them. (eg. movzb) */
2646 if ((i.types[op] & Reg8) != 0
2647 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2649 as_bad (_("`%%%s' not allowed with `%s%c'"),
2650 i.op[op].regs->reg_name,
2655 /* Warn if the e prefix on a general reg is present. */
2656 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2657 && (i.types[op] & Reg32) != 0
2658 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2660 /* Prohibit these changes in the 64bit mode, since the
2661 lowering is more complicated. */
2662 if (flag_code == CODE_64BIT)
2664 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2665 i.op[op].regs->reg_name,
2670 #if REGISTER_WARNINGS
2671 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2672 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2673 i.op[op].regs->reg_name,
2683 unsigned int overlap0, overlap1, overlap2;
2685 overlap0 = i.types[0] & i.tm.operand_types[0];
2686 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2687 && overlap0 != Imm8 && overlap0 != Imm8S
2688 && overlap0 != Imm16 && overlap0 != Imm32S
2689 && overlap0 != Imm32 && overlap0 != Imm64)
2693 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2695 : (i.suffix == WORD_MNEM_SUFFIX
2697 : (i.suffix == QWORD_MNEM_SUFFIX
2701 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2702 || overlap0 == (Imm16 | Imm32)
2703 || overlap0 == (Imm16 | Imm32S))
2705 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2708 if (overlap0 != Imm8 && overlap0 != Imm8S
2709 && overlap0 != Imm16 && overlap0 != Imm32S
2710 && overlap0 != Imm32 && overlap0 != Imm64)
2712 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2716 i.types[0] = overlap0;
2718 overlap1 = i.types[1] & i.tm.operand_types[1];
2719 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2720 && overlap1 != Imm8 && overlap1 != Imm8S
2721 && overlap1 != Imm16 && overlap1 != Imm32S
2722 && overlap1 != Imm32 && overlap1 != Imm64)
2726 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2728 : (i.suffix == WORD_MNEM_SUFFIX
2730 : (i.suffix == QWORD_MNEM_SUFFIX
2734 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2735 || overlap1 == (Imm16 | Imm32)
2736 || overlap1 == (Imm16 | Imm32S))
2738 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2741 if (overlap1 != Imm8 && overlap1 != Imm8S
2742 && overlap1 != Imm16 && overlap1 != Imm32S
2743 && overlap1 != Imm32 && overlap1 != Imm64)
2745 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2749 i.types[1] = overlap1;
2751 overlap2 = i.types[2] & i.tm.operand_types[2];
2752 assert ((overlap2 & Imm) == 0);
2753 i.types[2] = overlap2;
2761 /* Default segment register this instruction will use for memory
2762 accesses. 0 means unknown. This is only for optimizing out
2763 unnecessary segment overrides. */
2764 const seg_entry *default_seg = 0;
2766 /* The imul $imm, %reg instruction is converted into
2767 imul $imm, %reg, %reg, and the clr %reg instruction
2768 is converted into xor %reg, %reg. */
2769 if (i.tm.opcode_modifier & regKludge)
2771 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2772 /* Pretend we saw the extra register operand. */
2773 assert (i.op[first_reg_op + 1].regs == 0);
2774 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2775 i.types[first_reg_op + 1] = i.types[first_reg_op];
2779 if (i.tm.opcode_modifier & ShortForm)
2781 /* The register or float register operand is in operand 0 or 1. */
2782 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2783 /* Register goes in low 3 bits of opcode. */
2784 i.tm.base_opcode |= i.op[op].regs->reg_num;
2785 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2787 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2789 /* Warn about some common errors, but press on regardless.
2790 The first case can be generated by gcc (<= 2.8.1). */
2791 if (i.operands == 2)
2793 /* Reversed arguments on faddp, fsubp, etc. */
2794 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2795 i.op[1].regs->reg_name,
2796 i.op[0].regs->reg_name);
2800 /* Extraneous `l' suffix on fp insn. */
2801 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2802 i.op[0].regs->reg_name);
2806 else if (i.tm.opcode_modifier & Modrm)
2808 /* The opcode is completed (modulo i.tm.extension_opcode which
2809 must be put into the modrm byte). Now, we make the modrm and
2810 index base bytes based on all the info we've collected. */
2812 default_seg = build_modrm_byte ();
2814 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2816 if (i.tm.base_opcode == POP_SEG_SHORT
2817 && i.op[0].regs->reg_num == 1)
2819 as_bad (_("you can't `pop %%cs'"));
2822 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2823 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2826 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2830 else if ((i.tm.opcode_modifier & IsString) != 0)
2832 /* For the string instructions that allow a segment override
2833 on one of their operands, the default segment is ds. */
2837 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2838 as_warn (_("segment override on `lea' is ineffectual"));
2840 /* If a segment was explicitly specified, and the specified segment
2841 is not the default, use an opcode prefix to select it. If we
2842 never figured out what the default segment is, then default_seg
2843 will be zero at this point, and the specified segment prefix will
2845 if ((i.seg[0]) && (i.seg[0] != default_seg))
2847 if (!add_prefix (i.seg[0]->seg_prefix))
2853 static const seg_entry *
2856 const seg_entry *default_seg = 0;
2858 /* i.reg_operands MUST be the number of real register operands;
2859 implicit registers do not count. */
2860 if (i.reg_operands == 2)
2862 unsigned int source, dest;
2863 source = ((i.types[0]
2864 & (Reg | RegMMX | RegXMM
2866 | Control | Debug | Test))
2871 /* One of the register operands will be encoded in the i.tm.reg
2872 field, the other in the combined i.tm.mode and i.tm.regmem
2873 fields. If no form of this instruction supports a memory
2874 destination operand, then we assume the source operand may
2875 sometimes be a memory operand and so we need to store the
2876 destination in the i.rm.reg field. */
2877 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2879 i.rm.reg = i.op[dest].regs->reg_num;
2880 i.rm.regmem = i.op[source].regs->reg_num;
2881 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2883 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2888 i.rm.reg = i.op[source].regs->reg_num;
2889 i.rm.regmem = i.op[dest].regs->reg_num;
2890 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2892 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2895 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2897 if (!((i.types[0] | i.types[1]) & Control))
2899 i.rex &= ~(REX_EXTX | REX_EXTZ);
2900 add_prefix (LOCK_PREFIX_OPCODE);
2904 { /* If it's not 2 reg operands... */
2907 unsigned int fake_zero_displacement = 0;
2908 unsigned int op = ((i.types[0] & AnyMem)
2910 : (i.types[1] & AnyMem) ? 1 : 2);
2914 if (i.base_reg == 0)
2917 if (!i.disp_operands)
2918 fake_zero_displacement = 1;
2919 if (i.index_reg == 0)
2921 /* Operand is just <disp> */
2922 if (flag_code == CODE_64BIT)
2924 /* 64bit mode overwrites the 32bit absolute
2925 addressing by RIP relative addressing and
2926 absolute addressing is encoded by one of the
2927 redundant SIB forms. */
2928 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2929 i.sib.base = NO_BASE_REGISTER;
2930 i.sib.index = NO_INDEX_REGISTER;
2931 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2933 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2935 i.rm.regmem = NO_BASE_REGISTER_16;
2936 i.types[op] = Disp16;
2940 i.rm.regmem = NO_BASE_REGISTER;
2941 i.types[op] = Disp32;
2944 else /* !i.base_reg && i.index_reg */
2946 i.sib.index = i.index_reg->reg_num;
2947 i.sib.base = NO_BASE_REGISTER;
2948 i.sib.scale = i.log2_scale_factor;
2949 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2950 i.types[op] &= ~Disp;
2951 if (flag_code != CODE_64BIT)
2952 i.types[op] |= Disp32; /* Must be 32 bit */
2954 i.types[op] |= Disp32S;
2955 if ((i.index_reg->reg_flags & RegRex) != 0)
2959 /* RIP addressing for 64bit mode. */
2960 else if (i.base_reg->reg_type == BaseIndex)
2962 i.rm.regmem = NO_BASE_REGISTER;
2963 i.types[op] &= ~ Disp;
2964 i.types[op] |= Disp32S;
2965 i.flags[op] = Operand_PCrel;
2966 if (! i.disp_operands)
2967 fake_zero_displacement = 1;
2969 else if (i.base_reg->reg_type & Reg16)
2971 switch (i.base_reg->reg_num)
2974 if (i.index_reg == 0)
2976 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2977 i.rm.regmem = i.index_reg->reg_num - 6;
2981 if (i.index_reg == 0)
2984 if ((i.types[op] & Disp) == 0)
2986 /* fake (%bp) into 0(%bp) */
2987 i.types[op] |= Disp8;
2988 fake_zero_displacement = 1;
2991 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2992 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2994 default: /* (%si) -> 4 or (%di) -> 5 */
2995 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2997 i.rm.mode = mode_from_disp_size (i.types[op]);
2999 else /* i.base_reg and 32/64 bit mode */
3001 if (flag_code == CODE_64BIT
3002 && (i.types[op] & Disp))
3003 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3005 i.rm.regmem = i.base_reg->reg_num;
3006 if ((i.base_reg->reg_flags & RegRex) != 0)
3008 i.sib.base = i.base_reg->reg_num;
3009 /* x86-64 ignores REX prefix bit here to avoid decoder
3011 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3014 if (i.disp_operands == 0)
3016 fake_zero_displacement = 1;
3017 i.types[op] |= Disp8;
3020 else if (i.base_reg->reg_num == ESP_REG_NUM)
3024 i.sib.scale = i.log2_scale_factor;
3025 if (i.index_reg == 0)
3027 /* <disp>(%esp) becomes two byte modrm with no index
3028 register. We've already stored the code for esp
3029 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3030 Any base register besides %esp will not use the
3031 extra modrm byte. */
3032 i.sib.index = NO_INDEX_REGISTER;
3033 #if !SCALE1_WHEN_NO_INDEX
3034 /* Another case where we force the second modrm byte. */
3035 if (i.log2_scale_factor)
3036 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3041 i.sib.index = i.index_reg->reg_num;
3042 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3043 if ((i.index_reg->reg_flags & RegRex) != 0)
3046 i.rm.mode = mode_from_disp_size (i.types[op]);
3049 if (fake_zero_displacement)
3051 /* Fakes a zero displacement assuming that i.types[op]
3052 holds the correct displacement size. */
3055 assert (i.op[op].disps == 0);
3056 exp = &disp_expressions[i.disp_operands++];
3057 i.op[op].disps = exp;
3058 exp->X_op = O_constant;
3059 exp->X_add_number = 0;
3060 exp->X_add_symbol = (symbolS *) 0;
3061 exp->X_op_symbol = (symbolS *) 0;
3065 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3066 (if any) based on i.tm.extension_opcode. Again, we must be
3067 careful to make sure that segment/control/debug/test/MMX
3068 registers are coded into the i.rm.reg field. */
3073 & (Reg | RegMMX | RegXMM
3075 | Control | Debug | Test))
3078 & (Reg | RegMMX | RegXMM
3080 | Control | Debug | Test))
3083 /* If there is an extension opcode to put here, the register
3084 number must be put into the regmem field. */
3085 if (i.tm.extension_opcode != None)
3087 i.rm.regmem = i.op[op].regs->reg_num;
3088 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3093 i.rm.reg = i.op[op].regs->reg_num;
3094 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3098 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3099 must set it to 3 to indicate this is a register operand
3100 in the regmem field. */
3101 if (!i.mem_operands)
3105 /* Fill in i.rm.reg field with extension opcode (if any). */
3106 if (i.tm.extension_opcode != None)
3107 i.rm.reg = i.tm.extension_opcode;
3118 relax_substateT subtype;
3123 if (flag_code == CODE_16BIT)
3127 if (i.prefix[DATA_PREFIX] != 0)
3133 /* Pentium4 branch hints. */
3134 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3135 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3140 if (i.prefix[REX_PREFIX] != 0)
3146 if (i.prefixes != 0 && !intel_syntax)
3147 as_warn (_("skipping prefixes on this instruction"));
3149 /* It's always a symbol; End frag & setup for relax.
3150 Make sure there is enough room in this frag for the largest
3151 instruction we may generate in md_convert_frag. This is 2
3152 bytes for the opcode and room for the prefix and largest
3154 frag_grow (prefix + 2 + 4);
3155 /* Prefix and 1 opcode byte go in fr_fix. */
3156 p = frag_more (prefix + 1);
3157 if (i.prefix[DATA_PREFIX] != 0)
3158 *p++ = DATA_PREFIX_OPCODE;
3159 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3160 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3161 *p++ = i.prefix[SEG_PREFIX];
3162 if (i.prefix[REX_PREFIX] != 0)
3163 *p++ = i.prefix[REX_PREFIX];
3164 *p = i.tm.base_opcode;
3166 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3167 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3168 else if ((cpu_arch_flags & Cpu386) != 0)
3169 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3171 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3174 sym = i.op[0].disps->X_add_symbol;
3175 off = i.op[0].disps->X_add_number;
3177 if (i.op[0].disps->X_op != O_constant
3178 && i.op[0].disps->X_op != O_symbol)
3180 /* Handle complex expressions. */
3181 sym = make_expr_symbol (i.op[0].disps);
3185 /* 1 possible extra opcode + 4 byte displacement go in var part.
3186 Pass reloc in fr_var. */
3187 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3197 if (i.tm.opcode_modifier & JumpByte)
3199 /* This is a loop or jecxz type instruction. */
3201 if (i.prefix[ADDR_PREFIX] != 0)
3203 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3206 /* Pentium4 branch hints. */
3207 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3208 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3210 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3219 if (flag_code == CODE_16BIT)
3222 if (i.prefix[DATA_PREFIX] != 0)
3224 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3234 if (i.prefix[REX_PREFIX] != 0)
3236 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3240 if (i.prefixes != 0 && !intel_syntax)
3241 as_warn (_("skipping prefixes on this instruction"));
3243 p = frag_more (1 + size);
3244 *p++ = i.tm.base_opcode;
3246 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3247 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3249 /* All jumps handled here are signed, but don't use a signed limit
3250 check for 32 and 16 bit jumps as we want to allow wrap around at
3251 4G and 64k respectively. */
3253 fixP->fx_signed = 1;
3257 output_interseg_jump ()
3265 if (flag_code == CODE_16BIT)
3269 if (i.prefix[DATA_PREFIX] != 0)
3275 if (i.prefix[REX_PREFIX] != 0)
3285 if (i.prefixes != 0 && !intel_syntax)
3286 as_warn (_("skipping prefixes on this instruction"));
3288 /* 1 opcode; 2 segment; offset */
3289 p = frag_more (prefix + 1 + 2 + size);
3291 if (i.prefix[DATA_PREFIX] != 0)
3292 *p++ = DATA_PREFIX_OPCODE;
3294 if (i.prefix[REX_PREFIX] != 0)
3295 *p++ = i.prefix[REX_PREFIX];
3297 *p++ = i.tm.base_opcode;
3298 if (i.op[1].imms->X_op == O_constant)
3300 offsetT n = i.op[1].imms->X_add_number;
3303 && !fits_in_unsigned_word (n)
3304 && !fits_in_signed_word (n))
3306 as_bad (_("16-bit jump out of range"));
3309 md_number_to_chars (p, n, size);
3312 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3313 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3314 if (i.op[0].imms->X_op != O_constant)
3315 as_bad (_("can't handle non absolute segment in `%s'"),
3317 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3323 fragS *insn_start_frag;
3324 offsetT insn_start_off;
3326 /* Tie dwarf2 debug info to the address at the start of the insn.
3327 We can't do this after the insn has been output as the current
3328 frag may have been closed off. eg. by frag_var. */
3329 dwarf2_emit_insn (0);
3331 insn_start_frag = frag_now;
3332 insn_start_off = frag_now_fix ();
3335 if (i.tm.opcode_modifier & Jump)
3337 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3339 else if (i.tm.opcode_modifier & JumpInterSegment)
3340 output_interseg_jump ();
3343 /* Output normal instructions here. */
3347 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3348 more higher byte to specify a prefix the instruction
3350 if ((i.tm.base_opcode & 0xff0000) != 0)
3352 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3354 unsigned int prefix;
3355 prefix = (i.tm.base_opcode >> 16) & 0xff;
3357 if (prefix != REPE_PREFIX_OPCODE
3358 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3359 add_prefix (prefix);
3362 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3365 /* The prefix bytes. */
3367 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3373 md_number_to_chars (p, (valueT) *q, 1);
3377 /* Now the opcode; be careful about word order here! */
3378 if (fits_in_unsigned_byte (i.tm.base_opcode))
3380 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3386 /* Put out high byte first: can't use md_number_to_chars! */
3387 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3388 *p = i.tm.base_opcode & 0xff;
3391 /* Now the modrm byte and sib byte (if present). */
3392 if (i.tm.opcode_modifier & Modrm)
3395 md_number_to_chars (p,
3396 (valueT) (i.rm.regmem << 0
3400 /* If i.rm.regmem == ESP (4)
3401 && i.rm.mode != (Register mode)
3403 ==> need second modrm byte. */
3404 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3406 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3409 md_number_to_chars (p,
3410 (valueT) (i.sib.base << 0
3412 | i.sib.scale << 6),
3417 if (i.disp_operands)
3418 output_disp (insn_start_frag, insn_start_off);
3421 output_imm (insn_start_frag, insn_start_off);
3429 #endif /* DEBUG386 */
3433 output_disp (insn_start_frag, insn_start_off)
3434 fragS *insn_start_frag;
3435 offsetT insn_start_off;
3440 for (n = 0; n < i.operands; n++)
3442 if (i.types[n] & Disp)
3444 if (i.op[n].disps->X_op == O_constant)
3450 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3453 if (i.types[n] & Disp8)
3455 if (i.types[n] & Disp64)
3458 val = offset_in_range (i.op[n].disps->X_add_number,
3460 p = frag_more (size);
3461 md_number_to_chars (p, val, size);
3465 enum bfd_reloc_code_real reloc_type;
3468 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3470 /* The PC relative address is computed relative
3471 to the instruction boundary, so in case immediate
3472 fields follows, we need to adjust the value. */
3473 if (pcrel && i.imm_operands)
3478 for (n1 = 0; n1 < i.operands; n1++)
3479 if (i.types[n1] & Imm)
3481 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3484 if (i.types[n1] & (Imm8 | Imm8S))
3486 if (i.types[n1] & Imm64)
3491 /* We should find the immediate. */
3492 if (n1 == i.operands)
3494 i.op[n].disps->X_add_number -= imm_size;
3497 if (i.types[n] & Disp32S)
3500 if (i.types[n] & (Disp16 | Disp64))
3503 if (i.types[n] & Disp64)
3507 p = frag_more (size);
3508 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3510 && GOT_symbol == i.op[n].disps->X_add_symbol
3511 && (((reloc_type == BFD_RELOC_32
3512 || reloc_type == BFD_RELOC_X86_64_32S)
3513 && (i.op[n].disps->X_op == O_symbol
3514 || (i.op[n].disps->X_op == O_add
3515 && ((symbol_get_value_expression
3516 (i.op[n].disps->X_op_symbol)->X_op)
3518 || reloc_type == BFD_RELOC_32_PCREL))
3522 if (insn_start_frag == frag_now)
3523 add = (p - frag_now->fr_literal) - insn_start_off;
3528 add = insn_start_frag->fr_fix - insn_start_off;
3529 for (fr = insn_start_frag->fr_next;
3530 fr && fr != frag_now; fr = fr->fr_next)
3532 add += p - frag_now->fr_literal;
3535 if (flag_code != CODE_64BIT)
3536 reloc_type = BFD_RELOC_386_GOTPC;
3538 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3539 i.op[n].disps->X_add_number += add;
3541 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3542 i.op[n].disps, pcrel, reloc_type);
3549 output_imm (insn_start_frag, insn_start_off)
3550 fragS *insn_start_frag;
3551 offsetT insn_start_off;
3556 for (n = 0; n < i.operands; n++)
3558 if (i.types[n] & Imm)
3560 if (i.op[n].imms->X_op == O_constant)
3566 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3569 if (i.types[n] & (Imm8 | Imm8S))
3571 else if (i.types[n] & Imm64)
3574 val = offset_in_range (i.op[n].imms->X_add_number,
3576 p = frag_more (size);
3577 md_number_to_chars (p, val, size);
3581 /* Not absolute_section.
3582 Need a 32-bit fixup (don't support 8bit
3583 non-absolute imms). Try to support other
3585 enum bfd_reloc_code_real reloc_type;
3589 if ((i.types[n] & (Imm32S))
3590 && (i.suffix == QWORD_MNEM_SUFFIX
3591 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
3593 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3596 if (i.types[n] & (Imm8 | Imm8S))
3598 if (i.types[n] & Imm64)
3602 p = frag_more (size);
3603 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3605 /* This is tough to explain. We end up with this one if we
3606 * have operands that look like
3607 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3608 * obtain the absolute address of the GOT, and it is strongly
3609 * preferable from a performance point of view to avoid using
3610 * a runtime relocation for this. The actual sequence of
3611 * instructions often look something like:
3616 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3618 * The call and pop essentially return the absolute address
3619 * of the label .L66 and store it in %ebx. The linker itself
3620 * will ultimately change the first operand of the addl so
3621 * that %ebx points to the GOT, but to keep things simple, the
3622 * .o file must have this operand set so that it generates not
3623 * the absolute address of .L66, but the absolute address of
3624 * itself. This allows the linker itself simply treat a GOTPC
3625 * relocation as asking for a pcrel offset to the GOT to be
3626 * added in, and the addend of the relocation is stored in the
3627 * operand field for the instruction itself.
3629 * Our job here is to fix the operand so that it would add
3630 * the correct offset so that %ebx would point to itself. The
3631 * thing that is tricky is that .-.L66 will point to the
3632 * beginning of the instruction, so we need to further modify
3633 * the operand so that it will point to itself. There are
3634 * other cases where you have something like:
3636 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3638 * and here no correction would be required. Internally in
3639 * the assembler we treat operands of this form as not being
3640 * pcrel since the '.' is explicitly mentioned, and I wonder
3641 * whether it would simplify matters to do it this way. Who
3642 * knows. In earlier versions of the PIC patches, the
3643 * pcrel_adjust field was used to store the correction, but
3644 * since the expression is not pcrel, I felt it would be
3645 * confusing to do it this way. */
3647 if ((reloc_type == BFD_RELOC_32
3648 || reloc_type == BFD_RELOC_X86_64_32S)
3650 && GOT_symbol == i.op[n].imms->X_add_symbol
3651 && (i.op[n].imms->X_op == O_symbol
3652 || (i.op[n].imms->X_op == O_add
3653 && ((symbol_get_value_expression
3654 (i.op[n].imms->X_op_symbol)->X_op)
3659 if (insn_start_frag == frag_now)
3660 add = (p - frag_now->fr_literal) - insn_start_off;
3665 add = insn_start_frag->fr_fix - insn_start_off;
3666 for (fr = insn_start_frag->fr_next;
3667 fr && fr != frag_now; fr = fr->fr_next)
3669 add += p - frag_now->fr_literal;
3672 if (flag_code != CODE_64BIT)
3673 reloc_type = BFD_RELOC_386_GOTPC;
3675 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3676 i.op[n].imms->X_add_number += add;
3678 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3679 i.op[n].imms, 0, reloc_type);
3686 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
3688 /* Parse operands of the form
3689 <symbol>@GOTOFF+<nnn>
3690 and similar .plt or .got references.
3692 If we find one, set up the correct relocation in RELOC and copy the
3693 input string, minus the `@GOTOFF' into a malloc'd buffer for
3694 parsing by the calling routine. Return this buffer, and if ADJUST
3695 is non-null set it to the length of the string we removed from the
3696 input line. Otherwise return NULL. */
3698 lex_got (reloc, adjust)
3699 enum bfd_reloc_code_real *reloc;
3702 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3703 static const struct {
3705 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3707 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3708 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 } },
3709 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3710 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
3711 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3712 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3713 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3714 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
3715 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3716 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
3717 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3718 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
3719 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3724 for (cp = input_line_pointer; *cp != '@'; cp++)
3725 if (is_end_of_line[(unsigned char) *cp])
3728 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3732 len = strlen (gotrel[j].str);
3733 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3735 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3738 char *tmpbuf, *past_reloc;
3740 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3744 if (GOT_symbol == NULL)
3745 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3747 /* Replace the relocation token with ' ', so that
3748 errors like foo@GOTOFF1 will be detected. */
3750 /* The length of the first part of our input line. */
3751 first = cp - input_line_pointer;
3753 /* The second part goes from after the reloc token until
3754 (and including) an end_of_line char. Don't use strlen
3755 here as the end_of_line char may not be a NUL. */
3756 past_reloc = cp + 1 + len;
3757 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3759 second = cp - past_reloc;
3761 /* Allocate and copy string. The trailing NUL shouldn't
3762 be necessary, but be safe. */
3763 tmpbuf = xmalloc (first + second + 2);
3764 memcpy (tmpbuf, input_line_pointer, first);
3765 tmpbuf[first] = ' ';
3766 memcpy (tmpbuf + first + 1, past_reloc, second);
3767 tmpbuf[first + second + 1] = '\0';
3771 as_bad (_("@%s reloc is not supported in %s bit mode"),
3772 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3777 /* Might be a symbol version string. Don't as_bad here. */
3781 /* x86_cons_fix_new is called via the expression parsing code when a
3782 reloc is needed. We use this hook to get the correct .got reloc. */
3783 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3786 x86_cons_fix_new (frag, off, len, exp)
3792 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
3793 got_reloc = NO_RELOC;
3794 fix_new_exp (frag, off, len, exp, 0, r);
3798 x86_cons (exp, size)
3802 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
3804 /* Handle @GOTOFF and the like in an expression. */
3806 char *gotfree_input_line;
3809 save = input_line_pointer;
3810 gotfree_input_line = lex_got (&got_reloc, &adjust);
3811 if (gotfree_input_line)
3812 input_line_pointer = gotfree_input_line;
3816 if (gotfree_input_line)
3818 /* expression () has merrily parsed up to the end of line,
3819 or a comma - in the wrong buffer. Transfer how far
3820 input_line_pointer has moved to the right buffer. */
3821 input_line_pointer = (save
3822 + (input_line_pointer - gotfree_input_line)
3824 free (gotfree_input_line);
3835 x86_pe_cons_fix_new (frag, off, len, exp)
3841 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3843 if (exp->X_op == O_secrel)
3845 exp->X_op = O_symbol;
3846 r = BFD_RELOC_32_SECREL;
3849 fix_new_exp (frag, off, len, exp, 0, r);
3853 pe_directive_secrel (dummy)
3854 int dummy ATTRIBUTE_UNUSED;
3861 if (exp.X_op == O_symbol)
3862 exp.X_op = O_secrel;
3864 emit_expr (&exp, 4);
3866 while (*input_line_pointer++ == ',');
3868 input_line_pointer--;
3869 demand_empty_rest_of_line ();
3874 static int i386_immediate PARAMS ((char *));
3877 i386_immediate (imm_start)
3880 char *save_input_line_pointer;
3882 char *gotfree_input_line;
3887 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3889 as_bad (_("only 1 or 2 immediate operands are allowed"));
3893 exp = &im_expressions[i.imm_operands++];
3894 i.op[this_operand].imms = exp;
3896 if (is_space_char (*imm_start))
3899 save_input_line_pointer = input_line_pointer;
3900 input_line_pointer = imm_start;
3903 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3904 if (gotfree_input_line)
3905 input_line_pointer = gotfree_input_line;
3908 exp_seg = expression (exp);
3911 if (*input_line_pointer)
3912 as_bad (_("junk `%s' after expression"), input_line_pointer);
3914 input_line_pointer = save_input_line_pointer;
3916 if (gotfree_input_line)
3917 free (gotfree_input_line);
3920 if (exp->X_op == O_absent || exp->X_op == O_big)
3922 /* Missing or bad expr becomes absolute 0. */
3923 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3925 exp->X_op = O_constant;
3926 exp->X_add_number = 0;
3927 exp->X_add_symbol = (symbolS *) 0;
3928 exp->X_op_symbol = (symbolS *) 0;
3930 else if (exp->X_op == O_constant)
3932 /* Size it properly later. */
3933 i.types[this_operand] |= Imm64;
3934 /* If BFD64, sign extend val. */
3935 if (!use_rela_relocations)
3936 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3937 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3939 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3940 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3941 && exp_seg != absolute_section
3942 && exp_seg != text_section
3943 && exp_seg != data_section
3944 && exp_seg != bss_section
3945 && exp_seg != undefined_section
3946 && !bfd_is_com_section (exp_seg))
3948 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3954 /* This is an address. The size of the address will be
3955 determined later, depending on destination register,
3956 suffix, or the default for the section. */
3957 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3963 static char *i386_scale PARAMS ((char *));
3970 char *save = input_line_pointer;
3972 input_line_pointer = scale;
3973 val = get_absolute_expression ();
3978 i.log2_scale_factor = 0;
3981 i.log2_scale_factor = 1;
3984 i.log2_scale_factor = 2;
3987 i.log2_scale_factor = 3;
3991 char sep = *input_line_pointer;
3993 *input_line_pointer = '\0';
3994 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3996 *input_line_pointer = sep;
3997 input_line_pointer = save;
4001 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4003 as_warn (_("scale factor of %d without an index register"),
4004 1 << i.log2_scale_factor);
4005 #if SCALE1_WHEN_NO_INDEX
4006 i.log2_scale_factor = 0;
4009 scale = input_line_pointer;
4010 input_line_pointer = save;
4014 static int i386_displacement PARAMS ((char *, char *));
4017 i386_displacement (disp_start, disp_end)
4023 char *save_input_line_pointer;
4025 char *gotfree_input_line;
4027 int bigdisp = Disp32;
4029 if (flag_code == CODE_64BIT)
4031 if (i.prefix[ADDR_PREFIX] == 0)
4034 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4036 i.types[this_operand] |= bigdisp;
4038 exp = &disp_expressions[i.disp_operands];
4039 i.op[this_operand].disps = exp;
4041 save_input_line_pointer = input_line_pointer;
4042 input_line_pointer = disp_start;
4043 END_STRING_AND_SAVE (disp_end);
4045 #ifndef GCC_ASM_O_HACK
4046 #define GCC_ASM_O_HACK 0
4049 END_STRING_AND_SAVE (disp_end + 1);
4050 if ((i.types[this_operand] & BaseIndex) != 0
4051 && displacement_string_end[-1] == '+')
4053 /* This hack is to avoid a warning when using the "o"
4054 constraint within gcc asm statements.
4057 #define _set_tssldt_desc(n,addr,limit,type) \
4058 __asm__ __volatile__ ( \
4060 "movw %w1,2+%0\n\t" \
4062 "movb %b1,4+%0\n\t" \
4063 "movb %4,5+%0\n\t" \
4064 "movb $0,6+%0\n\t" \
4065 "movb %h1,7+%0\n\t" \
4067 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4069 This works great except that the output assembler ends
4070 up looking a bit weird if it turns out that there is
4071 no offset. You end up producing code that looks like:
4084 So here we provide the missing zero. */
4086 *displacement_string_end = '0';
4090 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4091 if (gotfree_input_line)
4092 input_line_pointer = gotfree_input_line;
4095 exp_seg = expression (exp);
4098 if (*input_line_pointer)
4099 as_bad (_("junk `%s' after expression"), input_line_pointer);
4101 RESTORE_END_STRING (disp_end + 1);
4103 RESTORE_END_STRING (disp_end);
4104 input_line_pointer = save_input_line_pointer;
4106 if (gotfree_input_line)
4107 free (gotfree_input_line);
4110 /* We do this to make sure that the section symbol is in
4111 the symbol table. We will ultimately change the relocation
4112 to be relative to the beginning of the section. */
4113 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4114 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4115 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4117 if (exp->X_op != O_symbol)
4119 as_bad (_("bad expression used with @%s"),
4120 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4126 if (S_IS_LOCAL (exp->X_add_symbol)
4127 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4128 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4129 exp->X_op = O_subtract;
4130 exp->X_op_symbol = GOT_symbol;
4131 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4132 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4133 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4134 i.reloc[this_operand] = BFD_RELOC_64;
4136 i.reloc[this_operand] = BFD_RELOC_32;
4139 if (exp->X_op == O_absent || exp->X_op == O_big)
4141 /* Missing or bad expr becomes absolute 0. */
4142 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4144 exp->X_op = O_constant;
4145 exp->X_add_number = 0;
4146 exp->X_add_symbol = (symbolS *) 0;
4147 exp->X_op_symbol = (symbolS *) 0;
4150 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4151 if (exp->X_op != O_constant
4152 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4153 && exp_seg != absolute_section
4154 && exp_seg != text_section
4155 && exp_seg != data_section
4156 && exp_seg != bss_section
4157 && exp_seg != undefined_section
4158 && !bfd_is_com_section (exp_seg))
4160 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4164 else if (flag_code == CODE_64BIT)
4165 i.types[this_operand] |= Disp32S | Disp32;
4169 static int i386_index_check PARAMS ((const char *));
4171 /* Make sure the memory operand we've been dealt is valid.
4172 Return 1 on success, 0 on a failure. */
4175 i386_index_check (operand_string)
4176 const char *operand_string;
4179 #if INFER_ADDR_PREFIX
4185 if (flag_code == CODE_64BIT)
4187 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4190 && ((i.base_reg->reg_type & RegXX) == 0)
4191 && (i.base_reg->reg_type != BaseIndex
4194 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4195 != (RegXX | BaseIndex))))
4200 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4204 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4205 != (Reg16 | BaseIndex)))
4207 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4208 != (Reg16 | BaseIndex))
4210 && i.base_reg->reg_num < 6
4211 && i.index_reg->reg_num >= 6
4212 && i.log2_scale_factor == 0))))
4219 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4221 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4222 != (Reg32 | BaseIndex))))
4228 #if INFER_ADDR_PREFIX
4229 if (i.prefix[ADDR_PREFIX] == 0)
4231 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4233 /* Change the size of any displacement too. At most one of
4234 Disp16 or Disp32 is set.
4235 FIXME. There doesn't seem to be any real need for separate
4236 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4237 Removing them would probably clean up the code quite a lot. */
4238 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4239 i.types[this_operand] ^= (Disp16 | Disp32);
4244 as_bad (_("`%s' is not a valid base/index expression"),
4248 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4250 flag_code_names[flag_code]);
4255 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4259 i386_operand (operand_string)
4260 char *operand_string;
4264 char *op_string = operand_string;
4266 if (is_space_char (*op_string))
4269 /* We check for an absolute prefix (differentiating,
4270 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4271 if (*op_string == ABSOLUTE_PREFIX)
4274 if (is_space_char (*op_string))
4276 i.types[this_operand] |= JumpAbsolute;
4279 /* Check if operand is a register. */
4280 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4281 && (r = parse_register (op_string, &end_op)) != NULL)
4283 /* Check for a segment override by searching for ':' after a
4284 segment register. */
4286 if (is_space_char (*op_string))
4288 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4293 i.seg[i.mem_operands] = &es;
4296 i.seg[i.mem_operands] = &cs;
4299 i.seg[i.mem_operands] = &ss;
4302 i.seg[i.mem_operands] = &ds;
4305 i.seg[i.mem_operands] = &fs;
4308 i.seg[i.mem_operands] = &gs;
4312 /* Skip the ':' and whitespace. */
4314 if (is_space_char (*op_string))
4317 if (!is_digit_char (*op_string)
4318 && !is_identifier_char (*op_string)
4319 && *op_string != '('
4320 && *op_string != ABSOLUTE_PREFIX)
4322 as_bad (_("bad memory operand `%s'"), op_string);
4325 /* Handle case of %es:*foo. */
4326 if (*op_string == ABSOLUTE_PREFIX)
4329 if (is_space_char (*op_string))
4331 i.types[this_operand] |= JumpAbsolute;
4333 goto do_memory_reference;
4337 as_bad (_("junk `%s' after register"), op_string);
4340 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4341 i.op[this_operand].regs = r;
4344 else if (*op_string == REGISTER_PREFIX)
4346 as_bad (_("bad register name `%s'"), op_string);
4349 else if (*op_string == IMMEDIATE_PREFIX)
4352 if (i.types[this_operand] & JumpAbsolute)
4354 as_bad (_("immediate operand illegal with absolute jump"));
4357 if (!i386_immediate (op_string))
4360 else if (is_digit_char (*op_string)
4361 || is_identifier_char (*op_string)
4362 || *op_string == '(')
4364 /* This is a memory reference of some sort. */
4367 /* Start and end of displacement string expression (if found). */
4368 char *displacement_string_start;
4369 char *displacement_string_end;
4371 do_memory_reference:
4372 if ((i.mem_operands == 1
4373 && (current_templates->start->opcode_modifier & IsString) == 0)
4374 || i.mem_operands == 2)
4376 as_bad (_("too many memory references for `%s'"),
4377 current_templates->start->name);
4381 /* Check for base index form. We detect the base index form by
4382 looking for an ')' at the end of the operand, searching
4383 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4385 base_string = op_string + strlen (op_string);
4388 if (is_space_char (*base_string))
4391 /* If we only have a displacement, set-up for it to be parsed later. */
4392 displacement_string_start = op_string;
4393 displacement_string_end = base_string + 1;
4395 if (*base_string == ')')
4398 unsigned int parens_balanced = 1;
4399 /* We've already checked that the number of left & right ()'s are
4400 equal, so this loop will not be infinite. */
4404 if (*base_string == ')')
4406 if (*base_string == '(')
4409 while (parens_balanced);
4411 temp_string = base_string;
4413 /* Skip past '(' and whitespace. */
4415 if (is_space_char (*base_string))
4418 if (*base_string == ','
4419 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4420 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4422 displacement_string_end = temp_string;
4424 i.types[this_operand] |= BaseIndex;
4428 base_string = end_op;
4429 if (is_space_char (*base_string))
4433 /* There may be an index reg or scale factor here. */
4434 if (*base_string == ',')
4437 if (is_space_char (*base_string))
4440 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4441 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4443 base_string = end_op;
4444 if (is_space_char (*base_string))
4446 if (*base_string == ',')
4449 if (is_space_char (*base_string))
4452 else if (*base_string != ')')
4454 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4459 else if (*base_string == REGISTER_PREFIX)
4461 as_bad (_("bad register name `%s'"), base_string);
4465 /* Check for scale factor. */
4466 if (*base_string != ')')
4468 char *end_scale = i386_scale (base_string);
4473 base_string = end_scale;
4474 if (is_space_char (*base_string))
4476 if (*base_string != ')')
4478 as_bad (_("expecting `)' after scale factor in `%s'"),
4483 else if (!i.index_reg)
4485 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4490 else if (*base_string != ')')
4492 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4497 else if (*base_string == REGISTER_PREFIX)
4499 as_bad (_("bad register name `%s'"), base_string);
4504 /* If there's an expression beginning the operand, parse it,
4505 assuming displacement_string_start and
4506 displacement_string_end are meaningful. */
4507 if (displacement_string_start != displacement_string_end)
4509 if (!i386_displacement (displacement_string_start,
4510 displacement_string_end))
4514 /* Special case for (%dx) while doing input/output op. */
4516 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4518 && i.log2_scale_factor == 0
4519 && i.seg[i.mem_operands] == 0
4520 && (i.types[this_operand] & Disp) == 0)
4522 i.types[this_operand] = InOutPortReg;
4526 if (i386_index_check (operand_string) == 0)
4532 /* It's not a memory operand; argh! */
4533 as_bad (_("invalid char %s beginning operand %d `%s'"),
4534 output_invalid (*op_string),
4539 return 1; /* Normal return. */
4542 /* md_estimate_size_before_relax()
4544 Called just before relax() for rs_machine_dependent frags. The x86
4545 assembler uses these frags to handle variable size jump
4548 Any symbol that is now undefined will not become defined.
4549 Return the correct fr_subtype in the frag.
4550 Return the initial "guess for variable size of frag" to caller.
4551 The guess is actually the growth beyond the fixed part. Whatever
4552 we do to grow the fixed or variable part contributes to our
4556 md_estimate_size_before_relax (fragP, segment)
4560 /* We've already got fragP->fr_subtype right; all we have to do is
4561 check for un-relaxable symbols. On an ELF system, we can't relax
4562 an externally visible symbol, because it may be overridden by a
4564 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4566 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4567 && (S_IS_EXTERNAL (fragP->fr_symbol)
4568 || S_IS_WEAK (fragP->fr_symbol)))
4572 /* Symbol is undefined in this segment, or we need to keep a
4573 reloc so that weak symbols can be overridden. */
4574 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4575 enum bfd_reloc_code_real reloc_type;
4576 unsigned char *opcode;
4579 if (fragP->fr_var != NO_RELOC)
4580 reloc_type = fragP->fr_var;
4582 reloc_type = BFD_RELOC_16_PCREL;
4584 reloc_type = BFD_RELOC_32_PCREL;
4586 old_fr_fix = fragP->fr_fix;
4587 opcode = (unsigned char *) fragP->fr_opcode;
4589 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4592 /* Make jmp (0xeb) a (d)word displacement jump. */
4594 fragP->fr_fix += size;
4595 fix_new (fragP, old_fr_fix, size,
4597 fragP->fr_offset, 1,
4603 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4605 /* Negate the condition, and branch past an
4606 unconditional jump. */
4609 /* Insert an unconditional jump. */
4611 /* We added two extra opcode bytes, and have a two byte
4613 fragP->fr_fix += 2 + 2;
4614 fix_new (fragP, old_fr_fix + 2, 2,
4616 fragP->fr_offset, 1,
4623 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4628 fixP = fix_new (fragP, old_fr_fix, 1,
4630 fragP->fr_offset, 1,
4632 fixP->fx_signed = 1;
4636 /* This changes the byte-displacement jump 0x7N
4637 to the (d)word-displacement jump 0x0f,0x8N. */
4638 opcode[1] = opcode[0] + 0x10;
4639 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4640 /* We've added an opcode byte. */
4641 fragP->fr_fix += 1 + size;
4642 fix_new (fragP, old_fr_fix + 1, size,
4644 fragP->fr_offset, 1,
4649 BAD_CASE (fragP->fr_subtype);
4653 return fragP->fr_fix - old_fr_fix;
4656 /* Guess size depending on current relax state. Initially the relax
4657 state will correspond to a short jump and we return 1, because
4658 the variable part of the frag (the branch offset) is one byte
4659 long. However, we can relax a section more than once and in that
4660 case we must either set fr_subtype back to the unrelaxed state,
4661 or return the value for the appropriate branch. */
4662 return md_relax_table[fragP->fr_subtype].rlx_length;
4665 /* Called after relax() is finished.
4667 In: Address of frag.
4668 fr_type == rs_machine_dependent.
4669 fr_subtype is what the address relaxed to.
4671 Out: Any fixSs and constants are set up.
4672 Caller will turn frag into a ".space 0". */
4675 md_convert_frag (abfd, sec, fragP)
4676 bfd *abfd ATTRIBUTE_UNUSED;
4677 segT sec ATTRIBUTE_UNUSED;
4680 unsigned char *opcode;
4681 unsigned char *where_to_put_displacement = NULL;
4682 offsetT target_address;
4683 offsetT opcode_address;
4684 unsigned int extension = 0;
4685 offsetT displacement_from_opcode_start;
4687 opcode = (unsigned char *) fragP->fr_opcode;
4689 /* Address we want to reach in file space. */
4690 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4692 /* Address opcode resides at in file space. */
4693 opcode_address = fragP->fr_address + fragP->fr_fix;
4695 /* Displacement from opcode start to fill into instruction. */
4696 displacement_from_opcode_start = target_address - opcode_address;
4698 if ((fragP->fr_subtype & BIG) == 0)
4700 /* Don't have to change opcode. */
4701 extension = 1; /* 1 opcode + 1 displacement */
4702 where_to_put_displacement = &opcode[1];
4706 if (no_cond_jump_promotion
4707 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4708 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4710 switch (fragP->fr_subtype)
4712 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4713 extension = 4; /* 1 opcode + 4 displacement */
4715 where_to_put_displacement = &opcode[1];
4718 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4719 extension = 2; /* 1 opcode + 2 displacement */
4721 where_to_put_displacement = &opcode[1];
4724 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4725 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4726 extension = 5; /* 2 opcode + 4 displacement */
4727 opcode[1] = opcode[0] + 0x10;
4728 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4729 where_to_put_displacement = &opcode[2];
4732 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4733 extension = 3; /* 2 opcode + 2 displacement */
4734 opcode[1] = opcode[0] + 0x10;
4735 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4736 where_to_put_displacement = &opcode[2];
4739 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4744 where_to_put_displacement = &opcode[3];
4748 BAD_CASE (fragP->fr_subtype);
4753 /* Now put displacement after opcode. */
4754 md_number_to_chars ((char *) where_to_put_displacement,
4755 (valueT) (displacement_from_opcode_start - extension),
4756 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4757 fragP->fr_fix += extension;
4760 /* Size of byte displacement jmp. */
4761 int md_short_jump_size = 2;
4763 /* Size of dword displacement jmp. */
4764 int md_long_jump_size = 5;
4766 /* Size of relocation record. */
4767 const int md_reloc_size = 8;
4770 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4772 addressT from_addr, to_addr;
4773 fragS *frag ATTRIBUTE_UNUSED;
4774 symbolS *to_symbol ATTRIBUTE_UNUSED;
4778 offset = to_addr - (from_addr + 2);
4779 /* Opcode for byte-disp jump. */
4780 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4781 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4785 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4787 addressT from_addr, to_addr;
4788 fragS *frag ATTRIBUTE_UNUSED;
4789 symbolS *to_symbol ATTRIBUTE_UNUSED;
4793 offset = to_addr - (from_addr + 5);
4794 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4795 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4798 /* Apply a fixup (fixS) to segment data, once it has been determined
4799 by our caller that we have all the info we need to fix it up.
4801 On the 386, immediates, displacements, and data pointers are all in
4802 the same (little-endian) format, so we don't need to care about which
4806 md_apply_fix (fixP, valP, seg)
4807 /* The fix we're to put in. */
4809 /* Pointer to the value of the bits. */
4811 /* Segment fix is from. */
4812 segT seg ATTRIBUTE_UNUSED;
4814 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4815 valueT value = *valP;
4817 #if !defined (TE_Mach)
4820 switch (fixP->fx_r_type)
4826 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4829 case BFD_RELOC_X86_64_32S:
4830 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4833 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4836 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4841 if (fixP->fx_addsy != NULL
4842 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4843 || fixP->fx_r_type == BFD_RELOC_64_PCREL
4844 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4845 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4846 && !use_rela_relocations)
4848 /* This is a hack. There should be a better way to handle this.
4849 This covers for the fact that bfd_install_relocation will
4850 subtract the current location (for partial_inplace, PC relative
4851 relocations); see more below. */
4853 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4855 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4858 value += fixP->fx_where + fixP->fx_frag->fr_address;
4860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4861 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4863 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
4866 || (symbol_section_p (fixP->fx_addsy)
4867 && sym_seg != absolute_section))
4868 && !generic_force_reloc (fixP))
4870 /* Yes, we add the values in twice. This is because
4871 bfd_install_relocation subtracts them out again. I think
4872 bfd_install_relocation is broken, but I don't dare change
4874 value += fixP->fx_where + fixP->fx_frag->fr_address;
4878 #if defined (OBJ_COFF) && defined (TE_PE)
4879 /* For some reason, the PE format does not store a
4880 section address offset for a PC relative symbol. */
4881 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4882 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4883 || S_IS_WEAK (fixP->fx_addsy)
4886 value += md_pcrel_from (fixP);
4890 /* Fix a few things - the dynamic linker expects certain values here,
4891 and we must not disappoint it. */
4892 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4893 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4895 switch (fixP->fx_r_type)
4897 case BFD_RELOC_386_PLT32:
4898 case BFD_RELOC_X86_64_PLT32:
4899 /* Make the jump instruction point to the address of the operand. At
4900 runtime we merely add the offset to the actual PLT entry. */
4904 case BFD_RELOC_386_TLS_GD:
4905 case BFD_RELOC_386_TLS_LDM:
4906 case BFD_RELOC_386_TLS_IE_32:
4907 case BFD_RELOC_386_TLS_IE:
4908 case BFD_RELOC_386_TLS_GOTIE:
4909 case BFD_RELOC_X86_64_TLSGD:
4910 case BFD_RELOC_X86_64_TLSLD:
4911 case BFD_RELOC_X86_64_GOTTPOFF:
4912 value = 0; /* Fully resolved at runtime. No addend. */
4914 case BFD_RELOC_386_TLS_LE:
4915 case BFD_RELOC_386_TLS_LDO_32:
4916 case BFD_RELOC_386_TLS_LE_32:
4917 case BFD_RELOC_X86_64_DTPOFF32:
4918 case BFD_RELOC_X86_64_DTPOFF64:
4919 case BFD_RELOC_X86_64_TPOFF32:
4920 case BFD_RELOC_X86_64_TPOFF64:
4921 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4924 case BFD_RELOC_386_GOT32:
4925 case BFD_RELOC_X86_64_GOT32:
4926 value = 0; /* Fully resolved at runtime. No addend. */
4929 case BFD_RELOC_VTABLE_INHERIT:
4930 case BFD_RELOC_VTABLE_ENTRY:
4937 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4939 #endif /* !defined (TE_Mach) */
4941 /* Are we finished with this relocation now? */
4942 if (fixP->fx_addsy == NULL)
4944 else if (use_rela_relocations)
4946 fixP->fx_no_overflow = 1;
4947 /* Remember value for tc_gen_reloc. */
4948 fixP->fx_addnumber = value;
4952 md_number_to_chars (p, value, fixP->fx_size);
4955 #define MAX_LITTLENUMS 6
4957 /* Turn the string pointed to by litP into a floating point constant
4958 of type TYPE, and emit the appropriate bytes. The number of
4959 LITTLENUMS emitted is stored in *SIZEP. An error message is
4960 returned, or NULL on OK. */
4963 md_atof (type, litP, sizeP)
4969 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4970 LITTLENUM_TYPE *wordP;
4992 return _("Bad call to md_atof ()");
4994 t = atof_ieee (input_line_pointer, type, words);
4996 input_line_pointer = t;
4998 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4999 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5000 the bigendian 386. */
5001 for (wordP = words + prec - 1; prec--;)
5003 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5004 litP += sizeof (LITTLENUM_TYPE);
5009 static char output_invalid_buf[8];
5016 sprintf (output_invalid_buf, "'%c'", c);
5018 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5019 return output_invalid_buf;
5022 /* REG_STRING starts *before* REGISTER_PREFIX. */
5024 static const reg_entry *
5025 parse_register (reg_string, end_op)
5029 char *s = reg_string;
5031 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5034 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5035 if (*s == REGISTER_PREFIX)
5038 if (is_space_char (*s))
5042 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5044 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5045 return (const reg_entry *) NULL;
5049 /* For naked regs, make sure that we are not dealing with an identifier.
5050 This prevents confusing an identifier like `eax_var' with register
5052 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5053 return (const reg_entry *) NULL;
5057 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5059 /* Handle floating point regs, allowing spaces in the (i) part. */
5060 if (r == i386_regtab /* %st is first entry of table */)
5062 if (is_space_char (*s))
5067 if (is_space_char (*s))
5069 if (*s >= '0' && *s <= '7')
5071 r = &i386_float_regtab[*s - '0'];
5073 if (is_space_char (*s))
5081 /* We have "%st(" then garbage. */
5082 return (const reg_entry *) NULL;
5087 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5088 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5089 && flag_code != CODE_64BIT)
5090 return (const reg_entry *) NULL;
5095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5096 const char *md_shortopts = "kVQ:sqn";
5098 const char *md_shortopts = "qn";
5101 struct option md_longopts[] = {
5102 #define OPTION_32 (OPTION_MD_BASE + 0)
5103 {"32", no_argument, NULL, OPTION_32},
5104 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5105 #define OPTION_64 (OPTION_MD_BASE + 1)
5106 {"64", no_argument, NULL, OPTION_64},
5108 {NULL, no_argument, NULL, 0}
5110 size_t md_longopts_size = sizeof (md_longopts);
5113 md_parse_option (c, arg)
5115 char *arg ATTRIBUTE_UNUSED;
5120 optimize_align_code = 0;
5127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5128 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5129 should be emitted or not. FIXME: Not implemented. */
5133 /* -V: SVR4 argument to print version ID. */
5135 print_version_id ();
5138 /* -k: Ignore for FreeBSD compatibility. */
5143 /* -s: On i386 Solaris, this tells the native assembler to use
5144 .stab instead of .stab.excl. We always use .stab anyhow. */
5149 const char **list, **l;
5151 list = bfd_target_list ();
5152 for (l = list; *l != NULL; l++)
5153 if (strcmp (*l, "elf64-x86-64") == 0)
5155 default_arch = "x86_64";
5159 as_fatal (_("No compiled in support for x86_64"));
5166 default_arch = "i386";
5176 md_show_usage (stream)
5179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5180 fprintf (stream, _("\
5182 -V print assembler version number\n\
5184 -n Do not optimize code alignment\n\
5185 -q quieten some warnings\n\
5188 fprintf (stream, _("\
5189 -n Do not optimize code alignment\n\
5190 -q quieten some warnings\n"));
5194 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5195 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5197 /* Pick the target format to use. */
5200 i386_target_format ()
5202 if (!strcmp (default_arch, "x86_64"))
5203 set_code_flag (CODE_64BIT);
5204 else if (!strcmp (default_arch, "i386"))
5205 set_code_flag (CODE_32BIT);
5207 as_fatal (_("Unknown architecture"));
5208 switch (OUTPUT_FLAVOR)
5210 #ifdef OBJ_MAYBE_AOUT
5211 case bfd_target_aout_flavour:
5212 return AOUT_TARGET_FORMAT;
5214 #ifdef OBJ_MAYBE_COFF
5215 case bfd_target_coff_flavour:
5218 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5219 case bfd_target_elf_flavour:
5221 if (flag_code == CODE_64BIT)
5222 use_rela_relocations = 1;
5223 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5232 #endif /* OBJ_MAYBE_ more than one */
5234 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5235 void i386_elf_emit_arch_note ()
5237 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5238 && cpu_arch_name != NULL)
5241 asection *seg = now_seg;
5242 subsegT subseg = now_subseg;
5243 Elf_Internal_Note i_note;
5244 Elf_External_Note e_note;
5245 asection *note_secp;
5248 /* Create the .note section. */
5249 note_secp = subseg_new (".note", 0);
5250 bfd_set_section_flags (stdoutput,
5252 SEC_HAS_CONTENTS | SEC_READONLY);
5254 /* Process the arch string. */
5255 len = strlen (cpu_arch_name);
5257 i_note.namesz = len + 1;
5259 i_note.type = NT_ARCH;
5260 p = frag_more (sizeof (e_note.namesz));
5261 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5262 p = frag_more (sizeof (e_note.descsz));
5263 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5264 p = frag_more (sizeof (e_note.type));
5265 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5266 p = frag_more (len + 1);
5267 strcpy (p, cpu_arch_name);
5269 frag_align (2, 0, 0);
5271 subseg_set (seg, subseg);
5277 md_undefined_symbol (name)
5280 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5281 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5282 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5283 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5287 if (symbol_find (name))
5288 as_bad (_("GOT already in symbol table"));
5289 GOT_symbol = symbol_new (name, undefined_section,
5290 (valueT) 0, &zero_address_frag);
5297 /* Round up a section size to the appropriate boundary. */
5300 md_section_align (segment, size)
5301 segT segment ATTRIBUTE_UNUSED;
5304 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5305 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5307 /* For a.out, force the section size to be aligned. If we don't do
5308 this, BFD will align it for us, but it will not write out the
5309 final bytes of the section. This may be a bug in BFD, but it is
5310 easier to fix it here since that is how the other a.out targets
5314 align = bfd_get_section_alignment (stdoutput, segment);
5315 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5322 /* On the i386, PC-relative offsets are relative to the start of the
5323 next instruction. That is, the address of the offset, plus its
5324 size, since the offset is always the last part of the insn. */
5327 md_pcrel_from (fixP)
5330 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5337 int ignore ATTRIBUTE_UNUSED;
5341 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5343 obj_elf_section_change_hook ();
5345 temp = get_absolute_expression ();
5346 subseg_set (bss_section, (subsegT) temp);
5347 demand_empty_rest_of_line ();
5353 i386_validate_fix (fixp)
5356 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5358 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5360 if (flag_code != CODE_64BIT)
5362 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5366 if (flag_code != CODE_64BIT)
5367 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5369 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
5376 tc_gen_reloc (section, fixp)
5377 asection *section ATTRIBUTE_UNUSED;
5381 bfd_reloc_code_real_type code;
5383 switch (fixp->fx_r_type)
5385 case BFD_RELOC_X86_64_PLT32:
5386 case BFD_RELOC_X86_64_GOT32:
5387 case BFD_RELOC_X86_64_GOTPCREL:
5388 case BFD_RELOC_386_PLT32:
5389 case BFD_RELOC_386_GOT32:
5390 case BFD_RELOC_386_GOTOFF:
5391 case BFD_RELOC_386_GOTPC:
5392 case BFD_RELOC_386_TLS_GD:
5393 case BFD_RELOC_386_TLS_LDM:
5394 case BFD_RELOC_386_TLS_LDO_32:
5395 case BFD_RELOC_386_TLS_IE_32:
5396 case BFD_RELOC_386_TLS_IE:
5397 case BFD_RELOC_386_TLS_GOTIE:
5398 case BFD_RELOC_386_TLS_LE_32:
5399 case BFD_RELOC_386_TLS_LE:
5400 case BFD_RELOC_X86_64_TLSGD:
5401 case BFD_RELOC_X86_64_TLSLD:
5402 case BFD_RELOC_X86_64_DTPOFF32:
5403 case BFD_RELOC_X86_64_DTPOFF64:
5404 case BFD_RELOC_X86_64_GOTTPOFF:
5405 case BFD_RELOC_X86_64_TPOFF32:
5406 case BFD_RELOC_X86_64_TPOFF64:
5407 case BFD_RELOC_X86_64_GOTOFF64:
5408 case BFD_RELOC_X86_64_GOTPC32:
5410 case BFD_RELOC_VTABLE_ENTRY:
5411 case BFD_RELOC_VTABLE_INHERIT:
5413 case BFD_RELOC_32_SECREL:
5415 code = fixp->fx_r_type;
5417 case BFD_RELOC_X86_64_32S:
5418 if (!fixp->fx_pcrel)
5420 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5421 code = fixp->fx_r_type;
5427 switch (fixp->fx_size)
5430 as_bad_where (fixp->fx_file, fixp->fx_line,
5431 _("can not do %d byte pc-relative relocation"),
5433 code = BFD_RELOC_32_PCREL;
5435 case 1: code = BFD_RELOC_8_PCREL; break;
5436 case 2: code = BFD_RELOC_16_PCREL; break;
5437 case 4: code = BFD_RELOC_32_PCREL; break;
5439 case 8: code = BFD_RELOC_64_PCREL; break;
5445 switch (fixp->fx_size)
5448 as_bad_where (fixp->fx_file, fixp->fx_line,
5449 _("can not do %d byte relocation"),
5451 code = BFD_RELOC_32;
5453 case 1: code = BFD_RELOC_8; break;
5454 case 2: code = BFD_RELOC_16; break;
5455 case 4: code = BFD_RELOC_32; break;
5457 case 8: code = BFD_RELOC_64; break;
5464 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
5466 && fixp->fx_addsy == GOT_symbol)
5468 if (flag_code != CODE_64BIT)
5469 code = BFD_RELOC_386_GOTPC;
5471 code = BFD_RELOC_X86_64_GOTPC32;
5474 rel = (arelent *) xmalloc (sizeof (arelent));
5475 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5476 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5478 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5480 if (!use_rela_relocations)
5482 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5483 vtable entry to be used in the relocation's section offset. */
5484 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5485 rel->address = fixp->fx_offset;
5489 /* Use the rela in 64bit mode. */
5492 if (!fixp->fx_pcrel)
5493 rel->addend = fixp->fx_offset;
5497 case BFD_RELOC_X86_64_PLT32:
5498 case BFD_RELOC_X86_64_GOT32:
5499 case BFD_RELOC_X86_64_GOTPCREL:
5500 case BFD_RELOC_X86_64_TLSGD:
5501 case BFD_RELOC_X86_64_TLSLD:
5502 case BFD_RELOC_X86_64_GOTTPOFF:
5503 rel->addend = fixp->fx_offset - fixp->fx_size;
5506 rel->addend = (section->vma
5508 + fixp->fx_addnumber
5509 + md_pcrel_from (fixp));
5514 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5515 if (rel->howto == NULL)
5517 as_bad_where (fixp->fx_file, fixp->fx_line,
5518 _("cannot represent relocation type %s"),
5519 bfd_get_reloc_code_name (code));
5520 /* Set howto to a garbage value so that we can keep going. */
5521 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5522 assert (rel->howto != NULL);
5529 /* Parse operands using Intel syntax. This implements a recursive descent
5530 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5533 FIXME: We do not recognize the full operand grammar defined in the MASM
5534 documentation. In particular, all the structure/union and
5535 high-level macro operands are missing.
5537 Uppercase words are terminals, lower case words are non-terminals.
5538 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5539 bars '|' denote choices. Most grammar productions are implemented in
5540 functions called 'intel_<production>'.
5542 Initial production is 'expr'.
5548 binOp & | AND | \| | OR | ^ | XOR
5550 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5552 constant digits [[ radixOverride ]]
5554 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5592 => expr expr cmpOp e04
5595 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5596 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5598 hexdigit a | b | c | d | e | f
5599 | A | B | C | D | E | F
5605 mulOp * | / | % | MOD | << | SHL | >> | SHR
5609 register specialRegister
5613 segmentRegister CS | DS | ES | FS | GS | SS
5615 specialRegister CR0 | CR2 | CR3 | CR4
5616 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5617 | TR3 | TR4 | TR5 | TR6 | TR7
5619 We simplify the grammar in obvious places (e.g., register parsing is
5620 done by calling parse_register) and eliminate immediate left recursion
5621 to implement a recursive-descent parser.
5625 expr' cmpOp e04 expr'
5676 /* Parsing structure for the intel syntax parser. Used to implement the
5677 semantic actions for the operand grammar. */
5678 struct intel_parser_s
5680 char *op_string; /* The string being parsed. */
5681 int got_a_float; /* Whether the operand is a float. */
5682 int op_modifier; /* Operand modifier. */
5683 int is_mem; /* 1 if operand is memory reference. */
5684 int in_offset; /* >=1 if parsing operand of offset. */
5685 int in_bracket; /* >=1 if parsing operand in brackets. */
5686 const reg_entry *reg; /* Last register reference found. */
5687 char *disp; /* Displacement string being built. */
5688 char *next_operand; /* Resume point when splitting operands. */
5691 static struct intel_parser_s intel_parser;
5693 /* Token structure for parsing intel syntax. */
5696 int code; /* Token code. */
5697 const reg_entry *reg; /* Register entry for register tokens. */
5698 char *str; /* String representation. */
5701 static struct intel_token cur_token, prev_token;
5703 /* Token codes for the intel parser. Since T_SHORT is already used
5704 by COFF, undefine it first to prevent a warning. */
5723 /* Prototypes for intel parser functions. */
5724 static int intel_match_token PARAMS ((int code));
5725 static void intel_get_token PARAMS ((void));
5726 static void intel_putback_token PARAMS ((void));
5727 static int intel_expr PARAMS ((void));
5728 static int intel_e04 PARAMS ((void));
5729 static int intel_e05 PARAMS ((void));
5730 static int intel_e06 PARAMS ((void));
5731 static int intel_e09 PARAMS ((void));
5732 static int intel_bracket_expr PARAMS ((void));
5733 static int intel_e10 PARAMS ((void));
5734 static int intel_e11 PARAMS ((void));
5737 i386_intel_operand (operand_string, got_a_float)
5738 char *operand_string;
5744 p = intel_parser.op_string = xstrdup (operand_string);
5745 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5749 /* Initialize token holders. */
5750 cur_token.code = prev_token.code = T_NIL;
5751 cur_token.reg = prev_token.reg = NULL;
5752 cur_token.str = prev_token.str = NULL;
5754 /* Initialize parser structure. */
5755 intel_parser.got_a_float = got_a_float;
5756 intel_parser.op_modifier = 0;
5757 intel_parser.is_mem = 0;
5758 intel_parser.in_offset = 0;
5759 intel_parser.in_bracket = 0;
5760 intel_parser.reg = NULL;
5761 intel_parser.disp[0] = '\0';
5762 intel_parser.next_operand = NULL;
5764 /* Read the first token and start the parser. */
5766 ret = intel_expr ();
5771 if (cur_token.code != T_NIL)
5773 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5774 current_templates->start->name, cur_token.str);
5777 /* If we found a memory reference, hand it over to i386_displacement
5778 to fill in the rest of the operand fields. */
5779 else if (intel_parser.is_mem)
5781 if ((i.mem_operands == 1
5782 && (current_templates->start->opcode_modifier & IsString) == 0)
5783 || i.mem_operands == 2)
5785 as_bad (_("too many memory references for '%s'"),
5786 current_templates->start->name);
5791 char *s = intel_parser.disp;
5794 if (!quiet_warnings && intel_parser.is_mem < 0)
5795 /* See the comments in intel_bracket_expr. */
5796 as_warn (_("Treating `%s' as memory reference"), operand_string);
5798 /* Add the displacement expression. */
5800 ret = i386_displacement (s, s + strlen (s));
5803 /* Swap base and index in 16-bit memory operands like
5804 [si+bx]. Since i386_index_check is also used in AT&T
5805 mode we have to do that here. */
5808 && (i.base_reg->reg_type & Reg16)
5809 && (i.index_reg->reg_type & Reg16)
5810 && i.base_reg->reg_num >= 6
5811 && i.index_reg->reg_num < 6)
5813 const reg_entry *base = i.index_reg;
5815 i.index_reg = i.base_reg;
5818 ret = i386_index_check (operand_string);
5823 /* Constant and OFFSET expressions are handled by i386_immediate. */
5824 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
5825 || intel_parser.reg == NULL)
5826 ret = i386_immediate (intel_parser.disp);
5828 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5830 if (!ret || !intel_parser.next_operand)
5832 intel_parser.op_string = intel_parser.next_operand;
5833 this_operand = i.operands++;
5837 free (intel_parser.disp);
5842 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5846 expr' cmpOp e04 expr'
5851 /* XXX Implement the comparison operators. */
5852 return intel_e04 ();
5869 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5870 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
5872 if (cur_token.code == '+')
5874 else if (cur_token.code == '-')
5875 nregs = NUM_ADDRESS_REGS;
5879 strcat (intel_parser.disp, cur_token.str);
5880 intel_match_token (cur_token.code);
5891 int nregs = ~NUM_ADDRESS_REGS;
5898 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5902 str[0] = cur_token.code;
5904 strcat (intel_parser.disp, str);
5909 intel_match_token (cur_token.code);
5914 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5915 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
5926 int nregs = ~NUM_ADDRESS_REGS;
5933 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
5937 str[0] = cur_token.code;
5939 strcat (intel_parser.disp, str);
5941 else if (cur_token.code == T_SHL)
5942 strcat (intel_parser.disp, "<<");
5943 else if (cur_token.code == T_SHR)
5944 strcat (intel_parser.disp, ">>");
5948 intel_match_token (cur_token.code);
5953 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5954 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
5972 int nregs = ~NUM_ADDRESS_REGS;
5977 /* Don't consume constants here. */
5978 if (cur_token.code == '+' || cur_token.code == '-')
5980 /* Need to look one token ahead - if the next token
5981 is a constant, the current token is its sign. */
5984 intel_match_token (cur_token.code);
5985 next_code = cur_token.code;
5986 intel_putback_token ();
5987 if (next_code == T_CONST)
5991 /* e09 OFFSET e09 */
5992 if (cur_token.code == T_OFFSET)
5995 ++intel_parser.in_offset;
5999 else if (cur_token.code == T_SHORT)
6000 intel_parser.op_modifier |= 1 << T_SHORT;
6003 else if (cur_token.code == '+')
6004 strcat (intel_parser.disp, "+");
6009 else if (cur_token.code == '-' || cur_token.code == '~')
6015 str[0] = cur_token.code;
6017 strcat (intel_parser.disp, str);
6024 intel_match_token (cur_token.code);
6032 /* e09' PTR e10 e09' */
6033 if (cur_token.code == T_PTR)
6037 if (prev_token.code == T_BYTE)
6038 suffix = BYTE_MNEM_SUFFIX;
6040 else if (prev_token.code == T_WORD)
6042 if (current_templates->start->name[0] == 'l'
6043 && current_templates->start->name[2] == 's'
6044 && current_templates->start->name[3] == 0)
6045 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6046 else if (intel_parser.got_a_float == 2) /* "fi..." */
6047 suffix = SHORT_MNEM_SUFFIX;
6049 suffix = WORD_MNEM_SUFFIX;
6052 else if (prev_token.code == T_DWORD)
6054 if (current_templates->start->name[0] == 'l'
6055 && current_templates->start->name[2] == 's'
6056 && current_templates->start->name[3] == 0)
6057 suffix = WORD_MNEM_SUFFIX;
6058 else if (flag_code == CODE_16BIT
6059 && (current_templates->start->opcode_modifier
6060 & (Jump|JumpDword|JumpInterSegment)))
6061 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6062 else if (intel_parser.got_a_float == 1) /* "f..." */
6063 suffix = SHORT_MNEM_SUFFIX;
6065 suffix = LONG_MNEM_SUFFIX;
6068 else if (prev_token.code == T_FWORD)
6070 if (current_templates->start->name[0] == 'l'
6071 && current_templates->start->name[2] == 's'
6072 && current_templates->start->name[3] == 0)
6073 suffix = LONG_MNEM_SUFFIX;
6074 else if (!intel_parser.got_a_float)
6076 if (flag_code == CODE_16BIT)
6077 add_prefix (DATA_PREFIX_OPCODE);
6078 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6081 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6084 else if (prev_token.code == T_QWORD)
6086 if (intel_parser.got_a_float == 1) /* "f..." */
6087 suffix = LONG_MNEM_SUFFIX;
6089 suffix = QWORD_MNEM_SUFFIX;
6092 else if (prev_token.code == T_TBYTE)
6094 if (intel_parser.got_a_float == 1)
6095 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6097 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6100 else if (prev_token.code == T_XMMWORD)
6102 /* XXX ignored for now, but accepted since gcc uses it */
6108 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6112 if (current_templates->start->base_opcode == 0x8d /* lea */)
6116 else if (i.suffix != suffix)
6118 as_bad (_("Conflicting operand modifiers"));
6124 /* e09' : e10 e09' */
6125 else if (cur_token.code == ':')
6127 if (prev_token.code != T_REG)
6129 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6130 segment/group identifier (which we don't have), using comma
6131 as the operand separator there is even less consistent, since
6132 there all branches only have a single operand. */
6133 if (this_operand != 0
6134 || intel_parser.in_offset
6135 || intel_parser.in_bracket
6136 || (!(current_templates->start->opcode_modifier
6137 & (Jump|JumpDword|JumpInterSegment))
6138 && !(current_templates->start->operand_types[0]
6140 return intel_match_token (T_NIL);
6141 /* Remember the start of the 2nd operand and terminate 1st
6143 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6144 another expression), but it gets at least the simplest case
6145 (a plain number or symbol on the left side) right. */
6146 intel_parser.next_operand = intel_parser.op_string;
6147 *--intel_parser.op_string = '\0';
6148 return intel_match_token (':');
6156 intel_match_token (cur_token.code);
6162 --intel_parser.in_offset;
6165 if (NUM_ADDRESS_REGS > nregs)
6167 as_bad (_("Invalid operand to `OFFSET'"));
6170 intel_parser.op_modifier |= 1 << T_OFFSET;
6173 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6174 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6179 intel_bracket_expr ()
6181 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6182 const char *start = intel_parser.op_string;
6185 if (i.op[this_operand].regs)
6186 return intel_match_token (T_NIL);
6188 intel_match_token ('[');
6190 /* Mark as a memory operand only if it's not already known to be an
6191 offset expression. If it's an offset expression, we need to keep
6193 if (!intel_parser.in_offset)
6195 ++intel_parser.in_bracket;
6196 /* Unfortunately gas always diverged from MASM in a respect that can't
6197 be easily fixed without risking to break code sequences likely to be
6198 encountered (the testsuite even check for this): MASM doesn't consider
6199 an expression inside brackets unconditionally as a memory reference.
6200 When that is e.g. a constant, an offset expression, or the sum of the
6201 two, this is still taken as a constant load. gas, however, always
6202 treated these as memory references. As a compromise, we'll try to make
6203 offset expressions inside brackets work the MASM way (since that's
6204 less likely to be found in real world code), but make constants alone
6205 continue to work the traditional gas way. In either case, issue a
6207 intel_parser.op_modifier &= ~was_offset;
6210 strcat (intel_parser.disp, "[");
6212 /* Add a '+' to the displacement string if necessary. */
6213 if (*intel_parser.disp != '\0'
6214 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6215 strcat (intel_parser.disp, "+");
6218 && (len = intel_parser.op_string - start - 1,
6219 intel_match_token (']')))
6221 /* Preserve brackets when the operand is an offset expression. */
6222 if (intel_parser.in_offset)
6223 strcat (intel_parser.disp, "]");
6226 --intel_parser.in_bracket;
6227 if (i.base_reg || i.index_reg)
6228 intel_parser.is_mem = 1;
6229 if (!intel_parser.is_mem)
6231 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6232 /* Defer the warning until all of the operand was parsed. */
6233 intel_parser.is_mem = -1;
6234 else if (!quiet_warnings)
6235 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6238 intel_parser.op_modifier |= was_offset;
6255 while (cur_token.code == '[')
6257 if (!intel_bracket_expr ())
6282 switch (cur_token.code)
6286 intel_match_token ('(');
6287 strcat (intel_parser.disp, "(");
6289 if (intel_expr () && intel_match_token (')'))
6291 strcat (intel_parser.disp, ")");
6298 /* Operands for jump/call inside brackets denote absolute addresses.
6299 XXX This shouldn't be needed anymore (or if it should rather live
6300 in intel_bracket_expr). */
6301 if (current_templates->start->opcode_modifier
6302 & (Jump|JumpDword|JumpByte|JumpInterSegment))
6303 i.types[this_operand] |= JumpAbsolute;
6305 return intel_bracket_expr ();
6310 strcat (intel_parser.disp, cur_token.str);
6311 intel_match_token (cur_token.code);
6313 /* Mark as a memory operand only if it's not already known to be an
6314 offset expression. */
6315 if (!intel_parser.in_offset)
6316 intel_parser.is_mem = 1;
6323 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6325 intel_match_token (T_REG);
6327 /* Check for segment change. */
6328 if (cur_token.code == ':')
6330 if (!(reg->reg_type & (SReg2 | SReg3)))
6332 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6335 else if (i.seg[i.mem_operands])
6336 as_warn (_("Extra segment override ignored"));
6339 if (!intel_parser.in_offset)
6340 intel_parser.is_mem = 1;
6341 switch (reg->reg_num)
6344 i.seg[i.mem_operands] = &es;
6347 i.seg[i.mem_operands] = &cs;
6350 i.seg[i.mem_operands] = &ss;
6353 i.seg[i.mem_operands] = &ds;
6356 i.seg[i.mem_operands] = &fs;
6359 i.seg[i.mem_operands] = &gs;
6365 /* Not a segment register. Check for register scaling. */
6366 else if (cur_token.code == '*')
6368 if (!intel_parser.in_bracket)
6370 as_bad (_("Register scaling only allowed in memory operands"));
6374 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6375 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6376 else if (i.index_reg)
6377 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6379 /* What follows must be a valid scale. */
6380 intel_match_token ('*');
6382 i.types[this_operand] |= BaseIndex;
6384 /* Set the scale after setting the register (otherwise,
6385 i386_scale will complain) */
6386 if (cur_token.code == '+' || cur_token.code == '-')
6388 char *str, sign = cur_token.code;
6389 intel_match_token (cur_token.code);
6390 if (cur_token.code != T_CONST)
6392 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6396 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6397 strcpy (str + 1, cur_token.str);
6399 if (!i386_scale (str))
6403 else if (!i386_scale (cur_token.str))
6405 intel_match_token (cur_token.code);
6408 /* No scaling. If this is a memory operand, the register is either a
6409 base register (first occurrence) or an index register (second
6411 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6416 else if (!i.index_reg)
6420 as_bad (_("Too many register references in memory operand"));
6424 i.types[this_operand] |= BaseIndex;
6427 /* Offset modifier. Add the register to the displacement string to be
6428 parsed as an immediate expression after we're done. */
6429 else if (intel_parser.in_offset)
6431 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6432 strcat (intel_parser.disp, reg->reg_name);
6435 /* It's neither base nor index nor offset. */
6436 else if (!intel_parser.is_mem)
6438 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6439 i.op[this_operand].regs = reg;
6444 as_bad (_("Invalid use of register"));
6448 /* Since registers are not part of the displacement string (except
6449 when we're parsing offset operands), we may need to remove any
6450 preceding '+' from the displacement string. */
6451 if (*intel_parser.disp != '\0'
6452 && !intel_parser.in_offset)
6454 char *s = intel_parser.disp;
6455 s += strlen (s) - 1;
6478 intel_match_token (cur_token.code);
6480 if (cur_token.code == T_PTR)
6483 /* It must have been an identifier. */
6484 intel_putback_token ();
6485 cur_token.code = T_ID;
6491 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
6495 /* The identifier represents a memory reference only if it's not
6496 preceded by an offset modifier and if it's not an equate. */
6497 symbolP = symbol_find(cur_token.str);
6498 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6499 intel_parser.is_mem = 1;
6507 char *save_str, sign = 0;
6509 /* Allow constants that start with `+' or `-'. */
6510 if (cur_token.code == '-' || cur_token.code == '+')
6512 sign = cur_token.code;
6513 intel_match_token (cur_token.code);
6514 if (cur_token.code != T_CONST)
6516 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6522 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6523 strcpy (save_str + !!sign, cur_token.str);
6527 /* Get the next token to check for register scaling. */
6528 intel_match_token (cur_token.code);
6530 /* Check if this constant is a scaling factor for an index register. */
6531 if (cur_token.code == '*')
6533 if (intel_match_token ('*') && cur_token.code == T_REG)
6535 const reg_entry *reg = cur_token.reg;
6537 if (!intel_parser.in_bracket)
6539 as_bad (_("Register scaling only allowed in memory operands"));
6543 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6544 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6545 else if (i.index_reg)
6546 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6548 /* The constant is followed by `* reg', so it must be
6551 i.types[this_operand] |= BaseIndex;
6553 /* Set the scale after setting the register (otherwise,
6554 i386_scale will complain) */
6555 if (!i386_scale (save_str))
6557 intel_match_token (T_REG);
6559 /* Since registers are not part of the displacement
6560 string, we may need to remove any preceding '+' from
6561 the displacement string. */
6562 if (*intel_parser.disp != '\0')
6564 char *s = intel_parser.disp;
6565 s += strlen (s) - 1;
6575 /* The constant was not used for register scaling. Since we have
6576 already consumed the token following `*' we now need to put it
6577 back in the stream. */
6578 intel_putback_token ();
6581 /* Add the constant to the displacement string. */
6582 strcat (intel_parser.disp, save_str);
6589 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6593 /* Match the given token against cur_token. If they match, read the next
6594 token from the operand string. */
6596 intel_match_token (code)
6599 if (cur_token.code == code)
6606 as_bad (_("Unexpected token `%s'"), cur_token.str);
6611 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6616 const reg_entry *reg;
6617 struct intel_token new_token;
6619 new_token.code = T_NIL;
6620 new_token.reg = NULL;
6621 new_token.str = NULL;
6623 /* Free the memory allocated to the previous token and move
6624 cur_token to prev_token. */
6626 free (prev_token.str);
6628 prev_token = cur_token;
6630 /* Skip whitespace. */
6631 while (is_space_char (*intel_parser.op_string))
6632 intel_parser.op_string++;
6634 /* Return an empty token if we find nothing else on the line. */
6635 if (*intel_parser.op_string == '\0')
6637 cur_token = new_token;
6641 /* The new token cannot be larger than the remainder of the operand
6643 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
6644 new_token.str[0] = '\0';
6646 if (strchr ("0123456789", *intel_parser.op_string))
6648 char *p = new_token.str;
6649 char *q = intel_parser.op_string;
6650 new_token.code = T_CONST;
6652 /* Allow any kind of identifier char to encompass floating point and
6653 hexadecimal numbers. */
6654 while (is_identifier_char (*q))
6658 /* Recognize special symbol names [0-9][bf]. */
6659 if (strlen (intel_parser.op_string) == 2
6660 && (intel_parser.op_string[1] == 'b'
6661 || intel_parser.op_string[1] == 'f'))
6662 new_token.code = T_ID;
6665 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6666 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6668 new_token.code = T_REG;
6669 new_token.reg = reg;
6671 if (*intel_parser.op_string == REGISTER_PREFIX)
6673 new_token.str[0] = REGISTER_PREFIX;
6674 new_token.str[1] = '\0';
6677 strcat (new_token.str, reg->reg_name);
6680 else if (is_identifier_char (*intel_parser.op_string))
6682 char *p = new_token.str;
6683 char *q = intel_parser.op_string;
6685 /* A '.' or '$' followed by an identifier char is an identifier.
6686 Otherwise, it's operator '.' followed by an expression. */
6687 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6689 new_token.code = '.';
6690 new_token.str[0] = '.';
6691 new_token.str[1] = '\0';
6695 while (is_identifier_char (*q) || *q == '@')
6699 if (strcasecmp (new_token.str, "NOT") == 0)
6700 new_token.code = '~';
6702 else if (strcasecmp (new_token.str, "MOD") == 0)
6703 new_token.code = '%';
6705 else if (strcasecmp (new_token.str, "AND") == 0)
6706 new_token.code = '&';
6708 else if (strcasecmp (new_token.str, "OR") == 0)
6709 new_token.code = '|';
6711 else if (strcasecmp (new_token.str, "XOR") == 0)
6712 new_token.code = '^';
6714 else if (strcasecmp (new_token.str, "SHL") == 0)
6715 new_token.code = T_SHL;
6717 else if (strcasecmp (new_token.str, "SHR") == 0)
6718 new_token.code = T_SHR;
6720 else if (strcasecmp (new_token.str, "BYTE") == 0)
6721 new_token.code = T_BYTE;
6723 else if (strcasecmp (new_token.str, "WORD") == 0)
6724 new_token.code = T_WORD;
6726 else if (strcasecmp (new_token.str, "DWORD") == 0)
6727 new_token.code = T_DWORD;
6729 else if (strcasecmp (new_token.str, "FWORD") == 0)
6730 new_token.code = T_FWORD;
6732 else if (strcasecmp (new_token.str, "QWORD") == 0)
6733 new_token.code = T_QWORD;
6735 else if (strcasecmp (new_token.str, "TBYTE") == 0
6736 /* XXX remove (gcc still uses it) */
6737 || strcasecmp (new_token.str, "XWORD") == 0)
6738 new_token.code = T_TBYTE;
6740 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6741 || strcasecmp (new_token.str, "OWORD") == 0)
6742 new_token.code = T_XMMWORD;
6744 else if (strcasecmp (new_token.str, "PTR") == 0)
6745 new_token.code = T_PTR;
6747 else if (strcasecmp (new_token.str, "SHORT") == 0)
6748 new_token.code = T_SHORT;
6750 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6752 new_token.code = T_OFFSET;
6754 /* ??? This is not mentioned in the MASM grammar but gcc
6755 makes use of it with -mintel-syntax. OFFSET may be
6756 followed by FLAT: */
6757 if (strncasecmp (q, " FLAT:", 6) == 0)
6758 strcat (new_token.str, " FLAT:");
6761 /* ??? This is not mentioned in the MASM grammar. */
6762 else if (strcasecmp (new_token.str, "FLAT") == 0)
6764 new_token.code = T_OFFSET;
6766 strcat (new_token.str, ":");
6768 as_bad (_("`:' expected"));
6772 new_token.code = T_ID;
6776 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6778 new_token.code = *intel_parser.op_string;
6779 new_token.str[0] = *intel_parser.op_string;
6780 new_token.str[1] = '\0';
6783 else if (strchr ("<>", *intel_parser.op_string)
6784 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6786 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6787 new_token.str[0] = *intel_parser.op_string;
6788 new_token.str[1] = *intel_parser.op_string;
6789 new_token.str[2] = '\0';
6793 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
6795 intel_parser.op_string += strlen (new_token.str);
6796 cur_token = new_token;
6799 /* Put cur_token back into the token stream and make cur_token point to
6802 intel_putback_token ()
6804 if (cur_token.code != T_NIL)
6806 intel_parser.op_string -= strlen (cur_token.str);
6807 free (cur_token.str);
6809 cur_token = prev_token;
6811 /* Forget prev_token. */
6812 prev_token.code = T_NIL;
6813 prev_token.reg = NULL;
6814 prev_token.str = NULL;
6818 tc_x86_regname_to_dw2regnum (const char *regname)
6820 unsigned int regnum;
6821 unsigned int regnames_count;
6822 static const char *const regnames_32[] =
6824 "eax", "ecx", "edx", "ebx",
6825 "esp", "ebp", "esi", "edi",
6826 "eip", "eflags", NULL,
6827 "st0", "st1", "st2", "st3",
6828 "st4", "st5", "st6", "st7",
6830 "xmm0", "xmm1", "xmm2", "xmm3",
6831 "xmm4", "xmm5", "xmm6", "xmm7",
6832 "mm0", "mm1", "mm2", "mm3",
6833 "mm4", "mm5", "mm6", "mm7"
6835 static const char *const regnames_64[] =
6837 "rax", "rdx", "rcx", "rbx",
6838 "rsi", "rdi", "rbp", "rsp",
6839 "r8", "r9", "r10", "r11",
6840 "r12", "r13", "r14", "r15",
6842 "xmm0", "xmm1", "xmm2", "xmm3",
6843 "xmm4", "xmm5", "xmm6", "xmm7",
6844 "xmm8", "xmm9", "xmm10", "xmm11",
6845 "xmm12", "xmm13", "xmm14", "xmm15",
6846 "st0", "st1", "st2", "st3",
6847 "st4", "st5", "st6", "st7",
6848 "mm0", "mm1", "mm2", "mm3",
6849 "mm4", "mm5", "mm6", "mm7"
6851 const char *const *regnames;
6853 if (flag_code == CODE_64BIT)
6855 regnames = regnames_64;
6856 regnames_count = ARRAY_SIZE (regnames_64);
6860 regnames = regnames_32;
6861 regnames_count = ARRAY_SIZE (regnames_32);
6864 for (regnum = 0; regnum < regnames_count; regnum++)
6865 if (regnames[regnum] != NULL
6866 && strcmp (regname, regnames[regnum]) == 0)
6873 tc_x86_frame_initial_instructions (void)
6875 static unsigned int sp_regno;
6878 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6881 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6882 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
6886 i386_elf_section_type (const char *str, size_t len)
6888 if (flag_code == CODE_64BIT
6889 && len == sizeof ("unwind") - 1
6890 && strncmp (str, "unwind", 6) == 0)
6891 return SHT_X86_64_UNWIND;
6898 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6902 expr.X_op = O_secrel;
6903 expr.X_add_symbol = symbol;
6904 expr.X_add_number = 0;
6905 emit_expr (&expr, size);