1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
461 const char line_separator_chars[] = ";";
463 /* Chars that can be used to separate mant from exp in floating point
465 const char EXP_CHARS[] = "eE";
467 /* Chars that mean this number is a floating point constant
470 const char FLT_CHARS[] = "fFdDxX";
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
501 /* The instruction we're assembling. */
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
511 /* Current operand we are working on. */
512 static int this_operand = -1;
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531 /* The ELF ABI to use. */
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
552 /* 1 for intel syntax,
554 static int intel_syntax = 0;
556 /* 1 for Intel64 ISA,
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
573 static int add_bnd_prefix = 0;
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
586 /* 1 if the assembler should generate relax relocations. */
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591 static enum check_kind
597 sse_check, operand_check = check_warning;
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
604 static int optimize = 0;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
613 static int optimize_for_space = 0;
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
658 /* Encode scalar AVX instructions with specific vector length. */
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 /* Encode EVEX WIG instructions with specific evex.w. */
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
698 #define UNCOND_JUMP 0
700 #define COND_JUMP86 2
705 #define SMALL16 (SMALL | CODE16)
707 #define BIG16 (BIG | CODE16)
711 #define INLINE __inline__
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
732 const relax_typeS md_relax_table[] =
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
771 static const arch_entry cpu_arch[] =
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1031 static const noarch_entry cpu_noarch[] =
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1067 /* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1071 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1078 && *input_line_pointer == ',')
1080 align = parse_align (needs_align - 1);
1082 if (align == (addressT) -1)
1097 bss_alloc (symbolP, size, align);
1102 pe_lcomm (int needs_align)
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1108 const pseudo_typeS md_pseudo_table[] =
1110 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1113 {"align", s_align_ptwo, 0},
1115 {"arch", set_cpu_arch, 0},
1119 {"lcomm", pe_lcomm, 1},
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1125 {"slong", signed_cons, 4},
1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
1132 {"code64", set_code_flag, CODE_64BIT},
1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
1145 {"file", dwarf2_directive_file, 0},
1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1150 {"secrel32", pe_directive_secrel, 0},
1155 /* For interface with expression (). */
1156 extern char *input_line_pointer;
1158 /* Hash table for instruction mnemonic lookup. */
1159 static struct hash_control *op_hash;
1161 /* Hash table for register lookup. */
1162 static struct hash_control *reg_hash;
1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
1167 static const unsigned char f32_1[] =
1169 static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171 static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173 static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1175 static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177 static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1179 static const unsigned char f16_3[] =
1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1181 static const unsigned char f16_4[] =
1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183 static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185 static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187 static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
1189 /* 32-bit NOPs patterns. */
1190 static const unsigned char *const f32_patt[] = {
1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1193 /* 16-bit NOPs patterns. */
1194 static const unsigned char *const f16_patt[] = {
1195 f32_1, f32_2, f16_3, f16_4
1197 /* nopl (%[re]ax) */
1198 static const unsigned char alt_3[] =
1200 /* nopl 0(%[re]ax) */
1201 static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203 /* nopl 0(%[re]ax,%[re]ax,1) */
1204 static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206 /* nopw 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopl 0L(%[re]ax) */
1210 static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212 /* nopl 0L(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215 /* nopw 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* data16 nopw %cs:0L(%eax,%eax,1) */
1222 static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* 32-bit and 64-bit NOPs patterns. */
1225 static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1227 alt_9, alt_10, alt_11
1230 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1234 i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1238 /* Place the longer NOP first. */
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1243 /* Use the smaller one if the requsted one isn't available. */
1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
1250 last = count % max_single_nop_size;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1258 nops = patt[last - 1];
1261 /* Use the smaller one plus one-byte NOP if the needed one
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1269 memcpy (where + offset, nops, last);
1274 fits_in_imm7 (offsetT num)
1276 return (num & 0x7f) == num;
1280 fits_in_imm31 (offsetT num)
1282 return (num & 0x7fffffff) == num;
1285 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1289 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1291 const unsigned char *const *patt = NULL;
1292 int max_single_nop_size;
1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
1296 switch (fragP->fr_type)
1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
1310 2. For the rest, alt_patt will be used.
1312 When -mtune= isn't used, alt_patt will be used if
1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1319 if (flag_code == CODE_16BIT)
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
1344 case PROCESSOR_CORE2:
1345 case PROCESSOR_COREI7:
1346 case PROCESSOR_L1OM:
1347 case PROCESSOR_K1OM:
1348 case PROCESSOR_GENERIC64:
1350 case PROCESSOR_ATHLON:
1352 case PROCESSOR_AMDFAM10:
1354 case PROCESSOR_ZNVER:
1358 case PROCESSOR_I386:
1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
1361 case PROCESSOR_PENTIUMPRO:
1362 case PROCESSOR_IAMCU:
1363 case PROCESSOR_GENERIC32:
1370 switch (fragP->tc_frag_data.tune)
1372 case PROCESSOR_UNKNOWN:
1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1374 PROCESSOR_UNKNOWN. */
1378 case PROCESSOR_I386:
1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
1381 case PROCESSOR_IAMCU:
1383 case PROCESSOR_ATHLON:
1385 case PROCESSOR_AMDFAM10:
1387 case PROCESSOR_ZNVER:
1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
1401 case PROCESSOR_CORE2:
1402 case PROCESSOR_COREI7:
1403 case PROCESSOR_L1OM:
1404 case PROCESSOR_K1OM:
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 case PROCESSOR_GENERIC64:
1416 if (patt == f32_patt)
1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1431 limit = max_single_nop_size;
1433 if (fragP->fr_type == rs_fill_nop)
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1446 fragP->fr_var = count;
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1454 /* Use "jmp disp8" if possible. */
1456 where[0] = jump_disp8[0];
1462 unsigned int size_of_jump;
1464 if (flag_code == CODE_16BIT)
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1472 where[0] = jump32_disp32[0];
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
1494 operand_type_all_zero (const union i386_operand_type *x)
1496 switch (ARRAY_SIZE(x->array))
1507 return !x->array[0];
1514 operand_type_set (union i386_operand_type *x, unsigned int v)
1516 switch (ARRAY_SIZE(x->array))
1534 operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
1537 switch (ARRAY_SIZE(x->array))
1540 if (x->array[2] != y->array[2])
1544 if (x->array[1] != y->array[1])
1548 return x->array[0] == y->array[0];
1556 cpu_flags_all_zero (const union i386_cpu_flags *x)
1558 switch (ARRAY_SIZE(x->array))
1573 return !x->array[0];
1580 cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1583 switch (ARRAY_SIZE(x->array))
1586 if (x->array[3] != y->array[3])
1590 if (x->array[2] != y->array[2])
1594 if (x->array[1] != y->array[1])
1598 return x->array[0] == y->array[0];
1606 cpu_flags_check_cpu64 (i386_cpu_flags f)
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1612 static INLINE i386_cpu_flags
1613 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1615 switch (ARRAY_SIZE (x.array))
1618 x.array [3] &= y.array [3];
1621 x.array [2] &= y.array [2];
1624 x.array [1] &= y.array [1];
1627 x.array [0] &= y.array [0];
1635 static INLINE i386_cpu_flags
1636 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1638 switch (ARRAY_SIZE (x.array))
1641 x.array [3] |= y.array [3];
1644 x.array [2] |= y.array [2];
1647 x.array [1] |= y.array [1];
1650 x.array [0] |= y.array [0];
1658 static INLINE i386_cpu_flags
1659 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1661 switch (ARRAY_SIZE (x.array))
1664 x.array [3] &= ~y.array [3];
1667 x.array [2] &= ~y.array [2];
1670 x.array [1] &= ~y.array [1];
1673 x.array [0] &= ~y.array [0];
1681 #define CPU_FLAGS_ARCH_MATCH 0x1
1682 #define CPU_FLAGS_64BIT_MATCH 0x2
1684 #define CPU_FLAGS_PERFECT_MATCH \
1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1687 /* Return CPU flags match bits. */
1690 cpu_flags_match (const insn_template *t)
1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1698 if (cpu_flags_all_zero (&x))
1700 /* This instruction is available on all archs. */
1701 match |= CPU_FLAGS_ARCH_MATCH;
1705 /* This instruction is available only on some archs. */
1706 i386_cpu_flags cpu = cpu_arch_flags;
1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1711 x.bitfield.cpuavx512vl = 0;
1713 cpu = cpu_flags_and (x, cpu);
1714 if (!cpu_flags_all_zero (&cpu))
1716 if (x.bitfield.cpuavx)
1718 /* We need to check a few extra flags with AVX. */
1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
1726 else if (x.bitfield.cpuavx512f)
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1736 match |= CPU_FLAGS_ARCH_MATCH;
1742 static INLINE i386_operand_type
1743 operand_type_and (i386_operand_type x, i386_operand_type y)
1745 switch (ARRAY_SIZE (x.array))
1748 x.array [2] &= y.array [2];
1751 x.array [1] &= y.array [1];
1754 x.array [0] &= y.array [0];
1762 static INLINE i386_operand_type
1763 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1765 switch (ARRAY_SIZE (x.array))
1768 x.array [2] &= ~y.array [2];
1771 x.array [1] &= ~y.array [1];
1774 x.array [0] &= ~y.array [0];
1782 static INLINE i386_operand_type
1783 operand_type_or (i386_operand_type x, i386_operand_type y)
1785 switch (ARRAY_SIZE (x.array))
1788 x.array [2] |= y.array [2];
1791 x.array [1] |= y.array [1];
1794 x.array [0] |= y.array [0];
1802 static INLINE i386_operand_type
1803 operand_type_xor (i386_operand_type x, i386_operand_type y)
1805 switch (ARRAY_SIZE (x.array))
1808 x.array [2] ^= y.array [2];
1811 x.array [1] ^= y.array [1];
1814 x.array [0] ^= y.array [0];
1822 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1825 static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
1827 static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833 static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
1835 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1836 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1837 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1846 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1857 operand_type_check (i386_operand_type t, enum operand_type c)
1862 return t.bitfield.reg;
1865 return (t.bitfield.imm8
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1894 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1895 operand J for instruction template T. */
1898 match_reg_size (const insn_template *t, unsigned int j)
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
1912 /* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1916 match_simd_size (const insn_template *t, unsigned int j)
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1926 /* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1930 match_mem_size (const insn_template *t, unsigned int j)
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
1940 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1941 down-conversion vpmov*. */
1942 || ((t->operand_types[j].bitfield.regsimd
1943 && !t->opcode_modifier.broadcast
1944 && (t->operand_types[j].bitfield.byte
1945 || t->operand_types[j].bitfield.word
1946 || t->operand_types[j].bitfield.dword
1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
1954 /* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1958 operand_size_match (const insn_template *t)
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
1977 if (t->operand_types[j].bitfield.reg
1978 && !match_reg_size (t, j))
1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2007 else if (!t->opcode_modifier.d)
2010 i.error = operand_size_mismatch;
2014 /* Check reverse. */
2015 gas_assert (i.operands == 2);
2018 for (j = 0; j < 2; j++)
2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
2022 && !match_reg_size (t, j ? 0 : 1))
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
2034 operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2037 i386_operand_type temp = overlap;
2039 temp.bitfield.jumpabsolute = 0;
2040 temp.bitfield.unspecified = 0;
2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
2048 temp.bitfield.ymmword = 0;
2049 temp.bitfield.zmmword = 0;
2050 if (operand_type_all_zero (&temp))
2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2058 i.error = operand_type_mismatch;
2062 /* If given types g0 and g1 are registers they must be of the same type
2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2068 operand_type_register_match (i386_operand_type g0,
2069 i386_operand_type t0,
2070 i386_operand_type g1,
2071 i386_operand_type t1)
2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2105 i.error = register_type_mismatch;
2110 static INLINE unsigned int
2111 register_number (const reg_entry *r)
2113 unsigned int nr = r->reg_num;
2115 if (r->reg_flags & RegRex)
2118 if (r->reg_flags & RegVRex)
2124 static INLINE unsigned int
2125 mode_from_disp_size (i386_operand_type t)
2127 if (t.bitfield.disp8)
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2138 fits_in_signed_byte (addressT num)
2140 return num + 0x80 <= 0xff;
2144 fits_in_unsigned_byte (addressT num)
2150 fits_in_unsigned_word (addressT num)
2152 return num <= 0xffff;
2156 fits_in_signed_word (addressT num)
2158 return num + 0x8000 <= 0xffff;
2162 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2167 return num + 0x80000000 <= 0xffffffff;
2169 } /* fits_in_signed_long() */
2172 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2177 return num <= 0xffffffff;
2179 } /* fits_in_unsigned_long() */
2182 fits_in_disp8 (offsetT num)
2184 int shift = i.memshift;
2190 mask = (1 << shift) - 1;
2192 /* Return 0 if NUM isn't properly aligned. */
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2201 fits_in_imm4 (offsetT num)
2203 return (num & 0xf) == num;
2206 static i386_operand_type
2207 smallest_imm_type (offsetT num)
2209 i386_operand_type t;
2211 operand_type_set (&t, 0);
2212 t.bitfield.imm64 = 1;
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2228 else if (fits_in_signed_byte (num))
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2236 else if (fits_in_unsigned_byte (num))
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2249 else if (fits_in_signed_long (num))
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2261 offset_in_range (offsetT val, int size)
2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2286 char buf1[40], buf2[40];
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
2313 static enum PREFIX_GROUP
2314 add_prefix (unsigned int prefix)
2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
2335 case DS_PREFIX_OPCODE:
2338 case CS_PREFIX_OPCODE:
2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
2352 case LOCK_PREFIX_OPCODE:
2361 case ADDR_PREFIX_OPCODE:
2365 case DATA_PREFIX_OPCODE:
2369 if (i.prefix[q] != 0)
2377 i.prefix[q] |= prefix;
2380 as_bad (_("same type of prefix used twice"));
2386 update_code_flag (int value, int check)
2388 PRINTF_LIKE ((*as_error));
2390 flag_code = (enum flag_code) value;
2391 if (flag_code == CODE_64BIT)
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2404 as_error = as_fatal;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2413 as_error = as_fatal;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 stackop_size = '\0';
2423 set_code_flag (int value)
2425 update_code_flag (value, 0);
2429 set_16bit_gcc_code_flag (int new_code_flag)
2431 flag_code = (enum flag_code) new_code_flag;
2432 if (flag_code != CODE_16BIT)
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
2436 stackop_size = LONG_MNEM_SUFFIX;
2440 set_intel_syntax (int syntax_flag)
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2449 int e = get_symbol_name (&string);
2451 if (strcmp (string, "prefix") == 0)
2453 else if (strcmp (string, "noprefix") == 0)
2456 as_bad (_("bad argument to syntax directive."));
2457 (void) restore_line_pointer (e);
2459 demand_empty_rest_of_line ();
2461 intel_syntax = syntax_flag;
2463 if (ask_naked_reg == 0)
2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2467 allow_naked_reg = (ask_naked_reg < 0);
2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
2473 register_prefix = allow_naked_reg ? "" : "%";
2477 set_intel_mnemonic (int mnemonic_flag)
2479 intel_mnemonic = mnemonic_flag;
2483 set_allow_index_reg (int flag)
2485 allow_index_reg = flag;
2489 set_check (int what)
2491 enum check_kind *kind;
2496 kind = &operand_check;
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2510 int e = get_symbol_name (&string);
2512 if (strcmp (string, "none") == 0)
2514 else if (strcmp (string, "warning") == 0)
2515 *kind = check_warning;
2516 else if (strcmp (string, "error") == 0)
2517 *kind = check_error;
2519 as_bad (_("bad argument to %s_check directive."), str);
2520 (void) restore_line_pointer (e);
2523 as_bad (_("missing argument for %s_check directive"), str);
2525 demand_empty_rest_of_line ();
2529 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2535 /* Intel LIOM is only supported on ELF. */
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2545 arch = default_arch;
2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2553 /* If we are targeting Intel L1OM, we must enable it. */
2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2555 || new_flag.bitfield.cpul1om)
2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2568 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2575 int e = get_symbol_name (&string);
2577 i386_cpu_flags flags;
2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2581 if (strcmp (string, cpu_arch[j].name) == 0)
2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2587 cpu_arch_name = cpu_arch[j].name;
2588 cpu_sub_arch_name = NULL;
2589 cpu_arch_flags = cpu_arch[j].flags;
2590 if (flag_code == CODE_64BIT)
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
2602 if (!cpu_arch_tune_set)
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2610 flags = cpu_flags_or (cpu_arch_flags,
2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2615 if (cpu_sub_arch_name)
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
2620 (const char *) NULL);
2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2625 cpu_arch_flags = flags;
2626 cpu_arch_isa_flags = flags;
2630 = cpu_flags_or (cpu_arch_isa_flags,
2632 (void) restore_line_pointer (e);
2633 demand_empty_rest_of_line ();
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2640 /* Disable an ISA extension. */
2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2648 if (cpu_sub_arch_name)
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2665 j = ARRAY_SIZE (cpu_arch);
2668 if (j >= ARRAY_SIZE (cpu_arch))
2669 as_bad (_("no such architecture: `%s'"), string);
2671 *input_line_pointer = e;
2674 as_bad (_("missing cpu architecture"));
2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2693 (void) restore_line_pointer (e);
2696 demand_empty_rest_of_line ();
2699 enum bfd_architecture
2702 if (cpu_arch_isa == PROCESSOR_L1OM)
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2724 return bfd_arch_i386;
2730 if (!strncmp (default_arch, "x86_64", 6))
2732 if (cpu_arch_isa == PROCESSOR_L1OM)
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2746 else if (default_arch[6] == '\0')
2747 return bfd_mach_x86_64;
2749 return bfd_mach_x64_32;
2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2761 return bfd_mach_i386_i386;
2764 as_fatal (_("unknown architecture"));
2770 const char *hash_err;
2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2775 /* Initialize op_hash hash table. */
2776 op_hash = hash_new ();
2779 const insn_template *optab;
2780 templates *core_optab;
2782 /* Setup for loop. */
2784 core_optab = XNEW (templates);
2785 core_optab->start = optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2793 /* different name --> ship out current template list;
2794 add to hash table; & begin anew. */
2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2798 (void *) core_optab);
2801 as_fatal (_("can't hash %s: %s"),
2805 if (optab->name == NULL)
2807 core_optab = XNEW (templates);
2808 core_optab->start = optab;
2813 /* Initialize reg_hash hash table. */
2814 reg_hash = hash_new ();
2816 const reg_entry *regtab;
2817 unsigned int regtab_size = i386_regtab_size;
2819 for (regtab = i386_regtab; regtab_size--; regtab++)
2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2823 as_fatal (_("can't hash %s: %s"),
2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2834 for (c = 0; c < 256; c++)
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2843 else if (ISLOWER (c))
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2849 else if (ISUPPER (c))
2851 mnemonic_chars[c] = TOLOWER (c);
2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2855 else if (c == '{' || c == '}')
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2861 if (ISALPHA (c) || ISDIGIT (c))
2862 identifier_chars[c] = c;
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2871 identifier_chars['@'] = '@';
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
2877 digit_chars['-'] = '-';
2878 mnemonic_chars['_'] = '_';
2879 mnemonic_chars['-'] = '-';
2880 mnemonic_chars['.'] = '.';
2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2888 if (flag_code == CODE_64BIT)
2890 #if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2894 x86_dwarf2_return_column = 16;
2896 x86_cie_data_alignment = -8;
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2906 i386_print_statistics (FILE *file)
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2914 /* Debugging routines for md_assemble. */
2915 static void pte (insn_template *);
2916 static void pt (i386_operand_type);
2917 static void pe (expressionS *);
2918 static void ps (symbolS *);
2921 pi (char *line, i386_insn *x)
2925 fprintf (stdout, "%s: template ", line);
2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2932 x->rm.mode, x->rm.reg, x->rm.regmem);
2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
2940 for (j = 0; j < x->operands; j++)
2942 fprintf (stdout, " #%d: ", j + 1);
2944 fprintf (stdout, "\n");
2945 if (x->types[j].bitfield.reg
2946 || x->types[j].bitfield.regmmx
2947 || x->types[j].bitfield.regsimd
2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
2962 pte (insn_template *t)
2965 fprintf (stdout, " %d operands ", t->operands);
2966 fprintf (stdout, "opcode %x ", t->base_opcode);
2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
2969 if (t->opcode_modifier.d)
2970 fprintf (stdout, "D");
2971 if (t->opcode_modifier.w)
2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
2974 for (j = 0; j < t->operands; j++)
2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
2978 fprintf (stdout, "\n");
2985 fprintf (stdout, " operation %d\n", e->X_op);
2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
2988 if (e->X_add_symbol)
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
3005 fprintf (stdout, "%s type %s%s",
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3011 static struct type_name
3013 i386_operand_type mask;
3016 const type_names[] =
3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
3048 { OPERAND_TYPE_REGYMM, "rYMM" },
3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
3051 { OPERAND_TYPE_ESSEG, "es" },
3055 pt (i386_operand_type t)
3058 i386_operand_type a;
3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3062 a = operand_type_and (t, type_names[j].mask);
3063 if (!operand_type_all_zero (&a))
3064 fprintf (stdout, "%s, ", type_names[j].name);
3069 #endif /* DEBUG386 */
3071 static bfd_reloc_code_real_type
3072 reloc (unsigned int size,
3075 bfd_reloc_code_real_type other)
3077 if (other != NO_RELOC)
3079 reloc_howto_type *rel;
3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3110 if (other == BFD_RELOC_SIZE32)
3113 other = BFD_RELOC_SIZE64;
3116 as_bad (_("there are no pc-relative size relocations"));
3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3128 as_bad (_("unknown relocation (%u)"), other);
3129 else if (size != bfd_get_reloc_size (rel))
3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3131 bfd_get_reloc_size (rel),
3133 else if (pcrel && !rel->pc_relative)
3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3137 || (rel->complain_on_overflow == complain_overflow_unsigned
3139 as_bad (_("relocated field and relocation type differ in signedness"));
3148 as_bad (_("there are no unsigned pc-relative relocations"));
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
3153 case 4: return BFD_RELOC_32_PCREL;
3154 case 8: return BFD_RELOC_64_PCREL;
3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3163 case 4: return BFD_RELOC_X86_64_32S;
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
3180 /* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3186 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3246 intel_float_operand (const char *mnemonic)
3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3255 switch (mnemonic[1])
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3261 return 2 /* integer op */;
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3279 switch (mnemonic[3])
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3298 /* Build the VEX prefix. */
3301 build_vex_prefix (const insn_template *t)
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3315 register_specifier = 0xf;
3317 /* Use 2-byte VEX prefix by swapping destination and source
3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
3321 && i.operands == i.reg_operands
3322 && i.tm.opcode_modifier.vexopcode == VEX0F
3323 && i.tm.opcode_modifier.load
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3337 gas_assert (i.rm.mode == 3);
3341 i.rm.regmem = i.rm.reg;
3344 /* Use the next insn. */
3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
3350 else if (i.tm.opcode_modifier.vex == VEX256)
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3372 case DATA_PREFIX_OPCODE:
3375 case REPE_PREFIX_OPCODE:
3378 case REPNE_PREFIX_OPCODE:
3385 /* Use 2-byte VEX prefix if possible. */
3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
3388 && i.tm.opcode_modifier.vexw != VEXW1
3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3391 /* 2-byte VEX prefix. */
3395 i.vex.bytes[0] = 0xc5;
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3406 /* 3-byte VEX prefix. */
3411 switch (i.tm.opcode_modifier.vexopcode)
3415 i.vex.bytes[0] = 0xc4;
3419 i.vex.bytes[0] = 0xc4;
3423 i.vex.bytes[0] = 0xc4;
3427 i.vex.bytes[0] = 0x8f;
3431 i.vex.bytes[0] = 0x8f;
3435 i.vex.bytes[0] = 0x8f;
3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3457 static INLINE bfd_boolean
3458 is_evex_encoding (const insn_template *t)
3460 return t->opcode_modifier.evex
3461 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3462 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3465 /* Build the EVEX prefix. */
3468 build_evex_prefix (void)
3470 unsigned int register_specifier;
3471 unsigned int implied_prefix;
3473 rex_byte vrex_used = 0;
3475 /* Check register specifier. */
3476 if (i.vex.register_specifier)
3478 gas_assert ((i.vrex & REX_X) == 0);
3480 register_specifier = i.vex.register_specifier->reg_num;
3481 if ((i.vex.register_specifier->reg_flags & RegRex))
3482 register_specifier += 8;
3483 /* The upper 16 registers are encoded in the fourth byte of the
3485 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3486 i.vex.bytes[3] = 0x8;
3487 register_specifier = ~register_specifier & 0xf;
3491 register_specifier = 0xf;
3493 /* Encode upper 16 vector index register in the fourth byte of
3495 if (!(i.vrex & REX_X))
3496 i.vex.bytes[3] = 0x8;
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3506 case DATA_PREFIX_OPCODE:
3509 case REPE_PREFIX_OPCODE:
3512 case REPNE_PREFIX_OPCODE:
3519 /* 4 byte EVEX prefix. */
3521 i.vex.bytes[0] = 0x62;
3524 switch (i.tm.opcode_modifier.vexopcode)
3540 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3542 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3544 /* The fifth bit of the second EVEX byte is 1's compliment of the
3545 REX_R bit in VREX. */
3546 if (!(i.vrex & REX_R))
3547 i.vex.bytes[1] |= 0x10;
3551 if ((i.reg_operands + i.imm_operands) == i.operands)
3553 /* When all operands are registers, the REX_X bit in REX is not
3554 used. We reuse it to encode the upper 16 registers, which is
3555 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3556 as 1's compliment. */
3557 if ((i.vrex & REX_B))
3560 i.vex.bytes[1] &= ~0x40;
3564 /* EVEX instructions shouldn't need the REX prefix. */
3565 i.vrex &= ~vrex_used;
3566 gas_assert (i.vrex == 0);
3568 /* Check the REX.W bit. */
3569 w = (i.rex & REX_W) ? 1 : 0;
3570 if (i.tm.opcode_modifier.vexw)
3572 if (i.tm.opcode_modifier.vexw == VEXW1)
3575 /* If w is not set it means we are dealing with WIG instruction. */
3578 if (evexwig == evexw1)
3582 /* Encode the U bit. */
3583 implied_prefix |= 0x4;
3585 /* The third byte of the EVEX prefix. */
3586 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3588 /* The fourth byte of the EVEX prefix. */
3589 /* The zeroing-masking bit. */
3590 if (i.mask && i.mask->zeroing)
3591 i.vex.bytes[3] |= 0x80;
3593 /* Don't always set the broadcast bit if there is no RC. */
3596 /* Encode the vector length. */
3597 unsigned int vec_length;
3599 if (!i.tm.opcode_modifier.evex
3600 || i.tm.opcode_modifier.evex == EVEXDYN)
3605 for (op = 0; op < i.tm.operands; ++op)
3606 if (i.tm.operand_types[op].bitfield.xmmword
3607 + i.tm.operand_types[op].bitfield.ymmword
3608 + i.tm.operand_types[op].bitfield.zmmword > 1)
3610 if (i.types[op].bitfield.zmmword)
3611 i.tm.opcode_modifier.evex = EVEX512;
3612 else if (i.types[op].bitfield.ymmword)
3613 i.tm.opcode_modifier.evex = EVEX256;
3614 else if (i.types[op].bitfield.xmmword)
3615 i.tm.opcode_modifier.evex = EVEX128;
3622 switch (i.tm.opcode_modifier.evex)
3624 case EVEXLIG: /* LL' is ignored */
3625 vec_length = evexlig << 5;
3628 vec_length = 0 << 5;
3631 vec_length = 1 << 5;
3634 vec_length = 2 << 5;
3640 i.vex.bytes[3] |= vec_length;
3641 /* Encode the broadcast bit. */
3643 i.vex.bytes[3] |= 0x10;
3647 if (i.rounding->type != saeonly)
3648 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3650 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3653 if (i.mask && i.mask->mask)
3654 i.vex.bytes[3] |= i.mask->mask->reg_num;
3658 process_immext (void)
3662 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3665 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3666 with an opcode suffix which is coded in the same place as an
3667 8-bit immediate field would be.
3668 Here we check those operands and remove them afterwards. */
3671 for (x = 0; x < i.operands; x++)
3672 if (register_number (i.op[x].regs) != x)
3673 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3674 register_prefix, i.op[x].regs->reg_name, x + 1,
3680 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3682 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3683 suffix which is coded in the same place as an 8-bit immediate
3685 Here we check those operands and remove them afterwards. */
3688 if (i.operands != 3)
3691 for (x = 0; x < 2; x++)
3692 if (register_number (i.op[x].regs) != x)
3693 goto bad_register_operand;
3695 /* Check for third operand for mwaitx/monitorx insn. */
3696 if (register_number (i.op[x].regs)
3697 != (x + (i.tm.extension_opcode == 0xfb)))
3699 bad_register_operand:
3700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3701 register_prefix, i.op[x].regs->reg_name, x+1,
3708 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3709 which is coded in the same place as an 8-bit immediate field
3710 would be. Here we fake an 8-bit immediate operand from the
3711 opcode suffix stored in tm.extension_opcode.
3713 AVX instructions also use this encoding, for some of
3714 3 argument instructions. */
3716 gas_assert (i.imm_operands <= 1
3718 || ((i.tm.opcode_modifier.vex
3719 || i.tm.opcode_modifier.vexopcode
3720 || is_evex_encoding (&i.tm))
3721 && i.operands <= 4)));
3723 exp = &im_expressions[i.imm_operands++];
3724 i.op[i.operands].imms = exp;
3725 i.types[i.operands] = imm8;
3727 exp->X_op = O_constant;
3728 exp->X_add_number = i.tm.extension_opcode;
3729 i.tm.extension_opcode = None;
3736 switch (i.tm.opcode_modifier.hleprefixok)
3741 as_bad (_("invalid instruction `%s' after `%s'"),
3742 i.tm.name, i.hle_prefix);
3745 if (i.prefix[LOCK_PREFIX])
3747 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3751 case HLEPrefixRelease:
3752 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3754 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3758 if (i.mem_operands == 0
3759 || !operand_type_check (i.types[i.operands - 1], anymem))
3761 as_bad (_("memory destination needed for instruction `%s'"
3762 " after `xrelease'"), i.tm.name);
3769 /* Try the shortest encoding by shortening operand size. */
3772 optimize_encoding (void)
3776 if (optimize_for_space
3777 && i.reg_operands == 1
3778 && i.imm_operands == 1
3779 && !i.types[1].bitfield.byte
3780 && i.op[0].imms->X_op == O_constant
3781 && fits_in_imm7 (i.op[0].imms->X_add_number)
3782 && ((i.tm.base_opcode == 0xa8
3783 && i.tm.extension_opcode == None)
3784 || (i.tm.base_opcode == 0xf6
3785 && i.tm.extension_opcode == 0x0)))
3788 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3790 unsigned int base_regnum = i.op[1].regs->reg_num;
3791 if (flag_code == CODE_64BIT || base_regnum < 4)
3793 i.types[1].bitfield.byte = 1;
3794 /* Ignore the suffix. */
3796 if (base_regnum >= 4
3797 && !(i.op[1].regs->reg_flags & RegRex))
3799 /* Handle SP, BP, SI and DI registers. */
3800 if (i.types[1].bitfield.word)
3802 else if (i.types[1].bitfield.dword)
3810 else if (flag_code == CODE_64BIT
3811 && ((i.types[1].bitfield.qword
3812 && i.reg_operands == 1
3813 && i.imm_operands == 1
3814 && i.op[0].imms->X_op == O_constant
3815 && ((i.tm.base_opcode == 0xb0
3816 && i.tm.extension_opcode == None
3817 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3818 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3819 && (((i.tm.base_opcode == 0x24
3820 || i.tm.base_opcode == 0xa8)
3821 && i.tm.extension_opcode == None)
3822 || (i.tm.base_opcode == 0x80
3823 && i.tm.extension_opcode == 0x4)
3824 || ((i.tm.base_opcode == 0xf6
3825 || i.tm.base_opcode == 0xc6)
3826 && i.tm.extension_opcode == 0x0)))))
3827 || (i.types[0].bitfield.qword
3828 && ((i.reg_operands == 2
3829 && i.op[0].regs == i.op[1].regs
3830 && ((i.tm.base_opcode == 0x30
3831 || i.tm.base_opcode == 0x28)
3832 && i.tm.extension_opcode == None))
3833 || (i.reg_operands == 1
3835 && i.tm.base_opcode == 0x30
3836 && i.tm.extension_opcode == None)))))
3839 andq $imm31, %r64 -> andl $imm31, %r32
3840 testq $imm31, %r64 -> testl $imm31, %r32
3841 xorq %r64, %r64 -> xorl %r32, %r32
3842 subq %r64, %r64 -> subl %r32, %r32
3843 movq $imm31, %r64 -> movl $imm31, %r32
3844 movq $imm32, %r64 -> movl $imm32, %r32
3846 i.tm.opcode_modifier.norex64 = 1;
3847 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3853 i.tm.operand_types[0].bitfield.imm32 = 1;
3854 i.tm.operand_types[0].bitfield.imm32s = 0;
3855 i.tm.operand_types[0].bitfield.imm64 = 0;
3856 i.types[0].bitfield.imm32 = 1;
3857 i.types[0].bitfield.imm32s = 0;
3858 i.types[0].bitfield.imm64 = 0;
3859 i.types[1].bitfield.dword = 1;
3860 i.types[1].bitfield.qword = 0;
3861 if (i.tm.base_opcode == 0xc6)
3864 movq $imm31, %r64 -> movl $imm31, %r32
3866 i.tm.base_opcode = 0xb0;
3867 i.tm.extension_opcode = None;
3868 i.tm.opcode_modifier.shortform = 1;
3869 i.tm.opcode_modifier.modrm = 0;
3873 else if (optimize > 1
3874 && i.reg_operands == 3
3875 && i.op[0].regs == i.op[1].regs
3876 && !i.types[2].bitfield.xmmword
3877 && (i.tm.opcode_modifier.vex
3880 && is_evex_encoding (&i.tm)
3881 && (i.vec_encoding != vex_encoding_evex
3882 || i.tm.cpu_flags.bitfield.cpuavx512vl
3883 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3884 && ((i.tm.base_opcode == 0x55
3885 || i.tm.base_opcode == 0x6655
3886 || i.tm.base_opcode == 0x66df
3887 || i.tm.base_opcode == 0x57
3888 || i.tm.base_opcode == 0x6657
3889 || i.tm.base_opcode == 0x66ef
3890 || i.tm.base_opcode == 0x66f8
3891 || i.tm.base_opcode == 0x66f9
3892 || i.tm.base_opcode == 0x66fa
3893 || i.tm.base_opcode == 0x66fb)
3894 && i.tm.extension_opcode == None))
3897 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3899 EVEX VOP %zmmM, %zmmM, %zmmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 EVEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandn and vpxor:
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandnd and vpandnq:
3911 EVEX VOP %zmmM, %zmmM, %zmmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 EVEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 VOP, one of vpxord and vpxorq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 if (is_evex_encoding (&i.tm))
3927 if (i.vec_encoding == vex_encoding_evex)
3928 i.tm.opcode_modifier.evex = EVEX128;
3931 i.tm.opcode_modifier.vex = VEX128;
3932 i.tm.opcode_modifier.vexw = VEXW0;
3933 i.tm.opcode_modifier.evex = 0;
3937 i.tm.opcode_modifier.vex = VEX128;
3939 if (i.tm.opcode_modifier.vex)
3940 for (j = 0; j < 3; j++)
3942 i.types[j].bitfield.xmmword = 1;
3943 i.types[j].bitfield.ymmword = 0;
3948 /* This is the guts of the machine-dependent assembler. LINE points to a
3949 machine dependent instruction. This function is supposed to emit
3950 the frags/bytes it assembles to. */
3953 md_assemble (char *line)
3956 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3957 const insn_template *t;
3959 /* Initialize globals. */
3960 memset (&i, '\0', sizeof (i));
3961 for (j = 0; j < MAX_OPERANDS; j++)
3962 i.reloc[j] = NO_RELOC;
3963 memset (disp_expressions, '\0', sizeof (disp_expressions));
3964 memset (im_expressions, '\0', sizeof (im_expressions));
3965 save_stack_p = save_stack;
3967 /* First parse an instruction mnemonic & call i386_operand for the operands.
3968 We assume that the scrubber has arranged it so that line[0] is the valid
3969 start of a (possibly prefixed) mnemonic. */
3971 line = parse_insn (line, mnemonic);
3974 mnem_suffix = i.suffix;
3976 line = parse_operands (line, mnemonic);
3978 xfree (i.memop1_string);
3979 i.memop1_string = NULL;
3983 /* Now we've parsed the mnemonic into a set of templates, and have the
3984 operands at hand. */
3986 /* All intel opcodes have reversed operands except for "bound" and
3987 "enter". We also don't reverse intersegment "jmp" and "call"
3988 instructions with 2 immediate operands so that the immediate segment
3989 precedes the offset, as it does when in AT&T mode. */
3992 && (strcmp (mnemonic, "bound") != 0)
3993 && (strcmp (mnemonic, "invlpga") != 0)
3994 && !(operand_type_check (i.types[0], imm)
3995 && operand_type_check (i.types[1], imm)))
3998 /* The order of the immediates should be reversed
3999 for 2 immediates extrq and insertq instructions */
4000 if (i.imm_operands == 2
4001 && (strcmp (mnemonic, "extrq") == 0
4002 || strcmp (mnemonic, "insertq") == 0))
4003 swap_2_operands (0, 1);
4008 /* Don't optimize displacement for movabs since it only takes 64bit
4011 && i.disp_encoding != disp_encoding_32bit
4012 && (flag_code != CODE_64BIT
4013 || strcmp (mnemonic, "movabs") != 0))
4016 /* Next, we find a template that matches the given insn,
4017 making sure the overlap of the given operands types is consistent
4018 with the template operand types. */
4020 if (!(t = match_template (mnem_suffix)))
4023 if (sse_check != check_none
4024 && !i.tm.opcode_modifier.noavx
4025 && !i.tm.cpu_flags.bitfield.cpuavx
4026 && (i.tm.cpu_flags.bitfield.cpusse
4027 || i.tm.cpu_flags.bitfield.cpusse2
4028 || i.tm.cpu_flags.bitfield.cpusse3
4029 || i.tm.cpu_flags.bitfield.cpussse3
4030 || i.tm.cpu_flags.bitfield.cpusse4_1
4031 || i.tm.cpu_flags.bitfield.cpusse4_2
4032 || i.tm.cpu_flags.bitfield.cpupclmul
4033 || i.tm.cpu_flags.bitfield.cpuaes
4034 || i.tm.cpu_flags.bitfield.cpugfni))
4036 (sse_check == check_warning
4038 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4041 /* Zap movzx and movsx suffix. The suffix has been set from
4042 "word ptr" or "byte ptr" on the source operand in Intel syntax
4043 or extracted from mnemonic in AT&T syntax. But we'll use
4044 the destination register to choose the suffix for encoding. */
4045 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4047 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4048 there is no suffix, the default will be byte extension. */
4049 if (i.reg_operands != 2
4052 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4057 if (i.tm.opcode_modifier.fwait)
4058 if (!add_prefix (FWAIT_OPCODE))
4061 /* Check if REP prefix is OK. */
4062 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4064 as_bad (_("invalid instruction `%s' after `%s'"),
4065 i.tm.name, i.rep_prefix);
4069 /* Check for lock without a lockable instruction. Destination operand
4070 must be memory unless it is xchg (0x86). */
4071 if (i.prefix[LOCK_PREFIX]
4072 && (!i.tm.opcode_modifier.islockable
4073 || i.mem_operands == 0
4074 || (i.tm.base_opcode != 0x86
4075 && !operand_type_check (i.types[i.operands - 1], anymem))))
4077 as_bad (_("expecting lockable instruction after `lock'"));
4081 /* Check if HLE prefix is OK. */
4082 if (i.hle_prefix && !check_hle ())
4085 /* Check BND prefix. */
4086 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4087 as_bad (_("expecting valid branch instruction after `bnd'"));
4089 /* Check NOTRACK prefix. */
4090 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4091 as_bad (_("expecting indirect branch instruction after `notrack'"));
4093 if (i.tm.cpu_flags.bitfield.cpumpx)
4095 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4096 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4097 else if (flag_code != CODE_16BIT
4098 ? i.prefix[ADDR_PREFIX]
4099 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4100 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4103 /* Insert BND prefix. */
4105 && i.tm.opcode_modifier.bndprefixok
4106 && !i.prefix[BND_PREFIX])
4107 add_prefix (BND_PREFIX_OPCODE);
4109 /* Check string instruction segment overrides. */
4110 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4112 if (!check_string ())
4114 i.disp_operands = 0;
4117 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4118 optimize_encoding ();
4120 if (!process_suffix ())
4123 /* Update operand types. */
4124 for (j = 0; j < i.operands; j++)
4125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4127 /* Make still unresolved immediate matches conform to size of immediate
4128 given in i.suffix. */
4129 if (!finalize_imm ())
4132 if (i.types[0].bitfield.imm1)
4133 i.imm_operands = 0; /* kludge for shift insns. */
4135 /* We only need to check those implicit registers for instructions
4136 with 3 operands or less. */
4137 if (i.operands <= 3)
4138 for (j = 0; j < i.operands; j++)
4139 if (i.types[j].bitfield.inoutportreg
4140 || i.types[j].bitfield.shiftcount
4141 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4144 /* ImmExt should be processed after SSE2AVX. */
4145 if (!i.tm.opcode_modifier.sse2avx
4146 && i.tm.opcode_modifier.immext)
4149 /* For insns with operands there are more diddles to do to the opcode. */
4152 if (!process_operands ())
4155 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4157 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4158 as_warn (_("translating to `%sp'"), i.tm.name);
4161 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4162 || is_evex_encoding (&i.tm))
4164 if (flag_code == CODE_16BIT)
4166 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4171 if (i.tm.opcode_modifier.vex)
4172 build_vex_prefix (t);
4174 build_evex_prefix ();
4177 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4178 instructions may define INT_OPCODE as well, so avoid this corner
4179 case for those instructions that use MODRM. */
4180 if (i.tm.base_opcode == INT_OPCODE
4181 && !i.tm.opcode_modifier.modrm
4182 && i.op[0].imms->X_add_number == 3)
4184 i.tm.base_opcode = INT3_OPCODE;
4188 if ((i.tm.opcode_modifier.jump
4189 || i.tm.opcode_modifier.jumpbyte
4190 || i.tm.opcode_modifier.jumpdword)
4191 && i.op[0].disps->X_op == O_constant)
4193 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4194 the absolute address given by the constant. Since ix86 jumps and
4195 calls are pc relative, we need to generate a reloc. */
4196 i.op[0].disps->X_add_symbol = &abs_symbol;
4197 i.op[0].disps->X_op = O_symbol;
4200 if (i.tm.opcode_modifier.rex64)
4203 /* For 8 bit registers we need an empty rex prefix. Also if the
4204 instruction already has a prefix, we need to convert old
4205 registers to new ones. */
4207 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4208 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4210 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4211 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4217 i.rex |= REX_OPCODE;
4218 for (x = 0; x < 2; x++)
4220 /* Look for 8 bit operand that uses old registers. */
4221 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4222 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4224 /* In case it is "hi" register, give up. */
4225 if (i.op[x].regs->reg_num > 3)
4226 as_bad (_("can't encode register '%s%s' in an "
4227 "instruction requiring REX prefix."),
4228 register_prefix, i.op[x].regs->reg_name);
4230 /* Otherwise it is equivalent to the extended register.
4231 Since the encoding doesn't change this is merely
4232 cosmetic cleanup for debug output. */
4234 i.op[x].regs = i.op[x].regs + 8;
4239 if (i.rex == 0 && i.rex_encoding)
4241 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4242 that uses legacy register. If it is "hi" register, don't add
4243 the REX_OPCODE byte. */
4245 for (x = 0; x < 2; x++)
4246 if (i.types[x].bitfield.reg
4247 && i.types[x].bitfield.byte
4248 && (i.op[x].regs->reg_flags & RegRex64) == 0
4249 && i.op[x].regs->reg_num > 3)
4251 i.rex_encoding = FALSE;
4260 add_prefix (REX_OPCODE | i.rex);
4262 /* We are ready to output the insn. */
4267 parse_insn (char *line, char *mnemonic)
4270 char *token_start = l;
4273 const insn_template *t;
4279 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4284 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4286 as_bad (_("no such instruction: `%s'"), token_start);
4291 if (!is_space_char (*l)
4292 && *l != END_OF_INSN
4294 || (*l != PREFIX_SEPARATOR
4297 as_bad (_("invalid character %s in mnemonic"),
4298 output_invalid (*l));
4301 if (token_start == l)
4303 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4304 as_bad (_("expecting prefix; got nothing"));
4306 as_bad (_("expecting mnemonic; got nothing"));
4310 /* Look up instruction (or prefix) via hash table. */
4311 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4313 if (*l != END_OF_INSN
4314 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4315 && current_templates
4316 && current_templates->start->opcode_modifier.isprefix)
4318 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4320 as_bad ((flag_code != CODE_64BIT
4321 ? _("`%s' is only supported in 64-bit mode")
4322 : _("`%s' is not supported in 64-bit mode")),
4323 current_templates->start->name);
4326 /* If we are in 16-bit mode, do not allow addr16 or data16.
4327 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4328 if ((current_templates->start->opcode_modifier.size16
4329 || current_templates->start->opcode_modifier.size32)
4330 && flag_code != CODE_64BIT
4331 && (current_templates->start->opcode_modifier.size32
4332 ^ (flag_code == CODE_16BIT)))
4334 as_bad (_("redundant %s prefix"),
4335 current_templates->start->name);
4338 if (current_templates->start->opcode_length == 0)
4340 /* Handle pseudo prefixes. */
4341 switch (current_templates->start->base_opcode)
4345 i.disp_encoding = disp_encoding_8bit;
4349 i.disp_encoding = disp_encoding_32bit;
4353 i.dir_encoding = dir_encoding_load;
4357 i.dir_encoding = dir_encoding_store;
4361 i.vec_encoding = vex_encoding_vex2;
4365 i.vec_encoding = vex_encoding_vex3;
4369 i.vec_encoding = vex_encoding_evex;
4373 i.rex_encoding = TRUE;
4377 i.no_optimize = TRUE;
4385 /* Add prefix, checking for repeated prefixes. */
4386 switch (add_prefix (current_templates->start->base_opcode))
4391 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4392 i.notrack_prefix = current_templates->start->name;
4395 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4396 i.hle_prefix = current_templates->start->name;
4397 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4398 i.bnd_prefix = current_templates->start->name;
4400 i.rep_prefix = current_templates->start->name;
4406 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4413 if (!current_templates)
4415 /* Check if we should swap operand or force 32bit displacement in
4417 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4418 i.dir_encoding = dir_encoding_store;
4419 else if (mnem_p - 3 == dot_p
4422 i.disp_encoding = disp_encoding_8bit;
4423 else if (mnem_p - 4 == dot_p
4427 i.disp_encoding = disp_encoding_32bit;
4432 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4435 if (!current_templates)
4438 /* See if we can get a match by trimming off a suffix. */
4441 case WORD_MNEM_SUFFIX:
4442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4443 i.suffix = SHORT_MNEM_SUFFIX;
4446 case BYTE_MNEM_SUFFIX:
4447 case QWORD_MNEM_SUFFIX:
4448 i.suffix = mnem_p[-1];
4450 current_templates = (const templates *) hash_find (op_hash,
4453 case SHORT_MNEM_SUFFIX:
4454 case LONG_MNEM_SUFFIX:
4457 i.suffix = mnem_p[-1];
4459 current_templates = (const templates *) hash_find (op_hash,
4468 if (intel_float_operand (mnemonic) == 1)
4469 i.suffix = SHORT_MNEM_SUFFIX;
4471 i.suffix = LONG_MNEM_SUFFIX;
4473 current_templates = (const templates *) hash_find (op_hash,
4478 if (!current_templates)
4480 as_bad (_("no such instruction: `%s'"), token_start);
4485 if (current_templates->start->opcode_modifier.jump
4486 || current_templates->start->opcode_modifier.jumpbyte)
4488 /* Check for a branch hint. We allow ",pt" and ",pn" for
4489 predict taken and predict not taken respectively.
4490 I'm not sure that branch hints actually do anything on loop
4491 and jcxz insns (JumpByte) for current Pentium4 chips. They
4492 may work in the future and it doesn't hurt to accept them
4494 if (l[0] == ',' && l[1] == 'p')
4498 if (!add_prefix (DS_PREFIX_OPCODE))
4502 else if (l[2] == 'n')
4504 if (!add_prefix (CS_PREFIX_OPCODE))
4510 /* Any other comma loses. */
4513 as_bad (_("invalid character %s in mnemonic"),
4514 output_invalid (*l));
4518 /* Check if instruction is supported on specified architecture. */
4520 for (t = current_templates->start; t < current_templates->end; ++t)
4522 supported |= cpu_flags_match (t);
4523 if (supported == CPU_FLAGS_PERFECT_MATCH)
4525 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4526 as_warn (_("use .code16 to ensure correct addressing mode"));
4532 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4533 as_bad (flag_code == CODE_64BIT
4534 ? _("`%s' is not supported in 64-bit mode")
4535 : _("`%s' is only supported in 64-bit mode"),
4536 current_templates->start->name);
4538 as_bad (_("`%s' is not supported on `%s%s'"),
4539 current_templates->start->name,
4540 cpu_arch_name ? cpu_arch_name : default_arch,
4541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4547 parse_operands (char *l, const char *mnemonic)
4551 /* 1 if operand is pending after ','. */
4552 unsigned int expecting_operand = 0;
4554 /* Non-zero if operand parens not balanced. */
4555 unsigned int paren_not_balanced;
4557 while (*l != END_OF_INSN)
4559 /* Skip optional white space before operand. */
4560 if (is_space_char (*l))
4562 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4564 as_bad (_("invalid character %s before operand %d"),
4565 output_invalid (*l),
4569 token_start = l; /* After white space. */
4570 paren_not_balanced = 0;
4571 while (paren_not_balanced || *l != ',')
4573 if (*l == END_OF_INSN)
4575 if (paren_not_balanced)
4578 as_bad (_("unbalanced parenthesis in operand %d."),
4581 as_bad (_("unbalanced brackets in operand %d."),
4586 break; /* we are done */
4588 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4590 as_bad (_("invalid character %s in operand %d"),
4591 output_invalid (*l),
4598 ++paren_not_balanced;
4600 --paren_not_balanced;
4605 ++paren_not_balanced;
4607 --paren_not_balanced;
4611 if (l != token_start)
4612 { /* Yes, we've read in another operand. */
4613 unsigned int operand_ok;
4614 this_operand = i.operands++;
4615 if (i.operands > MAX_OPERANDS)
4617 as_bad (_("spurious operands; (%d operands/instruction max)"),
4621 i.types[this_operand].bitfield.unspecified = 1;
4622 /* Now parse operand adding info to 'i' as we go along. */
4623 END_STRING_AND_SAVE (l);
4627 i386_intel_operand (token_start,
4628 intel_float_operand (mnemonic));
4630 operand_ok = i386_att_operand (token_start);
4632 RESTORE_END_STRING (l);
4638 if (expecting_operand)
4640 expecting_operand_after_comma:
4641 as_bad (_("expecting operand after ','; got nothing"));
4646 as_bad (_("expecting operand before ','; got nothing"));
4651 /* Now *l must be either ',' or END_OF_INSN. */
4654 if (*++l == END_OF_INSN)
4656 /* Just skip it, if it's \n complain. */
4657 goto expecting_operand_after_comma;
4659 expecting_operand = 1;
4666 swap_2_operands (int xchg1, int xchg2)
4668 union i386_op temp_op;
4669 i386_operand_type temp_type;
4670 enum bfd_reloc_code_real temp_reloc;
4672 temp_type = i.types[xchg2];
4673 i.types[xchg2] = i.types[xchg1];
4674 i.types[xchg1] = temp_type;
4675 temp_op = i.op[xchg2];
4676 i.op[xchg2] = i.op[xchg1];
4677 i.op[xchg1] = temp_op;
4678 temp_reloc = i.reloc[xchg2];
4679 i.reloc[xchg2] = i.reloc[xchg1];
4680 i.reloc[xchg1] = temp_reloc;
4684 if (i.mask->operand == xchg1)
4685 i.mask->operand = xchg2;
4686 else if (i.mask->operand == xchg2)
4687 i.mask->operand = xchg1;
4691 if (i.broadcast->operand == xchg1)
4692 i.broadcast->operand = xchg2;
4693 else if (i.broadcast->operand == xchg2)
4694 i.broadcast->operand = xchg1;
4698 if (i.rounding->operand == xchg1)
4699 i.rounding->operand = xchg2;
4700 else if (i.rounding->operand == xchg2)
4701 i.rounding->operand = xchg1;
4706 swap_operands (void)
4712 swap_2_operands (1, i.operands - 2);
4716 swap_2_operands (0, i.operands - 1);
4722 if (i.mem_operands == 2)
4724 const seg_entry *temp_seg;
4725 temp_seg = i.seg[0];
4726 i.seg[0] = i.seg[1];
4727 i.seg[1] = temp_seg;
4731 /* Try to ensure constant immediates are represented in the smallest
4736 char guess_suffix = 0;
4740 guess_suffix = i.suffix;
4741 else if (i.reg_operands)
4743 /* Figure out a suffix from the last register operand specified.
4744 We can't do this properly yet, ie. excluding InOutPortReg,
4745 but the following works for instructions with immediates.
4746 In any case, we can't set i.suffix yet. */
4747 for (op = i.operands; --op >= 0;)
4748 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4750 guess_suffix = BYTE_MNEM_SUFFIX;
4753 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4755 guess_suffix = WORD_MNEM_SUFFIX;
4758 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4760 guess_suffix = LONG_MNEM_SUFFIX;
4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4765 guess_suffix = QWORD_MNEM_SUFFIX;
4769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4770 guess_suffix = WORD_MNEM_SUFFIX;
4772 for (op = i.operands; --op >= 0;)
4773 if (operand_type_check (i.types[op], imm))
4775 switch (i.op[op].imms->X_op)
4778 /* If a suffix is given, this operand may be shortened. */
4779 switch (guess_suffix)
4781 case LONG_MNEM_SUFFIX:
4782 i.types[op].bitfield.imm32 = 1;
4783 i.types[op].bitfield.imm64 = 1;
4785 case WORD_MNEM_SUFFIX:
4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
4791 case BYTE_MNEM_SUFFIX:
4792 i.types[op].bitfield.imm8 = 1;
4793 i.types[op].bitfield.imm8s = 1;
4794 i.types[op].bitfield.imm16 = 1;
4795 i.types[op].bitfield.imm32 = 1;
4796 i.types[op].bitfield.imm32s = 1;
4797 i.types[op].bitfield.imm64 = 1;
4801 /* If this operand is at most 16 bits, convert it
4802 to a signed 16 bit number before trying to see
4803 whether it will fit in an even smaller size.
4804 This allows a 16-bit operand such as $0xffe0 to
4805 be recognised as within Imm8S range. */
4806 if ((i.types[op].bitfield.imm16)
4807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4809 i.op[op].imms->X_add_number =
4810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4813 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4814 if ((i.types[op].bitfield.imm32)
4815 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4818 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4819 ^ ((offsetT) 1 << 31))
4820 - ((offsetT) 1 << 31));
4824 = operand_type_or (i.types[op],
4825 smallest_imm_type (i.op[op].imms->X_add_number));
4827 /* We must avoid matching of Imm32 templates when 64bit
4828 only immediate is available. */
4829 if (guess_suffix == QWORD_MNEM_SUFFIX)
4830 i.types[op].bitfield.imm32 = 0;
4837 /* Symbols and expressions. */
4839 /* Convert symbolic operand to proper sizes for matching, but don't
4840 prevent matching a set of insns that only supports sizes other
4841 than those matching the insn suffix. */
4843 i386_operand_type mask, allowed;
4844 const insn_template *t;
4846 operand_type_set (&mask, 0);
4847 operand_type_set (&allowed, 0);
4849 for (t = current_templates->start;
4850 t < current_templates->end;
4852 allowed = operand_type_or (allowed,
4853 t->operand_types[op]);
4854 switch (guess_suffix)
4856 case QWORD_MNEM_SUFFIX:
4857 mask.bitfield.imm64 = 1;
4858 mask.bitfield.imm32s = 1;
4860 case LONG_MNEM_SUFFIX:
4861 mask.bitfield.imm32 = 1;
4863 case WORD_MNEM_SUFFIX:
4864 mask.bitfield.imm16 = 1;
4866 case BYTE_MNEM_SUFFIX:
4867 mask.bitfield.imm8 = 1;
4872 allowed = operand_type_and (mask, allowed);
4873 if (!operand_type_all_zero (&allowed))
4874 i.types[op] = operand_type_and (i.types[op], mask);
4881 /* Try to use the smallest displacement type too. */
4883 optimize_disp (void)
4887 for (op = i.operands; --op >= 0;)
4888 if (operand_type_check (i.types[op], disp))
4890 if (i.op[op].disps->X_op == O_constant)
4892 offsetT op_disp = i.op[op].disps->X_add_number;
4894 if (i.types[op].bitfield.disp16
4895 && (op_disp & ~(offsetT) 0xffff) == 0)
4897 /* If this operand is at most 16 bits, convert
4898 to a signed 16 bit number and don't use 64bit
4900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4901 i.types[op].bitfield.disp64 = 0;
4904 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4905 if (i.types[op].bitfield.disp32
4906 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4908 /* If this operand is at most 32 bits, convert
4909 to a signed 32 bit number and don't use 64bit
4911 op_disp &= (((offsetT) 2 << 31) - 1);
4912 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4913 i.types[op].bitfield.disp64 = 0;
4916 if (!op_disp && i.types[op].bitfield.baseindex)
4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
4926 else if (flag_code == CODE_64BIT)
4928 if (fits_in_signed_long (op_disp))
4930 i.types[op].bitfield.disp64 = 0;
4931 i.types[op].bitfield.disp32s = 1;
4933 if (i.prefix[ADDR_PREFIX]
4934 && fits_in_unsigned_long (op_disp))
4935 i.types[op].bitfield.disp32 = 1;
4937 if ((i.types[op].bitfield.disp32
4938 || i.types[op].bitfield.disp32s
4939 || i.types[op].bitfield.disp16)
4940 && fits_in_disp8 (op_disp))
4941 i.types[op].bitfield.disp8 = 1;
4943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4947 i.op[op].disps, 0, i.reloc[op]);
4948 i.types[op].bitfield.disp8 = 0;
4949 i.types[op].bitfield.disp16 = 0;
4950 i.types[op].bitfield.disp32 = 0;
4951 i.types[op].bitfield.disp32s = 0;
4952 i.types[op].bitfield.disp64 = 0;
4955 /* We only support 64bit displacement on constants. */
4956 i.types[op].bitfield.disp64 = 0;
4960 /* Check if operands are valid for the instruction. */
4963 check_VecOperands (const insn_template *t)
4967 /* Without VSIB byte, we can't have a vector register for index. */
4968 if (!t->opcode_modifier.vecsib
4970 && (i.index_reg->reg_type.bitfield.xmmword
4971 || i.index_reg->reg_type.bitfield.ymmword
4972 || i.index_reg->reg_type.bitfield.zmmword))
4974 i.error = unsupported_vector_index_register;
4978 /* Check if default mask is allowed. */
4979 if (t->opcode_modifier.nodefmask
4980 && (!i.mask || i.mask->mask->reg_num == 0))
4982 i.error = no_default_mask;
4986 /* For VSIB byte, we need a vector register for index, and all vector
4987 registers must be distinct. */
4988 if (t->opcode_modifier.vecsib)
4991 || !((t->opcode_modifier.vecsib == VecSIB128
4992 && i.index_reg->reg_type.bitfield.xmmword)
4993 || (t->opcode_modifier.vecsib == VecSIB256
4994 && i.index_reg->reg_type.bitfield.ymmword)
4995 || (t->opcode_modifier.vecsib == VecSIB512
4996 && i.index_reg->reg_type.bitfield.zmmword)))
4998 i.error = invalid_vsib_address;
5002 gas_assert (i.reg_operands == 2 || i.mask);
5003 if (i.reg_operands == 2 && !i.mask)
5005 gas_assert (i.types[0].bitfield.regsimd);
5006 gas_assert (i.types[0].bitfield.xmmword
5007 || i.types[0].bitfield.ymmword);
5008 gas_assert (i.types[2].bitfield.regsimd);
5009 gas_assert (i.types[2].bitfield.xmmword
5010 || i.types[2].bitfield.ymmword);
5011 if (operand_check == check_none)
5013 if (register_number (i.op[0].regs)
5014 != register_number (i.index_reg)
5015 && register_number (i.op[2].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[0].regs)
5018 != register_number (i.op[2].regs))
5020 if (operand_check == check_error)
5022 i.error = invalid_vector_register_set;
5025 as_warn (_("mask, index, and destination registers should be distinct"));
5027 else if (i.reg_operands == 1 && i.mask)
5029 if (i.types[1].bitfield.regsimd
5030 && (i.types[1].bitfield.xmmword
5031 || i.types[1].bitfield.ymmword
5032 || i.types[1].bitfield.zmmword)
5033 && (register_number (i.op[1].regs)
5034 == register_number (i.index_reg)))
5036 if (operand_check == check_error)
5038 i.error = invalid_vector_register_set;
5041 if (operand_check != check_none)
5042 as_warn (_("index and destination registers should be distinct"));
5047 /* Check if broadcast is supported by the instruction and is applied
5048 to the memory operand. */
5051 int broadcasted_opnd_size;
5053 /* Check if specified broadcast is supported in this instruction,
5054 and it's applied to memory operand of DWORD or QWORD type,
5055 depending on VecESize. */
5056 if (i.broadcast->type != t->opcode_modifier.broadcast
5057 || !i.types[i.broadcast->operand].bitfield.mem
5058 || (t->opcode_modifier.vecesize == 0
5059 && !i.types[i.broadcast->operand].bitfield.dword
5060 && !i.types[i.broadcast->operand].bitfield.unspecified)
5061 || (t->opcode_modifier.vecesize == 1
5062 && !i.types[i.broadcast->operand].bitfield.qword
5063 && !i.types[i.broadcast->operand].bitfield.unspecified))
5066 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5067 if (i.broadcast->type == BROADCAST_1TO16)
5068 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5069 else if (i.broadcast->type == BROADCAST_1TO8)
5070 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5071 else if (i.broadcast->type == BROADCAST_1TO4)
5072 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5073 else if (i.broadcast->type == BROADCAST_1TO2)
5074 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5078 if ((broadcasted_opnd_size == 256
5079 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5080 || (broadcasted_opnd_size == 512
5081 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5084 i.error = unsupported_broadcast;
5088 /* If broadcast is supported in this instruction, we need to check if
5089 operand of one-element size isn't specified without broadcast. */
5090 else if (t->opcode_modifier.broadcast && i.mem_operands)
5092 /* Find memory operand. */
5093 for (op = 0; op < i.operands; op++)
5094 if (operand_type_check (i.types[op], anymem))
5096 gas_assert (op < i.operands);
5097 /* Check size of the memory operand. */
5098 if ((t->opcode_modifier.vecesize == 0
5099 && i.types[op].bitfield.dword)
5100 || (t->opcode_modifier.vecesize == 1
5101 && i.types[op].bitfield.qword))
5103 i.error = broadcast_needed;
5108 /* Check if requested masking is supported. */
5110 && (!t->opcode_modifier.masking
5112 && t->opcode_modifier.masking == MERGING_MASKING)))
5114 i.error = unsupported_masking;
5118 /* Check if masking is applied to dest operand. */
5119 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5121 i.error = mask_not_on_destination;
5128 if ((i.rounding->type != saeonly
5129 && !t->opcode_modifier.staticrounding)
5130 || (i.rounding->type == saeonly
5131 && (t->opcode_modifier.staticrounding
5132 || !t->opcode_modifier.sae)))
5134 i.error = unsupported_rc_sae;
5137 /* If the instruction has several immediate operands and one of
5138 them is rounding, the rounding operand should be the last
5139 immediate operand. */
5140 if (i.imm_operands > 1
5141 && i.rounding->operand != (int) (i.imm_operands - 1))
5143 i.error = rc_sae_operand_not_last_imm;
5148 /* Check vector Disp8 operand. */
5149 if (t->opcode_modifier.disp8memshift
5150 && i.disp_encoding != disp_encoding_32bit)
5153 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5155 i.memshift = t->opcode_modifier.disp8memshift;
5157 for (op = 0; op < i.operands; op++)
5158 if (operand_type_check (i.types[op], disp)
5159 && i.op[op].disps->X_op == O_constant)
5161 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5163 i.types[op].bitfield.disp8 = 1;
5166 i.types[op].bitfield.disp8 = 0;
5175 /* Check if operands are valid for the instruction. Update VEX
5179 VEX_check_operands (const insn_template *t)
5181 if (i.vec_encoding == vex_encoding_evex)
5183 /* This instruction must be encoded with EVEX prefix. */
5184 if (!is_evex_encoding (t))
5186 i.error = unsupported;
5192 if (!t->opcode_modifier.vex)
5194 /* This instruction template doesn't have VEX prefix. */
5195 if (i.vec_encoding != vex_encoding_default)
5197 i.error = unsupported;
5203 /* Only check VEX_Imm4, which must be the first operand. */
5204 if (t->operand_types[0].bitfield.vec_imm4)
5206 if (i.op[0].imms->X_op != O_constant
5207 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5213 /* Turn off Imm8 so that update_imm won't complain. */
5214 i.types[0] = vec_imm4;
5220 static const insn_template *
5221 match_template (char mnem_suffix)
5223 /* Points to template once we've found it. */
5224 const insn_template *t;
5225 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5226 i386_operand_type overlap4;
5227 unsigned int found_reverse_match;
5228 i386_opcode_modifier suffix_check, mnemsuf_check;
5229 i386_operand_type operand_types [MAX_OPERANDS];
5230 int addr_prefix_disp;
5232 unsigned int found_cpu_match;
5233 unsigned int check_register;
5234 enum i386_error specific_error = 0;
5236 #if MAX_OPERANDS != 5
5237 # error "MAX_OPERANDS must be 5."
5240 found_reverse_match = 0;
5241 addr_prefix_disp = -1;
5243 memset (&suffix_check, 0, sizeof (suffix_check));
5244 if (i.suffix == BYTE_MNEM_SUFFIX)
5245 suffix_check.no_bsuf = 1;
5246 else if (i.suffix == WORD_MNEM_SUFFIX)
5247 suffix_check.no_wsuf = 1;
5248 else if (i.suffix == SHORT_MNEM_SUFFIX)
5249 suffix_check.no_ssuf = 1;
5250 else if (i.suffix == LONG_MNEM_SUFFIX)
5251 suffix_check.no_lsuf = 1;
5252 else if (i.suffix == QWORD_MNEM_SUFFIX)
5253 suffix_check.no_qsuf = 1;
5254 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5255 suffix_check.no_ldsuf = 1;
5257 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5260 switch (mnem_suffix)
5262 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5263 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5264 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5265 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5266 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5270 /* Must have right number of operands. */
5271 i.error = number_of_operands_mismatch;
5273 for (t = current_templates->start; t < current_templates->end; t++)
5275 addr_prefix_disp = -1;
5277 if (i.operands != t->operands)
5280 /* Check processor support. */
5281 i.error = unsupported;
5282 found_cpu_match = (cpu_flags_match (t)
5283 == CPU_FLAGS_PERFECT_MATCH);
5284 if (!found_cpu_match)
5287 /* Check AT&T mnemonic. */
5288 i.error = unsupported_with_intel_mnemonic;
5289 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5292 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5293 i.error = unsupported_syntax;
5294 if ((intel_syntax && t->opcode_modifier.attsyntax)
5295 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5296 || (intel64 && t->opcode_modifier.amd64)
5297 || (!intel64 && t->opcode_modifier.intel64))
5300 /* Check the suffix, except for some instructions in intel mode. */
5301 i.error = invalid_instruction_suffix;
5302 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5303 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5304 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5305 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5306 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5307 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5308 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5310 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5311 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5312 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5313 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5314 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5315 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5316 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5319 if (!operand_size_match (t))
5322 for (j = 0; j < MAX_OPERANDS; j++)
5323 operand_types[j] = t->operand_types[j];
5325 /* In general, don't allow 64-bit operands in 32-bit mode. */
5326 if (i.suffix == QWORD_MNEM_SUFFIX
5327 && flag_code != CODE_64BIT
5329 ? (!t->opcode_modifier.ignoresize
5330 && !intel_float_operand (t->name))
5331 : intel_float_operand (t->name) != 2)
5332 && ((!operand_types[0].bitfield.regmmx
5333 && !operand_types[0].bitfield.regsimd)
5334 || (!operand_types[t->operands > 1].bitfield.regmmx
5335 && !operand_types[t->operands > 1].bitfield.regsimd))
5336 && (t->base_opcode != 0x0fc7
5337 || t->extension_opcode != 1 /* cmpxchg8b */))
5340 /* In general, don't allow 32-bit operands on pre-386. */
5341 else if (i.suffix == LONG_MNEM_SUFFIX
5342 && !cpu_arch_flags.bitfield.cpui386
5344 ? (!t->opcode_modifier.ignoresize
5345 && !intel_float_operand (t->name))
5346 : intel_float_operand (t->name) != 2)
5347 && ((!operand_types[0].bitfield.regmmx
5348 && !operand_types[0].bitfield.regsimd)
5349 || (!operand_types[t->operands > 1].bitfield.regmmx
5350 && !operand_types[t->operands > 1].bitfield.regsimd)))
5353 /* Do not verify operands when there are none. */
5357 /* We've found a match; break out of loop. */
5361 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5362 into Disp32/Disp16/Disp32 operand. */
5363 if (i.prefix[ADDR_PREFIX] != 0)
5365 /* There should be only one Disp operand. */
5369 for (j = 0; j < MAX_OPERANDS; j++)
5371 if (operand_types[j].bitfield.disp16)
5373 addr_prefix_disp = j;
5374 operand_types[j].bitfield.disp32 = 1;
5375 operand_types[j].bitfield.disp16 = 0;
5381 for (j = 0; j < MAX_OPERANDS; j++)
5383 if (operand_types[j].bitfield.disp32)
5385 addr_prefix_disp = j;
5386 operand_types[j].bitfield.disp32 = 0;
5387 operand_types[j].bitfield.disp16 = 1;
5393 for (j = 0; j < MAX_OPERANDS; j++)
5395 if (operand_types[j].bitfield.disp64)
5397 addr_prefix_disp = j;
5398 operand_types[j].bitfield.disp64 = 0;
5399 operand_types[j].bitfield.disp32 = 1;
5407 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5408 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5411 /* We check register size if needed. */
5412 check_register = t->opcode_modifier.checkregsize;
5413 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5414 switch (t->operands)
5417 if (!operand_type_match (overlap0, i.types[0]))
5421 /* xchg %eax, %eax is a special case. It is an alias for nop
5422 only in 32bit mode and we can use opcode 0x90. In 64bit
5423 mode, we can't use 0x90 for xchg %eax, %eax since it should
5424 zero-extend %eax to %rax. */
5425 if (flag_code == CODE_64BIT
5426 && t->base_opcode == 0x90
5427 && operand_type_equal (&i.types [0], &acc32)
5428 && operand_type_equal (&i.types [1], &acc32))
5430 /* If we want store form, we reverse direction of operands. */
5431 if (i.dir_encoding == dir_encoding_store
5432 && t->opcode_modifier.d)
5437 /* If we want store form, we skip the current load. */
5438 if (i.dir_encoding == dir_encoding_store
5439 && i.mem_operands == 0
5440 && t->opcode_modifier.load)
5445 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5446 if (!operand_type_match (overlap0, i.types[0])
5447 || !operand_type_match (overlap1, i.types[1])
5449 && !operand_type_register_match (i.types[0],
5454 /* Check if other direction is valid ... */
5455 if (!t->opcode_modifier.d)
5459 /* Try reversing direction of operands. */
5460 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5461 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5462 if (!operand_type_match (overlap0, i.types[0])
5463 || !operand_type_match (overlap1, i.types[1])
5465 && !operand_type_register_match (i.types[0],
5470 /* Does not match either direction. */
5473 /* found_reverse_match holds which of D or FloatR
5475 if (!t->opcode_modifier.d)
5476 found_reverse_match = 0;
5477 else if (operand_types[0].bitfield.tbyte)
5478 found_reverse_match = Opcode_FloatD;
5480 found_reverse_match = Opcode_D;
5481 if (t->opcode_modifier.floatr)
5482 found_reverse_match |= Opcode_FloatR;
5486 /* Found a forward 2 operand match here. */
5487 switch (t->operands)
5490 overlap4 = operand_type_and (i.types[4],
5494 overlap3 = operand_type_and (i.types[3],
5498 overlap2 = operand_type_and (i.types[2],
5503 switch (t->operands)
5506 if (!operand_type_match (overlap4, i.types[4])
5507 || !operand_type_register_match (i.types[3],
5514 if (!operand_type_match (overlap3, i.types[3])
5516 && (!operand_type_register_match (i.types[1],
5520 || !operand_type_register_match (i.types[2],
5523 operand_types[3]))))
5527 /* Here we make use of the fact that there are no
5528 reverse match 3 operand instructions. */
5529 if (!operand_type_match (overlap2, i.types[2])
5531 && (!operand_type_register_match (i.types[0],
5535 || !operand_type_register_match (i.types[1],
5538 operand_types[2]))))
5543 /* Found either forward/reverse 2, 3 or 4 operand match here:
5544 slip through to break. */
5546 if (!found_cpu_match)
5548 found_reverse_match = 0;
5552 /* Check if vector and VEX operands are valid. */
5553 if (check_VecOperands (t) || VEX_check_operands (t))
5555 specific_error = i.error;
5559 /* We've found a match; break out of loop. */
5563 if (t == current_templates->end)
5565 /* We found no match. */
5566 const char *err_msg;
5567 switch (specific_error ? specific_error : i.error)
5571 case operand_size_mismatch:
5572 err_msg = _("operand size mismatch");
5574 case operand_type_mismatch:
5575 err_msg = _("operand type mismatch");
5577 case register_type_mismatch:
5578 err_msg = _("register type mismatch");
5580 case number_of_operands_mismatch:
5581 err_msg = _("number of operands mismatch");
5583 case invalid_instruction_suffix:
5584 err_msg = _("invalid instruction suffix");
5587 err_msg = _("constant doesn't fit in 4 bits");
5589 case unsupported_with_intel_mnemonic:
5590 err_msg = _("unsupported with Intel mnemonic");
5592 case unsupported_syntax:
5593 err_msg = _("unsupported syntax");
5596 as_bad (_("unsupported instruction `%s'"),
5597 current_templates->start->name);
5599 case invalid_vsib_address:
5600 err_msg = _("invalid VSIB address");
5602 case invalid_vector_register_set:
5603 err_msg = _("mask, index, and destination registers must be distinct");
5605 case unsupported_vector_index_register:
5606 err_msg = _("unsupported vector index register");
5608 case unsupported_broadcast:
5609 err_msg = _("unsupported broadcast");
5611 case broadcast_not_on_src_operand:
5612 err_msg = _("broadcast not on source memory operand");
5614 case broadcast_needed:
5615 err_msg = _("broadcast is needed for operand of such type");
5617 case unsupported_masking:
5618 err_msg = _("unsupported masking");
5620 case mask_not_on_destination:
5621 err_msg = _("mask not on destination operand");
5623 case no_default_mask:
5624 err_msg = _("default mask isn't allowed");
5626 case unsupported_rc_sae:
5627 err_msg = _("unsupported static rounding/sae");
5629 case rc_sae_operand_not_last_imm:
5631 err_msg = _("RC/SAE operand must precede immediate operands");
5633 err_msg = _("RC/SAE operand must follow immediate operands");
5635 case invalid_register_operand:
5636 err_msg = _("invalid register operand");
5639 as_bad (_("%s for `%s'"), err_msg,
5640 current_templates->start->name);
5644 if (!quiet_warnings)
5647 && (i.types[0].bitfield.jumpabsolute
5648 != operand_types[0].bitfield.jumpabsolute))
5650 as_warn (_("indirect %s without `*'"), t->name);
5653 if (t->opcode_modifier.isprefix
5654 && t->opcode_modifier.ignoresize)
5656 /* Warn them that a data or address size prefix doesn't
5657 affect assembly of the next line of code. */
5658 as_warn (_("stand-alone `%s' prefix"), t->name);
5662 /* Copy the template we found. */
5665 if (addr_prefix_disp != -1)
5666 i.tm.operand_types[addr_prefix_disp]
5667 = operand_types[addr_prefix_disp];
5669 if (found_reverse_match)
5671 /* If we found a reverse match we must alter the opcode
5672 direction bit. found_reverse_match holds bits to change
5673 (different for int & float insns). */
5675 i.tm.base_opcode ^= found_reverse_match;
5677 i.tm.operand_types[0] = operand_types[1];
5678 i.tm.operand_types[1] = operand_types[0];
5687 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5688 if (i.tm.operand_types[mem_op].bitfield.esseg)
5690 if (i.seg[0] != NULL && i.seg[0] != &es)
5692 as_bad (_("`%s' operand %d must use `%ses' segment"),
5698 /* There's only ever one segment override allowed per instruction.
5699 This instruction possibly has a legal segment override on the
5700 second operand, so copy the segment to where non-string
5701 instructions store it, allowing common code. */
5702 i.seg[0] = i.seg[1];
5704 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5706 if (i.seg[1] != NULL && i.seg[1] != &es)
5708 as_bad (_("`%s' operand %d must use `%ses' segment"),
5719 process_suffix (void)
5721 /* If matched instruction specifies an explicit instruction mnemonic
5723 if (i.tm.opcode_modifier.size16)
5724 i.suffix = WORD_MNEM_SUFFIX;
5725 else if (i.tm.opcode_modifier.size32)
5726 i.suffix = LONG_MNEM_SUFFIX;
5727 else if (i.tm.opcode_modifier.size64)
5728 i.suffix = QWORD_MNEM_SUFFIX;
5729 else if (i.reg_operands)
5731 /* If there's no instruction mnemonic suffix we try to invent one
5732 based on register operands. */
5735 /* We take i.suffix from the last register operand specified,
5736 Destination register type is more significant than source
5737 register type. crc32 in SSE4.2 prefers source register
5739 if (i.tm.base_opcode == 0xf20f38f1)
5741 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5742 i.suffix = WORD_MNEM_SUFFIX;
5743 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5744 i.suffix = LONG_MNEM_SUFFIX;
5745 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5746 i.suffix = QWORD_MNEM_SUFFIX;
5748 else if (i.tm.base_opcode == 0xf20f38f0)
5750 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5751 i.suffix = BYTE_MNEM_SUFFIX;
5758 if (i.tm.base_opcode == 0xf20f38f1
5759 || i.tm.base_opcode == 0xf20f38f0)
5761 /* We have to know the operand size for crc32. */
5762 as_bad (_("ambiguous memory operand size for `%s`"),
5767 for (op = i.operands; --op >= 0;)
5768 if (!i.tm.operand_types[op].bitfield.inoutportreg
5769 && !i.tm.operand_types[op].bitfield.shiftcount)
5771 if (!i.types[op].bitfield.reg)
5773 if (i.types[op].bitfield.byte)
5774 i.suffix = BYTE_MNEM_SUFFIX;
5775 else if (i.types[op].bitfield.word)
5776 i.suffix = WORD_MNEM_SUFFIX;
5777 else if (i.types[op].bitfield.dword)
5778 i.suffix = LONG_MNEM_SUFFIX;
5779 else if (i.types[op].bitfield.qword)
5780 i.suffix = QWORD_MNEM_SUFFIX;
5787 else if (i.suffix == BYTE_MNEM_SUFFIX)
5790 && i.tm.opcode_modifier.ignoresize
5791 && i.tm.opcode_modifier.no_bsuf)
5793 else if (!check_byte_reg ())
5796 else if (i.suffix == LONG_MNEM_SUFFIX)
5799 && i.tm.opcode_modifier.ignoresize
5800 && i.tm.opcode_modifier.no_lsuf)
5802 else if (!check_long_reg ())
5805 else if (i.suffix == QWORD_MNEM_SUFFIX)
5808 && i.tm.opcode_modifier.ignoresize
5809 && i.tm.opcode_modifier.no_qsuf)
5811 else if (!check_qword_reg ())
5814 else if (i.suffix == WORD_MNEM_SUFFIX)
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_wsuf)
5820 else if (!check_word_reg ())
5823 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5824 /* Do nothing if the instruction is going to ignore the prefix. */
5829 else if (i.tm.opcode_modifier.defaultsize
5831 /* exclude fldenv/frstor/fsave/fstenv */
5832 && i.tm.opcode_modifier.no_ssuf)
5834 i.suffix = stackop_size;
5836 else if (intel_syntax
5838 && (i.tm.operand_types[0].bitfield.jumpabsolute
5839 || i.tm.opcode_modifier.jumpbyte
5840 || i.tm.opcode_modifier.jumpintersegment
5841 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5842 && i.tm.extension_opcode <= 3)))
5847 if (!i.tm.opcode_modifier.no_qsuf)
5849 i.suffix = QWORD_MNEM_SUFFIX;
5854 if (!i.tm.opcode_modifier.no_lsuf)
5855 i.suffix = LONG_MNEM_SUFFIX;
5858 if (!i.tm.opcode_modifier.no_wsuf)
5859 i.suffix = WORD_MNEM_SUFFIX;
5868 if (i.tm.opcode_modifier.w)
5870 as_bad (_("no instruction mnemonic suffix given and "
5871 "no register operands; can't size instruction"));
5877 unsigned int suffixes;
5879 suffixes = !i.tm.opcode_modifier.no_bsuf;
5880 if (!i.tm.opcode_modifier.no_wsuf)
5882 if (!i.tm.opcode_modifier.no_lsuf)
5884 if (!i.tm.opcode_modifier.no_ldsuf)
5886 if (!i.tm.opcode_modifier.no_ssuf)
5888 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5891 /* There are more than suffix matches. */
5892 if (i.tm.opcode_modifier.w
5893 || ((suffixes & (suffixes - 1))
5894 && !i.tm.opcode_modifier.defaultsize
5895 && !i.tm.opcode_modifier.ignoresize))
5897 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5903 /* Change the opcode based on the operand size given by i.suffix. */
5906 /* Size floating point instruction. */
5907 case LONG_MNEM_SUFFIX:
5908 if (i.tm.opcode_modifier.floatmf)
5910 i.tm.base_opcode ^= 4;
5914 case WORD_MNEM_SUFFIX:
5915 case QWORD_MNEM_SUFFIX:
5916 /* It's not a byte, select word/dword operation. */
5917 if (i.tm.opcode_modifier.w)
5919 if (i.tm.opcode_modifier.shortform)
5920 i.tm.base_opcode |= 8;
5922 i.tm.base_opcode |= 1;
5925 case SHORT_MNEM_SUFFIX:
5926 /* Now select between word & dword operations via the operand
5927 size prefix, except for instructions that will ignore this
5929 if (i.tm.opcode_modifier.addrprefixop0)
5931 /* The address size override prefix changes the size of the
5933 if ((flag_code == CODE_32BIT
5934 && i.op->regs[0].reg_type.bitfield.word)
5935 || (flag_code != CODE_32BIT
5936 && i.op->regs[0].reg_type.bitfield.dword))
5937 if (!add_prefix (ADDR_PREFIX_OPCODE))
5940 else if (i.suffix != QWORD_MNEM_SUFFIX
5941 && !i.tm.opcode_modifier.ignoresize
5942 && !i.tm.opcode_modifier.floatmf
5943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5944 || (flag_code == CODE_64BIT
5945 && i.tm.opcode_modifier.jumpbyte)))
5947 unsigned int prefix = DATA_PREFIX_OPCODE;
5949 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5950 prefix = ADDR_PREFIX_OPCODE;
5952 if (!add_prefix (prefix))
5956 /* Set mode64 for an operand. */
5957 if (i.suffix == QWORD_MNEM_SUFFIX
5958 && flag_code == CODE_64BIT
5959 && !i.tm.opcode_modifier.norex64
5960 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5962 && ! (i.operands == 2
5963 && i.tm.base_opcode == 0x90
5964 && i.tm.extension_opcode == None
5965 && operand_type_equal (&i.types [0], &acc64)
5966 && operand_type_equal (&i.types [1], &acc64)))
5976 check_byte_reg (void)
5980 for (op = i.operands; --op >= 0;)
5982 /* Skip non-register operands. */
5983 if (!i.types[op].bitfield.reg)
5986 /* If this is an eight bit register, it's OK. If it's the 16 or
5987 32 bit version of an eight bit register, we will just use the
5988 low portion, and that's OK too. */
5989 if (i.types[op].bitfield.byte)
5992 /* I/O port address operands are OK too. */
5993 if (i.tm.operand_types[op].bitfield.inoutportreg)
5996 /* crc32 doesn't generate this warning. */
5997 if (i.tm.base_opcode == 0xf20f38f0)
6000 if ((i.types[op].bitfield.word
6001 || i.types[op].bitfield.dword
6002 || i.types[op].bitfield.qword)
6003 && i.op[op].regs->reg_num < 4
6004 /* Prohibit these changes in 64bit mode, since the lowering
6005 would be more complicated. */
6006 && flag_code != CODE_64BIT)
6008 #if REGISTER_WARNINGS
6009 if (!quiet_warnings)
6010 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6012 (i.op[op].regs + (i.types[op].bitfield.word
6013 ? REGNAM_AL - REGNAM_AX
6014 : REGNAM_AL - REGNAM_EAX))->reg_name,
6016 i.op[op].regs->reg_name,
6021 /* Any other register is bad. */
6022 if (i.types[op].bitfield.reg
6023 || i.types[op].bitfield.regmmx
6024 || i.types[op].bitfield.regsimd
6025 || i.types[op].bitfield.sreg2
6026 || i.types[op].bitfield.sreg3
6027 || i.types[op].bitfield.control
6028 || i.types[op].bitfield.debug
6029 || i.types[op].bitfield.test)
6031 as_bad (_("`%s%s' not allowed with `%s%c'"),
6033 i.op[op].regs->reg_name,
6043 check_long_reg (void)
6047 for (op = i.operands; --op >= 0;)
6048 /* Skip non-register operands. */
6049 if (!i.types[op].bitfield.reg)
6051 /* Reject eight bit registers, except where the template requires
6052 them. (eg. movzb) */
6053 else if (i.types[op].bitfield.byte
6054 && (i.tm.operand_types[op].bitfield.reg
6055 || i.tm.operand_types[op].bitfield.acc)
6056 && (i.tm.operand_types[op].bitfield.word
6057 || i.tm.operand_types[op].bitfield.dword))
6059 as_bad (_("`%s%s' not allowed with `%s%c'"),
6061 i.op[op].regs->reg_name,
6066 /* Warn if the e prefix on a general reg is missing. */
6067 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6068 && i.types[op].bitfield.word
6069 && (i.tm.operand_types[op].bitfield.reg
6070 || i.tm.operand_types[op].bitfield.acc)
6071 && i.tm.operand_types[op].bitfield.dword)
6073 /* Prohibit these changes in the 64bit mode, since the
6074 lowering is more complicated. */
6075 if (flag_code == CODE_64BIT)
6077 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6078 register_prefix, i.op[op].regs->reg_name,
6082 #if REGISTER_WARNINGS
6083 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6085 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6086 register_prefix, i.op[op].regs->reg_name, i.suffix);
6089 /* Warn if the r prefix on a general reg is present. */
6090 else if (i.types[op].bitfield.qword
6091 && (i.tm.operand_types[op].bitfield.reg
6092 || i.tm.operand_types[op].bitfield.acc)
6093 && i.tm.operand_types[op].bitfield.dword)
6096 && i.tm.opcode_modifier.toqword
6097 && !i.types[0].bitfield.regsimd)
6099 /* Convert to QWORD. We want REX byte. */
6100 i.suffix = QWORD_MNEM_SUFFIX;
6104 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6105 register_prefix, i.op[op].regs->reg_name,
6114 check_qword_reg (void)
6118 for (op = i.operands; --op >= 0; )
6119 /* Skip non-register operands. */
6120 if (!i.types[op].bitfield.reg)
6122 /* Reject eight bit registers, except where the template requires
6123 them. (eg. movzb) */
6124 else if (i.types[op].bitfield.byte
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && (i.tm.operand_types[op].bitfield.word
6128 || i.tm.operand_types[op].bitfield.dword))
6130 as_bad (_("`%s%s' not allowed with `%s%c'"),
6132 i.op[op].regs->reg_name,
6137 /* Warn if the r prefix on a general reg is missing. */
6138 else if ((i.types[op].bitfield.word
6139 || i.types[op].bitfield.dword)
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && i.tm.operand_types[op].bitfield.qword)
6144 /* Prohibit these changes in the 64bit mode, since the
6145 lowering is more complicated. */
6147 && i.tm.opcode_modifier.todword
6148 && !i.types[0].bitfield.regsimd)
6150 /* Convert to DWORD. We don't want REX byte. */
6151 i.suffix = LONG_MNEM_SUFFIX;
6155 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6156 register_prefix, i.op[op].regs->reg_name,
6165 check_word_reg (void)
6168 for (op = i.operands; --op >= 0;)
6169 /* Skip non-register operands. */
6170 if (!i.types[op].bitfield.reg)
6172 /* Reject eight bit registers, except where the template requires
6173 them. (eg. movzb) */
6174 else if (i.types[op].bitfield.byte
6175 && (i.tm.operand_types[op].bitfield.reg
6176 || i.tm.operand_types[op].bitfield.acc)
6177 && (i.tm.operand_types[op].bitfield.word
6178 || i.tm.operand_types[op].bitfield.dword))
6180 as_bad (_("`%s%s' not allowed with `%s%c'"),
6182 i.op[op].regs->reg_name,
6187 /* Warn if the e or r prefix on a general reg is present. */
6188 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6189 && (i.types[op].bitfield.dword
6190 || i.types[op].bitfield.qword)
6191 && (i.tm.operand_types[op].bitfield.reg
6192 || i.tm.operand_types[op].bitfield.acc)
6193 && i.tm.operand_types[op].bitfield.word)
6195 /* Prohibit these changes in the 64bit mode, since the
6196 lowering is more complicated. */
6197 if (flag_code == CODE_64BIT)
6199 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6200 register_prefix, i.op[op].regs->reg_name,
6204 #if REGISTER_WARNINGS
6205 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6207 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6208 register_prefix, i.op[op].regs->reg_name, i.suffix);
6215 update_imm (unsigned int j)
6217 i386_operand_type overlap = i.types[j];
6218 if ((overlap.bitfield.imm8
6219 || overlap.bitfield.imm8s
6220 || overlap.bitfield.imm16
6221 || overlap.bitfield.imm32
6222 || overlap.bitfield.imm32s
6223 || overlap.bitfield.imm64)
6224 && !operand_type_equal (&overlap, &imm8)
6225 && !operand_type_equal (&overlap, &imm8s)
6226 && !operand_type_equal (&overlap, &imm16)
6227 && !operand_type_equal (&overlap, &imm32)
6228 && !operand_type_equal (&overlap, &imm32s)
6229 && !operand_type_equal (&overlap, &imm64))
6233 i386_operand_type temp;
6235 operand_type_set (&temp, 0);
6236 if (i.suffix == BYTE_MNEM_SUFFIX)
6238 temp.bitfield.imm8 = overlap.bitfield.imm8;
6239 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6241 else if (i.suffix == WORD_MNEM_SUFFIX)
6242 temp.bitfield.imm16 = overlap.bitfield.imm16;
6243 else if (i.suffix == QWORD_MNEM_SUFFIX)
6245 temp.bitfield.imm64 = overlap.bitfield.imm64;
6246 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6249 temp.bitfield.imm32 = overlap.bitfield.imm32;
6252 else if (operand_type_equal (&overlap, &imm16_32_32s)
6253 || operand_type_equal (&overlap, &imm16_32)
6254 || operand_type_equal (&overlap, &imm16_32s))
6256 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6261 if (!operand_type_equal (&overlap, &imm8)
6262 && !operand_type_equal (&overlap, &imm8s)
6263 && !operand_type_equal (&overlap, &imm16)
6264 && !operand_type_equal (&overlap, &imm32)
6265 && !operand_type_equal (&overlap, &imm32s)
6266 && !operand_type_equal (&overlap, &imm64))
6268 as_bad (_("no instruction mnemonic suffix given; "
6269 "can't determine immediate size"));
6273 i.types[j] = overlap;
6283 /* Update the first 2 immediate operands. */
6284 n = i.operands > 2 ? 2 : i.operands;
6287 for (j = 0; j < n; j++)
6288 if (update_imm (j) == 0)
6291 /* The 3rd operand can't be immediate operand. */
6292 gas_assert (operand_type_check (i.types[2], imm) == 0);
6299 process_operands (void)
6301 /* Default segment register this instruction will use for memory
6302 accesses. 0 means unknown. This is only for optimizing out
6303 unnecessary segment overrides. */
6304 const seg_entry *default_seg = 0;
6306 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6308 unsigned int dupl = i.operands;
6309 unsigned int dest = dupl - 1;
6312 /* The destination must be an xmm register. */
6313 gas_assert (i.reg_operands
6314 && MAX_OPERANDS > dupl
6315 && operand_type_equal (&i.types[dest], ®xmm));
6317 if (i.tm.operand_types[0].bitfield.acc
6318 && i.tm.operand_types[0].bitfield.xmmword)
6320 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6322 /* Keep xmm0 for instructions with VEX prefix and 3
6324 i.tm.operand_types[0].bitfield.acc = 0;
6325 i.tm.operand_types[0].bitfield.regsimd = 1;
6330 /* We remove the first xmm0 and keep the number of
6331 operands unchanged, which in fact duplicates the
6333 for (j = 1; j < i.operands; j++)
6335 i.op[j - 1] = i.op[j];
6336 i.types[j - 1] = i.types[j];
6337 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6341 else if (i.tm.opcode_modifier.implicit1stxmm0)
6343 gas_assert ((MAX_OPERANDS - 1) > dupl
6344 && (i.tm.opcode_modifier.vexsources
6347 /* Add the implicit xmm0 for instructions with VEX prefix
6349 for (j = i.operands; j > 0; j--)
6351 i.op[j] = i.op[j - 1];
6352 i.types[j] = i.types[j - 1];
6353 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6356 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6357 i.types[0] = regxmm;
6358 i.tm.operand_types[0] = regxmm;
6361 i.reg_operands += 2;
6366 i.op[dupl] = i.op[dest];
6367 i.types[dupl] = i.types[dest];
6368 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6377 i.op[dupl] = i.op[dest];
6378 i.types[dupl] = i.types[dest];
6379 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6382 if (i.tm.opcode_modifier.immext)
6385 else if (i.tm.operand_types[0].bitfield.acc
6386 && i.tm.operand_types[0].bitfield.xmmword)
6390 for (j = 1; j < i.operands; j++)
6392 i.op[j - 1] = i.op[j];
6393 i.types[j - 1] = i.types[j];
6395 /* We need to adjust fields in i.tm since they are used by
6396 build_modrm_byte. */
6397 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6404 else if (i.tm.opcode_modifier.implicitquadgroup)
6406 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6408 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6409 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6410 regnum = register_number (i.op[1].regs);
6411 first_reg_in_group = regnum & ~3;
6412 last_reg_in_group = first_reg_in_group + 3;
6413 if (regnum != first_reg_in_group)
6414 as_warn (_("source register `%s%s' implicitly denotes"
6415 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6416 register_prefix, i.op[1].regs->reg_name,
6417 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6418 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6421 else if (i.tm.opcode_modifier.regkludge)
6423 /* The imul $imm, %reg instruction is converted into
6424 imul $imm, %reg, %reg, and the clr %reg instruction
6425 is converted into xor %reg, %reg. */
6427 unsigned int first_reg_op;
6429 if (operand_type_check (i.types[0], reg))
6433 /* Pretend we saw the extra register operand. */
6434 gas_assert (i.reg_operands == 1
6435 && i.op[first_reg_op + 1].regs == 0);
6436 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6437 i.types[first_reg_op + 1] = i.types[first_reg_op];
6442 if (i.tm.opcode_modifier.shortform)
6444 if (i.types[0].bitfield.sreg2
6445 || i.types[0].bitfield.sreg3)
6447 if (i.tm.base_opcode == POP_SEG_SHORT
6448 && i.op[0].regs->reg_num == 1)
6450 as_bad (_("you can't `pop %scs'"), register_prefix);
6453 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6454 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6459 /* The register or float register operand is in operand
6463 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6464 || operand_type_check (i.types[0], reg))
6468 /* Register goes in low 3 bits of opcode. */
6469 i.tm.base_opcode |= i.op[op].regs->reg_num;
6470 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6472 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6474 /* Warn about some common errors, but press on regardless.
6475 The first case can be generated by gcc (<= 2.8.1). */
6476 if (i.operands == 2)
6478 /* Reversed arguments on faddp, fsubp, etc. */
6479 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6480 register_prefix, i.op[!intel_syntax].regs->reg_name,
6481 register_prefix, i.op[intel_syntax].regs->reg_name);
6485 /* Extraneous `l' suffix on fp insn. */
6486 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6487 register_prefix, i.op[0].regs->reg_name);
6492 else if (i.tm.opcode_modifier.modrm)
6494 /* The opcode is completed (modulo i.tm.extension_opcode which
6495 must be put into the modrm byte). Now, we make the modrm and
6496 index base bytes based on all the info we've collected. */
6498 default_seg = build_modrm_byte ();
6500 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6504 else if (i.tm.opcode_modifier.isstring)
6506 /* For the string instructions that allow a segment override
6507 on one of their operands, the default segment is ds. */
6511 if (i.tm.base_opcode == 0x8d /* lea */
6514 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6516 /* If a segment was explicitly specified, and the specified segment
6517 is not the default, use an opcode prefix to select it. If we
6518 never figured out what the default segment is, then default_seg
6519 will be zero at this point, and the specified segment prefix will
6521 if ((i.seg[0]) && (i.seg[0] != default_seg))
6523 if (!add_prefix (i.seg[0]->seg_prefix))
6529 static const seg_entry *
6530 build_modrm_byte (void)
6532 const seg_entry *default_seg = 0;
6533 unsigned int source, dest;
6536 /* The first operand of instructions with VEX prefix and 3 sources
6537 must be VEX_Imm4. */
6538 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6541 unsigned int nds, reg_slot;
6544 if (i.tm.opcode_modifier.veximmext
6545 && i.tm.opcode_modifier.immext)
6547 dest = i.operands - 2;
6548 gas_assert (dest == 3);
6551 dest = i.operands - 1;
6554 /* There are 2 kinds of instructions:
6555 1. 5 operands: 4 register operands or 3 register operands
6556 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6557 VexW0 or VexW1. The destination must be either XMM, YMM or
6559 2. 4 operands: 4 register operands or 3 register operands
6560 plus 1 memory operand, VexXDS, and VexImmExt */
6561 gas_assert ((i.reg_operands == 4
6562 || (i.reg_operands == 3 && i.mem_operands == 1))
6563 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6564 && (i.tm.opcode_modifier.veximmext
6565 || (i.imm_operands == 1
6566 && i.types[0].bitfield.vec_imm4
6567 && (i.tm.opcode_modifier.vexw == VEXW0
6568 || i.tm.opcode_modifier.vexw == VEXW1)
6569 && i.tm.operand_types[dest].bitfield.regsimd)));
6571 if (i.imm_operands == 0)
6573 /* When there is no immediate operand, generate an 8bit
6574 immediate operand to encode the first operand. */
6575 exp = &im_expressions[i.imm_operands++];
6576 i.op[i.operands].imms = exp;
6577 i.types[i.operands] = imm8;
6579 /* If VexW1 is set, the first operand is the source and
6580 the second operand is encoded in the immediate operand. */
6581 if (i.tm.opcode_modifier.vexw == VEXW1)
6592 /* FMA swaps REG and NDS. */
6593 if (i.tm.cpu_flags.bitfield.cpufma)
6601 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6602 exp->X_op = O_constant;
6603 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6604 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6608 unsigned int imm_slot;
6610 if (i.tm.opcode_modifier.vexw == VEXW0)
6612 /* If VexW0 is set, the third operand is the source and
6613 the second operand is encoded in the immediate
6620 /* VexW1 is set, the second operand is the source and
6621 the third operand is encoded in the immediate
6627 if (i.tm.opcode_modifier.immext)
6629 /* When ImmExt is set, the immediate byte is the last
6631 imm_slot = i.operands - 1;
6639 /* Turn on Imm8 so that output_imm will generate it. */
6640 i.types[imm_slot].bitfield.imm8 = 1;
6643 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6644 i.op[imm_slot].imms->X_add_number
6645 |= register_number (i.op[reg_slot].regs) << 4;
6646 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6649 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6650 i.vex.register_specifier = i.op[nds].regs;
6655 /* i.reg_operands MUST be the number of real register operands;
6656 implicit registers do not count. If there are 3 register
6657 operands, it must be a instruction with VexNDS. For a
6658 instruction with VexNDD, the destination register is encoded
6659 in VEX prefix. If there are 4 register operands, it must be
6660 a instruction with VEX prefix and 3 sources. */
6661 if (i.mem_operands == 0
6662 && ((i.reg_operands == 2
6663 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6664 || (i.reg_operands == 3
6665 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6666 || (i.reg_operands == 4 && vex_3_sources)))
6674 /* When there are 3 operands, one of them may be immediate,
6675 which may be the first or the last operand. Otherwise,
6676 the first operand must be shift count register (cl) or it
6677 is an instruction with VexNDS. */
6678 gas_assert (i.imm_operands == 1
6679 || (i.imm_operands == 0
6680 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6681 || i.types[0].bitfield.shiftcount)));
6682 if (operand_type_check (i.types[0], imm)
6683 || i.types[0].bitfield.shiftcount)
6689 /* When there are 4 operands, the first two must be 8bit
6690 immediate operands. The source operand will be the 3rd
6693 For instructions with VexNDS, if the first operand
6694 an imm8, the source operand is the 2nd one. If the last
6695 operand is imm8, the source operand is the first one. */
6696 gas_assert ((i.imm_operands == 2
6697 && i.types[0].bitfield.imm8
6698 && i.types[1].bitfield.imm8)
6699 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6700 && i.imm_operands == 1
6701 && (i.types[0].bitfield.imm8
6702 || i.types[i.operands - 1].bitfield.imm8
6704 if (i.imm_operands == 2)
6708 if (i.types[0].bitfield.imm8)
6715 if (is_evex_encoding (&i.tm))
6717 /* For EVEX instructions, when there are 5 operands, the
6718 first one must be immediate operand. If the second one
6719 is immediate operand, the source operand is the 3th
6720 one. If the last one is immediate operand, the source
6721 operand is the 2nd one. */
6722 gas_assert (i.imm_operands == 2
6723 && i.tm.opcode_modifier.sae
6724 && operand_type_check (i.types[0], imm));
6725 if (operand_type_check (i.types[1], imm))
6727 else if (operand_type_check (i.types[4], imm))
6741 /* RC/SAE operand could be between DEST and SRC. That happens
6742 when one operand is GPR and the other one is XMM/YMM/ZMM
6744 if (i.rounding && i.rounding->operand == (int) dest)
6747 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6749 /* For instructions with VexNDS, the register-only source
6750 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6751 register. It is encoded in VEX prefix. We need to
6752 clear RegMem bit before calling operand_type_equal. */
6754 i386_operand_type op;
6757 /* Check register-only source operand when two source
6758 operands are swapped. */
6759 if (!i.tm.operand_types[source].bitfield.baseindex
6760 && i.tm.operand_types[dest].bitfield.baseindex)
6768 op = i.tm.operand_types[vvvv];
6769 op.bitfield.regmem = 0;
6770 if ((dest + 1) >= i.operands
6771 || ((!op.bitfield.reg
6772 || (!op.bitfield.dword && !op.bitfield.qword))
6773 && !op.bitfield.regsimd
6774 && !operand_type_equal (&op, ®mask)))
6776 i.vex.register_specifier = i.op[vvvv].regs;
6782 /* One of the register operands will be encoded in the i.tm.reg
6783 field, the other in the combined i.tm.mode and i.tm.regmem
6784 fields. If no form of this instruction supports a memory
6785 destination operand, then we assume the source operand may
6786 sometimes be a memory operand and so we need to store the
6787 destination in the i.rm.reg field. */
6788 if (!i.tm.operand_types[dest].bitfield.regmem
6789 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6791 i.rm.reg = i.op[dest].regs->reg_num;
6792 i.rm.regmem = i.op[source].regs->reg_num;
6793 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6795 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6797 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6799 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6804 i.rm.reg = i.op[source].regs->reg_num;
6805 i.rm.regmem = i.op[dest].regs->reg_num;
6806 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6808 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6810 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6812 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6815 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6817 if (!i.types[0].bitfield.control
6818 && !i.types[1].bitfield.control)
6820 i.rex &= ~(REX_R | REX_B);
6821 add_prefix (LOCK_PREFIX_OPCODE);
6825 { /* If it's not 2 reg operands... */
6830 unsigned int fake_zero_displacement = 0;
6833 for (op = 0; op < i.operands; op++)
6834 if (operand_type_check (i.types[op], anymem))
6836 gas_assert (op < i.operands);
6838 if (i.tm.opcode_modifier.vecsib)
6840 if (i.index_reg->reg_num == RegEiz
6841 || i.index_reg->reg_num == RegRiz)
6844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6847 i.sib.base = NO_BASE_REGISTER;
6848 i.sib.scale = i.log2_scale_factor;
6849 i.types[op].bitfield.disp8 = 0;
6850 i.types[op].bitfield.disp16 = 0;
6851 i.types[op].bitfield.disp64 = 0;
6852 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6854 /* Must be 32 bit */
6855 i.types[op].bitfield.disp32 = 1;
6856 i.types[op].bitfield.disp32s = 0;
6860 i.types[op].bitfield.disp32 = 0;
6861 i.types[op].bitfield.disp32s = 1;
6864 i.sib.index = i.index_reg->reg_num;
6865 if ((i.index_reg->reg_flags & RegRex) != 0)
6867 if ((i.index_reg->reg_flags & RegVRex) != 0)
6873 if (i.base_reg == 0)
6876 if (!i.disp_operands)
6877 fake_zero_displacement = 1;
6878 if (i.index_reg == 0)
6880 i386_operand_type newdisp;
6882 gas_assert (!i.tm.opcode_modifier.vecsib);
6883 /* Operand is just <disp> */
6884 if (flag_code == CODE_64BIT)
6886 /* 64bit mode overwrites the 32bit absolute
6887 addressing by RIP relative addressing and
6888 absolute addressing is encoded by one of the
6889 redundant SIB forms. */
6890 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6891 i.sib.base = NO_BASE_REGISTER;
6892 i.sib.index = NO_INDEX_REGISTER;
6893 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6895 else if ((flag_code == CODE_16BIT)
6896 ^ (i.prefix[ADDR_PREFIX] != 0))
6898 i.rm.regmem = NO_BASE_REGISTER_16;
6903 i.rm.regmem = NO_BASE_REGISTER;
6906 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6907 i.types[op] = operand_type_or (i.types[op], newdisp);
6909 else if (!i.tm.opcode_modifier.vecsib)
6911 /* !i.base_reg && i.index_reg */
6912 if (i.index_reg->reg_num == RegEiz
6913 || i.index_reg->reg_num == RegRiz)
6914 i.sib.index = NO_INDEX_REGISTER;
6916 i.sib.index = i.index_reg->reg_num;
6917 i.sib.base = NO_BASE_REGISTER;
6918 i.sib.scale = i.log2_scale_factor;
6919 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6920 i.types[op].bitfield.disp8 = 0;
6921 i.types[op].bitfield.disp16 = 0;
6922 i.types[op].bitfield.disp64 = 0;
6923 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6925 /* Must be 32 bit */
6926 i.types[op].bitfield.disp32 = 1;
6927 i.types[op].bitfield.disp32s = 0;
6931 i.types[op].bitfield.disp32 = 0;
6932 i.types[op].bitfield.disp32s = 1;
6934 if ((i.index_reg->reg_flags & RegRex) != 0)
6938 /* RIP addressing for 64bit mode. */
6939 else if (i.base_reg->reg_num == RegRip ||
6940 i.base_reg->reg_num == RegEip)
6942 gas_assert (!i.tm.opcode_modifier.vecsib);
6943 i.rm.regmem = NO_BASE_REGISTER;
6944 i.types[op].bitfield.disp8 = 0;
6945 i.types[op].bitfield.disp16 = 0;
6946 i.types[op].bitfield.disp32 = 0;
6947 i.types[op].bitfield.disp32s = 1;
6948 i.types[op].bitfield.disp64 = 0;
6949 i.flags[op] |= Operand_PCrel;
6950 if (! i.disp_operands)
6951 fake_zero_displacement = 1;
6953 else if (i.base_reg->reg_type.bitfield.word)
6955 gas_assert (!i.tm.opcode_modifier.vecsib);
6956 switch (i.base_reg->reg_num)
6959 if (i.index_reg == 0)
6961 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6962 i.rm.regmem = i.index_reg->reg_num - 6;
6966 if (i.index_reg == 0)
6969 if (operand_type_check (i.types[op], disp) == 0)
6971 /* fake (%bp) into 0(%bp) */
6972 i.types[op].bitfield.disp8 = 1;
6973 fake_zero_displacement = 1;
6976 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6977 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6979 default: /* (%si) -> 4 or (%di) -> 5 */
6980 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6982 i.rm.mode = mode_from_disp_size (i.types[op]);
6984 else /* i.base_reg and 32/64 bit mode */
6986 if (flag_code == CODE_64BIT
6987 && operand_type_check (i.types[op], disp))
6989 i.types[op].bitfield.disp16 = 0;
6990 i.types[op].bitfield.disp64 = 0;
6991 if (i.prefix[ADDR_PREFIX] == 0)
6993 i.types[op].bitfield.disp32 = 0;
6994 i.types[op].bitfield.disp32s = 1;
6998 i.types[op].bitfield.disp32 = 1;
6999 i.types[op].bitfield.disp32s = 0;
7003 if (!i.tm.opcode_modifier.vecsib)
7004 i.rm.regmem = i.base_reg->reg_num;
7005 if ((i.base_reg->reg_flags & RegRex) != 0)
7007 i.sib.base = i.base_reg->reg_num;
7008 /* x86-64 ignores REX prefix bit here to avoid decoder
7010 if (!(i.base_reg->reg_flags & RegRex)
7011 && (i.base_reg->reg_num == EBP_REG_NUM
7012 || i.base_reg->reg_num == ESP_REG_NUM))
7014 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7016 fake_zero_displacement = 1;
7017 i.types[op].bitfield.disp8 = 1;
7019 i.sib.scale = i.log2_scale_factor;
7020 if (i.index_reg == 0)
7022 gas_assert (!i.tm.opcode_modifier.vecsib);
7023 /* <disp>(%esp) becomes two byte modrm with no index
7024 register. We've already stored the code for esp
7025 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7026 Any base register besides %esp will not use the
7027 extra modrm byte. */
7028 i.sib.index = NO_INDEX_REGISTER;
7030 else if (!i.tm.opcode_modifier.vecsib)
7032 if (i.index_reg->reg_num == RegEiz
7033 || i.index_reg->reg_num == RegRiz)
7034 i.sib.index = NO_INDEX_REGISTER;
7036 i.sib.index = i.index_reg->reg_num;
7037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7038 if ((i.index_reg->reg_flags & RegRex) != 0)
7043 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7044 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7048 if (!fake_zero_displacement
7052 fake_zero_displacement = 1;
7053 if (i.disp_encoding == disp_encoding_8bit)
7054 i.types[op].bitfield.disp8 = 1;
7056 i.types[op].bitfield.disp32 = 1;
7058 i.rm.mode = mode_from_disp_size (i.types[op]);
7062 if (fake_zero_displacement)
7064 /* Fakes a zero displacement assuming that i.types[op]
7065 holds the correct displacement size. */
7068 gas_assert (i.op[op].disps == 0);
7069 exp = &disp_expressions[i.disp_operands++];
7070 i.op[op].disps = exp;
7071 exp->X_op = O_constant;
7072 exp->X_add_number = 0;
7073 exp->X_add_symbol = (symbolS *) 0;
7074 exp->X_op_symbol = (symbolS *) 0;
7082 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7084 if (operand_type_check (i.types[0], imm))
7085 i.vex.register_specifier = NULL;
7088 /* VEX.vvvv encodes one of the sources when the first
7089 operand is not an immediate. */
7090 if (i.tm.opcode_modifier.vexw == VEXW0)
7091 i.vex.register_specifier = i.op[0].regs;
7093 i.vex.register_specifier = i.op[1].regs;
7096 /* Destination is a XMM register encoded in the ModRM.reg
7098 i.rm.reg = i.op[2].regs->reg_num;
7099 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7102 /* ModRM.rm and VEX.B encodes the other source. */
7103 if (!i.mem_operands)
7107 if (i.tm.opcode_modifier.vexw == VEXW0)
7108 i.rm.regmem = i.op[1].regs->reg_num;
7110 i.rm.regmem = i.op[0].regs->reg_num;
7112 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7116 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7118 i.vex.register_specifier = i.op[2].regs;
7119 if (!i.mem_operands)
7122 i.rm.regmem = i.op[1].regs->reg_num;
7123 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7127 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7128 (if any) based on i.tm.extension_opcode. Again, we must be
7129 careful to make sure that segment/control/debug/test/MMX
7130 registers are coded into the i.rm.reg field. */
7131 else if (i.reg_operands)
7134 unsigned int vex_reg = ~0;
7136 for (op = 0; op < i.operands; op++)
7137 if (i.types[op].bitfield.reg
7138 || i.types[op].bitfield.regmmx
7139 || i.types[op].bitfield.regsimd
7140 || i.types[op].bitfield.regbnd
7141 || i.types[op].bitfield.regmask
7142 || i.types[op].bitfield.sreg2
7143 || i.types[op].bitfield.sreg3
7144 || i.types[op].bitfield.control
7145 || i.types[op].bitfield.debug
7146 || i.types[op].bitfield.test)
7151 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7153 /* For instructions with VexNDS, the register-only
7154 source operand is encoded in VEX prefix. */
7155 gas_assert (mem != (unsigned int) ~0);
7160 gas_assert (op < i.operands);
7164 /* Check register-only source operand when two source
7165 operands are swapped. */
7166 if (!i.tm.operand_types[op].bitfield.baseindex
7167 && i.tm.operand_types[op + 1].bitfield.baseindex)
7171 gas_assert (mem == (vex_reg + 1)
7172 && op < i.operands);
7177 gas_assert (vex_reg < i.operands);
7181 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7183 /* For instructions with VexNDD, the register destination
7184 is encoded in VEX prefix. */
7185 if (i.mem_operands == 0)
7187 /* There is no memory operand. */
7188 gas_assert ((op + 2) == i.operands);
7193 /* There are only 2 non-immediate operands. */
7194 gas_assert (op < i.imm_operands + 2
7195 && i.operands == i.imm_operands + 2);
7196 vex_reg = i.imm_operands + 1;
7200 gas_assert (op < i.operands);
7202 if (vex_reg != (unsigned int) ~0)
7204 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7206 if ((!type->bitfield.reg
7207 || (!type->bitfield.dword && !type->bitfield.qword))
7208 && !type->bitfield.regsimd
7209 && !operand_type_equal (type, ®mask))
7212 i.vex.register_specifier = i.op[vex_reg].regs;
7215 /* Don't set OP operand twice. */
7218 /* If there is an extension opcode to put here, the
7219 register number must be put into the regmem field. */
7220 if (i.tm.extension_opcode != None)
7222 i.rm.regmem = i.op[op].regs->reg_num;
7223 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7225 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7230 i.rm.reg = i.op[op].regs->reg_num;
7231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7233 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7238 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7239 must set it to 3 to indicate this is a register operand
7240 in the regmem field. */
7241 if (!i.mem_operands)
7245 /* Fill in i.rm.reg field with extension opcode (if any). */
7246 if (i.tm.extension_opcode != None)
7247 i.rm.reg = i.tm.extension_opcode;
7253 output_branch (void)
7259 relax_substateT subtype;
7263 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7264 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7267 if (i.prefix[DATA_PREFIX] != 0)
7273 /* Pentium4 branch hints. */
7274 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7275 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7280 if (i.prefix[REX_PREFIX] != 0)
7286 /* BND prefixed jump. */
7287 if (i.prefix[BND_PREFIX] != 0)
7289 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7293 if (i.prefixes != 0 && !intel_syntax)
7294 as_warn (_("skipping prefixes on this instruction"));
7296 /* It's always a symbol; End frag & setup for relax.
7297 Make sure there is enough room in this frag for the largest
7298 instruction we may generate in md_convert_frag. This is 2
7299 bytes for the opcode and room for the prefix and largest
7301 frag_grow (prefix + 2 + 4);
7302 /* Prefix and 1 opcode byte go in fr_fix. */
7303 p = frag_more (prefix + 1);
7304 if (i.prefix[DATA_PREFIX] != 0)
7305 *p++ = DATA_PREFIX_OPCODE;
7306 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7307 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7308 *p++ = i.prefix[SEG_PREFIX];
7309 if (i.prefix[REX_PREFIX] != 0)
7310 *p++ = i.prefix[REX_PREFIX];
7311 *p = i.tm.base_opcode;
7313 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7314 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7315 else if (cpu_arch_flags.bitfield.cpui386)
7316 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7318 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7321 sym = i.op[0].disps->X_add_symbol;
7322 off = i.op[0].disps->X_add_number;
7324 if (i.op[0].disps->X_op != O_constant
7325 && i.op[0].disps->X_op != O_symbol)
7327 /* Handle complex expressions. */
7328 sym = make_expr_symbol (i.op[0].disps);
7332 /* 1 possible extra opcode + 4 byte displacement go in var part.
7333 Pass reloc in fr_var. */
7334 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7338 /* Return TRUE iff PLT32 relocation should be used for branching to
7342 need_plt32_p (symbolS *s)
7344 /* PLT32 relocation is ELF only. */
7348 /* Since there is no need to prepare for PLT branch on x86-64, we
7349 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7350 be used as a marker for 32-bit PC-relative branches. */
7354 /* Weak or undefined symbol need PLT32 relocation. */
7355 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7358 /* Non-global symbol doesn't need PLT32 relocation. */
7359 if (! S_IS_EXTERNAL (s))
7362 /* Other global symbols need PLT32 relocation. NB: Symbol with
7363 non-default visibilities are treated as normal global symbol
7364 so that PLT32 relocation can be used as a marker for 32-bit
7365 PC-relative branches. It is useful for linker relaxation. */
7376 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7378 if (i.tm.opcode_modifier.jumpbyte)
7380 /* This is a loop or jecxz type instruction. */
7382 if (i.prefix[ADDR_PREFIX] != 0)
7384 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7387 /* Pentium4 branch hints. */
7388 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7389 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7391 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7400 if (flag_code == CODE_16BIT)
7403 if (i.prefix[DATA_PREFIX] != 0)
7405 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7415 if (i.prefix[REX_PREFIX] != 0)
7417 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7421 /* BND prefixed jump. */
7422 if (i.prefix[BND_PREFIX] != 0)
7424 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7428 if (i.prefixes != 0 && !intel_syntax)
7429 as_warn (_("skipping prefixes on this instruction"));
7431 p = frag_more (i.tm.opcode_length + size);
7432 switch (i.tm.opcode_length)
7435 *p++ = i.tm.base_opcode >> 8;
7438 *p++ = i.tm.base_opcode;
7444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7446 && jump_reloc == NO_RELOC
7447 && need_plt32_p (i.op[0].disps->X_add_symbol))
7448 jump_reloc = BFD_RELOC_X86_64_PLT32;
7451 jump_reloc = reloc (size, 1, 1, jump_reloc);
7453 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7454 i.op[0].disps, 1, jump_reloc);
7456 /* All jumps handled here are signed, but don't use a signed limit
7457 check for 32 and 16 bit jumps as we want to allow wrap around at
7458 4G and 64k respectively. */
7460 fixP->fx_signed = 1;
7464 output_interseg_jump (void)
7472 if (flag_code == CODE_16BIT)
7476 if (i.prefix[DATA_PREFIX] != 0)
7482 if (i.prefix[REX_PREFIX] != 0)
7492 if (i.prefixes != 0 && !intel_syntax)
7493 as_warn (_("skipping prefixes on this instruction"));
7495 /* 1 opcode; 2 segment; offset */
7496 p = frag_more (prefix + 1 + 2 + size);
7498 if (i.prefix[DATA_PREFIX] != 0)
7499 *p++ = DATA_PREFIX_OPCODE;
7501 if (i.prefix[REX_PREFIX] != 0)
7502 *p++ = i.prefix[REX_PREFIX];
7504 *p++ = i.tm.base_opcode;
7505 if (i.op[1].imms->X_op == O_constant)
7507 offsetT n = i.op[1].imms->X_add_number;
7510 && !fits_in_unsigned_word (n)
7511 && !fits_in_signed_word (n))
7513 as_bad (_("16-bit jump out of range"));
7516 md_number_to_chars (p, n, size);
7519 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7520 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7521 if (i.op[0].imms->X_op != O_constant)
7522 as_bad (_("can't handle non absolute segment in `%s'"),
7524 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7530 fragS *insn_start_frag;
7531 offsetT insn_start_off;
7533 /* Tie dwarf2 debug info to the address at the start of the insn.
7534 We can't do this after the insn has been output as the current
7535 frag may have been closed off. eg. by frag_var. */
7536 dwarf2_emit_insn (0);
7538 insn_start_frag = frag_now;
7539 insn_start_off = frag_now_fix ();
7542 if (i.tm.opcode_modifier.jump)
7544 else if (i.tm.opcode_modifier.jumpbyte
7545 || i.tm.opcode_modifier.jumpdword)
7547 else if (i.tm.opcode_modifier.jumpintersegment)
7548 output_interseg_jump ();
7551 /* Output normal instructions here. */
7555 unsigned int prefix;
7558 && i.tm.base_opcode == 0xfae
7560 && i.imm_operands == 1
7561 && (i.op[0].imms->X_add_number == 0xe8
7562 || i.op[0].imms->X_add_number == 0xf0
7563 || i.op[0].imms->X_add_number == 0xf8))
7565 /* Encode lfence, mfence, and sfence as
7566 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7567 offsetT val = 0x240483f0ULL;
7569 md_number_to_chars (p, val, 5);
7573 /* Some processors fail on LOCK prefix. This options makes
7574 assembler ignore LOCK prefix and serves as a workaround. */
7575 if (omit_lock_prefix)
7577 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7579 i.prefix[LOCK_PREFIX] = 0;
7582 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7583 don't need the explicit prefix. */
7584 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7586 switch (i.tm.opcode_length)
7589 if (i.tm.base_opcode & 0xff000000)
7591 prefix = (i.tm.base_opcode >> 24) & 0xff;
7596 if ((i.tm.base_opcode & 0xff0000) != 0)
7598 prefix = (i.tm.base_opcode >> 16) & 0xff;
7599 if (i.tm.cpu_flags.bitfield.cpupadlock)
7602 if (prefix != REPE_PREFIX_OPCODE
7603 || (i.prefix[REP_PREFIX]
7604 != REPE_PREFIX_OPCODE))
7605 add_prefix (prefix);
7608 add_prefix (prefix);
7614 /* Check for pseudo prefixes. */
7615 as_bad_where (insn_start_frag->fr_file,
7616 insn_start_frag->fr_line,
7617 _("pseudo prefix without instruction"));
7623 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7624 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7625 R_X86_64_GOTTPOFF relocation so that linker can safely
7626 perform IE->LE optimization. */
7627 if (x86_elf_abi == X86_64_X32_ABI
7629 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7630 && i.prefix[REX_PREFIX] == 0)
7631 add_prefix (REX_OPCODE);
7634 /* The prefix bytes. */
7635 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7637 FRAG_APPEND_1_CHAR (*q);
7641 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7646 /* REX byte is encoded in VEX prefix. */
7650 FRAG_APPEND_1_CHAR (*q);
7653 /* There should be no other prefixes for instructions
7658 /* For EVEX instructions i.vrex should become 0 after
7659 build_evex_prefix. For VEX instructions upper 16 registers
7660 aren't available, so VREX should be 0. */
7663 /* Now the VEX prefix. */
7664 p = frag_more (i.vex.length);
7665 for (j = 0; j < i.vex.length; j++)
7666 p[j] = i.vex.bytes[j];
7669 /* Now the opcode; be careful about word order here! */
7670 if (i.tm.opcode_length == 1)
7672 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7676 switch (i.tm.opcode_length)
7680 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7681 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7685 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7695 /* Put out high byte first: can't use md_number_to_chars! */
7696 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7697 *p = i.tm.base_opcode & 0xff;
7700 /* Now the modrm byte and sib byte (if present). */
7701 if (i.tm.opcode_modifier.modrm)
7703 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7706 /* If i.rm.regmem == ESP (4)
7707 && i.rm.mode != (Register mode)
7709 ==> need second modrm byte. */
7710 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7712 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7713 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7715 | i.sib.scale << 6));
7718 if (i.disp_operands)
7719 output_disp (insn_start_frag, insn_start_off);
7722 output_imm (insn_start_frag, insn_start_off);
7728 pi ("" /*line*/, &i);
7730 #endif /* DEBUG386 */
7733 /* Return the size of the displacement operand N. */
7736 disp_size (unsigned int n)
7740 if (i.types[n].bitfield.disp64)
7742 else if (i.types[n].bitfield.disp8)
7744 else if (i.types[n].bitfield.disp16)
7749 /* Return the size of the immediate operand N. */
7752 imm_size (unsigned int n)
7755 if (i.types[n].bitfield.imm64)
7757 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7759 else if (i.types[n].bitfield.imm16)
7765 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7770 for (n = 0; n < i.operands; n++)
7772 if (operand_type_check (i.types[n], disp))
7774 if (i.op[n].disps->X_op == O_constant)
7776 int size = disp_size (n);
7777 offsetT val = i.op[n].disps->X_add_number;
7779 val = offset_in_range (val >> i.memshift, size);
7780 p = frag_more (size);
7781 md_number_to_chars (p, val, size);
7785 enum bfd_reloc_code_real reloc_type;
7786 int size = disp_size (n);
7787 int sign = i.types[n].bitfield.disp32s;
7788 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7791 /* We can't have 8 bit displacement here. */
7792 gas_assert (!i.types[n].bitfield.disp8);
7794 /* The PC relative address is computed relative
7795 to the instruction boundary, so in case immediate
7796 fields follows, we need to adjust the value. */
7797 if (pcrel && i.imm_operands)
7802 for (n1 = 0; n1 < i.operands; n1++)
7803 if (operand_type_check (i.types[n1], imm))
7805 /* Only one immediate is allowed for PC
7806 relative address. */
7807 gas_assert (sz == 0);
7809 i.op[n].disps->X_add_number -= sz;
7811 /* We should find the immediate. */
7812 gas_assert (sz != 0);
7815 p = frag_more (size);
7816 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7818 && GOT_symbol == i.op[n].disps->X_add_symbol
7819 && (((reloc_type == BFD_RELOC_32
7820 || reloc_type == BFD_RELOC_X86_64_32S
7821 || (reloc_type == BFD_RELOC_64
7823 && (i.op[n].disps->X_op == O_symbol
7824 || (i.op[n].disps->X_op == O_add
7825 && ((symbol_get_value_expression
7826 (i.op[n].disps->X_op_symbol)->X_op)
7828 || reloc_type == BFD_RELOC_32_PCREL))
7832 if (insn_start_frag == frag_now)
7833 add = (p - frag_now->fr_literal) - insn_start_off;
7838 add = insn_start_frag->fr_fix - insn_start_off;
7839 for (fr = insn_start_frag->fr_next;
7840 fr && fr != frag_now; fr = fr->fr_next)
7842 add += p - frag_now->fr_literal;
7847 reloc_type = BFD_RELOC_386_GOTPC;
7848 i.op[n].imms->X_add_number += add;
7850 else if (reloc_type == BFD_RELOC_64)
7851 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7853 /* Don't do the adjustment for x86-64, as there
7854 the pcrel addressing is relative to the _next_
7855 insn, and that is taken care of in other code. */
7856 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7859 size, i.op[n].disps, pcrel,
7861 /* Check for "call/jmp *mem", "mov mem, %reg",
7862 "test %reg, mem" and "binop mem, %reg" where binop
7863 is one of adc, add, and, cmp, or, sbb, sub, xor
7864 instructions. Always generate R_386_GOT32X for
7865 "sym*GOT" operand in 32-bit mode. */
7866 if ((generate_relax_relocations
7869 && i.rm.regmem == 5))
7871 || (i.rm.mode == 0 && i.rm.regmem == 5))
7872 && ((i.operands == 1
7873 && i.tm.base_opcode == 0xff
7874 && (i.rm.reg == 2 || i.rm.reg == 4))
7876 && (i.tm.base_opcode == 0x8b
7877 || i.tm.base_opcode == 0x85
7878 || (i.tm.base_opcode & 0xc7) == 0x03))))
7882 fixP->fx_tcbit = i.rex != 0;
7884 && (i.base_reg->reg_num == RegRip
7885 || i.base_reg->reg_num == RegEip))
7886 fixP->fx_tcbit2 = 1;
7889 fixP->fx_tcbit2 = 1;
7897 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7902 for (n = 0; n < i.operands; n++)
7904 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7905 if (i.rounding && (int) n == i.rounding->operand)
7908 if (operand_type_check (i.types[n], imm))
7910 if (i.op[n].imms->X_op == O_constant)
7912 int size = imm_size (n);
7915 val = offset_in_range (i.op[n].imms->X_add_number,
7917 p = frag_more (size);
7918 md_number_to_chars (p, val, size);
7922 /* Not absolute_section.
7923 Need a 32-bit fixup (don't support 8bit
7924 non-absolute imms). Try to support other
7926 enum bfd_reloc_code_real reloc_type;
7927 int size = imm_size (n);
7930 if (i.types[n].bitfield.imm32s
7931 && (i.suffix == QWORD_MNEM_SUFFIX
7932 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7937 p = frag_more (size);
7938 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7940 /* This is tough to explain. We end up with this one if we
7941 * have operands that look like
7942 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7943 * obtain the absolute address of the GOT, and it is strongly
7944 * preferable from a performance point of view to avoid using
7945 * a runtime relocation for this. The actual sequence of
7946 * instructions often look something like:
7951 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7953 * The call and pop essentially return the absolute address
7954 * of the label .L66 and store it in %ebx. The linker itself
7955 * will ultimately change the first operand of the addl so
7956 * that %ebx points to the GOT, but to keep things simple, the
7957 * .o file must have this operand set so that it generates not
7958 * the absolute address of .L66, but the absolute address of
7959 * itself. This allows the linker itself simply treat a GOTPC
7960 * relocation as asking for a pcrel offset to the GOT to be
7961 * added in, and the addend of the relocation is stored in the
7962 * operand field for the instruction itself.
7964 * Our job here is to fix the operand so that it would add
7965 * the correct offset so that %ebx would point to itself. The
7966 * thing that is tricky is that .-.L66 will point to the
7967 * beginning of the instruction, so we need to further modify
7968 * the operand so that it will point to itself. There are
7969 * other cases where you have something like:
7971 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7973 * and here no correction would be required. Internally in
7974 * the assembler we treat operands of this form as not being
7975 * pcrel since the '.' is explicitly mentioned, and I wonder
7976 * whether it would simplify matters to do it this way. Who
7977 * knows. In earlier versions of the PIC patches, the
7978 * pcrel_adjust field was used to store the correction, but
7979 * since the expression is not pcrel, I felt it would be
7980 * confusing to do it this way. */
7982 if ((reloc_type == BFD_RELOC_32
7983 || reloc_type == BFD_RELOC_X86_64_32S
7984 || reloc_type == BFD_RELOC_64)
7986 && GOT_symbol == i.op[n].imms->X_add_symbol
7987 && (i.op[n].imms->X_op == O_symbol
7988 || (i.op[n].imms->X_op == O_add
7989 && ((symbol_get_value_expression
7990 (i.op[n].imms->X_op_symbol)->X_op)
7995 if (insn_start_frag == frag_now)
7996 add = (p - frag_now->fr_literal) - insn_start_off;
8001 add = insn_start_frag->fr_fix - insn_start_off;
8002 for (fr = insn_start_frag->fr_next;
8003 fr && fr != frag_now; fr = fr->fr_next)
8005 add += p - frag_now->fr_literal;
8009 reloc_type = BFD_RELOC_386_GOTPC;
8011 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8013 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8014 i.op[n].imms->X_add_number += add;
8016 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8017 i.op[n].imms, 0, reloc_type);
8023 /* x86_cons_fix_new is called via the expression parsing code when a
8024 reloc is needed. We use this hook to get the correct .got reloc. */
8025 static int cons_sign = -1;
8028 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8029 expressionS *exp, bfd_reloc_code_real_type r)
8031 r = reloc (len, 0, cons_sign, r);
8034 if (exp->X_op == O_secrel)
8036 exp->X_op = O_symbol;
8037 r = BFD_RELOC_32_SECREL;
8041 fix_new_exp (frag, off, len, exp, 0, r);
8044 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8045 purpose of the `.dc.a' internal pseudo-op. */
8048 x86_address_bytes (void)
8050 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8052 return stdoutput->arch_info->bits_per_address / 8;
8055 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8057 # define lex_got(reloc, adjust, types) NULL
8059 /* Parse operands of the form
8060 <symbol>@GOTOFF+<nnn>
8061 and similar .plt or .got references.
8063 If we find one, set up the correct relocation in RELOC and copy the
8064 input string, minus the `@GOTOFF' into a malloc'd buffer for
8065 parsing by the calling routine. Return this buffer, and if ADJUST
8066 is non-null set it to the length of the string we removed from the
8067 input line. Otherwise return NULL. */
8069 lex_got (enum bfd_reloc_code_real *rel,
8071 i386_operand_type *types)
8073 /* Some of the relocations depend on the size of what field is to
8074 be relocated. But in our callers i386_immediate and i386_displacement
8075 we don't yet know the operand size (this will be set by insn
8076 matching). Hence we record the word32 relocation here,
8077 and adjust the reloc according to the real size in reloc(). */
8078 static const struct {
8081 const enum bfd_reloc_code_real rel[2];
8082 const i386_operand_type types64;
8084 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8085 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8087 OPERAND_TYPE_IMM32_64 },
8089 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8090 BFD_RELOC_X86_64_PLTOFF64 },
8091 OPERAND_TYPE_IMM64 },
8092 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8093 BFD_RELOC_X86_64_PLT32 },
8094 OPERAND_TYPE_IMM32_32S_DISP32 },
8095 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8096 BFD_RELOC_X86_64_GOTPLT64 },
8097 OPERAND_TYPE_IMM64_DISP64 },
8098 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8099 BFD_RELOC_X86_64_GOTOFF64 },
8100 OPERAND_TYPE_IMM64_DISP64 },
8101 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8102 BFD_RELOC_X86_64_GOTPCREL },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8105 BFD_RELOC_X86_64_TLSGD },
8106 OPERAND_TYPE_IMM32_32S_DISP32 },
8107 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8108 _dummy_first_bfd_reloc_code_real },
8109 OPERAND_TYPE_NONE },
8110 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8111 BFD_RELOC_X86_64_TLSLD },
8112 OPERAND_TYPE_IMM32_32S_DISP32 },
8113 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8114 BFD_RELOC_X86_64_GOTTPOFF },
8115 OPERAND_TYPE_IMM32_32S_DISP32 },
8116 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8117 BFD_RELOC_X86_64_TPOFF32 },
8118 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8119 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8120 _dummy_first_bfd_reloc_code_real },
8121 OPERAND_TYPE_NONE },
8122 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8123 BFD_RELOC_X86_64_DTPOFF32 },
8124 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8125 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8126 _dummy_first_bfd_reloc_code_real },
8127 OPERAND_TYPE_NONE },
8128 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8129 _dummy_first_bfd_reloc_code_real },
8130 OPERAND_TYPE_NONE },
8131 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8132 BFD_RELOC_X86_64_GOT32 },
8133 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8134 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8135 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8136 OPERAND_TYPE_IMM32_32S_DISP32 },
8137 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8138 BFD_RELOC_X86_64_TLSDESC_CALL },
8139 OPERAND_TYPE_IMM32_32S_DISP32 },
8144 #if defined (OBJ_MAYBE_ELF)
8149 for (cp = input_line_pointer; *cp != '@'; cp++)
8150 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8153 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8155 int len = gotrel[j].len;
8156 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8158 if (gotrel[j].rel[object_64bit] != 0)
8161 char *tmpbuf, *past_reloc;
8163 *rel = gotrel[j].rel[object_64bit];
8167 if (flag_code != CODE_64BIT)
8169 types->bitfield.imm32 = 1;
8170 types->bitfield.disp32 = 1;
8173 *types = gotrel[j].types64;
8176 if (j != 0 && GOT_symbol == NULL)
8177 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8179 /* The length of the first part of our input line. */
8180 first = cp - input_line_pointer;
8182 /* The second part goes from after the reloc token until
8183 (and including) an end_of_line char or comma. */
8184 past_reloc = cp + 1 + len;
8186 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8188 second = cp + 1 - past_reloc;
8190 /* Allocate and copy string. The trailing NUL shouldn't
8191 be necessary, but be safe. */
8192 tmpbuf = XNEWVEC (char, first + second + 2);
8193 memcpy (tmpbuf, input_line_pointer, first);
8194 if (second != 0 && *past_reloc != ' ')
8195 /* Replace the relocation token with ' ', so that
8196 errors like foo@GOTOFF1 will be detected. */
8197 tmpbuf[first++] = ' ';
8199 /* Increment length by 1 if the relocation token is
8204 memcpy (tmpbuf + first, past_reloc, second);
8205 tmpbuf[first + second] = '\0';
8209 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8210 gotrel[j].str, 1 << (5 + object_64bit));
8215 /* Might be a symbol version string. Don't as_bad here. */
8224 /* Parse operands of the form
8225 <symbol>@SECREL32+<nnn>
8227 If we find one, set up the correct relocation in RELOC and copy the
8228 input string, minus the `@SECREL32' into a malloc'd buffer for
8229 parsing by the calling routine. Return this buffer, and if ADJUST
8230 is non-null set it to the length of the string we removed from the
8231 input line. Otherwise return NULL.
8233 This function is copied from the ELF version above adjusted for PE targets. */
8236 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8237 int *adjust ATTRIBUTE_UNUSED,
8238 i386_operand_type *types)
8244 const enum bfd_reloc_code_real rel[2];
8245 const i386_operand_type types64;
8249 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8250 BFD_RELOC_32_SECREL },
8251 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8257 for (cp = input_line_pointer; *cp != '@'; cp++)
8258 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8261 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8263 int len = gotrel[j].len;
8265 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8267 if (gotrel[j].rel[object_64bit] != 0)
8270 char *tmpbuf, *past_reloc;
8272 *rel = gotrel[j].rel[object_64bit];
8278 if (flag_code != CODE_64BIT)
8280 types->bitfield.imm32 = 1;
8281 types->bitfield.disp32 = 1;
8284 *types = gotrel[j].types64;
8287 /* The length of the first part of our input line. */
8288 first = cp - input_line_pointer;
8290 /* The second part goes from after the reloc token until
8291 (and including) an end_of_line char or comma. */
8292 past_reloc = cp + 1 + len;
8294 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8296 second = cp + 1 - past_reloc;
8298 /* Allocate and copy string. The trailing NUL shouldn't
8299 be necessary, but be safe. */
8300 tmpbuf = XNEWVEC (char, first + second + 2);
8301 memcpy (tmpbuf, input_line_pointer, first);
8302 if (second != 0 && *past_reloc != ' ')
8303 /* Replace the relocation token with ' ', so that
8304 errors like foo@SECLREL321 will be detected. */
8305 tmpbuf[first++] = ' ';
8306 memcpy (tmpbuf + first, past_reloc, second);
8307 tmpbuf[first + second] = '\0';
8311 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8312 gotrel[j].str, 1 << (5 + object_64bit));
8317 /* Might be a symbol version string. Don't as_bad here. */
8323 bfd_reloc_code_real_type
8324 x86_cons (expressionS *exp, int size)
8326 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8328 intel_syntax = -intel_syntax;
8331 if (size == 4 || (object_64bit && size == 8))
8333 /* Handle @GOTOFF and the like in an expression. */
8335 char *gotfree_input_line;
8338 save = input_line_pointer;
8339 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8340 if (gotfree_input_line)
8341 input_line_pointer = gotfree_input_line;
8345 if (gotfree_input_line)
8347 /* expression () has merrily parsed up to the end of line,
8348 or a comma - in the wrong buffer. Transfer how far
8349 input_line_pointer has moved to the right buffer. */
8350 input_line_pointer = (save
8351 + (input_line_pointer - gotfree_input_line)
8353 free (gotfree_input_line);
8354 if (exp->X_op == O_constant
8355 || exp->X_op == O_absent
8356 || exp->X_op == O_illegal
8357 || exp->X_op == O_register
8358 || exp->X_op == O_big)
8360 char c = *input_line_pointer;
8361 *input_line_pointer = 0;
8362 as_bad (_("missing or invalid expression `%s'"), save);
8363 *input_line_pointer = c;
8370 intel_syntax = -intel_syntax;
8373 i386_intel_simplify (exp);
8379 signed_cons (int size)
8381 if (flag_code == CODE_64BIT)
8389 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8396 if (exp.X_op == O_symbol)
8397 exp.X_op = O_secrel;
8399 emit_expr (&exp, 4);
8401 while (*input_line_pointer++ == ',');
8403 input_line_pointer--;
8404 demand_empty_rest_of_line ();
8408 /* Handle Vector operations. */
8411 check_VecOperations (char *op_string, char *op_end)
8413 const reg_entry *mask;
8418 && (op_end == NULL || op_string < op_end))
8421 if (*op_string == '{')
8425 /* Check broadcasts. */
8426 if (strncmp (op_string, "1to", 3) == 0)
8431 goto duplicated_vec_op;
8434 if (*op_string == '8')
8435 bcst_type = BROADCAST_1TO8;
8436 else if (*op_string == '4')
8437 bcst_type = BROADCAST_1TO4;
8438 else if (*op_string == '2')
8439 bcst_type = BROADCAST_1TO2;
8440 else if (*op_string == '1'
8441 && *(op_string+1) == '6')
8443 bcst_type = BROADCAST_1TO16;
8448 as_bad (_("Unsupported broadcast: `%s'"), saved);
8453 broadcast_op.type = bcst_type;
8454 broadcast_op.operand = this_operand;
8455 i.broadcast = &broadcast_op;
8457 /* Check masking operation. */
8458 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8460 /* k0 can't be used for write mask. */
8461 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8463 as_bad (_("`%s%s' can't be used for write mask"),
8464 register_prefix, mask->reg_name);
8470 mask_op.mask = mask;
8471 mask_op.zeroing = 0;
8472 mask_op.operand = this_operand;
8478 goto duplicated_vec_op;
8480 i.mask->mask = mask;
8482 /* Only "{z}" is allowed here. No need to check
8483 zeroing mask explicitly. */
8484 if (i.mask->operand != this_operand)
8486 as_bad (_("invalid write mask `%s'"), saved);
8493 /* Check zeroing-flag for masking operation. */
8494 else if (*op_string == 'z')
8498 mask_op.mask = NULL;
8499 mask_op.zeroing = 1;
8500 mask_op.operand = this_operand;
8505 if (i.mask->zeroing)
8508 as_bad (_("duplicated `%s'"), saved);
8512 i.mask->zeroing = 1;
8514 /* Only "{%k}" is allowed here. No need to check mask
8515 register explicitly. */
8516 if (i.mask->operand != this_operand)
8518 as_bad (_("invalid zeroing-masking `%s'"),
8527 goto unknown_vec_op;
8529 if (*op_string != '}')
8531 as_bad (_("missing `}' in `%s'"), saved);
8536 /* Strip whitespace since the addition of pseudo prefixes
8537 changed how the scrubber treats '{'. */
8538 if (is_space_char (*op_string))
8544 /* We don't know this one. */
8545 as_bad (_("unknown vector operation: `%s'"), saved);
8549 if (i.mask && i.mask->zeroing && !i.mask->mask)
8551 as_bad (_("zeroing-masking only allowed with write mask"));
8559 i386_immediate (char *imm_start)
8561 char *save_input_line_pointer;
8562 char *gotfree_input_line;
8565 i386_operand_type types;
8567 operand_type_set (&types, ~0);
8569 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8571 as_bad (_("at most %d immediate operands are allowed"),
8572 MAX_IMMEDIATE_OPERANDS);
8576 exp = &im_expressions[i.imm_operands++];
8577 i.op[this_operand].imms = exp;
8579 if (is_space_char (*imm_start))
8582 save_input_line_pointer = input_line_pointer;
8583 input_line_pointer = imm_start;
8585 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8586 if (gotfree_input_line)
8587 input_line_pointer = gotfree_input_line;
8589 exp_seg = expression (exp);
8593 /* Handle vector operations. */
8594 if (*input_line_pointer == '{')
8596 input_line_pointer = check_VecOperations (input_line_pointer,
8598 if (input_line_pointer == NULL)
8602 if (*input_line_pointer)
8603 as_bad (_("junk `%s' after expression"), input_line_pointer);
8605 input_line_pointer = save_input_line_pointer;
8606 if (gotfree_input_line)
8608 free (gotfree_input_line);
8610 if (exp->X_op == O_constant || exp->X_op == O_register)
8611 exp->X_op = O_illegal;
8614 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8618 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8619 i386_operand_type types, const char *imm_start)
8621 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8624 as_bad (_("missing or invalid immediate expression `%s'"),
8628 else if (exp->X_op == O_constant)
8630 /* Size it properly later. */
8631 i.types[this_operand].bitfield.imm64 = 1;
8632 /* If not 64bit, sign extend val. */
8633 if (flag_code != CODE_64BIT
8634 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8636 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8638 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8639 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8640 && exp_seg != absolute_section
8641 && exp_seg != text_section
8642 && exp_seg != data_section
8643 && exp_seg != bss_section
8644 && exp_seg != undefined_section
8645 && !bfd_is_com_section (exp_seg))
8647 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8651 else if (!intel_syntax && exp_seg == reg_section)
8654 as_bad (_("illegal immediate register operand %s"), imm_start);
8659 /* This is an address. The size of the address will be
8660 determined later, depending on destination register,
8661 suffix, or the default for the section. */
8662 i.types[this_operand].bitfield.imm8 = 1;
8663 i.types[this_operand].bitfield.imm16 = 1;
8664 i.types[this_operand].bitfield.imm32 = 1;
8665 i.types[this_operand].bitfield.imm32s = 1;
8666 i.types[this_operand].bitfield.imm64 = 1;
8667 i.types[this_operand] = operand_type_and (i.types[this_operand],
8675 i386_scale (char *scale)
8678 char *save = input_line_pointer;
8680 input_line_pointer = scale;
8681 val = get_absolute_expression ();
8686 i.log2_scale_factor = 0;
8689 i.log2_scale_factor = 1;
8692 i.log2_scale_factor = 2;
8695 i.log2_scale_factor = 3;
8699 char sep = *input_line_pointer;
8701 *input_line_pointer = '\0';
8702 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8704 *input_line_pointer = sep;
8705 input_line_pointer = save;
8709 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8711 as_warn (_("scale factor of %d without an index register"),
8712 1 << i.log2_scale_factor);
8713 i.log2_scale_factor = 0;
8715 scale = input_line_pointer;
8716 input_line_pointer = save;
8721 i386_displacement (char *disp_start, char *disp_end)
8725 char *save_input_line_pointer;
8726 char *gotfree_input_line;
8728 i386_operand_type bigdisp, types = anydisp;
8731 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8733 as_bad (_("at most %d displacement operands are allowed"),
8734 MAX_MEMORY_OPERANDS);
8738 operand_type_set (&bigdisp, 0);
8739 if ((i.types[this_operand].bitfield.jumpabsolute)
8740 || (!current_templates->start->opcode_modifier.jump
8741 && !current_templates->start->opcode_modifier.jumpdword))
8743 bigdisp.bitfield.disp32 = 1;
8744 override = (i.prefix[ADDR_PREFIX] != 0);
8745 if (flag_code == CODE_64BIT)
8749 bigdisp.bitfield.disp32s = 1;
8750 bigdisp.bitfield.disp64 = 1;
8753 else if ((flag_code == CODE_16BIT) ^ override)
8755 bigdisp.bitfield.disp32 = 0;
8756 bigdisp.bitfield.disp16 = 1;
8761 /* For PC-relative branches, the width of the displacement
8762 is dependent upon data size, not address size. */
8763 override = (i.prefix[DATA_PREFIX] != 0);
8764 if (flag_code == CODE_64BIT)
8766 if (override || i.suffix == WORD_MNEM_SUFFIX)
8767 bigdisp.bitfield.disp16 = 1;
8770 bigdisp.bitfield.disp32 = 1;
8771 bigdisp.bitfield.disp32s = 1;
8777 override = (i.suffix == (flag_code != CODE_16BIT
8779 : LONG_MNEM_SUFFIX));
8780 bigdisp.bitfield.disp32 = 1;
8781 if ((flag_code == CODE_16BIT) ^ override)
8783 bigdisp.bitfield.disp32 = 0;
8784 bigdisp.bitfield.disp16 = 1;
8788 i.types[this_operand] = operand_type_or (i.types[this_operand],
8791 exp = &disp_expressions[i.disp_operands];
8792 i.op[this_operand].disps = exp;
8794 save_input_line_pointer = input_line_pointer;
8795 input_line_pointer = disp_start;
8796 END_STRING_AND_SAVE (disp_end);
8798 #ifndef GCC_ASM_O_HACK
8799 #define GCC_ASM_O_HACK 0
8802 END_STRING_AND_SAVE (disp_end + 1);
8803 if (i.types[this_operand].bitfield.baseIndex
8804 && displacement_string_end[-1] == '+')
8806 /* This hack is to avoid a warning when using the "o"
8807 constraint within gcc asm statements.
8810 #define _set_tssldt_desc(n,addr,limit,type) \
8811 __asm__ __volatile__ ( \
8813 "movw %w1,2+%0\n\t" \
8815 "movb %b1,4+%0\n\t" \
8816 "movb %4,5+%0\n\t" \
8817 "movb $0,6+%0\n\t" \
8818 "movb %h1,7+%0\n\t" \
8820 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8822 This works great except that the output assembler ends
8823 up looking a bit weird if it turns out that there is
8824 no offset. You end up producing code that looks like:
8837 So here we provide the missing zero. */
8839 *displacement_string_end = '0';
8842 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8843 if (gotfree_input_line)
8844 input_line_pointer = gotfree_input_line;
8846 exp_seg = expression (exp);
8849 if (*input_line_pointer)
8850 as_bad (_("junk `%s' after expression"), input_line_pointer);
8852 RESTORE_END_STRING (disp_end + 1);
8854 input_line_pointer = save_input_line_pointer;
8855 if (gotfree_input_line)
8857 free (gotfree_input_line);
8859 if (exp->X_op == O_constant || exp->X_op == O_register)
8860 exp->X_op = O_illegal;
8863 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8865 RESTORE_END_STRING (disp_end);
8871 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8872 i386_operand_type types, const char *disp_start)
8874 i386_operand_type bigdisp;
8877 /* We do this to make sure that the section symbol is in
8878 the symbol table. We will ultimately change the relocation
8879 to be relative to the beginning of the section. */
8880 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8881 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8882 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8884 if (exp->X_op != O_symbol)
8887 if (S_IS_LOCAL (exp->X_add_symbol)
8888 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8889 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8890 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8891 exp->X_op = O_subtract;
8892 exp->X_op_symbol = GOT_symbol;
8893 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8894 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8895 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8896 i.reloc[this_operand] = BFD_RELOC_64;
8898 i.reloc[this_operand] = BFD_RELOC_32;
8901 else if (exp->X_op == O_absent
8902 || exp->X_op == O_illegal
8903 || exp->X_op == O_big)
8906 as_bad (_("missing or invalid displacement expression `%s'"),
8911 else if (flag_code == CODE_64BIT
8912 && !i.prefix[ADDR_PREFIX]
8913 && exp->X_op == O_constant)
8915 /* Since displacement is signed extended to 64bit, don't allow
8916 disp32 and turn off disp32s if they are out of range. */
8917 i.types[this_operand].bitfield.disp32 = 0;
8918 if (!fits_in_signed_long (exp->X_add_number))
8920 i.types[this_operand].bitfield.disp32s = 0;
8921 if (i.types[this_operand].bitfield.baseindex)
8923 as_bad (_("0x%lx out range of signed 32bit displacement"),
8924 (long) exp->X_add_number);
8930 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8931 else if (exp->X_op != O_constant
8932 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8933 && exp_seg != absolute_section
8934 && exp_seg != text_section
8935 && exp_seg != data_section
8936 && exp_seg != bss_section
8937 && exp_seg != undefined_section
8938 && !bfd_is_com_section (exp_seg))
8940 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8945 /* Check if this is a displacement only operand. */
8946 bigdisp = i.types[this_operand];
8947 bigdisp.bitfield.disp8 = 0;
8948 bigdisp.bitfield.disp16 = 0;
8949 bigdisp.bitfield.disp32 = 0;
8950 bigdisp.bitfield.disp32s = 0;
8951 bigdisp.bitfield.disp64 = 0;
8952 if (operand_type_all_zero (&bigdisp))
8953 i.types[this_operand] = operand_type_and (i.types[this_operand],
8959 /* Return the active addressing mode, taking address override and
8960 registers forming the address into consideration. Update the
8961 address override prefix if necessary. */
8963 static enum flag_code
8964 i386_addressing_mode (void)
8966 enum flag_code addr_mode;
8968 if (i.prefix[ADDR_PREFIX])
8969 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8972 addr_mode = flag_code;
8974 #if INFER_ADDR_PREFIX
8975 if (i.mem_operands == 0)
8977 /* Infer address prefix from the first memory operand. */
8978 const reg_entry *addr_reg = i.base_reg;
8980 if (addr_reg == NULL)
8981 addr_reg = i.index_reg;
8985 if (addr_reg->reg_num == RegEip
8986 || addr_reg->reg_num == RegEiz
8987 || addr_reg->reg_type.bitfield.dword)
8988 addr_mode = CODE_32BIT;
8989 else if (flag_code != CODE_64BIT
8990 && addr_reg->reg_type.bitfield.word)
8991 addr_mode = CODE_16BIT;
8993 if (addr_mode != flag_code)
8995 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8997 /* Change the size of any displacement too. At most one
8998 of Disp16 or Disp32 is set.
8999 FIXME. There doesn't seem to be any real need for
9000 separate Disp16 and Disp32 flags. The same goes for
9001 Imm16 and Imm32. Removing them would probably clean
9002 up the code quite a lot. */
9003 if (flag_code != CODE_64BIT
9004 && (i.types[this_operand].bitfield.disp16
9005 || i.types[this_operand].bitfield.disp32))
9006 i.types[this_operand]
9007 = operand_type_xor (i.types[this_operand], disp16_32);
9017 /* Make sure the memory operand we've been dealt is valid.
9018 Return 1 on success, 0 on a failure. */
9021 i386_index_check (const char *operand_string)
9023 const char *kind = "base/index";
9024 enum flag_code addr_mode = i386_addressing_mode ();
9026 if (current_templates->start->opcode_modifier.isstring
9027 && !current_templates->start->opcode_modifier.immext
9028 && (current_templates->end[-1].opcode_modifier.isstring
9031 /* Memory operands of string insns are special in that they only allow
9032 a single register (rDI, rSI, or rBX) as their memory address. */
9033 const reg_entry *expected_reg;
9034 static const char *di_si[][2] =
9040 static const char *bx[] = { "ebx", "bx", "rbx" };
9042 kind = "string address";
9044 if (current_templates->start->opcode_modifier.repprefixok)
9046 i386_operand_type type = current_templates->end[-1].operand_types[0];
9048 if (!type.bitfield.baseindex
9049 || ((!i.mem_operands != !intel_syntax)
9050 && current_templates->end[-1].operand_types[1]
9051 .bitfield.baseindex))
9052 type = current_templates->end[-1].operand_types[1];
9053 expected_reg = hash_find (reg_hash,
9054 di_si[addr_mode][type.bitfield.esseg]);
9058 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9060 if (i.base_reg != expected_reg
9062 || operand_type_check (i.types[this_operand], disp))
9064 /* The second memory operand must have the same size as
9068 && !((addr_mode == CODE_64BIT
9069 && i.base_reg->reg_type.bitfield.qword)
9070 || (addr_mode == CODE_32BIT
9071 ? i.base_reg->reg_type.bitfield.dword
9072 : i.base_reg->reg_type.bitfield.word)))
9075 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9077 intel_syntax ? '[' : '(',
9079 expected_reg->reg_name,
9080 intel_syntax ? ']' : ')');
9087 as_bad (_("`%s' is not a valid %s expression"),
9088 operand_string, kind);
9093 if (addr_mode != CODE_16BIT)
9095 /* 32-bit/64-bit checks. */
9097 && (addr_mode == CODE_64BIT
9098 ? !i.base_reg->reg_type.bitfield.qword
9099 : !i.base_reg->reg_type.bitfield.dword)
9101 || (i.base_reg->reg_num
9102 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9104 && !i.index_reg->reg_type.bitfield.xmmword
9105 && !i.index_reg->reg_type.bitfield.ymmword
9106 && !i.index_reg->reg_type.bitfield.zmmword
9107 && ((addr_mode == CODE_64BIT
9108 ? !(i.index_reg->reg_type.bitfield.qword
9109 || i.index_reg->reg_num == RegRiz)
9110 : !(i.index_reg->reg_type.bitfield.dword
9111 || i.index_reg->reg_num == RegEiz))
9112 || !i.index_reg->reg_type.bitfield.baseindex)))
9115 /* bndmk, bndldx, and bndstx have special restrictions. */
9116 if (current_templates->start->base_opcode == 0xf30f1b
9117 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9119 /* They cannot use RIP-relative addressing. */
9120 if (i.base_reg && i.base_reg->reg_num == RegRip)
9122 as_bad (_("`%s' cannot be used here"), operand_string);
9126 /* bndldx and bndstx ignore their scale factor. */
9127 if (current_templates->start->base_opcode != 0xf30f1b
9128 && i.log2_scale_factor)
9129 as_warn (_("register scaling is being ignored here"));
9134 /* 16-bit checks. */
9136 && (!i.base_reg->reg_type.bitfield.word
9137 || !i.base_reg->reg_type.bitfield.baseindex))
9139 && (!i.index_reg->reg_type.bitfield.word
9140 || !i.index_reg->reg_type.bitfield.baseindex
9142 && i.base_reg->reg_num < 6
9143 && i.index_reg->reg_num >= 6
9144 && i.log2_scale_factor == 0))))
9151 /* Handle vector immediates. */
9154 RC_SAE_immediate (const char *imm_start)
9156 unsigned int match_found, j;
9157 const char *pstr = imm_start;
9165 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9167 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9171 rc_op.type = RC_NamesTable[j].type;
9172 rc_op.operand = this_operand;
9173 i.rounding = &rc_op;
9177 as_bad (_("duplicated `%s'"), imm_start);
9180 pstr += RC_NamesTable[j].len;
9190 as_bad (_("Missing '}': '%s'"), imm_start);
9193 /* RC/SAE immediate string should contain nothing more. */;
9196 as_bad (_("Junk after '}': '%s'"), imm_start);
9200 exp = &im_expressions[i.imm_operands++];
9201 i.op[this_operand].imms = exp;
9203 exp->X_op = O_constant;
9204 exp->X_add_number = 0;
9205 exp->X_add_symbol = (symbolS *) 0;
9206 exp->X_op_symbol = (symbolS *) 0;
9208 i.types[this_operand].bitfield.imm8 = 1;
9212 /* Only string instructions can have a second memory operand, so
9213 reduce current_templates to just those if it contains any. */
9215 maybe_adjust_templates (void)
9217 const insn_template *t;
9219 gas_assert (i.mem_operands == 1);
9221 for (t = current_templates->start; t < current_templates->end; ++t)
9222 if (t->opcode_modifier.isstring)
9225 if (t < current_templates->end)
9227 static templates aux_templates;
9228 bfd_boolean recheck;
9230 aux_templates.start = t;
9231 for (; t < current_templates->end; ++t)
9232 if (!t->opcode_modifier.isstring)
9234 aux_templates.end = t;
9236 /* Determine whether to re-check the first memory operand. */
9237 recheck = (aux_templates.start != current_templates->start
9238 || t != current_templates->end);
9240 current_templates = &aux_templates;
9245 if (i.memop1_string != NULL
9246 && i386_index_check (i.memop1_string) == 0)
9255 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9259 i386_att_operand (char *operand_string)
9263 char *op_string = operand_string;
9265 if (is_space_char (*op_string))
9268 /* We check for an absolute prefix (differentiating,
9269 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9270 if (*op_string == ABSOLUTE_PREFIX)
9273 if (is_space_char (*op_string))
9275 i.types[this_operand].bitfield.jumpabsolute = 1;
9278 /* Check if operand is a register. */
9279 if ((r = parse_register (op_string, &end_op)) != NULL)
9281 i386_operand_type temp;
9283 /* Check for a segment override by searching for ':' after a
9284 segment register. */
9286 if (is_space_char (*op_string))
9288 if (*op_string == ':'
9289 && (r->reg_type.bitfield.sreg2
9290 || r->reg_type.bitfield.sreg3))
9295 i.seg[i.mem_operands] = &es;
9298 i.seg[i.mem_operands] = &cs;
9301 i.seg[i.mem_operands] = &ss;
9304 i.seg[i.mem_operands] = &ds;
9307 i.seg[i.mem_operands] = &fs;
9310 i.seg[i.mem_operands] = &gs;
9314 /* Skip the ':' and whitespace. */
9316 if (is_space_char (*op_string))
9319 if (!is_digit_char (*op_string)
9320 && !is_identifier_char (*op_string)
9321 && *op_string != '('
9322 && *op_string != ABSOLUTE_PREFIX)
9324 as_bad (_("bad memory operand `%s'"), op_string);
9327 /* Handle case of %es:*foo. */
9328 if (*op_string == ABSOLUTE_PREFIX)
9331 if (is_space_char (*op_string))
9333 i.types[this_operand].bitfield.jumpabsolute = 1;
9335 goto do_memory_reference;
9338 /* Handle vector operations. */
9339 if (*op_string == '{')
9341 op_string = check_VecOperations (op_string, NULL);
9342 if (op_string == NULL)
9348 as_bad (_("junk `%s' after register"), op_string);
9352 temp.bitfield.baseindex = 0;
9353 i.types[this_operand] = operand_type_or (i.types[this_operand],
9355 i.types[this_operand].bitfield.unspecified = 0;
9356 i.op[this_operand].regs = r;
9359 else if (*op_string == REGISTER_PREFIX)
9361 as_bad (_("bad register name `%s'"), op_string);
9364 else if (*op_string == IMMEDIATE_PREFIX)
9367 if (i.types[this_operand].bitfield.jumpabsolute)
9369 as_bad (_("immediate operand illegal with absolute jump"));
9372 if (!i386_immediate (op_string))
9375 else if (RC_SAE_immediate (operand_string))
9377 /* If it is a RC or SAE immediate, do nothing. */
9380 else if (is_digit_char (*op_string)
9381 || is_identifier_char (*op_string)
9382 || *op_string == '"'
9383 || *op_string == '(')
9385 /* This is a memory reference of some sort. */
9388 /* Start and end of displacement string expression (if found). */
9389 char *displacement_string_start;
9390 char *displacement_string_end;
9393 do_memory_reference:
9394 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9396 if ((i.mem_operands == 1
9397 && !current_templates->start->opcode_modifier.isstring)
9398 || i.mem_operands == 2)
9400 as_bad (_("too many memory references for `%s'"),
9401 current_templates->start->name);
9405 /* Check for base index form. We detect the base index form by
9406 looking for an ')' at the end of the operand, searching
9407 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9409 base_string = op_string + strlen (op_string);
9411 /* Handle vector operations. */
9412 vop_start = strchr (op_string, '{');
9413 if (vop_start && vop_start < base_string)
9415 if (check_VecOperations (vop_start, base_string) == NULL)
9417 base_string = vop_start;
9421 if (is_space_char (*base_string))
9424 /* If we only have a displacement, set-up for it to be parsed later. */
9425 displacement_string_start = op_string;
9426 displacement_string_end = base_string + 1;
9428 if (*base_string == ')')
9431 unsigned int parens_balanced = 1;
9432 /* We've already checked that the number of left & right ()'s are
9433 equal, so this loop will not be infinite. */
9437 if (*base_string == ')')
9439 if (*base_string == '(')
9442 while (parens_balanced);
9444 temp_string = base_string;
9446 /* Skip past '(' and whitespace. */
9448 if (is_space_char (*base_string))
9451 if (*base_string == ','
9452 || ((i.base_reg = parse_register (base_string, &end_op))
9455 displacement_string_end = temp_string;
9457 i.types[this_operand].bitfield.baseindex = 1;
9461 base_string = end_op;
9462 if (is_space_char (*base_string))
9466 /* There may be an index reg or scale factor here. */
9467 if (*base_string == ',')
9470 if (is_space_char (*base_string))
9473 if ((i.index_reg = parse_register (base_string, &end_op))
9476 base_string = end_op;
9477 if (is_space_char (*base_string))
9479 if (*base_string == ',')
9482 if (is_space_char (*base_string))
9485 else if (*base_string != ')')
9487 as_bad (_("expecting `,' or `)' "
9488 "after index register in `%s'"),
9493 else if (*base_string == REGISTER_PREFIX)
9495 end_op = strchr (base_string, ',');
9498 as_bad (_("bad register name `%s'"), base_string);
9502 /* Check for scale factor. */
9503 if (*base_string != ')')
9505 char *end_scale = i386_scale (base_string);
9510 base_string = end_scale;
9511 if (is_space_char (*base_string))
9513 if (*base_string != ')')
9515 as_bad (_("expecting `)' "
9516 "after scale factor in `%s'"),
9521 else if (!i.index_reg)
9523 as_bad (_("expecting index register or scale factor "
9524 "after `,'; got '%c'"),
9529 else if (*base_string != ')')
9531 as_bad (_("expecting `,' or `)' "
9532 "after base register in `%s'"),
9537 else if (*base_string == REGISTER_PREFIX)
9539 end_op = strchr (base_string, ',');
9542 as_bad (_("bad register name `%s'"), base_string);
9547 /* If there's an expression beginning the operand, parse it,
9548 assuming displacement_string_start and
9549 displacement_string_end are meaningful. */
9550 if (displacement_string_start != displacement_string_end)
9552 if (!i386_displacement (displacement_string_start,
9553 displacement_string_end))
9557 /* Special case for (%dx) while doing input/output op. */
9559 && operand_type_equal (&i.base_reg->reg_type,
9560 ®16_inoutportreg)
9562 && i.log2_scale_factor == 0
9563 && i.seg[i.mem_operands] == 0
9564 && !operand_type_check (i.types[this_operand], disp))
9566 i.types[this_operand] = inoutportreg;
9570 if (i386_index_check (operand_string) == 0)
9572 i.types[this_operand].bitfield.mem = 1;
9573 if (i.mem_operands == 0)
9574 i.memop1_string = xstrdup (operand_string);
9579 /* It's not a memory operand; argh! */
9580 as_bad (_("invalid char %s beginning operand %d `%s'"),
9581 output_invalid (*op_string),
9586 return 1; /* Normal return. */
9589 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9590 that an rs_machine_dependent frag may reach. */
9593 i386_frag_max_var (fragS *frag)
9595 /* The only relaxable frags are for jumps.
9596 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9597 gas_assert (frag->fr_type == rs_machine_dependent);
9598 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9601 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9603 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9605 /* STT_GNU_IFUNC symbol must go through PLT. */
9606 if ((symbol_get_bfdsym (fr_symbol)->flags
9607 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9610 if (!S_IS_EXTERNAL (fr_symbol))
9611 /* Symbol may be weak or local. */
9612 return !S_IS_WEAK (fr_symbol);
9614 /* Global symbols with non-default visibility can't be preempted. */
9615 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9618 if (fr_var != NO_RELOC)
9619 switch ((enum bfd_reloc_code_real) fr_var)
9621 case BFD_RELOC_386_PLT32:
9622 case BFD_RELOC_X86_64_PLT32:
9623 /* Symbol with PLT relocation may be preempted. */
9629 /* Global symbols with default visibility in a shared library may be
9630 preempted by another definition. */
9635 /* md_estimate_size_before_relax()
9637 Called just before relax() for rs_machine_dependent frags. The x86
9638 assembler uses these frags to handle variable size jump
9641 Any symbol that is now undefined will not become defined.
9642 Return the correct fr_subtype in the frag.
9643 Return the initial "guess for variable size of frag" to caller.
9644 The guess is actually the growth beyond the fixed part. Whatever
9645 we do to grow the fixed or variable part contributes to our
9649 md_estimate_size_before_relax (fragS *fragP, segT segment)
9651 /* We've already got fragP->fr_subtype right; all we have to do is
9652 check for un-relaxable symbols. On an ELF system, we can't relax
9653 an externally visible symbol, because it may be overridden by a
9655 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9656 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9658 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9661 #if defined (OBJ_COFF) && defined (TE_PE)
9662 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9663 && S_IS_WEAK (fragP->fr_symbol))
9667 /* Symbol is undefined in this segment, or we need to keep a
9668 reloc so that weak symbols can be overridden. */
9669 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9670 enum bfd_reloc_code_real reloc_type;
9671 unsigned char *opcode;
9674 if (fragP->fr_var != NO_RELOC)
9675 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9677 reloc_type = BFD_RELOC_16_PCREL;
9678 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9679 else if (need_plt32_p (fragP->fr_symbol))
9680 reloc_type = BFD_RELOC_X86_64_PLT32;
9683 reloc_type = BFD_RELOC_32_PCREL;
9685 old_fr_fix = fragP->fr_fix;
9686 opcode = (unsigned char *) fragP->fr_opcode;
9688 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9691 /* Make jmp (0xeb) a (d)word displacement jump. */
9693 fragP->fr_fix += size;
9694 fix_new (fragP, old_fr_fix, size,
9696 fragP->fr_offset, 1,
9702 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9704 /* Negate the condition, and branch past an
9705 unconditional jump. */
9708 /* Insert an unconditional jump. */
9710 /* We added two extra opcode bytes, and have a two byte
9712 fragP->fr_fix += 2 + 2;
9713 fix_new (fragP, old_fr_fix + 2, 2,
9715 fragP->fr_offset, 1,
9722 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9727 fixP = fix_new (fragP, old_fr_fix, 1,
9729 fragP->fr_offset, 1,
9731 fixP->fx_signed = 1;
9735 /* This changes the byte-displacement jump 0x7N
9736 to the (d)word-displacement jump 0x0f,0x8N. */
9737 opcode[1] = opcode[0] + 0x10;
9738 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9739 /* We've added an opcode byte. */
9740 fragP->fr_fix += 1 + size;
9741 fix_new (fragP, old_fr_fix + 1, size,
9743 fragP->fr_offset, 1,
9748 BAD_CASE (fragP->fr_subtype);
9752 return fragP->fr_fix - old_fr_fix;
9755 /* Guess size depending on current relax state. Initially the relax
9756 state will correspond to a short jump and we return 1, because
9757 the variable part of the frag (the branch offset) is one byte
9758 long. However, we can relax a section more than once and in that
9759 case we must either set fr_subtype back to the unrelaxed state,
9760 or return the value for the appropriate branch. */
9761 return md_relax_table[fragP->fr_subtype].rlx_length;
9764 /* Called after relax() is finished.
9766 In: Address of frag.
9767 fr_type == rs_machine_dependent.
9768 fr_subtype is what the address relaxed to.
9770 Out: Any fixSs and constants are set up.
9771 Caller will turn frag into a ".space 0". */
9774 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9777 unsigned char *opcode;
9778 unsigned char *where_to_put_displacement = NULL;
9779 offsetT target_address;
9780 offsetT opcode_address;
9781 unsigned int extension = 0;
9782 offsetT displacement_from_opcode_start;
9784 opcode = (unsigned char *) fragP->fr_opcode;
9786 /* Address we want to reach in file space. */
9787 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9789 /* Address opcode resides at in file space. */
9790 opcode_address = fragP->fr_address + fragP->fr_fix;
9792 /* Displacement from opcode start to fill into instruction. */
9793 displacement_from_opcode_start = target_address - opcode_address;
9795 if ((fragP->fr_subtype & BIG) == 0)
9797 /* Don't have to change opcode. */
9798 extension = 1; /* 1 opcode + 1 displacement */
9799 where_to_put_displacement = &opcode[1];
9803 if (no_cond_jump_promotion
9804 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9805 as_warn_where (fragP->fr_file, fragP->fr_line,
9806 _("long jump required"));
9808 switch (fragP->fr_subtype)
9810 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9811 extension = 4; /* 1 opcode + 4 displacement */
9813 where_to_put_displacement = &opcode[1];
9816 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9817 extension = 2; /* 1 opcode + 2 displacement */
9819 where_to_put_displacement = &opcode[1];
9822 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9823 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9824 extension = 5; /* 2 opcode + 4 displacement */
9825 opcode[1] = opcode[0] + 0x10;
9826 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9827 where_to_put_displacement = &opcode[2];
9830 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9831 extension = 3; /* 2 opcode + 2 displacement */
9832 opcode[1] = opcode[0] + 0x10;
9833 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9834 where_to_put_displacement = &opcode[2];
9837 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9842 where_to_put_displacement = &opcode[3];
9846 BAD_CASE (fragP->fr_subtype);
9851 /* If size if less then four we are sure that the operand fits,
9852 but if it's 4, then it could be that the displacement is larger
9854 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9856 && ((addressT) (displacement_from_opcode_start - extension
9857 + ((addressT) 1 << 31))
9858 > (((addressT) 2 << 31) - 1)))
9860 as_bad_where (fragP->fr_file, fragP->fr_line,
9861 _("jump target out of range"));
9862 /* Make us emit 0. */
9863 displacement_from_opcode_start = extension;
9865 /* Now put displacement after opcode. */
9866 md_number_to_chars ((char *) where_to_put_displacement,
9867 (valueT) (displacement_from_opcode_start - extension),
9868 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9869 fragP->fr_fix += extension;
9872 /* Apply a fixup (fixP) to segment data, once it has been determined
9873 by our caller that we have all the info we need to fix it up.
9875 Parameter valP is the pointer to the value of the bits.
9877 On the 386, immediates, displacements, and data pointers are all in
9878 the same (little-endian) format, so we don't need to care about which
9882 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9884 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9885 valueT value = *valP;
9887 #if !defined (TE_Mach)
9890 switch (fixP->fx_r_type)
9896 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9899 case BFD_RELOC_X86_64_32S:
9900 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9903 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9906 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9911 if (fixP->fx_addsy != NULL
9912 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9913 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9914 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9915 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9916 && !use_rela_relocations)
9918 /* This is a hack. There should be a better way to handle this.
9919 This covers for the fact that bfd_install_relocation will
9920 subtract the current location (for partial_inplace, PC relative
9921 relocations); see more below. */
9925 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9928 value += fixP->fx_where + fixP->fx_frag->fr_address;
9930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9933 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9936 || (symbol_section_p (fixP->fx_addsy)
9937 && sym_seg != absolute_section))
9938 && !generic_force_reloc (fixP))
9940 /* Yes, we add the values in twice. This is because
9941 bfd_install_relocation subtracts them out again. I think
9942 bfd_install_relocation is broken, but I don't dare change
9944 value += fixP->fx_where + fixP->fx_frag->fr_address;
9948 #if defined (OBJ_COFF) && defined (TE_PE)
9949 /* For some reason, the PE format does not store a
9950 section address offset for a PC relative symbol. */
9951 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9952 || S_IS_WEAK (fixP->fx_addsy))
9953 value += md_pcrel_from (fixP);
9956 #if defined (OBJ_COFF) && defined (TE_PE)
9957 if (fixP->fx_addsy != NULL
9958 && S_IS_WEAK (fixP->fx_addsy)
9959 /* PR 16858: Do not modify weak function references. */
9960 && ! fixP->fx_pcrel)
9962 #if !defined (TE_PEP)
9963 /* For x86 PE weak function symbols are neither PC-relative
9964 nor do they set S_IS_FUNCTION. So the only reliable way
9965 to detect them is to check the flags of their containing
9967 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9968 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9972 value -= S_GET_VALUE (fixP->fx_addsy);
9976 /* Fix a few things - the dynamic linker expects certain values here,
9977 and we must not disappoint it. */
9978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9979 if (IS_ELF && fixP->fx_addsy)
9980 switch (fixP->fx_r_type)
9982 case BFD_RELOC_386_PLT32:
9983 case BFD_RELOC_X86_64_PLT32:
9984 /* Make the jump instruction point to the address of the operand. At
9985 runtime we merely add the offset to the actual PLT entry. */
9989 case BFD_RELOC_386_TLS_GD:
9990 case BFD_RELOC_386_TLS_LDM:
9991 case BFD_RELOC_386_TLS_IE_32:
9992 case BFD_RELOC_386_TLS_IE:
9993 case BFD_RELOC_386_TLS_GOTIE:
9994 case BFD_RELOC_386_TLS_GOTDESC:
9995 case BFD_RELOC_X86_64_TLSGD:
9996 case BFD_RELOC_X86_64_TLSLD:
9997 case BFD_RELOC_X86_64_GOTTPOFF:
9998 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9999 value = 0; /* Fully resolved at runtime. No addend. */
10001 case BFD_RELOC_386_TLS_LE:
10002 case BFD_RELOC_386_TLS_LDO_32:
10003 case BFD_RELOC_386_TLS_LE_32:
10004 case BFD_RELOC_X86_64_DTPOFF32:
10005 case BFD_RELOC_X86_64_DTPOFF64:
10006 case BFD_RELOC_X86_64_TPOFF32:
10007 case BFD_RELOC_X86_64_TPOFF64:
10008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10011 case BFD_RELOC_386_TLS_DESC_CALL:
10012 case BFD_RELOC_X86_64_TLSDESC_CALL:
10013 value = 0; /* Fully resolved at runtime. No addend. */
10014 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10018 case BFD_RELOC_VTABLE_INHERIT:
10019 case BFD_RELOC_VTABLE_ENTRY:
10026 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10028 #endif /* !defined (TE_Mach) */
10030 /* Are we finished with this relocation now? */
10031 if (fixP->fx_addsy == NULL)
10033 #if defined (OBJ_COFF) && defined (TE_PE)
10034 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10037 /* Remember value for tc_gen_reloc. */
10038 fixP->fx_addnumber = value;
10039 /* Clear out the frag for now. */
10043 else if (use_rela_relocations)
10045 fixP->fx_no_overflow = 1;
10046 /* Remember value for tc_gen_reloc. */
10047 fixP->fx_addnumber = value;
10051 md_number_to_chars (p, value, fixP->fx_size);
10055 md_atof (int type, char *litP, int *sizeP)
10057 /* This outputs the LITTLENUMs in REVERSE order;
10058 in accord with the bigendian 386. */
10059 return ieee_md_atof (type, litP, sizeP, FALSE);
10062 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10065 output_invalid (int c)
10068 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10071 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10072 "(0x%x)", (unsigned char) c);
10073 return output_invalid_buf;
10076 /* REG_STRING starts *before* REGISTER_PREFIX. */
10078 static const reg_entry *
10079 parse_real_register (char *reg_string, char **end_op)
10081 char *s = reg_string;
10083 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10084 const reg_entry *r;
10086 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10087 if (*s == REGISTER_PREFIX)
10090 if (is_space_char (*s))
10093 p = reg_name_given;
10094 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10096 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10097 return (const reg_entry *) NULL;
10101 /* For naked regs, make sure that we are not dealing with an identifier.
10102 This prevents confusing an identifier like `eax_var' with register
10104 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10105 return (const reg_entry *) NULL;
10109 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10111 /* Handle floating point regs, allowing spaces in the (i) part. */
10112 if (r == i386_regtab /* %st is first entry of table */)
10114 if (is_space_char (*s))
10119 if (is_space_char (*s))
10121 if (*s >= '0' && *s <= '7')
10123 int fpr = *s - '0';
10125 if (is_space_char (*s))
10130 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10135 /* We have "%st(" then garbage. */
10136 return (const reg_entry *) NULL;
10140 if (r == NULL || allow_pseudo_reg)
10143 if (operand_type_all_zero (&r->reg_type))
10144 return (const reg_entry *) NULL;
10146 if ((r->reg_type.bitfield.dword
10147 || r->reg_type.bitfield.sreg3
10148 || r->reg_type.bitfield.control
10149 || r->reg_type.bitfield.debug
10150 || r->reg_type.bitfield.test)
10151 && !cpu_arch_flags.bitfield.cpui386)
10152 return (const reg_entry *) NULL;
10154 if (r->reg_type.bitfield.tbyte
10155 && !cpu_arch_flags.bitfield.cpu8087
10156 && !cpu_arch_flags.bitfield.cpu287
10157 && !cpu_arch_flags.bitfield.cpu387)
10158 return (const reg_entry *) NULL;
10160 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10161 return (const reg_entry *) NULL;
10163 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10164 return (const reg_entry *) NULL;
10166 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10167 return (const reg_entry *) NULL;
10169 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10170 return (const reg_entry *) NULL;
10172 if (r->reg_type.bitfield.regmask
10173 && !cpu_arch_flags.bitfield.cpuregmask)
10174 return (const reg_entry *) NULL;
10176 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10177 if (!allow_index_reg
10178 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10179 return (const reg_entry *) NULL;
10181 /* Upper 16 vector register is only available with VREX in 64bit
10183 if ((r->reg_flags & RegVRex))
10185 if (i.vec_encoding == vex_encoding_default)
10186 i.vec_encoding = vex_encoding_evex;
10188 if (!cpu_arch_flags.bitfield.cpuvrex
10189 || i.vec_encoding != vex_encoding_evex
10190 || flag_code != CODE_64BIT)
10191 return (const reg_entry *) NULL;
10194 if (((r->reg_flags & (RegRex64 | RegRex))
10195 || r->reg_type.bitfield.qword)
10196 && (!cpu_arch_flags.bitfield.cpulm
10197 || !operand_type_equal (&r->reg_type, &control))
10198 && flag_code != CODE_64BIT)
10199 return (const reg_entry *) NULL;
10201 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10202 return (const reg_entry *) NULL;
10207 /* REG_STRING starts *before* REGISTER_PREFIX. */
10209 static const reg_entry *
10210 parse_register (char *reg_string, char **end_op)
10212 const reg_entry *r;
10214 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10215 r = parse_real_register (reg_string, end_op);
10220 char *save = input_line_pointer;
10224 input_line_pointer = reg_string;
10225 c = get_symbol_name (®_string);
10226 symbolP = symbol_find (reg_string);
10227 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10229 const expressionS *e = symbol_get_value_expression (symbolP);
10231 know (e->X_op == O_register);
10232 know (e->X_add_number >= 0
10233 && (valueT) e->X_add_number < i386_regtab_size);
10234 r = i386_regtab + e->X_add_number;
10235 if ((r->reg_flags & RegVRex))
10236 i.vec_encoding = vex_encoding_evex;
10237 *end_op = input_line_pointer;
10239 *input_line_pointer = c;
10240 input_line_pointer = save;
10246 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10248 const reg_entry *r;
10249 char *end = input_line_pointer;
10252 r = parse_register (name, &input_line_pointer);
10253 if (r && end <= input_line_pointer)
10255 *nextcharP = *input_line_pointer;
10256 *input_line_pointer = 0;
10257 e->X_op = O_register;
10258 e->X_add_number = r - i386_regtab;
10261 input_line_pointer = end;
10263 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10267 md_operand (expressionS *e)
10270 const reg_entry *r;
10272 switch (*input_line_pointer)
10274 case REGISTER_PREFIX:
10275 r = parse_real_register (input_line_pointer, &end);
10278 e->X_op = O_register;
10279 e->X_add_number = r - i386_regtab;
10280 input_line_pointer = end;
10285 gas_assert (intel_syntax);
10286 end = input_line_pointer++;
10288 if (*input_line_pointer == ']')
10290 ++input_line_pointer;
10291 e->X_op_symbol = make_expr_symbol (e);
10292 e->X_add_symbol = NULL;
10293 e->X_add_number = 0;
10298 e->X_op = O_absent;
10299 input_line_pointer = end;
10306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10307 const char *md_shortopts = "kVQ:sqnO::";
10309 const char *md_shortopts = "qnO::";
10312 #define OPTION_32 (OPTION_MD_BASE + 0)
10313 #define OPTION_64 (OPTION_MD_BASE + 1)
10314 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10315 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10316 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10317 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10318 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10319 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10320 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10321 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10322 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10323 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10324 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10325 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10326 #define OPTION_X32 (OPTION_MD_BASE + 14)
10327 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10328 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10329 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10330 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10331 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10332 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10333 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10334 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10335 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10336 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10338 struct option md_longopts[] =
10340 {"32", no_argument, NULL, OPTION_32},
10341 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10342 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10343 {"64", no_argument, NULL, OPTION_64},
10345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10346 {"x32", no_argument, NULL, OPTION_X32},
10347 {"mshared", no_argument, NULL, OPTION_MSHARED},
10349 {"divide", no_argument, NULL, OPTION_DIVIDE},
10350 {"march", required_argument, NULL, OPTION_MARCH},
10351 {"mtune", required_argument, NULL, OPTION_MTUNE},
10352 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10353 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10354 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10355 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10356 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10357 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10358 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10359 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10360 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10361 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10362 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10363 # if defined (TE_PE) || defined (TE_PEP)
10364 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10366 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10367 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10368 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10369 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10370 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10371 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10372 {NULL, no_argument, NULL, 0}
10374 size_t md_longopts_size = sizeof (md_longopts);
10377 md_parse_option (int c, const char *arg)
10380 char *arch, *next, *saved;
10385 optimize_align_code = 0;
10389 quiet_warnings = 1;
10392 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10393 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10394 should be emitted or not. FIXME: Not implemented. */
10398 /* -V: SVR4 argument to print version ID. */
10400 print_version_id ();
10403 /* -k: Ignore for FreeBSD compatibility. */
10408 /* -s: On i386 Solaris, this tells the native assembler to use
10409 .stab instead of .stab.excl. We always use .stab anyhow. */
10412 case OPTION_MSHARED:
10416 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10417 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10420 const char **list, **l;
10422 list = bfd_target_list ();
10423 for (l = list; *l != NULL; l++)
10424 if (CONST_STRNEQ (*l, "elf64-x86-64")
10425 || strcmp (*l, "coff-x86-64") == 0
10426 || strcmp (*l, "pe-x86-64") == 0
10427 || strcmp (*l, "pei-x86-64") == 0
10428 || strcmp (*l, "mach-o-x86-64") == 0)
10430 default_arch = "x86_64";
10434 as_fatal (_("no compiled in support for x86_64"));
10440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10444 const char **list, **l;
10446 list = bfd_target_list ();
10447 for (l = list; *l != NULL; l++)
10448 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10450 default_arch = "x86_64:32";
10454 as_fatal (_("no compiled in support for 32bit x86_64"));
10458 as_fatal (_("32bit x86_64 is only supported for ELF"));
10463 default_arch = "i386";
10466 case OPTION_DIVIDE:
10467 #ifdef SVR4_COMMENT_CHARS
10472 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10474 for (s = i386_comment_chars; *s != '\0'; s++)
10478 i386_comment_chars = n;
10484 saved = xstrdup (arg);
10486 /* Allow -march=+nosse. */
10492 as_fatal (_("invalid -march= option: `%s'"), arg);
10493 next = strchr (arch, '+');
10496 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10498 if (strcmp (arch, cpu_arch [j].name) == 0)
10501 if (! cpu_arch[j].flags.bitfield.cpui386)
10504 cpu_arch_name = cpu_arch[j].name;
10505 cpu_sub_arch_name = NULL;
10506 cpu_arch_flags = cpu_arch[j].flags;
10507 cpu_arch_isa = cpu_arch[j].type;
10508 cpu_arch_isa_flags = cpu_arch[j].flags;
10509 if (!cpu_arch_tune_set)
10511 cpu_arch_tune = cpu_arch_isa;
10512 cpu_arch_tune_flags = cpu_arch_isa_flags;
10516 else if (*cpu_arch [j].name == '.'
10517 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10519 /* ISA extension. */
10520 i386_cpu_flags flags;
10522 flags = cpu_flags_or (cpu_arch_flags,
10523 cpu_arch[j].flags);
10525 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10527 if (cpu_sub_arch_name)
10529 char *name = cpu_sub_arch_name;
10530 cpu_sub_arch_name = concat (name,
10532 (const char *) NULL);
10536 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10537 cpu_arch_flags = flags;
10538 cpu_arch_isa_flags = flags;
10542 = cpu_flags_or (cpu_arch_isa_flags,
10543 cpu_arch[j].flags);
10548 if (j >= ARRAY_SIZE (cpu_arch))
10550 /* Disable an ISA extension. */
10551 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10552 if (strcmp (arch, cpu_noarch [j].name) == 0)
10554 i386_cpu_flags flags;
10556 flags = cpu_flags_and_not (cpu_arch_flags,
10557 cpu_noarch[j].flags);
10558 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10560 if (cpu_sub_arch_name)
10562 char *name = cpu_sub_arch_name;
10563 cpu_sub_arch_name = concat (arch,
10564 (const char *) NULL);
10568 cpu_sub_arch_name = xstrdup (arch);
10569 cpu_arch_flags = flags;
10570 cpu_arch_isa_flags = flags;
10575 if (j >= ARRAY_SIZE (cpu_noarch))
10576 j = ARRAY_SIZE (cpu_arch);
10579 if (j >= ARRAY_SIZE (cpu_arch))
10580 as_fatal (_("invalid -march= option: `%s'"), arg);
10584 while (next != NULL);
10590 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10591 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10593 if (strcmp (arg, cpu_arch [j].name) == 0)
10595 cpu_arch_tune_set = 1;
10596 cpu_arch_tune = cpu_arch [j].type;
10597 cpu_arch_tune_flags = cpu_arch[j].flags;
10601 if (j >= ARRAY_SIZE (cpu_arch))
10602 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10605 case OPTION_MMNEMONIC:
10606 if (strcasecmp (arg, "att") == 0)
10607 intel_mnemonic = 0;
10608 else if (strcasecmp (arg, "intel") == 0)
10609 intel_mnemonic = 1;
10611 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10614 case OPTION_MSYNTAX:
10615 if (strcasecmp (arg, "att") == 0)
10617 else if (strcasecmp (arg, "intel") == 0)
10620 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10623 case OPTION_MINDEX_REG:
10624 allow_index_reg = 1;
10627 case OPTION_MNAKED_REG:
10628 allow_naked_reg = 1;
10631 case OPTION_MSSE2AVX:
10635 case OPTION_MSSE_CHECK:
10636 if (strcasecmp (arg, "error") == 0)
10637 sse_check = check_error;
10638 else if (strcasecmp (arg, "warning") == 0)
10639 sse_check = check_warning;
10640 else if (strcasecmp (arg, "none") == 0)
10641 sse_check = check_none;
10643 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10646 case OPTION_MOPERAND_CHECK:
10647 if (strcasecmp (arg, "error") == 0)
10648 operand_check = check_error;
10649 else if (strcasecmp (arg, "warning") == 0)
10650 operand_check = check_warning;
10651 else if (strcasecmp (arg, "none") == 0)
10652 operand_check = check_none;
10654 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10657 case OPTION_MAVXSCALAR:
10658 if (strcasecmp (arg, "128") == 0)
10659 avxscalar = vex128;
10660 else if (strcasecmp (arg, "256") == 0)
10661 avxscalar = vex256;
10663 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10666 case OPTION_MADD_BND_PREFIX:
10667 add_bnd_prefix = 1;
10670 case OPTION_MEVEXLIG:
10671 if (strcmp (arg, "128") == 0)
10672 evexlig = evexl128;
10673 else if (strcmp (arg, "256") == 0)
10674 evexlig = evexl256;
10675 else if (strcmp (arg, "512") == 0)
10676 evexlig = evexl512;
10678 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10681 case OPTION_MEVEXRCIG:
10682 if (strcmp (arg, "rne") == 0)
10684 else if (strcmp (arg, "rd") == 0)
10686 else if (strcmp (arg, "ru") == 0)
10688 else if (strcmp (arg, "rz") == 0)
10691 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10694 case OPTION_MEVEXWIG:
10695 if (strcmp (arg, "0") == 0)
10697 else if (strcmp (arg, "1") == 0)
10700 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10703 # if defined (TE_PE) || defined (TE_PEP)
10704 case OPTION_MBIG_OBJ:
10709 case OPTION_MOMIT_LOCK_PREFIX:
10710 if (strcasecmp (arg, "yes") == 0)
10711 omit_lock_prefix = 1;
10712 else if (strcasecmp (arg, "no") == 0)
10713 omit_lock_prefix = 0;
10715 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10718 case OPTION_MFENCE_AS_LOCK_ADD:
10719 if (strcasecmp (arg, "yes") == 0)
10721 else if (strcasecmp (arg, "no") == 0)
10724 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10727 case OPTION_MRELAX_RELOCATIONS:
10728 if (strcasecmp (arg, "yes") == 0)
10729 generate_relax_relocations = 1;
10730 else if (strcasecmp (arg, "no") == 0)
10731 generate_relax_relocations = 0;
10733 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10736 case OPTION_MAMD64:
10740 case OPTION_MINTEL64:
10748 /* Turn off -Os. */
10749 optimize_for_space = 0;
10751 else if (*arg == 's')
10753 optimize_for_space = 1;
10754 /* Turn on all encoding optimizations. */
10759 optimize = atoi (arg);
10760 /* Turn off -Os. */
10761 optimize_for_space = 0;
10771 #define MESSAGE_TEMPLATE \
10775 output_message (FILE *stream, char *p, char *message, char *start,
10776 int *left_p, const char *name, int len)
10778 int size = sizeof (MESSAGE_TEMPLATE);
10779 int left = *left_p;
10781 /* Reserve 2 spaces for ", " or ",\0" */
10784 /* Check if there is any room. */
10792 p = mempcpy (p, name, len);
10796 /* Output the current message now and start a new one. */
10799 fprintf (stream, "%s\n", message);
10801 left = size - (start - message) - len - 2;
10803 gas_assert (left >= 0);
10805 p = mempcpy (p, name, len);
10813 show_arch (FILE *stream, int ext, int check)
10815 static char message[] = MESSAGE_TEMPLATE;
10816 char *start = message + 27;
10818 int size = sizeof (MESSAGE_TEMPLATE);
10825 left = size - (start - message);
10826 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10828 /* Should it be skipped? */
10829 if (cpu_arch [j].skip)
10832 name = cpu_arch [j].name;
10833 len = cpu_arch [j].len;
10836 /* It is an extension. Skip if we aren't asked to show it. */
10847 /* It is an processor. Skip if we show only extension. */
10850 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10852 /* It is an impossible processor - skip. */
10856 p = output_message (stream, p, message, start, &left, name, len);
10859 /* Display disabled extensions. */
10861 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10863 name = cpu_noarch [j].name;
10864 len = cpu_noarch [j].len;
10865 p = output_message (stream, p, message, start, &left, name,
10870 fprintf (stream, "%s\n", message);
10874 md_show_usage (FILE *stream)
10876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10877 fprintf (stream, _("\
10879 -V print assembler version number\n\
10882 fprintf (stream, _("\
10883 -n Do not optimize code alignment\n\
10884 -q quieten some warnings\n"));
10885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10886 fprintf (stream, _("\
10889 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10890 || defined (TE_PE) || defined (TE_PEP))
10891 fprintf (stream, _("\
10892 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10894 #ifdef SVR4_COMMENT_CHARS
10895 fprintf (stream, _("\
10896 --divide do not treat `/' as a comment character\n"));
10898 fprintf (stream, _("\
10899 --divide ignored\n"));
10901 fprintf (stream, _("\
10902 -march=CPU[,+EXTENSION...]\n\
10903 generate code for CPU and EXTENSION, CPU is one of:\n"));
10904 show_arch (stream, 0, 1);
10905 fprintf (stream, _("\
10906 EXTENSION is combination of:\n"));
10907 show_arch (stream, 1, 0);
10908 fprintf (stream, _("\
10909 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10910 show_arch (stream, 0, 0);
10911 fprintf (stream, _("\
10912 -msse2avx encode SSE instructions with VEX prefix\n"));
10913 fprintf (stream, _("\
10914 -msse-check=[none|error|warning]\n\
10915 check SSE instructions\n"));
10916 fprintf (stream, _("\
10917 -moperand-check=[none|error|warning]\n\
10918 check operand combinations for validity\n"));
10919 fprintf (stream, _("\
10920 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10922 fprintf (stream, _("\
10923 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10925 fprintf (stream, _("\
10926 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10927 for EVEX.W bit ignored instructions\n"));
10928 fprintf (stream, _("\
10929 -mevexrcig=[rne|rd|ru|rz]\n\
10930 encode EVEX instructions with specific EVEX.RC value\n\
10931 for SAE-only ignored instructions\n"));
10932 fprintf (stream, _("\
10933 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10934 fprintf (stream, _("\
10935 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10936 fprintf (stream, _("\
10937 -mindex-reg support pseudo index registers\n"));
10938 fprintf (stream, _("\
10939 -mnaked-reg don't require `%%' prefix for registers\n"));
10940 fprintf (stream, _("\
10941 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10942 fprintf (stream, _("\
10943 -mshared disable branch optimization for shared code\n"));
10944 # if defined (TE_PE) || defined (TE_PEP)
10945 fprintf (stream, _("\
10946 -mbig-obj generate big object files\n"));
10948 fprintf (stream, _("\
10949 -momit-lock-prefix=[no|yes]\n\
10950 strip all lock prefixes\n"));
10951 fprintf (stream, _("\
10952 -mfence-as-lock-add=[no|yes]\n\
10953 encode lfence, mfence and sfence as\n\
10954 lock addl $0x0, (%%{re}sp)\n"));
10955 fprintf (stream, _("\
10956 -mrelax-relocations=[no|yes]\n\
10957 generate relax relocations\n"));
10958 fprintf (stream, _("\
10959 -mamd64 accept only AMD64 ISA\n"));
10960 fprintf (stream, _("\
10961 -mintel64 accept only Intel64 ISA\n"));
10964 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10965 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10966 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10968 /* Pick the target format to use. */
10971 i386_target_format (void)
10973 if (!strncmp (default_arch, "x86_64", 6))
10975 update_code_flag (CODE_64BIT, 1);
10976 if (default_arch[6] == '\0')
10977 x86_elf_abi = X86_64_ABI;
10979 x86_elf_abi = X86_64_X32_ABI;
10981 else if (!strcmp (default_arch, "i386"))
10982 update_code_flag (CODE_32BIT, 1);
10983 else if (!strcmp (default_arch, "iamcu"))
10985 update_code_flag (CODE_32BIT, 1);
10986 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10988 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10989 cpu_arch_name = "iamcu";
10990 cpu_sub_arch_name = NULL;
10991 cpu_arch_flags = iamcu_flags;
10992 cpu_arch_isa = PROCESSOR_IAMCU;
10993 cpu_arch_isa_flags = iamcu_flags;
10994 if (!cpu_arch_tune_set)
10996 cpu_arch_tune = cpu_arch_isa;
10997 cpu_arch_tune_flags = cpu_arch_isa_flags;
11000 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11001 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11005 as_fatal (_("unknown architecture"));
11007 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11008 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11009 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11010 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11012 switch (OUTPUT_FLAVOR)
11014 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11015 case bfd_target_aout_flavour:
11016 return AOUT_TARGET_FORMAT;
11018 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11019 # if defined (TE_PE) || defined (TE_PEP)
11020 case bfd_target_coff_flavour:
11021 if (flag_code == CODE_64BIT)
11022 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11025 # elif defined (TE_GO32)
11026 case bfd_target_coff_flavour:
11027 return "coff-go32";
11029 case bfd_target_coff_flavour:
11030 return "coff-i386";
11033 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11034 case bfd_target_elf_flavour:
11036 const char *format;
11038 switch (x86_elf_abi)
11041 format = ELF_TARGET_FORMAT;
11044 use_rela_relocations = 1;
11046 format = ELF_TARGET_FORMAT64;
11048 case X86_64_X32_ABI:
11049 use_rela_relocations = 1;
11051 disallow_64bit_reloc = 1;
11052 format = ELF_TARGET_FORMAT32;
11055 if (cpu_arch_isa == PROCESSOR_L1OM)
11057 if (x86_elf_abi != X86_64_ABI)
11058 as_fatal (_("Intel L1OM is 64bit only"));
11059 return ELF_TARGET_L1OM_FORMAT;
11061 else if (cpu_arch_isa == PROCESSOR_K1OM)
11063 if (x86_elf_abi != X86_64_ABI)
11064 as_fatal (_("Intel K1OM is 64bit only"));
11065 return ELF_TARGET_K1OM_FORMAT;
11067 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11069 if (x86_elf_abi != I386_ABI)
11070 as_fatal (_("Intel MCU is 32bit only"));
11071 return ELF_TARGET_IAMCU_FORMAT;
11077 #if defined (OBJ_MACH_O)
11078 case bfd_target_mach_o_flavour:
11079 if (flag_code == CODE_64BIT)
11081 use_rela_relocations = 1;
11083 return "mach-o-x86-64";
11086 return "mach-o-i386";
11094 #endif /* OBJ_MAYBE_ more than one */
11097 md_undefined_symbol (char *name)
11099 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11100 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11101 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11102 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11106 if (symbol_find (name))
11107 as_bad (_("GOT already in symbol table"));
11108 GOT_symbol = symbol_new (name, undefined_section,
11109 (valueT) 0, &zero_address_frag);
11116 /* Round up a section size to the appropriate boundary. */
11119 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11121 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11122 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11124 /* For a.out, force the section size to be aligned. If we don't do
11125 this, BFD will align it for us, but it will not write out the
11126 final bytes of the section. This may be a bug in BFD, but it is
11127 easier to fix it here since that is how the other a.out targets
11131 align = bfd_get_section_alignment (stdoutput, segment);
11132 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11139 /* On the i386, PC-relative offsets are relative to the start of the
11140 next instruction. That is, the address of the offset, plus its
11141 size, since the offset is always the last part of the insn. */
11144 md_pcrel_from (fixS *fixP)
11146 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11152 s_bss (int ignore ATTRIBUTE_UNUSED)
11156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11158 obj_elf_section_change_hook ();
11160 temp = get_absolute_expression ();
11161 subseg_set (bss_section, (subsegT) temp);
11162 demand_empty_rest_of_line ();
11168 i386_validate_fix (fixS *fixp)
11170 if (fixp->fx_subsy)
11172 if (fixp->fx_subsy == GOT_symbol)
11174 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11179 if (fixp->fx_tcbit2)
11180 fixp->fx_r_type = (fixp->fx_tcbit
11181 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11182 : BFD_RELOC_X86_64_GOTPCRELX);
11185 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11190 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11192 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11194 fixp->fx_subsy = 0;
11197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11198 else if (!object_64bit)
11200 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11201 && fixp->fx_tcbit2)
11202 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11208 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11211 bfd_reloc_code_real_type code;
11213 switch (fixp->fx_r_type)
11215 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11216 case BFD_RELOC_SIZE32:
11217 case BFD_RELOC_SIZE64:
11218 if (S_IS_DEFINED (fixp->fx_addsy)
11219 && !S_IS_EXTERNAL (fixp->fx_addsy))
11221 /* Resolve size relocation against local symbol to size of
11222 the symbol plus addend. */
11223 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11224 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11225 && !fits_in_unsigned_long (value))
11226 as_bad_where (fixp->fx_file, fixp->fx_line,
11227 _("symbol size computation overflow"));
11228 fixp->fx_addsy = NULL;
11229 fixp->fx_subsy = NULL;
11230 md_apply_fix (fixp, (valueT *) &value, NULL);
11234 /* Fall through. */
11236 case BFD_RELOC_X86_64_PLT32:
11237 case BFD_RELOC_X86_64_GOT32:
11238 case BFD_RELOC_X86_64_GOTPCREL:
11239 case BFD_RELOC_X86_64_GOTPCRELX:
11240 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11241 case BFD_RELOC_386_PLT32:
11242 case BFD_RELOC_386_GOT32:
11243 case BFD_RELOC_386_GOT32X:
11244 case BFD_RELOC_386_GOTOFF:
11245 case BFD_RELOC_386_GOTPC:
11246 case BFD_RELOC_386_TLS_GD:
11247 case BFD_RELOC_386_TLS_LDM:
11248 case BFD_RELOC_386_TLS_LDO_32:
11249 case BFD_RELOC_386_TLS_IE_32:
11250 case BFD_RELOC_386_TLS_IE:
11251 case BFD_RELOC_386_TLS_GOTIE:
11252 case BFD_RELOC_386_TLS_LE_32:
11253 case BFD_RELOC_386_TLS_LE:
11254 case BFD_RELOC_386_TLS_GOTDESC:
11255 case BFD_RELOC_386_TLS_DESC_CALL:
11256 case BFD_RELOC_X86_64_TLSGD:
11257 case BFD_RELOC_X86_64_TLSLD:
11258 case BFD_RELOC_X86_64_DTPOFF32:
11259 case BFD_RELOC_X86_64_DTPOFF64:
11260 case BFD_RELOC_X86_64_GOTTPOFF:
11261 case BFD_RELOC_X86_64_TPOFF32:
11262 case BFD_RELOC_X86_64_TPOFF64:
11263 case BFD_RELOC_X86_64_GOTOFF64:
11264 case BFD_RELOC_X86_64_GOTPC32:
11265 case BFD_RELOC_X86_64_GOT64:
11266 case BFD_RELOC_X86_64_GOTPCREL64:
11267 case BFD_RELOC_X86_64_GOTPC64:
11268 case BFD_RELOC_X86_64_GOTPLT64:
11269 case BFD_RELOC_X86_64_PLTOFF64:
11270 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11271 case BFD_RELOC_X86_64_TLSDESC_CALL:
11272 case BFD_RELOC_RVA:
11273 case BFD_RELOC_VTABLE_ENTRY:
11274 case BFD_RELOC_VTABLE_INHERIT:
11276 case BFD_RELOC_32_SECREL:
11278 code = fixp->fx_r_type;
11280 case BFD_RELOC_X86_64_32S:
11281 if (!fixp->fx_pcrel)
11283 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11284 code = fixp->fx_r_type;
11287 /* Fall through. */
11289 if (fixp->fx_pcrel)
11291 switch (fixp->fx_size)
11294 as_bad_where (fixp->fx_file, fixp->fx_line,
11295 _("can not do %d byte pc-relative relocation"),
11297 code = BFD_RELOC_32_PCREL;
11299 case 1: code = BFD_RELOC_8_PCREL; break;
11300 case 2: code = BFD_RELOC_16_PCREL; break;
11301 case 4: code = BFD_RELOC_32_PCREL; break;
11303 case 8: code = BFD_RELOC_64_PCREL; break;
11309 switch (fixp->fx_size)
11312 as_bad_where (fixp->fx_file, fixp->fx_line,
11313 _("can not do %d byte relocation"),
11315 code = BFD_RELOC_32;
11317 case 1: code = BFD_RELOC_8; break;
11318 case 2: code = BFD_RELOC_16; break;
11319 case 4: code = BFD_RELOC_32; break;
11321 case 8: code = BFD_RELOC_64; break;
11328 if ((code == BFD_RELOC_32
11329 || code == BFD_RELOC_32_PCREL
11330 || code == BFD_RELOC_X86_64_32S)
11332 && fixp->fx_addsy == GOT_symbol)
11335 code = BFD_RELOC_386_GOTPC;
11337 code = BFD_RELOC_X86_64_GOTPC32;
11339 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11341 && fixp->fx_addsy == GOT_symbol)
11343 code = BFD_RELOC_X86_64_GOTPC64;
11346 rel = XNEW (arelent);
11347 rel->sym_ptr_ptr = XNEW (asymbol *);
11348 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11350 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11352 if (!use_rela_relocations)
11354 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11355 vtable entry to be used in the relocation's section offset. */
11356 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11357 rel->address = fixp->fx_offset;
11358 #if defined (OBJ_COFF) && defined (TE_PE)
11359 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11360 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11365 /* Use the rela in 64bit mode. */
11368 if (disallow_64bit_reloc)
11371 case BFD_RELOC_X86_64_DTPOFF64:
11372 case BFD_RELOC_X86_64_TPOFF64:
11373 case BFD_RELOC_64_PCREL:
11374 case BFD_RELOC_X86_64_GOTOFF64:
11375 case BFD_RELOC_X86_64_GOT64:
11376 case BFD_RELOC_X86_64_GOTPCREL64:
11377 case BFD_RELOC_X86_64_GOTPC64:
11378 case BFD_RELOC_X86_64_GOTPLT64:
11379 case BFD_RELOC_X86_64_PLTOFF64:
11380 as_bad_where (fixp->fx_file, fixp->fx_line,
11381 _("cannot represent relocation type %s in x32 mode"),
11382 bfd_get_reloc_code_name (code));
11388 if (!fixp->fx_pcrel)
11389 rel->addend = fixp->fx_offset;
11393 case BFD_RELOC_X86_64_PLT32:
11394 case BFD_RELOC_X86_64_GOT32:
11395 case BFD_RELOC_X86_64_GOTPCREL:
11396 case BFD_RELOC_X86_64_GOTPCRELX:
11397 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11398 case BFD_RELOC_X86_64_TLSGD:
11399 case BFD_RELOC_X86_64_TLSLD:
11400 case BFD_RELOC_X86_64_GOTTPOFF:
11401 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11402 case BFD_RELOC_X86_64_TLSDESC_CALL:
11403 rel->addend = fixp->fx_offset - fixp->fx_size;
11406 rel->addend = (section->vma
11408 + fixp->fx_addnumber
11409 + md_pcrel_from (fixp));
11414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11415 if (rel->howto == NULL)
11417 as_bad_where (fixp->fx_file, fixp->fx_line,
11418 _("cannot represent relocation type %s"),
11419 bfd_get_reloc_code_name (code));
11420 /* Set howto to a garbage value so that we can keep going. */
11421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11422 gas_assert (rel->howto != NULL);
11428 #include "tc-i386-intel.c"
11431 tc_x86_parse_to_dw2regnum (expressionS *exp)
11433 int saved_naked_reg;
11434 char saved_register_dot;
11436 saved_naked_reg = allow_naked_reg;
11437 allow_naked_reg = 1;
11438 saved_register_dot = register_chars['.'];
11439 register_chars['.'] = '.';
11440 allow_pseudo_reg = 1;
11441 expression_and_evaluate (exp);
11442 allow_pseudo_reg = 0;
11443 register_chars['.'] = saved_register_dot;
11444 allow_naked_reg = saved_naked_reg;
11446 if (exp->X_op == O_register && exp->X_add_number >= 0)
11448 if ((addressT) exp->X_add_number < i386_regtab_size)
11450 exp->X_op = O_constant;
11451 exp->X_add_number = i386_regtab[exp->X_add_number]
11452 .dw2_regnum[flag_code >> 1];
11455 exp->X_op = O_illegal;
11460 tc_x86_frame_initial_instructions (void)
11462 static unsigned int sp_regno[2];
11464 if (!sp_regno[flag_code >> 1])
11466 char *saved_input = input_line_pointer;
11467 char sp[][4] = {"esp", "rsp"};
11470 input_line_pointer = sp[flag_code >> 1];
11471 tc_x86_parse_to_dw2regnum (&exp);
11472 gas_assert (exp.X_op == O_constant);
11473 sp_regno[flag_code >> 1] = exp.X_add_number;
11474 input_line_pointer = saved_input;
11477 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11478 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11482 x86_dwarf2_addr_size (void)
11484 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11485 if (x86_elf_abi == X86_64_X32_ABI)
11488 return bfd_arch_bits_per_address (stdoutput) / 8;
11492 i386_elf_section_type (const char *str, size_t len)
11494 if (flag_code == CODE_64BIT
11495 && len == sizeof ("unwind") - 1
11496 && strncmp (str, "unwind", 6) == 0)
11497 return SHT_X86_64_UNWIND;
11504 i386_solaris_fix_up_eh_frame (segT sec)
11506 if (flag_code == CODE_64BIT)
11507 elf_section_type (sec) = SHT_X86_64_UNWIND;
11513 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11517 exp.X_op = O_secrel;
11518 exp.X_add_symbol = symbol;
11519 exp.X_add_number = 0;
11520 emit_expr (&exp, size);
11524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11525 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11528 x86_64_section_letter (int letter, const char **ptr_msg)
11530 if (flag_code == CODE_64BIT)
11533 return SHF_X86_64_LARGE;
11535 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11538 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11543 x86_64_section_word (char *str, size_t len)
11545 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11546 return SHF_X86_64_LARGE;
11552 handle_large_common (int small ATTRIBUTE_UNUSED)
11554 if (flag_code != CODE_64BIT)
11556 s_comm_internal (0, elf_common_parse);
11557 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11561 static segT lbss_section;
11562 asection *saved_com_section_ptr = elf_com_section_ptr;
11563 asection *saved_bss_section = bss_section;
11565 if (lbss_section == NULL)
11567 flagword applicable;
11568 segT seg = now_seg;
11569 subsegT subseg = now_subseg;
11571 /* The .lbss section is for local .largecomm symbols. */
11572 lbss_section = subseg_new (".lbss", 0);
11573 applicable = bfd_applicable_section_flags (stdoutput);
11574 bfd_set_section_flags (stdoutput, lbss_section,
11575 applicable & SEC_ALLOC);
11576 seg_info (lbss_section)->bss = 1;
11578 subseg_set (seg, subseg);
11581 elf_com_section_ptr = &_bfd_elf_large_com_section;
11582 bss_section = lbss_section;
11584 s_comm_internal (0, elf_common_parse);
11586 elf_com_section_ptr = saved_com_section_ptr;
11587 bss_section = saved_bss_section;
11590 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */