1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void optimize_imm PARAMS ((void));
93 static void optimize_disp PARAMS ((void));
94 static int match_template PARAMS ((void));
95 static int check_string PARAMS ((void));
96 static int process_suffix PARAMS ((void));
97 static int check_byte_reg PARAMS ((void));
98 static int check_long_reg PARAMS ((void));
99 static int check_qword_reg PARAMS ((void));
100 static int check_word_reg PARAMS ((void));
101 static int finalize_imm PARAMS ((void));
102 static int process_operands PARAMS ((void));
103 static const seg_entry *build_modrm_byte PARAMS ((void));
104 static void output_insn PARAMS ((void));
105 static void output_branch PARAMS ((void));
106 static void output_jump PARAMS ((void));
107 static void output_interseg_jump PARAMS ((void));
108 static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110 static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
113 static void s_bss PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED);
119 static const char *default_arch = DEFAULT_ARCH;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry *regs;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types[MAX_OPERANDS];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op[MAX_OPERANDS];
156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry *seg[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_GNU) \
202 && !defined (TE_LINUX) \
203 && !defined (TE_NETWARE) \
204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
206 /* This array holds the chars that always start a comment. If the
207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209 const char *i386_comment_chars = "#/";
210 #define SVR4_COMMENT_CHARS 1
211 #define PREFIX_SEPARATOR '\\'
214 const char *i386_comment_chars = "#";
215 #define PREFIX_SEPARATOR '/'
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
225 '/' isn't otherwise defined. */
226 const char line_comment_chars[] = "#/";
228 const char line_separator_chars[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point
232 const char EXP_CHARS[] = "eE";
234 /* Chars that mean this number is a floating point constant
237 const char FLT_CHARS[] = "fFdDxX";
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars[256];
241 static char register_chars[256];
242 static char operand_chars[256];
243 static char identifier_chars[256];
244 static char digit_chars[256];
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack[32];
262 static char *save_stack_p;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
268 /* The instruction we're assembling. */
271 /* Possible templates for current insn. */
272 static const templates *current_templates;
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions[2], im_expressions[2];
277 /* Current operand we are working on. */
278 static int this_operand;
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
289 static enum flag_code flag_code;
290 static unsigned int object_64bit;
291 static int use_rela_relocations = 0;
293 /* The names used to print error messages. */
294 static const char *flag_code_names[] =
301 /* 1 for intel syntax,
303 static int intel_syntax = 0;
305 /* 1 if register prefix % not required. */
306 static int allow_naked_reg = 0;
308 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311 static char stackop_size = '\0';
313 /* Non-zero to optimize code alignment. */
314 int optimize_align_code = 1;
316 /* Non-zero to quieten some warnings. */
317 static int quiet_warnings = 0;
320 static const char *cpu_arch_name = NULL;
321 static const char *cpu_sub_arch_name = NULL;
323 /* CPU feature flags. */
324 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
326 /* If we have selected a cpu we are generating instructions for. */
327 static int cpu_arch_tune_set = 0;
329 /* Cpu we are generating instructions for. */
330 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332 /* CPU feature flags of cpu we are generating instructions for. */
333 static unsigned int cpu_arch_tune_flags = 0;
335 /* CPU instruction set architecture used. */
336 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338 /* CPU feature flags of instruction set architecture used. */
339 static unsigned int cpu_arch_isa_flags = 0;
341 /* If set, conditional jumps are not automatically promoted to handle
342 larger than a byte offset. */
343 static unsigned int no_cond_jump_promotion = 0;
345 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
346 static symbolS *GOT_symbol;
348 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
349 unsigned int x86_dwarf2_return_column;
351 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
352 int x86_cie_data_alignment;
354 /* Interface to relax_segment.
355 There are 3 major relax states for 386 jump insns because the
356 different types of jumps add different sizes to frags when we're
357 figuring out what sort of jump to choose to reach a given label. */
360 #define UNCOND_JUMP 0
362 #define COND_JUMP86 2
367 #define SMALL16 (SMALL | CODE16)
369 #define BIG16 (BIG | CODE16)
373 #define INLINE __inline__
379 #define ENCODE_RELAX_STATE(type, size) \
380 ((relax_substateT) (((type) << 2) | (size)))
381 #define TYPE_FROM_RELAX_STATE(s) \
383 #define DISP_SIZE_FROM_RELAX_STATE(s) \
384 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
386 /* This table is used by relax_frag to promote short jumps to long
387 ones where necessary. SMALL (short) jumps may be promoted to BIG
388 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
389 don't allow a short jump in a 32 bit code segment to be promoted to
390 a 16 bit offset jump because it's slower (requires data size
391 prefix), and doesn't work, unless the destination is in the bottom
392 64k of the code segment (The top 16 bits of eip are zeroed). */
394 const relax_typeS md_relax_table[] =
397 1) most positive reach of this state,
398 2) most negative reach of this state,
399 3) how many bytes this mode will have in the variable part of the frag
400 4) which index into the table to try if we can't fit into this one. */
402 /* UNCOND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
405 /* dword jmp adds 4 bytes to frag:
406 0 extra opcode bytes, 4 displacement bytes. */
408 /* word jmp adds 2 byte2 to frag:
409 0 extra opcode bytes, 2 displacement bytes. */
412 /* COND_JUMP states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
418 /* word conditionals add 3 bytes to frag:
419 1 extra opcode byte, 2 displacement bytes. */
422 /* COND_JUMP86 states. */
423 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
425 /* dword conditionals adds 5 bytes to frag:
426 1 extra opcode byte, 4 displacement bytes. */
428 /* word conditionals add 4 bytes to frag:
429 1 displacement byte and a 3 byte long branch insn. */
433 static const arch_entry cpu_arch[] =
435 {"generic32", PROCESSOR_GENERIC32,
436 Cpu086|Cpu186|Cpu286|Cpu386},
437 {"generic64", PROCESSOR_GENERIC64,
438 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
439 |CpuMMX2|CpuSSE|CpuSSE2},
440 {"i8086", PROCESSOR_UNKNOWN,
442 {"i186", PROCESSOR_UNKNOWN,
444 {"i286", PROCESSOR_UNKNOWN,
445 Cpu086|Cpu186|Cpu286},
446 {"i386", PROCESSOR_GENERIC32,
447 Cpu086|Cpu186|Cpu286|Cpu386},
448 {"i486", PROCESSOR_I486,
449 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
450 {"i586", PROCESSOR_PENTIUM,
451 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
452 {"i686", PROCESSOR_PENTIUMPRO,
453 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
454 {"pentium", PROCESSOR_PENTIUM,
455 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
456 {"pentiumpro",PROCESSOR_PENTIUMPRO,
457 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
458 {"pentiumii", PROCESSOR_PENTIUMPRO,
459 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
460 {"pentiumiii",PROCESSOR_PENTIUMPRO,
461 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
463 {"pentium4", PROCESSOR_PENTIUM4,
464 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
467 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
470 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
472 {"yonah", PROCESSOR_YONAH,
473 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
475 {"merom", PROCESSOR_MEROM,
476 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
479 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
480 {"k6_2", PROCESSOR_K6,
481 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
482 {"athlon", PROCESSOR_ATHLON,
483 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
484 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
485 {"sledgehammer", PROCESSOR_K8,
486 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"opteron", PROCESSOR_K8,
489 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
490 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
492 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {".mmx", PROCESSOR_UNKNOWN,
496 {".sse", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE},
498 {".sse2", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
500 {".sse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
502 {".3dnow", PROCESSOR_UNKNOWN,
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
508 {".pacifica", PROCESSOR_UNKNOWN,
510 {".svme", PROCESSOR_UNKNOWN,
514 const pseudo_typeS md_pseudo_table[] =
516 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
517 {"align", s_align_bytes, 0},
519 {"align", s_align_ptwo, 0},
521 {"arch", set_cpu_arch, 0},
525 {"ffloat", float_cons, 'f'},
526 {"dfloat", float_cons, 'd'},
527 {"tfloat", float_cons, 'x'},
529 {"slong", signed_cons, 4},
530 {"noopt", s_ignore, 0},
531 {"optim", s_ignore, 0},
532 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
533 {"code16", set_code_flag, CODE_16BIT},
534 {"code32", set_code_flag, CODE_32BIT},
535 {"code64", set_code_flag, CODE_64BIT},
536 {"intel_syntax", set_intel_syntax, 1},
537 {"att_syntax", set_intel_syntax, 0},
538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
539 {"largecomm", handle_large_common, 0},
541 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
542 {"loc", dwarf2_directive_loc, 0},
543 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
546 {"secrel32", pe_directive_secrel, 0},
551 /* For interface with expression (). */
552 extern char *input_line_pointer;
554 /* Hash table for instruction mnemonic lookup. */
555 static struct hash_control *op_hash;
557 /* Hash table for register lookup. */
558 static struct hash_control *reg_hash;
561 i386_align_code (fragP, count)
565 /* Various efficient no-op patterns for aligning code labels.
566 Note: Don't try to assemble the instructions in the comments.
567 0L and 0w are not legal. */
568 static const char f32_1[] =
570 static const char f32_2[] =
571 {0x66,0x90}; /* xchg %ax,%ax */
572 static const char f32_3[] =
573 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
574 static const char f32_4[] =
575 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_5[] =
578 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_6[] =
580 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
581 static const char f32_7[] =
582 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_8[] =
585 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_9[] =
587 {0x89,0xf6, /* movl %esi,%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_10[] =
590 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_11[] =
593 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_12[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
598 static const char f32_13[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_14[] =
602 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f32_15[] =
605 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
606 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
607 static const char f16_3[] =
608 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
609 static const char f16_4[] =
610 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
611 static const char f16_5[] =
613 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_6[] =
615 {0x89,0xf6, /* mov %si,%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char f16_7[] =
618 {0x8d,0x74,0x00, /* lea 0(%si),%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_8[] =
621 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char *const f32_patt[] = {
624 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
625 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
627 static const char *const f16_patt[] = {
628 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
629 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
632 static const char alt_3[] =
634 /* nopl 0(%[re]ax) */
635 static const char alt_4[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11[] =
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14[] =
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15[] =
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
712 static const char alt_short_13[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 static const char alt_short_14[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt[] = {
726 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
727 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
728 alt_short_14, alt_short_15
730 static const char *const alt_long_patt[] = {
731 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
732 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
733 alt_long_14, alt_long_15
736 if (count <= 0 || count > 15)
739 /* We need to decide which NOP sequence to use for 32bit and
740 64bit. When -mtune= is used:
742 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
743 f32_patt will be used.
744 2. For PROCESSOR_K8 in 64bit, NOPs with 0x66 prefixe will be used.
745 3. For PROCESSOR_MEROM, alt_long_patt will be used.
746 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
747 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
748 and PROCESSOR_GENERIC64, alt_short_patt will be used.
750 When -mtune= isn't used, alt_short_patt will be used if
751 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
753 When -march= or .arch is used, we can't use anything beyond
754 cpu_arch_isa_flags. */
756 if (flag_code == CODE_16BIT)
758 memcpy (fragP->fr_literal + fragP->fr_fix,
759 f16_patt[count - 1], count);
761 /* Adjust jump offset. */
762 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
764 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
767 int nnops = (count + 3) / 4;
768 int len = count / nnops;
769 int remains = count - nnops * len;
772 /* The recommended way to pad 64bit code is to use NOPs preceded
773 by maximally four 0x66 prefixes. Balance the size of nops. */
774 for (i = 0; i < remains; i++)
776 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
777 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
780 for (; i < nnops; i++)
782 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
783 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
789 const char *const *patt = NULL;
791 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
793 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
794 switch (cpu_arch_tune)
796 case PROCESSOR_UNKNOWN:
797 /* We use cpu_arch_isa_flags to check if we SHOULD
798 optimize for Cpu686. */
799 if ((cpu_arch_isa_flags & Cpu686) != 0)
800 patt = alt_short_patt;
804 case PROCESSOR_MEROM:
805 patt = alt_long_patt;
807 case PROCESSOR_PENTIUMPRO:
808 case PROCESSOR_PENTIUM4:
809 case PROCESSOR_NOCONA:
810 case PROCESSOR_YONAH:
812 case PROCESSOR_ATHLON:
814 case PROCESSOR_GENERIC64:
815 patt = alt_short_patt;
818 case PROCESSOR_PENTIUM:
819 case PROCESSOR_GENERIC32:
826 switch (cpu_arch_tune)
828 case PROCESSOR_UNKNOWN:
829 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
830 PROCESSOR_UNKNOWN. */
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_PENTIUMPRO:
837 case PROCESSOR_PENTIUM4:
838 case PROCESSOR_NOCONA:
839 case PROCESSOR_YONAH:
841 case PROCESSOR_ATHLON:
843 case PROCESSOR_GENERIC32:
844 /* We use cpu_arch_isa_flags to check if we CAN optimize
846 if ((cpu_arch_isa_flags & Cpu686) != 0)
847 patt = alt_short_patt;
851 case PROCESSOR_MEROM:
852 if ((cpu_arch_isa_flags & Cpu686) != 0)
853 patt = alt_long_patt;
857 case PROCESSOR_GENERIC64:
858 patt = alt_short_patt;
863 memcpy (fragP->fr_literal + fragP->fr_fix,
864 patt[count - 1], count);
866 fragP->fr_var = count;
869 static INLINE unsigned int
870 mode_from_disp_size (t)
873 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
877 fits_in_signed_byte (num)
880 return (num >= -128) && (num <= 127);
884 fits_in_unsigned_byte (num)
887 return (num & 0xff) == num;
891 fits_in_unsigned_word (num)
894 return (num & 0xffff) == num;
898 fits_in_signed_word (num)
901 return (-32768 <= num) && (num <= 32767);
904 fits_in_signed_long (num)
905 offsetT num ATTRIBUTE_UNUSED;
910 return (!(((offsetT) -1 << 31) & num)
911 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
913 } /* fits_in_signed_long() */
915 fits_in_unsigned_long (num)
916 offsetT num ATTRIBUTE_UNUSED;
921 return (num & (((offsetT) 2 << 31) - 1)) == num;
923 } /* fits_in_unsigned_long() */
926 smallest_imm_type (num)
929 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
931 /* This code is disabled on the 486 because all the Imm1 forms
932 in the opcode table are slower on the i486. They're the
933 versions with the implicitly specified single-position
934 displacement, which has another syntax if you really want to
937 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
939 return (fits_in_signed_byte (num)
940 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
941 : fits_in_unsigned_byte (num)
942 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
943 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
944 ? (Imm16 | Imm32 | Imm32S | Imm64)
945 : fits_in_signed_long (num)
946 ? (Imm32 | Imm32S | Imm64)
947 : fits_in_unsigned_long (num)
953 offset_in_range (val, size)
961 case 1: mask = ((addressT) 1 << 8) - 1; break;
962 case 2: mask = ((addressT) 1 << 16) - 1; break;
963 case 4: mask = ((addressT) 2 << 31) - 1; break;
965 case 8: mask = ((addressT) 2 << 63) - 1; break;
970 /* If BFD64, sign extend val. */
971 if (!use_rela_relocations)
972 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
973 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
975 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
977 char buf1[40], buf2[40];
979 sprint_value (buf1, val);
980 sprint_value (buf2, val & mask);
981 as_warn (_("%s shortened to %s"), buf1, buf2);
986 /* Returns 0 if attempting to add a prefix where one from the same
987 class already exists, 1 if non rep/repne added, 2 if rep/repne
996 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
997 && flag_code == CODE_64BIT)
999 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1000 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1001 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1012 case CS_PREFIX_OPCODE:
1013 case DS_PREFIX_OPCODE:
1014 case ES_PREFIX_OPCODE:
1015 case FS_PREFIX_OPCODE:
1016 case GS_PREFIX_OPCODE:
1017 case SS_PREFIX_OPCODE:
1021 case REPNE_PREFIX_OPCODE:
1022 case REPE_PREFIX_OPCODE:
1025 case LOCK_PREFIX_OPCODE:
1033 case ADDR_PREFIX_OPCODE:
1037 case DATA_PREFIX_OPCODE:
1041 if (i.prefix[q] != 0)
1049 i.prefix[q] |= prefix;
1052 as_bad (_("same type of prefix used twice"));
1058 set_code_flag (value)
1062 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1063 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1064 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1066 as_bad (_("64bit mode not supported on this CPU."));
1068 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1070 as_bad (_("32bit mode not supported on this CPU."));
1072 stackop_size = '\0';
1076 set_16bit_gcc_code_flag (new_code_flag)
1079 flag_code = new_code_flag;
1080 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1081 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1082 stackop_size = LONG_MNEM_SUFFIX;
1086 set_intel_syntax (syntax_flag)
1089 /* Find out if register prefixing is specified. */
1090 int ask_naked_reg = 0;
1093 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1095 char *string = input_line_pointer;
1096 int e = get_symbol_end ();
1098 if (strcmp (string, "prefix") == 0)
1100 else if (strcmp (string, "noprefix") == 0)
1103 as_bad (_("bad argument to syntax directive."));
1104 *input_line_pointer = e;
1106 demand_empty_rest_of_line ();
1108 intel_syntax = syntax_flag;
1110 if (ask_naked_reg == 0)
1111 allow_naked_reg = (intel_syntax
1112 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1114 allow_naked_reg = (ask_naked_reg < 0);
1116 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1117 identifier_chars['$'] = intel_syntax ? '$' : 0;
1121 set_cpu_arch (dummy)
1122 int dummy ATTRIBUTE_UNUSED;
1126 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1128 char *string = input_line_pointer;
1129 int e = get_symbol_end ();
1132 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1134 if (strcmp (string, cpu_arch[i].name) == 0)
1138 cpu_arch_name = cpu_arch[i].name;
1139 cpu_sub_arch_name = NULL;
1140 cpu_arch_flags = (cpu_arch[i].flags
1141 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1142 cpu_arch_isa = cpu_arch[i].type;
1143 cpu_arch_isa_flags = cpu_arch[i].flags;
1144 if (!cpu_arch_tune_set)
1146 cpu_arch_tune = cpu_arch_isa;
1147 cpu_arch_tune_flags = cpu_arch_isa_flags;
1151 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1153 cpu_sub_arch_name = cpu_arch[i].name;
1154 cpu_arch_flags |= cpu_arch[i].flags;
1156 *input_line_pointer = e;
1157 demand_empty_rest_of_line ();
1161 if (i >= ARRAY_SIZE (cpu_arch))
1162 as_bad (_("no such architecture: `%s'"), string);
1164 *input_line_pointer = e;
1167 as_bad (_("missing cpu architecture"));
1169 no_cond_jump_promotion = 0;
1170 if (*input_line_pointer == ','
1171 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1173 char *string = ++input_line_pointer;
1174 int e = get_symbol_end ();
1176 if (strcmp (string, "nojumps") == 0)
1177 no_cond_jump_promotion = 1;
1178 else if (strcmp (string, "jumps") == 0)
1181 as_bad (_("no such architecture modifier: `%s'"), string);
1183 *input_line_pointer = e;
1186 demand_empty_rest_of_line ();
1192 if (!strcmp (default_arch, "x86_64"))
1193 return bfd_mach_x86_64;
1194 else if (!strcmp (default_arch, "i386"))
1195 return bfd_mach_i386_i386;
1197 as_fatal (_("Unknown architecture"));
1203 const char *hash_err;
1205 /* Initialize op_hash hash table. */
1206 op_hash = hash_new ();
1209 const template *optab;
1210 templates *core_optab;
1212 /* Setup for loop. */
1214 core_optab = (templates *) xmalloc (sizeof (templates));
1215 core_optab->start = optab;
1220 if (optab->name == NULL
1221 || strcmp (optab->name, (optab - 1)->name) != 0)
1223 /* different name --> ship out current template list;
1224 add to hash table; & begin anew. */
1225 core_optab->end = optab;
1226 hash_err = hash_insert (op_hash,
1231 as_fatal (_("Internal Error: Can't hash %s: %s"),
1235 if (optab->name == NULL)
1237 core_optab = (templates *) xmalloc (sizeof (templates));
1238 core_optab->start = optab;
1243 /* Initialize reg_hash hash table. */
1244 reg_hash = hash_new ();
1246 const reg_entry *regtab;
1248 for (regtab = i386_regtab;
1249 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1252 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1254 as_fatal (_("Internal Error: Can't hash %s: %s"),
1260 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1265 for (c = 0; c < 256; c++)
1270 mnemonic_chars[c] = c;
1271 register_chars[c] = c;
1272 operand_chars[c] = c;
1274 else if (ISLOWER (c))
1276 mnemonic_chars[c] = c;
1277 register_chars[c] = c;
1278 operand_chars[c] = c;
1280 else if (ISUPPER (c))
1282 mnemonic_chars[c] = TOLOWER (c);
1283 register_chars[c] = mnemonic_chars[c];
1284 operand_chars[c] = c;
1287 if (ISALPHA (c) || ISDIGIT (c))
1288 identifier_chars[c] = c;
1291 identifier_chars[c] = c;
1292 operand_chars[c] = c;
1297 identifier_chars['@'] = '@';
1300 identifier_chars['?'] = '?';
1301 operand_chars['?'] = '?';
1303 digit_chars['-'] = '-';
1304 mnemonic_chars['-'] = '-';
1305 identifier_chars['_'] = '_';
1306 identifier_chars['.'] = '.';
1308 for (p = operand_special_chars; *p != '\0'; p++)
1309 operand_chars[(unsigned char) *p] = *p;
1312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1315 record_alignment (text_section, 2);
1316 record_alignment (data_section, 2);
1317 record_alignment (bss_section, 2);
1321 if (flag_code == CODE_64BIT)
1323 x86_dwarf2_return_column = 16;
1324 x86_cie_data_alignment = -8;
1328 x86_dwarf2_return_column = 8;
1329 x86_cie_data_alignment = -4;
1334 i386_print_statistics (file)
1337 hash_print_statistics (file, "i386 opcode", op_hash);
1338 hash_print_statistics (file, "i386 register", reg_hash);
1343 /* Debugging routines for md_assemble. */
1344 static void pi PARAMS ((char *, i386_insn *));
1345 static void pte PARAMS ((template *));
1346 static void pt PARAMS ((unsigned int));
1347 static void pe PARAMS ((expressionS *));
1348 static void ps PARAMS ((symbolS *));
1357 fprintf (stdout, "%s: template ", line);
1359 fprintf (stdout, " address: base %s index %s scale %x\n",
1360 x->base_reg ? x->base_reg->reg_name : "none",
1361 x->index_reg ? x->index_reg->reg_name : "none",
1362 x->log2_scale_factor);
1363 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1364 x->rm.mode, x->rm.reg, x->rm.regmem);
1365 fprintf (stdout, " sib: base %x index %x scale %x\n",
1366 x->sib.base, x->sib.index, x->sib.scale);
1367 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1368 (x->rex & REX_MODE64) != 0,
1369 (x->rex & REX_EXTX) != 0,
1370 (x->rex & REX_EXTY) != 0,
1371 (x->rex & REX_EXTZ) != 0);
1372 for (i = 0; i < x->operands; i++)
1374 fprintf (stdout, " #%d: ", i + 1);
1376 fprintf (stdout, "\n");
1378 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1379 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1380 if (x->types[i] & Imm)
1382 if (x->types[i] & Disp)
1383 pe (x->op[i].disps);
1392 fprintf (stdout, " %d operands ", t->operands);
1393 fprintf (stdout, "opcode %x ", t->base_opcode);
1394 if (t->extension_opcode != None)
1395 fprintf (stdout, "ext %x ", t->extension_opcode);
1396 if (t->opcode_modifier & D)
1397 fprintf (stdout, "D");
1398 if (t->opcode_modifier & W)
1399 fprintf (stdout, "W");
1400 fprintf (stdout, "\n");
1401 for (i = 0; i < t->operands; i++)
1403 fprintf (stdout, " #%d type ", i + 1);
1404 pt (t->operand_types[i]);
1405 fprintf (stdout, "\n");
1413 fprintf (stdout, " operation %d\n", e->X_op);
1414 fprintf (stdout, " add_number %ld (%lx)\n",
1415 (long) e->X_add_number, (long) e->X_add_number);
1416 if (e->X_add_symbol)
1418 fprintf (stdout, " add_symbol ");
1419 ps (e->X_add_symbol);
1420 fprintf (stdout, "\n");
1424 fprintf (stdout, " op_symbol ");
1425 ps (e->X_op_symbol);
1426 fprintf (stdout, "\n");
1434 fprintf (stdout, "%s type %s%s",
1436 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1437 segment_name (S_GET_SEGMENT (s)));
1440 static struct type_name
1445 const type_names[] =
1458 { BaseIndex, "BaseIndex" },
1462 { Disp32S, "d32s" },
1464 { InOutPortReg, "InOutPortReg" },
1465 { ShiftCount, "ShiftCount" },
1466 { Control, "control reg" },
1467 { Test, "test reg" },
1468 { Debug, "debug reg" },
1469 { FloatReg, "FReg" },
1470 { FloatAcc, "FAcc" },
1474 { JumpAbsolute, "Jump Absolute" },
1485 const struct type_name *ty;
1487 for (ty = type_names; ty->mask; ty++)
1489 fprintf (stdout, "%s, ", ty->tname);
1493 #endif /* DEBUG386 */
1495 static bfd_reloc_code_real_type
1496 reloc (unsigned int size,
1499 bfd_reloc_code_real_type other)
1501 if (other != NO_RELOC)
1503 reloc_howto_type *reloc;
1508 case BFD_RELOC_X86_64_GOT32:
1509 return BFD_RELOC_X86_64_GOT64;
1511 case BFD_RELOC_X86_64_PLTOFF64:
1512 return BFD_RELOC_X86_64_PLTOFF64;
1514 case BFD_RELOC_X86_64_GOTPC32:
1515 other = BFD_RELOC_X86_64_GOTPC64;
1517 case BFD_RELOC_X86_64_GOTPCREL:
1518 other = BFD_RELOC_X86_64_GOTPCREL64;
1520 case BFD_RELOC_X86_64_TPOFF32:
1521 other = BFD_RELOC_X86_64_TPOFF64;
1523 case BFD_RELOC_X86_64_DTPOFF32:
1524 other = BFD_RELOC_X86_64_DTPOFF64;
1530 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1531 if (size == 4 && flag_code != CODE_64BIT)
1534 reloc = bfd_reloc_type_lookup (stdoutput, other);
1536 as_bad (_("unknown relocation (%u)"), other);
1537 else if (size != bfd_get_reloc_size (reloc))
1538 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1539 bfd_get_reloc_size (reloc),
1541 else if (pcrel && !reloc->pc_relative)
1542 as_bad (_("non-pc-relative relocation for pc-relative field"));
1543 else if ((reloc->complain_on_overflow == complain_overflow_signed
1545 || (reloc->complain_on_overflow == complain_overflow_unsigned
1547 as_bad (_("relocated field and relocation type differ in signedness"));
1556 as_bad (_("there are no unsigned pc-relative relocations"));
1559 case 1: return BFD_RELOC_8_PCREL;
1560 case 2: return BFD_RELOC_16_PCREL;
1561 case 4: return BFD_RELOC_32_PCREL;
1562 case 8: return BFD_RELOC_64_PCREL;
1564 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1571 case 4: return BFD_RELOC_X86_64_32S;
1576 case 1: return BFD_RELOC_8;
1577 case 2: return BFD_RELOC_16;
1578 case 4: return BFD_RELOC_32;
1579 case 8: return BFD_RELOC_64;
1581 as_bad (_("cannot do %s %u byte relocation"),
1582 sign > 0 ? "signed" : "unsigned", size);
1586 return BFD_RELOC_NONE;
1589 /* Here we decide which fixups can be adjusted to make them relative to
1590 the beginning of the section instead of the symbol. Basically we need
1591 to make sure that the dynamic relocations are done correctly, so in
1592 some cases we force the original symbol to be used. */
1595 tc_i386_fix_adjustable (fixP)
1596 fixS *fixP ATTRIBUTE_UNUSED;
1598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1602 /* Don't adjust pc-relative references to merge sections in 64-bit
1604 if (use_rela_relocations
1605 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1609 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1610 and changed later by validate_fix. */
1611 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1612 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1615 /* adjust_reloc_syms doesn't know about the GOT. */
1616 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1617 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1618 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1620 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1621 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1622 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1623 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1624 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1625 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1626 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1627 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1628 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1629 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1630 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1631 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1632 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1633 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1634 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1635 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1636 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1637 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1638 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1639 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1642 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1643 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1649 static int intel_float_operand PARAMS ((const char *mnemonic));
1652 intel_float_operand (mnemonic)
1653 const char *mnemonic;
1655 /* Note that the value returned is meaningful only for opcodes with (memory)
1656 operands, hence the code here is free to improperly handle opcodes that
1657 have no operands (for better performance and smaller code). */
1659 if (mnemonic[0] != 'f')
1660 return 0; /* non-math */
1662 switch (mnemonic[1])
1664 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1665 the fs segment override prefix not currently handled because no
1666 call path can make opcodes without operands get here */
1668 return 2 /* integer op */;
1670 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1671 return 3; /* fldcw/fldenv */
1674 if (mnemonic[2] != 'o' /* fnop */)
1675 return 3; /* non-waiting control op */
1678 if (mnemonic[2] == 's')
1679 return 3; /* frstor/frstpm */
1682 if (mnemonic[2] == 'a')
1683 return 3; /* fsave */
1684 if (mnemonic[2] == 't')
1686 switch (mnemonic[3])
1688 case 'c': /* fstcw */
1689 case 'd': /* fstdw */
1690 case 'e': /* fstenv */
1691 case 's': /* fsts[gw] */
1697 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1698 return 0; /* fxsave/fxrstor are not really math ops */
1705 /* This is the guts of the machine-dependent assembler. LINE points to a
1706 machine dependent instruction. This function is supposed to emit
1707 the frags/bytes it assembles to. */
1714 char mnemonic[MAX_MNEM_SIZE];
1716 /* Initialize globals. */
1717 memset (&i, '\0', sizeof (i));
1718 for (j = 0; j < MAX_OPERANDS; j++)
1719 i.reloc[j] = NO_RELOC;
1720 memset (disp_expressions, '\0', sizeof (disp_expressions));
1721 memset (im_expressions, '\0', sizeof (im_expressions));
1722 save_stack_p = save_stack;
1724 /* First parse an instruction mnemonic & call i386_operand for the operands.
1725 We assume that the scrubber has arranged it so that line[0] is the valid
1726 start of a (possibly prefixed) mnemonic. */
1728 line = parse_insn (line, mnemonic);
1732 line = parse_operands (line, mnemonic);
1736 /* Now we've parsed the mnemonic into a set of templates, and have the
1737 operands at hand. */
1739 /* All intel opcodes have reversed operands except for "bound" and
1740 "enter". We also don't reverse intersegment "jmp" and "call"
1741 instructions with 2 immediate operands so that the immediate segment
1742 precedes the offset, as it does when in AT&T mode. "enter" and the
1743 intersegment "jmp" and "call" instructions are the only ones that
1744 have two immediate operands. */
1745 if (intel_syntax && i.operands > 1
1746 && (strcmp (mnemonic, "bound") != 0)
1747 && (strcmp (mnemonic, "invlpga") != 0)
1748 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1754 /* Don't optimize displacement for movabs since it only takes 64bit
1757 && (flag_code != CODE_64BIT
1758 || strcmp (mnemonic, "movabs") != 0))
1761 /* Next, we find a template that matches the given insn,
1762 making sure the overlap of the given operands types is consistent
1763 with the template operand types. */
1765 if (!match_template ())
1770 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1772 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1773 i.tm.base_opcode ^= FloatR;
1775 /* Zap movzx and movsx suffix. The suffix may have been set from
1776 "word ptr" or "byte ptr" on the source operand, but we'll use
1777 the suffix later to choose the destination register. */
1778 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1780 if (i.reg_operands < 2
1782 && (~i.tm.opcode_modifier
1789 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1795 if (i.tm.opcode_modifier & FWait)
1796 if (!add_prefix (FWAIT_OPCODE))
1799 /* Check string instruction segment overrides. */
1800 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1802 if (!check_string ())
1806 if (!process_suffix ())
1809 /* Make still unresolved immediate matches conform to size of immediate
1810 given in i.suffix. */
1811 if (!finalize_imm ())
1814 if (i.types[0] & Imm1)
1815 i.imm_operands = 0; /* kludge for shift insns. */
1816 if (i.types[0] & ImplicitRegister)
1818 if (i.types[1] & ImplicitRegister)
1820 if (i.types[2] & ImplicitRegister)
1823 if (i.tm.opcode_modifier & ImmExt)
1827 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1829 /* These Intel Prescott New Instructions have the fixed
1830 operands with an opcode suffix which is coded in the same
1831 place as an 8-bit immediate field would be. Here we check
1832 those operands and remove them afterwards. */
1835 for (x = 0; x < i.operands; x++)
1836 if (i.op[x].regs->reg_num != x)
1837 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1838 i.op[x].regs->reg_name, x + 1, i.tm.name);
1842 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1843 opcode suffix which is coded in the same place as an 8-bit
1844 immediate field would be. Here we fake an 8-bit immediate
1845 operand from the opcode suffix stored in tm.extension_opcode. */
1847 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1849 exp = &im_expressions[i.imm_operands++];
1850 i.op[i.operands].imms = exp;
1851 i.types[i.operands++] = Imm8;
1852 exp->X_op = O_constant;
1853 exp->X_add_number = i.tm.extension_opcode;
1854 i.tm.extension_opcode = None;
1857 /* For insns with operands there are more diddles to do to the opcode. */
1860 if (!process_operands ())
1863 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1865 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1866 as_warn (_("translating to `%sp'"), i.tm.name);
1869 /* Handle conversion of 'int $3' --> special int3 insn. */
1870 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1872 i.tm.base_opcode = INT3_OPCODE;
1876 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1877 && i.op[0].disps->X_op == O_constant)
1879 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1880 the absolute address given by the constant. Since ix86 jumps and
1881 calls are pc relative, we need to generate a reloc. */
1882 i.op[0].disps->X_add_symbol = &abs_symbol;
1883 i.op[0].disps->X_op = O_symbol;
1886 if ((i.tm.opcode_modifier & Rex64) != 0)
1887 i.rex |= REX_MODE64;
1889 /* For 8 bit registers we need an empty rex prefix. Also if the
1890 instruction already has a prefix, we need to convert old
1891 registers to new ones. */
1893 if (((i.types[0] & Reg8) != 0
1894 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1895 || ((i.types[1] & Reg8) != 0
1896 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1897 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1902 i.rex |= REX_OPCODE;
1903 for (x = 0; x < 2; x++)
1905 /* Look for 8 bit operand that uses old registers. */
1906 if ((i.types[x] & Reg8) != 0
1907 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1909 /* In case it is "hi" register, give up. */
1910 if (i.op[x].regs->reg_num > 3)
1911 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1912 i.op[x].regs->reg_name);
1914 /* Otherwise it is equivalent to the extended register.
1915 Since the encoding doesn't change this is merely
1916 cosmetic cleanup for debug output. */
1918 i.op[x].regs = i.op[x].regs + 8;
1924 add_prefix (REX_OPCODE | i.rex);
1926 /* Record what ISA we have generated so far. */
1927 cpu_arch_isa_flags |= i.tm.cpu_flags;
1929 /* We are ready to output the insn. */
1934 parse_insn (line, mnemonic)
1939 char *token_start = l;
1944 /* Non-zero if we found a prefix only acceptable with string insns. */
1945 const char *expecting_string_instruction = NULL;
1950 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1953 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1955 as_bad (_("no such instruction: `%s'"), token_start);
1960 if (!is_space_char (*l)
1961 && *l != END_OF_INSN
1963 || (*l != PREFIX_SEPARATOR
1966 as_bad (_("invalid character %s in mnemonic"),
1967 output_invalid (*l));
1970 if (token_start == l)
1972 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1973 as_bad (_("expecting prefix; got nothing"));
1975 as_bad (_("expecting mnemonic; got nothing"));
1979 /* Look up instruction (or prefix) via hash table. */
1980 current_templates = hash_find (op_hash, mnemonic);
1982 if (*l != END_OF_INSN
1983 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1984 && current_templates
1985 && (current_templates->start->opcode_modifier & IsPrefix))
1987 if (current_templates->start->cpu_flags
1988 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1990 as_bad ((flag_code != CODE_64BIT
1991 ? _("`%s' is only supported in 64-bit mode")
1992 : _("`%s' is not supported in 64-bit mode")),
1993 current_templates->start->name);
1996 /* If we are in 16-bit mode, do not allow addr16 or data16.
1997 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1998 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1999 && flag_code != CODE_64BIT
2000 && (((current_templates->start->opcode_modifier & Size32) != 0)
2001 ^ (flag_code == CODE_16BIT)))
2003 as_bad (_("redundant %s prefix"),
2004 current_templates->start->name);
2007 /* Add prefix, checking for repeated prefixes. */
2008 switch (add_prefix (current_templates->start->base_opcode))
2013 expecting_string_instruction = current_templates->start->name;
2016 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2023 if (!current_templates)
2025 /* See if we can get a match by trimming off a suffix. */
2028 case WORD_MNEM_SUFFIX:
2029 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2030 i.suffix = SHORT_MNEM_SUFFIX;
2032 case BYTE_MNEM_SUFFIX:
2033 case QWORD_MNEM_SUFFIX:
2034 i.suffix = mnem_p[-1];
2036 current_templates = hash_find (op_hash, mnemonic);
2038 case SHORT_MNEM_SUFFIX:
2039 case LONG_MNEM_SUFFIX:
2042 i.suffix = mnem_p[-1];
2044 current_templates = hash_find (op_hash, mnemonic);
2052 if (intel_float_operand (mnemonic) == 1)
2053 i.suffix = SHORT_MNEM_SUFFIX;
2055 i.suffix = LONG_MNEM_SUFFIX;
2057 current_templates = hash_find (op_hash, mnemonic);
2061 if (!current_templates)
2063 as_bad (_("no such instruction: `%s'"), token_start);
2068 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2070 /* Check for a branch hint. We allow ",pt" and ",pn" for
2071 predict taken and predict not taken respectively.
2072 I'm not sure that branch hints actually do anything on loop
2073 and jcxz insns (JumpByte) for current Pentium4 chips. They
2074 may work in the future and it doesn't hurt to accept them
2076 if (l[0] == ',' && l[1] == 'p')
2080 if (!add_prefix (DS_PREFIX_OPCODE))
2084 else if (l[2] == 'n')
2086 if (!add_prefix (CS_PREFIX_OPCODE))
2092 /* Any other comma loses. */
2095 as_bad (_("invalid character %s in mnemonic"),
2096 output_invalid (*l));
2100 /* Check if instruction is supported on specified architecture. */
2102 for (t = current_templates->start; t < current_templates->end; ++t)
2104 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2105 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2107 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2110 if (!(supported & 2))
2112 as_bad (flag_code == CODE_64BIT
2113 ? _("`%s' is not supported in 64-bit mode")
2114 : _("`%s' is only supported in 64-bit mode"),
2115 current_templates->start->name);
2118 if (!(supported & 1))
2120 as_warn (_("`%s' is not supported on `%s%s'"),
2121 current_templates->start->name,
2123 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2125 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2127 as_warn (_("use .code16 to ensure correct addressing mode"));
2130 /* Check for rep/repne without a string instruction. */
2131 if (expecting_string_instruction)
2133 static templates override;
2135 for (t = current_templates->start; t < current_templates->end; ++t)
2136 if (t->opcode_modifier & IsString)
2138 if (t >= current_templates->end)
2140 as_bad (_("expecting string instruction after `%s'"),
2141 expecting_string_instruction);
2144 for (override.start = t; t < current_templates->end; ++t)
2145 if (!(t->opcode_modifier & IsString))
2148 current_templates = &override;
2155 parse_operands (l, mnemonic)
2157 const char *mnemonic;
2161 /* 1 if operand is pending after ','. */
2162 unsigned int expecting_operand = 0;
2164 /* Non-zero if operand parens not balanced. */
2165 unsigned int paren_not_balanced;
2167 while (*l != END_OF_INSN)
2169 /* Skip optional white space before operand. */
2170 if (is_space_char (*l))
2172 if (!is_operand_char (*l) && *l != END_OF_INSN)
2174 as_bad (_("invalid character %s before operand %d"),
2175 output_invalid (*l),
2179 token_start = l; /* after white space */
2180 paren_not_balanced = 0;
2181 while (paren_not_balanced || *l != ',')
2183 if (*l == END_OF_INSN)
2185 if (paren_not_balanced)
2188 as_bad (_("unbalanced parenthesis in operand %d."),
2191 as_bad (_("unbalanced brackets in operand %d."),
2196 break; /* we are done */
2198 else if (!is_operand_char (*l) && !is_space_char (*l))
2200 as_bad (_("invalid character %s in operand %d"),
2201 output_invalid (*l),
2208 ++paren_not_balanced;
2210 --paren_not_balanced;
2215 ++paren_not_balanced;
2217 --paren_not_balanced;
2221 if (l != token_start)
2222 { /* Yes, we've read in another operand. */
2223 unsigned int operand_ok;
2224 this_operand = i.operands++;
2225 if (i.operands > MAX_OPERANDS)
2227 as_bad (_("spurious operands; (%d operands/instruction max)"),
2231 /* Now parse operand adding info to 'i' as we go along. */
2232 END_STRING_AND_SAVE (l);
2236 i386_intel_operand (token_start,
2237 intel_float_operand (mnemonic));
2239 operand_ok = i386_operand (token_start);
2241 RESTORE_END_STRING (l);
2247 if (expecting_operand)
2249 expecting_operand_after_comma:
2250 as_bad (_("expecting operand after ','; got nothing"));
2255 as_bad (_("expecting operand before ','; got nothing"));
2260 /* Now *l must be either ',' or END_OF_INSN. */
2263 if (*++l == END_OF_INSN)
2265 /* Just skip it, if it's \n complain. */
2266 goto expecting_operand_after_comma;
2268 expecting_operand = 1;
2277 union i386_op temp_op;
2278 unsigned int temp_type;
2279 enum bfd_reloc_code_real temp_reloc;
2283 if (i.operands == 2)
2288 else if (i.operands == 3)
2293 temp_type = i.types[xchg2];
2294 i.types[xchg2] = i.types[xchg1];
2295 i.types[xchg1] = temp_type;
2296 temp_op = i.op[xchg2];
2297 i.op[xchg2] = i.op[xchg1];
2298 i.op[xchg1] = temp_op;
2299 temp_reloc = i.reloc[xchg2];
2300 i.reloc[xchg2] = i.reloc[xchg1];
2301 i.reloc[xchg1] = temp_reloc;
2303 if (i.mem_operands == 2)
2305 const seg_entry *temp_seg;
2306 temp_seg = i.seg[0];
2307 i.seg[0] = i.seg[1];
2308 i.seg[1] = temp_seg;
2312 /* Try to ensure constant immediates are represented in the smallest
2317 char guess_suffix = 0;
2321 guess_suffix = i.suffix;
2322 else if (i.reg_operands)
2324 /* Figure out a suffix from the last register operand specified.
2325 We can't do this properly yet, ie. excluding InOutPortReg,
2326 but the following works for instructions with immediates.
2327 In any case, we can't set i.suffix yet. */
2328 for (op = i.operands; --op >= 0;)
2329 if (i.types[op] & Reg)
2331 if (i.types[op] & Reg8)
2332 guess_suffix = BYTE_MNEM_SUFFIX;
2333 else if (i.types[op] & Reg16)
2334 guess_suffix = WORD_MNEM_SUFFIX;
2335 else if (i.types[op] & Reg32)
2336 guess_suffix = LONG_MNEM_SUFFIX;
2337 else if (i.types[op] & Reg64)
2338 guess_suffix = QWORD_MNEM_SUFFIX;
2342 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2343 guess_suffix = WORD_MNEM_SUFFIX;
2345 for (op = i.operands; --op >= 0;)
2346 if (i.types[op] & Imm)
2348 switch (i.op[op].imms->X_op)
2351 /* If a suffix is given, this operand may be shortened. */
2352 switch (guess_suffix)
2354 case LONG_MNEM_SUFFIX:
2355 i.types[op] |= Imm32 | Imm64;
2357 case WORD_MNEM_SUFFIX:
2358 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2360 case BYTE_MNEM_SUFFIX:
2361 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2365 /* If this operand is at most 16 bits, convert it
2366 to a signed 16 bit number before trying to see
2367 whether it will fit in an even smaller size.
2368 This allows a 16-bit operand such as $0xffe0 to
2369 be recognised as within Imm8S range. */
2370 if ((i.types[op] & Imm16)
2371 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2373 i.op[op].imms->X_add_number =
2374 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2376 if ((i.types[op] & Imm32)
2377 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2380 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2381 ^ ((offsetT) 1 << 31))
2382 - ((offsetT) 1 << 31));
2384 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2386 /* We must avoid matching of Imm32 templates when 64bit
2387 only immediate is available. */
2388 if (guess_suffix == QWORD_MNEM_SUFFIX)
2389 i.types[op] &= ~Imm32;
2396 /* Symbols and expressions. */
2398 /* Convert symbolic operand to proper sizes for matching, but don't
2399 prevent matching a set of insns that only supports sizes other
2400 than those matching the insn suffix. */
2402 unsigned int mask, allowed = 0;
2405 for (t = current_templates->start; t < current_templates->end; ++t)
2406 allowed |= t->operand_types[op];
2407 switch (guess_suffix)
2409 case QWORD_MNEM_SUFFIX:
2410 mask = Imm64 | Imm32S;
2412 case LONG_MNEM_SUFFIX:
2415 case WORD_MNEM_SUFFIX:
2418 case BYTE_MNEM_SUFFIX:
2426 i.types[op] &= mask;
2433 /* Try to use the smallest displacement type too. */
2439 for (op = i.operands; --op >= 0;)
2440 if (i.types[op] & Disp)
2442 if (i.op[op].disps->X_op == O_constant)
2444 offsetT disp = i.op[op].disps->X_add_number;
2446 if ((i.types[op] & Disp16)
2447 && (disp & ~(offsetT) 0xffff) == 0)
2449 /* If this operand is at most 16 bits, convert
2450 to a signed 16 bit number and don't use 64bit
2452 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2453 i.types[op] &= ~Disp64;
2455 if ((i.types[op] & Disp32)
2456 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2458 /* If this operand is at most 32 bits, convert
2459 to a signed 32 bit number and don't use 64bit
2461 disp &= (((offsetT) 2 << 31) - 1);
2462 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2463 i.types[op] &= ~Disp64;
2465 if (!disp && (i.types[op] & BaseIndex))
2467 i.types[op] &= ~Disp;
2471 else if (flag_code == CODE_64BIT)
2473 if (fits_in_signed_long (disp))
2475 i.types[op] &= ~Disp64;
2476 i.types[op] |= Disp32S;
2478 if (fits_in_unsigned_long (disp))
2479 i.types[op] |= Disp32;
2481 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2482 && fits_in_signed_byte (disp))
2483 i.types[op] |= Disp8;
2485 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2486 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2488 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2489 i.op[op].disps, 0, i.reloc[op]);
2490 i.types[op] &= ~Disp;
2493 /* We only support 64bit displacement on constants. */
2494 i.types[op] &= ~Disp64;
2501 /* Points to template once we've found it. */
2503 unsigned int overlap0, overlap1, overlap2;
2504 unsigned int found_reverse_match;
2507 #define MATCH(overlap, given, template) \
2508 ((overlap & ~JumpAbsolute) \
2509 && (((given) & (BaseIndex | JumpAbsolute)) \
2510 == ((overlap) & (BaseIndex | JumpAbsolute))))
2512 /* If given types r0 and r1 are registers they must be of the same type
2513 unless the expected operand type register overlap is null.
2514 Note that Acc in a template matches every size of reg. */
2515 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2516 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2517 || ((g0) & Reg) == ((g1) & Reg) \
2518 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2523 found_reverse_match = 0;
2524 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2526 : (i.suffix == WORD_MNEM_SUFFIX
2528 : (i.suffix == SHORT_MNEM_SUFFIX
2530 : (i.suffix == LONG_MNEM_SUFFIX
2532 : (i.suffix == QWORD_MNEM_SUFFIX
2534 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2535 ? No_xSuf : 0))))));
2537 for (t = current_templates->start; t < current_templates->end; t++)
2539 /* Must have right number of operands. */
2540 if (i.operands != t->operands)
2543 /* Check the suffix, except for some instructions in intel mode. */
2544 if ((t->opcode_modifier & suffix_check)
2546 && (t->opcode_modifier & IgnoreSize)))
2549 /* In general, don't allow 64-bit operands in 32-bit mode. */
2550 if (i.suffix == QWORD_MNEM_SUFFIX
2551 && flag_code != CODE_64BIT
2553 ? (!(t->opcode_modifier & IgnoreSize)
2554 && !intel_float_operand (t->name))
2555 : intel_float_operand (t->name) != 2)
2556 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2557 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2558 && (t->base_opcode != 0x0fc7
2559 || t->extension_opcode != 1 /* cmpxchg8b */))
2562 /* Do not verify operands when there are none. */
2563 else if (!t->operands)
2565 if (t->cpu_flags & ~cpu_arch_flags)
2567 /* We've found a match; break out of loop. */
2571 overlap0 = i.types[0] & t->operand_types[0];
2572 switch (t->operands)
2575 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2580 overlap1 = i.types[1] & t->operand_types[1];
2581 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2582 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2583 /* monitor in SSE3 is a very special case. The first
2584 register and the second register may have different
2586 || !((t->base_opcode == 0x0f01
2587 && t->extension_opcode == 0xc8)
2588 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2589 t->operand_types[0],
2590 overlap1, i.types[1],
2591 t->operand_types[1])))
2593 /* Check if other direction is valid ... */
2594 if ((t->opcode_modifier & (D | FloatD)) == 0)
2597 /* Try reversing direction of operands. */
2598 overlap0 = i.types[0] & t->operand_types[1];
2599 overlap1 = i.types[1] & t->operand_types[0];
2600 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2601 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2602 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2603 t->operand_types[1],
2604 overlap1, i.types[1],
2605 t->operand_types[0]))
2607 /* Does not match either direction. */
2610 /* found_reverse_match holds which of D or FloatDR
2612 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2614 /* Found a forward 2 operand match here. */
2615 else if (t->operands == 3)
2617 /* Here we make use of the fact that there are no
2618 reverse match 3 operand instructions, and all 3
2619 operand instructions only need to be checked for
2620 register consistency between operands 2 and 3. */
2621 overlap2 = i.types[2] & t->operand_types[2];
2622 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2623 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2624 t->operand_types[1],
2625 overlap2, i.types[2],
2626 t->operand_types[2]))
2630 /* Found either forward/reverse 2 or 3 operand match here:
2631 slip through to break. */
2633 if (t->cpu_flags & ~cpu_arch_flags)
2635 found_reverse_match = 0;
2638 /* We've found a match; break out of loop. */
2642 if (t == current_templates->end)
2644 /* We found no match. */
2645 as_bad (_("suffix or operands invalid for `%s'"),
2646 current_templates->start->name);
2650 if (!quiet_warnings)
2653 && ((i.types[0] & JumpAbsolute)
2654 != (t->operand_types[0] & JumpAbsolute)))
2656 as_warn (_("indirect %s without `*'"), t->name);
2659 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2660 == (IsPrefix | IgnoreSize))
2662 /* Warn them that a data or address size prefix doesn't
2663 affect assembly of the next line of code. */
2664 as_warn (_("stand-alone `%s' prefix"), t->name);
2668 /* Copy the template we found. */
2670 if (found_reverse_match)
2672 /* If we found a reverse match we must alter the opcode
2673 direction bit. found_reverse_match holds bits to change
2674 (different for int & float insns). */
2676 i.tm.base_opcode ^= found_reverse_match;
2678 i.tm.operand_types[0] = t->operand_types[1];
2679 i.tm.operand_types[1] = t->operand_types[0];
2688 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2689 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2691 if (i.seg[0] != NULL && i.seg[0] != &es)
2693 as_bad (_("`%s' operand %d must use `%%es' segment"),
2698 /* There's only ever one segment override allowed per instruction.
2699 This instruction possibly has a legal segment override on the
2700 second operand, so copy the segment to where non-string
2701 instructions store it, allowing common code. */
2702 i.seg[0] = i.seg[1];
2704 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2706 if (i.seg[1] != NULL && i.seg[1] != &es)
2708 as_bad (_("`%s' operand %d must use `%%es' segment"),
2718 process_suffix (void)
2720 /* If matched instruction specifies an explicit instruction mnemonic
2722 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2724 if (i.tm.opcode_modifier & Size16)
2725 i.suffix = WORD_MNEM_SUFFIX;
2726 else if (i.tm.opcode_modifier & Size64)
2727 i.suffix = QWORD_MNEM_SUFFIX;
2729 i.suffix = LONG_MNEM_SUFFIX;
2731 else if (i.reg_operands)
2733 /* If there's no instruction mnemonic suffix we try to invent one
2734 based on register operands. */
2737 /* We take i.suffix from the last register operand specified,
2738 Destination register type is more significant than source
2742 for (op = i.operands; --op >= 0;)
2743 if ((i.types[op] & Reg)
2744 && !(i.tm.operand_types[op] & InOutPortReg))
2746 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2747 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2748 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2753 else if (i.suffix == BYTE_MNEM_SUFFIX)
2755 if (!check_byte_reg ())
2758 else if (i.suffix == LONG_MNEM_SUFFIX)
2760 if (!check_long_reg ())
2763 else if (i.suffix == QWORD_MNEM_SUFFIX)
2765 if (!check_qword_reg ())
2768 else if (i.suffix == WORD_MNEM_SUFFIX)
2770 if (!check_word_reg ())
2773 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2774 /* Do nothing if the instruction is going to ignore the prefix. */
2779 else if ((i.tm.opcode_modifier & DefaultSize)
2781 /* exclude fldenv/frstor/fsave/fstenv */
2782 && (i.tm.opcode_modifier & No_sSuf))
2784 i.suffix = stackop_size;
2786 else if (intel_syntax
2788 && ((i.tm.operand_types[0] & JumpAbsolute)
2789 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2790 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2791 && i.tm.extension_opcode <= 3)))
2796 if (!(i.tm.opcode_modifier & No_qSuf))
2798 i.suffix = QWORD_MNEM_SUFFIX;
2802 if (!(i.tm.opcode_modifier & No_lSuf))
2803 i.suffix = LONG_MNEM_SUFFIX;
2806 if (!(i.tm.opcode_modifier & No_wSuf))
2807 i.suffix = WORD_MNEM_SUFFIX;
2816 if (i.tm.opcode_modifier & W)
2818 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2824 unsigned int suffixes = (~i.tm.opcode_modifier
2832 if ((i.tm.opcode_modifier & W)
2833 || ((suffixes & (suffixes - 1))
2834 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2836 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2842 /* Change the opcode based on the operand size given by i.suffix;
2843 We don't need to change things for byte insns. */
2845 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2847 /* It's not a byte, select word/dword operation. */
2848 if (i.tm.opcode_modifier & W)
2850 if (i.tm.opcode_modifier & ShortForm)
2851 i.tm.base_opcode |= 8;
2853 i.tm.base_opcode |= 1;
2856 /* Now select between word & dword operations via the operand
2857 size prefix, except for instructions that will ignore this
2859 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2861 /* monitor in SSE3 is a very special case. The default size
2862 of AX is the size of mode. The address size override
2863 prefix will change the size of AX. */
2864 if (i.op->regs[0].reg_type &
2865 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2866 if (!add_prefix (ADDR_PREFIX_OPCODE))
2869 else if (i.suffix != QWORD_MNEM_SUFFIX
2870 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2871 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2872 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2873 || (flag_code == CODE_64BIT
2874 && (i.tm.opcode_modifier & JumpByte))))
2876 unsigned int prefix = DATA_PREFIX_OPCODE;
2878 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2879 prefix = ADDR_PREFIX_OPCODE;
2881 if (!add_prefix (prefix))
2885 /* Set mode64 for an operand. */
2886 if (i.suffix == QWORD_MNEM_SUFFIX
2887 && flag_code == CODE_64BIT
2888 && (i.tm.opcode_modifier & NoRex64) == 0)
2890 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2893 || i.types [0] != (Acc | Reg64)
2894 || i.types [1] != (Acc | Reg64)
2895 || strcmp (i.tm.name, "xchg") != 0)
2896 i.rex |= REX_MODE64;
2899 /* Size floating point instruction. */
2900 if (i.suffix == LONG_MNEM_SUFFIX)
2901 if (i.tm.opcode_modifier & FloatMF)
2902 i.tm.base_opcode ^= 4;
2909 check_byte_reg (void)
2913 for (op = i.operands; --op >= 0;)
2915 /* If this is an eight bit register, it's OK. If it's the 16 or
2916 32 bit version of an eight bit register, we will just use the
2917 low portion, and that's OK too. */
2918 if (i.types[op] & Reg8)
2921 /* movzx and movsx should not generate this warning. */
2923 && (i.tm.base_opcode == 0xfb7
2924 || i.tm.base_opcode == 0xfb6
2925 || i.tm.base_opcode == 0x63
2926 || i.tm.base_opcode == 0xfbe
2927 || i.tm.base_opcode == 0xfbf))
2930 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2932 /* Prohibit these changes in the 64bit mode, since the
2933 lowering is more complicated. */
2934 if (flag_code == CODE_64BIT
2935 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2937 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2938 i.op[op].regs->reg_name,
2942 #if REGISTER_WARNINGS
2944 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2945 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2946 (i.op[op].regs + (i.types[op] & Reg16
2947 ? REGNAM_AL - REGNAM_AX
2948 : REGNAM_AL - REGNAM_EAX))->reg_name,
2949 i.op[op].regs->reg_name,
2954 /* Any other register is bad. */
2955 if (i.types[op] & (Reg | RegMMX | RegXMM
2957 | Control | Debug | Test
2958 | FloatReg | FloatAcc))
2960 as_bad (_("`%%%s' not allowed with `%s%c'"),
2961 i.op[op].regs->reg_name,
2975 for (op = i.operands; --op >= 0;)
2976 /* Reject eight bit registers, except where the template requires
2977 them. (eg. movzb) */
2978 if ((i.types[op] & Reg8) != 0
2979 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2981 as_bad (_("`%%%s' not allowed with `%s%c'"),
2982 i.op[op].regs->reg_name,
2987 /* Warn if the e prefix on a general reg is missing. */
2988 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2989 && (i.types[op] & Reg16) != 0
2990 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2992 /* Prohibit these changes in the 64bit mode, since the
2993 lowering is more complicated. */
2994 if (flag_code == CODE_64BIT)
2996 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2997 i.op[op].regs->reg_name,
3001 #if REGISTER_WARNINGS
3003 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3004 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3005 i.op[op].regs->reg_name,
3009 /* Warn if the r prefix on a general reg is missing. */
3010 else if ((i.types[op] & Reg64) != 0
3011 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3013 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3014 i.op[op].regs->reg_name,
3026 for (op = i.operands; --op >= 0; )
3027 /* Reject eight bit registers, except where the template requires
3028 them. (eg. movzb) */
3029 if ((i.types[op] & Reg8) != 0
3030 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3032 as_bad (_("`%%%s' not allowed with `%s%c'"),
3033 i.op[op].regs->reg_name,
3038 /* Warn if the e prefix on a general reg is missing. */
3039 else if (((i.types[op] & Reg16) != 0
3040 || (i.types[op] & Reg32) != 0)
3041 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3043 /* Prohibit these changes in the 64bit mode, since the
3044 lowering is more complicated. */
3045 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3046 i.op[op].regs->reg_name,
3057 for (op = i.operands; --op >= 0;)
3058 /* Reject eight bit registers, except where the template requires
3059 them. (eg. movzb) */
3060 if ((i.types[op] & Reg8) != 0
3061 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3063 as_bad (_("`%%%s' not allowed with `%s%c'"),
3064 i.op[op].regs->reg_name,
3069 /* Warn if the e prefix on a general reg is present. */
3070 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3071 && (i.types[op] & Reg32) != 0
3072 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3074 /* Prohibit these changes in the 64bit mode, since the
3075 lowering is more complicated. */
3076 if (flag_code == CODE_64BIT)
3078 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3079 i.op[op].regs->reg_name,
3084 #if REGISTER_WARNINGS
3085 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3086 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3087 i.op[op].regs->reg_name,
3097 unsigned int overlap0, overlap1, overlap2;
3099 overlap0 = i.types[0] & i.tm.operand_types[0];
3100 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3101 && overlap0 != Imm8 && overlap0 != Imm8S
3102 && overlap0 != Imm16 && overlap0 != Imm32S
3103 && overlap0 != Imm32 && overlap0 != Imm64)
3107 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3109 : (i.suffix == WORD_MNEM_SUFFIX
3111 : (i.suffix == QWORD_MNEM_SUFFIX
3115 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3116 || overlap0 == (Imm16 | Imm32)
3117 || overlap0 == (Imm16 | Imm32S))
3119 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3122 if (overlap0 != Imm8 && overlap0 != Imm8S
3123 && overlap0 != Imm16 && overlap0 != Imm32S
3124 && overlap0 != Imm32 && overlap0 != Imm64)
3126 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3130 i.types[0] = overlap0;
3132 overlap1 = i.types[1] & i.tm.operand_types[1];
3133 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3134 && overlap1 != Imm8 && overlap1 != Imm8S
3135 && overlap1 != Imm16 && overlap1 != Imm32S
3136 && overlap1 != Imm32 && overlap1 != Imm64)
3140 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3142 : (i.suffix == WORD_MNEM_SUFFIX
3144 : (i.suffix == QWORD_MNEM_SUFFIX
3148 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3149 || overlap1 == (Imm16 | Imm32)
3150 || overlap1 == (Imm16 | Imm32S))
3152 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3155 if (overlap1 != Imm8 && overlap1 != Imm8S
3156 && overlap1 != Imm16 && overlap1 != Imm32S
3157 && overlap1 != Imm32 && overlap1 != Imm64)
3159 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3163 i.types[1] = overlap1;
3165 overlap2 = i.types[2] & i.tm.operand_types[2];
3166 assert ((overlap2 & Imm) == 0);
3167 i.types[2] = overlap2;
3175 /* Default segment register this instruction will use for memory
3176 accesses. 0 means unknown. This is only for optimizing out
3177 unnecessary segment overrides. */
3178 const seg_entry *default_seg = 0;
3180 /* The imul $imm, %reg instruction is converted into
3181 imul $imm, %reg, %reg, and the clr %reg instruction
3182 is converted into xor %reg, %reg. */
3183 if (i.tm.opcode_modifier & regKludge)
3185 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3186 /* Pretend we saw the extra register operand. */
3187 assert (i.op[first_reg_op + 1].regs == 0);
3188 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3189 i.types[first_reg_op + 1] = i.types[first_reg_op];
3193 if (i.tm.opcode_modifier & ShortForm)
3195 /* The register or float register operand is in operand 0 or 1. */
3196 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3197 /* Register goes in low 3 bits of opcode. */
3198 i.tm.base_opcode |= i.op[op].regs->reg_num;
3199 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3201 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3203 /* Warn about some common errors, but press on regardless.
3204 The first case can be generated by gcc (<= 2.8.1). */
3205 if (i.operands == 2)
3207 /* Reversed arguments on faddp, fsubp, etc. */
3208 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3209 i.op[1].regs->reg_name,
3210 i.op[0].regs->reg_name);
3214 /* Extraneous `l' suffix on fp insn. */
3215 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3216 i.op[0].regs->reg_name);
3220 else if (i.tm.opcode_modifier & Modrm)
3222 /* The opcode is completed (modulo i.tm.extension_opcode which
3223 must be put into the modrm byte). Now, we make the modrm and
3224 index base bytes based on all the info we've collected. */
3226 default_seg = build_modrm_byte ();
3228 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3230 if (i.tm.base_opcode == POP_SEG_SHORT
3231 && i.op[0].regs->reg_num == 1)
3233 as_bad (_("you can't `pop %%cs'"));
3236 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3237 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3240 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3244 else if ((i.tm.opcode_modifier & IsString) != 0)
3246 /* For the string instructions that allow a segment override
3247 on one of their operands, the default segment is ds. */
3251 if ((i.tm.base_opcode == 0x8d /* lea */
3252 || (i.tm.cpu_flags & CpuSVME))
3253 && i.seg[0] && !quiet_warnings)
3254 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3256 /* If a segment was explicitly specified, and the specified segment
3257 is not the default, use an opcode prefix to select it. If we
3258 never figured out what the default segment is, then default_seg
3259 will be zero at this point, and the specified segment prefix will
3261 if ((i.seg[0]) && (i.seg[0] != default_seg))
3263 if (!add_prefix (i.seg[0]->seg_prefix))
3269 static const seg_entry *
3272 const seg_entry *default_seg = 0;
3274 /* i.reg_operands MUST be the number of real register operands;
3275 implicit registers do not count. */
3276 if (i.reg_operands == 2)
3278 unsigned int source, dest;
3279 source = ((i.types[0]
3280 & (Reg | RegMMX | RegXMM
3282 | Control | Debug | Test))
3287 /* One of the register operands will be encoded in the i.tm.reg
3288 field, the other in the combined i.tm.mode and i.tm.regmem
3289 fields. If no form of this instruction supports a memory
3290 destination operand, then we assume the source operand may
3291 sometimes be a memory operand and so we need to store the
3292 destination in the i.rm.reg field. */
3293 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3295 i.rm.reg = i.op[dest].regs->reg_num;
3296 i.rm.regmem = i.op[source].regs->reg_num;
3297 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3299 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3304 i.rm.reg = i.op[source].regs->reg_num;
3305 i.rm.regmem = i.op[dest].regs->reg_num;
3306 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3308 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3311 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3313 if (!((i.types[0] | i.types[1]) & Control))
3315 i.rex &= ~(REX_EXTX | REX_EXTZ);
3316 add_prefix (LOCK_PREFIX_OPCODE);
3320 { /* If it's not 2 reg operands... */
3323 unsigned int fake_zero_displacement = 0;
3324 unsigned int op = ((i.types[0] & AnyMem)
3326 : (i.types[1] & AnyMem) ? 1 : 2);
3330 if (i.base_reg == 0)
3333 if (!i.disp_operands)
3334 fake_zero_displacement = 1;
3335 if (i.index_reg == 0)
3337 /* Operand is just <disp> */
3338 if (flag_code == CODE_64BIT)
3340 /* 64bit mode overwrites the 32bit absolute
3341 addressing by RIP relative addressing and
3342 absolute addressing is encoded by one of the
3343 redundant SIB forms. */
3344 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3345 i.sib.base = NO_BASE_REGISTER;
3346 i.sib.index = NO_INDEX_REGISTER;
3347 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3349 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3351 i.rm.regmem = NO_BASE_REGISTER_16;
3352 i.types[op] = Disp16;
3356 i.rm.regmem = NO_BASE_REGISTER;
3357 i.types[op] = Disp32;
3360 else /* !i.base_reg && i.index_reg */
3362 i.sib.index = i.index_reg->reg_num;
3363 i.sib.base = NO_BASE_REGISTER;
3364 i.sib.scale = i.log2_scale_factor;
3365 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3366 i.types[op] &= ~Disp;
3367 if (flag_code != CODE_64BIT)
3368 i.types[op] |= Disp32; /* Must be 32 bit */
3370 i.types[op] |= Disp32S;
3371 if ((i.index_reg->reg_flags & RegRex) != 0)
3375 /* RIP addressing for 64bit mode. */
3376 else if (i.base_reg->reg_type == BaseIndex)
3378 i.rm.regmem = NO_BASE_REGISTER;
3379 i.types[op] &= ~ Disp;
3380 i.types[op] |= Disp32S;
3381 i.flags[op] = Operand_PCrel;
3382 if (! i.disp_operands)
3383 fake_zero_displacement = 1;
3385 else if (i.base_reg->reg_type & Reg16)
3387 switch (i.base_reg->reg_num)
3390 if (i.index_reg == 0)
3392 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3393 i.rm.regmem = i.index_reg->reg_num - 6;
3397 if (i.index_reg == 0)
3400 if ((i.types[op] & Disp) == 0)
3402 /* fake (%bp) into 0(%bp) */
3403 i.types[op] |= Disp8;
3404 fake_zero_displacement = 1;
3407 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3408 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3410 default: /* (%si) -> 4 or (%di) -> 5 */
3411 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3413 i.rm.mode = mode_from_disp_size (i.types[op]);
3415 else /* i.base_reg and 32/64 bit mode */
3417 if (flag_code == CODE_64BIT
3418 && (i.types[op] & Disp))
3419 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3421 i.rm.regmem = i.base_reg->reg_num;
3422 if ((i.base_reg->reg_flags & RegRex) != 0)
3424 i.sib.base = i.base_reg->reg_num;
3425 /* x86-64 ignores REX prefix bit here to avoid decoder
3427 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3430 if (i.disp_operands == 0)
3432 fake_zero_displacement = 1;
3433 i.types[op] |= Disp8;
3436 else if (i.base_reg->reg_num == ESP_REG_NUM)
3440 i.sib.scale = i.log2_scale_factor;
3441 if (i.index_reg == 0)
3443 /* <disp>(%esp) becomes two byte modrm with no index
3444 register. We've already stored the code for esp
3445 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3446 Any base register besides %esp will not use the
3447 extra modrm byte. */
3448 i.sib.index = NO_INDEX_REGISTER;
3449 #if !SCALE1_WHEN_NO_INDEX
3450 /* Another case where we force the second modrm byte. */
3451 if (i.log2_scale_factor)
3452 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3457 i.sib.index = i.index_reg->reg_num;
3458 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3459 if ((i.index_reg->reg_flags & RegRex) != 0)
3464 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3465 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3468 i.rm.mode = mode_from_disp_size (i.types[op]);
3471 if (fake_zero_displacement)
3473 /* Fakes a zero displacement assuming that i.types[op]
3474 holds the correct displacement size. */
3477 assert (i.op[op].disps == 0);
3478 exp = &disp_expressions[i.disp_operands++];
3479 i.op[op].disps = exp;
3480 exp->X_op = O_constant;
3481 exp->X_add_number = 0;
3482 exp->X_add_symbol = (symbolS *) 0;
3483 exp->X_op_symbol = (symbolS *) 0;
3487 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3488 (if any) based on i.tm.extension_opcode. Again, we must be
3489 careful to make sure that segment/control/debug/test/MMX
3490 registers are coded into the i.rm.reg field. */
3495 & (Reg | RegMMX | RegXMM
3497 | Control | Debug | Test))
3500 & (Reg | RegMMX | RegXMM
3502 | Control | Debug | Test))
3505 /* If there is an extension opcode to put here, the register
3506 number must be put into the regmem field. */
3507 if (i.tm.extension_opcode != None)
3509 i.rm.regmem = i.op[op].regs->reg_num;
3510 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3515 i.rm.reg = i.op[op].regs->reg_num;
3516 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3520 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3521 must set it to 3 to indicate this is a register operand
3522 in the regmem field. */
3523 if (!i.mem_operands)
3527 /* Fill in i.rm.reg field with extension opcode (if any). */
3528 if (i.tm.extension_opcode != None)
3529 i.rm.reg = i.tm.extension_opcode;
3540 relax_substateT subtype;
3545 if (flag_code == CODE_16BIT)
3549 if (i.prefix[DATA_PREFIX] != 0)
3555 /* Pentium4 branch hints. */
3556 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3557 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3562 if (i.prefix[REX_PREFIX] != 0)
3568 if (i.prefixes != 0 && !intel_syntax)
3569 as_warn (_("skipping prefixes on this instruction"));
3571 /* It's always a symbol; End frag & setup for relax.
3572 Make sure there is enough room in this frag for the largest
3573 instruction we may generate in md_convert_frag. This is 2
3574 bytes for the opcode and room for the prefix and largest
3576 frag_grow (prefix + 2 + 4);
3577 /* Prefix and 1 opcode byte go in fr_fix. */
3578 p = frag_more (prefix + 1);
3579 if (i.prefix[DATA_PREFIX] != 0)
3580 *p++ = DATA_PREFIX_OPCODE;
3581 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3582 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3583 *p++ = i.prefix[SEG_PREFIX];
3584 if (i.prefix[REX_PREFIX] != 0)
3585 *p++ = i.prefix[REX_PREFIX];
3586 *p = i.tm.base_opcode;
3588 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3589 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3590 else if ((cpu_arch_flags & Cpu386) != 0)
3591 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3593 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3596 sym = i.op[0].disps->X_add_symbol;
3597 off = i.op[0].disps->X_add_number;
3599 if (i.op[0].disps->X_op != O_constant
3600 && i.op[0].disps->X_op != O_symbol)
3602 /* Handle complex expressions. */
3603 sym = make_expr_symbol (i.op[0].disps);
3607 /* 1 possible extra opcode + 4 byte displacement go in var part.
3608 Pass reloc in fr_var. */
3609 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3619 if (i.tm.opcode_modifier & JumpByte)
3621 /* This is a loop or jecxz type instruction. */
3623 if (i.prefix[ADDR_PREFIX] != 0)
3625 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3628 /* Pentium4 branch hints. */
3629 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3630 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3632 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3641 if (flag_code == CODE_16BIT)
3644 if (i.prefix[DATA_PREFIX] != 0)
3646 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3656 if (i.prefix[REX_PREFIX] != 0)
3658 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3662 if (i.prefixes != 0 && !intel_syntax)
3663 as_warn (_("skipping prefixes on this instruction"));
3665 p = frag_more (1 + size);
3666 *p++ = i.tm.base_opcode;
3668 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3669 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3671 /* All jumps handled here are signed, but don't use a signed limit
3672 check for 32 and 16 bit jumps as we want to allow wrap around at
3673 4G and 64k respectively. */
3675 fixP->fx_signed = 1;
3679 output_interseg_jump ()
3687 if (flag_code == CODE_16BIT)
3691 if (i.prefix[DATA_PREFIX] != 0)
3697 if (i.prefix[REX_PREFIX] != 0)
3707 if (i.prefixes != 0 && !intel_syntax)
3708 as_warn (_("skipping prefixes on this instruction"));
3710 /* 1 opcode; 2 segment; offset */
3711 p = frag_more (prefix + 1 + 2 + size);
3713 if (i.prefix[DATA_PREFIX] != 0)
3714 *p++ = DATA_PREFIX_OPCODE;
3716 if (i.prefix[REX_PREFIX] != 0)
3717 *p++ = i.prefix[REX_PREFIX];
3719 *p++ = i.tm.base_opcode;
3720 if (i.op[1].imms->X_op == O_constant)
3722 offsetT n = i.op[1].imms->X_add_number;
3725 && !fits_in_unsigned_word (n)
3726 && !fits_in_signed_word (n))
3728 as_bad (_("16-bit jump out of range"));
3731 md_number_to_chars (p, n, size);
3734 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3735 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3736 if (i.op[0].imms->X_op != O_constant)
3737 as_bad (_("can't handle non absolute segment in `%s'"),
3739 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3745 fragS *insn_start_frag;
3746 offsetT insn_start_off;
3748 /* Tie dwarf2 debug info to the address at the start of the insn.
3749 We can't do this after the insn has been output as the current
3750 frag may have been closed off. eg. by frag_var. */
3751 dwarf2_emit_insn (0);
3753 insn_start_frag = frag_now;
3754 insn_start_off = frag_now_fix ();
3757 if (i.tm.opcode_modifier & Jump)
3759 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3761 else if (i.tm.opcode_modifier & JumpInterSegment)
3762 output_interseg_jump ();
3765 /* Output normal instructions here. */
3768 unsigned int prefix;
3770 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3771 Instructions have 3 bytes. We may use one more higher byte
3772 to specify a prefix the instruction requires. */
3773 if ((i.tm.cpu_flags & CpuMNI) != 0)
3775 if (i.tm.base_opcode & 0xff000000)
3777 prefix = (i.tm.base_opcode >> 24) & 0xff;
3781 else if ((i.tm.base_opcode & 0xff0000) != 0)
3783 prefix = (i.tm.base_opcode >> 16) & 0xff;
3784 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3787 if (prefix != REPE_PREFIX_OPCODE
3788 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3789 add_prefix (prefix);
3792 add_prefix (prefix);
3795 /* The prefix bytes. */
3797 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3803 md_number_to_chars (p, (valueT) *q, 1);
3807 /* Now the opcode; be careful about word order here! */
3808 if (fits_in_unsigned_byte (i.tm.base_opcode))
3810 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3814 if ((i.tm.cpu_flags & CpuMNI) != 0)
3817 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3822 /* Put out high byte first: can't use md_number_to_chars! */
3823 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3824 *p = i.tm.base_opcode & 0xff;
3827 /* Now the modrm byte and sib byte (if present). */
3828 if (i.tm.opcode_modifier & Modrm)
3831 md_number_to_chars (p,
3832 (valueT) (i.rm.regmem << 0
3836 /* If i.rm.regmem == ESP (4)
3837 && i.rm.mode != (Register mode)
3839 ==> need second modrm byte. */
3840 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3842 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3845 md_number_to_chars (p,
3846 (valueT) (i.sib.base << 0
3848 | i.sib.scale << 6),
3853 if (i.disp_operands)
3854 output_disp (insn_start_frag, insn_start_off);
3857 output_imm (insn_start_frag, insn_start_off);
3863 pi ("" /*line*/, &i);
3865 #endif /* DEBUG386 */
3869 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
3874 for (n = 0; n < i.operands; n++)
3876 if (i.types[n] & Disp)
3878 if (i.op[n].disps->X_op == O_constant)
3884 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3887 if (i.types[n] & Disp8)
3889 if (i.types[n] & Disp64)
3892 val = offset_in_range (i.op[n].disps->X_add_number,
3894 p = frag_more (size);
3895 md_number_to_chars (p, val, size);
3899 enum bfd_reloc_code_real reloc_type;
3902 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3904 /* The PC relative address is computed relative
3905 to the instruction boundary, so in case immediate
3906 fields follows, we need to adjust the value. */
3907 if (pcrel && i.imm_operands)
3912 for (n1 = 0; n1 < i.operands; n1++)
3913 if (i.types[n1] & Imm)
3915 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3918 if (i.types[n1] & (Imm8 | Imm8S))
3920 if (i.types[n1] & Imm64)
3925 /* We should find the immediate. */
3926 if (n1 == i.operands)
3928 i.op[n].disps->X_add_number -= imm_size;
3931 if (i.types[n] & Disp32S)
3934 if (i.types[n] & (Disp16 | Disp64))
3937 if (i.types[n] & Disp64)
3941 p = frag_more (size);
3942 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3944 && GOT_symbol == i.op[n].disps->X_add_symbol
3945 && (((reloc_type == BFD_RELOC_32
3946 || reloc_type == BFD_RELOC_X86_64_32S
3947 || (reloc_type == BFD_RELOC_64
3949 && (i.op[n].disps->X_op == O_symbol
3950 || (i.op[n].disps->X_op == O_add
3951 && ((symbol_get_value_expression
3952 (i.op[n].disps->X_op_symbol)->X_op)
3954 || reloc_type == BFD_RELOC_32_PCREL))
3958 if (insn_start_frag == frag_now)
3959 add = (p - frag_now->fr_literal) - insn_start_off;
3964 add = insn_start_frag->fr_fix - insn_start_off;
3965 for (fr = insn_start_frag->fr_next;
3966 fr && fr != frag_now; fr = fr->fr_next)
3968 add += p - frag_now->fr_literal;
3973 reloc_type = BFD_RELOC_386_GOTPC;
3974 i.op[n].imms->X_add_number += add;
3976 else if (reloc_type == BFD_RELOC_64)
3977 reloc_type = BFD_RELOC_X86_64_GOTPC64;
3979 /* Don't do the adjustment for x86-64, as there
3980 the pcrel addressing is relative to the _next_
3981 insn, and that is taken care of in other code. */
3982 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3984 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3985 i.op[n].disps, pcrel, reloc_type);
3992 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
3997 for (n = 0; n < i.operands; n++)
3999 if (i.types[n] & Imm)
4001 if (i.op[n].imms->X_op == O_constant)
4007 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4010 if (i.types[n] & (Imm8 | Imm8S))
4012 else if (i.types[n] & Imm64)
4015 val = offset_in_range (i.op[n].imms->X_add_number,
4017 p = frag_more (size);
4018 md_number_to_chars (p, val, size);
4022 /* Not absolute_section.
4023 Need a 32-bit fixup (don't support 8bit
4024 non-absolute imms). Try to support other
4026 enum bfd_reloc_code_real reloc_type;
4030 if ((i.types[n] & (Imm32S))
4031 && (i.suffix == QWORD_MNEM_SUFFIX
4032 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4034 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4037 if (i.types[n] & (Imm8 | Imm8S))
4039 if (i.types[n] & Imm64)
4043 p = frag_more (size);
4044 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4046 /* This is tough to explain. We end up with this one if we
4047 * have operands that look like
4048 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4049 * obtain the absolute address of the GOT, and it is strongly
4050 * preferable from a performance point of view to avoid using
4051 * a runtime relocation for this. The actual sequence of
4052 * instructions often look something like:
4057 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4059 * The call and pop essentially return the absolute address
4060 * of the label .L66 and store it in %ebx. The linker itself
4061 * will ultimately change the first operand of the addl so
4062 * that %ebx points to the GOT, but to keep things simple, the
4063 * .o file must have this operand set so that it generates not
4064 * the absolute address of .L66, but the absolute address of
4065 * itself. This allows the linker itself simply treat a GOTPC
4066 * relocation as asking for a pcrel offset to the GOT to be
4067 * added in, and the addend of the relocation is stored in the
4068 * operand field for the instruction itself.
4070 * Our job here is to fix the operand so that it would add
4071 * the correct offset so that %ebx would point to itself. The
4072 * thing that is tricky is that .-.L66 will point to the
4073 * beginning of the instruction, so we need to further modify
4074 * the operand so that it will point to itself. There are
4075 * other cases where you have something like:
4077 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4079 * and here no correction would be required. Internally in
4080 * the assembler we treat operands of this form as not being
4081 * pcrel since the '.' is explicitly mentioned, and I wonder
4082 * whether it would simplify matters to do it this way. Who
4083 * knows. In earlier versions of the PIC patches, the
4084 * pcrel_adjust field was used to store the correction, but
4085 * since the expression is not pcrel, I felt it would be
4086 * confusing to do it this way. */
4088 if ((reloc_type == BFD_RELOC_32
4089 || reloc_type == BFD_RELOC_X86_64_32S
4090 || reloc_type == BFD_RELOC_64)
4092 && GOT_symbol == i.op[n].imms->X_add_symbol
4093 && (i.op[n].imms->X_op == O_symbol
4094 || (i.op[n].imms->X_op == O_add
4095 && ((symbol_get_value_expression
4096 (i.op[n].imms->X_op_symbol)->X_op)
4101 if (insn_start_frag == frag_now)
4102 add = (p - frag_now->fr_literal) - insn_start_off;
4107 add = insn_start_frag->fr_fix - insn_start_off;
4108 for (fr = insn_start_frag->fr_next;
4109 fr && fr != frag_now; fr = fr->fr_next)
4111 add += p - frag_now->fr_literal;
4115 reloc_type = BFD_RELOC_386_GOTPC;
4117 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4119 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4120 i.op[n].imms->X_add_number += add;
4122 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4123 i.op[n].imms, 0, reloc_type);
4129 /* x86_cons_fix_new is called via the expression parsing code when a
4130 reloc is needed. We use this hook to get the correct .got reloc. */
4131 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4132 static int cons_sign = -1;
4135 x86_cons_fix_new (fragS *frag,
4140 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4142 got_reloc = NO_RELOC;
4145 if (exp->X_op == O_secrel)
4147 exp->X_op = O_symbol;
4148 r = BFD_RELOC_32_SECREL;
4152 fix_new_exp (frag, off, len, exp, 0, r);
4155 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4156 # define lex_got(reloc, adjust, types) NULL
4158 /* Parse operands of the form
4159 <symbol>@GOTOFF+<nnn>
4160 and similar .plt or .got references.
4162 If we find one, set up the correct relocation in RELOC and copy the
4163 input string, minus the `@GOTOFF' into a malloc'd buffer for
4164 parsing by the calling routine. Return this buffer, and if ADJUST
4165 is non-null set it to the length of the string we removed from the
4166 input line. Otherwise return NULL. */
4168 lex_got (enum bfd_reloc_code_real *reloc,
4170 unsigned int *types)
4172 /* Some of the relocations depend on the size of what field is to
4173 be relocated. But in our callers i386_immediate and i386_displacement
4174 we don't yet know the operand size (this will be set by insn
4175 matching). Hence we record the word32 relocation here,
4176 and adjust the reloc according to the real size in reloc(). */
4177 static const struct {
4179 const enum bfd_reloc_code_real rel[2];
4180 const unsigned int types64;
4182 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4183 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4184 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4185 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4186 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4187 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4188 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4189 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4190 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4191 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4192 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4193 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4194 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4195 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4196 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4197 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4198 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4206 for (cp = input_line_pointer; *cp != '@'; cp++)
4207 if (is_end_of_line[(unsigned char) *cp])
4210 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4214 len = strlen (gotrel[j].str);
4215 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4217 if (gotrel[j].rel[object_64bit] != 0)
4220 char *tmpbuf, *past_reloc;
4222 *reloc = gotrel[j].rel[object_64bit];
4228 if (flag_code != CODE_64BIT)
4229 *types = Imm32|Disp32;
4231 *types = gotrel[j].types64;
4234 if (GOT_symbol == NULL)
4235 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4237 /* Replace the relocation token with ' ', so that
4238 errors like foo@GOTOFF1 will be detected. */
4240 /* The length of the first part of our input line. */
4241 first = cp - input_line_pointer;
4243 /* The second part goes from after the reloc token until
4244 (and including) an end_of_line char. Don't use strlen
4245 here as the end_of_line char may not be a NUL. */
4246 past_reloc = cp + 1 + len;
4247 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4249 second = cp - past_reloc;
4251 /* Allocate and copy string. The trailing NUL shouldn't
4252 be necessary, but be safe. */
4253 tmpbuf = xmalloc (first + second + 2);
4254 memcpy (tmpbuf, input_line_pointer, first);
4255 tmpbuf[first] = ' ';
4256 memcpy (tmpbuf + first + 1, past_reloc, second);
4257 tmpbuf[first + second + 1] = '\0';
4261 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4262 gotrel[j].str, 1 << (5 + object_64bit));
4267 /* Might be a symbol version string. Don't as_bad here. */
4272 x86_cons (exp, size)
4276 if (size == 4 || (object_64bit && size == 8))
4278 /* Handle @GOTOFF and the like in an expression. */
4280 char *gotfree_input_line;
4283 save = input_line_pointer;
4284 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4285 if (gotfree_input_line)
4286 input_line_pointer = gotfree_input_line;
4290 if (gotfree_input_line)
4292 /* expression () has merrily parsed up to the end of line,
4293 or a comma - in the wrong buffer. Transfer how far
4294 input_line_pointer has moved to the right buffer. */
4295 input_line_pointer = (save
4296 + (input_line_pointer - gotfree_input_line)
4298 free (gotfree_input_line);
4306 static void signed_cons (int size)
4308 if (flag_code == CODE_64BIT)
4316 pe_directive_secrel (dummy)
4317 int dummy ATTRIBUTE_UNUSED;
4324 if (exp.X_op == O_symbol)
4325 exp.X_op = O_secrel;
4327 emit_expr (&exp, 4);
4329 while (*input_line_pointer++ == ',');
4331 input_line_pointer--;
4332 demand_empty_rest_of_line ();
4336 static int i386_immediate PARAMS ((char *));
4339 i386_immediate (imm_start)
4342 char *save_input_line_pointer;
4343 char *gotfree_input_line;
4346 unsigned int types = ~0U;
4348 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4350 as_bad (_("only 1 or 2 immediate operands are allowed"));
4354 exp = &im_expressions[i.imm_operands++];
4355 i.op[this_operand].imms = exp;
4357 if (is_space_char (*imm_start))
4360 save_input_line_pointer = input_line_pointer;
4361 input_line_pointer = imm_start;
4363 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4364 if (gotfree_input_line)
4365 input_line_pointer = gotfree_input_line;
4367 exp_seg = expression (exp);
4370 if (*input_line_pointer)
4371 as_bad (_("junk `%s' after expression"), input_line_pointer);
4373 input_line_pointer = save_input_line_pointer;
4374 if (gotfree_input_line)
4375 free (gotfree_input_line);
4377 if (exp->X_op == O_absent || exp->X_op == O_big)
4379 /* Missing or bad expr becomes absolute 0. */
4380 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4382 exp->X_op = O_constant;
4383 exp->X_add_number = 0;
4384 exp->X_add_symbol = (symbolS *) 0;
4385 exp->X_op_symbol = (symbolS *) 0;
4387 else if (exp->X_op == O_constant)
4389 /* Size it properly later. */
4390 i.types[this_operand] |= Imm64;
4391 /* If BFD64, sign extend val. */
4392 if (!use_rela_relocations)
4393 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4394 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4396 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4397 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4398 && exp_seg != absolute_section
4399 && exp_seg != text_section
4400 && exp_seg != data_section
4401 && exp_seg != bss_section
4402 && exp_seg != undefined_section
4403 && !bfd_is_com_section (exp_seg))
4405 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4409 else if (!intel_syntax && exp->X_op == O_register)
4411 as_bad (_("illegal immediate register operand %s"), imm_start);
4416 /* This is an address. The size of the address will be
4417 determined later, depending on destination register,
4418 suffix, or the default for the section. */
4419 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4420 i.types[this_operand] &= types;
4426 static char *i386_scale PARAMS ((char *));
4433 char *save = input_line_pointer;
4435 input_line_pointer = scale;
4436 val = get_absolute_expression ();
4441 i.log2_scale_factor = 0;
4444 i.log2_scale_factor = 1;
4447 i.log2_scale_factor = 2;
4450 i.log2_scale_factor = 3;
4454 char sep = *input_line_pointer;
4456 *input_line_pointer = '\0';
4457 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4459 *input_line_pointer = sep;
4460 input_line_pointer = save;
4464 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4466 as_warn (_("scale factor of %d without an index register"),
4467 1 << i.log2_scale_factor);
4468 #if SCALE1_WHEN_NO_INDEX
4469 i.log2_scale_factor = 0;
4472 scale = input_line_pointer;
4473 input_line_pointer = save;
4477 static int i386_displacement PARAMS ((char *, char *));
4480 i386_displacement (disp_start, disp_end)
4486 char *save_input_line_pointer;
4487 char *gotfree_input_line;
4488 int bigdisp, override;
4489 unsigned int types = Disp;
4491 if ((i.types[this_operand] & JumpAbsolute)
4492 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4495 override = (i.prefix[ADDR_PREFIX] != 0);
4499 /* For PC-relative branches, the width of the displacement
4500 is dependent upon data size, not address size. */
4502 override = (i.prefix[DATA_PREFIX] != 0);
4504 if (flag_code == CODE_64BIT)
4507 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4509 : Disp32S | Disp32);
4511 bigdisp = Disp64 | Disp32S | Disp32;
4518 override = (i.suffix == (flag_code != CODE_16BIT
4520 : LONG_MNEM_SUFFIX));
4523 if ((flag_code == CODE_16BIT) ^ override)
4526 i.types[this_operand] |= bigdisp;
4528 exp = &disp_expressions[i.disp_operands];
4529 i.op[this_operand].disps = exp;
4531 save_input_line_pointer = input_line_pointer;
4532 input_line_pointer = disp_start;
4533 END_STRING_AND_SAVE (disp_end);
4535 #ifndef GCC_ASM_O_HACK
4536 #define GCC_ASM_O_HACK 0
4539 END_STRING_AND_SAVE (disp_end + 1);
4540 if ((i.types[this_operand] & BaseIndex) != 0
4541 && displacement_string_end[-1] == '+')
4543 /* This hack is to avoid a warning when using the "o"
4544 constraint within gcc asm statements.
4547 #define _set_tssldt_desc(n,addr,limit,type) \
4548 __asm__ __volatile__ ( \
4550 "movw %w1,2+%0\n\t" \
4552 "movb %b1,4+%0\n\t" \
4553 "movb %4,5+%0\n\t" \
4554 "movb $0,6+%0\n\t" \
4555 "movb %h1,7+%0\n\t" \
4557 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4559 This works great except that the output assembler ends
4560 up looking a bit weird if it turns out that there is
4561 no offset. You end up producing code that looks like:
4574 So here we provide the missing zero. */
4576 *displacement_string_end = '0';
4579 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4580 if (gotfree_input_line)
4581 input_line_pointer = gotfree_input_line;
4583 exp_seg = expression (exp);
4586 if (*input_line_pointer)
4587 as_bad (_("junk `%s' after expression"), input_line_pointer);
4589 RESTORE_END_STRING (disp_end + 1);
4591 RESTORE_END_STRING (disp_end);
4592 input_line_pointer = save_input_line_pointer;
4593 if (gotfree_input_line)
4594 free (gotfree_input_line);
4596 /* We do this to make sure that the section symbol is in
4597 the symbol table. We will ultimately change the relocation
4598 to be relative to the beginning of the section. */
4599 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4600 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4601 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4603 if (exp->X_op != O_symbol)
4605 as_bad (_("bad expression used with @%s"),
4606 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4612 if (S_IS_LOCAL (exp->X_add_symbol)
4613 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4614 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4615 exp->X_op = O_subtract;
4616 exp->X_op_symbol = GOT_symbol;
4617 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4618 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4619 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4620 i.reloc[this_operand] = BFD_RELOC_64;
4622 i.reloc[this_operand] = BFD_RELOC_32;
4625 if (exp->X_op == O_absent || exp->X_op == O_big)
4627 /* Missing or bad expr becomes absolute 0. */
4628 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4630 exp->X_op = O_constant;
4631 exp->X_add_number = 0;
4632 exp->X_add_symbol = (symbolS *) 0;
4633 exp->X_op_symbol = (symbolS *) 0;
4636 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4637 if (exp->X_op != O_constant
4638 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4639 && exp_seg != absolute_section
4640 && exp_seg != text_section
4641 && exp_seg != data_section
4642 && exp_seg != bss_section
4643 && exp_seg != undefined_section
4644 && !bfd_is_com_section (exp_seg))
4646 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4651 if (!(i.types[this_operand] & ~Disp))
4652 i.types[this_operand] &= types;
4657 static int i386_index_check PARAMS ((const char *));
4659 /* Make sure the memory operand we've been dealt is valid.
4660 Return 1 on success, 0 on a failure. */
4663 i386_index_check (operand_string)
4664 const char *operand_string;
4667 #if INFER_ADDR_PREFIX
4673 if ((current_templates->start->cpu_flags & CpuSVME)
4674 && current_templates->end[-1].operand_types[0] == AnyMem)
4676 /* Memory operands of SVME insns are special in that they only allow
4677 rAX as their memory address and ignore any segment override. */
4680 /* SKINIT is even more restrictive: it always requires EAX. */
4681 if (strcmp (current_templates->start->name, "skinit") == 0)
4683 else if (flag_code == CODE_64BIT)
4684 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4686 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4690 || !(i.base_reg->reg_type & Acc)
4691 || !(i.base_reg->reg_type & RegXX)
4693 || (i.types[0] & Disp))
4696 else if (flag_code == CODE_64BIT)
4698 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4701 && ((i.base_reg->reg_type & RegXX) == 0)
4702 && (i.base_reg->reg_type != BaseIndex
4705 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4706 != (RegXX | BaseIndex))))
4711 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4715 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4716 != (Reg16 | BaseIndex)))
4718 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4719 != (Reg16 | BaseIndex))
4721 && i.base_reg->reg_num < 6
4722 && i.index_reg->reg_num >= 6
4723 && i.log2_scale_factor == 0))))
4730 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4732 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4733 != (Reg32 | BaseIndex))))
4739 #if INFER_ADDR_PREFIX
4740 if (i.prefix[ADDR_PREFIX] == 0)
4742 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4744 /* Change the size of any displacement too. At most one of
4745 Disp16 or Disp32 is set.
4746 FIXME. There doesn't seem to be any real need for separate
4747 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4748 Removing them would probably clean up the code quite a lot. */
4749 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4750 i.types[this_operand] ^= (Disp16 | Disp32);
4755 as_bad (_("`%s' is not a valid base/index expression"),
4759 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4761 flag_code_names[flag_code]);
4766 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4770 i386_operand (operand_string)
4771 char *operand_string;
4775 char *op_string = operand_string;
4777 if (is_space_char (*op_string))
4780 /* We check for an absolute prefix (differentiating,
4781 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4782 if (*op_string == ABSOLUTE_PREFIX)
4785 if (is_space_char (*op_string))
4787 i.types[this_operand] |= JumpAbsolute;
4790 /* Check if operand is a register. */
4791 if ((r = parse_register (op_string, &end_op)) != NULL)
4793 /* Check for a segment override by searching for ':' after a
4794 segment register. */
4796 if (is_space_char (*op_string))
4798 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4803 i.seg[i.mem_operands] = &es;
4806 i.seg[i.mem_operands] = &cs;
4809 i.seg[i.mem_operands] = &ss;
4812 i.seg[i.mem_operands] = &ds;
4815 i.seg[i.mem_operands] = &fs;
4818 i.seg[i.mem_operands] = &gs;
4822 /* Skip the ':' and whitespace. */
4824 if (is_space_char (*op_string))
4827 if (!is_digit_char (*op_string)
4828 && !is_identifier_char (*op_string)
4829 && *op_string != '('
4830 && *op_string != ABSOLUTE_PREFIX)
4832 as_bad (_("bad memory operand `%s'"), op_string);
4835 /* Handle case of %es:*foo. */
4836 if (*op_string == ABSOLUTE_PREFIX)
4839 if (is_space_char (*op_string))
4841 i.types[this_operand] |= JumpAbsolute;
4843 goto do_memory_reference;
4847 as_bad (_("junk `%s' after register"), op_string);
4850 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4851 i.op[this_operand].regs = r;
4854 else if (*op_string == REGISTER_PREFIX)
4856 as_bad (_("bad register name `%s'"), op_string);
4859 else if (*op_string == IMMEDIATE_PREFIX)
4862 if (i.types[this_operand] & JumpAbsolute)
4864 as_bad (_("immediate operand illegal with absolute jump"));
4867 if (!i386_immediate (op_string))
4870 else if (is_digit_char (*op_string)
4871 || is_identifier_char (*op_string)
4872 || *op_string == '(')
4874 /* This is a memory reference of some sort. */
4877 /* Start and end of displacement string expression (if found). */
4878 char *displacement_string_start;
4879 char *displacement_string_end;
4881 do_memory_reference:
4882 if ((i.mem_operands == 1
4883 && (current_templates->start->opcode_modifier & IsString) == 0)
4884 || i.mem_operands == 2)
4886 as_bad (_("too many memory references for `%s'"),
4887 current_templates->start->name);
4891 /* Check for base index form. We detect the base index form by
4892 looking for an ')' at the end of the operand, searching
4893 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4895 base_string = op_string + strlen (op_string);
4898 if (is_space_char (*base_string))
4901 /* If we only have a displacement, set-up for it to be parsed later. */
4902 displacement_string_start = op_string;
4903 displacement_string_end = base_string + 1;
4905 if (*base_string == ')')
4908 unsigned int parens_balanced = 1;
4909 /* We've already checked that the number of left & right ()'s are
4910 equal, so this loop will not be infinite. */
4914 if (*base_string == ')')
4916 if (*base_string == '(')
4919 while (parens_balanced);
4921 temp_string = base_string;
4923 /* Skip past '(' and whitespace. */
4925 if (is_space_char (*base_string))
4928 if (*base_string == ','
4929 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
4931 displacement_string_end = temp_string;
4933 i.types[this_operand] |= BaseIndex;
4937 base_string = end_op;
4938 if (is_space_char (*base_string))
4942 /* There may be an index reg or scale factor here. */
4943 if (*base_string == ',')
4946 if (is_space_char (*base_string))
4949 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
4951 base_string = end_op;
4952 if (is_space_char (*base_string))
4954 if (*base_string == ',')
4957 if (is_space_char (*base_string))
4960 else if (*base_string != ')')
4962 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4967 else if (*base_string == REGISTER_PREFIX)
4969 as_bad (_("bad register name `%s'"), base_string);
4973 /* Check for scale factor. */
4974 if (*base_string != ')')
4976 char *end_scale = i386_scale (base_string);
4981 base_string = end_scale;
4982 if (is_space_char (*base_string))
4984 if (*base_string != ')')
4986 as_bad (_("expecting `)' after scale factor in `%s'"),
4991 else if (!i.index_reg)
4993 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4998 else if (*base_string != ')')
5000 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5005 else if (*base_string == REGISTER_PREFIX)
5007 as_bad (_("bad register name `%s'"), base_string);
5012 /* If there's an expression beginning the operand, parse it,
5013 assuming displacement_string_start and
5014 displacement_string_end are meaningful. */
5015 if (displacement_string_start != displacement_string_end)
5017 if (!i386_displacement (displacement_string_start,
5018 displacement_string_end))
5022 /* Special case for (%dx) while doing input/output op. */
5024 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5026 && i.log2_scale_factor == 0
5027 && i.seg[i.mem_operands] == 0
5028 && (i.types[this_operand] & Disp) == 0)
5030 i.types[this_operand] = InOutPortReg;
5034 if (i386_index_check (operand_string) == 0)
5040 /* It's not a memory operand; argh! */
5041 as_bad (_("invalid char %s beginning operand %d `%s'"),
5042 output_invalid (*op_string),
5047 return 1; /* Normal return. */
5050 /* md_estimate_size_before_relax()
5052 Called just before relax() for rs_machine_dependent frags. The x86
5053 assembler uses these frags to handle variable size jump
5056 Any symbol that is now undefined will not become defined.
5057 Return the correct fr_subtype in the frag.
5058 Return the initial "guess for variable size of frag" to caller.
5059 The guess is actually the growth beyond the fixed part. Whatever
5060 we do to grow the fixed or variable part contributes to our
5064 md_estimate_size_before_relax (fragP, segment)
5068 /* We've already got fragP->fr_subtype right; all we have to do is
5069 check for un-relaxable symbols. On an ELF system, we can't relax
5070 an externally visible symbol, because it may be overridden by a
5072 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5073 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5075 && (S_IS_EXTERNAL (fragP->fr_symbol)
5076 || S_IS_WEAK (fragP->fr_symbol)))
5080 /* Symbol is undefined in this segment, or we need to keep a
5081 reloc so that weak symbols can be overridden. */
5082 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5083 enum bfd_reloc_code_real reloc_type;
5084 unsigned char *opcode;
5087 if (fragP->fr_var != NO_RELOC)
5088 reloc_type = fragP->fr_var;
5090 reloc_type = BFD_RELOC_16_PCREL;
5092 reloc_type = BFD_RELOC_32_PCREL;
5094 old_fr_fix = fragP->fr_fix;
5095 opcode = (unsigned char *) fragP->fr_opcode;
5097 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5100 /* Make jmp (0xeb) a (d)word displacement jump. */
5102 fragP->fr_fix += size;
5103 fix_new (fragP, old_fr_fix, size,
5105 fragP->fr_offset, 1,
5111 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5113 /* Negate the condition, and branch past an
5114 unconditional jump. */
5117 /* Insert an unconditional jump. */
5119 /* We added two extra opcode bytes, and have a two byte
5121 fragP->fr_fix += 2 + 2;
5122 fix_new (fragP, old_fr_fix + 2, 2,
5124 fragP->fr_offset, 1,
5131 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5136 fixP = fix_new (fragP, old_fr_fix, 1,
5138 fragP->fr_offset, 1,
5140 fixP->fx_signed = 1;
5144 /* This changes the byte-displacement jump 0x7N
5145 to the (d)word-displacement jump 0x0f,0x8N. */
5146 opcode[1] = opcode[0] + 0x10;
5147 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5148 /* We've added an opcode byte. */
5149 fragP->fr_fix += 1 + size;
5150 fix_new (fragP, old_fr_fix + 1, size,
5152 fragP->fr_offset, 1,
5157 BAD_CASE (fragP->fr_subtype);
5161 return fragP->fr_fix - old_fr_fix;
5164 /* Guess size depending on current relax state. Initially the relax
5165 state will correspond to a short jump and we return 1, because
5166 the variable part of the frag (the branch offset) is one byte
5167 long. However, we can relax a section more than once and in that
5168 case we must either set fr_subtype back to the unrelaxed state,
5169 or return the value for the appropriate branch. */
5170 return md_relax_table[fragP->fr_subtype].rlx_length;
5173 /* Called after relax() is finished.
5175 In: Address of frag.
5176 fr_type == rs_machine_dependent.
5177 fr_subtype is what the address relaxed to.
5179 Out: Any fixSs and constants are set up.
5180 Caller will turn frag into a ".space 0". */
5183 md_convert_frag (abfd, sec, fragP)
5184 bfd *abfd ATTRIBUTE_UNUSED;
5185 segT sec ATTRIBUTE_UNUSED;
5188 unsigned char *opcode;
5189 unsigned char *where_to_put_displacement = NULL;
5190 offsetT target_address;
5191 offsetT opcode_address;
5192 unsigned int extension = 0;
5193 offsetT displacement_from_opcode_start;
5195 opcode = (unsigned char *) fragP->fr_opcode;
5197 /* Address we want to reach in file space. */
5198 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5200 /* Address opcode resides at in file space. */
5201 opcode_address = fragP->fr_address + fragP->fr_fix;
5203 /* Displacement from opcode start to fill into instruction. */
5204 displacement_from_opcode_start = target_address - opcode_address;
5206 if ((fragP->fr_subtype & BIG) == 0)
5208 /* Don't have to change opcode. */
5209 extension = 1; /* 1 opcode + 1 displacement */
5210 where_to_put_displacement = &opcode[1];
5214 if (no_cond_jump_promotion
5215 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5216 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5218 switch (fragP->fr_subtype)
5220 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5221 extension = 4; /* 1 opcode + 4 displacement */
5223 where_to_put_displacement = &opcode[1];
5226 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5227 extension = 2; /* 1 opcode + 2 displacement */
5229 where_to_put_displacement = &opcode[1];
5232 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5233 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5234 extension = 5; /* 2 opcode + 4 displacement */
5235 opcode[1] = opcode[0] + 0x10;
5236 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5237 where_to_put_displacement = &opcode[2];
5240 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5241 extension = 3; /* 2 opcode + 2 displacement */
5242 opcode[1] = opcode[0] + 0x10;
5243 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5244 where_to_put_displacement = &opcode[2];
5247 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5252 where_to_put_displacement = &opcode[3];
5256 BAD_CASE (fragP->fr_subtype);
5261 /* If size if less then four we are sure that the operand fits,
5262 but if it's 4, then it could be that the displacement is larger
5264 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5266 && ((addressT) (displacement_from_opcode_start - extension
5267 + ((addressT) 1 << 31))
5268 > (((addressT) 2 << 31) - 1)))
5270 as_bad_where (fragP->fr_file, fragP->fr_line,
5271 _("jump target out of range"));
5272 /* Make us emit 0. */
5273 displacement_from_opcode_start = extension;
5275 /* Now put displacement after opcode. */
5276 md_number_to_chars ((char *) where_to_put_displacement,
5277 (valueT) (displacement_from_opcode_start - extension),
5278 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5279 fragP->fr_fix += extension;
5282 /* Size of byte displacement jmp. */
5283 int md_short_jump_size = 2;
5285 /* Size of dword displacement jmp. */
5286 int md_long_jump_size = 5;
5289 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5291 addressT from_addr, to_addr;
5292 fragS *frag ATTRIBUTE_UNUSED;
5293 symbolS *to_symbol ATTRIBUTE_UNUSED;
5297 offset = to_addr - (from_addr + 2);
5298 /* Opcode for byte-disp jump. */
5299 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5300 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5304 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5306 addressT from_addr, to_addr;
5307 fragS *frag ATTRIBUTE_UNUSED;
5308 symbolS *to_symbol ATTRIBUTE_UNUSED;
5312 offset = to_addr - (from_addr + 5);
5313 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5314 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5317 /* Apply a fixup (fixS) to segment data, once it has been determined
5318 by our caller that we have all the info we need to fix it up.
5320 On the 386, immediates, displacements, and data pointers are all in
5321 the same (little-endian) format, so we don't need to care about which
5325 md_apply_fix (fixP, valP, seg)
5326 /* The fix we're to put in. */
5328 /* Pointer to the value of the bits. */
5330 /* Segment fix is from. */
5331 segT seg ATTRIBUTE_UNUSED;
5333 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5334 valueT value = *valP;
5336 #if !defined (TE_Mach)
5339 switch (fixP->fx_r_type)
5345 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5348 case BFD_RELOC_X86_64_32S:
5349 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5352 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5355 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5360 if (fixP->fx_addsy != NULL
5361 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5362 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5363 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5364 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5365 && !use_rela_relocations)
5367 /* This is a hack. There should be a better way to handle this.
5368 This covers for the fact that bfd_install_relocation will
5369 subtract the current location (for partial_inplace, PC relative
5370 relocations); see more below. */
5374 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5377 value += fixP->fx_where + fixP->fx_frag->fr_address;
5379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5382 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5385 || (symbol_section_p (fixP->fx_addsy)
5386 && sym_seg != absolute_section))
5387 && !generic_force_reloc (fixP))
5389 /* Yes, we add the values in twice. This is because
5390 bfd_install_relocation subtracts them out again. I think
5391 bfd_install_relocation is broken, but I don't dare change
5393 value += fixP->fx_where + fixP->fx_frag->fr_address;
5397 #if defined (OBJ_COFF) && defined (TE_PE)
5398 /* For some reason, the PE format does not store a
5399 section address offset for a PC relative symbol. */
5400 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5401 || S_IS_WEAK (fixP->fx_addsy))
5402 value += md_pcrel_from (fixP);
5406 /* Fix a few things - the dynamic linker expects certain values here,
5407 and we must not disappoint it. */
5408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5409 if (IS_ELF && fixP->fx_addsy)
5410 switch (fixP->fx_r_type)
5412 case BFD_RELOC_386_PLT32:
5413 case BFD_RELOC_X86_64_PLT32:
5414 /* Make the jump instruction point to the address of the operand. At
5415 runtime we merely add the offset to the actual PLT entry. */
5419 case BFD_RELOC_386_TLS_GD:
5420 case BFD_RELOC_386_TLS_LDM:
5421 case BFD_RELOC_386_TLS_IE_32:
5422 case BFD_RELOC_386_TLS_IE:
5423 case BFD_RELOC_386_TLS_GOTIE:
5424 case BFD_RELOC_386_TLS_GOTDESC:
5425 case BFD_RELOC_X86_64_TLSGD:
5426 case BFD_RELOC_X86_64_TLSLD:
5427 case BFD_RELOC_X86_64_GOTTPOFF:
5428 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5429 value = 0; /* Fully resolved at runtime. No addend. */
5431 case BFD_RELOC_386_TLS_LE:
5432 case BFD_RELOC_386_TLS_LDO_32:
5433 case BFD_RELOC_386_TLS_LE_32:
5434 case BFD_RELOC_X86_64_DTPOFF32:
5435 case BFD_RELOC_X86_64_DTPOFF64:
5436 case BFD_RELOC_X86_64_TPOFF32:
5437 case BFD_RELOC_X86_64_TPOFF64:
5438 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5441 case BFD_RELOC_386_TLS_DESC_CALL:
5442 case BFD_RELOC_X86_64_TLSDESC_CALL:
5443 value = 0; /* Fully resolved at runtime. No addend. */
5444 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5448 case BFD_RELOC_386_GOT32:
5449 case BFD_RELOC_X86_64_GOT32:
5450 value = 0; /* Fully resolved at runtime. No addend. */
5453 case BFD_RELOC_VTABLE_INHERIT:
5454 case BFD_RELOC_VTABLE_ENTRY:
5461 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5463 #endif /* !defined (TE_Mach) */
5465 /* Are we finished with this relocation now? */
5466 if (fixP->fx_addsy == NULL)
5468 else if (use_rela_relocations)
5470 fixP->fx_no_overflow = 1;
5471 /* Remember value for tc_gen_reloc. */
5472 fixP->fx_addnumber = value;
5476 md_number_to_chars (p, value, fixP->fx_size);
5479 #define MAX_LITTLENUMS 6
5481 /* Turn the string pointed to by litP into a floating point constant
5482 of type TYPE, and emit the appropriate bytes. The number of
5483 LITTLENUMS emitted is stored in *SIZEP. An error message is
5484 returned, or NULL on OK. */
5487 md_atof (type, litP, sizeP)
5493 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5494 LITTLENUM_TYPE *wordP;
5516 return _("Bad call to md_atof ()");
5518 t = atof_ieee (input_line_pointer, type, words);
5520 input_line_pointer = t;
5522 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5523 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5524 the bigendian 386. */
5525 for (wordP = words + prec - 1; prec--;)
5527 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5528 litP += sizeof (LITTLENUM_TYPE);
5533 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5540 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5543 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5544 "(0x%x)", (unsigned char) c);
5545 return output_invalid_buf;
5548 /* REG_STRING starts *before* REGISTER_PREFIX. */
5550 static const reg_entry *
5551 parse_real_register (char *reg_string, char **end_op)
5553 char *s = reg_string;
5555 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5558 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5559 if (*s == REGISTER_PREFIX)
5562 if (is_space_char (*s))
5566 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5568 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5569 return (const reg_entry *) NULL;
5573 /* For naked regs, make sure that we are not dealing with an identifier.
5574 This prevents confusing an identifier like `eax_var' with register
5576 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5577 return (const reg_entry *) NULL;
5581 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5583 /* Handle floating point regs, allowing spaces in the (i) part. */
5584 if (r == i386_regtab /* %st is first entry of table */)
5586 if (is_space_char (*s))
5591 if (is_space_char (*s))
5593 if (*s >= '0' && *s <= '7')
5595 r = &i386_float_regtab[*s - '0'];
5597 if (is_space_char (*s))
5605 /* We have "%st(" then garbage. */
5606 return (const reg_entry *) NULL;
5611 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5612 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5613 && flag_code != CODE_64BIT)
5614 return (const reg_entry *) NULL;
5619 /* REG_STRING starts *before* REGISTER_PREFIX. */
5621 static const reg_entry *
5622 parse_register (char *reg_string, char **end_op)
5626 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5627 r = parse_real_register (reg_string, end_op);
5632 char *save = input_line_pointer;
5636 input_line_pointer = reg_string;
5637 c = get_symbol_end ();
5638 symbolP = symbol_find (reg_string);
5639 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5641 const expressionS *e = symbol_get_value_expression (symbolP);
5643 know (e->X_op == O_register);
5644 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5645 r = i386_regtab + e->X_add_number;
5646 *end_op = input_line_pointer;
5648 *input_line_pointer = c;
5649 input_line_pointer = save;
5655 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5658 char *end = input_line_pointer;
5661 r = parse_register (name, &input_line_pointer);
5662 if (r && end <= input_line_pointer)
5664 *nextcharP = *input_line_pointer;
5665 *input_line_pointer = 0;
5666 e->X_op = O_register;
5667 e->X_add_number = r - i386_regtab;
5670 input_line_pointer = end;
5676 md_operand (expressionS *e)
5678 if (*input_line_pointer == REGISTER_PREFIX)
5681 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5685 e->X_op = O_register;
5686 e->X_add_number = r - i386_regtab;
5687 input_line_pointer = end;
5693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5694 const char *md_shortopts = "kVQ:sqn";
5696 const char *md_shortopts = "qn";
5699 #define OPTION_32 (OPTION_MD_BASE + 0)
5700 #define OPTION_64 (OPTION_MD_BASE + 1)
5701 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5702 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5703 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5705 struct option md_longopts[] = {
5706 {"32", no_argument, NULL, OPTION_32},
5707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5708 {"64", no_argument, NULL, OPTION_64},
5710 {"divide", no_argument, NULL, OPTION_DIVIDE},
5711 {"march", required_argument, NULL, OPTION_MARCH},
5712 {"mtune", required_argument, NULL, OPTION_MTUNE},
5713 {NULL, no_argument, NULL, 0}
5715 size_t md_longopts_size = sizeof (md_longopts);
5718 md_parse_option (int c, char *arg)
5725 optimize_align_code = 0;
5732 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5733 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5734 should be emitted or not. FIXME: Not implemented. */
5738 /* -V: SVR4 argument to print version ID. */
5740 print_version_id ();
5743 /* -k: Ignore for FreeBSD compatibility. */
5748 /* -s: On i386 Solaris, this tells the native assembler to use
5749 .stab instead of .stab.excl. We always use .stab anyhow. */
5754 const char **list, **l;
5756 list = bfd_target_list ();
5757 for (l = list; *l != NULL; l++)
5758 if (strcmp (*l, "elf64-x86-64") == 0)
5760 default_arch = "x86_64";
5764 as_fatal (_("No compiled in support for x86_64"));
5771 default_arch = "i386";
5775 #ifdef SVR4_COMMENT_CHARS
5780 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5782 for (s = i386_comment_chars; *s != '\0'; s++)
5786 i386_comment_chars = n;
5793 as_fatal (_("Invalid -march= option: `%s'"), arg);
5794 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5796 if (strcmp (arg, cpu_arch [i].name) == 0)
5798 cpu_arch_isa = cpu_arch[i].type;
5799 cpu_arch_isa_flags = cpu_arch[i].flags;
5800 if (!cpu_arch_tune_set)
5802 cpu_arch_tune = cpu_arch_isa;
5803 cpu_arch_tune_flags = cpu_arch_isa_flags;
5808 if (i >= ARRAY_SIZE (cpu_arch))
5809 as_fatal (_("Invalid -march= option: `%s'"), arg);
5814 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5815 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5817 if (strcmp (arg, cpu_arch [i].name) == 0)
5819 cpu_arch_tune_set = 1;
5820 cpu_arch_tune = cpu_arch [i].type;
5821 cpu_arch_tune_flags = cpu_arch[i].flags;
5825 if (i >= ARRAY_SIZE (cpu_arch))
5826 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5836 md_show_usage (stream)
5839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5840 fprintf (stream, _("\
5842 -V print assembler version number\n\
5845 fprintf (stream, _("\
5846 -n Do not optimize code alignment\n\
5847 -q quieten some warnings\n"));
5848 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5849 fprintf (stream, _("\
5852 #ifdef SVR4_COMMENT_CHARS
5853 fprintf (stream, _("\
5854 --divide do not treat `/' as a comment character\n"));
5856 fprintf (stream, _("\
5857 --divide ignored\n"));
5859 fprintf (stream, _("\
5860 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5861 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5862 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5866 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5867 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5869 /* Pick the target format to use. */
5872 i386_target_format ()
5874 if (!strcmp (default_arch, "x86_64"))
5876 set_code_flag (CODE_64BIT);
5877 if (cpu_arch_isa_flags == 0)
5878 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5879 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5881 if (cpu_arch_tune_flags == 0)
5882 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5883 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5886 else if (!strcmp (default_arch, "i386"))
5888 set_code_flag (CODE_32BIT);
5889 if (cpu_arch_isa_flags == 0)
5890 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5891 if (cpu_arch_tune_flags == 0)
5892 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5895 as_fatal (_("Unknown architecture"));
5896 switch (OUTPUT_FLAVOR)
5898 #ifdef OBJ_MAYBE_AOUT
5899 case bfd_target_aout_flavour:
5900 return AOUT_TARGET_FORMAT;
5902 #ifdef OBJ_MAYBE_COFF
5903 case bfd_target_coff_flavour:
5906 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5907 case bfd_target_elf_flavour:
5909 if (flag_code == CODE_64BIT)
5912 use_rela_relocations = 1;
5914 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5923 #endif /* OBJ_MAYBE_ more than one */
5925 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5926 void i386_elf_emit_arch_note ()
5928 if (IS_ELF && cpu_arch_name != NULL)
5931 asection *seg = now_seg;
5932 subsegT subseg = now_subseg;
5933 Elf_Internal_Note i_note;
5934 Elf_External_Note e_note;
5935 asection *note_secp;
5938 /* Create the .note section. */
5939 note_secp = subseg_new (".note", 0);
5940 bfd_set_section_flags (stdoutput,
5942 SEC_HAS_CONTENTS | SEC_READONLY);
5944 /* Process the arch string. */
5945 len = strlen (cpu_arch_name);
5947 i_note.namesz = len + 1;
5949 i_note.type = NT_ARCH;
5950 p = frag_more (sizeof (e_note.namesz));
5951 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5952 p = frag_more (sizeof (e_note.descsz));
5953 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5954 p = frag_more (sizeof (e_note.type));
5955 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5956 p = frag_more (len + 1);
5957 strcpy (p, cpu_arch_name);
5959 frag_align (2, 0, 0);
5961 subseg_set (seg, subseg);
5967 md_undefined_symbol (name)
5970 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5971 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5972 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5973 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5977 if (symbol_find (name))
5978 as_bad (_("GOT already in symbol table"));
5979 GOT_symbol = symbol_new (name, undefined_section,
5980 (valueT) 0, &zero_address_frag);
5987 /* Round up a section size to the appropriate boundary. */
5990 md_section_align (segment, size)
5991 segT segment ATTRIBUTE_UNUSED;
5994 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5995 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5997 /* For a.out, force the section size to be aligned. If we don't do
5998 this, BFD will align it for us, but it will not write out the
5999 final bytes of the section. This may be a bug in BFD, but it is
6000 easier to fix it here since that is how the other a.out targets
6004 align = bfd_get_section_alignment (stdoutput, segment);
6005 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6012 /* On the i386, PC-relative offsets are relative to the start of the
6013 next instruction. That is, the address of the offset, plus its
6014 size, since the offset is always the last part of the insn. */
6017 md_pcrel_from (fixP)
6020 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6027 int ignore ATTRIBUTE_UNUSED;
6031 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6033 obj_elf_section_change_hook ();
6035 temp = get_absolute_expression ();
6036 subseg_set (bss_section, (subsegT) temp);
6037 demand_empty_rest_of_line ();
6043 i386_validate_fix (fixp)
6046 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6048 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6052 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6057 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6059 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6066 tc_gen_reloc (section, fixp)
6067 asection *section ATTRIBUTE_UNUSED;
6071 bfd_reloc_code_real_type code;
6073 switch (fixp->fx_r_type)
6075 case BFD_RELOC_X86_64_PLT32:
6076 case BFD_RELOC_X86_64_GOT32:
6077 case BFD_RELOC_X86_64_GOTPCREL:
6078 case BFD_RELOC_386_PLT32:
6079 case BFD_RELOC_386_GOT32:
6080 case BFD_RELOC_386_GOTOFF:
6081 case BFD_RELOC_386_GOTPC:
6082 case BFD_RELOC_386_TLS_GD:
6083 case BFD_RELOC_386_TLS_LDM:
6084 case BFD_RELOC_386_TLS_LDO_32:
6085 case BFD_RELOC_386_TLS_IE_32:
6086 case BFD_RELOC_386_TLS_IE:
6087 case BFD_RELOC_386_TLS_GOTIE:
6088 case BFD_RELOC_386_TLS_LE_32:
6089 case BFD_RELOC_386_TLS_LE:
6090 case BFD_RELOC_386_TLS_GOTDESC:
6091 case BFD_RELOC_386_TLS_DESC_CALL:
6092 case BFD_RELOC_X86_64_TLSGD:
6093 case BFD_RELOC_X86_64_TLSLD:
6094 case BFD_RELOC_X86_64_DTPOFF32:
6095 case BFD_RELOC_X86_64_DTPOFF64:
6096 case BFD_RELOC_X86_64_GOTTPOFF:
6097 case BFD_RELOC_X86_64_TPOFF32:
6098 case BFD_RELOC_X86_64_TPOFF64:
6099 case BFD_RELOC_X86_64_GOTOFF64:
6100 case BFD_RELOC_X86_64_GOTPC32:
6101 case BFD_RELOC_X86_64_GOT64:
6102 case BFD_RELOC_X86_64_GOTPCREL64:
6103 case BFD_RELOC_X86_64_GOTPC64:
6104 case BFD_RELOC_X86_64_GOTPLT64:
6105 case BFD_RELOC_X86_64_PLTOFF64:
6106 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6107 case BFD_RELOC_X86_64_TLSDESC_CALL:
6109 case BFD_RELOC_VTABLE_ENTRY:
6110 case BFD_RELOC_VTABLE_INHERIT:
6112 case BFD_RELOC_32_SECREL:
6114 code = fixp->fx_r_type;
6116 case BFD_RELOC_X86_64_32S:
6117 if (!fixp->fx_pcrel)
6119 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6120 code = fixp->fx_r_type;
6126 switch (fixp->fx_size)
6129 as_bad_where (fixp->fx_file, fixp->fx_line,
6130 _("can not do %d byte pc-relative relocation"),
6132 code = BFD_RELOC_32_PCREL;
6134 case 1: code = BFD_RELOC_8_PCREL; break;
6135 case 2: code = BFD_RELOC_16_PCREL; break;
6136 case 4: code = BFD_RELOC_32_PCREL; break;
6138 case 8: code = BFD_RELOC_64_PCREL; break;
6144 switch (fixp->fx_size)
6147 as_bad_where (fixp->fx_file, fixp->fx_line,
6148 _("can not do %d byte relocation"),
6150 code = BFD_RELOC_32;
6152 case 1: code = BFD_RELOC_8; break;
6153 case 2: code = BFD_RELOC_16; break;
6154 case 4: code = BFD_RELOC_32; break;
6156 case 8: code = BFD_RELOC_64; break;
6163 if ((code == BFD_RELOC_32
6164 || code == BFD_RELOC_32_PCREL
6165 || code == BFD_RELOC_X86_64_32S)
6167 && fixp->fx_addsy == GOT_symbol)
6170 code = BFD_RELOC_386_GOTPC;
6172 code = BFD_RELOC_X86_64_GOTPC32;
6174 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6176 && fixp->fx_addsy == GOT_symbol)
6178 code = BFD_RELOC_X86_64_GOTPC64;
6181 rel = (arelent *) xmalloc (sizeof (arelent));
6182 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6183 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6185 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6187 if (!use_rela_relocations)
6189 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6190 vtable entry to be used in the relocation's section offset. */
6191 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6192 rel->address = fixp->fx_offset;
6196 /* Use the rela in 64bit mode. */
6199 if (!fixp->fx_pcrel)
6200 rel->addend = fixp->fx_offset;
6204 case BFD_RELOC_X86_64_PLT32:
6205 case BFD_RELOC_X86_64_GOT32:
6206 case BFD_RELOC_X86_64_GOTPCREL:
6207 case BFD_RELOC_X86_64_TLSGD:
6208 case BFD_RELOC_X86_64_TLSLD:
6209 case BFD_RELOC_X86_64_GOTTPOFF:
6210 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6211 case BFD_RELOC_X86_64_TLSDESC_CALL:
6212 rel->addend = fixp->fx_offset - fixp->fx_size;
6215 rel->addend = (section->vma
6217 + fixp->fx_addnumber
6218 + md_pcrel_from (fixp));
6223 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6224 if (rel->howto == NULL)
6226 as_bad_where (fixp->fx_file, fixp->fx_line,
6227 _("cannot represent relocation type %s"),
6228 bfd_get_reloc_code_name (code));
6229 /* Set howto to a garbage value so that we can keep going. */
6230 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6231 assert (rel->howto != NULL);
6238 /* Parse operands using Intel syntax. This implements a recursive descent
6239 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6242 FIXME: We do not recognize the full operand grammar defined in the MASM
6243 documentation. In particular, all the structure/union and
6244 high-level macro operands are missing.
6246 Uppercase words are terminals, lower case words are non-terminals.
6247 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6248 bars '|' denote choices. Most grammar productions are implemented in
6249 functions called 'intel_<production>'.
6251 Initial production is 'expr'.
6257 binOp & | AND | \| | OR | ^ | XOR
6259 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6261 constant digits [[ radixOverride ]]
6263 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6301 => expr expr cmpOp e04
6304 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6305 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6307 hexdigit a | b | c | d | e | f
6308 | A | B | C | D | E | F
6314 mulOp * | / | % | MOD | << | SHL | >> | SHR
6318 register specialRegister
6322 segmentRegister CS | DS | ES | FS | GS | SS
6324 specialRegister CR0 | CR2 | CR3 | CR4
6325 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6326 | TR3 | TR4 | TR5 | TR6 | TR7
6328 We simplify the grammar in obvious places (e.g., register parsing is
6329 done by calling parse_register) and eliminate immediate left recursion
6330 to implement a recursive-descent parser.
6334 expr' cmpOp e04 expr'
6385 /* Parsing structure for the intel syntax parser. Used to implement the
6386 semantic actions for the operand grammar. */
6387 struct intel_parser_s
6389 char *op_string; /* The string being parsed. */
6390 int got_a_float; /* Whether the operand is a float. */
6391 int op_modifier; /* Operand modifier. */
6392 int is_mem; /* 1 if operand is memory reference. */
6393 int in_offset; /* >=1 if parsing operand of offset. */
6394 int in_bracket; /* >=1 if parsing operand in brackets. */
6395 const reg_entry *reg; /* Last register reference found. */
6396 char *disp; /* Displacement string being built. */
6397 char *next_operand; /* Resume point when splitting operands. */
6400 static struct intel_parser_s intel_parser;
6402 /* Token structure for parsing intel syntax. */
6405 int code; /* Token code. */
6406 const reg_entry *reg; /* Register entry for register tokens. */
6407 char *str; /* String representation. */
6410 static struct intel_token cur_token, prev_token;
6412 /* Token codes for the intel parser. Since T_SHORT is already used
6413 by COFF, undefine it first to prevent a warning. */
6432 /* Prototypes for intel parser functions. */
6433 static int intel_match_token PARAMS ((int code));
6434 static void intel_get_token PARAMS ((void));
6435 static void intel_putback_token PARAMS ((void));
6436 static int intel_expr PARAMS ((void));
6437 static int intel_e04 PARAMS ((void));
6438 static int intel_e05 PARAMS ((void));
6439 static int intel_e06 PARAMS ((void));
6440 static int intel_e09 PARAMS ((void));
6441 static int intel_bracket_expr PARAMS ((void));
6442 static int intel_e10 PARAMS ((void));
6443 static int intel_e11 PARAMS ((void));
6446 i386_intel_operand (operand_string, got_a_float)
6447 char *operand_string;
6453 p = intel_parser.op_string = xstrdup (operand_string);
6454 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6458 /* Initialize token holders. */
6459 cur_token.code = prev_token.code = T_NIL;
6460 cur_token.reg = prev_token.reg = NULL;
6461 cur_token.str = prev_token.str = NULL;
6463 /* Initialize parser structure. */
6464 intel_parser.got_a_float = got_a_float;
6465 intel_parser.op_modifier = 0;
6466 intel_parser.is_mem = 0;
6467 intel_parser.in_offset = 0;
6468 intel_parser.in_bracket = 0;
6469 intel_parser.reg = NULL;
6470 intel_parser.disp[0] = '\0';
6471 intel_parser.next_operand = NULL;
6473 /* Read the first token and start the parser. */
6475 ret = intel_expr ();
6480 if (cur_token.code != T_NIL)
6482 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6483 current_templates->start->name, cur_token.str);
6486 /* If we found a memory reference, hand it over to i386_displacement
6487 to fill in the rest of the operand fields. */
6488 else if (intel_parser.is_mem)
6490 if ((i.mem_operands == 1
6491 && (current_templates->start->opcode_modifier & IsString) == 0)
6492 || i.mem_operands == 2)
6494 as_bad (_("too many memory references for '%s'"),
6495 current_templates->start->name);
6500 char *s = intel_parser.disp;
6503 if (!quiet_warnings && intel_parser.is_mem < 0)
6504 /* See the comments in intel_bracket_expr. */
6505 as_warn (_("Treating `%s' as memory reference"), operand_string);
6507 /* Add the displacement expression. */
6509 ret = i386_displacement (s, s + strlen (s));
6512 /* Swap base and index in 16-bit memory operands like
6513 [si+bx]. Since i386_index_check is also used in AT&T
6514 mode we have to do that here. */
6517 && (i.base_reg->reg_type & Reg16)
6518 && (i.index_reg->reg_type & Reg16)
6519 && i.base_reg->reg_num >= 6
6520 && i.index_reg->reg_num < 6)
6522 const reg_entry *base = i.index_reg;
6524 i.index_reg = i.base_reg;
6527 ret = i386_index_check (operand_string);
6532 /* Constant and OFFSET expressions are handled by i386_immediate. */
6533 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6534 || intel_parser.reg == NULL)
6535 ret = i386_immediate (intel_parser.disp);
6537 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6539 if (!ret || !intel_parser.next_operand)
6541 intel_parser.op_string = intel_parser.next_operand;
6542 this_operand = i.operands++;
6546 free (intel_parser.disp);
6551 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6555 expr' cmpOp e04 expr'
6560 /* XXX Implement the comparison operators. */
6561 return intel_e04 ();
6578 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6579 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6581 if (cur_token.code == '+')
6583 else if (cur_token.code == '-')
6584 nregs = NUM_ADDRESS_REGS;
6588 strcat (intel_parser.disp, cur_token.str);
6589 intel_match_token (cur_token.code);
6600 int nregs = ~NUM_ADDRESS_REGS;
6607 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6611 str[0] = cur_token.code;
6613 strcat (intel_parser.disp, str);
6618 intel_match_token (cur_token.code);
6623 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6624 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6635 int nregs = ~NUM_ADDRESS_REGS;
6642 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6646 str[0] = cur_token.code;
6648 strcat (intel_parser.disp, str);
6650 else if (cur_token.code == T_SHL)
6651 strcat (intel_parser.disp, "<<");
6652 else if (cur_token.code == T_SHR)
6653 strcat (intel_parser.disp, ">>");
6657 intel_match_token (cur_token.code);
6662 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6663 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6681 int nregs = ~NUM_ADDRESS_REGS;
6686 /* Don't consume constants here. */
6687 if (cur_token.code == '+' || cur_token.code == '-')
6689 /* Need to look one token ahead - if the next token
6690 is a constant, the current token is its sign. */
6693 intel_match_token (cur_token.code);
6694 next_code = cur_token.code;
6695 intel_putback_token ();
6696 if (next_code == T_CONST)
6700 /* e09 OFFSET e09 */
6701 if (cur_token.code == T_OFFSET)
6704 ++intel_parser.in_offset;
6708 else if (cur_token.code == T_SHORT)
6709 intel_parser.op_modifier |= 1 << T_SHORT;
6712 else if (cur_token.code == '+')
6713 strcat (intel_parser.disp, "+");
6718 else if (cur_token.code == '-' || cur_token.code == '~')
6724 str[0] = cur_token.code;
6726 strcat (intel_parser.disp, str);
6733 intel_match_token (cur_token.code);
6741 /* e09' PTR e10 e09' */
6742 if (cur_token.code == T_PTR)
6746 if (prev_token.code == T_BYTE)
6747 suffix = BYTE_MNEM_SUFFIX;
6749 else if (prev_token.code == T_WORD)
6751 if (current_templates->start->name[0] == 'l'
6752 && current_templates->start->name[2] == 's'
6753 && current_templates->start->name[3] == 0)
6754 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6755 else if (intel_parser.got_a_float == 2) /* "fi..." */
6756 suffix = SHORT_MNEM_SUFFIX;
6758 suffix = WORD_MNEM_SUFFIX;
6761 else if (prev_token.code == T_DWORD)
6763 if (current_templates->start->name[0] == 'l'
6764 && current_templates->start->name[2] == 's'
6765 && current_templates->start->name[3] == 0)
6766 suffix = WORD_MNEM_SUFFIX;
6767 else if (flag_code == CODE_16BIT
6768 && (current_templates->start->opcode_modifier
6769 & (Jump | JumpDword)))
6770 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6771 else if (intel_parser.got_a_float == 1) /* "f..." */
6772 suffix = SHORT_MNEM_SUFFIX;
6774 suffix = LONG_MNEM_SUFFIX;
6777 else if (prev_token.code == T_FWORD)
6779 if (current_templates->start->name[0] == 'l'
6780 && current_templates->start->name[2] == 's'
6781 && current_templates->start->name[3] == 0)
6782 suffix = LONG_MNEM_SUFFIX;
6783 else if (!intel_parser.got_a_float)
6785 if (flag_code == CODE_16BIT)
6786 add_prefix (DATA_PREFIX_OPCODE);
6787 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6790 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6793 else if (prev_token.code == T_QWORD)
6795 if (intel_parser.got_a_float == 1) /* "f..." */
6796 suffix = LONG_MNEM_SUFFIX;
6798 suffix = QWORD_MNEM_SUFFIX;
6801 else if (prev_token.code == T_TBYTE)
6803 if (intel_parser.got_a_float == 1)
6804 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6806 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6809 else if (prev_token.code == T_XMMWORD)
6811 /* XXX ignored for now, but accepted since gcc uses it */
6817 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6821 /* Operands for jump/call using 'ptr' notation denote absolute
6823 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6824 i.types[this_operand] |= JumpAbsolute;
6826 if (current_templates->start->base_opcode == 0x8d /* lea */)
6830 else if (i.suffix != suffix)
6832 as_bad (_("Conflicting operand modifiers"));
6838 /* e09' : e10 e09' */
6839 else if (cur_token.code == ':')
6841 if (prev_token.code != T_REG)
6843 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6844 segment/group identifier (which we don't have), using comma
6845 as the operand separator there is even less consistent, since
6846 there all branches only have a single operand. */
6847 if (this_operand != 0
6848 || intel_parser.in_offset
6849 || intel_parser.in_bracket
6850 || (!(current_templates->start->opcode_modifier
6851 & (Jump|JumpDword|JumpInterSegment))
6852 && !(current_templates->start->operand_types[0]
6854 return intel_match_token (T_NIL);
6855 /* Remember the start of the 2nd operand and terminate 1st
6857 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6858 another expression), but it gets at least the simplest case
6859 (a plain number or symbol on the left side) right. */
6860 intel_parser.next_operand = intel_parser.op_string;
6861 *--intel_parser.op_string = '\0';
6862 return intel_match_token (':');
6870 intel_match_token (cur_token.code);
6876 --intel_parser.in_offset;
6879 if (NUM_ADDRESS_REGS > nregs)
6881 as_bad (_("Invalid operand to `OFFSET'"));
6884 intel_parser.op_modifier |= 1 << T_OFFSET;
6887 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6888 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6893 intel_bracket_expr ()
6895 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6896 const char *start = intel_parser.op_string;
6899 if (i.op[this_operand].regs)
6900 return intel_match_token (T_NIL);
6902 intel_match_token ('[');
6904 /* Mark as a memory operand only if it's not already known to be an
6905 offset expression. If it's an offset expression, we need to keep
6907 if (!intel_parser.in_offset)
6909 ++intel_parser.in_bracket;
6911 /* Operands for jump/call inside brackets denote absolute addresses. */
6912 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6913 i.types[this_operand] |= JumpAbsolute;
6915 /* Unfortunately gas always diverged from MASM in a respect that can't
6916 be easily fixed without risking to break code sequences likely to be
6917 encountered (the testsuite even check for this): MASM doesn't consider
6918 an expression inside brackets unconditionally as a memory reference.
6919 When that is e.g. a constant, an offset expression, or the sum of the
6920 two, this is still taken as a constant load. gas, however, always
6921 treated these as memory references. As a compromise, we'll try to make
6922 offset expressions inside brackets work the MASM way (since that's
6923 less likely to be found in real world code), but make constants alone
6924 continue to work the traditional gas way. In either case, issue a
6926 intel_parser.op_modifier &= ~was_offset;
6929 strcat (intel_parser.disp, "[");
6931 /* Add a '+' to the displacement string if necessary. */
6932 if (*intel_parser.disp != '\0'
6933 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6934 strcat (intel_parser.disp, "+");
6937 && (len = intel_parser.op_string - start - 1,
6938 intel_match_token (']')))
6940 /* Preserve brackets when the operand is an offset expression. */
6941 if (intel_parser.in_offset)
6942 strcat (intel_parser.disp, "]");
6945 --intel_parser.in_bracket;
6946 if (i.base_reg || i.index_reg)
6947 intel_parser.is_mem = 1;
6948 if (!intel_parser.is_mem)
6950 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6951 /* Defer the warning until all of the operand was parsed. */
6952 intel_parser.is_mem = -1;
6953 else if (!quiet_warnings)
6954 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6957 intel_parser.op_modifier |= was_offset;
6974 while (cur_token.code == '[')
6976 if (!intel_bracket_expr ())
7001 switch (cur_token.code)
7005 intel_match_token ('(');
7006 strcat (intel_parser.disp, "(");
7008 if (intel_expr () && intel_match_token (')'))
7010 strcat (intel_parser.disp, ")");
7017 return intel_bracket_expr ();
7022 strcat (intel_parser.disp, cur_token.str);
7023 intel_match_token (cur_token.code);
7025 /* Mark as a memory operand only if it's not already known to be an
7026 offset expression. */
7027 if (!intel_parser.in_offset)
7028 intel_parser.is_mem = 1;
7035 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7037 intel_match_token (T_REG);
7039 /* Check for segment change. */
7040 if (cur_token.code == ':')
7042 if (!(reg->reg_type & (SReg2 | SReg3)))
7044 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7047 else if (i.seg[i.mem_operands])
7048 as_warn (_("Extra segment override ignored"));
7051 if (!intel_parser.in_offset)
7052 intel_parser.is_mem = 1;
7053 switch (reg->reg_num)
7056 i.seg[i.mem_operands] = &es;
7059 i.seg[i.mem_operands] = &cs;
7062 i.seg[i.mem_operands] = &ss;
7065 i.seg[i.mem_operands] = &ds;
7068 i.seg[i.mem_operands] = &fs;
7071 i.seg[i.mem_operands] = &gs;
7077 /* Not a segment register. Check for register scaling. */
7078 else if (cur_token.code == '*')
7080 if (!intel_parser.in_bracket)
7082 as_bad (_("Register scaling only allowed in memory operands"));
7086 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7087 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7088 else if (i.index_reg)
7089 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7091 /* What follows must be a valid scale. */
7092 intel_match_token ('*');
7094 i.types[this_operand] |= BaseIndex;
7096 /* Set the scale after setting the register (otherwise,
7097 i386_scale will complain) */
7098 if (cur_token.code == '+' || cur_token.code == '-')
7100 char *str, sign = cur_token.code;
7101 intel_match_token (cur_token.code);
7102 if (cur_token.code != T_CONST)
7104 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7108 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7109 strcpy (str + 1, cur_token.str);
7111 if (!i386_scale (str))
7115 else if (!i386_scale (cur_token.str))
7117 intel_match_token (cur_token.code);
7120 /* No scaling. If this is a memory operand, the register is either a
7121 base register (first occurrence) or an index register (second
7123 else if (intel_parser.in_bracket)
7128 else if (!i.index_reg)
7132 as_bad (_("Too many register references in memory operand"));
7136 i.types[this_operand] |= BaseIndex;
7139 /* It's neither base nor index. */
7140 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7142 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7143 i.op[this_operand].regs = reg;
7148 as_bad (_("Invalid use of register"));
7152 /* Since registers are not part of the displacement string (except
7153 when we're parsing offset operands), we may need to remove any
7154 preceding '+' from the displacement string. */
7155 if (*intel_parser.disp != '\0'
7156 && !intel_parser.in_offset)
7158 char *s = intel_parser.disp;
7159 s += strlen (s) - 1;
7182 intel_match_token (cur_token.code);
7184 if (cur_token.code == T_PTR)
7187 /* It must have been an identifier. */
7188 intel_putback_token ();
7189 cur_token.code = T_ID;
7195 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7199 /* The identifier represents a memory reference only if it's not
7200 preceded by an offset modifier and if it's not an equate. */
7201 symbolP = symbol_find(cur_token.str);
7202 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7203 intel_parser.is_mem = 1;
7211 char *save_str, sign = 0;
7213 /* Allow constants that start with `+' or `-'. */
7214 if (cur_token.code == '-' || cur_token.code == '+')
7216 sign = cur_token.code;
7217 intel_match_token (cur_token.code);
7218 if (cur_token.code != T_CONST)
7220 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7226 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7227 strcpy (save_str + !!sign, cur_token.str);
7231 /* Get the next token to check for register scaling. */
7232 intel_match_token (cur_token.code);
7234 /* Check if this constant is a scaling factor for an index register. */
7235 if (cur_token.code == '*')
7237 if (intel_match_token ('*') && cur_token.code == T_REG)
7239 const reg_entry *reg = cur_token.reg;
7241 if (!intel_parser.in_bracket)
7243 as_bad (_("Register scaling only allowed in memory operands"));
7247 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7248 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7249 else if (i.index_reg)
7250 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7252 /* The constant is followed by `* reg', so it must be
7255 i.types[this_operand] |= BaseIndex;
7257 /* Set the scale after setting the register (otherwise,
7258 i386_scale will complain) */
7259 if (!i386_scale (save_str))
7261 intel_match_token (T_REG);
7263 /* Since registers are not part of the displacement
7264 string, we may need to remove any preceding '+' from
7265 the displacement string. */
7266 if (*intel_parser.disp != '\0')
7268 char *s = intel_parser.disp;
7269 s += strlen (s) - 1;
7279 /* The constant was not used for register scaling. Since we have
7280 already consumed the token following `*' we now need to put it
7281 back in the stream. */
7282 intel_putback_token ();
7285 /* Add the constant to the displacement string. */
7286 strcat (intel_parser.disp, save_str);
7293 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7297 /* Match the given token against cur_token. If they match, read the next
7298 token from the operand string. */
7300 intel_match_token (code)
7303 if (cur_token.code == code)
7310 as_bad (_("Unexpected token `%s'"), cur_token.str);
7315 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7320 const reg_entry *reg;
7321 struct intel_token new_token;
7323 new_token.code = T_NIL;
7324 new_token.reg = NULL;
7325 new_token.str = NULL;
7327 /* Free the memory allocated to the previous token and move
7328 cur_token to prev_token. */
7330 free (prev_token.str);
7332 prev_token = cur_token;
7334 /* Skip whitespace. */
7335 while (is_space_char (*intel_parser.op_string))
7336 intel_parser.op_string++;
7338 /* Return an empty token if we find nothing else on the line. */
7339 if (*intel_parser.op_string == '\0')
7341 cur_token = new_token;
7345 /* The new token cannot be larger than the remainder of the operand
7347 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7348 new_token.str[0] = '\0';
7350 if (strchr ("0123456789", *intel_parser.op_string))
7352 char *p = new_token.str;
7353 char *q = intel_parser.op_string;
7354 new_token.code = T_CONST;
7356 /* Allow any kind of identifier char to encompass floating point and
7357 hexadecimal numbers. */
7358 while (is_identifier_char (*q))
7362 /* Recognize special symbol names [0-9][bf]. */
7363 if (strlen (intel_parser.op_string) == 2
7364 && (intel_parser.op_string[1] == 'b'
7365 || intel_parser.op_string[1] == 'f'))
7366 new_token.code = T_ID;
7369 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7371 size_t len = end_op - intel_parser.op_string;
7373 new_token.code = T_REG;
7374 new_token.reg = reg;
7376 memcpy (new_token.str, intel_parser.op_string, len);
7377 new_token.str[len] = '\0';
7380 else if (is_identifier_char (*intel_parser.op_string))
7382 char *p = new_token.str;
7383 char *q = intel_parser.op_string;
7385 /* A '.' or '$' followed by an identifier char is an identifier.
7386 Otherwise, it's operator '.' followed by an expression. */
7387 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7389 new_token.code = '.';
7390 new_token.str[0] = '.';
7391 new_token.str[1] = '\0';
7395 while (is_identifier_char (*q) || *q == '@')
7399 if (strcasecmp (new_token.str, "NOT") == 0)
7400 new_token.code = '~';
7402 else if (strcasecmp (new_token.str, "MOD") == 0)
7403 new_token.code = '%';
7405 else if (strcasecmp (new_token.str, "AND") == 0)
7406 new_token.code = '&';
7408 else if (strcasecmp (new_token.str, "OR") == 0)
7409 new_token.code = '|';
7411 else if (strcasecmp (new_token.str, "XOR") == 0)
7412 new_token.code = '^';
7414 else if (strcasecmp (new_token.str, "SHL") == 0)
7415 new_token.code = T_SHL;
7417 else if (strcasecmp (new_token.str, "SHR") == 0)
7418 new_token.code = T_SHR;
7420 else if (strcasecmp (new_token.str, "BYTE") == 0)
7421 new_token.code = T_BYTE;
7423 else if (strcasecmp (new_token.str, "WORD") == 0)
7424 new_token.code = T_WORD;
7426 else if (strcasecmp (new_token.str, "DWORD") == 0)
7427 new_token.code = T_DWORD;
7429 else if (strcasecmp (new_token.str, "FWORD") == 0)
7430 new_token.code = T_FWORD;
7432 else if (strcasecmp (new_token.str, "QWORD") == 0)
7433 new_token.code = T_QWORD;
7435 else if (strcasecmp (new_token.str, "TBYTE") == 0
7436 /* XXX remove (gcc still uses it) */
7437 || strcasecmp (new_token.str, "XWORD") == 0)
7438 new_token.code = T_TBYTE;
7440 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7441 || strcasecmp (new_token.str, "OWORD") == 0)
7442 new_token.code = T_XMMWORD;
7444 else if (strcasecmp (new_token.str, "PTR") == 0)
7445 new_token.code = T_PTR;
7447 else if (strcasecmp (new_token.str, "SHORT") == 0)
7448 new_token.code = T_SHORT;
7450 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7452 new_token.code = T_OFFSET;
7454 /* ??? This is not mentioned in the MASM grammar but gcc
7455 makes use of it with -mintel-syntax. OFFSET may be
7456 followed by FLAT: */
7457 if (strncasecmp (q, " FLAT:", 6) == 0)
7458 strcat (new_token.str, " FLAT:");
7461 /* ??? This is not mentioned in the MASM grammar. */
7462 else if (strcasecmp (new_token.str, "FLAT") == 0)
7464 new_token.code = T_OFFSET;
7466 strcat (new_token.str, ":");
7468 as_bad (_("`:' expected"));
7472 new_token.code = T_ID;
7476 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7478 new_token.code = *intel_parser.op_string;
7479 new_token.str[0] = *intel_parser.op_string;
7480 new_token.str[1] = '\0';
7483 else if (strchr ("<>", *intel_parser.op_string)
7484 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7486 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7487 new_token.str[0] = *intel_parser.op_string;
7488 new_token.str[1] = *intel_parser.op_string;
7489 new_token.str[2] = '\0';
7493 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7495 intel_parser.op_string += strlen (new_token.str);
7496 cur_token = new_token;
7499 /* Put cur_token back into the token stream and make cur_token point to
7502 intel_putback_token ()
7504 if (cur_token.code != T_NIL)
7506 intel_parser.op_string -= strlen (cur_token.str);
7507 free (cur_token.str);
7509 cur_token = prev_token;
7511 /* Forget prev_token. */
7512 prev_token.code = T_NIL;
7513 prev_token.reg = NULL;
7514 prev_token.str = NULL;
7518 tc_x86_regname_to_dw2regnum (char *regname)
7520 unsigned int regnum;
7521 unsigned int regnames_count;
7522 static const char *const regnames_32[] =
7524 "eax", "ecx", "edx", "ebx",
7525 "esp", "ebp", "esi", "edi",
7526 "eip", "eflags", NULL,
7527 "st0", "st1", "st2", "st3",
7528 "st4", "st5", "st6", "st7",
7530 "xmm0", "xmm1", "xmm2", "xmm3",
7531 "xmm4", "xmm5", "xmm6", "xmm7",
7532 "mm0", "mm1", "mm2", "mm3",
7533 "mm4", "mm5", "mm6", "mm7",
7534 "fcw", "fsw", "mxcsr",
7535 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7538 static const char *const regnames_64[] =
7540 "rax", "rdx", "rcx", "rbx",
7541 "rsi", "rdi", "rbp", "rsp",
7542 "r8", "r9", "r10", "r11",
7543 "r12", "r13", "r14", "r15",
7545 "xmm0", "xmm1", "xmm2", "xmm3",
7546 "xmm4", "xmm5", "xmm6", "xmm7",
7547 "xmm8", "xmm9", "xmm10", "xmm11",
7548 "xmm12", "xmm13", "xmm14", "xmm15",
7549 "st0", "st1", "st2", "st3",
7550 "st4", "st5", "st6", "st7",
7551 "mm0", "mm1", "mm2", "mm3",
7552 "mm4", "mm5", "mm6", "mm7",
7554 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7555 "fs.base", "gs.base", NULL, NULL,
7557 "mxcsr", "fcw", "fsw"
7559 const char *const *regnames;
7561 if (flag_code == CODE_64BIT)
7563 regnames = regnames_64;
7564 regnames_count = ARRAY_SIZE (regnames_64);
7568 regnames = regnames_32;
7569 regnames_count = ARRAY_SIZE (regnames_32);
7572 for (regnum = 0; regnum < regnames_count; regnum++)
7573 if (regnames[regnum] != NULL
7574 && strcmp (regname, regnames[regnum]) == 0)
7581 tc_x86_frame_initial_instructions (void)
7583 static unsigned int sp_regno;
7586 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7589 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7590 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7594 i386_elf_section_type (const char *str, size_t len)
7596 if (flag_code == CODE_64BIT
7597 && len == sizeof ("unwind") - 1
7598 && strncmp (str, "unwind", 6) == 0)
7599 return SHT_X86_64_UNWIND;
7606 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7610 expr.X_op = O_secrel;
7611 expr.X_add_symbol = symbol;
7612 expr.X_add_number = 0;
7613 emit_expr (&expr, size);
7617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7618 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7621 x86_64_section_letter (int letter, char **ptr_msg)
7623 if (flag_code == CODE_64BIT)
7626 return SHF_X86_64_LARGE;
7628 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7631 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7636 x86_64_section_word (char *str, size_t len)
7638 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7639 return SHF_X86_64_LARGE;
7645 handle_large_common (int small ATTRIBUTE_UNUSED)
7647 if (flag_code != CODE_64BIT)
7649 s_comm_internal (0, elf_common_parse);
7650 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7654 static segT lbss_section;
7655 asection *saved_com_section_ptr = elf_com_section_ptr;
7656 asection *saved_bss_section = bss_section;
7658 if (lbss_section == NULL)
7660 flagword applicable;
7662 subsegT subseg = now_subseg;
7664 /* The .lbss section is for local .largecomm symbols. */
7665 lbss_section = subseg_new (".lbss", 0);
7666 applicable = bfd_applicable_section_flags (stdoutput);
7667 bfd_set_section_flags (stdoutput, lbss_section,
7668 applicable & SEC_ALLOC);
7669 seg_info (lbss_section)->bss = 1;
7671 subseg_set (seg, subseg);
7674 elf_com_section_ptr = &_bfd_elf_large_com_section;
7675 bss_section = lbss_section;
7677 s_comm_internal (0, elf_common_parse);
7679 elf_com_section_ptr = saved_com_section_ptr;
7680 bss_section = saved_bss_section;
7683 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */