1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
849 CPU_BTVER1_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
851 CPU_BTVER2_FLAGS, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
869 CPU_SSSE3_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_1_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
881 CPU_AVX512F_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
883 CPU_AVX512CD_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
885 CPU_AVX512ER_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
887 CPU_AVX512PF_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
889 CPU_AVX512DQ_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
891 CPU_AVX512BW_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
893 CPU_AVX512VL_FLAGS, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
897 CPU_VMFUNC_FLAGS, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
901 CPU_XSAVE_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEOPT_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEC_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
907 CPU_XSAVES_FLAGS, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
915 CPU_FSGSBASE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
917 CPU_RDRND_FLAGS, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
931 CPU_MOVBE_FLAGS, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
937 CPU_LZCNT_FLAGS, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
943 CPU_INVPCID_FLAGS, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
945 CPU_CLFLUSH_FLAGS, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
949 CPU_SYSCALL_FLAGS, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
951 CPU_RDTSCP_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
953 CPU_3DNOW_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
955 CPU_3DNOWA_FLAGS, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
957 CPU_PADLOCK_FLAGS, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
963 CPU_SSE4A_FLAGS, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
973 CPU_RDSEED_FLAGS, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
975 CPU_PRFCHW_FLAGS, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
983 CPU_CLFLUSHOPT_FLAGS, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
985 CPU_PREFETCHWT1_FLAGS, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
991 CPU_AVX512IFMA_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
993 CPU_AVX512VBMI_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1007 CPU_CLZERO_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1009 CPU_MWAITX_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1011 CPU_OSPKE_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1013 CPU_RDPID_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
1040 static const noarch_entry cpu_noarch[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1089 && *input_line_pointer == ',')
1091 align = parse_align (needs_align - 1);
1093 if (align == (addressT) -1)
1108 bss_alloc (symbolP, size, align);
1113 pe_lcomm (int needs_align)
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1119 const pseudo_typeS md_pseudo_table[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1124 {"align", s_align_ptwo, 0},
1126 {"arch", set_cpu_arch, 0},
1130 {"lcomm", pe_lcomm, 1},
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1136 {"slong", signed_cons, 4},
1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
1143 {"code64", set_code_flag, CODE_64BIT},
1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
1156 {"file", dwarf2_directive_file, 0},
1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1161 {"secrel32", pe_directive_secrel, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control *op_hash;
1172 /* Hash table for register lookup. */
1173 static struct hash_control *reg_hash;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1[] =
1180 static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt[] = {
1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt[] = {
1206 f32_1, f32_2, f16_3, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1238 alt_9, alt_10, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
1261 last = count % max_single_nop_size;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1269 nops = patt[last - 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1280 memcpy (where + offset, nops, last);
1285 fits_in_imm7 (offsetT num)
1287 return (num & 0x7f) == num;
1291 fits_in_imm31 (offsetT num)
1293 return (num & 0x7fffffff) == num;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1302 const unsigned char *const *patt = NULL;
1303 int max_single_nop_size;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
1307 switch (fragP->fr_type)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code == CODE_16BIT)
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
1354 case PROCESSOR_CORE:
1355 case PROCESSOR_CORE2:
1356 case PROCESSOR_COREI7:
1357 case PROCESSOR_L1OM:
1358 case PROCESSOR_K1OM:
1359 case PROCESSOR_GENERIC64:
1361 case PROCESSOR_ATHLON:
1363 case PROCESSOR_AMDFAM10:
1365 case PROCESSOR_ZNVER:
1369 case PROCESSOR_I386:
1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
1372 case PROCESSOR_PENTIUMPRO:
1373 case PROCESSOR_IAMCU:
1374 case PROCESSOR_GENERIC32:
1381 switch (fragP->tc_frag_data.tune)
1383 case PROCESSOR_UNKNOWN:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386:
1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
1392 case PROCESSOR_IAMCU:
1394 case PROCESSOR_ATHLON:
1396 case PROCESSOR_AMDFAM10:
1398 case PROCESSOR_ZNVER:
1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
1412 case PROCESSOR_CORE2:
1413 case PROCESSOR_COREI7:
1414 case PROCESSOR_L1OM:
1415 case PROCESSOR_K1OM:
1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1421 case PROCESSOR_GENERIC64:
1427 if (patt == f32_patt)
1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1442 limit = max_single_nop_size;
1444 if (fragP->fr_type == rs_fill_nop)
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1457 fragP->fr_var = count;
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1465 /* Use "jmp disp8" if possible. */
1467 where[0] = jump_disp8[0];
1473 unsigned int size_of_jump;
1475 if (flag_code == CODE_16BIT)
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1483 where[0] = jump32_disp32[0];
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
1505 operand_type_all_zero (const union i386_operand_type *x)
1507 switch (ARRAY_SIZE(x->array))
1518 return !x->array[0];
1525 operand_type_set (union i386_operand_type *x, unsigned int v)
1527 switch (ARRAY_SIZE(x->array))
1545 operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
1548 switch (ARRAY_SIZE(x->array))
1551 if (x->array[2] != y->array[2])
1555 if (x->array[1] != y->array[1])
1559 return x->array[0] == y->array[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags *x)
1569 switch (ARRAY_SIZE(x->array))
1584 return !x->array[0];
1591 cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1594 switch (ARRAY_SIZE(x->array))
1597 if (x->array[3] != y->array[3])
1601 if (x->array[2] != y->array[2])
1605 if (x->array[1] != y->array[1])
1609 return x->array[0] == y->array[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f)
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1626 switch (ARRAY_SIZE (x.array))
1629 x.array [3] &= y.array [3];
1632 x.array [2] &= y.array [2];
1635 x.array [1] &= y.array [1];
1638 x.array [0] &= y.array [0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1649 switch (ARRAY_SIZE (x.array))
1652 x.array [3] |= y.array [3];
1655 x.array [2] |= y.array [2];
1658 x.array [1] |= y.array [1];
1661 x.array [0] |= y.array [0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1672 switch (ARRAY_SIZE (x.array))
1675 x.array [3] &= ~y.array [3];
1678 x.array [2] &= ~y.array [2];
1681 x.array [1] &= ~y.array [1];
1684 x.array [0] &= ~y.array [0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template *t)
1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1709 if (cpu_flags_all_zero (&x))
1711 /* This instruction is available on all archs. */
1712 match |= CPU_FLAGS_ARCH_MATCH;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu = cpu_arch_flags;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1722 x.bitfield.cpuavx512vl = 0;
1724 cpu = cpu_flags_and (x, cpu);
1725 if (!cpu_flags_all_zero (&cpu))
1727 if (x.bitfield.cpuavx)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1737 else if (x.bitfield.cpuavx512f)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1747 match |= CPU_FLAGS_ARCH_MATCH;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x, i386_operand_type y)
1756 switch (ARRAY_SIZE (x.array))
1759 x.array [2] &= y.array [2];
1762 x.array [1] &= y.array [1];
1765 x.array [0] &= y.array [0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1776 switch (ARRAY_SIZE (x.array))
1779 x.array [2] &= ~y.array [2];
1782 x.array [1] &= ~y.array [1];
1785 x.array [0] &= ~y.array [0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x, i386_operand_type y)
1796 switch (ARRAY_SIZE (x.array))
1799 x.array [2] |= y.array [2];
1802 x.array [1] |= y.array [1];
1805 x.array [0] |= y.array [0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x, i386_operand_type y)
1816 switch (ARRAY_SIZE (x.array))
1819 x.array [2] ^= y.array [2];
1822 x.array [1] ^= y.array [1];
1825 x.array [0] ^= y.array [0];
1833 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1835 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
1841 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1842 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1843 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1852 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1863 operand_type_check (i386_operand_type t, enum operand_type c)
1868 return t.bitfield.reg;
1871 return (t.bitfield.imm8
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1901 between operand GIVEN and opeand WANTED for instruction template T. */
1904 match_operand_size (const insn_template *t, unsigned int wanted,
1907 return !((i.types[given].bitfield.byte
1908 && !t->operand_types[wanted].bitfield.byte)
1909 || (i.types[given].bitfield.word
1910 && !t->operand_types[wanted].bitfield.word)
1911 || (i.types[given].bitfield.dword
1912 && !t->operand_types[wanted].bitfield.dword)
1913 || (i.types[given].bitfield.qword
1914 && !t->operand_types[wanted].bitfield.qword)
1915 || (i.types[given].bitfield.tbyte
1916 && !t->operand_types[wanted].bitfield.tbyte));
1919 /* Return 1 if there is no conflict in SIMD register between operand
1920 GIVEN and opeand WANTED for instruction template T. */
1923 match_simd_size (const insn_template *t, unsigned int wanted,
1926 return !((i.types[given].bitfield.xmmword
1927 && !t->operand_types[wanted].bitfield.xmmword)
1928 || (i.types[given].bitfield.ymmword
1929 && !t->operand_types[wanted].bitfield.ymmword)
1930 || (i.types[given].bitfield.zmmword
1931 && !t->operand_types[wanted].bitfield.zmmword));
1934 /* Return 1 if there is no conflict in any size between operand GIVEN
1935 and opeand WANTED for instruction template T. */
1938 match_mem_size (const insn_template *t, unsigned int wanted,
1941 return (match_operand_size (t, wanted, given)
1942 && !((i.types[given].bitfield.unspecified
1944 && !t->operand_types[wanted].bitfield.unspecified)
1945 || (i.types[given].bitfield.fword
1946 && !t->operand_types[wanted].bitfield.fword)
1947 /* For scalar opcode templates to allow register and memory
1948 operands at the same time, some special casing is needed
1949 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1950 down-conversion vpmov*. */
1951 || ((t->operand_types[wanted].bitfield.regsimd
1952 && !t->opcode_modifier.broadcast
1953 && (t->operand_types[wanted].bitfield.byte
1954 || t->operand_types[wanted].bitfield.word
1955 || t->operand_types[wanted].bitfield.dword
1956 || t->operand_types[wanted].bitfield.qword))
1957 ? (i.types[given].bitfield.xmmword
1958 || i.types[given].bitfield.ymmword
1959 || i.types[given].bitfield.zmmword)
1960 : !match_simd_size(t, wanted, given))));
1963 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1964 operands for instruction template T, and it has MATCH_REVERSE set if there
1965 is no size conflict on any operands for the template with operands reversed
1966 (and the template allows for reversing in the first place). */
1968 #define MATCH_STRAIGHT 1
1969 #define MATCH_REVERSE 2
1971 static INLINE unsigned int
1972 operand_size_match (const insn_template *t)
1974 unsigned int j, match = MATCH_STRAIGHT;
1976 /* Don't check jump instructions. */
1977 if (t->opcode_modifier.jump
1978 || t->opcode_modifier.jumpbyte
1979 || t->opcode_modifier.jumpdword
1980 || t->opcode_modifier.jumpintersegment)
1983 /* Check memory and accumulator operand size. */
1984 for (j = 0; j < i.operands; j++)
1986 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1987 && t->operand_types[j].bitfield.anysize)
1990 if (t->operand_types[j].bitfield.reg
1991 && !match_operand_size (t, j, j))
1997 if (t->operand_types[j].bitfield.regsimd
1998 && !match_simd_size (t, j, j))
2004 if (t->operand_types[j].bitfield.acc
2005 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2011 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2018 if (!t->opcode_modifier.d)
2022 i.error = operand_size_mismatch;
2026 /* Check reverse. */
2027 gas_assert (i.operands == 2);
2029 for (j = 0; j < 2; j++)
2031 if ((t->operand_types[j].bitfield.reg
2032 || t->operand_types[j].bitfield.acc)
2033 && !match_operand_size (t, j, !j))
2036 if (i.types[!j].bitfield.mem
2037 && !match_mem_size (t, j, !j))
2041 return match | MATCH_REVERSE;
2045 operand_type_match (i386_operand_type overlap,
2046 i386_operand_type given)
2048 i386_operand_type temp = overlap;
2050 temp.bitfield.jumpabsolute = 0;
2051 temp.bitfield.unspecified = 0;
2052 temp.bitfield.byte = 0;
2053 temp.bitfield.word = 0;
2054 temp.bitfield.dword = 0;
2055 temp.bitfield.fword = 0;
2056 temp.bitfield.qword = 0;
2057 temp.bitfield.tbyte = 0;
2058 temp.bitfield.xmmword = 0;
2059 temp.bitfield.ymmword = 0;
2060 temp.bitfield.zmmword = 0;
2061 if (operand_type_all_zero (&temp))
2064 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2065 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2069 i.error = operand_type_mismatch;
2073 /* If given types g0 and g1 are registers they must be of the same type
2074 unless the expected operand type register overlap is null.
2075 Memory operand size of certain SIMD instructions is also being checked
2079 operand_type_register_match (i386_operand_type g0,
2080 i386_operand_type t0,
2081 i386_operand_type g1,
2082 i386_operand_type t1)
2084 if (!g0.bitfield.reg
2085 && !g0.bitfield.regsimd
2086 && (!operand_type_check (g0, anymem)
2087 || g0.bitfield.unspecified
2088 || !t0.bitfield.regsimd))
2091 if (!g1.bitfield.reg
2092 && !g1.bitfield.regsimd
2093 && (!operand_type_check (g1, anymem)
2094 || g1.bitfield.unspecified
2095 || !t1.bitfield.regsimd))
2098 if (g0.bitfield.byte == g1.bitfield.byte
2099 && g0.bitfield.word == g1.bitfield.word
2100 && g0.bitfield.dword == g1.bitfield.dword
2101 && g0.bitfield.qword == g1.bitfield.qword
2102 && g0.bitfield.xmmword == g1.bitfield.xmmword
2103 && g0.bitfield.ymmword == g1.bitfield.ymmword
2104 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2107 if (!(t0.bitfield.byte & t1.bitfield.byte)
2108 && !(t0.bitfield.word & t1.bitfield.word)
2109 && !(t0.bitfield.dword & t1.bitfield.dword)
2110 && !(t0.bitfield.qword & t1.bitfield.qword)
2111 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2112 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2113 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2116 i.error = register_type_mismatch;
2121 static INLINE unsigned int
2122 register_number (const reg_entry *r)
2124 unsigned int nr = r->reg_num;
2126 if (r->reg_flags & RegRex)
2129 if (r->reg_flags & RegVRex)
2135 static INLINE unsigned int
2136 mode_from_disp_size (i386_operand_type t)
2138 if (t.bitfield.disp8)
2140 else if (t.bitfield.disp16
2141 || t.bitfield.disp32
2142 || t.bitfield.disp32s)
2149 fits_in_signed_byte (addressT num)
2151 return num + 0x80 <= 0xff;
2155 fits_in_unsigned_byte (addressT num)
2161 fits_in_unsigned_word (addressT num)
2163 return num <= 0xffff;
2167 fits_in_signed_word (addressT num)
2169 return num + 0x8000 <= 0xffff;
2173 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2178 return num + 0x80000000 <= 0xffffffff;
2180 } /* fits_in_signed_long() */
2183 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2188 return num <= 0xffffffff;
2190 } /* fits_in_unsigned_long() */
2193 fits_in_disp8 (offsetT num)
2195 int shift = i.memshift;
2201 mask = (1 << shift) - 1;
2203 /* Return 0 if NUM isn't properly aligned. */
2207 /* Check if NUM will fit in 8bit after shift. */
2208 return fits_in_signed_byte (num >> shift);
2212 fits_in_imm4 (offsetT num)
2214 return (num & 0xf) == num;
2217 static i386_operand_type
2218 smallest_imm_type (offsetT num)
2220 i386_operand_type t;
2222 operand_type_set (&t, 0);
2223 t.bitfield.imm64 = 1;
2225 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2227 /* This code is disabled on the 486 because all the Imm1 forms
2228 in the opcode table are slower on the i486. They're the
2229 versions with the implicitly specified single-position
2230 displacement, which has another syntax if you really want to
2232 t.bitfield.imm1 = 1;
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2239 else if (fits_in_signed_byte (num))
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm8s = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2247 else if (fits_in_unsigned_byte (num))
2249 t.bitfield.imm8 = 1;
2250 t.bitfield.imm16 = 1;
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2254 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2256 t.bitfield.imm16 = 1;
2257 t.bitfield.imm32 = 1;
2258 t.bitfield.imm32s = 1;
2260 else if (fits_in_signed_long (num))
2262 t.bitfield.imm32 = 1;
2263 t.bitfield.imm32s = 1;
2265 else if (fits_in_unsigned_long (num))
2266 t.bitfield.imm32 = 1;
2272 offset_in_range (offsetT val, int size)
2278 case 1: mask = ((addressT) 1 << 8) - 1; break;
2279 case 2: mask = ((addressT) 1 << 16) - 1; break;
2280 case 4: mask = ((addressT) 2 << 31) - 1; break;
2282 case 8: mask = ((addressT) 2 << 63) - 1; break;
2288 /* If BFD64, sign extend val for 32bit address mode. */
2289 if (flag_code != CODE_64BIT
2290 || i.prefix[ADDR_PREFIX])
2291 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2292 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2295 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2297 char buf1[40], buf2[40];
2299 sprint_value (buf1, val);
2300 sprint_value (buf2, val & mask);
2301 as_warn (_("%s shortened to %s"), buf1, buf2);
2316 a. PREFIX_EXIST if attempting to add a prefix where one from the
2317 same class already exists.
2318 b. PREFIX_LOCK if lock prefix is added.
2319 c. PREFIX_REP if rep/repne prefix is added.
2320 d. PREFIX_DS if ds prefix is added.
2321 e. PREFIX_OTHER if other prefix is added.
2324 static enum PREFIX_GROUP
2325 add_prefix (unsigned int prefix)
2327 enum PREFIX_GROUP ret = PREFIX_OTHER;
2330 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2331 && flag_code == CODE_64BIT)
2333 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2334 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2335 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2336 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2347 case DS_PREFIX_OPCODE:
2350 case CS_PREFIX_OPCODE:
2351 case ES_PREFIX_OPCODE:
2352 case FS_PREFIX_OPCODE:
2353 case GS_PREFIX_OPCODE:
2354 case SS_PREFIX_OPCODE:
2358 case REPNE_PREFIX_OPCODE:
2359 case REPE_PREFIX_OPCODE:
2364 case LOCK_PREFIX_OPCODE:
2373 case ADDR_PREFIX_OPCODE:
2377 case DATA_PREFIX_OPCODE:
2381 if (i.prefix[q] != 0)
2389 i.prefix[q] |= prefix;
2392 as_bad (_("same type of prefix used twice"));
2398 update_code_flag (int value, int check)
2400 PRINTF_LIKE ((*as_error));
2402 flag_code = (enum flag_code) value;
2403 if (flag_code == CODE_64BIT)
2405 cpu_arch_flags.bitfield.cpu64 = 1;
2406 cpu_arch_flags.bitfield.cpuno64 = 0;
2410 cpu_arch_flags.bitfield.cpu64 = 0;
2411 cpu_arch_flags.bitfield.cpuno64 = 1;
2413 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2416 as_error = as_fatal;
2419 (*as_error) (_("64bit mode not supported on `%s'."),
2420 cpu_arch_name ? cpu_arch_name : default_arch);
2422 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2425 as_error = as_fatal;
2428 (*as_error) (_("32bit mode not supported on `%s'."),
2429 cpu_arch_name ? cpu_arch_name : default_arch);
2431 stackop_size = '\0';
2435 set_code_flag (int value)
2437 update_code_flag (value, 0);
2441 set_16bit_gcc_code_flag (int new_code_flag)
2443 flag_code = (enum flag_code) new_code_flag;
2444 if (flag_code != CODE_16BIT)
2446 cpu_arch_flags.bitfield.cpu64 = 0;
2447 cpu_arch_flags.bitfield.cpuno64 = 1;
2448 stackop_size = LONG_MNEM_SUFFIX;
2452 set_intel_syntax (int syntax_flag)
2454 /* Find out if register prefixing is specified. */
2455 int ask_naked_reg = 0;
2458 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2461 int e = get_symbol_name (&string);
2463 if (strcmp (string, "prefix") == 0)
2465 else if (strcmp (string, "noprefix") == 0)
2468 as_bad (_("bad argument to syntax directive."));
2469 (void) restore_line_pointer (e);
2471 demand_empty_rest_of_line ();
2473 intel_syntax = syntax_flag;
2475 if (ask_naked_reg == 0)
2476 allow_naked_reg = (intel_syntax
2477 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2479 allow_naked_reg = (ask_naked_reg < 0);
2481 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2483 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2484 identifier_chars['$'] = intel_syntax ? '$' : 0;
2485 register_prefix = allow_naked_reg ? "" : "%";
2489 set_intel_mnemonic (int mnemonic_flag)
2491 intel_mnemonic = mnemonic_flag;
2495 set_allow_index_reg (int flag)
2497 allow_index_reg = flag;
2501 set_check (int what)
2503 enum check_kind *kind;
2508 kind = &operand_check;
2519 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2522 int e = get_symbol_name (&string);
2524 if (strcmp (string, "none") == 0)
2526 else if (strcmp (string, "warning") == 0)
2527 *kind = check_warning;
2528 else if (strcmp (string, "error") == 0)
2529 *kind = check_error;
2531 as_bad (_("bad argument to %s_check directive."), str);
2532 (void) restore_line_pointer (e);
2535 as_bad (_("missing argument for %s_check directive"), str);
2537 demand_empty_rest_of_line ();
2541 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2542 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2545 static const char *arch;
2547 /* Intel LIOM is only supported on ELF. */
2553 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2554 use default_arch. */
2555 arch = cpu_arch_name;
2557 arch = default_arch;
2560 /* If we are targeting Intel MCU, we must enable it. */
2561 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2562 || new_flag.bitfield.cpuiamcu)
2565 /* If we are targeting Intel L1OM, we must enable it. */
2566 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2567 || new_flag.bitfield.cpul1om)
2570 /* If we are targeting Intel K1OM, we must enable it. */
2571 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2572 || new_flag.bitfield.cpuk1om)
2575 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2580 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2584 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2587 int e = get_symbol_name (&string);
2589 i386_cpu_flags flags;
2591 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2593 if (strcmp (string, cpu_arch[j].name) == 0)
2595 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2599 cpu_arch_name = cpu_arch[j].name;
2600 cpu_sub_arch_name = NULL;
2601 cpu_arch_flags = cpu_arch[j].flags;
2602 if (flag_code == CODE_64BIT)
2604 cpu_arch_flags.bitfield.cpu64 = 1;
2605 cpu_arch_flags.bitfield.cpuno64 = 0;
2609 cpu_arch_flags.bitfield.cpu64 = 0;
2610 cpu_arch_flags.bitfield.cpuno64 = 1;
2612 cpu_arch_isa = cpu_arch[j].type;
2613 cpu_arch_isa_flags = cpu_arch[j].flags;
2614 if (!cpu_arch_tune_set)
2616 cpu_arch_tune = cpu_arch_isa;
2617 cpu_arch_tune_flags = cpu_arch_isa_flags;
2622 flags = cpu_flags_or (cpu_arch_flags,
2625 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2627 if (cpu_sub_arch_name)
2629 char *name = cpu_sub_arch_name;
2630 cpu_sub_arch_name = concat (name,
2632 (const char *) NULL);
2636 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2637 cpu_arch_flags = flags;
2638 cpu_arch_isa_flags = flags;
2642 = cpu_flags_or (cpu_arch_isa_flags,
2644 (void) restore_line_pointer (e);
2645 demand_empty_rest_of_line ();
2650 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2652 /* Disable an ISA extension. */
2653 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2654 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2656 flags = cpu_flags_and_not (cpu_arch_flags,
2657 cpu_noarch[j].flags);
2658 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2660 if (cpu_sub_arch_name)
2662 char *name = cpu_sub_arch_name;
2663 cpu_sub_arch_name = concat (name, string,
2664 (const char *) NULL);
2668 cpu_sub_arch_name = xstrdup (string);
2669 cpu_arch_flags = flags;
2670 cpu_arch_isa_flags = flags;
2672 (void) restore_line_pointer (e);
2673 demand_empty_rest_of_line ();
2677 j = ARRAY_SIZE (cpu_arch);
2680 if (j >= ARRAY_SIZE (cpu_arch))
2681 as_bad (_("no such architecture: `%s'"), string);
2683 *input_line_pointer = e;
2686 as_bad (_("missing cpu architecture"));
2688 no_cond_jump_promotion = 0;
2689 if (*input_line_pointer == ','
2690 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2695 ++input_line_pointer;
2696 e = get_symbol_name (&string);
2698 if (strcmp (string, "nojumps") == 0)
2699 no_cond_jump_promotion = 1;
2700 else if (strcmp (string, "jumps") == 0)
2703 as_bad (_("no such architecture modifier: `%s'"), string);
2705 (void) restore_line_pointer (e);
2708 demand_empty_rest_of_line ();
2711 enum bfd_architecture
2714 if (cpu_arch_isa == PROCESSOR_L1OM)
2716 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2717 || flag_code != CODE_64BIT)
2718 as_fatal (_("Intel L1OM is 64bit ELF only"));
2719 return bfd_arch_l1om;
2721 else if (cpu_arch_isa == PROCESSOR_K1OM)
2723 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2724 || flag_code != CODE_64BIT)
2725 as_fatal (_("Intel K1OM is 64bit ELF only"));
2726 return bfd_arch_k1om;
2728 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2730 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2731 || flag_code == CODE_64BIT)
2732 as_fatal (_("Intel MCU is 32bit ELF only"));
2733 return bfd_arch_iamcu;
2736 return bfd_arch_i386;
2742 if (!strncmp (default_arch, "x86_64", 6))
2744 if (cpu_arch_isa == PROCESSOR_L1OM)
2746 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2747 || default_arch[6] != '\0')
2748 as_fatal (_("Intel L1OM is 64bit ELF only"));
2749 return bfd_mach_l1om;
2751 else if (cpu_arch_isa == PROCESSOR_K1OM)
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2754 || default_arch[6] != '\0')
2755 as_fatal (_("Intel K1OM is 64bit ELF only"));
2756 return bfd_mach_k1om;
2758 else if (default_arch[6] == '\0')
2759 return bfd_mach_x86_64;
2761 return bfd_mach_x64_32;
2763 else if (!strcmp (default_arch, "i386")
2764 || !strcmp (default_arch, "iamcu"))
2766 if (cpu_arch_isa == PROCESSOR_IAMCU)
2768 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2769 as_fatal (_("Intel MCU is 32bit ELF only"));
2770 return bfd_mach_i386_iamcu;
2773 return bfd_mach_i386_i386;
2776 as_fatal (_("unknown architecture"));
2782 const char *hash_err;
2784 /* Support pseudo prefixes like {disp32}. */
2785 lex_type ['{'] = LEX_BEGIN_NAME;
2787 /* Initialize op_hash hash table. */
2788 op_hash = hash_new ();
2791 const insn_template *optab;
2792 templates *core_optab;
2794 /* Setup for loop. */
2796 core_optab = XNEW (templates);
2797 core_optab->start = optab;
2802 if (optab->name == NULL
2803 || strcmp (optab->name, (optab - 1)->name) != 0)
2805 /* different name --> ship out current template list;
2806 add to hash table; & begin anew. */
2807 core_optab->end = optab;
2808 hash_err = hash_insert (op_hash,
2810 (void *) core_optab);
2813 as_fatal (_("can't hash %s: %s"),
2817 if (optab->name == NULL)
2819 core_optab = XNEW (templates);
2820 core_optab->start = optab;
2825 /* Initialize reg_hash hash table. */
2826 reg_hash = hash_new ();
2828 const reg_entry *regtab;
2829 unsigned int regtab_size = i386_regtab_size;
2831 for (regtab = i386_regtab; regtab_size--; regtab++)
2833 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2835 as_fatal (_("can't hash %s: %s"),
2841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2846 for (c = 0; c < 256; c++)
2851 mnemonic_chars[c] = c;
2852 register_chars[c] = c;
2853 operand_chars[c] = c;
2855 else if (ISLOWER (c))
2857 mnemonic_chars[c] = c;
2858 register_chars[c] = c;
2859 operand_chars[c] = c;
2861 else if (ISUPPER (c))
2863 mnemonic_chars[c] = TOLOWER (c);
2864 register_chars[c] = mnemonic_chars[c];
2865 operand_chars[c] = c;
2867 else if (c == '{' || c == '}')
2869 mnemonic_chars[c] = c;
2870 operand_chars[c] = c;
2873 if (ISALPHA (c) || ISDIGIT (c))
2874 identifier_chars[c] = c;
2877 identifier_chars[c] = c;
2878 operand_chars[c] = c;
2883 identifier_chars['@'] = '@';
2886 identifier_chars['?'] = '?';
2887 operand_chars['?'] = '?';
2889 digit_chars['-'] = '-';
2890 mnemonic_chars['_'] = '_';
2891 mnemonic_chars['-'] = '-';
2892 mnemonic_chars['.'] = '.';
2893 identifier_chars['_'] = '_';
2894 identifier_chars['.'] = '.';
2896 for (p = operand_special_chars; *p != '\0'; p++)
2897 operand_chars[(unsigned char) *p] = *p;
2900 if (flag_code == CODE_64BIT)
2902 #if defined (OBJ_COFF) && defined (TE_PE)
2903 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2906 x86_dwarf2_return_column = 16;
2908 x86_cie_data_alignment = -8;
2912 x86_dwarf2_return_column = 8;
2913 x86_cie_data_alignment = -4;
2918 i386_print_statistics (FILE *file)
2920 hash_print_statistics (file, "i386 opcode", op_hash);
2921 hash_print_statistics (file, "i386 register", reg_hash);
2926 /* Debugging routines for md_assemble. */
2927 static void pte (insn_template *);
2928 static void pt (i386_operand_type);
2929 static void pe (expressionS *);
2930 static void ps (symbolS *);
2933 pi (char *line, i386_insn *x)
2937 fprintf (stdout, "%s: template ", line);
2939 fprintf (stdout, " address: base %s index %s scale %x\n",
2940 x->base_reg ? x->base_reg->reg_name : "none",
2941 x->index_reg ? x->index_reg->reg_name : "none",
2942 x->log2_scale_factor);
2943 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2944 x->rm.mode, x->rm.reg, x->rm.regmem);
2945 fprintf (stdout, " sib: base %x index %x scale %x\n",
2946 x->sib.base, x->sib.index, x->sib.scale);
2947 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2948 (x->rex & REX_W) != 0,
2949 (x->rex & REX_R) != 0,
2950 (x->rex & REX_X) != 0,
2951 (x->rex & REX_B) != 0);
2952 for (j = 0; j < x->operands; j++)
2954 fprintf (stdout, " #%d: ", j + 1);
2956 fprintf (stdout, "\n");
2957 if (x->types[j].bitfield.reg
2958 || x->types[j].bitfield.regmmx
2959 || x->types[j].bitfield.regsimd
2960 || x->types[j].bitfield.sreg2
2961 || x->types[j].bitfield.sreg3
2962 || x->types[j].bitfield.control
2963 || x->types[j].bitfield.debug
2964 || x->types[j].bitfield.test)
2965 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2966 if (operand_type_check (x->types[j], imm))
2968 if (operand_type_check (x->types[j], disp))
2969 pe (x->op[j].disps);
2974 pte (insn_template *t)
2977 fprintf (stdout, " %d operands ", t->operands);
2978 fprintf (stdout, "opcode %x ", t->base_opcode);
2979 if (t->extension_opcode != None)
2980 fprintf (stdout, "ext %x ", t->extension_opcode);
2981 if (t->opcode_modifier.d)
2982 fprintf (stdout, "D");
2983 if (t->opcode_modifier.w)
2984 fprintf (stdout, "W");
2985 fprintf (stdout, "\n");
2986 for (j = 0; j < t->operands; j++)
2988 fprintf (stdout, " #%d type ", j + 1);
2989 pt (t->operand_types[j]);
2990 fprintf (stdout, "\n");
2997 fprintf (stdout, " operation %d\n", e->X_op);
2998 fprintf (stdout, " add_number %ld (%lx)\n",
2999 (long) e->X_add_number, (long) e->X_add_number);
3000 if (e->X_add_symbol)
3002 fprintf (stdout, " add_symbol ");
3003 ps (e->X_add_symbol);
3004 fprintf (stdout, "\n");
3008 fprintf (stdout, " op_symbol ");
3009 ps (e->X_op_symbol);
3010 fprintf (stdout, "\n");
3017 fprintf (stdout, "%s type %s%s",
3019 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3020 segment_name (S_GET_SEGMENT (s)));
3023 static struct type_name
3025 i386_operand_type mask;
3028 const type_names[] =
3030 { OPERAND_TYPE_REG8, "r8" },
3031 { OPERAND_TYPE_REG16, "r16" },
3032 { OPERAND_TYPE_REG32, "r32" },
3033 { OPERAND_TYPE_REG64, "r64" },
3034 { OPERAND_TYPE_IMM8, "i8" },
3035 { OPERAND_TYPE_IMM8, "i8s" },
3036 { OPERAND_TYPE_IMM16, "i16" },
3037 { OPERAND_TYPE_IMM32, "i32" },
3038 { OPERAND_TYPE_IMM32S, "i32s" },
3039 { OPERAND_TYPE_IMM64, "i64" },
3040 { OPERAND_TYPE_IMM1, "i1" },
3041 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3042 { OPERAND_TYPE_DISP8, "d8" },
3043 { OPERAND_TYPE_DISP16, "d16" },
3044 { OPERAND_TYPE_DISP32, "d32" },
3045 { OPERAND_TYPE_DISP32S, "d32s" },
3046 { OPERAND_TYPE_DISP64, "d64" },
3047 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3048 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3049 { OPERAND_TYPE_CONTROL, "control reg" },
3050 { OPERAND_TYPE_TEST, "test reg" },
3051 { OPERAND_TYPE_DEBUG, "debug reg" },
3052 { OPERAND_TYPE_FLOATREG, "FReg" },
3053 { OPERAND_TYPE_FLOATACC, "FAcc" },
3054 { OPERAND_TYPE_SREG2, "SReg2" },
3055 { OPERAND_TYPE_SREG3, "SReg3" },
3056 { OPERAND_TYPE_ACC, "Acc" },
3057 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3058 { OPERAND_TYPE_REGMMX, "rMMX" },
3059 { OPERAND_TYPE_REGXMM, "rXMM" },
3060 { OPERAND_TYPE_REGYMM, "rYMM" },
3061 { OPERAND_TYPE_REGZMM, "rZMM" },
3062 { OPERAND_TYPE_REGMASK, "Mask reg" },
3063 { OPERAND_TYPE_ESSEG, "es" },
3067 pt (i386_operand_type t)
3070 i386_operand_type a;
3072 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3074 a = operand_type_and (t, type_names[j].mask);
3075 if (!operand_type_all_zero (&a))
3076 fprintf (stdout, "%s, ", type_names[j].name);
3081 #endif /* DEBUG386 */
3083 static bfd_reloc_code_real_type
3084 reloc (unsigned int size,
3087 bfd_reloc_code_real_type other)
3089 if (other != NO_RELOC)
3091 reloc_howto_type *rel;
3096 case BFD_RELOC_X86_64_GOT32:
3097 return BFD_RELOC_X86_64_GOT64;
3099 case BFD_RELOC_X86_64_GOTPLT64:
3100 return BFD_RELOC_X86_64_GOTPLT64;
3102 case BFD_RELOC_X86_64_PLTOFF64:
3103 return BFD_RELOC_X86_64_PLTOFF64;
3105 case BFD_RELOC_X86_64_GOTPC32:
3106 other = BFD_RELOC_X86_64_GOTPC64;
3108 case BFD_RELOC_X86_64_GOTPCREL:
3109 other = BFD_RELOC_X86_64_GOTPCREL64;
3111 case BFD_RELOC_X86_64_TPOFF32:
3112 other = BFD_RELOC_X86_64_TPOFF64;
3114 case BFD_RELOC_X86_64_DTPOFF32:
3115 other = BFD_RELOC_X86_64_DTPOFF64;
3121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3122 if (other == BFD_RELOC_SIZE32)
3125 other = BFD_RELOC_SIZE64;
3128 as_bad (_("there are no pc-relative size relocations"));
3134 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3135 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3138 rel = bfd_reloc_type_lookup (stdoutput, other);
3140 as_bad (_("unknown relocation (%u)"), other);
3141 else if (size != bfd_get_reloc_size (rel))
3142 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3143 bfd_get_reloc_size (rel),
3145 else if (pcrel && !rel->pc_relative)
3146 as_bad (_("non-pc-relative relocation for pc-relative field"));
3147 else if ((rel->complain_on_overflow == complain_overflow_signed
3149 || (rel->complain_on_overflow == complain_overflow_unsigned
3151 as_bad (_("relocated field and relocation type differ in signedness"));
3160 as_bad (_("there are no unsigned pc-relative relocations"));
3163 case 1: return BFD_RELOC_8_PCREL;
3164 case 2: return BFD_RELOC_16_PCREL;
3165 case 4: return BFD_RELOC_32_PCREL;
3166 case 8: return BFD_RELOC_64_PCREL;
3168 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3175 case 4: return BFD_RELOC_X86_64_32S;
3180 case 1: return BFD_RELOC_8;
3181 case 2: return BFD_RELOC_16;
3182 case 4: return BFD_RELOC_32;
3183 case 8: return BFD_RELOC_64;
3185 as_bad (_("cannot do %s %u byte relocation"),
3186 sign > 0 ? "signed" : "unsigned", size);
3192 /* Here we decide which fixups can be adjusted to make them relative to
3193 the beginning of the section instead of the symbol. Basically we need
3194 to make sure that the dynamic relocations are done correctly, so in
3195 some cases we force the original symbol to be used. */
3198 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3204 /* Don't adjust pc-relative references to merge sections in 64-bit
3206 if (use_rela_relocations
3207 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3211 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3212 and changed later by validate_fix. */
3213 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3214 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3217 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3218 for size relocations. */
3219 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3220 || fixP->fx_r_type == BFD_RELOC_SIZE64
3221 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3222 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3223 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3224 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3234 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3249 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3250 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3251 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3258 intel_float_operand (const char *mnemonic)
3260 /* Note that the value returned is meaningful only for opcodes with (memory)
3261 operands, hence the code here is free to improperly handle opcodes that
3262 have no operands (for better performance and smaller code). */
3264 if (mnemonic[0] != 'f')
3265 return 0; /* non-math */
3267 switch (mnemonic[1])
3269 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3270 the fs segment override prefix not currently handled because no
3271 call path can make opcodes without operands get here */
3273 return 2 /* integer op */;
3275 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3276 return 3; /* fldcw/fldenv */
3279 if (mnemonic[2] != 'o' /* fnop */)
3280 return 3; /* non-waiting control op */
3283 if (mnemonic[2] == 's')
3284 return 3; /* frstor/frstpm */
3287 if (mnemonic[2] == 'a')
3288 return 3; /* fsave */
3289 if (mnemonic[2] == 't')
3291 switch (mnemonic[3])
3293 case 'c': /* fstcw */
3294 case 'd': /* fstdw */
3295 case 'e': /* fstenv */
3296 case 's': /* fsts[gw] */
3302 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3303 return 0; /* fxsave/fxrstor are not really math ops */
3310 /* Build the VEX prefix. */
3313 build_vex_prefix (const insn_template *t)
3315 unsigned int register_specifier;
3316 unsigned int implied_prefix;
3317 unsigned int vector_length;
3319 /* Check register specifier. */
3320 if (i.vex.register_specifier)
3322 register_specifier =
3323 ~register_number (i.vex.register_specifier) & 0xf;
3324 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3327 register_specifier = 0xf;
3329 /* Use 2-byte VEX prefix by swapping destination and source
3331 if (i.vec_encoding != vex_encoding_vex3
3332 && i.dir_encoding == dir_encoding_default
3333 && i.operands == i.reg_operands
3334 && i.tm.opcode_modifier.vexopcode == VEX0F
3335 && i.tm.opcode_modifier.load
3338 unsigned int xchg = i.operands - 1;
3339 union i386_op temp_op;
3340 i386_operand_type temp_type;
3342 temp_type = i.types[xchg];
3343 i.types[xchg] = i.types[0];
3344 i.types[0] = temp_type;
3345 temp_op = i.op[xchg];
3346 i.op[xchg] = i.op[0];
3349 gas_assert (i.rm.mode == 3);
3353 i.rm.regmem = i.rm.reg;
3356 /* Use the next insn. */
3360 if (i.tm.opcode_modifier.vex == VEXScalar)
3361 vector_length = avxscalar;
3362 else if (i.tm.opcode_modifier.vex == VEX256)
3368 /* Determine vector length from the last multi-length vector
3371 for (op = t->operands - 1; op >= 0; op--)
3372 if (t->operand_types[op].bitfield.xmmword
3373 && t->operand_types[op].bitfield.ymmword
3374 && i.types[op].bitfield.ymmword)
3381 switch ((i.tm.base_opcode >> 8) & 0xff)
3386 case DATA_PREFIX_OPCODE:
3389 case REPE_PREFIX_OPCODE:
3392 case REPNE_PREFIX_OPCODE:
3399 /* Use 2-byte VEX prefix if possible. */
3400 if (i.vec_encoding != vex_encoding_vex3
3401 && i.tm.opcode_modifier.vexopcode == VEX0F
3402 && i.tm.opcode_modifier.vexw != VEXW1
3403 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3405 /* 2-byte VEX prefix. */
3409 i.vex.bytes[0] = 0xc5;
3411 /* Check the REX.R bit. */
3412 r = (i.rex & REX_R) ? 0 : 1;
3413 i.vex.bytes[1] = (r << 7
3414 | register_specifier << 3
3415 | vector_length << 2
3420 /* 3-byte VEX prefix. */
3425 switch (i.tm.opcode_modifier.vexopcode)
3429 i.vex.bytes[0] = 0xc4;
3433 i.vex.bytes[0] = 0xc4;
3437 i.vex.bytes[0] = 0xc4;
3441 i.vex.bytes[0] = 0x8f;
3445 i.vex.bytes[0] = 0x8f;
3449 i.vex.bytes[0] = 0x8f;
3455 /* The high 3 bits of the second VEX byte are 1's compliment
3456 of RXB bits from REX. */
3457 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3459 /* Check the REX.W bit. */
3460 w = (i.rex & REX_W) ? 1 : 0;
3461 if (i.tm.opcode_modifier.vexw == VEXW1)
3464 i.vex.bytes[2] = (w << 7
3465 | register_specifier << 3
3466 | vector_length << 2
3471 static INLINE bfd_boolean
3472 is_evex_encoding (const insn_template *t)
3474 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3475 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3476 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3479 /* Build the EVEX prefix. */
3482 build_evex_prefix (void)
3484 unsigned int register_specifier;
3485 unsigned int implied_prefix;
3487 rex_byte vrex_used = 0;
3489 /* Check register specifier. */
3490 if (i.vex.register_specifier)
3492 gas_assert ((i.vrex & REX_X) == 0);
3494 register_specifier = i.vex.register_specifier->reg_num;
3495 if ((i.vex.register_specifier->reg_flags & RegRex))
3496 register_specifier += 8;
3497 /* The upper 16 registers are encoded in the fourth byte of the
3499 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3500 i.vex.bytes[3] = 0x8;
3501 register_specifier = ~register_specifier & 0xf;
3505 register_specifier = 0xf;
3507 /* Encode upper 16 vector index register in the fourth byte of
3509 if (!(i.vrex & REX_X))
3510 i.vex.bytes[3] = 0x8;
3515 switch ((i.tm.base_opcode >> 8) & 0xff)
3520 case DATA_PREFIX_OPCODE:
3523 case REPE_PREFIX_OPCODE:
3526 case REPNE_PREFIX_OPCODE:
3533 /* 4 byte EVEX prefix. */
3535 i.vex.bytes[0] = 0x62;
3538 switch (i.tm.opcode_modifier.vexopcode)
3554 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3556 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3558 /* The fifth bit of the second EVEX byte is 1's compliment of the
3559 REX_R bit in VREX. */
3560 if (!(i.vrex & REX_R))
3561 i.vex.bytes[1] |= 0x10;
3565 if ((i.reg_operands + i.imm_operands) == i.operands)
3567 /* When all operands are registers, the REX_X bit in REX is not
3568 used. We reuse it to encode the upper 16 registers, which is
3569 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3570 as 1's compliment. */
3571 if ((i.vrex & REX_B))
3574 i.vex.bytes[1] &= ~0x40;
3578 /* EVEX instructions shouldn't need the REX prefix. */
3579 i.vrex &= ~vrex_used;
3580 gas_assert (i.vrex == 0);
3582 /* Check the REX.W bit. */
3583 w = (i.rex & REX_W) ? 1 : 0;
3584 if (i.tm.opcode_modifier.vexw)
3586 if (i.tm.opcode_modifier.vexw == VEXW1)
3589 /* If w is not set it means we are dealing with WIG instruction. */
3592 if (evexwig == evexw1)
3596 /* Encode the U bit. */
3597 implied_prefix |= 0x4;
3599 /* The third byte of the EVEX prefix. */
3600 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3602 /* The fourth byte of the EVEX prefix. */
3603 /* The zeroing-masking bit. */
3604 if (i.mask && i.mask->zeroing)
3605 i.vex.bytes[3] |= 0x80;
3607 /* Don't always set the broadcast bit if there is no RC. */
3610 /* Encode the vector length. */
3611 unsigned int vec_length;
3613 if (!i.tm.opcode_modifier.evex
3614 || i.tm.opcode_modifier.evex == EVEXDYN)
3618 /* Determine vector length from the last multi-length vector
3621 for (op = i.operands - 1; op >= 0; op--)
3622 if (i.tm.operand_types[op].bitfield.xmmword
3623 + i.tm.operand_types[op].bitfield.ymmword
3624 + i.tm.operand_types[op].bitfield.zmmword > 1)
3626 if (i.types[op].bitfield.zmmword)
3628 i.tm.opcode_modifier.evex = EVEX512;
3631 else if (i.types[op].bitfield.ymmword)
3633 i.tm.opcode_modifier.evex = EVEX256;
3636 else if (i.types[op].bitfield.xmmword)
3638 i.tm.opcode_modifier.evex = EVEX128;
3641 else if (i.broadcast && (int) op == i.broadcast->operand)
3643 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3644 * i.broadcast->type)
3647 i.tm.opcode_modifier.evex = EVEX512;
3650 i.tm.opcode_modifier.evex = EVEX256;
3653 i.tm.opcode_modifier.evex = EVEX128;
3666 switch (i.tm.opcode_modifier.evex)
3668 case EVEXLIG: /* LL' is ignored */
3669 vec_length = evexlig << 5;
3672 vec_length = 0 << 5;
3675 vec_length = 1 << 5;
3678 vec_length = 2 << 5;
3684 i.vex.bytes[3] |= vec_length;
3685 /* Encode the broadcast bit. */
3687 i.vex.bytes[3] |= 0x10;
3691 if (i.rounding->type != saeonly)
3692 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3694 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3697 if (i.mask && i.mask->mask)
3698 i.vex.bytes[3] |= i.mask->mask->reg_num;
3702 process_immext (void)
3706 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3709 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3710 with an opcode suffix which is coded in the same place as an
3711 8-bit immediate field would be.
3712 Here we check those operands and remove them afterwards. */
3715 for (x = 0; x < i.operands; x++)
3716 if (register_number (i.op[x].regs) != x)
3717 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3718 register_prefix, i.op[x].regs->reg_name, x + 1,
3724 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3726 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3727 suffix which is coded in the same place as an 8-bit immediate
3729 Here we check those operands and remove them afterwards. */
3732 if (i.operands != 3)
3735 for (x = 0; x < 2; x++)
3736 if (register_number (i.op[x].regs) != x)
3737 goto bad_register_operand;
3739 /* Check for third operand for mwaitx/monitorx insn. */
3740 if (register_number (i.op[x].regs)
3741 != (x + (i.tm.extension_opcode == 0xfb)))
3743 bad_register_operand:
3744 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3745 register_prefix, i.op[x].regs->reg_name, x+1,
3752 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3753 which is coded in the same place as an 8-bit immediate field
3754 would be. Here we fake an 8-bit immediate operand from the
3755 opcode suffix stored in tm.extension_opcode.
3757 AVX instructions also use this encoding, for some of
3758 3 argument instructions. */
3760 gas_assert (i.imm_operands <= 1
3762 || ((i.tm.opcode_modifier.vex
3763 || i.tm.opcode_modifier.vexopcode
3764 || is_evex_encoding (&i.tm))
3765 && i.operands <= 4)));
3767 exp = &im_expressions[i.imm_operands++];
3768 i.op[i.operands].imms = exp;
3769 i.types[i.operands] = imm8;
3771 exp->X_op = O_constant;
3772 exp->X_add_number = i.tm.extension_opcode;
3773 i.tm.extension_opcode = None;
3780 switch (i.tm.opcode_modifier.hleprefixok)
3785 as_bad (_("invalid instruction `%s' after `%s'"),
3786 i.tm.name, i.hle_prefix);
3789 if (i.prefix[LOCK_PREFIX])
3791 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3795 case HLEPrefixRelease:
3796 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3798 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3802 if (i.mem_operands == 0
3803 || !operand_type_check (i.types[i.operands - 1], anymem))
3805 as_bad (_("memory destination needed for instruction `%s'"
3806 " after `xrelease'"), i.tm.name);
3813 /* Try the shortest encoding by shortening operand size. */
3816 optimize_encoding (void)
3820 if (optimize_for_space
3821 && i.reg_operands == 1
3822 && i.imm_operands == 1
3823 && !i.types[1].bitfield.byte
3824 && i.op[0].imms->X_op == O_constant
3825 && fits_in_imm7 (i.op[0].imms->X_add_number)
3826 && ((i.tm.base_opcode == 0xa8
3827 && i.tm.extension_opcode == None)
3828 || (i.tm.base_opcode == 0xf6
3829 && i.tm.extension_opcode == 0x0)))
3832 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3834 unsigned int base_regnum = i.op[1].regs->reg_num;
3835 if (flag_code == CODE_64BIT || base_regnum < 4)
3837 i.types[1].bitfield.byte = 1;
3838 /* Ignore the suffix. */
3840 if (base_regnum >= 4
3841 && !(i.op[1].regs->reg_flags & RegRex))
3843 /* Handle SP, BP, SI and DI registers. */
3844 if (i.types[1].bitfield.word)
3846 else if (i.types[1].bitfield.dword)
3854 else if (flag_code == CODE_64BIT
3855 && ((i.types[1].bitfield.qword
3856 && i.reg_operands == 1
3857 && i.imm_operands == 1
3858 && i.op[0].imms->X_op == O_constant
3859 && ((i.tm.base_opcode == 0xb0
3860 && i.tm.extension_opcode == None
3861 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3862 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3863 && (((i.tm.base_opcode == 0x24
3864 || i.tm.base_opcode == 0xa8)
3865 && i.tm.extension_opcode == None)
3866 || (i.tm.base_opcode == 0x80
3867 && i.tm.extension_opcode == 0x4)
3868 || ((i.tm.base_opcode == 0xf6
3869 || i.tm.base_opcode == 0xc6)
3870 && i.tm.extension_opcode == 0x0)))))
3871 || (i.types[0].bitfield.qword
3872 && ((i.reg_operands == 2
3873 && i.op[0].regs == i.op[1].regs
3874 && ((i.tm.base_opcode == 0x30
3875 || i.tm.base_opcode == 0x28)
3876 && i.tm.extension_opcode == None))
3877 || (i.reg_operands == 1
3879 && i.tm.base_opcode == 0x30
3880 && i.tm.extension_opcode == None)))))
3883 andq $imm31, %r64 -> andl $imm31, %r32
3884 testq $imm31, %r64 -> testl $imm31, %r32
3885 xorq %r64, %r64 -> xorl %r32, %r32
3886 subq %r64, %r64 -> subl %r32, %r32
3887 movq $imm31, %r64 -> movl $imm31, %r32
3888 movq $imm32, %r64 -> movl $imm32, %r32
3890 i.tm.opcode_modifier.norex64 = 1;
3891 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3894 movq $imm31, %r64 -> movl $imm31, %r32
3895 movq $imm32, %r64 -> movl $imm32, %r32
3897 i.tm.operand_types[0].bitfield.imm32 = 1;
3898 i.tm.operand_types[0].bitfield.imm32s = 0;
3899 i.tm.operand_types[0].bitfield.imm64 = 0;
3900 i.types[0].bitfield.imm32 = 1;
3901 i.types[0].bitfield.imm32s = 0;
3902 i.types[0].bitfield.imm64 = 0;
3903 i.types[1].bitfield.dword = 1;
3904 i.types[1].bitfield.qword = 0;
3905 if (i.tm.base_opcode == 0xc6)
3908 movq $imm31, %r64 -> movl $imm31, %r32
3910 i.tm.base_opcode = 0xb0;
3911 i.tm.extension_opcode = None;
3912 i.tm.opcode_modifier.shortform = 1;
3913 i.tm.opcode_modifier.modrm = 0;
3917 else if (optimize > 1
3918 && i.reg_operands == 3
3919 && i.op[0].regs == i.op[1].regs
3920 && !i.types[2].bitfield.xmmword
3921 && (i.tm.opcode_modifier.vex
3922 || ((!i.mask || i.mask->zeroing)
3924 && is_evex_encoding (&i.tm)
3925 && (i.vec_encoding != vex_encoding_evex
3926 || i.tm.cpu_flags.bitfield.cpuavx512vl
3927 || (i.tm.operand_types[2].bitfield.zmmword
3928 && i.types[2].bitfield.ymmword)
3929 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3930 && ((i.tm.base_opcode == 0x55
3931 || i.tm.base_opcode == 0x6655
3932 || i.tm.base_opcode == 0x66df
3933 || i.tm.base_opcode == 0x57
3934 || i.tm.base_opcode == 0x6657
3935 || i.tm.base_opcode == 0x66ef
3936 || i.tm.base_opcode == 0x66f8
3937 || i.tm.base_opcode == 0x66f9
3938 || i.tm.base_opcode == 0x66fa
3939 || i.tm.base_opcode == 0x66fb)
3940 && i.tm.extension_opcode == None))
3943 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3945 EVEX VOP %zmmM, %zmmM, %zmmN
3946 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3947 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3948 EVEX VOP %ymmM, %ymmM, %ymmN
3949 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3950 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3951 VEX VOP %ymmM, %ymmM, %ymmN
3952 -> VEX VOP %xmmM, %xmmM, %xmmN
3953 VOP, one of vpandn and vpxor:
3954 VEX VOP %ymmM, %ymmM, %ymmN
3955 -> VEX VOP %xmmM, %xmmM, %xmmN
3956 VOP, one of vpandnd and vpandnq:
3957 EVEX VOP %zmmM, %zmmM, %zmmN
3958 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3959 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3960 EVEX VOP %ymmM, %ymmM, %ymmN
3961 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3962 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3963 VOP, one of vpxord and vpxorq:
3964 EVEX VOP %zmmM, %zmmM, %zmmN
3965 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3966 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3967 EVEX VOP %ymmM, %ymmM, %ymmN
3968 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3969 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3971 if (is_evex_encoding (&i.tm))
3973 if (i.vec_encoding == vex_encoding_evex)
3974 i.tm.opcode_modifier.evex = EVEX128;
3977 i.tm.opcode_modifier.vex = VEX128;
3978 i.tm.opcode_modifier.vexw = VEXW0;
3979 i.tm.opcode_modifier.evex = 0;
3983 i.tm.opcode_modifier.vex = VEX128;
3985 if (i.tm.opcode_modifier.vex)
3986 for (j = 0; j < 3; j++)
3988 i.types[j].bitfield.xmmword = 1;
3989 i.types[j].bitfield.ymmword = 0;
3994 /* This is the guts of the machine-dependent assembler. LINE points to a
3995 machine dependent instruction. This function is supposed to emit
3996 the frags/bytes it assembles to. */
3999 md_assemble (char *line)
4002 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4003 const insn_template *t;
4005 /* Initialize globals. */
4006 memset (&i, '\0', sizeof (i));
4007 for (j = 0; j < MAX_OPERANDS; j++)
4008 i.reloc[j] = NO_RELOC;
4009 memset (disp_expressions, '\0', sizeof (disp_expressions));
4010 memset (im_expressions, '\0', sizeof (im_expressions));
4011 save_stack_p = save_stack;
4013 /* First parse an instruction mnemonic & call i386_operand for the operands.
4014 We assume that the scrubber has arranged it so that line[0] is the valid
4015 start of a (possibly prefixed) mnemonic. */
4017 line = parse_insn (line, mnemonic);
4020 mnem_suffix = i.suffix;
4022 line = parse_operands (line, mnemonic);
4024 xfree (i.memop1_string);
4025 i.memop1_string = NULL;
4029 /* Now we've parsed the mnemonic into a set of templates, and have the
4030 operands at hand. */
4032 /* All intel opcodes have reversed operands except for "bound" and
4033 "enter". We also don't reverse intersegment "jmp" and "call"
4034 instructions with 2 immediate operands so that the immediate segment
4035 precedes the offset, as it does when in AT&T mode. */
4038 && (strcmp (mnemonic, "bound") != 0)
4039 && (strcmp (mnemonic, "invlpga") != 0)
4040 && !(operand_type_check (i.types[0], imm)
4041 && operand_type_check (i.types[1], imm)))
4044 /* The order of the immediates should be reversed
4045 for 2 immediates extrq and insertq instructions */
4046 if (i.imm_operands == 2
4047 && (strcmp (mnemonic, "extrq") == 0
4048 || strcmp (mnemonic, "insertq") == 0))
4049 swap_2_operands (0, 1);
4054 /* Don't optimize displacement for movabs since it only takes 64bit
4057 && i.disp_encoding != disp_encoding_32bit
4058 && (flag_code != CODE_64BIT
4059 || strcmp (mnemonic, "movabs") != 0))
4062 /* Next, we find a template that matches the given insn,
4063 making sure the overlap of the given operands types is consistent
4064 with the template operand types. */
4066 if (!(t = match_template (mnem_suffix)))
4069 if (sse_check != check_none
4070 && !i.tm.opcode_modifier.noavx
4071 && !i.tm.cpu_flags.bitfield.cpuavx
4072 && (i.tm.cpu_flags.bitfield.cpusse
4073 || i.tm.cpu_flags.bitfield.cpusse2
4074 || i.tm.cpu_flags.bitfield.cpusse3
4075 || i.tm.cpu_flags.bitfield.cpussse3
4076 || i.tm.cpu_flags.bitfield.cpusse4_1
4077 || i.tm.cpu_flags.bitfield.cpusse4_2
4078 || i.tm.cpu_flags.bitfield.cpupclmul
4079 || i.tm.cpu_flags.bitfield.cpuaes
4080 || i.tm.cpu_flags.bitfield.cpugfni))
4082 (sse_check == check_warning
4084 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4087 /* Zap movzx and movsx suffix. The suffix has been set from
4088 "word ptr" or "byte ptr" on the source operand in Intel syntax
4089 or extracted from mnemonic in AT&T syntax. But we'll use
4090 the destination register to choose the suffix for encoding. */
4091 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4093 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4094 there is no suffix, the default will be byte extension. */
4095 if (i.reg_operands != 2
4098 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4103 if (i.tm.opcode_modifier.fwait)
4104 if (!add_prefix (FWAIT_OPCODE))
4107 /* Check if REP prefix is OK. */
4108 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4110 as_bad (_("invalid instruction `%s' after `%s'"),
4111 i.tm.name, i.rep_prefix);
4115 /* Check for lock without a lockable instruction. Destination operand
4116 must be memory unless it is xchg (0x86). */
4117 if (i.prefix[LOCK_PREFIX]
4118 && (!i.tm.opcode_modifier.islockable
4119 || i.mem_operands == 0
4120 || (i.tm.base_opcode != 0x86
4121 && !operand_type_check (i.types[i.operands - 1], anymem))))
4123 as_bad (_("expecting lockable instruction after `lock'"));
4127 /* Check if HLE prefix is OK. */
4128 if (i.hle_prefix && !check_hle ())
4131 /* Check BND prefix. */
4132 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4133 as_bad (_("expecting valid branch instruction after `bnd'"));
4135 /* Check NOTRACK prefix. */
4136 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4137 as_bad (_("expecting indirect branch instruction after `notrack'"));
4139 if (i.tm.cpu_flags.bitfield.cpumpx)
4141 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4142 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4143 else if (flag_code != CODE_16BIT
4144 ? i.prefix[ADDR_PREFIX]
4145 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4146 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4149 /* Insert BND prefix. */
4150 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4152 if (!i.prefix[BND_PREFIX])
4153 add_prefix (BND_PREFIX_OPCODE);
4154 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4156 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4157 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4161 /* Check string instruction segment overrides. */
4162 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4164 if (!check_string ())
4166 i.disp_operands = 0;
4169 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4170 optimize_encoding ();
4172 if (!process_suffix ())
4175 /* Update operand types. */
4176 for (j = 0; j < i.operands; j++)
4177 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4179 /* Make still unresolved immediate matches conform to size of immediate
4180 given in i.suffix. */
4181 if (!finalize_imm ())
4184 if (i.types[0].bitfield.imm1)
4185 i.imm_operands = 0; /* kludge for shift insns. */
4187 /* We only need to check those implicit registers for instructions
4188 with 3 operands or less. */
4189 if (i.operands <= 3)
4190 for (j = 0; j < i.operands; j++)
4191 if (i.types[j].bitfield.inoutportreg
4192 || i.types[j].bitfield.shiftcount
4193 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4196 /* ImmExt should be processed after SSE2AVX. */
4197 if (!i.tm.opcode_modifier.sse2avx
4198 && i.tm.opcode_modifier.immext)
4201 /* For insns with operands there are more diddles to do to the opcode. */
4204 if (!process_operands ())
4207 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4209 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4210 as_warn (_("translating to `%sp'"), i.tm.name);
4213 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4214 || is_evex_encoding (&i.tm))
4216 if (flag_code == CODE_16BIT)
4218 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4223 if (i.tm.opcode_modifier.vex)
4224 build_vex_prefix (t);
4226 build_evex_prefix ();
4229 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4230 instructions may define INT_OPCODE as well, so avoid this corner
4231 case for those instructions that use MODRM. */
4232 if (i.tm.base_opcode == INT_OPCODE
4233 && !i.tm.opcode_modifier.modrm
4234 && i.op[0].imms->X_add_number == 3)
4236 i.tm.base_opcode = INT3_OPCODE;
4240 if ((i.tm.opcode_modifier.jump
4241 || i.tm.opcode_modifier.jumpbyte
4242 || i.tm.opcode_modifier.jumpdword)
4243 && i.op[0].disps->X_op == O_constant)
4245 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4246 the absolute address given by the constant. Since ix86 jumps and
4247 calls are pc relative, we need to generate a reloc. */
4248 i.op[0].disps->X_add_symbol = &abs_symbol;
4249 i.op[0].disps->X_op = O_symbol;
4252 if (i.tm.opcode_modifier.rex64)
4255 /* For 8 bit registers we need an empty rex prefix. Also if the
4256 instruction already has a prefix, we need to convert old
4257 registers to new ones. */
4259 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4260 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4261 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4262 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4263 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4264 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4269 i.rex |= REX_OPCODE;
4270 for (x = 0; x < 2; x++)
4272 /* Look for 8 bit operand that uses old registers. */
4273 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4274 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4276 /* In case it is "hi" register, give up. */
4277 if (i.op[x].regs->reg_num > 3)
4278 as_bad (_("can't encode register '%s%s' in an "
4279 "instruction requiring REX prefix."),
4280 register_prefix, i.op[x].regs->reg_name);
4282 /* Otherwise it is equivalent to the extended register.
4283 Since the encoding doesn't change this is merely
4284 cosmetic cleanup for debug output. */
4286 i.op[x].regs = i.op[x].regs + 8;
4291 if (i.rex == 0 && i.rex_encoding)
4293 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4294 that uses legacy register. If it is "hi" register, don't add
4295 the REX_OPCODE byte. */
4297 for (x = 0; x < 2; x++)
4298 if (i.types[x].bitfield.reg
4299 && i.types[x].bitfield.byte
4300 && (i.op[x].regs->reg_flags & RegRex64) == 0
4301 && i.op[x].regs->reg_num > 3)
4303 i.rex_encoding = FALSE;
4312 add_prefix (REX_OPCODE | i.rex);
4314 /* We are ready to output the insn. */
4319 parse_insn (char *line, char *mnemonic)
4322 char *token_start = l;
4325 const insn_template *t;
4331 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4336 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4338 as_bad (_("no such instruction: `%s'"), token_start);
4343 if (!is_space_char (*l)
4344 && *l != END_OF_INSN
4346 || (*l != PREFIX_SEPARATOR
4349 as_bad (_("invalid character %s in mnemonic"),
4350 output_invalid (*l));
4353 if (token_start == l)
4355 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4356 as_bad (_("expecting prefix; got nothing"));
4358 as_bad (_("expecting mnemonic; got nothing"));
4362 /* Look up instruction (or prefix) via hash table. */
4363 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4365 if (*l != END_OF_INSN
4366 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4367 && current_templates
4368 && current_templates->start->opcode_modifier.isprefix)
4370 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4372 as_bad ((flag_code != CODE_64BIT
4373 ? _("`%s' is only supported in 64-bit mode")
4374 : _("`%s' is not supported in 64-bit mode")),
4375 current_templates->start->name);
4378 /* If we are in 16-bit mode, do not allow addr16 or data16.
4379 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4380 if ((current_templates->start->opcode_modifier.size16
4381 || current_templates->start->opcode_modifier.size32)
4382 && flag_code != CODE_64BIT
4383 && (current_templates->start->opcode_modifier.size32
4384 ^ (flag_code == CODE_16BIT)))
4386 as_bad (_("redundant %s prefix"),
4387 current_templates->start->name);
4390 if (current_templates->start->opcode_length == 0)
4392 /* Handle pseudo prefixes. */
4393 switch (current_templates->start->base_opcode)
4397 i.disp_encoding = disp_encoding_8bit;
4401 i.disp_encoding = disp_encoding_32bit;
4405 i.dir_encoding = dir_encoding_load;
4409 i.dir_encoding = dir_encoding_store;
4413 i.vec_encoding = vex_encoding_vex2;
4417 i.vec_encoding = vex_encoding_vex3;
4421 i.vec_encoding = vex_encoding_evex;
4425 i.rex_encoding = TRUE;
4429 i.no_optimize = TRUE;
4437 /* Add prefix, checking for repeated prefixes. */
4438 switch (add_prefix (current_templates->start->base_opcode))
4443 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4444 i.notrack_prefix = current_templates->start->name;
4447 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4448 i.hle_prefix = current_templates->start->name;
4449 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4450 i.bnd_prefix = current_templates->start->name;
4452 i.rep_prefix = current_templates->start->name;
4458 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4465 if (!current_templates)
4467 /* Check if we should swap operand or force 32bit displacement in
4469 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4470 i.dir_encoding = dir_encoding_store;
4471 else if (mnem_p - 3 == dot_p
4474 i.disp_encoding = disp_encoding_8bit;
4475 else if (mnem_p - 4 == dot_p
4479 i.disp_encoding = disp_encoding_32bit;
4484 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4487 if (!current_templates)
4490 /* See if we can get a match by trimming off a suffix. */
4493 case WORD_MNEM_SUFFIX:
4494 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4495 i.suffix = SHORT_MNEM_SUFFIX;
4498 case BYTE_MNEM_SUFFIX:
4499 case QWORD_MNEM_SUFFIX:
4500 i.suffix = mnem_p[-1];
4502 current_templates = (const templates *) hash_find (op_hash,
4505 case SHORT_MNEM_SUFFIX:
4506 case LONG_MNEM_SUFFIX:
4509 i.suffix = mnem_p[-1];
4511 current_templates = (const templates *) hash_find (op_hash,
4520 if (intel_float_operand (mnemonic) == 1)
4521 i.suffix = SHORT_MNEM_SUFFIX;
4523 i.suffix = LONG_MNEM_SUFFIX;
4525 current_templates = (const templates *) hash_find (op_hash,
4530 if (!current_templates)
4532 as_bad (_("no such instruction: `%s'"), token_start);
4537 if (current_templates->start->opcode_modifier.jump
4538 || current_templates->start->opcode_modifier.jumpbyte)
4540 /* Check for a branch hint. We allow ",pt" and ",pn" for
4541 predict taken and predict not taken respectively.
4542 I'm not sure that branch hints actually do anything on loop
4543 and jcxz insns (JumpByte) for current Pentium4 chips. They
4544 may work in the future and it doesn't hurt to accept them
4546 if (l[0] == ',' && l[1] == 'p')
4550 if (!add_prefix (DS_PREFIX_OPCODE))
4554 else if (l[2] == 'n')
4556 if (!add_prefix (CS_PREFIX_OPCODE))
4562 /* Any other comma loses. */
4565 as_bad (_("invalid character %s in mnemonic"),
4566 output_invalid (*l));
4570 /* Check if instruction is supported on specified architecture. */
4572 for (t = current_templates->start; t < current_templates->end; ++t)
4574 supported |= cpu_flags_match (t);
4575 if (supported == CPU_FLAGS_PERFECT_MATCH)
4577 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4578 as_warn (_("use .code16 to ensure correct addressing mode"));
4584 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4585 as_bad (flag_code == CODE_64BIT
4586 ? _("`%s' is not supported in 64-bit mode")
4587 : _("`%s' is only supported in 64-bit mode"),
4588 current_templates->start->name);
4590 as_bad (_("`%s' is not supported on `%s%s'"),
4591 current_templates->start->name,
4592 cpu_arch_name ? cpu_arch_name : default_arch,
4593 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4599 parse_operands (char *l, const char *mnemonic)
4603 /* 1 if operand is pending after ','. */
4604 unsigned int expecting_operand = 0;
4606 /* Non-zero if operand parens not balanced. */
4607 unsigned int paren_not_balanced;
4609 while (*l != END_OF_INSN)
4611 /* Skip optional white space before operand. */
4612 if (is_space_char (*l))
4614 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4616 as_bad (_("invalid character %s before operand %d"),
4617 output_invalid (*l),
4621 token_start = l; /* After white space. */
4622 paren_not_balanced = 0;
4623 while (paren_not_balanced || *l != ',')
4625 if (*l == END_OF_INSN)
4627 if (paren_not_balanced)
4630 as_bad (_("unbalanced parenthesis in operand %d."),
4633 as_bad (_("unbalanced brackets in operand %d."),
4638 break; /* we are done */
4640 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4642 as_bad (_("invalid character %s in operand %d"),
4643 output_invalid (*l),
4650 ++paren_not_balanced;
4652 --paren_not_balanced;
4657 ++paren_not_balanced;
4659 --paren_not_balanced;
4663 if (l != token_start)
4664 { /* Yes, we've read in another operand. */
4665 unsigned int operand_ok;
4666 this_operand = i.operands++;
4667 if (i.operands > MAX_OPERANDS)
4669 as_bad (_("spurious operands; (%d operands/instruction max)"),
4673 i.types[this_operand].bitfield.unspecified = 1;
4674 /* Now parse operand adding info to 'i' as we go along. */
4675 END_STRING_AND_SAVE (l);
4679 i386_intel_operand (token_start,
4680 intel_float_operand (mnemonic));
4682 operand_ok = i386_att_operand (token_start);
4684 RESTORE_END_STRING (l);
4690 if (expecting_operand)
4692 expecting_operand_after_comma:
4693 as_bad (_("expecting operand after ','; got nothing"));
4698 as_bad (_("expecting operand before ','; got nothing"));
4703 /* Now *l must be either ',' or END_OF_INSN. */
4706 if (*++l == END_OF_INSN)
4708 /* Just skip it, if it's \n complain. */
4709 goto expecting_operand_after_comma;
4711 expecting_operand = 1;
4718 swap_2_operands (int xchg1, int xchg2)
4720 union i386_op temp_op;
4721 i386_operand_type temp_type;
4722 enum bfd_reloc_code_real temp_reloc;
4724 temp_type = i.types[xchg2];
4725 i.types[xchg2] = i.types[xchg1];
4726 i.types[xchg1] = temp_type;
4727 temp_op = i.op[xchg2];
4728 i.op[xchg2] = i.op[xchg1];
4729 i.op[xchg1] = temp_op;
4730 temp_reloc = i.reloc[xchg2];
4731 i.reloc[xchg2] = i.reloc[xchg1];
4732 i.reloc[xchg1] = temp_reloc;
4736 if (i.mask->operand == xchg1)
4737 i.mask->operand = xchg2;
4738 else if (i.mask->operand == xchg2)
4739 i.mask->operand = xchg1;
4743 if (i.broadcast->operand == xchg1)
4744 i.broadcast->operand = xchg2;
4745 else if (i.broadcast->operand == xchg2)
4746 i.broadcast->operand = xchg1;
4750 if (i.rounding->operand == xchg1)
4751 i.rounding->operand = xchg2;
4752 else if (i.rounding->operand == xchg2)
4753 i.rounding->operand = xchg1;
4758 swap_operands (void)
4764 swap_2_operands (1, i.operands - 2);
4768 swap_2_operands (0, i.operands - 1);
4774 if (i.mem_operands == 2)
4776 const seg_entry *temp_seg;
4777 temp_seg = i.seg[0];
4778 i.seg[0] = i.seg[1];
4779 i.seg[1] = temp_seg;
4783 /* Try to ensure constant immediates are represented in the smallest
4788 char guess_suffix = 0;
4792 guess_suffix = i.suffix;
4793 else if (i.reg_operands)
4795 /* Figure out a suffix from the last register operand specified.
4796 We can't do this properly yet, ie. excluding InOutPortReg,
4797 but the following works for instructions with immediates.
4798 In any case, we can't set i.suffix yet. */
4799 for (op = i.operands; --op >= 0;)
4800 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4802 guess_suffix = BYTE_MNEM_SUFFIX;
4805 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4807 guess_suffix = WORD_MNEM_SUFFIX;
4810 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4812 guess_suffix = LONG_MNEM_SUFFIX;
4815 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4817 guess_suffix = QWORD_MNEM_SUFFIX;
4821 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4822 guess_suffix = WORD_MNEM_SUFFIX;
4824 for (op = i.operands; --op >= 0;)
4825 if (operand_type_check (i.types[op], imm))
4827 switch (i.op[op].imms->X_op)
4830 /* If a suffix is given, this operand may be shortened. */
4831 switch (guess_suffix)
4833 case LONG_MNEM_SUFFIX:
4834 i.types[op].bitfield.imm32 = 1;
4835 i.types[op].bitfield.imm64 = 1;
4837 case WORD_MNEM_SUFFIX:
4838 i.types[op].bitfield.imm16 = 1;
4839 i.types[op].bitfield.imm32 = 1;
4840 i.types[op].bitfield.imm32s = 1;
4841 i.types[op].bitfield.imm64 = 1;
4843 case BYTE_MNEM_SUFFIX:
4844 i.types[op].bitfield.imm8 = 1;
4845 i.types[op].bitfield.imm8s = 1;
4846 i.types[op].bitfield.imm16 = 1;
4847 i.types[op].bitfield.imm32 = 1;
4848 i.types[op].bitfield.imm32s = 1;
4849 i.types[op].bitfield.imm64 = 1;
4853 /* If this operand is at most 16 bits, convert it
4854 to a signed 16 bit number before trying to see
4855 whether it will fit in an even smaller size.
4856 This allows a 16-bit operand such as $0xffe0 to
4857 be recognised as within Imm8S range. */
4858 if ((i.types[op].bitfield.imm16)
4859 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4861 i.op[op].imms->X_add_number =
4862 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4865 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4866 if ((i.types[op].bitfield.imm32)
4867 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4870 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4871 ^ ((offsetT) 1 << 31))
4872 - ((offsetT) 1 << 31));
4876 = operand_type_or (i.types[op],
4877 smallest_imm_type (i.op[op].imms->X_add_number));
4879 /* We must avoid matching of Imm32 templates when 64bit
4880 only immediate is available. */
4881 if (guess_suffix == QWORD_MNEM_SUFFIX)
4882 i.types[op].bitfield.imm32 = 0;
4889 /* Symbols and expressions. */
4891 /* Convert symbolic operand to proper sizes for matching, but don't
4892 prevent matching a set of insns that only supports sizes other
4893 than those matching the insn suffix. */
4895 i386_operand_type mask, allowed;
4896 const insn_template *t;
4898 operand_type_set (&mask, 0);
4899 operand_type_set (&allowed, 0);
4901 for (t = current_templates->start;
4902 t < current_templates->end;
4904 allowed = operand_type_or (allowed,
4905 t->operand_types[op]);
4906 switch (guess_suffix)
4908 case QWORD_MNEM_SUFFIX:
4909 mask.bitfield.imm64 = 1;
4910 mask.bitfield.imm32s = 1;
4912 case LONG_MNEM_SUFFIX:
4913 mask.bitfield.imm32 = 1;
4915 case WORD_MNEM_SUFFIX:
4916 mask.bitfield.imm16 = 1;
4918 case BYTE_MNEM_SUFFIX:
4919 mask.bitfield.imm8 = 1;
4924 allowed = operand_type_and (mask, allowed);
4925 if (!operand_type_all_zero (&allowed))
4926 i.types[op] = operand_type_and (i.types[op], mask);
4933 /* Try to use the smallest displacement type too. */
4935 optimize_disp (void)
4939 for (op = i.operands; --op >= 0;)
4940 if (operand_type_check (i.types[op], disp))
4942 if (i.op[op].disps->X_op == O_constant)
4944 offsetT op_disp = i.op[op].disps->X_add_number;
4946 if (i.types[op].bitfield.disp16
4947 && (op_disp & ~(offsetT) 0xffff) == 0)
4949 /* If this operand is at most 16 bits, convert
4950 to a signed 16 bit number and don't use 64bit
4952 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4953 i.types[op].bitfield.disp64 = 0;
4956 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4957 if (i.types[op].bitfield.disp32
4958 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4960 /* If this operand is at most 32 bits, convert
4961 to a signed 32 bit number and don't use 64bit
4963 op_disp &= (((offsetT) 2 << 31) - 1);
4964 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4965 i.types[op].bitfield.disp64 = 0;
4968 if (!op_disp && i.types[op].bitfield.baseindex)
4970 i.types[op].bitfield.disp8 = 0;
4971 i.types[op].bitfield.disp16 = 0;
4972 i.types[op].bitfield.disp32 = 0;
4973 i.types[op].bitfield.disp32s = 0;
4974 i.types[op].bitfield.disp64 = 0;
4978 else if (flag_code == CODE_64BIT)
4980 if (fits_in_signed_long (op_disp))
4982 i.types[op].bitfield.disp64 = 0;
4983 i.types[op].bitfield.disp32s = 1;
4985 if (i.prefix[ADDR_PREFIX]
4986 && fits_in_unsigned_long (op_disp))
4987 i.types[op].bitfield.disp32 = 1;
4989 if ((i.types[op].bitfield.disp32
4990 || i.types[op].bitfield.disp32s
4991 || i.types[op].bitfield.disp16)
4992 && fits_in_disp8 (op_disp))
4993 i.types[op].bitfield.disp8 = 1;
4995 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4996 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4998 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4999 i.op[op].disps, 0, i.reloc[op]);
5000 i.types[op].bitfield.disp8 = 0;
5001 i.types[op].bitfield.disp16 = 0;
5002 i.types[op].bitfield.disp32 = 0;
5003 i.types[op].bitfield.disp32s = 0;
5004 i.types[op].bitfield.disp64 = 0;
5007 /* We only support 64bit displacement on constants. */
5008 i.types[op].bitfield.disp64 = 0;
5012 /* Check if operands are valid for the instruction. */
5015 check_VecOperands (const insn_template *t)
5019 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5021 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5022 any one operand are implicity requiring AVX512VL support if the actual
5023 operand size is YMMword or XMMword. Since this function runs after
5024 template matching, there's no need to check for YMMword/XMMword in
5026 cpu = cpu_flags_and (t->cpu_flags, avx512);
5027 if (!cpu_flags_all_zero (&cpu)
5028 && !t->cpu_flags.bitfield.cpuavx512vl
5029 && !cpu_arch_flags.bitfield.cpuavx512vl)
5031 for (op = 0; op < t->operands; ++op)
5033 if (t->operand_types[op].bitfield.zmmword
5034 && (i.types[op].bitfield.ymmword
5035 || i.types[op].bitfield.xmmword))
5037 i.error = unsupported;
5043 /* Without VSIB byte, we can't have a vector register for index. */
5044 if (!t->opcode_modifier.vecsib
5046 && (i.index_reg->reg_type.bitfield.xmmword
5047 || i.index_reg->reg_type.bitfield.ymmword
5048 || i.index_reg->reg_type.bitfield.zmmword))
5050 i.error = unsupported_vector_index_register;
5054 /* Check if default mask is allowed. */
5055 if (t->opcode_modifier.nodefmask
5056 && (!i.mask || i.mask->mask->reg_num == 0))
5058 i.error = no_default_mask;
5062 /* For VSIB byte, we need a vector register for index, and all vector
5063 registers must be distinct. */
5064 if (t->opcode_modifier.vecsib)
5067 || !((t->opcode_modifier.vecsib == VecSIB128
5068 && i.index_reg->reg_type.bitfield.xmmword)
5069 || (t->opcode_modifier.vecsib == VecSIB256
5070 && i.index_reg->reg_type.bitfield.ymmword)
5071 || (t->opcode_modifier.vecsib == VecSIB512
5072 && i.index_reg->reg_type.bitfield.zmmword)))
5074 i.error = invalid_vsib_address;
5078 gas_assert (i.reg_operands == 2 || i.mask);
5079 if (i.reg_operands == 2 && !i.mask)
5081 gas_assert (i.types[0].bitfield.regsimd);
5082 gas_assert (i.types[0].bitfield.xmmword
5083 || i.types[0].bitfield.ymmword);
5084 gas_assert (i.types[2].bitfield.regsimd);
5085 gas_assert (i.types[2].bitfield.xmmword
5086 || i.types[2].bitfield.ymmword);
5087 if (operand_check == check_none)
5089 if (register_number (i.op[0].regs)
5090 != register_number (i.index_reg)
5091 && register_number (i.op[2].regs)
5092 != register_number (i.index_reg)
5093 && register_number (i.op[0].regs)
5094 != register_number (i.op[2].regs))
5096 if (operand_check == check_error)
5098 i.error = invalid_vector_register_set;
5101 as_warn (_("mask, index, and destination registers should be distinct"));
5103 else if (i.reg_operands == 1 && i.mask)
5105 if (i.types[1].bitfield.regsimd
5106 && (i.types[1].bitfield.xmmword
5107 || i.types[1].bitfield.ymmword
5108 || i.types[1].bitfield.zmmword)
5109 && (register_number (i.op[1].regs)
5110 == register_number (i.index_reg)))
5112 if (operand_check == check_error)
5114 i.error = invalid_vector_register_set;
5117 if (operand_check != check_none)
5118 as_warn (_("index and destination registers should be distinct"));
5123 /* Check if broadcast is supported by the instruction and is applied
5124 to the memory operand. */
5127 i386_operand_type type, overlap;
5129 /* Check if specified broadcast is supported in this instruction,
5130 and it's applied to memory operand of DWORD or QWORD type. */
5131 op = i.broadcast->operand;
5132 if (!t->opcode_modifier.broadcast
5133 || !i.types[op].bitfield.mem
5134 || (!i.types[op].bitfield.unspecified
5135 && (t->operand_types[op].bitfield.dword
5136 ? !i.types[op].bitfield.dword
5137 : !i.types[op].bitfield.qword)))
5140 i.error = unsupported_broadcast;
5144 operand_type_set (&type, 0);
5145 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5148 type.bitfield.qword = 1;
5151 type.bitfield.xmmword = 1;
5154 type.bitfield.ymmword = 1;
5157 type.bitfield.zmmword = 1;
5163 overlap = operand_type_and (type, t->operand_types[op]);
5164 if (operand_type_all_zero (&overlap))
5167 if (t->opcode_modifier.checkregsize)
5171 type.bitfield.baseindex = 1;
5172 for (j = 0; j < i.operands; ++j)
5175 && !operand_type_register_match(i.types[j],
5176 t->operand_types[j],
5178 t->operand_types[op]))
5183 /* If broadcast is supported in this instruction, we need to check if
5184 operand of one-element size isn't specified without broadcast. */
5185 else if (t->opcode_modifier.broadcast && i.mem_operands)
5187 /* Find memory operand. */
5188 for (op = 0; op < i.operands; op++)
5189 if (operand_type_check (i.types[op], anymem))
5191 gas_assert (op < i.operands);
5192 /* Check size of the memory operand. */
5193 if (t->operand_types[op].bitfield.dword
5194 ? i.types[op].bitfield.dword
5195 : i.types[op].bitfield.qword)
5197 i.error = broadcast_needed;
5202 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5204 /* Check if requested masking is supported. */
5206 && (!t->opcode_modifier.masking
5208 && t->opcode_modifier.masking == MERGING_MASKING)))
5210 i.error = unsupported_masking;
5214 /* Check if masking is applied to dest operand. */
5215 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5217 i.error = mask_not_on_destination;
5224 if ((i.rounding->type != saeonly
5225 && !t->opcode_modifier.staticrounding)
5226 || (i.rounding->type == saeonly
5227 && (t->opcode_modifier.staticrounding
5228 || !t->opcode_modifier.sae)))
5230 i.error = unsupported_rc_sae;
5233 /* If the instruction has several immediate operands and one of
5234 them is rounding, the rounding operand should be the last
5235 immediate operand. */
5236 if (i.imm_operands > 1
5237 && i.rounding->operand != (int) (i.imm_operands - 1))
5239 i.error = rc_sae_operand_not_last_imm;
5244 /* Check vector Disp8 operand. */
5245 if (t->opcode_modifier.disp8memshift
5246 && i.disp_encoding != disp_encoding_32bit)
5249 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5250 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5251 i.memshift = t->opcode_modifier.disp8memshift;
5254 const i386_operand_type *type = NULL;
5257 for (op = 0; op < i.operands; op++)
5258 if (operand_type_check (i.types[op], anymem))
5260 if (t->operand_types[op].bitfield.xmmword
5261 + t->operand_types[op].bitfield.ymmword
5262 + t->operand_types[op].bitfield.zmmword <= 1)
5263 type = &t->operand_types[op];
5264 else if (!i.types[op].bitfield.unspecified)
5265 type = &i.types[op];
5267 else if (i.types[op].bitfield.regsimd)
5269 if (i.types[op].bitfield.zmmword)
5271 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5273 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5279 if (type->bitfield.zmmword)
5281 else if (type->bitfield.ymmword)
5283 else if (type->bitfield.xmmword)
5287 /* For the check in fits_in_disp8(). */
5288 if (i.memshift == 0)
5292 for (op = 0; op < i.operands; op++)
5293 if (operand_type_check (i.types[op], disp)
5294 && i.op[op].disps->X_op == O_constant)
5296 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5298 i.types[op].bitfield.disp8 = 1;
5301 i.types[op].bitfield.disp8 = 0;
5310 /* Check if operands are valid for the instruction. Update VEX
5314 VEX_check_operands (const insn_template *t)
5316 if (i.vec_encoding == vex_encoding_evex)
5318 /* This instruction must be encoded with EVEX prefix. */
5319 if (!is_evex_encoding (t))
5321 i.error = unsupported;
5327 if (!t->opcode_modifier.vex)
5329 /* This instruction template doesn't have VEX prefix. */
5330 if (i.vec_encoding != vex_encoding_default)
5332 i.error = unsupported;
5338 /* Only check VEX_Imm4, which must be the first operand. */
5339 if (t->operand_types[0].bitfield.vec_imm4)
5341 if (i.op[0].imms->X_op != O_constant
5342 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5348 /* Turn off Imm8 so that update_imm won't complain. */
5349 i.types[0] = vec_imm4;
5355 static const insn_template *
5356 match_template (char mnem_suffix)
5358 /* Points to template once we've found it. */
5359 const insn_template *t;
5360 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5361 i386_operand_type overlap4;
5362 unsigned int found_reverse_match;
5363 i386_opcode_modifier suffix_check, mnemsuf_check;
5364 i386_operand_type operand_types [MAX_OPERANDS];
5365 int addr_prefix_disp;
5367 unsigned int found_cpu_match, size_match;
5368 unsigned int check_register;
5369 enum i386_error specific_error = 0;
5371 #if MAX_OPERANDS != 5
5372 # error "MAX_OPERANDS must be 5."
5375 found_reverse_match = 0;
5376 addr_prefix_disp = -1;
5378 memset (&suffix_check, 0, sizeof (suffix_check));
5379 if (intel_syntax && i.broadcast)
5381 else if (i.suffix == BYTE_MNEM_SUFFIX)
5382 suffix_check.no_bsuf = 1;
5383 else if (i.suffix == WORD_MNEM_SUFFIX)
5384 suffix_check.no_wsuf = 1;
5385 else if (i.suffix == SHORT_MNEM_SUFFIX)
5386 suffix_check.no_ssuf = 1;
5387 else if (i.suffix == LONG_MNEM_SUFFIX)
5388 suffix_check.no_lsuf = 1;
5389 else if (i.suffix == QWORD_MNEM_SUFFIX)
5390 suffix_check.no_qsuf = 1;
5391 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5392 suffix_check.no_ldsuf = 1;
5394 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5397 switch (mnem_suffix)
5399 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5400 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5401 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5402 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5403 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5407 /* Must have right number of operands. */
5408 i.error = number_of_operands_mismatch;
5410 for (t = current_templates->start; t < current_templates->end; t++)
5412 addr_prefix_disp = -1;
5414 if (i.operands != t->operands)
5417 /* Check processor support. */
5418 i.error = unsupported;
5419 found_cpu_match = (cpu_flags_match (t)
5420 == CPU_FLAGS_PERFECT_MATCH);
5421 if (!found_cpu_match)
5424 /* Check AT&T mnemonic. */
5425 i.error = unsupported_with_intel_mnemonic;
5426 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5429 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5430 i.error = unsupported_syntax;
5431 if ((intel_syntax && t->opcode_modifier.attsyntax)
5432 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5433 || (intel64 && t->opcode_modifier.amd64)
5434 || (!intel64 && t->opcode_modifier.intel64))
5437 /* Check the suffix, except for some instructions in intel mode. */
5438 i.error = invalid_instruction_suffix;
5439 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5440 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5441 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5442 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5443 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5444 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5445 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5447 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5448 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5449 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5450 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5451 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5452 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5453 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5456 size_match = operand_size_match (t);
5460 for (j = 0; j < MAX_OPERANDS; j++)
5461 operand_types[j] = t->operand_types[j];
5463 /* In general, don't allow 64-bit operands in 32-bit mode. */
5464 if (i.suffix == QWORD_MNEM_SUFFIX
5465 && flag_code != CODE_64BIT
5467 ? (!t->opcode_modifier.ignoresize
5468 && !t->opcode_modifier.broadcast
5469 && !intel_float_operand (t->name))
5470 : intel_float_operand (t->name) != 2)
5471 && ((!operand_types[0].bitfield.regmmx
5472 && !operand_types[0].bitfield.regsimd)
5473 || (!operand_types[t->operands > 1].bitfield.regmmx
5474 && !operand_types[t->operands > 1].bitfield.regsimd))
5475 && (t->base_opcode != 0x0fc7
5476 || t->extension_opcode != 1 /* cmpxchg8b */))
5479 /* In general, don't allow 32-bit operands on pre-386. */
5480 else if (i.suffix == LONG_MNEM_SUFFIX
5481 && !cpu_arch_flags.bitfield.cpui386
5483 ? (!t->opcode_modifier.ignoresize
5484 && !intel_float_operand (t->name))
5485 : intel_float_operand (t->name) != 2)
5486 && ((!operand_types[0].bitfield.regmmx
5487 && !operand_types[0].bitfield.regsimd)
5488 || (!operand_types[t->operands > 1].bitfield.regmmx
5489 && !operand_types[t->operands > 1].bitfield.regsimd)))
5492 /* Do not verify operands when there are none. */
5496 /* We've found a match; break out of loop. */
5500 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5501 into Disp32/Disp16/Disp32 operand. */
5502 if (i.prefix[ADDR_PREFIX] != 0)
5504 /* There should be only one Disp operand. */
5508 for (j = 0; j < MAX_OPERANDS; j++)
5510 if (operand_types[j].bitfield.disp16)
5512 addr_prefix_disp = j;
5513 operand_types[j].bitfield.disp32 = 1;
5514 operand_types[j].bitfield.disp16 = 0;
5520 for (j = 0; j < MAX_OPERANDS; j++)
5522 if (operand_types[j].bitfield.disp32)
5524 addr_prefix_disp = j;
5525 operand_types[j].bitfield.disp32 = 0;
5526 operand_types[j].bitfield.disp16 = 1;
5532 for (j = 0; j < MAX_OPERANDS; j++)
5534 if (operand_types[j].bitfield.disp64)
5536 addr_prefix_disp = j;
5537 operand_types[j].bitfield.disp64 = 0;
5538 operand_types[j].bitfield.disp32 = 1;
5546 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5547 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5550 /* We check register size if needed. */
5551 if (t->opcode_modifier.checkregsize)
5553 check_register = (1 << t->operands) - 1;
5555 check_register &= ~(1 << i.broadcast->operand);
5560 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5561 switch (t->operands)
5564 if (!operand_type_match (overlap0, i.types[0]))
5568 /* xchg %eax, %eax is a special case. It is an alias for nop
5569 only in 32bit mode and we can use opcode 0x90. In 64bit
5570 mode, we can't use 0x90 for xchg %eax, %eax since it should
5571 zero-extend %eax to %rax. */
5572 if (flag_code == CODE_64BIT
5573 && t->base_opcode == 0x90
5574 && operand_type_equal (&i.types [0], &acc32)
5575 && operand_type_equal (&i.types [1], &acc32))
5577 /* xrelease mov %eax, <disp> is another special case. It must not
5578 match the accumulator-only encoding of mov. */
5579 if (flag_code != CODE_64BIT
5581 && t->base_opcode == 0xa0
5582 && i.types[0].bitfield.acc
5583 && operand_type_check (i.types[1], anymem))
5585 if (!(size_match & MATCH_STRAIGHT))
5587 /* If we want store form, we reverse direction of operands. */
5588 if (i.dir_encoding == dir_encoding_store
5589 && t->opcode_modifier.d)
5594 /* If we want store form, we skip the current load. */
5595 if (i.dir_encoding == dir_encoding_store
5596 && i.mem_operands == 0
5597 && t->opcode_modifier.load)
5602 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5603 if (!operand_type_match (overlap0, i.types[0])
5604 || !operand_type_match (overlap1, i.types[1])
5605 || ((check_register & 3) == 3
5606 && !operand_type_register_match (i.types[0],
5611 /* Check if other direction is valid ... */
5612 if (!t->opcode_modifier.d)
5616 if (!(size_match & MATCH_REVERSE))
5618 /* Try reversing direction of operands. */
5619 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5620 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5621 if (!operand_type_match (overlap0, i.types[0])
5622 || !operand_type_match (overlap1, i.types[1])
5624 && !operand_type_register_match (i.types[0],
5629 /* Does not match either direction. */
5632 /* found_reverse_match holds which of D or FloatR
5634 if (!t->opcode_modifier.d)
5635 found_reverse_match = 0;
5636 else if (operand_types[0].bitfield.tbyte)
5637 found_reverse_match = Opcode_FloatD;
5639 found_reverse_match = Opcode_D;
5640 if (t->opcode_modifier.floatr)
5641 found_reverse_match |= Opcode_FloatR;
5645 /* Found a forward 2 operand match here. */
5646 switch (t->operands)
5649 overlap4 = operand_type_and (i.types[4],
5653 overlap3 = operand_type_and (i.types[3],
5657 overlap2 = operand_type_and (i.types[2],
5662 switch (t->operands)
5665 if (!operand_type_match (overlap4, i.types[4])
5666 || !operand_type_register_match (i.types[3],
5673 if (!operand_type_match (overlap3, i.types[3])
5674 || ((check_register & 0xa) == 0xa
5675 && !operand_type_register_match (i.types[1],
5679 || ((check_register & 0xc) == 0xc
5680 && !operand_type_register_match (i.types[2],
5687 /* Here we make use of the fact that there are no
5688 reverse match 3 operand instructions. */
5689 if (!operand_type_match (overlap2, i.types[2])
5690 || ((check_register & 5) == 5
5691 && !operand_type_register_match (i.types[0],
5695 || ((check_register & 6) == 6
5696 && !operand_type_register_match (i.types[1],
5704 /* Found either forward/reverse 2, 3 or 4 operand match here:
5705 slip through to break. */
5707 if (!found_cpu_match)
5709 found_reverse_match = 0;
5713 /* Check if vector and VEX operands are valid. */
5714 if (check_VecOperands (t) || VEX_check_operands (t))
5716 specific_error = i.error;
5720 /* We've found a match; break out of loop. */
5724 if (t == current_templates->end)
5726 /* We found no match. */
5727 const char *err_msg;
5728 switch (specific_error ? specific_error : i.error)
5732 case operand_size_mismatch:
5733 err_msg = _("operand size mismatch");
5735 case operand_type_mismatch:
5736 err_msg = _("operand type mismatch");
5738 case register_type_mismatch:
5739 err_msg = _("register type mismatch");
5741 case number_of_operands_mismatch:
5742 err_msg = _("number of operands mismatch");
5744 case invalid_instruction_suffix:
5745 err_msg = _("invalid instruction suffix");
5748 err_msg = _("constant doesn't fit in 4 bits");
5750 case unsupported_with_intel_mnemonic:
5751 err_msg = _("unsupported with Intel mnemonic");
5753 case unsupported_syntax:
5754 err_msg = _("unsupported syntax");
5757 as_bad (_("unsupported instruction `%s'"),
5758 current_templates->start->name);
5760 case invalid_vsib_address:
5761 err_msg = _("invalid VSIB address");
5763 case invalid_vector_register_set:
5764 err_msg = _("mask, index, and destination registers must be distinct");
5766 case unsupported_vector_index_register:
5767 err_msg = _("unsupported vector index register");
5769 case unsupported_broadcast:
5770 err_msg = _("unsupported broadcast");
5772 case broadcast_not_on_src_operand:
5773 err_msg = _("broadcast not on source memory operand");
5775 case broadcast_needed:
5776 err_msg = _("broadcast is needed for operand of such type");
5778 case unsupported_masking:
5779 err_msg = _("unsupported masking");
5781 case mask_not_on_destination:
5782 err_msg = _("mask not on destination operand");
5784 case no_default_mask:
5785 err_msg = _("default mask isn't allowed");
5787 case unsupported_rc_sae:
5788 err_msg = _("unsupported static rounding/sae");
5790 case rc_sae_operand_not_last_imm:
5792 err_msg = _("RC/SAE operand must precede immediate operands");
5794 err_msg = _("RC/SAE operand must follow immediate operands");
5796 case invalid_register_operand:
5797 err_msg = _("invalid register operand");
5800 as_bad (_("%s for `%s'"), err_msg,
5801 current_templates->start->name);
5805 if (!quiet_warnings)
5808 && (i.types[0].bitfield.jumpabsolute
5809 != operand_types[0].bitfield.jumpabsolute))
5811 as_warn (_("indirect %s without `*'"), t->name);
5814 if (t->opcode_modifier.isprefix
5815 && t->opcode_modifier.ignoresize)
5817 /* Warn them that a data or address size prefix doesn't
5818 affect assembly of the next line of code. */
5819 as_warn (_("stand-alone `%s' prefix"), t->name);
5823 /* Copy the template we found. */
5826 if (addr_prefix_disp != -1)
5827 i.tm.operand_types[addr_prefix_disp]
5828 = operand_types[addr_prefix_disp];
5830 if (found_reverse_match)
5832 /* If we found a reverse match we must alter the opcode
5833 direction bit. found_reverse_match holds bits to change
5834 (different for int & float insns). */
5836 i.tm.base_opcode ^= found_reverse_match;
5838 i.tm.operand_types[0] = operand_types[1];
5839 i.tm.operand_types[1] = operand_types[0];
5848 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5849 if (i.tm.operand_types[mem_op].bitfield.esseg)
5851 if (i.seg[0] != NULL && i.seg[0] != &es)
5853 as_bad (_("`%s' operand %d must use `%ses' segment"),
5859 /* There's only ever one segment override allowed per instruction.
5860 This instruction possibly has a legal segment override on the
5861 second operand, so copy the segment to where non-string
5862 instructions store it, allowing common code. */
5863 i.seg[0] = i.seg[1];
5865 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5867 if (i.seg[1] != NULL && i.seg[1] != &es)
5869 as_bad (_("`%s' operand %d must use `%ses' segment"),
5880 process_suffix (void)
5882 /* If matched instruction specifies an explicit instruction mnemonic
5884 if (i.tm.opcode_modifier.size16)
5885 i.suffix = WORD_MNEM_SUFFIX;
5886 else if (i.tm.opcode_modifier.size32)
5887 i.suffix = LONG_MNEM_SUFFIX;
5888 else if (i.tm.opcode_modifier.size64)
5889 i.suffix = QWORD_MNEM_SUFFIX;
5890 else if (i.reg_operands)
5892 /* If there's no instruction mnemonic suffix we try to invent one
5893 based on register operands. */
5896 /* We take i.suffix from the last register operand specified,
5897 Destination register type is more significant than source
5898 register type. crc32 in SSE4.2 prefers source register
5900 if (i.tm.base_opcode == 0xf20f38f1)
5902 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5903 i.suffix = WORD_MNEM_SUFFIX;
5904 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5905 i.suffix = LONG_MNEM_SUFFIX;
5906 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5907 i.suffix = QWORD_MNEM_SUFFIX;
5909 else if (i.tm.base_opcode == 0xf20f38f0)
5911 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5912 i.suffix = BYTE_MNEM_SUFFIX;
5919 if (i.tm.base_opcode == 0xf20f38f1
5920 || i.tm.base_opcode == 0xf20f38f0)
5922 /* We have to know the operand size for crc32. */
5923 as_bad (_("ambiguous memory operand size for `%s`"),
5928 for (op = i.operands; --op >= 0;)
5929 if (!i.tm.operand_types[op].bitfield.inoutportreg
5930 && !i.tm.operand_types[op].bitfield.shiftcount)
5932 if (!i.types[op].bitfield.reg)
5934 if (i.types[op].bitfield.byte)
5935 i.suffix = BYTE_MNEM_SUFFIX;
5936 else if (i.types[op].bitfield.word)
5937 i.suffix = WORD_MNEM_SUFFIX;
5938 else if (i.types[op].bitfield.dword)
5939 i.suffix = LONG_MNEM_SUFFIX;
5940 else if (i.types[op].bitfield.qword)
5941 i.suffix = QWORD_MNEM_SUFFIX;
5948 else if (i.suffix == BYTE_MNEM_SUFFIX)
5951 && i.tm.opcode_modifier.ignoresize
5952 && i.tm.opcode_modifier.no_bsuf)
5954 else if (!check_byte_reg ())
5957 else if (i.suffix == LONG_MNEM_SUFFIX)
5960 && i.tm.opcode_modifier.ignoresize
5961 && i.tm.opcode_modifier.no_lsuf
5962 && !i.tm.opcode_modifier.todword
5963 && !i.tm.opcode_modifier.toqword)
5965 else if (!check_long_reg ())
5968 else if (i.suffix == QWORD_MNEM_SUFFIX)
5971 && i.tm.opcode_modifier.ignoresize
5972 && i.tm.opcode_modifier.no_qsuf
5973 && !i.tm.opcode_modifier.todword
5974 && !i.tm.opcode_modifier.toqword)
5976 else if (!check_qword_reg ())
5979 else if (i.suffix == WORD_MNEM_SUFFIX)
5982 && i.tm.opcode_modifier.ignoresize
5983 && i.tm.opcode_modifier.no_wsuf)
5985 else if (!check_word_reg ())
5988 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5989 /* Do nothing if the instruction is going to ignore the prefix. */
5994 else if (i.tm.opcode_modifier.defaultsize
5996 /* exclude fldenv/frstor/fsave/fstenv */
5997 && i.tm.opcode_modifier.no_ssuf)
5999 i.suffix = stackop_size;
6001 else if (intel_syntax
6003 && (i.tm.operand_types[0].bitfield.jumpabsolute
6004 || i.tm.opcode_modifier.jumpbyte
6005 || i.tm.opcode_modifier.jumpintersegment
6006 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6007 && i.tm.extension_opcode <= 3)))
6012 if (!i.tm.opcode_modifier.no_qsuf)
6014 i.suffix = QWORD_MNEM_SUFFIX;
6019 if (!i.tm.opcode_modifier.no_lsuf)
6020 i.suffix = LONG_MNEM_SUFFIX;
6023 if (!i.tm.opcode_modifier.no_wsuf)
6024 i.suffix = WORD_MNEM_SUFFIX;
6033 if (i.tm.opcode_modifier.w)
6035 as_bad (_("no instruction mnemonic suffix given and "
6036 "no register operands; can't size instruction"));
6042 unsigned int suffixes;
6044 suffixes = !i.tm.opcode_modifier.no_bsuf;
6045 if (!i.tm.opcode_modifier.no_wsuf)
6047 if (!i.tm.opcode_modifier.no_lsuf)
6049 if (!i.tm.opcode_modifier.no_ldsuf)
6051 if (!i.tm.opcode_modifier.no_ssuf)
6053 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6056 /* There are more than suffix matches. */
6057 if (i.tm.opcode_modifier.w
6058 || ((suffixes & (suffixes - 1))
6059 && !i.tm.opcode_modifier.defaultsize
6060 && !i.tm.opcode_modifier.ignoresize))
6062 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6068 /* Change the opcode based on the operand size given by i.suffix. */
6071 /* Size floating point instruction. */
6072 case LONG_MNEM_SUFFIX:
6073 if (i.tm.opcode_modifier.floatmf)
6075 i.tm.base_opcode ^= 4;
6079 case WORD_MNEM_SUFFIX:
6080 case QWORD_MNEM_SUFFIX:
6081 /* It's not a byte, select word/dword operation. */
6082 if (i.tm.opcode_modifier.w)
6084 if (i.tm.opcode_modifier.shortform)
6085 i.tm.base_opcode |= 8;
6087 i.tm.base_opcode |= 1;
6090 case SHORT_MNEM_SUFFIX:
6091 /* Now select between word & dword operations via the operand
6092 size prefix, except for instructions that will ignore this
6094 if (i.reg_operands > 0
6095 && i.types[0].bitfield.reg
6096 && i.tm.opcode_modifier.addrprefixopreg
6097 && (i.tm.opcode_modifier.immext
6098 || i.operands == 1))
6100 /* The address size override prefix changes the size of the
6102 if ((flag_code == CODE_32BIT
6103 && i.op[0].regs->reg_type.bitfield.word)
6104 || (flag_code != CODE_32BIT
6105 && i.op[0].regs->reg_type.bitfield.dword))
6106 if (!add_prefix (ADDR_PREFIX_OPCODE))
6109 else if (i.suffix != QWORD_MNEM_SUFFIX
6110 && !i.tm.opcode_modifier.ignoresize
6111 && !i.tm.opcode_modifier.floatmf
6112 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6113 || (flag_code == CODE_64BIT
6114 && i.tm.opcode_modifier.jumpbyte)))
6116 unsigned int prefix = DATA_PREFIX_OPCODE;
6118 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6119 prefix = ADDR_PREFIX_OPCODE;
6121 if (!add_prefix (prefix))
6125 /* Set mode64 for an operand. */
6126 if (i.suffix == QWORD_MNEM_SUFFIX
6127 && flag_code == CODE_64BIT
6128 && !i.tm.opcode_modifier.norex64
6129 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6131 && ! (i.operands == 2
6132 && i.tm.base_opcode == 0x90
6133 && i.tm.extension_opcode == None
6134 && operand_type_equal (&i.types [0], &acc64)
6135 && operand_type_equal (&i.types [1], &acc64)))
6141 if (i.reg_operands != 0
6143 && i.tm.opcode_modifier.addrprefixopreg
6144 && !i.tm.opcode_modifier.immext)
6146 /* Check invalid register operand when the address size override
6147 prefix changes the size of register operands. */
6149 enum { need_word, need_dword, need_qword } need;
6151 if (flag_code == CODE_32BIT)
6152 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6155 if (i.prefix[ADDR_PREFIX])
6158 need = flag_code == CODE_64BIT ? need_qword : need_word;
6161 for (op = 0; op < i.operands; op++)
6162 if (i.types[op].bitfield.reg
6163 && ((need == need_word
6164 && !i.op[op].regs->reg_type.bitfield.word)
6165 || (need == need_dword
6166 && !i.op[op].regs->reg_type.bitfield.dword)
6167 || (need == need_qword
6168 && !i.op[op].regs->reg_type.bitfield.qword)))
6170 as_bad (_("invalid register operand size for `%s'"),
6180 check_byte_reg (void)
6184 for (op = i.operands; --op >= 0;)
6186 /* Skip non-register operands. */
6187 if (!i.types[op].bitfield.reg)
6190 /* If this is an eight bit register, it's OK. If it's the 16 or
6191 32 bit version of an eight bit register, we will just use the
6192 low portion, and that's OK too. */
6193 if (i.types[op].bitfield.byte)
6196 /* I/O port address operands are OK too. */
6197 if (i.tm.operand_types[op].bitfield.inoutportreg)
6200 /* crc32 doesn't generate this warning. */
6201 if (i.tm.base_opcode == 0xf20f38f0)
6204 if ((i.types[op].bitfield.word
6205 || i.types[op].bitfield.dword
6206 || i.types[op].bitfield.qword)
6207 && i.op[op].regs->reg_num < 4
6208 /* Prohibit these changes in 64bit mode, since the lowering
6209 would be more complicated. */
6210 && flag_code != CODE_64BIT)
6212 #if REGISTER_WARNINGS
6213 if (!quiet_warnings)
6214 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6216 (i.op[op].regs + (i.types[op].bitfield.word
6217 ? REGNAM_AL - REGNAM_AX
6218 : REGNAM_AL - REGNAM_EAX))->reg_name,
6220 i.op[op].regs->reg_name,
6225 /* Any other register is bad. */
6226 if (i.types[op].bitfield.reg
6227 || i.types[op].bitfield.regmmx
6228 || i.types[op].bitfield.regsimd
6229 || i.types[op].bitfield.sreg2
6230 || i.types[op].bitfield.sreg3
6231 || i.types[op].bitfield.control
6232 || i.types[op].bitfield.debug
6233 || i.types[op].bitfield.test)
6235 as_bad (_("`%s%s' not allowed with `%s%c'"),
6237 i.op[op].regs->reg_name,
6247 check_long_reg (void)
6251 for (op = i.operands; --op >= 0;)
6252 /* Skip non-register operands. */
6253 if (!i.types[op].bitfield.reg)
6255 /* Reject eight bit registers, except where the template requires
6256 them. (eg. movzb) */
6257 else if (i.types[op].bitfield.byte
6258 && (i.tm.operand_types[op].bitfield.reg
6259 || i.tm.operand_types[op].bitfield.acc)
6260 && (i.tm.operand_types[op].bitfield.word
6261 || i.tm.operand_types[op].bitfield.dword))
6263 as_bad (_("`%s%s' not allowed with `%s%c'"),
6265 i.op[op].regs->reg_name,
6270 /* Warn if the e prefix on a general reg is missing. */
6271 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6272 && i.types[op].bitfield.word
6273 && (i.tm.operand_types[op].bitfield.reg
6274 || i.tm.operand_types[op].bitfield.acc)
6275 && i.tm.operand_types[op].bitfield.dword)
6277 /* Prohibit these changes in the 64bit mode, since the
6278 lowering is more complicated. */
6279 if (flag_code == CODE_64BIT)
6281 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6282 register_prefix, i.op[op].regs->reg_name,
6286 #if REGISTER_WARNINGS
6287 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6289 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6290 register_prefix, i.op[op].regs->reg_name, i.suffix);
6293 /* Warn if the r prefix on a general reg is present. */
6294 else if (i.types[op].bitfield.qword
6295 && (i.tm.operand_types[op].bitfield.reg
6296 || i.tm.operand_types[op].bitfield.acc)
6297 && i.tm.operand_types[op].bitfield.dword)
6300 && i.tm.opcode_modifier.toqword
6301 && !i.types[0].bitfield.regsimd)
6303 /* Convert to QWORD. We want REX byte. */
6304 i.suffix = QWORD_MNEM_SUFFIX;
6308 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6309 register_prefix, i.op[op].regs->reg_name,
6318 check_qword_reg (void)
6322 for (op = i.operands; --op >= 0; )
6323 /* Skip non-register operands. */
6324 if (!i.types[op].bitfield.reg)
6326 /* Reject eight bit registers, except where the template requires
6327 them. (eg. movzb) */
6328 else if (i.types[op].bitfield.byte
6329 && (i.tm.operand_types[op].bitfield.reg
6330 || i.tm.operand_types[op].bitfield.acc)
6331 && (i.tm.operand_types[op].bitfield.word
6332 || i.tm.operand_types[op].bitfield.dword))
6334 as_bad (_("`%s%s' not allowed with `%s%c'"),
6336 i.op[op].regs->reg_name,
6341 /* Warn if the r prefix on a general reg is missing. */
6342 else if ((i.types[op].bitfield.word
6343 || i.types[op].bitfield.dword)
6344 && (i.tm.operand_types[op].bitfield.reg
6345 || i.tm.operand_types[op].bitfield.acc)
6346 && i.tm.operand_types[op].bitfield.qword)
6348 /* Prohibit these changes in the 64bit mode, since the
6349 lowering is more complicated. */
6351 && i.tm.opcode_modifier.todword
6352 && !i.types[0].bitfield.regsimd)
6354 /* Convert to DWORD. We don't want REX byte. */
6355 i.suffix = LONG_MNEM_SUFFIX;
6359 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6360 register_prefix, i.op[op].regs->reg_name,
6369 check_word_reg (void)
6372 for (op = i.operands; --op >= 0;)
6373 /* Skip non-register operands. */
6374 if (!i.types[op].bitfield.reg)
6376 /* Reject eight bit registers, except where the template requires
6377 them. (eg. movzb) */
6378 else if (i.types[op].bitfield.byte
6379 && (i.tm.operand_types[op].bitfield.reg
6380 || i.tm.operand_types[op].bitfield.acc)
6381 && (i.tm.operand_types[op].bitfield.word
6382 || i.tm.operand_types[op].bitfield.dword))
6384 as_bad (_("`%s%s' not allowed with `%s%c'"),
6386 i.op[op].regs->reg_name,
6391 /* Warn if the e or r prefix on a general reg is present. */
6392 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6393 && (i.types[op].bitfield.dword
6394 || i.types[op].bitfield.qword)
6395 && (i.tm.operand_types[op].bitfield.reg
6396 || i.tm.operand_types[op].bitfield.acc)
6397 && i.tm.operand_types[op].bitfield.word)
6399 /* Prohibit these changes in the 64bit mode, since the
6400 lowering is more complicated. */
6401 if (flag_code == CODE_64BIT)
6403 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6404 register_prefix, i.op[op].regs->reg_name,
6408 #if REGISTER_WARNINGS
6409 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6411 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6412 register_prefix, i.op[op].regs->reg_name, i.suffix);
6419 update_imm (unsigned int j)
6421 i386_operand_type overlap = i.types[j];
6422 if ((overlap.bitfield.imm8
6423 || overlap.bitfield.imm8s
6424 || overlap.bitfield.imm16
6425 || overlap.bitfield.imm32
6426 || overlap.bitfield.imm32s
6427 || overlap.bitfield.imm64)
6428 && !operand_type_equal (&overlap, &imm8)
6429 && !operand_type_equal (&overlap, &imm8s)
6430 && !operand_type_equal (&overlap, &imm16)
6431 && !operand_type_equal (&overlap, &imm32)
6432 && !operand_type_equal (&overlap, &imm32s)
6433 && !operand_type_equal (&overlap, &imm64))
6437 i386_operand_type temp;
6439 operand_type_set (&temp, 0);
6440 if (i.suffix == BYTE_MNEM_SUFFIX)
6442 temp.bitfield.imm8 = overlap.bitfield.imm8;
6443 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6445 else if (i.suffix == WORD_MNEM_SUFFIX)
6446 temp.bitfield.imm16 = overlap.bitfield.imm16;
6447 else if (i.suffix == QWORD_MNEM_SUFFIX)
6449 temp.bitfield.imm64 = overlap.bitfield.imm64;
6450 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6453 temp.bitfield.imm32 = overlap.bitfield.imm32;
6456 else if (operand_type_equal (&overlap, &imm16_32_32s)
6457 || operand_type_equal (&overlap, &imm16_32)
6458 || operand_type_equal (&overlap, &imm16_32s))
6460 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6465 if (!operand_type_equal (&overlap, &imm8)
6466 && !operand_type_equal (&overlap, &imm8s)
6467 && !operand_type_equal (&overlap, &imm16)
6468 && !operand_type_equal (&overlap, &imm32)
6469 && !operand_type_equal (&overlap, &imm32s)
6470 && !operand_type_equal (&overlap, &imm64))
6472 as_bad (_("no instruction mnemonic suffix given; "
6473 "can't determine immediate size"));
6477 i.types[j] = overlap;
6487 /* Update the first 2 immediate operands. */
6488 n = i.operands > 2 ? 2 : i.operands;
6491 for (j = 0; j < n; j++)
6492 if (update_imm (j) == 0)
6495 /* The 3rd operand can't be immediate operand. */
6496 gas_assert (operand_type_check (i.types[2], imm) == 0);
6503 process_operands (void)
6505 /* Default segment register this instruction will use for memory
6506 accesses. 0 means unknown. This is only for optimizing out
6507 unnecessary segment overrides. */
6508 const seg_entry *default_seg = 0;
6510 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6512 unsigned int dupl = i.operands;
6513 unsigned int dest = dupl - 1;
6516 /* The destination must be an xmm register. */
6517 gas_assert (i.reg_operands
6518 && MAX_OPERANDS > dupl
6519 && operand_type_equal (&i.types[dest], ®xmm));
6521 if (i.tm.operand_types[0].bitfield.acc
6522 && i.tm.operand_types[0].bitfield.xmmword)
6524 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6526 /* Keep xmm0 for instructions with VEX prefix and 3
6528 i.tm.operand_types[0].bitfield.acc = 0;
6529 i.tm.operand_types[0].bitfield.regsimd = 1;
6534 /* We remove the first xmm0 and keep the number of
6535 operands unchanged, which in fact duplicates the
6537 for (j = 1; j < i.operands; j++)
6539 i.op[j - 1] = i.op[j];
6540 i.types[j - 1] = i.types[j];
6541 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6545 else if (i.tm.opcode_modifier.implicit1stxmm0)
6547 gas_assert ((MAX_OPERANDS - 1) > dupl
6548 && (i.tm.opcode_modifier.vexsources
6551 /* Add the implicit xmm0 for instructions with VEX prefix
6553 for (j = i.operands; j > 0; j--)
6555 i.op[j] = i.op[j - 1];
6556 i.types[j] = i.types[j - 1];
6557 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6560 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6561 i.types[0] = regxmm;
6562 i.tm.operand_types[0] = regxmm;
6565 i.reg_operands += 2;
6570 i.op[dupl] = i.op[dest];
6571 i.types[dupl] = i.types[dest];
6572 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6581 i.op[dupl] = i.op[dest];
6582 i.types[dupl] = i.types[dest];
6583 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6586 if (i.tm.opcode_modifier.immext)
6589 else if (i.tm.operand_types[0].bitfield.acc
6590 && i.tm.operand_types[0].bitfield.xmmword)
6594 for (j = 1; j < i.operands; j++)
6596 i.op[j - 1] = i.op[j];
6597 i.types[j - 1] = i.types[j];
6599 /* We need to adjust fields in i.tm since they are used by
6600 build_modrm_byte. */
6601 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6608 else if (i.tm.opcode_modifier.implicitquadgroup)
6610 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6612 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6613 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6614 regnum = register_number (i.op[1].regs);
6615 first_reg_in_group = regnum & ~3;
6616 last_reg_in_group = first_reg_in_group + 3;
6617 if (regnum != first_reg_in_group)
6618 as_warn (_("source register `%s%s' implicitly denotes"
6619 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6620 register_prefix, i.op[1].regs->reg_name,
6621 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6622 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6625 else if (i.tm.opcode_modifier.regkludge)
6627 /* The imul $imm, %reg instruction is converted into
6628 imul $imm, %reg, %reg, and the clr %reg instruction
6629 is converted into xor %reg, %reg. */
6631 unsigned int first_reg_op;
6633 if (operand_type_check (i.types[0], reg))
6637 /* Pretend we saw the extra register operand. */
6638 gas_assert (i.reg_operands == 1
6639 && i.op[first_reg_op + 1].regs == 0);
6640 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6641 i.types[first_reg_op + 1] = i.types[first_reg_op];
6646 if (i.tm.opcode_modifier.shortform)
6648 if (i.types[0].bitfield.sreg2
6649 || i.types[0].bitfield.sreg3)
6651 if (i.tm.base_opcode == POP_SEG_SHORT
6652 && i.op[0].regs->reg_num == 1)
6654 as_bad (_("you can't `pop %scs'"), register_prefix);
6657 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6658 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6663 /* The register or float register operand is in operand
6667 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6668 || operand_type_check (i.types[0], reg))
6672 /* Register goes in low 3 bits of opcode. */
6673 i.tm.base_opcode |= i.op[op].regs->reg_num;
6674 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6676 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6678 /* Warn about some common errors, but press on regardless.
6679 The first case can be generated by gcc (<= 2.8.1). */
6680 if (i.operands == 2)
6682 /* Reversed arguments on faddp, fsubp, etc. */
6683 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6684 register_prefix, i.op[!intel_syntax].regs->reg_name,
6685 register_prefix, i.op[intel_syntax].regs->reg_name);
6689 /* Extraneous `l' suffix on fp insn. */
6690 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6691 register_prefix, i.op[0].regs->reg_name);
6696 else if (i.tm.opcode_modifier.modrm)
6698 /* The opcode is completed (modulo i.tm.extension_opcode which
6699 must be put into the modrm byte). Now, we make the modrm and
6700 index base bytes based on all the info we've collected. */
6702 default_seg = build_modrm_byte ();
6704 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6708 else if (i.tm.opcode_modifier.isstring)
6710 /* For the string instructions that allow a segment override
6711 on one of their operands, the default segment is ds. */
6715 if (i.tm.base_opcode == 0x8d /* lea */
6718 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6720 /* If a segment was explicitly specified, and the specified segment
6721 is not the default, use an opcode prefix to select it. If we
6722 never figured out what the default segment is, then default_seg
6723 will be zero at this point, and the specified segment prefix will
6725 if ((i.seg[0]) && (i.seg[0] != default_seg))
6727 if (!add_prefix (i.seg[0]->seg_prefix))
6733 static const seg_entry *
6734 build_modrm_byte (void)
6736 const seg_entry *default_seg = 0;
6737 unsigned int source, dest;
6740 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6743 unsigned int nds, reg_slot;
6746 dest = i.operands - 1;
6749 /* There are 2 kinds of instructions:
6750 1. 5 operands: 4 register operands or 3 register operands
6751 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6752 VexW0 or VexW1. The destination must be either XMM, YMM or
6754 2. 4 operands: 4 register operands or 3 register operands
6755 plus 1 memory operand, with VexXDS. */
6756 gas_assert ((i.reg_operands == 4
6757 || (i.reg_operands == 3 && i.mem_operands == 1))
6758 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6759 && i.tm.opcode_modifier.vexw
6760 && i.tm.operand_types[dest].bitfield.regsimd);
6762 /* If VexW1 is set, the first non-immediate operand is the source and
6763 the second non-immediate one is encoded in the immediate operand. */
6764 if (i.tm.opcode_modifier.vexw == VEXW1)
6766 source = i.imm_operands;
6767 reg_slot = i.imm_operands + 1;
6771 source = i.imm_operands + 1;
6772 reg_slot = i.imm_operands;
6775 if (i.imm_operands == 0)
6777 /* When there is no immediate operand, generate an 8bit
6778 immediate operand to encode the first operand. */
6779 exp = &im_expressions[i.imm_operands++];
6780 i.op[i.operands].imms = exp;
6781 i.types[i.operands] = imm8;
6784 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6785 exp->X_op = O_constant;
6786 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6787 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6791 unsigned int imm_slot;
6793 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6795 if (i.tm.opcode_modifier.immext)
6797 /* When ImmExt is set, the immediate byte is the last
6799 imm_slot = i.operands - 1;
6807 /* Turn on Imm8 so that output_imm will generate it. */
6808 i.types[imm_slot].bitfield.imm8 = 1;
6811 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6812 i.op[imm_slot].imms->X_add_number
6813 |= register_number (i.op[reg_slot].regs) << 4;
6814 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6817 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6818 i.vex.register_specifier = i.op[nds].regs;
6823 /* i.reg_operands MUST be the number of real register operands;
6824 implicit registers do not count. If there are 3 register
6825 operands, it must be a instruction with VexNDS. For a
6826 instruction with VexNDD, the destination register is encoded
6827 in VEX prefix. If there are 4 register operands, it must be
6828 a instruction with VEX prefix and 3 sources. */
6829 if (i.mem_operands == 0
6830 && ((i.reg_operands == 2
6831 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6832 || (i.reg_operands == 3
6833 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6834 || (i.reg_operands == 4 && vex_3_sources)))
6842 /* When there are 3 operands, one of them may be immediate,
6843 which may be the first or the last operand. Otherwise,
6844 the first operand must be shift count register (cl) or it
6845 is an instruction with VexNDS. */
6846 gas_assert (i.imm_operands == 1
6847 || (i.imm_operands == 0
6848 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6849 || i.types[0].bitfield.shiftcount)));
6850 if (operand_type_check (i.types[0], imm)
6851 || i.types[0].bitfield.shiftcount)
6857 /* When there are 4 operands, the first two must be 8bit
6858 immediate operands. The source operand will be the 3rd
6861 For instructions with VexNDS, if the first operand
6862 an imm8, the source operand is the 2nd one. If the last
6863 operand is imm8, the source operand is the first one. */
6864 gas_assert ((i.imm_operands == 2
6865 && i.types[0].bitfield.imm8
6866 && i.types[1].bitfield.imm8)
6867 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6868 && i.imm_operands == 1
6869 && (i.types[0].bitfield.imm8
6870 || i.types[i.operands - 1].bitfield.imm8
6872 if (i.imm_operands == 2)
6876 if (i.types[0].bitfield.imm8)
6883 if (is_evex_encoding (&i.tm))
6885 /* For EVEX instructions, when there are 5 operands, the
6886 first one must be immediate operand. If the second one
6887 is immediate operand, the source operand is the 3th
6888 one. If the last one is immediate operand, the source
6889 operand is the 2nd one. */
6890 gas_assert (i.imm_operands == 2
6891 && i.tm.opcode_modifier.sae
6892 && operand_type_check (i.types[0], imm));
6893 if (operand_type_check (i.types[1], imm))
6895 else if (operand_type_check (i.types[4], imm))
6909 /* RC/SAE operand could be between DEST and SRC. That happens
6910 when one operand is GPR and the other one is XMM/YMM/ZMM
6912 if (i.rounding && i.rounding->operand == (int) dest)
6915 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6917 /* For instructions with VexNDS, the register-only source
6918 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6919 register. It is encoded in VEX prefix. We need to
6920 clear RegMem bit before calling operand_type_equal. */
6922 i386_operand_type op;
6925 /* Check register-only source operand when two source
6926 operands are swapped. */
6927 if (!i.tm.operand_types[source].bitfield.baseindex
6928 && i.tm.operand_types[dest].bitfield.baseindex)
6936 op = i.tm.operand_types[vvvv];
6937 op.bitfield.regmem = 0;
6938 if ((dest + 1) >= i.operands
6939 || ((!op.bitfield.reg
6940 || (!op.bitfield.dword && !op.bitfield.qword))
6941 && !op.bitfield.regsimd
6942 && !operand_type_equal (&op, ®mask)))
6944 i.vex.register_specifier = i.op[vvvv].regs;
6950 /* One of the register operands will be encoded in the i.tm.reg
6951 field, the other in the combined i.tm.mode and i.tm.regmem
6952 fields. If no form of this instruction supports a memory
6953 destination operand, then we assume the source operand may
6954 sometimes be a memory operand and so we need to store the
6955 destination in the i.rm.reg field. */
6956 if (!i.tm.operand_types[dest].bitfield.regmem
6957 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6959 i.rm.reg = i.op[dest].regs->reg_num;
6960 i.rm.regmem = i.op[source].regs->reg_num;
6961 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6963 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6965 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6967 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6972 i.rm.reg = i.op[source].regs->reg_num;
6973 i.rm.regmem = i.op[dest].regs->reg_num;
6974 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6976 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6978 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6980 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6983 if (flag_code != CODE_64BIT && (i.rex & REX_R))
6985 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
6988 add_prefix (LOCK_PREFIX_OPCODE);
6992 { /* If it's not 2 reg operands... */
6997 unsigned int fake_zero_displacement = 0;
7000 for (op = 0; op < i.operands; op++)
7001 if (operand_type_check (i.types[op], anymem))
7003 gas_assert (op < i.operands);
7005 if (i.tm.opcode_modifier.vecsib)
7007 if (i.index_reg->reg_num == RegEiz
7008 || i.index_reg->reg_num == RegRiz)
7011 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7014 i.sib.base = NO_BASE_REGISTER;
7015 i.sib.scale = i.log2_scale_factor;
7016 i.types[op].bitfield.disp8 = 0;
7017 i.types[op].bitfield.disp16 = 0;
7018 i.types[op].bitfield.disp64 = 0;
7019 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7021 /* Must be 32 bit */
7022 i.types[op].bitfield.disp32 = 1;
7023 i.types[op].bitfield.disp32s = 0;
7027 i.types[op].bitfield.disp32 = 0;
7028 i.types[op].bitfield.disp32s = 1;
7031 i.sib.index = i.index_reg->reg_num;
7032 if ((i.index_reg->reg_flags & RegRex) != 0)
7034 if ((i.index_reg->reg_flags & RegVRex) != 0)
7040 if (i.base_reg == 0)
7043 if (!i.disp_operands)
7044 fake_zero_displacement = 1;
7045 if (i.index_reg == 0)
7047 i386_operand_type newdisp;
7049 gas_assert (!i.tm.opcode_modifier.vecsib);
7050 /* Operand is just <disp> */
7051 if (flag_code == CODE_64BIT)
7053 /* 64bit mode overwrites the 32bit absolute
7054 addressing by RIP relative addressing and
7055 absolute addressing is encoded by one of the
7056 redundant SIB forms. */
7057 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7058 i.sib.base = NO_BASE_REGISTER;
7059 i.sib.index = NO_INDEX_REGISTER;
7060 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7062 else if ((flag_code == CODE_16BIT)
7063 ^ (i.prefix[ADDR_PREFIX] != 0))
7065 i.rm.regmem = NO_BASE_REGISTER_16;
7070 i.rm.regmem = NO_BASE_REGISTER;
7073 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7074 i.types[op] = operand_type_or (i.types[op], newdisp);
7076 else if (!i.tm.opcode_modifier.vecsib)
7078 /* !i.base_reg && i.index_reg */
7079 if (i.index_reg->reg_num == RegEiz
7080 || i.index_reg->reg_num == RegRiz)
7081 i.sib.index = NO_INDEX_REGISTER;
7083 i.sib.index = i.index_reg->reg_num;
7084 i.sib.base = NO_BASE_REGISTER;
7085 i.sib.scale = i.log2_scale_factor;
7086 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7087 i.types[op].bitfield.disp8 = 0;
7088 i.types[op].bitfield.disp16 = 0;
7089 i.types[op].bitfield.disp64 = 0;
7090 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7092 /* Must be 32 bit */
7093 i.types[op].bitfield.disp32 = 1;
7094 i.types[op].bitfield.disp32s = 0;
7098 i.types[op].bitfield.disp32 = 0;
7099 i.types[op].bitfield.disp32s = 1;
7101 if ((i.index_reg->reg_flags & RegRex) != 0)
7105 /* RIP addressing for 64bit mode. */
7106 else if (i.base_reg->reg_num == RegRip ||
7107 i.base_reg->reg_num == RegEip)
7109 gas_assert (!i.tm.opcode_modifier.vecsib);
7110 i.rm.regmem = NO_BASE_REGISTER;
7111 i.types[op].bitfield.disp8 = 0;
7112 i.types[op].bitfield.disp16 = 0;
7113 i.types[op].bitfield.disp32 = 0;
7114 i.types[op].bitfield.disp32s = 1;
7115 i.types[op].bitfield.disp64 = 0;
7116 i.flags[op] |= Operand_PCrel;
7117 if (! i.disp_operands)
7118 fake_zero_displacement = 1;
7120 else if (i.base_reg->reg_type.bitfield.word)
7122 gas_assert (!i.tm.opcode_modifier.vecsib);
7123 switch (i.base_reg->reg_num)
7126 if (i.index_reg == 0)
7128 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7129 i.rm.regmem = i.index_reg->reg_num - 6;
7133 if (i.index_reg == 0)
7136 if (operand_type_check (i.types[op], disp) == 0)
7138 /* fake (%bp) into 0(%bp) */
7139 i.types[op].bitfield.disp8 = 1;
7140 fake_zero_displacement = 1;
7143 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7144 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7146 default: /* (%si) -> 4 or (%di) -> 5 */
7147 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7149 i.rm.mode = mode_from_disp_size (i.types[op]);
7151 else /* i.base_reg and 32/64 bit mode */
7153 if (flag_code == CODE_64BIT
7154 && operand_type_check (i.types[op], disp))
7156 i.types[op].bitfield.disp16 = 0;
7157 i.types[op].bitfield.disp64 = 0;
7158 if (i.prefix[ADDR_PREFIX] == 0)
7160 i.types[op].bitfield.disp32 = 0;
7161 i.types[op].bitfield.disp32s = 1;
7165 i.types[op].bitfield.disp32 = 1;
7166 i.types[op].bitfield.disp32s = 0;
7170 if (!i.tm.opcode_modifier.vecsib)
7171 i.rm.regmem = i.base_reg->reg_num;
7172 if ((i.base_reg->reg_flags & RegRex) != 0)
7174 i.sib.base = i.base_reg->reg_num;
7175 /* x86-64 ignores REX prefix bit here to avoid decoder
7177 if (!(i.base_reg->reg_flags & RegRex)
7178 && (i.base_reg->reg_num == EBP_REG_NUM
7179 || i.base_reg->reg_num == ESP_REG_NUM))
7181 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7183 fake_zero_displacement = 1;
7184 i.types[op].bitfield.disp8 = 1;
7186 i.sib.scale = i.log2_scale_factor;
7187 if (i.index_reg == 0)
7189 gas_assert (!i.tm.opcode_modifier.vecsib);
7190 /* <disp>(%esp) becomes two byte modrm with no index
7191 register. We've already stored the code for esp
7192 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7193 Any base register besides %esp will not use the
7194 extra modrm byte. */
7195 i.sib.index = NO_INDEX_REGISTER;
7197 else if (!i.tm.opcode_modifier.vecsib)
7199 if (i.index_reg->reg_num == RegEiz
7200 || i.index_reg->reg_num == RegRiz)
7201 i.sib.index = NO_INDEX_REGISTER;
7203 i.sib.index = i.index_reg->reg_num;
7204 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7205 if ((i.index_reg->reg_flags & RegRex) != 0)
7210 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7211 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7215 if (!fake_zero_displacement
7219 fake_zero_displacement = 1;
7220 if (i.disp_encoding == disp_encoding_8bit)
7221 i.types[op].bitfield.disp8 = 1;
7223 i.types[op].bitfield.disp32 = 1;
7225 i.rm.mode = mode_from_disp_size (i.types[op]);
7229 if (fake_zero_displacement)
7231 /* Fakes a zero displacement assuming that i.types[op]
7232 holds the correct displacement size. */
7235 gas_assert (i.op[op].disps == 0);
7236 exp = &disp_expressions[i.disp_operands++];
7237 i.op[op].disps = exp;
7238 exp->X_op = O_constant;
7239 exp->X_add_number = 0;
7240 exp->X_add_symbol = (symbolS *) 0;
7241 exp->X_op_symbol = (symbolS *) 0;
7249 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7251 if (operand_type_check (i.types[0], imm))
7252 i.vex.register_specifier = NULL;
7255 /* VEX.vvvv encodes one of the sources when the first
7256 operand is not an immediate. */
7257 if (i.tm.opcode_modifier.vexw == VEXW0)
7258 i.vex.register_specifier = i.op[0].regs;
7260 i.vex.register_specifier = i.op[1].regs;
7263 /* Destination is a XMM register encoded in the ModRM.reg
7265 i.rm.reg = i.op[2].regs->reg_num;
7266 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7269 /* ModRM.rm and VEX.B encodes the other source. */
7270 if (!i.mem_operands)
7274 if (i.tm.opcode_modifier.vexw == VEXW0)
7275 i.rm.regmem = i.op[1].regs->reg_num;
7277 i.rm.regmem = i.op[0].regs->reg_num;
7279 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7283 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7285 i.vex.register_specifier = i.op[2].regs;
7286 if (!i.mem_operands)
7289 i.rm.regmem = i.op[1].regs->reg_num;
7290 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7294 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7295 (if any) based on i.tm.extension_opcode. Again, we must be
7296 careful to make sure that segment/control/debug/test/MMX
7297 registers are coded into the i.rm.reg field. */
7298 else if (i.reg_operands)
7301 unsigned int vex_reg = ~0;
7303 for (op = 0; op < i.operands; op++)
7304 if (i.types[op].bitfield.reg
7305 || i.types[op].bitfield.regmmx
7306 || i.types[op].bitfield.regsimd
7307 || i.types[op].bitfield.regbnd
7308 || i.types[op].bitfield.regmask
7309 || i.types[op].bitfield.sreg2
7310 || i.types[op].bitfield.sreg3
7311 || i.types[op].bitfield.control
7312 || i.types[op].bitfield.debug
7313 || i.types[op].bitfield.test)
7318 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7320 /* For instructions with VexNDS, the register-only
7321 source operand is encoded in VEX prefix. */
7322 gas_assert (mem != (unsigned int) ~0);
7327 gas_assert (op < i.operands);
7331 /* Check register-only source operand when two source
7332 operands are swapped. */
7333 if (!i.tm.operand_types[op].bitfield.baseindex
7334 && i.tm.operand_types[op + 1].bitfield.baseindex)
7338 gas_assert (mem == (vex_reg + 1)
7339 && op < i.operands);
7344 gas_assert (vex_reg < i.operands);
7348 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7350 /* For instructions with VexNDD, the register destination
7351 is encoded in VEX prefix. */
7352 if (i.mem_operands == 0)
7354 /* There is no memory operand. */
7355 gas_assert ((op + 2) == i.operands);
7360 /* There are only 2 non-immediate operands. */
7361 gas_assert (op < i.imm_operands + 2
7362 && i.operands == i.imm_operands + 2);
7363 vex_reg = i.imm_operands + 1;
7367 gas_assert (op < i.operands);
7369 if (vex_reg != (unsigned int) ~0)
7371 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7373 if ((!type->bitfield.reg
7374 || (!type->bitfield.dword && !type->bitfield.qword))
7375 && !type->bitfield.regsimd
7376 && !operand_type_equal (type, ®mask))
7379 i.vex.register_specifier = i.op[vex_reg].regs;
7382 /* Don't set OP operand twice. */
7385 /* If there is an extension opcode to put here, the
7386 register number must be put into the regmem field. */
7387 if (i.tm.extension_opcode != None)
7389 i.rm.regmem = i.op[op].regs->reg_num;
7390 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7392 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7397 i.rm.reg = i.op[op].regs->reg_num;
7398 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7400 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7405 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7406 must set it to 3 to indicate this is a register operand
7407 in the regmem field. */
7408 if (!i.mem_operands)
7412 /* Fill in i.rm.reg field with extension opcode (if any). */
7413 if (i.tm.extension_opcode != None)
7414 i.rm.reg = i.tm.extension_opcode;
7420 output_branch (void)
7426 relax_substateT subtype;
7430 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7431 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7434 if (i.prefix[DATA_PREFIX] != 0)
7440 /* Pentium4 branch hints. */
7441 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7442 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7447 if (i.prefix[REX_PREFIX] != 0)
7453 /* BND prefixed jump. */
7454 if (i.prefix[BND_PREFIX] != 0)
7456 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7460 if (i.prefixes != 0 && !intel_syntax)
7461 as_warn (_("skipping prefixes on this instruction"));
7463 /* It's always a symbol; End frag & setup for relax.
7464 Make sure there is enough room in this frag for the largest
7465 instruction we may generate in md_convert_frag. This is 2
7466 bytes for the opcode and room for the prefix and largest
7468 frag_grow (prefix + 2 + 4);
7469 /* Prefix and 1 opcode byte go in fr_fix. */
7470 p = frag_more (prefix + 1);
7471 if (i.prefix[DATA_PREFIX] != 0)
7472 *p++ = DATA_PREFIX_OPCODE;
7473 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7474 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7475 *p++ = i.prefix[SEG_PREFIX];
7476 if (i.prefix[REX_PREFIX] != 0)
7477 *p++ = i.prefix[REX_PREFIX];
7478 *p = i.tm.base_opcode;
7480 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7481 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7482 else if (cpu_arch_flags.bitfield.cpui386)
7483 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7485 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7488 sym = i.op[0].disps->X_add_symbol;
7489 off = i.op[0].disps->X_add_number;
7491 if (i.op[0].disps->X_op != O_constant
7492 && i.op[0].disps->X_op != O_symbol)
7494 /* Handle complex expressions. */
7495 sym = make_expr_symbol (i.op[0].disps);
7499 /* 1 possible extra opcode + 4 byte displacement go in var part.
7500 Pass reloc in fr_var. */
7501 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7505 /* Return TRUE iff PLT32 relocation should be used for branching to
7509 need_plt32_p (symbolS *s)
7511 /* PLT32 relocation is ELF only. */
7515 /* Since there is no need to prepare for PLT branch on x86-64, we
7516 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7517 be used as a marker for 32-bit PC-relative branches. */
7521 /* Weak or undefined symbol need PLT32 relocation. */
7522 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7525 /* Non-global symbol doesn't need PLT32 relocation. */
7526 if (! S_IS_EXTERNAL (s))
7529 /* Other global symbols need PLT32 relocation. NB: Symbol with
7530 non-default visibilities are treated as normal global symbol
7531 so that PLT32 relocation can be used as a marker for 32-bit
7532 PC-relative branches. It is useful for linker relaxation. */
7543 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7545 if (i.tm.opcode_modifier.jumpbyte)
7547 /* This is a loop or jecxz type instruction. */
7549 if (i.prefix[ADDR_PREFIX] != 0)
7551 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7554 /* Pentium4 branch hints. */
7555 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7556 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7558 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7567 if (flag_code == CODE_16BIT)
7570 if (i.prefix[DATA_PREFIX] != 0)
7572 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7582 if (i.prefix[REX_PREFIX] != 0)
7584 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7588 /* BND prefixed jump. */
7589 if (i.prefix[BND_PREFIX] != 0)
7591 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7595 if (i.prefixes != 0 && !intel_syntax)
7596 as_warn (_("skipping prefixes on this instruction"));
7598 p = frag_more (i.tm.opcode_length + size);
7599 switch (i.tm.opcode_length)
7602 *p++ = i.tm.base_opcode >> 8;
7605 *p++ = i.tm.base_opcode;
7611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7613 && jump_reloc == NO_RELOC
7614 && need_plt32_p (i.op[0].disps->X_add_symbol))
7615 jump_reloc = BFD_RELOC_X86_64_PLT32;
7618 jump_reloc = reloc (size, 1, 1, jump_reloc);
7620 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7621 i.op[0].disps, 1, jump_reloc);
7623 /* All jumps handled here are signed, but don't use a signed limit
7624 check for 32 and 16 bit jumps as we want to allow wrap around at
7625 4G and 64k respectively. */
7627 fixP->fx_signed = 1;
7631 output_interseg_jump (void)
7639 if (flag_code == CODE_16BIT)
7643 if (i.prefix[DATA_PREFIX] != 0)
7649 if (i.prefix[REX_PREFIX] != 0)
7659 if (i.prefixes != 0 && !intel_syntax)
7660 as_warn (_("skipping prefixes on this instruction"));
7662 /* 1 opcode; 2 segment; offset */
7663 p = frag_more (prefix + 1 + 2 + size);
7665 if (i.prefix[DATA_PREFIX] != 0)
7666 *p++ = DATA_PREFIX_OPCODE;
7668 if (i.prefix[REX_PREFIX] != 0)
7669 *p++ = i.prefix[REX_PREFIX];
7671 *p++ = i.tm.base_opcode;
7672 if (i.op[1].imms->X_op == O_constant)
7674 offsetT n = i.op[1].imms->X_add_number;
7677 && !fits_in_unsigned_word (n)
7678 && !fits_in_signed_word (n))
7680 as_bad (_("16-bit jump out of range"));
7683 md_number_to_chars (p, n, size);
7686 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7687 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7688 if (i.op[0].imms->X_op != O_constant)
7689 as_bad (_("can't handle non absolute segment in `%s'"),
7691 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7697 fragS *insn_start_frag;
7698 offsetT insn_start_off;
7700 /* Tie dwarf2 debug info to the address at the start of the insn.
7701 We can't do this after the insn has been output as the current
7702 frag may have been closed off. eg. by frag_var. */
7703 dwarf2_emit_insn (0);
7705 insn_start_frag = frag_now;
7706 insn_start_off = frag_now_fix ();
7709 if (i.tm.opcode_modifier.jump)
7711 else if (i.tm.opcode_modifier.jumpbyte
7712 || i.tm.opcode_modifier.jumpdword)
7714 else if (i.tm.opcode_modifier.jumpintersegment)
7715 output_interseg_jump ();
7718 /* Output normal instructions here. */
7722 unsigned int prefix;
7725 && i.tm.base_opcode == 0xfae
7727 && i.imm_operands == 1
7728 && (i.op[0].imms->X_add_number == 0xe8
7729 || i.op[0].imms->X_add_number == 0xf0
7730 || i.op[0].imms->X_add_number == 0xf8))
7732 /* Encode lfence, mfence, and sfence as
7733 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7734 offsetT val = 0x240483f0ULL;
7736 md_number_to_chars (p, val, 5);
7740 /* Some processors fail on LOCK prefix. This options makes
7741 assembler ignore LOCK prefix and serves as a workaround. */
7742 if (omit_lock_prefix)
7744 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7746 i.prefix[LOCK_PREFIX] = 0;
7749 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7750 don't need the explicit prefix. */
7751 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7753 switch (i.tm.opcode_length)
7756 if (i.tm.base_opcode & 0xff000000)
7758 prefix = (i.tm.base_opcode >> 24) & 0xff;
7759 add_prefix (prefix);
7763 if ((i.tm.base_opcode & 0xff0000) != 0)
7765 prefix = (i.tm.base_opcode >> 16) & 0xff;
7766 if (!i.tm.cpu_flags.bitfield.cpupadlock
7767 || prefix != REPE_PREFIX_OPCODE
7768 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7769 add_prefix (prefix);
7775 /* Check for pseudo prefixes. */
7776 as_bad_where (insn_start_frag->fr_file,
7777 insn_start_frag->fr_line,
7778 _("pseudo prefix without instruction"));
7784 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7785 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7786 R_X86_64_GOTTPOFF relocation so that linker can safely
7787 perform IE->LE optimization. */
7788 if (x86_elf_abi == X86_64_X32_ABI
7790 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7791 && i.prefix[REX_PREFIX] == 0)
7792 add_prefix (REX_OPCODE);
7795 /* The prefix bytes. */
7796 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7798 FRAG_APPEND_1_CHAR (*q);
7802 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7807 /* REX byte is encoded in VEX prefix. */
7811 FRAG_APPEND_1_CHAR (*q);
7814 /* There should be no other prefixes for instructions
7819 /* For EVEX instructions i.vrex should become 0 after
7820 build_evex_prefix. For VEX instructions upper 16 registers
7821 aren't available, so VREX should be 0. */
7824 /* Now the VEX prefix. */
7825 p = frag_more (i.vex.length);
7826 for (j = 0; j < i.vex.length; j++)
7827 p[j] = i.vex.bytes[j];
7830 /* Now the opcode; be careful about word order here! */
7831 if (i.tm.opcode_length == 1)
7833 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7837 switch (i.tm.opcode_length)
7841 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7842 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7846 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7856 /* Put out high byte first: can't use md_number_to_chars! */
7857 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7858 *p = i.tm.base_opcode & 0xff;
7861 /* Now the modrm byte and sib byte (if present). */
7862 if (i.tm.opcode_modifier.modrm)
7864 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7867 /* If i.rm.regmem == ESP (4)
7868 && i.rm.mode != (Register mode)
7870 ==> need second modrm byte. */
7871 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7873 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7874 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7876 | i.sib.scale << 6));
7879 if (i.disp_operands)
7880 output_disp (insn_start_frag, insn_start_off);
7883 output_imm (insn_start_frag, insn_start_off);
7889 pi ("" /*line*/, &i);
7891 #endif /* DEBUG386 */
7894 /* Return the size of the displacement operand N. */
7897 disp_size (unsigned int n)
7901 if (i.types[n].bitfield.disp64)
7903 else if (i.types[n].bitfield.disp8)
7905 else if (i.types[n].bitfield.disp16)
7910 /* Return the size of the immediate operand N. */
7913 imm_size (unsigned int n)
7916 if (i.types[n].bitfield.imm64)
7918 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7920 else if (i.types[n].bitfield.imm16)
7926 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7931 for (n = 0; n < i.operands; n++)
7933 if (operand_type_check (i.types[n], disp))
7935 if (i.op[n].disps->X_op == O_constant)
7937 int size = disp_size (n);
7938 offsetT val = i.op[n].disps->X_add_number;
7940 val = offset_in_range (val >> i.memshift, size);
7941 p = frag_more (size);
7942 md_number_to_chars (p, val, size);
7946 enum bfd_reloc_code_real reloc_type;
7947 int size = disp_size (n);
7948 int sign = i.types[n].bitfield.disp32s;
7949 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7952 /* We can't have 8 bit displacement here. */
7953 gas_assert (!i.types[n].bitfield.disp8);
7955 /* The PC relative address is computed relative
7956 to the instruction boundary, so in case immediate
7957 fields follows, we need to adjust the value. */
7958 if (pcrel && i.imm_operands)
7963 for (n1 = 0; n1 < i.operands; n1++)
7964 if (operand_type_check (i.types[n1], imm))
7966 /* Only one immediate is allowed for PC
7967 relative address. */
7968 gas_assert (sz == 0);
7970 i.op[n].disps->X_add_number -= sz;
7972 /* We should find the immediate. */
7973 gas_assert (sz != 0);
7976 p = frag_more (size);
7977 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7979 && GOT_symbol == i.op[n].disps->X_add_symbol
7980 && (((reloc_type == BFD_RELOC_32
7981 || reloc_type == BFD_RELOC_X86_64_32S
7982 || (reloc_type == BFD_RELOC_64
7984 && (i.op[n].disps->X_op == O_symbol
7985 || (i.op[n].disps->X_op == O_add
7986 && ((symbol_get_value_expression
7987 (i.op[n].disps->X_op_symbol)->X_op)
7989 || reloc_type == BFD_RELOC_32_PCREL))
7993 if (insn_start_frag == frag_now)
7994 add = (p - frag_now->fr_literal) - insn_start_off;
7999 add = insn_start_frag->fr_fix - insn_start_off;
8000 for (fr = insn_start_frag->fr_next;
8001 fr && fr != frag_now; fr = fr->fr_next)
8003 add += p - frag_now->fr_literal;
8008 reloc_type = BFD_RELOC_386_GOTPC;
8009 i.op[n].imms->X_add_number += add;
8011 else if (reloc_type == BFD_RELOC_64)
8012 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8014 /* Don't do the adjustment for x86-64, as there
8015 the pcrel addressing is relative to the _next_
8016 insn, and that is taken care of in other code. */
8017 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8019 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8020 size, i.op[n].disps, pcrel,
8022 /* Check for "call/jmp *mem", "mov mem, %reg",
8023 "test %reg, mem" and "binop mem, %reg" where binop
8024 is one of adc, add, and, cmp, or, sbb, sub, xor
8025 instructions. Always generate R_386_GOT32X for
8026 "sym*GOT" operand in 32-bit mode. */
8027 if ((generate_relax_relocations
8030 && i.rm.regmem == 5))
8032 || (i.rm.mode == 0 && i.rm.regmem == 5))
8033 && ((i.operands == 1
8034 && i.tm.base_opcode == 0xff
8035 && (i.rm.reg == 2 || i.rm.reg == 4))
8037 && (i.tm.base_opcode == 0x8b
8038 || i.tm.base_opcode == 0x85
8039 || (i.tm.base_opcode & 0xc7) == 0x03))))
8043 fixP->fx_tcbit = i.rex != 0;
8045 && (i.base_reg->reg_num == RegRip
8046 || i.base_reg->reg_num == RegEip))
8047 fixP->fx_tcbit2 = 1;
8050 fixP->fx_tcbit2 = 1;
8058 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8063 for (n = 0; n < i.operands; n++)
8065 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8066 if (i.rounding && (int) n == i.rounding->operand)
8069 if (operand_type_check (i.types[n], imm))
8071 if (i.op[n].imms->X_op == O_constant)
8073 int size = imm_size (n);
8076 val = offset_in_range (i.op[n].imms->X_add_number,
8078 p = frag_more (size);
8079 md_number_to_chars (p, val, size);
8083 /* Not absolute_section.
8084 Need a 32-bit fixup (don't support 8bit
8085 non-absolute imms). Try to support other
8087 enum bfd_reloc_code_real reloc_type;
8088 int size = imm_size (n);
8091 if (i.types[n].bitfield.imm32s
8092 && (i.suffix == QWORD_MNEM_SUFFIX
8093 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8098 p = frag_more (size);
8099 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8101 /* This is tough to explain. We end up with this one if we
8102 * have operands that look like
8103 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8104 * obtain the absolute address of the GOT, and it is strongly
8105 * preferable from a performance point of view to avoid using
8106 * a runtime relocation for this. The actual sequence of
8107 * instructions often look something like:
8112 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8114 * The call and pop essentially return the absolute address
8115 * of the label .L66 and store it in %ebx. The linker itself
8116 * will ultimately change the first operand of the addl so
8117 * that %ebx points to the GOT, but to keep things simple, the
8118 * .o file must have this operand set so that it generates not
8119 * the absolute address of .L66, but the absolute address of
8120 * itself. This allows the linker itself simply treat a GOTPC
8121 * relocation as asking for a pcrel offset to the GOT to be
8122 * added in, and the addend of the relocation is stored in the
8123 * operand field for the instruction itself.
8125 * Our job here is to fix the operand so that it would add
8126 * the correct offset so that %ebx would point to itself. The
8127 * thing that is tricky is that .-.L66 will point to the
8128 * beginning of the instruction, so we need to further modify
8129 * the operand so that it will point to itself. There are
8130 * other cases where you have something like:
8132 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8134 * and here no correction would be required. Internally in
8135 * the assembler we treat operands of this form as not being
8136 * pcrel since the '.' is explicitly mentioned, and I wonder
8137 * whether it would simplify matters to do it this way. Who
8138 * knows. In earlier versions of the PIC patches, the
8139 * pcrel_adjust field was used to store the correction, but
8140 * since the expression is not pcrel, I felt it would be
8141 * confusing to do it this way. */
8143 if ((reloc_type == BFD_RELOC_32
8144 || reloc_type == BFD_RELOC_X86_64_32S
8145 || reloc_type == BFD_RELOC_64)
8147 && GOT_symbol == i.op[n].imms->X_add_symbol
8148 && (i.op[n].imms->X_op == O_symbol
8149 || (i.op[n].imms->X_op == O_add
8150 && ((symbol_get_value_expression
8151 (i.op[n].imms->X_op_symbol)->X_op)
8156 if (insn_start_frag == frag_now)
8157 add = (p - frag_now->fr_literal) - insn_start_off;
8162 add = insn_start_frag->fr_fix - insn_start_off;
8163 for (fr = insn_start_frag->fr_next;
8164 fr && fr != frag_now; fr = fr->fr_next)
8166 add += p - frag_now->fr_literal;
8170 reloc_type = BFD_RELOC_386_GOTPC;
8172 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8174 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8175 i.op[n].imms->X_add_number += add;
8177 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8178 i.op[n].imms, 0, reloc_type);
8184 /* x86_cons_fix_new is called via the expression parsing code when a
8185 reloc is needed. We use this hook to get the correct .got reloc. */
8186 static int cons_sign = -1;
8189 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8190 expressionS *exp, bfd_reloc_code_real_type r)
8192 r = reloc (len, 0, cons_sign, r);
8195 if (exp->X_op == O_secrel)
8197 exp->X_op = O_symbol;
8198 r = BFD_RELOC_32_SECREL;
8202 fix_new_exp (frag, off, len, exp, 0, r);
8205 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8206 purpose of the `.dc.a' internal pseudo-op. */
8209 x86_address_bytes (void)
8211 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8213 return stdoutput->arch_info->bits_per_address / 8;
8216 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8218 # define lex_got(reloc, adjust, types) NULL
8220 /* Parse operands of the form
8221 <symbol>@GOTOFF+<nnn>
8222 and similar .plt or .got references.
8224 If we find one, set up the correct relocation in RELOC and copy the
8225 input string, minus the `@GOTOFF' into a malloc'd buffer for
8226 parsing by the calling routine. Return this buffer, and if ADJUST
8227 is non-null set it to the length of the string we removed from the
8228 input line. Otherwise return NULL. */
8230 lex_got (enum bfd_reloc_code_real *rel,
8232 i386_operand_type *types)
8234 /* Some of the relocations depend on the size of what field is to
8235 be relocated. But in our callers i386_immediate and i386_displacement
8236 we don't yet know the operand size (this will be set by insn
8237 matching). Hence we record the word32 relocation here,
8238 and adjust the reloc according to the real size in reloc(). */
8239 static const struct {
8242 const enum bfd_reloc_code_real rel[2];
8243 const i386_operand_type types64;
8245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8246 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8248 OPERAND_TYPE_IMM32_64 },
8250 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8251 BFD_RELOC_X86_64_PLTOFF64 },
8252 OPERAND_TYPE_IMM64 },
8253 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8254 BFD_RELOC_X86_64_PLT32 },
8255 OPERAND_TYPE_IMM32_32S_DISP32 },
8256 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8257 BFD_RELOC_X86_64_GOTPLT64 },
8258 OPERAND_TYPE_IMM64_DISP64 },
8259 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8260 BFD_RELOC_X86_64_GOTOFF64 },
8261 OPERAND_TYPE_IMM64_DISP64 },
8262 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8263 BFD_RELOC_X86_64_GOTPCREL },
8264 OPERAND_TYPE_IMM32_32S_DISP32 },
8265 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8266 BFD_RELOC_X86_64_TLSGD },
8267 OPERAND_TYPE_IMM32_32S_DISP32 },
8268 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8269 _dummy_first_bfd_reloc_code_real },
8270 OPERAND_TYPE_NONE },
8271 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8272 BFD_RELOC_X86_64_TLSLD },
8273 OPERAND_TYPE_IMM32_32S_DISP32 },
8274 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8275 BFD_RELOC_X86_64_GOTTPOFF },
8276 OPERAND_TYPE_IMM32_32S_DISP32 },
8277 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8278 BFD_RELOC_X86_64_TPOFF32 },
8279 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8280 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8281 _dummy_first_bfd_reloc_code_real },
8282 OPERAND_TYPE_NONE },
8283 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8284 BFD_RELOC_X86_64_DTPOFF32 },
8285 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8286 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8287 _dummy_first_bfd_reloc_code_real },
8288 OPERAND_TYPE_NONE },
8289 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8290 _dummy_first_bfd_reloc_code_real },
8291 OPERAND_TYPE_NONE },
8292 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8293 BFD_RELOC_X86_64_GOT32 },
8294 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8295 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8296 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8297 OPERAND_TYPE_IMM32_32S_DISP32 },
8298 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8299 BFD_RELOC_X86_64_TLSDESC_CALL },
8300 OPERAND_TYPE_IMM32_32S_DISP32 },
8305 #if defined (OBJ_MAYBE_ELF)
8310 for (cp = input_line_pointer; *cp != '@'; cp++)
8311 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8314 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8316 int len = gotrel[j].len;
8317 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8319 if (gotrel[j].rel[object_64bit] != 0)
8322 char *tmpbuf, *past_reloc;
8324 *rel = gotrel[j].rel[object_64bit];
8328 if (flag_code != CODE_64BIT)
8330 types->bitfield.imm32 = 1;
8331 types->bitfield.disp32 = 1;
8334 *types = gotrel[j].types64;
8337 if (j != 0 && GOT_symbol == NULL)
8338 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8340 /* The length of the first part of our input line. */
8341 first = cp - input_line_pointer;
8343 /* The second part goes from after the reloc token until
8344 (and including) an end_of_line char or comma. */
8345 past_reloc = cp + 1 + len;
8347 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8349 second = cp + 1 - past_reloc;
8351 /* Allocate and copy string. The trailing NUL shouldn't
8352 be necessary, but be safe. */
8353 tmpbuf = XNEWVEC (char, first + second + 2);
8354 memcpy (tmpbuf, input_line_pointer, first);
8355 if (second != 0 && *past_reloc != ' ')
8356 /* Replace the relocation token with ' ', so that
8357 errors like foo@GOTOFF1 will be detected. */
8358 tmpbuf[first++] = ' ';
8360 /* Increment length by 1 if the relocation token is
8365 memcpy (tmpbuf + first, past_reloc, second);
8366 tmpbuf[first + second] = '\0';
8370 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8371 gotrel[j].str, 1 << (5 + object_64bit));
8376 /* Might be a symbol version string. Don't as_bad here. */
8385 /* Parse operands of the form
8386 <symbol>@SECREL32+<nnn>
8388 If we find one, set up the correct relocation in RELOC and copy the
8389 input string, minus the `@SECREL32' into a malloc'd buffer for
8390 parsing by the calling routine. Return this buffer, and if ADJUST
8391 is non-null set it to the length of the string we removed from the
8392 input line. Otherwise return NULL.
8394 This function is copied from the ELF version above adjusted for PE targets. */
8397 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8398 int *adjust ATTRIBUTE_UNUSED,
8399 i386_operand_type *types)
8405 const enum bfd_reloc_code_real rel[2];
8406 const i386_operand_type types64;
8410 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8411 BFD_RELOC_32_SECREL },
8412 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8418 for (cp = input_line_pointer; *cp != '@'; cp++)
8419 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8422 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8424 int len = gotrel[j].len;
8426 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8428 if (gotrel[j].rel[object_64bit] != 0)
8431 char *tmpbuf, *past_reloc;
8433 *rel = gotrel[j].rel[object_64bit];
8439 if (flag_code != CODE_64BIT)
8441 types->bitfield.imm32 = 1;
8442 types->bitfield.disp32 = 1;
8445 *types = gotrel[j].types64;
8448 /* The length of the first part of our input line. */
8449 first = cp - input_line_pointer;
8451 /* The second part goes from after the reloc token until
8452 (and including) an end_of_line char or comma. */
8453 past_reloc = cp + 1 + len;
8455 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8457 second = cp + 1 - past_reloc;
8459 /* Allocate and copy string. The trailing NUL shouldn't
8460 be necessary, but be safe. */
8461 tmpbuf = XNEWVEC (char, first + second + 2);
8462 memcpy (tmpbuf, input_line_pointer, first);
8463 if (second != 0 && *past_reloc != ' ')
8464 /* Replace the relocation token with ' ', so that
8465 errors like foo@SECLREL321 will be detected. */
8466 tmpbuf[first++] = ' ';
8467 memcpy (tmpbuf + first, past_reloc, second);
8468 tmpbuf[first + second] = '\0';
8472 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8473 gotrel[j].str, 1 << (5 + object_64bit));
8478 /* Might be a symbol version string. Don't as_bad here. */
8484 bfd_reloc_code_real_type
8485 x86_cons (expressionS *exp, int size)
8487 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8489 intel_syntax = -intel_syntax;
8492 if (size == 4 || (object_64bit && size == 8))
8494 /* Handle @GOTOFF and the like in an expression. */
8496 char *gotfree_input_line;
8499 save = input_line_pointer;
8500 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8501 if (gotfree_input_line)
8502 input_line_pointer = gotfree_input_line;
8506 if (gotfree_input_line)
8508 /* expression () has merrily parsed up to the end of line,
8509 or a comma - in the wrong buffer. Transfer how far
8510 input_line_pointer has moved to the right buffer. */
8511 input_line_pointer = (save
8512 + (input_line_pointer - gotfree_input_line)
8514 free (gotfree_input_line);
8515 if (exp->X_op == O_constant
8516 || exp->X_op == O_absent
8517 || exp->X_op == O_illegal
8518 || exp->X_op == O_register
8519 || exp->X_op == O_big)
8521 char c = *input_line_pointer;
8522 *input_line_pointer = 0;
8523 as_bad (_("missing or invalid expression `%s'"), save);
8524 *input_line_pointer = c;
8531 intel_syntax = -intel_syntax;
8534 i386_intel_simplify (exp);
8540 signed_cons (int size)
8542 if (flag_code == CODE_64BIT)
8550 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8557 if (exp.X_op == O_symbol)
8558 exp.X_op = O_secrel;
8560 emit_expr (&exp, 4);
8562 while (*input_line_pointer++ == ',');
8564 input_line_pointer--;
8565 demand_empty_rest_of_line ();
8569 /* Handle Vector operations. */
8572 check_VecOperations (char *op_string, char *op_end)
8574 const reg_entry *mask;
8579 && (op_end == NULL || op_string < op_end))
8582 if (*op_string == '{')
8586 /* Check broadcasts. */
8587 if (strncmp (op_string, "1to", 3) == 0)
8592 goto duplicated_vec_op;
8595 if (*op_string == '8')
8597 else if (*op_string == '4')
8599 else if (*op_string == '2')
8601 else if (*op_string == '1'
8602 && *(op_string+1) == '6')
8609 as_bad (_("Unsupported broadcast: `%s'"), saved);
8614 broadcast_op.type = bcst_type;
8615 broadcast_op.operand = this_operand;
8616 i.broadcast = &broadcast_op;
8618 /* Check masking operation. */
8619 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8621 /* k0 can't be used for write mask. */
8622 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8624 as_bad (_("`%s%s' can't be used for write mask"),
8625 register_prefix, mask->reg_name);
8631 mask_op.mask = mask;
8632 mask_op.zeroing = 0;
8633 mask_op.operand = this_operand;
8639 goto duplicated_vec_op;
8641 i.mask->mask = mask;
8643 /* Only "{z}" is allowed here. No need to check
8644 zeroing mask explicitly. */
8645 if (i.mask->operand != this_operand)
8647 as_bad (_("invalid write mask `%s'"), saved);
8654 /* Check zeroing-flag for masking operation. */
8655 else if (*op_string == 'z')
8659 mask_op.mask = NULL;
8660 mask_op.zeroing = 1;
8661 mask_op.operand = this_operand;
8666 if (i.mask->zeroing)
8669 as_bad (_("duplicated `%s'"), saved);
8673 i.mask->zeroing = 1;
8675 /* Only "{%k}" is allowed here. No need to check mask
8676 register explicitly. */
8677 if (i.mask->operand != this_operand)
8679 as_bad (_("invalid zeroing-masking `%s'"),
8688 goto unknown_vec_op;
8690 if (*op_string != '}')
8692 as_bad (_("missing `}' in `%s'"), saved);
8697 /* Strip whitespace since the addition of pseudo prefixes
8698 changed how the scrubber treats '{'. */
8699 if (is_space_char (*op_string))
8705 /* We don't know this one. */
8706 as_bad (_("unknown vector operation: `%s'"), saved);
8710 if (i.mask && i.mask->zeroing && !i.mask->mask)
8712 as_bad (_("zeroing-masking only allowed with write mask"));
8720 i386_immediate (char *imm_start)
8722 char *save_input_line_pointer;
8723 char *gotfree_input_line;
8726 i386_operand_type types;
8728 operand_type_set (&types, ~0);
8730 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8732 as_bad (_("at most %d immediate operands are allowed"),
8733 MAX_IMMEDIATE_OPERANDS);
8737 exp = &im_expressions[i.imm_operands++];
8738 i.op[this_operand].imms = exp;
8740 if (is_space_char (*imm_start))
8743 save_input_line_pointer = input_line_pointer;
8744 input_line_pointer = imm_start;
8746 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8747 if (gotfree_input_line)
8748 input_line_pointer = gotfree_input_line;
8750 exp_seg = expression (exp);
8754 /* Handle vector operations. */
8755 if (*input_line_pointer == '{')
8757 input_line_pointer = check_VecOperations (input_line_pointer,
8759 if (input_line_pointer == NULL)
8763 if (*input_line_pointer)
8764 as_bad (_("junk `%s' after expression"), input_line_pointer);
8766 input_line_pointer = save_input_line_pointer;
8767 if (gotfree_input_line)
8769 free (gotfree_input_line);
8771 if (exp->X_op == O_constant || exp->X_op == O_register)
8772 exp->X_op = O_illegal;
8775 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8779 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8780 i386_operand_type types, const char *imm_start)
8782 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8785 as_bad (_("missing or invalid immediate expression `%s'"),
8789 else if (exp->X_op == O_constant)
8791 /* Size it properly later. */
8792 i.types[this_operand].bitfield.imm64 = 1;
8793 /* If not 64bit, sign extend val. */
8794 if (flag_code != CODE_64BIT
8795 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8797 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8799 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8800 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8801 && exp_seg != absolute_section
8802 && exp_seg != text_section
8803 && exp_seg != data_section
8804 && exp_seg != bss_section
8805 && exp_seg != undefined_section
8806 && !bfd_is_com_section (exp_seg))
8808 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8812 else if (!intel_syntax && exp_seg == reg_section)
8815 as_bad (_("illegal immediate register operand %s"), imm_start);
8820 /* This is an address. The size of the address will be
8821 determined later, depending on destination register,
8822 suffix, or the default for the section. */
8823 i.types[this_operand].bitfield.imm8 = 1;
8824 i.types[this_operand].bitfield.imm16 = 1;
8825 i.types[this_operand].bitfield.imm32 = 1;
8826 i.types[this_operand].bitfield.imm32s = 1;
8827 i.types[this_operand].bitfield.imm64 = 1;
8828 i.types[this_operand] = operand_type_and (i.types[this_operand],
8836 i386_scale (char *scale)
8839 char *save = input_line_pointer;
8841 input_line_pointer = scale;
8842 val = get_absolute_expression ();
8847 i.log2_scale_factor = 0;
8850 i.log2_scale_factor = 1;
8853 i.log2_scale_factor = 2;
8856 i.log2_scale_factor = 3;
8860 char sep = *input_line_pointer;
8862 *input_line_pointer = '\0';
8863 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8865 *input_line_pointer = sep;
8866 input_line_pointer = save;
8870 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8872 as_warn (_("scale factor of %d without an index register"),
8873 1 << i.log2_scale_factor);
8874 i.log2_scale_factor = 0;
8876 scale = input_line_pointer;
8877 input_line_pointer = save;
8882 i386_displacement (char *disp_start, char *disp_end)
8886 char *save_input_line_pointer;
8887 char *gotfree_input_line;
8889 i386_operand_type bigdisp, types = anydisp;
8892 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8894 as_bad (_("at most %d displacement operands are allowed"),
8895 MAX_MEMORY_OPERANDS);
8899 operand_type_set (&bigdisp, 0);
8900 if ((i.types[this_operand].bitfield.jumpabsolute)
8901 || (!current_templates->start->opcode_modifier.jump
8902 && !current_templates->start->opcode_modifier.jumpdword))
8904 bigdisp.bitfield.disp32 = 1;
8905 override = (i.prefix[ADDR_PREFIX] != 0);
8906 if (flag_code == CODE_64BIT)
8910 bigdisp.bitfield.disp32s = 1;
8911 bigdisp.bitfield.disp64 = 1;
8914 else if ((flag_code == CODE_16BIT) ^ override)
8916 bigdisp.bitfield.disp32 = 0;
8917 bigdisp.bitfield.disp16 = 1;
8922 /* For PC-relative branches, the width of the displacement
8923 is dependent upon data size, not address size. */
8924 override = (i.prefix[DATA_PREFIX] != 0);
8925 if (flag_code == CODE_64BIT)
8927 if (override || i.suffix == WORD_MNEM_SUFFIX)
8928 bigdisp.bitfield.disp16 = 1;
8931 bigdisp.bitfield.disp32 = 1;
8932 bigdisp.bitfield.disp32s = 1;
8938 override = (i.suffix == (flag_code != CODE_16BIT
8940 : LONG_MNEM_SUFFIX));
8941 bigdisp.bitfield.disp32 = 1;
8942 if ((flag_code == CODE_16BIT) ^ override)
8944 bigdisp.bitfield.disp32 = 0;
8945 bigdisp.bitfield.disp16 = 1;
8949 i.types[this_operand] = operand_type_or (i.types[this_operand],
8952 exp = &disp_expressions[i.disp_operands];
8953 i.op[this_operand].disps = exp;
8955 save_input_line_pointer = input_line_pointer;
8956 input_line_pointer = disp_start;
8957 END_STRING_AND_SAVE (disp_end);
8959 #ifndef GCC_ASM_O_HACK
8960 #define GCC_ASM_O_HACK 0
8963 END_STRING_AND_SAVE (disp_end + 1);
8964 if (i.types[this_operand].bitfield.baseIndex
8965 && displacement_string_end[-1] == '+')
8967 /* This hack is to avoid a warning when using the "o"
8968 constraint within gcc asm statements.
8971 #define _set_tssldt_desc(n,addr,limit,type) \
8972 __asm__ __volatile__ ( \
8974 "movw %w1,2+%0\n\t" \
8976 "movb %b1,4+%0\n\t" \
8977 "movb %4,5+%0\n\t" \
8978 "movb $0,6+%0\n\t" \
8979 "movb %h1,7+%0\n\t" \
8981 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8983 This works great except that the output assembler ends
8984 up looking a bit weird if it turns out that there is
8985 no offset. You end up producing code that looks like:
8998 So here we provide the missing zero. */
9000 *displacement_string_end = '0';
9003 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9004 if (gotfree_input_line)
9005 input_line_pointer = gotfree_input_line;
9007 exp_seg = expression (exp);
9010 if (*input_line_pointer)
9011 as_bad (_("junk `%s' after expression"), input_line_pointer);
9013 RESTORE_END_STRING (disp_end + 1);
9015 input_line_pointer = save_input_line_pointer;
9016 if (gotfree_input_line)
9018 free (gotfree_input_line);
9020 if (exp->X_op == O_constant || exp->X_op == O_register)
9021 exp->X_op = O_illegal;
9024 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9026 RESTORE_END_STRING (disp_end);
9032 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9033 i386_operand_type types, const char *disp_start)
9035 i386_operand_type bigdisp;
9038 /* We do this to make sure that the section symbol is in
9039 the symbol table. We will ultimately change the relocation
9040 to be relative to the beginning of the section. */
9041 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9042 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9043 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9045 if (exp->X_op != O_symbol)
9048 if (S_IS_LOCAL (exp->X_add_symbol)
9049 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9050 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9051 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9052 exp->X_op = O_subtract;
9053 exp->X_op_symbol = GOT_symbol;
9054 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9055 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9056 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9057 i.reloc[this_operand] = BFD_RELOC_64;
9059 i.reloc[this_operand] = BFD_RELOC_32;
9062 else if (exp->X_op == O_absent
9063 || exp->X_op == O_illegal
9064 || exp->X_op == O_big)
9067 as_bad (_("missing or invalid displacement expression `%s'"),
9072 else if (flag_code == CODE_64BIT
9073 && !i.prefix[ADDR_PREFIX]
9074 && exp->X_op == O_constant)
9076 /* Since displacement is signed extended to 64bit, don't allow
9077 disp32 and turn off disp32s if they are out of range. */
9078 i.types[this_operand].bitfield.disp32 = 0;
9079 if (!fits_in_signed_long (exp->X_add_number))
9081 i.types[this_operand].bitfield.disp32s = 0;
9082 if (i.types[this_operand].bitfield.baseindex)
9084 as_bad (_("0x%lx out range of signed 32bit displacement"),
9085 (long) exp->X_add_number);
9091 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9092 else if (exp->X_op != O_constant
9093 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9094 && exp_seg != absolute_section
9095 && exp_seg != text_section
9096 && exp_seg != data_section
9097 && exp_seg != bss_section
9098 && exp_seg != undefined_section
9099 && !bfd_is_com_section (exp_seg))
9101 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9106 /* Check if this is a displacement only operand. */
9107 bigdisp = i.types[this_operand];
9108 bigdisp.bitfield.disp8 = 0;
9109 bigdisp.bitfield.disp16 = 0;
9110 bigdisp.bitfield.disp32 = 0;
9111 bigdisp.bitfield.disp32s = 0;
9112 bigdisp.bitfield.disp64 = 0;
9113 if (operand_type_all_zero (&bigdisp))
9114 i.types[this_operand] = operand_type_and (i.types[this_operand],
9120 /* Return the active addressing mode, taking address override and
9121 registers forming the address into consideration. Update the
9122 address override prefix if necessary. */
9124 static enum flag_code
9125 i386_addressing_mode (void)
9127 enum flag_code addr_mode;
9129 if (i.prefix[ADDR_PREFIX])
9130 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9133 addr_mode = flag_code;
9135 #if INFER_ADDR_PREFIX
9136 if (i.mem_operands == 0)
9138 /* Infer address prefix from the first memory operand. */
9139 const reg_entry *addr_reg = i.base_reg;
9141 if (addr_reg == NULL)
9142 addr_reg = i.index_reg;
9146 if (addr_reg->reg_num == RegEip
9147 || addr_reg->reg_num == RegEiz
9148 || addr_reg->reg_type.bitfield.dword)
9149 addr_mode = CODE_32BIT;
9150 else if (flag_code != CODE_64BIT
9151 && addr_reg->reg_type.bitfield.word)
9152 addr_mode = CODE_16BIT;
9154 if (addr_mode != flag_code)
9156 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9158 /* Change the size of any displacement too. At most one
9159 of Disp16 or Disp32 is set.
9160 FIXME. There doesn't seem to be any real need for
9161 separate Disp16 and Disp32 flags. The same goes for
9162 Imm16 and Imm32. Removing them would probably clean
9163 up the code quite a lot. */
9164 if (flag_code != CODE_64BIT
9165 && (i.types[this_operand].bitfield.disp16
9166 || i.types[this_operand].bitfield.disp32))
9167 i.types[this_operand]
9168 = operand_type_xor (i.types[this_operand], disp16_32);
9178 /* Make sure the memory operand we've been dealt is valid.
9179 Return 1 on success, 0 on a failure. */
9182 i386_index_check (const char *operand_string)
9184 const char *kind = "base/index";
9185 enum flag_code addr_mode = i386_addressing_mode ();
9187 if (current_templates->start->opcode_modifier.isstring
9188 && !current_templates->start->opcode_modifier.immext
9189 && (current_templates->end[-1].opcode_modifier.isstring
9192 /* Memory operands of string insns are special in that they only allow
9193 a single register (rDI, rSI, or rBX) as their memory address. */
9194 const reg_entry *expected_reg;
9195 static const char *di_si[][2] =
9201 static const char *bx[] = { "ebx", "bx", "rbx" };
9203 kind = "string address";
9205 if (current_templates->start->opcode_modifier.repprefixok)
9207 i386_operand_type type = current_templates->end[-1].operand_types[0];
9209 if (!type.bitfield.baseindex
9210 || ((!i.mem_operands != !intel_syntax)
9211 && current_templates->end[-1].operand_types[1]
9212 .bitfield.baseindex))
9213 type = current_templates->end[-1].operand_types[1];
9214 expected_reg = hash_find (reg_hash,
9215 di_si[addr_mode][type.bitfield.esseg]);
9219 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9221 if (i.base_reg != expected_reg
9223 || operand_type_check (i.types[this_operand], disp))
9225 /* The second memory operand must have the same size as
9229 && !((addr_mode == CODE_64BIT
9230 && i.base_reg->reg_type.bitfield.qword)
9231 || (addr_mode == CODE_32BIT
9232 ? i.base_reg->reg_type.bitfield.dword
9233 : i.base_reg->reg_type.bitfield.word)))
9236 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9238 intel_syntax ? '[' : '(',
9240 expected_reg->reg_name,
9241 intel_syntax ? ']' : ')');
9248 as_bad (_("`%s' is not a valid %s expression"),
9249 operand_string, kind);
9254 if (addr_mode != CODE_16BIT)
9256 /* 32-bit/64-bit checks. */
9258 && (addr_mode == CODE_64BIT
9259 ? !i.base_reg->reg_type.bitfield.qword
9260 : !i.base_reg->reg_type.bitfield.dword)
9262 || (i.base_reg->reg_num
9263 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9265 && !i.index_reg->reg_type.bitfield.xmmword
9266 && !i.index_reg->reg_type.bitfield.ymmword
9267 && !i.index_reg->reg_type.bitfield.zmmword
9268 && ((addr_mode == CODE_64BIT
9269 ? !(i.index_reg->reg_type.bitfield.qword
9270 || i.index_reg->reg_num == RegRiz)
9271 : !(i.index_reg->reg_type.bitfield.dword
9272 || i.index_reg->reg_num == RegEiz))
9273 || !i.index_reg->reg_type.bitfield.baseindex)))
9276 /* bndmk, bndldx, and bndstx have special restrictions. */
9277 if (current_templates->start->base_opcode == 0xf30f1b
9278 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9280 /* They cannot use RIP-relative addressing. */
9281 if (i.base_reg && i.base_reg->reg_num == RegRip)
9283 as_bad (_("`%s' cannot be used here"), operand_string);
9287 /* bndldx and bndstx ignore their scale factor. */
9288 if (current_templates->start->base_opcode != 0xf30f1b
9289 && i.log2_scale_factor)
9290 as_warn (_("register scaling is being ignored here"));
9295 /* 16-bit checks. */
9297 && (!i.base_reg->reg_type.bitfield.word
9298 || !i.base_reg->reg_type.bitfield.baseindex))
9300 && (!i.index_reg->reg_type.bitfield.word
9301 || !i.index_reg->reg_type.bitfield.baseindex
9303 && i.base_reg->reg_num < 6
9304 && i.index_reg->reg_num >= 6
9305 && i.log2_scale_factor == 0))))
9312 /* Handle vector immediates. */
9315 RC_SAE_immediate (const char *imm_start)
9317 unsigned int match_found, j;
9318 const char *pstr = imm_start;
9326 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9328 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9332 rc_op.type = RC_NamesTable[j].type;
9333 rc_op.operand = this_operand;
9334 i.rounding = &rc_op;
9338 as_bad (_("duplicated `%s'"), imm_start);
9341 pstr += RC_NamesTable[j].len;
9351 as_bad (_("Missing '}': '%s'"), imm_start);
9354 /* RC/SAE immediate string should contain nothing more. */;
9357 as_bad (_("Junk after '}': '%s'"), imm_start);
9361 exp = &im_expressions[i.imm_operands++];
9362 i.op[this_operand].imms = exp;
9364 exp->X_op = O_constant;
9365 exp->X_add_number = 0;
9366 exp->X_add_symbol = (symbolS *) 0;
9367 exp->X_op_symbol = (symbolS *) 0;
9369 i.types[this_operand].bitfield.imm8 = 1;
9373 /* Only string instructions can have a second memory operand, so
9374 reduce current_templates to just those if it contains any. */
9376 maybe_adjust_templates (void)
9378 const insn_template *t;
9380 gas_assert (i.mem_operands == 1);
9382 for (t = current_templates->start; t < current_templates->end; ++t)
9383 if (t->opcode_modifier.isstring)
9386 if (t < current_templates->end)
9388 static templates aux_templates;
9389 bfd_boolean recheck;
9391 aux_templates.start = t;
9392 for (; t < current_templates->end; ++t)
9393 if (!t->opcode_modifier.isstring)
9395 aux_templates.end = t;
9397 /* Determine whether to re-check the first memory operand. */
9398 recheck = (aux_templates.start != current_templates->start
9399 || t != current_templates->end);
9401 current_templates = &aux_templates;
9406 if (i.memop1_string != NULL
9407 && i386_index_check (i.memop1_string) == 0)
9416 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9420 i386_att_operand (char *operand_string)
9424 char *op_string = operand_string;
9426 if (is_space_char (*op_string))
9429 /* We check for an absolute prefix (differentiating,
9430 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9431 if (*op_string == ABSOLUTE_PREFIX)
9434 if (is_space_char (*op_string))
9436 i.types[this_operand].bitfield.jumpabsolute = 1;
9439 /* Check if operand is a register. */
9440 if ((r = parse_register (op_string, &end_op)) != NULL)
9442 i386_operand_type temp;
9444 /* Check for a segment override by searching for ':' after a
9445 segment register. */
9447 if (is_space_char (*op_string))
9449 if (*op_string == ':'
9450 && (r->reg_type.bitfield.sreg2
9451 || r->reg_type.bitfield.sreg3))
9456 i.seg[i.mem_operands] = &es;
9459 i.seg[i.mem_operands] = &cs;
9462 i.seg[i.mem_operands] = &ss;
9465 i.seg[i.mem_operands] = &ds;
9468 i.seg[i.mem_operands] = &fs;
9471 i.seg[i.mem_operands] = &gs;
9475 /* Skip the ':' and whitespace. */
9477 if (is_space_char (*op_string))
9480 if (!is_digit_char (*op_string)
9481 && !is_identifier_char (*op_string)
9482 && *op_string != '('
9483 && *op_string != ABSOLUTE_PREFIX)
9485 as_bad (_("bad memory operand `%s'"), op_string);
9488 /* Handle case of %es:*foo. */
9489 if (*op_string == ABSOLUTE_PREFIX)
9492 if (is_space_char (*op_string))
9494 i.types[this_operand].bitfield.jumpabsolute = 1;
9496 goto do_memory_reference;
9499 /* Handle vector operations. */
9500 if (*op_string == '{')
9502 op_string = check_VecOperations (op_string, NULL);
9503 if (op_string == NULL)
9509 as_bad (_("junk `%s' after register"), op_string);
9513 temp.bitfield.baseindex = 0;
9514 i.types[this_operand] = operand_type_or (i.types[this_operand],
9516 i.types[this_operand].bitfield.unspecified = 0;
9517 i.op[this_operand].regs = r;
9520 else if (*op_string == REGISTER_PREFIX)
9522 as_bad (_("bad register name `%s'"), op_string);
9525 else if (*op_string == IMMEDIATE_PREFIX)
9528 if (i.types[this_operand].bitfield.jumpabsolute)
9530 as_bad (_("immediate operand illegal with absolute jump"));
9533 if (!i386_immediate (op_string))
9536 else if (RC_SAE_immediate (operand_string))
9538 /* If it is a RC or SAE immediate, do nothing. */
9541 else if (is_digit_char (*op_string)
9542 || is_identifier_char (*op_string)
9543 || *op_string == '"'
9544 || *op_string == '(')
9546 /* This is a memory reference of some sort. */
9549 /* Start and end of displacement string expression (if found). */
9550 char *displacement_string_start;
9551 char *displacement_string_end;
9554 do_memory_reference:
9555 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9557 if ((i.mem_operands == 1
9558 && !current_templates->start->opcode_modifier.isstring)
9559 || i.mem_operands == 2)
9561 as_bad (_("too many memory references for `%s'"),
9562 current_templates->start->name);
9566 /* Check for base index form. We detect the base index form by
9567 looking for an ')' at the end of the operand, searching
9568 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9570 base_string = op_string + strlen (op_string);
9572 /* Handle vector operations. */
9573 vop_start = strchr (op_string, '{');
9574 if (vop_start && vop_start < base_string)
9576 if (check_VecOperations (vop_start, base_string) == NULL)
9578 base_string = vop_start;
9582 if (is_space_char (*base_string))
9585 /* If we only have a displacement, set-up for it to be parsed later. */
9586 displacement_string_start = op_string;
9587 displacement_string_end = base_string + 1;
9589 if (*base_string == ')')
9592 unsigned int parens_balanced = 1;
9593 /* We've already checked that the number of left & right ()'s are
9594 equal, so this loop will not be infinite. */
9598 if (*base_string == ')')
9600 if (*base_string == '(')
9603 while (parens_balanced);
9605 temp_string = base_string;
9607 /* Skip past '(' and whitespace. */
9609 if (is_space_char (*base_string))
9612 if (*base_string == ','
9613 || ((i.base_reg = parse_register (base_string, &end_op))
9616 displacement_string_end = temp_string;
9618 i.types[this_operand].bitfield.baseindex = 1;
9622 base_string = end_op;
9623 if (is_space_char (*base_string))
9627 /* There may be an index reg or scale factor here. */
9628 if (*base_string == ',')
9631 if (is_space_char (*base_string))
9634 if ((i.index_reg = parse_register (base_string, &end_op))
9637 base_string = end_op;
9638 if (is_space_char (*base_string))
9640 if (*base_string == ',')
9643 if (is_space_char (*base_string))
9646 else if (*base_string != ')')
9648 as_bad (_("expecting `,' or `)' "
9649 "after index register in `%s'"),
9654 else if (*base_string == REGISTER_PREFIX)
9656 end_op = strchr (base_string, ',');
9659 as_bad (_("bad register name `%s'"), base_string);
9663 /* Check for scale factor. */
9664 if (*base_string != ')')
9666 char *end_scale = i386_scale (base_string);
9671 base_string = end_scale;
9672 if (is_space_char (*base_string))
9674 if (*base_string != ')')
9676 as_bad (_("expecting `)' "
9677 "after scale factor in `%s'"),
9682 else if (!i.index_reg)
9684 as_bad (_("expecting index register or scale factor "
9685 "after `,'; got '%c'"),
9690 else if (*base_string != ')')
9692 as_bad (_("expecting `,' or `)' "
9693 "after base register in `%s'"),
9698 else if (*base_string == REGISTER_PREFIX)
9700 end_op = strchr (base_string, ',');
9703 as_bad (_("bad register name `%s'"), base_string);
9708 /* If there's an expression beginning the operand, parse it,
9709 assuming displacement_string_start and
9710 displacement_string_end are meaningful. */
9711 if (displacement_string_start != displacement_string_end)
9713 if (!i386_displacement (displacement_string_start,
9714 displacement_string_end))
9718 /* Special case for (%dx) while doing input/output op. */
9720 && i.base_reg->reg_type.bitfield.inoutportreg
9722 && i.log2_scale_factor == 0
9723 && i.seg[i.mem_operands] == 0
9724 && !operand_type_check (i.types[this_operand], disp))
9726 i.types[this_operand] = i.base_reg->reg_type;
9730 if (i386_index_check (operand_string) == 0)
9732 i.types[this_operand].bitfield.mem = 1;
9733 if (i.mem_operands == 0)
9734 i.memop1_string = xstrdup (operand_string);
9739 /* It's not a memory operand; argh! */
9740 as_bad (_("invalid char %s beginning operand %d `%s'"),
9741 output_invalid (*op_string),
9746 return 1; /* Normal return. */
9749 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9750 that an rs_machine_dependent frag may reach. */
9753 i386_frag_max_var (fragS *frag)
9755 /* The only relaxable frags are for jumps.
9756 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9757 gas_assert (frag->fr_type == rs_machine_dependent);
9758 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9763 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9765 /* STT_GNU_IFUNC symbol must go through PLT. */
9766 if ((symbol_get_bfdsym (fr_symbol)->flags
9767 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9770 if (!S_IS_EXTERNAL (fr_symbol))
9771 /* Symbol may be weak or local. */
9772 return !S_IS_WEAK (fr_symbol);
9774 /* Global symbols with non-default visibility can't be preempted. */
9775 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9778 if (fr_var != NO_RELOC)
9779 switch ((enum bfd_reloc_code_real) fr_var)
9781 case BFD_RELOC_386_PLT32:
9782 case BFD_RELOC_X86_64_PLT32:
9783 /* Symbol with PLT relocation may be preempted. */
9789 /* Global symbols with default visibility in a shared library may be
9790 preempted by another definition. */
9795 /* md_estimate_size_before_relax()
9797 Called just before relax() for rs_machine_dependent frags. The x86
9798 assembler uses these frags to handle variable size jump
9801 Any symbol that is now undefined will not become defined.
9802 Return the correct fr_subtype in the frag.
9803 Return the initial "guess for variable size of frag" to caller.
9804 The guess is actually the growth beyond the fixed part. Whatever
9805 we do to grow the fixed or variable part contributes to our
9809 md_estimate_size_before_relax (fragS *fragP, segT segment)
9811 /* We've already got fragP->fr_subtype right; all we have to do is
9812 check for un-relaxable symbols. On an ELF system, we can't relax
9813 an externally visible symbol, because it may be overridden by a
9815 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9818 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9821 #if defined (OBJ_COFF) && defined (TE_PE)
9822 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9823 && S_IS_WEAK (fragP->fr_symbol))
9827 /* Symbol is undefined in this segment, or we need to keep a
9828 reloc so that weak symbols can be overridden. */
9829 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9830 enum bfd_reloc_code_real reloc_type;
9831 unsigned char *opcode;
9834 if (fragP->fr_var != NO_RELOC)
9835 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9837 reloc_type = BFD_RELOC_16_PCREL;
9838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9839 else if (need_plt32_p (fragP->fr_symbol))
9840 reloc_type = BFD_RELOC_X86_64_PLT32;
9843 reloc_type = BFD_RELOC_32_PCREL;
9845 old_fr_fix = fragP->fr_fix;
9846 opcode = (unsigned char *) fragP->fr_opcode;
9848 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9851 /* Make jmp (0xeb) a (d)word displacement jump. */
9853 fragP->fr_fix += size;
9854 fix_new (fragP, old_fr_fix, size,
9856 fragP->fr_offset, 1,
9862 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9864 /* Negate the condition, and branch past an
9865 unconditional jump. */
9868 /* Insert an unconditional jump. */
9870 /* We added two extra opcode bytes, and have a two byte
9872 fragP->fr_fix += 2 + 2;
9873 fix_new (fragP, old_fr_fix + 2, 2,
9875 fragP->fr_offset, 1,
9882 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9887 fixP = fix_new (fragP, old_fr_fix, 1,
9889 fragP->fr_offset, 1,
9891 fixP->fx_signed = 1;
9895 /* This changes the byte-displacement jump 0x7N
9896 to the (d)word-displacement jump 0x0f,0x8N. */
9897 opcode[1] = opcode[0] + 0x10;
9898 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9899 /* We've added an opcode byte. */
9900 fragP->fr_fix += 1 + size;
9901 fix_new (fragP, old_fr_fix + 1, size,
9903 fragP->fr_offset, 1,
9908 BAD_CASE (fragP->fr_subtype);
9912 return fragP->fr_fix - old_fr_fix;
9915 /* Guess size depending on current relax state. Initially the relax
9916 state will correspond to a short jump and we return 1, because
9917 the variable part of the frag (the branch offset) is one byte
9918 long. However, we can relax a section more than once and in that
9919 case we must either set fr_subtype back to the unrelaxed state,
9920 or return the value for the appropriate branch. */
9921 return md_relax_table[fragP->fr_subtype].rlx_length;
9924 /* Called after relax() is finished.
9926 In: Address of frag.
9927 fr_type == rs_machine_dependent.
9928 fr_subtype is what the address relaxed to.
9930 Out: Any fixSs and constants are set up.
9931 Caller will turn frag into a ".space 0". */
9934 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9937 unsigned char *opcode;
9938 unsigned char *where_to_put_displacement = NULL;
9939 offsetT target_address;
9940 offsetT opcode_address;
9941 unsigned int extension = 0;
9942 offsetT displacement_from_opcode_start;
9944 opcode = (unsigned char *) fragP->fr_opcode;
9946 /* Address we want to reach in file space. */
9947 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9949 /* Address opcode resides at in file space. */
9950 opcode_address = fragP->fr_address + fragP->fr_fix;
9952 /* Displacement from opcode start to fill into instruction. */
9953 displacement_from_opcode_start = target_address - opcode_address;
9955 if ((fragP->fr_subtype & BIG) == 0)
9957 /* Don't have to change opcode. */
9958 extension = 1; /* 1 opcode + 1 displacement */
9959 where_to_put_displacement = &opcode[1];
9963 if (no_cond_jump_promotion
9964 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9965 as_warn_where (fragP->fr_file, fragP->fr_line,
9966 _("long jump required"));
9968 switch (fragP->fr_subtype)
9970 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9971 extension = 4; /* 1 opcode + 4 displacement */
9973 where_to_put_displacement = &opcode[1];
9976 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9977 extension = 2; /* 1 opcode + 2 displacement */
9979 where_to_put_displacement = &opcode[1];
9982 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9983 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9984 extension = 5; /* 2 opcode + 4 displacement */
9985 opcode[1] = opcode[0] + 0x10;
9986 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9987 where_to_put_displacement = &opcode[2];
9990 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9991 extension = 3; /* 2 opcode + 2 displacement */
9992 opcode[1] = opcode[0] + 0x10;
9993 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9994 where_to_put_displacement = &opcode[2];
9997 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10002 where_to_put_displacement = &opcode[3];
10006 BAD_CASE (fragP->fr_subtype);
10011 /* If size if less then four we are sure that the operand fits,
10012 but if it's 4, then it could be that the displacement is larger
10014 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10016 && ((addressT) (displacement_from_opcode_start - extension
10017 + ((addressT) 1 << 31))
10018 > (((addressT) 2 << 31) - 1)))
10020 as_bad_where (fragP->fr_file, fragP->fr_line,
10021 _("jump target out of range"));
10022 /* Make us emit 0. */
10023 displacement_from_opcode_start = extension;
10025 /* Now put displacement after opcode. */
10026 md_number_to_chars ((char *) where_to_put_displacement,
10027 (valueT) (displacement_from_opcode_start - extension),
10028 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10029 fragP->fr_fix += extension;
10032 /* Apply a fixup (fixP) to segment data, once it has been determined
10033 by our caller that we have all the info we need to fix it up.
10035 Parameter valP is the pointer to the value of the bits.
10037 On the 386, immediates, displacements, and data pointers are all in
10038 the same (little-endian) format, so we don't need to care about which
10039 we are handling. */
10042 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10044 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10045 valueT value = *valP;
10047 #if !defined (TE_Mach)
10048 if (fixP->fx_pcrel)
10050 switch (fixP->fx_r_type)
10056 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10059 case BFD_RELOC_X86_64_32S:
10060 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10063 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10066 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10071 if (fixP->fx_addsy != NULL
10072 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10073 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10074 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10075 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10076 && !use_rela_relocations)
10078 /* This is a hack. There should be a better way to handle this.
10079 This covers for the fact that bfd_install_relocation will
10080 subtract the current location (for partial_inplace, PC relative
10081 relocations); see more below. */
10085 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10088 value += fixP->fx_where + fixP->fx_frag->fr_address;
10090 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10093 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10095 if ((sym_seg == seg
10096 || (symbol_section_p (fixP->fx_addsy)
10097 && sym_seg != absolute_section))
10098 && !generic_force_reloc (fixP))
10100 /* Yes, we add the values in twice. This is because
10101 bfd_install_relocation subtracts them out again. I think
10102 bfd_install_relocation is broken, but I don't dare change
10104 value += fixP->fx_where + fixP->fx_frag->fr_address;
10108 #if defined (OBJ_COFF) && defined (TE_PE)
10109 /* For some reason, the PE format does not store a
10110 section address offset for a PC relative symbol. */
10111 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10112 || S_IS_WEAK (fixP->fx_addsy))
10113 value += md_pcrel_from (fixP);
10116 #if defined (OBJ_COFF) && defined (TE_PE)
10117 if (fixP->fx_addsy != NULL
10118 && S_IS_WEAK (fixP->fx_addsy)
10119 /* PR 16858: Do not modify weak function references. */
10120 && ! fixP->fx_pcrel)
10122 #if !defined (TE_PEP)
10123 /* For x86 PE weak function symbols are neither PC-relative
10124 nor do they set S_IS_FUNCTION. So the only reliable way
10125 to detect them is to check the flags of their containing
10127 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10128 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10132 value -= S_GET_VALUE (fixP->fx_addsy);
10136 /* Fix a few things - the dynamic linker expects certain values here,
10137 and we must not disappoint it. */
10138 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10139 if (IS_ELF && fixP->fx_addsy)
10140 switch (fixP->fx_r_type)
10142 case BFD_RELOC_386_PLT32:
10143 case BFD_RELOC_X86_64_PLT32:
10144 /* Make the jump instruction point to the address of the operand. At
10145 runtime we merely add the offset to the actual PLT entry. */
10149 case BFD_RELOC_386_TLS_GD:
10150 case BFD_RELOC_386_TLS_LDM:
10151 case BFD_RELOC_386_TLS_IE_32:
10152 case BFD_RELOC_386_TLS_IE:
10153 case BFD_RELOC_386_TLS_GOTIE:
10154 case BFD_RELOC_386_TLS_GOTDESC:
10155 case BFD_RELOC_X86_64_TLSGD:
10156 case BFD_RELOC_X86_64_TLSLD:
10157 case BFD_RELOC_X86_64_GOTTPOFF:
10158 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10159 value = 0; /* Fully resolved at runtime. No addend. */
10161 case BFD_RELOC_386_TLS_LE:
10162 case BFD_RELOC_386_TLS_LDO_32:
10163 case BFD_RELOC_386_TLS_LE_32:
10164 case BFD_RELOC_X86_64_DTPOFF32:
10165 case BFD_RELOC_X86_64_DTPOFF64:
10166 case BFD_RELOC_X86_64_TPOFF32:
10167 case BFD_RELOC_X86_64_TPOFF64:
10168 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10171 case BFD_RELOC_386_TLS_DESC_CALL:
10172 case BFD_RELOC_X86_64_TLSDESC_CALL:
10173 value = 0; /* Fully resolved at runtime. No addend. */
10174 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10178 case BFD_RELOC_VTABLE_INHERIT:
10179 case BFD_RELOC_VTABLE_ENTRY:
10186 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10188 #endif /* !defined (TE_Mach) */
10190 /* Are we finished with this relocation now? */
10191 if (fixP->fx_addsy == NULL)
10193 #if defined (OBJ_COFF) && defined (TE_PE)
10194 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10197 /* Remember value for tc_gen_reloc. */
10198 fixP->fx_addnumber = value;
10199 /* Clear out the frag for now. */
10203 else if (use_rela_relocations)
10205 fixP->fx_no_overflow = 1;
10206 /* Remember value for tc_gen_reloc. */
10207 fixP->fx_addnumber = value;
10211 md_number_to_chars (p, value, fixP->fx_size);
10215 md_atof (int type, char *litP, int *sizeP)
10217 /* This outputs the LITTLENUMs in REVERSE order;
10218 in accord with the bigendian 386. */
10219 return ieee_md_atof (type, litP, sizeP, FALSE);
10222 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10225 output_invalid (int c)
10228 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10231 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10232 "(0x%x)", (unsigned char) c);
10233 return output_invalid_buf;
10236 /* REG_STRING starts *before* REGISTER_PREFIX. */
10238 static const reg_entry *
10239 parse_real_register (char *reg_string, char **end_op)
10241 char *s = reg_string;
10243 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10244 const reg_entry *r;
10246 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10247 if (*s == REGISTER_PREFIX)
10250 if (is_space_char (*s))
10253 p = reg_name_given;
10254 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10256 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10257 return (const reg_entry *) NULL;
10261 /* For naked regs, make sure that we are not dealing with an identifier.
10262 This prevents confusing an identifier like `eax_var' with register
10264 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10265 return (const reg_entry *) NULL;
10269 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10271 /* Handle floating point regs, allowing spaces in the (i) part. */
10272 if (r == i386_regtab /* %st is first entry of table */)
10274 if (!cpu_arch_flags.bitfield.cpu8087
10275 && !cpu_arch_flags.bitfield.cpu287
10276 && !cpu_arch_flags.bitfield.cpu387)
10277 return (const reg_entry *) NULL;
10279 if (is_space_char (*s))
10284 if (is_space_char (*s))
10286 if (*s >= '0' && *s <= '7')
10288 int fpr = *s - '0';
10290 if (is_space_char (*s))
10295 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10300 /* We have "%st(" then garbage. */
10301 return (const reg_entry *) NULL;
10305 if (r == NULL || allow_pseudo_reg)
10308 if (operand_type_all_zero (&r->reg_type))
10309 return (const reg_entry *) NULL;
10311 if ((r->reg_type.bitfield.dword
10312 || r->reg_type.bitfield.sreg3
10313 || r->reg_type.bitfield.control
10314 || r->reg_type.bitfield.debug
10315 || r->reg_type.bitfield.test)
10316 && !cpu_arch_flags.bitfield.cpui386)
10317 return (const reg_entry *) NULL;
10319 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10320 return (const reg_entry *) NULL;
10322 if (!cpu_arch_flags.bitfield.cpuavx512f)
10324 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10325 return (const reg_entry *) NULL;
10327 if (!cpu_arch_flags.bitfield.cpuavx)
10329 if (r->reg_type.bitfield.ymmword)
10330 return (const reg_entry *) NULL;
10332 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10333 return (const reg_entry *) NULL;
10337 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10338 return (const reg_entry *) NULL;
10340 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10341 if (!allow_index_reg
10342 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10343 return (const reg_entry *) NULL;
10345 /* Upper 16 vector registers are only available with VREX in 64bit
10346 mode, and require EVEX encoding. */
10347 if (r->reg_flags & RegVRex)
10349 if (!cpu_arch_flags.bitfield.cpuvrex
10350 || flag_code != CODE_64BIT)
10351 return (const reg_entry *) NULL;
10353 i.vec_encoding = vex_encoding_evex;
10356 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10357 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10358 && flag_code != CODE_64BIT)
10359 return (const reg_entry *) NULL;
10361 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10362 return (const reg_entry *) NULL;
10367 /* REG_STRING starts *before* REGISTER_PREFIX. */
10369 static const reg_entry *
10370 parse_register (char *reg_string, char **end_op)
10372 const reg_entry *r;
10374 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10375 r = parse_real_register (reg_string, end_op);
10380 char *save = input_line_pointer;
10384 input_line_pointer = reg_string;
10385 c = get_symbol_name (®_string);
10386 symbolP = symbol_find (reg_string);
10387 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10389 const expressionS *e = symbol_get_value_expression (symbolP);
10391 know (e->X_op == O_register);
10392 know (e->X_add_number >= 0
10393 && (valueT) e->X_add_number < i386_regtab_size);
10394 r = i386_regtab + e->X_add_number;
10395 if ((r->reg_flags & RegVRex))
10396 i.vec_encoding = vex_encoding_evex;
10397 *end_op = input_line_pointer;
10399 *input_line_pointer = c;
10400 input_line_pointer = save;
10406 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10408 const reg_entry *r;
10409 char *end = input_line_pointer;
10412 r = parse_register (name, &input_line_pointer);
10413 if (r && end <= input_line_pointer)
10415 *nextcharP = *input_line_pointer;
10416 *input_line_pointer = 0;
10417 e->X_op = O_register;
10418 e->X_add_number = r - i386_regtab;
10421 input_line_pointer = end;
10423 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10427 md_operand (expressionS *e)
10430 const reg_entry *r;
10432 switch (*input_line_pointer)
10434 case REGISTER_PREFIX:
10435 r = parse_real_register (input_line_pointer, &end);
10438 e->X_op = O_register;
10439 e->X_add_number = r - i386_regtab;
10440 input_line_pointer = end;
10445 gas_assert (intel_syntax);
10446 end = input_line_pointer++;
10448 if (*input_line_pointer == ']')
10450 ++input_line_pointer;
10451 e->X_op_symbol = make_expr_symbol (e);
10452 e->X_add_symbol = NULL;
10453 e->X_add_number = 0;
10458 e->X_op = O_absent;
10459 input_line_pointer = end;
10466 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10467 const char *md_shortopts = "kVQ:sqnO::";
10469 const char *md_shortopts = "qnO::";
10472 #define OPTION_32 (OPTION_MD_BASE + 0)
10473 #define OPTION_64 (OPTION_MD_BASE + 1)
10474 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10475 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10476 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10477 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10478 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10479 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10480 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10481 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10482 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10483 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10484 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10485 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10486 #define OPTION_X32 (OPTION_MD_BASE + 14)
10487 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10488 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10489 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10490 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10491 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10492 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10493 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10494 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10495 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10496 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10498 struct option md_longopts[] =
10500 {"32", no_argument, NULL, OPTION_32},
10501 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10502 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10503 {"64", no_argument, NULL, OPTION_64},
10505 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10506 {"x32", no_argument, NULL, OPTION_X32},
10507 {"mshared", no_argument, NULL, OPTION_MSHARED},
10509 {"divide", no_argument, NULL, OPTION_DIVIDE},
10510 {"march", required_argument, NULL, OPTION_MARCH},
10511 {"mtune", required_argument, NULL, OPTION_MTUNE},
10512 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10513 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10514 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10515 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10516 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10517 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10518 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10519 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10520 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10521 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10522 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10523 # if defined (TE_PE) || defined (TE_PEP)
10524 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10526 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10527 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10528 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10529 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10530 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10531 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10532 {NULL, no_argument, NULL, 0}
10534 size_t md_longopts_size = sizeof (md_longopts);
10537 md_parse_option (int c, const char *arg)
10540 char *arch, *next, *saved;
10545 optimize_align_code = 0;
10549 quiet_warnings = 1;
10552 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10553 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10554 should be emitted or not. FIXME: Not implemented. */
10558 /* -V: SVR4 argument to print version ID. */
10560 print_version_id ();
10563 /* -k: Ignore for FreeBSD compatibility. */
10568 /* -s: On i386 Solaris, this tells the native assembler to use
10569 .stab instead of .stab.excl. We always use .stab anyhow. */
10572 case OPTION_MSHARED:
10576 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10577 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10580 const char **list, **l;
10582 list = bfd_target_list ();
10583 for (l = list; *l != NULL; l++)
10584 if (CONST_STRNEQ (*l, "elf64-x86-64")
10585 || strcmp (*l, "coff-x86-64") == 0
10586 || strcmp (*l, "pe-x86-64") == 0
10587 || strcmp (*l, "pei-x86-64") == 0
10588 || strcmp (*l, "mach-o-x86-64") == 0)
10590 default_arch = "x86_64";
10594 as_fatal (_("no compiled in support for x86_64"));
10600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10604 const char **list, **l;
10606 list = bfd_target_list ();
10607 for (l = list; *l != NULL; l++)
10608 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10610 default_arch = "x86_64:32";
10614 as_fatal (_("no compiled in support for 32bit x86_64"));
10618 as_fatal (_("32bit x86_64 is only supported for ELF"));
10623 default_arch = "i386";
10626 case OPTION_DIVIDE:
10627 #ifdef SVR4_COMMENT_CHARS
10632 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10634 for (s = i386_comment_chars; *s != '\0'; s++)
10638 i386_comment_chars = n;
10644 saved = xstrdup (arg);
10646 /* Allow -march=+nosse. */
10652 as_fatal (_("invalid -march= option: `%s'"), arg);
10653 next = strchr (arch, '+');
10656 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10658 if (strcmp (arch, cpu_arch [j].name) == 0)
10661 if (! cpu_arch[j].flags.bitfield.cpui386)
10664 cpu_arch_name = cpu_arch[j].name;
10665 cpu_sub_arch_name = NULL;
10666 cpu_arch_flags = cpu_arch[j].flags;
10667 cpu_arch_isa = cpu_arch[j].type;
10668 cpu_arch_isa_flags = cpu_arch[j].flags;
10669 if (!cpu_arch_tune_set)
10671 cpu_arch_tune = cpu_arch_isa;
10672 cpu_arch_tune_flags = cpu_arch_isa_flags;
10676 else if (*cpu_arch [j].name == '.'
10677 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10679 /* ISA extension. */
10680 i386_cpu_flags flags;
10682 flags = cpu_flags_or (cpu_arch_flags,
10683 cpu_arch[j].flags);
10685 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10687 if (cpu_sub_arch_name)
10689 char *name = cpu_sub_arch_name;
10690 cpu_sub_arch_name = concat (name,
10692 (const char *) NULL);
10696 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10697 cpu_arch_flags = flags;
10698 cpu_arch_isa_flags = flags;
10702 = cpu_flags_or (cpu_arch_isa_flags,
10703 cpu_arch[j].flags);
10708 if (j >= ARRAY_SIZE (cpu_arch))
10710 /* Disable an ISA extension. */
10711 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10712 if (strcmp (arch, cpu_noarch [j].name) == 0)
10714 i386_cpu_flags flags;
10716 flags = cpu_flags_and_not (cpu_arch_flags,
10717 cpu_noarch[j].flags);
10718 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10720 if (cpu_sub_arch_name)
10722 char *name = cpu_sub_arch_name;
10723 cpu_sub_arch_name = concat (arch,
10724 (const char *) NULL);
10728 cpu_sub_arch_name = xstrdup (arch);
10729 cpu_arch_flags = flags;
10730 cpu_arch_isa_flags = flags;
10735 if (j >= ARRAY_SIZE (cpu_noarch))
10736 j = ARRAY_SIZE (cpu_arch);
10739 if (j >= ARRAY_SIZE (cpu_arch))
10740 as_fatal (_("invalid -march= option: `%s'"), arg);
10744 while (next != NULL);
10750 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10751 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10753 if (strcmp (arg, cpu_arch [j].name) == 0)
10755 cpu_arch_tune_set = 1;
10756 cpu_arch_tune = cpu_arch [j].type;
10757 cpu_arch_tune_flags = cpu_arch[j].flags;
10761 if (j >= ARRAY_SIZE (cpu_arch))
10762 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10765 case OPTION_MMNEMONIC:
10766 if (strcasecmp (arg, "att") == 0)
10767 intel_mnemonic = 0;
10768 else if (strcasecmp (arg, "intel") == 0)
10769 intel_mnemonic = 1;
10771 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10774 case OPTION_MSYNTAX:
10775 if (strcasecmp (arg, "att") == 0)
10777 else if (strcasecmp (arg, "intel") == 0)
10780 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10783 case OPTION_MINDEX_REG:
10784 allow_index_reg = 1;
10787 case OPTION_MNAKED_REG:
10788 allow_naked_reg = 1;
10791 case OPTION_MSSE2AVX:
10795 case OPTION_MSSE_CHECK:
10796 if (strcasecmp (arg, "error") == 0)
10797 sse_check = check_error;
10798 else if (strcasecmp (arg, "warning") == 0)
10799 sse_check = check_warning;
10800 else if (strcasecmp (arg, "none") == 0)
10801 sse_check = check_none;
10803 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10806 case OPTION_MOPERAND_CHECK:
10807 if (strcasecmp (arg, "error") == 0)
10808 operand_check = check_error;
10809 else if (strcasecmp (arg, "warning") == 0)
10810 operand_check = check_warning;
10811 else if (strcasecmp (arg, "none") == 0)
10812 operand_check = check_none;
10814 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10817 case OPTION_MAVXSCALAR:
10818 if (strcasecmp (arg, "128") == 0)
10819 avxscalar = vex128;
10820 else if (strcasecmp (arg, "256") == 0)
10821 avxscalar = vex256;
10823 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10826 case OPTION_MADD_BND_PREFIX:
10827 add_bnd_prefix = 1;
10830 case OPTION_MEVEXLIG:
10831 if (strcmp (arg, "128") == 0)
10832 evexlig = evexl128;
10833 else if (strcmp (arg, "256") == 0)
10834 evexlig = evexl256;
10835 else if (strcmp (arg, "512") == 0)
10836 evexlig = evexl512;
10838 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10841 case OPTION_MEVEXRCIG:
10842 if (strcmp (arg, "rne") == 0)
10844 else if (strcmp (arg, "rd") == 0)
10846 else if (strcmp (arg, "ru") == 0)
10848 else if (strcmp (arg, "rz") == 0)
10851 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10854 case OPTION_MEVEXWIG:
10855 if (strcmp (arg, "0") == 0)
10857 else if (strcmp (arg, "1") == 0)
10860 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10863 # if defined (TE_PE) || defined (TE_PEP)
10864 case OPTION_MBIG_OBJ:
10869 case OPTION_MOMIT_LOCK_PREFIX:
10870 if (strcasecmp (arg, "yes") == 0)
10871 omit_lock_prefix = 1;
10872 else if (strcasecmp (arg, "no") == 0)
10873 omit_lock_prefix = 0;
10875 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10878 case OPTION_MFENCE_AS_LOCK_ADD:
10879 if (strcasecmp (arg, "yes") == 0)
10881 else if (strcasecmp (arg, "no") == 0)
10884 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10887 case OPTION_MRELAX_RELOCATIONS:
10888 if (strcasecmp (arg, "yes") == 0)
10889 generate_relax_relocations = 1;
10890 else if (strcasecmp (arg, "no") == 0)
10891 generate_relax_relocations = 0;
10893 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10896 case OPTION_MAMD64:
10900 case OPTION_MINTEL64:
10908 /* Turn off -Os. */
10909 optimize_for_space = 0;
10911 else if (*arg == 's')
10913 optimize_for_space = 1;
10914 /* Turn on all encoding optimizations. */
10919 optimize = atoi (arg);
10920 /* Turn off -Os. */
10921 optimize_for_space = 0;
10931 #define MESSAGE_TEMPLATE \
10935 output_message (FILE *stream, char *p, char *message, char *start,
10936 int *left_p, const char *name, int len)
10938 int size = sizeof (MESSAGE_TEMPLATE);
10939 int left = *left_p;
10941 /* Reserve 2 spaces for ", " or ",\0" */
10944 /* Check if there is any room. */
10952 p = mempcpy (p, name, len);
10956 /* Output the current message now and start a new one. */
10959 fprintf (stream, "%s\n", message);
10961 left = size - (start - message) - len - 2;
10963 gas_assert (left >= 0);
10965 p = mempcpy (p, name, len);
10973 show_arch (FILE *stream, int ext, int check)
10975 static char message[] = MESSAGE_TEMPLATE;
10976 char *start = message + 27;
10978 int size = sizeof (MESSAGE_TEMPLATE);
10985 left = size - (start - message);
10986 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10988 /* Should it be skipped? */
10989 if (cpu_arch [j].skip)
10992 name = cpu_arch [j].name;
10993 len = cpu_arch [j].len;
10996 /* It is an extension. Skip if we aren't asked to show it. */
11007 /* It is an processor. Skip if we show only extension. */
11010 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11012 /* It is an impossible processor - skip. */
11016 p = output_message (stream, p, message, start, &left, name, len);
11019 /* Display disabled extensions. */
11021 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11023 name = cpu_noarch [j].name;
11024 len = cpu_noarch [j].len;
11025 p = output_message (stream, p, message, start, &left, name,
11030 fprintf (stream, "%s\n", message);
11034 md_show_usage (FILE *stream)
11036 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11037 fprintf (stream, _("\
11039 -V print assembler version number\n\
11042 fprintf (stream, _("\
11043 -n Do not optimize code alignment\n\
11044 -q quieten some warnings\n"));
11045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11046 fprintf (stream, _("\
11049 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11050 || defined (TE_PE) || defined (TE_PEP))
11051 fprintf (stream, _("\
11052 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11054 #ifdef SVR4_COMMENT_CHARS
11055 fprintf (stream, _("\
11056 --divide do not treat `/' as a comment character\n"));
11058 fprintf (stream, _("\
11059 --divide ignored\n"));
11061 fprintf (stream, _("\
11062 -march=CPU[,+EXTENSION...]\n\
11063 generate code for CPU and EXTENSION, CPU is one of:\n"));
11064 show_arch (stream, 0, 1);
11065 fprintf (stream, _("\
11066 EXTENSION is combination of:\n"));
11067 show_arch (stream, 1, 0);
11068 fprintf (stream, _("\
11069 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11070 show_arch (stream, 0, 0);
11071 fprintf (stream, _("\
11072 -msse2avx encode SSE instructions with VEX prefix\n"));
11073 fprintf (stream, _("\
11074 -msse-check=[none|error|warning]\n\
11075 check SSE instructions\n"));
11076 fprintf (stream, _("\
11077 -moperand-check=[none|error|warning]\n\
11078 check operand combinations for validity\n"));
11079 fprintf (stream, _("\
11080 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11082 fprintf (stream, _("\
11083 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11085 fprintf (stream, _("\
11086 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11087 for EVEX.W bit ignored instructions\n"));
11088 fprintf (stream, _("\
11089 -mevexrcig=[rne|rd|ru|rz]\n\
11090 encode EVEX instructions with specific EVEX.RC value\n\
11091 for SAE-only ignored instructions\n"));
11092 fprintf (stream, _("\
11093 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11094 fprintf (stream, _("\
11095 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11096 fprintf (stream, _("\
11097 -mindex-reg support pseudo index registers\n"));
11098 fprintf (stream, _("\
11099 -mnaked-reg don't require `%%' prefix for registers\n"));
11100 fprintf (stream, _("\
11101 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11102 fprintf (stream, _("\
11103 -mshared disable branch optimization for shared code\n"));
11104 # if defined (TE_PE) || defined (TE_PEP)
11105 fprintf (stream, _("\
11106 -mbig-obj generate big object files\n"));
11108 fprintf (stream, _("\
11109 -momit-lock-prefix=[no|yes]\n\
11110 strip all lock prefixes\n"));
11111 fprintf (stream, _("\
11112 -mfence-as-lock-add=[no|yes]\n\
11113 encode lfence, mfence and sfence as\n\
11114 lock addl $0x0, (%%{re}sp)\n"));
11115 fprintf (stream, _("\
11116 -mrelax-relocations=[no|yes]\n\
11117 generate relax relocations\n"));
11118 fprintf (stream, _("\
11119 -mamd64 accept only AMD64 ISA\n"));
11120 fprintf (stream, _("\
11121 -mintel64 accept only Intel64 ISA\n"));
11124 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11125 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11126 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11128 /* Pick the target format to use. */
11131 i386_target_format (void)
11133 if (!strncmp (default_arch, "x86_64", 6))
11135 update_code_flag (CODE_64BIT, 1);
11136 if (default_arch[6] == '\0')
11137 x86_elf_abi = X86_64_ABI;
11139 x86_elf_abi = X86_64_X32_ABI;
11141 else if (!strcmp (default_arch, "i386"))
11142 update_code_flag (CODE_32BIT, 1);
11143 else if (!strcmp (default_arch, "iamcu"))
11145 update_code_flag (CODE_32BIT, 1);
11146 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11148 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11149 cpu_arch_name = "iamcu";
11150 cpu_sub_arch_name = NULL;
11151 cpu_arch_flags = iamcu_flags;
11152 cpu_arch_isa = PROCESSOR_IAMCU;
11153 cpu_arch_isa_flags = iamcu_flags;
11154 if (!cpu_arch_tune_set)
11156 cpu_arch_tune = cpu_arch_isa;
11157 cpu_arch_tune_flags = cpu_arch_isa_flags;
11160 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11161 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11165 as_fatal (_("unknown architecture"));
11167 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11168 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11169 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11170 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11172 switch (OUTPUT_FLAVOR)
11174 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11175 case bfd_target_aout_flavour:
11176 return AOUT_TARGET_FORMAT;
11178 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11179 # if defined (TE_PE) || defined (TE_PEP)
11180 case bfd_target_coff_flavour:
11181 if (flag_code == CODE_64BIT)
11182 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11185 # elif defined (TE_GO32)
11186 case bfd_target_coff_flavour:
11187 return "coff-go32";
11189 case bfd_target_coff_flavour:
11190 return "coff-i386";
11193 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11194 case bfd_target_elf_flavour:
11196 const char *format;
11198 switch (x86_elf_abi)
11201 format = ELF_TARGET_FORMAT;
11204 use_rela_relocations = 1;
11206 format = ELF_TARGET_FORMAT64;
11208 case X86_64_X32_ABI:
11209 use_rela_relocations = 1;
11211 disallow_64bit_reloc = 1;
11212 format = ELF_TARGET_FORMAT32;
11215 if (cpu_arch_isa == PROCESSOR_L1OM)
11217 if (x86_elf_abi != X86_64_ABI)
11218 as_fatal (_("Intel L1OM is 64bit only"));
11219 return ELF_TARGET_L1OM_FORMAT;
11221 else if (cpu_arch_isa == PROCESSOR_K1OM)
11223 if (x86_elf_abi != X86_64_ABI)
11224 as_fatal (_("Intel K1OM is 64bit only"));
11225 return ELF_TARGET_K1OM_FORMAT;
11227 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11229 if (x86_elf_abi != I386_ABI)
11230 as_fatal (_("Intel MCU is 32bit only"));
11231 return ELF_TARGET_IAMCU_FORMAT;
11237 #if defined (OBJ_MACH_O)
11238 case bfd_target_mach_o_flavour:
11239 if (flag_code == CODE_64BIT)
11241 use_rela_relocations = 1;
11243 return "mach-o-x86-64";
11246 return "mach-o-i386";
11254 #endif /* OBJ_MAYBE_ more than one */
11257 md_undefined_symbol (char *name)
11259 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11260 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11261 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11262 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11266 if (symbol_find (name))
11267 as_bad (_("GOT already in symbol table"));
11268 GOT_symbol = symbol_new (name, undefined_section,
11269 (valueT) 0, &zero_address_frag);
11276 /* Round up a section size to the appropriate boundary. */
11279 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11281 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11282 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11284 /* For a.out, force the section size to be aligned. If we don't do
11285 this, BFD will align it for us, but it will not write out the
11286 final bytes of the section. This may be a bug in BFD, but it is
11287 easier to fix it here since that is how the other a.out targets
11291 align = bfd_get_section_alignment (stdoutput, segment);
11292 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11299 /* On the i386, PC-relative offsets are relative to the start of the
11300 next instruction. That is, the address of the offset, plus its
11301 size, since the offset is always the last part of the insn. */
11304 md_pcrel_from (fixS *fixP)
11306 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11312 s_bss (int ignore ATTRIBUTE_UNUSED)
11316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11318 obj_elf_section_change_hook ();
11320 temp = get_absolute_expression ();
11321 subseg_set (bss_section, (subsegT) temp);
11322 demand_empty_rest_of_line ();
11328 i386_validate_fix (fixS *fixp)
11330 if (fixp->fx_subsy)
11332 if (fixp->fx_subsy == GOT_symbol)
11334 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11339 if (fixp->fx_tcbit2)
11340 fixp->fx_r_type = (fixp->fx_tcbit
11341 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11342 : BFD_RELOC_X86_64_GOTPCRELX);
11345 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11350 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11352 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11354 fixp->fx_subsy = 0;
11357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11358 else if (!object_64bit)
11360 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11361 && fixp->fx_tcbit2)
11362 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11368 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11371 bfd_reloc_code_real_type code;
11373 switch (fixp->fx_r_type)
11375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11376 case BFD_RELOC_SIZE32:
11377 case BFD_RELOC_SIZE64:
11378 if (S_IS_DEFINED (fixp->fx_addsy)
11379 && !S_IS_EXTERNAL (fixp->fx_addsy))
11381 /* Resolve size relocation against local symbol to size of
11382 the symbol plus addend. */
11383 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11384 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11385 && !fits_in_unsigned_long (value))
11386 as_bad_where (fixp->fx_file, fixp->fx_line,
11387 _("symbol size computation overflow"));
11388 fixp->fx_addsy = NULL;
11389 fixp->fx_subsy = NULL;
11390 md_apply_fix (fixp, (valueT *) &value, NULL);
11394 /* Fall through. */
11396 case BFD_RELOC_X86_64_PLT32:
11397 case BFD_RELOC_X86_64_GOT32:
11398 case BFD_RELOC_X86_64_GOTPCREL:
11399 case BFD_RELOC_X86_64_GOTPCRELX:
11400 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11401 case BFD_RELOC_386_PLT32:
11402 case BFD_RELOC_386_GOT32:
11403 case BFD_RELOC_386_GOT32X:
11404 case BFD_RELOC_386_GOTOFF:
11405 case BFD_RELOC_386_GOTPC:
11406 case BFD_RELOC_386_TLS_GD:
11407 case BFD_RELOC_386_TLS_LDM:
11408 case BFD_RELOC_386_TLS_LDO_32:
11409 case BFD_RELOC_386_TLS_IE_32:
11410 case BFD_RELOC_386_TLS_IE:
11411 case BFD_RELOC_386_TLS_GOTIE:
11412 case BFD_RELOC_386_TLS_LE_32:
11413 case BFD_RELOC_386_TLS_LE:
11414 case BFD_RELOC_386_TLS_GOTDESC:
11415 case BFD_RELOC_386_TLS_DESC_CALL:
11416 case BFD_RELOC_X86_64_TLSGD:
11417 case BFD_RELOC_X86_64_TLSLD:
11418 case BFD_RELOC_X86_64_DTPOFF32:
11419 case BFD_RELOC_X86_64_DTPOFF64:
11420 case BFD_RELOC_X86_64_GOTTPOFF:
11421 case BFD_RELOC_X86_64_TPOFF32:
11422 case BFD_RELOC_X86_64_TPOFF64:
11423 case BFD_RELOC_X86_64_GOTOFF64:
11424 case BFD_RELOC_X86_64_GOTPC32:
11425 case BFD_RELOC_X86_64_GOT64:
11426 case BFD_RELOC_X86_64_GOTPCREL64:
11427 case BFD_RELOC_X86_64_GOTPC64:
11428 case BFD_RELOC_X86_64_GOTPLT64:
11429 case BFD_RELOC_X86_64_PLTOFF64:
11430 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11431 case BFD_RELOC_X86_64_TLSDESC_CALL:
11432 case BFD_RELOC_RVA:
11433 case BFD_RELOC_VTABLE_ENTRY:
11434 case BFD_RELOC_VTABLE_INHERIT:
11436 case BFD_RELOC_32_SECREL:
11438 code = fixp->fx_r_type;
11440 case BFD_RELOC_X86_64_32S:
11441 if (!fixp->fx_pcrel)
11443 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11444 code = fixp->fx_r_type;
11447 /* Fall through. */
11449 if (fixp->fx_pcrel)
11451 switch (fixp->fx_size)
11454 as_bad_where (fixp->fx_file, fixp->fx_line,
11455 _("can not do %d byte pc-relative relocation"),
11457 code = BFD_RELOC_32_PCREL;
11459 case 1: code = BFD_RELOC_8_PCREL; break;
11460 case 2: code = BFD_RELOC_16_PCREL; break;
11461 case 4: code = BFD_RELOC_32_PCREL; break;
11463 case 8: code = BFD_RELOC_64_PCREL; break;
11469 switch (fixp->fx_size)
11472 as_bad_where (fixp->fx_file, fixp->fx_line,
11473 _("can not do %d byte relocation"),
11475 code = BFD_RELOC_32;
11477 case 1: code = BFD_RELOC_8; break;
11478 case 2: code = BFD_RELOC_16; break;
11479 case 4: code = BFD_RELOC_32; break;
11481 case 8: code = BFD_RELOC_64; break;
11488 if ((code == BFD_RELOC_32
11489 || code == BFD_RELOC_32_PCREL
11490 || code == BFD_RELOC_X86_64_32S)
11492 && fixp->fx_addsy == GOT_symbol)
11495 code = BFD_RELOC_386_GOTPC;
11497 code = BFD_RELOC_X86_64_GOTPC32;
11499 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11501 && fixp->fx_addsy == GOT_symbol)
11503 code = BFD_RELOC_X86_64_GOTPC64;
11506 rel = XNEW (arelent);
11507 rel->sym_ptr_ptr = XNEW (asymbol *);
11508 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11510 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11512 if (!use_rela_relocations)
11514 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11515 vtable entry to be used in the relocation's section offset. */
11516 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11517 rel->address = fixp->fx_offset;
11518 #if defined (OBJ_COFF) && defined (TE_PE)
11519 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11520 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11525 /* Use the rela in 64bit mode. */
11528 if (disallow_64bit_reloc)
11531 case BFD_RELOC_X86_64_DTPOFF64:
11532 case BFD_RELOC_X86_64_TPOFF64:
11533 case BFD_RELOC_64_PCREL:
11534 case BFD_RELOC_X86_64_GOTOFF64:
11535 case BFD_RELOC_X86_64_GOT64:
11536 case BFD_RELOC_X86_64_GOTPCREL64:
11537 case BFD_RELOC_X86_64_GOTPC64:
11538 case BFD_RELOC_X86_64_GOTPLT64:
11539 case BFD_RELOC_X86_64_PLTOFF64:
11540 as_bad_where (fixp->fx_file, fixp->fx_line,
11541 _("cannot represent relocation type %s in x32 mode"),
11542 bfd_get_reloc_code_name (code));
11548 if (!fixp->fx_pcrel)
11549 rel->addend = fixp->fx_offset;
11553 case BFD_RELOC_X86_64_PLT32:
11554 case BFD_RELOC_X86_64_GOT32:
11555 case BFD_RELOC_X86_64_GOTPCREL:
11556 case BFD_RELOC_X86_64_GOTPCRELX:
11557 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11558 case BFD_RELOC_X86_64_TLSGD:
11559 case BFD_RELOC_X86_64_TLSLD:
11560 case BFD_RELOC_X86_64_GOTTPOFF:
11561 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11562 case BFD_RELOC_X86_64_TLSDESC_CALL:
11563 rel->addend = fixp->fx_offset - fixp->fx_size;
11566 rel->addend = (section->vma
11568 + fixp->fx_addnumber
11569 + md_pcrel_from (fixp));
11574 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11575 if (rel->howto == NULL)
11577 as_bad_where (fixp->fx_file, fixp->fx_line,
11578 _("cannot represent relocation type %s"),
11579 bfd_get_reloc_code_name (code));
11580 /* Set howto to a garbage value so that we can keep going. */
11581 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11582 gas_assert (rel->howto != NULL);
11588 #include "tc-i386-intel.c"
11591 tc_x86_parse_to_dw2regnum (expressionS *exp)
11593 int saved_naked_reg;
11594 char saved_register_dot;
11596 saved_naked_reg = allow_naked_reg;
11597 allow_naked_reg = 1;
11598 saved_register_dot = register_chars['.'];
11599 register_chars['.'] = '.';
11600 allow_pseudo_reg = 1;
11601 expression_and_evaluate (exp);
11602 allow_pseudo_reg = 0;
11603 register_chars['.'] = saved_register_dot;
11604 allow_naked_reg = saved_naked_reg;
11606 if (exp->X_op == O_register && exp->X_add_number >= 0)
11608 if ((addressT) exp->X_add_number < i386_regtab_size)
11610 exp->X_op = O_constant;
11611 exp->X_add_number = i386_regtab[exp->X_add_number]
11612 .dw2_regnum[flag_code >> 1];
11615 exp->X_op = O_illegal;
11620 tc_x86_frame_initial_instructions (void)
11622 static unsigned int sp_regno[2];
11624 if (!sp_regno[flag_code >> 1])
11626 char *saved_input = input_line_pointer;
11627 char sp[][4] = {"esp", "rsp"};
11630 input_line_pointer = sp[flag_code >> 1];
11631 tc_x86_parse_to_dw2regnum (&exp);
11632 gas_assert (exp.X_op == O_constant);
11633 sp_regno[flag_code >> 1] = exp.X_add_number;
11634 input_line_pointer = saved_input;
11637 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11638 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11642 x86_dwarf2_addr_size (void)
11644 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11645 if (x86_elf_abi == X86_64_X32_ABI)
11648 return bfd_arch_bits_per_address (stdoutput) / 8;
11652 i386_elf_section_type (const char *str, size_t len)
11654 if (flag_code == CODE_64BIT
11655 && len == sizeof ("unwind") - 1
11656 && strncmp (str, "unwind", 6) == 0)
11657 return SHT_X86_64_UNWIND;
11664 i386_solaris_fix_up_eh_frame (segT sec)
11666 if (flag_code == CODE_64BIT)
11667 elf_section_type (sec) = SHT_X86_64_UNWIND;
11673 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11677 exp.X_op = O_secrel;
11678 exp.X_add_symbol = symbol;
11679 exp.X_add_number = 0;
11680 emit_expr (&exp, size);
11684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11685 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11688 x86_64_section_letter (int letter, const char **ptr_msg)
11690 if (flag_code == CODE_64BIT)
11693 return SHF_X86_64_LARGE;
11695 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11698 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11703 x86_64_section_word (char *str, size_t len)
11705 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11706 return SHF_X86_64_LARGE;
11712 handle_large_common (int small ATTRIBUTE_UNUSED)
11714 if (flag_code != CODE_64BIT)
11716 s_comm_internal (0, elf_common_parse);
11717 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11721 static segT lbss_section;
11722 asection *saved_com_section_ptr = elf_com_section_ptr;
11723 asection *saved_bss_section = bss_section;
11725 if (lbss_section == NULL)
11727 flagword applicable;
11728 segT seg = now_seg;
11729 subsegT subseg = now_subseg;
11731 /* The .lbss section is for local .largecomm symbols. */
11732 lbss_section = subseg_new (".lbss", 0);
11733 applicable = bfd_applicable_section_flags (stdoutput);
11734 bfd_set_section_flags (stdoutput, lbss_section,
11735 applicable & SEC_ALLOC);
11736 seg_info (lbss_section)->bss = 1;
11738 subseg_set (seg, subseg);
11741 elf_com_section_ptr = &_bfd_elf_large_com_section;
11742 bss_section = lbss_section;
11744 s_comm_internal (0, elf_common_parse);
11746 elf_com_section_ptr = saved_com_section_ptr;
11747 bss_section = saved_bss_section;
11750 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */