1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcodes/i386-opc.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry *parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry *build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS *, offsetT);
96 static void output_disp (fragS *, offsetT);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED);
104 static const char *default_arch = DEFAULT_ARCH;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry *regs;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 unsigned int types[MAX_OPERANDS];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op[MAX_OPERANDS];
141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry *seg[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars = "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars = "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars[] = "#/";
213 const char line_separator_chars[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars[256];
226 static char register_chars[256];
227 static char operand_chars[256];
228 static char identifier_chars[256];
229 static char digit_chars[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack[32];
247 static char *save_stack_p;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates *current_templates;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
263 /* Current operand we are working on. */
264 static int this_operand;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code;
276 static unsigned int object_64bit;
277 static int use_rela_relocations = 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names[] =
287 /* 1 for intel syntax,
289 static int intel_syntax = 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg = 0;
294 /* Register prefix used for error message. */
295 static const char *register_prefix = "%";
297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300 static char stackop_size = '\0';
302 /* Non-zero to optimize code alignment. */
303 int optimize_align_code = 1;
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings = 0;
309 static const char *cpu_arch_name = NULL;
310 static const char *cpu_sub_arch_name = NULL;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
315 /* If we have selected a cpu we are generating instructions for. */
316 static int cpu_arch_tune_set = 0;
318 /* Cpu we are generating instructions for. */
319 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321 /* CPU feature flags of cpu we are generating instructions for. */
322 static unsigned int cpu_arch_tune_flags = 0;
324 /* CPU instruction set architecture used. */
325 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of instruction set architecture used. */
328 static unsigned int cpu_arch_isa_flags = 0;
330 /* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332 static unsigned int no_cond_jump_promotion = 0;
334 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
335 static symbolS *GOT_symbol;
337 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
338 unsigned int x86_dwarf2_return_column;
340 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341 int x86_cie_data_alignment;
343 /* Interface to relax_segment.
344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
349 #define UNCOND_JUMP 0
351 #define COND_JUMP86 2
356 #define SMALL16 (SMALL | CODE16)
358 #define BIG16 (BIG | CODE16)
362 #define INLINE __inline__
368 #define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370 #define TYPE_FROM_RELAX_STATE(s) \
372 #define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
375 /* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
383 const relax_typeS md_relax_table[] =
386 1) most positive reach of this state,
387 2) most negative reach of this state,
388 3) how many bytes this mode will have in the variable part of the frag
389 4) which index into the table to try if we can't fit into this one. */
391 /* UNCOND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 3 bytes to frag:
408 1 extra opcode byte, 2 displacement bytes. */
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
422 static const arch_entry cpu_arch[] =
424 {"generic32", PROCESSOR_GENERIC32,
425 Cpu186|Cpu286|Cpu386},
426 {"generic64", PROCESSOR_GENERIC64,
427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
431 {"i186", PROCESSOR_UNKNOWN,
433 {"i286", PROCESSOR_UNKNOWN,
435 {"i386", PROCESSOR_GENERIC32,
436 Cpu186|Cpu286|Cpu386},
437 {"i486", PROCESSOR_I486,
438 Cpu186|Cpu286|Cpu386|Cpu486},
439 {"i586", PROCESSOR_PENTIUM,
440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
441 {"i686", PROCESSOR_PENTIUMPRO,
442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
443 {"pentium", PROCESSOR_PENTIUM,
444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
447 {"pentiumii", PROCESSOR_PENTIUMPRO,
448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
451 {"pentium4", PROCESSOR_PENTIUM4,
452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
460 {"yonah", PROCESSOR_CORE,
461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
463 {"core", PROCESSOR_CORE,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
474 {"k6_2", PROCESSOR_K6,
475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
476 {"athlon", PROCESSOR_ATHLON,
477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"amdfam10", PROCESSOR_AMDFAM10,
489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
492 {".mmx", PROCESSOR_UNKNOWN,
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
502 {".3dnow", PROCESSOR_UNKNOWN,
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
508 {".pacifica", PROCESSOR_UNKNOWN,
510 {".svme", PROCESSOR_UNKNOWN,
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
550 {"secrel32", pe_directive_secrel, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control *op_hash;
561 /* Hash table for register lookup. */
562 static struct hash_control *reg_hash;
565 i386_align_code (fragS *fragP, int count)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1[] =
572 static const char f32_2[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
629 static const char *const f16_patt[] = {
630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
634 static const char alt_3[] =
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
738 if (count <= 0 || count > 15)
741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
747 0x66 prefix will be used.
748 3. For PROCESSOR_CORE2, alt_long_patt will be used.
749 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
750 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
751 and PROCESSOR_GENERIC64, alt_short_patt will be used.
753 When -mtune= isn't used, alt_short_patt will be used if
754 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
759 if (flag_code == CODE_16BIT)
761 memcpy (fragP->fr_literal + fragP->fr_fix,
762 f16_patt[count - 1], count);
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
767 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
770 int nnops = (count + 3) / 4;
771 int len = count / nnops;
772 int remains = count - nnops * len;
775 /* The recommended way to pad 64bit code is to use NOPs preceded
776 by maximally four 0x66 prefixes. Balance the size of nops. */
777 for (i = 0; i < remains; i++)
779 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
780 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
783 for (; i < nnops; i++)
785 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
786 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 const char *const *patt = NULL;
794 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
796 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
797 switch (cpu_arch_tune)
799 case PROCESSOR_UNKNOWN:
800 /* We use cpu_arch_isa_flags to check if we SHOULD
801 optimize for Cpu686. */
802 if ((cpu_arch_isa_flags & Cpu686) != 0)
803 patt = alt_short_patt;
807 case PROCESSOR_CORE2:
808 patt = alt_long_patt;
810 case PROCESSOR_PENTIUMPRO:
811 case PROCESSOR_PENTIUM4:
812 case PROCESSOR_NOCONA:
815 case PROCESSOR_ATHLON:
817 case PROCESSOR_GENERIC64:
818 case PROCESSOR_AMDFAM10:
819 patt = alt_short_patt;
822 case PROCESSOR_PENTIUM:
823 case PROCESSOR_GENERIC32:
830 switch (cpu_arch_tune)
832 case PROCESSOR_UNKNOWN:
833 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
834 PROCESSOR_UNKNOWN. */
839 case PROCESSOR_PENTIUM:
840 case PROCESSOR_PENTIUMPRO:
841 case PROCESSOR_PENTIUM4:
842 case PROCESSOR_NOCONA:
845 case PROCESSOR_ATHLON:
847 case PROCESSOR_AMDFAM10:
848 case PROCESSOR_GENERIC32:
849 /* We use cpu_arch_isa_flags to check if we CAN optimize
851 if ((cpu_arch_isa_flags & Cpu686) != 0)
852 patt = alt_short_patt;
856 case PROCESSOR_CORE2:
857 if ((cpu_arch_isa_flags & Cpu686) != 0)
858 patt = alt_long_patt;
862 case PROCESSOR_GENERIC64:
863 patt = alt_short_patt;
868 memcpy (fragP->fr_literal + fragP->fr_fix,
869 patt[count - 1], count);
871 fragP->fr_var = count;
874 static INLINE unsigned int
875 mode_from_disp_size (unsigned int t)
877 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
881 fits_in_signed_byte (offsetT num)
883 return (num >= -128) && (num <= 127);
887 fits_in_unsigned_byte (offsetT num)
889 return (num & 0xff) == num;
893 fits_in_unsigned_word (offsetT num)
895 return (num & 0xffff) == num;
899 fits_in_signed_word (offsetT num)
901 return (-32768 <= num) && (num <= 32767);
905 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
910 return (!(((offsetT) -1 << 31) & num)
911 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
913 } /* fits_in_signed_long() */
916 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
921 return (num & (((offsetT) 2 << 31) - 1)) == num;
923 } /* fits_in_unsigned_long() */
926 smallest_imm_type (offsetT num)
928 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
930 /* This code is disabled on the 486 because all the Imm1 forms
931 in the opcode table are slower on the i486. They're the
932 versions with the implicitly specified single-position
933 displacement, which has another syntax if you really want to
936 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
938 return (fits_in_signed_byte (num)
939 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
940 : fits_in_unsigned_byte (num)
941 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
942 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
943 ? (Imm16 | Imm32 | Imm32S | Imm64)
944 : fits_in_signed_long (num)
945 ? (Imm32 | Imm32S | Imm64)
946 : fits_in_unsigned_long (num)
952 offset_in_range (offsetT val, int size)
958 case 1: mask = ((addressT) 1 << 8) - 1; break;
959 case 2: mask = ((addressT) 1 << 16) - 1; break;
960 case 4: mask = ((addressT) 2 << 31) - 1; break;
962 case 8: mask = ((addressT) 2 << 63) - 1; break;
967 /* If BFD64, sign extend val. */
968 if (!use_rela_relocations)
969 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
970 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
972 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
974 char buf1[40], buf2[40];
976 sprint_value (buf1, val);
977 sprint_value (buf2, val & mask);
978 as_warn (_("%s shortened to %s"), buf1, buf2);
983 /* Returns 0 if attempting to add a prefix where one from the same
984 class already exists, 1 if non rep/repne added, 2 if rep/repne
987 add_prefix (unsigned int prefix)
992 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
993 && flag_code == CODE_64BIT)
995 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
996 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
997 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1008 case CS_PREFIX_OPCODE:
1009 case DS_PREFIX_OPCODE:
1010 case ES_PREFIX_OPCODE:
1011 case FS_PREFIX_OPCODE:
1012 case GS_PREFIX_OPCODE:
1013 case SS_PREFIX_OPCODE:
1017 case REPNE_PREFIX_OPCODE:
1018 case REPE_PREFIX_OPCODE:
1021 case LOCK_PREFIX_OPCODE:
1029 case ADDR_PREFIX_OPCODE:
1033 case DATA_PREFIX_OPCODE:
1037 if (i.prefix[q] != 0)
1045 i.prefix[q] |= prefix;
1048 as_bad (_("same type of prefix used twice"));
1054 set_code_flag (int value)
1057 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1058 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1059 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1061 as_bad (_("64bit mode not supported on this CPU."));
1063 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1065 as_bad (_("32bit mode not supported on this CPU."));
1067 stackop_size = '\0';
1071 set_16bit_gcc_code_flag (int new_code_flag)
1073 flag_code = new_code_flag;
1074 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1075 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1076 stackop_size = LONG_MNEM_SUFFIX;
1080 set_intel_syntax (int syntax_flag)
1082 /* Find out if register prefixing is specified. */
1083 int ask_naked_reg = 0;
1086 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1088 char *string = input_line_pointer;
1089 int e = get_symbol_end ();
1091 if (strcmp (string, "prefix") == 0)
1093 else if (strcmp (string, "noprefix") == 0)
1096 as_bad (_("bad argument to syntax directive."));
1097 *input_line_pointer = e;
1099 demand_empty_rest_of_line ();
1101 intel_syntax = syntax_flag;
1103 if (ask_naked_reg == 0)
1104 allow_naked_reg = (intel_syntax
1105 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1107 allow_naked_reg = (ask_naked_reg < 0);
1109 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1110 identifier_chars['$'] = intel_syntax ? '$' : 0;
1111 register_prefix = allow_naked_reg ? "" : "%";
1115 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1119 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1121 char *string = input_line_pointer;
1122 int e = get_symbol_end ();
1125 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1127 if (strcmp (string, cpu_arch[i].name) == 0)
1131 cpu_arch_name = cpu_arch[i].name;
1132 cpu_sub_arch_name = NULL;
1133 cpu_arch_flags = (cpu_arch[i].flags
1134 | (flag_code == CODE_64BIT
1135 ? Cpu64 : CpuNo64));
1136 cpu_arch_isa = cpu_arch[i].type;
1137 cpu_arch_isa_flags = cpu_arch[i].flags;
1138 if (!cpu_arch_tune_set)
1140 cpu_arch_tune = cpu_arch_isa;
1141 cpu_arch_tune_flags = cpu_arch_isa_flags;
1145 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1147 cpu_sub_arch_name = cpu_arch[i].name;
1148 cpu_arch_flags |= cpu_arch[i].flags;
1150 *input_line_pointer = e;
1151 demand_empty_rest_of_line ();
1155 if (i >= ARRAY_SIZE (cpu_arch))
1156 as_bad (_("no such architecture: `%s'"), string);
1158 *input_line_pointer = e;
1161 as_bad (_("missing cpu architecture"));
1163 no_cond_jump_promotion = 0;
1164 if (*input_line_pointer == ','
1165 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1167 char *string = ++input_line_pointer;
1168 int e = get_symbol_end ();
1170 if (strcmp (string, "nojumps") == 0)
1171 no_cond_jump_promotion = 1;
1172 else if (strcmp (string, "jumps") == 0)
1175 as_bad (_("no such architecture modifier: `%s'"), string);
1177 *input_line_pointer = e;
1180 demand_empty_rest_of_line ();
1186 if (!strcmp (default_arch, "x86_64"))
1187 return bfd_mach_x86_64;
1188 else if (!strcmp (default_arch, "i386"))
1189 return bfd_mach_i386_i386;
1191 as_fatal (_("Unknown architecture"));
1197 const char *hash_err;
1199 /* Initialize op_hash hash table. */
1200 op_hash = hash_new ();
1203 const template *optab;
1204 templates *core_optab;
1206 /* Setup for loop. */
1208 core_optab = (templates *) xmalloc (sizeof (templates));
1209 core_optab->start = optab;
1214 if (optab->name == NULL
1215 || strcmp (optab->name, (optab - 1)->name) != 0)
1217 /* different name --> ship out current template list;
1218 add to hash table; & begin anew. */
1219 core_optab->end = optab;
1220 hash_err = hash_insert (op_hash,
1225 as_fatal (_("Internal Error: Can't hash %s: %s"),
1229 if (optab->name == NULL)
1231 core_optab = (templates *) xmalloc (sizeof (templates));
1232 core_optab->start = optab;
1237 /* Initialize reg_hash hash table. */
1238 reg_hash = hash_new ();
1240 const reg_entry *regtab;
1241 unsigned int regtab_size = i386_regtab_size;
1243 for (regtab = i386_regtab; regtab_size--; regtab++)
1245 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1258 for (c = 0; c < 256; c++)
1263 mnemonic_chars[c] = c;
1264 register_chars[c] = c;
1265 operand_chars[c] = c;
1267 else if (ISLOWER (c))
1269 mnemonic_chars[c] = c;
1270 register_chars[c] = c;
1271 operand_chars[c] = c;
1273 else if (ISUPPER (c))
1275 mnemonic_chars[c] = TOLOWER (c);
1276 register_chars[c] = mnemonic_chars[c];
1277 operand_chars[c] = c;
1280 if (ISALPHA (c) || ISDIGIT (c))
1281 identifier_chars[c] = c;
1284 identifier_chars[c] = c;
1285 operand_chars[c] = c;
1290 identifier_chars['@'] = '@';
1293 identifier_chars['?'] = '?';
1294 operand_chars['?'] = '?';
1296 digit_chars['-'] = '-';
1297 mnemonic_chars['-'] = '-';
1298 identifier_chars['_'] = '_';
1299 identifier_chars['.'] = '.';
1301 for (p = operand_special_chars; *p != '\0'; p++)
1302 operand_chars[(unsigned char) *p] = *p;
1305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1308 record_alignment (text_section, 2);
1309 record_alignment (data_section, 2);
1310 record_alignment (bss_section, 2);
1314 if (flag_code == CODE_64BIT)
1316 x86_dwarf2_return_column = 16;
1317 x86_cie_data_alignment = -8;
1321 x86_dwarf2_return_column = 8;
1322 x86_cie_data_alignment = -4;
1327 i386_print_statistics (FILE *file)
1329 hash_print_statistics (file, "i386 opcode", op_hash);
1330 hash_print_statistics (file, "i386 register", reg_hash);
1335 /* Debugging routines for md_assemble. */
1336 static void pte (template *);
1337 static void pt (unsigned int);
1338 static void pe (expressionS *);
1339 static void ps (symbolS *);
1342 pi (char *line, i386_insn *x)
1346 fprintf (stdout, "%s: template ", line);
1348 fprintf (stdout, " address: base %s index %s scale %x\n",
1349 x->base_reg ? x->base_reg->reg_name : "none",
1350 x->index_reg ? x->index_reg->reg_name : "none",
1351 x->log2_scale_factor);
1352 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1353 x->rm.mode, x->rm.reg, x->rm.regmem);
1354 fprintf (stdout, " sib: base %x index %x scale %x\n",
1355 x->sib.base, x->sib.index, x->sib.scale);
1356 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1357 (x->rex & REX_MODE64) != 0,
1358 (x->rex & REX_EXTX) != 0,
1359 (x->rex & REX_EXTY) != 0,
1360 (x->rex & REX_EXTZ) != 0);
1361 for (i = 0; i < x->operands; i++)
1363 fprintf (stdout, " #%d: ", i + 1);
1365 fprintf (stdout, "\n");
1367 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1368 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1369 if (x->types[i] & Imm)
1371 if (x->types[i] & Disp)
1372 pe (x->op[i].disps);
1380 fprintf (stdout, " %d operands ", t->operands);
1381 fprintf (stdout, "opcode %x ", t->base_opcode);
1382 if (t->extension_opcode != None)
1383 fprintf (stdout, "ext %x ", t->extension_opcode);
1384 if (t->opcode_modifier & D)
1385 fprintf (stdout, "D");
1386 if (t->opcode_modifier & W)
1387 fprintf (stdout, "W");
1388 fprintf (stdout, "\n");
1389 for (i = 0; i < t->operands; i++)
1391 fprintf (stdout, " #%d type ", i + 1);
1392 pt (t->operand_types[i]);
1393 fprintf (stdout, "\n");
1400 fprintf (stdout, " operation %d\n", e->X_op);
1401 fprintf (stdout, " add_number %ld (%lx)\n",
1402 (long) e->X_add_number, (long) e->X_add_number);
1403 if (e->X_add_symbol)
1405 fprintf (stdout, " add_symbol ");
1406 ps (e->X_add_symbol);
1407 fprintf (stdout, "\n");
1411 fprintf (stdout, " op_symbol ");
1412 ps (e->X_op_symbol);
1413 fprintf (stdout, "\n");
1420 fprintf (stdout, "%s type %s%s",
1422 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1423 segment_name (S_GET_SEGMENT (s)));
1426 static struct type_name
1431 const type_names[] =
1444 { BaseIndex, "BaseIndex" },
1448 { Disp32S, "d32s" },
1450 { InOutPortReg, "InOutPortReg" },
1451 { ShiftCount, "ShiftCount" },
1452 { Control, "control reg" },
1453 { Test, "test reg" },
1454 { Debug, "debug reg" },
1455 { FloatReg, "FReg" },
1456 { FloatAcc, "FAcc" },
1460 { JumpAbsolute, "Jump Absolute" },
1471 const struct type_name *ty;
1473 for (ty = type_names; ty->mask; ty++)
1475 fprintf (stdout, "%s, ", ty->tname);
1479 #endif /* DEBUG386 */
1481 static bfd_reloc_code_real_type
1482 reloc (unsigned int size,
1485 bfd_reloc_code_real_type other)
1487 if (other != NO_RELOC)
1489 reloc_howto_type *reloc;
1494 case BFD_RELOC_X86_64_GOT32:
1495 return BFD_RELOC_X86_64_GOT64;
1497 case BFD_RELOC_X86_64_PLTOFF64:
1498 return BFD_RELOC_X86_64_PLTOFF64;
1500 case BFD_RELOC_X86_64_GOTPC32:
1501 other = BFD_RELOC_X86_64_GOTPC64;
1503 case BFD_RELOC_X86_64_GOTPCREL:
1504 other = BFD_RELOC_X86_64_GOTPCREL64;
1506 case BFD_RELOC_X86_64_TPOFF32:
1507 other = BFD_RELOC_X86_64_TPOFF64;
1509 case BFD_RELOC_X86_64_DTPOFF32:
1510 other = BFD_RELOC_X86_64_DTPOFF64;
1516 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1517 if (size == 4 && flag_code != CODE_64BIT)
1520 reloc = bfd_reloc_type_lookup (stdoutput, other);
1522 as_bad (_("unknown relocation (%u)"), other);
1523 else if (size != bfd_get_reloc_size (reloc))
1524 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1525 bfd_get_reloc_size (reloc),
1527 else if (pcrel && !reloc->pc_relative)
1528 as_bad (_("non-pc-relative relocation for pc-relative field"));
1529 else if ((reloc->complain_on_overflow == complain_overflow_signed
1531 || (reloc->complain_on_overflow == complain_overflow_unsigned
1533 as_bad (_("relocated field and relocation type differ in signedness"));
1542 as_bad (_("there are no unsigned pc-relative relocations"));
1545 case 1: return BFD_RELOC_8_PCREL;
1546 case 2: return BFD_RELOC_16_PCREL;
1547 case 4: return BFD_RELOC_32_PCREL;
1548 case 8: return BFD_RELOC_64_PCREL;
1550 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1557 case 4: return BFD_RELOC_X86_64_32S;
1562 case 1: return BFD_RELOC_8;
1563 case 2: return BFD_RELOC_16;
1564 case 4: return BFD_RELOC_32;
1565 case 8: return BFD_RELOC_64;
1567 as_bad (_("cannot do %s %u byte relocation"),
1568 sign > 0 ? "signed" : "unsigned", size);
1572 return BFD_RELOC_NONE;
1575 /* Here we decide which fixups can be adjusted to make them relative to
1576 the beginning of the section instead of the symbol. Basically we need
1577 to make sure that the dynamic relocations are done correctly, so in
1578 some cases we force the original symbol to be used. */
1581 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
1583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1587 /* Don't adjust pc-relative references to merge sections in 64-bit
1589 if (use_rela_relocations
1590 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1594 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1595 and changed later by validate_fix. */
1596 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1597 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1600 /* adjust_reloc_syms doesn't know about the GOT. */
1601 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1602 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1603 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1616 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1626 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1628 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1635 intel_float_operand (const char *mnemonic)
1637 /* Note that the value returned is meaningful only for opcodes with (memory)
1638 operands, hence the code here is free to improperly handle opcodes that
1639 have no operands (for better performance and smaller code). */
1641 if (mnemonic[0] != 'f')
1642 return 0; /* non-math */
1644 switch (mnemonic[1])
1646 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1647 the fs segment override prefix not currently handled because no
1648 call path can make opcodes without operands get here */
1650 return 2 /* integer op */;
1652 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1653 return 3; /* fldcw/fldenv */
1656 if (mnemonic[2] != 'o' /* fnop */)
1657 return 3; /* non-waiting control op */
1660 if (mnemonic[2] == 's')
1661 return 3; /* frstor/frstpm */
1664 if (mnemonic[2] == 'a')
1665 return 3; /* fsave */
1666 if (mnemonic[2] == 't')
1668 switch (mnemonic[3])
1670 case 'c': /* fstcw */
1671 case 'd': /* fstdw */
1672 case 'e': /* fstenv */
1673 case 's': /* fsts[gw] */
1679 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1680 return 0; /* fxsave/fxrstor are not really math ops */
1687 /* This is the guts of the machine-dependent assembler. LINE points to a
1688 machine dependent instruction. This function is supposed to emit
1689 the frags/bytes it assembles to. */
1696 char mnemonic[MAX_MNEM_SIZE];
1698 /* Initialize globals. */
1699 memset (&i, '\0', sizeof (i));
1700 for (j = 0; j < MAX_OPERANDS; j++)
1701 i.reloc[j] = NO_RELOC;
1702 memset (disp_expressions, '\0', sizeof (disp_expressions));
1703 memset (im_expressions, '\0', sizeof (im_expressions));
1704 save_stack_p = save_stack;
1706 /* First parse an instruction mnemonic & call i386_operand for the operands.
1707 We assume that the scrubber has arranged it so that line[0] is the valid
1708 start of a (possibly prefixed) mnemonic. */
1710 line = parse_insn (line, mnemonic);
1714 line = parse_operands (line, mnemonic);
1718 /* The order of the immediates should be reversed
1719 for 2 immediates extrq and insertq instructions */
1720 if ((i.imm_operands == 2)
1721 && ((strcmp (mnemonic, "extrq") == 0)
1722 || (strcmp (mnemonic, "insertq") == 0)))
1724 swap_2_operands (0, 1);
1725 /* "extrq" and insertq" are the only two instructions whose operands
1726 have to be reversed even though they have two immediate operands.
1732 /* Now we've parsed the mnemonic into a set of templates, and have the
1733 operands at hand. */
1735 /* All intel opcodes have reversed operands except for "bound" and
1736 "enter". We also don't reverse intersegment "jmp" and "call"
1737 instructions with 2 immediate operands so that the immediate segment
1738 precedes the offset, as it does when in AT&T mode. */
1741 && (strcmp (mnemonic, "bound") != 0)
1742 && (strcmp (mnemonic, "invlpga") != 0)
1743 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1749 /* Don't optimize displacement for movabs since it only takes 64bit
1752 && (flag_code != CODE_64BIT
1753 || strcmp (mnemonic, "movabs") != 0))
1756 /* Next, we find a template that matches the given insn,
1757 making sure the overlap of the given operands types is consistent
1758 with the template operand types. */
1760 if (!match_template ())
1765 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1767 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1768 i.tm.base_opcode ^= Opcode_FloatR;
1770 /* Zap movzx and movsx suffix. The suffix may have been set from
1771 "word ptr" or "byte ptr" on the source operand, but we'll use
1772 the suffix later to choose the destination register. */
1773 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1775 if (i.reg_operands < 2
1777 && (~i.tm.opcode_modifier
1784 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1790 if (i.tm.opcode_modifier & FWait)
1791 if (!add_prefix (FWAIT_OPCODE))
1794 /* Check string instruction segment overrides. */
1795 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1797 if (!check_string ())
1801 if (!process_suffix ())
1804 /* Make still unresolved immediate matches conform to size of immediate
1805 given in i.suffix. */
1806 if (!finalize_imm ())
1809 if (i.types[0] & Imm1)
1810 i.imm_operands = 0; /* kludge for shift insns. */
1811 if (i.types[0] & ImplicitRegister)
1813 if (i.types[1] & ImplicitRegister)
1815 if (i.types[2] & ImplicitRegister)
1818 if (i.tm.opcode_modifier & ImmExt)
1822 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1824 /* Streaming SIMD extensions 3 Instructions have the fixed
1825 operands with an opcode suffix which is coded in the same
1826 place as an 8-bit immediate field would be. Here we check
1827 those operands and remove them afterwards. */
1830 for (x = 0; x < i.operands; x++)
1831 if (i.op[x].regs->reg_num != x)
1832 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1833 i.op[x].regs->reg_name, x + 1, i.tm.name);
1837 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1838 opcode suffix which is coded in the same place as an 8-bit
1839 immediate field would be. Here we fake an 8-bit immediate
1840 operand from the opcode suffix stored in tm.extension_opcode. */
1842 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1844 exp = &im_expressions[i.imm_operands++];
1845 i.op[i.operands].imms = exp;
1846 i.types[i.operands++] = Imm8;
1847 exp->X_op = O_constant;
1848 exp->X_add_number = i.tm.extension_opcode;
1849 i.tm.extension_opcode = None;
1852 /* For insns with operands there are more diddles to do to the opcode. */
1855 if (!process_operands ())
1858 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1860 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1861 as_warn (_("translating to `%sp'"), i.tm.name);
1864 /* Handle conversion of 'int $3' --> special int3 insn. */
1865 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1867 i.tm.base_opcode = INT3_OPCODE;
1871 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1872 && i.op[0].disps->X_op == O_constant)
1874 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1875 the absolute address given by the constant. Since ix86 jumps and
1876 calls are pc relative, we need to generate a reloc. */
1877 i.op[0].disps->X_add_symbol = &abs_symbol;
1878 i.op[0].disps->X_op = O_symbol;
1881 if ((i.tm.opcode_modifier & Rex64) != 0)
1882 i.rex |= REX_MODE64;
1884 /* For 8 bit registers we need an empty rex prefix. Also if the
1885 instruction already has a prefix, we need to convert old
1886 registers to new ones. */
1888 if (((i.types[0] & Reg8) != 0
1889 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1890 || ((i.types[1] & Reg8) != 0
1891 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1892 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1897 i.rex |= REX_OPCODE;
1898 for (x = 0; x < 2; x++)
1900 /* Look for 8 bit operand that uses old registers. */
1901 if ((i.types[x] & Reg8) != 0
1902 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1904 /* In case it is "hi" register, give up. */
1905 if (i.op[x].regs->reg_num > 3)
1906 as_bad (_("can't encode register '%%%s' in an "
1907 "instruction requiring REX prefix."),
1908 i.op[x].regs->reg_name);
1910 /* Otherwise it is equivalent to the extended register.
1911 Since the encoding doesn't change this is merely
1912 cosmetic cleanup for debug output. */
1914 i.op[x].regs = i.op[x].regs + 8;
1920 add_prefix (REX_OPCODE | i.rex);
1922 /* We are ready to output the insn. */
1927 parse_insn (char *line, char *mnemonic)
1930 char *token_start = l;
1935 /* Non-zero if we found a prefix only acceptable with string insns. */
1936 const char *expecting_string_instruction = NULL;
1941 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1944 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1946 as_bad (_("no such instruction: `%s'"), token_start);
1951 if (!is_space_char (*l)
1952 && *l != END_OF_INSN
1954 || (*l != PREFIX_SEPARATOR
1957 as_bad (_("invalid character %s in mnemonic"),
1958 output_invalid (*l));
1961 if (token_start == l)
1963 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1964 as_bad (_("expecting prefix; got nothing"));
1966 as_bad (_("expecting mnemonic; got nothing"));
1970 /* Look up instruction (or prefix) via hash table. */
1971 current_templates = hash_find (op_hash, mnemonic);
1973 if (*l != END_OF_INSN
1974 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1975 && current_templates
1976 && (current_templates->start->opcode_modifier & IsPrefix))
1978 if (current_templates->start->cpu_flags
1979 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1981 as_bad ((flag_code != CODE_64BIT
1982 ? _("`%s' is only supported in 64-bit mode")
1983 : _("`%s' is not supported in 64-bit mode")),
1984 current_templates->start->name);
1987 /* If we are in 16-bit mode, do not allow addr16 or data16.
1988 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1989 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1990 && flag_code != CODE_64BIT
1991 && (((current_templates->start->opcode_modifier & Size32) != 0)
1992 ^ (flag_code == CODE_16BIT)))
1994 as_bad (_("redundant %s prefix"),
1995 current_templates->start->name);
1998 /* Add prefix, checking for repeated prefixes. */
1999 switch (add_prefix (current_templates->start->base_opcode))
2004 expecting_string_instruction = current_templates->start->name;
2007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2014 if (!current_templates)
2016 /* See if we can get a match by trimming off a suffix. */
2019 case WORD_MNEM_SUFFIX:
2020 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2021 i.suffix = SHORT_MNEM_SUFFIX;
2023 case BYTE_MNEM_SUFFIX:
2024 case QWORD_MNEM_SUFFIX:
2025 i.suffix = mnem_p[-1];
2027 current_templates = hash_find (op_hash, mnemonic);
2029 case SHORT_MNEM_SUFFIX:
2030 case LONG_MNEM_SUFFIX:
2033 i.suffix = mnem_p[-1];
2035 current_templates = hash_find (op_hash, mnemonic);
2043 if (intel_float_operand (mnemonic) == 1)
2044 i.suffix = SHORT_MNEM_SUFFIX;
2046 i.suffix = LONG_MNEM_SUFFIX;
2048 current_templates = hash_find (op_hash, mnemonic);
2052 if (!current_templates)
2054 as_bad (_("no such instruction: `%s'"), token_start);
2059 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2061 /* Check for a branch hint. We allow ",pt" and ",pn" for
2062 predict taken and predict not taken respectively.
2063 I'm not sure that branch hints actually do anything on loop
2064 and jcxz insns (JumpByte) for current Pentium4 chips. They
2065 may work in the future and it doesn't hurt to accept them
2067 if (l[0] == ',' && l[1] == 'p')
2071 if (!add_prefix (DS_PREFIX_OPCODE))
2075 else if (l[2] == 'n')
2077 if (!add_prefix (CS_PREFIX_OPCODE))
2083 /* Any other comma loses. */
2086 as_bad (_("invalid character %s in mnemonic"),
2087 output_invalid (*l));
2091 /* Check if instruction is supported on specified architecture. */
2093 for (t = current_templates->start; t < current_templates->end; ++t)
2095 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2096 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2098 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2101 if (!(supported & 2))
2103 as_bad (flag_code == CODE_64BIT
2104 ? _("`%s' is not supported in 64-bit mode")
2105 : _("`%s' is only supported in 64-bit mode"),
2106 current_templates->start->name);
2109 if (!(supported & 1))
2111 as_warn (_("`%s' is not supported on `%s%s'"),
2112 current_templates->start->name,
2114 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2116 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2118 as_warn (_("use .code16 to ensure correct addressing mode"));
2121 /* Check for rep/repne without a string instruction. */
2122 if (expecting_string_instruction)
2124 static templates override;
2126 for (t = current_templates->start; t < current_templates->end; ++t)
2127 if (t->opcode_modifier & IsString)
2129 if (t >= current_templates->end)
2131 as_bad (_("expecting string instruction after `%s'"),
2132 expecting_string_instruction);
2135 for (override.start = t; t < current_templates->end; ++t)
2136 if (!(t->opcode_modifier & IsString))
2139 current_templates = &override;
2146 parse_operands (char *l, const char *mnemonic)
2150 /* 1 if operand is pending after ','. */
2151 unsigned int expecting_operand = 0;
2153 /* Non-zero if operand parens not balanced. */
2154 unsigned int paren_not_balanced;
2156 while (*l != END_OF_INSN)
2158 /* Skip optional white space before operand. */
2159 if (is_space_char (*l))
2161 if (!is_operand_char (*l) && *l != END_OF_INSN)
2163 as_bad (_("invalid character %s before operand %d"),
2164 output_invalid (*l),
2168 token_start = l; /* after white space */
2169 paren_not_balanced = 0;
2170 while (paren_not_balanced || *l != ',')
2172 if (*l == END_OF_INSN)
2174 if (paren_not_balanced)
2177 as_bad (_("unbalanced parenthesis in operand %d."),
2180 as_bad (_("unbalanced brackets in operand %d."),
2185 break; /* we are done */
2187 else if (!is_operand_char (*l) && !is_space_char (*l))
2189 as_bad (_("invalid character %s in operand %d"),
2190 output_invalid (*l),
2197 ++paren_not_balanced;
2199 --paren_not_balanced;
2204 ++paren_not_balanced;
2206 --paren_not_balanced;
2210 if (l != token_start)
2211 { /* Yes, we've read in another operand. */
2212 unsigned int operand_ok;
2213 this_operand = i.operands++;
2214 if (i.operands > MAX_OPERANDS)
2216 as_bad (_("spurious operands; (%d operands/instruction max)"),
2220 /* Now parse operand adding info to 'i' as we go along. */
2221 END_STRING_AND_SAVE (l);
2225 i386_intel_operand (token_start,
2226 intel_float_operand (mnemonic));
2228 operand_ok = i386_operand (token_start);
2230 RESTORE_END_STRING (l);
2236 if (expecting_operand)
2238 expecting_operand_after_comma:
2239 as_bad (_("expecting operand after ','; got nothing"));
2244 as_bad (_("expecting operand before ','; got nothing"));
2249 /* Now *l must be either ',' or END_OF_INSN. */
2252 if (*++l == END_OF_INSN)
2254 /* Just skip it, if it's \n complain. */
2255 goto expecting_operand_after_comma;
2257 expecting_operand = 1;
2264 swap_2_operands (int xchg1, int xchg2)
2266 union i386_op temp_op;
2267 unsigned int temp_type;
2268 enum bfd_reloc_code_real temp_reloc;
2270 temp_type = i.types[xchg2];
2271 i.types[xchg2] = i.types[xchg1];
2272 i.types[xchg1] = temp_type;
2273 temp_op = i.op[xchg2];
2274 i.op[xchg2] = i.op[xchg1];
2275 i.op[xchg1] = temp_op;
2276 temp_reloc = i.reloc[xchg2];
2277 i.reloc[xchg2] = i.reloc[xchg1];
2278 i.reloc[xchg1] = temp_reloc;
2282 swap_operands (void)
2287 swap_2_operands (1, i.operands - 2);
2290 swap_2_operands (0, i.operands - 1);
2296 if (i.mem_operands == 2)
2298 const seg_entry *temp_seg;
2299 temp_seg = i.seg[0];
2300 i.seg[0] = i.seg[1];
2301 i.seg[1] = temp_seg;
2305 /* Try to ensure constant immediates are represented in the smallest
2310 char guess_suffix = 0;
2314 guess_suffix = i.suffix;
2315 else if (i.reg_operands)
2317 /* Figure out a suffix from the last register operand specified.
2318 We can't do this properly yet, ie. excluding InOutPortReg,
2319 but the following works for instructions with immediates.
2320 In any case, we can't set i.suffix yet. */
2321 for (op = i.operands; --op >= 0;)
2322 if (i.types[op] & Reg)
2324 if (i.types[op] & Reg8)
2325 guess_suffix = BYTE_MNEM_SUFFIX;
2326 else if (i.types[op] & Reg16)
2327 guess_suffix = WORD_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg32)
2329 guess_suffix = LONG_MNEM_SUFFIX;
2330 else if (i.types[op] & Reg64)
2331 guess_suffix = QWORD_MNEM_SUFFIX;
2335 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2336 guess_suffix = WORD_MNEM_SUFFIX;
2338 for (op = i.operands; --op >= 0;)
2339 if (i.types[op] & Imm)
2341 switch (i.op[op].imms->X_op)
2344 /* If a suffix is given, this operand may be shortened. */
2345 switch (guess_suffix)
2347 case LONG_MNEM_SUFFIX:
2348 i.types[op] |= Imm32 | Imm64;
2350 case WORD_MNEM_SUFFIX:
2351 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2353 case BYTE_MNEM_SUFFIX:
2354 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2358 /* If this operand is at most 16 bits, convert it
2359 to a signed 16 bit number before trying to see
2360 whether it will fit in an even smaller size.
2361 This allows a 16-bit operand such as $0xffe0 to
2362 be recognised as within Imm8S range. */
2363 if ((i.types[op] & Imm16)
2364 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2366 i.op[op].imms->X_add_number =
2367 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2369 if ((i.types[op] & Imm32)
2370 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2373 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2374 ^ ((offsetT) 1 << 31))
2375 - ((offsetT) 1 << 31));
2377 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2379 /* We must avoid matching of Imm32 templates when 64bit
2380 only immediate is available. */
2381 if (guess_suffix == QWORD_MNEM_SUFFIX)
2382 i.types[op] &= ~Imm32;
2389 /* Symbols and expressions. */
2391 /* Convert symbolic operand to proper sizes for matching, but don't
2392 prevent matching a set of insns that only supports sizes other
2393 than those matching the insn suffix. */
2395 unsigned int mask, allowed = 0;
2398 for (t = current_templates->start;
2399 t < current_templates->end;
2401 allowed |= t->operand_types[op];
2402 switch (guess_suffix)
2404 case QWORD_MNEM_SUFFIX:
2405 mask = Imm64 | Imm32S;
2407 case LONG_MNEM_SUFFIX:
2410 case WORD_MNEM_SUFFIX:
2413 case BYTE_MNEM_SUFFIX:
2421 i.types[op] &= mask;
2428 /* Try to use the smallest displacement type too. */
2430 optimize_disp (void)
2434 for (op = i.operands; --op >= 0;)
2435 if (i.types[op] & Disp)
2437 if (i.op[op].disps->X_op == O_constant)
2439 offsetT disp = i.op[op].disps->X_add_number;
2441 if ((i.types[op] & Disp16)
2442 && (disp & ~(offsetT) 0xffff) == 0)
2444 /* If this operand is at most 16 bits, convert
2445 to a signed 16 bit number and don't use 64bit
2447 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2448 i.types[op] &= ~Disp64;
2450 if ((i.types[op] & Disp32)
2451 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2453 /* If this operand is at most 32 bits, convert
2454 to a signed 32 bit number and don't use 64bit
2456 disp &= (((offsetT) 2 << 31) - 1);
2457 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2458 i.types[op] &= ~Disp64;
2460 if (!disp && (i.types[op] & BaseIndex))
2462 i.types[op] &= ~Disp;
2466 else if (flag_code == CODE_64BIT)
2468 if (fits_in_signed_long (disp))
2470 i.types[op] &= ~Disp64;
2471 i.types[op] |= Disp32S;
2473 if (fits_in_unsigned_long (disp))
2474 i.types[op] |= Disp32;
2476 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2477 && fits_in_signed_byte (disp))
2478 i.types[op] |= Disp8;
2480 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2481 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2483 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2484 i.op[op].disps, 0, i.reloc[op]);
2485 i.types[op] &= ~Disp;
2488 /* We only support 64bit displacement on constants. */
2489 i.types[op] &= ~Disp64;
2494 match_template (void)
2496 /* Points to template once we've found it. */
2498 unsigned int overlap0, overlap1, overlap2, overlap3;
2499 unsigned int found_reverse_match;
2501 unsigned int operand_types [MAX_OPERANDS];
2502 int addr_prefix_disp;
2505 #if MAX_OPERANDS != 4
2506 # error "MAX_OPERANDS must be 4."
2509 #define MATCH(overlap, given, template) \
2510 ((overlap & ~JumpAbsolute) \
2511 && (((given) & (BaseIndex | JumpAbsolute)) \
2512 == ((overlap) & (BaseIndex | JumpAbsolute))))
2514 /* If given types r0 and r1 are registers they must be of the same type
2515 unless the expected operand type register overlap is null.
2516 Note that Acc in a template matches every size of reg. */
2517 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2518 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2519 || ((g0) & Reg) == ((g1) & Reg) \
2520 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2526 found_reverse_match = 0;
2527 for (j = 0; j < MAX_OPERANDS; j++)
2528 operand_types [j] = 0;
2529 addr_prefix_disp = -1;
2530 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2532 : (i.suffix == WORD_MNEM_SUFFIX
2534 : (i.suffix == SHORT_MNEM_SUFFIX
2536 : (i.suffix == LONG_MNEM_SUFFIX
2538 : (i.suffix == QWORD_MNEM_SUFFIX
2540 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2541 ? No_xSuf : 0))))));
2543 for (t = current_templates->start; t < current_templates->end; t++)
2545 addr_prefix_disp = -1;
2547 /* Must have right number of operands. */
2548 if (i.operands != t->operands)
2551 /* Check the suffix, except for some instructions in intel mode. */
2552 if ((t->opcode_modifier & suffix_check)
2554 && (t->opcode_modifier & IgnoreSize)))
2557 for (j = 0; j < MAX_OPERANDS; j++)
2558 operand_types [j] = t->operand_types [j];
2560 /* In general, don't allow 64-bit operands in 32-bit mode. */
2561 if (i.suffix == QWORD_MNEM_SUFFIX
2562 && flag_code != CODE_64BIT
2564 ? (!(t->opcode_modifier & IgnoreSize)
2565 && !intel_float_operand (t->name))
2566 : intel_float_operand (t->name) != 2)
2567 && (!(operand_types[0] & (RegMMX | RegXMM))
2568 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2569 && (t->base_opcode != 0x0fc7
2570 || t->extension_opcode != 1 /* cmpxchg8b */))
2573 /* Do not verify operands when there are none. */
2574 else if (!t->operands)
2576 if (t->cpu_flags & ~cpu_arch_flags)
2578 /* We've found a match; break out of loop. */
2582 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2583 into Disp32/Disp16/Disp32 operand. */
2584 if (i.prefix[ADDR_PREFIX] != 0)
2586 unsigned int DispOn = 0, DispOff = 0;
2604 for (j = 0; j < MAX_OPERANDS; j++)
2606 /* There should be only one Disp operand. */
2607 if ((operand_types[j] & DispOff))
2609 addr_prefix_disp = j;
2610 operand_types[j] |= DispOn;
2611 operand_types[j] &= ~DispOff;
2617 overlap0 = i.types[0] & operand_types[0];
2618 switch (t->operands)
2621 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2627 overlap1 = i.types[1] & operand_types[1];
2628 if (!MATCH (overlap0, i.types[0], operand_types[0])
2629 || !MATCH (overlap1, i.types[1], operand_types[1])
2630 /* monitor in SSE3 is a very special case. The first
2631 register and the second register may have different
2633 || !((t->base_opcode == 0x0f01
2634 && t->extension_opcode == 0xc8)
2635 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2637 overlap1, i.types[1],
2640 /* Check if other direction is valid ... */
2641 if ((t->opcode_modifier & (D | FloatD)) == 0)
2644 /* Try reversing direction of operands. */
2645 overlap0 = i.types[0] & operand_types[1];
2646 overlap1 = i.types[1] & operand_types[0];
2647 if (!MATCH (overlap0, i.types[0], operand_types[1])
2648 || !MATCH (overlap1, i.types[1], operand_types[0])
2649 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2651 overlap1, i.types[1],
2654 /* Does not match either direction. */
2657 /* found_reverse_match holds which of D or FloatDR
2659 if ((t->opcode_modifier & D))
2660 found_reverse_match = Opcode_D;
2661 else if ((t->opcode_modifier & FloatD))
2662 found_reverse_match = Opcode_FloatD;
2664 found_reverse_match = 0;
2665 if ((t->opcode_modifier & FloatR))
2666 found_reverse_match |= Opcode_FloatR;
2670 /* Found a forward 2 operand match here. */
2671 switch (t->operands)
2674 overlap3 = i.types[3] & operand_types[3];
2676 overlap2 = i.types[2] & operand_types[2];
2680 switch (t->operands)
2683 if (!MATCH (overlap3, i.types[3], operand_types[3])
2684 || !CONSISTENT_REGISTER_MATCH (overlap2,
2692 /* Here we make use of the fact that there are no
2693 reverse match 3 operand instructions, and all 3
2694 operand instructions only need to be checked for
2695 register consistency between operands 2 and 3. */
2696 if (!MATCH (overlap2, i.types[2], operand_types[2])
2697 || !CONSISTENT_REGISTER_MATCH (overlap1,
2707 /* Found either forward/reverse 2, 3 or 4 operand match here:
2708 slip through to break. */
2710 if (t->cpu_flags & ~cpu_arch_flags)
2712 found_reverse_match = 0;
2715 /* We've found a match; break out of loop. */
2719 if (t == current_templates->end)
2721 /* We found no match. */
2722 as_bad (_("suffix or operands invalid for `%s'"),
2723 current_templates->start->name);
2727 if (!quiet_warnings)
2730 && ((i.types[0] & JumpAbsolute)
2731 != (operand_types[0] & JumpAbsolute)))
2733 as_warn (_("indirect %s without `*'"), t->name);
2736 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2737 == (IsPrefix | IgnoreSize))
2739 /* Warn them that a data or address size prefix doesn't
2740 affect assembly of the next line of code. */
2741 as_warn (_("stand-alone `%s' prefix"), t->name);
2745 /* Copy the template we found. */
2748 if (addr_prefix_disp != -1)
2749 i.tm.operand_types[addr_prefix_disp]
2750 = operand_types[addr_prefix_disp];
2752 if (found_reverse_match)
2754 /* If we found a reverse match we must alter the opcode
2755 direction bit. found_reverse_match holds bits to change
2756 (different for int & float insns). */
2758 i.tm.base_opcode ^= found_reverse_match;
2760 i.tm.operand_types[0] = operand_types[1];
2761 i.tm.operand_types[1] = operand_types[0];
2770 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2771 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2773 if (i.seg[0] != NULL && i.seg[0] != &es)
2775 as_bad (_("`%s' operand %d must use `%%es' segment"),
2780 /* There's only ever one segment override allowed per instruction.
2781 This instruction possibly has a legal segment override on the
2782 second operand, so copy the segment to where non-string
2783 instructions store it, allowing common code. */
2784 i.seg[0] = i.seg[1];
2786 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2788 if (i.seg[1] != NULL && i.seg[1] != &es)
2790 as_bad (_("`%s' operand %d must use `%%es' segment"),
2800 process_suffix (void)
2802 /* If matched instruction specifies an explicit instruction mnemonic
2804 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2806 if (i.tm.opcode_modifier & Size16)
2807 i.suffix = WORD_MNEM_SUFFIX;
2808 else if (i.tm.opcode_modifier & Size64)
2809 i.suffix = QWORD_MNEM_SUFFIX;
2811 i.suffix = LONG_MNEM_SUFFIX;
2813 else if (i.reg_operands)
2815 /* If there's no instruction mnemonic suffix we try to invent one
2816 based on register operands. */
2819 /* We take i.suffix from the last register operand specified,
2820 Destination register type is more significant than source
2824 for (op = i.operands; --op >= 0;)
2825 if ((i.types[op] & Reg)
2826 && !(i.tm.operand_types[op] & InOutPortReg))
2828 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2829 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2830 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2835 else if (i.suffix == BYTE_MNEM_SUFFIX)
2837 if (!check_byte_reg ())
2840 else if (i.suffix == LONG_MNEM_SUFFIX)
2842 if (!check_long_reg ())
2845 else if (i.suffix == QWORD_MNEM_SUFFIX)
2847 if (!check_qword_reg ())
2850 else if (i.suffix == WORD_MNEM_SUFFIX)
2852 if (!check_word_reg ())
2855 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2856 /* Do nothing if the instruction is going to ignore the prefix. */
2861 else if ((i.tm.opcode_modifier & DefaultSize)
2863 /* exclude fldenv/frstor/fsave/fstenv */
2864 && (i.tm.opcode_modifier & No_sSuf))
2866 i.suffix = stackop_size;
2868 else if (intel_syntax
2870 && ((i.tm.operand_types[0] & JumpAbsolute)
2871 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2872 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2873 && i.tm.extension_opcode <= 3)))
2878 if (!(i.tm.opcode_modifier & No_qSuf))
2880 i.suffix = QWORD_MNEM_SUFFIX;
2884 if (!(i.tm.opcode_modifier & No_lSuf))
2885 i.suffix = LONG_MNEM_SUFFIX;
2888 if (!(i.tm.opcode_modifier & No_wSuf))
2889 i.suffix = WORD_MNEM_SUFFIX;
2898 if (i.tm.opcode_modifier & W)
2900 as_bad (_("no instruction mnemonic suffix given and "
2901 "no register operands; can't size instruction"));
2907 unsigned int suffixes = (~i.tm.opcode_modifier
2915 if ((i.tm.opcode_modifier & W)
2916 || ((suffixes & (suffixes - 1))
2917 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2919 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2925 /* Change the opcode based on the operand size given by i.suffix;
2926 We don't need to change things for byte insns. */
2928 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2930 /* It's not a byte, select word/dword operation. */
2931 if (i.tm.opcode_modifier & W)
2933 if (i.tm.opcode_modifier & ShortForm)
2934 i.tm.base_opcode |= 8;
2936 i.tm.base_opcode |= 1;
2939 /* Now select between word & dword operations via the operand
2940 size prefix, except for instructions that will ignore this
2942 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2944 /* monitor in SSE3 is a very special case. The default size
2945 of AX is the size of mode. The address size override
2946 prefix will change the size of AX. */
2947 if (i.op->regs[0].reg_type &
2948 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2949 if (!add_prefix (ADDR_PREFIX_OPCODE))
2952 else if (i.suffix != QWORD_MNEM_SUFFIX
2953 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2954 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2955 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2956 || (flag_code == CODE_64BIT
2957 && (i.tm.opcode_modifier & JumpByte))))
2959 unsigned int prefix = DATA_PREFIX_OPCODE;
2961 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2962 prefix = ADDR_PREFIX_OPCODE;
2964 if (!add_prefix (prefix))
2968 /* Set mode64 for an operand. */
2969 if (i.suffix == QWORD_MNEM_SUFFIX
2970 && flag_code == CODE_64BIT
2971 && (i.tm.opcode_modifier & NoRex64) == 0)
2973 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2976 || i.types [0] != (Acc | Reg64)
2977 || i.types [1] != (Acc | Reg64)
2978 || strcmp (i.tm.name, "xchg") != 0)
2979 i.rex |= REX_MODE64;
2982 /* Size floating point instruction. */
2983 if (i.suffix == LONG_MNEM_SUFFIX)
2984 if (i.tm.opcode_modifier & FloatMF)
2985 i.tm.base_opcode ^= 4;
2992 check_byte_reg (void)
2996 for (op = i.operands; --op >= 0;)
2998 /* If this is an eight bit register, it's OK. If it's the 16 or
2999 32 bit version of an eight bit register, we will just use the
3000 low portion, and that's OK too. */
3001 if (i.types[op] & Reg8)
3004 /* movzx and movsx should not generate this warning. */
3006 && (i.tm.base_opcode == 0xfb7
3007 || i.tm.base_opcode == 0xfb6
3008 || i.tm.base_opcode == 0x63
3009 || i.tm.base_opcode == 0xfbe
3010 || i.tm.base_opcode == 0xfbf))
3013 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3015 /* Prohibit these changes in the 64bit mode, since the
3016 lowering is more complicated. */
3017 if (flag_code == CODE_64BIT
3018 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3020 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3021 register_prefix, i.op[op].regs->reg_name,
3025 #if REGISTER_WARNINGS
3027 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3028 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3029 (i.op[op].regs + (i.types[op] & Reg16
3030 ? REGNAM_AL - REGNAM_AX
3031 : REGNAM_AL - REGNAM_EAX))->reg_name,
3032 i.op[op].regs->reg_name,
3037 /* Any other register is bad. */
3038 if (i.types[op] & (Reg | RegMMX | RegXMM
3040 | Control | Debug | Test
3041 | FloatReg | FloatAcc))
3043 as_bad (_("`%%%s' not allowed with `%s%c'"),
3044 i.op[op].regs->reg_name,
3054 check_long_reg (void)
3058 for (op = i.operands; --op >= 0;)
3059 /* Reject eight bit registers, except where the template requires
3060 them. (eg. movzb) */
3061 if ((i.types[op] & Reg8) != 0
3062 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3064 as_bad (_("`%%%s' not allowed with `%s%c'"),
3065 i.op[op].regs->reg_name,
3070 /* Warn if the e prefix on a general reg is missing. */
3071 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3072 && (i.types[op] & Reg16) != 0
3073 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3075 /* Prohibit these changes in the 64bit mode, since the
3076 lowering is more complicated. */
3077 if (flag_code == CODE_64BIT)
3079 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3080 register_prefix, i.op[op].regs->reg_name,
3084 #if REGISTER_WARNINGS
3086 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3087 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3088 i.op[op].regs->reg_name,
3092 /* Warn if the r prefix on a general reg is missing. */
3093 else if ((i.types[op] & Reg64) != 0
3094 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3096 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3097 register_prefix, i.op[op].regs->reg_name,
3105 check_qword_reg (void)
3109 for (op = i.operands; --op >= 0; )
3110 /* Reject eight bit registers, except where the template requires
3111 them. (eg. movzb) */
3112 if ((i.types[op] & Reg8) != 0
3113 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3115 as_bad (_("`%%%s' not allowed with `%s%c'"),
3116 i.op[op].regs->reg_name,
3121 /* Warn if the e prefix on a general reg is missing. */
3122 else if (((i.types[op] & Reg16) != 0
3123 || (i.types[op] & Reg32) != 0)
3124 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3126 /* Prohibit these changes in the 64bit mode, since the
3127 lowering is more complicated. */
3128 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3129 register_prefix, i.op[op].regs->reg_name,
3137 check_word_reg (void)
3140 for (op = i.operands; --op >= 0;)
3141 /* Reject eight bit registers, except where the template requires
3142 them. (eg. movzb) */
3143 if ((i.types[op] & Reg8) != 0
3144 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3146 as_bad (_("`%%%s' not allowed with `%s%c'"),
3147 i.op[op].regs->reg_name,
3152 /* Warn if the e prefix on a general reg is present. */
3153 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3154 && (i.types[op] & Reg32) != 0
3155 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3157 /* Prohibit these changes in the 64bit mode, since the
3158 lowering is more complicated. */
3159 if (flag_code == CODE_64BIT)
3161 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3162 register_prefix, i.op[op].regs->reg_name,
3167 #if REGISTER_WARNINGS
3168 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3169 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3170 i.op[op].regs->reg_name,
3180 unsigned int overlap0, overlap1, overlap2;
3182 overlap0 = i.types[0] & i.tm.operand_types[0];
3183 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3184 && overlap0 != Imm8 && overlap0 != Imm8S
3185 && overlap0 != Imm16 && overlap0 != Imm32S
3186 && overlap0 != Imm32 && overlap0 != Imm64)
3190 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3192 : (i.suffix == WORD_MNEM_SUFFIX
3194 : (i.suffix == QWORD_MNEM_SUFFIX
3198 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3199 || overlap0 == (Imm16 | Imm32)
3200 || overlap0 == (Imm16 | Imm32S))
3202 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3205 if (overlap0 != Imm8 && overlap0 != Imm8S
3206 && overlap0 != Imm16 && overlap0 != Imm32S
3207 && overlap0 != Imm32 && overlap0 != Imm64)
3209 as_bad (_("no instruction mnemonic suffix given; "
3210 "can't determine immediate size"));
3214 i.types[0] = overlap0;
3216 overlap1 = i.types[1] & i.tm.operand_types[1];
3217 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3218 && overlap1 != Imm8 && overlap1 != Imm8S
3219 && overlap1 != Imm16 && overlap1 != Imm32S
3220 && overlap1 != Imm32 && overlap1 != Imm64)
3224 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3226 : (i.suffix == WORD_MNEM_SUFFIX
3228 : (i.suffix == QWORD_MNEM_SUFFIX
3232 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3233 || overlap1 == (Imm16 | Imm32)
3234 || overlap1 == (Imm16 | Imm32S))
3236 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3239 if (overlap1 != Imm8 && overlap1 != Imm8S
3240 && overlap1 != Imm16 && overlap1 != Imm32S
3241 && overlap1 != Imm32 && overlap1 != Imm64)
3243 as_bad (_("no instruction mnemonic suffix given; "
3244 "can't determine immediate size %x %c"),
3245 overlap1, i.suffix);
3249 i.types[1] = overlap1;
3251 overlap2 = i.types[2] & i.tm.operand_types[2];
3252 assert ((overlap2 & Imm) == 0);
3253 i.types[2] = overlap2;
3259 process_operands (void)
3261 /* Default segment register this instruction will use for memory
3262 accesses. 0 means unknown. This is only for optimizing out
3263 unnecessary segment overrides. */
3264 const seg_entry *default_seg = 0;
3266 /* The imul $imm, %reg instruction is converted into
3267 imul $imm, %reg, %reg, and the clr %reg instruction
3268 is converted into xor %reg, %reg. */
3269 if (i.tm.opcode_modifier & regKludge)
3271 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3272 /* Pretend we saw the extra register operand. */
3273 assert (i.reg_operands == 1
3274 && i.op[first_reg_op + 1].regs == 0);
3275 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3276 i.types[first_reg_op + 1] = i.types[first_reg_op];
3281 if (i.tm.opcode_modifier & ShortForm)
3283 if (i.types[0] & (SReg2 | SReg3))
3285 if (i.tm.base_opcode == POP_SEG_SHORT
3286 && i.op[0].regs->reg_num == 1)
3288 as_bad (_("you can't `pop %%cs'"));
3291 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3292 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3297 /* The register or float register operand is in operand 0 or 1. */
3298 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3299 /* Register goes in low 3 bits of opcode. */
3300 i.tm.base_opcode |= i.op[op].regs->reg_num;
3301 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3303 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3305 /* Warn about some common errors, but press on regardless.
3306 The first case can be generated by gcc (<= 2.8.1). */
3307 if (i.operands == 2)
3309 /* Reversed arguments on faddp, fsubp, etc. */
3310 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3311 i.op[1].regs->reg_name,
3312 i.op[0].regs->reg_name);
3316 /* Extraneous `l' suffix on fp insn. */
3317 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3318 i.op[0].regs->reg_name);
3323 else if (i.tm.opcode_modifier & Modrm)
3325 /* The opcode is completed (modulo i.tm.extension_opcode which
3326 must be put into the modrm byte). Now, we make the modrm and
3327 index base bytes based on all the info we've collected. */
3329 default_seg = build_modrm_byte ();
3331 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
3335 else if ((i.tm.opcode_modifier & IsString) != 0)
3337 /* For the string instructions that allow a segment override
3338 on one of their operands, the default segment is ds. */
3342 if ((i.tm.base_opcode == 0x8d /* lea */
3343 || (i.tm.cpu_flags & CpuSVME))
3344 && i.seg[0] && !quiet_warnings)
3345 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3347 /* If a segment was explicitly specified, and the specified segment
3348 is not the default, use an opcode prefix to select it. If we
3349 never figured out what the default segment is, then default_seg
3350 will be zero at this point, and the specified segment prefix will
3352 if ((i.seg[0]) && (i.seg[0] != default_seg))
3354 if (!add_prefix (i.seg[0]->seg_prefix))
3360 static const seg_entry *
3361 build_modrm_byte (void)
3363 const seg_entry *default_seg = 0;
3365 /* i.reg_operands MUST be the number of real register operands;
3366 implicit registers do not count. */
3367 if (i.reg_operands == 2)
3369 unsigned int source, dest;
3377 /* When there are 3 operands, one of them may be immediate,
3378 which may be the first or the last operand. Otherwise,
3379 the first operand must be shift count register (cl). */
3380 assert (i.imm_operands == 1
3381 || (i.imm_operands == 0
3382 && (i.types[0] & ShiftCount)));
3383 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
3386 /* When there are 4 operands, the first two must be immediate
3387 operands. The source operand will be the 3rd one. */
3388 assert (i.imm_operands == 2
3389 && (i.types[0] & Imm)
3390 && (i.types[1] & Imm));
3400 /* One of the register operands will be encoded in the i.tm.reg
3401 field, the other in the combined i.tm.mode and i.tm.regmem
3402 fields. If no form of this instruction supports a memory
3403 destination operand, then we assume the source operand may
3404 sometimes be a memory operand and so we need to store the
3405 destination in the i.rm.reg field. */
3406 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3408 i.rm.reg = i.op[dest].regs->reg_num;
3409 i.rm.regmem = i.op[source].regs->reg_num;
3410 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3412 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3417 i.rm.reg = i.op[source].regs->reg_num;
3418 i.rm.regmem = i.op[dest].regs->reg_num;
3419 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3421 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3424 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3426 if (!((i.types[0] | i.types[1]) & Control))
3428 i.rex &= ~(REX_EXTX | REX_EXTZ);
3429 add_prefix (LOCK_PREFIX_OPCODE);
3433 { /* If it's not 2 reg operands... */
3436 unsigned int fake_zero_displacement = 0;
3439 for (op = 0; op < i.operands; op++)
3440 if ((i.types[op] & AnyMem))
3442 assert (op < i.operands);
3446 if (i.base_reg == 0)
3449 if (!i.disp_operands)
3450 fake_zero_displacement = 1;
3451 if (i.index_reg == 0)
3453 /* Operand is just <disp> */
3454 if (flag_code == CODE_64BIT)
3456 /* 64bit mode overwrites the 32bit absolute
3457 addressing by RIP relative addressing and
3458 absolute addressing is encoded by one of the
3459 redundant SIB forms. */
3460 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3461 i.sib.base = NO_BASE_REGISTER;
3462 i.sib.index = NO_INDEX_REGISTER;
3463 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3464 ? Disp32S : Disp32);
3466 else if ((flag_code == CODE_16BIT)
3467 ^ (i.prefix[ADDR_PREFIX] != 0))
3469 i.rm.regmem = NO_BASE_REGISTER_16;
3470 i.types[op] = Disp16;
3474 i.rm.regmem = NO_BASE_REGISTER;
3475 i.types[op] = Disp32;
3478 else /* !i.base_reg && i.index_reg */
3480 i.sib.index = i.index_reg->reg_num;
3481 i.sib.base = NO_BASE_REGISTER;
3482 i.sib.scale = i.log2_scale_factor;
3483 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3484 i.types[op] &= ~Disp;
3485 if (flag_code != CODE_64BIT)
3486 i.types[op] |= Disp32; /* Must be 32 bit */
3488 i.types[op] |= Disp32S;
3489 if ((i.index_reg->reg_flags & RegRex) != 0)
3493 /* RIP addressing for 64bit mode. */
3494 else if (i.base_reg->reg_type == BaseIndex)
3496 i.rm.regmem = NO_BASE_REGISTER;
3497 i.types[op] &= ~ Disp;
3498 i.types[op] |= Disp32S;
3499 i.flags[op] |= Operand_PCrel;
3500 if (! i.disp_operands)
3501 fake_zero_displacement = 1;
3503 else if (i.base_reg->reg_type & Reg16)
3505 switch (i.base_reg->reg_num)
3508 if (i.index_reg == 0)
3510 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3511 i.rm.regmem = i.index_reg->reg_num - 6;
3515 if (i.index_reg == 0)
3518 if ((i.types[op] & Disp) == 0)
3520 /* fake (%bp) into 0(%bp) */
3521 i.types[op] |= Disp8;
3522 fake_zero_displacement = 1;
3525 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3526 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3528 default: /* (%si) -> 4 or (%di) -> 5 */
3529 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3531 i.rm.mode = mode_from_disp_size (i.types[op]);
3533 else /* i.base_reg and 32/64 bit mode */
3535 if (flag_code == CODE_64BIT
3536 && (i.types[op] & Disp))
3537 i.types[op] = ((i.types[op] & Disp8)
3538 | (i.prefix[ADDR_PREFIX] == 0
3539 ? Disp32S : Disp32));
3541 i.rm.regmem = i.base_reg->reg_num;
3542 if ((i.base_reg->reg_flags & RegRex) != 0)
3544 i.sib.base = i.base_reg->reg_num;
3545 /* x86-64 ignores REX prefix bit here to avoid decoder
3547 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3550 if (i.disp_operands == 0)
3552 fake_zero_displacement = 1;
3553 i.types[op] |= Disp8;
3556 else if (i.base_reg->reg_num == ESP_REG_NUM)
3560 i.sib.scale = i.log2_scale_factor;
3561 if (i.index_reg == 0)
3563 /* <disp>(%esp) becomes two byte modrm with no index
3564 register. We've already stored the code for esp
3565 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3566 Any base register besides %esp will not use the
3567 extra modrm byte. */
3568 i.sib.index = NO_INDEX_REGISTER;
3569 #if !SCALE1_WHEN_NO_INDEX
3570 /* Another case where we force the second modrm byte. */
3571 if (i.log2_scale_factor)
3572 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3577 i.sib.index = i.index_reg->reg_num;
3578 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3579 if ((i.index_reg->reg_flags & RegRex) != 0)
3584 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3585 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3588 i.rm.mode = mode_from_disp_size (i.types[op]);
3591 if (fake_zero_displacement)
3593 /* Fakes a zero displacement assuming that i.types[op]
3594 holds the correct displacement size. */
3597 assert (i.op[op].disps == 0);
3598 exp = &disp_expressions[i.disp_operands++];
3599 i.op[op].disps = exp;
3600 exp->X_op = O_constant;
3601 exp->X_add_number = 0;
3602 exp->X_add_symbol = (symbolS *) 0;
3603 exp->X_op_symbol = (symbolS *) 0;
3607 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3608 (if any) based on i.tm.extension_opcode. Again, we must be
3609 careful to make sure that segment/control/debug/test/MMX
3610 registers are coded into the i.rm.reg field. */
3615 for (op = 0; op < i.operands; op++)
3616 if ((i.types[op] & (Reg | RegMMX | RegXMM
3618 | Control | Debug | Test)))
3620 assert (op < i.operands);
3622 /* If there is an extension opcode to put here, the register
3623 number must be put into the regmem field. */
3624 if (i.tm.extension_opcode != None)
3626 i.rm.regmem = i.op[op].regs->reg_num;
3627 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3632 i.rm.reg = i.op[op].regs->reg_num;
3633 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3637 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3638 must set it to 3 to indicate this is a register operand
3639 in the regmem field. */
3640 if (!i.mem_operands)
3644 /* Fill in i.rm.reg field with extension opcode (if any). */
3645 if (i.tm.extension_opcode != None)
3646 i.rm.reg = i.tm.extension_opcode;
3652 output_branch (void)
3657 relax_substateT subtype;
3662 if (flag_code == CODE_16BIT)
3666 if (i.prefix[DATA_PREFIX] != 0)
3672 /* Pentium4 branch hints. */
3673 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3674 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3679 if (i.prefix[REX_PREFIX] != 0)
3685 if (i.prefixes != 0 && !intel_syntax)
3686 as_warn (_("skipping prefixes on this instruction"));
3688 /* It's always a symbol; End frag & setup for relax.
3689 Make sure there is enough room in this frag for the largest
3690 instruction we may generate in md_convert_frag. This is 2
3691 bytes for the opcode and room for the prefix and largest
3693 frag_grow (prefix + 2 + 4);
3694 /* Prefix and 1 opcode byte go in fr_fix. */
3695 p = frag_more (prefix + 1);
3696 if (i.prefix[DATA_PREFIX] != 0)
3697 *p++ = DATA_PREFIX_OPCODE;
3698 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3699 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3700 *p++ = i.prefix[SEG_PREFIX];
3701 if (i.prefix[REX_PREFIX] != 0)
3702 *p++ = i.prefix[REX_PREFIX];
3703 *p = i.tm.base_opcode;
3705 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3706 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3707 else if ((cpu_arch_flags & Cpu386) != 0)
3708 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3710 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3713 sym = i.op[0].disps->X_add_symbol;
3714 off = i.op[0].disps->X_add_number;
3716 if (i.op[0].disps->X_op != O_constant
3717 && i.op[0].disps->X_op != O_symbol)
3719 /* Handle complex expressions. */
3720 sym = make_expr_symbol (i.op[0].disps);
3724 /* 1 possible extra opcode + 4 byte displacement go in var part.
3725 Pass reloc in fr_var. */
3726 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3736 if (i.tm.opcode_modifier & JumpByte)
3738 /* This is a loop or jecxz type instruction. */
3740 if (i.prefix[ADDR_PREFIX] != 0)
3742 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3745 /* Pentium4 branch hints. */
3746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3749 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3758 if (flag_code == CODE_16BIT)
3761 if (i.prefix[DATA_PREFIX] != 0)
3763 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3773 if (i.prefix[REX_PREFIX] != 0)
3775 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3779 if (i.prefixes != 0 && !intel_syntax)
3780 as_warn (_("skipping prefixes on this instruction"));
3782 p = frag_more (1 + size);
3783 *p++ = i.tm.base_opcode;
3785 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3786 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3788 /* All jumps handled here are signed, but don't use a signed limit
3789 check for 32 and 16 bit jumps as we want to allow wrap around at
3790 4G and 64k respectively. */
3792 fixP->fx_signed = 1;
3796 output_interseg_jump (void)
3804 if (flag_code == CODE_16BIT)
3808 if (i.prefix[DATA_PREFIX] != 0)
3814 if (i.prefix[REX_PREFIX] != 0)
3824 if (i.prefixes != 0 && !intel_syntax)
3825 as_warn (_("skipping prefixes on this instruction"));
3827 /* 1 opcode; 2 segment; offset */
3828 p = frag_more (prefix + 1 + 2 + size);
3830 if (i.prefix[DATA_PREFIX] != 0)
3831 *p++ = DATA_PREFIX_OPCODE;
3833 if (i.prefix[REX_PREFIX] != 0)
3834 *p++ = i.prefix[REX_PREFIX];
3836 *p++ = i.tm.base_opcode;
3837 if (i.op[1].imms->X_op == O_constant)
3839 offsetT n = i.op[1].imms->X_add_number;
3842 && !fits_in_unsigned_word (n)
3843 && !fits_in_signed_word (n))
3845 as_bad (_("16-bit jump out of range"));
3848 md_number_to_chars (p, n, size);
3851 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3852 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3853 if (i.op[0].imms->X_op != O_constant)
3854 as_bad (_("can't handle non absolute segment in `%s'"),
3856 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3862 fragS *insn_start_frag;
3863 offsetT insn_start_off;
3865 /* Tie dwarf2 debug info to the address at the start of the insn.
3866 We can't do this after the insn has been output as the current
3867 frag may have been closed off. eg. by frag_var. */
3868 dwarf2_emit_insn (0);
3870 insn_start_frag = frag_now;
3871 insn_start_off = frag_now_fix ();
3874 if (i.tm.opcode_modifier & Jump)
3876 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3878 else if (i.tm.opcode_modifier & JumpInterSegment)
3879 output_interseg_jump ();
3882 /* Output normal instructions here. */
3885 unsigned int prefix;
3887 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3888 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3889 use one more higher byte to specify a prefix the instruction
3891 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3893 if (i.tm.base_opcode & 0xff000000)
3895 prefix = (i.tm.base_opcode >> 24) & 0xff;
3899 else if ((i.tm.base_opcode & 0xff0000) != 0)
3901 prefix = (i.tm.base_opcode >> 16) & 0xff;
3902 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3905 if (prefix != REPE_PREFIX_OPCODE
3906 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3907 add_prefix (prefix);
3910 add_prefix (prefix);
3913 /* The prefix bytes. */
3915 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3921 md_number_to_chars (p, (valueT) *q, 1);
3925 /* Now the opcode; be careful about word order here! */
3926 if (fits_in_unsigned_byte (i.tm.base_opcode))
3928 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3932 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3935 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3940 /* Put out high byte first: can't use md_number_to_chars! */
3941 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3942 *p = i.tm.base_opcode & 0xff;
3945 /* Now the modrm byte and sib byte (if present). */
3946 if (i.tm.opcode_modifier & Modrm)
3949 md_number_to_chars (p,
3950 (valueT) (i.rm.regmem << 0
3954 /* If i.rm.regmem == ESP (4)
3955 && i.rm.mode != (Register mode)
3957 ==> need second modrm byte. */
3958 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3960 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3963 md_number_to_chars (p,
3964 (valueT) (i.sib.base << 0
3966 | i.sib.scale << 6),
3971 if (i.disp_operands)
3972 output_disp (insn_start_frag, insn_start_off);
3975 output_imm (insn_start_frag, insn_start_off);
3981 pi ("" /*line*/, &i);
3983 #endif /* DEBUG386 */
3987 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
3992 for (n = 0; n < i.operands; n++)
3994 if (i.types[n] & Disp)
3996 if (i.op[n].disps->X_op == O_constant)
4002 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4005 if (i.types[n] & Disp8)
4007 if (i.types[n] & Disp64)
4010 val = offset_in_range (i.op[n].disps->X_add_number,
4012 p = frag_more (size);
4013 md_number_to_chars (p, val, size);
4017 enum bfd_reloc_code_real reloc_type;
4020 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4022 /* The PC relative address is computed relative
4023 to the instruction boundary, so in case immediate
4024 fields follows, we need to adjust the value. */
4025 if (pcrel && i.imm_operands)
4030 for (n1 = 0; n1 < i.operands; n1++)
4031 if (i.types[n1] & Imm)
4033 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4036 if (i.types[n1] & (Imm8 | Imm8S))
4038 if (i.types[n1] & Imm64)
4043 /* We should find the immediate. */
4044 if (n1 == i.operands)
4046 i.op[n].disps->X_add_number -= imm_size;
4049 if (i.types[n] & Disp32S)
4052 if (i.types[n] & (Disp16 | Disp64))
4055 if (i.types[n] & Disp64)
4059 p = frag_more (size);
4060 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4062 && GOT_symbol == i.op[n].disps->X_add_symbol
4063 && (((reloc_type == BFD_RELOC_32
4064 || reloc_type == BFD_RELOC_X86_64_32S
4065 || (reloc_type == BFD_RELOC_64
4067 && (i.op[n].disps->X_op == O_symbol
4068 || (i.op[n].disps->X_op == O_add
4069 && ((symbol_get_value_expression
4070 (i.op[n].disps->X_op_symbol)->X_op)
4072 || reloc_type == BFD_RELOC_32_PCREL))
4076 if (insn_start_frag == frag_now)
4077 add = (p - frag_now->fr_literal) - insn_start_off;
4082 add = insn_start_frag->fr_fix - insn_start_off;
4083 for (fr = insn_start_frag->fr_next;
4084 fr && fr != frag_now; fr = fr->fr_next)
4086 add += p - frag_now->fr_literal;
4091 reloc_type = BFD_RELOC_386_GOTPC;
4092 i.op[n].imms->X_add_number += add;
4094 else if (reloc_type == BFD_RELOC_64)
4095 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4097 /* Don't do the adjustment for x86-64, as there
4098 the pcrel addressing is relative to the _next_
4099 insn, and that is taken care of in other code. */
4100 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4102 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4103 i.op[n].disps, pcrel, reloc_type);
4110 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4115 for (n = 0; n < i.operands; n++)
4117 if (i.types[n] & Imm)
4119 if (i.op[n].imms->X_op == O_constant)
4125 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4128 if (i.types[n] & (Imm8 | Imm8S))
4130 else if (i.types[n] & Imm64)
4133 val = offset_in_range (i.op[n].imms->X_add_number,
4135 p = frag_more (size);
4136 md_number_to_chars (p, val, size);
4140 /* Not absolute_section.
4141 Need a 32-bit fixup (don't support 8bit
4142 non-absolute imms). Try to support other
4144 enum bfd_reloc_code_real reloc_type;
4148 if ((i.types[n] & (Imm32S))
4149 && (i.suffix == QWORD_MNEM_SUFFIX
4150 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4152 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4155 if (i.types[n] & (Imm8 | Imm8S))
4157 if (i.types[n] & Imm64)
4161 p = frag_more (size);
4162 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4164 /* This is tough to explain. We end up with this one if we
4165 * have operands that look like
4166 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4167 * obtain the absolute address of the GOT, and it is strongly
4168 * preferable from a performance point of view to avoid using
4169 * a runtime relocation for this. The actual sequence of
4170 * instructions often look something like:
4175 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4177 * The call and pop essentially return the absolute address
4178 * of the label .L66 and store it in %ebx. The linker itself
4179 * will ultimately change the first operand of the addl so
4180 * that %ebx points to the GOT, but to keep things simple, the
4181 * .o file must have this operand set so that it generates not
4182 * the absolute address of .L66, but the absolute address of
4183 * itself. This allows the linker itself simply treat a GOTPC
4184 * relocation as asking for a pcrel offset to the GOT to be
4185 * added in, and the addend of the relocation is stored in the
4186 * operand field for the instruction itself.
4188 * Our job here is to fix the operand so that it would add
4189 * the correct offset so that %ebx would point to itself. The
4190 * thing that is tricky is that .-.L66 will point to the
4191 * beginning of the instruction, so we need to further modify
4192 * the operand so that it will point to itself. There are
4193 * other cases where you have something like:
4195 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4197 * and here no correction would be required. Internally in
4198 * the assembler we treat operands of this form as not being
4199 * pcrel since the '.' is explicitly mentioned, and I wonder
4200 * whether it would simplify matters to do it this way. Who
4201 * knows. In earlier versions of the PIC patches, the
4202 * pcrel_adjust field was used to store the correction, but
4203 * since the expression is not pcrel, I felt it would be
4204 * confusing to do it this way. */
4206 if ((reloc_type == BFD_RELOC_32
4207 || reloc_type == BFD_RELOC_X86_64_32S
4208 || reloc_type == BFD_RELOC_64)
4210 && GOT_symbol == i.op[n].imms->X_add_symbol
4211 && (i.op[n].imms->X_op == O_symbol
4212 || (i.op[n].imms->X_op == O_add
4213 && ((symbol_get_value_expression
4214 (i.op[n].imms->X_op_symbol)->X_op)
4219 if (insn_start_frag == frag_now)
4220 add = (p - frag_now->fr_literal) - insn_start_off;
4225 add = insn_start_frag->fr_fix - insn_start_off;
4226 for (fr = insn_start_frag->fr_next;
4227 fr && fr != frag_now; fr = fr->fr_next)
4229 add += p - frag_now->fr_literal;
4233 reloc_type = BFD_RELOC_386_GOTPC;
4235 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4237 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4238 i.op[n].imms->X_add_number += add;
4240 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4241 i.op[n].imms, 0, reloc_type);
4247 /* x86_cons_fix_new is called via the expression parsing code when a
4248 reloc is needed. We use this hook to get the correct .got reloc. */
4249 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4250 static int cons_sign = -1;
4253 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
4256 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4258 got_reloc = NO_RELOC;
4261 if (exp->X_op == O_secrel)
4263 exp->X_op = O_symbol;
4264 r = BFD_RELOC_32_SECREL;
4268 fix_new_exp (frag, off, len, exp, 0, r);
4271 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4272 # define lex_got(reloc, adjust, types) NULL
4274 /* Parse operands of the form
4275 <symbol>@GOTOFF+<nnn>
4276 and similar .plt or .got references.
4278 If we find one, set up the correct relocation in RELOC and copy the
4279 input string, minus the `@GOTOFF' into a malloc'd buffer for
4280 parsing by the calling routine. Return this buffer, and if ADJUST
4281 is non-null set it to the length of the string we removed from the
4282 input line. Otherwise return NULL. */
4284 lex_got (enum bfd_reloc_code_real *reloc,
4286 unsigned int *types)
4288 /* Some of the relocations depend on the size of what field is to
4289 be relocated. But in our callers i386_immediate and i386_displacement
4290 we don't yet know the operand size (this will be set by insn
4291 matching). Hence we record the word32 relocation here,
4292 and adjust the reloc according to the real size in reloc(). */
4293 static const struct {
4295 const enum bfd_reloc_code_real rel[2];
4296 const unsigned int types64;
4299 BFD_RELOC_X86_64_PLTOFF64 },
4301 { "PLT", { BFD_RELOC_386_PLT32,
4302 BFD_RELOC_X86_64_PLT32 },
4303 Imm32 | Imm32S | Disp32 },
4305 BFD_RELOC_X86_64_GOTPLT64 },
4307 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4308 BFD_RELOC_X86_64_GOTOFF64 },
4311 BFD_RELOC_X86_64_GOTPCREL },
4312 Imm32 | Imm32S | Disp32 },
4313 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4314 BFD_RELOC_X86_64_TLSGD },
4315 Imm32 | Imm32S | Disp32 },
4316 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4320 BFD_RELOC_X86_64_TLSLD },
4321 Imm32 | Imm32S | Disp32 },
4322 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4323 BFD_RELOC_X86_64_GOTTPOFF },
4324 Imm32 | Imm32S | Disp32 },
4325 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4326 BFD_RELOC_X86_64_TPOFF32 },
4327 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4328 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4331 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4332 BFD_RELOC_X86_64_DTPOFF32 },
4333 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4334 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4337 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4340 { "GOT", { BFD_RELOC_386_GOT32,
4341 BFD_RELOC_X86_64_GOT32 },
4342 Imm32 | Imm32S | Disp32 | Imm64 },
4343 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4344 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4345 Imm32 | Imm32S | Disp32 },
4346 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4347 BFD_RELOC_X86_64_TLSDESC_CALL },
4348 Imm32 | Imm32S | Disp32 }
4356 for (cp = input_line_pointer; *cp != '@'; cp++)
4357 if (is_end_of_line[(unsigned char) *cp])
4360 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4364 len = strlen (gotrel[j].str);
4365 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4367 if (gotrel[j].rel[object_64bit] != 0)
4370 char *tmpbuf, *past_reloc;
4372 *reloc = gotrel[j].rel[object_64bit];
4378 if (flag_code != CODE_64BIT)
4379 *types = Imm32 | Disp32;
4381 *types = gotrel[j].types64;
4384 if (GOT_symbol == NULL)
4385 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4387 /* Replace the relocation token with ' ', so that
4388 errors like foo@GOTOFF1 will be detected. */
4390 /* The length of the first part of our input line. */
4391 first = cp - input_line_pointer;
4393 /* The second part goes from after the reloc token until
4394 (and including) an end_of_line char. Don't use strlen
4395 here as the end_of_line char may not be a NUL. */
4396 past_reloc = cp + 1 + len;
4397 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4399 second = cp - past_reloc;
4401 /* Allocate and copy string. The trailing NUL shouldn't
4402 be necessary, but be safe. */
4403 tmpbuf = xmalloc (first + second + 2);
4404 memcpy (tmpbuf, input_line_pointer, first);
4405 tmpbuf[first] = ' ';
4406 memcpy (tmpbuf + first + 1, past_reloc, second);
4407 tmpbuf[first + second + 1] = '\0';
4411 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4412 gotrel[j].str, 1 << (5 + object_64bit));
4417 /* Might be a symbol version string. Don't as_bad here. */
4422 x86_cons (expressionS *exp, int size)
4424 if (size == 4 || (object_64bit && size == 8))
4426 /* Handle @GOTOFF and the like in an expression. */
4428 char *gotfree_input_line;
4431 save = input_line_pointer;
4432 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4433 if (gotfree_input_line)
4434 input_line_pointer = gotfree_input_line;
4438 if (gotfree_input_line)
4440 /* expression () has merrily parsed up to the end of line,
4441 or a comma - in the wrong buffer. Transfer how far
4442 input_line_pointer has moved to the right buffer. */
4443 input_line_pointer = (save
4444 + (input_line_pointer - gotfree_input_line)
4446 free (gotfree_input_line);
4454 static void signed_cons (int size)
4456 if (flag_code == CODE_64BIT)
4464 pe_directive_secrel (dummy)
4465 int dummy ATTRIBUTE_UNUSED;
4472 if (exp.X_op == O_symbol)
4473 exp.X_op = O_secrel;
4475 emit_expr (&exp, 4);
4477 while (*input_line_pointer++ == ',');
4479 input_line_pointer--;
4480 demand_empty_rest_of_line ();
4485 i386_immediate (char *imm_start)
4487 char *save_input_line_pointer;
4488 char *gotfree_input_line;
4491 unsigned int types = ~0U;
4493 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4495 as_bad (_("at most %d immediate operands are allowed"),
4496 MAX_IMMEDIATE_OPERANDS);
4500 exp = &im_expressions[i.imm_operands++];
4501 i.op[this_operand].imms = exp;
4503 if (is_space_char (*imm_start))
4506 save_input_line_pointer = input_line_pointer;
4507 input_line_pointer = imm_start;
4509 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4510 if (gotfree_input_line)
4511 input_line_pointer = gotfree_input_line;
4513 exp_seg = expression (exp);
4516 if (*input_line_pointer)
4517 as_bad (_("junk `%s' after expression"), input_line_pointer);
4519 input_line_pointer = save_input_line_pointer;
4520 if (gotfree_input_line)
4521 free (gotfree_input_line);
4523 if (exp->X_op == O_absent || exp->X_op == O_big)
4525 /* Missing or bad expr becomes absolute 0. */
4526 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4528 exp->X_op = O_constant;
4529 exp->X_add_number = 0;
4530 exp->X_add_symbol = (symbolS *) 0;
4531 exp->X_op_symbol = (symbolS *) 0;
4533 else if (exp->X_op == O_constant)
4535 /* Size it properly later. */
4536 i.types[this_operand] |= Imm64;
4537 /* If BFD64, sign extend val. */
4538 if (!use_rela_relocations
4539 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4541 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4543 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4544 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4545 && exp_seg != absolute_section
4546 && exp_seg != text_section
4547 && exp_seg != data_section
4548 && exp_seg != bss_section
4549 && exp_seg != undefined_section
4550 && !bfd_is_com_section (exp_seg))
4552 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4556 else if (!intel_syntax && exp->X_op == O_register)
4558 as_bad (_("illegal immediate register operand %s"), imm_start);
4563 /* This is an address. The size of the address will be
4564 determined later, depending on destination register,
4565 suffix, or the default for the section. */
4566 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4567 i.types[this_operand] &= types;
4574 i386_scale (char *scale)
4577 char *save = input_line_pointer;
4579 input_line_pointer = scale;
4580 val = get_absolute_expression ();
4585 i.log2_scale_factor = 0;
4588 i.log2_scale_factor = 1;
4591 i.log2_scale_factor = 2;
4594 i.log2_scale_factor = 3;
4598 char sep = *input_line_pointer;
4600 *input_line_pointer = '\0';
4601 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4603 *input_line_pointer = sep;
4604 input_line_pointer = save;
4608 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4610 as_warn (_("scale factor of %d without an index register"),
4611 1 << i.log2_scale_factor);
4612 #if SCALE1_WHEN_NO_INDEX
4613 i.log2_scale_factor = 0;
4616 scale = input_line_pointer;
4617 input_line_pointer = save;
4622 i386_displacement (char *disp_start, char *disp_end)
4626 char *save_input_line_pointer;
4627 char *gotfree_input_line;
4628 int bigdisp, override;
4629 unsigned int types = Disp;
4631 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4633 as_bad (_("at most %d displacement operands are allowed"),
4634 MAX_MEMORY_OPERANDS);
4638 if ((i.types[this_operand] & JumpAbsolute)
4639 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4642 override = (i.prefix[ADDR_PREFIX] != 0);
4646 /* For PC-relative branches, the width of the displacement
4647 is dependent upon data size, not address size. */
4649 override = (i.prefix[DATA_PREFIX] != 0);
4651 if (flag_code == CODE_64BIT)
4654 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4656 : Disp32S | Disp32);
4658 bigdisp = Disp64 | Disp32S | Disp32;
4665 override = (i.suffix == (flag_code != CODE_16BIT
4667 : LONG_MNEM_SUFFIX));
4670 if ((flag_code == CODE_16BIT) ^ override)
4673 i.types[this_operand] |= bigdisp;
4675 exp = &disp_expressions[i.disp_operands];
4676 i.op[this_operand].disps = exp;
4678 save_input_line_pointer = input_line_pointer;
4679 input_line_pointer = disp_start;
4680 END_STRING_AND_SAVE (disp_end);
4682 #ifndef GCC_ASM_O_HACK
4683 #define GCC_ASM_O_HACK 0
4686 END_STRING_AND_SAVE (disp_end + 1);
4687 if ((i.types[this_operand] & BaseIndex) != 0
4688 && displacement_string_end[-1] == '+')
4690 /* This hack is to avoid a warning when using the "o"
4691 constraint within gcc asm statements.
4694 #define _set_tssldt_desc(n,addr,limit,type) \
4695 __asm__ __volatile__ ( \
4697 "movw %w1,2+%0\n\t" \
4699 "movb %b1,4+%0\n\t" \
4700 "movb %4,5+%0\n\t" \
4701 "movb $0,6+%0\n\t" \
4702 "movb %h1,7+%0\n\t" \
4704 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4706 This works great except that the output assembler ends
4707 up looking a bit weird if it turns out that there is
4708 no offset. You end up producing code that looks like:
4721 So here we provide the missing zero. */
4723 *displacement_string_end = '0';
4726 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4727 if (gotfree_input_line)
4728 input_line_pointer = gotfree_input_line;
4730 exp_seg = expression (exp);
4733 if (*input_line_pointer)
4734 as_bad (_("junk `%s' after expression"), input_line_pointer);
4736 RESTORE_END_STRING (disp_end + 1);
4738 RESTORE_END_STRING (disp_end);
4739 input_line_pointer = save_input_line_pointer;
4740 if (gotfree_input_line)
4741 free (gotfree_input_line);
4743 /* We do this to make sure that the section symbol is in
4744 the symbol table. We will ultimately change the relocation
4745 to be relative to the beginning of the section. */
4746 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4747 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4748 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4750 if (exp->X_op != O_symbol)
4752 as_bad (_("bad expression used with @%s"),
4753 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4759 if (S_IS_LOCAL (exp->X_add_symbol)
4760 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4761 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4762 exp->X_op = O_subtract;
4763 exp->X_op_symbol = GOT_symbol;
4764 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4765 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4766 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4767 i.reloc[this_operand] = BFD_RELOC_64;
4769 i.reloc[this_operand] = BFD_RELOC_32;
4772 if (exp->X_op == O_absent || exp->X_op == O_big)
4774 /* Missing or bad expr becomes absolute 0. */
4775 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4777 exp->X_op = O_constant;
4778 exp->X_add_number = 0;
4779 exp->X_add_symbol = (symbolS *) 0;
4780 exp->X_op_symbol = (symbolS *) 0;
4783 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4784 if (exp->X_op != O_constant
4785 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4786 && exp_seg != absolute_section
4787 && exp_seg != text_section
4788 && exp_seg != data_section
4789 && exp_seg != bss_section
4790 && exp_seg != undefined_section
4791 && !bfd_is_com_section (exp_seg))
4793 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4798 if (!(i.types[this_operand] & ~Disp))
4799 i.types[this_operand] &= types;
4804 /* Make sure the memory operand we've been dealt is valid.
4805 Return 1 on success, 0 on a failure. */
4808 i386_index_check (const char *operand_string)
4811 #if INFER_ADDR_PREFIX
4817 if ((current_templates->start->cpu_flags & CpuSVME)
4818 && current_templates->end[-1].operand_types[0] == AnyMem)
4820 /* Memory operands of SVME insns are special in that they only allow
4821 rAX as their memory address and ignore any segment override. */
4824 /* SKINIT is even more restrictive: it always requires EAX. */
4825 if (strcmp (current_templates->start->name, "skinit") == 0)
4827 else if (flag_code == CODE_64BIT)
4828 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4830 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4834 || !(i.base_reg->reg_type & Acc)
4835 || !(i.base_reg->reg_type & RegXX)
4837 || (i.types[0] & Disp))
4840 else if (flag_code == CODE_64BIT)
4842 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4845 && ((i.base_reg->reg_type & RegXX) == 0)
4846 && (i.base_reg->reg_type != BaseIndex
4849 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4850 != (RegXX | BaseIndex))))
4855 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4859 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4860 != (Reg16 | BaseIndex)))
4862 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4863 != (Reg16 | BaseIndex))
4865 && i.base_reg->reg_num < 6
4866 && i.index_reg->reg_num >= 6
4867 && i.log2_scale_factor == 0))))
4874 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4876 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4877 != (Reg32 | BaseIndex))))
4883 #if INFER_ADDR_PREFIX
4884 if (i.prefix[ADDR_PREFIX] == 0)
4886 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4888 /* Change the size of any displacement too. At most one of
4889 Disp16 or Disp32 is set.
4890 FIXME. There doesn't seem to be any real need for separate
4891 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4892 Removing them would probably clean up the code quite a lot. */
4893 if (flag_code != CODE_64BIT
4894 && (i.types[this_operand] & (Disp16 | Disp32)))
4895 i.types[this_operand] ^= (Disp16 | Disp32);
4900 as_bad (_("`%s' is not a valid base/index expression"),
4904 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4906 flag_code_names[flag_code]);
4911 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4915 i386_operand (char *operand_string)
4919 char *op_string = operand_string;
4921 if (is_space_char (*op_string))
4924 /* We check for an absolute prefix (differentiating,
4925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4926 if (*op_string == ABSOLUTE_PREFIX)
4929 if (is_space_char (*op_string))
4931 i.types[this_operand] |= JumpAbsolute;
4934 /* Check if operand is a register. */
4935 if ((r = parse_register (op_string, &end_op)) != NULL)
4937 /* Check for a segment override by searching for ':' after a
4938 segment register. */
4940 if (is_space_char (*op_string))
4942 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4947 i.seg[i.mem_operands] = &es;
4950 i.seg[i.mem_operands] = &cs;
4953 i.seg[i.mem_operands] = &ss;
4956 i.seg[i.mem_operands] = &ds;
4959 i.seg[i.mem_operands] = &fs;
4962 i.seg[i.mem_operands] = &gs;
4966 /* Skip the ':' and whitespace. */
4968 if (is_space_char (*op_string))
4971 if (!is_digit_char (*op_string)
4972 && !is_identifier_char (*op_string)
4973 && *op_string != '('
4974 && *op_string != ABSOLUTE_PREFIX)
4976 as_bad (_("bad memory operand `%s'"), op_string);
4979 /* Handle case of %es:*foo. */
4980 if (*op_string == ABSOLUTE_PREFIX)
4983 if (is_space_char (*op_string))
4985 i.types[this_operand] |= JumpAbsolute;
4987 goto do_memory_reference;
4991 as_bad (_("junk `%s' after register"), op_string);
4994 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4995 i.op[this_operand].regs = r;
4998 else if (*op_string == REGISTER_PREFIX)
5000 as_bad (_("bad register name `%s'"), op_string);
5003 else if (*op_string == IMMEDIATE_PREFIX)
5006 if (i.types[this_operand] & JumpAbsolute)
5008 as_bad (_("immediate operand illegal with absolute jump"));
5011 if (!i386_immediate (op_string))
5014 else if (is_digit_char (*op_string)
5015 || is_identifier_char (*op_string)
5016 || *op_string == '(')
5018 /* This is a memory reference of some sort. */
5021 /* Start and end of displacement string expression (if found). */
5022 char *displacement_string_start;
5023 char *displacement_string_end;
5025 do_memory_reference:
5026 if ((i.mem_operands == 1
5027 && (current_templates->start->opcode_modifier & IsString) == 0)
5028 || i.mem_operands == 2)
5030 as_bad (_("too many memory references for `%s'"),
5031 current_templates->start->name);
5035 /* Check for base index form. We detect the base index form by
5036 looking for an ')' at the end of the operand, searching
5037 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5039 base_string = op_string + strlen (op_string);
5042 if (is_space_char (*base_string))
5045 /* If we only have a displacement, set-up for it to be parsed later. */
5046 displacement_string_start = op_string;
5047 displacement_string_end = base_string + 1;
5049 if (*base_string == ')')
5052 unsigned int parens_balanced = 1;
5053 /* We've already checked that the number of left & right ()'s are
5054 equal, so this loop will not be infinite. */
5058 if (*base_string == ')')
5060 if (*base_string == '(')
5063 while (parens_balanced);
5065 temp_string = base_string;
5067 /* Skip past '(' and whitespace. */
5069 if (is_space_char (*base_string))
5072 if (*base_string == ','
5073 || ((i.base_reg = parse_register (base_string, &end_op))
5076 displacement_string_end = temp_string;
5078 i.types[this_operand] |= BaseIndex;
5082 base_string = end_op;
5083 if (is_space_char (*base_string))
5087 /* There may be an index reg or scale factor here. */
5088 if (*base_string == ',')
5091 if (is_space_char (*base_string))
5094 if ((i.index_reg = parse_register (base_string, &end_op))
5097 base_string = end_op;
5098 if (is_space_char (*base_string))
5100 if (*base_string == ',')
5103 if (is_space_char (*base_string))
5106 else if (*base_string != ')')
5108 as_bad (_("expecting `,' or `)' "
5109 "after index register in `%s'"),
5114 else if (*base_string == REGISTER_PREFIX)
5116 as_bad (_("bad register name `%s'"), base_string);
5120 /* Check for scale factor. */
5121 if (*base_string != ')')
5123 char *end_scale = i386_scale (base_string);
5128 base_string = end_scale;
5129 if (is_space_char (*base_string))
5131 if (*base_string != ')')
5133 as_bad (_("expecting `)' "
5134 "after scale factor in `%s'"),
5139 else if (!i.index_reg)
5141 as_bad (_("expecting index register or scale factor "
5142 "after `,'; got '%c'"),
5147 else if (*base_string != ')')
5149 as_bad (_("expecting `,' or `)' "
5150 "after base register in `%s'"),
5155 else if (*base_string == REGISTER_PREFIX)
5157 as_bad (_("bad register name `%s'"), base_string);
5162 /* If there's an expression beginning the operand, parse it,
5163 assuming displacement_string_start and
5164 displacement_string_end are meaningful. */
5165 if (displacement_string_start != displacement_string_end)
5167 if (!i386_displacement (displacement_string_start,
5168 displacement_string_end))
5172 /* Special case for (%dx) while doing input/output op. */
5174 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5176 && i.log2_scale_factor == 0
5177 && i.seg[i.mem_operands] == 0
5178 && (i.types[this_operand] & Disp) == 0)
5180 i.types[this_operand] = InOutPortReg;
5184 if (i386_index_check (operand_string) == 0)
5190 /* It's not a memory operand; argh! */
5191 as_bad (_("invalid char %s beginning operand %d `%s'"),
5192 output_invalid (*op_string),
5197 return 1; /* Normal return. */
5200 /* md_estimate_size_before_relax()
5202 Called just before relax() for rs_machine_dependent frags. The x86
5203 assembler uses these frags to handle variable size jump
5206 Any symbol that is now undefined will not become defined.
5207 Return the correct fr_subtype in the frag.
5208 Return the initial "guess for variable size of frag" to caller.
5209 The guess is actually the growth beyond the fixed part. Whatever
5210 we do to grow the fixed or variable part contributes to our
5214 md_estimate_size_before_relax (fragP, segment)
5218 /* We've already got fragP->fr_subtype right; all we have to do is
5219 check for un-relaxable symbols. On an ELF system, we can't relax
5220 an externally visible symbol, because it may be overridden by a
5222 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5225 && (S_IS_EXTERNAL (fragP->fr_symbol)
5226 || S_IS_WEAK (fragP->fr_symbol)))
5230 /* Symbol is undefined in this segment, or we need to keep a
5231 reloc so that weak symbols can be overridden. */
5232 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5233 enum bfd_reloc_code_real reloc_type;
5234 unsigned char *opcode;
5237 if (fragP->fr_var != NO_RELOC)
5238 reloc_type = fragP->fr_var;
5240 reloc_type = BFD_RELOC_16_PCREL;
5242 reloc_type = BFD_RELOC_32_PCREL;
5244 old_fr_fix = fragP->fr_fix;
5245 opcode = (unsigned char *) fragP->fr_opcode;
5247 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5250 /* Make jmp (0xeb) a (d)word displacement jump. */
5252 fragP->fr_fix += size;
5253 fix_new (fragP, old_fr_fix, size,
5255 fragP->fr_offset, 1,
5261 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5263 /* Negate the condition, and branch past an
5264 unconditional jump. */
5267 /* Insert an unconditional jump. */
5269 /* We added two extra opcode bytes, and have a two byte
5271 fragP->fr_fix += 2 + 2;
5272 fix_new (fragP, old_fr_fix + 2, 2,
5274 fragP->fr_offset, 1,
5281 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5286 fixP = fix_new (fragP, old_fr_fix, 1,
5288 fragP->fr_offset, 1,
5290 fixP->fx_signed = 1;
5294 /* This changes the byte-displacement jump 0x7N
5295 to the (d)word-displacement jump 0x0f,0x8N. */
5296 opcode[1] = opcode[0] + 0x10;
5297 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5298 /* We've added an opcode byte. */
5299 fragP->fr_fix += 1 + size;
5300 fix_new (fragP, old_fr_fix + 1, size,
5302 fragP->fr_offset, 1,
5307 BAD_CASE (fragP->fr_subtype);
5311 return fragP->fr_fix - old_fr_fix;
5314 /* Guess size depending on current relax state. Initially the relax
5315 state will correspond to a short jump and we return 1, because
5316 the variable part of the frag (the branch offset) is one byte
5317 long. However, we can relax a section more than once and in that
5318 case we must either set fr_subtype back to the unrelaxed state,
5319 or return the value for the appropriate branch. */
5320 return md_relax_table[fragP->fr_subtype].rlx_length;
5323 /* Called after relax() is finished.
5325 In: Address of frag.
5326 fr_type == rs_machine_dependent.
5327 fr_subtype is what the address relaxed to.
5329 Out: Any fixSs and constants are set up.
5330 Caller will turn frag into a ".space 0". */
5333 md_convert_frag (abfd, sec, fragP)
5334 bfd *abfd ATTRIBUTE_UNUSED;
5335 segT sec ATTRIBUTE_UNUSED;
5338 unsigned char *opcode;
5339 unsigned char *where_to_put_displacement = NULL;
5340 offsetT target_address;
5341 offsetT opcode_address;
5342 unsigned int extension = 0;
5343 offsetT displacement_from_opcode_start;
5345 opcode = (unsigned char *) fragP->fr_opcode;
5347 /* Address we want to reach in file space. */
5348 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5350 /* Address opcode resides at in file space. */
5351 opcode_address = fragP->fr_address + fragP->fr_fix;
5353 /* Displacement from opcode start to fill into instruction. */
5354 displacement_from_opcode_start = target_address - opcode_address;
5356 if ((fragP->fr_subtype & BIG) == 0)
5358 /* Don't have to change opcode. */
5359 extension = 1; /* 1 opcode + 1 displacement */
5360 where_to_put_displacement = &opcode[1];
5364 if (no_cond_jump_promotion
5365 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5366 as_warn_where (fragP->fr_file, fragP->fr_line,
5367 _("long jump required"));
5369 switch (fragP->fr_subtype)
5371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5372 extension = 4; /* 1 opcode + 4 displacement */
5374 where_to_put_displacement = &opcode[1];
5377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5378 extension = 2; /* 1 opcode + 2 displacement */
5380 where_to_put_displacement = &opcode[1];
5383 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5385 extension = 5; /* 2 opcode + 4 displacement */
5386 opcode[1] = opcode[0] + 0x10;
5387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5388 where_to_put_displacement = &opcode[2];
5391 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5392 extension = 3; /* 2 opcode + 2 displacement */
5393 opcode[1] = opcode[0] + 0x10;
5394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5395 where_to_put_displacement = &opcode[2];
5398 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5403 where_to_put_displacement = &opcode[3];
5407 BAD_CASE (fragP->fr_subtype);
5412 /* If size if less then four we are sure that the operand fits,
5413 but if it's 4, then it could be that the displacement is larger
5415 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5417 && ((addressT) (displacement_from_opcode_start - extension
5418 + ((addressT) 1 << 31))
5419 > (((addressT) 2 << 31) - 1)))
5421 as_bad_where (fragP->fr_file, fragP->fr_line,
5422 _("jump target out of range"));
5423 /* Make us emit 0. */
5424 displacement_from_opcode_start = extension;
5426 /* Now put displacement after opcode. */
5427 md_number_to_chars ((char *) where_to_put_displacement,
5428 (valueT) (displacement_from_opcode_start - extension),
5429 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5430 fragP->fr_fix += extension;
5433 /* Size of byte displacement jmp. */
5434 int md_short_jump_size = 2;
5436 /* Size of dword displacement jmp. */
5437 int md_long_jump_size = 5;
5440 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5442 addressT from_addr, to_addr;
5443 fragS *frag ATTRIBUTE_UNUSED;
5444 symbolS *to_symbol ATTRIBUTE_UNUSED;
5448 offset = to_addr - (from_addr + 2);
5449 /* Opcode for byte-disp jump. */
5450 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5451 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5455 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5457 addressT from_addr, to_addr;
5458 fragS *frag ATTRIBUTE_UNUSED;
5459 symbolS *to_symbol ATTRIBUTE_UNUSED;
5463 offset = to_addr - (from_addr + 5);
5464 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5465 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5468 /* Apply a fixup (fixS) to segment data, once it has been determined
5469 by our caller that we have all the info we need to fix it up.
5471 On the 386, immediates, displacements, and data pointers are all in
5472 the same (little-endian) format, so we don't need to care about which
5476 md_apply_fix (fixP, valP, seg)
5477 /* The fix we're to put in. */
5479 /* Pointer to the value of the bits. */
5481 /* Segment fix is from. */
5482 segT seg ATTRIBUTE_UNUSED;
5484 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5485 valueT value = *valP;
5487 #if !defined (TE_Mach)
5490 switch (fixP->fx_r_type)
5496 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5499 case BFD_RELOC_X86_64_32S:
5500 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5503 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5506 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5511 if (fixP->fx_addsy != NULL
5512 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5513 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5514 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5515 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5516 && !use_rela_relocations)
5518 /* This is a hack. There should be a better way to handle this.
5519 This covers for the fact that bfd_install_relocation will
5520 subtract the current location (for partial_inplace, PC relative
5521 relocations); see more below. */
5525 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5528 value += fixP->fx_where + fixP->fx_frag->fr_address;
5530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5533 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5536 || (symbol_section_p (fixP->fx_addsy)
5537 && sym_seg != absolute_section))
5538 && !generic_force_reloc (fixP))
5540 /* Yes, we add the values in twice. This is because
5541 bfd_install_relocation subtracts them out again. I think
5542 bfd_install_relocation is broken, but I don't dare change
5544 value += fixP->fx_where + fixP->fx_frag->fr_address;
5548 #if defined (OBJ_COFF) && defined (TE_PE)
5549 /* For some reason, the PE format does not store a
5550 section address offset for a PC relative symbol. */
5551 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5552 || S_IS_WEAK (fixP->fx_addsy))
5553 value += md_pcrel_from (fixP);
5557 /* Fix a few things - the dynamic linker expects certain values here,
5558 and we must not disappoint it. */
5559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5560 if (IS_ELF && fixP->fx_addsy)
5561 switch (fixP->fx_r_type)
5563 case BFD_RELOC_386_PLT32:
5564 case BFD_RELOC_X86_64_PLT32:
5565 /* Make the jump instruction point to the address of the operand. At
5566 runtime we merely add the offset to the actual PLT entry. */
5570 case BFD_RELOC_386_TLS_GD:
5571 case BFD_RELOC_386_TLS_LDM:
5572 case BFD_RELOC_386_TLS_IE_32:
5573 case BFD_RELOC_386_TLS_IE:
5574 case BFD_RELOC_386_TLS_GOTIE:
5575 case BFD_RELOC_386_TLS_GOTDESC:
5576 case BFD_RELOC_X86_64_TLSGD:
5577 case BFD_RELOC_X86_64_TLSLD:
5578 case BFD_RELOC_X86_64_GOTTPOFF:
5579 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5580 value = 0; /* Fully resolved at runtime. No addend. */
5582 case BFD_RELOC_386_TLS_LE:
5583 case BFD_RELOC_386_TLS_LDO_32:
5584 case BFD_RELOC_386_TLS_LE_32:
5585 case BFD_RELOC_X86_64_DTPOFF32:
5586 case BFD_RELOC_X86_64_DTPOFF64:
5587 case BFD_RELOC_X86_64_TPOFF32:
5588 case BFD_RELOC_X86_64_TPOFF64:
5589 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5592 case BFD_RELOC_386_TLS_DESC_CALL:
5593 case BFD_RELOC_X86_64_TLSDESC_CALL:
5594 value = 0; /* Fully resolved at runtime. No addend. */
5595 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5599 case BFD_RELOC_386_GOT32:
5600 case BFD_RELOC_X86_64_GOT32:
5601 value = 0; /* Fully resolved at runtime. No addend. */
5604 case BFD_RELOC_VTABLE_INHERIT:
5605 case BFD_RELOC_VTABLE_ENTRY:
5612 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5614 #endif /* !defined (TE_Mach) */
5616 /* Are we finished with this relocation now? */
5617 if (fixP->fx_addsy == NULL)
5619 else if (use_rela_relocations)
5621 fixP->fx_no_overflow = 1;
5622 /* Remember value for tc_gen_reloc. */
5623 fixP->fx_addnumber = value;
5627 md_number_to_chars (p, value, fixP->fx_size);
5630 #define MAX_LITTLENUMS 6
5632 /* Turn the string pointed to by litP into a floating point constant
5633 of type TYPE, and emit the appropriate bytes. The number of
5634 LITTLENUMS emitted is stored in *SIZEP. An error message is
5635 returned, or NULL on OK. */
5638 md_atof (type, litP, sizeP)
5644 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5645 LITTLENUM_TYPE *wordP;
5667 return _("Bad call to md_atof ()");
5669 t = atof_ieee (input_line_pointer, type, words);
5671 input_line_pointer = t;
5673 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5674 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5675 the bigendian 386. */
5676 for (wordP = words + prec - 1; prec--;)
5678 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5679 litP += sizeof (LITTLENUM_TYPE);
5684 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5687 output_invalid (int c)
5690 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5693 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5694 "(0x%x)", (unsigned char) c);
5695 return output_invalid_buf;
5698 /* REG_STRING starts *before* REGISTER_PREFIX. */
5700 static const reg_entry *
5701 parse_real_register (char *reg_string, char **end_op)
5703 char *s = reg_string;
5705 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5708 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5709 if (*s == REGISTER_PREFIX)
5712 if (is_space_char (*s))
5716 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5718 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5719 return (const reg_entry *) NULL;
5723 /* For naked regs, make sure that we are not dealing with an identifier.
5724 This prevents confusing an identifier like `eax_var' with register
5726 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5727 return (const reg_entry *) NULL;
5731 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5733 /* Handle floating point regs, allowing spaces in the (i) part. */
5734 if (r == i386_regtab /* %st is first entry of table */)
5736 if (is_space_char (*s))
5741 if (is_space_char (*s))
5743 if (*s >= '0' && *s <= '7')
5745 r = &i386_float_regtab[*s - '0'];
5747 if (is_space_char (*s))
5755 /* We have "%st(" then garbage. */
5756 return (const reg_entry *) NULL;
5761 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5762 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5763 && flag_code != CODE_64BIT)
5764 return (const reg_entry *) NULL;
5769 /* REG_STRING starts *before* REGISTER_PREFIX. */
5771 static const reg_entry *
5772 parse_register (char *reg_string, char **end_op)
5776 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5777 r = parse_real_register (reg_string, end_op);
5782 char *save = input_line_pointer;
5786 input_line_pointer = reg_string;
5787 c = get_symbol_end ();
5788 symbolP = symbol_find (reg_string);
5789 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5791 const expressionS *e = symbol_get_value_expression (symbolP);
5793 know (e->X_op == O_register);
5794 know (e->X_add_number >= 0
5795 && (valueT) e->X_add_number < i386_regtab_size);
5796 r = i386_regtab + e->X_add_number;
5797 *end_op = input_line_pointer;
5799 *input_line_pointer = c;
5800 input_line_pointer = save;
5806 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5809 char *end = input_line_pointer;
5812 r = parse_register (name, &input_line_pointer);
5813 if (r && end <= input_line_pointer)
5815 *nextcharP = *input_line_pointer;
5816 *input_line_pointer = 0;
5817 e->X_op = O_register;
5818 e->X_add_number = r - i386_regtab;
5821 input_line_pointer = end;
5827 md_operand (expressionS *e)
5829 if (*input_line_pointer == REGISTER_PREFIX)
5832 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5836 e->X_op = O_register;
5837 e->X_add_number = r - i386_regtab;
5838 input_line_pointer = end;
5844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5845 const char *md_shortopts = "kVQ:sqn";
5847 const char *md_shortopts = "qn";
5850 #define OPTION_32 (OPTION_MD_BASE + 0)
5851 #define OPTION_64 (OPTION_MD_BASE + 1)
5852 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5853 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5854 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5856 struct option md_longopts[] =
5858 {"32", no_argument, NULL, OPTION_32},
5859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5860 {"64", no_argument, NULL, OPTION_64},
5862 {"divide", no_argument, NULL, OPTION_DIVIDE},
5863 {"march", required_argument, NULL, OPTION_MARCH},
5864 {"mtune", required_argument, NULL, OPTION_MTUNE},
5865 {NULL, no_argument, NULL, 0}
5867 size_t md_longopts_size = sizeof (md_longopts);
5870 md_parse_option (int c, char *arg)
5877 optimize_align_code = 0;
5884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5885 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5886 should be emitted or not. FIXME: Not implemented. */
5890 /* -V: SVR4 argument to print version ID. */
5892 print_version_id ();
5895 /* -k: Ignore for FreeBSD compatibility. */
5900 /* -s: On i386 Solaris, this tells the native assembler to use
5901 .stab instead of .stab.excl. We always use .stab anyhow. */
5904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5907 const char **list, **l;
5909 list = bfd_target_list ();
5910 for (l = list; *l != NULL; l++)
5911 if (CONST_STRNEQ (*l, "elf64-x86-64")
5912 || strcmp (*l, "coff-x86-64") == 0
5913 || strcmp (*l, "pe-x86-64") == 0
5914 || strcmp (*l, "pei-x86-64") == 0)
5916 default_arch = "x86_64";
5920 as_fatal (_("No compiled in support for x86_64"));
5927 default_arch = "i386";
5931 #ifdef SVR4_COMMENT_CHARS
5936 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5938 for (s = i386_comment_chars; *s != '\0'; s++)
5942 i386_comment_chars = n;
5949 as_fatal (_("Invalid -march= option: `%s'"), arg);
5950 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5952 if (strcmp (arg, cpu_arch [i].name) == 0)
5954 cpu_arch_isa = cpu_arch[i].type;
5955 cpu_arch_isa_flags = cpu_arch[i].flags;
5956 if (!cpu_arch_tune_set)
5958 cpu_arch_tune = cpu_arch_isa;
5959 cpu_arch_tune_flags = cpu_arch_isa_flags;
5964 if (i >= ARRAY_SIZE (cpu_arch))
5965 as_fatal (_("Invalid -march= option: `%s'"), arg);
5970 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5971 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5973 if (strcmp (arg, cpu_arch [i].name) == 0)
5975 cpu_arch_tune_set = 1;
5976 cpu_arch_tune = cpu_arch [i].type;
5977 cpu_arch_tune_flags = cpu_arch[i].flags;
5981 if (i >= ARRAY_SIZE (cpu_arch))
5982 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5992 md_show_usage (stream)
5995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5996 fprintf (stream, _("\
5998 -V print assembler version number\n\
6001 fprintf (stream, _("\
6002 -n Do not optimize code alignment\n\
6003 -q quieten some warnings\n"));
6004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6005 fprintf (stream, _("\
6008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6009 fprintf (stream, _("\
6010 --32/--64 generate 32bit/64bit code\n"));
6012 #ifdef SVR4_COMMENT_CHARS
6013 fprintf (stream, _("\
6014 --divide do not treat `/' as a comment character\n"));
6016 fprintf (stream, _("\
6017 --divide ignored\n"));
6019 fprintf (stream, _("\
6020 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6021 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6022 core, core2, k6, athlon, k8, generic32, generic64\n"));
6028 x86_64_target_format (void)
6030 if (strcmp (default_arch, "x86_64") == 0)
6032 set_code_flag (CODE_64BIT);
6033 return COFF_TARGET_FORMAT;
6035 else if (strcmp (default_arch, "i386") == 0)
6037 set_code_flag (CODE_32BIT);
6041 as_fatal (_("Unknown architecture"));
6046 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6047 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6049 /* Pick the target format to use. */
6052 i386_target_format (void)
6054 if (!strcmp (default_arch, "x86_64"))
6056 set_code_flag (CODE_64BIT);
6057 if (cpu_arch_isa_flags == 0)
6058 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6059 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6061 if (cpu_arch_tune_flags == 0)
6062 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6063 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6066 else if (!strcmp (default_arch, "i386"))
6068 set_code_flag (CODE_32BIT);
6069 if (cpu_arch_isa_flags == 0)
6070 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6071 if (cpu_arch_tune_flags == 0)
6072 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6075 as_fatal (_("Unknown architecture"));
6076 switch (OUTPUT_FLAVOR)
6078 #ifdef OBJ_MAYBE_AOUT
6079 case bfd_target_aout_flavour:
6080 return AOUT_TARGET_FORMAT;
6082 #ifdef OBJ_MAYBE_COFF
6083 case bfd_target_coff_flavour:
6086 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6087 case bfd_target_elf_flavour:
6089 if (flag_code == CODE_64BIT)
6092 use_rela_relocations = 1;
6094 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6103 #endif /* OBJ_MAYBE_ more than one */
6105 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6107 i386_elf_emit_arch_note (void)
6109 if (IS_ELF && cpu_arch_name != NULL)
6112 asection *seg = now_seg;
6113 subsegT subseg = now_subseg;
6114 Elf_Internal_Note i_note;
6115 Elf_External_Note e_note;
6116 asection *note_secp;
6119 /* Create the .note section. */
6120 note_secp = subseg_new (".note", 0);
6121 bfd_set_section_flags (stdoutput,
6123 SEC_HAS_CONTENTS | SEC_READONLY);
6125 /* Process the arch string. */
6126 len = strlen (cpu_arch_name);
6128 i_note.namesz = len + 1;
6130 i_note.type = NT_ARCH;
6131 p = frag_more (sizeof (e_note.namesz));
6132 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6133 p = frag_more (sizeof (e_note.descsz));
6134 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6135 p = frag_more (sizeof (e_note.type));
6136 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6137 p = frag_more (len + 1);
6138 strcpy (p, cpu_arch_name);
6140 frag_align (2, 0, 0);
6142 subseg_set (seg, subseg);
6148 md_undefined_symbol (name)
6151 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6152 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6153 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6154 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6158 if (symbol_find (name))
6159 as_bad (_("GOT already in symbol table"));
6160 GOT_symbol = symbol_new (name, undefined_section,
6161 (valueT) 0, &zero_address_frag);
6168 /* Round up a section size to the appropriate boundary. */
6171 md_section_align (segment, size)
6172 segT segment ATTRIBUTE_UNUSED;
6175 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6176 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6178 /* For a.out, force the section size to be aligned. If we don't do
6179 this, BFD will align it for us, but it will not write out the
6180 final bytes of the section. This may be a bug in BFD, but it is
6181 easier to fix it here since that is how the other a.out targets
6185 align = bfd_get_section_alignment (stdoutput, segment);
6186 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6193 /* On the i386, PC-relative offsets are relative to the start of the
6194 next instruction. That is, the address of the offset, plus its
6195 size, since the offset is always the last part of the insn. */
6198 md_pcrel_from (fixS *fixP)
6200 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6206 s_bss (int ignore ATTRIBUTE_UNUSED)
6210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6212 obj_elf_section_change_hook ();
6214 temp = get_absolute_expression ();
6215 subseg_set (bss_section, (subsegT) temp);
6216 demand_empty_rest_of_line ();
6222 i386_validate_fix (fixS *fixp)
6224 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6226 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6230 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6235 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6237 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6244 tc_gen_reloc (section, fixp)
6245 asection *section ATTRIBUTE_UNUSED;
6249 bfd_reloc_code_real_type code;
6251 switch (fixp->fx_r_type)
6253 case BFD_RELOC_X86_64_PLT32:
6254 case BFD_RELOC_X86_64_GOT32:
6255 case BFD_RELOC_X86_64_GOTPCREL:
6256 case BFD_RELOC_386_PLT32:
6257 case BFD_RELOC_386_GOT32:
6258 case BFD_RELOC_386_GOTOFF:
6259 case BFD_RELOC_386_GOTPC:
6260 case BFD_RELOC_386_TLS_GD:
6261 case BFD_RELOC_386_TLS_LDM:
6262 case BFD_RELOC_386_TLS_LDO_32:
6263 case BFD_RELOC_386_TLS_IE_32:
6264 case BFD_RELOC_386_TLS_IE:
6265 case BFD_RELOC_386_TLS_GOTIE:
6266 case BFD_RELOC_386_TLS_LE_32:
6267 case BFD_RELOC_386_TLS_LE:
6268 case BFD_RELOC_386_TLS_GOTDESC:
6269 case BFD_RELOC_386_TLS_DESC_CALL:
6270 case BFD_RELOC_X86_64_TLSGD:
6271 case BFD_RELOC_X86_64_TLSLD:
6272 case BFD_RELOC_X86_64_DTPOFF32:
6273 case BFD_RELOC_X86_64_DTPOFF64:
6274 case BFD_RELOC_X86_64_GOTTPOFF:
6275 case BFD_RELOC_X86_64_TPOFF32:
6276 case BFD_RELOC_X86_64_TPOFF64:
6277 case BFD_RELOC_X86_64_GOTOFF64:
6278 case BFD_RELOC_X86_64_GOTPC32:
6279 case BFD_RELOC_X86_64_GOT64:
6280 case BFD_RELOC_X86_64_GOTPCREL64:
6281 case BFD_RELOC_X86_64_GOTPC64:
6282 case BFD_RELOC_X86_64_GOTPLT64:
6283 case BFD_RELOC_X86_64_PLTOFF64:
6284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6285 case BFD_RELOC_X86_64_TLSDESC_CALL:
6287 case BFD_RELOC_VTABLE_ENTRY:
6288 case BFD_RELOC_VTABLE_INHERIT:
6290 case BFD_RELOC_32_SECREL:
6292 code = fixp->fx_r_type;
6294 case BFD_RELOC_X86_64_32S:
6295 if (!fixp->fx_pcrel)
6297 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6298 code = fixp->fx_r_type;
6304 switch (fixp->fx_size)
6307 as_bad_where (fixp->fx_file, fixp->fx_line,
6308 _("can not do %d byte pc-relative relocation"),
6310 code = BFD_RELOC_32_PCREL;
6312 case 1: code = BFD_RELOC_8_PCREL; break;
6313 case 2: code = BFD_RELOC_16_PCREL; break;
6314 case 4: code = BFD_RELOC_32_PCREL; break;
6316 case 8: code = BFD_RELOC_64_PCREL; break;
6322 switch (fixp->fx_size)
6325 as_bad_where (fixp->fx_file, fixp->fx_line,
6326 _("can not do %d byte relocation"),
6328 code = BFD_RELOC_32;
6330 case 1: code = BFD_RELOC_8; break;
6331 case 2: code = BFD_RELOC_16; break;
6332 case 4: code = BFD_RELOC_32; break;
6334 case 8: code = BFD_RELOC_64; break;
6341 if ((code == BFD_RELOC_32
6342 || code == BFD_RELOC_32_PCREL
6343 || code == BFD_RELOC_X86_64_32S)
6345 && fixp->fx_addsy == GOT_symbol)
6348 code = BFD_RELOC_386_GOTPC;
6350 code = BFD_RELOC_X86_64_GOTPC32;
6352 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6354 && fixp->fx_addsy == GOT_symbol)
6356 code = BFD_RELOC_X86_64_GOTPC64;
6359 rel = (arelent *) xmalloc (sizeof (arelent));
6360 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6361 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6363 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6365 if (!use_rela_relocations)
6367 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6368 vtable entry to be used in the relocation's section offset. */
6369 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6370 rel->address = fixp->fx_offset;
6374 /* Use the rela in 64bit mode. */
6377 if (!fixp->fx_pcrel)
6378 rel->addend = fixp->fx_offset;
6382 case BFD_RELOC_X86_64_PLT32:
6383 case BFD_RELOC_X86_64_GOT32:
6384 case BFD_RELOC_X86_64_GOTPCREL:
6385 case BFD_RELOC_X86_64_TLSGD:
6386 case BFD_RELOC_X86_64_TLSLD:
6387 case BFD_RELOC_X86_64_GOTTPOFF:
6388 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6389 case BFD_RELOC_X86_64_TLSDESC_CALL:
6390 rel->addend = fixp->fx_offset - fixp->fx_size;
6393 rel->addend = (section->vma
6395 + fixp->fx_addnumber
6396 + md_pcrel_from (fixp));
6401 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6402 if (rel->howto == NULL)
6404 as_bad_where (fixp->fx_file, fixp->fx_line,
6405 _("cannot represent relocation type %s"),
6406 bfd_get_reloc_code_name (code));
6407 /* Set howto to a garbage value so that we can keep going. */
6408 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6409 assert (rel->howto != NULL);
6416 /* Parse operands using Intel syntax. This implements a recursive descent
6417 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6420 FIXME: We do not recognize the full operand grammar defined in the MASM
6421 documentation. In particular, all the structure/union and
6422 high-level macro operands are missing.
6424 Uppercase words are terminals, lower case words are non-terminals.
6425 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6426 bars '|' denote choices. Most grammar productions are implemented in
6427 functions called 'intel_<production>'.
6429 Initial production is 'expr'.
6435 binOp & | AND | \| | OR | ^ | XOR
6437 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6439 constant digits [[ radixOverride ]]
6441 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6479 => expr expr cmpOp e04
6482 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6483 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6485 hexdigit a | b | c | d | e | f
6486 | A | B | C | D | E | F
6492 mulOp * | / | % | MOD | << | SHL | >> | SHR
6496 register specialRegister
6500 segmentRegister CS | DS | ES | FS | GS | SS
6502 specialRegister CR0 | CR2 | CR3 | CR4
6503 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6504 | TR3 | TR4 | TR5 | TR6 | TR7
6506 We simplify the grammar in obvious places (e.g., register parsing is
6507 done by calling parse_register) and eliminate immediate left recursion
6508 to implement a recursive-descent parser.
6512 expr' cmpOp e04 expr'
6563 /* Parsing structure for the intel syntax parser. Used to implement the
6564 semantic actions for the operand grammar. */
6565 struct intel_parser_s
6567 char *op_string; /* The string being parsed. */
6568 int got_a_float; /* Whether the operand is a float. */
6569 int op_modifier; /* Operand modifier. */
6570 int is_mem; /* 1 if operand is memory reference. */
6571 int in_offset; /* >=1 if parsing operand of offset. */
6572 int in_bracket; /* >=1 if parsing operand in brackets. */
6573 const reg_entry *reg; /* Last register reference found. */
6574 char *disp; /* Displacement string being built. */
6575 char *next_operand; /* Resume point when splitting operands. */
6578 static struct intel_parser_s intel_parser;
6580 /* Token structure for parsing intel syntax. */
6583 int code; /* Token code. */
6584 const reg_entry *reg; /* Register entry for register tokens. */
6585 char *str; /* String representation. */
6588 static struct intel_token cur_token, prev_token;
6590 /* Token codes for the intel parser. Since T_SHORT is already used
6591 by COFF, undefine it first to prevent a warning. */
6610 /* Prototypes for intel parser functions. */
6611 static int intel_match_token (int);
6612 static void intel_putback_token (void);
6613 static void intel_get_token (void);
6614 static int intel_expr (void);
6615 static int intel_e04 (void);
6616 static int intel_e05 (void);
6617 static int intel_e06 (void);
6618 static int intel_e09 (void);
6619 static int intel_e10 (void);
6620 static int intel_e11 (void);
6623 i386_intel_operand (char *operand_string, int got_a_float)
6628 p = intel_parser.op_string = xstrdup (operand_string);
6629 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6633 /* Initialize token holders. */
6634 cur_token.code = prev_token.code = T_NIL;
6635 cur_token.reg = prev_token.reg = NULL;
6636 cur_token.str = prev_token.str = NULL;
6638 /* Initialize parser structure. */
6639 intel_parser.got_a_float = got_a_float;
6640 intel_parser.op_modifier = 0;
6641 intel_parser.is_mem = 0;
6642 intel_parser.in_offset = 0;
6643 intel_parser.in_bracket = 0;
6644 intel_parser.reg = NULL;
6645 intel_parser.disp[0] = '\0';
6646 intel_parser.next_operand = NULL;
6648 /* Read the first token and start the parser. */
6650 ret = intel_expr ();
6655 if (cur_token.code != T_NIL)
6657 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6658 current_templates->start->name, cur_token.str);
6661 /* If we found a memory reference, hand it over to i386_displacement
6662 to fill in the rest of the operand fields. */
6663 else if (intel_parser.is_mem)
6665 if ((i.mem_operands == 1
6666 && (current_templates->start->opcode_modifier & IsString) == 0)
6667 || i.mem_operands == 2)
6669 as_bad (_("too many memory references for '%s'"),
6670 current_templates->start->name);
6675 char *s = intel_parser.disp;
6678 if (!quiet_warnings && intel_parser.is_mem < 0)
6679 /* See the comments in intel_bracket_expr. */
6680 as_warn (_("Treating `%s' as memory reference"), operand_string);
6682 /* Add the displacement expression. */
6684 ret = i386_displacement (s, s + strlen (s));
6687 /* Swap base and index in 16-bit memory operands like
6688 [si+bx]. Since i386_index_check is also used in AT&T
6689 mode we have to do that here. */
6692 && (i.base_reg->reg_type & Reg16)
6693 && (i.index_reg->reg_type & Reg16)
6694 && i.base_reg->reg_num >= 6
6695 && i.index_reg->reg_num < 6)
6697 const reg_entry *base = i.index_reg;
6699 i.index_reg = i.base_reg;
6702 ret = i386_index_check (operand_string);
6707 /* Constant and OFFSET expressions are handled by i386_immediate. */
6708 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6709 || intel_parser.reg == NULL)
6710 ret = i386_immediate (intel_parser.disp);
6712 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6714 if (!ret || !intel_parser.next_operand)
6716 intel_parser.op_string = intel_parser.next_operand;
6717 this_operand = i.operands++;
6721 free (intel_parser.disp);
6726 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6730 expr' cmpOp e04 expr'
6735 /* XXX Implement the comparison operators. */
6736 return intel_e04 ();
6753 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6754 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6756 if (cur_token.code == '+')
6758 else if (cur_token.code == '-')
6759 nregs = NUM_ADDRESS_REGS;
6763 strcat (intel_parser.disp, cur_token.str);
6764 intel_match_token (cur_token.code);
6775 int nregs = ~NUM_ADDRESS_REGS;
6782 if (cur_token.code == '&'
6783 || cur_token.code == '|'
6784 || cur_token.code == '^')
6788 str[0] = cur_token.code;
6790 strcat (intel_parser.disp, str);
6795 intel_match_token (cur_token.code);
6800 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6801 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6812 int nregs = ~NUM_ADDRESS_REGS;
6819 if (cur_token.code == '*'
6820 || cur_token.code == '/'
6821 || cur_token.code == '%')
6825 str[0] = cur_token.code;
6827 strcat (intel_parser.disp, str);
6829 else if (cur_token.code == T_SHL)
6830 strcat (intel_parser.disp, "<<");
6831 else if (cur_token.code == T_SHR)
6832 strcat (intel_parser.disp, ">>");
6836 intel_match_token (cur_token.code);
6841 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6842 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6860 int nregs = ~NUM_ADDRESS_REGS;
6865 /* Don't consume constants here. */
6866 if (cur_token.code == '+' || cur_token.code == '-')
6868 /* Need to look one token ahead - if the next token
6869 is a constant, the current token is its sign. */
6872 intel_match_token (cur_token.code);
6873 next_code = cur_token.code;
6874 intel_putback_token ();
6875 if (next_code == T_CONST)
6879 /* e09 OFFSET e09 */
6880 if (cur_token.code == T_OFFSET)
6883 ++intel_parser.in_offset;
6887 else if (cur_token.code == T_SHORT)
6888 intel_parser.op_modifier |= 1 << T_SHORT;
6891 else if (cur_token.code == '+')
6892 strcat (intel_parser.disp, "+");
6897 else if (cur_token.code == '-' || cur_token.code == '~')
6903 str[0] = cur_token.code;
6905 strcat (intel_parser.disp, str);
6912 intel_match_token (cur_token.code);
6920 /* e09' PTR e10 e09' */
6921 if (cur_token.code == T_PTR)
6925 if (prev_token.code == T_BYTE)
6926 suffix = BYTE_MNEM_SUFFIX;
6928 else if (prev_token.code == T_WORD)
6930 if (current_templates->start->name[0] == 'l'
6931 && current_templates->start->name[2] == 's'
6932 && current_templates->start->name[3] == 0)
6933 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6934 else if (intel_parser.got_a_float == 2) /* "fi..." */
6935 suffix = SHORT_MNEM_SUFFIX;
6937 suffix = WORD_MNEM_SUFFIX;
6940 else if (prev_token.code == T_DWORD)
6942 if (current_templates->start->name[0] == 'l'
6943 && current_templates->start->name[2] == 's'
6944 && current_templates->start->name[3] == 0)
6945 suffix = WORD_MNEM_SUFFIX;
6946 else if (flag_code == CODE_16BIT
6947 && (current_templates->start->opcode_modifier
6948 & (Jump | JumpDword)))
6949 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6950 else if (intel_parser.got_a_float == 1) /* "f..." */
6951 suffix = SHORT_MNEM_SUFFIX;
6953 suffix = LONG_MNEM_SUFFIX;
6956 else if (prev_token.code == T_FWORD)
6958 if (current_templates->start->name[0] == 'l'
6959 && current_templates->start->name[2] == 's'
6960 && current_templates->start->name[3] == 0)
6961 suffix = LONG_MNEM_SUFFIX;
6962 else if (!intel_parser.got_a_float)
6964 if (flag_code == CODE_16BIT)
6965 add_prefix (DATA_PREFIX_OPCODE);
6966 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6969 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6972 else if (prev_token.code == T_QWORD)
6974 if (intel_parser.got_a_float == 1) /* "f..." */
6975 suffix = LONG_MNEM_SUFFIX;
6977 suffix = QWORD_MNEM_SUFFIX;
6980 else if (prev_token.code == T_TBYTE)
6982 if (intel_parser.got_a_float == 1)
6983 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6985 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6988 else if (prev_token.code == T_XMMWORD)
6990 /* XXX ignored for now, but accepted since gcc uses it */
6996 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7000 /* Operands for jump/call using 'ptr' notation denote absolute
7002 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7003 i.types[this_operand] |= JumpAbsolute;
7005 if (current_templates->start->base_opcode == 0x8d /* lea */)
7009 else if (i.suffix != suffix)
7011 as_bad (_("Conflicting operand modifiers"));
7017 /* e09' : e10 e09' */
7018 else if (cur_token.code == ':')
7020 if (prev_token.code != T_REG)
7022 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7023 segment/group identifier (which we don't have), using comma
7024 as the operand separator there is even less consistent, since
7025 there all branches only have a single operand. */
7026 if (this_operand != 0
7027 || intel_parser.in_offset
7028 || intel_parser.in_bracket
7029 || (!(current_templates->start->opcode_modifier
7030 & (Jump|JumpDword|JumpInterSegment))
7031 && !(current_templates->start->operand_types[0]
7033 return intel_match_token (T_NIL);
7034 /* Remember the start of the 2nd operand and terminate 1st
7036 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7037 another expression), but it gets at least the simplest case
7038 (a plain number or symbol on the left side) right. */
7039 intel_parser.next_operand = intel_parser.op_string;
7040 *--intel_parser.op_string = '\0';
7041 return intel_match_token (':');
7049 intel_match_token (cur_token.code);
7055 --intel_parser.in_offset;
7058 if (NUM_ADDRESS_REGS > nregs)
7060 as_bad (_("Invalid operand to `OFFSET'"));
7063 intel_parser.op_modifier |= 1 << T_OFFSET;
7066 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7067 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7072 intel_bracket_expr (void)
7074 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7075 const char *start = intel_parser.op_string;
7078 if (i.op[this_operand].regs)
7079 return intel_match_token (T_NIL);
7081 intel_match_token ('[');
7083 /* Mark as a memory operand only if it's not already known to be an
7084 offset expression. If it's an offset expression, we need to keep
7086 if (!intel_parser.in_offset)
7088 ++intel_parser.in_bracket;
7090 /* Operands for jump/call inside brackets denote absolute addresses. */
7091 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7092 i.types[this_operand] |= JumpAbsolute;
7094 /* Unfortunately gas always diverged from MASM in a respect that can't
7095 be easily fixed without risking to break code sequences likely to be
7096 encountered (the testsuite even check for this): MASM doesn't consider
7097 an expression inside brackets unconditionally as a memory reference.
7098 When that is e.g. a constant, an offset expression, or the sum of the
7099 two, this is still taken as a constant load. gas, however, always
7100 treated these as memory references. As a compromise, we'll try to make
7101 offset expressions inside brackets work the MASM way (since that's
7102 less likely to be found in real world code), but make constants alone
7103 continue to work the traditional gas way. In either case, issue a
7105 intel_parser.op_modifier &= ~was_offset;
7108 strcat (intel_parser.disp, "[");
7110 /* Add a '+' to the displacement string if necessary. */
7111 if (*intel_parser.disp != '\0'
7112 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7113 strcat (intel_parser.disp, "+");
7116 && (len = intel_parser.op_string - start - 1,
7117 intel_match_token (']')))
7119 /* Preserve brackets when the operand is an offset expression. */
7120 if (intel_parser.in_offset)
7121 strcat (intel_parser.disp, "]");
7124 --intel_parser.in_bracket;
7125 if (i.base_reg || i.index_reg)
7126 intel_parser.is_mem = 1;
7127 if (!intel_parser.is_mem)
7129 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7130 /* Defer the warning until all of the operand was parsed. */
7131 intel_parser.is_mem = -1;
7132 else if (!quiet_warnings)
7133 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7134 len, start, len, start);
7137 intel_parser.op_modifier |= was_offset;
7154 while (cur_token.code == '[')
7156 if (!intel_bracket_expr ())
7181 switch (cur_token.code)
7185 intel_match_token ('(');
7186 strcat (intel_parser.disp, "(");
7188 if (intel_expr () && intel_match_token (')'))
7190 strcat (intel_parser.disp, ")");
7197 return intel_bracket_expr ();
7202 strcat (intel_parser.disp, cur_token.str);
7203 intel_match_token (cur_token.code);
7205 /* Mark as a memory operand only if it's not already known to be an
7206 offset expression. */
7207 if (!intel_parser.in_offset)
7208 intel_parser.is_mem = 1;
7215 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7217 intel_match_token (T_REG);
7219 /* Check for segment change. */
7220 if (cur_token.code == ':')
7222 if (!(reg->reg_type & (SReg2 | SReg3)))
7224 as_bad (_("`%s' is not a valid segment register"),
7228 else if (i.seg[i.mem_operands])
7229 as_warn (_("Extra segment override ignored"));
7232 if (!intel_parser.in_offset)
7233 intel_parser.is_mem = 1;
7234 switch (reg->reg_num)
7237 i.seg[i.mem_operands] = &es;
7240 i.seg[i.mem_operands] = &cs;
7243 i.seg[i.mem_operands] = &ss;
7246 i.seg[i.mem_operands] = &ds;
7249 i.seg[i.mem_operands] = &fs;
7252 i.seg[i.mem_operands] = &gs;
7258 /* Not a segment register. Check for register scaling. */
7259 else if (cur_token.code == '*')
7261 if (!intel_parser.in_bracket)
7263 as_bad (_("Register scaling only allowed in memory operands"));
7267 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7268 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7269 else if (i.index_reg)
7270 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7272 /* What follows must be a valid scale. */
7273 intel_match_token ('*');
7275 i.types[this_operand] |= BaseIndex;
7277 /* Set the scale after setting the register (otherwise,
7278 i386_scale will complain) */
7279 if (cur_token.code == '+' || cur_token.code == '-')
7281 char *str, sign = cur_token.code;
7282 intel_match_token (cur_token.code);
7283 if (cur_token.code != T_CONST)
7285 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7289 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7290 strcpy (str + 1, cur_token.str);
7292 if (!i386_scale (str))
7296 else if (!i386_scale (cur_token.str))
7298 intel_match_token (cur_token.code);
7301 /* No scaling. If this is a memory operand, the register is either a
7302 base register (first occurrence) or an index register (second
7304 else if (intel_parser.in_bracket)
7309 else if (!i.index_reg)
7313 as_bad (_("Too many register references in memory operand"));
7317 i.types[this_operand] |= BaseIndex;
7320 /* It's neither base nor index. */
7321 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7323 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7324 i.op[this_operand].regs = reg;
7329 as_bad (_("Invalid use of register"));
7333 /* Since registers are not part of the displacement string (except
7334 when we're parsing offset operands), we may need to remove any
7335 preceding '+' from the displacement string. */
7336 if (*intel_parser.disp != '\0'
7337 && !intel_parser.in_offset)
7339 char *s = intel_parser.disp;
7340 s += strlen (s) - 1;
7363 intel_match_token (cur_token.code);
7365 if (cur_token.code == T_PTR)
7368 /* It must have been an identifier. */
7369 intel_putback_token ();
7370 cur_token.code = T_ID;
7376 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7380 /* The identifier represents a memory reference only if it's not
7381 preceded by an offset modifier and if it's not an equate. */
7382 symbolP = symbol_find(cur_token.str);
7383 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7384 intel_parser.is_mem = 1;
7392 char *save_str, sign = 0;
7394 /* Allow constants that start with `+' or `-'. */
7395 if (cur_token.code == '-' || cur_token.code == '+')
7397 sign = cur_token.code;
7398 intel_match_token (cur_token.code);
7399 if (cur_token.code != T_CONST)
7401 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7407 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7408 strcpy (save_str + !!sign, cur_token.str);
7412 /* Get the next token to check for register scaling. */
7413 intel_match_token (cur_token.code);
7415 /* Check if this constant is a scaling factor for an
7417 if (cur_token.code == '*')
7419 if (intel_match_token ('*') && cur_token.code == T_REG)
7421 const reg_entry *reg = cur_token.reg;
7423 if (!intel_parser.in_bracket)
7425 as_bad (_("Register scaling only allowed "
7426 "in memory operands"));
7430 /* Disallow things like [1*si].
7431 sp and esp are invalid as index. */
7432 if (reg->reg_type & Reg16)
7433 reg = i386_regtab + REGNAM_AX + 4;
7434 else if (i.index_reg)
7435 reg = i386_regtab + REGNAM_EAX + 4;
7437 /* The constant is followed by `* reg', so it must be
7440 i.types[this_operand] |= BaseIndex;
7442 /* Set the scale after setting the register (otherwise,
7443 i386_scale will complain) */
7444 if (!i386_scale (save_str))
7446 intel_match_token (T_REG);
7448 /* Since registers are not part of the displacement
7449 string, we may need to remove any preceding '+' from
7450 the displacement string. */
7451 if (*intel_parser.disp != '\0')
7453 char *s = intel_parser.disp;
7454 s += strlen (s) - 1;
7464 /* The constant was not used for register scaling. Since we have
7465 already consumed the token following `*' we now need to put it
7466 back in the stream. */
7467 intel_putback_token ();
7470 /* Add the constant to the displacement string. */
7471 strcat (intel_parser.disp, save_str);
7478 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7482 /* Match the given token against cur_token. If they match, read the next
7483 token from the operand string. */
7485 intel_match_token (int code)
7487 if (cur_token.code == code)
7494 as_bad (_("Unexpected token `%s'"), cur_token.str);
7499 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7501 intel_get_token (void)
7504 const reg_entry *reg;
7505 struct intel_token new_token;
7507 new_token.code = T_NIL;
7508 new_token.reg = NULL;
7509 new_token.str = NULL;
7511 /* Free the memory allocated to the previous token and move
7512 cur_token to prev_token. */
7514 free (prev_token.str);
7516 prev_token = cur_token;
7518 /* Skip whitespace. */
7519 while (is_space_char (*intel_parser.op_string))
7520 intel_parser.op_string++;
7522 /* Return an empty token if we find nothing else on the line. */
7523 if (*intel_parser.op_string == '\0')
7525 cur_token = new_token;
7529 /* The new token cannot be larger than the remainder of the operand
7531 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7532 new_token.str[0] = '\0';
7534 if (strchr ("0123456789", *intel_parser.op_string))
7536 char *p = new_token.str;
7537 char *q = intel_parser.op_string;
7538 new_token.code = T_CONST;
7540 /* Allow any kind of identifier char to encompass floating point and
7541 hexadecimal numbers. */
7542 while (is_identifier_char (*q))
7546 /* Recognize special symbol names [0-9][bf]. */
7547 if (strlen (intel_parser.op_string) == 2
7548 && (intel_parser.op_string[1] == 'b'
7549 || intel_parser.op_string[1] == 'f'))
7550 new_token.code = T_ID;
7553 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7555 size_t len = end_op - intel_parser.op_string;
7557 new_token.code = T_REG;
7558 new_token.reg = reg;
7560 memcpy (new_token.str, intel_parser.op_string, len);
7561 new_token.str[len] = '\0';
7564 else if (is_identifier_char (*intel_parser.op_string))
7566 char *p = new_token.str;
7567 char *q = intel_parser.op_string;
7569 /* A '.' or '$' followed by an identifier char is an identifier.
7570 Otherwise, it's operator '.' followed by an expression. */
7571 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7573 new_token.code = '.';
7574 new_token.str[0] = '.';
7575 new_token.str[1] = '\0';
7579 while (is_identifier_char (*q) || *q == '@')
7583 if (strcasecmp (new_token.str, "NOT") == 0)
7584 new_token.code = '~';
7586 else if (strcasecmp (new_token.str, "MOD") == 0)
7587 new_token.code = '%';
7589 else if (strcasecmp (new_token.str, "AND") == 0)
7590 new_token.code = '&';
7592 else if (strcasecmp (new_token.str, "OR") == 0)
7593 new_token.code = '|';
7595 else if (strcasecmp (new_token.str, "XOR") == 0)
7596 new_token.code = '^';
7598 else if (strcasecmp (new_token.str, "SHL") == 0)
7599 new_token.code = T_SHL;
7601 else if (strcasecmp (new_token.str, "SHR") == 0)
7602 new_token.code = T_SHR;
7604 else if (strcasecmp (new_token.str, "BYTE") == 0)
7605 new_token.code = T_BYTE;
7607 else if (strcasecmp (new_token.str, "WORD") == 0)
7608 new_token.code = T_WORD;
7610 else if (strcasecmp (new_token.str, "DWORD") == 0)
7611 new_token.code = T_DWORD;
7613 else if (strcasecmp (new_token.str, "FWORD") == 0)
7614 new_token.code = T_FWORD;
7616 else if (strcasecmp (new_token.str, "QWORD") == 0)
7617 new_token.code = T_QWORD;
7619 else if (strcasecmp (new_token.str, "TBYTE") == 0
7620 /* XXX remove (gcc still uses it) */
7621 || strcasecmp (new_token.str, "XWORD") == 0)
7622 new_token.code = T_TBYTE;
7624 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7625 || strcasecmp (new_token.str, "OWORD") == 0)
7626 new_token.code = T_XMMWORD;
7628 else if (strcasecmp (new_token.str, "PTR") == 0)
7629 new_token.code = T_PTR;
7631 else if (strcasecmp (new_token.str, "SHORT") == 0)
7632 new_token.code = T_SHORT;
7634 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7636 new_token.code = T_OFFSET;
7638 /* ??? This is not mentioned in the MASM grammar but gcc
7639 makes use of it with -mintel-syntax. OFFSET may be
7640 followed by FLAT: */
7641 if (strncasecmp (q, " FLAT:", 6) == 0)
7642 strcat (new_token.str, " FLAT:");
7645 /* ??? This is not mentioned in the MASM grammar. */
7646 else if (strcasecmp (new_token.str, "FLAT") == 0)
7648 new_token.code = T_OFFSET;
7650 strcat (new_token.str, ":");
7652 as_bad (_("`:' expected"));
7656 new_token.code = T_ID;
7660 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7662 new_token.code = *intel_parser.op_string;
7663 new_token.str[0] = *intel_parser.op_string;
7664 new_token.str[1] = '\0';
7667 else if (strchr ("<>", *intel_parser.op_string)
7668 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7670 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7671 new_token.str[0] = *intel_parser.op_string;
7672 new_token.str[1] = *intel_parser.op_string;
7673 new_token.str[2] = '\0';
7677 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7679 intel_parser.op_string += strlen (new_token.str);
7680 cur_token = new_token;
7683 /* Put cur_token back into the token stream and make cur_token point to
7686 intel_putback_token (void)
7688 if (cur_token.code != T_NIL)
7690 intel_parser.op_string -= strlen (cur_token.str);
7691 free (cur_token.str);
7693 cur_token = prev_token;
7695 /* Forget prev_token. */
7696 prev_token.code = T_NIL;
7697 prev_token.reg = NULL;
7698 prev_token.str = NULL;
7702 tc_x86_regname_to_dw2regnum (char *regname)
7704 unsigned int regnum;
7705 unsigned int regnames_count;
7706 static const char *const regnames_32[] =
7708 "eax", "ecx", "edx", "ebx",
7709 "esp", "ebp", "esi", "edi",
7710 "eip", "eflags", NULL,
7711 "st0", "st1", "st2", "st3",
7712 "st4", "st5", "st6", "st7",
7714 "xmm0", "xmm1", "xmm2", "xmm3",
7715 "xmm4", "xmm5", "xmm6", "xmm7",
7716 "mm0", "mm1", "mm2", "mm3",
7717 "mm4", "mm5", "mm6", "mm7",
7718 "fcw", "fsw", "mxcsr",
7719 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7722 static const char *const regnames_64[] =
7724 "rax", "rdx", "rcx", "rbx",
7725 "rsi", "rdi", "rbp", "rsp",
7726 "r8", "r9", "r10", "r11",
7727 "r12", "r13", "r14", "r15",
7729 "xmm0", "xmm1", "xmm2", "xmm3",
7730 "xmm4", "xmm5", "xmm6", "xmm7",
7731 "xmm8", "xmm9", "xmm10", "xmm11",
7732 "xmm12", "xmm13", "xmm14", "xmm15",
7733 "st0", "st1", "st2", "st3",
7734 "st4", "st5", "st6", "st7",
7735 "mm0", "mm1", "mm2", "mm3",
7736 "mm4", "mm5", "mm6", "mm7",
7738 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7739 "fs.base", "gs.base", NULL, NULL,
7741 "mxcsr", "fcw", "fsw"
7743 const char *const *regnames;
7745 if (flag_code == CODE_64BIT)
7747 regnames = regnames_64;
7748 regnames_count = ARRAY_SIZE (regnames_64);
7752 regnames = regnames_32;
7753 regnames_count = ARRAY_SIZE (regnames_32);
7756 for (regnum = 0; regnum < regnames_count; regnum++)
7757 if (regnames[regnum] != NULL
7758 && strcmp (regname, regnames[regnum]) == 0)
7765 tc_x86_frame_initial_instructions (void)
7767 static unsigned int sp_regno;
7770 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7773 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7774 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7778 i386_elf_section_type (const char *str, size_t len)
7780 if (flag_code == CODE_64BIT
7781 && len == sizeof ("unwind") - 1
7782 && strncmp (str, "unwind", 6) == 0)
7783 return SHT_X86_64_UNWIND;
7790 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7794 expr.X_op = O_secrel;
7795 expr.X_add_symbol = symbol;
7796 expr.X_add_number = 0;
7797 emit_expr (&expr, size);
7801 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7802 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7805 x86_64_section_letter (int letter, char **ptr_msg)
7807 if (flag_code == CODE_64BIT)
7810 return SHF_X86_64_LARGE;
7812 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7815 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7820 x86_64_section_word (char *str, size_t len)
7822 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7823 return SHF_X86_64_LARGE;
7829 handle_large_common (int small ATTRIBUTE_UNUSED)
7831 if (flag_code != CODE_64BIT)
7833 s_comm_internal (0, elf_common_parse);
7834 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7838 static segT lbss_section;
7839 asection *saved_com_section_ptr = elf_com_section_ptr;
7840 asection *saved_bss_section = bss_section;
7842 if (lbss_section == NULL)
7844 flagword applicable;
7846 subsegT subseg = now_subseg;
7848 /* The .lbss section is for local .largecomm symbols. */
7849 lbss_section = subseg_new (".lbss", 0);
7850 applicable = bfd_applicable_section_flags (stdoutput);
7851 bfd_set_section_flags (stdoutput, lbss_section,
7852 applicable & SEC_ALLOC);
7853 seg_info (lbss_section)->bss = 1;
7855 subseg_set (seg, subseg);
7858 elf_com_section_ptr = &_bfd_elf_large_com_section;
7859 bss_section = lbss_section;
7861 s_comm_internal (0, elf_common_parse);
7863 elf_com_section_ptr = saved_com_section_ptr;
7864 bss_section = saved_bss_section;
7867 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */