1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
461 const char line_separator_chars[] = ";";
463 /* Chars that can be used to separate mant from exp in floating point
465 const char EXP_CHARS[] = "eE";
467 /* Chars that mean this number is a floating point constant
470 const char FLT_CHARS[] = "fFdDxX";
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
501 /* The instruction we're assembling. */
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
511 /* Current operand we are working on. */
512 static int this_operand = -1;
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531 /* The ELF ABI to use. */
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
552 /* 1 for intel syntax,
554 static int intel_syntax = 0;
556 /* 1 for Intel64 ISA,
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
573 static int add_bnd_prefix = 0;
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
586 /* 1 if the assembler should generate relax relocations. */
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591 static enum check_kind
597 sse_check, operand_check = check_warning;
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
604 static int optimize = 0;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
613 static int optimize_for_space = 0;
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
658 /* Encode scalar AVX instructions with specific vector length. */
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 /* Encode EVEX WIG instructions with specific evex.w. */
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
698 #define UNCOND_JUMP 0
700 #define COND_JUMP86 2
705 #define SMALL16 (SMALL | CODE16)
707 #define BIG16 (BIG | CODE16)
711 #define INLINE __inline__
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
732 const relax_typeS md_relax_table[] =
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
771 static const arch_entry cpu_arch[] =
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1031 static const noarch_entry cpu_noarch[] =
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1067 /* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1071 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1078 && *input_line_pointer == ',')
1080 align = parse_align (needs_align - 1);
1082 if (align == (addressT) -1)
1097 bss_alloc (symbolP, size, align);
1102 pe_lcomm (int needs_align)
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1108 const pseudo_typeS md_pseudo_table[] =
1110 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1113 {"align", s_align_ptwo, 0},
1115 {"arch", set_cpu_arch, 0},
1119 {"lcomm", pe_lcomm, 1},
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1125 {"slong", signed_cons, 4},
1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
1132 {"code64", set_code_flag, CODE_64BIT},
1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
1145 {"file", dwarf2_directive_file, 0},
1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1150 {"secrel32", pe_directive_secrel, 0},
1155 /* For interface with expression (). */
1156 extern char *input_line_pointer;
1158 /* Hash table for instruction mnemonic lookup. */
1159 static struct hash_control *op_hash;
1161 /* Hash table for register lookup. */
1162 static struct hash_control *reg_hash;
1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
1167 static const unsigned char f32_1[] =
1169 static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171 static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173 static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1175 static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177 static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1179 static const unsigned char f16_3[] =
1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1181 static const unsigned char f16_4[] =
1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183 static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185 static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187 static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
1189 /* 32-bit NOPs patterns. */
1190 static const unsigned char *const f32_patt[] = {
1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1193 /* 16-bit NOPs patterns. */
1194 static const unsigned char *const f16_patt[] = {
1195 f32_1, f32_2, f16_3, f16_4
1197 /* nopl (%[re]ax) */
1198 static const unsigned char alt_3[] =
1200 /* nopl 0(%[re]ax) */
1201 static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203 /* nopl 0(%[re]ax,%[re]ax,1) */
1204 static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206 /* nopw 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopl 0L(%[re]ax) */
1210 static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212 /* nopl 0L(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215 /* nopw 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* data16 nopw %cs:0L(%eax,%eax,1) */
1222 static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* 32-bit and 64-bit NOPs patterns. */
1225 static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1227 alt_9, alt_10, alt_11
1230 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1234 i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1238 /* Place the longer NOP first. */
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1243 /* Use the smaller one if the requsted one isn't available. */
1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
1250 last = count % max_single_nop_size;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1258 nops = patt[last - 1];
1261 /* Use the smaller one plus one-byte NOP if the needed one
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1269 memcpy (where + offset, nops, last);
1274 fits_in_imm7 (offsetT num)
1276 return (num & 0x7f) == num;
1280 fits_in_imm31 (offsetT num)
1282 return (num & 0x7fffffff) == num;
1285 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1289 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1291 const unsigned char *const *patt = NULL;
1292 int max_single_nop_size;
1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
1296 switch (fragP->fr_type)
1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
1310 2. For the rest, alt_patt will be used.
1312 When -mtune= isn't used, alt_patt will be used if
1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1319 if (flag_code == CODE_16BIT)
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
1344 case PROCESSOR_CORE2:
1345 case PROCESSOR_COREI7:
1346 case PROCESSOR_L1OM:
1347 case PROCESSOR_K1OM:
1348 case PROCESSOR_GENERIC64:
1350 case PROCESSOR_ATHLON:
1352 case PROCESSOR_AMDFAM10:
1354 case PROCESSOR_ZNVER:
1358 case PROCESSOR_I386:
1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
1361 case PROCESSOR_PENTIUMPRO:
1362 case PROCESSOR_IAMCU:
1363 case PROCESSOR_GENERIC32:
1370 switch (fragP->tc_frag_data.tune)
1372 case PROCESSOR_UNKNOWN:
1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1374 PROCESSOR_UNKNOWN. */
1378 case PROCESSOR_I386:
1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
1381 case PROCESSOR_IAMCU:
1383 case PROCESSOR_ATHLON:
1385 case PROCESSOR_AMDFAM10:
1387 case PROCESSOR_ZNVER:
1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
1401 case PROCESSOR_CORE2:
1402 case PROCESSOR_COREI7:
1403 case PROCESSOR_L1OM:
1404 case PROCESSOR_K1OM:
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 case PROCESSOR_GENERIC64:
1416 if (patt == f32_patt)
1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1431 limit = max_single_nop_size;
1433 if (fragP->fr_type == rs_fill_nop)
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1446 fragP->fr_var = count;
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1454 /* Use "jmp disp8" if possible. */
1456 where[0] = jump_disp8[0];
1462 unsigned int size_of_jump;
1464 if (flag_code == CODE_16BIT)
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1472 where[0] = jump32_disp32[0];
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
1494 operand_type_all_zero (const union i386_operand_type *x)
1496 switch (ARRAY_SIZE(x->array))
1507 return !x->array[0];
1514 operand_type_set (union i386_operand_type *x, unsigned int v)
1516 switch (ARRAY_SIZE(x->array))
1534 operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
1537 switch (ARRAY_SIZE(x->array))
1540 if (x->array[2] != y->array[2])
1544 if (x->array[1] != y->array[1])
1548 return x->array[0] == y->array[0];
1556 cpu_flags_all_zero (const union i386_cpu_flags *x)
1558 switch (ARRAY_SIZE(x->array))
1573 return !x->array[0];
1580 cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1583 switch (ARRAY_SIZE(x->array))
1586 if (x->array[3] != y->array[3])
1590 if (x->array[2] != y->array[2])
1594 if (x->array[1] != y->array[1])
1598 return x->array[0] == y->array[0];
1606 cpu_flags_check_cpu64 (i386_cpu_flags f)
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1612 static INLINE i386_cpu_flags
1613 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1615 switch (ARRAY_SIZE (x.array))
1618 x.array [3] &= y.array [3];
1621 x.array [2] &= y.array [2];
1624 x.array [1] &= y.array [1];
1627 x.array [0] &= y.array [0];
1635 static INLINE i386_cpu_flags
1636 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1638 switch (ARRAY_SIZE (x.array))
1641 x.array [3] |= y.array [3];
1644 x.array [2] |= y.array [2];
1647 x.array [1] |= y.array [1];
1650 x.array [0] |= y.array [0];
1658 static INLINE i386_cpu_flags
1659 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1661 switch (ARRAY_SIZE (x.array))
1664 x.array [3] &= ~y.array [3];
1667 x.array [2] &= ~y.array [2];
1670 x.array [1] &= ~y.array [1];
1673 x.array [0] &= ~y.array [0];
1681 #define CPU_FLAGS_ARCH_MATCH 0x1
1682 #define CPU_FLAGS_64BIT_MATCH 0x2
1684 #define CPU_FLAGS_PERFECT_MATCH \
1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1687 /* Return CPU flags match bits. */
1690 cpu_flags_match (const insn_template *t)
1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1698 if (cpu_flags_all_zero (&x))
1700 /* This instruction is available on all archs. */
1701 match |= CPU_FLAGS_ARCH_MATCH;
1705 /* This instruction is available only on some archs. */
1706 i386_cpu_flags cpu = cpu_arch_flags;
1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1711 x.bitfield.cpuavx512vl = 0;
1713 cpu = cpu_flags_and (x, cpu);
1714 if (!cpu_flags_all_zero (&cpu))
1716 if (x.bitfield.cpuavx)
1718 /* We need to check a few extra flags with AVX. */
1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
1726 else if (x.bitfield.cpuavx512f)
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1736 match |= CPU_FLAGS_ARCH_MATCH;
1742 static INLINE i386_operand_type
1743 operand_type_and (i386_operand_type x, i386_operand_type y)
1745 switch (ARRAY_SIZE (x.array))
1748 x.array [2] &= y.array [2];
1751 x.array [1] &= y.array [1];
1754 x.array [0] &= y.array [0];
1762 static INLINE i386_operand_type
1763 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1765 switch (ARRAY_SIZE (x.array))
1768 x.array [2] &= ~y.array [2];
1771 x.array [1] &= ~y.array [1];
1774 x.array [0] &= ~y.array [0];
1782 static INLINE i386_operand_type
1783 operand_type_or (i386_operand_type x, i386_operand_type y)
1785 switch (ARRAY_SIZE (x.array))
1788 x.array [2] |= y.array [2];
1791 x.array [1] |= y.array [1];
1794 x.array [0] |= y.array [0];
1802 static INLINE i386_operand_type
1803 operand_type_xor (i386_operand_type x, i386_operand_type y)
1805 switch (ARRAY_SIZE (x.array))
1808 x.array [2] ^= y.array [2];
1811 x.array [1] ^= y.array [1];
1814 x.array [0] ^= y.array [0];
1822 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1825 static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
1827 static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833 static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
1835 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1836 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1837 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1846 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1857 operand_type_check (i386_operand_type t, enum operand_type c)
1862 return t.bitfield.reg;
1865 return (t.bitfield.imm8
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1894 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1895 operand J for instruction template T. */
1898 match_reg_size (const insn_template *t, unsigned int j)
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
1912 /* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1916 match_simd_size (const insn_template *t, unsigned int j)
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1926 /* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1930 match_mem_size (const insn_template *t, unsigned int j)
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
1940 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1941 down-conversion vpmov*. */
1942 || ((t->operand_types[j].bitfield.regsimd
1943 && !t->opcode_modifier.broadcast
1944 && (t->operand_types[j].bitfield.byte
1945 || t->operand_types[j].bitfield.word
1946 || t->operand_types[j].bitfield.dword
1947 || t->operand_types[j].bitfield.qword))
1948 ? (i.types[j].bitfield.xmmword
1949 || i.types[j].bitfield.ymmword
1950 || i.types[j].bitfield.zmmword)
1951 : !match_simd_size(t, j))));
1954 /* Return 1 if there is no size conflict on any operands for
1955 instruction template T. */
1958 operand_size_match (const insn_template *t)
1963 /* Don't check jump instructions. */
1964 if (t->opcode_modifier.jump
1965 || t->opcode_modifier.jumpbyte
1966 || t->opcode_modifier.jumpdword
1967 || t->opcode_modifier.jumpintersegment)
1970 /* Check memory and accumulator operand size. */
1971 for (j = 0; j < i.operands; j++)
1973 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1974 && t->operand_types[j].bitfield.anysize)
1977 if (t->operand_types[j].bitfield.reg
1978 && !match_reg_size (t, j))
1984 if (t->operand_types[j].bitfield.regsimd
1985 && !match_simd_size (t, j))
1991 if (t->operand_types[j].bitfield.acc
1992 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1998 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2007 else if (!t->opcode_modifier.d)
2010 i.error = operand_size_mismatch;
2014 /* Check reverse. */
2015 gas_assert (i.operands == 2);
2018 for (j = 0; j < 2; j++)
2020 if ((t->operand_types[j].bitfield.reg
2021 || t->operand_types[j].bitfield.acc)
2022 && !match_reg_size (t, j ? 0 : 1))
2025 if (i.types[j].bitfield.mem
2026 && !match_mem_size (t, j ? 0 : 1))
2034 operand_type_match (i386_operand_type overlap,
2035 i386_operand_type given)
2037 i386_operand_type temp = overlap;
2039 temp.bitfield.jumpabsolute = 0;
2040 temp.bitfield.unspecified = 0;
2041 temp.bitfield.byte = 0;
2042 temp.bitfield.word = 0;
2043 temp.bitfield.dword = 0;
2044 temp.bitfield.fword = 0;
2045 temp.bitfield.qword = 0;
2046 temp.bitfield.tbyte = 0;
2047 temp.bitfield.xmmword = 0;
2048 temp.bitfield.ymmword = 0;
2049 temp.bitfield.zmmword = 0;
2050 if (operand_type_all_zero (&temp))
2053 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2054 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2058 i.error = operand_type_mismatch;
2062 /* If given types g0 and g1 are registers they must be of the same type
2063 unless the expected operand type register overlap is null.
2064 Memory operand size of certain SIMD instructions is also being checked
2068 operand_type_register_match (i386_operand_type g0,
2069 i386_operand_type t0,
2070 i386_operand_type g1,
2071 i386_operand_type t1)
2073 if (!g0.bitfield.reg
2074 && !g0.bitfield.regsimd
2075 && (!operand_type_check (g0, anymem)
2076 || g0.bitfield.unspecified
2077 || !t0.bitfield.regsimd))
2080 if (!g1.bitfield.reg
2081 && !g1.bitfield.regsimd
2082 && (!operand_type_check (g1, anymem)
2083 || g1.bitfield.unspecified
2084 || !t1.bitfield.regsimd))
2087 if (g0.bitfield.byte == g1.bitfield.byte
2088 && g0.bitfield.word == g1.bitfield.word
2089 && g0.bitfield.dword == g1.bitfield.dword
2090 && g0.bitfield.qword == g1.bitfield.qword
2091 && g0.bitfield.xmmword == g1.bitfield.xmmword
2092 && g0.bitfield.ymmword == g1.bitfield.ymmword
2093 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2096 if (!(t0.bitfield.byte & t1.bitfield.byte)
2097 && !(t0.bitfield.word & t1.bitfield.word)
2098 && !(t0.bitfield.dword & t1.bitfield.dword)
2099 && !(t0.bitfield.qword & t1.bitfield.qword)
2100 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2101 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2102 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2105 i.error = register_type_mismatch;
2110 static INLINE unsigned int
2111 register_number (const reg_entry *r)
2113 unsigned int nr = r->reg_num;
2115 if (r->reg_flags & RegRex)
2118 if (r->reg_flags & RegVRex)
2124 static INLINE unsigned int
2125 mode_from_disp_size (i386_operand_type t)
2127 if (t.bitfield.disp8)
2129 else if (t.bitfield.disp16
2130 || t.bitfield.disp32
2131 || t.bitfield.disp32s)
2138 fits_in_signed_byte (addressT num)
2140 return num + 0x80 <= 0xff;
2144 fits_in_unsigned_byte (addressT num)
2150 fits_in_unsigned_word (addressT num)
2152 return num <= 0xffff;
2156 fits_in_signed_word (addressT num)
2158 return num + 0x8000 <= 0xffff;
2162 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2167 return num + 0x80000000 <= 0xffffffff;
2169 } /* fits_in_signed_long() */
2172 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2177 return num <= 0xffffffff;
2179 } /* fits_in_unsigned_long() */
2182 fits_in_disp8 (offsetT num)
2184 int shift = i.memshift;
2190 mask = (1 << shift) - 1;
2192 /* Return 0 if NUM isn't properly aligned. */
2196 /* Check if NUM will fit in 8bit after shift. */
2197 return fits_in_signed_byte (num >> shift);
2201 fits_in_imm4 (offsetT num)
2203 return (num & 0xf) == num;
2206 static i386_operand_type
2207 smallest_imm_type (offsetT num)
2209 i386_operand_type t;
2211 operand_type_set (&t, 0);
2212 t.bitfield.imm64 = 1;
2214 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2216 /* This code is disabled on the 486 because all the Imm1 forms
2217 in the opcode table are slower on the i486. They're the
2218 versions with the implicitly specified single-position
2219 displacement, which has another syntax if you really want to
2221 t.bitfield.imm1 = 1;
2222 t.bitfield.imm8 = 1;
2223 t.bitfield.imm8s = 1;
2224 t.bitfield.imm16 = 1;
2225 t.bitfield.imm32 = 1;
2226 t.bitfield.imm32s = 1;
2228 else if (fits_in_signed_byte (num))
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2236 else if (fits_in_unsigned_byte (num))
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2243 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2249 else if (fits_in_signed_long (num))
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2254 else if (fits_in_unsigned_long (num))
2255 t.bitfield.imm32 = 1;
2261 offset_in_range (offsetT val, int size)
2267 case 1: mask = ((addressT) 1 << 8) - 1; break;
2268 case 2: mask = ((addressT) 1 << 16) - 1; break;
2269 case 4: mask = ((addressT) 2 << 31) - 1; break;
2271 case 8: mask = ((addressT) 2 << 63) - 1; break;
2277 /* If BFD64, sign extend val for 32bit address mode. */
2278 if (flag_code != CODE_64BIT
2279 || i.prefix[ADDR_PREFIX])
2280 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2281 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2284 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2286 char buf1[40], buf2[40];
2288 sprint_value (buf1, val);
2289 sprint_value (buf2, val & mask);
2290 as_warn (_("%s shortened to %s"), buf1, buf2);
2305 a. PREFIX_EXIST if attempting to add a prefix where one from the
2306 same class already exists.
2307 b. PREFIX_LOCK if lock prefix is added.
2308 c. PREFIX_REP if rep/repne prefix is added.
2309 d. PREFIX_DS if ds prefix is added.
2310 e. PREFIX_OTHER if other prefix is added.
2313 static enum PREFIX_GROUP
2314 add_prefix (unsigned int prefix)
2316 enum PREFIX_GROUP ret = PREFIX_OTHER;
2319 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2320 && flag_code == CODE_64BIT)
2322 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2323 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2324 && (prefix & (REX_R | REX_X | REX_B))))
2335 case DS_PREFIX_OPCODE:
2338 case CS_PREFIX_OPCODE:
2339 case ES_PREFIX_OPCODE:
2340 case FS_PREFIX_OPCODE:
2341 case GS_PREFIX_OPCODE:
2342 case SS_PREFIX_OPCODE:
2346 case REPNE_PREFIX_OPCODE:
2347 case REPE_PREFIX_OPCODE:
2352 case LOCK_PREFIX_OPCODE:
2361 case ADDR_PREFIX_OPCODE:
2365 case DATA_PREFIX_OPCODE:
2369 if (i.prefix[q] != 0)
2377 i.prefix[q] |= prefix;
2380 as_bad (_("same type of prefix used twice"));
2386 update_code_flag (int value, int check)
2388 PRINTF_LIKE ((*as_error));
2390 flag_code = (enum flag_code) value;
2391 if (flag_code == CODE_64BIT)
2393 cpu_arch_flags.bitfield.cpu64 = 1;
2394 cpu_arch_flags.bitfield.cpuno64 = 0;
2398 cpu_arch_flags.bitfield.cpu64 = 0;
2399 cpu_arch_flags.bitfield.cpuno64 = 1;
2401 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2404 as_error = as_fatal;
2407 (*as_error) (_("64bit mode not supported on `%s'."),
2408 cpu_arch_name ? cpu_arch_name : default_arch);
2410 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2413 as_error = as_fatal;
2416 (*as_error) (_("32bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 stackop_size = '\0';
2423 set_code_flag (int value)
2425 update_code_flag (value, 0);
2429 set_16bit_gcc_code_flag (int new_code_flag)
2431 flag_code = (enum flag_code) new_code_flag;
2432 if (flag_code != CODE_16BIT)
2434 cpu_arch_flags.bitfield.cpu64 = 0;
2435 cpu_arch_flags.bitfield.cpuno64 = 1;
2436 stackop_size = LONG_MNEM_SUFFIX;
2440 set_intel_syntax (int syntax_flag)
2442 /* Find out if register prefixing is specified. */
2443 int ask_naked_reg = 0;
2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2449 int e = get_symbol_name (&string);
2451 if (strcmp (string, "prefix") == 0)
2453 else if (strcmp (string, "noprefix") == 0)
2456 as_bad (_("bad argument to syntax directive."));
2457 (void) restore_line_pointer (e);
2459 demand_empty_rest_of_line ();
2461 intel_syntax = syntax_flag;
2463 if (ask_naked_reg == 0)
2464 allow_naked_reg = (intel_syntax
2465 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2467 allow_naked_reg = (ask_naked_reg < 0);
2469 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2471 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2472 identifier_chars['$'] = intel_syntax ? '$' : 0;
2473 register_prefix = allow_naked_reg ? "" : "%";
2477 set_intel_mnemonic (int mnemonic_flag)
2479 intel_mnemonic = mnemonic_flag;
2483 set_allow_index_reg (int flag)
2485 allow_index_reg = flag;
2489 set_check (int what)
2491 enum check_kind *kind;
2496 kind = &operand_check;
2507 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2510 int e = get_symbol_name (&string);
2512 if (strcmp (string, "none") == 0)
2514 else if (strcmp (string, "warning") == 0)
2515 *kind = check_warning;
2516 else if (strcmp (string, "error") == 0)
2517 *kind = check_error;
2519 as_bad (_("bad argument to %s_check directive."), str);
2520 (void) restore_line_pointer (e);
2523 as_bad (_("missing argument for %s_check directive"), str);
2525 demand_empty_rest_of_line ();
2529 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2530 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 static const char *arch;
2535 /* Intel LIOM is only supported on ELF. */
2541 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2542 use default_arch. */
2543 arch = cpu_arch_name;
2545 arch = default_arch;
2548 /* If we are targeting Intel MCU, we must enable it. */
2549 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2550 || new_flag.bitfield.cpuiamcu)
2553 /* If we are targeting Intel L1OM, we must enable it. */
2554 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2555 || new_flag.bitfield.cpul1om)
2558 /* If we are targeting Intel K1OM, we must enable it. */
2559 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2560 || new_flag.bitfield.cpuk1om)
2563 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2568 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2572 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2575 int e = get_symbol_name (&string);
2577 i386_cpu_flags flags;
2579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2581 if (strcmp (string, cpu_arch[j].name) == 0)
2583 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2587 cpu_arch_name = cpu_arch[j].name;
2588 cpu_sub_arch_name = NULL;
2589 cpu_arch_flags = cpu_arch[j].flags;
2590 if (flag_code == CODE_64BIT)
2592 cpu_arch_flags.bitfield.cpu64 = 1;
2593 cpu_arch_flags.bitfield.cpuno64 = 0;
2597 cpu_arch_flags.bitfield.cpu64 = 0;
2598 cpu_arch_flags.bitfield.cpuno64 = 1;
2600 cpu_arch_isa = cpu_arch[j].type;
2601 cpu_arch_isa_flags = cpu_arch[j].flags;
2602 if (!cpu_arch_tune_set)
2604 cpu_arch_tune = cpu_arch_isa;
2605 cpu_arch_tune_flags = cpu_arch_isa_flags;
2610 flags = cpu_flags_or (cpu_arch_flags,
2613 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2615 if (cpu_sub_arch_name)
2617 char *name = cpu_sub_arch_name;
2618 cpu_sub_arch_name = concat (name,
2620 (const char *) NULL);
2624 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2625 cpu_arch_flags = flags;
2626 cpu_arch_isa_flags = flags;
2630 = cpu_flags_or (cpu_arch_isa_flags,
2632 (void) restore_line_pointer (e);
2633 demand_empty_rest_of_line ();
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2640 /* Disable an ISA extension. */
2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2648 if (cpu_sub_arch_name)
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2665 j = ARRAY_SIZE (cpu_arch);
2668 if (j >= ARRAY_SIZE (cpu_arch))
2669 as_bad (_("no such architecture: `%s'"), string);
2671 *input_line_pointer = e;
2674 as_bad (_("missing cpu architecture"));
2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2693 (void) restore_line_pointer (e);
2696 demand_empty_rest_of_line ();
2699 enum bfd_architecture
2702 if (cpu_arch_isa == PROCESSOR_L1OM)
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2724 return bfd_arch_i386;
2730 if (!strncmp (default_arch, "x86_64", 6))
2732 if (cpu_arch_isa == PROCESSOR_L1OM)
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2746 else if (default_arch[6] == '\0')
2747 return bfd_mach_x86_64;
2749 return bfd_mach_x64_32;
2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2761 return bfd_mach_i386_i386;
2764 as_fatal (_("unknown architecture"));
2770 const char *hash_err;
2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2775 /* Initialize op_hash hash table. */
2776 op_hash = hash_new ();
2779 const insn_template *optab;
2780 templates *core_optab;
2782 /* Setup for loop. */
2784 core_optab = XNEW (templates);
2785 core_optab->start = optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2793 /* different name --> ship out current template list;
2794 add to hash table; & begin anew. */
2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2798 (void *) core_optab);
2801 as_fatal (_("can't hash %s: %s"),
2805 if (optab->name == NULL)
2807 core_optab = XNEW (templates);
2808 core_optab->start = optab;
2813 /* Initialize reg_hash hash table. */
2814 reg_hash = hash_new ();
2816 const reg_entry *regtab;
2817 unsigned int regtab_size = i386_regtab_size;
2819 for (regtab = i386_regtab; regtab_size--; regtab++)
2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2823 as_fatal (_("can't hash %s: %s"),
2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2834 for (c = 0; c < 256; c++)
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2843 else if (ISLOWER (c))
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2849 else if (ISUPPER (c))
2851 mnemonic_chars[c] = TOLOWER (c);
2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2855 else if (c == '{' || c == '}')
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2861 if (ISALPHA (c) || ISDIGIT (c))
2862 identifier_chars[c] = c;
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2871 identifier_chars['@'] = '@';
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
2877 digit_chars['-'] = '-';
2878 mnemonic_chars['_'] = '_';
2879 mnemonic_chars['-'] = '-';
2880 mnemonic_chars['.'] = '.';
2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2888 if (flag_code == CODE_64BIT)
2890 #if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2894 x86_dwarf2_return_column = 16;
2896 x86_cie_data_alignment = -8;
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2906 i386_print_statistics (FILE *file)
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2914 /* Debugging routines for md_assemble. */
2915 static void pte (insn_template *);
2916 static void pt (i386_operand_type);
2917 static void pe (expressionS *);
2918 static void ps (symbolS *);
2921 pi (char *line, i386_insn *x)
2925 fprintf (stdout, "%s: template ", line);
2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2932 x->rm.mode, x->rm.reg, x->rm.regmem);
2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
2940 for (j = 0; j < x->operands; j++)
2942 fprintf (stdout, " #%d: ", j + 1);
2944 fprintf (stdout, "\n");
2945 if (x->types[j].bitfield.reg
2946 || x->types[j].bitfield.regmmx
2947 || x->types[j].bitfield.regsimd
2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
2962 pte (insn_template *t)
2965 fprintf (stdout, " %d operands ", t->operands);
2966 fprintf (stdout, "opcode %x ", t->base_opcode);
2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
2969 if (t->opcode_modifier.d)
2970 fprintf (stdout, "D");
2971 if (t->opcode_modifier.w)
2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
2974 for (j = 0; j < t->operands; j++)
2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
2978 fprintf (stdout, "\n");
2985 fprintf (stdout, " operation %d\n", e->X_op);
2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
2988 if (e->X_add_symbol)
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
3005 fprintf (stdout, "%s type %s%s",
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3011 static struct type_name
3013 i386_operand_type mask;
3016 const type_names[] =
3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
3048 { OPERAND_TYPE_REGYMM, "rYMM" },
3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
3051 { OPERAND_TYPE_ESSEG, "es" },
3055 pt (i386_operand_type t)
3058 i386_operand_type a;
3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3062 a = operand_type_and (t, type_names[j].mask);
3063 if (!operand_type_all_zero (&a))
3064 fprintf (stdout, "%s, ", type_names[j].name);
3069 #endif /* DEBUG386 */
3071 static bfd_reloc_code_real_type
3072 reloc (unsigned int size,
3075 bfd_reloc_code_real_type other)
3077 if (other != NO_RELOC)
3079 reloc_howto_type *rel;
3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3110 if (other == BFD_RELOC_SIZE32)
3113 other = BFD_RELOC_SIZE64;
3116 as_bad (_("there are no pc-relative size relocations"));
3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3128 as_bad (_("unknown relocation (%u)"), other);
3129 else if (size != bfd_get_reloc_size (rel))
3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3131 bfd_get_reloc_size (rel),
3133 else if (pcrel && !rel->pc_relative)
3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3137 || (rel->complain_on_overflow == complain_overflow_unsigned
3139 as_bad (_("relocated field and relocation type differ in signedness"));
3148 as_bad (_("there are no unsigned pc-relative relocations"));
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
3153 case 4: return BFD_RELOC_32_PCREL;
3154 case 8: return BFD_RELOC_64_PCREL;
3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3163 case 4: return BFD_RELOC_X86_64_32S;
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
3180 /* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3186 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3246 intel_float_operand (const char *mnemonic)
3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3255 switch (mnemonic[1])
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3261 return 2 /* integer op */;
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3279 switch (mnemonic[3])
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3298 /* Build the VEX prefix. */
3301 build_vex_prefix (const insn_template *t)
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3315 register_specifier = 0xf;
3317 /* Use 2-byte VEX prefix by swapping destination and source
3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
3321 && i.operands == i.reg_operands
3322 && i.tm.opcode_modifier.vexopcode == VEX0F
3323 && i.tm.opcode_modifier.load
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3337 gas_assert (i.rm.mode == 3);
3341 i.rm.regmem = i.rm.reg;
3344 /* Use the next insn. */
3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
3350 else if (i.tm.opcode_modifier.vex == VEX256)
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3372 case DATA_PREFIX_OPCODE:
3375 case REPE_PREFIX_OPCODE:
3378 case REPNE_PREFIX_OPCODE:
3385 /* Use 2-byte VEX prefix if possible. */
3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
3388 && i.tm.opcode_modifier.vexw != VEXW1
3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3391 /* 2-byte VEX prefix. */
3395 i.vex.bytes[0] = 0xc5;
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3406 /* 3-byte VEX prefix. */
3411 switch (i.tm.opcode_modifier.vexopcode)
3415 i.vex.bytes[0] = 0xc4;
3419 i.vex.bytes[0] = 0xc4;
3423 i.vex.bytes[0] = 0xc4;
3427 i.vex.bytes[0] = 0x8f;
3431 i.vex.bytes[0] = 0x8f;
3435 i.vex.bytes[0] = 0x8f;
3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3457 static INLINE bfd_boolean
3458 is_evex_encoding (const insn_template *t)
3460 return t->opcode_modifier.evex
3461 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3462 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3465 /* Build the EVEX prefix. */
3468 build_evex_prefix (void)
3470 unsigned int register_specifier;
3471 unsigned int implied_prefix;
3473 rex_byte vrex_used = 0;
3475 /* Check register specifier. */
3476 if (i.vex.register_specifier)
3478 gas_assert ((i.vrex & REX_X) == 0);
3480 register_specifier = i.vex.register_specifier->reg_num;
3481 if ((i.vex.register_specifier->reg_flags & RegRex))
3482 register_specifier += 8;
3483 /* The upper 16 registers are encoded in the fourth byte of the
3485 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3486 i.vex.bytes[3] = 0x8;
3487 register_specifier = ~register_specifier & 0xf;
3491 register_specifier = 0xf;
3493 /* Encode upper 16 vector index register in the fourth byte of
3495 if (!(i.vrex & REX_X))
3496 i.vex.bytes[3] = 0x8;
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3506 case DATA_PREFIX_OPCODE:
3509 case REPE_PREFIX_OPCODE:
3512 case REPNE_PREFIX_OPCODE:
3519 /* 4 byte EVEX prefix. */
3521 i.vex.bytes[0] = 0x62;
3524 switch (i.tm.opcode_modifier.vexopcode)
3540 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3542 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3544 /* The fifth bit of the second EVEX byte is 1's compliment of the
3545 REX_R bit in VREX. */
3546 if (!(i.vrex & REX_R))
3547 i.vex.bytes[1] |= 0x10;
3551 if ((i.reg_operands + i.imm_operands) == i.operands)
3553 /* When all operands are registers, the REX_X bit in REX is not
3554 used. We reuse it to encode the upper 16 registers, which is
3555 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3556 as 1's compliment. */
3557 if ((i.vrex & REX_B))
3560 i.vex.bytes[1] &= ~0x40;
3564 /* EVEX instructions shouldn't need the REX prefix. */
3565 i.vrex &= ~vrex_used;
3566 gas_assert (i.vrex == 0);
3568 /* Check the REX.W bit. */
3569 w = (i.rex & REX_W) ? 1 : 0;
3570 if (i.tm.opcode_modifier.vexw)
3572 if (i.tm.opcode_modifier.vexw == VEXW1)
3575 /* If w is not set it means we are dealing with WIG instruction. */
3578 if (evexwig == evexw1)
3582 /* Encode the U bit. */
3583 implied_prefix |= 0x4;
3585 /* The third byte of the EVEX prefix. */
3586 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3588 /* The fourth byte of the EVEX prefix. */
3589 /* The zeroing-masking bit. */
3590 if (i.mask && i.mask->zeroing)
3591 i.vex.bytes[3] |= 0x80;
3593 /* Don't always set the broadcast bit if there is no RC. */
3596 /* Encode the vector length. */
3597 unsigned int vec_length;
3599 if (!i.tm.opcode_modifier.evex
3600 || i.tm.opcode_modifier.evex == EVEXDYN)
3605 for (op = 0; op < i.tm.operands; ++op)
3606 if (i.tm.operand_types[op].bitfield.xmmword
3607 + i.tm.operand_types[op].bitfield.ymmword
3608 + i.tm.operand_types[op].bitfield.zmmword > 1)
3610 if (i.types[op].bitfield.zmmword)
3611 i.tm.opcode_modifier.evex = EVEX512;
3612 else if (i.types[op].bitfield.ymmword)
3613 i.tm.opcode_modifier.evex = EVEX256;
3614 else if (i.types[op].bitfield.xmmword)
3615 i.tm.opcode_modifier.evex = EVEX128;
3622 switch (i.tm.opcode_modifier.evex)
3624 case EVEXLIG: /* LL' is ignored */
3625 vec_length = evexlig << 5;
3628 vec_length = 0 << 5;
3631 vec_length = 1 << 5;
3634 vec_length = 2 << 5;
3640 i.vex.bytes[3] |= vec_length;
3641 /* Encode the broadcast bit. */
3643 i.vex.bytes[3] |= 0x10;
3647 if (i.rounding->type != saeonly)
3648 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3650 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3653 if (i.mask && i.mask->mask)
3654 i.vex.bytes[3] |= i.mask->mask->reg_num;
3658 process_immext (void)
3662 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3665 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3666 with an opcode suffix which is coded in the same place as an
3667 8-bit immediate field would be.
3668 Here we check those operands and remove them afterwards. */
3671 for (x = 0; x < i.operands; x++)
3672 if (register_number (i.op[x].regs) != x)
3673 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3674 register_prefix, i.op[x].regs->reg_name, x + 1,
3680 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3682 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3683 suffix which is coded in the same place as an 8-bit immediate
3685 Here we check those operands and remove them afterwards. */
3688 if (i.operands != 3)
3691 for (x = 0; x < 2; x++)
3692 if (register_number (i.op[x].regs) != x)
3693 goto bad_register_operand;
3695 /* Check for third operand for mwaitx/monitorx insn. */
3696 if (register_number (i.op[x].regs)
3697 != (x + (i.tm.extension_opcode == 0xfb)))
3699 bad_register_operand:
3700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3701 register_prefix, i.op[x].regs->reg_name, x+1,
3708 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3709 which is coded in the same place as an 8-bit immediate field
3710 would be. Here we fake an 8-bit immediate operand from the
3711 opcode suffix stored in tm.extension_opcode.
3713 AVX instructions also use this encoding, for some of
3714 3 argument instructions. */
3716 gas_assert (i.imm_operands <= 1
3718 || ((i.tm.opcode_modifier.vex
3719 || i.tm.opcode_modifier.vexopcode
3720 || is_evex_encoding (&i.tm))
3721 && i.operands <= 4)));
3723 exp = &im_expressions[i.imm_operands++];
3724 i.op[i.operands].imms = exp;
3725 i.types[i.operands] = imm8;
3727 exp->X_op = O_constant;
3728 exp->X_add_number = i.tm.extension_opcode;
3729 i.tm.extension_opcode = None;
3736 switch (i.tm.opcode_modifier.hleprefixok)
3741 as_bad (_("invalid instruction `%s' after `%s'"),
3742 i.tm.name, i.hle_prefix);
3745 if (i.prefix[LOCK_PREFIX])
3747 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3751 case HLEPrefixRelease:
3752 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3754 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3758 if (i.mem_operands == 0
3759 || !operand_type_check (i.types[i.operands - 1], anymem))
3761 as_bad (_("memory destination needed for instruction `%s'"
3762 " after `xrelease'"), i.tm.name);
3769 /* Try the shortest encoding by shortening operand size. */
3772 optimize_encoding (void)
3776 if (optimize_for_space
3777 && i.reg_operands == 1
3778 && i.imm_operands == 1
3779 && !i.types[1].bitfield.byte
3780 && i.op[0].imms->X_op == O_constant
3781 && fits_in_imm7 (i.op[0].imms->X_add_number)
3782 && ((i.tm.base_opcode == 0xa8
3783 && i.tm.extension_opcode == None)
3784 || (i.tm.base_opcode == 0xf6
3785 && i.tm.extension_opcode == 0x0)))
3788 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3790 unsigned int base_regnum = i.op[1].regs->reg_num;
3791 if (flag_code == CODE_64BIT || base_regnum < 4)
3793 i.types[1].bitfield.byte = 1;
3794 /* Ignore the suffix. */
3796 if (base_regnum >= 4
3797 && !(i.op[1].regs->reg_flags & RegRex))
3799 /* Handle SP, BP, SI and DI registers. */
3800 if (i.types[1].bitfield.word)
3802 else if (i.types[1].bitfield.dword)
3810 else if (flag_code == CODE_64BIT
3811 && ((i.types[1].bitfield.qword
3812 && i.reg_operands == 1
3813 && i.imm_operands == 1
3814 && i.op[0].imms->X_op == O_constant
3815 && ((i.tm.base_opcode == 0xb0
3816 && i.tm.extension_opcode == None
3817 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3818 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3819 && (((i.tm.base_opcode == 0x24
3820 || i.tm.base_opcode == 0xa8)
3821 && i.tm.extension_opcode == None)
3822 || (i.tm.base_opcode == 0x80
3823 && i.tm.extension_opcode == 0x4)
3824 || ((i.tm.base_opcode == 0xf6
3825 || i.tm.base_opcode == 0xc6)
3826 && i.tm.extension_opcode == 0x0)))))
3827 || (i.types[0].bitfield.qword
3828 && ((i.reg_operands == 2
3829 && i.op[0].regs == i.op[1].regs
3830 && ((i.tm.base_opcode == 0x30
3831 || i.tm.base_opcode == 0x28)
3832 && i.tm.extension_opcode == None))
3833 || (i.reg_operands == 1
3835 && i.tm.base_opcode == 0x30
3836 && i.tm.extension_opcode == None)))))
3839 andq $imm31, %r64 -> andl $imm31, %r32
3840 testq $imm31, %r64 -> testl $imm31, %r32
3841 xorq %r64, %r64 -> xorl %r32, %r32
3842 subq %r64, %r64 -> subl %r32, %r32
3843 movq $imm31, %r64 -> movl $imm31, %r32
3844 movq $imm32, %r64 -> movl $imm32, %r32
3846 i.tm.opcode_modifier.norex64 = 1;
3847 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3850 movq $imm31, %r64 -> movl $imm31, %r32
3851 movq $imm32, %r64 -> movl $imm32, %r32
3853 i.tm.operand_types[0].bitfield.imm32 = 1;
3854 i.tm.operand_types[0].bitfield.imm32s = 0;
3855 i.tm.operand_types[0].bitfield.imm64 = 0;
3856 i.types[0].bitfield.imm32 = 1;
3857 i.types[0].bitfield.imm32s = 0;
3858 i.types[0].bitfield.imm64 = 0;
3859 i.types[1].bitfield.dword = 1;
3860 i.types[1].bitfield.qword = 0;
3861 if (i.tm.base_opcode == 0xc6)
3864 movq $imm31, %r64 -> movl $imm31, %r32
3866 i.tm.base_opcode = 0xb0;
3867 i.tm.extension_opcode = None;
3868 i.tm.opcode_modifier.shortform = 1;
3869 i.tm.opcode_modifier.modrm = 0;
3873 else if (optimize > 1
3874 && i.reg_operands == 3
3875 && i.op[0].regs == i.op[1].regs
3876 && !i.types[2].bitfield.xmmword
3877 && (i.tm.opcode_modifier.vex
3880 && is_evex_encoding (&i.tm)
3881 && (i.vec_encoding != vex_encoding_evex
3882 || i.tm.cpu_flags.bitfield.cpuavx512vl
3883 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3884 && ((i.tm.base_opcode == 0x55
3885 || i.tm.base_opcode == 0x6655
3886 || i.tm.base_opcode == 0x66df
3887 || i.tm.base_opcode == 0x57
3888 || i.tm.base_opcode == 0x6657
3889 || i.tm.base_opcode == 0x66ef
3890 || i.tm.base_opcode == 0x66f8
3891 || i.tm.base_opcode == 0x66f9
3892 || i.tm.base_opcode == 0x66fa
3893 || i.tm.base_opcode == 0x66fb)
3894 && i.tm.extension_opcode == None))
3897 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3899 EVEX VOP %zmmM, %zmmM, %zmmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 EVEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandn and vpxor:
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandnd and vpandnq:
3911 EVEX VOP %zmmM, %zmmM, %zmmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 EVEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 VOP, one of vpxord and vpxorq:
3918 EVEX VOP %zmmM, %zmmM, %zmmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 EVEX VOP %ymmM, %ymmM, %ymmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 if (is_evex_encoding (&i.tm))
3927 if (i.vec_encoding == vex_encoding_evex)
3928 i.tm.opcode_modifier.evex = EVEX128;
3931 i.tm.opcode_modifier.vex = VEX128;
3932 i.tm.opcode_modifier.vexw = VEXW0;
3933 i.tm.opcode_modifier.evex = 0;
3937 i.tm.opcode_modifier.vex = VEX128;
3939 if (i.tm.opcode_modifier.vex)
3940 for (j = 0; j < 3; j++)
3942 i.types[j].bitfield.xmmword = 1;
3943 i.types[j].bitfield.ymmword = 0;
3948 /* This is the guts of the machine-dependent assembler. LINE points to a
3949 machine dependent instruction. This function is supposed to emit
3950 the frags/bytes it assembles to. */
3953 md_assemble (char *line)
3956 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3957 const insn_template *t;
3959 /* Initialize globals. */
3960 memset (&i, '\0', sizeof (i));
3961 for (j = 0; j < MAX_OPERANDS; j++)
3962 i.reloc[j] = NO_RELOC;
3963 memset (disp_expressions, '\0', sizeof (disp_expressions));
3964 memset (im_expressions, '\0', sizeof (im_expressions));
3965 save_stack_p = save_stack;
3967 /* First parse an instruction mnemonic & call i386_operand for the operands.
3968 We assume that the scrubber has arranged it so that line[0] is the valid
3969 start of a (possibly prefixed) mnemonic. */
3971 line = parse_insn (line, mnemonic);
3974 mnem_suffix = i.suffix;
3976 line = parse_operands (line, mnemonic);
3978 xfree (i.memop1_string);
3979 i.memop1_string = NULL;
3983 /* Now we've parsed the mnemonic into a set of templates, and have the
3984 operands at hand. */
3986 /* All intel opcodes have reversed operands except for "bound" and
3987 "enter". We also don't reverse intersegment "jmp" and "call"
3988 instructions with 2 immediate operands so that the immediate segment
3989 precedes the offset, as it does when in AT&T mode. */
3992 && (strcmp (mnemonic, "bound") != 0)
3993 && (strcmp (mnemonic, "invlpga") != 0)
3994 && !(operand_type_check (i.types[0], imm)
3995 && operand_type_check (i.types[1], imm)))
3998 /* The order of the immediates should be reversed
3999 for 2 immediates extrq and insertq instructions */
4000 if (i.imm_operands == 2
4001 && (strcmp (mnemonic, "extrq") == 0
4002 || strcmp (mnemonic, "insertq") == 0))
4003 swap_2_operands (0, 1);
4008 /* Don't optimize displacement for movabs since it only takes 64bit
4011 && i.disp_encoding != disp_encoding_32bit
4012 && (flag_code != CODE_64BIT
4013 || strcmp (mnemonic, "movabs") != 0))
4016 /* Next, we find a template that matches the given insn,
4017 making sure the overlap of the given operands types is consistent
4018 with the template operand types. */
4020 if (!(t = match_template (mnem_suffix)))
4023 if (sse_check != check_none
4024 && !i.tm.opcode_modifier.noavx
4025 && !i.tm.cpu_flags.bitfield.cpuavx
4026 && (i.tm.cpu_flags.bitfield.cpusse
4027 || i.tm.cpu_flags.bitfield.cpusse2
4028 || i.tm.cpu_flags.bitfield.cpusse3
4029 || i.tm.cpu_flags.bitfield.cpussse3
4030 || i.tm.cpu_flags.bitfield.cpusse4_1
4031 || i.tm.cpu_flags.bitfield.cpusse4_2
4032 || i.tm.cpu_flags.bitfield.cpupclmul
4033 || i.tm.cpu_flags.bitfield.cpuaes
4034 || i.tm.cpu_flags.bitfield.cpugfni))
4036 (sse_check == check_warning
4038 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4041 /* Zap movzx and movsx suffix. The suffix has been set from
4042 "word ptr" or "byte ptr" on the source operand in Intel syntax
4043 or extracted from mnemonic in AT&T syntax. But we'll use
4044 the destination register to choose the suffix for encoding. */
4045 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4047 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4048 there is no suffix, the default will be byte extension. */
4049 if (i.reg_operands != 2
4052 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4057 if (i.tm.opcode_modifier.fwait)
4058 if (!add_prefix (FWAIT_OPCODE))
4061 /* Check if REP prefix is OK. */
4062 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4064 as_bad (_("invalid instruction `%s' after `%s'"),
4065 i.tm.name, i.rep_prefix);
4069 /* Check for lock without a lockable instruction. Destination operand
4070 must be memory unless it is xchg (0x86). */
4071 if (i.prefix[LOCK_PREFIX]
4072 && (!i.tm.opcode_modifier.islockable
4073 || i.mem_operands == 0
4074 || (i.tm.base_opcode != 0x86
4075 && !operand_type_check (i.types[i.operands - 1], anymem))))
4077 as_bad (_("expecting lockable instruction after `lock'"));
4081 /* Check if HLE prefix is OK. */
4082 if (i.hle_prefix && !check_hle ())
4085 /* Check BND prefix. */
4086 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4087 as_bad (_("expecting valid branch instruction after `bnd'"));
4089 /* Check NOTRACK prefix. */
4090 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4091 as_bad (_("expecting indirect branch instruction after `notrack'"));
4093 if (i.tm.cpu_flags.bitfield.cpumpx)
4095 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4096 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4097 else if (flag_code != CODE_16BIT
4098 ? i.prefix[ADDR_PREFIX]
4099 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4100 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4103 /* Insert BND prefix. */
4105 && i.tm.opcode_modifier.bndprefixok
4106 && !i.prefix[BND_PREFIX])
4107 add_prefix (BND_PREFIX_OPCODE);
4109 /* Check string instruction segment overrides. */
4110 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4112 if (!check_string ())
4114 i.disp_operands = 0;
4117 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4118 optimize_encoding ();
4120 if (!process_suffix ())
4123 /* Update operand types. */
4124 for (j = 0; j < i.operands; j++)
4125 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4127 /* Make still unresolved immediate matches conform to size of immediate
4128 given in i.suffix. */
4129 if (!finalize_imm ())
4132 if (i.types[0].bitfield.imm1)
4133 i.imm_operands = 0; /* kludge for shift insns. */
4135 /* We only need to check those implicit registers for instructions
4136 with 3 operands or less. */
4137 if (i.operands <= 3)
4138 for (j = 0; j < i.operands; j++)
4139 if (i.types[j].bitfield.inoutportreg
4140 || i.types[j].bitfield.shiftcount
4141 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4144 /* ImmExt should be processed after SSE2AVX. */
4145 if (!i.tm.opcode_modifier.sse2avx
4146 && i.tm.opcode_modifier.immext)
4149 /* For insns with operands there are more diddles to do to the opcode. */
4152 if (!process_operands ())
4155 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4157 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4158 as_warn (_("translating to `%sp'"), i.tm.name);
4161 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4162 || is_evex_encoding (&i.tm))
4164 if (flag_code == CODE_16BIT)
4166 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4171 if (i.tm.opcode_modifier.vex)
4172 build_vex_prefix (t);
4174 build_evex_prefix ();
4177 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4178 instructions may define INT_OPCODE as well, so avoid this corner
4179 case for those instructions that use MODRM. */
4180 if (i.tm.base_opcode == INT_OPCODE
4181 && !i.tm.opcode_modifier.modrm
4182 && i.op[0].imms->X_add_number == 3)
4184 i.tm.base_opcode = INT3_OPCODE;
4188 if ((i.tm.opcode_modifier.jump
4189 || i.tm.opcode_modifier.jumpbyte
4190 || i.tm.opcode_modifier.jumpdword)
4191 && i.op[0].disps->X_op == O_constant)
4193 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4194 the absolute address given by the constant. Since ix86 jumps and
4195 calls are pc relative, we need to generate a reloc. */
4196 i.op[0].disps->X_add_symbol = &abs_symbol;
4197 i.op[0].disps->X_op = O_symbol;
4200 if (i.tm.opcode_modifier.rex64)
4203 /* For 8 bit registers we need an empty rex prefix. Also if the
4204 instruction already has a prefix, we need to convert old
4205 registers to new ones. */
4207 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4208 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4210 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4211 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4217 i.rex |= REX_OPCODE;
4218 for (x = 0; x < 2; x++)
4220 /* Look for 8 bit operand that uses old registers. */
4221 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4222 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4224 /* In case it is "hi" register, give up. */
4225 if (i.op[x].regs->reg_num > 3)
4226 as_bad (_("can't encode register '%s%s' in an "
4227 "instruction requiring REX prefix."),
4228 register_prefix, i.op[x].regs->reg_name);
4230 /* Otherwise it is equivalent to the extended register.
4231 Since the encoding doesn't change this is merely
4232 cosmetic cleanup for debug output. */
4234 i.op[x].regs = i.op[x].regs + 8;
4239 if (i.rex == 0 && i.rex_encoding)
4241 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4242 that uses legacy register. If it is "hi" register, don't add
4243 the REX_OPCODE byte. */
4245 for (x = 0; x < 2; x++)
4246 if (i.types[x].bitfield.reg
4247 && i.types[x].bitfield.byte
4248 && (i.op[x].regs->reg_flags & RegRex64) == 0
4249 && i.op[x].regs->reg_num > 3)
4251 i.rex_encoding = FALSE;
4260 add_prefix (REX_OPCODE | i.rex);
4262 /* We are ready to output the insn. */
4267 parse_insn (char *line, char *mnemonic)
4270 char *token_start = l;
4273 const insn_template *t;
4279 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4284 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4286 as_bad (_("no such instruction: `%s'"), token_start);
4291 if (!is_space_char (*l)
4292 && *l != END_OF_INSN
4294 || (*l != PREFIX_SEPARATOR
4297 as_bad (_("invalid character %s in mnemonic"),
4298 output_invalid (*l));
4301 if (token_start == l)
4303 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4304 as_bad (_("expecting prefix; got nothing"));
4306 as_bad (_("expecting mnemonic; got nothing"));
4310 /* Look up instruction (or prefix) via hash table. */
4311 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4313 if (*l != END_OF_INSN
4314 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4315 && current_templates
4316 && current_templates->start->opcode_modifier.isprefix)
4318 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4320 as_bad ((flag_code != CODE_64BIT
4321 ? _("`%s' is only supported in 64-bit mode")
4322 : _("`%s' is not supported in 64-bit mode")),
4323 current_templates->start->name);
4326 /* If we are in 16-bit mode, do not allow addr16 or data16.
4327 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4328 if ((current_templates->start->opcode_modifier.size16
4329 || current_templates->start->opcode_modifier.size32)
4330 && flag_code != CODE_64BIT
4331 && (current_templates->start->opcode_modifier.size32
4332 ^ (flag_code == CODE_16BIT)))
4334 as_bad (_("redundant %s prefix"),
4335 current_templates->start->name);
4338 if (current_templates->start->opcode_length == 0)
4340 /* Handle pseudo prefixes. */
4341 switch (current_templates->start->base_opcode)
4345 i.disp_encoding = disp_encoding_8bit;
4349 i.disp_encoding = disp_encoding_32bit;
4353 i.dir_encoding = dir_encoding_load;
4357 i.dir_encoding = dir_encoding_store;
4361 i.vec_encoding = vex_encoding_vex2;
4365 i.vec_encoding = vex_encoding_vex3;
4369 i.vec_encoding = vex_encoding_evex;
4373 i.rex_encoding = TRUE;
4377 i.no_optimize = TRUE;
4385 /* Add prefix, checking for repeated prefixes. */
4386 switch (add_prefix (current_templates->start->base_opcode))
4391 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4392 i.notrack_prefix = current_templates->start->name;
4395 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4396 i.hle_prefix = current_templates->start->name;
4397 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4398 i.bnd_prefix = current_templates->start->name;
4400 i.rep_prefix = current_templates->start->name;
4406 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4413 if (!current_templates)
4415 /* Check if we should swap operand or force 32bit displacement in
4417 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4418 i.dir_encoding = dir_encoding_store;
4419 else if (mnem_p - 3 == dot_p
4422 i.disp_encoding = disp_encoding_8bit;
4423 else if (mnem_p - 4 == dot_p
4427 i.disp_encoding = disp_encoding_32bit;
4432 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4435 if (!current_templates)
4438 /* See if we can get a match by trimming off a suffix. */
4441 case WORD_MNEM_SUFFIX:
4442 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4443 i.suffix = SHORT_MNEM_SUFFIX;
4446 case BYTE_MNEM_SUFFIX:
4447 case QWORD_MNEM_SUFFIX:
4448 i.suffix = mnem_p[-1];
4450 current_templates = (const templates *) hash_find (op_hash,
4453 case SHORT_MNEM_SUFFIX:
4454 case LONG_MNEM_SUFFIX:
4457 i.suffix = mnem_p[-1];
4459 current_templates = (const templates *) hash_find (op_hash,
4468 if (intel_float_operand (mnemonic) == 1)
4469 i.suffix = SHORT_MNEM_SUFFIX;
4471 i.suffix = LONG_MNEM_SUFFIX;
4473 current_templates = (const templates *) hash_find (op_hash,
4478 if (!current_templates)
4480 as_bad (_("no such instruction: `%s'"), token_start);
4485 if (current_templates->start->opcode_modifier.jump
4486 || current_templates->start->opcode_modifier.jumpbyte)
4488 /* Check for a branch hint. We allow ",pt" and ",pn" for
4489 predict taken and predict not taken respectively.
4490 I'm not sure that branch hints actually do anything on loop
4491 and jcxz insns (JumpByte) for current Pentium4 chips. They
4492 may work in the future and it doesn't hurt to accept them
4494 if (l[0] == ',' && l[1] == 'p')
4498 if (!add_prefix (DS_PREFIX_OPCODE))
4502 else if (l[2] == 'n')
4504 if (!add_prefix (CS_PREFIX_OPCODE))
4510 /* Any other comma loses. */
4513 as_bad (_("invalid character %s in mnemonic"),
4514 output_invalid (*l));
4518 /* Check if instruction is supported on specified architecture. */
4520 for (t = current_templates->start; t < current_templates->end; ++t)
4522 supported |= cpu_flags_match (t);
4523 if (supported == CPU_FLAGS_PERFECT_MATCH)
4525 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4526 as_warn (_("use .code16 to ensure correct addressing mode"));
4532 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4533 as_bad (flag_code == CODE_64BIT
4534 ? _("`%s' is not supported in 64-bit mode")
4535 : _("`%s' is only supported in 64-bit mode"),
4536 current_templates->start->name);
4538 as_bad (_("`%s' is not supported on `%s%s'"),
4539 current_templates->start->name,
4540 cpu_arch_name ? cpu_arch_name : default_arch,
4541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4547 parse_operands (char *l, const char *mnemonic)
4551 /* 1 if operand is pending after ','. */
4552 unsigned int expecting_operand = 0;
4554 /* Non-zero if operand parens not balanced. */
4555 unsigned int paren_not_balanced;
4557 while (*l != END_OF_INSN)
4559 /* Skip optional white space before operand. */
4560 if (is_space_char (*l))
4562 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4564 as_bad (_("invalid character %s before operand %d"),
4565 output_invalid (*l),
4569 token_start = l; /* After white space. */
4570 paren_not_balanced = 0;
4571 while (paren_not_balanced || *l != ',')
4573 if (*l == END_OF_INSN)
4575 if (paren_not_balanced)
4578 as_bad (_("unbalanced parenthesis in operand %d."),
4581 as_bad (_("unbalanced brackets in operand %d."),
4586 break; /* we are done */
4588 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4590 as_bad (_("invalid character %s in operand %d"),
4591 output_invalid (*l),
4598 ++paren_not_balanced;
4600 --paren_not_balanced;
4605 ++paren_not_balanced;
4607 --paren_not_balanced;
4611 if (l != token_start)
4612 { /* Yes, we've read in another operand. */
4613 unsigned int operand_ok;
4614 this_operand = i.operands++;
4615 if (i.operands > MAX_OPERANDS)
4617 as_bad (_("spurious operands; (%d operands/instruction max)"),
4621 i.types[this_operand].bitfield.unspecified = 1;
4622 /* Now parse operand adding info to 'i' as we go along. */
4623 END_STRING_AND_SAVE (l);
4627 i386_intel_operand (token_start,
4628 intel_float_operand (mnemonic));
4630 operand_ok = i386_att_operand (token_start);
4632 RESTORE_END_STRING (l);
4638 if (expecting_operand)
4640 expecting_operand_after_comma:
4641 as_bad (_("expecting operand after ','; got nothing"));
4646 as_bad (_("expecting operand before ','; got nothing"));
4651 /* Now *l must be either ',' or END_OF_INSN. */
4654 if (*++l == END_OF_INSN)
4656 /* Just skip it, if it's \n complain. */
4657 goto expecting_operand_after_comma;
4659 expecting_operand = 1;
4666 swap_2_operands (int xchg1, int xchg2)
4668 union i386_op temp_op;
4669 i386_operand_type temp_type;
4670 enum bfd_reloc_code_real temp_reloc;
4672 temp_type = i.types[xchg2];
4673 i.types[xchg2] = i.types[xchg1];
4674 i.types[xchg1] = temp_type;
4675 temp_op = i.op[xchg2];
4676 i.op[xchg2] = i.op[xchg1];
4677 i.op[xchg1] = temp_op;
4678 temp_reloc = i.reloc[xchg2];
4679 i.reloc[xchg2] = i.reloc[xchg1];
4680 i.reloc[xchg1] = temp_reloc;
4684 if (i.mask->operand == xchg1)
4685 i.mask->operand = xchg2;
4686 else if (i.mask->operand == xchg2)
4687 i.mask->operand = xchg1;
4691 if (i.broadcast->operand == xchg1)
4692 i.broadcast->operand = xchg2;
4693 else if (i.broadcast->operand == xchg2)
4694 i.broadcast->operand = xchg1;
4698 if (i.rounding->operand == xchg1)
4699 i.rounding->operand = xchg2;
4700 else if (i.rounding->operand == xchg2)
4701 i.rounding->operand = xchg1;
4706 swap_operands (void)
4712 swap_2_operands (1, i.operands - 2);
4716 swap_2_operands (0, i.operands - 1);
4722 if (i.mem_operands == 2)
4724 const seg_entry *temp_seg;
4725 temp_seg = i.seg[0];
4726 i.seg[0] = i.seg[1];
4727 i.seg[1] = temp_seg;
4731 /* Try to ensure constant immediates are represented in the smallest
4736 char guess_suffix = 0;
4740 guess_suffix = i.suffix;
4741 else if (i.reg_operands)
4743 /* Figure out a suffix from the last register operand specified.
4744 We can't do this properly yet, ie. excluding InOutPortReg,
4745 but the following works for instructions with immediates.
4746 In any case, we can't set i.suffix yet. */
4747 for (op = i.operands; --op >= 0;)
4748 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4750 guess_suffix = BYTE_MNEM_SUFFIX;
4753 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4755 guess_suffix = WORD_MNEM_SUFFIX;
4758 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4760 guess_suffix = LONG_MNEM_SUFFIX;
4763 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4765 guess_suffix = QWORD_MNEM_SUFFIX;
4769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4770 guess_suffix = WORD_MNEM_SUFFIX;
4772 for (op = i.operands; --op >= 0;)
4773 if (operand_type_check (i.types[op], imm))
4775 switch (i.op[op].imms->X_op)
4778 /* If a suffix is given, this operand may be shortened. */
4779 switch (guess_suffix)
4781 case LONG_MNEM_SUFFIX:
4782 i.types[op].bitfield.imm32 = 1;
4783 i.types[op].bitfield.imm64 = 1;
4785 case WORD_MNEM_SUFFIX:
4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
4791 case BYTE_MNEM_SUFFIX:
4792 i.types[op].bitfield.imm8 = 1;
4793 i.types[op].bitfield.imm8s = 1;
4794 i.types[op].bitfield.imm16 = 1;
4795 i.types[op].bitfield.imm32 = 1;
4796 i.types[op].bitfield.imm32s = 1;
4797 i.types[op].bitfield.imm64 = 1;
4801 /* If this operand is at most 16 bits, convert it
4802 to a signed 16 bit number before trying to see
4803 whether it will fit in an even smaller size.
4804 This allows a 16-bit operand such as $0xffe0 to
4805 be recognised as within Imm8S range. */
4806 if ((i.types[op].bitfield.imm16)
4807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4809 i.op[op].imms->X_add_number =
4810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4813 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4814 if ((i.types[op].bitfield.imm32)
4815 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4818 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4819 ^ ((offsetT) 1 << 31))
4820 - ((offsetT) 1 << 31));
4824 = operand_type_or (i.types[op],
4825 smallest_imm_type (i.op[op].imms->X_add_number));
4827 /* We must avoid matching of Imm32 templates when 64bit
4828 only immediate is available. */
4829 if (guess_suffix == QWORD_MNEM_SUFFIX)
4830 i.types[op].bitfield.imm32 = 0;
4837 /* Symbols and expressions. */
4839 /* Convert symbolic operand to proper sizes for matching, but don't
4840 prevent matching a set of insns that only supports sizes other
4841 than those matching the insn suffix. */
4843 i386_operand_type mask, allowed;
4844 const insn_template *t;
4846 operand_type_set (&mask, 0);
4847 operand_type_set (&allowed, 0);
4849 for (t = current_templates->start;
4850 t < current_templates->end;
4852 allowed = operand_type_or (allowed,
4853 t->operand_types[op]);
4854 switch (guess_suffix)
4856 case QWORD_MNEM_SUFFIX:
4857 mask.bitfield.imm64 = 1;
4858 mask.bitfield.imm32s = 1;
4860 case LONG_MNEM_SUFFIX:
4861 mask.bitfield.imm32 = 1;
4863 case WORD_MNEM_SUFFIX:
4864 mask.bitfield.imm16 = 1;
4866 case BYTE_MNEM_SUFFIX:
4867 mask.bitfield.imm8 = 1;
4872 allowed = operand_type_and (mask, allowed);
4873 if (!operand_type_all_zero (&allowed))
4874 i.types[op] = operand_type_and (i.types[op], mask);
4881 /* Try to use the smallest displacement type too. */
4883 optimize_disp (void)
4887 for (op = i.operands; --op >= 0;)
4888 if (operand_type_check (i.types[op], disp))
4890 if (i.op[op].disps->X_op == O_constant)
4892 offsetT op_disp = i.op[op].disps->X_add_number;
4894 if (i.types[op].bitfield.disp16
4895 && (op_disp & ~(offsetT) 0xffff) == 0)
4897 /* If this operand is at most 16 bits, convert
4898 to a signed 16 bit number and don't use 64bit
4900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4901 i.types[op].bitfield.disp64 = 0;
4904 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4905 if (i.types[op].bitfield.disp32
4906 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4908 /* If this operand is at most 32 bits, convert
4909 to a signed 32 bit number and don't use 64bit
4911 op_disp &= (((offsetT) 2 << 31) - 1);
4912 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4913 i.types[op].bitfield.disp64 = 0;
4916 if (!op_disp && i.types[op].bitfield.baseindex)
4918 i.types[op].bitfield.disp8 = 0;
4919 i.types[op].bitfield.disp16 = 0;
4920 i.types[op].bitfield.disp32 = 0;
4921 i.types[op].bitfield.disp32s = 0;
4922 i.types[op].bitfield.disp64 = 0;
4926 else if (flag_code == CODE_64BIT)
4928 if (fits_in_signed_long (op_disp))
4930 i.types[op].bitfield.disp64 = 0;
4931 i.types[op].bitfield.disp32s = 1;
4933 if (i.prefix[ADDR_PREFIX]
4934 && fits_in_unsigned_long (op_disp))
4935 i.types[op].bitfield.disp32 = 1;
4937 if ((i.types[op].bitfield.disp32
4938 || i.types[op].bitfield.disp32s
4939 || i.types[op].bitfield.disp16)
4940 && fits_in_disp8 (op_disp))
4941 i.types[op].bitfield.disp8 = 1;
4943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4947 i.op[op].disps, 0, i.reloc[op]);
4948 i.types[op].bitfield.disp8 = 0;
4949 i.types[op].bitfield.disp16 = 0;
4950 i.types[op].bitfield.disp32 = 0;
4951 i.types[op].bitfield.disp32s = 0;
4952 i.types[op].bitfield.disp64 = 0;
4955 /* We only support 64bit displacement on constants. */
4956 i.types[op].bitfield.disp64 = 0;
4960 /* Check if operands are valid for the instruction. */
4963 check_VecOperands (const insn_template *t)
4967 /* Without VSIB byte, we can't have a vector register for index. */
4968 if (!t->opcode_modifier.vecsib
4970 && (i.index_reg->reg_type.bitfield.xmmword
4971 || i.index_reg->reg_type.bitfield.ymmword
4972 || i.index_reg->reg_type.bitfield.zmmword))
4974 i.error = unsupported_vector_index_register;
4978 /* Check if default mask is allowed. */
4979 if (t->opcode_modifier.nodefmask
4980 && (!i.mask || i.mask->mask->reg_num == 0))
4982 i.error = no_default_mask;
4986 /* For VSIB byte, we need a vector register for index, and all vector
4987 registers must be distinct. */
4988 if (t->opcode_modifier.vecsib)
4991 || !((t->opcode_modifier.vecsib == VecSIB128
4992 && i.index_reg->reg_type.bitfield.xmmword)
4993 || (t->opcode_modifier.vecsib == VecSIB256
4994 && i.index_reg->reg_type.bitfield.ymmword)
4995 || (t->opcode_modifier.vecsib == VecSIB512
4996 && i.index_reg->reg_type.bitfield.zmmword)))
4998 i.error = invalid_vsib_address;
5002 gas_assert (i.reg_operands == 2 || i.mask);
5003 if (i.reg_operands == 2 && !i.mask)
5005 gas_assert (i.types[0].bitfield.regsimd);
5006 gas_assert (i.types[0].bitfield.xmmword
5007 || i.types[0].bitfield.ymmword);
5008 gas_assert (i.types[2].bitfield.regsimd);
5009 gas_assert (i.types[2].bitfield.xmmword
5010 || i.types[2].bitfield.ymmword);
5011 if (operand_check == check_none)
5013 if (register_number (i.op[0].regs)
5014 != register_number (i.index_reg)
5015 && register_number (i.op[2].regs)
5016 != register_number (i.index_reg)
5017 && register_number (i.op[0].regs)
5018 != register_number (i.op[2].regs))
5020 if (operand_check == check_error)
5022 i.error = invalid_vector_register_set;
5025 as_warn (_("mask, index, and destination registers should be distinct"));
5027 else if (i.reg_operands == 1 && i.mask)
5029 if (i.types[1].bitfield.regsimd
5030 && (i.types[1].bitfield.xmmword
5031 || i.types[1].bitfield.ymmword
5032 || i.types[1].bitfield.zmmword)
5033 && (register_number (i.op[1].regs)
5034 == register_number (i.index_reg)))
5036 if (operand_check == check_error)
5038 i.error = invalid_vector_register_set;
5041 if (operand_check != check_none)
5042 as_warn (_("index and destination registers should be distinct"));
5047 /* Check if broadcast is supported by the instruction and is applied
5048 to the memory operand. */
5051 i386_operand_type type, overlap;
5053 /* Check if specified broadcast is supported in this instruction,
5054 and it's applied to memory operand of DWORD or QWORD type. */
5055 op = i.broadcast->operand;
5056 if (!t->opcode_modifier.broadcast
5057 || !i.types[op].bitfield.mem
5058 || (!i.types[op].bitfield.unspecified
5059 && (t->operand_types[op].bitfield.dword
5060 ? !i.types[op].bitfield.dword
5061 : !i.types[op].bitfield.qword)))
5064 i.error = unsupported_broadcast;
5068 operand_type_set (&type, 0);
5069 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5072 type.bitfield.qword = 1;
5075 type.bitfield.xmmword = 1;
5078 type.bitfield.ymmword = 1;
5081 type.bitfield.zmmword = 1;
5087 overlap = operand_type_and (type, t->operand_types[op]);
5088 if (operand_type_all_zero (&overlap))
5091 if (t->opcode_modifier.checkregsize)
5095 for (j = 0; j < i.operands; ++j)
5098 && !operand_type_register_match(i.types[j],
5099 t->operand_types[j],
5101 t->operand_types[op]))
5106 /* If broadcast is supported in this instruction, we need to check if
5107 operand of one-element size isn't specified without broadcast. */
5108 else if (t->opcode_modifier.broadcast && i.mem_operands)
5110 /* Find memory operand. */
5111 for (op = 0; op < i.operands; op++)
5112 if (operand_type_check (i.types[op], anymem))
5114 gas_assert (op < i.operands);
5115 /* Check size of the memory operand. */
5116 if (t->operand_types[op].bitfield.dword
5117 ? i.types[op].bitfield.dword
5118 : i.types[op].bitfield.qword)
5120 i.error = broadcast_needed;
5125 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5127 /* Check if requested masking is supported. */
5129 && (!t->opcode_modifier.masking
5131 && t->opcode_modifier.masking == MERGING_MASKING)))
5133 i.error = unsupported_masking;
5137 /* Check if masking is applied to dest operand. */
5138 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5140 i.error = mask_not_on_destination;
5147 if ((i.rounding->type != saeonly
5148 && !t->opcode_modifier.staticrounding)
5149 || (i.rounding->type == saeonly
5150 && (t->opcode_modifier.staticrounding
5151 || !t->opcode_modifier.sae)))
5153 i.error = unsupported_rc_sae;
5156 /* If the instruction has several immediate operands and one of
5157 them is rounding, the rounding operand should be the last
5158 immediate operand. */
5159 if (i.imm_operands > 1
5160 && i.rounding->operand != (int) (i.imm_operands - 1))
5162 i.error = rc_sae_operand_not_last_imm;
5167 /* Check vector Disp8 operand. */
5168 if (t->opcode_modifier.disp8memshift
5169 && i.disp_encoding != disp_encoding_32bit)
5172 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5174 i.memshift = t->opcode_modifier.disp8memshift;
5176 for (op = 0; op < i.operands; op++)
5177 if (operand_type_check (i.types[op], disp)
5178 && i.op[op].disps->X_op == O_constant)
5180 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5182 i.types[op].bitfield.disp8 = 1;
5185 i.types[op].bitfield.disp8 = 0;
5194 /* Check if operands are valid for the instruction. Update VEX
5198 VEX_check_operands (const insn_template *t)
5200 if (i.vec_encoding == vex_encoding_evex)
5202 /* This instruction must be encoded with EVEX prefix. */
5203 if (!is_evex_encoding (t))
5205 i.error = unsupported;
5211 if (!t->opcode_modifier.vex)
5213 /* This instruction template doesn't have VEX prefix. */
5214 if (i.vec_encoding != vex_encoding_default)
5216 i.error = unsupported;
5222 /* Only check VEX_Imm4, which must be the first operand. */
5223 if (t->operand_types[0].bitfield.vec_imm4)
5225 if (i.op[0].imms->X_op != O_constant
5226 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5232 /* Turn off Imm8 so that update_imm won't complain. */
5233 i.types[0] = vec_imm4;
5239 static const insn_template *
5240 match_template (char mnem_suffix)
5242 /* Points to template once we've found it. */
5243 const insn_template *t;
5244 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5245 i386_operand_type overlap4;
5246 unsigned int found_reverse_match;
5247 i386_opcode_modifier suffix_check, mnemsuf_check;
5248 i386_operand_type operand_types [MAX_OPERANDS];
5249 int addr_prefix_disp;
5251 unsigned int found_cpu_match;
5252 unsigned int check_register;
5253 enum i386_error specific_error = 0;
5255 #if MAX_OPERANDS != 5
5256 # error "MAX_OPERANDS must be 5."
5259 found_reverse_match = 0;
5260 addr_prefix_disp = -1;
5262 memset (&suffix_check, 0, sizeof (suffix_check));
5263 if (i.suffix == BYTE_MNEM_SUFFIX)
5264 suffix_check.no_bsuf = 1;
5265 else if (i.suffix == WORD_MNEM_SUFFIX)
5266 suffix_check.no_wsuf = 1;
5267 else if (i.suffix == SHORT_MNEM_SUFFIX)
5268 suffix_check.no_ssuf = 1;
5269 else if (i.suffix == LONG_MNEM_SUFFIX)
5270 suffix_check.no_lsuf = 1;
5271 else if (i.suffix == QWORD_MNEM_SUFFIX)
5272 suffix_check.no_qsuf = 1;
5273 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5274 suffix_check.no_ldsuf = 1;
5276 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5279 switch (mnem_suffix)
5281 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5282 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5283 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5284 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5285 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5289 /* Must have right number of operands. */
5290 i.error = number_of_operands_mismatch;
5292 for (t = current_templates->start; t < current_templates->end; t++)
5294 addr_prefix_disp = -1;
5296 if (i.operands != t->operands)
5299 /* Check processor support. */
5300 i.error = unsupported;
5301 found_cpu_match = (cpu_flags_match (t)
5302 == CPU_FLAGS_PERFECT_MATCH);
5303 if (!found_cpu_match)
5306 /* Check AT&T mnemonic. */
5307 i.error = unsupported_with_intel_mnemonic;
5308 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5311 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5312 i.error = unsupported_syntax;
5313 if ((intel_syntax && t->opcode_modifier.attsyntax)
5314 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5315 || (intel64 && t->opcode_modifier.amd64)
5316 || (!intel64 && t->opcode_modifier.intel64))
5319 /* Check the suffix, except for some instructions in intel mode. */
5320 i.error = invalid_instruction_suffix;
5321 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5322 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5323 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5324 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5325 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5326 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5327 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5329 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5330 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5331 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5332 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5333 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5334 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5335 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5338 if (!operand_size_match (t))
5341 for (j = 0; j < MAX_OPERANDS; j++)
5342 operand_types[j] = t->operand_types[j];
5344 /* In general, don't allow 64-bit operands in 32-bit mode. */
5345 if (i.suffix == QWORD_MNEM_SUFFIX
5346 && flag_code != CODE_64BIT
5348 ? (!t->opcode_modifier.ignoresize
5349 && !intel_float_operand (t->name))
5350 : intel_float_operand (t->name) != 2)
5351 && ((!operand_types[0].bitfield.regmmx
5352 && !operand_types[0].bitfield.regsimd)
5353 || (!operand_types[t->operands > 1].bitfield.regmmx
5354 && !operand_types[t->operands > 1].bitfield.regsimd))
5355 && (t->base_opcode != 0x0fc7
5356 || t->extension_opcode != 1 /* cmpxchg8b */))
5359 /* In general, don't allow 32-bit operands on pre-386. */
5360 else if (i.suffix == LONG_MNEM_SUFFIX
5361 && !cpu_arch_flags.bitfield.cpui386
5363 ? (!t->opcode_modifier.ignoresize
5364 && !intel_float_operand (t->name))
5365 : intel_float_operand (t->name) != 2)
5366 && ((!operand_types[0].bitfield.regmmx
5367 && !operand_types[0].bitfield.regsimd)
5368 || (!operand_types[t->operands > 1].bitfield.regmmx
5369 && !operand_types[t->operands > 1].bitfield.regsimd)))
5372 /* Do not verify operands when there are none. */
5376 /* We've found a match; break out of loop. */
5380 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5381 into Disp32/Disp16/Disp32 operand. */
5382 if (i.prefix[ADDR_PREFIX] != 0)
5384 /* There should be only one Disp operand. */
5388 for (j = 0; j < MAX_OPERANDS; j++)
5390 if (operand_types[j].bitfield.disp16)
5392 addr_prefix_disp = j;
5393 operand_types[j].bitfield.disp32 = 1;
5394 operand_types[j].bitfield.disp16 = 0;
5400 for (j = 0; j < MAX_OPERANDS; j++)
5402 if (operand_types[j].bitfield.disp32)
5404 addr_prefix_disp = j;
5405 operand_types[j].bitfield.disp32 = 0;
5406 operand_types[j].bitfield.disp16 = 1;
5412 for (j = 0; j < MAX_OPERANDS; j++)
5414 if (operand_types[j].bitfield.disp64)
5416 addr_prefix_disp = j;
5417 operand_types[j].bitfield.disp64 = 0;
5418 operand_types[j].bitfield.disp32 = 1;
5426 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5427 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5430 /* We check register size if needed. */
5431 check_register = t->opcode_modifier.checkregsize;
5432 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5433 switch (t->operands)
5436 if (!operand_type_match (overlap0, i.types[0]))
5440 /* xchg %eax, %eax is a special case. It is an alias for nop
5441 only in 32bit mode and we can use opcode 0x90. In 64bit
5442 mode, we can't use 0x90 for xchg %eax, %eax since it should
5443 zero-extend %eax to %rax. */
5444 if (flag_code == CODE_64BIT
5445 && t->base_opcode == 0x90
5446 && operand_type_equal (&i.types [0], &acc32)
5447 && operand_type_equal (&i.types [1], &acc32))
5449 /* xrelease mov %eax, <disp> is another special case. It must not
5450 match the accumulator-only encoding of mov. */
5451 if (flag_code != CODE_64BIT
5453 && t->base_opcode == 0xa0
5454 && i.types[0].bitfield.acc
5455 && operand_type_check (i.types[1], anymem))
5457 /* If we want store form, we reverse direction of operands. */
5458 if (i.dir_encoding == dir_encoding_store
5459 && t->opcode_modifier.d)
5464 /* If we want store form, we skip the current load. */
5465 if (i.dir_encoding == dir_encoding_store
5466 && i.mem_operands == 0
5467 && t->opcode_modifier.load)
5472 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5473 if (!operand_type_match (overlap0, i.types[0])
5474 || !operand_type_match (overlap1, i.types[1])
5476 && !operand_type_register_match (i.types[0],
5481 /* Check if other direction is valid ... */
5482 if (!t->opcode_modifier.d)
5486 /* Try reversing direction of operands. */
5487 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5488 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5489 if (!operand_type_match (overlap0, i.types[0])
5490 || !operand_type_match (overlap1, i.types[1])
5492 && !operand_type_register_match (i.types[0],
5497 /* Does not match either direction. */
5500 /* found_reverse_match holds which of D or FloatR
5502 if (!t->opcode_modifier.d)
5503 found_reverse_match = 0;
5504 else if (operand_types[0].bitfield.tbyte)
5505 found_reverse_match = Opcode_FloatD;
5507 found_reverse_match = Opcode_D;
5508 if (t->opcode_modifier.floatr)
5509 found_reverse_match |= Opcode_FloatR;
5513 /* Found a forward 2 operand match here. */
5514 switch (t->operands)
5517 overlap4 = operand_type_and (i.types[4],
5521 overlap3 = operand_type_and (i.types[3],
5525 overlap2 = operand_type_and (i.types[2],
5530 switch (t->operands)
5533 if (!operand_type_match (overlap4, i.types[4])
5534 || !operand_type_register_match (i.types[3],
5541 if (!operand_type_match (overlap3, i.types[3])
5543 && (!operand_type_register_match (i.types[1],
5547 || !operand_type_register_match (i.types[2],
5550 operand_types[3]))))
5554 /* Here we make use of the fact that there are no
5555 reverse match 3 operand instructions. */
5556 if (!operand_type_match (overlap2, i.types[2])
5558 && (!operand_type_register_match (i.types[0],
5562 || !operand_type_register_match (i.types[1],
5565 operand_types[2]))))
5570 /* Found either forward/reverse 2, 3 or 4 operand match here:
5571 slip through to break. */
5573 if (!found_cpu_match)
5575 found_reverse_match = 0;
5579 /* Check if vector and VEX operands are valid. */
5580 if (check_VecOperands (t) || VEX_check_operands (t))
5582 specific_error = i.error;
5586 /* We've found a match; break out of loop. */
5590 if (t == current_templates->end)
5592 /* We found no match. */
5593 const char *err_msg;
5594 switch (specific_error ? specific_error : i.error)
5598 case operand_size_mismatch:
5599 err_msg = _("operand size mismatch");
5601 case operand_type_mismatch:
5602 err_msg = _("operand type mismatch");
5604 case register_type_mismatch:
5605 err_msg = _("register type mismatch");
5607 case number_of_operands_mismatch:
5608 err_msg = _("number of operands mismatch");
5610 case invalid_instruction_suffix:
5611 err_msg = _("invalid instruction suffix");
5614 err_msg = _("constant doesn't fit in 4 bits");
5616 case unsupported_with_intel_mnemonic:
5617 err_msg = _("unsupported with Intel mnemonic");
5619 case unsupported_syntax:
5620 err_msg = _("unsupported syntax");
5623 as_bad (_("unsupported instruction `%s'"),
5624 current_templates->start->name);
5626 case invalid_vsib_address:
5627 err_msg = _("invalid VSIB address");
5629 case invalid_vector_register_set:
5630 err_msg = _("mask, index, and destination registers must be distinct");
5632 case unsupported_vector_index_register:
5633 err_msg = _("unsupported vector index register");
5635 case unsupported_broadcast:
5636 err_msg = _("unsupported broadcast");
5638 case broadcast_not_on_src_operand:
5639 err_msg = _("broadcast not on source memory operand");
5641 case broadcast_needed:
5642 err_msg = _("broadcast is needed for operand of such type");
5644 case unsupported_masking:
5645 err_msg = _("unsupported masking");
5647 case mask_not_on_destination:
5648 err_msg = _("mask not on destination operand");
5650 case no_default_mask:
5651 err_msg = _("default mask isn't allowed");
5653 case unsupported_rc_sae:
5654 err_msg = _("unsupported static rounding/sae");
5656 case rc_sae_operand_not_last_imm:
5658 err_msg = _("RC/SAE operand must precede immediate operands");
5660 err_msg = _("RC/SAE operand must follow immediate operands");
5662 case invalid_register_operand:
5663 err_msg = _("invalid register operand");
5666 as_bad (_("%s for `%s'"), err_msg,
5667 current_templates->start->name);
5671 if (!quiet_warnings)
5674 && (i.types[0].bitfield.jumpabsolute
5675 != operand_types[0].bitfield.jumpabsolute))
5677 as_warn (_("indirect %s without `*'"), t->name);
5680 if (t->opcode_modifier.isprefix
5681 && t->opcode_modifier.ignoresize)
5683 /* Warn them that a data or address size prefix doesn't
5684 affect assembly of the next line of code. */
5685 as_warn (_("stand-alone `%s' prefix"), t->name);
5689 /* Copy the template we found. */
5692 if (addr_prefix_disp != -1)
5693 i.tm.operand_types[addr_prefix_disp]
5694 = operand_types[addr_prefix_disp];
5696 if (found_reverse_match)
5698 /* If we found a reverse match we must alter the opcode
5699 direction bit. found_reverse_match holds bits to change
5700 (different for int & float insns). */
5702 i.tm.base_opcode ^= found_reverse_match;
5704 i.tm.operand_types[0] = operand_types[1];
5705 i.tm.operand_types[1] = operand_types[0];
5714 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5715 if (i.tm.operand_types[mem_op].bitfield.esseg)
5717 if (i.seg[0] != NULL && i.seg[0] != &es)
5719 as_bad (_("`%s' operand %d must use `%ses' segment"),
5725 /* There's only ever one segment override allowed per instruction.
5726 This instruction possibly has a legal segment override on the
5727 second operand, so copy the segment to where non-string
5728 instructions store it, allowing common code. */
5729 i.seg[0] = i.seg[1];
5731 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5733 if (i.seg[1] != NULL && i.seg[1] != &es)
5735 as_bad (_("`%s' operand %d must use `%ses' segment"),
5746 process_suffix (void)
5748 /* If matched instruction specifies an explicit instruction mnemonic
5750 if (i.tm.opcode_modifier.size16)
5751 i.suffix = WORD_MNEM_SUFFIX;
5752 else if (i.tm.opcode_modifier.size32)
5753 i.suffix = LONG_MNEM_SUFFIX;
5754 else if (i.tm.opcode_modifier.size64)
5755 i.suffix = QWORD_MNEM_SUFFIX;
5756 else if (i.reg_operands)
5758 /* If there's no instruction mnemonic suffix we try to invent one
5759 based on register operands. */
5762 /* We take i.suffix from the last register operand specified,
5763 Destination register type is more significant than source
5764 register type. crc32 in SSE4.2 prefers source register
5766 if (i.tm.base_opcode == 0xf20f38f1)
5768 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5769 i.suffix = WORD_MNEM_SUFFIX;
5770 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5771 i.suffix = LONG_MNEM_SUFFIX;
5772 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5773 i.suffix = QWORD_MNEM_SUFFIX;
5775 else if (i.tm.base_opcode == 0xf20f38f0)
5777 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5778 i.suffix = BYTE_MNEM_SUFFIX;
5785 if (i.tm.base_opcode == 0xf20f38f1
5786 || i.tm.base_opcode == 0xf20f38f0)
5788 /* We have to know the operand size for crc32. */
5789 as_bad (_("ambiguous memory operand size for `%s`"),
5794 for (op = i.operands; --op >= 0;)
5795 if (!i.tm.operand_types[op].bitfield.inoutportreg
5796 && !i.tm.operand_types[op].bitfield.shiftcount)
5798 if (!i.types[op].bitfield.reg)
5800 if (i.types[op].bitfield.byte)
5801 i.suffix = BYTE_MNEM_SUFFIX;
5802 else if (i.types[op].bitfield.word)
5803 i.suffix = WORD_MNEM_SUFFIX;
5804 else if (i.types[op].bitfield.dword)
5805 i.suffix = LONG_MNEM_SUFFIX;
5806 else if (i.types[op].bitfield.qword)
5807 i.suffix = QWORD_MNEM_SUFFIX;
5814 else if (i.suffix == BYTE_MNEM_SUFFIX)
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_bsuf)
5820 else if (!check_byte_reg ())
5823 else if (i.suffix == LONG_MNEM_SUFFIX)
5826 && i.tm.opcode_modifier.ignoresize
5827 && i.tm.opcode_modifier.no_lsuf
5828 && !i.tm.opcode_modifier.todword
5829 && !i.tm.opcode_modifier.toqword)
5831 else if (!check_long_reg ())
5834 else if (i.suffix == QWORD_MNEM_SUFFIX)
5837 && i.tm.opcode_modifier.ignoresize
5838 && i.tm.opcode_modifier.no_qsuf
5839 && !i.tm.opcode_modifier.todword
5840 && !i.tm.opcode_modifier.toqword)
5842 else if (!check_qword_reg ())
5845 else if (i.suffix == WORD_MNEM_SUFFIX)
5848 && i.tm.opcode_modifier.ignoresize
5849 && i.tm.opcode_modifier.no_wsuf)
5851 else if (!check_word_reg ())
5854 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5855 /* Do nothing if the instruction is going to ignore the prefix. */
5860 else if (i.tm.opcode_modifier.defaultsize
5862 /* exclude fldenv/frstor/fsave/fstenv */
5863 && i.tm.opcode_modifier.no_ssuf)
5865 i.suffix = stackop_size;
5867 else if (intel_syntax
5869 && (i.tm.operand_types[0].bitfield.jumpabsolute
5870 || i.tm.opcode_modifier.jumpbyte
5871 || i.tm.opcode_modifier.jumpintersegment
5872 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5873 && i.tm.extension_opcode <= 3)))
5878 if (!i.tm.opcode_modifier.no_qsuf)
5880 i.suffix = QWORD_MNEM_SUFFIX;
5885 if (!i.tm.opcode_modifier.no_lsuf)
5886 i.suffix = LONG_MNEM_SUFFIX;
5889 if (!i.tm.opcode_modifier.no_wsuf)
5890 i.suffix = WORD_MNEM_SUFFIX;
5899 if (i.tm.opcode_modifier.w)
5901 as_bad (_("no instruction mnemonic suffix given and "
5902 "no register operands; can't size instruction"));
5908 unsigned int suffixes;
5910 suffixes = !i.tm.opcode_modifier.no_bsuf;
5911 if (!i.tm.opcode_modifier.no_wsuf)
5913 if (!i.tm.opcode_modifier.no_lsuf)
5915 if (!i.tm.opcode_modifier.no_ldsuf)
5917 if (!i.tm.opcode_modifier.no_ssuf)
5919 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5922 /* There are more than suffix matches. */
5923 if (i.tm.opcode_modifier.w
5924 || ((suffixes & (suffixes - 1))
5925 && !i.tm.opcode_modifier.defaultsize
5926 && !i.tm.opcode_modifier.ignoresize))
5928 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5934 /* Change the opcode based on the operand size given by i.suffix. */
5937 /* Size floating point instruction. */
5938 case LONG_MNEM_SUFFIX:
5939 if (i.tm.opcode_modifier.floatmf)
5941 i.tm.base_opcode ^= 4;
5945 case WORD_MNEM_SUFFIX:
5946 case QWORD_MNEM_SUFFIX:
5947 /* It's not a byte, select word/dword operation. */
5948 if (i.tm.opcode_modifier.w)
5950 if (i.tm.opcode_modifier.shortform)
5951 i.tm.base_opcode |= 8;
5953 i.tm.base_opcode |= 1;
5956 case SHORT_MNEM_SUFFIX:
5957 /* Now select between word & dword operations via the operand
5958 size prefix, except for instructions that will ignore this
5960 if (i.tm.opcode_modifier.addrprefixop0)
5962 /* The address size override prefix changes the size of the
5964 if ((flag_code == CODE_32BIT
5965 && i.op->regs[0].reg_type.bitfield.word)
5966 || (flag_code != CODE_32BIT
5967 && i.op->regs[0].reg_type.bitfield.dword))
5968 if (!add_prefix (ADDR_PREFIX_OPCODE))
5971 else if (i.suffix != QWORD_MNEM_SUFFIX
5972 && !i.tm.opcode_modifier.ignoresize
5973 && !i.tm.opcode_modifier.floatmf
5974 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5975 || (flag_code == CODE_64BIT
5976 && i.tm.opcode_modifier.jumpbyte)))
5978 unsigned int prefix = DATA_PREFIX_OPCODE;
5980 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5981 prefix = ADDR_PREFIX_OPCODE;
5983 if (!add_prefix (prefix))
5987 /* Set mode64 for an operand. */
5988 if (i.suffix == QWORD_MNEM_SUFFIX
5989 && flag_code == CODE_64BIT
5990 && !i.tm.opcode_modifier.norex64
5991 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5993 && ! (i.operands == 2
5994 && i.tm.base_opcode == 0x90
5995 && i.tm.extension_opcode == None
5996 && operand_type_equal (&i.types [0], &acc64)
5997 && operand_type_equal (&i.types [1], &acc64)))
6007 check_byte_reg (void)
6011 for (op = i.operands; --op >= 0;)
6013 /* Skip non-register operands. */
6014 if (!i.types[op].bitfield.reg)
6017 /* If this is an eight bit register, it's OK. If it's the 16 or
6018 32 bit version of an eight bit register, we will just use the
6019 low portion, and that's OK too. */
6020 if (i.types[op].bitfield.byte)
6023 /* I/O port address operands are OK too. */
6024 if (i.tm.operand_types[op].bitfield.inoutportreg)
6027 /* crc32 doesn't generate this warning. */
6028 if (i.tm.base_opcode == 0xf20f38f0)
6031 if ((i.types[op].bitfield.word
6032 || i.types[op].bitfield.dword
6033 || i.types[op].bitfield.qword)
6034 && i.op[op].regs->reg_num < 4
6035 /* Prohibit these changes in 64bit mode, since the lowering
6036 would be more complicated. */
6037 && flag_code != CODE_64BIT)
6039 #if REGISTER_WARNINGS
6040 if (!quiet_warnings)
6041 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6043 (i.op[op].regs + (i.types[op].bitfield.word
6044 ? REGNAM_AL - REGNAM_AX
6045 : REGNAM_AL - REGNAM_EAX))->reg_name,
6047 i.op[op].regs->reg_name,
6052 /* Any other register is bad. */
6053 if (i.types[op].bitfield.reg
6054 || i.types[op].bitfield.regmmx
6055 || i.types[op].bitfield.regsimd
6056 || i.types[op].bitfield.sreg2
6057 || i.types[op].bitfield.sreg3
6058 || i.types[op].bitfield.control
6059 || i.types[op].bitfield.debug
6060 || i.types[op].bitfield.test)
6062 as_bad (_("`%s%s' not allowed with `%s%c'"),
6064 i.op[op].regs->reg_name,
6074 check_long_reg (void)
6078 for (op = i.operands; --op >= 0;)
6079 /* Skip non-register operands. */
6080 if (!i.types[op].bitfield.reg)
6082 /* Reject eight bit registers, except where the template requires
6083 them. (eg. movzb) */
6084 else if (i.types[op].bitfield.byte
6085 && (i.tm.operand_types[op].bitfield.reg
6086 || i.tm.operand_types[op].bitfield.acc)
6087 && (i.tm.operand_types[op].bitfield.word
6088 || i.tm.operand_types[op].bitfield.dword))
6090 as_bad (_("`%s%s' not allowed with `%s%c'"),
6092 i.op[op].regs->reg_name,
6097 /* Warn if the e prefix on a general reg is missing. */
6098 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6099 && i.types[op].bitfield.word
6100 && (i.tm.operand_types[op].bitfield.reg
6101 || i.tm.operand_types[op].bitfield.acc)
6102 && i.tm.operand_types[op].bitfield.dword)
6104 /* Prohibit these changes in the 64bit mode, since the
6105 lowering is more complicated. */
6106 if (flag_code == CODE_64BIT)
6108 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6109 register_prefix, i.op[op].regs->reg_name,
6113 #if REGISTER_WARNINGS
6114 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6116 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6117 register_prefix, i.op[op].regs->reg_name, i.suffix);
6120 /* Warn if the r prefix on a general reg is present. */
6121 else if (i.types[op].bitfield.qword
6122 && (i.tm.operand_types[op].bitfield.reg
6123 || i.tm.operand_types[op].bitfield.acc)
6124 && i.tm.operand_types[op].bitfield.dword)
6127 && i.tm.opcode_modifier.toqword
6128 && !i.types[0].bitfield.regsimd)
6130 /* Convert to QWORD. We want REX byte. */
6131 i.suffix = QWORD_MNEM_SUFFIX;
6135 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6136 register_prefix, i.op[op].regs->reg_name,
6145 check_qword_reg (void)
6149 for (op = i.operands; --op >= 0; )
6150 /* Skip non-register operands. */
6151 if (!i.types[op].bitfield.reg)
6153 /* Reject eight bit registers, except where the template requires
6154 them. (eg. movzb) */
6155 else if (i.types[op].bitfield.byte
6156 && (i.tm.operand_types[op].bitfield.reg
6157 || i.tm.operand_types[op].bitfield.acc)
6158 && (i.tm.operand_types[op].bitfield.word
6159 || i.tm.operand_types[op].bitfield.dword))
6161 as_bad (_("`%s%s' not allowed with `%s%c'"),
6163 i.op[op].regs->reg_name,
6168 /* Warn if the r prefix on a general reg is missing. */
6169 else if ((i.types[op].bitfield.word
6170 || i.types[op].bitfield.dword)
6171 && (i.tm.operand_types[op].bitfield.reg
6172 || i.tm.operand_types[op].bitfield.acc)
6173 && i.tm.operand_types[op].bitfield.qword)
6175 /* Prohibit these changes in the 64bit mode, since the
6176 lowering is more complicated. */
6178 && i.tm.opcode_modifier.todword
6179 && !i.types[0].bitfield.regsimd)
6181 /* Convert to DWORD. We don't want REX byte. */
6182 i.suffix = LONG_MNEM_SUFFIX;
6186 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6187 register_prefix, i.op[op].regs->reg_name,
6196 check_word_reg (void)
6199 for (op = i.operands; --op >= 0;)
6200 /* Skip non-register operands. */
6201 if (!i.types[op].bitfield.reg)
6203 /* Reject eight bit registers, except where the template requires
6204 them. (eg. movzb) */
6205 else if (i.types[op].bitfield.byte
6206 && (i.tm.operand_types[op].bitfield.reg
6207 || i.tm.operand_types[op].bitfield.acc)
6208 && (i.tm.operand_types[op].bitfield.word
6209 || i.tm.operand_types[op].bitfield.dword))
6211 as_bad (_("`%s%s' not allowed with `%s%c'"),
6213 i.op[op].regs->reg_name,
6218 /* Warn if the e or r prefix on a general reg is present. */
6219 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6220 && (i.types[op].bitfield.dword
6221 || i.types[op].bitfield.qword)
6222 && (i.tm.operand_types[op].bitfield.reg
6223 || i.tm.operand_types[op].bitfield.acc)
6224 && i.tm.operand_types[op].bitfield.word)
6226 /* Prohibit these changes in the 64bit mode, since the
6227 lowering is more complicated. */
6228 if (flag_code == CODE_64BIT)
6230 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6231 register_prefix, i.op[op].regs->reg_name,
6235 #if REGISTER_WARNINGS
6236 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6238 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6239 register_prefix, i.op[op].regs->reg_name, i.suffix);
6246 update_imm (unsigned int j)
6248 i386_operand_type overlap = i.types[j];
6249 if ((overlap.bitfield.imm8
6250 || overlap.bitfield.imm8s
6251 || overlap.bitfield.imm16
6252 || overlap.bitfield.imm32
6253 || overlap.bitfield.imm32s
6254 || overlap.bitfield.imm64)
6255 && !operand_type_equal (&overlap, &imm8)
6256 && !operand_type_equal (&overlap, &imm8s)
6257 && !operand_type_equal (&overlap, &imm16)
6258 && !operand_type_equal (&overlap, &imm32)
6259 && !operand_type_equal (&overlap, &imm32s)
6260 && !operand_type_equal (&overlap, &imm64))
6264 i386_operand_type temp;
6266 operand_type_set (&temp, 0);
6267 if (i.suffix == BYTE_MNEM_SUFFIX)
6269 temp.bitfield.imm8 = overlap.bitfield.imm8;
6270 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6272 else if (i.suffix == WORD_MNEM_SUFFIX)
6273 temp.bitfield.imm16 = overlap.bitfield.imm16;
6274 else if (i.suffix == QWORD_MNEM_SUFFIX)
6276 temp.bitfield.imm64 = overlap.bitfield.imm64;
6277 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6280 temp.bitfield.imm32 = overlap.bitfield.imm32;
6283 else if (operand_type_equal (&overlap, &imm16_32_32s)
6284 || operand_type_equal (&overlap, &imm16_32)
6285 || operand_type_equal (&overlap, &imm16_32s))
6287 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6292 if (!operand_type_equal (&overlap, &imm8)
6293 && !operand_type_equal (&overlap, &imm8s)
6294 && !operand_type_equal (&overlap, &imm16)
6295 && !operand_type_equal (&overlap, &imm32)
6296 && !operand_type_equal (&overlap, &imm32s)
6297 && !operand_type_equal (&overlap, &imm64))
6299 as_bad (_("no instruction mnemonic suffix given; "
6300 "can't determine immediate size"));
6304 i.types[j] = overlap;
6314 /* Update the first 2 immediate operands. */
6315 n = i.operands > 2 ? 2 : i.operands;
6318 for (j = 0; j < n; j++)
6319 if (update_imm (j) == 0)
6322 /* The 3rd operand can't be immediate operand. */
6323 gas_assert (operand_type_check (i.types[2], imm) == 0);
6330 process_operands (void)
6332 /* Default segment register this instruction will use for memory
6333 accesses. 0 means unknown. This is only for optimizing out
6334 unnecessary segment overrides. */
6335 const seg_entry *default_seg = 0;
6337 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6339 unsigned int dupl = i.operands;
6340 unsigned int dest = dupl - 1;
6343 /* The destination must be an xmm register. */
6344 gas_assert (i.reg_operands
6345 && MAX_OPERANDS > dupl
6346 && operand_type_equal (&i.types[dest], ®xmm));
6348 if (i.tm.operand_types[0].bitfield.acc
6349 && i.tm.operand_types[0].bitfield.xmmword)
6351 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6353 /* Keep xmm0 for instructions with VEX prefix and 3
6355 i.tm.operand_types[0].bitfield.acc = 0;
6356 i.tm.operand_types[0].bitfield.regsimd = 1;
6361 /* We remove the first xmm0 and keep the number of
6362 operands unchanged, which in fact duplicates the
6364 for (j = 1; j < i.operands; j++)
6366 i.op[j - 1] = i.op[j];
6367 i.types[j - 1] = i.types[j];
6368 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6372 else if (i.tm.opcode_modifier.implicit1stxmm0)
6374 gas_assert ((MAX_OPERANDS - 1) > dupl
6375 && (i.tm.opcode_modifier.vexsources
6378 /* Add the implicit xmm0 for instructions with VEX prefix
6380 for (j = i.operands; j > 0; j--)
6382 i.op[j] = i.op[j - 1];
6383 i.types[j] = i.types[j - 1];
6384 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6387 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6388 i.types[0] = regxmm;
6389 i.tm.operand_types[0] = regxmm;
6392 i.reg_operands += 2;
6397 i.op[dupl] = i.op[dest];
6398 i.types[dupl] = i.types[dest];
6399 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6408 i.op[dupl] = i.op[dest];
6409 i.types[dupl] = i.types[dest];
6410 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6413 if (i.tm.opcode_modifier.immext)
6416 else if (i.tm.operand_types[0].bitfield.acc
6417 && i.tm.operand_types[0].bitfield.xmmword)
6421 for (j = 1; j < i.operands; j++)
6423 i.op[j - 1] = i.op[j];
6424 i.types[j - 1] = i.types[j];
6426 /* We need to adjust fields in i.tm since they are used by
6427 build_modrm_byte. */
6428 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6435 else if (i.tm.opcode_modifier.implicitquadgroup)
6437 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6439 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6440 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6441 regnum = register_number (i.op[1].regs);
6442 first_reg_in_group = regnum & ~3;
6443 last_reg_in_group = first_reg_in_group + 3;
6444 if (regnum != first_reg_in_group)
6445 as_warn (_("source register `%s%s' implicitly denotes"
6446 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6447 register_prefix, i.op[1].regs->reg_name,
6448 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6449 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6452 else if (i.tm.opcode_modifier.regkludge)
6454 /* The imul $imm, %reg instruction is converted into
6455 imul $imm, %reg, %reg, and the clr %reg instruction
6456 is converted into xor %reg, %reg. */
6458 unsigned int first_reg_op;
6460 if (operand_type_check (i.types[0], reg))
6464 /* Pretend we saw the extra register operand. */
6465 gas_assert (i.reg_operands == 1
6466 && i.op[first_reg_op + 1].regs == 0);
6467 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6468 i.types[first_reg_op + 1] = i.types[first_reg_op];
6473 if (i.tm.opcode_modifier.shortform)
6475 if (i.types[0].bitfield.sreg2
6476 || i.types[0].bitfield.sreg3)
6478 if (i.tm.base_opcode == POP_SEG_SHORT
6479 && i.op[0].regs->reg_num == 1)
6481 as_bad (_("you can't `pop %scs'"), register_prefix);
6484 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6485 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6490 /* The register or float register operand is in operand
6494 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6495 || operand_type_check (i.types[0], reg))
6499 /* Register goes in low 3 bits of opcode. */
6500 i.tm.base_opcode |= i.op[op].regs->reg_num;
6501 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6503 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6505 /* Warn about some common errors, but press on regardless.
6506 The first case can be generated by gcc (<= 2.8.1). */
6507 if (i.operands == 2)
6509 /* Reversed arguments on faddp, fsubp, etc. */
6510 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6511 register_prefix, i.op[!intel_syntax].regs->reg_name,
6512 register_prefix, i.op[intel_syntax].regs->reg_name);
6516 /* Extraneous `l' suffix on fp insn. */
6517 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6518 register_prefix, i.op[0].regs->reg_name);
6523 else if (i.tm.opcode_modifier.modrm)
6525 /* The opcode is completed (modulo i.tm.extension_opcode which
6526 must be put into the modrm byte). Now, we make the modrm and
6527 index base bytes based on all the info we've collected. */
6529 default_seg = build_modrm_byte ();
6531 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6535 else if (i.tm.opcode_modifier.isstring)
6537 /* For the string instructions that allow a segment override
6538 on one of their operands, the default segment is ds. */
6542 if (i.tm.base_opcode == 0x8d /* lea */
6545 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6547 /* If a segment was explicitly specified, and the specified segment
6548 is not the default, use an opcode prefix to select it. If we
6549 never figured out what the default segment is, then default_seg
6550 will be zero at this point, and the specified segment prefix will
6552 if ((i.seg[0]) && (i.seg[0] != default_seg))
6554 if (!add_prefix (i.seg[0]->seg_prefix))
6560 static const seg_entry *
6561 build_modrm_byte (void)
6563 const seg_entry *default_seg = 0;
6564 unsigned int source, dest;
6567 /* The first operand of instructions with VEX prefix and 3 sources
6568 must be VEX_Imm4. */
6569 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6572 unsigned int nds, reg_slot;
6575 if (i.tm.opcode_modifier.veximmext
6576 && i.tm.opcode_modifier.immext)
6578 dest = i.operands - 2;
6579 gas_assert (dest == 3);
6582 dest = i.operands - 1;
6585 /* There are 2 kinds of instructions:
6586 1. 5 operands: 4 register operands or 3 register operands
6587 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6588 VexW0 or VexW1. The destination must be either XMM, YMM or
6590 2. 4 operands: 4 register operands or 3 register operands
6591 plus 1 memory operand, VexXDS, and VexImmExt */
6592 gas_assert ((i.reg_operands == 4
6593 || (i.reg_operands == 3 && i.mem_operands == 1))
6594 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6595 && (i.tm.opcode_modifier.veximmext
6596 || (i.imm_operands == 1
6597 && i.types[0].bitfield.vec_imm4
6598 && (i.tm.opcode_modifier.vexw == VEXW0
6599 || i.tm.opcode_modifier.vexw == VEXW1)
6600 && i.tm.operand_types[dest].bitfield.regsimd)));
6602 if (i.imm_operands == 0)
6604 /* When there is no immediate operand, generate an 8bit
6605 immediate operand to encode the first operand. */
6606 exp = &im_expressions[i.imm_operands++];
6607 i.op[i.operands].imms = exp;
6608 i.types[i.operands] = imm8;
6610 /* If VexW1 is set, the first operand is the source and
6611 the second operand is encoded in the immediate operand. */
6612 if (i.tm.opcode_modifier.vexw == VEXW1)
6623 /* FMA swaps REG and NDS. */
6624 if (i.tm.cpu_flags.bitfield.cpufma)
6632 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6633 exp->X_op = O_constant;
6634 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6635 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6639 unsigned int imm_slot;
6641 if (i.tm.opcode_modifier.vexw == VEXW0)
6643 /* If VexW0 is set, the third operand is the source and
6644 the second operand is encoded in the immediate
6651 /* VexW1 is set, the second operand is the source and
6652 the third operand is encoded in the immediate
6658 if (i.tm.opcode_modifier.immext)
6660 /* When ImmExt is set, the immediate byte is the last
6662 imm_slot = i.operands - 1;
6670 /* Turn on Imm8 so that output_imm will generate it. */
6671 i.types[imm_slot].bitfield.imm8 = 1;
6674 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6675 i.op[imm_slot].imms->X_add_number
6676 |= register_number (i.op[reg_slot].regs) << 4;
6677 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6680 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6681 i.vex.register_specifier = i.op[nds].regs;
6686 /* i.reg_operands MUST be the number of real register operands;
6687 implicit registers do not count. If there are 3 register
6688 operands, it must be a instruction with VexNDS. For a
6689 instruction with VexNDD, the destination register is encoded
6690 in VEX prefix. If there are 4 register operands, it must be
6691 a instruction with VEX prefix and 3 sources. */
6692 if (i.mem_operands == 0
6693 && ((i.reg_operands == 2
6694 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6695 || (i.reg_operands == 3
6696 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6697 || (i.reg_operands == 4 && vex_3_sources)))
6705 /* When there are 3 operands, one of them may be immediate,
6706 which may be the first or the last operand. Otherwise,
6707 the first operand must be shift count register (cl) or it
6708 is an instruction with VexNDS. */
6709 gas_assert (i.imm_operands == 1
6710 || (i.imm_operands == 0
6711 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6712 || i.types[0].bitfield.shiftcount)));
6713 if (operand_type_check (i.types[0], imm)
6714 || i.types[0].bitfield.shiftcount)
6720 /* When there are 4 operands, the first two must be 8bit
6721 immediate operands. The source operand will be the 3rd
6724 For instructions with VexNDS, if the first operand
6725 an imm8, the source operand is the 2nd one. If the last
6726 operand is imm8, the source operand is the first one. */
6727 gas_assert ((i.imm_operands == 2
6728 && i.types[0].bitfield.imm8
6729 && i.types[1].bitfield.imm8)
6730 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6731 && i.imm_operands == 1
6732 && (i.types[0].bitfield.imm8
6733 || i.types[i.operands - 1].bitfield.imm8
6735 if (i.imm_operands == 2)
6739 if (i.types[0].bitfield.imm8)
6746 if (is_evex_encoding (&i.tm))
6748 /* For EVEX instructions, when there are 5 operands, the
6749 first one must be immediate operand. If the second one
6750 is immediate operand, the source operand is the 3th
6751 one. If the last one is immediate operand, the source
6752 operand is the 2nd one. */
6753 gas_assert (i.imm_operands == 2
6754 && i.tm.opcode_modifier.sae
6755 && operand_type_check (i.types[0], imm));
6756 if (operand_type_check (i.types[1], imm))
6758 else if (operand_type_check (i.types[4], imm))
6772 /* RC/SAE operand could be between DEST and SRC. That happens
6773 when one operand is GPR and the other one is XMM/YMM/ZMM
6775 if (i.rounding && i.rounding->operand == (int) dest)
6778 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6780 /* For instructions with VexNDS, the register-only source
6781 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6782 register. It is encoded in VEX prefix. We need to
6783 clear RegMem bit before calling operand_type_equal. */
6785 i386_operand_type op;
6788 /* Check register-only source operand when two source
6789 operands are swapped. */
6790 if (!i.tm.operand_types[source].bitfield.baseindex
6791 && i.tm.operand_types[dest].bitfield.baseindex)
6799 op = i.tm.operand_types[vvvv];
6800 op.bitfield.regmem = 0;
6801 if ((dest + 1) >= i.operands
6802 || ((!op.bitfield.reg
6803 || (!op.bitfield.dword && !op.bitfield.qword))
6804 && !op.bitfield.regsimd
6805 && !operand_type_equal (&op, ®mask)))
6807 i.vex.register_specifier = i.op[vvvv].regs;
6813 /* One of the register operands will be encoded in the i.tm.reg
6814 field, the other in the combined i.tm.mode and i.tm.regmem
6815 fields. If no form of this instruction supports a memory
6816 destination operand, then we assume the source operand may
6817 sometimes be a memory operand and so we need to store the
6818 destination in the i.rm.reg field. */
6819 if (!i.tm.operand_types[dest].bitfield.regmem
6820 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6822 i.rm.reg = i.op[dest].regs->reg_num;
6823 i.rm.regmem = i.op[source].regs->reg_num;
6824 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6826 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6828 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6830 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6835 i.rm.reg = i.op[source].regs->reg_num;
6836 i.rm.regmem = i.op[dest].regs->reg_num;
6837 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6839 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6841 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6843 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6846 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6848 if (!i.types[0].bitfield.control
6849 && !i.types[1].bitfield.control)
6851 i.rex &= ~(REX_R | REX_B);
6852 add_prefix (LOCK_PREFIX_OPCODE);
6856 { /* If it's not 2 reg operands... */
6861 unsigned int fake_zero_displacement = 0;
6864 for (op = 0; op < i.operands; op++)
6865 if (operand_type_check (i.types[op], anymem))
6867 gas_assert (op < i.operands);
6869 if (i.tm.opcode_modifier.vecsib)
6871 if (i.index_reg->reg_num == RegEiz
6872 || i.index_reg->reg_num == RegRiz)
6875 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6878 i.sib.base = NO_BASE_REGISTER;
6879 i.sib.scale = i.log2_scale_factor;
6880 i.types[op].bitfield.disp8 = 0;
6881 i.types[op].bitfield.disp16 = 0;
6882 i.types[op].bitfield.disp64 = 0;
6883 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6885 /* Must be 32 bit */
6886 i.types[op].bitfield.disp32 = 1;
6887 i.types[op].bitfield.disp32s = 0;
6891 i.types[op].bitfield.disp32 = 0;
6892 i.types[op].bitfield.disp32s = 1;
6895 i.sib.index = i.index_reg->reg_num;
6896 if ((i.index_reg->reg_flags & RegRex) != 0)
6898 if ((i.index_reg->reg_flags & RegVRex) != 0)
6904 if (i.base_reg == 0)
6907 if (!i.disp_operands)
6908 fake_zero_displacement = 1;
6909 if (i.index_reg == 0)
6911 i386_operand_type newdisp;
6913 gas_assert (!i.tm.opcode_modifier.vecsib);
6914 /* Operand is just <disp> */
6915 if (flag_code == CODE_64BIT)
6917 /* 64bit mode overwrites the 32bit absolute
6918 addressing by RIP relative addressing and
6919 absolute addressing is encoded by one of the
6920 redundant SIB forms. */
6921 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6922 i.sib.base = NO_BASE_REGISTER;
6923 i.sib.index = NO_INDEX_REGISTER;
6924 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6926 else if ((flag_code == CODE_16BIT)
6927 ^ (i.prefix[ADDR_PREFIX] != 0))
6929 i.rm.regmem = NO_BASE_REGISTER_16;
6934 i.rm.regmem = NO_BASE_REGISTER;
6937 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6938 i.types[op] = operand_type_or (i.types[op], newdisp);
6940 else if (!i.tm.opcode_modifier.vecsib)
6942 /* !i.base_reg && i.index_reg */
6943 if (i.index_reg->reg_num == RegEiz
6944 || i.index_reg->reg_num == RegRiz)
6945 i.sib.index = NO_INDEX_REGISTER;
6947 i.sib.index = i.index_reg->reg_num;
6948 i.sib.base = NO_BASE_REGISTER;
6949 i.sib.scale = i.log2_scale_factor;
6950 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6951 i.types[op].bitfield.disp8 = 0;
6952 i.types[op].bitfield.disp16 = 0;
6953 i.types[op].bitfield.disp64 = 0;
6954 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6956 /* Must be 32 bit */
6957 i.types[op].bitfield.disp32 = 1;
6958 i.types[op].bitfield.disp32s = 0;
6962 i.types[op].bitfield.disp32 = 0;
6963 i.types[op].bitfield.disp32s = 1;
6965 if ((i.index_reg->reg_flags & RegRex) != 0)
6969 /* RIP addressing for 64bit mode. */
6970 else if (i.base_reg->reg_num == RegRip ||
6971 i.base_reg->reg_num == RegEip)
6973 gas_assert (!i.tm.opcode_modifier.vecsib);
6974 i.rm.regmem = NO_BASE_REGISTER;
6975 i.types[op].bitfield.disp8 = 0;
6976 i.types[op].bitfield.disp16 = 0;
6977 i.types[op].bitfield.disp32 = 0;
6978 i.types[op].bitfield.disp32s = 1;
6979 i.types[op].bitfield.disp64 = 0;
6980 i.flags[op] |= Operand_PCrel;
6981 if (! i.disp_operands)
6982 fake_zero_displacement = 1;
6984 else if (i.base_reg->reg_type.bitfield.word)
6986 gas_assert (!i.tm.opcode_modifier.vecsib);
6987 switch (i.base_reg->reg_num)
6990 if (i.index_reg == 0)
6992 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6993 i.rm.regmem = i.index_reg->reg_num - 6;
6997 if (i.index_reg == 0)
7000 if (operand_type_check (i.types[op], disp) == 0)
7002 /* fake (%bp) into 0(%bp) */
7003 i.types[op].bitfield.disp8 = 1;
7004 fake_zero_displacement = 1;
7007 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7008 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7010 default: /* (%si) -> 4 or (%di) -> 5 */
7011 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7013 i.rm.mode = mode_from_disp_size (i.types[op]);
7015 else /* i.base_reg and 32/64 bit mode */
7017 if (flag_code == CODE_64BIT
7018 && operand_type_check (i.types[op], disp))
7020 i.types[op].bitfield.disp16 = 0;
7021 i.types[op].bitfield.disp64 = 0;
7022 if (i.prefix[ADDR_PREFIX] == 0)
7024 i.types[op].bitfield.disp32 = 0;
7025 i.types[op].bitfield.disp32s = 1;
7029 i.types[op].bitfield.disp32 = 1;
7030 i.types[op].bitfield.disp32s = 0;
7034 if (!i.tm.opcode_modifier.vecsib)
7035 i.rm.regmem = i.base_reg->reg_num;
7036 if ((i.base_reg->reg_flags & RegRex) != 0)
7038 i.sib.base = i.base_reg->reg_num;
7039 /* x86-64 ignores REX prefix bit here to avoid decoder
7041 if (!(i.base_reg->reg_flags & RegRex)
7042 && (i.base_reg->reg_num == EBP_REG_NUM
7043 || i.base_reg->reg_num == ESP_REG_NUM))
7045 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7047 fake_zero_displacement = 1;
7048 i.types[op].bitfield.disp8 = 1;
7050 i.sib.scale = i.log2_scale_factor;
7051 if (i.index_reg == 0)
7053 gas_assert (!i.tm.opcode_modifier.vecsib);
7054 /* <disp>(%esp) becomes two byte modrm with no index
7055 register. We've already stored the code for esp
7056 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7057 Any base register besides %esp will not use the
7058 extra modrm byte. */
7059 i.sib.index = NO_INDEX_REGISTER;
7061 else if (!i.tm.opcode_modifier.vecsib)
7063 if (i.index_reg->reg_num == RegEiz
7064 || i.index_reg->reg_num == RegRiz)
7065 i.sib.index = NO_INDEX_REGISTER;
7067 i.sib.index = i.index_reg->reg_num;
7068 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7069 if ((i.index_reg->reg_flags & RegRex) != 0)
7074 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7075 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7079 if (!fake_zero_displacement
7083 fake_zero_displacement = 1;
7084 if (i.disp_encoding == disp_encoding_8bit)
7085 i.types[op].bitfield.disp8 = 1;
7087 i.types[op].bitfield.disp32 = 1;
7089 i.rm.mode = mode_from_disp_size (i.types[op]);
7093 if (fake_zero_displacement)
7095 /* Fakes a zero displacement assuming that i.types[op]
7096 holds the correct displacement size. */
7099 gas_assert (i.op[op].disps == 0);
7100 exp = &disp_expressions[i.disp_operands++];
7101 i.op[op].disps = exp;
7102 exp->X_op = O_constant;
7103 exp->X_add_number = 0;
7104 exp->X_add_symbol = (symbolS *) 0;
7105 exp->X_op_symbol = (symbolS *) 0;
7113 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7115 if (operand_type_check (i.types[0], imm))
7116 i.vex.register_specifier = NULL;
7119 /* VEX.vvvv encodes one of the sources when the first
7120 operand is not an immediate. */
7121 if (i.tm.opcode_modifier.vexw == VEXW0)
7122 i.vex.register_specifier = i.op[0].regs;
7124 i.vex.register_specifier = i.op[1].regs;
7127 /* Destination is a XMM register encoded in the ModRM.reg
7129 i.rm.reg = i.op[2].regs->reg_num;
7130 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7133 /* ModRM.rm and VEX.B encodes the other source. */
7134 if (!i.mem_operands)
7138 if (i.tm.opcode_modifier.vexw == VEXW0)
7139 i.rm.regmem = i.op[1].regs->reg_num;
7141 i.rm.regmem = i.op[0].regs->reg_num;
7143 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7147 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7149 i.vex.register_specifier = i.op[2].regs;
7150 if (!i.mem_operands)
7153 i.rm.regmem = i.op[1].regs->reg_num;
7154 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7158 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7159 (if any) based on i.tm.extension_opcode. Again, we must be
7160 careful to make sure that segment/control/debug/test/MMX
7161 registers are coded into the i.rm.reg field. */
7162 else if (i.reg_operands)
7165 unsigned int vex_reg = ~0;
7167 for (op = 0; op < i.operands; op++)
7168 if (i.types[op].bitfield.reg
7169 || i.types[op].bitfield.regmmx
7170 || i.types[op].bitfield.regsimd
7171 || i.types[op].bitfield.regbnd
7172 || i.types[op].bitfield.regmask
7173 || i.types[op].bitfield.sreg2
7174 || i.types[op].bitfield.sreg3
7175 || i.types[op].bitfield.control
7176 || i.types[op].bitfield.debug
7177 || i.types[op].bitfield.test)
7182 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7184 /* For instructions with VexNDS, the register-only
7185 source operand is encoded in VEX prefix. */
7186 gas_assert (mem != (unsigned int) ~0);
7191 gas_assert (op < i.operands);
7195 /* Check register-only source operand when two source
7196 operands are swapped. */
7197 if (!i.tm.operand_types[op].bitfield.baseindex
7198 && i.tm.operand_types[op + 1].bitfield.baseindex)
7202 gas_assert (mem == (vex_reg + 1)
7203 && op < i.operands);
7208 gas_assert (vex_reg < i.operands);
7212 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7214 /* For instructions with VexNDD, the register destination
7215 is encoded in VEX prefix. */
7216 if (i.mem_operands == 0)
7218 /* There is no memory operand. */
7219 gas_assert ((op + 2) == i.operands);
7224 /* There are only 2 non-immediate operands. */
7225 gas_assert (op < i.imm_operands + 2
7226 && i.operands == i.imm_operands + 2);
7227 vex_reg = i.imm_operands + 1;
7231 gas_assert (op < i.operands);
7233 if (vex_reg != (unsigned int) ~0)
7235 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7237 if ((!type->bitfield.reg
7238 || (!type->bitfield.dword && !type->bitfield.qword))
7239 && !type->bitfield.regsimd
7240 && !operand_type_equal (type, ®mask))
7243 i.vex.register_specifier = i.op[vex_reg].regs;
7246 /* Don't set OP operand twice. */
7249 /* If there is an extension opcode to put here, the
7250 register number must be put into the regmem field. */
7251 if (i.tm.extension_opcode != None)
7253 i.rm.regmem = i.op[op].regs->reg_num;
7254 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7256 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7261 i.rm.reg = i.op[op].regs->reg_num;
7262 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7264 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7269 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7270 must set it to 3 to indicate this is a register operand
7271 in the regmem field. */
7272 if (!i.mem_operands)
7276 /* Fill in i.rm.reg field with extension opcode (if any). */
7277 if (i.tm.extension_opcode != None)
7278 i.rm.reg = i.tm.extension_opcode;
7284 output_branch (void)
7290 relax_substateT subtype;
7294 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7295 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7298 if (i.prefix[DATA_PREFIX] != 0)
7304 /* Pentium4 branch hints. */
7305 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7306 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7311 if (i.prefix[REX_PREFIX] != 0)
7317 /* BND prefixed jump. */
7318 if (i.prefix[BND_PREFIX] != 0)
7320 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7324 if (i.prefixes != 0 && !intel_syntax)
7325 as_warn (_("skipping prefixes on this instruction"));
7327 /* It's always a symbol; End frag & setup for relax.
7328 Make sure there is enough room in this frag for the largest
7329 instruction we may generate in md_convert_frag. This is 2
7330 bytes for the opcode and room for the prefix and largest
7332 frag_grow (prefix + 2 + 4);
7333 /* Prefix and 1 opcode byte go in fr_fix. */
7334 p = frag_more (prefix + 1);
7335 if (i.prefix[DATA_PREFIX] != 0)
7336 *p++ = DATA_PREFIX_OPCODE;
7337 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7338 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7339 *p++ = i.prefix[SEG_PREFIX];
7340 if (i.prefix[REX_PREFIX] != 0)
7341 *p++ = i.prefix[REX_PREFIX];
7342 *p = i.tm.base_opcode;
7344 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7345 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7346 else if (cpu_arch_flags.bitfield.cpui386)
7347 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7349 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7352 sym = i.op[0].disps->X_add_symbol;
7353 off = i.op[0].disps->X_add_number;
7355 if (i.op[0].disps->X_op != O_constant
7356 && i.op[0].disps->X_op != O_symbol)
7358 /* Handle complex expressions. */
7359 sym = make_expr_symbol (i.op[0].disps);
7363 /* 1 possible extra opcode + 4 byte displacement go in var part.
7364 Pass reloc in fr_var. */
7365 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7369 /* Return TRUE iff PLT32 relocation should be used for branching to
7373 need_plt32_p (symbolS *s)
7375 /* PLT32 relocation is ELF only. */
7379 /* Since there is no need to prepare for PLT branch on x86-64, we
7380 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7381 be used as a marker for 32-bit PC-relative branches. */
7385 /* Weak or undefined symbol need PLT32 relocation. */
7386 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7389 /* Non-global symbol doesn't need PLT32 relocation. */
7390 if (! S_IS_EXTERNAL (s))
7393 /* Other global symbols need PLT32 relocation. NB: Symbol with
7394 non-default visibilities are treated as normal global symbol
7395 so that PLT32 relocation can be used as a marker for 32-bit
7396 PC-relative branches. It is useful for linker relaxation. */
7407 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7409 if (i.tm.opcode_modifier.jumpbyte)
7411 /* This is a loop or jecxz type instruction. */
7413 if (i.prefix[ADDR_PREFIX] != 0)
7415 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7418 /* Pentium4 branch hints. */
7419 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7420 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7422 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7431 if (flag_code == CODE_16BIT)
7434 if (i.prefix[DATA_PREFIX] != 0)
7436 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7446 if (i.prefix[REX_PREFIX] != 0)
7448 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7452 /* BND prefixed jump. */
7453 if (i.prefix[BND_PREFIX] != 0)
7455 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7459 if (i.prefixes != 0 && !intel_syntax)
7460 as_warn (_("skipping prefixes on this instruction"));
7462 p = frag_more (i.tm.opcode_length + size);
7463 switch (i.tm.opcode_length)
7466 *p++ = i.tm.base_opcode >> 8;
7469 *p++ = i.tm.base_opcode;
7475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7477 && jump_reloc == NO_RELOC
7478 && need_plt32_p (i.op[0].disps->X_add_symbol))
7479 jump_reloc = BFD_RELOC_X86_64_PLT32;
7482 jump_reloc = reloc (size, 1, 1, jump_reloc);
7484 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7485 i.op[0].disps, 1, jump_reloc);
7487 /* All jumps handled here are signed, but don't use a signed limit
7488 check for 32 and 16 bit jumps as we want to allow wrap around at
7489 4G and 64k respectively. */
7491 fixP->fx_signed = 1;
7495 output_interseg_jump (void)
7503 if (flag_code == CODE_16BIT)
7507 if (i.prefix[DATA_PREFIX] != 0)
7513 if (i.prefix[REX_PREFIX] != 0)
7523 if (i.prefixes != 0 && !intel_syntax)
7524 as_warn (_("skipping prefixes on this instruction"));
7526 /* 1 opcode; 2 segment; offset */
7527 p = frag_more (prefix + 1 + 2 + size);
7529 if (i.prefix[DATA_PREFIX] != 0)
7530 *p++ = DATA_PREFIX_OPCODE;
7532 if (i.prefix[REX_PREFIX] != 0)
7533 *p++ = i.prefix[REX_PREFIX];
7535 *p++ = i.tm.base_opcode;
7536 if (i.op[1].imms->X_op == O_constant)
7538 offsetT n = i.op[1].imms->X_add_number;
7541 && !fits_in_unsigned_word (n)
7542 && !fits_in_signed_word (n))
7544 as_bad (_("16-bit jump out of range"));
7547 md_number_to_chars (p, n, size);
7550 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7551 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7552 if (i.op[0].imms->X_op != O_constant)
7553 as_bad (_("can't handle non absolute segment in `%s'"),
7555 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7561 fragS *insn_start_frag;
7562 offsetT insn_start_off;
7564 /* Tie dwarf2 debug info to the address at the start of the insn.
7565 We can't do this after the insn has been output as the current
7566 frag may have been closed off. eg. by frag_var. */
7567 dwarf2_emit_insn (0);
7569 insn_start_frag = frag_now;
7570 insn_start_off = frag_now_fix ();
7573 if (i.tm.opcode_modifier.jump)
7575 else if (i.tm.opcode_modifier.jumpbyte
7576 || i.tm.opcode_modifier.jumpdword)
7578 else if (i.tm.opcode_modifier.jumpintersegment)
7579 output_interseg_jump ();
7582 /* Output normal instructions here. */
7586 unsigned int prefix;
7589 && i.tm.base_opcode == 0xfae
7591 && i.imm_operands == 1
7592 && (i.op[0].imms->X_add_number == 0xe8
7593 || i.op[0].imms->X_add_number == 0xf0
7594 || i.op[0].imms->X_add_number == 0xf8))
7596 /* Encode lfence, mfence, and sfence as
7597 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7598 offsetT val = 0x240483f0ULL;
7600 md_number_to_chars (p, val, 5);
7604 /* Some processors fail on LOCK prefix. This options makes
7605 assembler ignore LOCK prefix and serves as a workaround. */
7606 if (omit_lock_prefix)
7608 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7610 i.prefix[LOCK_PREFIX] = 0;
7613 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7614 don't need the explicit prefix. */
7615 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7617 switch (i.tm.opcode_length)
7620 if (i.tm.base_opcode & 0xff000000)
7622 prefix = (i.tm.base_opcode >> 24) & 0xff;
7627 if ((i.tm.base_opcode & 0xff0000) != 0)
7629 prefix = (i.tm.base_opcode >> 16) & 0xff;
7630 if (i.tm.cpu_flags.bitfield.cpupadlock)
7633 if (prefix != REPE_PREFIX_OPCODE
7634 || (i.prefix[REP_PREFIX]
7635 != REPE_PREFIX_OPCODE))
7636 add_prefix (prefix);
7639 add_prefix (prefix);
7645 /* Check for pseudo prefixes. */
7646 as_bad_where (insn_start_frag->fr_file,
7647 insn_start_frag->fr_line,
7648 _("pseudo prefix without instruction"));
7654 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7655 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7656 R_X86_64_GOTTPOFF relocation so that linker can safely
7657 perform IE->LE optimization. */
7658 if (x86_elf_abi == X86_64_X32_ABI
7660 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7661 && i.prefix[REX_PREFIX] == 0)
7662 add_prefix (REX_OPCODE);
7665 /* The prefix bytes. */
7666 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7668 FRAG_APPEND_1_CHAR (*q);
7672 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7677 /* REX byte is encoded in VEX prefix. */
7681 FRAG_APPEND_1_CHAR (*q);
7684 /* There should be no other prefixes for instructions
7689 /* For EVEX instructions i.vrex should become 0 after
7690 build_evex_prefix. For VEX instructions upper 16 registers
7691 aren't available, so VREX should be 0. */
7694 /* Now the VEX prefix. */
7695 p = frag_more (i.vex.length);
7696 for (j = 0; j < i.vex.length; j++)
7697 p[j] = i.vex.bytes[j];
7700 /* Now the opcode; be careful about word order here! */
7701 if (i.tm.opcode_length == 1)
7703 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7707 switch (i.tm.opcode_length)
7711 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7712 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7716 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7726 /* Put out high byte first: can't use md_number_to_chars! */
7727 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7728 *p = i.tm.base_opcode & 0xff;
7731 /* Now the modrm byte and sib byte (if present). */
7732 if (i.tm.opcode_modifier.modrm)
7734 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7737 /* If i.rm.regmem == ESP (4)
7738 && i.rm.mode != (Register mode)
7740 ==> need second modrm byte. */
7741 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7743 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7744 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7746 | i.sib.scale << 6));
7749 if (i.disp_operands)
7750 output_disp (insn_start_frag, insn_start_off);
7753 output_imm (insn_start_frag, insn_start_off);
7759 pi ("" /*line*/, &i);
7761 #endif /* DEBUG386 */
7764 /* Return the size of the displacement operand N. */
7767 disp_size (unsigned int n)
7771 if (i.types[n].bitfield.disp64)
7773 else if (i.types[n].bitfield.disp8)
7775 else if (i.types[n].bitfield.disp16)
7780 /* Return the size of the immediate operand N. */
7783 imm_size (unsigned int n)
7786 if (i.types[n].bitfield.imm64)
7788 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7790 else if (i.types[n].bitfield.imm16)
7796 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7801 for (n = 0; n < i.operands; n++)
7803 if (operand_type_check (i.types[n], disp))
7805 if (i.op[n].disps->X_op == O_constant)
7807 int size = disp_size (n);
7808 offsetT val = i.op[n].disps->X_add_number;
7810 val = offset_in_range (val >> i.memshift, size);
7811 p = frag_more (size);
7812 md_number_to_chars (p, val, size);
7816 enum bfd_reloc_code_real reloc_type;
7817 int size = disp_size (n);
7818 int sign = i.types[n].bitfield.disp32s;
7819 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7822 /* We can't have 8 bit displacement here. */
7823 gas_assert (!i.types[n].bitfield.disp8);
7825 /* The PC relative address is computed relative
7826 to the instruction boundary, so in case immediate
7827 fields follows, we need to adjust the value. */
7828 if (pcrel && i.imm_operands)
7833 for (n1 = 0; n1 < i.operands; n1++)
7834 if (operand_type_check (i.types[n1], imm))
7836 /* Only one immediate is allowed for PC
7837 relative address. */
7838 gas_assert (sz == 0);
7840 i.op[n].disps->X_add_number -= sz;
7842 /* We should find the immediate. */
7843 gas_assert (sz != 0);
7846 p = frag_more (size);
7847 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7849 && GOT_symbol == i.op[n].disps->X_add_symbol
7850 && (((reloc_type == BFD_RELOC_32
7851 || reloc_type == BFD_RELOC_X86_64_32S
7852 || (reloc_type == BFD_RELOC_64
7854 && (i.op[n].disps->X_op == O_symbol
7855 || (i.op[n].disps->X_op == O_add
7856 && ((symbol_get_value_expression
7857 (i.op[n].disps->X_op_symbol)->X_op)
7859 || reloc_type == BFD_RELOC_32_PCREL))
7863 if (insn_start_frag == frag_now)
7864 add = (p - frag_now->fr_literal) - insn_start_off;
7869 add = insn_start_frag->fr_fix - insn_start_off;
7870 for (fr = insn_start_frag->fr_next;
7871 fr && fr != frag_now; fr = fr->fr_next)
7873 add += p - frag_now->fr_literal;
7878 reloc_type = BFD_RELOC_386_GOTPC;
7879 i.op[n].imms->X_add_number += add;
7881 else if (reloc_type == BFD_RELOC_64)
7882 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7884 /* Don't do the adjustment for x86-64, as there
7885 the pcrel addressing is relative to the _next_
7886 insn, and that is taken care of in other code. */
7887 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7889 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7890 size, i.op[n].disps, pcrel,
7892 /* Check for "call/jmp *mem", "mov mem, %reg",
7893 "test %reg, mem" and "binop mem, %reg" where binop
7894 is one of adc, add, and, cmp, or, sbb, sub, xor
7895 instructions. Always generate R_386_GOT32X for
7896 "sym*GOT" operand in 32-bit mode. */
7897 if ((generate_relax_relocations
7900 && i.rm.regmem == 5))
7902 || (i.rm.mode == 0 && i.rm.regmem == 5))
7903 && ((i.operands == 1
7904 && i.tm.base_opcode == 0xff
7905 && (i.rm.reg == 2 || i.rm.reg == 4))
7907 && (i.tm.base_opcode == 0x8b
7908 || i.tm.base_opcode == 0x85
7909 || (i.tm.base_opcode & 0xc7) == 0x03))))
7913 fixP->fx_tcbit = i.rex != 0;
7915 && (i.base_reg->reg_num == RegRip
7916 || i.base_reg->reg_num == RegEip))
7917 fixP->fx_tcbit2 = 1;
7920 fixP->fx_tcbit2 = 1;
7928 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7933 for (n = 0; n < i.operands; n++)
7935 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7936 if (i.rounding && (int) n == i.rounding->operand)
7939 if (operand_type_check (i.types[n], imm))
7941 if (i.op[n].imms->X_op == O_constant)
7943 int size = imm_size (n);
7946 val = offset_in_range (i.op[n].imms->X_add_number,
7948 p = frag_more (size);
7949 md_number_to_chars (p, val, size);
7953 /* Not absolute_section.
7954 Need a 32-bit fixup (don't support 8bit
7955 non-absolute imms). Try to support other
7957 enum bfd_reloc_code_real reloc_type;
7958 int size = imm_size (n);
7961 if (i.types[n].bitfield.imm32s
7962 && (i.suffix == QWORD_MNEM_SUFFIX
7963 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7968 p = frag_more (size);
7969 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7971 /* This is tough to explain. We end up with this one if we
7972 * have operands that look like
7973 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7974 * obtain the absolute address of the GOT, and it is strongly
7975 * preferable from a performance point of view to avoid using
7976 * a runtime relocation for this. The actual sequence of
7977 * instructions often look something like:
7982 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7984 * The call and pop essentially return the absolute address
7985 * of the label .L66 and store it in %ebx. The linker itself
7986 * will ultimately change the first operand of the addl so
7987 * that %ebx points to the GOT, but to keep things simple, the
7988 * .o file must have this operand set so that it generates not
7989 * the absolute address of .L66, but the absolute address of
7990 * itself. This allows the linker itself simply treat a GOTPC
7991 * relocation as asking for a pcrel offset to the GOT to be
7992 * added in, and the addend of the relocation is stored in the
7993 * operand field for the instruction itself.
7995 * Our job here is to fix the operand so that it would add
7996 * the correct offset so that %ebx would point to itself. The
7997 * thing that is tricky is that .-.L66 will point to the
7998 * beginning of the instruction, so we need to further modify
7999 * the operand so that it will point to itself. There are
8000 * other cases where you have something like:
8002 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8004 * and here no correction would be required. Internally in
8005 * the assembler we treat operands of this form as not being
8006 * pcrel since the '.' is explicitly mentioned, and I wonder
8007 * whether it would simplify matters to do it this way. Who
8008 * knows. In earlier versions of the PIC patches, the
8009 * pcrel_adjust field was used to store the correction, but
8010 * since the expression is not pcrel, I felt it would be
8011 * confusing to do it this way. */
8013 if ((reloc_type == BFD_RELOC_32
8014 || reloc_type == BFD_RELOC_X86_64_32S
8015 || reloc_type == BFD_RELOC_64)
8017 && GOT_symbol == i.op[n].imms->X_add_symbol
8018 && (i.op[n].imms->X_op == O_symbol
8019 || (i.op[n].imms->X_op == O_add
8020 && ((symbol_get_value_expression
8021 (i.op[n].imms->X_op_symbol)->X_op)
8026 if (insn_start_frag == frag_now)
8027 add = (p - frag_now->fr_literal) - insn_start_off;
8032 add = insn_start_frag->fr_fix - insn_start_off;
8033 for (fr = insn_start_frag->fr_next;
8034 fr && fr != frag_now; fr = fr->fr_next)
8036 add += p - frag_now->fr_literal;
8040 reloc_type = BFD_RELOC_386_GOTPC;
8042 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8044 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8045 i.op[n].imms->X_add_number += add;
8047 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8048 i.op[n].imms, 0, reloc_type);
8054 /* x86_cons_fix_new is called via the expression parsing code when a
8055 reloc is needed. We use this hook to get the correct .got reloc. */
8056 static int cons_sign = -1;
8059 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8060 expressionS *exp, bfd_reloc_code_real_type r)
8062 r = reloc (len, 0, cons_sign, r);
8065 if (exp->X_op == O_secrel)
8067 exp->X_op = O_symbol;
8068 r = BFD_RELOC_32_SECREL;
8072 fix_new_exp (frag, off, len, exp, 0, r);
8075 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8076 purpose of the `.dc.a' internal pseudo-op. */
8079 x86_address_bytes (void)
8081 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8083 return stdoutput->arch_info->bits_per_address / 8;
8086 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8088 # define lex_got(reloc, adjust, types) NULL
8090 /* Parse operands of the form
8091 <symbol>@GOTOFF+<nnn>
8092 and similar .plt or .got references.
8094 If we find one, set up the correct relocation in RELOC and copy the
8095 input string, minus the `@GOTOFF' into a malloc'd buffer for
8096 parsing by the calling routine. Return this buffer, and if ADJUST
8097 is non-null set it to the length of the string we removed from the
8098 input line. Otherwise return NULL. */
8100 lex_got (enum bfd_reloc_code_real *rel,
8102 i386_operand_type *types)
8104 /* Some of the relocations depend on the size of what field is to
8105 be relocated. But in our callers i386_immediate and i386_displacement
8106 we don't yet know the operand size (this will be set by insn
8107 matching). Hence we record the word32 relocation here,
8108 and adjust the reloc according to the real size in reloc(). */
8109 static const struct {
8112 const enum bfd_reloc_code_real rel[2];
8113 const i386_operand_type types64;
8115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8116 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8118 OPERAND_TYPE_IMM32_64 },
8120 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8121 BFD_RELOC_X86_64_PLTOFF64 },
8122 OPERAND_TYPE_IMM64 },
8123 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8124 BFD_RELOC_X86_64_PLT32 },
8125 OPERAND_TYPE_IMM32_32S_DISP32 },
8126 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8127 BFD_RELOC_X86_64_GOTPLT64 },
8128 OPERAND_TYPE_IMM64_DISP64 },
8129 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8130 BFD_RELOC_X86_64_GOTOFF64 },
8131 OPERAND_TYPE_IMM64_DISP64 },
8132 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8133 BFD_RELOC_X86_64_GOTPCREL },
8134 OPERAND_TYPE_IMM32_32S_DISP32 },
8135 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8136 BFD_RELOC_X86_64_TLSGD },
8137 OPERAND_TYPE_IMM32_32S_DISP32 },
8138 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8139 _dummy_first_bfd_reloc_code_real },
8140 OPERAND_TYPE_NONE },
8141 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8142 BFD_RELOC_X86_64_TLSLD },
8143 OPERAND_TYPE_IMM32_32S_DISP32 },
8144 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8145 BFD_RELOC_X86_64_GOTTPOFF },
8146 OPERAND_TYPE_IMM32_32S_DISP32 },
8147 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8148 BFD_RELOC_X86_64_TPOFF32 },
8149 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8150 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8151 _dummy_first_bfd_reloc_code_real },
8152 OPERAND_TYPE_NONE },
8153 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8154 BFD_RELOC_X86_64_DTPOFF32 },
8155 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8156 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8157 _dummy_first_bfd_reloc_code_real },
8158 OPERAND_TYPE_NONE },
8159 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8160 _dummy_first_bfd_reloc_code_real },
8161 OPERAND_TYPE_NONE },
8162 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8163 BFD_RELOC_X86_64_GOT32 },
8164 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8165 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8166 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8167 OPERAND_TYPE_IMM32_32S_DISP32 },
8168 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8169 BFD_RELOC_X86_64_TLSDESC_CALL },
8170 OPERAND_TYPE_IMM32_32S_DISP32 },
8175 #if defined (OBJ_MAYBE_ELF)
8180 for (cp = input_line_pointer; *cp != '@'; cp++)
8181 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8184 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8186 int len = gotrel[j].len;
8187 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8189 if (gotrel[j].rel[object_64bit] != 0)
8192 char *tmpbuf, *past_reloc;
8194 *rel = gotrel[j].rel[object_64bit];
8198 if (flag_code != CODE_64BIT)
8200 types->bitfield.imm32 = 1;
8201 types->bitfield.disp32 = 1;
8204 *types = gotrel[j].types64;
8207 if (j != 0 && GOT_symbol == NULL)
8208 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8210 /* The length of the first part of our input line. */
8211 first = cp - input_line_pointer;
8213 /* The second part goes from after the reloc token until
8214 (and including) an end_of_line char or comma. */
8215 past_reloc = cp + 1 + len;
8217 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8219 second = cp + 1 - past_reloc;
8221 /* Allocate and copy string. The trailing NUL shouldn't
8222 be necessary, but be safe. */
8223 tmpbuf = XNEWVEC (char, first + second + 2);
8224 memcpy (tmpbuf, input_line_pointer, first);
8225 if (second != 0 && *past_reloc != ' ')
8226 /* Replace the relocation token with ' ', so that
8227 errors like foo@GOTOFF1 will be detected. */
8228 tmpbuf[first++] = ' ';
8230 /* Increment length by 1 if the relocation token is
8235 memcpy (tmpbuf + first, past_reloc, second);
8236 tmpbuf[first + second] = '\0';
8240 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8241 gotrel[j].str, 1 << (5 + object_64bit));
8246 /* Might be a symbol version string. Don't as_bad here. */
8255 /* Parse operands of the form
8256 <symbol>@SECREL32+<nnn>
8258 If we find one, set up the correct relocation in RELOC and copy the
8259 input string, minus the `@SECREL32' into a malloc'd buffer for
8260 parsing by the calling routine. Return this buffer, and if ADJUST
8261 is non-null set it to the length of the string we removed from the
8262 input line. Otherwise return NULL.
8264 This function is copied from the ELF version above adjusted for PE targets. */
8267 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8268 int *adjust ATTRIBUTE_UNUSED,
8269 i386_operand_type *types)
8275 const enum bfd_reloc_code_real rel[2];
8276 const i386_operand_type types64;
8280 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8281 BFD_RELOC_32_SECREL },
8282 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8288 for (cp = input_line_pointer; *cp != '@'; cp++)
8289 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8292 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8294 int len = gotrel[j].len;
8296 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8298 if (gotrel[j].rel[object_64bit] != 0)
8301 char *tmpbuf, *past_reloc;
8303 *rel = gotrel[j].rel[object_64bit];
8309 if (flag_code != CODE_64BIT)
8311 types->bitfield.imm32 = 1;
8312 types->bitfield.disp32 = 1;
8315 *types = gotrel[j].types64;
8318 /* The length of the first part of our input line. */
8319 first = cp - input_line_pointer;
8321 /* The second part goes from after the reloc token until
8322 (and including) an end_of_line char or comma. */
8323 past_reloc = cp + 1 + len;
8325 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8327 second = cp + 1 - past_reloc;
8329 /* Allocate and copy string. The trailing NUL shouldn't
8330 be necessary, but be safe. */
8331 tmpbuf = XNEWVEC (char, first + second + 2);
8332 memcpy (tmpbuf, input_line_pointer, first);
8333 if (second != 0 && *past_reloc != ' ')
8334 /* Replace the relocation token with ' ', so that
8335 errors like foo@SECLREL321 will be detected. */
8336 tmpbuf[first++] = ' ';
8337 memcpy (tmpbuf + first, past_reloc, second);
8338 tmpbuf[first + second] = '\0';
8342 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8343 gotrel[j].str, 1 << (5 + object_64bit));
8348 /* Might be a symbol version string. Don't as_bad here. */
8354 bfd_reloc_code_real_type
8355 x86_cons (expressionS *exp, int size)
8357 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8359 intel_syntax = -intel_syntax;
8362 if (size == 4 || (object_64bit && size == 8))
8364 /* Handle @GOTOFF and the like in an expression. */
8366 char *gotfree_input_line;
8369 save = input_line_pointer;
8370 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8371 if (gotfree_input_line)
8372 input_line_pointer = gotfree_input_line;
8376 if (gotfree_input_line)
8378 /* expression () has merrily parsed up to the end of line,
8379 or a comma - in the wrong buffer. Transfer how far
8380 input_line_pointer has moved to the right buffer. */
8381 input_line_pointer = (save
8382 + (input_line_pointer - gotfree_input_line)
8384 free (gotfree_input_line);
8385 if (exp->X_op == O_constant
8386 || exp->X_op == O_absent
8387 || exp->X_op == O_illegal
8388 || exp->X_op == O_register
8389 || exp->X_op == O_big)
8391 char c = *input_line_pointer;
8392 *input_line_pointer = 0;
8393 as_bad (_("missing or invalid expression `%s'"), save);
8394 *input_line_pointer = c;
8401 intel_syntax = -intel_syntax;
8404 i386_intel_simplify (exp);
8410 signed_cons (int size)
8412 if (flag_code == CODE_64BIT)
8420 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8427 if (exp.X_op == O_symbol)
8428 exp.X_op = O_secrel;
8430 emit_expr (&exp, 4);
8432 while (*input_line_pointer++ == ',');
8434 input_line_pointer--;
8435 demand_empty_rest_of_line ();
8439 /* Handle Vector operations. */
8442 check_VecOperations (char *op_string, char *op_end)
8444 const reg_entry *mask;
8449 && (op_end == NULL || op_string < op_end))
8452 if (*op_string == '{')
8456 /* Check broadcasts. */
8457 if (strncmp (op_string, "1to", 3) == 0)
8462 goto duplicated_vec_op;
8465 if (*op_string == '8')
8467 else if (*op_string == '4')
8469 else if (*op_string == '2')
8471 else if (*op_string == '1'
8472 && *(op_string+1) == '6')
8479 as_bad (_("Unsupported broadcast: `%s'"), saved);
8484 broadcast_op.type = bcst_type;
8485 broadcast_op.operand = this_operand;
8486 i.broadcast = &broadcast_op;
8488 /* Check masking operation. */
8489 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8491 /* k0 can't be used for write mask. */
8492 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8494 as_bad (_("`%s%s' can't be used for write mask"),
8495 register_prefix, mask->reg_name);
8501 mask_op.mask = mask;
8502 mask_op.zeroing = 0;
8503 mask_op.operand = this_operand;
8509 goto duplicated_vec_op;
8511 i.mask->mask = mask;
8513 /* Only "{z}" is allowed here. No need to check
8514 zeroing mask explicitly. */
8515 if (i.mask->operand != this_operand)
8517 as_bad (_("invalid write mask `%s'"), saved);
8524 /* Check zeroing-flag for masking operation. */
8525 else if (*op_string == 'z')
8529 mask_op.mask = NULL;
8530 mask_op.zeroing = 1;
8531 mask_op.operand = this_operand;
8536 if (i.mask->zeroing)
8539 as_bad (_("duplicated `%s'"), saved);
8543 i.mask->zeroing = 1;
8545 /* Only "{%k}" is allowed here. No need to check mask
8546 register explicitly. */
8547 if (i.mask->operand != this_operand)
8549 as_bad (_("invalid zeroing-masking `%s'"),
8558 goto unknown_vec_op;
8560 if (*op_string != '}')
8562 as_bad (_("missing `}' in `%s'"), saved);
8567 /* Strip whitespace since the addition of pseudo prefixes
8568 changed how the scrubber treats '{'. */
8569 if (is_space_char (*op_string))
8575 /* We don't know this one. */
8576 as_bad (_("unknown vector operation: `%s'"), saved);
8580 if (i.mask && i.mask->zeroing && !i.mask->mask)
8582 as_bad (_("zeroing-masking only allowed with write mask"));
8590 i386_immediate (char *imm_start)
8592 char *save_input_line_pointer;
8593 char *gotfree_input_line;
8596 i386_operand_type types;
8598 operand_type_set (&types, ~0);
8600 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8602 as_bad (_("at most %d immediate operands are allowed"),
8603 MAX_IMMEDIATE_OPERANDS);
8607 exp = &im_expressions[i.imm_operands++];
8608 i.op[this_operand].imms = exp;
8610 if (is_space_char (*imm_start))
8613 save_input_line_pointer = input_line_pointer;
8614 input_line_pointer = imm_start;
8616 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8617 if (gotfree_input_line)
8618 input_line_pointer = gotfree_input_line;
8620 exp_seg = expression (exp);
8624 /* Handle vector operations. */
8625 if (*input_line_pointer == '{')
8627 input_line_pointer = check_VecOperations (input_line_pointer,
8629 if (input_line_pointer == NULL)
8633 if (*input_line_pointer)
8634 as_bad (_("junk `%s' after expression"), input_line_pointer);
8636 input_line_pointer = save_input_line_pointer;
8637 if (gotfree_input_line)
8639 free (gotfree_input_line);
8641 if (exp->X_op == O_constant || exp->X_op == O_register)
8642 exp->X_op = O_illegal;
8645 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8649 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8650 i386_operand_type types, const char *imm_start)
8652 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8655 as_bad (_("missing or invalid immediate expression `%s'"),
8659 else if (exp->X_op == O_constant)
8661 /* Size it properly later. */
8662 i.types[this_operand].bitfield.imm64 = 1;
8663 /* If not 64bit, sign extend val. */
8664 if (flag_code != CODE_64BIT
8665 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8667 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8669 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8670 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8671 && exp_seg != absolute_section
8672 && exp_seg != text_section
8673 && exp_seg != data_section
8674 && exp_seg != bss_section
8675 && exp_seg != undefined_section
8676 && !bfd_is_com_section (exp_seg))
8678 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8682 else if (!intel_syntax && exp_seg == reg_section)
8685 as_bad (_("illegal immediate register operand %s"), imm_start);
8690 /* This is an address. The size of the address will be
8691 determined later, depending on destination register,
8692 suffix, or the default for the section. */
8693 i.types[this_operand].bitfield.imm8 = 1;
8694 i.types[this_operand].bitfield.imm16 = 1;
8695 i.types[this_operand].bitfield.imm32 = 1;
8696 i.types[this_operand].bitfield.imm32s = 1;
8697 i.types[this_operand].bitfield.imm64 = 1;
8698 i.types[this_operand] = operand_type_and (i.types[this_operand],
8706 i386_scale (char *scale)
8709 char *save = input_line_pointer;
8711 input_line_pointer = scale;
8712 val = get_absolute_expression ();
8717 i.log2_scale_factor = 0;
8720 i.log2_scale_factor = 1;
8723 i.log2_scale_factor = 2;
8726 i.log2_scale_factor = 3;
8730 char sep = *input_line_pointer;
8732 *input_line_pointer = '\0';
8733 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8735 *input_line_pointer = sep;
8736 input_line_pointer = save;
8740 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8742 as_warn (_("scale factor of %d without an index register"),
8743 1 << i.log2_scale_factor);
8744 i.log2_scale_factor = 0;
8746 scale = input_line_pointer;
8747 input_line_pointer = save;
8752 i386_displacement (char *disp_start, char *disp_end)
8756 char *save_input_line_pointer;
8757 char *gotfree_input_line;
8759 i386_operand_type bigdisp, types = anydisp;
8762 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8764 as_bad (_("at most %d displacement operands are allowed"),
8765 MAX_MEMORY_OPERANDS);
8769 operand_type_set (&bigdisp, 0);
8770 if ((i.types[this_operand].bitfield.jumpabsolute)
8771 || (!current_templates->start->opcode_modifier.jump
8772 && !current_templates->start->opcode_modifier.jumpdword))
8774 bigdisp.bitfield.disp32 = 1;
8775 override = (i.prefix[ADDR_PREFIX] != 0);
8776 if (flag_code == CODE_64BIT)
8780 bigdisp.bitfield.disp32s = 1;
8781 bigdisp.bitfield.disp64 = 1;
8784 else if ((flag_code == CODE_16BIT) ^ override)
8786 bigdisp.bitfield.disp32 = 0;
8787 bigdisp.bitfield.disp16 = 1;
8792 /* For PC-relative branches, the width of the displacement
8793 is dependent upon data size, not address size. */
8794 override = (i.prefix[DATA_PREFIX] != 0);
8795 if (flag_code == CODE_64BIT)
8797 if (override || i.suffix == WORD_MNEM_SUFFIX)
8798 bigdisp.bitfield.disp16 = 1;
8801 bigdisp.bitfield.disp32 = 1;
8802 bigdisp.bitfield.disp32s = 1;
8808 override = (i.suffix == (flag_code != CODE_16BIT
8810 : LONG_MNEM_SUFFIX));
8811 bigdisp.bitfield.disp32 = 1;
8812 if ((flag_code == CODE_16BIT) ^ override)
8814 bigdisp.bitfield.disp32 = 0;
8815 bigdisp.bitfield.disp16 = 1;
8819 i.types[this_operand] = operand_type_or (i.types[this_operand],
8822 exp = &disp_expressions[i.disp_operands];
8823 i.op[this_operand].disps = exp;
8825 save_input_line_pointer = input_line_pointer;
8826 input_line_pointer = disp_start;
8827 END_STRING_AND_SAVE (disp_end);
8829 #ifndef GCC_ASM_O_HACK
8830 #define GCC_ASM_O_HACK 0
8833 END_STRING_AND_SAVE (disp_end + 1);
8834 if (i.types[this_operand].bitfield.baseIndex
8835 && displacement_string_end[-1] == '+')
8837 /* This hack is to avoid a warning when using the "o"
8838 constraint within gcc asm statements.
8841 #define _set_tssldt_desc(n,addr,limit,type) \
8842 __asm__ __volatile__ ( \
8844 "movw %w1,2+%0\n\t" \
8846 "movb %b1,4+%0\n\t" \
8847 "movb %4,5+%0\n\t" \
8848 "movb $0,6+%0\n\t" \
8849 "movb %h1,7+%0\n\t" \
8851 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8853 This works great except that the output assembler ends
8854 up looking a bit weird if it turns out that there is
8855 no offset. You end up producing code that looks like:
8868 So here we provide the missing zero. */
8870 *displacement_string_end = '0';
8873 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8874 if (gotfree_input_line)
8875 input_line_pointer = gotfree_input_line;
8877 exp_seg = expression (exp);
8880 if (*input_line_pointer)
8881 as_bad (_("junk `%s' after expression"), input_line_pointer);
8883 RESTORE_END_STRING (disp_end + 1);
8885 input_line_pointer = save_input_line_pointer;
8886 if (gotfree_input_line)
8888 free (gotfree_input_line);
8890 if (exp->X_op == O_constant || exp->X_op == O_register)
8891 exp->X_op = O_illegal;
8894 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8896 RESTORE_END_STRING (disp_end);
8902 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8903 i386_operand_type types, const char *disp_start)
8905 i386_operand_type bigdisp;
8908 /* We do this to make sure that the section symbol is in
8909 the symbol table. We will ultimately change the relocation
8910 to be relative to the beginning of the section. */
8911 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8912 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8913 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8915 if (exp->X_op != O_symbol)
8918 if (S_IS_LOCAL (exp->X_add_symbol)
8919 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8920 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8921 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8922 exp->X_op = O_subtract;
8923 exp->X_op_symbol = GOT_symbol;
8924 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8925 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8926 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8927 i.reloc[this_operand] = BFD_RELOC_64;
8929 i.reloc[this_operand] = BFD_RELOC_32;
8932 else if (exp->X_op == O_absent
8933 || exp->X_op == O_illegal
8934 || exp->X_op == O_big)
8937 as_bad (_("missing or invalid displacement expression `%s'"),
8942 else if (flag_code == CODE_64BIT
8943 && !i.prefix[ADDR_PREFIX]
8944 && exp->X_op == O_constant)
8946 /* Since displacement is signed extended to 64bit, don't allow
8947 disp32 and turn off disp32s if they are out of range. */
8948 i.types[this_operand].bitfield.disp32 = 0;
8949 if (!fits_in_signed_long (exp->X_add_number))
8951 i.types[this_operand].bitfield.disp32s = 0;
8952 if (i.types[this_operand].bitfield.baseindex)
8954 as_bad (_("0x%lx out range of signed 32bit displacement"),
8955 (long) exp->X_add_number);
8961 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8962 else if (exp->X_op != O_constant
8963 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8964 && exp_seg != absolute_section
8965 && exp_seg != text_section
8966 && exp_seg != data_section
8967 && exp_seg != bss_section
8968 && exp_seg != undefined_section
8969 && !bfd_is_com_section (exp_seg))
8971 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8976 /* Check if this is a displacement only operand. */
8977 bigdisp = i.types[this_operand];
8978 bigdisp.bitfield.disp8 = 0;
8979 bigdisp.bitfield.disp16 = 0;
8980 bigdisp.bitfield.disp32 = 0;
8981 bigdisp.bitfield.disp32s = 0;
8982 bigdisp.bitfield.disp64 = 0;
8983 if (operand_type_all_zero (&bigdisp))
8984 i.types[this_operand] = operand_type_and (i.types[this_operand],
8990 /* Return the active addressing mode, taking address override and
8991 registers forming the address into consideration. Update the
8992 address override prefix if necessary. */
8994 static enum flag_code
8995 i386_addressing_mode (void)
8997 enum flag_code addr_mode;
8999 if (i.prefix[ADDR_PREFIX])
9000 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9003 addr_mode = flag_code;
9005 #if INFER_ADDR_PREFIX
9006 if (i.mem_operands == 0)
9008 /* Infer address prefix from the first memory operand. */
9009 const reg_entry *addr_reg = i.base_reg;
9011 if (addr_reg == NULL)
9012 addr_reg = i.index_reg;
9016 if (addr_reg->reg_num == RegEip
9017 || addr_reg->reg_num == RegEiz
9018 || addr_reg->reg_type.bitfield.dword)
9019 addr_mode = CODE_32BIT;
9020 else if (flag_code != CODE_64BIT
9021 && addr_reg->reg_type.bitfield.word)
9022 addr_mode = CODE_16BIT;
9024 if (addr_mode != flag_code)
9026 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9028 /* Change the size of any displacement too. At most one
9029 of Disp16 or Disp32 is set.
9030 FIXME. There doesn't seem to be any real need for
9031 separate Disp16 and Disp32 flags. The same goes for
9032 Imm16 and Imm32. Removing them would probably clean
9033 up the code quite a lot. */
9034 if (flag_code != CODE_64BIT
9035 && (i.types[this_operand].bitfield.disp16
9036 || i.types[this_operand].bitfield.disp32))
9037 i.types[this_operand]
9038 = operand_type_xor (i.types[this_operand], disp16_32);
9048 /* Make sure the memory operand we've been dealt is valid.
9049 Return 1 on success, 0 on a failure. */
9052 i386_index_check (const char *operand_string)
9054 const char *kind = "base/index";
9055 enum flag_code addr_mode = i386_addressing_mode ();
9057 if (current_templates->start->opcode_modifier.isstring
9058 && !current_templates->start->opcode_modifier.immext
9059 && (current_templates->end[-1].opcode_modifier.isstring
9062 /* Memory operands of string insns are special in that they only allow
9063 a single register (rDI, rSI, or rBX) as their memory address. */
9064 const reg_entry *expected_reg;
9065 static const char *di_si[][2] =
9071 static const char *bx[] = { "ebx", "bx", "rbx" };
9073 kind = "string address";
9075 if (current_templates->start->opcode_modifier.repprefixok)
9077 i386_operand_type type = current_templates->end[-1].operand_types[0];
9079 if (!type.bitfield.baseindex
9080 || ((!i.mem_operands != !intel_syntax)
9081 && current_templates->end[-1].operand_types[1]
9082 .bitfield.baseindex))
9083 type = current_templates->end[-1].operand_types[1];
9084 expected_reg = hash_find (reg_hash,
9085 di_si[addr_mode][type.bitfield.esseg]);
9089 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9091 if (i.base_reg != expected_reg
9093 || operand_type_check (i.types[this_operand], disp))
9095 /* The second memory operand must have the same size as
9099 && !((addr_mode == CODE_64BIT
9100 && i.base_reg->reg_type.bitfield.qword)
9101 || (addr_mode == CODE_32BIT
9102 ? i.base_reg->reg_type.bitfield.dword
9103 : i.base_reg->reg_type.bitfield.word)))
9106 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9108 intel_syntax ? '[' : '(',
9110 expected_reg->reg_name,
9111 intel_syntax ? ']' : ')');
9118 as_bad (_("`%s' is not a valid %s expression"),
9119 operand_string, kind);
9124 if (addr_mode != CODE_16BIT)
9126 /* 32-bit/64-bit checks. */
9128 && (addr_mode == CODE_64BIT
9129 ? !i.base_reg->reg_type.bitfield.qword
9130 : !i.base_reg->reg_type.bitfield.dword)
9132 || (i.base_reg->reg_num
9133 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9135 && !i.index_reg->reg_type.bitfield.xmmword
9136 && !i.index_reg->reg_type.bitfield.ymmword
9137 && !i.index_reg->reg_type.bitfield.zmmword
9138 && ((addr_mode == CODE_64BIT
9139 ? !(i.index_reg->reg_type.bitfield.qword
9140 || i.index_reg->reg_num == RegRiz)
9141 : !(i.index_reg->reg_type.bitfield.dword
9142 || i.index_reg->reg_num == RegEiz))
9143 || !i.index_reg->reg_type.bitfield.baseindex)))
9146 /* bndmk, bndldx, and bndstx have special restrictions. */
9147 if (current_templates->start->base_opcode == 0xf30f1b
9148 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9150 /* They cannot use RIP-relative addressing. */
9151 if (i.base_reg && i.base_reg->reg_num == RegRip)
9153 as_bad (_("`%s' cannot be used here"), operand_string);
9157 /* bndldx and bndstx ignore their scale factor. */
9158 if (current_templates->start->base_opcode != 0xf30f1b
9159 && i.log2_scale_factor)
9160 as_warn (_("register scaling is being ignored here"));
9165 /* 16-bit checks. */
9167 && (!i.base_reg->reg_type.bitfield.word
9168 || !i.base_reg->reg_type.bitfield.baseindex))
9170 && (!i.index_reg->reg_type.bitfield.word
9171 || !i.index_reg->reg_type.bitfield.baseindex
9173 && i.base_reg->reg_num < 6
9174 && i.index_reg->reg_num >= 6
9175 && i.log2_scale_factor == 0))))
9182 /* Handle vector immediates. */
9185 RC_SAE_immediate (const char *imm_start)
9187 unsigned int match_found, j;
9188 const char *pstr = imm_start;
9196 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9198 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9202 rc_op.type = RC_NamesTable[j].type;
9203 rc_op.operand = this_operand;
9204 i.rounding = &rc_op;
9208 as_bad (_("duplicated `%s'"), imm_start);
9211 pstr += RC_NamesTable[j].len;
9221 as_bad (_("Missing '}': '%s'"), imm_start);
9224 /* RC/SAE immediate string should contain nothing more. */;
9227 as_bad (_("Junk after '}': '%s'"), imm_start);
9231 exp = &im_expressions[i.imm_operands++];
9232 i.op[this_operand].imms = exp;
9234 exp->X_op = O_constant;
9235 exp->X_add_number = 0;
9236 exp->X_add_symbol = (symbolS *) 0;
9237 exp->X_op_symbol = (symbolS *) 0;
9239 i.types[this_operand].bitfield.imm8 = 1;
9243 /* Only string instructions can have a second memory operand, so
9244 reduce current_templates to just those if it contains any. */
9246 maybe_adjust_templates (void)
9248 const insn_template *t;
9250 gas_assert (i.mem_operands == 1);
9252 for (t = current_templates->start; t < current_templates->end; ++t)
9253 if (t->opcode_modifier.isstring)
9256 if (t < current_templates->end)
9258 static templates aux_templates;
9259 bfd_boolean recheck;
9261 aux_templates.start = t;
9262 for (; t < current_templates->end; ++t)
9263 if (!t->opcode_modifier.isstring)
9265 aux_templates.end = t;
9267 /* Determine whether to re-check the first memory operand. */
9268 recheck = (aux_templates.start != current_templates->start
9269 || t != current_templates->end);
9271 current_templates = &aux_templates;
9276 if (i.memop1_string != NULL
9277 && i386_index_check (i.memop1_string) == 0)
9286 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9290 i386_att_operand (char *operand_string)
9294 char *op_string = operand_string;
9296 if (is_space_char (*op_string))
9299 /* We check for an absolute prefix (differentiating,
9300 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9301 if (*op_string == ABSOLUTE_PREFIX)
9304 if (is_space_char (*op_string))
9306 i.types[this_operand].bitfield.jumpabsolute = 1;
9309 /* Check if operand is a register. */
9310 if ((r = parse_register (op_string, &end_op)) != NULL)
9312 i386_operand_type temp;
9314 /* Check for a segment override by searching for ':' after a
9315 segment register. */
9317 if (is_space_char (*op_string))
9319 if (*op_string == ':'
9320 && (r->reg_type.bitfield.sreg2
9321 || r->reg_type.bitfield.sreg3))
9326 i.seg[i.mem_operands] = &es;
9329 i.seg[i.mem_operands] = &cs;
9332 i.seg[i.mem_operands] = &ss;
9335 i.seg[i.mem_operands] = &ds;
9338 i.seg[i.mem_operands] = &fs;
9341 i.seg[i.mem_operands] = &gs;
9345 /* Skip the ':' and whitespace. */
9347 if (is_space_char (*op_string))
9350 if (!is_digit_char (*op_string)
9351 && !is_identifier_char (*op_string)
9352 && *op_string != '('
9353 && *op_string != ABSOLUTE_PREFIX)
9355 as_bad (_("bad memory operand `%s'"), op_string);
9358 /* Handle case of %es:*foo. */
9359 if (*op_string == ABSOLUTE_PREFIX)
9362 if (is_space_char (*op_string))
9364 i.types[this_operand].bitfield.jumpabsolute = 1;
9366 goto do_memory_reference;
9369 /* Handle vector operations. */
9370 if (*op_string == '{')
9372 op_string = check_VecOperations (op_string, NULL);
9373 if (op_string == NULL)
9379 as_bad (_("junk `%s' after register"), op_string);
9383 temp.bitfield.baseindex = 0;
9384 i.types[this_operand] = operand_type_or (i.types[this_operand],
9386 i.types[this_operand].bitfield.unspecified = 0;
9387 i.op[this_operand].regs = r;
9390 else if (*op_string == REGISTER_PREFIX)
9392 as_bad (_("bad register name `%s'"), op_string);
9395 else if (*op_string == IMMEDIATE_PREFIX)
9398 if (i.types[this_operand].bitfield.jumpabsolute)
9400 as_bad (_("immediate operand illegal with absolute jump"));
9403 if (!i386_immediate (op_string))
9406 else if (RC_SAE_immediate (operand_string))
9408 /* If it is a RC or SAE immediate, do nothing. */
9411 else if (is_digit_char (*op_string)
9412 || is_identifier_char (*op_string)
9413 || *op_string == '"'
9414 || *op_string == '(')
9416 /* This is a memory reference of some sort. */
9419 /* Start and end of displacement string expression (if found). */
9420 char *displacement_string_start;
9421 char *displacement_string_end;
9424 do_memory_reference:
9425 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9427 if ((i.mem_operands == 1
9428 && !current_templates->start->opcode_modifier.isstring)
9429 || i.mem_operands == 2)
9431 as_bad (_("too many memory references for `%s'"),
9432 current_templates->start->name);
9436 /* Check for base index form. We detect the base index form by
9437 looking for an ')' at the end of the operand, searching
9438 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9440 base_string = op_string + strlen (op_string);
9442 /* Handle vector operations. */
9443 vop_start = strchr (op_string, '{');
9444 if (vop_start && vop_start < base_string)
9446 if (check_VecOperations (vop_start, base_string) == NULL)
9448 base_string = vop_start;
9452 if (is_space_char (*base_string))
9455 /* If we only have a displacement, set-up for it to be parsed later. */
9456 displacement_string_start = op_string;
9457 displacement_string_end = base_string + 1;
9459 if (*base_string == ')')
9462 unsigned int parens_balanced = 1;
9463 /* We've already checked that the number of left & right ()'s are
9464 equal, so this loop will not be infinite. */
9468 if (*base_string == ')')
9470 if (*base_string == '(')
9473 while (parens_balanced);
9475 temp_string = base_string;
9477 /* Skip past '(' and whitespace. */
9479 if (is_space_char (*base_string))
9482 if (*base_string == ','
9483 || ((i.base_reg = parse_register (base_string, &end_op))
9486 displacement_string_end = temp_string;
9488 i.types[this_operand].bitfield.baseindex = 1;
9492 base_string = end_op;
9493 if (is_space_char (*base_string))
9497 /* There may be an index reg or scale factor here. */
9498 if (*base_string == ',')
9501 if (is_space_char (*base_string))
9504 if ((i.index_reg = parse_register (base_string, &end_op))
9507 base_string = end_op;
9508 if (is_space_char (*base_string))
9510 if (*base_string == ',')
9513 if (is_space_char (*base_string))
9516 else if (*base_string != ')')
9518 as_bad (_("expecting `,' or `)' "
9519 "after index register in `%s'"),
9524 else if (*base_string == REGISTER_PREFIX)
9526 end_op = strchr (base_string, ',');
9529 as_bad (_("bad register name `%s'"), base_string);
9533 /* Check for scale factor. */
9534 if (*base_string != ')')
9536 char *end_scale = i386_scale (base_string);
9541 base_string = end_scale;
9542 if (is_space_char (*base_string))
9544 if (*base_string != ')')
9546 as_bad (_("expecting `)' "
9547 "after scale factor in `%s'"),
9552 else if (!i.index_reg)
9554 as_bad (_("expecting index register or scale factor "
9555 "after `,'; got '%c'"),
9560 else if (*base_string != ')')
9562 as_bad (_("expecting `,' or `)' "
9563 "after base register in `%s'"),
9568 else if (*base_string == REGISTER_PREFIX)
9570 end_op = strchr (base_string, ',');
9573 as_bad (_("bad register name `%s'"), base_string);
9578 /* If there's an expression beginning the operand, parse it,
9579 assuming displacement_string_start and
9580 displacement_string_end are meaningful. */
9581 if (displacement_string_start != displacement_string_end)
9583 if (!i386_displacement (displacement_string_start,
9584 displacement_string_end))
9588 /* Special case for (%dx) while doing input/output op. */
9590 && operand_type_equal (&i.base_reg->reg_type,
9591 ®16_inoutportreg)
9593 && i.log2_scale_factor == 0
9594 && i.seg[i.mem_operands] == 0
9595 && !operand_type_check (i.types[this_operand], disp))
9597 i.types[this_operand] = inoutportreg;
9601 if (i386_index_check (operand_string) == 0)
9603 i.types[this_operand].bitfield.mem = 1;
9604 if (i.mem_operands == 0)
9605 i.memop1_string = xstrdup (operand_string);
9610 /* It's not a memory operand; argh! */
9611 as_bad (_("invalid char %s beginning operand %d `%s'"),
9612 output_invalid (*op_string),
9617 return 1; /* Normal return. */
9620 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9621 that an rs_machine_dependent frag may reach. */
9624 i386_frag_max_var (fragS *frag)
9626 /* The only relaxable frags are for jumps.
9627 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9628 gas_assert (frag->fr_type == rs_machine_dependent);
9629 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9632 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9634 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9636 /* STT_GNU_IFUNC symbol must go through PLT. */
9637 if ((symbol_get_bfdsym (fr_symbol)->flags
9638 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9641 if (!S_IS_EXTERNAL (fr_symbol))
9642 /* Symbol may be weak or local. */
9643 return !S_IS_WEAK (fr_symbol);
9645 /* Global symbols with non-default visibility can't be preempted. */
9646 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9649 if (fr_var != NO_RELOC)
9650 switch ((enum bfd_reloc_code_real) fr_var)
9652 case BFD_RELOC_386_PLT32:
9653 case BFD_RELOC_X86_64_PLT32:
9654 /* Symbol with PLT relocation may be preempted. */
9660 /* Global symbols with default visibility in a shared library may be
9661 preempted by another definition. */
9666 /* md_estimate_size_before_relax()
9668 Called just before relax() for rs_machine_dependent frags. The x86
9669 assembler uses these frags to handle variable size jump
9672 Any symbol that is now undefined will not become defined.
9673 Return the correct fr_subtype in the frag.
9674 Return the initial "guess for variable size of frag" to caller.
9675 The guess is actually the growth beyond the fixed part. Whatever
9676 we do to grow the fixed or variable part contributes to our
9680 md_estimate_size_before_relax (fragS *fragP, segT segment)
9682 /* We've already got fragP->fr_subtype right; all we have to do is
9683 check for un-relaxable symbols. On an ELF system, we can't relax
9684 an externally visible symbol, because it may be overridden by a
9686 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9687 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9689 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9692 #if defined (OBJ_COFF) && defined (TE_PE)
9693 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9694 && S_IS_WEAK (fragP->fr_symbol))
9698 /* Symbol is undefined in this segment, or we need to keep a
9699 reloc so that weak symbols can be overridden. */
9700 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9701 enum bfd_reloc_code_real reloc_type;
9702 unsigned char *opcode;
9705 if (fragP->fr_var != NO_RELOC)
9706 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9708 reloc_type = BFD_RELOC_16_PCREL;
9709 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9710 else if (need_plt32_p (fragP->fr_symbol))
9711 reloc_type = BFD_RELOC_X86_64_PLT32;
9714 reloc_type = BFD_RELOC_32_PCREL;
9716 old_fr_fix = fragP->fr_fix;
9717 opcode = (unsigned char *) fragP->fr_opcode;
9719 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9722 /* Make jmp (0xeb) a (d)word displacement jump. */
9724 fragP->fr_fix += size;
9725 fix_new (fragP, old_fr_fix, size,
9727 fragP->fr_offset, 1,
9733 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9735 /* Negate the condition, and branch past an
9736 unconditional jump. */
9739 /* Insert an unconditional jump. */
9741 /* We added two extra opcode bytes, and have a two byte
9743 fragP->fr_fix += 2 + 2;
9744 fix_new (fragP, old_fr_fix + 2, 2,
9746 fragP->fr_offset, 1,
9753 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9758 fixP = fix_new (fragP, old_fr_fix, 1,
9760 fragP->fr_offset, 1,
9762 fixP->fx_signed = 1;
9766 /* This changes the byte-displacement jump 0x7N
9767 to the (d)word-displacement jump 0x0f,0x8N. */
9768 opcode[1] = opcode[0] + 0x10;
9769 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9770 /* We've added an opcode byte. */
9771 fragP->fr_fix += 1 + size;
9772 fix_new (fragP, old_fr_fix + 1, size,
9774 fragP->fr_offset, 1,
9779 BAD_CASE (fragP->fr_subtype);
9783 return fragP->fr_fix - old_fr_fix;
9786 /* Guess size depending on current relax state. Initially the relax
9787 state will correspond to a short jump and we return 1, because
9788 the variable part of the frag (the branch offset) is one byte
9789 long. However, we can relax a section more than once and in that
9790 case we must either set fr_subtype back to the unrelaxed state,
9791 or return the value for the appropriate branch. */
9792 return md_relax_table[fragP->fr_subtype].rlx_length;
9795 /* Called after relax() is finished.
9797 In: Address of frag.
9798 fr_type == rs_machine_dependent.
9799 fr_subtype is what the address relaxed to.
9801 Out: Any fixSs and constants are set up.
9802 Caller will turn frag into a ".space 0". */
9805 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9808 unsigned char *opcode;
9809 unsigned char *where_to_put_displacement = NULL;
9810 offsetT target_address;
9811 offsetT opcode_address;
9812 unsigned int extension = 0;
9813 offsetT displacement_from_opcode_start;
9815 opcode = (unsigned char *) fragP->fr_opcode;
9817 /* Address we want to reach in file space. */
9818 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9820 /* Address opcode resides at in file space. */
9821 opcode_address = fragP->fr_address + fragP->fr_fix;
9823 /* Displacement from opcode start to fill into instruction. */
9824 displacement_from_opcode_start = target_address - opcode_address;
9826 if ((fragP->fr_subtype & BIG) == 0)
9828 /* Don't have to change opcode. */
9829 extension = 1; /* 1 opcode + 1 displacement */
9830 where_to_put_displacement = &opcode[1];
9834 if (no_cond_jump_promotion
9835 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9836 as_warn_where (fragP->fr_file, fragP->fr_line,
9837 _("long jump required"));
9839 switch (fragP->fr_subtype)
9841 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9842 extension = 4; /* 1 opcode + 4 displacement */
9844 where_to_put_displacement = &opcode[1];
9847 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9848 extension = 2; /* 1 opcode + 2 displacement */
9850 where_to_put_displacement = &opcode[1];
9853 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9854 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9855 extension = 5; /* 2 opcode + 4 displacement */
9856 opcode[1] = opcode[0] + 0x10;
9857 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9858 where_to_put_displacement = &opcode[2];
9861 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9862 extension = 3; /* 2 opcode + 2 displacement */
9863 opcode[1] = opcode[0] + 0x10;
9864 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9865 where_to_put_displacement = &opcode[2];
9868 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9873 where_to_put_displacement = &opcode[3];
9877 BAD_CASE (fragP->fr_subtype);
9882 /* If size if less then four we are sure that the operand fits,
9883 but if it's 4, then it could be that the displacement is larger
9885 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9887 && ((addressT) (displacement_from_opcode_start - extension
9888 + ((addressT) 1 << 31))
9889 > (((addressT) 2 << 31) - 1)))
9891 as_bad_where (fragP->fr_file, fragP->fr_line,
9892 _("jump target out of range"));
9893 /* Make us emit 0. */
9894 displacement_from_opcode_start = extension;
9896 /* Now put displacement after opcode. */
9897 md_number_to_chars ((char *) where_to_put_displacement,
9898 (valueT) (displacement_from_opcode_start - extension),
9899 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9900 fragP->fr_fix += extension;
9903 /* Apply a fixup (fixP) to segment data, once it has been determined
9904 by our caller that we have all the info we need to fix it up.
9906 Parameter valP is the pointer to the value of the bits.
9908 On the 386, immediates, displacements, and data pointers are all in
9909 the same (little-endian) format, so we don't need to care about which
9913 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9915 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9916 valueT value = *valP;
9918 #if !defined (TE_Mach)
9921 switch (fixP->fx_r_type)
9927 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9930 case BFD_RELOC_X86_64_32S:
9931 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9934 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9937 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9942 if (fixP->fx_addsy != NULL
9943 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9944 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9945 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9946 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9947 && !use_rela_relocations)
9949 /* This is a hack. There should be a better way to handle this.
9950 This covers for the fact that bfd_install_relocation will
9951 subtract the current location (for partial_inplace, PC relative
9952 relocations); see more below. */
9956 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9959 value += fixP->fx_where + fixP->fx_frag->fr_address;
9961 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9964 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9967 || (symbol_section_p (fixP->fx_addsy)
9968 && sym_seg != absolute_section))
9969 && !generic_force_reloc (fixP))
9971 /* Yes, we add the values in twice. This is because
9972 bfd_install_relocation subtracts them out again. I think
9973 bfd_install_relocation is broken, but I don't dare change
9975 value += fixP->fx_where + fixP->fx_frag->fr_address;
9979 #if defined (OBJ_COFF) && defined (TE_PE)
9980 /* For some reason, the PE format does not store a
9981 section address offset for a PC relative symbol. */
9982 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9983 || S_IS_WEAK (fixP->fx_addsy))
9984 value += md_pcrel_from (fixP);
9987 #if defined (OBJ_COFF) && defined (TE_PE)
9988 if (fixP->fx_addsy != NULL
9989 && S_IS_WEAK (fixP->fx_addsy)
9990 /* PR 16858: Do not modify weak function references. */
9991 && ! fixP->fx_pcrel)
9993 #if !defined (TE_PEP)
9994 /* For x86 PE weak function symbols are neither PC-relative
9995 nor do they set S_IS_FUNCTION. So the only reliable way
9996 to detect them is to check the flags of their containing
9998 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9999 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10003 value -= S_GET_VALUE (fixP->fx_addsy);
10007 /* Fix a few things - the dynamic linker expects certain values here,
10008 and we must not disappoint it. */
10009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10010 if (IS_ELF && fixP->fx_addsy)
10011 switch (fixP->fx_r_type)
10013 case BFD_RELOC_386_PLT32:
10014 case BFD_RELOC_X86_64_PLT32:
10015 /* Make the jump instruction point to the address of the operand. At
10016 runtime we merely add the offset to the actual PLT entry. */
10020 case BFD_RELOC_386_TLS_GD:
10021 case BFD_RELOC_386_TLS_LDM:
10022 case BFD_RELOC_386_TLS_IE_32:
10023 case BFD_RELOC_386_TLS_IE:
10024 case BFD_RELOC_386_TLS_GOTIE:
10025 case BFD_RELOC_386_TLS_GOTDESC:
10026 case BFD_RELOC_X86_64_TLSGD:
10027 case BFD_RELOC_X86_64_TLSLD:
10028 case BFD_RELOC_X86_64_GOTTPOFF:
10029 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10030 value = 0; /* Fully resolved at runtime. No addend. */
10032 case BFD_RELOC_386_TLS_LE:
10033 case BFD_RELOC_386_TLS_LDO_32:
10034 case BFD_RELOC_386_TLS_LE_32:
10035 case BFD_RELOC_X86_64_DTPOFF32:
10036 case BFD_RELOC_X86_64_DTPOFF64:
10037 case BFD_RELOC_X86_64_TPOFF32:
10038 case BFD_RELOC_X86_64_TPOFF64:
10039 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10042 case BFD_RELOC_386_TLS_DESC_CALL:
10043 case BFD_RELOC_X86_64_TLSDESC_CALL:
10044 value = 0; /* Fully resolved at runtime. No addend. */
10045 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10049 case BFD_RELOC_VTABLE_INHERIT:
10050 case BFD_RELOC_VTABLE_ENTRY:
10057 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10059 #endif /* !defined (TE_Mach) */
10061 /* Are we finished with this relocation now? */
10062 if (fixP->fx_addsy == NULL)
10064 #if defined (OBJ_COFF) && defined (TE_PE)
10065 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10068 /* Remember value for tc_gen_reloc. */
10069 fixP->fx_addnumber = value;
10070 /* Clear out the frag for now. */
10074 else if (use_rela_relocations)
10076 fixP->fx_no_overflow = 1;
10077 /* Remember value for tc_gen_reloc. */
10078 fixP->fx_addnumber = value;
10082 md_number_to_chars (p, value, fixP->fx_size);
10086 md_atof (int type, char *litP, int *sizeP)
10088 /* This outputs the LITTLENUMs in REVERSE order;
10089 in accord with the bigendian 386. */
10090 return ieee_md_atof (type, litP, sizeP, FALSE);
10093 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10096 output_invalid (int c)
10099 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10102 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10103 "(0x%x)", (unsigned char) c);
10104 return output_invalid_buf;
10107 /* REG_STRING starts *before* REGISTER_PREFIX. */
10109 static const reg_entry *
10110 parse_real_register (char *reg_string, char **end_op)
10112 char *s = reg_string;
10114 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10115 const reg_entry *r;
10117 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10118 if (*s == REGISTER_PREFIX)
10121 if (is_space_char (*s))
10124 p = reg_name_given;
10125 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10127 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10128 return (const reg_entry *) NULL;
10132 /* For naked regs, make sure that we are not dealing with an identifier.
10133 This prevents confusing an identifier like `eax_var' with register
10135 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10136 return (const reg_entry *) NULL;
10140 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10142 /* Handle floating point regs, allowing spaces in the (i) part. */
10143 if (r == i386_regtab /* %st is first entry of table */)
10145 if (is_space_char (*s))
10150 if (is_space_char (*s))
10152 if (*s >= '0' && *s <= '7')
10154 int fpr = *s - '0';
10156 if (is_space_char (*s))
10161 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10166 /* We have "%st(" then garbage. */
10167 return (const reg_entry *) NULL;
10171 if (r == NULL || allow_pseudo_reg)
10174 if (operand_type_all_zero (&r->reg_type))
10175 return (const reg_entry *) NULL;
10177 if ((r->reg_type.bitfield.dword
10178 || r->reg_type.bitfield.sreg3
10179 || r->reg_type.bitfield.control
10180 || r->reg_type.bitfield.debug
10181 || r->reg_type.bitfield.test)
10182 && !cpu_arch_flags.bitfield.cpui386)
10183 return (const reg_entry *) NULL;
10185 if (r->reg_type.bitfield.tbyte
10186 && !cpu_arch_flags.bitfield.cpu8087
10187 && !cpu_arch_flags.bitfield.cpu287
10188 && !cpu_arch_flags.bitfield.cpu387)
10189 return (const reg_entry *) NULL;
10191 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10192 return (const reg_entry *) NULL;
10194 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10195 return (const reg_entry *) NULL;
10197 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10198 return (const reg_entry *) NULL;
10200 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10201 return (const reg_entry *) NULL;
10203 if (r->reg_type.bitfield.regmask
10204 && !cpu_arch_flags.bitfield.cpuregmask)
10205 return (const reg_entry *) NULL;
10207 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10208 if (!allow_index_reg
10209 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10210 return (const reg_entry *) NULL;
10212 /* Upper 16 vector register is only available with VREX in 64bit
10214 if ((r->reg_flags & RegVRex))
10216 if (i.vec_encoding == vex_encoding_default)
10217 i.vec_encoding = vex_encoding_evex;
10219 if (!cpu_arch_flags.bitfield.cpuvrex
10220 || i.vec_encoding != vex_encoding_evex
10221 || flag_code != CODE_64BIT)
10222 return (const reg_entry *) NULL;
10225 if (((r->reg_flags & (RegRex64 | RegRex))
10226 || r->reg_type.bitfield.qword)
10227 && (!cpu_arch_flags.bitfield.cpulm
10228 || !operand_type_equal (&r->reg_type, &control))
10229 && flag_code != CODE_64BIT)
10230 return (const reg_entry *) NULL;
10232 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10233 return (const reg_entry *) NULL;
10238 /* REG_STRING starts *before* REGISTER_PREFIX. */
10240 static const reg_entry *
10241 parse_register (char *reg_string, char **end_op)
10243 const reg_entry *r;
10245 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10246 r = parse_real_register (reg_string, end_op);
10251 char *save = input_line_pointer;
10255 input_line_pointer = reg_string;
10256 c = get_symbol_name (®_string);
10257 symbolP = symbol_find (reg_string);
10258 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10260 const expressionS *e = symbol_get_value_expression (symbolP);
10262 know (e->X_op == O_register);
10263 know (e->X_add_number >= 0
10264 && (valueT) e->X_add_number < i386_regtab_size);
10265 r = i386_regtab + e->X_add_number;
10266 if ((r->reg_flags & RegVRex))
10267 i.vec_encoding = vex_encoding_evex;
10268 *end_op = input_line_pointer;
10270 *input_line_pointer = c;
10271 input_line_pointer = save;
10277 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10279 const reg_entry *r;
10280 char *end = input_line_pointer;
10283 r = parse_register (name, &input_line_pointer);
10284 if (r && end <= input_line_pointer)
10286 *nextcharP = *input_line_pointer;
10287 *input_line_pointer = 0;
10288 e->X_op = O_register;
10289 e->X_add_number = r - i386_regtab;
10292 input_line_pointer = end;
10294 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10298 md_operand (expressionS *e)
10301 const reg_entry *r;
10303 switch (*input_line_pointer)
10305 case REGISTER_PREFIX:
10306 r = parse_real_register (input_line_pointer, &end);
10309 e->X_op = O_register;
10310 e->X_add_number = r - i386_regtab;
10311 input_line_pointer = end;
10316 gas_assert (intel_syntax);
10317 end = input_line_pointer++;
10319 if (*input_line_pointer == ']')
10321 ++input_line_pointer;
10322 e->X_op_symbol = make_expr_symbol (e);
10323 e->X_add_symbol = NULL;
10324 e->X_add_number = 0;
10329 e->X_op = O_absent;
10330 input_line_pointer = end;
10337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10338 const char *md_shortopts = "kVQ:sqnO::";
10340 const char *md_shortopts = "qnO::";
10343 #define OPTION_32 (OPTION_MD_BASE + 0)
10344 #define OPTION_64 (OPTION_MD_BASE + 1)
10345 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10346 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10347 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10348 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10349 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10350 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10351 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10352 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10353 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10354 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10355 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10356 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10357 #define OPTION_X32 (OPTION_MD_BASE + 14)
10358 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10359 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10360 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10361 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10362 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10363 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10364 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10365 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10366 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10367 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10369 struct option md_longopts[] =
10371 {"32", no_argument, NULL, OPTION_32},
10372 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10373 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10374 {"64", no_argument, NULL, OPTION_64},
10376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10377 {"x32", no_argument, NULL, OPTION_X32},
10378 {"mshared", no_argument, NULL, OPTION_MSHARED},
10380 {"divide", no_argument, NULL, OPTION_DIVIDE},
10381 {"march", required_argument, NULL, OPTION_MARCH},
10382 {"mtune", required_argument, NULL, OPTION_MTUNE},
10383 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10384 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10385 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10386 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10387 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10388 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10389 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10390 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10391 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10392 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10393 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10394 # if defined (TE_PE) || defined (TE_PEP)
10395 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10397 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10398 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10399 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10400 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10401 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10402 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10403 {NULL, no_argument, NULL, 0}
10405 size_t md_longopts_size = sizeof (md_longopts);
10408 md_parse_option (int c, const char *arg)
10411 char *arch, *next, *saved;
10416 optimize_align_code = 0;
10420 quiet_warnings = 1;
10423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10424 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10425 should be emitted or not. FIXME: Not implemented. */
10429 /* -V: SVR4 argument to print version ID. */
10431 print_version_id ();
10434 /* -k: Ignore for FreeBSD compatibility. */
10439 /* -s: On i386 Solaris, this tells the native assembler to use
10440 .stab instead of .stab.excl. We always use .stab anyhow. */
10443 case OPTION_MSHARED:
10447 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10448 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10451 const char **list, **l;
10453 list = bfd_target_list ();
10454 for (l = list; *l != NULL; l++)
10455 if (CONST_STRNEQ (*l, "elf64-x86-64")
10456 || strcmp (*l, "coff-x86-64") == 0
10457 || strcmp (*l, "pe-x86-64") == 0
10458 || strcmp (*l, "pei-x86-64") == 0
10459 || strcmp (*l, "mach-o-x86-64") == 0)
10461 default_arch = "x86_64";
10465 as_fatal (_("no compiled in support for x86_64"));
10471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10475 const char **list, **l;
10477 list = bfd_target_list ();
10478 for (l = list; *l != NULL; l++)
10479 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10481 default_arch = "x86_64:32";
10485 as_fatal (_("no compiled in support for 32bit x86_64"));
10489 as_fatal (_("32bit x86_64 is only supported for ELF"));
10494 default_arch = "i386";
10497 case OPTION_DIVIDE:
10498 #ifdef SVR4_COMMENT_CHARS
10503 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10505 for (s = i386_comment_chars; *s != '\0'; s++)
10509 i386_comment_chars = n;
10515 saved = xstrdup (arg);
10517 /* Allow -march=+nosse. */
10523 as_fatal (_("invalid -march= option: `%s'"), arg);
10524 next = strchr (arch, '+');
10527 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10529 if (strcmp (arch, cpu_arch [j].name) == 0)
10532 if (! cpu_arch[j].flags.bitfield.cpui386)
10535 cpu_arch_name = cpu_arch[j].name;
10536 cpu_sub_arch_name = NULL;
10537 cpu_arch_flags = cpu_arch[j].flags;
10538 cpu_arch_isa = cpu_arch[j].type;
10539 cpu_arch_isa_flags = cpu_arch[j].flags;
10540 if (!cpu_arch_tune_set)
10542 cpu_arch_tune = cpu_arch_isa;
10543 cpu_arch_tune_flags = cpu_arch_isa_flags;
10547 else if (*cpu_arch [j].name == '.'
10548 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10550 /* ISA extension. */
10551 i386_cpu_flags flags;
10553 flags = cpu_flags_or (cpu_arch_flags,
10554 cpu_arch[j].flags);
10556 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10558 if (cpu_sub_arch_name)
10560 char *name = cpu_sub_arch_name;
10561 cpu_sub_arch_name = concat (name,
10563 (const char *) NULL);
10567 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10568 cpu_arch_flags = flags;
10569 cpu_arch_isa_flags = flags;
10573 = cpu_flags_or (cpu_arch_isa_flags,
10574 cpu_arch[j].flags);
10579 if (j >= ARRAY_SIZE (cpu_arch))
10581 /* Disable an ISA extension. */
10582 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10583 if (strcmp (arch, cpu_noarch [j].name) == 0)
10585 i386_cpu_flags flags;
10587 flags = cpu_flags_and_not (cpu_arch_flags,
10588 cpu_noarch[j].flags);
10589 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10591 if (cpu_sub_arch_name)
10593 char *name = cpu_sub_arch_name;
10594 cpu_sub_arch_name = concat (arch,
10595 (const char *) NULL);
10599 cpu_sub_arch_name = xstrdup (arch);
10600 cpu_arch_flags = flags;
10601 cpu_arch_isa_flags = flags;
10606 if (j >= ARRAY_SIZE (cpu_noarch))
10607 j = ARRAY_SIZE (cpu_arch);
10610 if (j >= ARRAY_SIZE (cpu_arch))
10611 as_fatal (_("invalid -march= option: `%s'"), arg);
10615 while (next != NULL);
10621 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10622 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10624 if (strcmp (arg, cpu_arch [j].name) == 0)
10626 cpu_arch_tune_set = 1;
10627 cpu_arch_tune = cpu_arch [j].type;
10628 cpu_arch_tune_flags = cpu_arch[j].flags;
10632 if (j >= ARRAY_SIZE (cpu_arch))
10633 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10636 case OPTION_MMNEMONIC:
10637 if (strcasecmp (arg, "att") == 0)
10638 intel_mnemonic = 0;
10639 else if (strcasecmp (arg, "intel") == 0)
10640 intel_mnemonic = 1;
10642 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10645 case OPTION_MSYNTAX:
10646 if (strcasecmp (arg, "att") == 0)
10648 else if (strcasecmp (arg, "intel") == 0)
10651 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10654 case OPTION_MINDEX_REG:
10655 allow_index_reg = 1;
10658 case OPTION_MNAKED_REG:
10659 allow_naked_reg = 1;
10662 case OPTION_MSSE2AVX:
10666 case OPTION_MSSE_CHECK:
10667 if (strcasecmp (arg, "error") == 0)
10668 sse_check = check_error;
10669 else if (strcasecmp (arg, "warning") == 0)
10670 sse_check = check_warning;
10671 else if (strcasecmp (arg, "none") == 0)
10672 sse_check = check_none;
10674 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10677 case OPTION_MOPERAND_CHECK:
10678 if (strcasecmp (arg, "error") == 0)
10679 operand_check = check_error;
10680 else if (strcasecmp (arg, "warning") == 0)
10681 operand_check = check_warning;
10682 else if (strcasecmp (arg, "none") == 0)
10683 operand_check = check_none;
10685 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10688 case OPTION_MAVXSCALAR:
10689 if (strcasecmp (arg, "128") == 0)
10690 avxscalar = vex128;
10691 else if (strcasecmp (arg, "256") == 0)
10692 avxscalar = vex256;
10694 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10697 case OPTION_MADD_BND_PREFIX:
10698 add_bnd_prefix = 1;
10701 case OPTION_MEVEXLIG:
10702 if (strcmp (arg, "128") == 0)
10703 evexlig = evexl128;
10704 else if (strcmp (arg, "256") == 0)
10705 evexlig = evexl256;
10706 else if (strcmp (arg, "512") == 0)
10707 evexlig = evexl512;
10709 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10712 case OPTION_MEVEXRCIG:
10713 if (strcmp (arg, "rne") == 0)
10715 else if (strcmp (arg, "rd") == 0)
10717 else if (strcmp (arg, "ru") == 0)
10719 else if (strcmp (arg, "rz") == 0)
10722 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10725 case OPTION_MEVEXWIG:
10726 if (strcmp (arg, "0") == 0)
10728 else if (strcmp (arg, "1") == 0)
10731 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10734 # if defined (TE_PE) || defined (TE_PEP)
10735 case OPTION_MBIG_OBJ:
10740 case OPTION_MOMIT_LOCK_PREFIX:
10741 if (strcasecmp (arg, "yes") == 0)
10742 omit_lock_prefix = 1;
10743 else if (strcasecmp (arg, "no") == 0)
10744 omit_lock_prefix = 0;
10746 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10749 case OPTION_MFENCE_AS_LOCK_ADD:
10750 if (strcasecmp (arg, "yes") == 0)
10752 else if (strcasecmp (arg, "no") == 0)
10755 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10758 case OPTION_MRELAX_RELOCATIONS:
10759 if (strcasecmp (arg, "yes") == 0)
10760 generate_relax_relocations = 1;
10761 else if (strcasecmp (arg, "no") == 0)
10762 generate_relax_relocations = 0;
10764 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10767 case OPTION_MAMD64:
10771 case OPTION_MINTEL64:
10779 /* Turn off -Os. */
10780 optimize_for_space = 0;
10782 else if (*arg == 's')
10784 optimize_for_space = 1;
10785 /* Turn on all encoding optimizations. */
10790 optimize = atoi (arg);
10791 /* Turn off -Os. */
10792 optimize_for_space = 0;
10802 #define MESSAGE_TEMPLATE \
10806 output_message (FILE *stream, char *p, char *message, char *start,
10807 int *left_p, const char *name, int len)
10809 int size = sizeof (MESSAGE_TEMPLATE);
10810 int left = *left_p;
10812 /* Reserve 2 spaces for ", " or ",\0" */
10815 /* Check if there is any room. */
10823 p = mempcpy (p, name, len);
10827 /* Output the current message now and start a new one. */
10830 fprintf (stream, "%s\n", message);
10832 left = size - (start - message) - len - 2;
10834 gas_assert (left >= 0);
10836 p = mempcpy (p, name, len);
10844 show_arch (FILE *stream, int ext, int check)
10846 static char message[] = MESSAGE_TEMPLATE;
10847 char *start = message + 27;
10849 int size = sizeof (MESSAGE_TEMPLATE);
10856 left = size - (start - message);
10857 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10859 /* Should it be skipped? */
10860 if (cpu_arch [j].skip)
10863 name = cpu_arch [j].name;
10864 len = cpu_arch [j].len;
10867 /* It is an extension. Skip if we aren't asked to show it. */
10878 /* It is an processor. Skip if we show only extension. */
10881 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10883 /* It is an impossible processor - skip. */
10887 p = output_message (stream, p, message, start, &left, name, len);
10890 /* Display disabled extensions. */
10892 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10894 name = cpu_noarch [j].name;
10895 len = cpu_noarch [j].len;
10896 p = output_message (stream, p, message, start, &left, name,
10901 fprintf (stream, "%s\n", message);
10905 md_show_usage (FILE *stream)
10907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10908 fprintf (stream, _("\
10910 -V print assembler version number\n\
10913 fprintf (stream, _("\
10914 -n Do not optimize code alignment\n\
10915 -q quieten some warnings\n"));
10916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10917 fprintf (stream, _("\
10920 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10921 || defined (TE_PE) || defined (TE_PEP))
10922 fprintf (stream, _("\
10923 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10925 #ifdef SVR4_COMMENT_CHARS
10926 fprintf (stream, _("\
10927 --divide do not treat `/' as a comment character\n"));
10929 fprintf (stream, _("\
10930 --divide ignored\n"));
10932 fprintf (stream, _("\
10933 -march=CPU[,+EXTENSION...]\n\
10934 generate code for CPU and EXTENSION, CPU is one of:\n"));
10935 show_arch (stream, 0, 1);
10936 fprintf (stream, _("\
10937 EXTENSION is combination of:\n"));
10938 show_arch (stream, 1, 0);
10939 fprintf (stream, _("\
10940 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10941 show_arch (stream, 0, 0);
10942 fprintf (stream, _("\
10943 -msse2avx encode SSE instructions with VEX prefix\n"));
10944 fprintf (stream, _("\
10945 -msse-check=[none|error|warning]\n\
10946 check SSE instructions\n"));
10947 fprintf (stream, _("\
10948 -moperand-check=[none|error|warning]\n\
10949 check operand combinations for validity\n"));
10950 fprintf (stream, _("\
10951 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10953 fprintf (stream, _("\
10954 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10956 fprintf (stream, _("\
10957 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10958 for EVEX.W bit ignored instructions\n"));
10959 fprintf (stream, _("\
10960 -mevexrcig=[rne|rd|ru|rz]\n\
10961 encode EVEX instructions with specific EVEX.RC value\n\
10962 for SAE-only ignored instructions\n"));
10963 fprintf (stream, _("\
10964 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10965 fprintf (stream, _("\
10966 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10967 fprintf (stream, _("\
10968 -mindex-reg support pseudo index registers\n"));
10969 fprintf (stream, _("\
10970 -mnaked-reg don't require `%%' prefix for registers\n"));
10971 fprintf (stream, _("\
10972 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10973 fprintf (stream, _("\
10974 -mshared disable branch optimization for shared code\n"));
10975 # if defined (TE_PE) || defined (TE_PEP)
10976 fprintf (stream, _("\
10977 -mbig-obj generate big object files\n"));
10979 fprintf (stream, _("\
10980 -momit-lock-prefix=[no|yes]\n\
10981 strip all lock prefixes\n"));
10982 fprintf (stream, _("\
10983 -mfence-as-lock-add=[no|yes]\n\
10984 encode lfence, mfence and sfence as\n\
10985 lock addl $0x0, (%%{re}sp)\n"));
10986 fprintf (stream, _("\
10987 -mrelax-relocations=[no|yes]\n\
10988 generate relax relocations\n"));
10989 fprintf (stream, _("\
10990 -mamd64 accept only AMD64 ISA\n"));
10991 fprintf (stream, _("\
10992 -mintel64 accept only Intel64 ISA\n"));
10995 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10996 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10997 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10999 /* Pick the target format to use. */
11002 i386_target_format (void)
11004 if (!strncmp (default_arch, "x86_64", 6))
11006 update_code_flag (CODE_64BIT, 1);
11007 if (default_arch[6] == '\0')
11008 x86_elf_abi = X86_64_ABI;
11010 x86_elf_abi = X86_64_X32_ABI;
11012 else if (!strcmp (default_arch, "i386"))
11013 update_code_flag (CODE_32BIT, 1);
11014 else if (!strcmp (default_arch, "iamcu"))
11016 update_code_flag (CODE_32BIT, 1);
11017 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11019 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11020 cpu_arch_name = "iamcu";
11021 cpu_sub_arch_name = NULL;
11022 cpu_arch_flags = iamcu_flags;
11023 cpu_arch_isa = PROCESSOR_IAMCU;
11024 cpu_arch_isa_flags = iamcu_flags;
11025 if (!cpu_arch_tune_set)
11027 cpu_arch_tune = cpu_arch_isa;
11028 cpu_arch_tune_flags = cpu_arch_isa_flags;
11031 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11032 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11036 as_fatal (_("unknown architecture"));
11038 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11039 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11040 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11041 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11043 switch (OUTPUT_FLAVOR)
11045 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11046 case bfd_target_aout_flavour:
11047 return AOUT_TARGET_FORMAT;
11049 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11050 # if defined (TE_PE) || defined (TE_PEP)
11051 case bfd_target_coff_flavour:
11052 if (flag_code == CODE_64BIT)
11053 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11056 # elif defined (TE_GO32)
11057 case bfd_target_coff_flavour:
11058 return "coff-go32";
11060 case bfd_target_coff_flavour:
11061 return "coff-i386";
11064 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11065 case bfd_target_elf_flavour:
11067 const char *format;
11069 switch (x86_elf_abi)
11072 format = ELF_TARGET_FORMAT;
11075 use_rela_relocations = 1;
11077 format = ELF_TARGET_FORMAT64;
11079 case X86_64_X32_ABI:
11080 use_rela_relocations = 1;
11082 disallow_64bit_reloc = 1;
11083 format = ELF_TARGET_FORMAT32;
11086 if (cpu_arch_isa == PROCESSOR_L1OM)
11088 if (x86_elf_abi != X86_64_ABI)
11089 as_fatal (_("Intel L1OM is 64bit only"));
11090 return ELF_TARGET_L1OM_FORMAT;
11092 else if (cpu_arch_isa == PROCESSOR_K1OM)
11094 if (x86_elf_abi != X86_64_ABI)
11095 as_fatal (_("Intel K1OM is 64bit only"));
11096 return ELF_TARGET_K1OM_FORMAT;
11098 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11100 if (x86_elf_abi != I386_ABI)
11101 as_fatal (_("Intel MCU is 32bit only"));
11102 return ELF_TARGET_IAMCU_FORMAT;
11108 #if defined (OBJ_MACH_O)
11109 case bfd_target_mach_o_flavour:
11110 if (flag_code == CODE_64BIT)
11112 use_rela_relocations = 1;
11114 return "mach-o-x86-64";
11117 return "mach-o-i386";
11125 #endif /* OBJ_MAYBE_ more than one */
11128 md_undefined_symbol (char *name)
11130 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11131 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11132 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11133 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11137 if (symbol_find (name))
11138 as_bad (_("GOT already in symbol table"));
11139 GOT_symbol = symbol_new (name, undefined_section,
11140 (valueT) 0, &zero_address_frag);
11147 /* Round up a section size to the appropriate boundary. */
11150 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11152 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11153 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11155 /* For a.out, force the section size to be aligned. If we don't do
11156 this, BFD will align it for us, but it will not write out the
11157 final bytes of the section. This may be a bug in BFD, but it is
11158 easier to fix it here since that is how the other a.out targets
11162 align = bfd_get_section_alignment (stdoutput, segment);
11163 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11170 /* On the i386, PC-relative offsets are relative to the start of the
11171 next instruction. That is, the address of the offset, plus its
11172 size, since the offset is always the last part of the insn. */
11175 md_pcrel_from (fixS *fixP)
11177 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11183 s_bss (int ignore ATTRIBUTE_UNUSED)
11187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11189 obj_elf_section_change_hook ();
11191 temp = get_absolute_expression ();
11192 subseg_set (bss_section, (subsegT) temp);
11193 demand_empty_rest_of_line ();
11199 i386_validate_fix (fixS *fixp)
11201 if (fixp->fx_subsy)
11203 if (fixp->fx_subsy == GOT_symbol)
11205 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11210 if (fixp->fx_tcbit2)
11211 fixp->fx_r_type = (fixp->fx_tcbit
11212 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11213 : BFD_RELOC_X86_64_GOTPCRELX);
11216 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11221 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11223 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11225 fixp->fx_subsy = 0;
11228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11229 else if (!object_64bit)
11231 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11232 && fixp->fx_tcbit2)
11233 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11239 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11242 bfd_reloc_code_real_type code;
11244 switch (fixp->fx_r_type)
11246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11247 case BFD_RELOC_SIZE32:
11248 case BFD_RELOC_SIZE64:
11249 if (S_IS_DEFINED (fixp->fx_addsy)
11250 && !S_IS_EXTERNAL (fixp->fx_addsy))
11252 /* Resolve size relocation against local symbol to size of
11253 the symbol plus addend. */
11254 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11255 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11256 && !fits_in_unsigned_long (value))
11257 as_bad_where (fixp->fx_file, fixp->fx_line,
11258 _("symbol size computation overflow"));
11259 fixp->fx_addsy = NULL;
11260 fixp->fx_subsy = NULL;
11261 md_apply_fix (fixp, (valueT *) &value, NULL);
11265 /* Fall through. */
11267 case BFD_RELOC_X86_64_PLT32:
11268 case BFD_RELOC_X86_64_GOT32:
11269 case BFD_RELOC_X86_64_GOTPCREL:
11270 case BFD_RELOC_X86_64_GOTPCRELX:
11271 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11272 case BFD_RELOC_386_PLT32:
11273 case BFD_RELOC_386_GOT32:
11274 case BFD_RELOC_386_GOT32X:
11275 case BFD_RELOC_386_GOTOFF:
11276 case BFD_RELOC_386_GOTPC:
11277 case BFD_RELOC_386_TLS_GD:
11278 case BFD_RELOC_386_TLS_LDM:
11279 case BFD_RELOC_386_TLS_LDO_32:
11280 case BFD_RELOC_386_TLS_IE_32:
11281 case BFD_RELOC_386_TLS_IE:
11282 case BFD_RELOC_386_TLS_GOTIE:
11283 case BFD_RELOC_386_TLS_LE_32:
11284 case BFD_RELOC_386_TLS_LE:
11285 case BFD_RELOC_386_TLS_GOTDESC:
11286 case BFD_RELOC_386_TLS_DESC_CALL:
11287 case BFD_RELOC_X86_64_TLSGD:
11288 case BFD_RELOC_X86_64_TLSLD:
11289 case BFD_RELOC_X86_64_DTPOFF32:
11290 case BFD_RELOC_X86_64_DTPOFF64:
11291 case BFD_RELOC_X86_64_GOTTPOFF:
11292 case BFD_RELOC_X86_64_TPOFF32:
11293 case BFD_RELOC_X86_64_TPOFF64:
11294 case BFD_RELOC_X86_64_GOTOFF64:
11295 case BFD_RELOC_X86_64_GOTPC32:
11296 case BFD_RELOC_X86_64_GOT64:
11297 case BFD_RELOC_X86_64_GOTPCREL64:
11298 case BFD_RELOC_X86_64_GOTPC64:
11299 case BFD_RELOC_X86_64_GOTPLT64:
11300 case BFD_RELOC_X86_64_PLTOFF64:
11301 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11302 case BFD_RELOC_X86_64_TLSDESC_CALL:
11303 case BFD_RELOC_RVA:
11304 case BFD_RELOC_VTABLE_ENTRY:
11305 case BFD_RELOC_VTABLE_INHERIT:
11307 case BFD_RELOC_32_SECREL:
11309 code = fixp->fx_r_type;
11311 case BFD_RELOC_X86_64_32S:
11312 if (!fixp->fx_pcrel)
11314 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11315 code = fixp->fx_r_type;
11318 /* Fall through. */
11320 if (fixp->fx_pcrel)
11322 switch (fixp->fx_size)
11325 as_bad_where (fixp->fx_file, fixp->fx_line,
11326 _("can not do %d byte pc-relative relocation"),
11328 code = BFD_RELOC_32_PCREL;
11330 case 1: code = BFD_RELOC_8_PCREL; break;
11331 case 2: code = BFD_RELOC_16_PCREL; break;
11332 case 4: code = BFD_RELOC_32_PCREL; break;
11334 case 8: code = BFD_RELOC_64_PCREL; break;
11340 switch (fixp->fx_size)
11343 as_bad_where (fixp->fx_file, fixp->fx_line,
11344 _("can not do %d byte relocation"),
11346 code = BFD_RELOC_32;
11348 case 1: code = BFD_RELOC_8; break;
11349 case 2: code = BFD_RELOC_16; break;
11350 case 4: code = BFD_RELOC_32; break;
11352 case 8: code = BFD_RELOC_64; break;
11359 if ((code == BFD_RELOC_32
11360 || code == BFD_RELOC_32_PCREL
11361 || code == BFD_RELOC_X86_64_32S)
11363 && fixp->fx_addsy == GOT_symbol)
11366 code = BFD_RELOC_386_GOTPC;
11368 code = BFD_RELOC_X86_64_GOTPC32;
11370 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11372 && fixp->fx_addsy == GOT_symbol)
11374 code = BFD_RELOC_X86_64_GOTPC64;
11377 rel = XNEW (arelent);
11378 rel->sym_ptr_ptr = XNEW (asymbol *);
11379 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11381 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11383 if (!use_rela_relocations)
11385 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11386 vtable entry to be used in the relocation's section offset. */
11387 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11388 rel->address = fixp->fx_offset;
11389 #if defined (OBJ_COFF) && defined (TE_PE)
11390 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11391 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11396 /* Use the rela in 64bit mode. */
11399 if (disallow_64bit_reloc)
11402 case BFD_RELOC_X86_64_DTPOFF64:
11403 case BFD_RELOC_X86_64_TPOFF64:
11404 case BFD_RELOC_64_PCREL:
11405 case BFD_RELOC_X86_64_GOTOFF64:
11406 case BFD_RELOC_X86_64_GOT64:
11407 case BFD_RELOC_X86_64_GOTPCREL64:
11408 case BFD_RELOC_X86_64_GOTPC64:
11409 case BFD_RELOC_X86_64_GOTPLT64:
11410 case BFD_RELOC_X86_64_PLTOFF64:
11411 as_bad_where (fixp->fx_file, fixp->fx_line,
11412 _("cannot represent relocation type %s in x32 mode"),
11413 bfd_get_reloc_code_name (code));
11419 if (!fixp->fx_pcrel)
11420 rel->addend = fixp->fx_offset;
11424 case BFD_RELOC_X86_64_PLT32:
11425 case BFD_RELOC_X86_64_GOT32:
11426 case BFD_RELOC_X86_64_GOTPCREL:
11427 case BFD_RELOC_X86_64_GOTPCRELX:
11428 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11429 case BFD_RELOC_X86_64_TLSGD:
11430 case BFD_RELOC_X86_64_TLSLD:
11431 case BFD_RELOC_X86_64_GOTTPOFF:
11432 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11433 case BFD_RELOC_X86_64_TLSDESC_CALL:
11434 rel->addend = fixp->fx_offset - fixp->fx_size;
11437 rel->addend = (section->vma
11439 + fixp->fx_addnumber
11440 + md_pcrel_from (fixp));
11445 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11446 if (rel->howto == NULL)
11448 as_bad_where (fixp->fx_file, fixp->fx_line,
11449 _("cannot represent relocation type %s"),
11450 bfd_get_reloc_code_name (code));
11451 /* Set howto to a garbage value so that we can keep going. */
11452 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11453 gas_assert (rel->howto != NULL);
11459 #include "tc-i386-intel.c"
11462 tc_x86_parse_to_dw2regnum (expressionS *exp)
11464 int saved_naked_reg;
11465 char saved_register_dot;
11467 saved_naked_reg = allow_naked_reg;
11468 allow_naked_reg = 1;
11469 saved_register_dot = register_chars['.'];
11470 register_chars['.'] = '.';
11471 allow_pseudo_reg = 1;
11472 expression_and_evaluate (exp);
11473 allow_pseudo_reg = 0;
11474 register_chars['.'] = saved_register_dot;
11475 allow_naked_reg = saved_naked_reg;
11477 if (exp->X_op == O_register && exp->X_add_number >= 0)
11479 if ((addressT) exp->X_add_number < i386_regtab_size)
11481 exp->X_op = O_constant;
11482 exp->X_add_number = i386_regtab[exp->X_add_number]
11483 .dw2_regnum[flag_code >> 1];
11486 exp->X_op = O_illegal;
11491 tc_x86_frame_initial_instructions (void)
11493 static unsigned int sp_regno[2];
11495 if (!sp_regno[flag_code >> 1])
11497 char *saved_input = input_line_pointer;
11498 char sp[][4] = {"esp", "rsp"};
11501 input_line_pointer = sp[flag_code >> 1];
11502 tc_x86_parse_to_dw2regnum (&exp);
11503 gas_assert (exp.X_op == O_constant);
11504 sp_regno[flag_code >> 1] = exp.X_add_number;
11505 input_line_pointer = saved_input;
11508 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11509 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11513 x86_dwarf2_addr_size (void)
11515 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11516 if (x86_elf_abi == X86_64_X32_ABI)
11519 return bfd_arch_bits_per_address (stdoutput) / 8;
11523 i386_elf_section_type (const char *str, size_t len)
11525 if (flag_code == CODE_64BIT
11526 && len == sizeof ("unwind") - 1
11527 && strncmp (str, "unwind", 6) == 0)
11528 return SHT_X86_64_UNWIND;
11535 i386_solaris_fix_up_eh_frame (segT sec)
11537 if (flag_code == CODE_64BIT)
11538 elf_section_type (sec) = SHT_X86_64_UNWIND;
11544 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11548 exp.X_op = O_secrel;
11549 exp.X_add_symbol = symbol;
11550 exp.X_add_number = 0;
11551 emit_expr (&exp, size);
11555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11556 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11559 x86_64_section_letter (int letter, const char **ptr_msg)
11561 if (flag_code == CODE_64BIT)
11564 return SHF_X86_64_LARGE;
11566 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11569 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11574 x86_64_section_word (char *str, size_t len)
11576 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11577 return SHF_X86_64_LARGE;
11583 handle_large_common (int small ATTRIBUTE_UNUSED)
11585 if (flag_code != CODE_64BIT)
11587 s_comm_internal (0, elf_common_parse);
11588 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11592 static segT lbss_section;
11593 asection *saved_com_section_ptr = elf_com_section_ptr;
11594 asection *saved_bss_section = bss_section;
11596 if (lbss_section == NULL)
11598 flagword applicable;
11599 segT seg = now_seg;
11600 subsegT subseg = now_subseg;
11602 /* The .lbss section is for local .largecomm symbols. */
11603 lbss_section = subseg_new (".lbss", 0);
11604 applicable = bfd_applicable_section_flags (stdoutput);
11605 bfd_set_section_flags (stdoutput, lbss_section,
11606 applicable & SEC_ALLOC);
11607 seg_info (lbss_section)->bss = 1;
11609 subseg_set (seg, subseg);
11612 elf_com_section_ptr = &_bfd_elf_large_com_section;
11613 bss_section = lbss_section;
11615 s_comm_internal (0, elf_common_parse);
11617 elf_com_section_ptr = saved_com_section_ptr;
11618 bss_section = saved_bss_section;
11621 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */