1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
461 const char line_separator_chars[] = ";";
463 /* Chars that can be used to separate mant from exp in floating point
465 const char EXP_CHARS[] = "eE";
467 /* Chars that mean this number is a floating point constant
470 const char FLT_CHARS[] = "fFdDxX";
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
501 /* The instruction we're assembling. */
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
511 /* Current operand we are working on. */
512 static int this_operand = -1;
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531 /* The ELF ABI to use. */
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
552 /* 1 for intel syntax,
554 static int intel_syntax = 0;
556 /* 1 for Intel64 ISA,
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
573 static int add_bnd_prefix = 0;
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
586 /* 1 if the assembler should generate relax relocations. */
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591 static enum check_kind
597 sse_check, operand_check = check_warning;
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
604 static int optimize = 0;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
613 static int optimize_for_space = 0;
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
658 /* Encode scalar AVX instructions with specific vector length. */
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 /* Encode EVEX WIG instructions with specific evex.w. */
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
698 #define UNCOND_JUMP 0
700 #define COND_JUMP86 2
705 #define SMALL16 (SMALL | CODE16)
707 #define BIG16 (BIG | CODE16)
711 #define INLINE __inline__
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
732 const relax_typeS md_relax_table[] =
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
771 static const arch_entry cpu_arch[] =
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1031 static const noarch_entry cpu_noarch[] =
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1067 /* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1071 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1078 && *input_line_pointer == ',')
1080 align = parse_align (needs_align - 1);
1082 if (align == (addressT) -1)
1097 bss_alloc (symbolP, size, align);
1102 pe_lcomm (int needs_align)
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1108 const pseudo_typeS md_pseudo_table[] =
1110 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1113 {"align", s_align_ptwo, 0},
1115 {"arch", set_cpu_arch, 0},
1119 {"lcomm", pe_lcomm, 1},
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1125 {"slong", signed_cons, 4},
1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
1132 {"code64", set_code_flag, CODE_64BIT},
1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
1145 {"file", dwarf2_directive_file, 0},
1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1150 {"secrel32", pe_directive_secrel, 0},
1155 /* For interface with expression (). */
1156 extern char *input_line_pointer;
1158 /* Hash table for instruction mnemonic lookup. */
1159 static struct hash_control *op_hash;
1161 /* Hash table for register lookup. */
1162 static struct hash_control *reg_hash;
1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
1167 static const unsigned char f32_1[] =
1169 static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171 static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173 static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1175 static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177 static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1179 static const unsigned char f16_3[] =
1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1181 static const unsigned char f16_4[] =
1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183 static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185 static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187 static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
1189 /* 32-bit NOPs patterns. */
1190 static const unsigned char *const f32_patt[] = {
1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1193 /* 16-bit NOPs patterns. */
1194 static const unsigned char *const f16_patt[] = {
1195 f32_1, f32_2, f16_3, f16_4
1197 /* nopl (%[re]ax) */
1198 static const unsigned char alt_3[] =
1200 /* nopl 0(%[re]ax) */
1201 static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203 /* nopl 0(%[re]ax,%[re]ax,1) */
1204 static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206 /* nopw 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopl 0L(%[re]ax) */
1210 static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212 /* nopl 0L(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215 /* nopw 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* data16 nopw %cs:0L(%eax,%eax,1) */
1222 static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* 32-bit and 64-bit NOPs patterns. */
1225 static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1227 alt_9, alt_10, alt_11
1230 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1234 i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1238 /* Place the longer NOP first. */
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1243 /* Use the smaller one if the requsted one isn't available. */
1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
1250 last = count % max_single_nop_size;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1258 nops = patt[last - 1];
1261 /* Use the smaller one plus one-byte NOP if the needed one
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1269 memcpy (where + offset, nops, last);
1274 fits_in_imm7 (offsetT num)
1276 return (num & 0x7f) == num;
1280 fits_in_imm31 (offsetT num)
1282 return (num & 0x7fffffff) == num;
1285 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1289 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1291 const unsigned char *const *patt = NULL;
1292 int max_single_nop_size;
1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
1296 switch (fragP->fr_type)
1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
1310 2. For the rest, alt_patt will be used.
1312 When -mtune= isn't used, alt_patt will be used if
1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1319 if (flag_code == CODE_16BIT)
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
1344 case PROCESSOR_CORE2:
1345 case PROCESSOR_COREI7:
1346 case PROCESSOR_L1OM:
1347 case PROCESSOR_K1OM:
1348 case PROCESSOR_GENERIC64:
1350 case PROCESSOR_ATHLON:
1352 case PROCESSOR_AMDFAM10:
1354 case PROCESSOR_ZNVER:
1358 case PROCESSOR_I386:
1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
1361 case PROCESSOR_PENTIUMPRO:
1362 case PROCESSOR_IAMCU:
1363 case PROCESSOR_GENERIC32:
1370 switch (fragP->tc_frag_data.tune)
1372 case PROCESSOR_UNKNOWN:
1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1374 PROCESSOR_UNKNOWN. */
1378 case PROCESSOR_I386:
1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
1381 case PROCESSOR_IAMCU:
1383 case PROCESSOR_ATHLON:
1385 case PROCESSOR_AMDFAM10:
1387 case PROCESSOR_ZNVER:
1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
1401 case PROCESSOR_CORE2:
1402 case PROCESSOR_COREI7:
1403 case PROCESSOR_L1OM:
1404 case PROCESSOR_K1OM:
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 case PROCESSOR_GENERIC64:
1416 if (patt == f32_patt)
1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1431 limit = max_single_nop_size;
1433 if (fragP->fr_type == rs_fill_nop)
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1446 fragP->fr_var = count;
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1454 /* Use "jmp disp8" if possible. */
1456 where[0] = jump_disp8[0];
1462 unsigned int size_of_jump;
1464 if (flag_code == CODE_16BIT)
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1472 where[0] = jump32_disp32[0];
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
1494 operand_type_all_zero (const union i386_operand_type *x)
1496 switch (ARRAY_SIZE(x->array))
1507 return !x->array[0];
1514 operand_type_set (union i386_operand_type *x, unsigned int v)
1516 switch (ARRAY_SIZE(x->array))
1534 operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
1537 switch (ARRAY_SIZE(x->array))
1540 if (x->array[2] != y->array[2])
1544 if (x->array[1] != y->array[1])
1548 return x->array[0] == y->array[0];
1556 cpu_flags_all_zero (const union i386_cpu_flags *x)
1558 switch (ARRAY_SIZE(x->array))
1573 return !x->array[0];
1580 cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1583 switch (ARRAY_SIZE(x->array))
1586 if (x->array[3] != y->array[3])
1590 if (x->array[2] != y->array[2])
1594 if (x->array[1] != y->array[1])
1598 return x->array[0] == y->array[0];
1606 cpu_flags_check_cpu64 (i386_cpu_flags f)
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1612 static INLINE i386_cpu_flags
1613 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1615 switch (ARRAY_SIZE (x.array))
1618 x.array [3] &= y.array [3];
1621 x.array [2] &= y.array [2];
1624 x.array [1] &= y.array [1];
1627 x.array [0] &= y.array [0];
1635 static INLINE i386_cpu_flags
1636 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1638 switch (ARRAY_SIZE (x.array))
1641 x.array [3] |= y.array [3];
1644 x.array [2] |= y.array [2];
1647 x.array [1] |= y.array [1];
1650 x.array [0] |= y.array [0];
1658 static INLINE i386_cpu_flags
1659 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1661 switch (ARRAY_SIZE (x.array))
1664 x.array [3] &= ~y.array [3];
1667 x.array [2] &= ~y.array [2];
1670 x.array [1] &= ~y.array [1];
1673 x.array [0] &= ~y.array [0];
1681 #define CPU_FLAGS_ARCH_MATCH 0x1
1682 #define CPU_FLAGS_64BIT_MATCH 0x2
1684 #define CPU_FLAGS_PERFECT_MATCH \
1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1687 /* Return CPU flags match bits. */
1690 cpu_flags_match (const insn_template *t)
1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1698 if (cpu_flags_all_zero (&x))
1700 /* This instruction is available on all archs. */
1701 match |= CPU_FLAGS_ARCH_MATCH;
1705 /* This instruction is available only on some archs. */
1706 i386_cpu_flags cpu = cpu_arch_flags;
1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1711 x.bitfield.cpuavx512vl = 0;
1713 cpu = cpu_flags_and (x, cpu);
1714 if (!cpu_flags_all_zero (&cpu))
1716 if (x.bitfield.cpuavx)
1718 /* We need to check a few extra flags with AVX. */
1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
1726 else if (x.bitfield.cpuavx512f)
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1736 match |= CPU_FLAGS_ARCH_MATCH;
1742 static INLINE i386_operand_type
1743 operand_type_and (i386_operand_type x, i386_operand_type y)
1745 switch (ARRAY_SIZE (x.array))
1748 x.array [2] &= y.array [2];
1751 x.array [1] &= y.array [1];
1754 x.array [0] &= y.array [0];
1762 static INLINE i386_operand_type
1763 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1765 switch (ARRAY_SIZE (x.array))
1768 x.array [2] &= ~y.array [2];
1771 x.array [1] &= ~y.array [1];
1774 x.array [0] &= ~y.array [0];
1782 static INLINE i386_operand_type
1783 operand_type_or (i386_operand_type x, i386_operand_type y)
1785 switch (ARRAY_SIZE (x.array))
1788 x.array [2] |= y.array [2];
1791 x.array [1] |= y.array [1];
1794 x.array [0] |= y.array [0];
1802 static INLINE i386_operand_type
1803 operand_type_xor (i386_operand_type x, i386_operand_type y)
1805 switch (ARRAY_SIZE (x.array))
1808 x.array [2] ^= y.array [2];
1811 x.array [1] ^= y.array [1];
1814 x.array [0] ^= y.array [0];
1822 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1825 static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
1827 static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833 static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
1835 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1836 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1837 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1846 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1857 operand_type_check (i386_operand_type t, enum operand_type c)
1862 return t.bitfield.reg;
1865 return (t.bitfield.imm8
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1894 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1895 operand J for instruction template T. */
1898 match_reg_size (const insn_template *t, unsigned int j)
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
1912 /* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1916 match_simd_size (const insn_template *t, unsigned int j)
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1926 /* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1930 match_mem_size (const insn_template *t, unsigned int j)
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
1941 || ((t->operand_types[j].bitfield.regsimd
1942 && !t->opcode_modifier.broadcast
1943 && (t->operand_types[j].bitfield.dword
1944 || t->operand_types[j].bitfield.qword))
1945 ? (i.types[j].bitfield.xmmword
1946 || i.types[j].bitfield.ymmword
1947 || i.types[j].bitfield.zmmword)
1948 : !match_simd_size(t, j))));
1951 /* Return 1 if there is no size conflict on any operands for
1952 instruction template T. */
1955 operand_size_match (const insn_template *t)
1960 /* Don't check jump instructions. */
1961 if (t->opcode_modifier.jump
1962 || t->opcode_modifier.jumpbyte
1963 || t->opcode_modifier.jumpdword
1964 || t->opcode_modifier.jumpintersegment)
1967 /* Check memory and accumulator operand size. */
1968 for (j = 0; j < i.operands; j++)
1970 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1971 && t->operand_types[j].bitfield.anysize)
1974 if (t->operand_types[j].bitfield.reg
1975 && !match_reg_size (t, j))
1981 if (t->operand_types[j].bitfield.regsimd
1982 && !match_simd_size (t, j))
1988 if (t->operand_types[j].bitfield.acc
1989 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1995 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2004 else if (!t->opcode_modifier.d)
2007 i.error = operand_size_mismatch;
2011 /* Check reverse. */
2012 gas_assert (i.operands == 2);
2015 for (j = 0; j < 2; j++)
2017 if ((t->operand_types[j].bitfield.reg
2018 || t->operand_types[j].bitfield.acc)
2019 && !match_reg_size (t, j ? 0 : 1))
2022 if (i.types[j].bitfield.mem
2023 && !match_mem_size (t, j ? 0 : 1))
2031 operand_type_match (i386_operand_type overlap,
2032 i386_operand_type given)
2034 i386_operand_type temp = overlap;
2036 temp.bitfield.jumpabsolute = 0;
2037 temp.bitfield.unspecified = 0;
2038 temp.bitfield.byte = 0;
2039 temp.bitfield.word = 0;
2040 temp.bitfield.dword = 0;
2041 temp.bitfield.fword = 0;
2042 temp.bitfield.qword = 0;
2043 temp.bitfield.tbyte = 0;
2044 temp.bitfield.xmmword = 0;
2045 temp.bitfield.ymmword = 0;
2046 temp.bitfield.zmmword = 0;
2047 if (operand_type_all_zero (&temp))
2050 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2051 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2055 i.error = operand_type_mismatch;
2059 /* If given types g0 and g1 are registers they must be of the same type
2060 unless the expected operand type register overlap is null.
2061 Memory operand size of certain SIMD instructions is also being checked
2065 operand_type_register_match (i386_operand_type g0,
2066 i386_operand_type t0,
2067 i386_operand_type g1,
2068 i386_operand_type t1)
2070 if (!g0.bitfield.reg
2071 && !g0.bitfield.regsimd
2072 && (!operand_type_check (g0, anymem)
2073 || g0.bitfield.unspecified
2074 || !t0.bitfield.regsimd))
2077 if (!g1.bitfield.reg
2078 && !g1.bitfield.regsimd
2079 && (!operand_type_check (g1, anymem)
2080 || g1.bitfield.unspecified
2081 || !t1.bitfield.regsimd))
2084 if (g0.bitfield.byte == g1.bitfield.byte
2085 && g0.bitfield.word == g1.bitfield.word
2086 && g0.bitfield.dword == g1.bitfield.dword
2087 && g0.bitfield.qword == g1.bitfield.qword
2088 && g0.bitfield.xmmword == g1.bitfield.xmmword
2089 && g0.bitfield.ymmword == g1.bitfield.ymmword
2090 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2093 if (!(t0.bitfield.byte & t1.bitfield.byte)
2094 && !(t0.bitfield.word & t1.bitfield.word)
2095 && !(t0.bitfield.dword & t1.bitfield.dword)
2096 && !(t0.bitfield.qword & t1.bitfield.qword)
2097 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2098 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2099 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2102 i.error = register_type_mismatch;
2107 static INLINE unsigned int
2108 register_number (const reg_entry *r)
2110 unsigned int nr = r->reg_num;
2112 if (r->reg_flags & RegRex)
2115 if (r->reg_flags & RegVRex)
2121 static INLINE unsigned int
2122 mode_from_disp_size (i386_operand_type t)
2124 if (t.bitfield.disp8)
2126 else if (t.bitfield.disp16
2127 || t.bitfield.disp32
2128 || t.bitfield.disp32s)
2135 fits_in_signed_byte (addressT num)
2137 return num + 0x80 <= 0xff;
2141 fits_in_unsigned_byte (addressT num)
2147 fits_in_unsigned_word (addressT num)
2149 return num <= 0xffff;
2153 fits_in_signed_word (addressT num)
2155 return num + 0x8000 <= 0xffff;
2159 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2164 return num + 0x80000000 <= 0xffffffff;
2166 } /* fits_in_signed_long() */
2169 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2174 return num <= 0xffffffff;
2176 } /* fits_in_unsigned_long() */
2179 fits_in_disp8 (offsetT num)
2181 int shift = i.memshift;
2187 mask = (1 << shift) - 1;
2189 /* Return 0 if NUM isn't properly aligned. */
2193 /* Check if NUM will fit in 8bit after shift. */
2194 return fits_in_signed_byte (num >> shift);
2198 fits_in_imm4 (offsetT num)
2200 return (num & 0xf) == num;
2203 static i386_operand_type
2204 smallest_imm_type (offsetT num)
2206 i386_operand_type t;
2208 operand_type_set (&t, 0);
2209 t.bitfield.imm64 = 1;
2211 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2213 /* This code is disabled on the 486 because all the Imm1 forms
2214 in the opcode table are slower on the i486. They're the
2215 versions with the implicitly specified single-position
2216 displacement, which has another syntax if you really want to
2218 t.bitfield.imm1 = 1;
2219 t.bitfield.imm8 = 1;
2220 t.bitfield.imm8s = 1;
2221 t.bitfield.imm16 = 1;
2222 t.bitfield.imm32 = 1;
2223 t.bitfield.imm32s = 1;
2225 else if (fits_in_signed_byte (num))
2227 t.bitfield.imm8 = 1;
2228 t.bitfield.imm8s = 1;
2229 t.bitfield.imm16 = 1;
2230 t.bitfield.imm32 = 1;
2231 t.bitfield.imm32s = 1;
2233 else if (fits_in_unsigned_byte (num))
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2240 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2246 else if (fits_in_signed_long (num))
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2251 else if (fits_in_unsigned_long (num))
2252 t.bitfield.imm32 = 1;
2258 offset_in_range (offsetT val, int size)
2264 case 1: mask = ((addressT) 1 << 8) - 1; break;
2265 case 2: mask = ((addressT) 1 << 16) - 1; break;
2266 case 4: mask = ((addressT) 2 << 31) - 1; break;
2268 case 8: mask = ((addressT) 2 << 63) - 1; break;
2274 /* If BFD64, sign extend val for 32bit address mode. */
2275 if (flag_code != CODE_64BIT
2276 || i.prefix[ADDR_PREFIX])
2277 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2278 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2281 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2283 char buf1[40], buf2[40];
2285 sprint_value (buf1, val);
2286 sprint_value (buf2, val & mask);
2287 as_warn (_("%s shortened to %s"), buf1, buf2);
2302 a. PREFIX_EXIST if attempting to add a prefix where one from the
2303 same class already exists.
2304 b. PREFIX_LOCK if lock prefix is added.
2305 c. PREFIX_REP if rep/repne prefix is added.
2306 d. PREFIX_DS if ds prefix is added.
2307 e. PREFIX_OTHER if other prefix is added.
2310 static enum PREFIX_GROUP
2311 add_prefix (unsigned int prefix)
2313 enum PREFIX_GROUP ret = PREFIX_OTHER;
2316 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2317 && flag_code == CODE_64BIT)
2319 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2320 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2321 && (prefix & (REX_R | REX_X | REX_B))))
2332 case DS_PREFIX_OPCODE:
2335 case CS_PREFIX_OPCODE:
2336 case ES_PREFIX_OPCODE:
2337 case FS_PREFIX_OPCODE:
2338 case GS_PREFIX_OPCODE:
2339 case SS_PREFIX_OPCODE:
2343 case REPNE_PREFIX_OPCODE:
2344 case REPE_PREFIX_OPCODE:
2349 case LOCK_PREFIX_OPCODE:
2358 case ADDR_PREFIX_OPCODE:
2362 case DATA_PREFIX_OPCODE:
2366 if (i.prefix[q] != 0)
2374 i.prefix[q] |= prefix;
2377 as_bad (_("same type of prefix used twice"));
2383 update_code_flag (int value, int check)
2385 PRINTF_LIKE ((*as_error));
2387 flag_code = (enum flag_code) value;
2388 if (flag_code == CODE_64BIT)
2390 cpu_arch_flags.bitfield.cpu64 = 1;
2391 cpu_arch_flags.bitfield.cpuno64 = 0;
2395 cpu_arch_flags.bitfield.cpu64 = 0;
2396 cpu_arch_flags.bitfield.cpuno64 = 1;
2398 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2401 as_error = as_fatal;
2404 (*as_error) (_("64bit mode not supported on `%s'."),
2405 cpu_arch_name ? cpu_arch_name : default_arch);
2407 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2410 as_error = as_fatal;
2413 (*as_error) (_("32bit mode not supported on `%s'."),
2414 cpu_arch_name ? cpu_arch_name : default_arch);
2416 stackop_size = '\0';
2420 set_code_flag (int value)
2422 update_code_flag (value, 0);
2426 set_16bit_gcc_code_flag (int new_code_flag)
2428 flag_code = (enum flag_code) new_code_flag;
2429 if (flag_code != CODE_16BIT)
2431 cpu_arch_flags.bitfield.cpu64 = 0;
2432 cpu_arch_flags.bitfield.cpuno64 = 1;
2433 stackop_size = LONG_MNEM_SUFFIX;
2437 set_intel_syntax (int syntax_flag)
2439 /* Find out if register prefixing is specified. */
2440 int ask_naked_reg = 0;
2443 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2446 int e = get_symbol_name (&string);
2448 if (strcmp (string, "prefix") == 0)
2450 else if (strcmp (string, "noprefix") == 0)
2453 as_bad (_("bad argument to syntax directive."));
2454 (void) restore_line_pointer (e);
2456 demand_empty_rest_of_line ();
2458 intel_syntax = syntax_flag;
2460 if (ask_naked_reg == 0)
2461 allow_naked_reg = (intel_syntax
2462 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2464 allow_naked_reg = (ask_naked_reg < 0);
2466 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2468 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2469 identifier_chars['$'] = intel_syntax ? '$' : 0;
2470 register_prefix = allow_naked_reg ? "" : "%";
2474 set_intel_mnemonic (int mnemonic_flag)
2476 intel_mnemonic = mnemonic_flag;
2480 set_allow_index_reg (int flag)
2482 allow_index_reg = flag;
2486 set_check (int what)
2488 enum check_kind *kind;
2493 kind = &operand_check;
2504 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2507 int e = get_symbol_name (&string);
2509 if (strcmp (string, "none") == 0)
2511 else if (strcmp (string, "warning") == 0)
2512 *kind = check_warning;
2513 else if (strcmp (string, "error") == 0)
2514 *kind = check_error;
2516 as_bad (_("bad argument to %s_check directive."), str);
2517 (void) restore_line_pointer (e);
2520 as_bad (_("missing argument for %s_check directive"), str);
2522 demand_empty_rest_of_line ();
2526 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2527 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2530 static const char *arch;
2532 /* Intel LIOM is only supported on ELF. */
2538 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2539 use default_arch. */
2540 arch = cpu_arch_name;
2542 arch = default_arch;
2545 /* If we are targeting Intel MCU, we must enable it. */
2546 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2547 || new_flag.bitfield.cpuiamcu)
2550 /* If we are targeting Intel L1OM, we must enable it. */
2551 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2552 || new_flag.bitfield.cpul1om)
2555 /* If we are targeting Intel K1OM, we must enable it. */
2556 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2557 || new_flag.bitfield.cpuk1om)
2560 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2565 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2569 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2572 int e = get_symbol_name (&string);
2574 i386_cpu_flags flags;
2576 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2578 if (strcmp (string, cpu_arch[j].name) == 0)
2580 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2584 cpu_arch_name = cpu_arch[j].name;
2585 cpu_sub_arch_name = NULL;
2586 cpu_arch_flags = cpu_arch[j].flags;
2587 if (flag_code == CODE_64BIT)
2589 cpu_arch_flags.bitfield.cpu64 = 1;
2590 cpu_arch_flags.bitfield.cpuno64 = 0;
2594 cpu_arch_flags.bitfield.cpu64 = 0;
2595 cpu_arch_flags.bitfield.cpuno64 = 1;
2597 cpu_arch_isa = cpu_arch[j].type;
2598 cpu_arch_isa_flags = cpu_arch[j].flags;
2599 if (!cpu_arch_tune_set)
2601 cpu_arch_tune = cpu_arch_isa;
2602 cpu_arch_tune_flags = cpu_arch_isa_flags;
2607 flags = cpu_flags_or (cpu_arch_flags,
2610 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2612 if (cpu_sub_arch_name)
2614 char *name = cpu_sub_arch_name;
2615 cpu_sub_arch_name = concat (name,
2617 (const char *) NULL);
2621 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2622 cpu_arch_flags = flags;
2623 cpu_arch_isa_flags = flags;
2625 (void) restore_line_pointer (e);
2626 demand_empty_rest_of_line ();
2631 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2633 /* Disable an ISA extension. */
2634 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2635 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2637 flags = cpu_flags_and_not (cpu_arch_flags,
2638 cpu_noarch[j].flags);
2639 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2641 if (cpu_sub_arch_name)
2643 char *name = cpu_sub_arch_name;
2644 cpu_sub_arch_name = concat (name, string,
2645 (const char *) NULL);
2649 cpu_sub_arch_name = xstrdup (string);
2650 cpu_arch_flags = flags;
2651 cpu_arch_isa_flags = flags;
2653 (void) restore_line_pointer (e);
2654 demand_empty_rest_of_line ();
2658 j = ARRAY_SIZE (cpu_arch);
2661 if (j >= ARRAY_SIZE (cpu_arch))
2662 as_bad (_("no such architecture: `%s'"), string);
2664 *input_line_pointer = e;
2667 as_bad (_("missing cpu architecture"));
2669 no_cond_jump_promotion = 0;
2670 if (*input_line_pointer == ','
2671 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2676 ++input_line_pointer;
2677 e = get_symbol_name (&string);
2679 if (strcmp (string, "nojumps") == 0)
2680 no_cond_jump_promotion = 1;
2681 else if (strcmp (string, "jumps") == 0)
2684 as_bad (_("no such architecture modifier: `%s'"), string);
2686 (void) restore_line_pointer (e);
2689 demand_empty_rest_of_line ();
2692 enum bfd_architecture
2695 if (cpu_arch_isa == PROCESSOR_L1OM)
2697 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2698 || flag_code != CODE_64BIT)
2699 as_fatal (_("Intel L1OM is 64bit ELF only"));
2700 return bfd_arch_l1om;
2702 else if (cpu_arch_isa == PROCESSOR_K1OM)
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel K1OM is 64bit ELF only"));
2707 return bfd_arch_k1om;
2709 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code == CODE_64BIT)
2713 as_fatal (_("Intel MCU is 32bit ELF only"));
2714 return bfd_arch_iamcu;
2717 return bfd_arch_i386;
2723 if (!strncmp (default_arch, "x86_64", 6))
2725 if (cpu_arch_isa == PROCESSOR_L1OM)
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || default_arch[6] != '\0')
2729 as_fatal (_("Intel L1OM is 64bit ELF only"));
2730 return bfd_mach_l1om;
2732 else if (cpu_arch_isa == PROCESSOR_K1OM)
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel K1OM is 64bit ELF only"));
2737 return bfd_mach_k1om;
2739 else if (default_arch[6] == '\0')
2740 return bfd_mach_x86_64;
2742 return bfd_mach_x64_32;
2744 else if (!strcmp (default_arch, "i386")
2745 || !strcmp (default_arch, "iamcu"))
2747 if (cpu_arch_isa == PROCESSOR_IAMCU)
2749 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2750 as_fatal (_("Intel MCU is 32bit ELF only"));
2751 return bfd_mach_i386_iamcu;
2754 return bfd_mach_i386_i386;
2757 as_fatal (_("unknown architecture"));
2763 const char *hash_err;
2765 /* Support pseudo prefixes like {disp32}. */
2766 lex_type ['{'] = LEX_BEGIN_NAME;
2768 /* Initialize op_hash hash table. */
2769 op_hash = hash_new ();
2772 const insn_template *optab;
2773 templates *core_optab;
2775 /* Setup for loop. */
2777 core_optab = XNEW (templates);
2778 core_optab->start = optab;
2783 if (optab->name == NULL
2784 || strcmp (optab->name, (optab - 1)->name) != 0)
2786 /* different name --> ship out current template list;
2787 add to hash table; & begin anew. */
2788 core_optab->end = optab;
2789 hash_err = hash_insert (op_hash,
2791 (void *) core_optab);
2794 as_fatal (_("can't hash %s: %s"),
2798 if (optab->name == NULL)
2800 core_optab = XNEW (templates);
2801 core_optab->start = optab;
2806 /* Initialize reg_hash hash table. */
2807 reg_hash = hash_new ();
2809 const reg_entry *regtab;
2810 unsigned int regtab_size = i386_regtab_size;
2812 for (regtab = i386_regtab; regtab_size--; regtab++)
2814 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2816 as_fatal (_("can't hash %s: %s"),
2822 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2827 for (c = 0; c < 256; c++)
2832 mnemonic_chars[c] = c;
2833 register_chars[c] = c;
2834 operand_chars[c] = c;
2836 else if (ISLOWER (c))
2838 mnemonic_chars[c] = c;
2839 register_chars[c] = c;
2840 operand_chars[c] = c;
2842 else if (ISUPPER (c))
2844 mnemonic_chars[c] = TOLOWER (c);
2845 register_chars[c] = mnemonic_chars[c];
2846 operand_chars[c] = c;
2848 else if (c == '{' || c == '}')
2850 mnemonic_chars[c] = c;
2851 operand_chars[c] = c;
2854 if (ISALPHA (c) || ISDIGIT (c))
2855 identifier_chars[c] = c;
2858 identifier_chars[c] = c;
2859 operand_chars[c] = c;
2864 identifier_chars['@'] = '@';
2867 identifier_chars['?'] = '?';
2868 operand_chars['?'] = '?';
2870 digit_chars['-'] = '-';
2871 mnemonic_chars['_'] = '_';
2872 mnemonic_chars['-'] = '-';
2873 mnemonic_chars['.'] = '.';
2874 identifier_chars['_'] = '_';
2875 identifier_chars['.'] = '.';
2877 for (p = operand_special_chars; *p != '\0'; p++)
2878 operand_chars[(unsigned char) *p] = *p;
2881 if (flag_code == CODE_64BIT)
2883 #if defined (OBJ_COFF) && defined (TE_PE)
2884 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2887 x86_dwarf2_return_column = 16;
2889 x86_cie_data_alignment = -8;
2893 x86_dwarf2_return_column = 8;
2894 x86_cie_data_alignment = -4;
2899 i386_print_statistics (FILE *file)
2901 hash_print_statistics (file, "i386 opcode", op_hash);
2902 hash_print_statistics (file, "i386 register", reg_hash);
2907 /* Debugging routines for md_assemble. */
2908 static void pte (insn_template *);
2909 static void pt (i386_operand_type);
2910 static void pe (expressionS *);
2911 static void ps (symbolS *);
2914 pi (char *line, i386_insn *x)
2918 fprintf (stdout, "%s: template ", line);
2920 fprintf (stdout, " address: base %s index %s scale %x\n",
2921 x->base_reg ? x->base_reg->reg_name : "none",
2922 x->index_reg ? x->index_reg->reg_name : "none",
2923 x->log2_scale_factor);
2924 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2925 x->rm.mode, x->rm.reg, x->rm.regmem);
2926 fprintf (stdout, " sib: base %x index %x scale %x\n",
2927 x->sib.base, x->sib.index, x->sib.scale);
2928 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2929 (x->rex & REX_W) != 0,
2930 (x->rex & REX_R) != 0,
2931 (x->rex & REX_X) != 0,
2932 (x->rex & REX_B) != 0);
2933 for (j = 0; j < x->operands; j++)
2935 fprintf (stdout, " #%d: ", j + 1);
2937 fprintf (stdout, "\n");
2938 if (x->types[j].bitfield.reg
2939 || x->types[j].bitfield.regmmx
2940 || x->types[j].bitfield.regsimd
2941 || x->types[j].bitfield.sreg2
2942 || x->types[j].bitfield.sreg3
2943 || x->types[j].bitfield.control
2944 || x->types[j].bitfield.debug
2945 || x->types[j].bitfield.test)
2946 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2947 if (operand_type_check (x->types[j], imm))
2949 if (operand_type_check (x->types[j], disp))
2950 pe (x->op[j].disps);
2955 pte (insn_template *t)
2958 fprintf (stdout, " %d operands ", t->operands);
2959 fprintf (stdout, "opcode %x ", t->base_opcode);
2960 if (t->extension_opcode != None)
2961 fprintf (stdout, "ext %x ", t->extension_opcode);
2962 if (t->opcode_modifier.d)
2963 fprintf (stdout, "D");
2964 if (t->opcode_modifier.w)
2965 fprintf (stdout, "W");
2966 fprintf (stdout, "\n");
2967 for (j = 0; j < t->operands; j++)
2969 fprintf (stdout, " #%d type ", j + 1);
2970 pt (t->operand_types[j]);
2971 fprintf (stdout, "\n");
2978 fprintf (stdout, " operation %d\n", e->X_op);
2979 fprintf (stdout, " add_number %ld (%lx)\n",
2980 (long) e->X_add_number, (long) e->X_add_number);
2981 if (e->X_add_symbol)
2983 fprintf (stdout, " add_symbol ");
2984 ps (e->X_add_symbol);
2985 fprintf (stdout, "\n");
2989 fprintf (stdout, " op_symbol ");
2990 ps (e->X_op_symbol);
2991 fprintf (stdout, "\n");
2998 fprintf (stdout, "%s type %s%s",
3000 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3001 segment_name (S_GET_SEGMENT (s)));
3004 static struct type_name
3006 i386_operand_type mask;
3009 const type_names[] =
3011 { OPERAND_TYPE_REG8, "r8" },
3012 { OPERAND_TYPE_REG16, "r16" },
3013 { OPERAND_TYPE_REG32, "r32" },
3014 { OPERAND_TYPE_REG64, "r64" },
3015 { OPERAND_TYPE_IMM8, "i8" },
3016 { OPERAND_TYPE_IMM8, "i8s" },
3017 { OPERAND_TYPE_IMM16, "i16" },
3018 { OPERAND_TYPE_IMM32, "i32" },
3019 { OPERAND_TYPE_IMM32S, "i32s" },
3020 { OPERAND_TYPE_IMM64, "i64" },
3021 { OPERAND_TYPE_IMM1, "i1" },
3022 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3023 { OPERAND_TYPE_DISP8, "d8" },
3024 { OPERAND_TYPE_DISP16, "d16" },
3025 { OPERAND_TYPE_DISP32, "d32" },
3026 { OPERAND_TYPE_DISP32S, "d32s" },
3027 { OPERAND_TYPE_DISP64, "d64" },
3028 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3029 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3030 { OPERAND_TYPE_CONTROL, "control reg" },
3031 { OPERAND_TYPE_TEST, "test reg" },
3032 { OPERAND_TYPE_DEBUG, "debug reg" },
3033 { OPERAND_TYPE_FLOATREG, "FReg" },
3034 { OPERAND_TYPE_FLOATACC, "FAcc" },
3035 { OPERAND_TYPE_SREG2, "SReg2" },
3036 { OPERAND_TYPE_SREG3, "SReg3" },
3037 { OPERAND_TYPE_ACC, "Acc" },
3038 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3039 { OPERAND_TYPE_REGMMX, "rMMX" },
3040 { OPERAND_TYPE_REGXMM, "rXMM" },
3041 { OPERAND_TYPE_REGYMM, "rYMM" },
3042 { OPERAND_TYPE_REGZMM, "rZMM" },
3043 { OPERAND_TYPE_REGMASK, "Mask reg" },
3044 { OPERAND_TYPE_ESSEG, "es" },
3048 pt (i386_operand_type t)
3051 i386_operand_type a;
3053 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3055 a = operand_type_and (t, type_names[j].mask);
3056 if (!operand_type_all_zero (&a))
3057 fprintf (stdout, "%s, ", type_names[j].name);
3062 #endif /* DEBUG386 */
3064 static bfd_reloc_code_real_type
3065 reloc (unsigned int size,
3068 bfd_reloc_code_real_type other)
3070 if (other != NO_RELOC)
3072 reloc_howto_type *rel;
3077 case BFD_RELOC_X86_64_GOT32:
3078 return BFD_RELOC_X86_64_GOT64;
3080 case BFD_RELOC_X86_64_GOTPLT64:
3081 return BFD_RELOC_X86_64_GOTPLT64;
3083 case BFD_RELOC_X86_64_PLTOFF64:
3084 return BFD_RELOC_X86_64_PLTOFF64;
3086 case BFD_RELOC_X86_64_GOTPC32:
3087 other = BFD_RELOC_X86_64_GOTPC64;
3089 case BFD_RELOC_X86_64_GOTPCREL:
3090 other = BFD_RELOC_X86_64_GOTPCREL64;
3092 case BFD_RELOC_X86_64_TPOFF32:
3093 other = BFD_RELOC_X86_64_TPOFF64;
3095 case BFD_RELOC_X86_64_DTPOFF32:
3096 other = BFD_RELOC_X86_64_DTPOFF64;
3102 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3103 if (other == BFD_RELOC_SIZE32)
3106 other = BFD_RELOC_SIZE64;
3109 as_bad (_("there are no pc-relative size relocations"));
3115 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3116 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3119 rel = bfd_reloc_type_lookup (stdoutput, other);
3121 as_bad (_("unknown relocation (%u)"), other);
3122 else if (size != bfd_get_reloc_size (rel))
3123 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3124 bfd_get_reloc_size (rel),
3126 else if (pcrel && !rel->pc_relative)
3127 as_bad (_("non-pc-relative relocation for pc-relative field"));
3128 else if ((rel->complain_on_overflow == complain_overflow_signed
3130 || (rel->complain_on_overflow == complain_overflow_unsigned
3132 as_bad (_("relocated field and relocation type differ in signedness"));
3141 as_bad (_("there are no unsigned pc-relative relocations"));
3144 case 1: return BFD_RELOC_8_PCREL;
3145 case 2: return BFD_RELOC_16_PCREL;
3146 case 4: return BFD_RELOC_32_PCREL;
3147 case 8: return BFD_RELOC_64_PCREL;
3149 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3156 case 4: return BFD_RELOC_X86_64_32S;
3161 case 1: return BFD_RELOC_8;
3162 case 2: return BFD_RELOC_16;
3163 case 4: return BFD_RELOC_32;
3164 case 8: return BFD_RELOC_64;
3166 as_bad (_("cannot do %s %u byte relocation"),
3167 sign > 0 ? "signed" : "unsigned", size);
3173 /* Here we decide which fixups can be adjusted to make them relative to
3174 the beginning of the section instead of the symbol. Basically we need
3175 to make sure that the dynamic relocations are done correctly, so in
3176 some cases we force the original symbol to be used. */
3179 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3185 /* Don't adjust pc-relative references to merge sections in 64-bit
3187 if (use_rela_relocations
3188 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3192 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3193 and changed later by validate_fix. */
3194 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3195 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3198 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3199 for size relocations. */
3200 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3201 || fixP->fx_r_type == BFD_RELOC_SIZE64
3202 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3203 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3204 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3205 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3206 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3207 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3208 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3209 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3216 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3217 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3218 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3219 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3231 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3232 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3239 intel_float_operand (const char *mnemonic)
3241 /* Note that the value returned is meaningful only for opcodes with (memory)
3242 operands, hence the code here is free to improperly handle opcodes that
3243 have no operands (for better performance and smaller code). */
3245 if (mnemonic[0] != 'f')
3246 return 0; /* non-math */
3248 switch (mnemonic[1])
3250 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3251 the fs segment override prefix not currently handled because no
3252 call path can make opcodes without operands get here */
3254 return 2 /* integer op */;
3256 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3257 return 3; /* fldcw/fldenv */
3260 if (mnemonic[2] != 'o' /* fnop */)
3261 return 3; /* non-waiting control op */
3264 if (mnemonic[2] == 's')
3265 return 3; /* frstor/frstpm */
3268 if (mnemonic[2] == 'a')
3269 return 3; /* fsave */
3270 if (mnemonic[2] == 't')
3272 switch (mnemonic[3])
3274 case 'c': /* fstcw */
3275 case 'd': /* fstdw */
3276 case 'e': /* fstenv */
3277 case 's': /* fsts[gw] */
3283 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3284 return 0; /* fxsave/fxrstor are not really math ops */
3291 /* Build the VEX prefix. */
3294 build_vex_prefix (const insn_template *t)
3296 unsigned int register_specifier;
3297 unsigned int implied_prefix;
3298 unsigned int vector_length;
3300 /* Check register specifier. */
3301 if (i.vex.register_specifier)
3303 register_specifier =
3304 ~register_number (i.vex.register_specifier) & 0xf;
3305 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3308 register_specifier = 0xf;
3310 /* Use 2-byte VEX prefix by swapping destination and source
3312 if (i.vec_encoding != vex_encoding_vex3
3313 && i.dir_encoding == dir_encoding_default
3314 && i.operands == i.reg_operands
3315 && i.tm.opcode_modifier.vexopcode == VEX0F
3316 && i.tm.opcode_modifier.load
3319 unsigned int xchg = i.operands - 1;
3320 union i386_op temp_op;
3321 i386_operand_type temp_type;
3323 temp_type = i.types[xchg];
3324 i.types[xchg] = i.types[0];
3325 i.types[0] = temp_type;
3326 temp_op = i.op[xchg];
3327 i.op[xchg] = i.op[0];
3330 gas_assert (i.rm.mode == 3);
3334 i.rm.regmem = i.rm.reg;
3337 /* Use the next insn. */
3341 if (i.tm.opcode_modifier.vex == VEXScalar)
3342 vector_length = avxscalar;
3343 else if (i.tm.opcode_modifier.vex == VEX256)
3350 for (op = 0; op < t->operands; ++op)
3351 if (t->operand_types[op].bitfield.xmmword
3352 && t->operand_types[op].bitfield.ymmword
3353 && i.types[op].bitfield.ymmword)
3360 switch ((i.tm.base_opcode >> 8) & 0xff)
3365 case DATA_PREFIX_OPCODE:
3368 case REPE_PREFIX_OPCODE:
3371 case REPNE_PREFIX_OPCODE:
3378 /* Use 2-byte VEX prefix if possible. */
3379 if (i.vec_encoding != vex_encoding_vex3
3380 && i.tm.opcode_modifier.vexopcode == VEX0F
3381 && i.tm.opcode_modifier.vexw != VEXW1
3382 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3384 /* 2-byte VEX prefix. */
3388 i.vex.bytes[0] = 0xc5;
3390 /* Check the REX.R bit. */
3391 r = (i.rex & REX_R) ? 0 : 1;
3392 i.vex.bytes[1] = (r << 7
3393 | register_specifier << 3
3394 | vector_length << 2
3399 /* 3-byte VEX prefix. */
3404 switch (i.tm.opcode_modifier.vexopcode)
3408 i.vex.bytes[0] = 0xc4;
3412 i.vex.bytes[0] = 0xc4;
3416 i.vex.bytes[0] = 0xc4;
3420 i.vex.bytes[0] = 0x8f;
3424 i.vex.bytes[0] = 0x8f;
3428 i.vex.bytes[0] = 0x8f;
3434 /* The high 3 bits of the second VEX byte are 1's compliment
3435 of RXB bits from REX. */
3436 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3438 /* Check the REX.W bit. */
3439 w = (i.rex & REX_W) ? 1 : 0;
3440 if (i.tm.opcode_modifier.vexw == VEXW1)
3443 i.vex.bytes[2] = (w << 7
3444 | register_specifier << 3
3445 | vector_length << 2
3450 static INLINE bfd_boolean
3451 is_evex_encoding (const insn_template *t)
3453 return t->opcode_modifier.evex
3454 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3455 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3458 /* Build the EVEX prefix. */
3461 build_evex_prefix (void)
3463 unsigned int register_specifier;
3464 unsigned int implied_prefix;
3466 rex_byte vrex_used = 0;
3468 /* Check register specifier. */
3469 if (i.vex.register_specifier)
3471 gas_assert ((i.vrex & REX_X) == 0);
3473 register_specifier = i.vex.register_specifier->reg_num;
3474 if ((i.vex.register_specifier->reg_flags & RegRex))
3475 register_specifier += 8;
3476 /* The upper 16 registers are encoded in the fourth byte of the
3478 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3479 i.vex.bytes[3] = 0x8;
3480 register_specifier = ~register_specifier & 0xf;
3484 register_specifier = 0xf;
3486 /* Encode upper 16 vector index register in the fourth byte of
3488 if (!(i.vrex & REX_X))
3489 i.vex.bytes[3] = 0x8;
3494 switch ((i.tm.base_opcode >> 8) & 0xff)
3499 case DATA_PREFIX_OPCODE:
3502 case REPE_PREFIX_OPCODE:
3505 case REPNE_PREFIX_OPCODE:
3512 /* 4 byte EVEX prefix. */
3514 i.vex.bytes[0] = 0x62;
3517 switch (i.tm.opcode_modifier.vexopcode)
3533 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3535 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3537 /* The fifth bit of the second EVEX byte is 1's compliment of the
3538 REX_R bit in VREX. */
3539 if (!(i.vrex & REX_R))
3540 i.vex.bytes[1] |= 0x10;
3544 if ((i.reg_operands + i.imm_operands) == i.operands)
3546 /* When all operands are registers, the REX_X bit in REX is not
3547 used. We reuse it to encode the upper 16 registers, which is
3548 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3549 as 1's compliment. */
3550 if ((i.vrex & REX_B))
3553 i.vex.bytes[1] &= ~0x40;
3557 /* EVEX instructions shouldn't need the REX prefix. */
3558 i.vrex &= ~vrex_used;
3559 gas_assert (i.vrex == 0);
3561 /* Check the REX.W bit. */
3562 w = (i.rex & REX_W) ? 1 : 0;
3563 if (i.tm.opcode_modifier.vexw)
3565 if (i.tm.opcode_modifier.vexw == VEXW1)
3568 /* If w is not set it means we are dealing with WIG instruction. */
3571 if (evexwig == evexw1)
3575 /* Encode the U bit. */
3576 implied_prefix |= 0x4;
3578 /* The third byte of the EVEX prefix. */
3579 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3581 /* The fourth byte of the EVEX prefix. */
3582 /* The zeroing-masking bit. */
3583 if (i.mask && i.mask->zeroing)
3584 i.vex.bytes[3] |= 0x80;
3586 /* Don't always set the broadcast bit if there is no RC. */
3589 /* Encode the vector length. */
3590 unsigned int vec_length;
3592 if (!i.tm.opcode_modifier.evex
3593 || i.tm.opcode_modifier.evex == EVEXDYN)
3598 for (op = 0; op < i.tm.operands; ++op)
3599 if (i.tm.operand_types[op].bitfield.xmmword
3600 + i.tm.operand_types[op].bitfield.ymmword
3601 + i.tm.operand_types[op].bitfield.zmmword > 1)
3603 if (i.types[op].bitfield.zmmword)
3604 i.tm.opcode_modifier.evex = EVEX512;
3605 else if (i.types[op].bitfield.ymmword)
3606 i.tm.opcode_modifier.evex = EVEX256;
3607 else if (i.types[op].bitfield.xmmword)
3608 i.tm.opcode_modifier.evex = EVEX128;
3615 switch (i.tm.opcode_modifier.evex)
3617 case EVEXLIG: /* LL' is ignored */
3618 vec_length = evexlig << 5;
3621 vec_length = 0 << 5;
3624 vec_length = 1 << 5;
3627 vec_length = 2 << 5;
3633 i.vex.bytes[3] |= vec_length;
3634 /* Encode the broadcast bit. */
3636 i.vex.bytes[3] |= 0x10;
3640 if (i.rounding->type != saeonly)
3641 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3643 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3646 if (i.mask && i.mask->mask)
3647 i.vex.bytes[3] |= i.mask->mask->reg_num;
3651 process_immext (void)
3655 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3658 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3659 with an opcode suffix which is coded in the same place as an
3660 8-bit immediate field would be.
3661 Here we check those operands and remove them afterwards. */
3664 for (x = 0; x < i.operands; x++)
3665 if (register_number (i.op[x].regs) != x)
3666 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3667 register_prefix, i.op[x].regs->reg_name, x + 1,
3673 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3675 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3676 suffix which is coded in the same place as an 8-bit immediate
3678 Here we check those operands and remove them afterwards. */
3681 if (i.operands != 3)
3684 for (x = 0; x < 2; x++)
3685 if (register_number (i.op[x].regs) != x)
3686 goto bad_register_operand;
3688 /* Check for third operand for mwaitx/monitorx insn. */
3689 if (register_number (i.op[x].regs)
3690 != (x + (i.tm.extension_opcode == 0xfb)))
3692 bad_register_operand:
3693 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3694 register_prefix, i.op[x].regs->reg_name, x+1,
3701 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3702 which is coded in the same place as an 8-bit immediate field
3703 would be. Here we fake an 8-bit immediate operand from the
3704 opcode suffix stored in tm.extension_opcode.
3706 AVX instructions also use this encoding, for some of
3707 3 argument instructions. */
3709 gas_assert (i.imm_operands <= 1
3711 || ((i.tm.opcode_modifier.vex
3712 || i.tm.opcode_modifier.vexopcode
3713 || is_evex_encoding (&i.tm))
3714 && i.operands <= 4)));
3716 exp = &im_expressions[i.imm_operands++];
3717 i.op[i.operands].imms = exp;
3718 i.types[i.operands] = imm8;
3720 exp->X_op = O_constant;
3721 exp->X_add_number = i.tm.extension_opcode;
3722 i.tm.extension_opcode = None;
3729 switch (i.tm.opcode_modifier.hleprefixok)
3734 as_bad (_("invalid instruction `%s' after `%s'"),
3735 i.tm.name, i.hle_prefix);
3738 if (i.prefix[LOCK_PREFIX])
3740 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3744 case HLEPrefixRelease:
3745 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3747 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3751 if (i.mem_operands == 0
3752 || !operand_type_check (i.types[i.operands - 1], anymem))
3754 as_bad (_("memory destination needed for instruction `%s'"
3755 " after `xrelease'"), i.tm.name);
3762 /* Try the shortest encoding by shortening operand size. */
3765 optimize_encoding (void)
3769 if (optimize_for_space
3770 && i.reg_operands == 1
3771 && i.imm_operands == 1
3772 && !i.types[1].bitfield.byte
3773 && i.op[0].imms->X_op == O_constant
3774 && fits_in_imm7 (i.op[0].imms->X_add_number)
3775 && ((i.tm.base_opcode == 0xa8
3776 && i.tm.extension_opcode == None)
3777 || (i.tm.base_opcode == 0xf6
3778 && i.tm.extension_opcode == 0x0)))
3781 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3783 unsigned int base_regnum = i.op[1].regs->reg_num;
3784 if (flag_code == CODE_64BIT || base_regnum < 4)
3786 i.types[1].bitfield.byte = 1;
3787 /* Ignore the suffix. */
3789 if (base_regnum >= 4
3790 && !(i.op[1].regs->reg_flags & RegRex))
3792 /* Handle SP, BP, SI and DI registers. */
3793 if (i.types[1].bitfield.word)
3795 else if (i.types[1].bitfield.dword)
3803 else if (flag_code == CODE_64BIT
3804 && ((i.reg_operands == 1
3805 && i.imm_operands == 1
3806 && i.op[0].imms->X_op == O_constant
3807 && ((i.tm.base_opcode == 0xb0
3808 && i.tm.extension_opcode == None
3809 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3810 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3811 && (((i.tm.base_opcode == 0x24
3812 || i.tm.base_opcode == 0xa8)
3813 && i.tm.extension_opcode == None)
3814 || (i.tm.base_opcode == 0x80
3815 && i.tm.extension_opcode == 0x4)
3816 || ((i.tm.base_opcode == 0xf6
3817 || i.tm.base_opcode == 0xc6)
3818 && i.tm.extension_opcode == 0x0)))))
3819 || (i.reg_operands == 2
3820 && i.op[0].regs == i.op[1].regs
3821 && ((i.tm.base_opcode == 0x30
3822 || i.tm.base_opcode == 0x28)
3823 && i.tm.extension_opcode == None)))
3824 && i.types[1].bitfield.qword)
3827 andq $imm31, %r64 -> andl $imm31, %r32
3828 testq $imm31, %r64 -> testl $imm31, %r32
3829 xorq %r64, %r64 -> xorl %r32, %r32
3830 subq %r64, %r64 -> subl %r32, %r32
3831 movq $imm31, %r64 -> movl $imm31, %r32
3832 movq $imm32, %r64 -> movl $imm32, %r32
3834 i.tm.opcode_modifier.norex64 = 1;
3835 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3838 movq $imm31, %r64 -> movl $imm31, %r32
3839 movq $imm32, %r64 -> movl $imm32, %r32
3841 i.tm.operand_types[0].bitfield.imm32 = 1;
3842 i.tm.operand_types[0].bitfield.imm32s = 0;
3843 i.tm.operand_types[0].bitfield.imm64 = 0;
3844 i.types[0].bitfield.imm32 = 1;
3845 i.types[0].bitfield.imm32s = 0;
3846 i.types[0].bitfield.imm64 = 0;
3847 i.types[1].bitfield.dword = 1;
3848 i.types[1].bitfield.qword = 0;
3849 if (i.tm.base_opcode == 0xc6)
3852 movq $imm31, %r64 -> movl $imm31, %r32
3854 i.tm.base_opcode = 0xb0;
3855 i.tm.extension_opcode = None;
3856 i.tm.opcode_modifier.shortform = 1;
3857 i.tm.opcode_modifier.modrm = 0;
3861 else if (optimize > 1
3862 && i.reg_operands == 3
3863 && i.op[0].regs == i.op[1].regs
3864 && !i.types[2].bitfield.xmmword
3865 && (i.tm.opcode_modifier.vex
3868 && is_evex_encoding (&i.tm)
3869 && cpu_arch_flags.bitfield.cpuavx512vl))
3870 && ((i.tm.base_opcode == 0x55
3871 || i.tm.base_opcode == 0x6655
3872 || i.tm.base_opcode == 0x66df
3873 || i.tm.base_opcode == 0x57
3874 || i.tm.base_opcode == 0x6657
3875 || i.tm.base_opcode == 0x66ef
3876 || i.tm.base_opcode == 0x66f8
3877 || i.tm.base_opcode == 0x66f9
3878 || i.tm.base_opcode == 0x66fa
3879 || i.tm.base_opcode == 0x66fb)
3880 && i.tm.extension_opcode == None))
3883 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3885 EVEX VOP %zmmM, %zmmM, %zmmN
3886 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3887 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3888 EVEX VOP %ymmM, %ymmM, %ymmN
3889 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3890 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3891 VEX VOP %ymmM, %ymmM, %ymmN
3892 -> VEX VOP %xmmM, %xmmM, %xmmN
3893 VOP, one of vpandn and vpxor:
3894 VEX VOP %ymmM, %ymmM, %ymmN
3895 -> VEX VOP %xmmM, %xmmM, %xmmN
3896 VOP, one of vpandnd and vpandnq:
3897 EVEX VOP %zmmM, %zmmM, %zmmN
3898 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3899 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3900 EVEX VOP %ymmM, %ymmM, %ymmN
3901 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3902 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3903 VOP, one of vpxord and vpxorq:
3904 EVEX VOP %zmmM, %zmmM, %zmmN
3905 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3906 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3907 EVEX VOP %ymmM, %ymmM, %ymmN
3908 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3909 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 if (is_evex_encoding (&i.tm))
3913 /* If only lower 16 vector registers are used, we can use
3915 for (j = 0; j < 3; j++)
3916 if (register_number (i.op[j].regs) > 15)
3920 i.tm.opcode_modifier.evex = EVEX128;
3923 i.tm.opcode_modifier.vex = VEX128;
3924 i.tm.opcode_modifier.vexw = VEXW0;
3925 i.tm.opcode_modifier.evex = 0;
3929 i.tm.opcode_modifier.vex = VEX128;
3931 if (i.tm.opcode_modifier.vex)
3932 for (j = 0; j < 3; j++)
3934 i.types[j].bitfield.xmmword = 1;
3935 i.types[j].bitfield.ymmword = 0;
3940 /* This is the guts of the machine-dependent assembler. LINE points to a
3941 machine dependent instruction. This function is supposed to emit
3942 the frags/bytes it assembles to. */
3945 md_assemble (char *line)
3948 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3949 const insn_template *t;
3951 /* Initialize globals. */
3952 memset (&i, '\0', sizeof (i));
3953 for (j = 0; j < MAX_OPERANDS; j++)
3954 i.reloc[j] = NO_RELOC;
3955 memset (disp_expressions, '\0', sizeof (disp_expressions));
3956 memset (im_expressions, '\0', sizeof (im_expressions));
3957 save_stack_p = save_stack;
3959 /* First parse an instruction mnemonic & call i386_operand for the operands.
3960 We assume that the scrubber has arranged it so that line[0] is the valid
3961 start of a (possibly prefixed) mnemonic. */
3963 line = parse_insn (line, mnemonic);
3966 mnem_suffix = i.suffix;
3968 line = parse_operands (line, mnemonic);
3970 xfree (i.memop1_string);
3971 i.memop1_string = NULL;
3975 /* Now we've parsed the mnemonic into a set of templates, and have the
3976 operands at hand. */
3978 /* All intel opcodes have reversed operands except for "bound" and
3979 "enter". We also don't reverse intersegment "jmp" and "call"
3980 instructions with 2 immediate operands so that the immediate segment
3981 precedes the offset, as it does when in AT&T mode. */
3984 && (strcmp (mnemonic, "bound") != 0)
3985 && (strcmp (mnemonic, "invlpga") != 0)
3986 && !(operand_type_check (i.types[0], imm)
3987 && operand_type_check (i.types[1], imm)))
3990 /* The order of the immediates should be reversed
3991 for 2 immediates extrq and insertq instructions */
3992 if (i.imm_operands == 2
3993 && (strcmp (mnemonic, "extrq") == 0
3994 || strcmp (mnemonic, "insertq") == 0))
3995 swap_2_operands (0, 1);
4000 /* Don't optimize displacement for movabs since it only takes 64bit
4003 && i.disp_encoding != disp_encoding_32bit
4004 && (flag_code != CODE_64BIT
4005 || strcmp (mnemonic, "movabs") != 0))
4008 /* Next, we find a template that matches the given insn,
4009 making sure the overlap of the given operands types is consistent
4010 with the template operand types. */
4012 if (!(t = match_template (mnem_suffix)))
4015 if (sse_check != check_none
4016 && !i.tm.opcode_modifier.noavx
4017 && !i.tm.cpu_flags.bitfield.cpuavx
4018 && (i.tm.cpu_flags.bitfield.cpusse
4019 || i.tm.cpu_flags.bitfield.cpusse2
4020 || i.tm.cpu_flags.bitfield.cpusse3
4021 || i.tm.cpu_flags.bitfield.cpussse3
4022 || i.tm.cpu_flags.bitfield.cpusse4_1
4023 || i.tm.cpu_flags.bitfield.cpusse4_2
4024 || i.tm.cpu_flags.bitfield.cpupclmul
4025 || i.tm.cpu_flags.bitfield.cpuaes
4026 || i.tm.cpu_flags.bitfield.cpugfni))
4028 (sse_check == check_warning
4030 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4033 /* Zap movzx and movsx suffix. The suffix has been set from
4034 "word ptr" or "byte ptr" on the source operand in Intel syntax
4035 or extracted from mnemonic in AT&T syntax. But we'll use
4036 the destination register to choose the suffix for encoding. */
4037 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4039 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4040 there is no suffix, the default will be byte extension. */
4041 if (i.reg_operands != 2
4044 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4049 if (i.tm.opcode_modifier.fwait)
4050 if (!add_prefix (FWAIT_OPCODE))
4053 /* Check if REP prefix is OK. */
4054 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4056 as_bad (_("invalid instruction `%s' after `%s'"),
4057 i.tm.name, i.rep_prefix);
4061 /* Check for lock without a lockable instruction. Destination operand
4062 must be memory unless it is xchg (0x86). */
4063 if (i.prefix[LOCK_PREFIX]
4064 && (!i.tm.opcode_modifier.islockable
4065 || i.mem_operands == 0
4066 || (i.tm.base_opcode != 0x86
4067 && !operand_type_check (i.types[i.operands - 1], anymem))))
4069 as_bad (_("expecting lockable instruction after `lock'"));
4073 /* Check if HLE prefix is OK. */
4074 if (i.hle_prefix && !check_hle ())
4077 /* Check BND prefix. */
4078 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4079 as_bad (_("expecting valid branch instruction after `bnd'"));
4081 /* Check NOTRACK prefix. */
4082 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4083 as_bad (_("expecting indirect branch instruction after `notrack'"));
4085 if (i.tm.cpu_flags.bitfield.cpumpx)
4087 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4088 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4089 else if (flag_code != CODE_16BIT
4090 ? i.prefix[ADDR_PREFIX]
4091 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4092 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4095 /* Insert BND prefix. */
4097 && i.tm.opcode_modifier.bndprefixok
4098 && !i.prefix[BND_PREFIX])
4099 add_prefix (BND_PREFIX_OPCODE);
4101 /* Check string instruction segment overrides. */
4102 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4104 if (!check_string ())
4106 i.disp_operands = 0;
4109 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4110 optimize_encoding ();
4112 if (!process_suffix ())
4115 /* Update operand types. */
4116 for (j = 0; j < i.operands; j++)
4117 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4119 /* Make still unresolved immediate matches conform to size of immediate
4120 given in i.suffix. */
4121 if (!finalize_imm ())
4124 if (i.types[0].bitfield.imm1)
4125 i.imm_operands = 0; /* kludge for shift insns. */
4127 /* We only need to check those implicit registers for instructions
4128 with 3 operands or less. */
4129 if (i.operands <= 3)
4130 for (j = 0; j < i.operands; j++)
4131 if (i.types[j].bitfield.inoutportreg
4132 || i.types[j].bitfield.shiftcount
4133 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4136 /* ImmExt should be processed after SSE2AVX. */
4137 if (!i.tm.opcode_modifier.sse2avx
4138 && i.tm.opcode_modifier.immext)
4141 /* For insns with operands there are more diddles to do to the opcode. */
4144 if (!process_operands ())
4147 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4149 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4150 as_warn (_("translating to `%sp'"), i.tm.name);
4153 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4154 || is_evex_encoding (&i.tm))
4156 if (flag_code == CODE_16BIT)
4158 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4163 if (i.tm.opcode_modifier.vex)
4164 build_vex_prefix (t);
4166 build_evex_prefix ();
4169 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4170 instructions may define INT_OPCODE as well, so avoid this corner
4171 case for those instructions that use MODRM. */
4172 if (i.tm.base_opcode == INT_OPCODE
4173 && !i.tm.opcode_modifier.modrm
4174 && i.op[0].imms->X_add_number == 3)
4176 i.tm.base_opcode = INT3_OPCODE;
4180 if ((i.tm.opcode_modifier.jump
4181 || i.tm.opcode_modifier.jumpbyte
4182 || i.tm.opcode_modifier.jumpdword)
4183 && i.op[0].disps->X_op == O_constant)
4185 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4186 the absolute address given by the constant. Since ix86 jumps and
4187 calls are pc relative, we need to generate a reloc. */
4188 i.op[0].disps->X_add_symbol = &abs_symbol;
4189 i.op[0].disps->X_op = O_symbol;
4192 if (i.tm.opcode_modifier.rex64)
4195 /* For 8 bit registers we need an empty rex prefix. Also if the
4196 instruction already has a prefix, we need to convert old
4197 registers to new ones. */
4199 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4200 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4201 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4202 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4203 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4204 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4209 i.rex |= REX_OPCODE;
4210 for (x = 0; x < 2; x++)
4212 /* Look for 8 bit operand that uses old registers. */
4213 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4214 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4216 /* In case it is "hi" register, give up. */
4217 if (i.op[x].regs->reg_num > 3)
4218 as_bad (_("can't encode register '%s%s' in an "
4219 "instruction requiring REX prefix."),
4220 register_prefix, i.op[x].regs->reg_name);
4222 /* Otherwise it is equivalent to the extended register.
4223 Since the encoding doesn't change this is merely
4224 cosmetic cleanup for debug output. */
4226 i.op[x].regs = i.op[x].regs + 8;
4231 if (i.rex == 0 && i.rex_encoding)
4233 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4234 that uses legacy register. If it is "hi" register, don't add
4235 the REX_OPCODE byte. */
4237 for (x = 0; x < 2; x++)
4238 if (i.types[x].bitfield.reg
4239 && i.types[x].bitfield.byte
4240 && (i.op[x].regs->reg_flags & RegRex64) == 0
4241 && i.op[x].regs->reg_num > 3)
4243 i.rex_encoding = FALSE;
4252 add_prefix (REX_OPCODE | i.rex);
4254 /* We are ready to output the insn. */
4259 parse_insn (char *line, char *mnemonic)
4262 char *token_start = l;
4265 const insn_template *t;
4271 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4276 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4278 as_bad (_("no such instruction: `%s'"), token_start);
4283 if (!is_space_char (*l)
4284 && *l != END_OF_INSN
4286 || (*l != PREFIX_SEPARATOR
4289 as_bad (_("invalid character %s in mnemonic"),
4290 output_invalid (*l));
4293 if (token_start == l)
4295 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4296 as_bad (_("expecting prefix; got nothing"));
4298 as_bad (_("expecting mnemonic; got nothing"));
4302 /* Look up instruction (or prefix) via hash table. */
4303 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4305 if (*l != END_OF_INSN
4306 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4307 && current_templates
4308 && current_templates->start->opcode_modifier.isprefix)
4310 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4312 as_bad ((flag_code != CODE_64BIT
4313 ? _("`%s' is only supported in 64-bit mode")
4314 : _("`%s' is not supported in 64-bit mode")),
4315 current_templates->start->name);
4318 /* If we are in 16-bit mode, do not allow addr16 or data16.
4319 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4320 if ((current_templates->start->opcode_modifier.size16
4321 || current_templates->start->opcode_modifier.size32)
4322 && flag_code != CODE_64BIT
4323 && (current_templates->start->opcode_modifier.size32
4324 ^ (flag_code == CODE_16BIT)))
4326 as_bad (_("redundant %s prefix"),
4327 current_templates->start->name);
4330 if (current_templates->start->opcode_length == 0)
4332 /* Handle pseudo prefixes. */
4333 switch (current_templates->start->base_opcode)
4337 i.disp_encoding = disp_encoding_8bit;
4341 i.disp_encoding = disp_encoding_32bit;
4345 i.dir_encoding = dir_encoding_load;
4349 i.dir_encoding = dir_encoding_store;
4353 i.vec_encoding = vex_encoding_vex2;
4357 i.vec_encoding = vex_encoding_vex3;
4361 i.vec_encoding = vex_encoding_evex;
4365 i.rex_encoding = TRUE;
4369 i.no_optimize = TRUE;
4377 /* Add prefix, checking for repeated prefixes. */
4378 switch (add_prefix (current_templates->start->base_opcode))
4383 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4384 i.notrack_prefix = current_templates->start->name;
4387 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4388 i.hle_prefix = current_templates->start->name;
4389 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4390 i.bnd_prefix = current_templates->start->name;
4392 i.rep_prefix = current_templates->start->name;
4398 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4405 if (!current_templates)
4407 /* Check if we should swap operand or force 32bit displacement in
4409 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4410 i.dir_encoding = dir_encoding_store;
4411 else if (mnem_p - 3 == dot_p
4414 i.disp_encoding = disp_encoding_8bit;
4415 else if (mnem_p - 4 == dot_p
4419 i.disp_encoding = disp_encoding_32bit;
4424 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4427 if (!current_templates)
4430 /* See if we can get a match by trimming off a suffix. */
4433 case WORD_MNEM_SUFFIX:
4434 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4435 i.suffix = SHORT_MNEM_SUFFIX;
4438 case BYTE_MNEM_SUFFIX:
4439 case QWORD_MNEM_SUFFIX:
4440 i.suffix = mnem_p[-1];
4442 current_templates = (const templates *) hash_find (op_hash,
4445 case SHORT_MNEM_SUFFIX:
4446 case LONG_MNEM_SUFFIX:
4449 i.suffix = mnem_p[-1];
4451 current_templates = (const templates *) hash_find (op_hash,
4460 if (intel_float_operand (mnemonic) == 1)
4461 i.suffix = SHORT_MNEM_SUFFIX;
4463 i.suffix = LONG_MNEM_SUFFIX;
4465 current_templates = (const templates *) hash_find (op_hash,
4470 if (!current_templates)
4472 as_bad (_("no such instruction: `%s'"), token_start);
4477 if (current_templates->start->opcode_modifier.jump
4478 || current_templates->start->opcode_modifier.jumpbyte)
4480 /* Check for a branch hint. We allow ",pt" and ",pn" for
4481 predict taken and predict not taken respectively.
4482 I'm not sure that branch hints actually do anything on loop
4483 and jcxz insns (JumpByte) for current Pentium4 chips. They
4484 may work in the future and it doesn't hurt to accept them
4486 if (l[0] == ',' && l[1] == 'p')
4490 if (!add_prefix (DS_PREFIX_OPCODE))
4494 else if (l[2] == 'n')
4496 if (!add_prefix (CS_PREFIX_OPCODE))
4502 /* Any other comma loses. */
4505 as_bad (_("invalid character %s in mnemonic"),
4506 output_invalid (*l));
4510 /* Check if instruction is supported on specified architecture. */
4512 for (t = current_templates->start; t < current_templates->end; ++t)
4514 supported |= cpu_flags_match (t);
4515 if (supported == CPU_FLAGS_PERFECT_MATCH)
4517 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4518 as_warn (_("use .code16 to ensure correct addressing mode"));
4524 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4525 as_bad (flag_code == CODE_64BIT
4526 ? _("`%s' is not supported in 64-bit mode")
4527 : _("`%s' is only supported in 64-bit mode"),
4528 current_templates->start->name);
4530 as_bad (_("`%s' is not supported on `%s%s'"),
4531 current_templates->start->name,
4532 cpu_arch_name ? cpu_arch_name : default_arch,
4533 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4539 parse_operands (char *l, const char *mnemonic)
4543 /* 1 if operand is pending after ','. */
4544 unsigned int expecting_operand = 0;
4546 /* Non-zero if operand parens not balanced. */
4547 unsigned int paren_not_balanced;
4549 while (*l != END_OF_INSN)
4551 /* Skip optional white space before operand. */
4552 if (is_space_char (*l))
4554 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4556 as_bad (_("invalid character %s before operand %d"),
4557 output_invalid (*l),
4561 token_start = l; /* After white space. */
4562 paren_not_balanced = 0;
4563 while (paren_not_balanced || *l != ',')
4565 if (*l == END_OF_INSN)
4567 if (paren_not_balanced)
4570 as_bad (_("unbalanced parenthesis in operand %d."),
4573 as_bad (_("unbalanced brackets in operand %d."),
4578 break; /* we are done */
4580 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4582 as_bad (_("invalid character %s in operand %d"),
4583 output_invalid (*l),
4590 ++paren_not_balanced;
4592 --paren_not_balanced;
4597 ++paren_not_balanced;
4599 --paren_not_balanced;
4603 if (l != token_start)
4604 { /* Yes, we've read in another operand. */
4605 unsigned int operand_ok;
4606 this_operand = i.operands++;
4607 if (i.operands > MAX_OPERANDS)
4609 as_bad (_("spurious operands; (%d operands/instruction max)"),
4613 i.types[this_operand].bitfield.unspecified = 1;
4614 /* Now parse operand adding info to 'i' as we go along. */
4615 END_STRING_AND_SAVE (l);
4619 i386_intel_operand (token_start,
4620 intel_float_operand (mnemonic));
4622 operand_ok = i386_att_operand (token_start);
4624 RESTORE_END_STRING (l);
4630 if (expecting_operand)
4632 expecting_operand_after_comma:
4633 as_bad (_("expecting operand after ','; got nothing"));
4638 as_bad (_("expecting operand before ','; got nothing"));
4643 /* Now *l must be either ',' or END_OF_INSN. */
4646 if (*++l == END_OF_INSN)
4648 /* Just skip it, if it's \n complain. */
4649 goto expecting_operand_after_comma;
4651 expecting_operand = 1;
4658 swap_2_operands (int xchg1, int xchg2)
4660 union i386_op temp_op;
4661 i386_operand_type temp_type;
4662 enum bfd_reloc_code_real temp_reloc;
4664 temp_type = i.types[xchg2];
4665 i.types[xchg2] = i.types[xchg1];
4666 i.types[xchg1] = temp_type;
4667 temp_op = i.op[xchg2];
4668 i.op[xchg2] = i.op[xchg1];
4669 i.op[xchg1] = temp_op;
4670 temp_reloc = i.reloc[xchg2];
4671 i.reloc[xchg2] = i.reloc[xchg1];
4672 i.reloc[xchg1] = temp_reloc;
4676 if (i.mask->operand == xchg1)
4677 i.mask->operand = xchg2;
4678 else if (i.mask->operand == xchg2)
4679 i.mask->operand = xchg1;
4683 if (i.broadcast->operand == xchg1)
4684 i.broadcast->operand = xchg2;
4685 else if (i.broadcast->operand == xchg2)
4686 i.broadcast->operand = xchg1;
4690 if (i.rounding->operand == xchg1)
4691 i.rounding->operand = xchg2;
4692 else if (i.rounding->operand == xchg2)
4693 i.rounding->operand = xchg1;
4698 swap_operands (void)
4704 swap_2_operands (1, i.operands - 2);
4708 swap_2_operands (0, i.operands - 1);
4714 if (i.mem_operands == 2)
4716 const seg_entry *temp_seg;
4717 temp_seg = i.seg[0];
4718 i.seg[0] = i.seg[1];
4719 i.seg[1] = temp_seg;
4723 /* Try to ensure constant immediates are represented in the smallest
4728 char guess_suffix = 0;
4732 guess_suffix = i.suffix;
4733 else if (i.reg_operands)
4735 /* Figure out a suffix from the last register operand specified.
4736 We can't do this properly yet, ie. excluding InOutPortReg,
4737 but the following works for instructions with immediates.
4738 In any case, we can't set i.suffix yet. */
4739 for (op = i.operands; --op >= 0;)
4740 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4742 guess_suffix = BYTE_MNEM_SUFFIX;
4745 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4747 guess_suffix = WORD_MNEM_SUFFIX;
4750 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4752 guess_suffix = LONG_MNEM_SUFFIX;
4755 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4757 guess_suffix = QWORD_MNEM_SUFFIX;
4761 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4762 guess_suffix = WORD_MNEM_SUFFIX;
4764 for (op = i.operands; --op >= 0;)
4765 if (operand_type_check (i.types[op], imm))
4767 switch (i.op[op].imms->X_op)
4770 /* If a suffix is given, this operand may be shortened. */
4771 switch (guess_suffix)
4773 case LONG_MNEM_SUFFIX:
4774 i.types[op].bitfield.imm32 = 1;
4775 i.types[op].bitfield.imm64 = 1;
4777 case WORD_MNEM_SUFFIX:
4778 i.types[op].bitfield.imm16 = 1;
4779 i.types[op].bitfield.imm32 = 1;
4780 i.types[op].bitfield.imm32s = 1;
4781 i.types[op].bitfield.imm64 = 1;
4783 case BYTE_MNEM_SUFFIX:
4784 i.types[op].bitfield.imm8 = 1;
4785 i.types[op].bitfield.imm8s = 1;
4786 i.types[op].bitfield.imm16 = 1;
4787 i.types[op].bitfield.imm32 = 1;
4788 i.types[op].bitfield.imm32s = 1;
4789 i.types[op].bitfield.imm64 = 1;
4793 /* If this operand is at most 16 bits, convert it
4794 to a signed 16 bit number before trying to see
4795 whether it will fit in an even smaller size.
4796 This allows a 16-bit operand such as $0xffe0 to
4797 be recognised as within Imm8S range. */
4798 if ((i.types[op].bitfield.imm16)
4799 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4801 i.op[op].imms->X_add_number =
4802 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4805 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4806 if ((i.types[op].bitfield.imm32)
4807 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4810 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4811 ^ ((offsetT) 1 << 31))
4812 - ((offsetT) 1 << 31));
4816 = operand_type_or (i.types[op],
4817 smallest_imm_type (i.op[op].imms->X_add_number));
4819 /* We must avoid matching of Imm32 templates when 64bit
4820 only immediate is available. */
4821 if (guess_suffix == QWORD_MNEM_SUFFIX)
4822 i.types[op].bitfield.imm32 = 0;
4829 /* Symbols and expressions. */
4831 /* Convert symbolic operand to proper sizes for matching, but don't
4832 prevent matching a set of insns that only supports sizes other
4833 than those matching the insn suffix. */
4835 i386_operand_type mask, allowed;
4836 const insn_template *t;
4838 operand_type_set (&mask, 0);
4839 operand_type_set (&allowed, 0);
4841 for (t = current_templates->start;
4842 t < current_templates->end;
4844 allowed = operand_type_or (allowed,
4845 t->operand_types[op]);
4846 switch (guess_suffix)
4848 case QWORD_MNEM_SUFFIX:
4849 mask.bitfield.imm64 = 1;
4850 mask.bitfield.imm32s = 1;
4852 case LONG_MNEM_SUFFIX:
4853 mask.bitfield.imm32 = 1;
4855 case WORD_MNEM_SUFFIX:
4856 mask.bitfield.imm16 = 1;
4858 case BYTE_MNEM_SUFFIX:
4859 mask.bitfield.imm8 = 1;
4864 allowed = operand_type_and (mask, allowed);
4865 if (!operand_type_all_zero (&allowed))
4866 i.types[op] = operand_type_and (i.types[op], mask);
4873 /* Try to use the smallest displacement type too. */
4875 optimize_disp (void)
4879 for (op = i.operands; --op >= 0;)
4880 if (operand_type_check (i.types[op], disp))
4882 if (i.op[op].disps->X_op == O_constant)
4884 offsetT op_disp = i.op[op].disps->X_add_number;
4886 if (i.types[op].bitfield.disp16
4887 && (op_disp & ~(offsetT) 0xffff) == 0)
4889 /* If this operand is at most 16 bits, convert
4890 to a signed 16 bit number and don't use 64bit
4892 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4893 i.types[op].bitfield.disp64 = 0;
4896 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4897 if (i.types[op].bitfield.disp32
4898 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4900 /* If this operand is at most 32 bits, convert
4901 to a signed 32 bit number and don't use 64bit
4903 op_disp &= (((offsetT) 2 << 31) - 1);
4904 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4905 i.types[op].bitfield.disp64 = 0;
4908 if (!op_disp && i.types[op].bitfield.baseindex)
4910 i.types[op].bitfield.disp8 = 0;
4911 i.types[op].bitfield.disp16 = 0;
4912 i.types[op].bitfield.disp32 = 0;
4913 i.types[op].bitfield.disp32s = 0;
4914 i.types[op].bitfield.disp64 = 0;
4918 else if (flag_code == CODE_64BIT)
4920 if (fits_in_signed_long (op_disp))
4922 i.types[op].bitfield.disp64 = 0;
4923 i.types[op].bitfield.disp32s = 1;
4925 if (i.prefix[ADDR_PREFIX]
4926 && fits_in_unsigned_long (op_disp))
4927 i.types[op].bitfield.disp32 = 1;
4929 if ((i.types[op].bitfield.disp32
4930 || i.types[op].bitfield.disp32s
4931 || i.types[op].bitfield.disp16)
4932 && fits_in_disp8 (op_disp))
4933 i.types[op].bitfield.disp8 = 1;
4935 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4936 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4938 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4939 i.op[op].disps, 0, i.reloc[op]);
4940 i.types[op].bitfield.disp8 = 0;
4941 i.types[op].bitfield.disp16 = 0;
4942 i.types[op].bitfield.disp32 = 0;
4943 i.types[op].bitfield.disp32s = 0;
4944 i.types[op].bitfield.disp64 = 0;
4947 /* We only support 64bit displacement on constants. */
4948 i.types[op].bitfield.disp64 = 0;
4952 /* Check if operands are valid for the instruction. */
4955 check_VecOperands (const insn_template *t)
4959 /* Without VSIB byte, we can't have a vector register for index. */
4960 if (!t->opcode_modifier.vecsib
4962 && (i.index_reg->reg_type.bitfield.xmmword
4963 || i.index_reg->reg_type.bitfield.ymmword
4964 || i.index_reg->reg_type.bitfield.zmmword))
4966 i.error = unsupported_vector_index_register;
4970 /* Check if default mask is allowed. */
4971 if (t->opcode_modifier.nodefmask
4972 && (!i.mask || i.mask->mask->reg_num == 0))
4974 i.error = no_default_mask;
4978 /* For VSIB byte, we need a vector register for index, and all vector
4979 registers must be distinct. */
4980 if (t->opcode_modifier.vecsib)
4983 || !((t->opcode_modifier.vecsib == VecSIB128
4984 && i.index_reg->reg_type.bitfield.xmmword)
4985 || (t->opcode_modifier.vecsib == VecSIB256
4986 && i.index_reg->reg_type.bitfield.ymmword)
4987 || (t->opcode_modifier.vecsib == VecSIB512
4988 && i.index_reg->reg_type.bitfield.zmmword)))
4990 i.error = invalid_vsib_address;
4994 gas_assert (i.reg_operands == 2 || i.mask);
4995 if (i.reg_operands == 2 && !i.mask)
4997 gas_assert (i.types[0].bitfield.regsimd);
4998 gas_assert (i.types[0].bitfield.xmmword
4999 || i.types[0].bitfield.ymmword);
5000 gas_assert (i.types[2].bitfield.regsimd);
5001 gas_assert (i.types[2].bitfield.xmmword
5002 || i.types[2].bitfield.ymmword);
5003 if (operand_check == check_none)
5005 if (register_number (i.op[0].regs)
5006 != register_number (i.index_reg)
5007 && register_number (i.op[2].regs)
5008 != register_number (i.index_reg)
5009 && register_number (i.op[0].regs)
5010 != register_number (i.op[2].regs))
5012 if (operand_check == check_error)
5014 i.error = invalid_vector_register_set;
5017 as_warn (_("mask, index, and destination registers should be distinct"));
5019 else if (i.reg_operands == 1 && i.mask)
5021 if (i.types[1].bitfield.regsimd
5022 && (i.types[1].bitfield.xmmword
5023 || i.types[1].bitfield.ymmword
5024 || i.types[1].bitfield.zmmword)
5025 && (register_number (i.op[1].regs)
5026 == register_number (i.index_reg)))
5028 if (operand_check == check_error)
5030 i.error = invalid_vector_register_set;
5033 if (operand_check != check_none)
5034 as_warn (_("index and destination registers should be distinct"));
5039 /* Check if broadcast is supported by the instruction and is applied
5040 to the memory operand. */
5043 int broadcasted_opnd_size;
5045 /* Check if specified broadcast is supported in this instruction,
5046 and it's applied to memory operand of DWORD or QWORD type,
5047 depending on VecESize. */
5048 if (i.broadcast->type != t->opcode_modifier.broadcast
5049 || !i.types[i.broadcast->operand].bitfield.mem
5050 || (t->opcode_modifier.vecesize == 0
5051 && !i.types[i.broadcast->operand].bitfield.dword
5052 && !i.types[i.broadcast->operand].bitfield.unspecified)
5053 || (t->opcode_modifier.vecesize == 1
5054 && !i.types[i.broadcast->operand].bitfield.qword
5055 && !i.types[i.broadcast->operand].bitfield.unspecified))
5058 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5059 if (i.broadcast->type == BROADCAST_1TO16)
5060 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5061 else if (i.broadcast->type == BROADCAST_1TO8)
5062 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5063 else if (i.broadcast->type == BROADCAST_1TO4)
5064 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5065 else if (i.broadcast->type == BROADCAST_1TO2)
5066 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5070 if ((broadcasted_opnd_size == 256
5071 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5072 || (broadcasted_opnd_size == 512
5073 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5076 i.error = unsupported_broadcast;
5080 /* If broadcast is supported in this instruction, we need to check if
5081 operand of one-element size isn't specified without broadcast. */
5082 else if (t->opcode_modifier.broadcast && i.mem_operands)
5084 /* Find memory operand. */
5085 for (op = 0; op < i.operands; op++)
5086 if (operand_type_check (i.types[op], anymem))
5088 gas_assert (op < i.operands);
5089 /* Check size of the memory operand. */
5090 if ((t->opcode_modifier.vecesize == 0
5091 && i.types[op].bitfield.dword)
5092 || (t->opcode_modifier.vecesize == 1
5093 && i.types[op].bitfield.qword))
5095 i.error = broadcast_needed;
5100 /* Check if requested masking is supported. */
5102 && (!t->opcode_modifier.masking
5104 && t->opcode_modifier.masking == MERGING_MASKING)))
5106 i.error = unsupported_masking;
5110 /* Check if masking is applied to dest operand. */
5111 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5113 i.error = mask_not_on_destination;
5120 if ((i.rounding->type != saeonly
5121 && !t->opcode_modifier.staticrounding)
5122 || (i.rounding->type == saeonly
5123 && (t->opcode_modifier.staticrounding
5124 || !t->opcode_modifier.sae)))
5126 i.error = unsupported_rc_sae;
5129 /* If the instruction has several immediate operands and one of
5130 them is rounding, the rounding operand should be the last
5131 immediate operand. */
5132 if (i.imm_operands > 1
5133 && i.rounding->operand != (int) (i.imm_operands - 1))
5135 i.error = rc_sae_operand_not_last_imm;
5140 /* Check vector Disp8 operand. */
5141 if (t->opcode_modifier.disp8memshift
5142 && i.disp_encoding != disp_encoding_32bit)
5145 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5147 i.memshift = t->opcode_modifier.disp8memshift;
5149 for (op = 0; op < i.operands; op++)
5150 if (operand_type_check (i.types[op], disp)
5151 && i.op[op].disps->X_op == O_constant)
5153 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5155 i.types[op].bitfield.disp8 = 1;
5158 i.types[op].bitfield.disp8 = 0;
5167 /* Check if operands are valid for the instruction. Update VEX
5171 VEX_check_operands (const insn_template *t)
5173 if (i.vec_encoding == vex_encoding_evex)
5175 /* This instruction must be encoded with EVEX prefix. */
5176 if (!is_evex_encoding (t))
5178 i.error = unsupported;
5184 if (!t->opcode_modifier.vex)
5186 /* This instruction template doesn't have VEX prefix. */
5187 if (i.vec_encoding != vex_encoding_default)
5189 i.error = unsupported;
5195 /* Only check VEX_Imm4, which must be the first operand. */
5196 if (t->operand_types[0].bitfield.vec_imm4)
5198 if (i.op[0].imms->X_op != O_constant
5199 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5205 /* Turn off Imm8 so that update_imm won't complain. */
5206 i.types[0] = vec_imm4;
5212 static const insn_template *
5213 match_template (char mnem_suffix)
5215 /* Points to template once we've found it. */
5216 const insn_template *t;
5217 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5218 i386_operand_type overlap4;
5219 unsigned int found_reverse_match;
5220 i386_opcode_modifier suffix_check, mnemsuf_check;
5221 i386_operand_type operand_types [MAX_OPERANDS];
5222 int addr_prefix_disp;
5224 unsigned int found_cpu_match;
5225 unsigned int check_register;
5226 enum i386_error specific_error = 0;
5228 #if MAX_OPERANDS != 5
5229 # error "MAX_OPERANDS must be 5."
5232 found_reverse_match = 0;
5233 addr_prefix_disp = -1;
5235 memset (&suffix_check, 0, sizeof (suffix_check));
5236 if (i.suffix == BYTE_MNEM_SUFFIX)
5237 suffix_check.no_bsuf = 1;
5238 else if (i.suffix == WORD_MNEM_SUFFIX)
5239 suffix_check.no_wsuf = 1;
5240 else if (i.suffix == SHORT_MNEM_SUFFIX)
5241 suffix_check.no_ssuf = 1;
5242 else if (i.suffix == LONG_MNEM_SUFFIX)
5243 suffix_check.no_lsuf = 1;
5244 else if (i.suffix == QWORD_MNEM_SUFFIX)
5245 suffix_check.no_qsuf = 1;
5246 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5247 suffix_check.no_ldsuf = 1;
5249 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5252 switch (mnem_suffix)
5254 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5255 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5256 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5257 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5258 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5262 /* Must have right number of operands. */
5263 i.error = number_of_operands_mismatch;
5265 for (t = current_templates->start; t < current_templates->end; t++)
5267 addr_prefix_disp = -1;
5269 if (i.operands != t->operands)
5272 /* Check processor support. */
5273 i.error = unsupported;
5274 found_cpu_match = (cpu_flags_match (t)
5275 == CPU_FLAGS_PERFECT_MATCH);
5276 if (!found_cpu_match)
5279 /* Check AT&T mnemonic. */
5280 i.error = unsupported_with_intel_mnemonic;
5281 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5284 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5285 i.error = unsupported_syntax;
5286 if ((intel_syntax && t->opcode_modifier.attsyntax)
5287 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5288 || (intel64 && t->opcode_modifier.amd64)
5289 || (!intel64 && t->opcode_modifier.intel64))
5292 /* Check the suffix, except for some instructions in intel mode. */
5293 i.error = invalid_instruction_suffix;
5294 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5295 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5296 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5297 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5298 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5299 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5300 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5302 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5303 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5304 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5305 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5306 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5307 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5308 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5311 if (!operand_size_match (t))
5314 for (j = 0; j < MAX_OPERANDS; j++)
5315 operand_types[j] = t->operand_types[j];
5317 /* In general, don't allow 64-bit operands in 32-bit mode. */
5318 if (i.suffix == QWORD_MNEM_SUFFIX
5319 && flag_code != CODE_64BIT
5321 ? (!t->opcode_modifier.ignoresize
5322 && !intel_float_operand (t->name))
5323 : intel_float_operand (t->name) != 2)
5324 && ((!operand_types[0].bitfield.regmmx
5325 && !operand_types[0].bitfield.regsimd)
5326 || (!operand_types[t->operands > 1].bitfield.regmmx
5327 && !operand_types[t->operands > 1].bitfield.regsimd))
5328 && (t->base_opcode != 0x0fc7
5329 || t->extension_opcode != 1 /* cmpxchg8b */))
5332 /* In general, don't allow 32-bit operands on pre-386. */
5333 else if (i.suffix == LONG_MNEM_SUFFIX
5334 && !cpu_arch_flags.bitfield.cpui386
5336 ? (!t->opcode_modifier.ignoresize
5337 && !intel_float_operand (t->name))
5338 : intel_float_operand (t->name) != 2)
5339 && ((!operand_types[0].bitfield.regmmx
5340 && !operand_types[0].bitfield.regsimd)
5341 || (!operand_types[t->operands > 1].bitfield.regmmx
5342 && !operand_types[t->operands > 1].bitfield.regsimd)))
5345 /* Do not verify operands when there are none. */
5349 /* We've found a match; break out of loop. */
5353 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5354 into Disp32/Disp16/Disp32 operand. */
5355 if (i.prefix[ADDR_PREFIX] != 0)
5357 /* There should be only one Disp operand. */
5361 for (j = 0; j < MAX_OPERANDS; j++)
5363 if (operand_types[j].bitfield.disp16)
5365 addr_prefix_disp = j;
5366 operand_types[j].bitfield.disp32 = 1;
5367 operand_types[j].bitfield.disp16 = 0;
5373 for (j = 0; j < MAX_OPERANDS; j++)
5375 if (operand_types[j].bitfield.disp32)
5377 addr_prefix_disp = j;
5378 operand_types[j].bitfield.disp32 = 0;
5379 operand_types[j].bitfield.disp16 = 1;
5385 for (j = 0; j < MAX_OPERANDS; j++)
5387 if (operand_types[j].bitfield.disp64)
5389 addr_prefix_disp = j;
5390 operand_types[j].bitfield.disp64 = 0;
5391 operand_types[j].bitfield.disp32 = 1;
5399 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5400 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5403 /* We check register size if needed. */
5404 check_register = t->opcode_modifier.checkregsize;
5405 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5406 switch (t->operands)
5409 if (!operand_type_match (overlap0, i.types[0]))
5413 /* xchg %eax, %eax is a special case. It is an alias for nop
5414 only in 32bit mode and we can use opcode 0x90. In 64bit
5415 mode, we can't use 0x90 for xchg %eax, %eax since it should
5416 zero-extend %eax to %rax. */
5417 if (flag_code == CODE_64BIT
5418 && t->base_opcode == 0x90
5419 && operand_type_equal (&i.types [0], &acc32)
5420 && operand_type_equal (&i.types [1], &acc32))
5422 /* If we want store form, we reverse direction of operands. */
5423 if (i.dir_encoding == dir_encoding_store
5424 && t->opcode_modifier.d)
5429 /* If we want store form, we skip the current load. */
5430 if (i.dir_encoding == dir_encoding_store
5431 && i.mem_operands == 0
5432 && t->opcode_modifier.load)
5437 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5438 if (!operand_type_match (overlap0, i.types[0])
5439 || !operand_type_match (overlap1, i.types[1])
5441 && !operand_type_register_match (i.types[0],
5446 /* Check if other direction is valid ... */
5447 if (!t->opcode_modifier.d)
5451 /* Try reversing direction of operands. */
5452 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5453 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5454 if (!operand_type_match (overlap0, i.types[0])
5455 || !operand_type_match (overlap1, i.types[1])
5457 && !operand_type_register_match (i.types[0],
5462 /* Does not match either direction. */
5465 /* found_reverse_match holds which of D or FloatR
5467 if (!t->opcode_modifier.d)
5468 found_reverse_match = 0;
5469 else if (operand_types[0].bitfield.tbyte)
5470 found_reverse_match = Opcode_FloatD;
5472 found_reverse_match = Opcode_D;
5473 if (t->opcode_modifier.floatr)
5474 found_reverse_match |= Opcode_FloatR;
5478 /* Found a forward 2 operand match here. */
5479 switch (t->operands)
5482 overlap4 = operand_type_and (i.types[4],
5486 overlap3 = operand_type_and (i.types[3],
5490 overlap2 = operand_type_and (i.types[2],
5495 switch (t->operands)
5498 if (!operand_type_match (overlap4, i.types[4])
5499 || !operand_type_register_match (i.types[3],
5506 if (!operand_type_match (overlap3, i.types[3])
5508 && !operand_type_register_match (i.types[2],
5515 /* Here we make use of the fact that there are no
5516 reverse match 3 operand instructions. */
5517 if (!operand_type_match (overlap2, i.types[2])
5519 && (!operand_type_register_match (i.types[0],
5523 || !operand_type_register_match (i.types[1],
5526 operand_types[2]))))
5531 /* Found either forward/reverse 2, 3 or 4 operand match here:
5532 slip through to break. */
5534 if (!found_cpu_match)
5536 found_reverse_match = 0;
5540 /* Check if vector and VEX operands are valid. */
5541 if (check_VecOperands (t) || VEX_check_operands (t))
5543 specific_error = i.error;
5547 /* We've found a match; break out of loop. */
5551 if (t == current_templates->end)
5553 /* We found no match. */
5554 const char *err_msg;
5555 switch (specific_error ? specific_error : i.error)
5559 case operand_size_mismatch:
5560 err_msg = _("operand size mismatch");
5562 case operand_type_mismatch:
5563 err_msg = _("operand type mismatch");
5565 case register_type_mismatch:
5566 err_msg = _("register type mismatch");
5568 case number_of_operands_mismatch:
5569 err_msg = _("number of operands mismatch");
5571 case invalid_instruction_suffix:
5572 err_msg = _("invalid instruction suffix");
5575 err_msg = _("constant doesn't fit in 4 bits");
5577 case unsupported_with_intel_mnemonic:
5578 err_msg = _("unsupported with Intel mnemonic");
5580 case unsupported_syntax:
5581 err_msg = _("unsupported syntax");
5584 as_bad (_("unsupported instruction `%s'"),
5585 current_templates->start->name);
5587 case invalid_vsib_address:
5588 err_msg = _("invalid VSIB address");
5590 case invalid_vector_register_set:
5591 err_msg = _("mask, index, and destination registers must be distinct");
5593 case unsupported_vector_index_register:
5594 err_msg = _("unsupported vector index register");
5596 case unsupported_broadcast:
5597 err_msg = _("unsupported broadcast");
5599 case broadcast_not_on_src_operand:
5600 err_msg = _("broadcast not on source memory operand");
5602 case broadcast_needed:
5603 err_msg = _("broadcast is needed for operand of such type");
5605 case unsupported_masking:
5606 err_msg = _("unsupported masking");
5608 case mask_not_on_destination:
5609 err_msg = _("mask not on destination operand");
5611 case no_default_mask:
5612 err_msg = _("default mask isn't allowed");
5614 case unsupported_rc_sae:
5615 err_msg = _("unsupported static rounding/sae");
5617 case rc_sae_operand_not_last_imm:
5619 err_msg = _("RC/SAE operand must precede immediate operands");
5621 err_msg = _("RC/SAE operand must follow immediate operands");
5623 case invalid_register_operand:
5624 err_msg = _("invalid register operand");
5627 as_bad (_("%s for `%s'"), err_msg,
5628 current_templates->start->name);
5632 if (!quiet_warnings)
5635 && (i.types[0].bitfield.jumpabsolute
5636 != operand_types[0].bitfield.jumpabsolute))
5638 as_warn (_("indirect %s without `*'"), t->name);
5641 if (t->opcode_modifier.isprefix
5642 && t->opcode_modifier.ignoresize)
5644 /* Warn them that a data or address size prefix doesn't
5645 affect assembly of the next line of code. */
5646 as_warn (_("stand-alone `%s' prefix"), t->name);
5650 /* Copy the template we found. */
5653 if (addr_prefix_disp != -1)
5654 i.tm.operand_types[addr_prefix_disp]
5655 = operand_types[addr_prefix_disp];
5657 if (found_reverse_match)
5659 /* If we found a reverse match we must alter the opcode
5660 direction bit. found_reverse_match holds bits to change
5661 (different for int & float insns). */
5663 i.tm.base_opcode ^= found_reverse_match;
5665 i.tm.operand_types[0] = operand_types[1];
5666 i.tm.operand_types[1] = operand_types[0];
5675 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5676 if (i.tm.operand_types[mem_op].bitfield.esseg)
5678 if (i.seg[0] != NULL && i.seg[0] != &es)
5680 as_bad (_("`%s' operand %d must use `%ses' segment"),
5686 /* There's only ever one segment override allowed per instruction.
5687 This instruction possibly has a legal segment override on the
5688 second operand, so copy the segment to where non-string
5689 instructions store it, allowing common code. */
5690 i.seg[0] = i.seg[1];
5692 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5694 if (i.seg[1] != NULL && i.seg[1] != &es)
5696 as_bad (_("`%s' operand %d must use `%ses' segment"),
5707 process_suffix (void)
5709 /* If matched instruction specifies an explicit instruction mnemonic
5711 if (i.tm.opcode_modifier.size16)
5712 i.suffix = WORD_MNEM_SUFFIX;
5713 else if (i.tm.opcode_modifier.size32)
5714 i.suffix = LONG_MNEM_SUFFIX;
5715 else if (i.tm.opcode_modifier.size64)
5716 i.suffix = QWORD_MNEM_SUFFIX;
5717 else if (i.reg_operands)
5719 /* If there's no instruction mnemonic suffix we try to invent one
5720 based on register operands. */
5723 /* We take i.suffix from the last register operand specified,
5724 Destination register type is more significant than source
5725 register type. crc32 in SSE4.2 prefers source register
5727 if (i.tm.base_opcode == 0xf20f38f1)
5729 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5730 i.suffix = WORD_MNEM_SUFFIX;
5731 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5732 i.suffix = LONG_MNEM_SUFFIX;
5733 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5734 i.suffix = QWORD_MNEM_SUFFIX;
5736 else if (i.tm.base_opcode == 0xf20f38f0)
5738 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5739 i.suffix = BYTE_MNEM_SUFFIX;
5746 if (i.tm.base_opcode == 0xf20f38f1
5747 || i.tm.base_opcode == 0xf20f38f0)
5749 /* We have to know the operand size for crc32. */
5750 as_bad (_("ambiguous memory operand size for `%s`"),
5755 for (op = i.operands; --op >= 0;)
5756 if (!i.tm.operand_types[op].bitfield.inoutportreg
5757 && !i.tm.operand_types[op].bitfield.shiftcount)
5759 if (!i.types[op].bitfield.reg)
5761 if (i.types[op].bitfield.byte)
5762 i.suffix = BYTE_MNEM_SUFFIX;
5763 else if (i.types[op].bitfield.word)
5764 i.suffix = WORD_MNEM_SUFFIX;
5765 else if (i.types[op].bitfield.dword)
5766 i.suffix = LONG_MNEM_SUFFIX;
5767 else if (i.types[op].bitfield.qword)
5768 i.suffix = QWORD_MNEM_SUFFIX;
5775 else if (i.suffix == BYTE_MNEM_SUFFIX)
5778 && i.tm.opcode_modifier.ignoresize
5779 && i.tm.opcode_modifier.no_bsuf)
5781 else if (!check_byte_reg ())
5784 else if (i.suffix == LONG_MNEM_SUFFIX)
5787 && i.tm.opcode_modifier.ignoresize
5788 && i.tm.opcode_modifier.no_lsuf)
5790 else if (!check_long_reg ())
5793 else if (i.suffix == QWORD_MNEM_SUFFIX)
5796 && i.tm.opcode_modifier.ignoresize
5797 && i.tm.opcode_modifier.no_qsuf)
5799 else if (!check_qword_reg ())
5802 else if (i.suffix == WORD_MNEM_SUFFIX)
5805 && i.tm.opcode_modifier.ignoresize
5806 && i.tm.opcode_modifier.no_wsuf)
5808 else if (!check_word_reg ())
5811 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5812 /* Do nothing if the instruction is going to ignore the prefix. */
5817 else if (i.tm.opcode_modifier.defaultsize
5819 /* exclude fldenv/frstor/fsave/fstenv */
5820 && i.tm.opcode_modifier.no_ssuf)
5822 i.suffix = stackop_size;
5824 else if (intel_syntax
5826 && (i.tm.operand_types[0].bitfield.jumpabsolute
5827 || i.tm.opcode_modifier.jumpbyte
5828 || i.tm.opcode_modifier.jumpintersegment
5829 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5830 && i.tm.extension_opcode <= 3)))
5835 if (!i.tm.opcode_modifier.no_qsuf)
5837 i.suffix = QWORD_MNEM_SUFFIX;
5842 if (!i.tm.opcode_modifier.no_lsuf)
5843 i.suffix = LONG_MNEM_SUFFIX;
5846 if (!i.tm.opcode_modifier.no_wsuf)
5847 i.suffix = WORD_MNEM_SUFFIX;
5856 if (i.tm.opcode_modifier.w)
5858 as_bad (_("no instruction mnemonic suffix given and "
5859 "no register operands; can't size instruction"));
5865 unsigned int suffixes;
5867 suffixes = !i.tm.opcode_modifier.no_bsuf;
5868 if (!i.tm.opcode_modifier.no_wsuf)
5870 if (!i.tm.opcode_modifier.no_lsuf)
5872 if (!i.tm.opcode_modifier.no_ldsuf)
5874 if (!i.tm.opcode_modifier.no_ssuf)
5876 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5879 /* There are more than suffix matches. */
5880 if (i.tm.opcode_modifier.w
5881 || ((suffixes & (suffixes - 1))
5882 && !i.tm.opcode_modifier.defaultsize
5883 && !i.tm.opcode_modifier.ignoresize))
5885 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5891 /* Change the opcode based on the operand size given by i.suffix. */
5894 /* Size floating point instruction. */
5895 case LONG_MNEM_SUFFIX:
5896 if (i.tm.opcode_modifier.floatmf)
5898 i.tm.base_opcode ^= 4;
5902 case WORD_MNEM_SUFFIX:
5903 case QWORD_MNEM_SUFFIX:
5904 /* It's not a byte, select word/dword operation. */
5905 if (i.tm.opcode_modifier.w)
5907 if (i.tm.opcode_modifier.shortform)
5908 i.tm.base_opcode |= 8;
5910 i.tm.base_opcode |= 1;
5913 case SHORT_MNEM_SUFFIX:
5914 /* Now select between word & dword operations via the operand
5915 size prefix, except for instructions that will ignore this
5917 if (i.tm.opcode_modifier.addrprefixop0)
5919 /* The address size override prefix changes the size of the
5921 if ((flag_code == CODE_32BIT
5922 && i.op->regs[0].reg_type.bitfield.word)
5923 || (flag_code != CODE_32BIT
5924 && i.op->regs[0].reg_type.bitfield.dword))
5925 if (!add_prefix (ADDR_PREFIX_OPCODE))
5928 else if (i.suffix != QWORD_MNEM_SUFFIX
5929 && !i.tm.opcode_modifier.ignoresize
5930 && !i.tm.opcode_modifier.floatmf
5931 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5932 || (flag_code == CODE_64BIT
5933 && i.tm.opcode_modifier.jumpbyte)))
5935 unsigned int prefix = DATA_PREFIX_OPCODE;
5937 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5938 prefix = ADDR_PREFIX_OPCODE;
5940 if (!add_prefix (prefix))
5944 /* Set mode64 for an operand. */
5945 if (i.suffix == QWORD_MNEM_SUFFIX
5946 && flag_code == CODE_64BIT
5947 && !i.tm.opcode_modifier.norex64
5948 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5950 && ! (i.operands == 2
5951 && i.tm.base_opcode == 0x90
5952 && i.tm.extension_opcode == None
5953 && operand_type_equal (&i.types [0], &acc64)
5954 && operand_type_equal (&i.types [1], &acc64)))
5964 check_byte_reg (void)
5968 for (op = i.operands; --op >= 0;)
5970 /* Skip non-register operands. */
5971 if (!i.types[op].bitfield.reg)
5974 /* If this is an eight bit register, it's OK. If it's the 16 or
5975 32 bit version of an eight bit register, we will just use the
5976 low portion, and that's OK too. */
5977 if (i.types[op].bitfield.byte)
5980 /* I/O port address operands are OK too. */
5981 if (i.tm.operand_types[op].bitfield.inoutportreg)
5984 /* crc32 doesn't generate this warning. */
5985 if (i.tm.base_opcode == 0xf20f38f0)
5988 if ((i.types[op].bitfield.word
5989 || i.types[op].bitfield.dword
5990 || i.types[op].bitfield.qword)
5991 && i.op[op].regs->reg_num < 4
5992 /* Prohibit these changes in 64bit mode, since the lowering
5993 would be more complicated. */
5994 && flag_code != CODE_64BIT)
5996 #if REGISTER_WARNINGS
5997 if (!quiet_warnings)
5998 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6000 (i.op[op].regs + (i.types[op].bitfield.word
6001 ? REGNAM_AL - REGNAM_AX
6002 : REGNAM_AL - REGNAM_EAX))->reg_name,
6004 i.op[op].regs->reg_name,
6009 /* Any other register is bad. */
6010 if (i.types[op].bitfield.reg
6011 || i.types[op].bitfield.regmmx
6012 || i.types[op].bitfield.regsimd
6013 || i.types[op].bitfield.sreg2
6014 || i.types[op].bitfield.sreg3
6015 || i.types[op].bitfield.control
6016 || i.types[op].bitfield.debug
6017 || i.types[op].bitfield.test)
6019 as_bad (_("`%s%s' not allowed with `%s%c'"),
6021 i.op[op].regs->reg_name,
6031 check_long_reg (void)
6035 for (op = i.operands; --op >= 0;)
6036 /* Skip non-register operands. */
6037 if (!i.types[op].bitfield.reg)
6039 /* Reject eight bit registers, except where the template requires
6040 them. (eg. movzb) */
6041 else if (i.types[op].bitfield.byte
6042 && (i.tm.operand_types[op].bitfield.reg
6043 || i.tm.operand_types[op].bitfield.acc)
6044 && (i.tm.operand_types[op].bitfield.word
6045 || i.tm.operand_types[op].bitfield.dword))
6047 as_bad (_("`%s%s' not allowed with `%s%c'"),
6049 i.op[op].regs->reg_name,
6054 /* Warn if the e prefix on a general reg is missing. */
6055 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6056 && i.types[op].bitfield.word
6057 && (i.tm.operand_types[op].bitfield.reg
6058 || i.tm.operand_types[op].bitfield.acc)
6059 && i.tm.operand_types[op].bitfield.dword)
6061 /* Prohibit these changes in the 64bit mode, since the
6062 lowering is more complicated. */
6063 if (flag_code == CODE_64BIT)
6065 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6066 register_prefix, i.op[op].regs->reg_name,
6070 #if REGISTER_WARNINGS
6071 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6073 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6074 register_prefix, i.op[op].regs->reg_name, i.suffix);
6077 /* Warn if the r prefix on a general reg is present. */
6078 else if (i.types[op].bitfield.qword
6079 && (i.tm.operand_types[op].bitfield.reg
6080 || i.tm.operand_types[op].bitfield.acc)
6081 && i.tm.operand_types[op].bitfield.dword)
6084 && i.tm.opcode_modifier.toqword
6085 && !i.types[0].bitfield.regsimd)
6087 /* Convert to QWORD. We want REX byte. */
6088 i.suffix = QWORD_MNEM_SUFFIX;
6092 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6093 register_prefix, i.op[op].regs->reg_name,
6102 check_qword_reg (void)
6106 for (op = i.operands; --op >= 0; )
6107 /* Skip non-register operands. */
6108 if (!i.types[op].bitfield.reg)
6110 /* Reject eight bit registers, except where the template requires
6111 them. (eg. movzb) */
6112 else if (i.types[op].bitfield.byte
6113 && (i.tm.operand_types[op].bitfield.reg
6114 || i.tm.operand_types[op].bitfield.acc)
6115 && (i.tm.operand_types[op].bitfield.word
6116 || i.tm.operand_types[op].bitfield.dword))
6118 as_bad (_("`%s%s' not allowed with `%s%c'"),
6120 i.op[op].regs->reg_name,
6125 /* Warn if the r prefix on a general reg is missing. */
6126 else if ((i.types[op].bitfield.word
6127 || i.types[op].bitfield.dword)
6128 && (i.tm.operand_types[op].bitfield.reg
6129 || i.tm.operand_types[op].bitfield.acc)
6130 && i.tm.operand_types[op].bitfield.qword)
6132 /* Prohibit these changes in the 64bit mode, since the
6133 lowering is more complicated. */
6135 && i.tm.opcode_modifier.todword
6136 && !i.types[0].bitfield.regsimd)
6138 /* Convert to DWORD. We don't want REX byte. */
6139 i.suffix = LONG_MNEM_SUFFIX;
6143 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6144 register_prefix, i.op[op].regs->reg_name,
6153 check_word_reg (void)
6156 for (op = i.operands; --op >= 0;)
6157 /* Skip non-register operands. */
6158 if (!i.types[op].bitfield.reg)
6160 /* Reject eight bit registers, except where the template requires
6161 them. (eg. movzb) */
6162 else if (i.types[op].bitfield.byte
6163 && (i.tm.operand_types[op].bitfield.reg
6164 || i.tm.operand_types[op].bitfield.acc)
6165 && (i.tm.operand_types[op].bitfield.word
6166 || i.tm.operand_types[op].bitfield.dword))
6168 as_bad (_("`%s%s' not allowed with `%s%c'"),
6170 i.op[op].regs->reg_name,
6175 /* Warn if the e or r prefix on a general reg is present. */
6176 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6177 && (i.types[op].bitfield.dword
6178 || i.types[op].bitfield.qword)
6179 && (i.tm.operand_types[op].bitfield.reg
6180 || i.tm.operand_types[op].bitfield.acc)
6181 && i.tm.operand_types[op].bitfield.word)
6183 /* Prohibit these changes in the 64bit mode, since the
6184 lowering is more complicated. */
6185 if (flag_code == CODE_64BIT)
6187 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6188 register_prefix, i.op[op].regs->reg_name,
6192 #if REGISTER_WARNINGS
6193 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6195 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6196 register_prefix, i.op[op].regs->reg_name, i.suffix);
6203 update_imm (unsigned int j)
6205 i386_operand_type overlap = i.types[j];
6206 if ((overlap.bitfield.imm8
6207 || overlap.bitfield.imm8s
6208 || overlap.bitfield.imm16
6209 || overlap.bitfield.imm32
6210 || overlap.bitfield.imm32s
6211 || overlap.bitfield.imm64)
6212 && !operand_type_equal (&overlap, &imm8)
6213 && !operand_type_equal (&overlap, &imm8s)
6214 && !operand_type_equal (&overlap, &imm16)
6215 && !operand_type_equal (&overlap, &imm32)
6216 && !operand_type_equal (&overlap, &imm32s)
6217 && !operand_type_equal (&overlap, &imm64))
6221 i386_operand_type temp;
6223 operand_type_set (&temp, 0);
6224 if (i.suffix == BYTE_MNEM_SUFFIX)
6226 temp.bitfield.imm8 = overlap.bitfield.imm8;
6227 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6229 else if (i.suffix == WORD_MNEM_SUFFIX)
6230 temp.bitfield.imm16 = overlap.bitfield.imm16;
6231 else if (i.suffix == QWORD_MNEM_SUFFIX)
6233 temp.bitfield.imm64 = overlap.bitfield.imm64;
6234 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6237 temp.bitfield.imm32 = overlap.bitfield.imm32;
6240 else if (operand_type_equal (&overlap, &imm16_32_32s)
6241 || operand_type_equal (&overlap, &imm16_32)
6242 || operand_type_equal (&overlap, &imm16_32s))
6244 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6249 if (!operand_type_equal (&overlap, &imm8)
6250 && !operand_type_equal (&overlap, &imm8s)
6251 && !operand_type_equal (&overlap, &imm16)
6252 && !operand_type_equal (&overlap, &imm32)
6253 && !operand_type_equal (&overlap, &imm32s)
6254 && !operand_type_equal (&overlap, &imm64))
6256 as_bad (_("no instruction mnemonic suffix given; "
6257 "can't determine immediate size"));
6261 i.types[j] = overlap;
6271 /* Update the first 2 immediate operands. */
6272 n = i.operands > 2 ? 2 : i.operands;
6275 for (j = 0; j < n; j++)
6276 if (update_imm (j) == 0)
6279 /* The 3rd operand can't be immediate operand. */
6280 gas_assert (operand_type_check (i.types[2], imm) == 0);
6287 process_operands (void)
6289 /* Default segment register this instruction will use for memory
6290 accesses. 0 means unknown. This is only for optimizing out
6291 unnecessary segment overrides. */
6292 const seg_entry *default_seg = 0;
6294 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6296 unsigned int dupl = i.operands;
6297 unsigned int dest = dupl - 1;
6300 /* The destination must be an xmm register. */
6301 gas_assert (i.reg_operands
6302 && MAX_OPERANDS > dupl
6303 && operand_type_equal (&i.types[dest], ®xmm));
6305 if (i.tm.operand_types[0].bitfield.acc
6306 && i.tm.operand_types[0].bitfield.xmmword)
6308 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6310 /* Keep xmm0 for instructions with VEX prefix and 3
6312 i.tm.operand_types[0].bitfield.acc = 0;
6313 i.tm.operand_types[0].bitfield.regsimd = 1;
6318 /* We remove the first xmm0 and keep the number of
6319 operands unchanged, which in fact duplicates the
6321 for (j = 1; j < i.operands; j++)
6323 i.op[j - 1] = i.op[j];
6324 i.types[j - 1] = i.types[j];
6325 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6329 else if (i.tm.opcode_modifier.implicit1stxmm0)
6331 gas_assert ((MAX_OPERANDS - 1) > dupl
6332 && (i.tm.opcode_modifier.vexsources
6335 /* Add the implicit xmm0 for instructions with VEX prefix
6337 for (j = i.operands; j > 0; j--)
6339 i.op[j] = i.op[j - 1];
6340 i.types[j] = i.types[j - 1];
6341 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6344 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6345 i.types[0] = regxmm;
6346 i.tm.operand_types[0] = regxmm;
6349 i.reg_operands += 2;
6354 i.op[dupl] = i.op[dest];
6355 i.types[dupl] = i.types[dest];
6356 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6365 i.op[dupl] = i.op[dest];
6366 i.types[dupl] = i.types[dest];
6367 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6370 if (i.tm.opcode_modifier.immext)
6373 else if (i.tm.operand_types[0].bitfield.acc
6374 && i.tm.operand_types[0].bitfield.xmmword)
6378 for (j = 1; j < i.operands; j++)
6380 i.op[j - 1] = i.op[j];
6381 i.types[j - 1] = i.types[j];
6383 /* We need to adjust fields in i.tm since they are used by
6384 build_modrm_byte. */
6385 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6392 else if (i.tm.opcode_modifier.implicitquadgroup)
6394 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6396 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6397 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6398 regnum = register_number (i.op[1].regs);
6399 first_reg_in_group = regnum & ~3;
6400 last_reg_in_group = first_reg_in_group + 3;
6401 if (regnum != first_reg_in_group)
6402 as_warn (_("source register `%s%s' implicitly denotes"
6403 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6404 register_prefix, i.op[1].regs->reg_name,
6405 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6406 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6409 else if (i.tm.opcode_modifier.regkludge)
6411 /* The imul $imm, %reg instruction is converted into
6412 imul $imm, %reg, %reg, and the clr %reg instruction
6413 is converted into xor %reg, %reg. */
6415 unsigned int first_reg_op;
6417 if (operand_type_check (i.types[0], reg))
6421 /* Pretend we saw the extra register operand. */
6422 gas_assert (i.reg_operands == 1
6423 && i.op[first_reg_op + 1].regs == 0);
6424 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6425 i.types[first_reg_op + 1] = i.types[first_reg_op];
6430 if (i.tm.opcode_modifier.shortform)
6432 if (i.types[0].bitfield.sreg2
6433 || i.types[0].bitfield.sreg3)
6435 if (i.tm.base_opcode == POP_SEG_SHORT
6436 && i.op[0].regs->reg_num == 1)
6438 as_bad (_("you can't `pop %scs'"), register_prefix);
6441 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6442 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6447 /* The register or float register operand is in operand
6451 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6452 || operand_type_check (i.types[0], reg))
6456 /* Register goes in low 3 bits of opcode. */
6457 i.tm.base_opcode |= i.op[op].regs->reg_num;
6458 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6460 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6462 /* Warn about some common errors, but press on regardless.
6463 The first case can be generated by gcc (<= 2.8.1). */
6464 if (i.operands == 2)
6466 /* Reversed arguments on faddp, fsubp, etc. */
6467 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6468 register_prefix, i.op[!intel_syntax].regs->reg_name,
6469 register_prefix, i.op[intel_syntax].regs->reg_name);
6473 /* Extraneous `l' suffix on fp insn. */
6474 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6475 register_prefix, i.op[0].regs->reg_name);
6480 else if (i.tm.opcode_modifier.modrm)
6482 /* The opcode is completed (modulo i.tm.extension_opcode which
6483 must be put into the modrm byte). Now, we make the modrm and
6484 index base bytes based on all the info we've collected. */
6486 default_seg = build_modrm_byte ();
6488 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6492 else if (i.tm.opcode_modifier.isstring)
6494 /* For the string instructions that allow a segment override
6495 on one of their operands, the default segment is ds. */
6499 if (i.tm.base_opcode == 0x8d /* lea */
6502 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6504 /* If a segment was explicitly specified, and the specified segment
6505 is not the default, use an opcode prefix to select it. If we
6506 never figured out what the default segment is, then default_seg
6507 will be zero at this point, and the specified segment prefix will
6509 if ((i.seg[0]) && (i.seg[0] != default_seg))
6511 if (!add_prefix (i.seg[0]->seg_prefix))
6517 static const seg_entry *
6518 build_modrm_byte (void)
6520 const seg_entry *default_seg = 0;
6521 unsigned int source, dest;
6524 /* The first operand of instructions with VEX prefix and 3 sources
6525 must be VEX_Imm4. */
6526 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6529 unsigned int nds, reg_slot;
6532 if (i.tm.opcode_modifier.veximmext
6533 && i.tm.opcode_modifier.immext)
6535 dest = i.operands - 2;
6536 gas_assert (dest == 3);
6539 dest = i.operands - 1;
6542 /* There are 2 kinds of instructions:
6543 1. 5 operands: 4 register operands or 3 register operands
6544 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6545 VexW0 or VexW1. The destination must be either XMM, YMM or
6547 2. 4 operands: 4 register operands or 3 register operands
6548 plus 1 memory operand, VexXDS, and VexImmExt */
6549 gas_assert ((i.reg_operands == 4
6550 || (i.reg_operands == 3 && i.mem_operands == 1))
6551 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6552 && (i.tm.opcode_modifier.veximmext
6553 || (i.imm_operands == 1
6554 && i.types[0].bitfield.vec_imm4
6555 && (i.tm.opcode_modifier.vexw == VEXW0
6556 || i.tm.opcode_modifier.vexw == VEXW1)
6557 && i.tm.operand_types[dest].bitfield.regsimd)));
6559 if (i.imm_operands == 0)
6561 /* When there is no immediate operand, generate an 8bit
6562 immediate operand to encode the first operand. */
6563 exp = &im_expressions[i.imm_operands++];
6564 i.op[i.operands].imms = exp;
6565 i.types[i.operands] = imm8;
6567 /* If VexW1 is set, the first operand is the source and
6568 the second operand is encoded in the immediate operand. */
6569 if (i.tm.opcode_modifier.vexw == VEXW1)
6580 /* FMA swaps REG and NDS. */
6581 if (i.tm.cpu_flags.bitfield.cpufma)
6589 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6590 exp->X_op = O_constant;
6591 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6592 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6596 unsigned int imm_slot;
6598 if (i.tm.opcode_modifier.vexw == VEXW0)
6600 /* If VexW0 is set, the third operand is the source and
6601 the second operand is encoded in the immediate
6608 /* VexW1 is set, the second operand is the source and
6609 the third operand is encoded in the immediate
6615 if (i.tm.opcode_modifier.immext)
6617 /* When ImmExt is set, the immediate byte is the last
6619 imm_slot = i.operands - 1;
6627 /* Turn on Imm8 so that output_imm will generate it. */
6628 i.types[imm_slot].bitfield.imm8 = 1;
6631 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6632 i.op[imm_slot].imms->X_add_number
6633 |= register_number (i.op[reg_slot].regs) << 4;
6634 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6637 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6638 i.vex.register_specifier = i.op[nds].regs;
6643 /* i.reg_operands MUST be the number of real register operands;
6644 implicit registers do not count. If there are 3 register
6645 operands, it must be a instruction with VexNDS. For a
6646 instruction with VexNDD, the destination register is encoded
6647 in VEX prefix. If there are 4 register operands, it must be
6648 a instruction with VEX prefix and 3 sources. */
6649 if (i.mem_operands == 0
6650 && ((i.reg_operands == 2
6651 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6652 || (i.reg_operands == 3
6653 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6654 || (i.reg_operands == 4 && vex_3_sources)))
6662 /* When there are 3 operands, one of them may be immediate,
6663 which may be the first or the last operand. Otherwise,
6664 the first operand must be shift count register (cl) or it
6665 is an instruction with VexNDS. */
6666 gas_assert (i.imm_operands == 1
6667 || (i.imm_operands == 0
6668 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6669 || i.types[0].bitfield.shiftcount)));
6670 if (operand_type_check (i.types[0], imm)
6671 || i.types[0].bitfield.shiftcount)
6677 /* When there are 4 operands, the first two must be 8bit
6678 immediate operands. The source operand will be the 3rd
6681 For instructions with VexNDS, if the first operand
6682 an imm8, the source operand is the 2nd one. If the last
6683 operand is imm8, the source operand is the first one. */
6684 gas_assert ((i.imm_operands == 2
6685 && i.types[0].bitfield.imm8
6686 && i.types[1].bitfield.imm8)
6687 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6688 && i.imm_operands == 1
6689 && (i.types[0].bitfield.imm8
6690 || i.types[i.operands - 1].bitfield.imm8
6692 if (i.imm_operands == 2)
6696 if (i.types[0].bitfield.imm8)
6703 if (is_evex_encoding (&i.tm))
6705 /* For EVEX instructions, when there are 5 operands, the
6706 first one must be immediate operand. If the second one
6707 is immediate operand, the source operand is the 3th
6708 one. If the last one is immediate operand, the source
6709 operand is the 2nd one. */
6710 gas_assert (i.imm_operands == 2
6711 && i.tm.opcode_modifier.sae
6712 && operand_type_check (i.types[0], imm));
6713 if (operand_type_check (i.types[1], imm))
6715 else if (operand_type_check (i.types[4], imm))
6729 /* RC/SAE operand could be between DEST and SRC. That happens
6730 when one operand is GPR and the other one is XMM/YMM/ZMM
6732 if (i.rounding && i.rounding->operand == (int) dest)
6735 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6737 /* For instructions with VexNDS, the register-only source
6738 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6739 register. It is encoded in VEX prefix. We need to
6740 clear RegMem bit before calling operand_type_equal. */
6742 i386_operand_type op;
6745 /* Check register-only source operand when two source
6746 operands are swapped. */
6747 if (!i.tm.operand_types[source].bitfield.baseindex
6748 && i.tm.operand_types[dest].bitfield.baseindex)
6756 op = i.tm.operand_types[vvvv];
6757 op.bitfield.regmem = 0;
6758 if ((dest + 1) >= i.operands
6759 || ((!op.bitfield.reg
6760 || (!op.bitfield.dword && !op.bitfield.qword))
6761 && !op.bitfield.regsimd
6762 && !operand_type_equal (&op, ®mask)))
6764 i.vex.register_specifier = i.op[vvvv].regs;
6770 /* One of the register operands will be encoded in the i.tm.reg
6771 field, the other in the combined i.tm.mode and i.tm.regmem
6772 fields. If no form of this instruction supports a memory
6773 destination operand, then we assume the source operand may
6774 sometimes be a memory operand and so we need to store the
6775 destination in the i.rm.reg field. */
6776 if (!i.tm.operand_types[dest].bitfield.regmem
6777 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6779 i.rm.reg = i.op[dest].regs->reg_num;
6780 i.rm.regmem = i.op[source].regs->reg_num;
6781 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6783 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6785 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6787 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6792 i.rm.reg = i.op[source].regs->reg_num;
6793 i.rm.regmem = i.op[dest].regs->reg_num;
6794 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6796 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6798 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6800 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6803 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6805 if (!i.types[0].bitfield.control
6806 && !i.types[1].bitfield.control)
6808 i.rex &= ~(REX_R | REX_B);
6809 add_prefix (LOCK_PREFIX_OPCODE);
6813 { /* If it's not 2 reg operands... */
6818 unsigned int fake_zero_displacement = 0;
6821 for (op = 0; op < i.operands; op++)
6822 if (operand_type_check (i.types[op], anymem))
6824 gas_assert (op < i.operands);
6826 if (i.tm.opcode_modifier.vecsib)
6828 if (i.index_reg->reg_num == RegEiz
6829 || i.index_reg->reg_num == RegRiz)
6832 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6835 i.sib.base = NO_BASE_REGISTER;
6836 i.sib.scale = i.log2_scale_factor;
6837 i.types[op].bitfield.disp8 = 0;
6838 i.types[op].bitfield.disp16 = 0;
6839 i.types[op].bitfield.disp64 = 0;
6840 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6842 /* Must be 32 bit */
6843 i.types[op].bitfield.disp32 = 1;
6844 i.types[op].bitfield.disp32s = 0;
6848 i.types[op].bitfield.disp32 = 0;
6849 i.types[op].bitfield.disp32s = 1;
6852 i.sib.index = i.index_reg->reg_num;
6853 if ((i.index_reg->reg_flags & RegRex) != 0)
6855 if ((i.index_reg->reg_flags & RegVRex) != 0)
6861 if (i.base_reg == 0)
6864 if (!i.disp_operands)
6865 fake_zero_displacement = 1;
6866 if (i.index_reg == 0)
6868 i386_operand_type newdisp;
6870 gas_assert (!i.tm.opcode_modifier.vecsib);
6871 /* Operand is just <disp> */
6872 if (flag_code == CODE_64BIT)
6874 /* 64bit mode overwrites the 32bit absolute
6875 addressing by RIP relative addressing and
6876 absolute addressing is encoded by one of the
6877 redundant SIB forms. */
6878 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6879 i.sib.base = NO_BASE_REGISTER;
6880 i.sib.index = NO_INDEX_REGISTER;
6881 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6883 else if ((flag_code == CODE_16BIT)
6884 ^ (i.prefix[ADDR_PREFIX] != 0))
6886 i.rm.regmem = NO_BASE_REGISTER_16;
6891 i.rm.regmem = NO_BASE_REGISTER;
6894 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6895 i.types[op] = operand_type_or (i.types[op], newdisp);
6897 else if (!i.tm.opcode_modifier.vecsib)
6899 /* !i.base_reg && i.index_reg */
6900 if (i.index_reg->reg_num == RegEiz
6901 || i.index_reg->reg_num == RegRiz)
6902 i.sib.index = NO_INDEX_REGISTER;
6904 i.sib.index = i.index_reg->reg_num;
6905 i.sib.base = NO_BASE_REGISTER;
6906 i.sib.scale = i.log2_scale_factor;
6907 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6908 i.types[op].bitfield.disp8 = 0;
6909 i.types[op].bitfield.disp16 = 0;
6910 i.types[op].bitfield.disp64 = 0;
6911 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6913 /* Must be 32 bit */
6914 i.types[op].bitfield.disp32 = 1;
6915 i.types[op].bitfield.disp32s = 0;
6919 i.types[op].bitfield.disp32 = 0;
6920 i.types[op].bitfield.disp32s = 1;
6922 if ((i.index_reg->reg_flags & RegRex) != 0)
6926 /* RIP addressing for 64bit mode. */
6927 else if (i.base_reg->reg_num == RegRip ||
6928 i.base_reg->reg_num == RegEip)
6930 gas_assert (!i.tm.opcode_modifier.vecsib);
6931 i.rm.regmem = NO_BASE_REGISTER;
6932 i.types[op].bitfield.disp8 = 0;
6933 i.types[op].bitfield.disp16 = 0;
6934 i.types[op].bitfield.disp32 = 0;
6935 i.types[op].bitfield.disp32s = 1;
6936 i.types[op].bitfield.disp64 = 0;
6937 i.flags[op] |= Operand_PCrel;
6938 if (! i.disp_operands)
6939 fake_zero_displacement = 1;
6941 else if (i.base_reg->reg_type.bitfield.word)
6943 gas_assert (!i.tm.opcode_modifier.vecsib);
6944 switch (i.base_reg->reg_num)
6947 if (i.index_reg == 0)
6949 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6950 i.rm.regmem = i.index_reg->reg_num - 6;
6954 if (i.index_reg == 0)
6957 if (operand_type_check (i.types[op], disp) == 0)
6959 /* fake (%bp) into 0(%bp) */
6960 i.types[op].bitfield.disp8 = 1;
6961 fake_zero_displacement = 1;
6964 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6965 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6967 default: /* (%si) -> 4 or (%di) -> 5 */
6968 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6970 i.rm.mode = mode_from_disp_size (i.types[op]);
6972 else /* i.base_reg and 32/64 bit mode */
6974 if (flag_code == CODE_64BIT
6975 && operand_type_check (i.types[op], disp))
6977 i.types[op].bitfield.disp16 = 0;
6978 i.types[op].bitfield.disp64 = 0;
6979 if (i.prefix[ADDR_PREFIX] == 0)
6981 i.types[op].bitfield.disp32 = 0;
6982 i.types[op].bitfield.disp32s = 1;
6986 i.types[op].bitfield.disp32 = 1;
6987 i.types[op].bitfield.disp32s = 0;
6991 if (!i.tm.opcode_modifier.vecsib)
6992 i.rm.regmem = i.base_reg->reg_num;
6993 if ((i.base_reg->reg_flags & RegRex) != 0)
6995 i.sib.base = i.base_reg->reg_num;
6996 /* x86-64 ignores REX prefix bit here to avoid decoder
6998 if (!(i.base_reg->reg_flags & RegRex)
6999 && (i.base_reg->reg_num == EBP_REG_NUM
7000 || i.base_reg->reg_num == ESP_REG_NUM))
7002 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7004 fake_zero_displacement = 1;
7005 i.types[op].bitfield.disp8 = 1;
7007 i.sib.scale = i.log2_scale_factor;
7008 if (i.index_reg == 0)
7010 gas_assert (!i.tm.opcode_modifier.vecsib);
7011 /* <disp>(%esp) becomes two byte modrm with no index
7012 register. We've already stored the code for esp
7013 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7014 Any base register besides %esp will not use the
7015 extra modrm byte. */
7016 i.sib.index = NO_INDEX_REGISTER;
7018 else if (!i.tm.opcode_modifier.vecsib)
7020 if (i.index_reg->reg_num == RegEiz
7021 || i.index_reg->reg_num == RegRiz)
7022 i.sib.index = NO_INDEX_REGISTER;
7024 i.sib.index = i.index_reg->reg_num;
7025 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7026 if ((i.index_reg->reg_flags & RegRex) != 0)
7031 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7032 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7036 if (!fake_zero_displacement
7040 fake_zero_displacement = 1;
7041 if (i.disp_encoding == disp_encoding_8bit)
7042 i.types[op].bitfield.disp8 = 1;
7044 i.types[op].bitfield.disp32 = 1;
7046 i.rm.mode = mode_from_disp_size (i.types[op]);
7050 if (fake_zero_displacement)
7052 /* Fakes a zero displacement assuming that i.types[op]
7053 holds the correct displacement size. */
7056 gas_assert (i.op[op].disps == 0);
7057 exp = &disp_expressions[i.disp_operands++];
7058 i.op[op].disps = exp;
7059 exp->X_op = O_constant;
7060 exp->X_add_number = 0;
7061 exp->X_add_symbol = (symbolS *) 0;
7062 exp->X_op_symbol = (symbolS *) 0;
7070 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7072 if (operand_type_check (i.types[0], imm))
7073 i.vex.register_specifier = NULL;
7076 /* VEX.vvvv encodes one of the sources when the first
7077 operand is not an immediate. */
7078 if (i.tm.opcode_modifier.vexw == VEXW0)
7079 i.vex.register_specifier = i.op[0].regs;
7081 i.vex.register_specifier = i.op[1].regs;
7084 /* Destination is a XMM register encoded in the ModRM.reg
7086 i.rm.reg = i.op[2].regs->reg_num;
7087 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7090 /* ModRM.rm and VEX.B encodes the other source. */
7091 if (!i.mem_operands)
7095 if (i.tm.opcode_modifier.vexw == VEXW0)
7096 i.rm.regmem = i.op[1].regs->reg_num;
7098 i.rm.regmem = i.op[0].regs->reg_num;
7100 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7104 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7106 i.vex.register_specifier = i.op[2].regs;
7107 if (!i.mem_operands)
7110 i.rm.regmem = i.op[1].regs->reg_num;
7111 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7115 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7116 (if any) based on i.tm.extension_opcode. Again, we must be
7117 careful to make sure that segment/control/debug/test/MMX
7118 registers are coded into the i.rm.reg field. */
7119 else if (i.reg_operands)
7122 unsigned int vex_reg = ~0;
7124 for (op = 0; op < i.operands; op++)
7125 if (i.types[op].bitfield.reg
7126 || i.types[op].bitfield.regmmx
7127 || i.types[op].bitfield.regsimd
7128 || i.types[op].bitfield.regbnd
7129 || i.types[op].bitfield.regmask
7130 || i.types[op].bitfield.sreg2
7131 || i.types[op].bitfield.sreg3
7132 || i.types[op].bitfield.control
7133 || i.types[op].bitfield.debug
7134 || i.types[op].bitfield.test)
7139 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7141 /* For instructions with VexNDS, the register-only
7142 source operand is encoded in VEX prefix. */
7143 gas_assert (mem != (unsigned int) ~0);
7148 gas_assert (op < i.operands);
7152 /* Check register-only source operand when two source
7153 operands are swapped. */
7154 if (!i.tm.operand_types[op].bitfield.baseindex
7155 && i.tm.operand_types[op + 1].bitfield.baseindex)
7159 gas_assert (mem == (vex_reg + 1)
7160 && op < i.operands);
7165 gas_assert (vex_reg < i.operands);
7169 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7171 /* For instructions with VexNDD, the register destination
7172 is encoded in VEX prefix. */
7173 if (i.mem_operands == 0)
7175 /* There is no memory operand. */
7176 gas_assert ((op + 2) == i.operands);
7181 /* There are only 2 non-immediate operands. */
7182 gas_assert (op < i.imm_operands + 2
7183 && i.operands == i.imm_operands + 2);
7184 vex_reg = i.imm_operands + 1;
7188 gas_assert (op < i.operands);
7190 if (vex_reg != (unsigned int) ~0)
7192 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7194 if ((!type->bitfield.reg
7195 || (!type->bitfield.dword && !type->bitfield.qword))
7196 && !type->bitfield.regsimd
7197 && !operand_type_equal (type, ®mask))
7200 i.vex.register_specifier = i.op[vex_reg].regs;
7203 /* Don't set OP operand twice. */
7206 /* If there is an extension opcode to put here, the
7207 register number must be put into the regmem field. */
7208 if (i.tm.extension_opcode != None)
7210 i.rm.regmem = i.op[op].regs->reg_num;
7211 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7213 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7218 i.rm.reg = i.op[op].regs->reg_num;
7219 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7221 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7226 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7227 must set it to 3 to indicate this is a register operand
7228 in the regmem field. */
7229 if (!i.mem_operands)
7233 /* Fill in i.rm.reg field with extension opcode (if any). */
7234 if (i.tm.extension_opcode != None)
7235 i.rm.reg = i.tm.extension_opcode;
7241 output_branch (void)
7247 relax_substateT subtype;
7251 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7252 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7255 if (i.prefix[DATA_PREFIX] != 0)
7261 /* Pentium4 branch hints. */
7262 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7263 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7268 if (i.prefix[REX_PREFIX] != 0)
7274 /* BND prefixed jump. */
7275 if (i.prefix[BND_PREFIX] != 0)
7277 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7281 if (i.prefixes != 0 && !intel_syntax)
7282 as_warn (_("skipping prefixes on this instruction"));
7284 /* It's always a symbol; End frag & setup for relax.
7285 Make sure there is enough room in this frag for the largest
7286 instruction we may generate in md_convert_frag. This is 2
7287 bytes for the opcode and room for the prefix and largest
7289 frag_grow (prefix + 2 + 4);
7290 /* Prefix and 1 opcode byte go in fr_fix. */
7291 p = frag_more (prefix + 1);
7292 if (i.prefix[DATA_PREFIX] != 0)
7293 *p++ = DATA_PREFIX_OPCODE;
7294 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7295 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7296 *p++ = i.prefix[SEG_PREFIX];
7297 if (i.prefix[REX_PREFIX] != 0)
7298 *p++ = i.prefix[REX_PREFIX];
7299 *p = i.tm.base_opcode;
7301 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7302 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7303 else if (cpu_arch_flags.bitfield.cpui386)
7304 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7306 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7309 sym = i.op[0].disps->X_add_symbol;
7310 off = i.op[0].disps->X_add_number;
7312 if (i.op[0].disps->X_op != O_constant
7313 && i.op[0].disps->X_op != O_symbol)
7315 /* Handle complex expressions. */
7316 sym = make_expr_symbol (i.op[0].disps);
7320 /* 1 possible extra opcode + 4 byte displacement go in var part.
7321 Pass reloc in fr_var. */
7322 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7326 /* Return TRUE iff PLT32 relocation should be used for branching to
7330 need_plt32_p (symbolS *s)
7332 /* PLT32 relocation is ELF only. */
7336 /* Since there is no need to prepare for PLT branch on x86-64, we
7337 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7338 be used as a marker for 32-bit PC-relative branches. */
7342 /* Weak or undefined symbol need PLT32 relocation. */
7343 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7346 /* Non-global symbol doesn't need PLT32 relocation. */
7347 if (! S_IS_EXTERNAL (s))
7350 /* Other global symbols need PLT32 relocation. NB: Symbol with
7351 non-default visibilities are treated as normal global symbol
7352 so that PLT32 relocation can be used as a marker for 32-bit
7353 PC-relative branches. It is useful for linker relaxation. */
7364 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7366 if (i.tm.opcode_modifier.jumpbyte)
7368 /* This is a loop or jecxz type instruction. */
7370 if (i.prefix[ADDR_PREFIX] != 0)
7372 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7375 /* Pentium4 branch hints. */
7376 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7377 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7379 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7388 if (flag_code == CODE_16BIT)
7391 if (i.prefix[DATA_PREFIX] != 0)
7393 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7403 if (i.prefix[REX_PREFIX] != 0)
7405 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7409 /* BND prefixed jump. */
7410 if (i.prefix[BND_PREFIX] != 0)
7412 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7416 if (i.prefixes != 0 && !intel_syntax)
7417 as_warn (_("skipping prefixes on this instruction"));
7419 p = frag_more (i.tm.opcode_length + size);
7420 switch (i.tm.opcode_length)
7423 *p++ = i.tm.base_opcode >> 8;
7426 *p++ = i.tm.base_opcode;
7432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7434 && jump_reloc == NO_RELOC
7435 && need_plt32_p (i.op[0].disps->X_add_symbol))
7436 jump_reloc = BFD_RELOC_X86_64_PLT32;
7439 jump_reloc = reloc (size, 1, 1, jump_reloc);
7441 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7442 i.op[0].disps, 1, jump_reloc);
7444 /* All jumps handled here are signed, but don't use a signed limit
7445 check for 32 and 16 bit jumps as we want to allow wrap around at
7446 4G and 64k respectively. */
7448 fixP->fx_signed = 1;
7452 output_interseg_jump (void)
7460 if (flag_code == CODE_16BIT)
7464 if (i.prefix[DATA_PREFIX] != 0)
7470 if (i.prefix[REX_PREFIX] != 0)
7480 if (i.prefixes != 0 && !intel_syntax)
7481 as_warn (_("skipping prefixes on this instruction"));
7483 /* 1 opcode; 2 segment; offset */
7484 p = frag_more (prefix + 1 + 2 + size);
7486 if (i.prefix[DATA_PREFIX] != 0)
7487 *p++ = DATA_PREFIX_OPCODE;
7489 if (i.prefix[REX_PREFIX] != 0)
7490 *p++ = i.prefix[REX_PREFIX];
7492 *p++ = i.tm.base_opcode;
7493 if (i.op[1].imms->X_op == O_constant)
7495 offsetT n = i.op[1].imms->X_add_number;
7498 && !fits_in_unsigned_word (n)
7499 && !fits_in_signed_word (n))
7501 as_bad (_("16-bit jump out of range"));
7504 md_number_to_chars (p, n, size);
7507 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7508 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7509 if (i.op[0].imms->X_op != O_constant)
7510 as_bad (_("can't handle non absolute segment in `%s'"),
7512 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7518 fragS *insn_start_frag;
7519 offsetT insn_start_off;
7521 /* Tie dwarf2 debug info to the address at the start of the insn.
7522 We can't do this after the insn has been output as the current
7523 frag may have been closed off. eg. by frag_var. */
7524 dwarf2_emit_insn (0);
7526 insn_start_frag = frag_now;
7527 insn_start_off = frag_now_fix ();
7530 if (i.tm.opcode_modifier.jump)
7532 else if (i.tm.opcode_modifier.jumpbyte
7533 || i.tm.opcode_modifier.jumpdword)
7535 else if (i.tm.opcode_modifier.jumpintersegment)
7536 output_interseg_jump ();
7539 /* Output normal instructions here. */
7543 unsigned int prefix;
7546 && i.tm.base_opcode == 0xfae
7548 && i.imm_operands == 1
7549 && (i.op[0].imms->X_add_number == 0xe8
7550 || i.op[0].imms->X_add_number == 0xf0
7551 || i.op[0].imms->X_add_number == 0xf8))
7553 /* Encode lfence, mfence, and sfence as
7554 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7555 offsetT val = 0x240483f0ULL;
7557 md_number_to_chars (p, val, 5);
7561 /* Some processors fail on LOCK prefix. This options makes
7562 assembler ignore LOCK prefix and serves as a workaround. */
7563 if (omit_lock_prefix)
7565 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7567 i.prefix[LOCK_PREFIX] = 0;
7570 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7571 don't need the explicit prefix. */
7572 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7574 switch (i.tm.opcode_length)
7577 if (i.tm.base_opcode & 0xff000000)
7579 prefix = (i.tm.base_opcode >> 24) & 0xff;
7584 if ((i.tm.base_opcode & 0xff0000) != 0)
7586 prefix = (i.tm.base_opcode >> 16) & 0xff;
7587 if (i.tm.cpu_flags.bitfield.cpupadlock)
7590 if (prefix != REPE_PREFIX_OPCODE
7591 || (i.prefix[REP_PREFIX]
7592 != REPE_PREFIX_OPCODE))
7593 add_prefix (prefix);
7596 add_prefix (prefix);
7602 /* Check for pseudo prefixes. */
7603 as_bad_where (insn_start_frag->fr_file,
7604 insn_start_frag->fr_line,
7605 _("pseudo prefix without instruction"));
7611 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7612 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7613 R_X86_64_GOTTPOFF relocation so that linker can safely
7614 perform IE->LE optimization. */
7615 if (x86_elf_abi == X86_64_X32_ABI
7617 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7618 && i.prefix[REX_PREFIX] == 0)
7619 add_prefix (REX_OPCODE);
7622 /* The prefix bytes. */
7623 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7625 FRAG_APPEND_1_CHAR (*q);
7629 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7634 /* REX byte is encoded in VEX prefix. */
7638 FRAG_APPEND_1_CHAR (*q);
7641 /* There should be no other prefixes for instructions
7646 /* For EVEX instructions i.vrex should become 0 after
7647 build_evex_prefix. For VEX instructions upper 16 registers
7648 aren't available, so VREX should be 0. */
7651 /* Now the VEX prefix. */
7652 p = frag_more (i.vex.length);
7653 for (j = 0; j < i.vex.length; j++)
7654 p[j] = i.vex.bytes[j];
7657 /* Now the opcode; be careful about word order here! */
7658 if (i.tm.opcode_length == 1)
7660 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7664 switch (i.tm.opcode_length)
7668 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7669 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7673 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7683 /* Put out high byte first: can't use md_number_to_chars! */
7684 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7685 *p = i.tm.base_opcode & 0xff;
7688 /* Now the modrm byte and sib byte (if present). */
7689 if (i.tm.opcode_modifier.modrm)
7691 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7694 /* If i.rm.regmem == ESP (4)
7695 && i.rm.mode != (Register mode)
7697 ==> need second modrm byte. */
7698 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7700 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7701 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7703 | i.sib.scale << 6));
7706 if (i.disp_operands)
7707 output_disp (insn_start_frag, insn_start_off);
7710 output_imm (insn_start_frag, insn_start_off);
7716 pi ("" /*line*/, &i);
7718 #endif /* DEBUG386 */
7721 /* Return the size of the displacement operand N. */
7724 disp_size (unsigned int n)
7728 if (i.types[n].bitfield.disp64)
7730 else if (i.types[n].bitfield.disp8)
7732 else if (i.types[n].bitfield.disp16)
7737 /* Return the size of the immediate operand N. */
7740 imm_size (unsigned int n)
7743 if (i.types[n].bitfield.imm64)
7745 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7747 else if (i.types[n].bitfield.imm16)
7753 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7758 for (n = 0; n < i.operands; n++)
7760 if (operand_type_check (i.types[n], disp))
7762 if (i.op[n].disps->X_op == O_constant)
7764 int size = disp_size (n);
7765 offsetT val = i.op[n].disps->X_add_number;
7767 val = offset_in_range (val >> i.memshift, size);
7768 p = frag_more (size);
7769 md_number_to_chars (p, val, size);
7773 enum bfd_reloc_code_real reloc_type;
7774 int size = disp_size (n);
7775 int sign = i.types[n].bitfield.disp32s;
7776 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7779 /* We can't have 8 bit displacement here. */
7780 gas_assert (!i.types[n].bitfield.disp8);
7782 /* The PC relative address is computed relative
7783 to the instruction boundary, so in case immediate
7784 fields follows, we need to adjust the value. */
7785 if (pcrel && i.imm_operands)
7790 for (n1 = 0; n1 < i.operands; n1++)
7791 if (operand_type_check (i.types[n1], imm))
7793 /* Only one immediate is allowed for PC
7794 relative address. */
7795 gas_assert (sz == 0);
7797 i.op[n].disps->X_add_number -= sz;
7799 /* We should find the immediate. */
7800 gas_assert (sz != 0);
7803 p = frag_more (size);
7804 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7806 && GOT_symbol == i.op[n].disps->X_add_symbol
7807 && (((reloc_type == BFD_RELOC_32
7808 || reloc_type == BFD_RELOC_X86_64_32S
7809 || (reloc_type == BFD_RELOC_64
7811 && (i.op[n].disps->X_op == O_symbol
7812 || (i.op[n].disps->X_op == O_add
7813 && ((symbol_get_value_expression
7814 (i.op[n].disps->X_op_symbol)->X_op)
7816 || reloc_type == BFD_RELOC_32_PCREL))
7820 if (insn_start_frag == frag_now)
7821 add = (p - frag_now->fr_literal) - insn_start_off;
7826 add = insn_start_frag->fr_fix - insn_start_off;
7827 for (fr = insn_start_frag->fr_next;
7828 fr && fr != frag_now; fr = fr->fr_next)
7830 add += p - frag_now->fr_literal;
7835 reloc_type = BFD_RELOC_386_GOTPC;
7836 i.op[n].imms->X_add_number += add;
7838 else if (reloc_type == BFD_RELOC_64)
7839 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7841 /* Don't do the adjustment for x86-64, as there
7842 the pcrel addressing is relative to the _next_
7843 insn, and that is taken care of in other code. */
7844 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7846 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7847 size, i.op[n].disps, pcrel,
7849 /* Check for "call/jmp *mem", "mov mem, %reg",
7850 "test %reg, mem" and "binop mem, %reg" where binop
7851 is one of adc, add, and, cmp, or, sbb, sub, xor
7852 instructions. Always generate R_386_GOT32X for
7853 "sym*GOT" operand in 32-bit mode. */
7854 if ((generate_relax_relocations
7857 && i.rm.regmem == 5))
7859 || (i.rm.mode == 0 && i.rm.regmem == 5))
7860 && ((i.operands == 1
7861 && i.tm.base_opcode == 0xff
7862 && (i.rm.reg == 2 || i.rm.reg == 4))
7864 && (i.tm.base_opcode == 0x8b
7865 || i.tm.base_opcode == 0x85
7866 || (i.tm.base_opcode & 0xc7) == 0x03))))
7870 fixP->fx_tcbit = i.rex != 0;
7872 && (i.base_reg->reg_num == RegRip
7873 || i.base_reg->reg_num == RegEip))
7874 fixP->fx_tcbit2 = 1;
7877 fixP->fx_tcbit2 = 1;
7885 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7890 for (n = 0; n < i.operands; n++)
7892 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7893 if (i.rounding && (int) n == i.rounding->operand)
7896 if (operand_type_check (i.types[n], imm))
7898 if (i.op[n].imms->X_op == O_constant)
7900 int size = imm_size (n);
7903 val = offset_in_range (i.op[n].imms->X_add_number,
7905 p = frag_more (size);
7906 md_number_to_chars (p, val, size);
7910 /* Not absolute_section.
7911 Need a 32-bit fixup (don't support 8bit
7912 non-absolute imms). Try to support other
7914 enum bfd_reloc_code_real reloc_type;
7915 int size = imm_size (n);
7918 if (i.types[n].bitfield.imm32s
7919 && (i.suffix == QWORD_MNEM_SUFFIX
7920 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7925 p = frag_more (size);
7926 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7928 /* This is tough to explain. We end up with this one if we
7929 * have operands that look like
7930 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7931 * obtain the absolute address of the GOT, and it is strongly
7932 * preferable from a performance point of view to avoid using
7933 * a runtime relocation for this. The actual sequence of
7934 * instructions often look something like:
7939 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7941 * The call and pop essentially return the absolute address
7942 * of the label .L66 and store it in %ebx. The linker itself
7943 * will ultimately change the first operand of the addl so
7944 * that %ebx points to the GOT, but to keep things simple, the
7945 * .o file must have this operand set so that it generates not
7946 * the absolute address of .L66, but the absolute address of
7947 * itself. This allows the linker itself simply treat a GOTPC
7948 * relocation as asking for a pcrel offset to the GOT to be
7949 * added in, and the addend of the relocation is stored in the
7950 * operand field for the instruction itself.
7952 * Our job here is to fix the operand so that it would add
7953 * the correct offset so that %ebx would point to itself. The
7954 * thing that is tricky is that .-.L66 will point to the
7955 * beginning of the instruction, so we need to further modify
7956 * the operand so that it will point to itself. There are
7957 * other cases where you have something like:
7959 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7961 * and here no correction would be required. Internally in
7962 * the assembler we treat operands of this form as not being
7963 * pcrel since the '.' is explicitly mentioned, and I wonder
7964 * whether it would simplify matters to do it this way. Who
7965 * knows. In earlier versions of the PIC patches, the
7966 * pcrel_adjust field was used to store the correction, but
7967 * since the expression is not pcrel, I felt it would be
7968 * confusing to do it this way. */
7970 if ((reloc_type == BFD_RELOC_32
7971 || reloc_type == BFD_RELOC_X86_64_32S
7972 || reloc_type == BFD_RELOC_64)
7974 && GOT_symbol == i.op[n].imms->X_add_symbol
7975 && (i.op[n].imms->X_op == O_symbol
7976 || (i.op[n].imms->X_op == O_add
7977 && ((symbol_get_value_expression
7978 (i.op[n].imms->X_op_symbol)->X_op)
7983 if (insn_start_frag == frag_now)
7984 add = (p - frag_now->fr_literal) - insn_start_off;
7989 add = insn_start_frag->fr_fix - insn_start_off;
7990 for (fr = insn_start_frag->fr_next;
7991 fr && fr != frag_now; fr = fr->fr_next)
7993 add += p - frag_now->fr_literal;
7997 reloc_type = BFD_RELOC_386_GOTPC;
7999 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8001 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8002 i.op[n].imms->X_add_number += add;
8004 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8005 i.op[n].imms, 0, reloc_type);
8011 /* x86_cons_fix_new is called via the expression parsing code when a
8012 reloc is needed. We use this hook to get the correct .got reloc. */
8013 static int cons_sign = -1;
8016 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8017 expressionS *exp, bfd_reloc_code_real_type r)
8019 r = reloc (len, 0, cons_sign, r);
8022 if (exp->X_op == O_secrel)
8024 exp->X_op = O_symbol;
8025 r = BFD_RELOC_32_SECREL;
8029 fix_new_exp (frag, off, len, exp, 0, r);
8032 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8033 purpose of the `.dc.a' internal pseudo-op. */
8036 x86_address_bytes (void)
8038 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8040 return stdoutput->arch_info->bits_per_address / 8;
8043 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8045 # define lex_got(reloc, adjust, types) NULL
8047 /* Parse operands of the form
8048 <symbol>@GOTOFF+<nnn>
8049 and similar .plt or .got references.
8051 If we find one, set up the correct relocation in RELOC and copy the
8052 input string, minus the `@GOTOFF' into a malloc'd buffer for
8053 parsing by the calling routine. Return this buffer, and if ADJUST
8054 is non-null set it to the length of the string we removed from the
8055 input line. Otherwise return NULL. */
8057 lex_got (enum bfd_reloc_code_real *rel,
8059 i386_operand_type *types)
8061 /* Some of the relocations depend on the size of what field is to
8062 be relocated. But in our callers i386_immediate and i386_displacement
8063 we don't yet know the operand size (this will be set by insn
8064 matching). Hence we record the word32 relocation here,
8065 and adjust the reloc according to the real size in reloc(). */
8066 static const struct {
8069 const enum bfd_reloc_code_real rel[2];
8070 const i386_operand_type types64;
8072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8073 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8075 OPERAND_TYPE_IMM32_64 },
8077 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8078 BFD_RELOC_X86_64_PLTOFF64 },
8079 OPERAND_TYPE_IMM64 },
8080 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8081 BFD_RELOC_X86_64_PLT32 },
8082 OPERAND_TYPE_IMM32_32S_DISP32 },
8083 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8084 BFD_RELOC_X86_64_GOTPLT64 },
8085 OPERAND_TYPE_IMM64_DISP64 },
8086 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8087 BFD_RELOC_X86_64_GOTOFF64 },
8088 OPERAND_TYPE_IMM64_DISP64 },
8089 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8090 BFD_RELOC_X86_64_GOTPCREL },
8091 OPERAND_TYPE_IMM32_32S_DISP32 },
8092 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8093 BFD_RELOC_X86_64_TLSGD },
8094 OPERAND_TYPE_IMM32_32S_DISP32 },
8095 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8096 _dummy_first_bfd_reloc_code_real },
8097 OPERAND_TYPE_NONE },
8098 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8099 BFD_RELOC_X86_64_TLSLD },
8100 OPERAND_TYPE_IMM32_32S_DISP32 },
8101 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8102 BFD_RELOC_X86_64_GOTTPOFF },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8105 BFD_RELOC_X86_64_TPOFF32 },
8106 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8107 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8108 _dummy_first_bfd_reloc_code_real },
8109 OPERAND_TYPE_NONE },
8110 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8111 BFD_RELOC_X86_64_DTPOFF32 },
8112 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8113 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8114 _dummy_first_bfd_reloc_code_real },
8115 OPERAND_TYPE_NONE },
8116 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8117 _dummy_first_bfd_reloc_code_real },
8118 OPERAND_TYPE_NONE },
8119 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8120 BFD_RELOC_X86_64_GOT32 },
8121 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8122 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8123 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8124 OPERAND_TYPE_IMM32_32S_DISP32 },
8125 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8126 BFD_RELOC_X86_64_TLSDESC_CALL },
8127 OPERAND_TYPE_IMM32_32S_DISP32 },
8132 #if defined (OBJ_MAYBE_ELF)
8137 for (cp = input_line_pointer; *cp != '@'; cp++)
8138 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8141 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8143 int len = gotrel[j].len;
8144 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8146 if (gotrel[j].rel[object_64bit] != 0)
8149 char *tmpbuf, *past_reloc;
8151 *rel = gotrel[j].rel[object_64bit];
8155 if (flag_code != CODE_64BIT)
8157 types->bitfield.imm32 = 1;
8158 types->bitfield.disp32 = 1;
8161 *types = gotrel[j].types64;
8164 if (j != 0 && GOT_symbol == NULL)
8165 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8167 /* The length of the first part of our input line. */
8168 first = cp - input_line_pointer;
8170 /* The second part goes from after the reloc token until
8171 (and including) an end_of_line char or comma. */
8172 past_reloc = cp + 1 + len;
8174 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8176 second = cp + 1 - past_reloc;
8178 /* Allocate and copy string. The trailing NUL shouldn't
8179 be necessary, but be safe. */
8180 tmpbuf = XNEWVEC (char, first + second + 2);
8181 memcpy (tmpbuf, input_line_pointer, first);
8182 if (second != 0 && *past_reloc != ' ')
8183 /* Replace the relocation token with ' ', so that
8184 errors like foo@GOTOFF1 will be detected. */
8185 tmpbuf[first++] = ' ';
8187 /* Increment length by 1 if the relocation token is
8192 memcpy (tmpbuf + first, past_reloc, second);
8193 tmpbuf[first + second] = '\0';
8197 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8198 gotrel[j].str, 1 << (5 + object_64bit));
8203 /* Might be a symbol version string. Don't as_bad here. */
8212 /* Parse operands of the form
8213 <symbol>@SECREL32+<nnn>
8215 If we find one, set up the correct relocation in RELOC and copy the
8216 input string, minus the `@SECREL32' into a malloc'd buffer for
8217 parsing by the calling routine. Return this buffer, and if ADJUST
8218 is non-null set it to the length of the string we removed from the
8219 input line. Otherwise return NULL.
8221 This function is copied from the ELF version above adjusted for PE targets. */
8224 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8225 int *adjust ATTRIBUTE_UNUSED,
8226 i386_operand_type *types)
8232 const enum bfd_reloc_code_real rel[2];
8233 const i386_operand_type types64;
8237 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8238 BFD_RELOC_32_SECREL },
8239 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8245 for (cp = input_line_pointer; *cp != '@'; cp++)
8246 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8249 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8251 int len = gotrel[j].len;
8253 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8255 if (gotrel[j].rel[object_64bit] != 0)
8258 char *tmpbuf, *past_reloc;
8260 *rel = gotrel[j].rel[object_64bit];
8266 if (flag_code != CODE_64BIT)
8268 types->bitfield.imm32 = 1;
8269 types->bitfield.disp32 = 1;
8272 *types = gotrel[j].types64;
8275 /* The length of the first part of our input line. */
8276 first = cp - input_line_pointer;
8278 /* The second part goes from after the reloc token until
8279 (and including) an end_of_line char or comma. */
8280 past_reloc = cp + 1 + len;
8282 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8284 second = cp + 1 - past_reloc;
8286 /* Allocate and copy string. The trailing NUL shouldn't
8287 be necessary, but be safe. */
8288 tmpbuf = XNEWVEC (char, first + second + 2);
8289 memcpy (tmpbuf, input_line_pointer, first);
8290 if (second != 0 && *past_reloc != ' ')
8291 /* Replace the relocation token with ' ', so that
8292 errors like foo@SECLREL321 will be detected. */
8293 tmpbuf[first++] = ' ';
8294 memcpy (tmpbuf + first, past_reloc, second);
8295 tmpbuf[first + second] = '\0';
8299 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8300 gotrel[j].str, 1 << (5 + object_64bit));
8305 /* Might be a symbol version string. Don't as_bad here. */
8311 bfd_reloc_code_real_type
8312 x86_cons (expressionS *exp, int size)
8314 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8316 intel_syntax = -intel_syntax;
8319 if (size == 4 || (object_64bit && size == 8))
8321 /* Handle @GOTOFF and the like in an expression. */
8323 char *gotfree_input_line;
8326 save = input_line_pointer;
8327 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8328 if (gotfree_input_line)
8329 input_line_pointer = gotfree_input_line;
8333 if (gotfree_input_line)
8335 /* expression () has merrily parsed up to the end of line,
8336 or a comma - in the wrong buffer. Transfer how far
8337 input_line_pointer has moved to the right buffer. */
8338 input_line_pointer = (save
8339 + (input_line_pointer - gotfree_input_line)
8341 free (gotfree_input_line);
8342 if (exp->X_op == O_constant
8343 || exp->X_op == O_absent
8344 || exp->X_op == O_illegal
8345 || exp->X_op == O_register
8346 || exp->X_op == O_big)
8348 char c = *input_line_pointer;
8349 *input_line_pointer = 0;
8350 as_bad (_("missing or invalid expression `%s'"), save);
8351 *input_line_pointer = c;
8358 intel_syntax = -intel_syntax;
8361 i386_intel_simplify (exp);
8367 signed_cons (int size)
8369 if (flag_code == CODE_64BIT)
8377 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8384 if (exp.X_op == O_symbol)
8385 exp.X_op = O_secrel;
8387 emit_expr (&exp, 4);
8389 while (*input_line_pointer++ == ',');
8391 input_line_pointer--;
8392 demand_empty_rest_of_line ();
8396 /* Handle Vector operations. */
8399 check_VecOperations (char *op_string, char *op_end)
8401 const reg_entry *mask;
8406 && (op_end == NULL || op_string < op_end))
8409 if (*op_string == '{')
8413 /* Check broadcasts. */
8414 if (strncmp (op_string, "1to", 3) == 0)
8419 goto duplicated_vec_op;
8422 if (*op_string == '8')
8423 bcst_type = BROADCAST_1TO8;
8424 else if (*op_string == '4')
8425 bcst_type = BROADCAST_1TO4;
8426 else if (*op_string == '2')
8427 bcst_type = BROADCAST_1TO2;
8428 else if (*op_string == '1'
8429 && *(op_string+1) == '6')
8431 bcst_type = BROADCAST_1TO16;
8436 as_bad (_("Unsupported broadcast: `%s'"), saved);
8441 broadcast_op.type = bcst_type;
8442 broadcast_op.operand = this_operand;
8443 i.broadcast = &broadcast_op;
8445 /* Check masking operation. */
8446 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8448 /* k0 can't be used for write mask. */
8449 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8451 as_bad (_("`%s%s' can't be used for write mask"),
8452 register_prefix, mask->reg_name);
8458 mask_op.mask = mask;
8459 mask_op.zeroing = 0;
8460 mask_op.operand = this_operand;
8466 goto duplicated_vec_op;
8468 i.mask->mask = mask;
8470 /* Only "{z}" is allowed here. No need to check
8471 zeroing mask explicitly. */
8472 if (i.mask->operand != this_operand)
8474 as_bad (_("invalid write mask `%s'"), saved);
8481 /* Check zeroing-flag for masking operation. */
8482 else if (*op_string == 'z')
8486 mask_op.mask = NULL;
8487 mask_op.zeroing = 1;
8488 mask_op.operand = this_operand;
8493 if (i.mask->zeroing)
8496 as_bad (_("duplicated `%s'"), saved);
8500 i.mask->zeroing = 1;
8502 /* Only "{%k}" is allowed here. No need to check mask
8503 register explicitly. */
8504 if (i.mask->operand != this_operand)
8506 as_bad (_("invalid zeroing-masking `%s'"),
8515 goto unknown_vec_op;
8517 if (*op_string != '}')
8519 as_bad (_("missing `}' in `%s'"), saved);
8526 /* We don't know this one. */
8527 as_bad (_("unknown vector operation: `%s'"), saved);
8531 if (i.mask && i.mask->zeroing && !i.mask->mask)
8533 as_bad (_("zeroing-masking only allowed with write mask"));
8541 i386_immediate (char *imm_start)
8543 char *save_input_line_pointer;
8544 char *gotfree_input_line;
8547 i386_operand_type types;
8549 operand_type_set (&types, ~0);
8551 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8553 as_bad (_("at most %d immediate operands are allowed"),
8554 MAX_IMMEDIATE_OPERANDS);
8558 exp = &im_expressions[i.imm_operands++];
8559 i.op[this_operand].imms = exp;
8561 if (is_space_char (*imm_start))
8564 save_input_line_pointer = input_line_pointer;
8565 input_line_pointer = imm_start;
8567 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8568 if (gotfree_input_line)
8569 input_line_pointer = gotfree_input_line;
8571 exp_seg = expression (exp);
8575 /* Handle vector operations. */
8576 if (*input_line_pointer == '{')
8578 input_line_pointer = check_VecOperations (input_line_pointer,
8580 if (input_line_pointer == NULL)
8584 if (*input_line_pointer)
8585 as_bad (_("junk `%s' after expression"), input_line_pointer);
8587 input_line_pointer = save_input_line_pointer;
8588 if (gotfree_input_line)
8590 free (gotfree_input_line);
8592 if (exp->X_op == O_constant || exp->X_op == O_register)
8593 exp->X_op = O_illegal;
8596 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8600 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8601 i386_operand_type types, const char *imm_start)
8603 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8606 as_bad (_("missing or invalid immediate expression `%s'"),
8610 else if (exp->X_op == O_constant)
8612 /* Size it properly later. */
8613 i.types[this_operand].bitfield.imm64 = 1;
8614 /* If not 64bit, sign extend val. */
8615 if (flag_code != CODE_64BIT
8616 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8618 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8620 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8621 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8622 && exp_seg != absolute_section
8623 && exp_seg != text_section
8624 && exp_seg != data_section
8625 && exp_seg != bss_section
8626 && exp_seg != undefined_section
8627 && !bfd_is_com_section (exp_seg))
8629 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8633 else if (!intel_syntax && exp_seg == reg_section)
8636 as_bad (_("illegal immediate register operand %s"), imm_start);
8641 /* This is an address. The size of the address will be
8642 determined later, depending on destination register,
8643 suffix, or the default for the section. */
8644 i.types[this_operand].bitfield.imm8 = 1;
8645 i.types[this_operand].bitfield.imm16 = 1;
8646 i.types[this_operand].bitfield.imm32 = 1;
8647 i.types[this_operand].bitfield.imm32s = 1;
8648 i.types[this_operand].bitfield.imm64 = 1;
8649 i.types[this_operand] = operand_type_and (i.types[this_operand],
8657 i386_scale (char *scale)
8660 char *save = input_line_pointer;
8662 input_line_pointer = scale;
8663 val = get_absolute_expression ();
8668 i.log2_scale_factor = 0;
8671 i.log2_scale_factor = 1;
8674 i.log2_scale_factor = 2;
8677 i.log2_scale_factor = 3;
8681 char sep = *input_line_pointer;
8683 *input_line_pointer = '\0';
8684 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8686 *input_line_pointer = sep;
8687 input_line_pointer = save;
8691 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8693 as_warn (_("scale factor of %d without an index register"),
8694 1 << i.log2_scale_factor);
8695 i.log2_scale_factor = 0;
8697 scale = input_line_pointer;
8698 input_line_pointer = save;
8703 i386_displacement (char *disp_start, char *disp_end)
8707 char *save_input_line_pointer;
8708 char *gotfree_input_line;
8710 i386_operand_type bigdisp, types = anydisp;
8713 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8715 as_bad (_("at most %d displacement operands are allowed"),
8716 MAX_MEMORY_OPERANDS);
8720 operand_type_set (&bigdisp, 0);
8721 if ((i.types[this_operand].bitfield.jumpabsolute)
8722 || (!current_templates->start->opcode_modifier.jump
8723 && !current_templates->start->opcode_modifier.jumpdword))
8725 bigdisp.bitfield.disp32 = 1;
8726 override = (i.prefix[ADDR_PREFIX] != 0);
8727 if (flag_code == CODE_64BIT)
8731 bigdisp.bitfield.disp32s = 1;
8732 bigdisp.bitfield.disp64 = 1;
8735 else if ((flag_code == CODE_16BIT) ^ override)
8737 bigdisp.bitfield.disp32 = 0;
8738 bigdisp.bitfield.disp16 = 1;
8743 /* For PC-relative branches, the width of the displacement
8744 is dependent upon data size, not address size. */
8745 override = (i.prefix[DATA_PREFIX] != 0);
8746 if (flag_code == CODE_64BIT)
8748 if (override || i.suffix == WORD_MNEM_SUFFIX)
8749 bigdisp.bitfield.disp16 = 1;
8752 bigdisp.bitfield.disp32 = 1;
8753 bigdisp.bitfield.disp32s = 1;
8759 override = (i.suffix == (flag_code != CODE_16BIT
8761 : LONG_MNEM_SUFFIX));
8762 bigdisp.bitfield.disp32 = 1;
8763 if ((flag_code == CODE_16BIT) ^ override)
8765 bigdisp.bitfield.disp32 = 0;
8766 bigdisp.bitfield.disp16 = 1;
8770 i.types[this_operand] = operand_type_or (i.types[this_operand],
8773 exp = &disp_expressions[i.disp_operands];
8774 i.op[this_operand].disps = exp;
8776 save_input_line_pointer = input_line_pointer;
8777 input_line_pointer = disp_start;
8778 END_STRING_AND_SAVE (disp_end);
8780 #ifndef GCC_ASM_O_HACK
8781 #define GCC_ASM_O_HACK 0
8784 END_STRING_AND_SAVE (disp_end + 1);
8785 if (i.types[this_operand].bitfield.baseIndex
8786 && displacement_string_end[-1] == '+')
8788 /* This hack is to avoid a warning when using the "o"
8789 constraint within gcc asm statements.
8792 #define _set_tssldt_desc(n,addr,limit,type) \
8793 __asm__ __volatile__ ( \
8795 "movw %w1,2+%0\n\t" \
8797 "movb %b1,4+%0\n\t" \
8798 "movb %4,5+%0\n\t" \
8799 "movb $0,6+%0\n\t" \
8800 "movb %h1,7+%0\n\t" \
8802 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8804 This works great except that the output assembler ends
8805 up looking a bit weird if it turns out that there is
8806 no offset. You end up producing code that looks like:
8819 So here we provide the missing zero. */
8821 *displacement_string_end = '0';
8824 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8825 if (gotfree_input_line)
8826 input_line_pointer = gotfree_input_line;
8828 exp_seg = expression (exp);
8831 if (*input_line_pointer)
8832 as_bad (_("junk `%s' after expression"), input_line_pointer);
8834 RESTORE_END_STRING (disp_end + 1);
8836 input_line_pointer = save_input_line_pointer;
8837 if (gotfree_input_line)
8839 free (gotfree_input_line);
8841 if (exp->X_op == O_constant || exp->X_op == O_register)
8842 exp->X_op = O_illegal;
8845 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8847 RESTORE_END_STRING (disp_end);
8853 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8854 i386_operand_type types, const char *disp_start)
8856 i386_operand_type bigdisp;
8859 /* We do this to make sure that the section symbol is in
8860 the symbol table. We will ultimately change the relocation
8861 to be relative to the beginning of the section. */
8862 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8863 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8864 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8866 if (exp->X_op != O_symbol)
8869 if (S_IS_LOCAL (exp->X_add_symbol)
8870 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8871 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8872 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8873 exp->X_op = O_subtract;
8874 exp->X_op_symbol = GOT_symbol;
8875 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8876 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8877 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8878 i.reloc[this_operand] = BFD_RELOC_64;
8880 i.reloc[this_operand] = BFD_RELOC_32;
8883 else if (exp->X_op == O_absent
8884 || exp->X_op == O_illegal
8885 || exp->X_op == O_big)
8888 as_bad (_("missing or invalid displacement expression `%s'"),
8893 else if (flag_code == CODE_64BIT
8894 && !i.prefix[ADDR_PREFIX]
8895 && exp->X_op == O_constant)
8897 /* Since displacement is signed extended to 64bit, don't allow
8898 disp32 and turn off disp32s if they are out of range. */
8899 i.types[this_operand].bitfield.disp32 = 0;
8900 if (!fits_in_signed_long (exp->X_add_number))
8902 i.types[this_operand].bitfield.disp32s = 0;
8903 if (i.types[this_operand].bitfield.baseindex)
8905 as_bad (_("0x%lx out range of signed 32bit displacement"),
8906 (long) exp->X_add_number);
8912 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8913 else if (exp->X_op != O_constant
8914 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8915 && exp_seg != absolute_section
8916 && exp_seg != text_section
8917 && exp_seg != data_section
8918 && exp_seg != bss_section
8919 && exp_seg != undefined_section
8920 && !bfd_is_com_section (exp_seg))
8922 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8927 /* Check if this is a displacement only operand. */
8928 bigdisp = i.types[this_operand];
8929 bigdisp.bitfield.disp8 = 0;
8930 bigdisp.bitfield.disp16 = 0;
8931 bigdisp.bitfield.disp32 = 0;
8932 bigdisp.bitfield.disp32s = 0;
8933 bigdisp.bitfield.disp64 = 0;
8934 if (operand_type_all_zero (&bigdisp))
8935 i.types[this_operand] = operand_type_and (i.types[this_operand],
8941 /* Return the active addressing mode, taking address override and
8942 registers forming the address into consideration. Update the
8943 address override prefix if necessary. */
8945 static enum flag_code
8946 i386_addressing_mode (void)
8948 enum flag_code addr_mode;
8950 if (i.prefix[ADDR_PREFIX])
8951 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8954 addr_mode = flag_code;
8956 #if INFER_ADDR_PREFIX
8957 if (i.mem_operands == 0)
8959 /* Infer address prefix from the first memory operand. */
8960 const reg_entry *addr_reg = i.base_reg;
8962 if (addr_reg == NULL)
8963 addr_reg = i.index_reg;
8967 if (addr_reg->reg_num == RegEip
8968 || addr_reg->reg_num == RegEiz
8969 || addr_reg->reg_type.bitfield.dword)
8970 addr_mode = CODE_32BIT;
8971 else if (flag_code != CODE_64BIT
8972 && addr_reg->reg_type.bitfield.word)
8973 addr_mode = CODE_16BIT;
8975 if (addr_mode != flag_code)
8977 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8979 /* Change the size of any displacement too. At most one
8980 of Disp16 or Disp32 is set.
8981 FIXME. There doesn't seem to be any real need for
8982 separate Disp16 and Disp32 flags. The same goes for
8983 Imm16 and Imm32. Removing them would probably clean
8984 up the code quite a lot. */
8985 if (flag_code != CODE_64BIT
8986 && (i.types[this_operand].bitfield.disp16
8987 || i.types[this_operand].bitfield.disp32))
8988 i.types[this_operand]
8989 = operand_type_xor (i.types[this_operand], disp16_32);
8999 /* Make sure the memory operand we've been dealt is valid.
9000 Return 1 on success, 0 on a failure. */
9003 i386_index_check (const char *operand_string)
9005 const char *kind = "base/index";
9006 enum flag_code addr_mode = i386_addressing_mode ();
9008 if (current_templates->start->opcode_modifier.isstring
9009 && !current_templates->start->opcode_modifier.immext
9010 && (current_templates->end[-1].opcode_modifier.isstring
9013 /* Memory operands of string insns are special in that they only allow
9014 a single register (rDI, rSI, or rBX) as their memory address. */
9015 const reg_entry *expected_reg;
9016 static const char *di_si[][2] =
9022 static const char *bx[] = { "ebx", "bx", "rbx" };
9024 kind = "string address";
9026 if (current_templates->start->opcode_modifier.repprefixok)
9028 i386_operand_type type = current_templates->end[-1].operand_types[0];
9030 if (!type.bitfield.baseindex
9031 || ((!i.mem_operands != !intel_syntax)
9032 && current_templates->end[-1].operand_types[1]
9033 .bitfield.baseindex))
9034 type = current_templates->end[-1].operand_types[1];
9035 expected_reg = hash_find (reg_hash,
9036 di_si[addr_mode][type.bitfield.esseg]);
9040 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9042 if (i.base_reg != expected_reg
9044 || operand_type_check (i.types[this_operand], disp))
9046 /* The second memory operand must have the same size as
9050 && !((addr_mode == CODE_64BIT
9051 && i.base_reg->reg_type.bitfield.qword)
9052 || (addr_mode == CODE_32BIT
9053 ? i.base_reg->reg_type.bitfield.dword
9054 : i.base_reg->reg_type.bitfield.word)))
9057 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9059 intel_syntax ? '[' : '(',
9061 expected_reg->reg_name,
9062 intel_syntax ? ']' : ')');
9069 as_bad (_("`%s' is not a valid %s expression"),
9070 operand_string, kind);
9075 if (addr_mode != CODE_16BIT)
9077 /* 32-bit/64-bit checks. */
9079 && (addr_mode == CODE_64BIT
9080 ? !i.base_reg->reg_type.bitfield.qword
9081 : !i.base_reg->reg_type.bitfield.dword)
9083 || (i.base_reg->reg_num
9084 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9086 && !i.index_reg->reg_type.bitfield.xmmword
9087 && !i.index_reg->reg_type.bitfield.ymmword
9088 && !i.index_reg->reg_type.bitfield.zmmword
9089 && ((addr_mode == CODE_64BIT
9090 ? !(i.index_reg->reg_type.bitfield.qword
9091 || i.index_reg->reg_num == RegRiz)
9092 : !(i.index_reg->reg_type.bitfield.dword
9093 || i.index_reg->reg_num == RegEiz))
9094 || !i.index_reg->reg_type.bitfield.baseindex)))
9097 /* bndmk, bndldx, and bndstx have special restrictions. */
9098 if (current_templates->start->base_opcode == 0xf30f1b
9099 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9101 /* They cannot use RIP-relative addressing. */
9102 if (i.base_reg && i.base_reg->reg_num == RegRip)
9104 as_bad (_("`%s' cannot be used here"), operand_string);
9108 /* bndldx and bndstx ignore their scale factor. */
9109 if (current_templates->start->base_opcode != 0xf30f1b
9110 && i.log2_scale_factor)
9111 as_warn (_("register scaling is being ignored here"));
9116 /* 16-bit checks. */
9118 && (!i.base_reg->reg_type.bitfield.word
9119 || !i.base_reg->reg_type.bitfield.baseindex))
9121 && (!i.index_reg->reg_type.bitfield.word
9122 || !i.index_reg->reg_type.bitfield.baseindex
9124 && i.base_reg->reg_num < 6
9125 && i.index_reg->reg_num >= 6
9126 && i.log2_scale_factor == 0))))
9133 /* Handle vector immediates. */
9136 RC_SAE_immediate (const char *imm_start)
9138 unsigned int match_found, j;
9139 const char *pstr = imm_start;
9147 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9149 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9153 rc_op.type = RC_NamesTable[j].type;
9154 rc_op.operand = this_operand;
9155 i.rounding = &rc_op;
9159 as_bad (_("duplicated `%s'"), imm_start);
9162 pstr += RC_NamesTable[j].len;
9172 as_bad (_("Missing '}': '%s'"), imm_start);
9175 /* RC/SAE immediate string should contain nothing more. */;
9178 as_bad (_("Junk after '}': '%s'"), imm_start);
9182 exp = &im_expressions[i.imm_operands++];
9183 i.op[this_operand].imms = exp;
9185 exp->X_op = O_constant;
9186 exp->X_add_number = 0;
9187 exp->X_add_symbol = (symbolS *) 0;
9188 exp->X_op_symbol = (symbolS *) 0;
9190 i.types[this_operand].bitfield.imm8 = 1;
9194 /* Only string instructions can have a second memory operand, so
9195 reduce current_templates to just those if it contains any. */
9197 maybe_adjust_templates (void)
9199 const insn_template *t;
9201 gas_assert (i.mem_operands == 1);
9203 for (t = current_templates->start; t < current_templates->end; ++t)
9204 if (t->opcode_modifier.isstring)
9207 if (t < current_templates->end)
9209 static templates aux_templates;
9210 bfd_boolean recheck;
9212 aux_templates.start = t;
9213 for (; t < current_templates->end; ++t)
9214 if (!t->opcode_modifier.isstring)
9216 aux_templates.end = t;
9218 /* Determine whether to re-check the first memory operand. */
9219 recheck = (aux_templates.start != current_templates->start
9220 || t != current_templates->end);
9222 current_templates = &aux_templates;
9227 if (i.memop1_string != NULL
9228 && i386_index_check (i.memop1_string) == 0)
9237 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9241 i386_att_operand (char *operand_string)
9245 char *op_string = operand_string;
9247 if (is_space_char (*op_string))
9250 /* We check for an absolute prefix (differentiating,
9251 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9252 if (*op_string == ABSOLUTE_PREFIX)
9255 if (is_space_char (*op_string))
9257 i.types[this_operand].bitfield.jumpabsolute = 1;
9260 /* Check if operand is a register. */
9261 if ((r = parse_register (op_string, &end_op)) != NULL)
9263 i386_operand_type temp;
9265 /* Check for a segment override by searching for ':' after a
9266 segment register. */
9268 if (is_space_char (*op_string))
9270 if (*op_string == ':'
9271 && (r->reg_type.bitfield.sreg2
9272 || r->reg_type.bitfield.sreg3))
9277 i.seg[i.mem_operands] = &es;
9280 i.seg[i.mem_operands] = &cs;
9283 i.seg[i.mem_operands] = &ss;
9286 i.seg[i.mem_operands] = &ds;
9289 i.seg[i.mem_operands] = &fs;
9292 i.seg[i.mem_operands] = &gs;
9296 /* Skip the ':' and whitespace. */
9298 if (is_space_char (*op_string))
9301 if (!is_digit_char (*op_string)
9302 && !is_identifier_char (*op_string)
9303 && *op_string != '('
9304 && *op_string != ABSOLUTE_PREFIX)
9306 as_bad (_("bad memory operand `%s'"), op_string);
9309 /* Handle case of %es:*foo. */
9310 if (*op_string == ABSOLUTE_PREFIX)
9313 if (is_space_char (*op_string))
9315 i.types[this_operand].bitfield.jumpabsolute = 1;
9317 goto do_memory_reference;
9320 /* Handle vector operations. */
9321 if (*op_string == '{')
9323 op_string = check_VecOperations (op_string, NULL);
9324 if (op_string == NULL)
9330 as_bad (_("junk `%s' after register"), op_string);
9334 temp.bitfield.baseindex = 0;
9335 i.types[this_operand] = operand_type_or (i.types[this_operand],
9337 i.types[this_operand].bitfield.unspecified = 0;
9338 i.op[this_operand].regs = r;
9341 else if (*op_string == REGISTER_PREFIX)
9343 as_bad (_("bad register name `%s'"), op_string);
9346 else if (*op_string == IMMEDIATE_PREFIX)
9349 if (i.types[this_operand].bitfield.jumpabsolute)
9351 as_bad (_("immediate operand illegal with absolute jump"));
9354 if (!i386_immediate (op_string))
9357 else if (RC_SAE_immediate (operand_string))
9359 /* If it is a RC or SAE immediate, do nothing. */
9362 else if (is_digit_char (*op_string)
9363 || is_identifier_char (*op_string)
9364 || *op_string == '"'
9365 || *op_string == '(')
9367 /* This is a memory reference of some sort. */
9370 /* Start and end of displacement string expression (if found). */
9371 char *displacement_string_start;
9372 char *displacement_string_end;
9375 do_memory_reference:
9376 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9378 if ((i.mem_operands == 1
9379 && !current_templates->start->opcode_modifier.isstring)
9380 || i.mem_operands == 2)
9382 as_bad (_("too many memory references for `%s'"),
9383 current_templates->start->name);
9387 /* Check for base index form. We detect the base index form by
9388 looking for an ')' at the end of the operand, searching
9389 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9391 base_string = op_string + strlen (op_string);
9393 /* Handle vector operations. */
9394 vop_start = strchr (op_string, '{');
9395 if (vop_start && vop_start < base_string)
9397 if (check_VecOperations (vop_start, base_string) == NULL)
9399 base_string = vop_start;
9403 if (is_space_char (*base_string))
9406 /* If we only have a displacement, set-up for it to be parsed later. */
9407 displacement_string_start = op_string;
9408 displacement_string_end = base_string + 1;
9410 if (*base_string == ')')
9413 unsigned int parens_balanced = 1;
9414 /* We've already checked that the number of left & right ()'s are
9415 equal, so this loop will not be infinite. */
9419 if (*base_string == ')')
9421 if (*base_string == '(')
9424 while (parens_balanced);
9426 temp_string = base_string;
9428 /* Skip past '(' and whitespace. */
9430 if (is_space_char (*base_string))
9433 if (*base_string == ','
9434 || ((i.base_reg = parse_register (base_string, &end_op))
9437 displacement_string_end = temp_string;
9439 i.types[this_operand].bitfield.baseindex = 1;
9443 base_string = end_op;
9444 if (is_space_char (*base_string))
9448 /* There may be an index reg or scale factor here. */
9449 if (*base_string == ',')
9452 if (is_space_char (*base_string))
9455 if ((i.index_reg = parse_register (base_string, &end_op))
9458 base_string = end_op;
9459 if (is_space_char (*base_string))
9461 if (*base_string == ',')
9464 if (is_space_char (*base_string))
9467 else if (*base_string != ')')
9469 as_bad (_("expecting `,' or `)' "
9470 "after index register in `%s'"),
9475 else if (*base_string == REGISTER_PREFIX)
9477 end_op = strchr (base_string, ',');
9480 as_bad (_("bad register name `%s'"), base_string);
9484 /* Check for scale factor. */
9485 if (*base_string != ')')
9487 char *end_scale = i386_scale (base_string);
9492 base_string = end_scale;
9493 if (is_space_char (*base_string))
9495 if (*base_string != ')')
9497 as_bad (_("expecting `)' "
9498 "after scale factor in `%s'"),
9503 else if (!i.index_reg)
9505 as_bad (_("expecting index register or scale factor "
9506 "after `,'; got '%c'"),
9511 else if (*base_string != ')')
9513 as_bad (_("expecting `,' or `)' "
9514 "after base register in `%s'"),
9519 else if (*base_string == REGISTER_PREFIX)
9521 end_op = strchr (base_string, ',');
9524 as_bad (_("bad register name `%s'"), base_string);
9529 /* If there's an expression beginning the operand, parse it,
9530 assuming displacement_string_start and
9531 displacement_string_end are meaningful. */
9532 if (displacement_string_start != displacement_string_end)
9534 if (!i386_displacement (displacement_string_start,
9535 displacement_string_end))
9539 /* Special case for (%dx) while doing input/output op. */
9541 && operand_type_equal (&i.base_reg->reg_type,
9542 ®16_inoutportreg)
9544 && i.log2_scale_factor == 0
9545 && i.seg[i.mem_operands] == 0
9546 && !operand_type_check (i.types[this_operand], disp))
9548 i.types[this_operand] = inoutportreg;
9552 if (i386_index_check (operand_string) == 0)
9554 i.types[this_operand].bitfield.mem = 1;
9555 if (i.mem_operands == 0)
9556 i.memop1_string = xstrdup (operand_string);
9561 /* It's not a memory operand; argh! */
9562 as_bad (_("invalid char %s beginning operand %d `%s'"),
9563 output_invalid (*op_string),
9568 return 1; /* Normal return. */
9571 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9572 that an rs_machine_dependent frag may reach. */
9575 i386_frag_max_var (fragS *frag)
9577 /* The only relaxable frags are for jumps.
9578 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9579 gas_assert (frag->fr_type == rs_machine_dependent);
9580 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9585 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9587 /* STT_GNU_IFUNC symbol must go through PLT. */
9588 if ((symbol_get_bfdsym (fr_symbol)->flags
9589 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9592 if (!S_IS_EXTERNAL (fr_symbol))
9593 /* Symbol may be weak or local. */
9594 return !S_IS_WEAK (fr_symbol);
9596 /* Global symbols with non-default visibility can't be preempted. */
9597 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9600 if (fr_var != NO_RELOC)
9601 switch ((enum bfd_reloc_code_real) fr_var)
9603 case BFD_RELOC_386_PLT32:
9604 case BFD_RELOC_X86_64_PLT32:
9605 /* Symbol with PLT relocation may be preempted. */
9611 /* Global symbols with default visibility in a shared library may be
9612 preempted by another definition. */
9617 /* md_estimate_size_before_relax()
9619 Called just before relax() for rs_machine_dependent frags. The x86
9620 assembler uses these frags to handle variable size jump
9623 Any symbol that is now undefined will not become defined.
9624 Return the correct fr_subtype in the frag.
9625 Return the initial "guess for variable size of frag" to caller.
9626 The guess is actually the growth beyond the fixed part. Whatever
9627 we do to grow the fixed or variable part contributes to our
9631 md_estimate_size_before_relax (fragS *fragP, segT segment)
9633 /* We've already got fragP->fr_subtype right; all we have to do is
9634 check for un-relaxable symbols. On an ELF system, we can't relax
9635 an externally visible symbol, because it may be overridden by a
9637 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9640 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9643 #if defined (OBJ_COFF) && defined (TE_PE)
9644 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9645 && S_IS_WEAK (fragP->fr_symbol))
9649 /* Symbol is undefined in this segment, or we need to keep a
9650 reloc so that weak symbols can be overridden. */
9651 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9652 enum bfd_reloc_code_real reloc_type;
9653 unsigned char *opcode;
9656 if (fragP->fr_var != NO_RELOC)
9657 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9659 reloc_type = BFD_RELOC_16_PCREL;
9660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9661 else if (need_plt32_p (fragP->fr_symbol))
9662 reloc_type = BFD_RELOC_X86_64_PLT32;
9665 reloc_type = BFD_RELOC_32_PCREL;
9667 old_fr_fix = fragP->fr_fix;
9668 opcode = (unsigned char *) fragP->fr_opcode;
9670 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9673 /* Make jmp (0xeb) a (d)word displacement jump. */
9675 fragP->fr_fix += size;
9676 fix_new (fragP, old_fr_fix, size,
9678 fragP->fr_offset, 1,
9684 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9686 /* Negate the condition, and branch past an
9687 unconditional jump. */
9690 /* Insert an unconditional jump. */
9692 /* We added two extra opcode bytes, and have a two byte
9694 fragP->fr_fix += 2 + 2;
9695 fix_new (fragP, old_fr_fix + 2, 2,
9697 fragP->fr_offset, 1,
9704 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9709 fixP = fix_new (fragP, old_fr_fix, 1,
9711 fragP->fr_offset, 1,
9713 fixP->fx_signed = 1;
9717 /* This changes the byte-displacement jump 0x7N
9718 to the (d)word-displacement jump 0x0f,0x8N. */
9719 opcode[1] = opcode[0] + 0x10;
9720 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9721 /* We've added an opcode byte. */
9722 fragP->fr_fix += 1 + size;
9723 fix_new (fragP, old_fr_fix + 1, size,
9725 fragP->fr_offset, 1,
9730 BAD_CASE (fragP->fr_subtype);
9734 return fragP->fr_fix - old_fr_fix;
9737 /* Guess size depending on current relax state. Initially the relax
9738 state will correspond to a short jump and we return 1, because
9739 the variable part of the frag (the branch offset) is one byte
9740 long. However, we can relax a section more than once and in that
9741 case we must either set fr_subtype back to the unrelaxed state,
9742 or return the value for the appropriate branch. */
9743 return md_relax_table[fragP->fr_subtype].rlx_length;
9746 /* Called after relax() is finished.
9748 In: Address of frag.
9749 fr_type == rs_machine_dependent.
9750 fr_subtype is what the address relaxed to.
9752 Out: Any fixSs and constants are set up.
9753 Caller will turn frag into a ".space 0". */
9756 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9759 unsigned char *opcode;
9760 unsigned char *where_to_put_displacement = NULL;
9761 offsetT target_address;
9762 offsetT opcode_address;
9763 unsigned int extension = 0;
9764 offsetT displacement_from_opcode_start;
9766 opcode = (unsigned char *) fragP->fr_opcode;
9768 /* Address we want to reach in file space. */
9769 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9771 /* Address opcode resides at in file space. */
9772 opcode_address = fragP->fr_address + fragP->fr_fix;
9774 /* Displacement from opcode start to fill into instruction. */
9775 displacement_from_opcode_start = target_address - opcode_address;
9777 if ((fragP->fr_subtype & BIG) == 0)
9779 /* Don't have to change opcode. */
9780 extension = 1; /* 1 opcode + 1 displacement */
9781 where_to_put_displacement = &opcode[1];
9785 if (no_cond_jump_promotion
9786 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9787 as_warn_where (fragP->fr_file, fragP->fr_line,
9788 _("long jump required"));
9790 switch (fragP->fr_subtype)
9792 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9793 extension = 4; /* 1 opcode + 4 displacement */
9795 where_to_put_displacement = &opcode[1];
9798 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9799 extension = 2; /* 1 opcode + 2 displacement */
9801 where_to_put_displacement = &opcode[1];
9804 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9805 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9806 extension = 5; /* 2 opcode + 4 displacement */
9807 opcode[1] = opcode[0] + 0x10;
9808 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9809 where_to_put_displacement = &opcode[2];
9812 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9813 extension = 3; /* 2 opcode + 2 displacement */
9814 opcode[1] = opcode[0] + 0x10;
9815 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9816 where_to_put_displacement = &opcode[2];
9819 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9824 where_to_put_displacement = &opcode[3];
9828 BAD_CASE (fragP->fr_subtype);
9833 /* If size if less then four we are sure that the operand fits,
9834 but if it's 4, then it could be that the displacement is larger
9836 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9838 && ((addressT) (displacement_from_opcode_start - extension
9839 + ((addressT) 1 << 31))
9840 > (((addressT) 2 << 31) - 1)))
9842 as_bad_where (fragP->fr_file, fragP->fr_line,
9843 _("jump target out of range"));
9844 /* Make us emit 0. */
9845 displacement_from_opcode_start = extension;
9847 /* Now put displacement after opcode. */
9848 md_number_to_chars ((char *) where_to_put_displacement,
9849 (valueT) (displacement_from_opcode_start - extension),
9850 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9851 fragP->fr_fix += extension;
9854 /* Apply a fixup (fixP) to segment data, once it has been determined
9855 by our caller that we have all the info we need to fix it up.
9857 Parameter valP is the pointer to the value of the bits.
9859 On the 386, immediates, displacements, and data pointers are all in
9860 the same (little-endian) format, so we don't need to care about which
9864 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9866 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9867 valueT value = *valP;
9869 #if !defined (TE_Mach)
9872 switch (fixP->fx_r_type)
9878 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9881 case BFD_RELOC_X86_64_32S:
9882 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9885 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9888 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9893 if (fixP->fx_addsy != NULL
9894 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9895 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9896 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9897 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9898 && !use_rela_relocations)
9900 /* This is a hack. There should be a better way to handle this.
9901 This covers for the fact that bfd_install_relocation will
9902 subtract the current location (for partial_inplace, PC relative
9903 relocations); see more below. */
9907 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9910 value += fixP->fx_where + fixP->fx_frag->fr_address;
9912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9915 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9918 || (symbol_section_p (fixP->fx_addsy)
9919 && sym_seg != absolute_section))
9920 && !generic_force_reloc (fixP))
9922 /* Yes, we add the values in twice. This is because
9923 bfd_install_relocation subtracts them out again. I think
9924 bfd_install_relocation is broken, but I don't dare change
9926 value += fixP->fx_where + fixP->fx_frag->fr_address;
9930 #if defined (OBJ_COFF) && defined (TE_PE)
9931 /* For some reason, the PE format does not store a
9932 section address offset for a PC relative symbol. */
9933 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9934 || S_IS_WEAK (fixP->fx_addsy))
9935 value += md_pcrel_from (fixP);
9938 #if defined (OBJ_COFF) && defined (TE_PE)
9939 if (fixP->fx_addsy != NULL
9940 && S_IS_WEAK (fixP->fx_addsy)
9941 /* PR 16858: Do not modify weak function references. */
9942 && ! fixP->fx_pcrel)
9944 #if !defined (TE_PEP)
9945 /* For x86 PE weak function symbols are neither PC-relative
9946 nor do they set S_IS_FUNCTION. So the only reliable way
9947 to detect them is to check the flags of their containing
9949 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9950 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9954 value -= S_GET_VALUE (fixP->fx_addsy);
9958 /* Fix a few things - the dynamic linker expects certain values here,
9959 and we must not disappoint it. */
9960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9961 if (IS_ELF && fixP->fx_addsy)
9962 switch (fixP->fx_r_type)
9964 case BFD_RELOC_386_PLT32:
9965 case BFD_RELOC_X86_64_PLT32:
9966 /* Make the jump instruction point to the address of the operand. At
9967 runtime we merely add the offset to the actual PLT entry. */
9971 case BFD_RELOC_386_TLS_GD:
9972 case BFD_RELOC_386_TLS_LDM:
9973 case BFD_RELOC_386_TLS_IE_32:
9974 case BFD_RELOC_386_TLS_IE:
9975 case BFD_RELOC_386_TLS_GOTIE:
9976 case BFD_RELOC_386_TLS_GOTDESC:
9977 case BFD_RELOC_X86_64_TLSGD:
9978 case BFD_RELOC_X86_64_TLSLD:
9979 case BFD_RELOC_X86_64_GOTTPOFF:
9980 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9981 value = 0; /* Fully resolved at runtime. No addend. */
9983 case BFD_RELOC_386_TLS_LE:
9984 case BFD_RELOC_386_TLS_LDO_32:
9985 case BFD_RELOC_386_TLS_LE_32:
9986 case BFD_RELOC_X86_64_DTPOFF32:
9987 case BFD_RELOC_X86_64_DTPOFF64:
9988 case BFD_RELOC_X86_64_TPOFF32:
9989 case BFD_RELOC_X86_64_TPOFF64:
9990 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9993 case BFD_RELOC_386_TLS_DESC_CALL:
9994 case BFD_RELOC_X86_64_TLSDESC_CALL:
9995 value = 0; /* Fully resolved at runtime. No addend. */
9996 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10000 case BFD_RELOC_VTABLE_INHERIT:
10001 case BFD_RELOC_VTABLE_ENTRY:
10008 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10010 #endif /* !defined (TE_Mach) */
10012 /* Are we finished with this relocation now? */
10013 if (fixP->fx_addsy == NULL)
10015 #if defined (OBJ_COFF) && defined (TE_PE)
10016 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10019 /* Remember value for tc_gen_reloc. */
10020 fixP->fx_addnumber = value;
10021 /* Clear out the frag for now. */
10025 else if (use_rela_relocations)
10027 fixP->fx_no_overflow = 1;
10028 /* Remember value for tc_gen_reloc. */
10029 fixP->fx_addnumber = value;
10033 md_number_to_chars (p, value, fixP->fx_size);
10037 md_atof (int type, char *litP, int *sizeP)
10039 /* This outputs the LITTLENUMs in REVERSE order;
10040 in accord with the bigendian 386. */
10041 return ieee_md_atof (type, litP, sizeP, FALSE);
10044 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10047 output_invalid (int c)
10050 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10053 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10054 "(0x%x)", (unsigned char) c);
10055 return output_invalid_buf;
10058 /* REG_STRING starts *before* REGISTER_PREFIX. */
10060 static const reg_entry *
10061 parse_real_register (char *reg_string, char **end_op)
10063 char *s = reg_string;
10065 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10066 const reg_entry *r;
10068 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10069 if (*s == REGISTER_PREFIX)
10072 if (is_space_char (*s))
10075 p = reg_name_given;
10076 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10078 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10079 return (const reg_entry *) NULL;
10083 /* For naked regs, make sure that we are not dealing with an identifier.
10084 This prevents confusing an identifier like `eax_var' with register
10086 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10087 return (const reg_entry *) NULL;
10091 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10093 /* Handle floating point regs, allowing spaces in the (i) part. */
10094 if (r == i386_regtab /* %st is first entry of table */)
10096 if (is_space_char (*s))
10101 if (is_space_char (*s))
10103 if (*s >= '0' && *s <= '7')
10105 int fpr = *s - '0';
10107 if (is_space_char (*s))
10112 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10117 /* We have "%st(" then garbage. */
10118 return (const reg_entry *) NULL;
10122 if (r == NULL || allow_pseudo_reg)
10125 if (operand_type_all_zero (&r->reg_type))
10126 return (const reg_entry *) NULL;
10128 if ((r->reg_type.bitfield.dword
10129 || r->reg_type.bitfield.sreg3
10130 || r->reg_type.bitfield.control
10131 || r->reg_type.bitfield.debug
10132 || r->reg_type.bitfield.test)
10133 && !cpu_arch_flags.bitfield.cpui386)
10134 return (const reg_entry *) NULL;
10136 if (r->reg_type.bitfield.tbyte
10137 && !cpu_arch_flags.bitfield.cpu8087
10138 && !cpu_arch_flags.bitfield.cpu287
10139 && !cpu_arch_flags.bitfield.cpu387)
10140 return (const reg_entry *) NULL;
10142 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10143 return (const reg_entry *) NULL;
10145 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10146 return (const reg_entry *) NULL;
10148 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10149 return (const reg_entry *) NULL;
10151 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10152 return (const reg_entry *) NULL;
10154 if (r->reg_type.bitfield.regmask
10155 && !cpu_arch_flags.bitfield.cpuregmask)
10156 return (const reg_entry *) NULL;
10158 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10159 if (!allow_index_reg
10160 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10161 return (const reg_entry *) NULL;
10163 /* Upper 16 vector register is only available with VREX in 64bit
10165 if ((r->reg_flags & RegVRex))
10167 if (i.vec_encoding == vex_encoding_default)
10168 i.vec_encoding = vex_encoding_evex;
10170 if (!cpu_arch_flags.bitfield.cpuvrex
10171 || i.vec_encoding != vex_encoding_evex
10172 || flag_code != CODE_64BIT)
10173 return (const reg_entry *) NULL;
10176 if (((r->reg_flags & (RegRex64 | RegRex))
10177 || r->reg_type.bitfield.qword)
10178 && (!cpu_arch_flags.bitfield.cpulm
10179 || !operand_type_equal (&r->reg_type, &control))
10180 && flag_code != CODE_64BIT)
10181 return (const reg_entry *) NULL;
10183 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10184 return (const reg_entry *) NULL;
10189 /* REG_STRING starts *before* REGISTER_PREFIX. */
10191 static const reg_entry *
10192 parse_register (char *reg_string, char **end_op)
10194 const reg_entry *r;
10196 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10197 r = parse_real_register (reg_string, end_op);
10202 char *save = input_line_pointer;
10206 input_line_pointer = reg_string;
10207 c = get_symbol_name (®_string);
10208 symbolP = symbol_find (reg_string);
10209 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10211 const expressionS *e = symbol_get_value_expression (symbolP);
10213 know (e->X_op == O_register);
10214 know (e->X_add_number >= 0
10215 && (valueT) e->X_add_number < i386_regtab_size);
10216 r = i386_regtab + e->X_add_number;
10217 if ((r->reg_flags & RegVRex))
10218 i.vec_encoding = vex_encoding_evex;
10219 *end_op = input_line_pointer;
10221 *input_line_pointer = c;
10222 input_line_pointer = save;
10228 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10230 const reg_entry *r;
10231 char *end = input_line_pointer;
10234 r = parse_register (name, &input_line_pointer);
10235 if (r && end <= input_line_pointer)
10237 *nextcharP = *input_line_pointer;
10238 *input_line_pointer = 0;
10239 e->X_op = O_register;
10240 e->X_add_number = r - i386_regtab;
10243 input_line_pointer = end;
10245 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10249 md_operand (expressionS *e)
10252 const reg_entry *r;
10254 switch (*input_line_pointer)
10256 case REGISTER_PREFIX:
10257 r = parse_real_register (input_line_pointer, &end);
10260 e->X_op = O_register;
10261 e->X_add_number = r - i386_regtab;
10262 input_line_pointer = end;
10267 gas_assert (intel_syntax);
10268 end = input_line_pointer++;
10270 if (*input_line_pointer == ']')
10272 ++input_line_pointer;
10273 e->X_op_symbol = make_expr_symbol (e);
10274 e->X_add_symbol = NULL;
10275 e->X_add_number = 0;
10280 e->X_op = O_absent;
10281 input_line_pointer = end;
10288 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10289 const char *md_shortopts = "kVQ:sqnO::";
10291 const char *md_shortopts = "qnO::";
10294 #define OPTION_32 (OPTION_MD_BASE + 0)
10295 #define OPTION_64 (OPTION_MD_BASE + 1)
10296 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10297 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10298 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10299 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10300 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10301 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10302 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10303 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10304 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10305 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10306 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10307 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10308 #define OPTION_X32 (OPTION_MD_BASE + 14)
10309 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10310 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10311 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10312 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10313 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10314 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10315 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10316 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10317 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10318 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10320 struct option md_longopts[] =
10322 {"32", no_argument, NULL, OPTION_32},
10323 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10324 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10325 {"64", no_argument, NULL, OPTION_64},
10327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10328 {"x32", no_argument, NULL, OPTION_X32},
10329 {"mshared", no_argument, NULL, OPTION_MSHARED},
10331 {"divide", no_argument, NULL, OPTION_DIVIDE},
10332 {"march", required_argument, NULL, OPTION_MARCH},
10333 {"mtune", required_argument, NULL, OPTION_MTUNE},
10334 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10335 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10336 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10337 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10338 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10339 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10340 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10341 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10342 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10343 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10344 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10345 # if defined (TE_PE) || defined (TE_PEP)
10346 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10348 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10349 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10350 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10351 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10352 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10353 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10354 {NULL, no_argument, NULL, 0}
10356 size_t md_longopts_size = sizeof (md_longopts);
10359 md_parse_option (int c, const char *arg)
10362 char *arch, *next, *saved;
10367 optimize_align_code = 0;
10371 quiet_warnings = 1;
10374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10375 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10376 should be emitted or not. FIXME: Not implemented. */
10380 /* -V: SVR4 argument to print version ID. */
10382 print_version_id ();
10385 /* -k: Ignore for FreeBSD compatibility. */
10390 /* -s: On i386 Solaris, this tells the native assembler to use
10391 .stab instead of .stab.excl. We always use .stab anyhow. */
10394 case OPTION_MSHARED:
10398 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10399 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10402 const char **list, **l;
10404 list = bfd_target_list ();
10405 for (l = list; *l != NULL; l++)
10406 if (CONST_STRNEQ (*l, "elf64-x86-64")
10407 || strcmp (*l, "coff-x86-64") == 0
10408 || strcmp (*l, "pe-x86-64") == 0
10409 || strcmp (*l, "pei-x86-64") == 0
10410 || strcmp (*l, "mach-o-x86-64") == 0)
10412 default_arch = "x86_64";
10416 as_fatal (_("no compiled in support for x86_64"));
10422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10426 const char **list, **l;
10428 list = bfd_target_list ();
10429 for (l = list; *l != NULL; l++)
10430 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10432 default_arch = "x86_64:32";
10436 as_fatal (_("no compiled in support for 32bit x86_64"));
10440 as_fatal (_("32bit x86_64 is only supported for ELF"));
10445 default_arch = "i386";
10448 case OPTION_DIVIDE:
10449 #ifdef SVR4_COMMENT_CHARS
10454 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10456 for (s = i386_comment_chars; *s != '\0'; s++)
10460 i386_comment_chars = n;
10466 saved = xstrdup (arg);
10468 /* Allow -march=+nosse. */
10474 as_fatal (_("invalid -march= option: `%s'"), arg);
10475 next = strchr (arch, '+');
10478 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10480 if (strcmp (arch, cpu_arch [j].name) == 0)
10483 if (! cpu_arch[j].flags.bitfield.cpui386)
10486 cpu_arch_name = cpu_arch[j].name;
10487 cpu_sub_arch_name = NULL;
10488 cpu_arch_flags = cpu_arch[j].flags;
10489 cpu_arch_isa = cpu_arch[j].type;
10490 cpu_arch_isa_flags = cpu_arch[j].flags;
10491 if (!cpu_arch_tune_set)
10493 cpu_arch_tune = cpu_arch_isa;
10494 cpu_arch_tune_flags = cpu_arch_isa_flags;
10498 else if (*cpu_arch [j].name == '.'
10499 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10501 /* ISA extension. */
10502 i386_cpu_flags flags;
10504 flags = cpu_flags_or (cpu_arch_flags,
10505 cpu_arch[j].flags);
10507 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10509 if (cpu_sub_arch_name)
10511 char *name = cpu_sub_arch_name;
10512 cpu_sub_arch_name = concat (name,
10514 (const char *) NULL);
10518 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10519 cpu_arch_flags = flags;
10520 cpu_arch_isa_flags = flags;
10526 if (j >= ARRAY_SIZE (cpu_arch))
10528 /* Disable an ISA extension. */
10529 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10530 if (strcmp (arch, cpu_noarch [j].name) == 0)
10532 i386_cpu_flags flags;
10534 flags = cpu_flags_and_not (cpu_arch_flags,
10535 cpu_noarch[j].flags);
10536 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10538 if (cpu_sub_arch_name)
10540 char *name = cpu_sub_arch_name;
10541 cpu_sub_arch_name = concat (arch,
10542 (const char *) NULL);
10546 cpu_sub_arch_name = xstrdup (arch);
10547 cpu_arch_flags = flags;
10548 cpu_arch_isa_flags = flags;
10553 if (j >= ARRAY_SIZE (cpu_noarch))
10554 j = ARRAY_SIZE (cpu_arch);
10557 if (j >= ARRAY_SIZE (cpu_arch))
10558 as_fatal (_("invalid -march= option: `%s'"), arg);
10562 while (next != NULL);
10568 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10569 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10571 if (strcmp (arg, cpu_arch [j].name) == 0)
10573 cpu_arch_tune_set = 1;
10574 cpu_arch_tune = cpu_arch [j].type;
10575 cpu_arch_tune_flags = cpu_arch[j].flags;
10579 if (j >= ARRAY_SIZE (cpu_arch))
10580 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10583 case OPTION_MMNEMONIC:
10584 if (strcasecmp (arg, "att") == 0)
10585 intel_mnemonic = 0;
10586 else if (strcasecmp (arg, "intel") == 0)
10587 intel_mnemonic = 1;
10589 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10592 case OPTION_MSYNTAX:
10593 if (strcasecmp (arg, "att") == 0)
10595 else if (strcasecmp (arg, "intel") == 0)
10598 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10601 case OPTION_MINDEX_REG:
10602 allow_index_reg = 1;
10605 case OPTION_MNAKED_REG:
10606 allow_naked_reg = 1;
10609 case OPTION_MSSE2AVX:
10613 case OPTION_MSSE_CHECK:
10614 if (strcasecmp (arg, "error") == 0)
10615 sse_check = check_error;
10616 else if (strcasecmp (arg, "warning") == 0)
10617 sse_check = check_warning;
10618 else if (strcasecmp (arg, "none") == 0)
10619 sse_check = check_none;
10621 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10624 case OPTION_MOPERAND_CHECK:
10625 if (strcasecmp (arg, "error") == 0)
10626 operand_check = check_error;
10627 else if (strcasecmp (arg, "warning") == 0)
10628 operand_check = check_warning;
10629 else if (strcasecmp (arg, "none") == 0)
10630 operand_check = check_none;
10632 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10635 case OPTION_MAVXSCALAR:
10636 if (strcasecmp (arg, "128") == 0)
10637 avxscalar = vex128;
10638 else if (strcasecmp (arg, "256") == 0)
10639 avxscalar = vex256;
10641 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10644 case OPTION_MADD_BND_PREFIX:
10645 add_bnd_prefix = 1;
10648 case OPTION_MEVEXLIG:
10649 if (strcmp (arg, "128") == 0)
10650 evexlig = evexl128;
10651 else if (strcmp (arg, "256") == 0)
10652 evexlig = evexl256;
10653 else if (strcmp (arg, "512") == 0)
10654 evexlig = evexl512;
10656 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10659 case OPTION_MEVEXRCIG:
10660 if (strcmp (arg, "rne") == 0)
10662 else if (strcmp (arg, "rd") == 0)
10664 else if (strcmp (arg, "ru") == 0)
10666 else if (strcmp (arg, "rz") == 0)
10669 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10672 case OPTION_MEVEXWIG:
10673 if (strcmp (arg, "0") == 0)
10675 else if (strcmp (arg, "1") == 0)
10678 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10681 # if defined (TE_PE) || defined (TE_PEP)
10682 case OPTION_MBIG_OBJ:
10687 case OPTION_MOMIT_LOCK_PREFIX:
10688 if (strcasecmp (arg, "yes") == 0)
10689 omit_lock_prefix = 1;
10690 else if (strcasecmp (arg, "no") == 0)
10691 omit_lock_prefix = 0;
10693 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10696 case OPTION_MFENCE_AS_LOCK_ADD:
10697 if (strcasecmp (arg, "yes") == 0)
10699 else if (strcasecmp (arg, "no") == 0)
10702 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10705 case OPTION_MRELAX_RELOCATIONS:
10706 if (strcasecmp (arg, "yes") == 0)
10707 generate_relax_relocations = 1;
10708 else if (strcasecmp (arg, "no") == 0)
10709 generate_relax_relocations = 0;
10711 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10714 case OPTION_MAMD64:
10718 case OPTION_MINTEL64:
10726 /* Turn off -Os. */
10727 optimize_for_space = 0;
10729 else if (*arg == 's')
10731 optimize_for_space = 1;
10732 /* Turn on all encoding optimizations. */
10737 optimize = atoi (arg);
10738 /* Turn off -Os. */
10739 optimize_for_space = 0;
10749 #define MESSAGE_TEMPLATE \
10753 output_message (FILE *stream, char *p, char *message, char *start,
10754 int *left_p, const char *name, int len)
10756 int size = sizeof (MESSAGE_TEMPLATE);
10757 int left = *left_p;
10759 /* Reserve 2 spaces for ", " or ",\0" */
10762 /* Check if there is any room. */
10770 p = mempcpy (p, name, len);
10774 /* Output the current message now and start a new one. */
10777 fprintf (stream, "%s\n", message);
10779 left = size - (start - message) - len - 2;
10781 gas_assert (left >= 0);
10783 p = mempcpy (p, name, len);
10791 show_arch (FILE *stream, int ext, int check)
10793 static char message[] = MESSAGE_TEMPLATE;
10794 char *start = message + 27;
10796 int size = sizeof (MESSAGE_TEMPLATE);
10803 left = size - (start - message);
10804 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10806 /* Should it be skipped? */
10807 if (cpu_arch [j].skip)
10810 name = cpu_arch [j].name;
10811 len = cpu_arch [j].len;
10814 /* It is an extension. Skip if we aren't asked to show it. */
10825 /* It is an processor. Skip if we show only extension. */
10828 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10830 /* It is an impossible processor - skip. */
10834 p = output_message (stream, p, message, start, &left, name, len);
10837 /* Display disabled extensions. */
10839 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10841 name = cpu_noarch [j].name;
10842 len = cpu_noarch [j].len;
10843 p = output_message (stream, p, message, start, &left, name,
10848 fprintf (stream, "%s\n", message);
10852 md_show_usage (FILE *stream)
10854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10855 fprintf (stream, _("\
10857 -V print assembler version number\n\
10860 fprintf (stream, _("\
10861 -n Do not optimize code alignment\n\
10862 -q quieten some warnings\n"));
10863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10864 fprintf (stream, _("\
10867 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10868 || defined (TE_PE) || defined (TE_PEP))
10869 fprintf (stream, _("\
10870 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10872 #ifdef SVR4_COMMENT_CHARS
10873 fprintf (stream, _("\
10874 --divide do not treat `/' as a comment character\n"));
10876 fprintf (stream, _("\
10877 --divide ignored\n"));
10879 fprintf (stream, _("\
10880 -march=CPU[,+EXTENSION...]\n\
10881 generate code for CPU and EXTENSION, CPU is one of:\n"));
10882 show_arch (stream, 0, 1);
10883 fprintf (stream, _("\
10884 EXTENSION is combination of:\n"));
10885 show_arch (stream, 1, 0);
10886 fprintf (stream, _("\
10887 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10888 show_arch (stream, 0, 0);
10889 fprintf (stream, _("\
10890 -msse2avx encode SSE instructions with VEX prefix\n"));
10891 fprintf (stream, _("\
10892 -msse-check=[none|error|warning]\n\
10893 check SSE instructions\n"));
10894 fprintf (stream, _("\
10895 -moperand-check=[none|error|warning]\n\
10896 check operand combinations for validity\n"));
10897 fprintf (stream, _("\
10898 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10900 fprintf (stream, _("\
10901 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10903 fprintf (stream, _("\
10904 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10905 for EVEX.W bit ignored instructions\n"));
10906 fprintf (stream, _("\
10907 -mevexrcig=[rne|rd|ru|rz]\n\
10908 encode EVEX instructions with specific EVEX.RC value\n\
10909 for SAE-only ignored instructions\n"));
10910 fprintf (stream, _("\
10911 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10912 fprintf (stream, _("\
10913 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10914 fprintf (stream, _("\
10915 -mindex-reg support pseudo index registers\n"));
10916 fprintf (stream, _("\
10917 -mnaked-reg don't require `%%' prefix for registers\n"));
10918 fprintf (stream, _("\
10919 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10920 fprintf (stream, _("\
10921 -mshared disable branch optimization for shared code\n"));
10922 # if defined (TE_PE) || defined (TE_PEP)
10923 fprintf (stream, _("\
10924 -mbig-obj generate big object files\n"));
10926 fprintf (stream, _("\
10927 -momit-lock-prefix=[no|yes]\n\
10928 strip all lock prefixes\n"));
10929 fprintf (stream, _("\
10930 -mfence-as-lock-add=[no|yes]\n\
10931 encode lfence, mfence and sfence as\n\
10932 lock addl $0x0, (%%{re}sp)\n"));
10933 fprintf (stream, _("\
10934 -mrelax-relocations=[no|yes]\n\
10935 generate relax relocations\n"));
10936 fprintf (stream, _("\
10937 -mamd64 accept only AMD64 ISA\n"));
10938 fprintf (stream, _("\
10939 -mintel64 accept only Intel64 ISA\n"));
10942 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10943 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10944 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10946 /* Pick the target format to use. */
10949 i386_target_format (void)
10951 if (!strncmp (default_arch, "x86_64", 6))
10953 update_code_flag (CODE_64BIT, 1);
10954 if (default_arch[6] == '\0')
10955 x86_elf_abi = X86_64_ABI;
10957 x86_elf_abi = X86_64_X32_ABI;
10959 else if (!strcmp (default_arch, "i386"))
10960 update_code_flag (CODE_32BIT, 1);
10961 else if (!strcmp (default_arch, "iamcu"))
10963 update_code_flag (CODE_32BIT, 1);
10964 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10966 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10967 cpu_arch_name = "iamcu";
10968 cpu_sub_arch_name = NULL;
10969 cpu_arch_flags = iamcu_flags;
10970 cpu_arch_isa = PROCESSOR_IAMCU;
10971 cpu_arch_isa_flags = iamcu_flags;
10972 if (!cpu_arch_tune_set)
10974 cpu_arch_tune = cpu_arch_isa;
10975 cpu_arch_tune_flags = cpu_arch_isa_flags;
10978 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10979 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10983 as_fatal (_("unknown architecture"));
10985 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10986 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10987 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10988 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10990 switch (OUTPUT_FLAVOR)
10992 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10993 case bfd_target_aout_flavour:
10994 return AOUT_TARGET_FORMAT;
10996 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10997 # if defined (TE_PE) || defined (TE_PEP)
10998 case bfd_target_coff_flavour:
10999 if (flag_code == CODE_64BIT)
11000 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11003 # elif defined (TE_GO32)
11004 case bfd_target_coff_flavour:
11005 return "coff-go32";
11007 case bfd_target_coff_flavour:
11008 return "coff-i386";
11011 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11012 case bfd_target_elf_flavour:
11014 const char *format;
11016 switch (x86_elf_abi)
11019 format = ELF_TARGET_FORMAT;
11022 use_rela_relocations = 1;
11024 format = ELF_TARGET_FORMAT64;
11026 case X86_64_X32_ABI:
11027 use_rela_relocations = 1;
11029 disallow_64bit_reloc = 1;
11030 format = ELF_TARGET_FORMAT32;
11033 if (cpu_arch_isa == PROCESSOR_L1OM)
11035 if (x86_elf_abi != X86_64_ABI)
11036 as_fatal (_("Intel L1OM is 64bit only"));
11037 return ELF_TARGET_L1OM_FORMAT;
11039 else if (cpu_arch_isa == PROCESSOR_K1OM)
11041 if (x86_elf_abi != X86_64_ABI)
11042 as_fatal (_("Intel K1OM is 64bit only"));
11043 return ELF_TARGET_K1OM_FORMAT;
11045 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11047 if (x86_elf_abi != I386_ABI)
11048 as_fatal (_("Intel MCU is 32bit only"));
11049 return ELF_TARGET_IAMCU_FORMAT;
11055 #if defined (OBJ_MACH_O)
11056 case bfd_target_mach_o_flavour:
11057 if (flag_code == CODE_64BIT)
11059 use_rela_relocations = 1;
11061 return "mach-o-x86-64";
11064 return "mach-o-i386";
11072 #endif /* OBJ_MAYBE_ more than one */
11075 md_undefined_symbol (char *name)
11077 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11078 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11079 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11080 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11084 if (symbol_find (name))
11085 as_bad (_("GOT already in symbol table"));
11086 GOT_symbol = symbol_new (name, undefined_section,
11087 (valueT) 0, &zero_address_frag);
11094 /* Round up a section size to the appropriate boundary. */
11097 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11099 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11100 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11102 /* For a.out, force the section size to be aligned. If we don't do
11103 this, BFD will align it for us, but it will not write out the
11104 final bytes of the section. This may be a bug in BFD, but it is
11105 easier to fix it here since that is how the other a.out targets
11109 align = bfd_get_section_alignment (stdoutput, segment);
11110 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11117 /* On the i386, PC-relative offsets are relative to the start of the
11118 next instruction. That is, the address of the offset, plus its
11119 size, since the offset is always the last part of the insn. */
11122 md_pcrel_from (fixS *fixP)
11124 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11130 s_bss (int ignore ATTRIBUTE_UNUSED)
11134 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11136 obj_elf_section_change_hook ();
11138 temp = get_absolute_expression ();
11139 subseg_set (bss_section, (subsegT) temp);
11140 demand_empty_rest_of_line ();
11146 i386_validate_fix (fixS *fixp)
11148 if (fixp->fx_subsy)
11150 if (fixp->fx_subsy == GOT_symbol)
11152 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11157 if (fixp->fx_tcbit2)
11158 fixp->fx_r_type = (fixp->fx_tcbit
11159 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11160 : BFD_RELOC_X86_64_GOTPCRELX);
11163 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11168 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11170 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11172 fixp->fx_subsy = 0;
11175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11176 else if (!object_64bit)
11178 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11179 && fixp->fx_tcbit2)
11180 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11186 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11189 bfd_reloc_code_real_type code;
11191 switch (fixp->fx_r_type)
11193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11194 case BFD_RELOC_SIZE32:
11195 case BFD_RELOC_SIZE64:
11196 if (S_IS_DEFINED (fixp->fx_addsy)
11197 && !S_IS_EXTERNAL (fixp->fx_addsy))
11199 /* Resolve size relocation against local symbol to size of
11200 the symbol plus addend. */
11201 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11202 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11203 && !fits_in_unsigned_long (value))
11204 as_bad_where (fixp->fx_file, fixp->fx_line,
11205 _("symbol size computation overflow"));
11206 fixp->fx_addsy = NULL;
11207 fixp->fx_subsy = NULL;
11208 md_apply_fix (fixp, (valueT *) &value, NULL);
11212 /* Fall through. */
11214 case BFD_RELOC_X86_64_PLT32:
11215 case BFD_RELOC_X86_64_GOT32:
11216 case BFD_RELOC_X86_64_GOTPCREL:
11217 case BFD_RELOC_X86_64_GOTPCRELX:
11218 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11219 case BFD_RELOC_386_PLT32:
11220 case BFD_RELOC_386_GOT32:
11221 case BFD_RELOC_386_GOT32X:
11222 case BFD_RELOC_386_GOTOFF:
11223 case BFD_RELOC_386_GOTPC:
11224 case BFD_RELOC_386_TLS_GD:
11225 case BFD_RELOC_386_TLS_LDM:
11226 case BFD_RELOC_386_TLS_LDO_32:
11227 case BFD_RELOC_386_TLS_IE_32:
11228 case BFD_RELOC_386_TLS_IE:
11229 case BFD_RELOC_386_TLS_GOTIE:
11230 case BFD_RELOC_386_TLS_LE_32:
11231 case BFD_RELOC_386_TLS_LE:
11232 case BFD_RELOC_386_TLS_GOTDESC:
11233 case BFD_RELOC_386_TLS_DESC_CALL:
11234 case BFD_RELOC_X86_64_TLSGD:
11235 case BFD_RELOC_X86_64_TLSLD:
11236 case BFD_RELOC_X86_64_DTPOFF32:
11237 case BFD_RELOC_X86_64_DTPOFF64:
11238 case BFD_RELOC_X86_64_GOTTPOFF:
11239 case BFD_RELOC_X86_64_TPOFF32:
11240 case BFD_RELOC_X86_64_TPOFF64:
11241 case BFD_RELOC_X86_64_GOTOFF64:
11242 case BFD_RELOC_X86_64_GOTPC32:
11243 case BFD_RELOC_X86_64_GOT64:
11244 case BFD_RELOC_X86_64_GOTPCREL64:
11245 case BFD_RELOC_X86_64_GOTPC64:
11246 case BFD_RELOC_X86_64_GOTPLT64:
11247 case BFD_RELOC_X86_64_PLTOFF64:
11248 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11249 case BFD_RELOC_X86_64_TLSDESC_CALL:
11250 case BFD_RELOC_RVA:
11251 case BFD_RELOC_VTABLE_ENTRY:
11252 case BFD_RELOC_VTABLE_INHERIT:
11254 case BFD_RELOC_32_SECREL:
11256 code = fixp->fx_r_type;
11258 case BFD_RELOC_X86_64_32S:
11259 if (!fixp->fx_pcrel)
11261 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11262 code = fixp->fx_r_type;
11265 /* Fall through. */
11267 if (fixp->fx_pcrel)
11269 switch (fixp->fx_size)
11272 as_bad_where (fixp->fx_file, fixp->fx_line,
11273 _("can not do %d byte pc-relative relocation"),
11275 code = BFD_RELOC_32_PCREL;
11277 case 1: code = BFD_RELOC_8_PCREL; break;
11278 case 2: code = BFD_RELOC_16_PCREL; break;
11279 case 4: code = BFD_RELOC_32_PCREL; break;
11281 case 8: code = BFD_RELOC_64_PCREL; break;
11287 switch (fixp->fx_size)
11290 as_bad_where (fixp->fx_file, fixp->fx_line,
11291 _("can not do %d byte relocation"),
11293 code = BFD_RELOC_32;
11295 case 1: code = BFD_RELOC_8; break;
11296 case 2: code = BFD_RELOC_16; break;
11297 case 4: code = BFD_RELOC_32; break;
11299 case 8: code = BFD_RELOC_64; break;
11306 if ((code == BFD_RELOC_32
11307 || code == BFD_RELOC_32_PCREL
11308 || code == BFD_RELOC_X86_64_32S)
11310 && fixp->fx_addsy == GOT_symbol)
11313 code = BFD_RELOC_386_GOTPC;
11315 code = BFD_RELOC_X86_64_GOTPC32;
11317 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11319 && fixp->fx_addsy == GOT_symbol)
11321 code = BFD_RELOC_X86_64_GOTPC64;
11324 rel = XNEW (arelent);
11325 rel->sym_ptr_ptr = XNEW (asymbol *);
11326 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11328 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11330 if (!use_rela_relocations)
11332 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11333 vtable entry to be used in the relocation's section offset. */
11334 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11335 rel->address = fixp->fx_offset;
11336 #if defined (OBJ_COFF) && defined (TE_PE)
11337 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11338 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11343 /* Use the rela in 64bit mode. */
11346 if (disallow_64bit_reloc)
11349 case BFD_RELOC_X86_64_DTPOFF64:
11350 case BFD_RELOC_X86_64_TPOFF64:
11351 case BFD_RELOC_64_PCREL:
11352 case BFD_RELOC_X86_64_GOTOFF64:
11353 case BFD_RELOC_X86_64_GOT64:
11354 case BFD_RELOC_X86_64_GOTPCREL64:
11355 case BFD_RELOC_X86_64_GOTPC64:
11356 case BFD_RELOC_X86_64_GOTPLT64:
11357 case BFD_RELOC_X86_64_PLTOFF64:
11358 as_bad_where (fixp->fx_file, fixp->fx_line,
11359 _("cannot represent relocation type %s in x32 mode"),
11360 bfd_get_reloc_code_name (code));
11366 if (!fixp->fx_pcrel)
11367 rel->addend = fixp->fx_offset;
11371 case BFD_RELOC_X86_64_PLT32:
11372 case BFD_RELOC_X86_64_GOT32:
11373 case BFD_RELOC_X86_64_GOTPCREL:
11374 case BFD_RELOC_X86_64_GOTPCRELX:
11375 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11376 case BFD_RELOC_X86_64_TLSGD:
11377 case BFD_RELOC_X86_64_TLSLD:
11378 case BFD_RELOC_X86_64_GOTTPOFF:
11379 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11380 case BFD_RELOC_X86_64_TLSDESC_CALL:
11381 rel->addend = fixp->fx_offset - fixp->fx_size;
11384 rel->addend = (section->vma
11386 + fixp->fx_addnumber
11387 + md_pcrel_from (fixp));
11392 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11393 if (rel->howto == NULL)
11395 as_bad_where (fixp->fx_file, fixp->fx_line,
11396 _("cannot represent relocation type %s"),
11397 bfd_get_reloc_code_name (code));
11398 /* Set howto to a garbage value so that we can keep going. */
11399 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11400 gas_assert (rel->howto != NULL);
11406 #include "tc-i386-intel.c"
11409 tc_x86_parse_to_dw2regnum (expressionS *exp)
11411 int saved_naked_reg;
11412 char saved_register_dot;
11414 saved_naked_reg = allow_naked_reg;
11415 allow_naked_reg = 1;
11416 saved_register_dot = register_chars['.'];
11417 register_chars['.'] = '.';
11418 allow_pseudo_reg = 1;
11419 expression_and_evaluate (exp);
11420 allow_pseudo_reg = 0;
11421 register_chars['.'] = saved_register_dot;
11422 allow_naked_reg = saved_naked_reg;
11424 if (exp->X_op == O_register && exp->X_add_number >= 0)
11426 if ((addressT) exp->X_add_number < i386_regtab_size)
11428 exp->X_op = O_constant;
11429 exp->X_add_number = i386_regtab[exp->X_add_number]
11430 .dw2_regnum[flag_code >> 1];
11433 exp->X_op = O_illegal;
11438 tc_x86_frame_initial_instructions (void)
11440 static unsigned int sp_regno[2];
11442 if (!sp_regno[flag_code >> 1])
11444 char *saved_input = input_line_pointer;
11445 char sp[][4] = {"esp", "rsp"};
11448 input_line_pointer = sp[flag_code >> 1];
11449 tc_x86_parse_to_dw2regnum (&exp);
11450 gas_assert (exp.X_op == O_constant);
11451 sp_regno[flag_code >> 1] = exp.X_add_number;
11452 input_line_pointer = saved_input;
11455 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11456 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11460 x86_dwarf2_addr_size (void)
11462 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11463 if (x86_elf_abi == X86_64_X32_ABI)
11466 return bfd_arch_bits_per_address (stdoutput) / 8;
11470 i386_elf_section_type (const char *str, size_t len)
11472 if (flag_code == CODE_64BIT
11473 && len == sizeof ("unwind") - 1
11474 && strncmp (str, "unwind", 6) == 0)
11475 return SHT_X86_64_UNWIND;
11482 i386_solaris_fix_up_eh_frame (segT sec)
11484 if (flag_code == CODE_64BIT)
11485 elf_section_type (sec) = SHT_X86_64_UNWIND;
11491 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11495 exp.X_op = O_secrel;
11496 exp.X_add_symbol = symbol;
11497 exp.X_add_number = 0;
11498 emit_expr (&exp, size);
11502 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11503 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11506 x86_64_section_letter (int letter, const char **ptr_msg)
11508 if (flag_code == CODE_64BIT)
11511 return SHF_X86_64_LARGE;
11513 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11516 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11521 x86_64_section_word (char *str, size_t len)
11523 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11524 return SHF_X86_64_LARGE;
11530 handle_large_common (int small ATTRIBUTE_UNUSED)
11532 if (flag_code != CODE_64BIT)
11534 s_comm_internal (0, elf_common_parse);
11535 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11539 static segT lbss_section;
11540 asection *saved_com_section_ptr = elf_com_section_ptr;
11541 asection *saved_bss_section = bss_section;
11543 if (lbss_section == NULL)
11545 flagword applicable;
11546 segT seg = now_seg;
11547 subsegT subseg = now_subseg;
11549 /* The .lbss section is for local .largecomm symbols. */
11550 lbss_section = subseg_new (".lbss", 0);
11551 applicable = bfd_applicable_section_flags (stdoutput);
11552 bfd_set_section_flags (stdoutput, lbss_section,
11553 applicable & SEC_ALLOC);
11554 seg_info (lbss_section)->bss = 1;
11556 subseg_set (seg, subseg);
11559 elf_com_section_ptr = &_bfd_elf_large_com_section;
11560 bss_section = lbss_section;
11562 s_comm_internal (0, elf_common_parse);
11564 elf_com_section_ptr = saved_com_section_ptr;
11565 bss_section = saved_bss_section;
11568 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */