1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if pseudo registers are permitted. */
417 static int allow_pseudo_reg = 0;
419 /* 1 if register prefix % not required. */
420 static int allow_naked_reg = 0;
422 /* 1 if pseudo index register, eiz/riz, is allowed . */
423 static int allow_index_reg = 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix = "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size = '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code = 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings = 0;
440 static const char *cpu_arch_name = NULL;
441 static char *cpu_sub_arch_name = NULL;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set = 0;
449 /* Cpu we are generating instructions for. */
450 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags;
455 /* CPU instruction set architecture used. */
456 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
458 /* CPU feature flags of instruction set architecture used. */
459 static i386_cpu_flags cpu_arch_isa_flags;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion = 0;
465 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
466 static symbolS *GOT_symbol;
468 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
469 unsigned int x86_dwarf2_return_column;
471 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472 int x86_cie_data_alignment;
474 /* Interface to relax_segment.
475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
480 #define UNCOND_JUMP 0
482 #define COND_JUMP86 2
487 #define SMALL16 (SMALL | CODE16)
489 #define BIG16 (BIG | CODE16)
493 #define INLINE __inline__
499 #define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501 #define TYPE_FROM_RELAX_STATE(s) \
503 #define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
506 /* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
514 const relax_typeS md_relax_table[] =
517 1) most positive reach of this state,
518 2) most negative reach of this state,
519 3) how many bytes this mode will have in the variable part of the frag
520 4) which index into the table to try if we can't fit into this one. */
522 /* UNCOND_JUMP states. */
523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
538 /* word conditionals add 3 bytes to frag:
539 1 extra opcode byte, 2 displacement bytes. */
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
553 static const arch_entry cpu_arch[] =
555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
561 { "i186", PROCESSOR_UNKNOWN,
563 { "i286", PROCESSOR_UNKNOWN,
565 { "i386", PROCESSOR_I386,
567 { "i486", PROCESSOR_I486,
569 { "i586", PROCESSOR_PENTIUM,
571 { "i686", PROCESSOR_PENTIUMPRO,
573 { "pentium", PROCESSOR_PENTIUM,
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
581 { "pentium4", PROCESSOR_PENTIUM4,
583 { "prescott", PROCESSOR_NOCONA,
585 { "nocona", PROCESSOR_NOCONA,
587 { "yonah", PROCESSOR_CORE,
589 { "core", PROCESSOR_CORE,
591 { "merom", PROCESSOR_CORE2,
593 { "core2", PROCESSOR_CORE2,
595 { "k6", PROCESSOR_K6,
597 { "k6_2", PROCESSOR_K6,
599 { "athlon", PROCESSOR_ATHLON,
601 { "sledgehammer", PROCESSOR_K8,
603 { "opteron", PROCESSOR_K8,
605 { "k8", PROCESSOR_K8,
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
611 { ".sse", PROCESSOR_UNKNOWN,
613 { ".sse2", PROCESSOR_UNKNOWN,
615 { ".sse3", PROCESSOR_UNKNOWN,
617 { ".ssse3", PROCESSOR_UNKNOWN,
619 { ".sse4.1", PROCESSOR_UNKNOWN,
621 { ".sse4.2", PROCESSOR_UNKNOWN,
623 { ".sse4", PROCESSOR_UNKNOWN,
625 { ".vmx", PROCESSOR_UNKNOWN,
627 { ".smx", PROCESSOR_UNKNOWN,
629 { ".xsave", PROCESSOR_UNKNOWN,
631 { ".3dnow", PROCESSOR_UNKNOWN,
633 { ".3dnowa", PROCESSOR_UNKNOWN,
635 { ".padlock", PROCESSOR_UNKNOWN,
637 { ".pacifica", PROCESSOR_UNKNOWN,
639 { ".svme", PROCESSOR_UNKNOWN,
641 { ".sse4a", PROCESSOR_UNKNOWN,
643 { ".abm", PROCESSOR_UNKNOWN,
645 { ".sse5", PROCESSOR_UNKNOWN,
649 const pseudo_typeS md_pseudo_table[] =
651 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
654 {"align", s_align_ptwo, 0},
656 {"arch", set_cpu_arch, 0},
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
664 {"slong", signed_cons, 4},
665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
685 {"secrel32", pe_directive_secrel, 0},
690 /* For interface with expression (). */
691 extern char *input_line_pointer;
693 /* Hash table for instruction mnemonic lookup. */
694 static struct hash_control *op_hash;
696 /* Hash table for register lookup. */
697 static struct hash_control *reg_hash;
700 i386_align_code (fragS *fragP, int count)
702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
705 static const char f32_1[] =
707 static const char f32_2[] =
708 {0x66,0x90}; /* xchg %ax,%ax */
709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
766 static const char *const f16_patt[] = {
767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
770 static const char alt_3[] =
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
896 if (flag_code == CODE_16BIT)
900 memcpy (fragP->fr_literal + fragP->fr_fix,
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
911 const char *const *patt = NULL;
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
921 if (cpu_arch_isa_flags.bitfield.cpui686)
922 patt = alt_long_patt;
926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
935 case PROCESSOR_ATHLON:
937 case PROCESSOR_AMDFAM10:
938 patt = alt_short_patt;
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
950 switch (cpu_arch_tune)
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
960 case PROCESSOR_PENTIUM:
962 case PROCESSOR_ATHLON:
964 case PROCESSOR_AMDFAM10:
965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
968 if (cpu_arch_isa_flags.bitfield.cpui686)
969 patt = alt_short_patt;
973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
977 case PROCESSOR_CORE2:
978 if (cpu_arch_isa_flags.bitfield.cpui686)
979 patt = alt_long_patt;
983 case PROCESSOR_GENERIC64:
984 patt = alt_long_patt;
989 if (patt == f32_patt)
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1023 fragP->fr_var = count;
1027 uints_all_zero (const unsigned int *x, unsigned int size)
1045 uints_set (unsigned int *x, unsigned int v, unsigned int size)
1062 uints_equal (const unsigned int *x, const unsigned int *y,
1074 return x[0] == y [0];
1081 #define UINTS_ALL_ZERO(x) \
1082 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
1083 #define UINTS_SET(x, v) \
1084 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
1085 #define UINTS_CLEAR(x) \
1086 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
1087 #define UINTS_EQUAL(x, y) \
1088 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
1091 cpu_flags_check_cpu64 (i386_cpu_flags f)
1093 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1094 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1097 static INLINE i386_cpu_flags
1098 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1100 switch (ARRAY_SIZE (x.array))
1103 x.array [2] &= y.array [2];
1105 x.array [1] &= y.array [1];
1107 x.array [0] &= y.array [0];
1115 static INLINE i386_cpu_flags
1116 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1118 switch (ARRAY_SIZE (x.array))
1121 x.array [2] |= y.array [2];
1123 x.array [1] |= y.array [1];
1125 x.array [0] |= y.array [0];
1133 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1134 1 if compatible with arch, 0 if there is no match. */
1137 cpu_flags_match (i386_cpu_flags x)
1139 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1141 x.bitfield.cpu64 = 0;
1142 x.bitfield.cpuno64 = 0;
1144 if (UINTS_ALL_ZERO (x))
1148 i386_cpu_flags cpu = cpu_arch_flags;
1150 cpu.bitfield.cpu64 = 0;
1151 cpu.bitfield.cpuno64 = 0;
1152 cpu = cpu_flags_and (x, cpu);
1153 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1158 static INLINE i386_operand_type
1159 operand_type_and (i386_operand_type x, i386_operand_type y)
1161 switch (ARRAY_SIZE (x.array))
1164 x.array [2] &= y.array [2];
1166 x.array [1] &= y.array [1];
1168 x.array [0] &= y.array [0];
1176 static INLINE i386_operand_type
1177 operand_type_or (i386_operand_type x, i386_operand_type y)
1179 switch (ARRAY_SIZE (x.array))
1182 x.array [2] |= y.array [2];
1184 x.array [1] |= y.array [1];
1186 x.array [0] |= y.array [0];
1194 static INLINE i386_operand_type
1195 operand_type_xor (i386_operand_type x, i386_operand_type y)
1197 switch (ARRAY_SIZE (x.array))
1200 x.array [2] ^= y.array [2];
1202 x.array [1] ^= y.array [1];
1204 x.array [0] ^= y.array [0];
1212 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1213 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1214 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1215 static const i386_operand_type reg16_inoutportreg
1216 = OPERAND_TYPE_REG16_INOUTPORTREG;
1217 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1218 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1219 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1220 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1221 static const i386_operand_type anydisp
1222 = OPERAND_TYPE_ANYDISP;
1223 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1224 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1225 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1226 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1227 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1228 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1229 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1230 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1231 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1232 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1243 operand_type_check (i386_operand_type t, enum operand_type c)
1248 return (t.bitfield.reg8
1251 || t.bitfield.reg64);
1254 return (t.bitfield.imm8
1258 || t.bitfield.imm32s
1259 || t.bitfield.imm64);
1262 return (t.bitfield.disp8
1263 || t.bitfield.disp16
1264 || t.bitfield.disp32
1265 || t.bitfield.disp32s
1266 || t.bitfield.disp64);
1269 return (t.bitfield.disp8
1270 || t.bitfield.disp16
1271 || t.bitfield.disp32
1272 || t.bitfield.disp32s
1273 || t.bitfield.disp64
1274 || t.bitfield.baseindex);
1281 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1282 operand J for instruction template T. */
1285 match_reg_size (const template *t, unsigned int j)
1287 return !((i.types[j].bitfield.byte
1288 && !t->operand_types[j].bitfield.byte)
1289 || (i.types[j].bitfield.word
1290 && !t->operand_types[j].bitfield.word)
1291 || (i.types[j].bitfield.dword
1292 && !t->operand_types[j].bitfield.dword)
1293 || (i.types[j].bitfield.qword
1294 && !t->operand_types[j].bitfield.qword));
1297 /* Return 1 if there is no conflict in any size on operand J for
1298 instruction template T. */
1301 match_mem_size (const template *t, unsigned int j)
1303 return (match_reg_size (t, j)
1304 && !((i.types[j].bitfield.unspecified
1305 && !t->operand_types[j].bitfield.unspecified)
1306 || (i.types[j].bitfield.fword
1307 && !t->operand_types[j].bitfield.fword)
1308 || (i.types[j].bitfield.tbyte
1309 && !t->operand_types[j].bitfield.tbyte)
1310 || (i.types[j].bitfield.xmmword
1311 && !t->operand_types[j].bitfield.xmmword)));
1314 /* Return 1 if there is no size conflict on any operands for
1315 instruction template T. */
1318 operand_size_match (const template *t)
1323 /* Don't check jump instructions. */
1324 if (t->opcode_modifier.jump
1325 || t->opcode_modifier.jumpbyte
1326 || t->opcode_modifier.jumpdword
1327 || t->opcode_modifier.jumpintersegment)
1330 /* Check memory and accumulator operand size. */
1331 for (j = 0; j < i.operands; j++)
1333 if (t->operand_types[j].bitfield.anysize)
1336 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1342 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1350 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1353 /* Check reverse. */
1354 assert (i.operands == 2);
1357 for (j = 0; j < 2; j++)
1359 if (t->operand_types[j].bitfield.acc
1360 && !match_reg_size (t, j ? 0 : 1))
1366 if (i.types[j].bitfield.mem
1367 && !match_mem_size (t, j ? 0 : 1))
1378 operand_type_match (i386_operand_type overlap,
1379 i386_operand_type given)
1381 i386_operand_type temp = overlap;
1383 temp.bitfield.jumpabsolute = 0;
1384 temp.bitfield.unspecified = 0;
1385 temp.bitfield.byte = 0;
1386 temp.bitfield.word = 0;
1387 temp.bitfield.dword = 0;
1388 temp.bitfield.fword = 0;
1389 temp.bitfield.qword = 0;
1390 temp.bitfield.tbyte = 0;
1391 temp.bitfield.xmmword = 0;
1392 if (UINTS_ALL_ZERO (temp))
1395 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1396 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1399 /* If given types g0 and g1 are registers they must be of the same type
1400 unless the expected operand type register overlap is null.
1401 Note that Acc in a template matches every size of reg. */
1404 operand_type_register_match (i386_operand_type m0,
1405 i386_operand_type g0,
1406 i386_operand_type t0,
1407 i386_operand_type m1,
1408 i386_operand_type g1,
1409 i386_operand_type t1)
1411 if (!operand_type_check (g0, reg))
1414 if (!operand_type_check (g1, reg))
1417 if (g0.bitfield.reg8 == g1.bitfield.reg8
1418 && g0.bitfield.reg16 == g1.bitfield.reg16
1419 && g0.bitfield.reg32 == g1.bitfield.reg32
1420 && g0.bitfield.reg64 == g1.bitfield.reg64)
1423 if (m0.bitfield.acc)
1425 t0.bitfield.reg8 = 1;
1426 t0.bitfield.reg16 = 1;
1427 t0.bitfield.reg32 = 1;
1428 t0.bitfield.reg64 = 1;
1431 if (m1.bitfield.acc)
1433 t1.bitfield.reg8 = 1;
1434 t1.bitfield.reg16 = 1;
1435 t1.bitfield.reg32 = 1;
1436 t1.bitfield.reg64 = 1;
1439 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1440 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1441 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1442 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1445 static INLINE unsigned int
1446 mode_from_disp_size (i386_operand_type t)
1448 if (t.bitfield.disp8)
1450 else if (t.bitfield.disp16
1451 || t.bitfield.disp32
1452 || t.bitfield.disp32s)
1459 fits_in_signed_byte (offsetT num)
1461 return (num >= -128) && (num <= 127);
1465 fits_in_unsigned_byte (offsetT num)
1467 return (num & 0xff) == num;
1471 fits_in_unsigned_word (offsetT num)
1473 return (num & 0xffff) == num;
1477 fits_in_signed_word (offsetT num)
1479 return (-32768 <= num) && (num <= 32767);
1483 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1488 return (!(((offsetT) -1 << 31) & num)
1489 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1491 } /* fits_in_signed_long() */
1494 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1499 return (num & (((offsetT) 2 << 31) - 1)) == num;
1501 } /* fits_in_unsigned_long() */
1503 static i386_operand_type
1504 smallest_imm_type (offsetT num)
1506 i386_operand_type t;
1509 t.bitfield.imm64 = 1;
1511 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1513 /* This code is disabled on the 486 because all the Imm1 forms
1514 in the opcode table are slower on the i486. They're the
1515 versions with the implicitly specified single-position
1516 displacement, which has another syntax if you really want to
1518 t.bitfield.imm1 = 1;
1519 t.bitfield.imm8 = 1;
1520 t.bitfield.imm8s = 1;
1521 t.bitfield.imm16 = 1;
1522 t.bitfield.imm32 = 1;
1523 t.bitfield.imm32s = 1;
1525 else if (fits_in_signed_byte (num))
1527 t.bitfield.imm8 = 1;
1528 t.bitfield.imm8s = 1;
1529 t.bitfield.imm16 = 1;
1530 t.bitfield.imm32 = 1;
1531 t.bitfield.imm32s = 1;
1533 else if (fits_in_unsigned_byte (num))
1535 t.bitfield.imm8 = 1;
1536 t.bitfield.imm16 = 1;
1537 t.bitfield.imm32 = 1;
1538 t.bitfield.imm32s = 1;
1540 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1542 t.bitfield.imm16 = 1;
1543 t.bitfield.imm32 = 1;
1544 t.bitfield.imm32s = 1;
1546 else if (fits_in_signed_long (num))
1548 t.bitfield.imm32 = 1;
1549 t.bitfield.imm32s = 1;
1551 else if (fits_in_unsigned_long (num))
1552 t.bitfield.imm32 = 1;
1558 offset_in_range (offsetT val, int size)
1564 case 1: mask = ((addressT) 1 << 8) - 1; break;
1565 case 2: mask = ((addressT) 1 << 16) - 1; break;
1566 case 4: mask = ((addressT) 2 << 31) - 1; break;
1568 case 8: mask = ((addressT) 2 << 63) - 1; break;
1573 /* If BFD64, sign extend val. */
1574 if (!use_rela_relocations)
1575 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1576 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1578 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1580 char buf1[40], buf2[40];
1582 sprint_value (buf1, val);
1583 sprint_value (buf2, val & mask);
1584 as_warn (_("%s shortened to %s"), buf1, buf2);
1589 /* Returns 0 if attempting to add a prefix where one from the same
1590 class already exists, 1 if non rep/repne added, 2 if rep/repne
1593 add_prefix (unsigned int prefix)
1598 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1599 && flag_code == CODE_64BIT)
1601 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1602 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1603 && (prefix & (REX_R | REX_X | REX_B))))
1614 case CS_PREFIX_OPCODE:
1615 case DS_PREFIX_OPCODE:
1616 case ES_PREFIX_OPCODE:
1617 case FS_PREFIX_OPCODE:
1618 case GS_PREFIX_OPCODE:
1619 case SS_PREFIX_OPCODE:
1623 case REPNE_PREFIX_OPCODE:
1624 case REPE_PREFIX_OPCODE:
1627 case LOCK_PREFIX_OPCODE:
1635 case ADDR_PREFIX_OPCODE:
1639 case DATA_PREFIX_OPCODE:
1643 if (i.prefix[q] != 0)
1651 i.prefix[q] |= prefix;
1654 as_bad (_("same type of prefix used twice"));
1660 set_code_flag (int value)
1663 if (flag_code == CODE_64BIT)
1665 cpu_arch_flags.bitfield.cpu64 = 1;
1666 cpu_arch_flags.bitfield.cpuno64 = 0;
1670 cpu_arch_flags.bitfield.cpu64 = 0;
1671 cpu_arch_flags.bitfield.cpuno64 = 1;
1673 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1675 as_bad (_("64bit mode not supported on this CPU."));
1677 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1679 as_bad (_("32bit mode not supported on this CPU."));
1681 stackop_size = '\0';
1685 set_16bit_gcc_code_flag (int new_code_flag)
1687 flag_code = new_code_flag;
1688 if (flag_code != CODE_16BIT)
1690 cpu_arch_flags.bitfield.cpu64 = 0;
1691 cpu_arch_flags.bitfield.cpuno64 = 1;
1692 stackop_size = LONG_MNEM_SUFFIX;
1696 set_intel_syntax (int syntax_flag)
1698 /* Find out if register prefixing is specified. */
1699 int ask_naked_reg = 0;
1702 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1704 char *string = input_line_pointer;
1705 int e = get_symbol_end ();
1707 if (strcmp (string, "prefix") == 0)
1709 else if (strcmp (string, "noprefix") == 0)
1712 as_bad (_("bad argument to syntax directive."));
1713 *input_line_pointer = e;
1715 demand_empty_rest_of_line ();
1717 intel_syntax = syntax_flag;
1719 if (ask_naked_reg == 0)
1720 allow_naked_reg = (intel_syntax
1721 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1723 allow_naked_reg = (ask_naked_reg < 0);
1725 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1726 identifier_chars['$'] = intel_syntax ? '$' : 0;
1727 register_prefix = allow_naked_reg ? "" : "%";
1731 set_intel_mnemonic (int mnemonic_flag)
1733 intel_mnemonic = mnemonic_flag;
1737 set_allow_index_reg (int flag)
1739 allow_index_reg = flag;
1743 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1747 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1749 char *string = input_line_pointer;
1750 int e = get_symbol_end ();
1752 i386_cpu_flags flags;
1754 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1756 if (strcmp (string, cpu_arch[i].name) == 0)
1760 cpu_arch_name = cpu_arch[i].name;
1761 cpu_sub_arch_name = NULL;
1762 cpu_arch_flags = cpu_arch[i].flags;
1763 if (flag_code == CODE_64BIT)
1765 cpu_arch_flags.bitfield.cpu64 = 1;
1766 cpu_arch_flags.bitfield.cpuno64 = 0;
1770 cpu_arch_flags.bitfield.cpu64 = 0;
1771 cpu_arch_flags.bitfield.cpuno64 = 1;
1773 cpu_arch_isa = cpu_arch[i].type;
1774 cpu_arch_isa_flags = cpu_arch[i].flags;
1775 if (!cpu_arch_tune_set)
1777 cpu_arch_tune = cpu_arch_isa;
1778 cpu_arch_tune_flags = cpu_arch_isa_flags;
1783 flags = cpu_flags_or (cpu_arch_flags,
1785 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1787 if (cpu_sub_arch_name)
1789 char *name = cpu_sub_arch_name;
1790 cpu_sub_arch_name = concat (name,
1792 (const char *) NULL);
1796 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1797 cpu_arch_flags = flags;
1799 *input_line_pointer = e;
1800 demand_empty_rest_of_line ();
1804 if (i >= ARRAY_SIZE (cpu_arch))
1805 as_bad (_("no such architecture: `%s'"), string);
1807 *input_line_pointer = e;
1810 as_bad (_("missing cpu architecture"));
1812 no_cond_jump_promotion = 0;
1813 if (*input_line_pointer == ','
1814 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1816 char *string = ++input_line_pointer;
1817 int e = get_symbol_end ();
1819 if (strcmp (string, "nojumps") == 0)
1820 no_cond_jump_promotion = 1;
1821 else if (strcmp (string, "jumps") == 0)
1824 as_bad (_("no such architecture modifier: `%s'"), string);
1826 *input_line_pointer = e;
1829 demand_empty_rest_of_line ();
1835 if (!strcmp (default_arch, "x86_64"))
1836 return bfd_mach_x86_64;
1837 else if (!strcmp (default_arch, "i386"))
1838 return bfd_mach_i386_i386;
1840 as_fatal (_("Unknown architecture"));
1846 const char *hash_err;
1848 /* Initialize op_hash hash table. */
1849 op_hash = hash_new ();
1852 const template *optab;
1853 templates *core_optab;
1855 /* Setup for loop. */
1857 core_optab = (templates *) xmalloc (sizeof (templates));
1858 core_optab->start = optab;
1863 if (optab->name == NULL
1864 || strcmp (optab->name, (optab - 1)->name) != 0)
1866 /* different name --> ship out current template list;
1867 add to hash table; & begin anew. */
1868 core_optab->end = optab;
1869 hash_err = hash_insert (op_hash,
1874 as_fatal (_("Internal Error: Can't hash %s: %s"),
1878 if (optab->name == NULL)
1880 core_optab = (templates *) xmalloc (sizeof (templates));
1881 core_optab->start = optab;
1886 /* Initialize reg_hash hash table. */
1887 reg_hash = hash_new ();
1889 const reg_entry *regtab;
1890 unsigned int regtab_size = i386_regtab_size;
1892 for (regtab = i386_regtab; regtab_size--; regtab++)
1894 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1896 as_fatal (_("Internal Error: Can't hash %s: %s"),
1902 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1907 for (c = 0; c < 256; c++)
1912 mnemonic_chars[c] = c;
1913 register_chars[c] = c;
1914 operand_chars[c] = c;
1916 else if (ISLOWER (c))
1918 mnemonic_chars[c] = c;
1919 register_chars[c] = c;
1920 operand_chars[c] = c;
1922 else if (ISUPPER (c))
1924 mnemonic_chars[c] = TOLOWER (c);
1925 register_chars[c] = mnemonic_chars[c];
1926 operand_chars[c] = c;
1929 if (ISALPHA (c) || ISDIGIT (c))
1930 identifier_chars[c] = c;
1933 identifier_chars[c] = c;
1934 operand_chars[c] = c;
1939 identifier_chars['@'] = '@';
1942 identifier_chars['?'] = '?';
1943 operand_chars['?'] = '?';
1945 digit_chars['-'] = '-';
1946 mnemonic_chars['-'] = '-';
1947 mnemonic_chars['.'] = '.';
1948 identifier_chars['_'] = '_';
1949 identifier_chars['.'] = '.';
1951 for (p = operand_special_chars; *p != '\0'; p++)
1952 operand_chars[(unsigned char) *p] = *p;
1955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1958 record_alignment (text_section, 2);
1959 record_alignment (data_section, 2);
1960 record_alignment (bss_section, 2);
1964 if (flag_code == CODE_64BIT)
1966 x86_dwarf2_return_column = 16;
1967 x86_cie_data_alignment = -8;
1971 x86_dwarf2_return_column = 8;
1972 x86_cie_data_alignment = -4;
1977 i386_print_statistics (FILE *file)
1979 hash_print_statistics (file, "i386 opcode", op_hash);
1980 hash_print_statistics (file, "i386 register", reg_hash);
1985 /* Debugging routines for md_assemble. */
1986 static void pte (template *);
1987 static void pt (i386_operand_type);
1988 static void pe (expressionS *);
1989 static void ps (symbolS *);
1992 pi (char *line, i386_insn *x)
1996 fprintf (stdout, "%s: template ", line);
1998 fprintf (stdout, " address: base %s index %s scale %x\n",
1999 x->base_reg ? x->base_reg->reg_name : "none",
2000 x->index_reg ? x->index_reg->reg_name : "none",
2001 x->log2_scale_factor);
2002 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2003 x->rm.mode, x->rm.reg, x->rm.regmem);
2004 fprintf (stdout, " sib: base %x index %x scale %x\n",
2005 x->sib.base, x->sib.index, x->sib.scale);
2006 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2007 (x->rex & REX_W) != 0,
2008 (x->rex & REX_R) != 0,
2009 (x->rex & REX_X) != 0,
2010 (x->rex & REX_B) != 0);
2011 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2012 x->drex.reg, x->drex.rex);
2013 for (i = 0; i < x->operands; i++)
2015 fprintf (stdout, " #%d: ", i + 1);
2017 fprintf (stdout, "\n");
2018 if (x->types[i].bitfield.reg8
2019 || x->types[i].bitfield.reg16
2020 || x->types[i].bitfield.reg32
2021 || x->types[i].bitfield.reg64
2022 || x->types[i].bitfield.regmmx
2023 || x->types[i].bitfield.regxmm
2024 || x->types[i].bitfield.sreg2
2025 || x->types[i].bitfield.sreg3
2026 || x->types[i].bitfield.control
2027 || x->types[i].bitfield.debug
2028 || x->types[i].bitfield.test)
2029 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2030 if (operand_type_check (x->types[i], imm))
2032 if (operand_type_check (x->types[i], disp))
2033 pe (x->op[i].disps);
2041 fprintf (stdout, " %d operands ", t->operands);
2042 fprintf (stdout, "opcode %x ", t->base_opcode);
2043 if (t->extension_opcode != None)
2044 fprintf (stdout, "ext %x ", t->extension_opcode);
2045 if (t->opcode_modifier.d)
2046 fprintf (stdout, "D");
2047 if (t->opcode_modifier.w)
2048 fprintf (stdout, "W");
2049 fprintf (stdout, "\n");
2050 for (i = 0; i < t->operands; i++)
2052 fprintf (stdout, " #%d type ", i + 1);
2053 pt (t->operand_types[i]);
2054 fprintf (stdout, "\n");
2061 fprintf (stdout, " operation %d\n", e->X_op);
2062 fprintf (stdout, " add_number %ld (%lx)\n",
2063 (long) e->X_add_number, (long) e->X_add_number);
2064 if (e->X_add_symbol)
2066 fprintf (stdout, " add_symbol ");
2067 ps (e->X_add_symbol);
2068 fprintf (stdout, "\n");
2072 fprintf (stdout, " op_symbol ");
2073 ps (e->X_op_symbol);
2074 fprintf (stdout, "\n");
2081 fprintf (stdout, "%s type %s%s",
2083 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2084 segment_name (S_GET_SEGMENT (s)));
2087 static struct type_name
2089 i386_operand_type mask;
2092 const type_names[] =
2094 { OPERAND_TYPE_REG8, "r8" },
2095 { OPERAND_TYPE_REG16, "r16" },
2096 { OPERAND_TYPE_REG32, "r32" },
2097 { OPERAND_TYPE_REG64, "r64" },
2098 { OPERAND_TYPE_IMM8, "i8" },
2099 { OPERAND_TYPE_IMM8, "i8s" },
2100 { OPERAND_TYPE_IMM16, "i16" },
2101 { OPERAND_TYPE_IMM32, "i32" },
2102 { OPERAND_TYPE_IMM32S, "i32s" },
2103 { OPERAND_TYPE_IMM64, "i64" },
2104 { OPERAND_TYPE_IMM1, "i1" },
2105 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2106 { OPERAND_TYPE_DISP8, "d8" },
2107 { OPERAND_TYPE_DISP16, "d16" },
2108 { OPERAND_TYPE_DISP32, "d32" },
2109 { OPERAND_TYPE_DISP32S, "d32s" },
2110 { OPERAND_TYPE_DISP64, "d64" },
2111 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2112 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2113 { OPERAND_TYPE_CONTROL, "control reg" },
2114 { OPERAND_TYPE_TEST, "test reg" },
2115 { OPERAND_TYPE_DEBUG, "debug reg" },
2116 { OPERAND_TYPE_FLOATREG, "FReg" },
2117 { OPERAND_TYPE_FLOATACC, "FAcc" },
2118 { OPERAND_TYPE_SREG2, "SReg2" },
2119 { OPERAND_TYPE_SREG3, "SReg3" },
2120 { OPERAND_TYPE_ACC, "Acc" },
2121 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2122 { OPERAND_TYPE_REGMMX, "rMMX" },
2123 { OPERAND_TYPE_REGXMM, "rXMM" },
2124 { OPERAND_TYPE_ESSEG, "es" },
2128 pt (i386_operand_type t)
2131 i386_operand_type a;
2133 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2135 a = operand_type_and (t, type_names[j].mask);
2136 if (!UINTS_ALL_ZERO (a))
2137 fprintf (stdout, "%s, ", type_names[j].name);
2142 #endif /* DEBUG386 */
2144 static bfd_reloc_code_real_type
2145 reloc (unsigned int size,
2148 bfd_reloc_code_real_type other)
2150 if (other != NO_RELOC)
2152 reloc_howto_type *reloc;
2157 case BFD_RELOC_X86_64_GOT32:
2158 return BFD_RELOC_X86_64_GOT64;
2160 case BFD_RELOC_X86_64_PLTOFF64:
2161 return BFD_RELOC_X86_64_PLTOFF64;
2163 case BFD_RELOC_X86_64_GOTPC32:
2164 other = BFD_RELOC_X86_64_GOTPC64;
2166 case BFD_RELOC_X86_64_GOTPCREL:
2167 other = BFD_RELOC_X86_64_GOTPCREL64;
2169 case BFD_RELOC_X86_64_TPOFF32:
2170 other = BFD_RELOC_X86_64_TPOFF64;
2172 case BFD_RELOC_X86_64_DTPOFF32:
2173 other = BFD_RELOC_X86_64_DTPOFF64;
2179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2180 if (size == 4 && flag_code != CODE_64BIT)
2183 reloc = bfd_reloc_type_lookup (stdoutput, other);
2185 as_bad (_("unknown relocation (%u)"), other);
2186 else if (size != bfd_get_reloc_size (reloc))
2187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2188 bfd_get_reloc_size (reloc),
2190 else if (pcrel && !reloc->pc_relative)
2191 as_bad (_("non-pc-relative relocation for pc-relative field"));
2192 else if ((reloc->complain_on_overflow == complain_overflow_signed
2194 || (reloc->complain_on_overflow == complain_overflow_unsigned
2196 as_bad (_("relocated field and relocation type differ in signedness"));
2205 as_bad (_("there are no unsigned pc-relative relocations"));
2208 case 1: return BFD_RELOC_8_PCREL;
2209 case 2: return BFD_RELOC_16_PCREL;
2210 case 4: return BFD_RELOC_32_PCREL;
2211 case 8: return BFD_RELOC_64_PCREL;
2213 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2220 case 4: return BFD_RELOC_X86_64_32S;
2225 case 1: return BFD_RELOC_8;
2226 case 2: return BFD_RELOC_16;
2227 case 4: return BFD_RELOC_32;
2228 case 8: return BFD_RELOC_64;
2230 as_bad (_("cannot do %s %u byte relocation"),
2231 sign > 0 ? "signed" : "unsigned", size);
2235 return BFD_RELOC_NONE;
2238 /* Here we decide which fixups can be adjusted to make them relative to
2239 the beginning of the section instead of the symbol. Basically we need
2240 to make sure that the dynamic relocations are done correctly, so in
2241 some cases we force the original symbol to be used. */
2244 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2250 /* Don't adjust pc-relative references to merge sections in 64-bit
2252 if (use_rela_relocations
2253 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2257 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2258 and changed later by validate_fix. */
2259 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2260 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2263 /* adjust_reloc_syms doesn't know about the GOT. */
2264 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2265 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2266 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2267 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2268 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2269 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2270 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2271 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2272 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2273 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2274 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2275 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2276 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2277 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2278 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2279 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2280 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2281 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2282 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2283 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2284 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2285 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2286 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2287 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2288 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2289 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2290 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2291 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2298 intel_float_operand (const char *mnemonic)
2300 /* Note that the value returned is meaningful only for opcodes with (memory)
2301 operands, hence the code here is free to improperly handle opcodes that
2302 have no operands (for better performance and smaller code). */
2304 if (mnemonic[0] != 'f')
2305 return 0; /* non-math */
2307 switch (mnemonic[1])
2309 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2310 the fs segment override prefix not currently handled because no
2311 call path can make opcodes without operands get here */
2313 return 2 /* integer op */;
2315 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2316 return 3; /* fldcw/fldenv */
2319 if (mnemonic[2] != 'o' /* fnop */)
2320 return 3; /* non-waiting control op */
2323 if (mnemonic[2] == 's')
2324 return 3; /* frstor/frstpm */
2327 if (mnemonic[2] == 'a')
2328 return 3; /* fsave */
2329 if (mnemonic[2] == 't')
2331 switch (mnemonic[3])
2333 case 'c': /* fstcw */
2334 case 'd': /* fstdw */
2335 case 'e': /* fstenv */
2336 case 's': /* fsts[gw] */
2342 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2343 return 0; /* fxsave/fxrstor are not really math ops */
2350 /* This is the guts of the machine-dependent assembler. LINE points to a
2351 machine dependent instruction. This function is supposed to emit
2352 the frags/bytes it assembles to. */
2359 char mnemonic[MAX_MNEM_SIZE];
2361 /* Initialize globals. */
2362 memset (&i, '\0', sizeof (i));
2363 for (j = 0; j < MAX_OPERANDS; j++)
2364 i.reloc[j] = NO_RELOC;
2365 memset (disp_expressions, '\0', sizeof (disp_expressions));
2366 memset (im_expressions, '\0', sizeof (im_expressions));
2367 save_stack_p = save_stack;
2369 /* First parse an instruction mnemonic & call i386_operand for the operands.
2370 We assume that the scrubber has arranged it so that line[0] is the valid
2371 start of a (possibly prefixed) mnemonic. */
2373 line = parse_insn (line, mnemonic);
2377 line = parse_operands (line, mnemonic);
2381 /* Now we've parsed the mnemonic into a set of templates, and have the
2382 operands at hand. */
2384 /* All intel opcodes have reversed operands except for "bound" and
2385 "enter". We also don't reverse intersegment "jmp" and "call"
2386 instructions with 2 immediate operands so that the immediate segment
2387 precedes the offset, as it does when in AT&T mode. */
2390 && (strcmp (mnemonic, "bound") != 0)
2391 && (strcmp (mnemonic, "invlpga") != 0)
2392 && !(operand_type_check (i.types[0], imm)
2393 && operand_type_check (i.types[1], imm)))
2396 /* The order of the immediates should be reversed
2397 for 2 immediates extrq and insertq instructions */
2398 if (i.imm_operands == 2
2399 && (strcmp (mnemonic, "extrq") == 0
2400 || strcmp (mnemonic, "insertq") == 0))
2401 swap_2_operands (0, 1);
2406 /* Don't optimize displacement for movabs since it only takes 64bit
2409 && (flag_code != CODE_64BIT
2410 || strcmp (mnemonic, "movabs") != 0))
2413 /* Next, we find a template that matches the given insn,
2414 making sure the overlap of the given operands types is consistent
2415 with the template operand types. */
2417 if (!match_template ())
2420 /* Zap movzx and movsx suffix. The suffix has been set from
2421 "word ptr" or "byte ptr" on the source operand in Intel syntax
2422 or extracted from mnemonic in AT&T syntax. But we'll use
2423 the destination register to choose the suffix for encoding. */
2424 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2426 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2427 there is no suffix, the default will be byte extension. */
2428 if (i.reg_operands != 2
2431 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2436 if (i.tm.opcode_modifier.fwait)
2437 if (!add_prefix (FWAIT_OPCODE))
2440 /* Check string instruction segment overrides. */
2441 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2443 if (!check_string ())
2447 if (!process_suffix ())
2450 /* Make still unresolved immediate matches conform to size of immediate
2451 given in i.suffix. */
2452 if (!finalize_imm ())
2455 if (i.types[0].bitfield.imm1)
2456 i.imm_operands = 0; /* kludge for shift insns. */
2458 for (j = 0; j < 3; j++)
2459 if (i.types[j].bitfield.inoutportreg
2460 || i.types[j].bitfield.shiftcount
2461 || i.types[j].bitfield.acc
2462 || i.types[j].bitfield.floatacc)
2465 if (i.tm.opcode_modifier.immext)
2469 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2471 /* Streaming SIMD extensions 3 Instructions have the fixed
2472 operands with an opcode suffix which is coded in the same
2473 place as an 8-bit immediate field would be. Here we check
2474 those operands and remove them afterwards. */
2477 for (x = 0; x < i.operands; x++)
2478 if (i.op[x].regs->reg_num != x)
2479 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2481 i.op[x].regs->reg_name,
2487 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2488 opcode suffix which is coded in the same place as an 8-bit
2489 immediate field would be. Here we fake an 8-bit immediate
2490 operand from the opcode suffix stored in tm.extension_opcode.
2491 SSE5 also uses this encoding, for some of its 3 argument
2494 assert (i.imm_operands == 0
2496 || (i.tm.cpu_flags.bitfield.cpusse5
2497 && i.operands <= 3)));
2499 exp = &im_expressions[i.imm_operands++];
2500 i.op[i.operands].imms = exp;
2501 UINTS_CLEAR (i.types[i.operands]);
2502 i.types[i.operands].bitfield.imm8 = 1;
2504 exp->X_op = O_constant;
2505 exp->X_add_number = i.tm.extension_opcode;
2506 i.tm.extension_opcode = None;
2509 /* For insns with operands there are more diddles to do to the opcode. */
2512 if (!process_operands ())
2515 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2517 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2518 as_warn (_("translating to `%sp'"), i.tm.name);
2521 /* Handle conversion of 'int $3' --> special int3 insn. */
2522 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2524 i.tm.base_opcode = INT3_OPCODE;
2528 if ((i.tm.opcode_modifier.jump
2529 || i.tm.opcode_modifier.jumpbyte
2530 || i.tm.opcode_modifier.jumpdword)
2531 && i.op[0].disps->X_op == O_constant)
2533 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2534 the absolute address given by the constant. Since ix86 jumps and
2535 calls are pc relative, we need to generate a reloc. */
2536 i.op[0].disps->X_add_symbol = &abs_symbol;
2537 i.op[0].disps->X_op = O_symbol;
2540 if (i.tm.opcode_modifier.rex64)
2543 /* For 8 bit registers we need an empty rex prefix. Also if the
2544 instruction already has a prefix, we need to convert old
2545 registers to new ones. */
2547 if ((i.types[0].bitfield.reg8
2548 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2549 || (i.types[1].bitfield.reg8
2550 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2551 || ((i.types[0].bitfield.reg8
2552 || i.types[1].bitfield.reg8)
2557 i.rex |= REX_OPCODE;
2558 for (x = 0; x < 2; x++)
2560 /* Look for 8 bit operand that uses old registers. */
2561 if (i.types[x].bitfield.reg8
2562 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2564 /* In case it is "hi" register, give up. */
2565 if (i.op[x].regs->reg_num > 3)
2566 as_bad (_("can't encode register '%s%s' in an "
2567 "instruction requiring REX prefix."),
2568 register_prefix, i.op[x].regs->reg_name);
2570 /* Otherwise it is equivalent to the extended register.
2571 Since the encoding doesn't change this is merely
2572 cosmetic cleanup for debug output. */
2574 i.op[x].regs = i.op[x].regs + 8;
2579 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2581 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2586 else if (i.rex != 0)
2587 add_prefix (REX_OPCODE | i.rex);
2589 /* We are ready to output the insn. */
2594 parse_insn (char *line, char *mnemonic)
2597 char *token_start = l;
2602 /* Non-zero if we found a prefix only acceptable with string insns. */
2603 const char *expecting_string_instruction = NULL;
2608 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2611 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2613 as_bad (_("no such instruction: `%s'"), token_start);
2618 if (!is_space_char (*l)
2619 && *l != END_OF_INSN
2621 || (*l != PREFIX_SEPARATOR
2624 as_bad (_("invalid character %s in mnemonic"),
2625 output_invalid (*l));
2628 if (token_start == l)
2630 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2631 as_bad (_("expecting prefix; got nothing"));
2633 as_bad (_("expecting mnemonic; got nothing"));
2637 /* Look up instruction (or prefix) via hash table. */
2638 current_templates = hash_find (op_hash, mnemonic);
2640 if (*l != END_OF_INSN
2641 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2642 && current_templates
2643 && current_templates->start->opcode_modifier.isprefix)
2645 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2647 as_bad ((flag_code != CODE_64BIT
2648 ? _("`%s' is only supported in 64-bit mode")
2649 : _("`%s' is not supported in 64-bit mode")),
2650 current_templates->start->name);
2653 /* If we are in 16-bit mode, do not allow addr16 or data16.
2654 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2655 if ((current_templates->start->opcode_modifier.size16
2656 || current_templates->start->opcode_modifier.size32)
2657 && flag_code != CODE_64BIT
2658 && (current_templates->start->opcode_modifier.size32
2659 ^ (flag_code == CODE_16BIT)))
2661 as_bad (_("redundant %s prefix"),
2662 current_templates->start->name);
2665 /* Add prefix, checking for repeated prefixes. */
2666 switch (add_prefix (current_templates->start->base_opcode))
2671 expecting_string_instruction = current_templates->start->name;
2674 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2681 if (!current_templates)
2683 /* See if we can get a match by trimming off a suffix. */
2686 case WORD_MNEM_SUFFIX:
2687 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2688 i.suffix = SHORT_MNEM_SUFFIX;
2690 case BYTE_MNEM_SUFFIX:
2691 case QWORD_MNEM_SUFFIX:
2692 i.suffix = mnem_p[-1];
2694 current_templates = hash_find (op_hash, mnemonic);
2696 case SHORT_MNEM_SUFFIX:
2697 case LONG_MNEM_SUFFIX:
2700 i.suffix = mnem_p[-1];
2702 current_templates = hash_find (op_hash, mnemonic);
2710 if (intel_float_operand (mnemonic) == 1)
2711 i.suffix = SHORT_MNEM_SUFFIX;
2713 i.suffix = LONG_MNEM_SUFFIX;
2715 current_templates = hash_find (op_hash, mnemonic);
2719 if (!current_templates)
2721 as_bad (_("no such instruction: `%s'"), token_start);
2726 if (current_templates->start->opcode_modifier.jump
2727 || current_templates->start->opcode_modifier.jumpbyte)
2729 /* Check for a branch hint. We allow ",pt" and ",pn" for
2730 predict taken and predict not taken respectively.
2731 I'm not sure that branch hints actually do anything on loop
2732 and jcxz insns (JumpByte) for current Pentium4 chips. They
2733 may work in the future and it doesn't hurt to accept them
2735 if (l[0] == ',' && l[1] == 'p')
2739 if (!add_prefix (DS_PREFIX_OPCODE))
2743 else if (l[2] == 'n')
2745 if (!add_prefix (CS_PREFIX_OPCODE))
2751 /* Any other comma loses. */
2754 as_bad (_("invalid character %s in mnemonic"),
2755 output_invalid (*l));
2759 /* Check if instruction is supported on specified architecture. */
2761 for (t = current_templates->start; t < current_templates->end; ++t)
2763 supported |= cpu_flags_match (t->cpu_flags);
2768 if (!(supported & 2))
2770 as_bad (flag_code == CODE_64BIT
2771 ? _("`%s' is not supported in 64-bit mode")
2772 : _("`%s' is only supported in 64-bit mode"),
2773 current_templates->start->name);
2776 if (!(supported & 1))
2778 as_bad (_("`%s' is not supported on `%s%s'"),
2779 current_templates->start->name, cpu_arch_name,
2780 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2785 if (!cpu_arch_flags.bitfield.cpui386
2786 && (flag_code != CODE_16BIT))
2788 as_warn (_("use .code16 to ensure correct addressing mode"));
2791 /* Check for rep/repne without a string instruction. */
2792 if (expecting_string_instruction)
2794 static templates override;
2796 for (t = current_templates->start; t < current_templates->end; ++t)
2797 if (t->opcode_modifier.isstring)
2799 if (t >= current_templates->end)
2801 as_bad (_("expecting string instruction after `%s'"),
2802 expecting_string_instruction);
2805 for (override.start = t; t < current_templates->end; ++t)
2806 if (!t->opcode_modifier.isstring)
2809 current_templates = &override;
2816 parse_operands (char *l, const char *mnemonic)
2820 /* 1 if operand is pending after ','. */
2821 unsigned int expecting_operand = 0;
2823 /* Non-zero if operand parens not balanced. */
2824 unsigned int paren_not_balanced;
2826 while (*l != END_OF_INSN)
2828 /* Skip optional white space before operand. */
2829 if (is_space_char (*l))
2831 if (!is_operand_char (*l) && *l != END_OF_INSN)
2833 as_bad (_("invalid character %s before operand %d"),
2834 output_invalid (*l),
2838 token_start = l; /* after white space */
2839 paren_not_balanced = 0;
2840 while (paren_not_balanced || *l != ',')
2842 if (*l == END_OF_INSN)
2844 if (paren_not_balanced)
2847 as_bad (_("unbalanced parenthesis in operand %d."),
2850 as_bad (_("unbalanced brackets in operand %d."),
2855 break; /* we are done */
2857 else if (!is_operand_char (*l) && !is_space_char (*l))
2859 as_bad (_("invalid character %s in operand %d"),
2860 output_invalid (*l),
2867 ++paren_not_balanced;
2869 --paren_not_balanced;
2874 ++paren_not_balanced;
2876 --paren_not_balanced;
2880 if (l != token_start)
2881 { /* Yes, we've read in another operand. */
2882 unsigned int operand_ok;
2883 this_operand = i.operands++;
2884 i.types[this_operand].bitfield.unspecified = 1;
2885 if (i.operands > MAX_OPERANDS)
2887 as_bad (_("spurious operands; (%d operands/instruction max)"),
2891 /* Now parse operand adding info to 'i' as we go along. */
2892 END_STRING_AND_SAVE (l);
2896 i386_intel_operand (token_start,
2897 intel_float_operand (mnemonic));
2899 operand_ok = i386_att_operand (token_start);
2901 RESTORE_END_STRING (l);
2907 if (expecting_operand)
2909 expecting_operand_after_comma:
2910 as_bad (_("expecting operand after ','; got nothing"));
2915 as_bad (_("expecting operand before ','; got nothing"));
2920 /* Now *l must be either ',' or END_OF_INSN. */
2923 if (*++l == END_OF_INSN)
2925 /* Just skip it, if it's \n complain. */
2926 goto expecting_operand_after_comma;
2928 expecting_operand = 1;
2935 swap_2_operands (int xchg1, int xchg2)
2937 union i386_op temp_op;
2938 i386_operand_type temp_type;
2939 enum bfd_reloc_code_real temp_reloc;
2941 temp_type = i.types[xchg2];
2942 i.types[xchg2] = i.types[xchg1];
2943 i.types[xchg1] = temp_type;
2944 temp_op = i.op[xchg2];
2945 i.op[xchg2] = i.op[xchg1];
2946 i.op[xchg1] = temp_op;
2947 temp_reloc = i.reloc[xchg2];
2948 i.reloc[xchg2] = i.reloc[xchg1];
2949 i.reloc[xchg1] = temp_reloc;
2953 swap_operands (void)
2958 swap_2_operands (1, i.operands - 2);
2961 swap_2_operands (0, i.operands - 1);
2967 if (i.mem_operands == 2)
2969 const seg_entry *temp_seg;
2970 temp_seg = i.seg[0];
2971 i.seg[0] = i.seg[1];
2972 i.seg[1] = temp_seg;
2976 /* Try to ensure constant immediates are represented in the smallest
2981 char guess_suffix = 0;
2985 guess_suffix = i.suffix;
2986 else if (i.reg_operands)
2988 /* Figure out a suffix from the last register operand specified.
2989 We can't do this properly yet, ie. excluding InOutPortReg,
2990 but the following works for instructions with immediates.
2991 In any case, we can't set i.suffix yet. */
2992 for (op = i.operands; --op >= 0;)
2993 if (i.types[op].bitfield.reg8)
2995 guess_suffix = BYTE_MNEM_SUFFIX;
2998 else if (i.types[op].bitfield.reg16)
3000 guess_suffix = WORD_MNEM_SUFFIX;
3003 else if (i.types[op].bitfield.reg32)
3005 guess_suffix = LONG_MNEM_SUFFIX;
3008 else if (i.types[op].bitfield.reg64)
3010 guess_suffix = QWORD_MNEM_SUFFIX;
3014 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3015 guess_suffix = WORD_MNEM_SUFFIX;
3017 for (op = i.operands; --op >= 0;)
3018 if (operand_type_check (i.types[op], imm))
3020 switch (i.op[op].imms->X_op)
3023 /* If a suffix is given, this operand may be shortened. */
3024 switch (guess_suffix)
3026 case LONG_MNEM_SUFFIX:
3027 i.types[op].bitfield.imm32 = 1;
3028 i.types[op].bitfield.imm64 = 1;
3030 case WORD_MNEM_SUFFIX:
3031 i.types[op].bitfield.imm16 = 1;
3032 i.types[op].bitfield.imm32 = 1;
3033 i.types[op].bitfield.imm32s = 1;
3034 i.types[op].bitfield.imm64 = 1;
3036 case BYTE_MNEM_SUFFIX:
3037 i.types[op].bitfield.imm8 = 1;
3038 i.types[op].bitfield.imm8s = 1;
3039 i.types[op].bitfield.imm16 = 1;
3040 i.types[op].bitfield.imm32 = 1;
3041 i.types[op].bitfield.imm32s = 1;
3042 i.types[op].bitfield.imm64 = 1;
3046 /* If this operand is at most 16 bits, convert it
3047 to a signed 16 bit number before trying to see
3048 whether it will fit in an even smaller size.
3049 This allows a 16-bit operand such as $0xffe0 to
3050 be recognised as within Imm8S range. */
3051 if ((i.types[op].bitfield.imm16)
3052 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3054 i.op[op].imms->X_add_number =
3055 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3057 if ((i.types[op].bitfield.imm32)
3058 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3061 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3062 ^ ((offsetT) 1 << 31))
3063 - ((offsetT) 1 << 31));
3066 = operand_type_or (i.types[op],
3067 smallest_imm_type (i.op[op].imms->X_add_number));
3069 /* We must avoid matching of Imm32 templates when 64bit
3070 only immediate is available. */
3071 if (guess_suffix == QWORD_MNEM_SUFFIX)
3072 i.types[op].bitfield.imm32 = 0;
3079 /* Symbols and expressions. */
3081 /* Convert symbolic operand to proper sizes for matching, but don't
3082 prevent matching a set of insns that only supports sizes other
3083 than those matching the insn suffix. */
3085 i386_operand_type mask, allowed;
3089 UINTS_CLEAR (allowed);
3091 for (t = current_templates->start;
3092 t < current_templates->end;
3094 allowed = operand_type_or (allowed,
3095 t->operand_types[op]);
3096 switch (guess_suffix)
3098 case QWORD_MNEM_SUFFIX:
3099 mask.bitfield.imm64 = 1;
3100 mask.bitfield.imm32s = 1;
3102 case LONG_MNEM_SUFFIX:
3103 mask.bitfield.imm32 = 1;
3105 case WORD_MNEM_SUFFIX:
3106 mask.bitfield.imm16 = 1;
3108 case BYTE_MNEM_SUFFIX:
3109 mask.bitfield.imm8 = 1;
3114 allowed = operand_type_and (mask, allowed);
3115 if (!UINTS_ALL_ZERO (allowed))
3116 i.types[op] = operand_type_and (i.types[op], mask);
3123 /* Try to use the smallest displacement type too. */
3125 optimize_disp (void)
3129 for (op = i.operands; --op >= 0;)
3130 if (operand_type_check (i.types[op], disp))
3132 if (i.op[op].disps->X_op == O_constant)
3134 offsetT disp = i.op[op].disps->X_add_number;
3136 if (i.types[op].bitfield.disp16
3137 && (disp & ~(offsetT) 0xffff) == 0)
3139 /* If this operand is at most 16 bits, convert
3140 to a signed 16 bit number and don't use 64bit
3142 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3143 i.types[op].bitfield.disp64 = 0;
3145 if (i.types[op].bitfield.disp32
3146 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3148 /* If this operand is at most 32 bits, convert
3149 to a signed 32 bit number and don't use 64bit
3151 disp &= (((offsetT) 2 << 31) - 1);
3152 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3153 i.types[op].bitfield.disp64 = 0;
3155 if (!disp && i.types[op].bitfield.baseindex)
3157 i.types[op].bitfield.disp8 = 0;
3158 i.types[op].bitfield.disp16 = 0;
3159 i.types[op].bitfield.disp32 = 0;
3160 i.types[op].bitfield.disp32s = 0;
3161 i.types[op].bitfield.disp64 = 0;
3165 else if (flag_code == CODE_64BIT)
3167 if (fits_in_signed_long (disp))
3169 i.types[op].bitfield.disp64 = 0;
3170 i.types[op].bitfield.disp32s = 1;
3172 if (fits_in_unsigned_long (disp))
3173 i.types[op].bitfield.disp32 = 1;
3175 if ((i.types[op].bitfield.disp32
3176 || i.types[op].bitfield.disp32s
3177 || i.types[op].bitfield.disp16)
3178 && fits_in_signed_byte (disp))
3179 i.types[op].bitfield.disp8 = 1;
3181 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3182 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3184 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3185 i.op[op].disps, 0, i.reloc[op]);
3186 i.types[op].bitfield.disp8 = 0;
3187 i.types[op].bitfield.disp16 = 0;
3188 i.types[op].bitfield.disp32 = 0;
3189 i.types[op].bitfield.disp32s = 0;
3190 i.types[op].bitfield.disp64 = 0;
3193 /* We only support 64bit displacement on constants. */
3194 i.types[op].bitfield.disp64 = 0;
3199 match_template (void)
3201 /* Points to template once we've found it. */
3203 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3204 unsigned int found_reverse_match;
3205 i386_opcode_modifier suffix_check;
3206 i386_operand_type operand_types [MAX_OPERANDS];
3207 int addr_prefix_disp;
3209 unsigned int found_cpu_match;
3210 unsigned int check_register;
3212 #if MAX_OPERANDS != 4
3213 # error "MAX_OPERANDS must be 4."
3216 found_reverse_match = 0;
3217 addr_prefix_disp = -1;
3219 memset (&suffix_check, 0, sizeof (suffix_check));
3220 if (i.suffix == BYTE_MNEM_SUFFIX)
3221 suffix_check.no_bsuf = 1;
3222 else if (i.suffix == WORD_MNEM_SUFFIX)
3223 suffix_check.no_wsuf = 1;
3224 else if (i.suffix == SHORT_MNEM_SUFFIX)
3225 suffix_check.no_ssuf = 1;
3226 else if (i.suffix == LONG_MNEM_SUFFIX)
3227 suffix_check.no_lsuf = 1;
3228 else if (i.suffix == QWORD_MNEM_SUFFIX)
3229 suffix_check.no_qsuf = 1;
3230 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3231 suffix_check.no_ldsuf = 1;
3233 for (t = current_templates->start; t < current_templates->end; t++)
3235 addr_prefix_disp = -1;
3237 /* Must have right number of operands. */
3238 if (i.operands != t->operands)
3241 /* Check processor support. */
3242 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3243 if (!found_cpu_match)
3246 /* Check old gcc support. */
3247 if (!old_gcc && t->opcode_modifier.oldgcc)
3250 /* Check AT&T mnemonic. */
3251 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3254 /* Check AT&T syntax Intel syntax. */
3255 if ((intel_syntax && t->opcode_modifier.attsyntax)
3256 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3259 /* Check the suffix, except for some instructions in intel mode. */
3260 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3261 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3262 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3263 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3264 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3265 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3266 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3269 if (!operand_size_match (t))
3272 for (j = 0; j < MAX_OPERANDS; j++)
3273 operand_types[j] = t->operand_types[j];
3275 /* In general, don't allow 64-bit operands in 32-bit mode. */
3276 if (i.suffix == QWORD_MNEM_SUFFIX
3277 && flag_code != CODE_64BIT
3279 ? (!t->opcode_modifier.ignoresize
3280 && !intel_float_operand (t->name))
3281 : intel_float_operand (t->name) != 2)
3282 && ((!operand_types[0].bitfield.regmmx
3283 && !operand_types[0].bitfield.regxmm)
3284 || (!operand_types[t->operands > 1].bitfield.regmmx
3285 && !!operand_types[t->operands > 1].bitfield.regxmm))
3286 && (t->base_opcode != 0x0fc7
3287 || t->extension_opcode != 1 /* cmpxchg8b */))
3290 /* Do not verify operands when there are none. */
3294 /* We've found a match; break out of loop. */
3298 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3299 into Disp32/Disp16/Disp32 operand. */
3300 if (i.prefix[ADDR_PREFIX] != 0)
3302 /* There should be only one Disp operand. */
3306 for (j = 0; j < MAX_OPERANDS; j++)
3308 if (operand_types[j].bitfield.disp16)
3310 addr_prefix_disp = j;
3311 operand_types[j].bitfield.disp32 = 1;
3312 operand_types[j].bitfield.disp16 = 0;
3318 for (j = 0; j < MAX_OPERANDS; j++)
3320 if (operand_types[j].bitfield.disp32)
3322 addr_prefix_disp = j;
3323 operand_types[j].bitfield.disp32 = 0;
3324 operand_types[j].bitfield.disp16 = 1;
3330 for (j = 0; j < MAX_OPERANDS; j++)
3332 if (operand_types[j].bitfield.disp64)
3334 addr_prefix_disp = j;
3335 operand_types[j].bitfield.disp64 = 0;
3336 operand_types[j].bitfield.disp32 = 1;
3344 /* We check register size only if size of operands can be
3345 encoded the canonical way. */
3346 check_register = t->opcode_modifier.w;
3347 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3348 switch (t->operands)
3351 if (!operand_type_match (overlap0, i.types[0]))
3355 /* xchg %eax, %eax is a special case. It is an aliase for nop
3356 only in 32bit mode and we can use opcode 0x90. In 64bit
3357 mode, we can't use 0x90 for xchg %eax, %eax since it should
3358 zero-extend %eax to %rax. */
3359 if (flag_code == CODE_64BIT
3360 && t->base_opcode == 0x90
3361 && UINTS_EQUAL (i.types [0], acc32)
3362 && UINTS_EQUAL (i.types [1], acc32))
3366 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3367 if (!operand_type_match (overlap0, i.types[0])
3368 || !operand_type_match (overlap1, i.types[1])
3370 && !operand_type_register_match (overlap0, i.types[0],
3372 overlap1, i.types[1],
3375 /* Check if other direction is valid ... */
3376 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3379 /* Try reversing direction of operands. */
3380 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3381 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3382 if (!operand_type_match (overlap0, i.types[0])
3383 || !operand_type_match (overlap1, i.types[1])
3385 && !operand_type_register_match (overlap0,
3392 /* Does not match either direction. */
3395 /* found_reverse_match holds which of D or FloatDR
3397 if (t->opcode_modifier.d)
3398 found_reverse_match = Opcode_D;
3399 else if (t->opcode_modifier.floatd)
3400 found_reverse_match = Opcode_FloatD;
3402 found_reverse_match = 0;
3403 if (t->opcode_modifier.floatr)
3404 found_reverse_match |= Opcode_FloatR;
3408 /* Found a forward 2 operand match here. */
3409 switch (t->operands)
3412 overlap3 = operand_type_and (i.types[3],
3415 overlap2 = operand_type_and (i.types[2],
3420 switch (t->operands)
3423 if (!operand_type_match (overlap3, i.types[3])
3425 && !operand_type_register_match (overlap2,
3433 /* Here we make use of the fact that there are no
3434 reverse match 3 operand instructions, and all 3
3435 operand instructions only need to be checked for
3436 register consistency between operands 2 and 3. */
3437 if (!operand_type_match (overlap2, i.types[2])
3439 && !operand_type_register_match (overlap1,
3449 /* Found either forward/reverse 2, 3 or 4 operand match here:
3450 slip through to break. */
3452 if (!found_cpu_match)
3454 found_reverse_match = 0;
3457 /* We've found a match; break out of loop. */
3461 if (t == current_templates->end)
3463 /* We found no match. */
3464 as_bad (_("suffix or operands invalid for `%s'"),
3465 current_templates->start->name);
3469 if (!quiet_warnings)
3472 && (i.types[0].bitfield.jumpabsolute
3473 != operand_types[0].bitfield.jumpabsolute))
3475 as_warn (_("indirect %s without `*'"), t->name);
3478 if (t->opcode_modifier.isprefix
3479 && t->opcode_modifier.ignoresize)
3481 /* Warn them that a data or address size prefix doesn't
3482 affect assembly of the next line of code. */
3483 as_warn (_("stand-alone `%s' prefix"), t->name);
3487 /* Copy the template we found. */
3490 if (addr_prefix_disp != -1)
3491 i.tm.operand_types[addr_prefix_disp]
3492 = operand_types[addr_prefix_disp];
3494 if (found_reverse_match)
3496 /* If we found a reverse match we must alter the opcode
3497 direction bit. found_reverse_match holds bits to change
3498 (different for int & float insns). */
3500 i.tm.base_opcode ^= found_reverse_match;
3502 i.tm.operand_types[0] = operand_types[1];
3503 i.tm.operand_types[1] = operand_types[0];
3512 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3513 if (i.tm.operand_types[mem_op].bitfield.esseg)
3515 if (i.seg[0] != NULL && i.seg[0] != &es)
3517 as_bad (_("`%s' operand %d must use `%%es' segment"),
3522 /* There's only ever one segment override allowed per instruction.
3523 This instruction possibly has a legal segment override on the
3524 second operand, so copy the segment to where non-string
3525 instructions store it, allowing common code. */
3526 i.seg[0] = i.seg[1];
3528 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3530 if (i.seg[1] != NULL && i.seg[1] != &es)
3532 as_bad (_("`%s' operand %d must use `%%es' segment"),
3542 process_suffix (void)
3544 /* If matched instruction specifies an explicit instruction mnemonic
3546 if (i.tm.opcode_modifier.size16)
3547 i.suffix = WORD_MNEM_SUFFIX;
3548 else if (i.tm.opcode_modifier.size32)
3549 i.suffix = LONG_MNEM_SUFFIX;
3550 else if (i.tm.opcode_modifier.size64)
3551 i.suffix = QWORD_MNEM_SUFFIX;
3552 else if (i.reg_operands)
3554 /* If there's no instruction mnemonic suffix we try to invent one
3555 based on register operands. */
3558 /* We take i.suffix from the last register operand specified,
3559 Destination register type is more significant than source
3560 register type. crc32 in SSE4.2 prefers source register
3562 if (i.tm.base_opcode == 0xf20f38f1)
3564 if (i.types[0].bitfield.reg16)
3565 i.suffix = WORD_MNEM_SUFFIX;
3566 else if (i.types[0].bitfield.reg32)
3567 i.suffix = LONG_MNEM_SUFFIX;
3568 else if (i.types[0].bitfield.reg64)
3569 i.suffix = QWORD_MNEM_SUFFIX;
3571 else if (i.tm.base_opcode == 0xf20f38f0)
3573 if (i.types[0].bitfield.reg8)
3574 i.suffix = BYTE_MNEM_SUFFIX;
3581 if (i.tm.base_opcode == 0xf20f38f1
3582 || i.tm.base_opcode == 0xf20f38f0)
3584 /* We have to know the operand size for crc32. */
3585 as_bad (_("ambiguous memory operand size for `%s`"),
3590 for (op = i.operands; --op >= 0;)
3591 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3593 if (i.types[op].bitfield.reg8)
3595 i.suffix = BYTE_MNEM_SUFFIX;
3598 else if (i.types[op].bitfield.reg16)
3600 i.suffix = WORD_MNEM_SUFFIX;
3603 else if (i.types[op].bitfield.reg32)
3605 i.suffix = LONG_MNEM_SUFFIX;
3608 else if (i.types[op].bitfield.reg64)
3610 i.suffix = QWORD_MNEM_SUFFIX;
3616 else if (i.suffix == BYTE_MNEM_SUFFIX)
3618 if (!check_byte_reg ())
3621 else if (i.suffix == LONG_MNEM_SUFFIX)
3623 if (!check_long_reg ())
3626 else if (i.suffix == QWORD_MNEM_SUFFIX)
3629 && i.tm.opcode_modifier.ignoresize
3630 && i.tm.opcode_modifier.no_qsuf)
3632 else if (!check_qword_reg ())
3635 else if (i.suffix == WORD_MNEM_SUFFIX)
3637 if (!check_word_reg ())
3640 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3642 /* Skip if the instruction has x suffix. match_template
3643 should check if it is a valid suffix. */
3645 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3646 /* Do nothing if the instruction is going to ignore the prefix. */
3651 else if (i.tm.opcode_modifier.defaultsize
3653 /* exclude fldenv/frstor/fsave/fstenv */
3654 && i.tm.opcode_modifier.no_ssuf)
3656 i.suffix = stackop_size;
3658 else if (intel_syntax
3660 && (i.tm.operand_types[0].bitfield.jumpabsolute
3661 || i.tm.opcode_modifier.jumpbyte
3662 || i.tm.opcode_modifier.jumpintersegment
3663 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3664 && i.tm.extension_opcode <= 3)))
3669 if (!i.tm.opcode_modifier.no_qsuf)
3671 i.suffix = QWORD_MNEM_SUFFIX;
3675 if (!i.tm.opcode_modifier.no_lsuf)
3676 i.suffix = LONG_MNEM_SUFFIX;
3679 if (!i.tm.opcode_modifier.no_wsuf)
3680 i.suffix = WORD_MNEM_SUFFIX;
3689 if (i.tm.opcode_modifier.w)
3691 as_bad (_("no instruction mnemonic suffix given and "
3692 "no register operands; can't size instruction"));
3698 unsigned int suffixes;
3700 suffixes = !i.tm.opcode_modifier.no_bsuf;
3701 if (!i.tm.opcode_modifier.no_wsuf)
3703 if (!i.tm.opcode_modifier.no_lsuf)
3705 if (!i.tm.opcode_modifier.no_ldsuf)
3707 if (!i.tm.opcode_modifier.no_ssuf)
3709 if (!i.tm.opcode_modifier.no_qsuf)
3712 /* There are more than suffix matches. */
3713 if (i.tm.opcode_modifier.w
3714 || ((suffixes & (suffixes - 1))
3715 && !i.tm.opcode_modifier.defaultsize
3716 && !i.tm.opcode_modifier.ignoresize))
3718 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3724 /* Change the opcode based on the operand size given by i.suffix;
3725 We don't need to change things for byte insns. */
3728 && i.suffix != BYTE_MNEM_SUFFIX
3729 && i.suffix != XMMWORD_MNEM_SUFFIX)
3731 /* It's not a byte, select word/dword operation. */
3732 if (i.tm.opcode_modifier.w)
3734 if (i.tm.opcode_modifier.shortform)
3735 i.tm.base_opcode |= 8;
3737 i.tm.base_opcode |= 1;
3740 /* Now select between word & dword operations via the operand
3741 size prefix, except for instructions that will ignore this
3743 if (i.tm.opcode_modifier.addrprefixop0)
3745 /* The address size override prefix changes the size of the
3747 if ((flag_code == CODE_32BIT
3748 && i.op->regs[0].reg_type.bitfield.reg16)
3749 || (flag_code != CODE_32BIT
3750 && i.op->regs[0].reg_type.bitfield.reg32))
3751 if (!add_prefix (ADDR_PREFIX_OPCODE))
3754 else if (i.suffix != QWORD_MNEM_SUFFIX
3755 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3756 && !i.tm.opcode_modifier.ignoresize
3757 && !i.tm.opcode_modifier.floatmf
3758 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3759 || (flag_code == CODE_64BIT
3760 && i.tm.opcode_modifier.jumpbyte)))
3762 unsigned int prefix = DATA_PREFIX_OPCODE;
3764 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3765 prefix = ADDR_PREFIX_OPCODE;
3767 if (!add_prefix (prefix))
3771 /* Set mode64 for an operand. */
3772 if (i.suffix == QWORD_MNEM_SUFFIX
3773 && flag_code == CODE_64BIT
3774 && !i.tm.opcode_modifier.norex64)
3776 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3777 need rex64. cmpxchg8b is also a special case. */
3778 if (! (i.operands == 2
3779 && i.tm.base_opcode == 0x90
3780 && i.tm.extension_opcode == None
3781 && UINTS_EQUAL (i.types [0], acc64)
3782 && UINTS_EQUAL (i.types [1], acc64))
3783 && ! (i.operands == 1
3784 && i.tm.base_opcode == 0xfc7
3785 && i.tm.extension_opcode == 1
3786 && !operand_type_check (i.types [0], reg)
3787 && operand_type_check (i.types [0], anymem)))
3791 /* Size floating point instruction. */
3792 if (i.suffix == LONG_MNEM_SUFFIX)
3793 if (i.tm.opcode_modifier.floatmf)
3794 i.tm.base_opcode ^= 4;
3801 check_byte_reg (void)
3805 for (op = i.operands; --op >= 0;)
3807 /* If this is an eight bit register, it's OK. If it's the 16 or
3808 32 bit version of an eight bit register, we will just use the
3809 low portion, and that's OK too. */
3810 if (i.types[op].bitfield.reg8)
3813 /* Don't generate this warning if not needed. */
3814 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3817 /* crc32 doesn't generate this warning. */
3818 if (i.tm.base_opcode == 0xf20f38f0)
3821 if ((i.types[op].bitfield.reg16
3822 || i.types[op].bitfield.reg32
3823 || i.types[op].bitfield.reg64)
3824 && i.op[op].regs->reg_num < 4)
3826 /* Prohibit these changes in the 64bit mode, since the
3827 lowering is more complicated. */
3828 if (flag_code == CODE_64BIT
3829 && !i.tm.operand_types[op].bitfield.inoutportreg)
3831 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3832 register_prefix, i.op[op].regs->reg_name,
3836 #if REGISTER_WARNINGS
3838 && !i.tm.operand_types[op].bitfield.inoutportreg)
3839 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3841 (i.op[op].regs + (i.types[op].bitfield.reg16
3842 ? REGNAM_AL - REGNAM_AX
3843 : REGNAM_AL - REGNAM_EAX))->reg_name,
3845 i.op[op].regs->reg_name,
3850 /* Any other register is bad. */
3851 if (i.types[op].bitfield.reg16
3852 || i.types[op].bitfield.reg32
3853 || i.types[op].bitfield.reg64
3854 || i.types[op].bitfield.regmmx
3855 || i.types[op].bitfield.regxmm
3856 || i.types[op].bitfield.sreg2
3857 || i.types[op].bitfield.sreg3
3858 || i.types[op].bitfield.control
3859 || i.types[op].bitfield.debug
3860 || i.types[op].bitfield.test
3861 || i.types[op].bitfield.floatreg
3862 || i.types[op].bitfield.floatacc)
3864 as_bad (_("`%s%s' not allowed with `%s%c'"),
3866 i.op[op].regs->reg_name,
3876 check_long_reg (void)
3880 for (op = i.operands; --op >= 0;)
3881 /* Reject eight bit registers, except where the template requires
3882 them. (eg. movzb) */
3883 if (i.types[op].bitfield.reg8
3884 && (i.tm.operand_types[op].bitfield.reg16
3885 || i.tm.operand_types[op].bitfield.reg32
3886 || i.tm.operand_types[op].bitfield.acc))
3888 as_bad (_("`%s%s' not allowed with `%s%c'"),
3890 i.op[op].regs->reg_name,
3895 /* Warn if the e prefix on a general reg is missing. */
3896 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3897 && i.types[op].bitfield.reg16
3898 && (i.tm.operand_types[op].bitfield.reg32
3899 || i.tm.operand_types[op].bitfield.acc))
3901 /* Prohibit these changes in the 64bit mode, since the
3902 lowering is more complicated. */
3903 if (flag_code == CODE_64BIT)
3905 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3906 register_prefix, i.op[op].regs->reg_name,
3910 #if REGISTER_WARNINGS
3912 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3914 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3916 i.op[op].regs->reg_name,
3920 /* Warn if the r prefix on a general reg is missing. */
3921 else if (i.types[op].bitfield.reg64
3922 && (i.tm.operand_types[op].bitfield.reg32
3923 || i.tm.operand_types[op].bitfield.acc))
3926 && i.tm.opcode_modifier.toqword
3927 && !i.types[0].bitfield.regxmm)
3929 /* Convert to QWORD. We want REX byte. */
3930 i.suffix = QWORD_MNEM_SUFFIX;
3934 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3935 register_prefix, i.op[op].regs->reg_name,
3944 check_qword_reg (void)
3948 for (op = i.operands; --op >= 0; )
3949 /* Reject eight bit registers, except where the template requires
3950 them. (eg. movzb) */
3951 if (i.types[op].bitfield.reg8
3952 && (i.tm.operand_types[op].bitfield.reg16
3953 || i.tm.operand_types[op].bitfield.reg32
3954 || i.tm.operand_types[op].bitfield.acc))
3956 as_bad (_("`%s%s' not allowed with `%s%c'"),
3958 i.op[op].regs->reg_name,
3963 /* Warn if the e prefix on a general reg is missing. */
3964 else if ((i.types[op].bitfield.reg16
3965 || i.types[op].bitfield.reg32)
3966 && (i.tm.operand_types[op].bitfield.reg32
3967 || i.tm.operand_types[op].bitfield.acc))
3969 /* Prohibit these changes in the 64bit mode, since the
3970 lowering is more complicated. */
3972 && i.tm.opcode_modifier.todword
3973 && !i.types[0].bitfield.regxmm)
3975 /* Convert to DWORD. We don't want REX byte. */
3976 i.suffix = LONG_MNEM_SUFFIX;
3980 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3981 register_prefix, i.op[op].regs->reg_name,
3990 check_word_reg (void)
3993 for (op = i.operands; --op >= 0;)
3994 /* Reject eight bit registers, except where the template requires
3995 them. (eg. movzb) */
3996 if (i.types[op].bitfield.reg8
3997 && (i.tm.operand_types[op].bitfield.reg16
3998 || i.tm.operand_types[op].bitfield.reg32
3999 || i.tm.operand_types[op].bitfield.acc))
4001 as_bad (_("`%s%s' not allowed with `%s%c'"),
4003 i.op[op].regs->reg_name,
4008 /* Warn if the e prefix on a general reg is present. */
4009 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4010 && i.types[op].bitfield.reg32
4011 && (i.tm.operand_types[op].bitfield.reg16
4012 || i.tm.operand_types[op].bitfield.acc))
4014 /* Prohibit these changes in the 64bit mode, since the
4015 lowering is more complicated. */
4016 if (flag_code == CODE_64BIT)
4018 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4019 register_prefix, i.op[op].regs->reg_name,
4024 #if REGISTER_WARNINGS
4025 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4027 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4029 i.op[op].regs->reg_name,
4037 update_imm (unsigned int j)
4039 i386_operand_type overlap;
4041 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4042 if ((overlap.bitfield.imm8
4043 || overlap.bitfield.imm8s
4044 || overlap.bitfield.imm16
4045 || overlap.bitfield.imm32
4046 || overlap.bitfield.imm32s
4047 || overlap.bitfield.imm64)
4048 && !UINTS_EQUAL (overlap, imm8)
4049 && !UINTS_EQUAL (overlap, imm8s)
4050 && !UINTS_EQUAL (overlap, imm16)
4051 && !UINTS_EQUAL (overlap, imm32)
4052 && !UINTS_EQUAL (overlap, imm32s)
4053 && !UINTS_EQUAL (overlap, imm64))
4057 i386_operand_type temp;
4060 if (i.suffix == BYTE_MNEM_SUFFIX)
4062 temp.bitfield.imm8 = overlap.bitfield.imm8;
4063 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4065 else if (i.suffix == WORD_MNEM_SUFFIX)
4066 temp.bitfield.imm16 = overlap.bitfield.imm16;
4067 else if (i.suffix == QWORD_MNEM_SUFFIX)
4069 temp.bitfield.imm64 = overlap.bitfield.imm64;
4070 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4073 temp.bitfield.imm32 = overlap.bitfield.imm32;
4076 else if (UINTS_EQUAL (overlap, imm16_32_32s)
4077 || UINTS_EQUAL (overlap, imm16_32)
4078 || UINTS_EQUAL (overlap, imm16_32s))
4080 UINTS_CLEAR (overlap);
4081 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4082 overlap.bitfield.imm16 = 1;
4084 overlap.bitfield.imm32s = 1;
4086 if (!UINTS_EQUAL (overlap, imm8)
4087 && !UINTS_EQUAL (overlap, imm8s)
4088 && !UINTS_EQUAL (overlap, imm16)
4089 && !UINTS_EQUAL (overlap, imm32)
4090 && !UINTS_EQUAL (overlap, imm32s)
4091 && !UINTS_EQUAL (overlap, imm64))
4093 as_bad (_("no instruction mnemonic suffix given; "
4094 "can't determine immediate size"));
4098 i.types[j] = overlap;
4108 for (j = 0; j < 2; j++)
4109 if (update_imm (j) == 0)
4112 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4113 assert (operand_type_check (i.types[2], imm) == 0);
4121 i.drex.modrm_reg = 0;
4122 i.drex.modrm_regmem = 0;
4124 /* SSE5 4 operand instructions must have the destination the same as
4125 one of the inputs. Figure out the destination register and cache
4126 it away in the drex field, and remember which fields to use for
4128 if (i.tm.opcode_modifier.drex
4129 && i.tm.opcode_modifier.drexv
4132 i.tm.extension_opcode = None;
4134 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4135 if (i.types[0].bitfield.regxmm != 0
4136 && i.types[1].bitfield.regxmm != 0
4137 && i.types[2].bitfield.regxmm != 0
4138 && i.types[3].bitfield.regxmm != 0
4139 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4140 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4142 /* Clear the arguments that are stored in drex. */
4143 UINTS_CLEAR (i.types[0]);
4144 UINTS_CLEAR (i.types[3]);
4145 i.reg_operands -= 2;
4147 /* There are two different ways to encode a 4 operand
4148 instruction with all registers that uses OC1 set to
4149 0 or 1. Favor setting OC1 to 0 since this mimics the
4150 actions of other SSE5 assemblers. Use modrm encoding 2
4151 for register/register. Include the high order bit that
4152 is normally stored in the REX byte in the register
4154 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4155 i.drex.modrm_reg = 2;
4156 i.drex.modrm_regmem = 1;
4157 i.drex.reg = (i.op[3].regs->reg_num
4158 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4161 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4162 else if (i.types[0].bitfield.regxmm != 0
4163 && i.types[1].bitfield.regxmm != 0
4164 && (i.types[2].bitfield.regxmm
4165 || operand_type_check (i.types[2], anymem))
4166 && i.types[3].bitfield.regxmm != 0
4167 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4168 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4170 /* clear the arguments that are stored in drex */
4171 UINTS_CLEAR (i.types[0]);
4172 UINTS_CLEAR (i.types[3]);
4173 i.reg_operands -= 2;
4175 /* Specify the modrm encoding for memory addressing. Include
4176 the high order bit that is normally stored in the REX byte
4177 in the register field. */
4178 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4179 i.drex.modrm_reg = 1;
4180 i.drex.modrm_regmem = 2;
4181 i.drex.reg = (i.op[3].regs->reg_num
4182 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4185 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4186 else if (i.types[0].bitfield.regxmm != 0
4187 && operand_type_check (i.types[1], anymem) != 0
4188 && i.types[2].bitfield.regxmm != 0
4189 && i.types[3].bitfield.regxmm != 0
4190 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4191 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4193 /* Clear the arguments that are stored in drex. */
4194 UINTS_CLEAR (i.types[0]);
4195 UINTS_CLEAR (i.types[3]);
4196 i.reg_operands -= 2;
4198 /* Specify the modrm encoding for memory addressing. Include
4199 the high order bit that is normally stored in the REX byte
4200 in the register field. */
4201 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4202 i.drex.modrm_reg = 2;
4203 i.drex.modrm_regmem = 1;
4204 i.drex.reg = (i.op[3].regs->reg_num
4205 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4208 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4209 else if (i.types[0].bitfield.regxmm != 0
4210 && i.types[1].bitfield.regxmm != 0
4211 && i.types[2].bitfield.regxmm != 0
4212 && i.types[3].bitfield.regxmm != 0
4213 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4214 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4216 /* clear the arguments that are stored in drex */
4217 UINTS_CLEAR (i.types[2]);
4218 UINTS_CLEAR (i.types[3]);
4219 i.reg_operands -= 2;
4221 /* There are two different ways to encode a 4 operand
4222 instruction with all registers that uses OC1 set to
4223 0 or 1. Favor setting OC1 to 0 since this mimics the
4224 actions of other SSE5 assemblers. Use modrm encoding
4225 2 for register/register. Include the high order bit that
4226 is normally stored in the REX byte in the register
4228 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4229 i.drex.modrm_reg = 1;
4230 i.drex.modrm_regmem = 0;
4232 /* Remember the register, including the upper bits */
4233 i.drex.reg = (i.op[3].regs->reg_num
4234 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4237 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4238 else if (i.types[0].bitfield.regxmm != 0
4239 && (i.types[1].bitfield.regxmm
4240 || operand_type_check (i.types[1], anymem))
4241 && i.types[2].bitfield.regxmm != 0
4242 && i.types[3].bitfield.regxmm != 0
4243 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4244 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4246 /* Clear the arguments that are stored in drex. */
4247 UINTS_CLEAR (i.types[2]);
4248 UINTS_CLEAR (i.types[3]);
4249 i.reg_operands -= 2;
4251 /* Specify the modrm encoding and remember the register
4252 including the bits normally stored in the REX byte. */
4253 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4254 i.drex.modrm_reg = 0;
4255 i.drex.modrm_regmem = 1;
4256 i.drex.reg = (i.op[3].regs->reg_num
4257 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4260 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4261 else if (operand_type_check (i.types[0], anymem) != 0
4262 && i.types[1].bitfield.regxmm != 0
4263 && i.types[2].bitfield.regxmm != 0
4264 && i.types[3].bitfield.regxmm != 0
4265 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4266 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4268 /* clear the arguments that are stored in drex */
4269 UINTS_CLEAR (i.types[2]);
4270 UINTS_CLEAR (i.types[3]);
4271 i.reg_operands -= 2;
4273 /* Specify the modrm encoding and remember the register
4274 including the bits normally stored in the REX byte. */
4275 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4276 i.drex.modrm_reg = 1;
4277 i.drex.modrm_regmem = 0;
4278 i.drex.reg = (i.op[3].regs->reg_num
4279 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4283 as_bad (_("Incorrect operands for the '%s' instruction"),
4287 /* SSE5 instructions with the DREX byte where the only memory operand
4288 is in the 2nd argument, and the first and last xmm register must
4289 match, and is encoded in the DREX byte. */
4290 else if (i.tm.opcode_modifier.drex
4291 && !i.tm.opcode_modifier.drexv
4294 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4295 if (i.types[0].bitfield.regxmm != 0
4296 && (i.types[1].bitfield.regxmm
4297 || operand_type_check(i.types[1], anymem))
4298 && i.types[2].bitfield.regxmm != 0
4299 && i.types[3].bitfield.regxmm != 0
4300 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4301 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4303 /* clear the arguments that are stored in drex */
4304 UINTS_CLEAR (i.types[0]);
4305 UINTS_CLEAR (i.types[3]);
4306 i.reg_operands -= 2;
4308 /* Specify the modrm encoding and remember the register
4309 including the high bit normally stored in the REX
4311 i.drex.modrm_reg = 2;
4312 i.drex.modrm_regmem = 1;
4313 i.drex.reg = (i.op[3].regs->reg_num
4314 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4318 as_bad (_("Incorrect operands for the '%s' instruction"),
4322 /* SSE5 3 operand instructions that the result is a register, being
4323 either operand can be a memory operand, using OC0 to note which
4324 one is the memory. */
4325 else if (i.tm.opcode_modifier.drex
4326 && i.tm.opcode_modifier.drexv
4329 i.tm.extension_opcode = None;
4331 /* Case 1: 3 operand insn, src1 = register. */
4332 if (i.types[0].bitfield.regxmm != 0
4333 && i.types[1].bitfield.regxmm != 0
4334 && i.types[2].bitfield.regxmm != 0)
4336 /* Clear the arguments that are stored in drex. */
4337 UINTS_CLEAR (i.types[2]);
4340 /* Specify the modrm encoding and remember the register
4341 including the high bit normally stored in the REX byte. */
4342 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4343 i.drex.modrm_reg = 1;
4344 i.drex.modrm_regmem = 0;
4345 i.drex.reg = (i.op[2].regs->reg_num
4346 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4349 /* Case 2: 3 operand insn, src1 = memory. */
4350 else if (operand_type_check (i.types[0], anymem) != 0
4351 && i.types[1].bitfield.regxmm != 0
4352 && i.types[2].bitfield.regxmm != 0)
4354 /* Clear the arguments that are stored in drex. */
4355 UINTS_CLEAR (i.types[2]);
4358 /* Specify the modrm encoding and remember the register
4359 including the high bit normally stored in the REX
4361 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4362 i.drex.modrm_reg = 1;
4363 i.drex.modrm_regmem = 0;
4364 i.drex.reg = (i.op[2].regs->reg_num
4365 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4368 /* Case 3: 3 operand insn, src2 = memory. */
4369 else if (i.types[0].bitfield.regxmm != 0
4370 && operand_type_check (i.types[1], anymem) != 0
4371 && i.types[2].bitfield.regxmm != 0)
4373 /* Clear the arguments that are stored in drex. */
4374 UINTS_CLEAR (i.types[2]);
4377 /* Specify the modrm encoding and remember the register
4378 including the high bit normally stored in the REX byte. */
4379 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4380 i.drex.modrm_reg = 0;
4381 i.drex.modrm_regmem = 1;
4382 i.drex.reg = (i.op[2].regs->reg_num
4383 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4387 as_bad (_("Incorrect operands for the '%s' instruction"),
4391 /* SSE5 4 operand instructions that are the comparison instructions
4392 where the first operand is the immediate value of the comparison
4394 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4396 /* Case 1: 4 operand insn, src1 = reg/memory. */
4397 if (operand_type_check (i.types[0], imm) != 0
4398 && (i.types[1].bitfield.regxmm
4399 || operand_type_check (i.types[1], anymem))
4400 && i.types[2].bitfield.regxmm != 0
4401 && i.types[3].bitfield.regxmm != 0)
4403 /* clear the arguments that are stored in drex */
4404 UINTS_CLEAR (i.types[3]);
4407 /* Specify the modrm encoding and remember the register
4408 including the high bit normally stored in the REX byte. */
4409 i.drex.modrm_reg = 2;
4410 i.drex.modrm_regmem = 1;
4411 i.drex.reg = (i.op[3].regs->reg_num
4412 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4415 /* Case 2: 3 operand insn with ImmExt that places the
4416 opcode_extension as an immediate argument. This is used for
4417 all of the varients of comparison that supplies the appropriate
4418 value as part of the instruction. */
4419 else if ((i.types[0].bitfield.regxmm
4420 || operand_type_check (i.types[0], anymem))
4421 && i.types[1].bitfield.regxmm != 0
4422 && i.types[2].bitfield.regxmm != 0
4423 && operand_type_check (i.types[3], imm) != 0)
4425 /* clear the arguments that are stored in drex */
4426 UINTS_CLEAR (i.types[2]);
4429 /* Specify the modrm encoding and remember the register
4430 including the high bit normally stored in the REX byte. */
4431 i.drex.modrm_reg = 1;
4432 i.drex.modrm_regmem = 0;
4433 i.drex.reg = (i.op[2].regs->reg_num
4434 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4438 as_bad (_("Incorrect operands for the '%s' instruction"),
4442 else if (i.tm.opcode_modifier.drex
4443 || i.tm.opcode_modifier.drexv
4444 || i.tm.opcode_modifier.drexc)
4445 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4449 process_operands (void)
4451 /* Default segment register this instruction will use for memory
4452 accesses. 0 means unknown. This is only for optimizing out
4453 unnecessary segment overrides. */
4454 const seg_entry *default_seg = 0;
4456 /* Handle all of the DREX munging that SSE5 needs. */
4457 if (i.tm.opcode_modifier.drex
4458 || i.tm.opcode_modifier.drexv
4459 || i.tm.opcode_modifier.drexc)
4462 if (i.tm.opcode_modifier.firstxmm0)
4466 /* The first operand is implicit and must be xmm0. */
4467 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4468 if (i.op[0].regs->reg_num != 0)
4471 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4472 i.tm.name, register_prefix);
4474 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4475 i.tm.name, register_prefix);
4479 for (j = 1; j < i.operands; j++)
4481 i.op[j - 1] = i.op[j];
4482 i.types[j - 1] = i.types[j];
4484 /* We need to adjust fields in i.tm since they are used by
4485 build_modrm_byte. */
4486 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4493 else if (i.tm.opcode_modifier.regkludge)
4495 /* The imul $imm, %reg instruction is converted into
4496 imul $imm, %reg, %reg, and the clr %reg instruction
4497 is converted into xor %reg, %reg. */
4499 unsigned int first_reg_op;
4501 if (operand_type_check (i.types[0], reg))
4505 /* Pretend we saw the extra register operand. */
4506 assert (i.reg_operands == 1
4507 && i.op[first_reg_op + 1].regs == 0);
4508 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4509 i.types[first_reg_op + 1] = i.types[first_reg_op];
4514 if (i.tm.opcode_modifier.shortform)
4516 if (i.types[0].bitfield.sreg2
4517 || i.types[0].bitfield.sreg3)
4519 if (i.tm.base_opcode == POP_SEG_SHORT
4520 && i.op[0].regs->reg_num == 1)
4522 as_bad (_("you can't `pop %%cs'"));
4525 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4526 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4531 /* The register or float register operand is in operand
4535 if (i.types[0].bitfield.floatreg
4536 || operand_type_check (i.types[0], reg))
4540 /* Register goes in low 3 bits of opcode. */
4541 i.tm.base_opcode |= i.op[op].regs->reg_num;
4542 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4544 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4546 /* Warn about some common errors, but press on regardless.
4547 The first case can be generated by gcc (<= 2.8.1). */
4548 if (i.operands == 2)
4550 /* Reversed arguments on faddp, fsubp, etc. */
4551 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4552 register_prefix, i.op[1].regs->reg_name,
4553 register_prefix, i.op[0].regs->reg_name);
4557 /* Extraneous `l' suffix on fp insn. */
4558 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4559 register_prefix, i.op[0].regs->reg_name);
4564 else if (i.tm.opcode_modifier.modrm)
4566 /* The opcode is completed (modulo i.tm.extension_opcode which
4567 must be put into the modrm byte). Now, we make the modrm and
4568 index base bytes based on all the info we've collected. */
4570 default_seg = build_modrm_byte ();
4572 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4576 else if (i.tm.opcode_modifier.isstring)
4578 /* For the string instructions that allow a segment override
4579 on one of their operands, the default segment is ds. */
4583 if (i.tm.base_opcode == 0x8d /* lea */
4586 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4588 /* If a segment was explicitly specified, and the specified segment
4589 is not the default, use an opcode prefix to select it. If we
4590 never figured out what the default segment is, then default_seg
4591 will be zero at this point, and the specified segment prefix will
4593 if ((i.seg[0]) && (i.seg[0] != default_seg))
4595 if (!add_prefix (i.seg[0]->seg_prefix))
4601 static const seg_entry *
4602 build_modrm_byte (void)
4604 const seg_entry *default_seg = 0;
4606 /* SSE5 4 operand instructions are encoded in such a way that one of
4607 the inputs must match the destination register. Process_drex hides
4608 the 3rd argument in the drex field, so that by the time we get
4609 here, it looks to GAS as if this is a 2 operand instruction. */
4610 if ((i.tm.opcode_modifier.drex
4611 || i.tm.opcode_modifier.drexv
4612 || i.tm.opcode_modifier.drexc)
4613 && i.reg_operands == 2)
4615 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4616 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4618 i.rm.reg = reg->reg_num;
4619 i.rm.regmem = regmem->reg_num;
4621 if ((reg->reg_flags & RegRex) != 0)
4623 if ((regmem->reg_flags & RegRex) != 0)
4627 /* i.reg_operands MUST be the number of real register operands;
4628 implicit registers do not count. */
4629 else if (i.reg_operands == 2)
4631 unsigned int source, dest;
4639 /* When there are 3 operands, one of them may be immediate,
4640 which may be the first or the last operand. Otherwise,
4641 the first operand must be shift count register (cl). */
4642 assert (i.imm_operands == 1
4643 || (i.imm_operands == 0
4644 && i.types[0].bitfield.shiftcount));
4645 if (operand_type_check (i.types[0], imm)
4646 || i.types[0].bitfield.shiftcount)
4652 /* When there are 4 operands, the first two must be 8bit
4653 immediate operands. The source operand will be the 3rd
4655 assert (i.imm_operands == 2
4656 && i.types[0].bitfield.imm8
4657 && i.types[1].bitfield.imm8);
4667 /* One of the register operands will be encoded in the i.tm.reg
4668 field, the other in the combined i.tm.mode and i.tm.regmem
4669 fields. If no form of this instruction supports a memory
4670 destination operand, then we assume the source operand may
4671 sometimes be a memory operand and so we need to store the
4672 destination in the i.rm.reg field. */
4673 if (!i.tm.operand_types[dest].bitfield.regmem
4674 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4676 i.rm.reg = i.op[dest].regs->reg_num;
4677 i.rm.regmem = i.op[source].regs->reg_num;
4678 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4680 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4685 i.rm.reg = i.op[source].regs->reg_num;
4686 i.rm.regmem = i.op[dest].regs->reg_num;
4687 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4689 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4692 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4694 if (!i.types[0].bitfield.control
4695 && !i.types[1].bitfield.control)
4697 i.rex &= ~(REX_R | REX_B);
4698 add_prefix (LOCK_PREFIX_OPCODE);
4702 { /* If it's not 2 reg operands... */
4705 unsigned int fake_zero_displacement = 0;
4708 /* This has been precalculated for SSE5 instructions
4709 that have a DREX field earlier in process_drex. */
4710 if (i.tm.opcode_modifier.drex
4711 || i.tm.opcode_modifier.drexv
4712 || i.tm.opcode_modifier.drexc)
4713 op = i.drex.modrm_regmem;
4716 for (op = 0; op < i.operands; op++)
4717 if (operand_type_check (i.types[op], anymem))
4719 assert (op < i.operands);
4724 if (i.base_reg == 0)
4727 if (!i.disp_operands)
4728 fake_zero_displacement = 1;
4729 if (i.index_reg == 0)
4731 /* Operand is just <disp> */
4732 if (flag_code == CODE_64BIT)
4734 /* 64bit mode overwrites the 32bit absolute
4735 addressing by RIP relative addressing and
4736 absolute addressing is encoded by one of the
4737 redundant SIB forms. */
4738 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4739 i.sib.base = NO_BASE_REGISTER;
4740 i.sib.index = NO_INDEX_REGISTER;
4741 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4742 ? disp32s : disp32);
4744 else if ((flag_code == CODE_16BIT)
4745 ^ (i.prefix[ADDR_PREFIX] != 0))
4747 i.rm.regmem = NO_BASE_REGISTER_16;
4748 i.types[op] = disp16;
4752 i.rm.regmem = NO_BASE_REGISTER;
4753 i.types[op] = disp32;
4756 else /* !i.base_reg && i.index_reg */
4758 if (i.index_reg->reg_num == RegEiz
4759 || i.index_reg->reg_num == RegRiz)
4760 i.sib.index = NO_INDEX_REGISTER;
4762 i.sib.index = i.index_reg->reg_num;
4763 i.sib.base = NO_BASE_REGISTER;
4764 i.sib.scale = i.log2_scale_factor;
4765 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4766 i.types[op].bitfield.disp8 = 0;
4767 i.types[op].bitfield.disp16 = 0;
4768 i.types[op].bitfield.disp64 = 0;
4769 if (flag_code != CODE_64BIT)
4771 /* Must be 32 bit */
4772 i.types[op].bitfield.disp32 = 1;
4773 i.types[op].bitfield.disp32s = 0;
4777 i.types[op].bitfield.disp32 = 0;
4778 i.types[op].bitfield.disp32s = 1;
4780 if ((i.index_reg->reg_flags & RegRex) != 0)
4784 /* RIP addressing for 64bit mode. */
4785 else if (i.base_reg->reg_num == RegRip ||
4786 i.base_reg->reg_num == RegEip)
4788 i.rm.regmem = NO_BASE_REGISTER;
4789 i.types[op].bitfield.disp8 = 0;
4790 i.types[op].bitfield.disp16 = 0;
4791 i.types[op].bitfield.disp32 = 0;
4792 i.types[op].bitfield.disp32s = 1;
4793 i.types[op].bitfield.disp64 = 0;
4794 i.flags[op] |= Operand_PCrel;
4795 if (! i.disp_operands)
4796 fake_zero_displacement = 1;
4798 else if (i.base_reg->reg_type.bitfield.reg16)
4800 switch (i.base_reg->reg_num)
4803 if (i.index_reg == 0)
4805 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4806 i.rm.regmem = i.index_reg->reg_num - 6;
4810 if (i.index_reg == 0)
4813 if (operand_type_check (i.types[op], disp) == 0)
4815 /* fake (%bp) into 0(%bp) */
4816 i.types[op].bitfield.disp8 = 1;
4817 fake_zero_displacement = 1;
4820 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4821 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4823 default: /* (%si) -> 4 or (%di) -> 5 */
4824 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4826 i.rm.mode = mode_from_disp_size (i.types[op]);
4828 else /* i.base_reg and 32/64 bit mode */
4830 if (flag_code == CODE_64BIT
4831 && operand_type_check (i.types[op], disp))
4833 i386_operand_type temp;
4835 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4837 if (i.prefix[ADDR_PREFIX] == 0)
4838 i.types[op].bitfield.disp32s = 1;
4840 i.types[op].bitfield.disp32 = 1;
4843 i.rm.regmem = i.base_reg->reg_num;
4844 if ((i.base_reg->reg_flags & RegRex) != 0)
4846 i.sib.base = i.base_reg->reg_num;
4847 /* x86-64 ignores REX prefix bit here to avoid decoder
4849 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4852 if (i.disp_operands == 0)
4854 fake_zero_displacement = 1;
4855 i.types[op].bitfield.disp8 = 1;
4858 else if (i.base_reg->reg_num == ESP_REG_NUM)
4862 i.sib.scale = i.log2_scale_factor;
4863 if (i.index_reg == 0)
4865 /* <disp>(%esp) becomes two byte modrm with no index
4866 register. We've already stored the code for esp
4867 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4868 Any base register besides %esp will not use the
4869 extra modrm byte. */
4870 i.sib.index = NO_INDEX_REGISTER;
4874 if (i.index_reg->reg_num == RegEiz
4875 || i.index_reg->reg_num == RegRiz)
4876 i.sib.index = NO_INDEX_REGISTER;
4878 i.sib.index = i.index_reg->reg_num;
4879 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4880 if ((i.index_reg->reg_flags & RegRex) != 0)
4885 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4886 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4889 i.rm.mode = mode_from_disp_size (i.types[op]);
4892 if (fake_zero_displacement)
4894 /* Fakes a zero displacement assuming that i.types[op]
4895 holds the correct displacement size. */
4898 assert (i.op[op].disps == 0);
4899 exp = &disp_expressions[i.disp_operands++];
4900 i.op[op].disps = exp;
4901 exp->X_op = O_constant;
4902 exp->X_add_number = 0;
4903 exp->X_add_symbol = (symbolS *) 0;
4904 exp->X_op_symbol = (symbolS *) 0;
4908 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4909 (if any) based on i.tm.extension_opcode. Again, we must be
4910 careful to make sure that segment/control/debug/test/MMX
4911 registers are coded into the i.rm.reg field. */
4916 /* This has been precalculated for SSE5 instructions
4917 that have a DREX field earlier in process_drex. */
4918 if (i.tm.opcode_modifier.drex
4919 || i.tm.opcode_modifier.drexv
4920 || i.tm.opcode_modifier.drexc)
4922 op = i.drex.modrm_reg;
4923 i.rm.reg = i.op[op].regs->reg_num;
4924 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4929 for (op = 0; op < i.operands; op++)
4930 if (i.types[op].bitfield.reg8
4931 || i.types[op].bitfield.reg16
4932 || i.types[op].bitfield.reg32
4933 || i.types[op].bitfield.reg64
4934 || i.types[op].bitfield.regmmx
4935 || i.types[op].bitfield.regxmm
4936 || i.types[op].bitfield.sreg2
4937 || i.types[op].bitfield.sreg3
4938 || i.types[op].bitfield.control
4939 || i.types[op].bitfield.debug
4940 || i.types[op].bitfield.test)
4943 assert (op < i.operands);
4945 /* If there is an extension opcode to put here, the
4946 register number must be put into the regmem field. */
4947 if (i.tm.extension_opcode != None)
4949 i.rm.regmem = i.op[op].regs->reg_num;
4950 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4955 i.rm.reg = i.op[op].regs->reg_num;
4956 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4962 must set it to 3 to indicate this is a register operand
4963 in the regmem field. */
4964 if (!i.mem_operands)
4968 /* Fill in i.rm.reg field with extension opcode (if any). */
4969 if (i.tm.extension_opcode != None
4970 && !(i.tm.opcode_modifier.drex
4971 || i.tm.opcode_modifier.drexv
4972 || i.tm.opcode_modifier.drexc))
4973 i.rm.reg = i.tm.extension_opcode;
4979 output_branch (void)
4984 relax_substateT subtype;
4989 if (flag_code == CODE_16BIT)
4993 if (i.prefix[DATA_PREFIX] != 0)
4999 /* Pentium4 branch hints. */
5000 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5001 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5006 if (i.prefix[REX_PREFIX] != 0)
5012 if (i.prefixes != 0 && !intel_syntax)
5013 as_warn (_("skipping prefixes on this instruction"));
5015 /* It's always a symbol; End frag & setup for relax.
5016 Make sure there is enough room in this frag for the largest
5017 instruction we may generate in md_convert_frag. This is 2
5018 bytes for the opcode and room for the prefix and largest
5020 frag_grow (prefix + 2 + 4);
5021 /* Prefix and 1 opcode byte go in fr_fix. */
5022 p = frag_more (prefix + 1);
5023 if (i.prefix[DATA_PREFIX] != 0)
5024 *p++ = DATA_PREFIX_OPCODE;
5025 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5026 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5027 *p++ = i.prefix[SEG_PREFIX];
5028 if (i.prefix[REX_PREFIX] != 0)
5029 *p++ = i.prefix[REX_PREFIX];
5030 *p = i.tm.base_opcode;
5032 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5033 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5034 else if (cpu_arch_flags.bitfield.cpui386)
5035 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5037 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5040 sym = i.op[0].disps->X_add_symbol;
5041 off = i.op[0].disps->X_add_number;
5043 if (i.op[0].disps->X_op != O_constant
5044 && i.op[0].disps->X_op != O_symbol)
5046 /* Handle complex expressions. */
5047 sym = make_expr_symbol (i.op[0].disps);
5051 /* 1 possible extra opcode + 4 byte displacement go in var part.
5052 Pass reloc in fr_var. */
5053 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5063 if (i.tm.opcode_modifier.jumpbyte)
5065 /* This is a loop or jecxz type instruction. */
5067 if (i.prefix[ADDR_PREFIX] != 0)
5069 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5072 /* Pentium4 branch hints. */
5073 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5074 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5076 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5085 if (flag_code == CODE_16BIT)
5088 if (i.prefix[DATA_PREFIX] != 0)
5090 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5100 if (i.prefix[REX_PREFIX] != 0)
5102 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5106 if (i.prefixes != 0 && !intel_syntax)
5107 as_warn (_("skipping prefixes on this instruction"));
5109 p = frag_more (1 + size);
5110 *p++ = i.tm.base_opcode;
5112 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5113 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5115 /* All jumps handled here are signed, but don't use a signed limit
5116 check for 32 and 16 bit jumps as we want to allow wrap around at
5117 4G and 64k respectively. */
5119 fixP->fx_signed = 1;
5123 output_interseg_jump (void)
5131 if (flag_code == CODE_16BIT)
5135 if (i.prefix[DATA_PREFIX] != 0)
5141 if (i.prefix[REX_PREFIX] != 0)
5151 if (i.prefixes != 0 && !intel_syntax)
5152 as_warn (_("skipping prefixes on this instruction"));
5154 /* 1 opcode; 2 segment; offset */
5155 p = frag_more (prefix + 1 + 2 + size);
5157 if (i.prefix[DATA_PREFIX] != 0)
5158 *p++ = DATA_PREFIX_OPCODE;
5160 if (i.prefix[REX_PREFIX] != 0)
5161 *p++ = i.prefix[REX_PREFIX];
5163 *p++ = i.tm.base_opcode;
5164 if (i.op[1].imms->X_op == O_constant)
5166 offsetT n = i.op[1].imms->X_add_number;
5169 && !fits_in_unsigned_word (n)
5170 && !fits_in_signed_word (n))
5172 as_bad (_("16-bit jump out of range"));
5175 md_number_to_chars (p, n, size);
5178 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5179 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5180 if (i.op[0].imms->X_op != O_constant)
5181 as_bad (_("can't handle non absolute segment in `%s'"),
5183 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5189 fragS *insn_start_frag;
5190 offsetT insn_start_off;
5192 /* Tie dwarf2 debug info to the address at the start of the insn.
5193 We can't do this after the insn has been output as the current
5194 frag may have been closed off. eg. by frag_var. */
5195 dwarf2_emit_insn (0);
5197 insn_start_frag = frag_now;
5198 insn_start_off = frag_now_fix ();
5201 if (i.tm.opcode_modifier.jump)
5203 else if (i.tm.opcode_modifier.jumpbyte
5204 || i.tm.opcode_modifier.jumpdword)
5206 else if (i.tm.opcode_modifier.jumpintersegment)
5207 output_interseg_jump ();
5210 /* Output normal instructions here. */
5214 unsigned int prefix;
5216 switch (i.tm.opcode_length)
5219 if (i.tm.base_opcode & 0xff000000)
5221 prefix = (i.tm.base_opcode >> 24) & 0xff;
5226 if ((i.tm.base_opcode & 0xff0000) != 0)
5228 prefix = (i.tm.base_opcode >> 16) & 0xff;
5229 if (i.tm.cpu_flags.bitfield.cpupadlock)
5232 if (prefix != REPE_PREFIX_OPCODE
5233 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5234 add_prefix (prefix);
5237 add_prefix (prefix);
5246 /* The prefix bytes. */
5247 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5249 FRAG_APPEND_1_CHAR (*q);
5251 /* Now the opcode; be careful about word order here! */
5252 if (i.tm.opcode_length == 1)
5254 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5258 switch (i.tm.opcode_length)
5262 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5272 /* Put out high byte first: can't use md_number_to_chars! */
5273 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5274 *p = i.tm.base_opcode & 0xff;
5276 /* On SSE5, encode the OC1 bit in the DREX field if this
5277 encoding has multiple formats. */
5278 if (i.tm.opcode_modifier.drex
5279 && i.tm.opcode_modifier.drexv
5280 && DREX_OC1 (i.tm.extension_opcode))
5281 *p |= DREX_OC1_MASK;
5284 /* Now the modrm byte and sib byte (if present). */
5285 if (i.tm.opcode_modifier.modrm)
5287 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5290 /* If i.rm.regmem == ESP (4)
5291 && i.rm.mode != (Register mode)
5293 ==> need second modrm byte. */
5294 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5296 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5297 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5299 | i.sib.scale << 6));
5302 /* Write the DREX byte if needed. */
5303 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5306 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5308 /* Encode the OC0 bit if this encoding has multiple
5310 if ((i.tm.opcode_modifier.drex
5311 || i.tm.opcode_modifier.drexv)
5312 && DREX_OC0 (i.tm.extension_opcode))
5313 *p |= DREX_OC0_MASK;
5316 if (i.disp_operands)
5317 output_disp (insn_start_frag, insn_start_off);
5320 output_imm (insn_start_frag, insn_start_off);
5326 pi ("" /*line*/, &i);
5328 #endif /* DEBUG386 */
5331 /* Return the size of the displacement operand N. */
5334 disp_size (unsigned int n)
5337 if (i.types[n].bitfield.disp64)
5339 else if (i.types[n].bitfield.disp8)
5341 else if (i.types[n].bitfield.disp16)
5346 /* Return the size of the immediate operand N. */
5349 imm_size (unsigned int n)
5352 if (i.types[n].bitfield.imm64)
5354 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5356 else if (i.types[n].bitfield.imm16)
5362 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5367 for (n = 0; n < i.operands; n++)
5369 if (operand_type_check (i.types[n], disp))
5371 if (i.op[n].disps->X_op == O_constant)
5373 int size = disp_size (n);
5376 val = offset_in_range (i.op[n].disps->X_add_number,
5378 p = frag_more (size);
5379 md_number_to_chars (p, val, size);
5383 enum bfd_reloc_code_real reloc_type;
5384 int size = disp_size (n);
5385 int sign = i.types[n].bitfield.disp32s;
5386 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5388 /* We can't have 8 bit displacement here. */
5389 assert (!i.types[n].bitfield.disp8);
5391 /* The PC relative address is computed relative
5392 to the instruction boundary, so in case immediate
5393 fields follows, we need to adjust the value. */
5394 if (pcrel && i.imm_operands)
5399 for (n1 = 0; n1 < i.operands; n1++)
5400 if (operand_type_check (i.types[n1], imm))
5402 /* Only one immediate is allowed for PC
5403 relative address. */
5406 i.op[n].disps->X_add_number -= sz;
5408 /* We should find the immediate. */
5412 p = frag_more (size);
5413 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5415 && GOT_symbol == i.op[n].disps->X_add_symbol
5416 && (((reloc_type == BFD_RELOC_32
5417 || reloc_type == BFD_RELOC_X86_64_32S
5418 || (reloc_type == BFD_RELOC_64
5420 && (i.op[n].disps->X_op == O_symbol
5421 || (i.op[n].disps->X_op == O_add
5422 && ((symbol_get_value_expression
5423 (i.op[n].disps->X_op_symbol)->X_op)
5425 || reloc_type == BFD_RELOC_32_PCREL))
5429 if (insn_start_frag == frag_now)
5430 add = (p - frag_now->fr_literal) - insn_start_off;
5435 add = insn_start_frag->fr_fix - insn_start_off;
5436 for (fr = insn_start_frag->fr_next;
5437 fr && fr != frag_now; fr = fr->fr_next)
5439 add += p - frag_now->fr_literal;
5444 reloc_type = BFD_RELOC_386_GOTPC;
5445 i.op[n].imms->X_add_number += add;
5447 else if (reloc_type == BFD_RELOC_64)
5448 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5450 /* Don't do the adjustment for x86-64, as there
5451 the pcrel addressing is relative to the _next_
5452 insn, and that is taken care of in other code. */
5453 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5455 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5456 i.op[n].disps, pcrel, reloc_type);
5463 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5468 for (n = 0; n < i.operands; n++)
5470 if (operand_type_check (i.types[n], imm))
5472 if (i.op[n].imms->X_op == O_constant)
5474 int size = imm_size (n);
5477 val = offset_in_range (i.op[n].imms->X_add_number,
5479 p = frag_more (size);
5480 md_number_to_chars (p, val, size);
5484 /* Not absolute_section.
5485 Need a 32-bit fixup (don't support 8bit
5486 non-absolute imms). Try to support other
5488 enum bfd_reloc_code_real reloc_type;
5489 int size = imm_size (n);
5492 if (i.types[n].bitfield.imm32s
5493 && (i.suffix == QWORD_MNEM_SUFFIX
5494 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5499 p = frag_more (size);
5500 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5502 /* This is tough to explain. We end up with this one if we
5503 * have operands that look like
5504 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5505 * obtain the absolute address of the GOT, and it is strongly
5506 * preferable from a performance point of view to avoid using
5507 * a runtime relocation for this. The actual sequence of
5508 * instructions often look something like:
5513 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5515 * The call and pop essentially return the absolute address
5516 * of the label .L66 and store it in %ebx. The linker itself
5517 * will ultimately change the first operand of the addl so
5518 * that %ebx points to the GOT, but to keep things simple, the
5519 * .o file must have this operand set so that it generates not
5520 * the absolute address of .L66, but the absolute address of
5521 * itself. This allows the linker itself simply treat a GOTPC
5522 * relocation as asking for a pcrel offset to the GOT to be
5523 * added in, and the addend of the relocation is stored in the
5524 * operand field for the instruction itself.
5526 * Our job here is to fix the operand so that it would add
5527 * the correct offset so that %ebx would point to itself. The
5528 * thing that is tricky is that .-.L66 will point to the
5529 * beginning of the instruction, so we need to further modify
5530 * the operand so that it will point to itself. There are
5531 * other cases where you have something like:
5533 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5535 * and here no correction would be required. Internally in
5536 * the assembler we treat operands of this form as not being
5537 * pcrel since the '.' is explicitly mentioned, and I wonder
5538 * whether it would simplify matters to do it this way. Who
5539 * knows. In earlier versions of the PIC patches, the
5540 * pcrel_adjust field was used to store the correction, but
5541 * since the expression is not pcrel, I felt it would be
5542 * confusing to do it this way. */
5544 if ((reloc_type == BFD_RELOC_32
5545 || reloc_type == BFD_RELOC_X86_64_32S
5546 || reloc_type == BFD_RELOC_64)
5548 && GOT_symbol == i.op[n].imms->X_add_symbol
5549 && (i.op[n].imms->X_op == O_symbol
5550 || (i.op[n].imms->X_op == O_add
5551 && ((symbol_get_value_expression
5552 (i.op[n].imms->X_op_symbol)->X_op)
5557 if (insn_start_frag == frag_now)
5558 add = (p - frag_now->fr_literal) - insn_start_off;
5563 add = insn_start_frag->fr_fix - insn_start_off;
5564 for (fr = insn_start_frag->fr_next;
5565 fr && fr != frag_now; fr = fr->fr_next)
5567 add += p - frag_now->fr_literal;
5571 reloc_type = BFD_RELOC_386_GOTPC;
5573 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5575 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5576 i.op[n].imms->X_add_number += add;
5578 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5579 i.op[n].imms, 0, reloc_type);
5585 /* x86_cons_fix_new is called via the expression parsing code when a
5586 reloc is needed. We use this hook to get the correct .got reloc. */
5587 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5588 static int cons_sign = -1;
5591 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5594 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5596 got_reloc = NO_RELOC;
5599 if (exp->X_op == O_secrel)
5601 exp->X_op = O_symbol;
5602 r = BFD_RELOC_32_SECREL;
5606 fix_new_exp (frag, off, len, exp, 0, r);
5609 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5610 # define lex_got(reloc, adjust, types) NULL
5612 /* Parse operands of the form
5613 <symbol>@GOTOFF+<nnn>
5614 and similar .plt or .got references.
5616 If we find one, set up the correct relocation in RELOC and copy the
5617 input string, minus the `@GOTOFF' into a malloc'd buffer for
5618 parsing by the calling routine. Return this buffer, and if ADJUST
5619 is non-null set it to the length of the string we removed from the
5620 input line. Otherwise return NULL. */
5622 lex_got (enum bfd_reloc_code_real *reloc,
5624 i386_operand_type *types)
5626 /* Some of the relocations depend on the size of what field is to
5627 be relocated. But in our callers i386_immediate and i386_displacement
5628 we don't yet know the operand size (this will be set by insn
5629 matching). Hence we record the word32 relocation here,
5630 and adjust the reloc according to the real size in reloc(). */
5631 static const struct {
5633 const enum bfd_reloc_code_real rel[2];
5634 const i386_operand_type types64;
5637 BFD_RELOC_X86_64_PLTOFF64 },
5638 OPERAND_TYPE_IMM64 },
5639 { "PLT", { BFD_RELOC_386_PLT32,
5640 BFD_RELOC_X86_64_PLT32 },
5641 OPERAND_TYPE_IMM32_32S_DISP32 },
5643 BFD_RELOC_X86_64_GOTPLT64 },
5644 OPERAND_TYPE_IMM64_DISP64 },
5645 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5646 BFD_RELOC_X86_64_GOTOFF64 },
5647 OPERAND_TYPE_IMM64_DISP64 },
5649 BFD_RELOC_X86_64_GOTPCREL },
5650 OPERAND_TYPE_IMM32_32S_DISP32 },
5651 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5652 BFD_RELOC_X86_64_TLSGD },
5653 OPERAND_TYPE_IMM32_32S_DISP32 },
5654 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5656 OPERAND_TYPE_NONE },
5658 BFD_RELOC_X86_64_TLSLD },
5659 OPERAND_TYPE_IMM32_32S_DISP32 },
5660 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5661 BFD_RELOC_X86_64_GOTTPOFF },
5662 OPERAND_TYPE_IMM32_32S_DISP32 },
5663 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5664 BFD_RELOC_X86_64_TPOFF32 },
5665 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5666 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5668 OPERAND_TYPE_NONE },
5669 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5670 BFD_RELOC_X86_64_DTPOFF32 },
5672 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5673 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5675 OPERAND_TYPE_NONE },
5676 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5678 OPERAND_TYPE_NONE },
5679 { "GOT", { BFD_RELOC_386_GOT32,
5680 BFD_RELOC_X86_64_GOT32 },
5681 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5682 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5683 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5684 OPERAND_TYPE_IMM32_32S_DISP32 },
5685 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5686 BFD_RELOC_X86_64_TLSDESC_CALL },
5687 OPERAND_TYPE_IMM32_32S_DISP32 },
5695 for (cp = input_line_pointer; *cp != '@'; cp++)
5696 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5699 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5703 len = strlen (gotrel[j].str);
5704 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5706 if (gotrel[j].rel[object_64bit] != 0)
5709 char *tmpbuf, *past_reloc;
5711 *reloc = gotrel[j].rel[object_64bit];
5717 if (flag_code != CODE_64BIT)
5719 types->bitfield.imm32 = 1;
5720 types->bitfield.disp32 = 1;
5723 *types = gotrel[j].types64;
5726 if (GOT_symbol == NULL)
5727 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5729 /* The length of the first part of our input line. */
5730 first = cp - input_line_pointer;
5732 /* The second part goes from after the reloc token until
5733 (and including) an end_of_line char or comma. */
5734 past_reloc = cp + 1 + len;
5736 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5738 second = cp + 1 - past_reloc;
5740 /* Allocate and copy string. The trailing NUL shouldn't
5741 be necessary, but be safe. */
5742 tmpbuf = xmalloc (first + second + 2);
5743 memcpy (tmpbuf, input_line_pointer, first);
5744 if (second != 0 && *past_reloc != ' ')
5745 /* Replace the relocation token with ' ', so that
5746 errors like foo@GOTOFF1 will be detected. */
5747 tmpbuf[first++] = ' ';
5748 memcpy (tmpbuf + first, past_reloc, second);
5749 tmpbuf[first + second] = '\0';
5753 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5754 gotrel[j].str, 1 << (5 + object_64bit));
5759 /* Might be a symbol version string. Don't as_bad here. */
5764 x86_cons (expressionS *exp, int size)
5766 if (size == 4 || (object_64bit && size == 8))
5768 /* Handle @GOTOFF and the like in an expression. */
5770 char *gotfree_input_line;
5773 save = input_line_pointer;
5774 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5775 if (gotfree_input_line)
5776 input_line_pointer = gotfree_input_line;
5780 if (gotfree_input_line)
5782 /* expression () has merrily parsed up to the end of line,
5783 or a comma - in the wrong buffer. Transfer how far
5784 input_line_pointer has moved to the right buffer. */
5785 input_line_pointer = (save
5786 + (input_line_pointer - gotfree_input_line)
5788 free (gotfree_input_line);
5789 if (exp->X_op == O_constant
5790 || exp->X_op == O_absent
5791 || exp->X_op == O_illegal
5792 || exp->X_op == O_register
5793 || exp->X_op == O_big)
5795 char c = *input_line_pointer;
5796 *input_line_pointer = 0;
5797 as_bad (_("missing or invalid expression `%s'"), save);
5798 *input_line_pointer = c;
5807 static void signed_cons (int size)
5809 if (flag_code == CODE_64BIT)
5817 pe_directive_secrel (dummy)
5818 int dummy ATTRIBUTE_UNUSED;
5825 if (exp.X_op == O_symbol)
5826 exp.X_op = O_secrel;
5828 emit_expr (&exp, 4);
5830 while (*input_line_pointer++ == ',');
5832 input_line_pointer--;
5833 demand_empty_rest_of_line ();
5838 i386_immediate (char *imm_start)
5840 char *save_input_line_pointer;
5841 char *gotfree_input_line;
5844 i386_operand_type types;
5846 UINTS_SET (types, ~0);
5848 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5850 as_bad (_("at most %d immediate operands are allowed"),
5851 MAX_IMMEDIATE_OPERANDS);
5855 exp = &im_expressions[i.imm_operands++];
5856 i.op[this_operand].imms = exp;
5858 if (is_space_char (*imm_start))
5861 save_input_line_pointer = input_line_pointer;
5862 input_line_pointer = imm_start;
5864 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5865 if (gotfree_input_line)
5866 input_line_pointer = gotfree_input_line;
5868 exp_seg = expression (exp);
5871 if (*input_line_pointer)
5872 as_bad (_("junk `%s' after expression"), input_line_pointer);
5874 input_line_pointer = save_input_line_pointer;
5875 if (gotfree_input_line)
5876 free (gotfree_input_line);
5878 if (exp->X_op == O_absent
5879 || exp->X_op == O_illegal
5880 || exp->X_op == O_big
5881 || (gotfree_input_line
5882 && (exp->X_op == O_constant
5883 || exp->X_op == O_register)))
5885 as_bad (_("missing or invalid immediate expression `%s'"),
5889 else if (exp->X_op == O_constant)
5891 /* Size it properly later. */
5892 i.types[this_operand].bitfield.imm64 = 1;
5893 /* If BFD64, sign extend val. */
5894 if (!use_rela_relocations
5895 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5897 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5899 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5900 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5901 && exp_seg != absolute_section
5902 && exp_seg != text_section
5903 && exp_seg != data_section
5904 && exp_seg != bss_section
5905 && exp_seg != undefined_section
5906 && !bfd_is_com_section (exp_seg))
5908 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5912 else if (!intel_syntax && exp->X_op == O_register)
5914 as_bad (_("illegal immediate register operand %s"), imm_start);
5919 /* This is an address. The size of the address will be
5920 determined later, depending on destination register,
5921 suffix, or the default for the section. */
5922 i.types[this_operand].bitfield.imm8 = 1;
5923 i.types[this_operand].bitfield.imm16 = 1;
5924 i.types[this_operand].bitfield.imm32 = 1;
5925 i.types[this_operand].bitfield.imm32s = 1;
5926 i.types[this_operand].bitfield.imm64 = 1;
5927 i.types[this_operand] = operand_type_and (i.types[this_operand],
5935 i386_scale (char *scale)
5938 char *save = input_line_pointer;
5940 input_line_pointer = scale;
5941 val = get_absolute_expression ();
5946 i.log2_scale_factor = 0;
5949 i.log2_scale_factor = 1;
5952 i.log2_scale_factor = 2;
5955 i.log2_scale_factor = 3;
5959 char sep = *input_line_pointer;
5961 *input_line_pointer = '\0';
5962 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5964 *input_line_pointer = sep;
5965 input_line_pointer = save;
5969 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5971 as_warn (_("scale factor of %d without an index register"),
5972 1 << i.log2_scale_factor);
5973 i.log2_scale_factor = 0;
5975 scale = input_line_pointer;
5976 input_line_pointer = save;
5981 i386_displacement (char *disp_start, char *disp_end)
5985 char *save_input_line_pointer;
5986 char *gotfree_input_line;
5988 i386_operand_type bigdisp, types = anydisp;
5991 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5993 as_bad (_("at most %d displacement operands are allowed"),
5994 MAX_MEMORY_OPERANDS);
5998 UINTS_CLEAR (bigdisp);
5999 if ((i.types[this_operand].bitfield.jumpabsolute)
6000 || (!current_templates->start->opcode_modifier.jump
6001 && !current_templates->start->opcode_modifier.jumpdword))
6003 bigdisp.bitfield.disp32 = 1;
6004 override = (i.prefix[ADDR_PREFIX] != 0);
6005 if (flag_code == CODE_64BIT)
6009 bigdisp.bitfield.disp32s = 1;
6010 bigdisp.bitfield.disp64 = 1;
6013 else if ((flag_code == CODE_16BIT) ^ override)
6015 bigdisp.bitfield.disp32 = 0;
6016 bigdisp.bitfield.disp16 = 1;
6021 /* For PC-relative branches, the width of the displacement
6022 is dependent upon data size, not address size. */
6023 override = (i.prefix[DATA_PREFIX] != 0);
6024 if (flag_code == CODE_64BIT)
6026 if (override || i.suffix == WORD_MNEM_SUFFIX)
6027 bigdisp.bitfield.disp16 = 1;
6030 bigdisp.bitfield.disp32 = 1;
6031 bigdisp.bitfield.disp32s = 1;
6037 override = (i.suffix == (flag_code != CODE_16BIT
6039 : LONG_MNEM_SUFFIX));
6040 bigdisp.bitfield.disp32 = 1;
6041 if ((flag_code == CODE_16BIT) ^ override)
6043 bigdisp.bitfield.disp32 = 0;
6044 bigdisp.bitfield.disp16 = 1;
6048 i.types[this_operand] = operand_type_or (i.types[this_operand],
6051 exp = &disp_expressions[i.disp_operands];
6052 i.op[this_operand].disps = exp;
6054 save_input_line_pointer = input_line_pointer;
6055 input_line_pointer = disp_start;
6056 END_STRING_AND_SAVE (disp_end);
6058 #ifndef GCC_ASM_O_HACK
6059 #define GCC_ASM_O_HACK 0
6062 END_STRING_AND_SAVE (disp_end + 1);
6063 if (i.types[this_operand].bitfield.baseIndex
6064 && displacement_string_end[-1] == '+')
6066 /* This hack is to avoid a warning when using the "o"
6067 constraint within gcc asm statements.
6070 #define _set_tssldt_desc(n,addr,limit,type) \
6071 __asm__ __volatile__ ( \
6073 "movw %w1,2+%0\n\t" \
6075 "movb %b1,4+%0\n\t" \
6076 "movb %4,5+%0\n\t" \
6077 "movb $0,6+%0\n\t" \
6078 "movb %h1,7+%0\n\t" \
6080 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6082 This works great except that the output assembler ends
6083 up looking a bit weird if it turns out that there is
6084 no offset. You end up producing code that looks like:
6097 So here we provide the missing zero. */
6099 *displacement_string_end = '0';
6102 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6103 if (gotfree_input_line)
6104 input_line_pointer = gotfree_input_line;
6106 exp_seg = expression (exp);
6109 if (*input_line_pointer)
6110 as_bad (_("junk `%s' after expression"), input_line_pointer);
6112 RESTORE_END_STRING (disp_end + 1);
6114 input_line_pointer = save_input_line_pointer;
6115 if (gotfree_input_line)
6116 free (gotfree_input_line);
6119 /* We do this to make sure that the section symbol is in
6120 the symbol table. We will ultimately change the relocation
6121 to be relative to the beginning of the section. */
6122 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6123 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6124 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6126 if (exp->X_op != O_symbol)
6129 if (S_IS_LOCAL (exp->X_add_symbol)
6130 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6131 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6132 exp->X_op = O_subtract;
6133 exp->X_op_symbol = GOT_symbol;
6134 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6135 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6136 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6137 i.reloc[this_operand] = BFD_RELOC_64;
6139 i.reloc[this_operand] = BFD_RELOC_32;
6142 else if (exp->X_op == O_absent
6143 || exp->X_op == O_illegal
6144 || exp->X_op == O_big
6145 || (gotfree_input_line
6146 && (exp->X_op == O_constant
6147 || exp->X_op == O_register)))
6150 as_bad (_("missing or invalid displacement expression `%s'"),
6155 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6156 else if (exp->X_op != O_constant
6157 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6158 && exp_seg != absolute_section
6159 && exp_seg != text_section
6160 && exp_seg != data_section
6161 && exp_seg != bss_section
6162 && exp_seg != undefined_section
6163 && !bfd_is_com_section (exp_seg))
6165 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6170 RESTORE_END_STRING (disp_end);
6172 /* Check if this is a displacement only operand. */
6173 bigdisp = i.types[this_operand];
6174 bigdisp.bitfield.disp8 = 0;
6175 bigdisp.bitfield.disp16 = 0;
6176 bigdisp.bitfield.disp32 = 0;
6177 bigdisp.bitfield.disp32s = 0;
6178 bigdisp.bitfield.disp64 = 0;
6179 if (UINTS_ALL_ZERO (bigdisp))
6180 i.types[this_operand] = operand_type_and (i.types[this_operand],
6186 /* Make sure the memory operand we've been dealt is valid.
6187 Return 1 on success, 0 on a failure. */
6190 i386_index_check (const char *operand_string)
6193 #if INFER_ADDR_PREFIX
6199 if (flag_code == CODE_64BIT)
6202 && ((i.prefix[ADDR_PREFIX] == 0
6203 && !i.base_reg->reg_type.bitfield.reg64)
6204 || (i.prefix[ADDR_PREFIX]
6205 && !i.base_reg->reg_type.bitfield.reg32))
6207 || i.base_reg->reg_num !=
6208 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6210 && (!i.index_reg->reg_type.bitfield.baseindex
6211 || (i.prefix[ADDR_PREFIX] == 0
6212 && i.index_reg->reg_num != RegRiz
6213 && !i.index_reg->reg_type.bitfield.reg64
6215 || (i.prefix[ADDR_PREFIX]
6216 && i.index_reg->reg_num != RegEiz
6217 && !i.index_reg->reg_type.bitfield.reg32))))
6222 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6226 && (!i.base_reg->reg_type.bitfield.reg16
6227 || !i.base_reg->reg_type.bitfield.baseindex))
6229 && (!i.index_reg->reg_type.bitfield.reg16
6230 || !i.index_reg->reg_type.bitfield.baseindex
6232 && i.base_reg->reg_num < 6
6233 && i.index_reg->reg_num >= 6
6234 && i.log2_scale_factor == 0))))
6241 && !i.base_reg->reg_type.bitfield.reg32)
6243 && ((!i.index_reg->reg_type.bitfield.reg32
6244 && i.index_reg->reg_num != RegEiz)
6245 || !i.index_reg->reg_type.bitfield.baseindex)))
6251 #if INFER_ADDR_PREFIX
6252 if (i.prefix[ADDR_PREFIX] == 0)
6254 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6256 /* Change the size of any displacement too. At most one of
6257 Disp16 or Disp32 is set.
6258 FIXME. There doesn't seem to be any real need for separate
6259 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6260 Removing them would probably clean up the code quite a lot. */
6261 if (flag_code != CODE_64BIT
6262 && (i.types[this_operand].bitfield.disp16
6263 || i.types[this_operand].bitfield.disp32))
6264 i.types[this_operand]
6265 = operand_type_xor (i.types[this_operand], disp16_32);
6270 as_bad (_("`%s' is not a valid base/index expression"),
6274 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6276 flag_code_names[flag_code]);
6281 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6285 i386_att_operand (char *operand_string)
6289 char *op_string = operand_string;
6291 if (is_space_char (*op_string))
6294 /* We check for an absolute prefix (differentiating,
6295 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6296 if (*op_string == ABSOLUTE_PREFIX)
6299 if (is_space_char (*op_string))
6301 i.types[this_operand].bitfield.jumpabsolute = 1;
6304 /* Check if operand is a register. */
6305 if ((r = parse_register (op_string, &end_op)) != NULL)
6307 i386_operand_type temp;
6309 /* Check for a segment override by searching for ':' after a
6310 segment register. */
6312 if (is_space_char (*op_string))
6314 if (*op_string == ':'
6315 && (r->reg_type.bitfield.sreg2
6316 || r->reg_type.bitfield.sreg3))
6321 i.seg[i.mem_operands] = &es;
6324 i.seg[i.mem_operands] = &cs;
6327 i.seg[i.mem_operands] = &ss;
6330 i.seg[i.mem_operands] = &ds;
6333 i.seg[i.mem_operands] = &fs;
6336 i.seg[i.mem_operands] = &gs;
6340 /* Skip the ':' and whitespace. */
6342 if (is_space_char (*op_string))
6345 if (!is_digit_char (*op_string)
6346 && !is_identifier_char (*op_string)
6347 && *op_string != '('
6348 && *op_string != ABSOLUTE_PREFIX)
6350 as_bad (_("bad memory operand `%s'"), op_string);
6353 /* Handle case of %es:*foo. */
6354 if (*op_string == ABSOLUTE_PREFIX)
6357 if (is_space_char (*op_string))
6359 i.types[this_operand].bitfield.jumpabsolute = 1;
6361 goto do_memory_reference;
6365 as_bad (_("junk `%s' after register"), op_string);
6369 temp.bitfield.baseindex = 0;
6370 i.types[this_operand] = operand_type_or (i.types[this_operand],
6372 i.types[this_operand].bitfield.unspecified = 0;
6373 i.op[this_operand].regs = r;
6376 else if (*op_string == REGISTER_PREFIX)
6378 as_bad (_("bad register name `%s'"), op_string);
6381 else if (*op_string == IMMEDIATE_PREFIX)
6384 if (i.types[this_operand].bitfield.jumpabsolute)
6386 as_bad (_("immediate operand illegal with absolute jump"));
6389 if (!i386_immediate (op_string))
6392 else if (is_digit_char (*op_string)
6393 || is_identifier_char (*op_string)
6394 || *op_string == '(')
6396 /* This is a memory reference of some sort. */
6399 /* Start and end of displacement string expression (if found). */
6400 char *displacement_string_start;
6401 char *displacement_string_end;
6403 do_memory_reference:
6404 if ((i.mem_operands == 1
6405 && !current_templates->start->opcode_modifier.isstring)
6406 || i.mem_operands == 2)
6408 as_bad (_("too many memory references for `%s'"),
6409 current_templates->start->name);
6413 /* Check for base index form. We detect the base index form by
6414 looking for an ')' at the end of the operand, searching
6415 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6417 base_string = op_string + strlen (op_string);
6420 if (is_space_char (*base_string))
6423 /* If we only have a displacement, set-up for it to be parsed later. */
6424 displacement_string_start = op_string;
6425 displacement_string_end = base_string + 1;
6427 if (*base_string == ')')
6430 unsigned int parens_balanced = 1;
6431 /* We've already checked that the number of left & right ()'s are
6432 equal, so this loop will not be infinite. */
6436 if (*base_string == ')')
6438 if (*base_string == '(')
6441 while (parens_balanced);
6443 temp_string = base_string;
6445 /* Skip past '(' and whitespace. */
6447 if (is_space_char (*base_string))
6450 if (*base_string == ','
6451 || ((i.base_reg = parse_register (base_string, &end_op))
6454 displacement_string_end = temp_string;
6456 i.types[this_operand].bitfield.baseindex = 1;
6460 base_string = end_op;
6461 if (is_space_char (*base_string))
6465 /* There may be an index reg or scale factor here. */
6466 if (*base_string == ',')
6469 if (is_space_char (*base_string))
6472 if ((i.index_reg = parse_register (base_string, &end_op))
6475 base_string = end_op;
6476 if (is_space_char (*base_string))
6478 if (*base_string == ',')
6481 if (is_space_char (*base_string))
6484 else if (*base_string != ')')
6486 as_bad (_("expecting `,' or `)' "
6487 "after index register in `%s'"),
6492 else if (*base_string == REGISTER_PREFIX)
6494 as_bad (_("bad register name `%s'"), base_string);
6498 /* Check for scale factor. */
6499 if (*base_string != ')')
6501 char *end_scale = i386_scale (base_string);
6506 base_string = end_scale;
6507 if (is_space_char (*base_string))
6509 if (*base_string != ')')
6511 as_bad (_("expecting `)' "
6512 "after scale factor in `%s'"),
6517 else if (!i.index_reg)
6519 as_bad (_("expecting index register or scale factor "
6520 "after `,'; got '%c'"),
6525 else if (*base_string != ')')
6527 as_bad (_("expecting `,' or `)' "
6528 "after base register in `%s'"),
6533 else if (*base_string == REGISTER_PREFIX)
6535 as_bad (_("bad register name `%s'"), base_string);
6540 /* If there's an expression beginning the operand, parse it,
6541 assuming displacement_string_start and
6542 displacement_string_end are meaningful. */
6543 if (displacement_string_start != displacement_string_end)
6545 if (!i386_displacement (displacement_string_start,
6546 displacement_string_end))
6550 /* Special case for (%dx) while doing input/output op. */
6552 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6554 && i.log2_scale_factor == 0
6555 && i.seg[i.mem_operands] == 0
6556 && !operand_type_check (i.types[this_operand], disp))
6558 UINTS_CLEAR (i.types[this_operand]);
6559 i.types[this_operand].bitfield.inoutportreg = 1;
6563 if (i386_index_check (operand_string) == 0)
6565 i.types[this_operand].bitfield.mem = 1;
6570 /* It's not a memory operand; argh! */
6571 as_bad (_("invalid char %s beginning operand %d `%s'"),
6572 output_invalid (*op_string),
6577 return 1; /* Normal return. */
6580 /* md_estimate_size_before_relax()
6582 Called just before relax() for rs_machine_dependent frags. The x86
6583 assembler uses these frags to handle variable size jump
6586 Any symbol that is now undefined will not become defined.
6587 Return the correct fr_subtype in the frag.
6588 Return the initial "guess for variable size of frag" to caller.
6589 The guess is actually the growth beyond the fixed part. Whatever
6590 we do to grow the fixed or variable part contributes to our
6594 md_estimate_size_before_relax (fragP, segment)
6598 /* We've already got fragP->fr_subtype right; all we have to do is
6599 check for un-relaxable symbols. On an ELF system, we can't relax
6600 an externally visible symbol, because it may be overridden by a
6602 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6605 && (S_IS_EXTERNAL (fragP->fr_symbol)
6606 || S_IS_WEAK (fragP->fr_symbol)))
6610 /* Symbol is undefined in this segment, or we need to keep a
6611 reloc so that weak symbols can be overridden. */
6612 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6613 enum bfd_reloc_code_real reloc_type;
6614 unsigned char *opcode;
6617 if (fragP->fr_var != NO_RELOC)
6618 reloc_type = fragP->fr_var;
6620 reloc_type = BFD_RELOC_16_PCREL;
6622 reloc_type = BFD_RELOC_32_PCREL;
6624 old_fr_fix = fragP->fr_fix;
6625 opcode = (unsigned char *) fragP->fr_opcode;
6627 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6630 /* Make jmp (0xeb) a (d)word displacement jump. */
6632 fragP->fr_fix += size;
6633 fix_new (fragP, old_fr_fix, size,
6635 fragP->fr_offset, 1,
6641 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6643 /* Negate the condition, and branch past an
6644 unconditional jump. */
6647 /* Insert an unconditional jump. */
6649 /* We added two extra opcode bytes, and have a two byte
6651 fragP->fr_fix += 2 + 2;
6652 fix_new (fragP, old_fr_fix + 2, 2,
6654 fragP->fr_offset, 1,
6661 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6666 fixP = fix_new (fragP, old_fr_fix, 1,
6668 fragP->fr_offset, 1,
6670 fixP->fx_signed = 1;
6674 /* This changes the byte-displacement jump 0x7N
6675 to the (d)word-displacement jump 0x0f,0x8N. */
6676 opcode[1] = opcode[0] + 0x10;
6677 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6678 /* We've added an opcode byte. */
6679 fragP->fr_fix += 1 + size;
6680 fix_new (fragP, old_fr_fix + 1, size,
6682 fragP->fr_offset, 1,
6687 BAD_CASE (fragP->fr_subtype);
6691 return fragP->fr_fix - old_fr_fix;
6694 /* Guess size depending on current relax state. Initially the relax
6695 state will correspond to a short jump and we return 1, because
6696 the variable part of the frag (the branch offset) is one byte
6697 long. However, we can relax a section more than once and in that
6698 case we must either set fr_subtype back to the unrelaxed state,
6699 or return the value for the appropriate branch. */
6700 return md_relax_table[fragP->fr_subtype].rlx_length;
6703 /* Called after relax() is finished.
6705 In: Address of frag.
6706 fr_type == rs_machine_dependent.
6707 fr_subtype is what the address relaxed to.
6709 Out: Any fixSs and constants are set up.
6710 Caller will turn frag into a ".space 0". */
6713 md_convert_frag (abfd, sec, fragP)
6714 bfd *abfd ATTRIBUTE_UNUSED;
6715 segT sec ATTRIBUTE_UNUSED;
6718 unsigned char *opcode;
6719 unsigned char *where_to_put_displacement = NULL;
6720 offsetT target_address;
6721 offsetT opcode_address;
6722 unsigned int extension = 0;
6723 offsetT displacement_from_opcode_start;
6725 opcode = (unsigned char *) fragP->fr_opcode;
6727 /* Address we want to reach in file space. */
6728 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6730 /* Address opcode resides at in file space. */
6731 opcode_address = fragP->fr_address + fragP->fr_fix;
6733 /* Displacement from opcode start to fill into instruction. */
6734 displacement_from_opcode_start = target_address - opcode_address;
6736 if ((fragP->fr_subtype & BIG) == 0)
6738 /* Don't have to change opcode. */
6739 extension = 1; /* 1 opcode + 1 displacement */
6740 where_to_put_displacement = &opcode[1];
6744 if (no_cond_jump_promotion
6745 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6746 as_warn_where (fragP->fr_file, fragP->fr_line,
6747 _("long jump required"));
6749 switch (fragP->fr_subtype)
6751 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6752 extension = 4; /* 1 opcode + 4 displacement */
6754 where_to_put_displacement = &opcode[1];
6757 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6758 extension = 2; /* 1 opcode + 2 displacement */
6760 where_to_put_displacement = &opcode[1];
6763 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6764 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6765 extension = 5; /* 2 opcode + 4 displacement */
6766 opcode[1] = opcode[0] + 0x10;
6767 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6768 where_to_put_displacement = &opcode[2];
6771 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6772 extension = 3; /* 2 opcode + 2 displacement */
6773 opcode[1] = opcode[0] + 0x10;
6774 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6775 where_to_put_displacement = &opcode[2];
6778 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6783 where_to_put_displacement = &opcode[3];
6787 BAD_CASE (fragP->fr_subtype);
6792 /* If size if less then four we are sure that the operand fits,
6793 but if it's 4, then it could be that the displacement is larger
6795 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6797 && ((addressT) (displacement_from_opcode_start - extension
6798 + ((addressT) 1 << 31))
6799 > (((addressT) 2 << 31) - 1)))
6801 as_bad_where (fragP->fr_file, fragP->fr_line,
6802 _("jump target out of range"));
6803 /* Make us emit 0. */
6804 displacement_from_opcode_start = extension;
6806 /* Now put displacement after opcode. */
6807 md_number_to_chars ((char *) where_to_put_displacement,
6808 (valueT) (displacement_from_opcode_start - extension),
6809 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6810 fragP->fr_fix += extension;
6813 /* Apply a fixup (fixS) to segment data, once it has been determined
6814 by our caller that we have all the info we need to fix it up.
6816 On the 386, immediates, displacements, and data pointers are all in
6817 the same (little-endian) format, so we don't need to care about which
6821 md_apply_fix (fixP, valP, seg)
6822 /* The fix we're to put in. */
6824 /* Pointer to the value of the bits. */
6826 /* Segment fix is from. */
6827 segT seg ATTRIBUTE_UNUSED;
6829 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6830 valueT value = *valP;
6832 #if !defined (TE_Mach)
6835 switch (fixP->fx_r_type)
6841 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6844 case BFD_RELOC_X86_64_32S:
6845 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6848 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6851 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6856 if (fixP->fx_addsy != NULL
6857 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6858 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6859 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6860 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6861 && !use_rela_relocations)
6863 /* This is a hack. There should be a better way to handle this.
6864 This covers for the fact that bfd_install_relocation will
6865 subtract the current location (for partial_inplace, PC relative
6866 relocations); see more below. */
6870 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6873 value += fixP->fx_where + fixP->fx_frag->fr_address;
6875 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6878 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6881 || (symbol_section_p (fixP->fx_addsy)
6882 && sym_seg != absolute_section))
6883 && !generic_force_reloc (fixP))
6885 /* Yes, we add the values in twice. This is because
6886 bfd_install_relocation subtracts them out again. I think
6887 bfd_install_relocation is broken, but I don't dare change
6889 value += fixP->fx_where + fixP->fx_frag->fr_address;
6893 #if defined (OBJ_COFF) && defined (TE_PE)
6894 /* For some reason, the PE format does not store a
6895 section address offset for a PC relative symbol. */
6896 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6897 || S_IS_WEAK (fixP->fx_addsy))
6898 value += md_pcrel_from (fixP);
6902 /* Fix a few things - the dynamic linker expects certain values here,
6903 and we must not disappoint it. */
6904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6905 if (IS_ELF && fixP->fx_addsy)
6906 switch (fixP->fx_r_type)
6908 case BFD_RELOC_386_PLT32:
6909 case BFD_RELOC_X86_64_PLT32:
6910 /* Make the jump instruction point to the address of the operand. At
6911 runtime we merely add the offset to the actual PLT entry. */
6915 case BFD_RELOC_386_TLS_GD:
6916 case BFD_RELOC_386_TLS_LDM:
6917 case BFD_RELOC_386_TLS_IE_32:
6918 case BFD_RELOC_386_TLS_IE:
6919 case BFD_RELOC_386_TLS_GOTIE:
6920 case BFD_RELOC_386_TLS_GOTDESC:
6921 case BFD_RELOC_X86_64_TLSGD:
6922 case BFD_RELOC_X86_64_TLSLD:
6923 case BFD_RELOC_X86_64_GOTTPOFF:
6924 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6925 value = 0; /* Fully resolved at runtime. No addend. */
6927 case BFD_RELOC_386_TLS_LE:
6928 case BFD_RELOC_386_TLS_LDO_32:
6929 case BFD_RELOC_386_TLS_LE_32:
6930 case BFD_RELOC_X86_64_DTPOFF32:
6931 case BFD_RELOC_X86_64_DTPOFF64:
6932 case BFD_RELOC_X86_64_TPOFF32:
6933 case BFD_RELOC_X86_64_TPOFF64:
6934 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6937 case BFD_RELOC_386_TLS_DESC_CALL:
6938 case BFD_RELOC_X86_64_TLSDESC_CALL:
6939 value = 0; /* Fully resolved at runtime. No addend. */
6940 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6944 case BFD_RELOC_386_GOT32:
6945 case BFD_RELOC_X86_64_GOT32:
6946 value = 0; /* Fully resolved at runtime. No addend. */
6949 case BFD_RELOC_VTABLE_INHERIT:
6950 case BFD_RELOC_VTABLE_ENTRY:
6957 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6959 #endif /* !defined (TE_Mach) */
6961 /* Are we finished with this relocation now? */
6962 if (fixP->fx_addsy == NULL)
6964 else if (use_rela_relocations)
6966 fixP->fx_no_overflow = 1;
6967 /* Remember value for tc_gen_reloc. */
6968 fixP->fx_addnumber = value;
6972 md_number_to_chars (p, value, fixP->fx_size);
6976 md_atof (int type, char *litP, int *sizeP)
6978 /* This outputs the LITTLENUMs in REVERSE order;
6979 in accord with the bigendian 386. */
6980 return ieee_md_atof (type, litP, sizeP, FALSE);
6983 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6986 output_invalid (int c)
6989 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6992 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6993 "(0x%x)", (unsigned char) c);
6994 return output_invalid_buf;
6997 /* REG_STRING starts *before* REGISTER_PREFIX. */
6999 static const reg_entry *
7000 parse_real_register (char *reg_string, char **end_op)
7002 char *s = reg_string;
7004 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7007 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7008 if (*s == REGISTER_PREFIX)
7011 if (is_space_char (*s))
7015 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7017 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7018 return (const reg_entry *) NULL;
7022 /* For naked regs, make sure that we are not dealing with an identifier.
7023 This prevents confusing an identifier like `eax_var' with register
7025 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7026 return (const reg_entry *) NULL;
7030 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7032 /* Handle floating point regs, allowing spaces in the (i) part. */
7033 if (r == i386_regtab /* %st is first entry of table */)
7035 if (is_space_char (*s))
7040 if (is_space_char (*s))
7042 if (*s >= '0' && *s <= '7')
7046 if (is_space_char (*s))
7051 r = hash_find (reg_hash, "st(0)");
7056 /* We have "%st(" then garbage. */
7057 return (const reg_entry *) NULL;
7061 if (r == NULL || allow_pseudo_reg)
7064 if (UINTS_ALL_ZERO (r->reg_type))
7065 return (const reg_entry *) NULL;
7067 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7068 if (!allow_index_reg
7069 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7070 return (const reg_entry *) NULL;
7072 if (((r->reg_flags & (RegRex64 | RegRex))
7073 || r->reg_type.bitfield.reg64)
7074 && (!cpu_arch_flags.bitfield.cpulm
7075 || !UINTS_EQUAL (r->reg_type, control))
7076 && flag_code != CODE_64BIT)
7077 return (const reg_entry *) NULL;
7079 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7080 return (const reg_entry *) NULL;
7085 /* REG_STRING starts *before* REGISTER_PREFIX. */
7087 static const reg_entry *
7088 parse_register (char *reg_string, char **end_op)
7092 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7093 r = parse_real_register (reg_string, end_op);
7098 char *save = input_line_pointer;
7102 input_line_pointer = reg_string;
7103 c = get_symbol_end ();
7104 symbolP = symbol_find (reg_string);
7105 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7107 const expressionS *e = symbol_get_value_expression (symbolP);
7109 know (e->X_op == O_register);
7110 know (e->X_add_number >= 0
7111 && (valueT) e->X_add_number < i386_regtab_size);
7112 r = i386_regtab + e->X_add_number;
7113 *end_op = input_line_pointer;
7115 *input_line_pointer = c;
7116 input_line_pointer = save;
7122 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7125 char *end = input_line_pointer;
7128 r = parse_register (name, &input_line_pointer);
7129 if (r && end <= input_line_pointer)
7131 *nextcharP = *input_line_pointer;
7132 *input_line_pointer = 0;
7133 e->X_op = O_register;
7134 e->X_add_number = r - i386_regtab;
7137 input_line_pointer = end;
7143 md_operand (expressionS *e)
7145 if (*input_line_pointer == REGISTER_PREFIX)
7148 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7152 e->X_op = O_register;
7153 e->X_add_number = r - i386_regtab;
7154 input_line_pointer = end;
7160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7161 const char *md_shortopts = "kVQ:sqn";
7163 const char *md_shortopts = "qn";
7166 #define OPTION_32 (OPTION_MD_BASE + 0)
7167 #define OPTION_64 (OPTION_MD_BASE + 1)
7168 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7169 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7170 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7171 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7172 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7173 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7174 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7175 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7177 struct option md_longopts[] =
7179 {"32", no_argument, NULL, OPTION_32},
7180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7181 {"64", no_argument, NULL, OPTION_64},
7183 {"divide", no_argument, NULL, OPTION_DIVIDE},
7184 {"march", required_argument, NULL, OPTION_MARCH},
7185 {"mtune", required_argument, NULL, OPTION_MTUNE},
7186 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7187 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7188 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7189 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7190 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7191 {NULL, no_argument, NULL, 0}
7193 size_t md_longopts_size = sizeof (md_longopts);
7196 md_parse_option (int c, char *arg)
7204 optimize_align_code = 0;
7211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7212 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7213 should be emitted or not. FIXME: Not implemented. */
7217 /* -V: SVR4 argument to print version ID. */
7219 print_version_id ();
7222 /* -k: Ignore for FreeBSD compatibility. */
7227 /* -s: On i386 Solaris, this tells the native assembler to use
7228 .stab instead of .stab.excl. We always use .stab anyhow. */
7231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7234 const char **list, **l;
7236 list = bfd_target_list ();
7237 for (l = list; *l != NULL; l++)
7238 if (CONST_STRNEQ (*l, "elf64-x86-64")
7239 || strcmp (*l, "coff-x86-64") == 0
7240 || strcmp (*l, "pe-x86-64") == 0
7241 || strcmp (*l, "pei-x86-64") == 0)
7243 default_arch = "x86_64";
7247 as_fatal (_("No compiled in support for x86_64"));
7254 default_arch = "i386";
7258 #ifdef SVR4_COMMENT_CHARS
7263 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7265 for (s = i386_comment_chars; *s != '\0'; s++)
7269 i386_comment_chars = n;
7275 arch = xstrdup (arg);
7279 as_fatal (_("Invalid -march= option: `%s'"), arg);
7280 next = strchr (arch, '+');
7283 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7285 if (strcmp (arch, cpu_arch [i].name) == 0)
7288 cpu_arch_name = cpu_arch[i].name;
7289 cpu_sub_arch_name = NULL;
7290 cpu_arch_flags = cpu_arch[i].flags;
7291 cpu_arch_isa = cpu_arch[i].type;
7292 cpu_arch_isa_flags = cpu_arch[i].flags;
7293 if (!cpu_arch_tune_set)
7295 cpu_arch_tune = cpu_arch_isa;
7296 cpu_arch_tune_flags = cpu_arch_isa_flags;
7300 else if (*cpu_arch [i].name == '.'
7301 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7303 /* ISA entension. */
7304 i386_cpu_flags flags;
7305 flags = cpu_flags_or (cpu_arch_flags,
7307 if (!UINTS_EQUAL (flags, cpu_arch_flags))
7309 if (cpu_sub_arch_name)
7311 char *name = cpu_sub_arch_name;
7312 cpu_sub_arch_name = concat (name,
7314 (const char *) NULL);
7318 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7319 cpu_arch_flags = flags;
7325 if (i >= ARRAY_SIZE (cpu_arch))
7326 as_fatal (_("Invalid -march= option: `%s'"), arg);
7330 while (next != NULL );
7335 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7336 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7338 if (strcmp (arg, cpu_arch [i].name) == 0)
7340 cpu_arch_tune_set = 1;
7341 cpu_arch_tune = cpu_arch [i].type;
7342 cpu_arch_tune_flags = cpu_arch[i].flags;
7346 if (i >= ARRAY_SIZE (cpu_arch))
7347 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7350 case OPTION_MMNEMONIC:
7351 if (strcasecmp (arg, "att") == 0)
7353 else if (strcasecmp (arg, "intel") == 0)
7356 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7359 case OPTION_MSYNTAX:
7360 if (strcasecmp (arg, "att") == 0)
7362 else if (strcasecmp (arg, "intel") == 0)
7365 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7368 case OPTION_MINDEX_REG:
7369 allow_index_reg = 1;
7372 case OPTION_MNAKED_REG:
7373 allow_naked_reg = 1;
7376 case OPTION_MOLD_GCC:
7387 md_show_usage (stream)
7390 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7391 fprintf (stream, _("\
7393 -V print assembler version number\n\
7396 fprintf (stream, _("\
7397 -n Do not optimize code alignment\n\
7398 -q quieten some warnings\n"));
7399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7400 fprintf (stream, _("\
7403 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7404 fprintf (stream, _("\
7405 --32/--64 generate 32bit/64bit code\n"));
7407 #ifdef SVR4_COMMENT_CHARS
7408 fprintf (stream, _("\
7409 --divide do not treat `/' as a comment character\n"));
7411 fprintf (stream, _("\
7412 --divide ignored\n"));
7414 fprintf (stream, _("\
7415 -march=CPU[,+EXTENSION...]\n\
7416 generate code for CPU and EXTENSION, CPU is one of:\n\
7417 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7418 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7419 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7420 generic32, generic64\n\
7421 EXTENSION is combination of:\n\
7422 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7423 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7425 fprintf (stream, _("\
7426 -mtune=CPU optimize for CPU, CPU is one of:\n\
7427 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7428 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7429 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7430 generic32, generic64\n"));
7431 fprintf (stream, _("\
7432 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7433 fprintf (stream, _("\
7434 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7435 fprintf (stream, _("\
7436 -mindex-reg support pseudo index registers\n"));
7437 fprintf (stream, _("\
7438 -mnaked-reg don't require `%%' prefix for registers\n"));
7439 fprintf (stream, _("\
7440 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7443 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7444 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7446 /* Pick the target format to use. */
7449 i386_target_format (void)
7451 if (!strcmp (default_arch, "x86_64"))
7453 set_code_flag (CODE_64BIT);
7454 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7456 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7457 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7458 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7459 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7460 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7461 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7462 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7463 cpu_arch_isa_flags.bitfield.cpummx= 1;
7464 cpu_arch_isa_flags.bitfield.cpusse = 1;
7465 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7467 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7469 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7470 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7471 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7472 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7473 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7474 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7475 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7476 cpu_arch_tune_flags.bitfield.cpummx= 1;
7477 cpu_arch_tune_flags.bitfield.cpusse = 1;
7478 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7481 else if (!strcmp (default_arch, "i386"))
7483 set_code_flag (CODE_32BIT);
7484 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7486 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7487 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7488 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7490 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7492 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7493 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7494 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7498 as_fatal (_("Unknown architecture"));
7499 switch (OUTPUT_FLAVOR)
7502 case bfd_target_coff_flavour:
7503 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7506 #ifdef OBJ_MAYBE_AOUT
7507 case bfd_target_aout_flavour:
7508 return AOUT_TARGET_FORMAT;
7510 #ifdef OBJ_MAYBE_COFF
7511 case bfd_target_coff_flavour:
7514 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7515 case bfd_target_elf_flavour:
7517 if (flag_code == CODE_64BIT)
7520 use_rela_relocations = 1;
7522 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7531 #endif /* OBJ_MAYBE_ more than one */
7533 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7535 i386_elf_emit_arch_note (void)
7537 if (IS_ELF && cpu_arch_name != NULL)
7540 asection *seg = now_seg;
7541 subsegT subseg = now_subseg;
7542 Elf_Internal_Note i_note;
7543 Elf_External_Note e_note;
7544 asection *note_secp;
7547 /* Create the .note section. */
7548 note_secp = subseg_new (".note", 0);
7549 bfd_set_section_flags (stdoutput,
7551 SEC_HAS_CONTENTS | SEC_READONLY);
7553 /* Process the arch string. */
7554 len = strlen (cpu_arch_name);
7556 i_note.namesz = len + 1;
7558 i_note.type = NT_ARCH;
7559 p = frag_more (sizeof (e_note.namesz));
7560 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7561 p = frag_more (sizeof (e_note.descsz));
7562 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7563 p = frag_more (sizeof (e_note.type));
7564 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7565 p = frag_more (len + 1);
7566 strcpy (p, cpu_arch_name);
7568 frag_align (2, 0, 0);
7570 subseg_set (seg, subseg);
7576 md_undefined_symbol (name)
7579 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7580 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7581 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7582 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7586 if (symbol_find (name))
7587 as_bad (_("GOT already in symbol table"));
7588 GOT_symbol = symbol_new (name, undefined_section,
7589 (valueT) 0, &zero_address_frag);
7596 /* Round up a section size to the appropriate boundary. */
7599 md_section_align (segment, size)
7600 segT segment ATTRIBUTE_UNUSED;
7603 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7604 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7606 /* For a.out, force the section size to be aligned. If we don't do
7607 this, BFD will align it for us, but it will not write out the
7608 final bytes of the section. This may be a bug in BFD, but it is
7609 easier to fix it here since that is how the other a.out targets
7613 align = bfd_get_section_alignment (stdoutput, segment);
7614 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7621 /* On the i386, PC-relative offsets are relative to the start of the
7622 next instruction. That is, the address of the offset, plus its
7623 size, since the offset is always the last part of the insn. */
7626 md_pcrel_from (fixS *fixP)
7628 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7634 s_bss (int ignore ATTRIBUTE_UNUSED)
7638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7640 obj_elf_section_change_hook ();
7642 temp = get_absolute_expression ();
7643 subseg_set (bss_section, (subsegT) temp);
7644 demand_empty_rest_of_line ();
7650 i386_validate_fix (fixS *fixp)
7652 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7654 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7658 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7663 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7665 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7672 tc_gen_reloc (section, fixp)
7673 asection *section ATTRIBUTE_UNUSED;
7677 bfd_reloc_code_real_type code;
7679 switch (fixp->fx_r_type)
7681 case BFD_RELOC_X86_64_PLT32:
7682 case BFD_RELOC_X86_64_GOT32:
7683 case BFD_RELOC_X86_64_GOTPCREL:
7684 case BFD_RELOC_386_PLT32:
7685 case BFD_RELOC_386_GOT32:
7686 case BFD_RELOC_386_GOTOFF:
7687 case BFD_RELOC_386_GOTPC:
7688 case BFD_RELOC_386_TLS_GD:
7689 case BFD_RELOC_386_TLS_LDM:
7690 case BFD_RELOC_386_TLS_LDO_32:
7691 case BFD_RELOC_386_TLS_IE_32:
7692 case BFD_RELOC_386_TLS_IE:
7693 case BFD_RELOC_386_TLS_GOTIE:
7694 case BFD_RELOC_386_TLS_LE_32:
7695 case BFD_RELOC_386_TLS_LE:
7696 case BFD_RELOC_386_TLS_GOTDESC:
7697 case BFD_RELOC_386_TLS_DESC_CALL:
7698 case BFD_RELOC_X86_64_TLSGD:
7699 case BFD_RELOC_X86_64_TLSLD:
7700 case BFD_RELOC_X86_64_DTPOFF32:
7701 case BFD_RELOC_X86_64_DTPOFF64:
7702 case BFD_RELOC_X86_64_GOTTPOFF:
7703 case BFD_RELOC_X86_64_TPOFF32:
7704 case BFD_RELOC_X86_64_TPOFF64:
7705 case BFD_RELOC_X86_64_GOTOFF64:
7706 case BFD_RELOC_X86_64_GOTPC32:
7707 case BFD_RELOC_X86_64_GOT64:
7708 case BFD_RELOC_X86_64_GOTPCREL64:
7709 case BFD_RELOC_X86_64_GOTPC64:
7710 case BFD_RELOC_X86_64_GOTPLT64:
7711 case BFD_RELOC_X86_64_PLTOFF64:
7712 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7713 case BFD_RELOC_X86_64_TLSDESC_CALL:
7715 case BFD_RELOC_VTABLE_ENTRY:
7716 case BFD_RELOC_VTABLE_INHERIT:
7718 case BFD_RELOC_32_SECREL:
7720 code = fixp->fx_r_type;
7722 case BFD_RELOC_X86_64_32S:
7723 if (!fixp->fx_pcrel)
7725 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7726 code = fixp->fx_r_type;
7732 switch (fixp->fx_size)
7735 as_bad_where (fixp->fx_file, fixp->fx_line,
7736 _("can not do %d byte pc-relative relocation"),
7738 code = BFD_RELOC_32_PCREL;
7740 case 1: code = BFD_RELOC_8_PCREL; break;
7741 case 2: code = BFD_RELOC_16_PCREL; break;
7742 case 4: code = BFD_RELOC_32_PCREL; break;
7744 case 8: code = BFD_RELOC_64_PCREL; break;
7750 switch (fixp->fx_size)
7753 as_bad_where (fixp->fx_file, fixp->fx_line,
7754 _("can not do %d byte relocation"),
7756 code = BFD_RELOC_32;
7758 case 1: code = BFD_RELOC_8; break;
7759 case 2: code = BFD_RELOC_16; break;
7760 case 4: code = BFD_RELOC_32; break;
7762 case 8: code = BFD_RELOC_64; break;
7769 if ((code == BFD_RELOC_32
7770 || code == BFD_RELOC_32_PCREL
7771 || code == BFD_RELOC_X86_64_32S)
7773 && fixp->fx_addsy == GOT_symbol)
7776 code = BFD_RELOC_386_GOTPC;
7778 code = BFD_RELOC_X86_64_GOTPC32;
7780 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7782 && fixp->fx_addsy == GOT_symbol)
7784 code = BFD_RELOC_X86_64_GOTPC64;
7787 rel = (arelent *) xmalloc (sizeof (arelent));
7788 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7789 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7791 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7793 if (!use_rela_relocations)
7795 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7796 vtable entry to be used in the relocation's section offset. */
7797 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7798 rel->address = fixp->fx_offset;
7802 /* Use the rela in 64bit mode. */
7805 if (!fixp->fx_pcrel)
7806 rel->addend = fixp->fx_offset;
7810 case BFD_RELOC_X86_64_PLT32:
7811 case BFD_RELOC_X86_64_GOT32:
7812 case BFD_RELOC_X86_64_GOTPCREL:
7813 case BFD_RELOC_X86_64_TLSGD:
7814 case BFD_RELOC_X86_64_TLSLD:
7815 case BFD_RELOC_X86_64_GOTTPOFF:
7816 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7817 case BFD_RELOC_X86_64_TLSDESC_CALL:
7818 rel->addend = fixp->fx_offset - fixp->fx_size;
7821 rel->addend = (section->vma
7823 + fixp->fx_addnumber
7824 + md_pcrel_from (fixp));
7829 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7830 if (rel->howto == NULL)
7832 as_bad_where (fixp->fx_file, fixp->fx_line,
7833 _("cannot represent relocation type %s"),
7834 bfd_get_reloc_code_name (code));
7835 /* Set howto to a garbage value so that we can keep going. */
7836 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7837 assert (rel->howto != NULL);
7844 /* Parse operands using Intel syntax. This implements a recursive descent
7845 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7848 FIXME: We do not recognize the full operand grammar defined in the MASM
7849 documentation. In particular, all the structure/union and
7850 high-level macro operands are missing.
7852 Uppercase words are terminals, lower case words are non-terminals.
7853 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7854 bars '|' denote choices. Most grammar productions are implemented in
7855 functions called 'intel_<production>'.
7857 Initial production is 'expr'.
7863 binOp & | AND | \| | OR | ^ | XOR
7865 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7867 constant digits [[ radixOverride ]]
7869 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7907 => expr expr cmpOp e04
7910 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7911 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7913 hexdigit a | b | c | d | e | f
7914 | A | B | C | D | E | F
7920 mulOp * | / | % | MOD | << | SHL | >> | SHR
7924 register specialRegister
7928 segmentRegister CS | DS | ES | FS | GS | SS
7930 specialRegister CR0 | CR2 | CR3 | CR4
7931 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7932 | TR3 | TR4 | TR5 | TR6 | TR7
7934 We simplify the grammar in obvious places (e.g., register parsing is
7935 done by calling parse_register) and eliminate immediate left recursion
7936 to implement a recursive-descent parser.
7940 expr' cmpOp e04 expr'
7991 /* Parsing structure for the intel syntax parser. Used to implement the
7992 semantic actions for the operand grammar. */
7993 struct intel_parser_s
7995 char *op_string; /* The string being parsed. */
7996 int got_a_float; /* Whether the operand is a float. */
7997 int op_modifier; /* Operand modifier. */
7998 int is_mem; /* 1 if operand is memory reference. */
7999 int in_offset; /* >=1 if parsing operand of offset. */
8000 int in_bracket; /* >=1 if parsing operand in brackets. */
8001 const reg_entry *reg; /* Last register reference found. */
8002 char *disp; /* Displacement string being built. */
8003 char *next_operand; /* Resume point when splitting operands. */
8006 static struct intel_parser_s intel_parser;
8008 /* Token structure for parsing intel syntax. */
8011 int code; /* Token code. */
8012 const reg_entry *reg; /* Register entry for register tokens. */
8013 char *str; /* String representation. */
8016 static struct intel_token cur_token, prev_token;
8018 /* Token codes for the intel parser. Since T_SHORT is already used
8019 by COFF, undefine it first to prevent a warning. */
8038 /* Prototypes for intel parser functions. */
8039 static int intel_match_token (int);
8040 static void intel_putback_token (void);
8041 static void intel_get_token (void);
8042 static int intel_expr (void);
8043 static int intel_e04 (void);
8044 static int intel_e05 (void);
8045 static int intel_e06 (void);
8046 static int intel_e09 (void);
8047 static int intel_e10 (void);
8048 static int intel_e11 (void);
8051 i386_intel_operand (char *operand_string, int got_a_float)
8056 p = intel_parser.op_string = xstrdup (operand_string);
8057 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8061 /* Initialize token holders. */
8062 cur_token.code = prev_token.code = T_NIL;
8063 cur_token.reg = prev_token.reg = NULL;
8064 cur_token.str = prev_token.str = NULL;
8066 /* Initialize parser structure. */
8067 intel_parser.got_a_float = got_a_float;
8068 intel_parser.op_modifier = 0;
8069 intel_parser.is_mem = 0;
8070 intel_parser.in_offset = 0;
8071 intel_parser.in_bracket = 0;
8072 intel_parser.reg = NULL;
8073 intel_parser.disp[0] = '\0';
8074 intel_parser.next_operand = NULL;
8076 /* Read the first token and start the parser. */
8078 ret = intel_expr ();
8083 if (cur_token.code != T_NIL)
8085 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8086 current_templates->start->name, cur_token.str);
8089 /* If we found a memory reference, hand it over to i386_displacement
8090 to fill in the rest of the operand fields. */
8091 else if (intel_parser.is_mem)
8093 if ((i.mem_operands == 1
8094 && !current_templates->start->opcode_modifier.isstring)
8095 || i.mem_operands == 2)
8097 as_bad (_("too many memory references for '%s'"),
8098 current_templates->start->name);
8103 char *s = intel_parser.disp;
8104 i.types[this_operand].bitfield.mem = 1;
8107 if (!quiet_warnings && intel_parser.is_mem < 0)
8108 /* See the comments in intel_bracket_expr. */
8109 as_warn (_("Treating `%s' as memory reference"), operand_string);
8111 /* Add the displacement expression. */
8113 ret = i386_displacement (s, s + strlen (s));
8116 /* Swap base and index in 16-bit memory operands like
8117 [si+bx]. Since i386_index_check is also used in AT&T
8118 mode we have to do that here. */
8121 && i.base_reg->reg_type.bitfield.reg16
8122 && i.index_reg->reg_type.bitfield.reg16
8123 && i.base_reg->reg_num >= 6
8124 && i.index_reg->reg_num < 6)
8126 const reg_entry *base = i.index_reg;
8128 i.index_reg = i.base_reg;
8131 ret = i386_index_check (operand_string);
8136 /* Constant and OFFSET expressions are handled by i386_immediate. */
8137 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8138 || intel_parser.reg == NULL)
8140 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8142 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8143 as_warn (_("Segment override ignored"));
8144 i.seg[i.mem_operands] = NULL;
8146 ret = i386_immediate (intel_parser.disp);
8149 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8151 if (!ret || !intel_parser.next_operand)
8153 intel_parser.op_string = intel_parser.next_operand;
8154 this_operand = i.operands++;
8155 i.types[this_operand].bitfield.unspecified = 1;
8159 free (intel_parser.disp);
8164 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8168 expr' cmpOp e04 expr'
8173 /* XXX Implement the comparison operators. */
8174 return intel_e04 ();
8191 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8192 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8194 if (cur_token.code == '+')
8196 else if (cur_token.code == '-')
8197 nregs = NUM_ADDRESS_REGS;
8201 strcat (intel_parser.disp, cur_token.str);
8202 intel_match_token (cur_token.code);
8213 int nregs = ~NUM_ADDRESS_REGS;
8220 if (cur_token.code == '&'
8221 || cur_token.code == '|'
8222 || cur_token.code == '^')
8226 str[0] = cur_token.code;
8228 strcat (intel_parser.disp, str);
8233 intel_match_token (cur_token.code);
8238 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8239 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8250 int nregs = ~NUM_ADDRESS_REGS;
8257 if (cur_token.code == '*'
8258 || cur_token.code == '/'
8259 || cur_token.code == '%')
8263 str[0] = cur_token.code;
8265 strcat (intel_parser.disp, str);
8267 else if (cur_token.code == T_SHL)
8268 strcat (intel_parser.disp, "<<");
8269 else if (cur_token.code == T_SHR)
8270 strcat (intel_parser.disp, ">>");
8274 intel_match_token (cur_token.code);
8279 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8280 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8298 int nregs = ~NUM_ADDRESS_REGS;
8303 /* Don't consume constants here. */
8304 if (cur_token.code == '+' || cur_token.code == '-')
8306 /* Need to look one token ahead - if the next token
8307 is a constant, the current token is its sign. */
8310 intel_match_token (cur_token.code);
8311 next_code = cur_token.code;
8312 intel_putback_token ();
8313 if (next_code == T_CONST)
8317 /* e09 OFFSET e09 */
8318 if (cur_token.code == T_OFFSET)
8321 ++intel_parser.in_offset;
8325 else if (cur_token.code == T_SHORT)
8326 intel_parser.op_modifier |= 1 << T_SHORT;
8329 else if (cur_token.code == '+')
8330 strcat (intel_parser.disp, "+");
8335 else if (cur_token.code == '-' || cur_token.code == '~')
8341 str[0] = cur_token.code;
8343 strcat (intel_parser.disp, str);
8350 intel_match_token (cur_token.code);
8358 /* e09' PTR e10 e09' */
8359 if (cur_token.code == T_PTR)
8363 if (prev_token.code == T_BYTE)
8365 suffix = BYTE_MNEM_SUFFIX;
8366 i.types[this_operand].bitfield.byte = 1;
8369 else if (prev_token.code == T_WORD)
8371 if ((current_templates->start->name[0] == 'l'
8372 && current_templates->start->name[2] == 's'
8373 && current_templates->start->name[3] == 0)
8374 || current_templates->start->base_opcode == 0x62 /* bound */)
8375 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8376 else if (intel_parser.got_a_float == 2) /* "fi..." */
8377 suffix = SHORT_MNEM_SUFFIX;
8379 suffix = WORD_MNEM_SUFFIX;
8380 i.types[this_operand].bitfield.word = 1;
8383 else if (prev_token.code == T_DWORD)
8385 if ((current_templates->start->name[0] == 'l'
8386 && current_templates->start->name[2] == 's'
8387 && current_templates->start->name[3] == 0)
8388 || current_templates->start->base_opcode == 0x62 /* bound */)
8389 suffix = WORD_MNEM_SUFFIX;
8390 else if (flag_code == CODE_16BIT
8391 && (current_templates->start->opcode_modifier.jump
8392 || current_templates->start->opcode_modifier.jumpdword))
8393 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8394 else if (intel_parser.got_a_float == 1) /* "f..." */
8395 suffix = SHORT_MNEM_SUFFIX;
8397 suffix = LONG_MNEM_SUFFIX;
8398 i.types[this_operand].bitfield.dword = 1;
8401 else if (prev_token.code == T_FWORD)
8403 if (current_templates->start->name[0] == 'l'
8404 && current_templates->start->name[2] == 's'
8405 && current_templates->start->name[3] == 0)
8406 suffix = LONG_MNEM_SUFFIX;
8407 else if (!intel_parser.got_a_float)
8409 if (flag_code == CODE_16BIT)
8410 add_prefix (DATA_PREFIX_OPCODE);
8411 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8414 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8415 i.types[this_operand].bitfield.fword = 1;
8418 else if (prev_token.code == T_QWORD)
8420 if (current_templates->start->base_opcode == 0x62 /* bound */
8421 || intel_parser.got_a_float == 1) /* "f..." */
8422 suffix = LONG_MNEM_SUFFIX;
8424 suffix = QWORD_MNEM_SUFFIX;
8425 i.types[this_operand].bitfield.qword = 1;
8428 else if (prev_token.code == T_TBYTE)
8430 if (intel_parser.got_a_float == 1)
8431 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8433 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8436 else if (prev_token.code == T_XMMWORD)
8438 suffix = XMMWORD_MNEM_SUFFIX;
8439 i.types[this_operand].bitfield.xmmword = 1;
8444 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8448 i.types[this_operand].bitfield.unspecified = 0;
8450 /* Operands for jump/call using 'ptr' notation denote absolute
8452 if (current_templates->start->opcode_modifier.jump
8453 || current_templates->start->opcode_modifier.jumpdword)
8454 i.types[this_operand].bitfield.jumpabsolute = 1;
8456 if (current_templates->start->base_opcode == 0x8d /* lea */)
8460 else if (i.suffix != suffix)
8462 as_bad (_("Conflicting operand modifiers"));
8468 /* e09' : e10 e09' */
8469 else if (cur_token.code == ':')
8471 if (prev_token.code != T_REG)
8473 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8474 segment/group identifier (which we don't have), using comma
8475 as the operand separator there is even less consistent, since
8476 there all branches only have a single operand. */
8477 if (this_operand != 0
8478 || intel_parser.in_offset
8479 || intel_parser.in_bracket
8480 || (!current_templates->start->opcode_modifier.jump
8481 && !current_templates->start->opcode_modifier.jumpdword
8482 && !current_templates->start->opcode_modifier.jumpintersegment
8483 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8484 return intel_match_token (T_NIL);
8485 /* Remember the start of the 2nd operand and terminate 1st
8487 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8488 another expression), but it gets at least the simplest case
8489 (a plain number or symbol on the left side) right. */
8490 intel_parser.next_operand = intel_parser.op_string;
8491 *--intel_parser.op_string = '\0';
8492 return intel_match_token (':');
8500 intel_match_token (cur_token.code);
8506 --intel_parser.in_offset;
8509 if (NUM_ADDRESS_REGS > nregs)
8511 as_bad (_("Invalid operand to `OFFSET'"));
8514 intel_parser.op_modifier |= 1 << T_OFFSET;
8517 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8518 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8523 intel_bracket_expr (void)
8525 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8526 const char *start = intel_parser.op_string;
8529 if (i.op[this_operand].regs)
8530 return intel_match_token (T_NIL);
8532 intel_match_token ('[');
8534 /* Mark as a memory operand only if it's not already known to be an
8535 offset expression. If it's an offset expression, we need to keep
8537 if (!intel_parser.in_offset)
8539 ++intel_parser.in_bracket;
8541 /* Operands for jump/call inside brackets denote absolute addresses. */
8542 if (current_templates->start->opcode_modifier.jump
8543 || current_templates->start->opcode_modifier.jumpdword)
8544 i.types[this_operand].bitfield.jumpabsolute = 1;
8546 /* Unfortunately gas always diverged from MASM in a respect that can't
8547 be easily fixed without risking to break code sequences likely to be
8548 encountered (the testsuite even check for this): MASM doesn't consider
8549 an expression inside brackets unconditionally as a memory reference.
8550 When that is e.g. a constant, an offset expression, or the sum of the
8551 two, this is still taken as a constant load. gas, however, always
8552 treated these as memory references. As a compromise, we'll try to make
8553 offset expressions inside brackets work the MASM way (since that's
8554 less likely to be found in real world code), but make constants alone
8555 continue to work the traditional gas way. In either case, issue a
8557 intel_parser.op_modifier &= ~was_offset;
8560 strcat (intel_parser.disp, "[");
8562 /* Add a '+' to the displacement string if necessary. */
8563 if (*intel_parser.disp != '\0'
8564 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8565 strcat (intel_parser.disp, "+");
8568 && (len = intel_parser.op_string - start - 1,
8569 intel_match_token (']')))
8571 /* Preserve brackets when the operand is an offset expression. */
8572 if (intel_parser.in_offset)
8573 strcat (intel_parser.disp, "]");
8576 --intel_parser.in_bracket;
8577 if (i.base_reg || i.index_reg)
8578 intel_parser.is_mem = 1;
8579 if (!intel_parser.is_mem)
8581 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8582 /* Defer the warning until all of the operand was parsed. */
8583 intel_parser.is_mem = -1;
8584 else if (!quiet_warnings)
8585 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8586 len, start, len, start);
8589 intel_parser.op_modifier |= was_offset;
8606 while (cur_token.code == '[')
8608 if (!intel_bracket_expr ())
8633 switch (cur_token.code)
8637 intel_match_token ('(');
8638 strcat (intel_parser.disp, "(");
8640 if (intel_expr () && intel_match_token (')'))
8642 strcat (intel_parser.disp, ")");
8649 return intel_bracket_expr ();
8654 strcat (intel_parser.disp, cur_token.str);
8655 intel_match_token (cur_token.code);
8657 /* Mark as a memory operand only if it's not already known to be an
8658 offset expression. */
8659 if (!intel_parser.in_offset)
8660 intel_parser.is_mem = 1;
8667 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8669 intel_match_token (T_REG);
8671 /* Check for segment change. */
8672 if (cur_token.code == ':')
8674 if (!reg->reg_type.bitfield.sreg2
8675 && !reg->reg_type.bitfield.sreg3)
8677 as_bad (_("`%s' is not a valid segment register"),
8681 else if (i.mem_operands >= 2)
8682 as_warn (_("Segment override ignored"));
8683 else if (i.seg[i.mem_operands])
8684 as_warn (_("Extra segment override ignored"));
8687 if (!intel_parser.in_offset)
8688 intel_parser.is_mem = 1;
8689 switch (reg->reg_num)
8692 i.seg[i.mem_operands] = &es;
8695 i.seg[i.mem_operands] = &cs;
8698 i.seg[i.mem_operands] = &ss;
8701 i.seg[i.mem_operands] = &ds;
8704 i.seg[i.mem_operands] = &fs;
8707 i.seg[i.mem_operands] = &gs;
8713 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8715 as_bad (_("cannot use `FLAT' here"));
8719 /* Not a segment register. Check for register scaling. */
8720 else if (cur_token.code == '*')
8722 if (!intel_parser.in_bracket)
8724 as_bad (_("Register scaling only allowed in memory operands"));
8728 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8729 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8730 else if (i.index_reg)
8731 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8733 /* What follows must be a valid scale. */
8734 intel_match_token ('*');
8736 i.types[this_operand].bitfield.baseindex = 1;
8738 /* Set the scale after setting the register (otherwise,
8739 i386_scale will complain) */
8740 if (cur_token.code == '+' || cur_token.code == '-')
8742 char *str, sign = cur_token.code;
8743 intel_match_token (cur_token.code);
8744 if (cur_token.code != T_CONST)
8746 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8750 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8751 strcpy (str + 1, cur_token.str);
8753 if (!i386_scale (str))
8757 else if (!i386_scale (cur_token.str))
8759 intel_match_token (cur_token.code);
8762 /* No scaling. If this is a memory operand, the register is either a
8763 base register (first occurrence) or an index register (second
8765 else if (intel_parser.in_bracket)
8770 else if (!i.index_reg)
8774 as_bad (_("Too many register references in memory operand"));
8778 i.types[this_operand].bitfield.baseindex = 1;
8781 /* It's neither base nor index. */
8782 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8784 i386_operand_type temp = reg->reg_type;
8785 temp.bitfield.baseindex = 0;
8786 i.types[this_operand] = operand_type_or (i.types[this_operand],
8788 i.types[this_operand].bitfield.unspecified = 0;
8789 i.op[this_operand].regs = reg;
8794 as_bad (_("Invalid use of register"));
8798 /* Since registers are not part of the displacement string (except
8799 when we're parsing offset operands), we may need to remove any
8800 preceding '+' from the displacement string. */
8801 if (*intel_parser.disp != '\0'
8802 && !intel_parser.in_offset)
8804 char *s = intel_parser.disp;
8805 s += strlen (s) - 1;
8828 intel_match_token (cur_token.code);
8830 if (cur_token.code == T_PTR)
8833 /* It must have been an identifier. */
8834 intel_putback_token ();
8835 cur_token.code = T_ID;
8841 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8845 /* The identifier represents a memory reference only if it's not
8846 preceded by an offset modifier and if it's not an equate. */
8847 symbolP = symbol_find(cur_token.str);
8848 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8849 intel_parser.is_mem = 1;
8857 char *save_str, sign = 0;
8859 /* Allow constants that start with `+' or `-'. */
8860 if (cur_token.code == '-' || cur_token.code == '+')
8862 sign = cur_token.code;
8863 intel_match_token (cur_token.code);
8864 if (cur_token.code != T_CONST)
8866 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8872 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8873 strcpy (save_str + !!sign, cur_token.str);
8877 /* Get the next token to check for register scaling. */
8878 intel_match_token (cur_token.code);
8880 /* Check if this constant is a scaling factor for an
8882 if (cur_token.code == '*')
8884 if (intel_match_token ('*') && cur_token.code == T_REG)
8886 const reg_entry *reg = cur_token.reg;
8888 if (!intel_parser.in_bracket)
8890 as_bad (_("Register scaling only allowed "
8891 "in memory operands"));
8895 /* Disallow things like [1*si].
8896 sp and esp are invalid as index. */
8897 if (reg->reg_type.bitfield.reg16)
8898 reg = i386_regtab + REGNAM_AX + 4;
8899 else if (i.index_reg)
8900 reg = i386_regtab + REGNAM_EAX + 4;
8902 /* The constant is followed by `* reg', so it must be
8905 i.types[this_operand].bitfield.baseindex = 1;
8907 /* Set the scale after setting the register (otherwise,
8908 i386_scale will complain) */
8909 if (!i386_scale (save_str))
8911 intel_match_token (T_REG);
8913 /* Since registers are not part of the displacement
8914 string, we may need to remove any preceding '+' from
8915 the displacement string. */
8916 if (*intel_parser.disp != '\0')
8918 char *s = intel_parser.disp;
8919 s += strlen (s) - 1;
8929 /* The constant was not used for register scaling. Since we have
8930 already consumed the token following `*' we now need to put it
8931 back in the stream. */
8932 intel_putback_token ();
8935 /* Add the constant to the displacement string. */
8936 strcat (intel_parser.disp, save_str);
8943 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8947 /* Match the given token against cur_token. If they match, read the next
8948 token from the operand string. */
8950 intel_match_token (int code)
8952 if (cur_token.code == code)
8959 as_bad (_("Unexpected token `%s'"), cur_token.str);
8964 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8966 intel_get_token (void)
8969 const reg_entry *reg;
8970 struct intel_token new_token;
8972 new_token.code = T_NIL;
8973 new_token.reg = NULL;
8974 new_token.str = NULL;
8976 /* Free the memory allocated to the previous token and move
8977 cur_token to prev_token. */
8979 free (prev_token.str);
8981 prev_token = cur_token;
8983 /* Skip whitespace. */
8984 while (is_space_char (*intel_parser.op_string))
8985 intel_parser.op_string++;
8987 /* Return an empty token if we find nothing else on the line. */
8988 if (*intel_parser.op_string == '\0')
8990 cur_token = new_token;
8994 /* The new token cannot be larger than the remainder of the operand
8996 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8997 new_token.str[0] = '\0';
8999 if (strchr ("0123456789", *intel_parser.op_string))
9001 char *p = new_token.str;
9002 char *q = intel_parser.op_string;
9003 new_token.code = T_CONST;
9005 /* Allow any kind of identifier char to encompass floating point and
9006 hexadecimal numbers. */
9007 while (is_identifier_char (*q))
9011 /* Recognize special symbol names [0-9][bf]. */
9012 if (strlen (intel_parser.op_string) == 2
9013 && (intel_parser.op_string[1] == 'b'
9014 || intel_parser.op_string[1] == 'f'))
9015 new_token.code = T_ID;
9018 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9020 size_t len = end_op - intel_parser.op_string;
9022 new_token.code = T_REG;
9023 new_token.reg = reg;
9025 memcpy (new_token.str, intel_parser.op_string, len);
9026 new_token.str[len] = '\0';
9029 else if (is_identifier_char (*intel_parser.op_string))
9031 char *p = new_token.str;
9032 char *q = intel_parser.op_string;
9034 /* A '.' or '$' followed by an identifier char is an identifier.
9035 Otherwise, it's operator '.' followed by an expression. */
9036 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9038 new_token.code = '.';
9039 new_token.str[0] = '.';
9040 new_token.str[1] = '\0';
9044 while (is_identifier_char (*q) || *q == '@')
9048 if (strcasecmp (new_token.str, "NOT") == 0)
9049 new_token.code = '~';
9051 else if (strcasecmp (new_token.str, "MOD") == 0)
9052 new_token.code = '%';
9054 else if (strcasecmp (new_token.str, "AND") == 0)
9055 new_token.code = '&';
9057 else if (strcasecmp (new_token.str, "OR") == 0)
9058 new_token.code = '|';
9060 else if (strcasecmp (new_token.str, "XOR") == 0)
9061 new_token.code = '^';
9063 else if (strcasecmp (new_token.str, "SHL") == 0)
9064 new_token.code = T_SHL;
9066 else if (strcasecmp (new_token.str, "SHR") == 0)
9067 new_token.code = T_SHR;
9069 else if (strcasecmp (new_token.str, "BYTE") == 0)
9070 new_token.code = T_BYTE;
9072 else if (strcasecmp (new_token.str, "WORD") == 0)
9073 new_token.code = T_WORD;
9075 else if (strcasecmp (new_token.str, "DWORD") == 0)
9076 new_token.code = T_DWORD;
9078 else if (strcasecmp (new_token.str, "FWORD") == 0)
9079 new_token.code = T_FWORD;
9081 else if (strcasecmp (new_token.str, "QWORD") == 0)
9082 new_token.code = T_QWORD;
9084 else if (strcasecmp (new_token.str, "TBYTE") == 0
9085 /* XXX remove (gcc still uses it) */
9086 || strcasecmp (new_token.str, "XWORD") == 0)
9087 new_token.code = T_TBYTE;
9089 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9090 || strcasecmp (new_token.str, "OWORD") == 0)
9091 new_token.code = T_XMMWORD;
9093 else if (strcasecmp (new_token.str, "PTR") == 0)
9094 new_token.code = T_PTR;
9096 else if (strcasecmp (new_token.str, "SHORT") == 0)
9097 new_token.code = T_SHORT;
9099 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9101 new_token.code = T_OFFSET;
9103 /* ??? This is not mentioned in the MASM grammar but gcc
9104 makes use of it with -mintel-syntax. OFFSET may be
9105 followed by FLAT: */
9106 if (strncasecmp (q, " FLAT:", 6) == 0)
9107 strcat (new_token.str, " FLAT:");
9111 new_token.code = T_ID;
9115 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9117 new_token.code = *intel_parser.op_string;
9118 new_token.str[0] = *intel_parser.op_string;
9119 new_token.str[1] = '\0';
9122 else if (strchr ("<>", *intel_parser.op_string)
9123 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9125 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9126 new_token.str[0] = *intel_parser.op_string;
9127 new_token.str[1] = *intel_parser.op_string;
9128 new_token.str[2] = '\0';
9132 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9134 intel_parser.op_string += strlen (new_token.str);
9135 cur_token = new_token;
9138 /* Put cur_token back into the token stream and make cur_token point to
9141 intel_putback_token (void)
9143 if (cur_token.code != T_NIL)
9145 intel_parser.op_string -= strlen (cur_token.str);
9146 free (cur_token.str);
9148 cur_token = prev_token;
9150 /* Forget prev_token. */
9151 prev_token.code = T_NIL;
9152 prev_token.reg = NULL;
9153 prev_token.str = NULL;
9157 tc_x86_parse_to_dw2regnum (expressionS *exp)
9159 int saved_naked_reg;
9160 char saved_register_dot;
9162 saved_naked_reg = allow_naked_reg;
9163 allow_naked_reg = 1;
9164 saved_register_dot = register_chars['.'];
9165 register_chars['.'] = '.';
9166 allow_pseudo_reg = 1;
9167 expression_and_evaluate (exp);
9168 allow_pseudo_reg = 0;
9169 register_chars['.'] = saved_register_dot;
9170 allow_naked_reg = saved_naked_reg;
9172 if (exp->X_op == O_register && exp->X_add_number >= 0)
9174 if ((addressT) exp->X_add_number < i386_regtab_size)
9176 exp->X_op = O_constant;
9177 exp->X_add_number = i386_regtab[exp->X_add_number]
9178 .dw2_regnum[flag_code >> 1];
9181 exp->X_op = O_illegal;
9186 tc_x86_frame_initial_instructions (void)
9188 static unsigned int sp_regno[2];
9190 if (!sp_regno[flag_code >> 1])
9192 char *saved_input = input_line_pointer;
9193 char sp[][4] = {"esp", "rsp"};
9196 input_line_pointer = sp[flag_code >> 1];
9197 tc_x86_parse_to_dw2regnum (&exp);
9198 assert (exp.X_op == O_constant);
9199 sp_regno[flag_code >> 1] = exp.X_add_number;
9200 input_line_pointer = saved_input;
9203 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9204 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9208 i386_elf_section_type (const char *str, size_t len)
9210 if (flag_code == CODE_64BIT
9211 && len == sizeof ("unwind") - 1
9212 && strncmp (str, "unwind", 6) == 0)
9213 return SHT_X86_64_UNWIND;
9220 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9224 expr.X_op = O_secrel;
9225 expr.X_add_symbol = symbol;
9226 expr.X_add_number = 0;
9227 emit_expr (&expr, size);
9231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9232 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9235 x86_64_section_letter (int letter, char **ptr_msg)
9237 if (flag_code == CODE_64BIT)
9240 return SHF_X86_64_LARGE;
9242 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9245 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9250 x86_64_section_word (char *str, size_t len)
9252 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9253 return SHF_X86_64_LARGE;
9259 handle_large_common (int small ATTRIBUTE_UNUSED)
9261 if (flag_code != CODE_64BIT)
9263 s_comm_internal (0, elf_common_parse);
9264 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9268 static segT lbss_section;
9269 asection *saved_com_section_ptr = elf_com_section_ptr;
9270 asection *saved_bss_section = bss_section;
9272 if (lbss_section == NULL)
9274 flagword applicable;
9276 subsegT subseg = now_subseg;
9278 /* The .lbss section is for local .largecomm symbols. */
9279 lbss_section = subseg_new (".lbss", 0);
9280 applicable = bfd_applicable_section_flags (stdoutput);
9281 bfd_set_section_flags (stdoutput, lbss_section,
9282 applicable & SEC_ALLOC);
9283 seg_info (lbss_section)->bss = 1;
9285 subseg_set (seg, subseg);
9288 elf_com_section_ptr = &_bfd_elf_large_com_section;
9289 bss_section = lbss_section;
9291 s_comm_internal (0, elf_common_parse);
9293 elf_com_section_ptr = saved_com_section_ptr;
9294 bss_section = saved_bss_section;
9297 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */