1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void swap_imm_operands PARAMS ((void));
93 static void optimize_imm PARAMS ((void));
94 static void optimize_disp PARAMS ((void));
95 static int match_template PARAMS ((void));
96 static int check_string PARAMS ((void));
97 static int process_suffix PARAMS ((void));
98 static int check_byte_reg PARAMS ((void));
99 static int check_long_reg PARAMS ((void));
100 static int check_qword_reg PARAMS ((void));
101 static int check_word_reg PARAMS ((void));
102 static int finalize_imm PARAMS ((void));
103 static int process_operands PARAMS ((void));
104 static const seg_entry *build_modrm_byte PARAMS ((void));
105 static void output_insn PARAMS ((void));
106 static void output_branch PARAMS ((void));
107 static void output_jump PARAMS ((void));
108 static void output_interseg_jump PARAMS ((void));
109 static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111 static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
114 static void s_bss PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED);
120 static const char *default_arch = DEFAULT_ARCH;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry *regs;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types[MAX_OPERANDS];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op[MAX_OPERANDS];
157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry *seg[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars = "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars = "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars[] = "#/";
229 const char line_separator_chars[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars[256];
242 static char register_chars[256];
243 static char operand_chars[256];
244 static char identifier_chars[256];
245 static char digit_chars[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack[32];
263 static char *save_stack_p;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates *current_templates;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions[2], im_expressions[2];
278 /* Current operand we are working on. */
279 static int this_operand;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code;
291 static unsigned int object_64bit;
292 static int use_rela_relocations = 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names[] =
302 /* 1 for intel syntax,
304 static int intel_syntax = 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg = 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size = '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code = 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings = 0;
321 static const char *cpu_arch_name = NULL;
322 static const char *cpu_sub_arch_name = NULL;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set = 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags = 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags = 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion = 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS *GOT_symbol;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch[] =
436 {"generic32", PROCESSOR_GENERIC32,
437 Cpu186|Cpu286|Cpu386},
438 {"generic64", PROCESSOR_GENERIC64,
439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
443 {"i186", PROCESSOR_UNKNOWN,
445 {"i286", PROCESSOR_UNKNOWN,
447 {"i386", PROCESSOR_GENERIC32,
448 Cpu186|Cpu286|Cpu386},
449 {"i486", PROCESSOR_I486,
450 Cpu186|Cpu286|Cpu386|Cpu486},
451 {"i586", PROCESSOR_PENTIUM,
452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
453 {"i686", PROCESSOR_PENTIUMPRO,
454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
455 {"pentium", PROCESSOR_PENTIUM,
456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
459 {"pentiumii", PROCESSOR_PENTIUMPRO,
460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
463 {"pentium4", PROCESSOR_PENTIUM4,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
472 {"yonah", PROCESSOR_CORE,
473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
475 {"core", PROCESSOR_CORE,
476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
478 {"merom", PROCESSOR_CORE2,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
480 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
481 {"core2", PROCESSOR_CORE2,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
483 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
486 {"k6_2", PROCESSOR_K6,
487 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
488 {"athlon", PROCESSOR_ATHLON,
489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
491 {"sledgehammer", PROCESSOR_K8,
492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"opteron", PROCESSOR_K8,
495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
496 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
498 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
499 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
500 {"amdfam10", PROCESSOR_AMDFAM10,
501 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
502 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
504 {".mmx", PROCESSOR_UNKNOWN,
506 {".sse", PROCESSOR_UNKNOWN,
507 CpuMMX|CpuMMX2|CpuSSE},
508 {".sse2", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
510 {".sse3", PROCESSOR_UNKNOWN,
511 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
512 {".ssse3", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
514 {".3dnow", PROCESSOR_UNKNOWN,
516 {".3dnowa", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
518 {".padlock", PROCESSOR_UNKNOWN,
520 {".pacifica", PROCESSOR_UNKNOWN,
522 {".svme", PROCESSOR_UNKNOWN,
524 {".sse4a", PROCESSOR_UNKNOWN,
525 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
526 {".abm", PROCESSOR_UNKNOWN,
530 const pseudo_typeS md_pseudo_table[] =
532 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes, 0},
535 {"align", s_align_ptwo, 0},
537 {"arch", set_cpu_arch, 0},
541 {"ffloat", float_cons, 'f'},
542 {"dfloat", float_cons, 'd'},
543 {"tfloat", float_cons, 'x'},
545 {"slong", signed_cons, 4},
546 {"noopt", s_ignore, 0},
547 {"optim", s_ignore, 0},
548 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
549 {"code16", set_code_flag, CODE_16BIT},
550 {"code32", set_code_flag, CODE_32BIT},
551 {"code64", set_code_flag, CODE_64BIT},
552 {"intel_syntax", set_intel_syntax, 1},
553 {"att_syntax", set_intel_syntax, 0},
554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common, 0},
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
558 {"loc", dwarf2_directive_loc, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
562 {"secrel32", pe_directive_secrel, 0},
567 /* For interface with expression (). */
568 extern char *input_line_pointer;
570 /* Hash table for instruction mnemonic lookup. */
571 static struct hash_control *op_hash;
573 /* Hash table for register lookup. */
574 static struct hash_control *reg_hash;
577 i386_align_code (fragP, count)
581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
584 static const char f32_1[] =
586 static const char f32_2[] =
587 {0x66,0x90}; /* xchg %ax,%ax */
588 static const char f32_3[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5[] =
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8[] =
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
623 static const char f16_3[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
625 static const char f16_4[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5[] =
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt[] = {
640 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
641 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
643 static const char *const f16_patt[] = {
644 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
645 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
648 static const char alt_3[] =
650 /* nopl 0(%[re]ax) */
651 static const char alt_4[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13[] =
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15[] =
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
728 static const char alt_short_13[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
733 static const char alt_short_14[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt[] = {
742 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
743 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
744 alt_short_14, alt_short_15
746 static const char *const alt_long_patt[] = {
747 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
748 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
749 alt_long_14, alt_long_15
752 if (count <= 0 || count > 15)
755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
772 if (flag_code == CODE_16BIT)
774 memcpy (fragP->fr_literal + fragP->fr_fix,
775 f16_patt[count - 1], count);
777 /* Adjust jump offset. */
778 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
780 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
783 int nnops = (count + 3) / 4;
784 int len = count / nnops;
785 int remains = count - nnops * len;
788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
790 for (i = 0; i < remains; i++)
792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
793 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
796 for (; i < nnops; i++)
798 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
799 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
805 const char *const *patt = NULL;
807 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune)
812 case PROCESSOR_UNKNOWN:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags & Cpu686) != 0)
816 patt = alt_short_patt;
820 case PROCESSOR_CORE2:
821 patt = alt_long_patt;
823 case PROCESSOR_PENTIUMPRO:
824 case PROCESSOR_PENTIUM4:
825 case PROCESSOR_NOCONA:
828 case PROCESSOR_ATHLON:
830 case PROCESSOR_GENERIC64:
831 case PROCESSOR_AMDFAM10:
832 patt = alt_short_patt;
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_GENERIC32:
843 switch (cpu_arch_tune)
845 case PROCESSOR_UNKNOWN:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
852 case PROCESSOR_PENTIUM:
853 case PROCESSOR_PENTIUMPRO:
854 case PROCESSOR_PENTIUM4:
855 case PROCESSOR_NOCONA:
858 case PROCESSOR_ATHLON:
860 case PROCESSOR_AMDFAM10:
861 case PROCESSOR_GENERIC32:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
864 if ((cpu_arch_isa_flags & Cpu686) != 0)
865 patt = alt_short_patt;
869 case PROCESSOR_CORE2:
870 if ((cpu_arch_isa_flags & Cpu686) != 0)
871 patt = alt_long_patt;
875 case PROCESSOR_GENERIC64:
876 patt = alt_short_patt;
881 memcpy (fragP->fr_literal + fragP->fr_fix,
882 patt[count - 1], count);
884 fragP->fr_var = count;
887 static INLINE unsigned int
888 mode_from_disp_size (t)
891 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
895 fits_in_signed_byte (num)
898 return (num >= -128) && (num <= 127);
902 fits_in_unsigned_byte (num)
905 return (num & 0xff) == num;
909 fits_in_unsigned_word (num)
912 return (num & 0xffff) == num;
916 fits_in_signed_word (num)
919 return (-32768 <= num) && (num <= 32767);
923 fits_in_signed_long (num)
924 offsetT num ATTRIBUTE_UNUSED;
929 return (!(((offsetT) -1 << 31) & num)
930 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
932 } /* fits_in_signed_long() */
935 fits_in_unsigned_long (num)
936 offsetT num ATTRIBUTE_UNUSED;
941 return (num & (((offsetT) 2 << 31) - 1)) == num;
943 } /* fits_in_unsigned_long() */
946 smallest_imm_type (num)
949 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
951 /* This code is disabled on the 486 because all the Imm1 forms
952 in the opcode table are slower on the i486. They're the
953 versions with the implicitly specified single-position
954 displacement, which has another syntax if you really want to
957 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
959 return (fits_in_signed_byte (num)
960 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
961 : fits_in_unsigned_byte (num)
962 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
963 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
964 ? (Imm16 | Imm32 | Imm32S | Imm64)
965 : fits_in_signed_long (num)
966 ? (Imm32 | Imm32S | Imm64)
967 : fits_in_unsigned_long (num)
973 offset_in_range (val, size)
981 case 1: mask = ((addressT) 1 << 8) - 1; break;
982 case 2: mask = ((addressT) 1 << 16) - 1; break;
983 case 4: mask = ((addressT) 2 << 31) - 1; break;
985 case 8: mask = ((addressT) 2 << 63) - 1; break;
990 /* If BFD64, sign extend val. */
991 if (!use_rela_relocations)
992 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
993 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
995 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
997 char buf1[40], buf2[40];
999 sprint_value (buf1, val);
1000 sprint_value (buf2, val & mask);
1001 as_warn (_("%s shortened to %s"), buf1, buf2);
1006 /* Returns 0 if attempting to add a prefix where one from the same
1007 class already exists, 1 if non rep/repne added, 2 if rep/repne
1011 unsigned int prefix;
1016 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1017 && flag_code == CODE_64BIT)
1019 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1020 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1021 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1032 case CS_PREFIX_OPCODE:
1033 case DS_PREFIX_OPCODE:
1034 case ES_PREFIX_OPCODE:
1035 case FS_PREFIX_OPCODE:
1036 case GS_PREFIX_OPCODE:
1037 case SS_PREFIX_OPCODE:
1041 case REPNE_PREFIX_OPCODE:
1042 case REPE_PREFIX_OPCODE:
1045 case LOCK_PREFIX_OPCODE:
1053 case ADDR_PREFIX_OPCODE:
1057 case DATA_PREFIX_OPCODE:
1061 if (i.prefix[q] != 0)
1069 i.prefix[q] |= prefix;
1072 as_bad (_("same type of prefix used twice"));
1078 set_code_flag (value)
1082 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1083 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1084 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1086 as_bad (_("64bit mode not supported on this CPU."));
1088 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1090 as_bad (_("32bit mode not supported on this CPU."));
1092 stackop_size = '\0';
1096 set_16bit_gcc_code_flag (new_code_flag)
1099 flag_code = new_code_flag;
1100 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1101 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1102 stackop_size = LONG_MNEM_SUFFIX;
1106 set_intel_syntax (syntax_flag)
1109 /* Find out if register prefixing is specified. */
1110 int ask_naked_reg = 0;
1113 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1115 char *string = input_line_pointer;
1116 int e = get_symbol_end ();
1118 if (strcmp (string, "prefix") == 0)
1120 else if (strcmp (string, "noprefix") == 0)
1123 as_bad (_("bad argument to syntax directive."));
1124 *input_line_pointer = e;
1126 demand_empty_rest_of_line ();
1128 intel_syntax = syntax_flag;
1130 if (ask_naked_reg == 0)
1131 allow_naked_reg = (intel_syntax
1132 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1134 allow_naked_reg = (ask_naked_reg < 0);
1136 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1137 identifier_chars['$'] = intel_syntax ? '$' : 0;
1141 set_cpu_arch (dummy)
1142 int dummy ATTRIBUTE_UNUSED;
1146 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1148 char *string = input_line_pointer;
1149 int e = get_symbol_end ();
1152 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1154 if (strcmp (string, cpu_arch[i].name) == 0)
1158 cpu_arch_name = cpu_arch[i].name;
1159 cpu_sub_arch_name = NULL;
1160 cpu_arch_flags = (cpu_arch[i].flags
1161 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1162 cpu_arch_isa = cpu_arch[i].type;
1163 cpu_arch_isa_flags = cpu_arch[i].flags;
1164 if (!cpu_arch_tune_set)
1166 cpu_arch_tune = cpu_arch_isa;
1167 cpu_arch_tune_flags = cpu_arch_isa_flags;
1171 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1173 cpu_sub_arch_name = cpu_arch[i].name;
1174 cpu_arch_flags |= cpu_arch[i].flags;
1176 *input_line_pointer = e;
1177 demand_empty_rest_of_line ();
1181 if (i >= ARRAY_SIZE (cpu_arch))
1182 as_bad (_("no such architecture: `%s'"), string);
1184 *input_line_pointer = e;
1187 as_bad (_("missing cpu architecture"));
1189 no_cond_jump_promotion = 0;
1190 if (*input_line_pointer == ','
1191 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1193 char *string = ++input_line_pointer;
1194 int e = get_symbol_end ();
1196 if (strcmp (string, "nojumps") == 0)
1197 no_cond_jump_promotion = 1;
1198 else if (strcmp (string, "jumps") == 0)
1201 as_bad (_("no such architecture modifier: `%s'"), string);
1203 *input_line_pointer = e;
1206 demand_empty_rest_of_line ();
1212 if (!strcmp (default_arch, "x86_64"))
1213 return bfd_mach_x86_64;
1214 else if (!strcmp (default_arch, "i386"))
1215 return bfd_mach_i386_i386;
1217 as_fatal (_("Unknown architecture"));
1223 const char *hash_err;
1225 /* Initialize op_hash hash table. */
1226 op_hash = hash_new ();
1229 const template *optab;
1230 templates *core_optab;
1232 /* Setup for loop. */
1234 core_optab = (templates *) xmalloc (sizeof (templates));
1235 core_optab->start = optab;
1240 if (optab->name == NULL
1241 || strcmp (optab->name, (optab - 1)->name) != 0)
1243 /* different name --> ship out current template list;
1244 add to hash table; & begin anew. */
1245 core_optab->end = optab;
1246 hash_err = hash_insert (op_hash,
1251 as_fatal (_("Internal Error: Can't hash %s: %s"),
1255 if (optab->name == NULL)
1257 core_optab = (templates *) xmalloc (sizeof (templates));
1258 core_optab->start = optab;
1263 /* Initialize reg_hash hash table. */
1264 reg_hash = hash_new ();
1266 const reg_entry *regtab;
1268 for (regtab = i386_regtab;
1269 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1272 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1274 as_fatal (_("Internal Error: Can't hash %s: %s"),
1280 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1285 for (c = 0; c < 256; c++)
1290 mnemonic_chars[c] = c;
1291 register_chars[c] = c;
1292 operand_chars[c] = c;
1294 else if (ISLOWER (c))
1296 mnemonic_chars[c] = c;
1297 register_chars[c] = c;
1298 operand_chars[c] = c;
1300 else if (ISUPPER (c))
1302 mnemonic_chars[c] = TOLOWER (c);
1303 register_chars[c] = mnemonic_chars[c];
1304 operand_chars[c] = c;
1307 if (ISALPHA (c) || ISDIGIT (c))
1308 identifier_chars[c] = c;
1311 identifier_chars[c] = c;
1312 operand_chars[c] = c;
1317 identifier_chars['@'] = '@';
1320 identifier_chars['?'] = '?';
1321 operand_chars['?'] = '?';
1323 digit_chars['-'] = '-';
1324 mnemonic_chars['-'] = '-';
1325 identifier_chars['_'] = '_';
1326 identifier_chars['.'] = '.';
1328 for (p = operand_special_chars; *p != '\0'; p++)
1329 operand_chars[(unsigned char) *p] = *p;
1332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1335 record_alignment (text_section, 2);
1336 record_alignment (data_section, 2);
1337 record_alignment (bss_section, 2);
1341 if (flag_code == CODE_64BIT)
1343 x86_dwarf2_return_column = 16;
1344 x86_cie_data_alignment = -8;
1348 x86_dwarf2_return_column = 8;
1349 x86_cie_data_alignment = -4;
1354 i386_print_statistics (file)
1357 hash_print_statistics (file, "i386 opcode", op_hash);
1358 hash_print_statistics (file, "i386 register", reg_hash);
1363 /* Debugging routines for md_assemble. */
1364 static void pi PARAMS ((char *, i386_insn *));
1365 static void pte PARAMS ((template *));
1366 static void pt PARAMS ((unsigned int));
1367 static void pe PARAMS ((expressionS *));
1368 static void ps PARAMS ((symbolS *));
1377 fprintf (stdout, "%s: template ", line);
1379 fprintf (stdout, " address: base %s index %s scale %x\n",
1380 x->base_reg ? x->base_reg->reg_name : "none",
1381 x->index_reg ? x->index_reg->reg_name : "none",
1382 x->log2_scale_factor);
1383 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1384 x->rm.mode, x->rm.reg, x->rm.regmem);
1385 fprintf (stdout, " sib: base %x index %x scale %x\n",
1386 x->sib.base, x->sib.index, x->sib.scale);
1387 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1388 (x->rex & REX_MODE64) != 0,
1389 (x->rex & REX_EXTX) != 0,
1390 (x->rex & REX_EXTY) != 0,
1391 (x->rex & REX_EXTZ) != 0);
1392 for (i = 0; i < x->operands; i++)
1394 fprintf (stdout, " #%d: ", i + 1);
1396 fprintf (stdout, "\n");
1398 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1399 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1400 if (x->types[i] & Imm)
1402 if (x->types[i] & Disp)
1403 pe (x->op[i].disps);
1412 fprintf (stdout, " %d operands ", t->operands);
1413 fprintf (stdout, "opcode %x ", t->base_opcode);
1414 if (t->extension_opcode != None)
1415 fprintf (stdout, "ext %x ", t->extension_opcode);
1416 if (t->opcode_modifier & D)
1417 fprintf (stdout, "D");
1418 if (t->opcode_modifier & W)
1419 fprintf (stdout, "W");
1420 fprintf (stdout, "\n");
1421 for (i = 0; i < t->operands; i++)
1423 fprintf (stdout, " #%d type ", i + 1);
1424 pt (t->operand_types[i]);
1425 fprintf (stdout, "\n");
1433 fprintf (stdout, " operation %d\n", e->X_op);
1434 fprintf (stdout, " add_number %ld (%lx)\n",
1435 (long) e->X_add_number, (long) e->X_add_number);
1436 if (e->X_add_symbol)
1438 fprintf (stdout, " add_symbol ");
1439 ps (e->X_add_symbol);
1440 fprintf (stdout, "\n");
1444 fprintf (stdout, " op_symbol ");
1445 ps (e->X_op_symbol);
1446 fprintf (stdout, "\n");
1454 fprintf (stdout, "%s type %s%s",
1456 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1457 segment_name (S_GET_SEGMENT (s)));
1460 static struct type_name
1465 const type_names[] =
1478 { BaseIndex, "BaseIndex" },
1482 { Disp32S, "d32s" },
1484 { InOutPortReg, "InOutPortReg" },
1485 { ShiftCount, "ShiftCount" },
1486 { Control, "control reg" },
1487 { Test, "test reg" },
1488 { Debug, "debug reg" },
1489 { FloatReg, "FReg" },
1490 { FloatAcc, "FAcc" },
1494 { JumpAbsolute, "Jump Absolute" },
1505 const struct type_name *ty;
1507 for (ty = type_names; ty->mask; ty++)
1509 fprintf (stdout, "%s, ", ty->tname);
1513 #endif /* DEBUG386 */
1515 static bfd_reloc_code_real_type
1516 reloc (unsigned int size,
1519 bfd_reloc_code_real_type other)
1521 if (other != NO_RELOC)
1523 reloc_howto_type *reloc;
1528 case BFD_RELOC_X86_64_GOT32:
1529 return BFD_RELOC_X86_64_GOT64;
1531 case BFD_RELOC_X86_64_PLTOFF64:
1532 return BFD_RELOC_X86_64_PLTOFF64;
1534 case BFD_RELOC_X86_64_GOTPC32:
1535 other = BFD_RELOC_X86_64_GOTPC64;
1537 case BFD_RELOC_X86_64_GOTPCREL:
1538 other = BFD_RELOC_X86_64_GOTPCREL64;
1540 case BFD_RELOC_X86_64_TPOFF32:
1541 other = BFD_RELOC_X86_64_TPOFF64;
1543 case BFD_RELOC_X86_64_DTPOFF32:
1544 other = BFD_RELOC_X86_64_DTPOFF64;
1550 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1551 if (size == 4 && flag_code != CODE_64BIT)
1554 reloc = bfd_reloc_type_lookup (stdoutput, other);
1556 as_bad (_("unknown relocation (%u)"), other);
1557 else if (size != bfd_get_reloc_size (reloc))
1558 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1559 bfd_get_reloc_size (reloc),
1561 else if (pcrel && !reloc->pc_relative)
1562 as_bad (_("non-pc-relative relocation for pc-relative field"));
1563 else if ((reloc->complain_on_overflow == complain_overflow_signed
1565 || (reloc->complain_on_overflow == complain_overflow_unsigned
1567 as_bad (_("relocated field and relocation type differ in signedness"));
1576 as_bad (_("there are no unsigned pc-relative relocations"));
1579 case 1: return BFD_RELOC_8_PCREL;
1580 case 2: return BFD_RELOC_16_PCREL;
1581 case 4: return BFD_RELOC_32_PCREL;
1582 case 8: return BFD_RELOC_64_PCREL;
1584 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1591 case 4: return BFD_RELOC_X86_64_32S;
1596 case 1: return BFD_RELOC_8;
1597 case 2: return BFD_RELOC_16;
1598 case 4: return BFD_RELOC_32;
1599 case 8: return BFD_RELOC_64;
1601 as_bad (_("cannot do %s %u byte relocation"),
1602 sign > 0 ? "signed" : "unsigned", size);
1606 return BFD_RELOC_NONE;
1609 /* Here we decide which fixups can be adjusted to make them relative to
1610 the beginning of the section instead of the symbol. Basically we need
1611 to make sure that the dynamic relocations are done correctly, so in
1612 some cases we force the original symbol to be used. */
1615 tc_i386_fix_adjustable (fixP)
1616 fixS *fixP ATTRIBUTE_UNUSED;
1618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1622 /* Don't adjust pc-relative references to merge sections in 64-bit
1624 if (use_rela_relocations
1625 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1629 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1630 and changed later by validate_fix. */
1631 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1632 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1635 /* adjust_reloc_syms doesn't know about the GOT. */
1636 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1637 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1638 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1639 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1647 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1648 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1652 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1653 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1654 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1656 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1658 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1661 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1662 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1663 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1669 static int intel_float_operand PARAMS ((const char *mnemonic));
1672 intel_float_operand (mnemonic)
1673 const char *mnemonic;
1675 /* Note that the value returned is meaningful only for opcodes with (memory)
1676 operands, hence the code here is free to improperly handle opcodes that
1677 have no operands (for better performance and smaller code). */
1679 if (mnemonic[0] != 'f')
1680 return 0; /* non-math */
1682 switch (mnemonic[1])
1684 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1685 the fs segment override prefix not currently handled because no
1686 call path can make opcodes without operands get here */
1688 return 2 /* integer op */;
1690 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1691 return 3; /* fldcw/fldenv */
1694 if (mnemonic[2] != 'o' /* fnop */)
1695 return 3; /* non-waiting control op */
1698 if (mnemonic[2] == 's')
1699 return 3; /* frstor/frstpm */
1702 if (mnemonic[2] == 'a')
1703 return 3; /* fsave */
1704 if (mnemonic[2] == 't')
1706 switch (mnemonic[3])
1708 case 'c': /* fstcw */
1709 case 'd': /* fstdw */
1710 case 'e': /* fstenv */
1711 case 's': /* fsts[gw] */
1717 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1718 return 0; /* fxsave/fxrstor are not really math ops */
1725 /* This is the guts of the machine-dependent assembler. LINE points to a
1726 machine dependent instruction. This function is supposed to emit
1727 the frags/bytes it assembles to. */
1734 char mnemonic[MAX_MNEM_SIZE];
1736 /* Initialize globals. */
1737 memset (&i, '\0', sizeof (i));
1738 for (j = 0; j < MAX_OPERANDS; j++)
1739 i.reloc[j] = NO_RELOC;
1740 memset (disp_expressions, '\0', sizeof (disp_expressions));
1741 memset (im_expressions, '\0', sizeof (im_expressions));
1742 save_stack_p = save_stack;
1744 /* First parse an instruction mnemonic & call i386_operand for the operands.
1745 We assume that the scrubber has arranged it so that line[0] is the valid
1746 start of a (possibly prefixed) mnemonic. */
1748 line = parse_insn (line, mnemonic);
1752 line = parse_operands (line, mnemonic);
1756 /* The order of the immediates should be reversed
1757 for 2 immediates extrq and insertq instructions */
1758 if ((i.imm_operands == 2) &&
1759 ((strcmp (mnemonic, "extrq") == 0)
1760 || (strcmp (mnemonic, "insertq") == 0)))
1762 swap_imm_operands ();
1763 /* "extrq" and insertq" are the only two instructions whose operands
1764 have to be reversed even though they have two immediate operands.
1770 /* Now we've parsed the mnemonic into a set of templates, and have the
1771 operands at hand. */
1773 /* All intel opcodes have reversed operands except for "bound" and
1774 "enter". We also don't reverse intersegment "jmp" and "call"
1775 instructions with 2 immediate operands so that the immediate segment
1776 precedes the offset, as it does when in AT&T mode. */
1777 if (intel_syntax && i.operands > 1
1778 && (strcmp (mnemonic, "bound") != 0)
1779 && (strcmp (mnemonic, "invlpga") != 0)
1780 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1786 /* Don't optimize displacement for movabs since it only takes 64bit
1789 && (flag_code != CODE_64BIT
1790 || strcmp (mnemonic, "movabs") != 0))
1793 /* Next, we find a template that matches the given insn,
1794 making sure the overlap of the given operands types is consistent
1795 with the template operand types. */
1797 if (!match_template ())
1802 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1804 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1805 i.tm.base_opcode ^= FloatR;
1807 /* Zap movzx and movsx suffix. The suffix may have been set from
1808 "word ptr" or "byte ptr" on the source operand, but we'll use
1809 the suffix later to choose the destination register. */
1810 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1812 if (i.reg_operands < 2
1814 && (~i.tm.opcode_modifier
1821 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1827 if (i.tm.opcode_modifier & FWait)
1828 if (!add_prefix (FWAIT_OPCODE))
1831 /* Check string instruction segment overrides. */
1832 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1834 if (!check_string ())
1838 if (!process_suffix ())
1841 /* Make still unresolved immediate matches conform to size of immediate
1842 given in i.suffix. */
1843 if (!finalize_imm ())
1846 if (i.types[0] & Imm1)
1847 i.imm_operands = 0; /* kludge for shift insns. */
1848 if (i.types[0] & ImplicitRegister)
1850 if (i.types[1] & ImplicitRegister)
1852 if (i.types[2] & ImplicitRegister)
1855 if (i.tm.opcode_modifier & ImmExt)
1859 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1861 /* Streaming SIMD extensions 3 Instructions have the fixed
1862 operands with an opcode suffix which is coded in the same
1863 place as an 8-bit immediate field would be. Here we check
1864 those operands and remove them afterwards. */
1867 for (x = 0; x < i.operands; x++)
1868 if (i.op[x].regs->reg_num != x)
1869 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1870 i.op[x].regs->reg_name, x + 1, i.tm.name);
1874 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1875 opcode suffix which is coded in the same place as an 8-bit
1876 immediate field would be. Here we fake an 8-bit immediate
1877 operand from the opcode suffix stored in tm.extension_opcode. */
1879 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1881 exp = &im_expressions[i.imm_operands++];
1882 i.op[i.operands].imms = exp;
1883 i.types[i.operands++] = Imm8;
1884 exp->X_op = O_constant;
1885 exp->X_add_number = i.tm.extension_opcode;
1886 i.tm.extension_opcode = None;
1889 /* For insns with operands there are more diddles to do to the opcode. */
1892 if (!process_operands ())
1895 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1897 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1898 as_warn (_("translating to `%sp'"), i.tm.name);
1901 /* Handle conversion of 'int $3' --> special int3 insn. */
1902 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1904 i.tm.base_opcode = INT3_OPCODE;
1908 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1909 && i.op[0].disps->X_op == O_constant)
1911 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1912 the absolute address given by the constant. Since ix86 jumps and
1913 calls are pc relative, we need to generate a reloc. */
1914 i.op[0].disps->X_add_symbol = &abs_symbol;
1915 i.op[0].disps->X_op = O_symbol;
1918 if ((i.tm.opcode_modifier & Rex64) != 0)
1919 i.rex |= REX_MODE64;
1921 /* For 8 bit registers we need an empty rex prefix. Also if the
1922 instruction already has a prefix, we need to convert old
1923 registers to new ones. */
1925 if (((i.types[0] & Reg8) != 0
1926 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1927 || ((i.types[1] & Reg8) != 0
1928 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1929 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1934 i.rex |= REX_OPCODE;
1935 for (x = 0; x < 2; x++)
1937 /* Look for 8 bit operand that uses old registers. */
1938 if ((i.types[x] & Reg8) != 0
1939 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1941 /* In case it is "hi" register, give up. */
1942 if (i.op[x].regs->reg_num > 3)
1943 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1944 i.op[x].regs->reg_name);
1946 /* Otherwise it is equivalent to the extended register.
1947 Since the encoding doesn't change this is merely
1948 cosmetic cleanup for debug output. */
1950 i.op[x].regs = i.op[x].regs + 8;
1956 add_prefix (REX_OPCODE | i.rex);
1958 /* We are ready to output the insn. */
1963 parse_insn (line, mnemonic)
1968 char *token_start = l;
1973 /* Non-zero if we found a prefix only acceptable with string insns. */
1974 const char *expecting_string_instruction = NULL;
1979 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1982 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1984 as_bad (_("no such instruction: `%s'"), token_start);
1989 if (!is_space_char (*l)
1990 && *l != END_OF_INSN
1992 || (*l != PREFIX_SEPARATOR
1995 as_bad (_("invalid character %s in mnemonic"),
1996 output_invalid (*l));
1999 if (token_start == l)
2001 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2002 as_bad (_("expecting prefix; got nothing"));
2004 as_bad (_("expecting mnemonic; got nothing"));
2008 /* Look up instruction (or prefix) via hash table. */
2009 current_templates = hash_find (op_hash, mnemonic);
2011 if (*l != END_OF_INSN
2012 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2013 && current_templates
2014 && (current_templates->start->opcode_modifier & IsPrefix))
2016 if (current_templates->start->cpu_flags
2017 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2019 as_bad ((flag_code != CODE_64BIT
2020 ? _("`%s' is only supported in 64-bit mode")
2021 : _("`%s' is not supported in 64-bit mode")),
2022 current_templates->start->name);
2025 /* If we are in 16-bit mode, do not allow addr16 or data16.
2026 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2027 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2028 && flag_code != CODE_64BIT
2029 && (((current_templates->start->opcode_modifier & Size32) != 0)
2030 ^ (flag_code == CODE_16BIT)))
2032 as_bad (_("redundant %s prefix"),
2033 current_templates->start->name);
2036 /* Add prefix, checking for repeated prefixes. */
2037 switch (add_prefix (current_templates->start->base_opcode))
2042 expecting_string_instruction = current_templates->start->name;
2045 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2052 if (!current_templates)
2054 /* See if we can get a match by trimming off a suffix. */
2057 case WORD_MNEM_SUFFIX:
2058 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2059 i.suffix = SHORT_MNEM_SUFFIX;
2061 case BYTE_MNEM_SUFFIX:
2062 case QWORD_MNEM_SUFFIX:
2063 i.suffix = mnem_p[-1];
2065 current_templates = hash_find (op_hash, mnemonic);
2067 case SHORT_MNEM_SUFFIX:
2068 case LONG_MNEM_SUFFIX:
2071 i.suffix = mnem_p[-1];
2073 current_templates = hash_find (op_hash, mnemonic);
2081 if (intel_float_operand (mnemonic) == 1)
2082 i.suffix = SHORT_MNEM_SUFFIX;
2084 i.suffix = LONG_MNEM_SUFFIX;
2086 current_templates = hash_find (op_hash, mnemonic);
2090 if (!current_templates)
2092 as_bad (_("no such instruction: `%s'"), token_start);
2097 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2099 /* Check for a branch hint. We allow ",pt" and ",pn" for
2100 predict taken and predict not taken respectively.
2101 I'm not sure that branch hints actually do anything on loop
2102 and jcxz insns (JumpByte) for current Pentium4 chips. They
2103 may work in the future and it doesn't hurt to accept them
2105 if (l[0] == ',' && l[1] == 'p')
2109 if (!add_prefix (DS_PREFIX_OPCODE))
2113 else if (l[2] == 'n')
2115 if (!add_prefix (CS_PREFIX_OPCODE))
2121 /* Any other comma loses. */
2124 as_bad (_("invalid character %s in mnemonic"),
2125 output_invalid (*l));
2129 /* Check if instruction is supported on specified architecture. */
2131 for (t = current_templates->start; t < current_templates->end; ++t)
2133 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2134 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2136 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2139 if (!(supported & 2))
2141 as_bad (flag_code == CODE_64BIT
2142 ? _("`%s' is not supported in 64-bit mode")
2143 : _("`%s' is only supported in 64-bit mode"),
2144 current_templates->start->name);
2147 if (!(supported & 1))
2149 as_warn (_("`%s' is not supported on `%s%s'"),
2150 current_templates->start->name,
2152 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2154 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2156 as_warn (_("use .code16 to ensure correct addressing mode"));
2159 /* Check for rep/repne without a string instruction. */
2160 if (expecting_string_instruction)
2162 static templates override;
2164 for (t = current_templates->start; t < current_templates->end; ++t)
2165 if (t->opcode_modifier & IsString)
2167 if (t >= current_templates->end)
2169 as_bad (_("expecting string instruction after `%s'"),
2170 expecting_string_instruction);
2173 for (override.start = t; t < current_templates->end; ++t)
2174 if (!(t->opcode_modifier & IsString))
2177 current_templates = &override;
2184 parse_operands (l, mnemonic)
2186 const char *mnemonic;
2190 /* 1 if operand is pending after ','. */
2191 unsigned int expecting_operand = 0;
2193 /* Non-zero if operand parens not balanced. */
2194 unsigned int paren_not_balanced;
2196 while (*l != END_OF_INSN)
2198 /* Skip optional white space before operand. */
2199 if (is_space_char (*l))
2201 if (!is_operand_char (*l) && *l != END_OF_INSN)
2203 as_bad (_("invalid character %s before operand %d"),
2204 output_invalid (*l),
2208 token_start = l; /* after white space */
2209 paren_not_balanced = 0;
2210 while (paren_not_balanced || *l != ',')
2212 if (*l == END_OF_INSN)
2214 if (paren_not_balanced)
2217 as_bad (_("unbalanced parenthesis in operand %d."),
2220 as_bad (_("unbalanced brackets in operand %d."),
2225 break; /* we are done */
2227 else if (!is_operand_char (*l) && !is_space_char (*l))
2229 as_bad (_("invalid character %s in operand %d"),
2230 output_invalid (*l),
2237 ++paren_not_balanced;
2239 --paren_not_balanced;
2244 ++paren_not_balanced;
2246 --paren_not_balanced;
2250 if (l != token_start)
2251 { /* Yes, we've read in another operand. */
2252 unsigned int operand_ok;
2253 this_operand = i.operands++;
2254 if (i.operands > MAX_OPERANDS)
2256 as_bad (_("spurious operands; (%d operands/instruction max)"),
2260 /* Now parse operand adding info to 'i' as we go along. */
2261 END_STRING_AND_SAVE (l);
2265 i386_intel_operand (token_start,
2266 intel_float_operand (mnemonic));
2268 operand_ok = i386_operand (token_start);
2270 RESTORE_END_STRING (l);
2276 if (expecting_operand)
2278 expecting_operand_after_comma:
2279 as_bad (_("expecting operand after ','; got nothing"));
2284 as_bad (_("expecting operand before ','; got nothing"));
2289 /* Now *l must be either ',' or END_OF_INSN. */
2292 if (*++l == END_OF_INSN)
2294 /* Just skip it, if it's \n complain. */
2295 goto expecting_operand_after_comma;
2297 expecting_operand = 1;
2304 swap_imm_operands ()
2306 union i386_op temp_op;
2307 unsigned int temp_type;
2308 enum bfd_reloc_code_real temp_reloc;
2312 temp_type = i.types[xchg2];
2313 i.types[xchg2] = i.types[xchg1];
2314 i.types[xchg1] = temp_type;
2315 temp_op = i.op[xchg2];
2316 i.op[xchg2] = i.op[xchg1];
2317 i.op[xchg1] = temp_op;
2318 temp_reloc = i.reloc[xchg2];
2319 i.reloc[xchg2] = i.reloc[xchg1];
2320 i.reloc[xchg1] = temp_reloc;
2327 union i386_op temp_op;
2328 unsigned int temp_type;
2329 enum bfd_reloc_code_real temp_reloc;
2333 if (i.operands == 4)
2334 /* There will be two exchanges in a 4 operand instruction.
2335 First exchange is the done inside this block.(1st and 4rth operand)
2336 The next exchange is done outside this block.(2nd and 3rd operand) */
2340 temp_type = i.types[xchg2];
2341 i.types[xchg2] = i.types[xchg1];
2342 i.types[xchg1] = temp_type;
2343 temp_op = i.op[xchg2];
2344 i.op[xchg2] = i.op[xchg1];
2345 i.op[xchg1] = temp_op;
2346 temp_reloc = i.reloc[xchg2];
2347 i.reloc[xchg2] = i.reloc[xchg1];
2348 i.reloc[xchg1] = temp_reloc;
2353 if (i.operands == 2)
2358 else if (i.operands == 3)
2363 temp_type = i.types[xchg2];
2364 i.types[xchg2] = i.types[xchg1];
2365 i.types[xchg1] = temp_type;
2366 temp_op = i.op[xchg2];
2367 i.op[xchg2] = i.op[xchg1];
2368 i.op[xchg1] = temp_op;
2369 temp_reloc = i.reloc[xchg2];
2370 i.reloc[xchg2] = i.reloc[xchg1];
2371 i.reloc[xchg1] = temp_reloc;
2373 if (i.mem_operands == 2)
2375 const seg_entry *temp_seg;
2376 temp_seg = i.seg[0];
2377 i.seg[0] = i.seg[1];
2378 i.seg[1] = temp_seg;
2382 /* Try to ensure constant immediates are represented in the smallest
2387 char guess_suffix = 0;
2391 guess_suffix = i.suffix;
2392 else if (i.reg_operands)
2394 /* Figure out a suffix from the last register operand specified.
2395 We can't do this properly yet, ie. excluding InOutPortReg,
2396 but the following works for instructions with immediates.
2397 In any case, we can't set i.suffix yet. */
2398 for (op = i.operands; --op >= 0;)
2399 if (i.types[op] & Reg)
2401 if (i.types[op] & Reg8)
2402 guess_suffix = BYTE_MNEM_SUFFIX;
2403 else if (i.types[op] & Reg16)
2404 guess_suffix = WORD_MNEM_SUFFIX;
2405 else if (i.types[op] & Reg32)
2406 guess_suffix = LONG_MNEM_SUFFIX;
2407 else if (i.types[op] & Reg64)
2408 guess_suffix = QWORD_MNEM_SUFFIX;
2412 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2413 guess_suffix = WORD_MNEM_SUFFIX;
2415 for (op = i.operands; --op >= 0;)
2416 if (i.types[op] & Imm)
2418 switch (i.op[op].imms->X_op)
2421 /* If a suffix is given, this operand may be shortened. */
2422 switch (guess_suffix)
2424 case LONG_MNEM_SUFFIX:
2425 i.types[op] |= Imm32 | Imm64;
2427 case WORD_MNEM_SUFFIX:
2428 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2430 case BYTE_MNEM_SUFFIX:
2431 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2435 /* If this operand is at most 16 bits, convert it
2436 to a signed 16 bit number before trying to see
2437 whether it will fit in an even smaller size.
2438 This allows a 16-bit operand such as $0xffe0 to
2439 be recognised as within Imm8S range. */
2440 if ((i.types[op] & Imm16)
2441 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2443 i.op[op].imms->X_add_number =
2444 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2446 if ((i.types[op] & Imm32)
2447 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2450 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2451 ^ ((offsetT) 1 << 31))
2452 - ((offsetT) 1 << 31));
2454 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2456 /* We must avoid matching of Imm32 templates when 64bit
2457 only immediate is available. */
2458 if (guess_suffix == QWORD_MNEM_SUFFIX)
2459 i.types[op] &= ~Imm32;
2466 /* Symbols and expressions. */
2468 /* Convert symbolic operand to proper sizes for matching, but don't
2469 prevent matching a set of insns that only supports sizes other
2470 than those matching the insn suffix. */
2472 unsigned int mask, allowed = 0;
2475 for (t = current_templates->start; t < current_templates->end; ++t)
2476 allowed |= t->operand_types[op];
2477 switch (guess_suffix)
2479 case QWORD_MNEM_SUFFIX:
2480 mask = Imm64 | Imm32S;
2482 case LONG_MNEM_SUFFIX:
2485 case WORD_MNEM_SUFFIX:
2488 case BYTE_MNEM_SUFFIX:
2496 i.types[op] &= mask;
2503 /* Try to use the smallest displacement type too. */
2509 for (op = i.operands; --op >= 0;)
2510 if (i.types[op] & Disp)
2512 if (i.op[op].disps->X_op == O_constant)
2514 offsetT disp = i.op[op].disps->X_add_number;
2516 if ((i.types[op] & Disp16)
2517 && (disp & ~(offsetT) 0xffff) == 0)
2519 /* If this operand is at most 16 bits, convert
2520 to a signed 16 bit number and don't use 64bit
2522 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2523 i.types[op] &= ~Disp64;
2525 if ((i.types[op] & Disp32)
2526 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2528 /* If this operand is at most 32 bits, convert
2529 to a signed 32 bit number and don't use 64bit
2531 disp &= (((offsetT) 2 << 31) - 1);
2532 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2533 i.types[op] &= ~Disp64;
2535 if (!disp && (i.types[op] & BaseIndex))
2537 i.types[op] &= ~Disp;
2541 else if (flag_code == CODE_64BIT)
2543 if (fits_in_signed_long (disp))
2545 i.types[op] &= ~Disp64;
2546 i.types[op] |= Disp32S;
2548 if (fits_in_unsigned_long (disp))
2549 i.types[op] |= Disp32;
2551 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2552 && fits_in_signed_byte (disp))
2553 i.types[op] |= Disp8;
2555 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2556 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2558 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2559 i.op[op].disps, 0, i.reloc[op]);
2560 i.types[op] &= ~Disp;
2563 /* We only support 64bit displacement on constants. */
2564 i.types[op] &= ~Disp64;
2571 /* Points to template once we've found it. */
2573 unsigned int overlap0, overlap1, overlap2, overlap3;
2574 unsigned int found_reverse_match;
2576 unsigned int operand_types [MAX_OPERANDS];
2577 int addr_prefix_disp;
2580 #if MAX_OPERANDS != 4
2581 # error "MAX_OPERANDS must be 4."
2584 #define MATCH(overlap, given, template) \
2585 ((overlap & ~JumpAbsolute) \
2586 && (((given) & (BaseIndex | JumpAbsolute)) \
2587 == ((overlap) & (BaseIndex | JumpAbsolute))))
2589 /* If given types r0 and r1 are registers they must be of the same type
2590 unless the expected operand type register overlap is null.
2591 Note that Acc in a template matches every size of reg. */
2592 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2593 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2594 || ((g0) & Reg) == ((g1) & Reg) \
2595 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2601 found_reverse_match = 0;
2602 for (j = 0; j < MAX_OPERANDS; j++)
2603 operand_types [j] = 0;
2604 addr_prefix_disp = -1;
2605 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2607 : (i.suffix == WORD_MNEM_SUFFIX
2609 : (i.suffix == SHORT_MNEM_SUFFIX
2611 : (i.suffix == LONG_MNEM_SUFFIX
2613 : (i.suffix == QWORD_MNEM_SUFFIX
2615 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2616 ? No_xSuf : 0))))));
2618 for (t = current_templates->start; t < current_templates->end; t++)
2620 addr_prefix_disp = -1;
2622 /* Must have right number of operands. */
2623 if (i.operands != t->operands)
2626 /* Check the suffix, except for some instructions in intel mode. */
2627 if ((t->opcode_modifier & suffix_check)
2629 && (t->opcode_modifier & IgnoreSize)))
2632 for (j = 0; j < MAX_OPERANDS; j++)
2633 operand_types [j] = t->operand_types [j];
2635 /* In general, don't allow 64-bit operands in 32-bit mode. */
2636 if (i.suffix == QWORD_MNEM_SUFFIX
2637 && flag_code != CODE_64BIT
2639 ? (!(t->opcode_modifier & IgnoreSize)
2640 && !intel_float_operand (t->name))
2641 : intel_float_operand (t->name) != 2)
2642 && (!(operand_types[0] & (RegMMX | RegXMM))
2643 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2644 && (t->base_opcode != 0x0fc7
2645 || t->extension_opcode != 1 /* cmpxchg8b */))
2648 /* Do not verify operands when there are none. */
2649 else if (!t->operands)
2651 if (t->cpu_flags & ~cpu_arch_flags)
2653 /* We've found a match; break out of loop. */
2657 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2658 into Disp32/Disp16/Disp32 operand. */
2659 if (i.prefix[ADDR_PREFIX] != 0)
2661 unsigned int DispOn = 0, DispOff = 0;
2679 for (j = 0; j < MAX_OPERANDS; j++)
2681 /* There should be only one Disp operand. */
2682 if ((operand_types[j] & DispOff))
2684 addr_prefix_disp = j;
2685 operand_types[j] |= DispOn;
2686 operand_types[j] &= ~DispOff;
2692 overlap0 = i.types[0] & operand_types[0];
2693 switch (t->operands)
2696 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2702 overlap1 = i.types[1] & operand_types[1];
2703 if (!MATCH (overlap0, i.types[0], operand_types[0])
2704 || !MATCH (overlap1, i.types[1], operand_types[1])
2705 /* monitor in SSE3 is a very special case. The first
2706 register and the second register may have different
2708 || !((t->base_opcode == 0x0f01
2709 && t->extension_opcode == 0xc8)
2710 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2712 overlap1, i.types[1],
2715 /* Check if other direction is valid ... */
2716 if ((t->opcode_modifier & (D | FloatD)) == 0)
2719 /* Try reversing direction of operands. */
2720 overlap0 = i.types[0] & operand_types[1];
2721 overlap1 = i.types[1] & operand_types[0];
2722 if (!MATCH (overlap0, i.types[0], operand_types[1])
2723 || !MATCH (overlap1, i.types[1], operand_types[0])
2724 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2726 overlap1, i.types[1],
2729 /* Does not match either direction. */
2732 /* found_reverse_match holds which of D or FloatDR
2734 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2738 /* Found a forward 2 operand match here. */
2739 switch (t->operands)
2742 overlap3 = i.types[3] & operand_types[3];
2744 overlap2 = i.types[2] & operand_types[2];
2748 switch (t->operands)
2751 if (!MATCH (overlap3, i.types[3], operand_types[3])
2752 || !CONSISTENT_REGISTER_MATCH (overlap2,
2760 /* Here we make use of the fact that there are no
2761 reverse match 3 operand instructions, and all 3
2762 operand instructions only need to be checked for
2763 register consistency between operands 2 and 3. */
2764 if (!MATCH (overlap2, i.types[2], operand_types[2])
2765 || !CONSISTENT_REGISTER_MATCH (overlap1,
2775 /* Found either forward/reverse 2, 3 or 4 operand match here:
2776 slip through to break. */
2778 if (t->cpu_flags & ~cpu_arch_flags)
2780 found_reverse_match = 0;
2783 /* We've found a match; break out of loop. */
2787 if (t == current_templates->end)
2789 /* We found no match. */
2790 as_bad (_("suffix or operands invalid for `%s'"),
2791 current_templates->start->name);
2795 if (!quiet_warnings)
2798 && ((i.types[0] & JumpAbsolute)
2799 != (operand_types[0] & JumpAbsolute)))
2801 as_warn (_("indirect %s without `*'"), t->name);
2804 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2805 == (IsPrefix | IgnoreSize))
2807 /* Warn them that a data or address size prefix doesn't
2808 affect assembly of the next line of code. */
2809 as_warn (_("stand-alone `%s' prefix"), t->name);
2813 /* Copy the template we found. */
2816 if (addr_prefix_disp != -1)
2817 i.tm.operand_types[addr_prefix_disp]
2818 = operand_types[addr_prefix_disp];
2820 if (found_reverse_match)
2822 /* If we found a reverse match we must alter the opcode
2823 direction bit. found_reverse_match holds bits to change
2824 (different for int & float insns). */
2826 i.tm.base_opcode ^= found_reverse_match;
2828 i.tm.operand_types[0] = operand_types[1];
2829 i.tm.operand_types[1] = operand_types[0];
2838 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2839 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2841 if (i.seg[0] != NULL && i.seg[0] != &es)
2843 as_bad (_("`%s' operand %d must use `%%es' segment"),
2848 /* There's only ever one segment override allowed per instruction.
2849 This instruction possibly has a legal segment override on the
2850 second operand, so copy the segment to where non-string
2851 instructions store it, allowing common code. */
2852 i.seg[0] = i.seg[1];
2854 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2856 if (i.seg[1] != NULL && i.seg[1] != &es)
2858 as_bad (_("`%s' operand %d must use `%%es' segment"),
2868 process_suffix (void)
2870 /* If matched instruction specifies an explicit instruction mnemonic
2872 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2874 if (i.tm.opcode_modifier & Size16)
2875 i.suffix = WORD_MNEM_SUFFIX;
2876 else if (i.tm.opcode_modifier & Size64)
2877 i.suffix = QWORD_MNEM_SUFFIX;
2879 i.suffix = LONG_MNEM_SUFFIX;
2881 else if (i.reg_operands)
2883 /* If there's no instruction mnemonic suffix we try to invent one
2884 based on register operands. */
2887 /* We take i.suffix from the last register operand specified,
2888 Destination register type is more significant than source
2892 for (op = i.operands; --op >= 0;)
2893 if ((i.types[op] & Reg)
2894 && !(i.tm.operand_types[op] & InOutPortReg))
2896 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2897 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2898 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2903 else if (i.suffix == BYTE_MNEM_SUFFIX)
2905 if (!check_byte_reg ())
2908 else if (i.suffix == LONG_MNEM_SUFFIX)
2910 if (!check_long_reg ())
2913 else if (i.suffix == QWORD_MNEM_SUFFIX)
2915 if (!check_qword_reg ())
2918 else if (i.suffix == WORD_MNEM_SUFFIX)
2920 if (!check_word_reg ())
2923 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2924 /* Do nothing if the instruction is going to ignore the prefix. */
2929 else if ((i.tm.opcode_modifier & DefaultSize)
2931 /* exclude fldenv/frstor/fsave/fstenv */
2932 && (i.tm.opcode_modifier & No_sSuf))
2934 i.suffix = stackop_size;
2936 else if (intel_syntax
2938 && ((i.tm.operand_types[0] & JumpAbsolute)
2939 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2940 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2941 && i.tm.extension_opcode <= 3)))
2946 if (!(i.tm.opcode_modifier & No_qSuf))
2948 i.suffix = QWORD_MNEM_SUFFIX;
2952 if (!(i.tm.opcode_modifier & No_lSuf))
2953 i.suffix = LONG_MNEM_SUFFIX;
2956 if (!(i.tm.opcode_modifier & No_wSuf))
2957 i.suffix = WORD_MNEM_SUFFIX;
2966 if (i.tm.opcode_modifier & W)
2968 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2974 unsigned int suffixes = (~i.tm.opcode_modifier
2982 if ((i.tm.opcode_modifier & W)
2983 || ((suffixes & (suffixes - 1))
2984 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2986 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2992 /* Change the opcode based on the operand size given by i.suffix;
2993 We don't need to change things for byte insns. */
2995 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2997 /* It's not a byte, select word/dword operation. */
2998 if (i.tm.opcode_modifier & W)
3000 if (i.tm.opcode_modifier & ShortForm)
3001 i.tm.base_opcode |= 8;
3003 i.tm.base_opcode |= 1;
3006 /* Now select between word & dword operations via the operand
3007 size prefix, except for instructions that will ignore this
3009 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3011 /* monitor in SSE3 is a very special case. The default size
3012 of AX is the size of mode. The address size override
3013 prefix will change the size of AX. */
3014 if (i.op->regs[0].reg_type &
3015 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3016 if (!add_prefix (ADDR_PREFIX_OPCODE))
3019 else if (i.suffix != QWORD_MNEM_SUFFIX
3020 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3021 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3022 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3023 || (flag_code == CODE_64BIT
3024 && (i.tm.opcode_modifier & JumpByte))))
3026 unsigned int prefix = DATA_PREFIX_OPCODE;
3028 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3029 prefix = ADDR_PREFIX_OPCODE;
3031 if (!add_prefix (prefix))
3035 /* Set mode64 for an operand. */
3036 if (i.suffix == QWORD_MNEM_SUFFIX
3037 && flag_code == CODE_64BIT
3038 && (i.tm.opcode_modifier & NoRex64) == 0)
3040 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3043 || i.types [0] != (Acc | Reg64)
3044 || i.types [1] != (Acc | Reg64)
3045 || strcmp (i.tm.name, "xchg") != 0)
3046 i.rex |= REX_MODE64;
3049 /* Size floating point instruction. */
3050 if (i.suffix == LONG_MNEM_SUFFIX)
3051 if (i.tm.opcode_modifier & FloatMF)
3052 i.tm.base_opcode ^= 4;
3059 check_byte_reg (void)
3063 for (op = i.operands; --op >= 0;)
3065 /* If this is an eight bit register, it's OK. If it's the 16 or
3066 32 bit version of an eight bit register, we will just use the
3067 low portion, and that's OK too. */
3068 if (i.types[op] & Reg8)
3071 /* movzx and movsx should not generate this warning. */
3073 && (i.tm.base_opcode == 0xfb7
3074 || i.tm.base_opcode == 0xfb6
3075 || i.tm.base_opcode == 0x63
3076 || i.tm.base_opcode == 0xfbe
3077 || i.tm.base_opcode == 0xfbf))
3080 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3082 /* Prohibit these changes in the 64bit mode, since the
3083 lowering is more complicated. */
3084 if (flag_code == CODE_64BIT
3085 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3087 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3088 i.op[op].regs->reg_name,
3092 #if REGISTER_WARNINGS
3094 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3095 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3096 (i.op[op].regs + (i.types[op] & Reg16
3097 ? REGNAM_AL - REGNAM_AX
3098 : REGNAM_AL - REGNAM_EAX))->reg_name,
3099 i.op[op].regs->reg_name,
3104 /* Any other register is bad. */
3105 if (i.types[op] & (Reg | RegMMX | RegXMM
3107 | Control | Debug | Test
3108 | FloatReg | FloatAcc))
3110 as_bad (_("`%%%s' not allowed with `%s%c'"),
3111 i.op[op].regs->reg_name,
3125 for (op = i.operands; --op >= 0;)
3126 /* Reject eight bit registers, except where the template requires
3127 them. (eg. movzb) */
3128 if ((i.types[op] & Reg8) != 0
3129 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3131 as_bad (_("`%%%s' not allowed with `%s%c'"),
3132 i.op[op].regs->reg_name,
3137 /* Warn if the e prefix on a general reg is missing. */
3138 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3139 && (i.types[op] & Reg16) != 0
3140 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3142 /* Prohibit these changes in the 64bit mode, since the
3143 lowering is more complicated. */
3144 if (flag_code == CODE_64BIT)
3146 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3147 i.op[op].regs->reg_name,
3151 #if REGISTER_WARNINGS
3153 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3154 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3155 i.op[op].regs->reg_name,
3159 /* Warn if the r prefix on a general reg is missing. */
3160 else if ((i.types[op] & Reg64) != 0
3161 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3163 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3164 i.op[op].regs->reg_name,
3176 for (op = i.operands; --op >= 0; )
3177 /* Reject eight bit registers, except where the template requires
3178 them. (eg. movzb) */
3179 if ((i.types[op] & Reg8) != 0
3180 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3182 as_bad (_("`%%%s' not allowed with `%s%c'"),
3183 i.op[op].regs->reg_name,
3188 /* Warn if the e prefix on a general reg is missing. */
3189 else if (((i.types[op] & Reg16) != 0
3190 || (i.types[op] & Reg32) != 0)
3191 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3193 /* Prohibit these changes in the 64bit mode, since the
3194 lowering is more complicated. */
3195 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3196 i.op[op].regs->reg_name,
3207 for (op = i.operands; --op >= 0;)
3208 /* Reject eight bit registers, except where the template requires
3209 them. (eg. movzb) */
3210 if ((i.types[op] & Reg8) != 0
3211 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3213 as_bad (_("`%%%s' not allowed with `%s%c'"),
3214 i.op[op].regs->reg_name,
3219 /* Warn if the e prefix on a general reg is present. */
3220 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3221 && (i.types[op] & Reg32) != 0
3222 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3224 /* Prohibit these changes in the 64bit mode, since the
3225 lowering is more complicated. */
3226 if (flag_code == CODE_64BIT)
3228 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3229 i.op[op].regs->reg_name,
3234 #if REGISTER_WARNINGS
3235 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3236 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3237 i.op[op].regs->reg_name,
3247 unsigned int overlap0, overlap1, overlap2;
3249 overlap0 = i.types[0] & i.tm.operand_types[0];
3250 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3251 && overlap0 != Imm8 && overlap0 != Imm8S
3252 && overlap0 != Imm16 && overlap0 != Imm32S
3253 && overlap0 != Imm32 && overlap0 != Imm64)
3257 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3259 : (i.suffix == WORD_MNEM_SUFFIX
3261 : (i.suffix == QWORD_MNEM_SUFFIX
3265 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3266 || overlap0 == (Imm16 | Imm32)
3267 || overlap0 == (Imm16 | Imm32S))
3269 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3272 if (overlap0 != Imm8 && overlap0 != Imm8S
3273 && overlap0 != Imm16 && overlap0 != Imm32S
3274 && overlap0 != Imm32 && overlap0 != Imm64)
3276 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3280 i.types[0] = overlap0;
3282 overlap1 = i.types[1] & i.tm.operand_types[1];
3283 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3284 && overlap1 != Imm8 && overlap1 != Imm8S
3285 && overlap1 != Imm16 && overlap1 != Imm32S
3286 && overlap1 != Imm32 && overlap1 != Imm64)
3290 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3292 : (i.suffix == WORD_MNEM_SUFFIX
3294 : (i.suffix == QWORD_MNEM_SUFFIX
3298 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3299 || overlap1 == (Imm16 | Imm32)
3300 || overlap1 == (Imm16 | Imm32S))
3302 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3305 if (overlap1 != Imm8 && overlap1 != Imm8S
3306 && overlap1 != Imm16 && overlap1 != Imm32S
3307 && overlap1 != Imm32 && overlap1 != Imm64)
3309 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3313 i.types[1] = overlap1;
3315 overlap2 = i.types[2] & i.tm.operand_types[2];
3316 assert ((overlap2 & Imm) == 0);
3317 i.types[2] = overlap2;
3325 /* Default segment register this instruction will use for memory
3326 accesses. 0 means unknown. This is only for optimizing out
3327 unnecessary segment overrides. */
3328 const seg_entry *default_seg = 0;
3330 /* The imul $imm, %reg instruction is converted into
3331 imul $imm, %reg, %reg, and the clr %reg instruction
3332 is converted into xor %reg, %reg. */
3333 if (i.tm.opcode_modifier & regKludge)
3335 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3336 /* Pretend we saw the extra register operand. */
3337 assert (i.op[first_reg_op + 1].regs == 0);
3338 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3339 i.types[first_reg_op + 1] = i.types[first_reg_op];
3343 if (i.tm.opcode_modifier & ShortForm)
3345 /* The register or float register operand is in operand 0 or 1. */
3346 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3347 /* Register goes in low 3 bits of opcode. */
3348 i.tm.base_opcode |= i.op[op].regs->reg_num;
3349 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3351 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3353 /* Warn about some common errors, but press on regardless.
3354 The first case can be generated by gcc (<= 2.8.1). */
3355 if (i.operands == 2)
3357 /* Reversed arguments on faddp, fsubp, etc. */
3358 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3359 i.op[1].regs->reg_name,
3360 i.op[0].regs->reg_name);
3364 /* Extraneous `l' suffix on fp insn. */
3365 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3366 i.op[0].regs->reg_name);
3370 else if (i.tm.opcode_modifier & Modrm)
3372 /* The opcode is completed (modulo i.tm.extension_opcode which
3373 must be put into the modrm byte). Now, we make the modrm and
3374 index base bytes based on all the info we've collected. */
3376 default_seg = build_modrm_byte ();
3378 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3380 if (i.tm.base_opcode == POP_SEG_SHORT
3381 && i.op[0].regs->reg_num == 1)
3383 as_bad (_("you can't `pop %%cs'"));
3386 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3387 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3390 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3394 else if ((i.tm.opcode_modifier & IsString) != 0)
3396 /* For the string instructions that allow a segment override
3397 on one of their operands, the default segment is ds. */
3401 if ((i.tm.base_opcode == 0x8d /* lea */
3402 || (i.tm.cpu_flags & CpuSVME))
3403 && i.seg[0] && !quiet_warnings)
3404 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3406 /* If a segment was explicitly specified, and the specified segment
3407 is not the default, use an opcode prefix to select it. If we
3408 never figured out what the default segment is, then default_seg
3409 will be zero at this point, and the specified segment prefix will
3411 if ((i.seg[0]) && (i.seg[0] != default_seg))
3413 if (!add_prefix (i.seg[0]->seg_prefix))
3419 static const seg_entry *
3422 const seg_entry *default_seg = 0;
3424 /* i.reg_operands MUST be the number of real register operands;
3425 implicit registers do not count. */
3426 if (i.reg_operands == 2)
3428 unsigned int source, dest;
3429 source = ((i.types[0]
3430 & (Reg | RegMMX | RegXMM
3432 | Control | Debug | Test))
3435 /* In 4 operands instructions with 2 immediate operands, the first
3436 two are immediate bytes and hence source operand will be in the
3437 next byte after the immediates */
3438 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
3442 /* One of the register operands will be encoded in the i.tm.reg
3443 field, the other in the combined i.tm.mode and i.tm.regmem
3444 fields. If no form of this instruction supports a memory
3445 destination operand, then we assume the source operand may
3446 sometimes be a memory operand and so we need to store the
3447 destination in the i.rm.reg field. */
3448 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3450 i.rm.reg = i.op[dest].regs->reg_num;
3451 i.rm.regmem = i.op[source].regs->reg_num;
3452 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3454 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3459 i.rm.reg = i.op[source].regs->reg_num;
3460 i.rm.regmem = i.op[dest].regs->reg_num;
3461 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3463 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3466 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3468 if (!((i.types[0] | i.types[1]) & Control))
3470 i.rex &= ~(REX_EXTX | REX_EXTZ);
3471 add_prefix (LOCK_PREFIX_OPCODE);
3475 { /* If it's not 2 reg operands... */
3478 unsigned int fake_zero_displacement = 0;
3479 unsigned int op = ((i.types[0] & AnyMem)
3481 : (i.types[1] & AnyMem) ? 1 : 2);
3485 if (i.base_reg == 0)
3488 if (!i.disp_operands)
3489 fake_zero_displacement = 1;
3490 if (i.index_reg == 0)
3492 /* Operand is just <disp> */
3493 if (flag_code == CODE_64BIT)
3495 /* 64bit mode overwrites the 32bit absolute
3496 addressing by RIP relative addressing and
3497 absolute addressing is encoded by one of the
3498 redundant SIB forms. */
3499 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3500 i.sib.base = NO_BASE_REGISTER;
3501 i.sib.index = NO_INDEX_REGISTER;
3502 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3503 ? Disp32S : Disp32);
3505 else if ((flag_code == CODE_16BIT)
3506 ^ (i.prefix[ADDR_PREFIX] != 0))
3508 i.rm.regmem = NO_BASE_REGISTER_16;
3509 i.types[op] = Disp16;
3513 i.rm.regmem = NO_BASE_REGISTER;
3514 i.types[op] = Disp32;
3517 else /* !i.base_reg && i.index_reg */
3519 i.sib.index = i.index_reg->reg_num;
3520 i.sib.base = NO_BASE_REGISTER;
3521 i.sib.scale = i.log2_scale_factor;
3522 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3523 i.types[op] &= ~Disp;
3524 if (flag_code != CODE_64BIT)
3525 i.types[op] |= Disp32; /* Must be 32 bit */
3527 i.types[op] |= Disp32S;
3528 if ((i.index_reg->reg_flags & RegRex) != 0)
3532 /* RIP addressing for 64bit mode. */
3533 else if (i.base_reg->reg_type == BaseIndex)
3535 i.rm.regmem = NO_BASE_REGISTER;
3536 i.types[op] &= ~ Disp;
3537 i.types[op] |= Disp32S;
3538 i.flags[op] |= Operand_PCrel;
3539 if (! i.disp_operands)
3540 fake_zero_displacement = 1;
3542 else if (i.base_reg->reg_type & Reg16)
3544 switch (i.base_reg->reg_num)
3547 if (i.index_reg == 0)
3549 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3550 i.rm.regmem = i.index_reg->reg_num - 6;
3554 if (i.index_reg == 0)
3557 if ((i.types[op] & Disp) == 0)
3559 /* fake (%bp) into 0(%bp) */
3560 i.types[op] |= Disp8;
3561 fake_zero_displacement = 1;
3564 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3565 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3567 default: /* (%si) -> 4 or (%di) -> 5 */
3568 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3570 i.rm.mode = mode_from_disp_size (i.types[op]);
3572 else /* i.base_reg and 32/64 bit mode */
3574 if (flag_code == CODE_64BIT
3575 && (i.types[op] & Disp))
3576 i.types[op] = ((i.types[op] & Disp8)
3577 | (i.prefix[ADDR_PREFIX] == 0
3578 ? Disp32S : Disp32));
3580 i.rm.regmem = i.base_reg->reg_num;
3581 if ((i.base_reg->reg_flags & RegRex) != 0)
3583 i.sib.base = i.base_reg->reg_num;
3584 /* x86-64 ignores REX prefix bit here to avoid decoder
3586 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3589 if (i.disp_operands == 0)
3591 fake_zero_displacement = 1;
3592 i.types[op] |= Disp8;
3595 else if (i.base_reg->reg_num == ESP_REG_NUM)
3599 i.sib.scale = i.log2_scale_factor;
3600 if (i.index_reg == 0)
3602 /* <disp>(%esp) becomes two byte modrm with no index
3603 register. We've already stored the code for esp
3604 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3605 Any base register besides %esp will not use the
3606 extra modrm byte. */
3607 i.sib.index = NO_INDEX_REGISTER;
3608 #if !SCALE1_WHEN_NO_INDEX
3609 /* Another case where we force the second modrm byte. */
3610 if (i.log2_scale_factor)
3611 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3616 i.sib.index = i.index_reg->reg_num;
3617 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3618 if ((i.index_reg->reg_flags & RegRex) != 0)
3623 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3624 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3627 i.rm.mode = mode_from_disp_size (i.types[op]);
3630 if (fake_zero_displacement)
3632 /* Fakes a zero displacement assuming that i.types[op]
3633 holds the correct displacement size. */
3636 assert (i.op[op].disps == 0);
3637 exp = &disp_expressions[i.disp_operands++];
3638 i.op[op].disps = exp;
3639 exp->X_op = O_constant;
3640 exp->X_add_number = 0;
3641 exp->X_add_symbol = (symbolS *) 0;
3642 exp->X_op_symbol = (symbolS *) 0;
3646 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3647 (if any) based on i.tm.extension_opcode. Again, we must be
3648 careful to make sure that segment/control/debug/test/MMX
3649 registers are coded into the i.rm.reg field. */
3654 & (Reg | RegMMX | RegXMM
3656 | Control | Debug | Test))
3659 & (Reg | RegMMX | RegXMM
3661 | Control | Debug | Test))
3664 /* If there is an extension opcode to put here, the register
3665 number must be put into the regmem field. */
3666 if (i.tm.extension_opcode != None)
3668 i.rm.regmem = i.op[op].regs->reg_num;
3669 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3674 i.rm.reg = i.op[op].regs->reg_num;
3675 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3679 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3680 must set it to 3 to indicate this is a register operand
3681 in the regmem field. */
3682 if (!i.mem_operands)
3686 /* Fill in i.rm.reg field with extension opcode (if any). */
3687 if (i.tm.extension_opcode != None)
3688 i.rm.reg = i.tm.extension_opcode;
3699 relax_substateT subtype;
3704 if (flag_code == CODE_16BIT)
3708 if (i.prefix[DATA_PREFIX] != 0)
3714 /* Pentium4 branch hints. */
3715 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3716 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3721 if (i.prefix[REX_PREFIX] != 0)
3727 if (i.prefixes != 0 && !intel_syntax)
3728 as_warn (_("skipping prefixes on this instruction"));
3730 /* It's always a symbol; End frag & setup for relax.
3731 Make sure there is enough room in this frag for the largest
3732 instruction we may generate in md_convert_frag. This is 2
3733 bytes for the opcode and room for the prefix and largest
3735 frag_grow (prefix + 2 + 4);
3736 /* Prefix and 1 opcode byte go in fr_fix. */
3737 p = frag_more (prefix + 1);
3738 if (i.prefix[DATA_PREFIX] != 0)
3739 *p++ = DATA_PREFIX_OPCODE;
3740 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3741 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3742 *p++ = i.prefix[SEG_PREFIX];
3743 if (i.prefix[REX_PREFIX] != 0)
3744 *p++ = i.prefix[REX_PREFIX];
3745 *p = i.tm.base_opcode;
3747 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3748 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3749 else if ((cpu_arch_flags & Cpu386) != 0)
3750 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3752 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3755 sym = i.op[0].disps->X_add_symbol;
3756 off = i.op[0].disps->X_add_number;
3758 if (i.op[0].disps->X_op != O_constant
3759 && i.op[0].disps->X_op != O_symbol)
3761 /* Handle complex expressions. */
3762 sym = make_expr_symbol (i.op[0].disps);
3766 /* 1 possible extra opcode + 4 byte displacement go in var part.
3767 Pass reloc in fr_var. */
3768 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3778 if (i.tm.opcode_modifier & JumpByte)
3780 /* This is a loop or jecxz type instruction. */
3782 if (i.prefix[ADDR_PREFIX] != 0)
3784 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3787 /* Pentium4 branch hints. */
3788 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3789 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3791 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3800 if (flag_code == CODE_16BIT)
3803 if (i.prefix[DATA_PREFIX] != 0)
3805 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3815 if (i.prefix[REX_PREFIX] != 0)
3817 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3821 if (i.prefixes != 0 && !intel_syntax)
3822 as_warn (_("skipping prefixes on this instruction"));
3824 p = frag_more (1 + size);
3825 *p++ = i.tm.base_opcode;
3827 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3828 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3830 /* All jumps handled here are signed, but don't use a signed limit
3831 check for 32 and 16 bit jumps as we want to allow wrap around at
3832 4G and 64k respectively. */
3834 fixP->fx_signed = 1;
3838 output_interseg_jump ()
3846 if (flag_code == CODE_16BIT)
3850 if (i.prefix[DATA_PREFIX] != 0)
3856 if (i.prefix[REX_PREFIX] != 0)
3866 if (i.prefixes != 0 && !intel_syntax)
3867 as_warn (_("skipping prefixes on this instruction"));
3869 /* 1 opcode; 2 segment; offset */
3870 p = frag_more (prefix + 1 + 2 + size);
3872 if (i.prefix[DATA_PREFIX] != 0)
3873 *p++ = DATA_PREFIX_OPCODE;
3875 if (i.prefix[REX_PREFIX] != 0)
3876 *p++ = i.prefix[REX_PREFIX];
3878 *p++ = i.tm.base_opcode;
3879 if (i.op[1].imms->X_op == O_constant)
3881 offsetT n = i.op[1].imms->X_add_number;
3884 && !fits_in_unsigned_word (n)
3885 && !fits_in_signed_word (n))
3887 as_bad (_("16-bit jump out of range"));
3890 md_number_to_chars (p, n, size);
3893 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3894 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3895 if (i.op[0].imms->X_op != O_constant)
3896 as_bad (_("can't handle non absolute segment in `%s'"),
3898 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3904 fragS *insn_start_frag;
3905 offsetT insn_start_off;
3907 /* Tie dwarf2 debug info to the address at the start of the insn.
3908 We can't do this after the insn has been output as the current
3909 frag may have been closed off. eg. by frag_var. */
3910 dwarf2_emit_insn (0);
3912 insn_start_frag = frag_now;
3913 insn_start_off = frag_now_fix ();
3916 if (i.tm.opcode_modifier & Jump)
3918 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3920 else if (i.tm.opcode_modifier & JumpInterSegment)
3921 output_interseg_jump ();
3924 /* Output normal instructions here. */
3927 unsigned int prefix;
3929 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3930 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3931 use one more higher byte to specify a prefix the instruction
3933 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3935 if (i.tm.base_opcode & 0xff000000)
3937 prefix = (i.tm.base_opcode >> 24) & 0xff;
3941 else if ((i.tm.base_opcode & 0xff0000) != 0)
3943 prefix = (i.tm.base_opcode >> 16) & 0xff;
3944 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3947 if (prefix != REPE_PREFIX_OPCODE
3948 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3949 add_prefix (prefix);
3952 add_prefix (prefix);
3955 /* The prefix bytes. */
3957 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3963 md_number_to_chars (p, (valueT) *q, 1);
3967 /* Now the opcode; be careful about word order here! */
3968 if (fits_in_unsigned_byte (i.tm.base_opcode))
3970 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3974 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3977 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3982 /* Put out high byte first: can't use md_number_to_chars! */
3983 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3984 *p = i.tm.base_opcode & 0xff;
3987 /* Now the modrm byte and sib byte (if present). */
3988 if (i.tm.opcode_modifier & Modrm)
3991 md_number_to_chars (p,
3992 (valueT) (i.rm.regmem << 0
3996 /* If i.rm.regmem == ESP (4)
3997 && i.rm.mode != (Register mode)
3999 ==> need second modrm byte. */
4000 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4002 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4005 md_number_to_chars (p,
4006 (valueT) (i.sib.base << 0
4008 | i.sib.scale << 6),
4013 if (i.disp_operands)
4014 output_disp (insn_start_frag, insn_start_off);
4017 output_imm (insn_start_frag, insn_start_off);
4023 pi ("" /*line*/, &i);
4025 #endif /* DEBUG386 */
4029 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
4034 for (n = 0; n < i.operands; n++)
4036 if (i.types[n] & Disp)
4038 if (i.op[n].disps->X_op == O_constant)
4044 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4047 if (i.types[n] & Disp8)
4049 if (i.types[n] & Disp64)
4052 val = offset_in_range (i.op[n].disps->X_add_number,
4054 p = frag_more (size);
4055 md_number_to_chars (p, val, size);
4059 enum bfd_reloc_code_real reloc_type;
4062 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4064 /* The PC relative address is computed relative
4065 to the instruction boundary, so in case immediate
4066 fields follows, we need to adjust the value. */
4067 if (pcrel && i.imm_operands)
4072 for (n1 = 0; n1 < i.operands; n1++)
4073 if (i.types[n1] & Imm)
4075 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4078 if (i.types[n1] & (Imm8 | Imm8S))
4080 if (i.types[n1] & Imm64)
4085 /* We should find the immediate. */
4086 if (n1 == i.operands)
4088 i.op[n].disps->X_add_number -= imm_size;
4091 if (i.types[n] & Disp32S)
4094 if (i.types[n] & (Disp16 | Disp64))
4097 if (i.types[n] & Disp64)
4101 p = frag_more (size);
4102 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4104 && GOT_symbol == i.op[n].disps->X_add_symbol
4105 && (((reloc_type == BFD_RELOC_32
4106 || reloc_type == BFD_RELOC_X86_64_32S
4107 || (reloc_type == BFD_RELOC_64
4109 && (i.op[n].disps->X_op == O_symbol
4110 || (i.op[n].disps->X_op == O_add
4111 && ((symbol_get_value_expression
4112 (i.op[n].disps->X_op_symbol)->X_op)
4114 || reloc_type == BFD_RELOC_32_PCREL))
4118 if (insn_start_frag == frag_now)
4119 add = (p - frag_now->fr_literal) - insn_start_off;
4124 add = insn_start_frag->fr_fix - insn_start_off;
4125 for (fr = insn_start_frag->fr_next;
4126 fr && fr != frag_now; fr = fr->fr_next)
4128 add += p - frag_now->fr_literal;
4133 reloc_type = BFD_RELOC_386_GOTPC;
4134 i.op[n].imms->X_add_number += add;
4136 else if (reloc_type == BFD_RELOC_64)
4137 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4139 /* Don't do the adjustment for x86-64, as there
4140 the pcrel addressing is relative to the _next_
4141 insn, and that is taken care of in other code. */
4142 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4144 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4145 i.op[n].disps, pcrel, reloc_type);
4152 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4157 for (n = 0; n < i.operands; n++)
4159 if (i.types[n] & Imm)
4161 if (i.op[n].imms->X_op == O_constant)
4167 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4170 if (i.types[n] & (Imm8 | Imm8S))
4172 else if (i.types[n] & Imm64)
4175 val = offset_in_range (i.op[n].imms->X_add_number,
4177 p = frag_more (size);
4178 md_number_to_chars (p, val, size);
4182 /* Not absolute_section.
4183 Need a 32-bit fixup (don't support 8bit
4184 non-absolute imms). Try to support other
4186 enum bfd_reloc_code_real reloc_type;
4190 if ((i.types[n] & (Imm32S))
4191 && (i.suffix == QWORD_MNEM_SUFFIX
4192 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4194 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4197 if (i.types[n] & (Imm8 | Imm8S))
4199 if (i.types[n] & Imm64)
4203 p = frag_more (size);
4204 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4206 /* This is tough to explain. We end up with this one if we
4207 * have operands that look like
4208 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4209 * obtain the absolute address of the GOT, and it is strongly
4210 * preferable from a performance point of view to avoid using
4211 * a runtime relocation for this. The actual sequence of
4212 * instructions often look something like:
4217 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4219 * The call and pop essentially return the absolute address
4220 * of the label .L66 and store it in %ebx. The linker itself
4221 * will ultimately change the first operand of the addl so
4222 * that %ebx points to the GOT, but to keep things simple, the
4223 * .o file must have this operand set so that it generates not
4224 * the absolute address of .L66, but the absolute address of
4225 * itself. This allows the linker itself simply treat a GOTPC
4226 * relocation as asking for a pcrel offset to the GOT to be
4227 * added in, and the addend of the relocation is stored in the
4228 * operand field for the instruction itself.
4230 * Our job here is to fix the operand so that it would add
4231 * the correct offset so that %ebx would point to itself. The
4232 * thing that is tricky is that .-.L66 will point to the
4233 * beginning of the instruction, so we need to further modify
4234 * the operand so that it will point to itself. There are
4235 * other cases where you have something like:
4237 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4239 * and here no correction would be required. Internally in
4240 * the assembler we treat operands of this form as not being
4241 * pcrel since the '.' is explicitly mentioned, and I wonder
4242 * whether it would simplify matters to do it this way. Who
4243 * knows. In earlier versions of the PIC patches, the
4244 * pcrel_adjust field was used to store the correction, but
4245 * since the expression is not pcrel, I felt it would be
4246 * confusing to do it this way. */
4248 if ((reloc_type == BFD_RELOC_32
4249 || reloc_type == BFD_RELOC_X86_64_32S
4250 || reloc_type == BFD_RELOC_64)
4252 && GOT_symbol == i.op[n].imms->X_add_symbol
4253 && (i.op[n].imms->X_op == O_symbol
4254 || (i.op[n].imms->X_op == O_add
4255 && ((symbol_get_value_expression
4256 (i.op[n].imms->X_op_symbol)->X_op)
4261 if (insn_start_frag == frag_now)
4262 add = (p - frag_now->fr_literal) - insn_start_off;
4267 add = insn_start_frag->fr_fix - insn_start_off;
4268 for (fr = insn_start_frag->fr_next;
4269 fr && fr != frag_now; fr = fr->fr_next)
4271 add += p - frag_now->fr_literal;
4275 reloc_type = BFD_RELOC_386_GOTPC;
4277 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4279 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4280 i.op[n].imms->X_add_number += add;
4282 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4283 i.op[n].imms, 0, reloc_type);
4289 /* x86_cons_fix_new is called via the expression parsing code when a
4290 reloc is needed. We use this hook to get the correct .got reloc. */
4291 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4292 static int cons_sign = -1;
4295 x86_cons_fix_new (fragS *frag,
4300 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4302 got_reloc = NO_RELOC;
4305 if (exp->X_op == O_secrel)
4307 exp->X_op = O_symbol;
4308 r = BFD_RELOC_32_SECREL;
4312 fix_new_exp (frag, off, len, exp, 0, r);
4315 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4316 # define lex_got(reloc, adjust, types) NULL
4318 /* Parse operands of the form
4319 <symbol>@GOTOFF+<nnn>
4320 and similar .plt or .got references.
4322 If we find one, set up the correct relocation in RELOC and copy the
4323 input string, minus the `@GOTOFF' into a malloc'd buffer for
4324 parsing by the calling routine. Return this buffer, and if ADJUST
4325 is non-null set it to the length of the string we removed from the
4326 input line. Otherwise return NULL. */
4328 lex_got (enum bfd_reloc_code_real *reloc,
4330 unsigned int *types)
4332 /* Some of the relocations depend on the size of what field is to
4333 be relocated. But in our callers i386_immediate and i386_displacement
4334 we don't yet know the operand size (this will be set by insn
4335 matching). Hence we record the word32 relocation here,
4336 and adjust the reloc according to the real size in reloc(). */
4337 static const struct {
4339 const enum bfd_reloc_code_real rel[2];
4340 const unsigned int types64;
4342 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4343 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4344 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4345 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4346 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4347 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4348 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4349 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4350 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4351 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4352 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4353 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4354 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4355 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4356 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4357 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4358 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4366 for (cp = input_line_pointer; *cp != '@'; cp++)
4367 if (is_end_of_line[(unsigned char) *cp])
4370 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4374 len = strlen (gotrel[j].str);
4375 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4377 if (gotrel[j].rel[object_64bit] != 0)
4380 char *tmpbuf, *past_reloc;
4382 *reloc = gotrel[j].rel[object_64bit];
4388 if (flag_code != CODE_64BIT)
4389 *types = Imm32|Disp32;
4391 *types = gotrel[j].types64;
4394 if (GOT_symbol == NULL)
4395 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4397 /* Replace the relocation token with ' ', so that
4398 errors like foo@GOTOFF1 will be detected. */
4400 /* The length of the first part of our input line. */
4401 first = cp - input_line_pointer;
4403 /* The second part goes from after the reloc token until
4404 (and including) an end_of_line char. Don't use strlen
4405 here as the end_of_line char may not be a NUL. */
4406 past_reloc = cp + 1 + len;
4407 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4409 second = cp - past_reloc;
4411 /* Allocate and copy string. The trailing NUL shouldn't
4412 be necessary, but be safe. */
4413 tmpbuf = xmalloc (first + second + 2);
4414 memcpy (tmpbuf, input_line_pointer, first);
4415 tmpbuf[first] = ' ';
4416 memcpy (tmpbuf + first + 1, past_reloc, second);
4417 tmpbuf[first + second + 1] = '\0';
4421 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4422 gotrel[j].str, 1 << (5 + object_64bit));
4427 /* Might be a symbol version string. Don't as_bad here. */
4432 x86_cons (exp, size)
4436 if (size == 4 || (object_64bit && size == 8))
4438 /* Handle @GOTOFF and the like in an expression. */
4440 char *gotfree_input_line;
4443 save = input_line_pointer;
4444 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4445 if (gotfree_input_line)
4446 input_line_pointer = gotfree_input_line;
4450 if (gotfree_input_line)
4452 /* expression () has merrily parsed up to the end of line,
4453 or a comma - in the wrong buffer. Transfer how far
4454 input_line_pointer has moved to the right buffer. */
4455 input_line_pointer = (save
4456 + (input_line_pointer - gotfree_input_line)
4458 free (gotfree_input_line);
4466 static void signed_cons (int size)
4468 if (flag_code == CODE_64BIT)
4476 pe_directive_secrel (dummy)
4477 int dummy ATTRIBUTE_UNUSED;
4484 if (exp.X_op == O_symbol)
4485 exp.X_op = O_secrel;
4487 emit_expr (&exp, 4);
4489 while (*input_line_pointer++ == ',');
4491 input_line_pointer--;
4492 demand_empty_rest_of_line ();
4497 i386_immediate (char *imm_start)
4499 char *save_input_line_pointer;
4500 char *gotfree_input_line;
4503 unsigned int types = ~0U;
4505 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4507 as_bad (_("only 1 or 2 immediate operands are allowed"));
4511 exp = &im_expressions[i.imm_operands++];
4512 i.op[this_operand].imms = exp;
4514 if (is_space_char (*imm_start))
4517 save_input_line_pointer = input_line_pointer;
4518 input_line_pointer = imm_start;
4520 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4521 if (gotfree_input_line)
4522 input_line_pointer = gotfree_input_line;
4524 exp_seg = expression (exp);
4527 if (*input_line_pointer)
4528 as_bad (_("junk `%s' after expression"), input_line_pointer);
4530 input_line_pointer = save_input_line_pointer;
4531 if (gotfree_input_line)
4532 free (gotfree_input_line);
4534 if (exp->X_op == O_absent || exp->X_op == O_big)
4536 /* Missing or bad expr becomes absolute 0. */
4537 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4539 exp->X_op = O_constant;
4540 exp->X_add_number = 0;
4541 exp->X_add_symbol = (symbolS *) 0;
4542 exp->X_op_symbol = (symbolS *) 0;
4544 else if (exp->X_op == O_constant)
4546 /* Size it properly later. */
4547 i.types[this_operand] |= Imm64;
4548 /* If BFD64, sign extend val. */
4549 if (!use_rela_relocations)
4550 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4551 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4553 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4554 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4555 && exp_seg != absolute_section
4556 && exp_seg != text_section
4557 && exp_seg != data_section
4558 && exp_seg != bss_section
4559 && exp_seg != undefined_section
4560 && !bfd_is_com_section (exp_seg))
4562 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4566 else if (!intel_syntax && exp->X_op == O_register)
4568 as_bad (_("illegal immediate register operand %s"), imm_start);
4573 /* This is an address. The size of the address will be
4574 determined later, depending on destination register,
4575 suffix, or the default for the section. */
4576 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4577 i.types[this_operand] &= types;
4583 static char *i386_scale PARAMS ((char *));
4590 char *save = input_line_pointer;
4592 input_line_pointer = scale;
4593 val = get_absolute_expression ();
4598 i.log2_scale_factor = 0;
4601 i.log2_scale_factor = 1;
4604 i.log2_scale_factor = 2;
4607 i.log2_scale_factor = 3;
4611 char sep = *input_line_pointer;
4613 *input_line_pointer = '\0';
4614 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4616 *input_line_pointer = sep;
4617 input_line_pointer = save;
4621 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4623 as_warn (_("scale factor of %d without an index register"),
4624 1 << i.log2_scale_factor);
4625 #if SCALE1_WHEN_NO_INDEX
4626 i.log2_scale_factor = 0;
4629 scale = input_line_pointer;
4630 input_line_pointer = save;
4634 static int i386_displacement PARAMS ((char *, char *));
4637 i386_displacement (disp_start, disp_end)
4643 char *save_input_line_pointer;
4644 char *gotfree_input_line;
4645 int bigdisp, override;
4646 unsigned int types = Disp;
4648 if ((i.types[this_operand] & JumpAbsolute)
4649 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4652 override = (i.prefix[ADDR_PREFIX] != 0);
4656 /* For PC-relative branches, the width of the displacement
4657 is dependent upon data size, not address size. */
4659 override = (i.prefix[DATA_PREFIX] != 0);
4661 if (flag_code == CODE_64BIT)
4664 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4666 : Disp32S | Disp32);
4668 bigdisp = Disp64 | Disp32S | Disp32;
4675 override = (i.suffix == (flag_code != CODE_16BIT
4677 : LONG_MNEM_SUFFIX));
4680 if ((flag_code == CODE_16BIT) ^ override)
4683 i.types[this_operand] |= bigdisp;
4685 exp = &disp_expressions[i.disp_operands];
4686 i.op[this_operand].disps = exp;
4688 save_input_line_pointer = input_line_pointer;
4689 input_line_pointer = disp_start;
4690 END_STRING_AND_SAVE (disp_end);
4692 #ifndef GCC_ASM_O_HACK
4693 #define GCC_ASM_O_HACK 0
4696 END_STRING_AND_SAVE (disp_end + 1);
4697 if ((i.types[this_operand] & BaseIndex) != 0
4698 && displacement_string_end[-1] == '+')
4700 /* This hack is to avoid a warning when using the "o"
4701 constraint within gcc asm statements.
4704 #define _set_tssldt_desc(n,addr,limit,type) \
4705 __asm__ __volatile__ ( \
4707 "movw %w1,2+%0\n\t" \
4709 "movb %b1,4+%0\n\t" \
4710 "movb %4,5+%0\n\t" \
4711 "movb $0,6+%0\n\t" \
4712 "movb %h1,7+%0\n\t" \
4714 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4716 This works great except that the output assembler ends
4717 up looking a bit weird if it turns out that there is
4718 no offset. You end up producing code that looks like:
4731 So here we provide the missing zero. */
4733 *displacement_string_end = '0';
4736 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4737 if (gotfree_input_line)
4738 input_line_pointer = gotfree_input_line;
4740 exp_seg = expression (exp);
4743 if (*input_line_pointer)
4744 as_bad (_("junk `%s' after expression"), input_line_pointer);
4746 RESTORE_END_STRING (disp_end + 1);
4748 RESTORE_END_STRING (disp_end);
4749 input_line_pointer = save_input_line_pointer;
4750 if (gotfree_input_line)
4751 free (gotfree_input_line);
4753 /* We do this to make sure that the section symbol is in
4754 the symbol table. We will ultimately change the relocation
4755 to be relative to the beginning of the section. */
4756 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4757 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4758 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4760 if (exp->X_op != O_symbol)
4762 as_bad (_("bad expression used with @%s"),
4763 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4769 if (S_IS_LOCAL (exp->X_add_symbol)
4770 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4771 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4772 exp->X_op = O_subtract;
4773 exp->X_op_symbol = GOT_symbol;
4774 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4775 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4776 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4777 i.reloc[this_operand] = BFD_RELOC_64;
4779 i.reloc[this_operand] = BFD_RELOC_32;
4782 if (exp->X_op == O_absent || exp->X_op == O_big)
4784 /* Missing or bad expr becomes absolute 0. */
4785 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4787 exp->X_op = O_constant;
4788 exp->X_add_number = 0;
4789 exp->X_add_symbol = (symbolS *) 0;
4790 exp->X_op_symbol = (symbolS *) 0;
4793 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4794 if (exp->X_op != O_constant
4795 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4796 && exp_seg != absolute_section
4797 && exp_seg != text_section
4798 && exp_seg != data_section
4799 && exp_seg != bss_section
4800 && exp_seg != undefined_section
4801 && !bfd_is_com_section (exp_seg))
4803 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4808 if (!(i.types[this_operand] & ~Disp))
4809 i.types[this_operand] &= types;
4814 static int i386_index_check PARAMS ((const char *));
4816 /* Make sure the memory operand we've been dealt is valid.
4817 Return 1 on success, 0 on a failure. */
4820 i386_index_check (operand_string)
4821 const char *operand_string;
4824 #if INFER_ADDR_PREFIX
4830 if ((current_templates->start->cpu_flags & CpuSVME)
4831 && current_templates->end[-1].operand_types[0] == AnyMem)
4833 /* Memory operands of SVME insns are special in that they only allow
4834 rAX as their memory address and ignore any segment override. */
4837 /* SKINIT is even more restrictive: it always requires EAX. */
4838 if (strcmp (current_templates->start->name, "skinit") == 0)
4840 else if (flag_code == CODE_64BIT)
4841 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4843 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4847 || !(i.base_reg->reg_type & Acc)
4848 || !(i.base_reg->reg_type & RegXX)
4850 || (i.types[0] & Disp))
4853 else if (flag_code == CODE_64BIT)
4855 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4858 && ((i.base_reg->reg_type & RegXX) == 0)
4859 && (i.base_reg->reg_type != BaseIndex
4862 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4863 != (RegXX | BaseIndex))))
4868 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4872 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4873 != (Reg16 | BaseIndex)))
4875 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4876 != (Reg16 | BaseIndex))
4878 && i.base_reg->reg_num < 6
4879 && i.index_reg->reg_num >= 6
4880 && i.log2_scale_factor == 0))))
4887 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4889 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4890 != (Reg32 | BaseIndex))))
4896 #if INFER_ADDR_PREFIX
4897 if (i.prefix[ADDR_PREFIX] == 0)
4899 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4901 /* Change the size of any displacement too. At most one of
4902 Disp16 or Disp32 is set.
4903 FIXME. There doesn't seem to be any real need for separate
4904 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4905 Removing them would probably clean up the code quite a lot. */
4906 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4907 i.types[this_operand] ^= (Disp16 | Disp32);
4912 as_bad (_("`%s' is not a valid base/index expression"),
4916 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4918 flag_code_names[flag_code]);
4923 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4927 i386_operand (operand_string)
4928 char *operand_string;
4932 char *op_string = operand_string;
4934 if (is_space_char (*op_string))
4937 /* We check for an absolute prefix (differentiating,
4938 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4939 if (*op_string == ABSOLUTE_PREFIX)
4942 if (is_space_char (*op_string))
4944 i.types[this_operand] |= JumpAbsolute;
4947 /* Check if operand is a register. */
4948 if ((r = parse_register (op_string, &end_op)) != NULL)
4950 /* Check for a segment override by searching for ':' after a
4951 segment register. */
4953 if (is_space_char (*op_string))
4955 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4960 i.seg[i.mem_operands] = &es;
4963 i.seg[i.mem_operands] = &cs;
4966 i.seg[i.mem_operands] = &ss;
4969 i.seg[i.mem_operands] = &ds;
4972 i.seg[i.mem_operands] = &fs;
4975 i.seg[i.mem_operands] = &gs;
4979 /* Skip the ':' and whitespace. */
4981 if (is_space_char (*op_string))
4984 if (!is_digit_char (*op_string)
4985 && !is_identifier_char (*op_string)
4986 && *op_string != '('
4987 && *op_string != ABSOLUTE_PREFIX)
4989 as_bad (_("bad memory operand `%s'"), op_string);
4992 /* Handle case of %es:*foo. */
4993 if (*op_string == ABSOLUTE_PREFIX)
4996 if (is_space_char (*op_string))
4998 i.types[this_operand] |= JumpAbsolute;
5000 goto do_memory_reference;
5004 as_bad (_("junk `%s' after register"), op_string);
5007 i.types[this_operand] |= r->reg_type & ~BaseIndex;
5008 i.op[this_operand].regs = r;
5011 else if (*op_string == REGISTER_PREFIX)
5013 as_bad (_("bad register name `%s'"), op_string);
5016 else if (*op_string == IMMEDIATE_PREFIX)
5019 if (i.types[this_operand] & JumpAbsolute)
5021 as_bad (_("immediate operand illegal with absolute jump"));
5024 if (!i386_immediate (op_string))
5027 else if (is_digit_char (*op_string)
5028 || is_identifier_char (*op_string)
5029 || *op_string == '(')
5031 /* This is a memory reference of some sort. */
5034 /* Start and end of displacement string expression (if found). */
5035 char *displacement_string_start;
5036 char *displacement_string_end;
5038 do_memory_reference:
5039 if ((i.mem_operands == 1
5040 && (current_templates->start->opcode_modifier & IsString) == 0)
5041 || i.mem_operands == 2)
5043 as_bad (_("too many memory references for `%s'"),
5044 current_templates->start->name);
5048 /* Check for base index form. We detect the base index form by
5049 looking for an ')' at the end of the operand, searching
5050 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5052 base_string = op_string + strlen (op_string);
5055 if (is_space_char (*base_string))
5058 /* If we only have a displacement, set-up for it to be parsed later. */
5059 displacement_string_start = op_string;
5060 displacement_string_end = base_string + 1;
5062 if (*base_string == ')')
5065 unsigned int parens_balanced = 1;
5066 /* We've already checked that the number of left & right ()'s are
5067 equal, so this loop will not be infinite. */
5071 if (*base_string == ')')
5073 if (*base_string == '(')
5076 while (parens_balanced);
5078 temp_string = base_string;
5080 /* Skip past '(' and whitespace. */
5082 if (is_space_char (*base_string))
5085 if (*base_string == ','
5086 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
5088 displacement_string_end = temp_string;
5090 i.types[this_operand] |= BaseIndex;
5094 base_string = end_op;
5095 if (is_space_char (*base_string))
5099 /* There may be an index reg or scale factor here. */
5100 if (*base_string == ',')
5103 if (is_space_char (*base_string))
5106 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5108 base_string = end_op;
5109 if (is_space_char (*base_string))
5111 if (*base_string == ',')
5114 if (is_space_char (*base_string))
5117 else if (*base_string != ')')
5119 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5124 else if (*base_string == REGISTER_PREFIX)
5126 as_bad (_("bad register name `%s'"), base_string);
5130 /* Check for scale factor. */
5131 if (*base_string != ')')
5133 char *end_scale = i386_scale (base_string);
5138 base_string = end_scale;
5139 if (is_space_char (*base_string))
5141 if (*base_string != ')')
5143 as_bad (_("expecting `)' after scale factor in `%s'"),
5148 else if (!i.index_reg)
5150 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5155 else if (*base_string != ')')
5157 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5162 else if (*base_string == REGISTER_PREFIX)
5164 as_bad (_("bad register name `%s'"), base_string);
5169 /* If there's an expression beginning the operand, parse it,
5170 assuming displacement_string_start and
5171 displacement_string_end are meaningful. */
5172 if (displacement_string_start != displacement_string_end)
5174 if (!i386_displacement (displacement_string_start,
5175 displacement_string_end))
5179 /* Special case for (%dx) while doing input/output op. */
5181 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5183 && i.log2_scale_factor == 0
5184 && i.seg[i.mem_operands] == 0
5185 && (i.types[this_operand] & Disp) == 0)
5187 i.types[this_operand] = InOutPortReg;
5191 if (i386_index_check (operand_string) == 0)
5197 /* It's not a memory operand; argh! */
5198 as_bad (_("invalid char %s beginning operand %d `%s'"),
5199 output_invalid (*op_string),
5204 return 1; /* Normal return. */
5207 /* md_estimate_size_before_relax()
5209 Called just before relax() for rs_machine_dependent frags. The x86
5210 assembler uses these frags to handle variable size jump
5213 Any symbol that is now undefined will not become defined.
5214 Return the correct fr_subtype in the frag.
5215 Return the initial "guess for variable size of frag" to caller.
5216 The guess is actually the growth beyond the fixed part. Whatever
5217 we do to grow the fixed or variable part contributes to our
5221 md_estimate_size_before_relax (fragP, segment)
5225 /* We've already got fragP->fr_subtype right; all we have to do is
5226 check for un-relaxable symbols. On an ELF system, we can't relax
5227 an externally visible symbol, because it may be overridden by a
5229 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5232 && (S_IS_EXTERNAL (fragP->fr_symbol)
5233 || S_IS_WEAK (fragP->fr_symbol)))
5237 /* Symbol is undefined in this segment, or we need to keep a
5238 reloc so that weak symbols can be overridden. */
5239 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5240 enum bfd_reloc_code_real reloc_type;
5241 unsigned char *opcode;
5244 if (fragP->fr_var != NO_RELOC)
5245 reloc_type = fragP->fr_var;
5247 reloc_type = BFD_RELOC_16_PCREL;
5249 reloc_type = BFD_RELOC_32_PCREL;
5251 old_fr_fix = fragP->fr_fix;
5252 opcode = (unsigned char *) fragP->fr_opcode;
5254 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5257 /* Make jmp (0xeb) a (d)word displacement jump. */
5259 fragP->fr_fix += size;
5260 fix_new (fragP, old_fr_fix, size,
5262 fragP->fr_offset, 1,
5268 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5270 /* Negate the condition, and branch past an
5271 unconditional jump. */
5274 /* Insert an unconditional jump. */
5276 /* We added two extra opcode bytes, and have a two byte
5278 fragP->fr_fix += 2 + 2;
5279 fix_new (fragP, old_fr_fix + 2, 2,
5281 fragP->fr_offset, 1,
5288 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5293 fixP = fix_new (fragP, old_fr_fix, 1,
5295 fragP->fr_offset, 1,
5297 fixP->fx_signed = 1;
5301 /* This changes the byte-displacement jump 0x7N
5302 to the (d)word-displacement jump 0x0f,0x8N. */
5303 opcode[1] = opcode[0] + 0x10;
5304 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5305 /* We've added an opcode byte. */
5306 fragP->fr_fix += 1 + size;
5307 fix_new (fragP, old_fr_fix + 1, size,
5309 fragP->fr_offset, 1,
5314 BAD_CASE (fragP->fr_subtype);
5318 return fragP->fr_fix - old_fr_fix;
5321 /* Guess size depending on current relax state. Initially the relax
5322 state will correspond to a short jump and we return 1, because
5323 the variable part of the frag (the branch offset) is one byte
5324 long. However, we can relax a section more than once and in that
5325 case we must either set fr_subtype back to the unrelaxed state,
5326 or return the value for the appropriate branch. */
5327 return md_relax_table[fragP->fr_subtype].rlx_length;
5330 /* Called after relax() is finished.
5332 In: Address of frag.
5333 fr_type == rs_machine_dependent.
5334 fr_subtype is what the address relaxed to.
5336 Out: Any fixSs and constants are set up.
5337 Caller will turn frag into a ".space 0". */
5340 md_convert_frag (abfd, sec, fragP)
5341 bfd *abfd ATTRIBUTE_UNUSED;
5342 segT sec ATTRIBUTE_UNUSED;
5345 unsigned char *opcode;
5346 unsigned char *where_to_put_displacement = NULL;
5347 offsetT target_address;
5348 offsetT opcode_address;
5349 unsigned int extension = 0;
5350 offsetT displacement_from_opcode_start;
5352 opcode = (unsigned char *) fragP->fr_opcode;
5354 /* Address we want to reach in file space. */
5355 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5357 /* Address opcode resides at in file space. */
5358 opcode_address = fragP->fr_address + fragP->fr_fix;
5360 /* Displacement from opcode start to fill into instruction. */
5361 displacement_from_opcode_start = target_address - opcode_address;
5363 if ((fragP->fr_subtype & BIG) == 0)
5365 /* Don't have to change opcode. */
5366 extension = 1; /* 1 opcode + 1 displacement */
5367 where_to_put_displacement = &opcode[1];
5371 if (no_cond_jump_promotion
5372 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5373 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5375 switch (fragP->fr_subtype)
5377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5378 extension = 4; /* 1 opcode + 4 displacement */
5380 where_to_put_displacement = &opcode[1];
5383 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5384 extension = 2; /* 1 opcode + 2 displacement */
5386 where_to_put_displacement = &opcode[1];
5389 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5390 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5391 extension = 5; /* 2 opcode + 4 displacement */
5392 opcode[1] = opcode[0] + 0x10;
5393 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5394 where_to_put_displacement = &opcode[2];
5397 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5398 extension = 3; /* 2 opcode + 2 displacement */
5399 opcode[1] = opcode[0] + 0x10;
5400 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5401 where_to_put_displacement = &opcode[2];
5404 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5409 where_to_put_displacement = &opcode[3];
5413 BAD_CASE (fragP->fr_subtype);
5418 /* If size if less then four we are sure that the operand fits,
5419 but if it's 4, then it could be that the displacement is larger
5421 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5423 && ((addressT) (displacement_from_opcode_start - extension
5424 + ((addressT) 1 << 31))
5425 > (((addressT) 2 << 31) - 1)))
5427 as_bad_where (fragP->fr_file, fragP->fr_line,
5428 _("jump target out of range"));
5429 /* Make us emit 0. */
5430 displacement_from_opcode_start = extension;
5432 /* Now put displacement after opcode. */
5433 md_number_to_chars ((char *) where_to_put_displacement,
5434 (valueT) (displacement_from_opcode_start - extension),
5435 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5436 fragP->fr_fix += extension;
5439 /* Size of byte displacement jmp. */
5440 int md_short_jump_size = 2;
5442 /* Size of dword displacement jmp. */
5443 int md_long_jump_size = 5;
5446 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5448 addressT from_addr, to_addr;
5449 fragS *frag ATTRIBUTE_UNUSED;
5450 symbolS *to_symbol ATTRIBUTE_UNUSED;
5454 offset = to_addr - (from_addr + 2);
5455 /* Opcode for byte-disp jump. */
5456 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5457 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5461 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5463 addressT from_addr, to_addr;
5464 fragS *frag ATTRIBUTE_UNUSED;
5465 symbolS *to_symbol ATTRIBUTE_UNUSED;
5469 offset = to_addr - (from_addr + 5);
5470 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5471 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5474 /* Apply a fixup (fixS) to segment data, once it has been determined
5475 by our caller that we have all the info we need to fix it up.
5477 On the 386, immediates, displacements, and data pointers are all in
5478 the same (little-endian) format, so we don't need to care about which
5482 md_apply_fix (fixP, valP, seg)
5483 /* The fix we're to put in. */
5485 /* Pointer to the value of the bits. */
5487 /* Segment fix is from. */
5488 segT seg ATTRIBUTE_UNUSED;
5490 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5491 valueT value = *valP;
5493 #if !defined (TE_Mach)
5496 switch (fixP->fx_r_type)
5502 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5505 case BFD_RELOC_X86_64_32S:
5506 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5509 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5512 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5517 if (fixP->fx_addsy != NULL
5518 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5519 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5520 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5521 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5522 && !use_rela_relocations)
5524 /* This is a hack. There should be a better way to handle this.
5525 This covers for the fact that bfd_install_relocation will
5526 subtract the current location (for partial_inplace, PC relative
5527 relocations); see more below. */
5531 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5534 value += fixP->fx_where + fixP->fx_frag->fr_address;
5536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5539 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5542 || (symbol_section_p (fixP->fx_addsy)
5543 && sym_seg != absolute_section))
5544 && !generic_force_reloc (fixP))
5546 /* Yes, we add the values in twice. This is because
5547 bfd_install_relocation subtracts them out again. I think
5548 bfd_install_relocation is broken, but I don't dare change
5550 value += fixP->fx_where + fixP->fx_frag->fr_address;
5554 #if defined (OBJ_COFF) && defined (TE_PE)
5555 /* For some reason, the PE format does not store a
5556 section address offset for a PC relative symbol. */
5557 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5558 || S_IS_WEAK (fixP->fx_addsy))
5559 value += md_pcrel_from (fixP);
5563 /* Fix a few things - the dynamic linker expects certain values here,
5564 and we must not disappoint it. */
5565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5566 if (IS_ELF && fixP->fx_addsy)
5567 switch (fixP->fx_r_type)
5569 case BFD_RELOC_386_PLT32:
5570 case BFD_RELOC_X86_64_PLT32:
5571 /* Make the jump instruction point to the address of the operand. At
5572 runtime we merely add the offset to the actual PLT entry. */
5576 case BFD_RELOC_386_TLS_GD:
5577 case BFD_RELOC_386_TLS_LDM:
5578 case BFD_RELOC_386_TLS_IE_32:
5579 case BFD_RELOC_386_TLS_IE:
5580 case BFD_RELOC_386_TLS_GOTIE:
5581 case BFD_RELOC_386_TLS_GOTDESC:
5582 case BFD_RELOC_X86_64_TLSGD:
5583 case BFD_RELOC_X86_64_TLSLD:
5584 case BFD_RELOC_X86_64_GOTTPOFF:
5585 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5586 value = 0; /* Fully resolved at runtime. No addend. */
5588 case BFD_RELOC_386_TLS_LE:
5589 case BFD_RELOC_386_TLS_LDO_32:
5590 case BFD_RELOC_386_TLS_LE_32:
5591 case BFD_RELOC_X86_64_DTPOFF32:
5592 case BFD_RELOC_X86_64_DTPOFF64:
5593 case BFD_RELOC_X86_64_TPOFF32:
5594 case BFD_RELOC_X86_64_TPOFF64:
5595 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5598 case BFD_RELOC_386_TLS_DESC_CALL:
5599 case BFD_RELOC_X86_64_TLSDESC_CALL:
5600 value = 0; /* Fully resolved at runtime. No addend. */
5601 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5605 case BFD_RELOC_386_GOT32:
5606 case BFD_RELOC_X86_64_GOT32:
5607 value = 0; /* Fully resolved at runtime. No addend. */
5610 case BFD_RELOC_VTABLE_INHERIT:
5611 case BFD_RELOC_VTABLE_ENTRY:
5618 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5620 #endif /* !defined (TE_Mach) */
5622 /* Are we finished with this relocation now? */
5623 if (fixP->fx_addsy == NULL)
5625 else if (use_rela_relocations)
5627 fixP->fx_no_overflow = 1;
5628 /* Remember value for tc_gen_reloc. */
5629 fixP->fx_addnumber = value;
5633 md_number_to_chars (p, value, fixP->fx_size);
5636 #define MAX_LITTLENUMS 6
5638 /* Turn the string pointed to by litP into a floating point constant
5639 of type TYPE, and emit the appropriate bytes. The number of
5640 LITTLENUMS emitted is stored in *SIZEP. An error message is
5641 returned, or NULL on OK. */
5644 md_atof (type, litP, sizeP)
5650 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5651 LITTLENUM_TYPE *wordP;
5673 return _("Bad call to md_atof ()");
5675 t = atof_ieee (input_line_pointer, type, words);
5677 input_line_pointer = t;
5679 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5680 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5681 the bigendian 386. */
5682 for (wordP = words + prec - 1; prec--;)
5684 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5685 litP += sizeof (LITTLENUM_TYPE);
5690 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5697 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5700 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5701 "(0x%x)", (unsigned char) c);
5702 return output_invalid_buf;
5705 /* REG_STRING starts *before* REGISTER_PREFIX. */
5707 static const reg_entry *
5708 parse_real_register (char *reg_string, char **end_op)
5710 char *s = reg_string;
5712 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5715 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5716 if (*s == REGISTER_PREFIX)
5719 if (is_space_char (*s))
5723 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5725 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5726 return (const reg_entry *) NULL;
5730 /* For naked regs, make sure that we are not dealing with an identifier.
5731 This prevents confusing an identifier like `eax_var' with register
5733 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5734 return (const reg_entry *) NULL;
5738 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5740 /* Handle floating point regs, allowing spaces in the (i) part. */
5741 if (r == i386_regtab /* %st is first entry of table */)
5743 if (is_space_char (*s))
5748 if (is_space_char (*s))
5750 if (*s >= '0' && *s <= '7')
5752 r = &i386_float_regtab[*s - '0'];
5754 if (is_space_char (*s))
5762 /* We have "%st(" then garbage. */
5763 return (const reg_entry *) NULL;
5768 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5769 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5770 && flag_code != CODE_64BIT)
5771 return (const reg_entry *) NULL;
5776 /* REG_STRING starts *before* REGISTER_PREFIX. */
5778 static const reg_entry *
5779 parse_register (char *reg_string, char **end_op)
5783 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5784 r = parse_real_register (reg_string, end_op);
5789 char *save = input_line_pointer;
5793 input_line_pointer = reg_string;
5794 c = get_symbol_end ();
5795 symbolP = symbol_find (reg_string);
5796 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5798 const expressionS *e = symbol_get_value_expression (symbolP);
5800 know (e->X_op == O_register);
5801 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5802 r = i386_regtab + e->X_add_number;
5803 *end_op = input_line_pointer;
5805 *input_line_pointer = c;
5806 input_line_pointer = save;
5812 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5815 char *end = input_line_pointer;
5818 r = parse_register (name, &input_line_pointer);
5819 if (r && end <= input_line_pointer)
5821 *nextcharP = *input_line_pointer;
5822 *input_line_pointer = 0;
5823 e->X_op = O_register;
5824 e->X_add_number = r - i386_regtab;
5827 input_line_pointer = end;
5833 md_operand (expressionS *e)
5835 if (*input_line_pointer == REGISTER_PREFIX)
5838 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5842 e->X_op = O_register;
5843 e->X_add_number = r - i386_regtab;
5844 input_line_pointer = end;
5850 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5851 const char *md_shortopts = "kVQ:sqn";
5853 const char *md_shortopts = "qn";
5856 #define OPTION_32 (OPTION_MD_BASE + 0)
5857 #define OPTION_64 (OPTION_MD_BASE + 1)
5858 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5859 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5860 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5862 struct option md_longopts[] =
5864 {"32", no_argument, NULL, OPTION_32},
5865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5866 {"64", no_argument, NULL, OPTION_64},
5868 {"divide", no_argument, NULL, OPTION_DIVIDE},
5869 {"march", required_argument, NULL, OPTION_MARCH},
5870 {"mtune", required_argument, NULL, OPTION_MTUNE},
5871 {NULL, no_argument, NULL, 0}
5873 size_t md_longopts_size = sizeof (md_longopts);
5876 md_parse_option (int c, char *arg)
5883 optimize_align_code = 0;
5890 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5891 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5892 should be emitted or not. FIXME: Not implemented. */
5896 /* -V: SVR4 argument to print version ID. */
5898 print_version_id ();
5901 /* -k: Ignore for FreeBSD compatibility. */
5906 /* -s: On i386 Solaris, this tells the native assembler to use
5907 .stab instead of .stab.excl. We always use .stab anyhow. */
5910 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5913 const char **list, **l;
5915 list = bfd_target_list ();
5916 for (l = list; *l != NULL; l++)
5917 if (CONST_STRNEQ (*l, "elf64-x86-64")
5918 || strcmp (*l, "coff-x86-64") == 0
5919 || strcmp (*l, "pe-x86-64") == 0
5920 || strcmp (*l, "pei-x86-64") == 0)
5922 default_arch = "x86_64";
5926 as_fatal (_("No compiled in support for x86_64"));
5933 default_arch = "i386";
5937 #ifdef SVR4_COMMENT_CHARS
5942 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5944 for (s = i386_comment_chars; *s != '\0'; s++)
5948 i386_comment_chars = n;
5955 as_fatal (_("Invalid -march= option: `%s'"), arg);
5956 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5958 if (strcmp (arg, cpu_arch [i].name) == 0)
5960 cpu_arch_isa = cpu_arch[i].type;
5961 cpu_arch_isa_flags = cpu_arch[i].flags;
5962 if (!cpu_arch_tune_set)
5964 cpu_arch_tune = cpu_arch_isa;
5965 cpu_arch_tune_flags = cpu_arch_isa_flags;
5970 if (i >= ARRAY_SIZE (cpu_arch))
5971 as_fatal (_("Invalid -march= option: `%s'"), arg);
5976 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5977 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5979 if (strcmp (arg, cpu_arch [i].name) == 0)
5981 cpu_arch_tune_set = 1;
5982 cpu_arch_tune = cpu_arch [i].type;
5983 cpu_arch_tune_flags = cpu_arch[i].flags;
5987 if (i >= ARRAY_SIZE (cpu_arch))
5988 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5998 md_show_usage (stream)
6001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6002 fprintf (stream, _("\
6004 -V print assembler version number\n\
6007 fprintf (stream, _("\
6008 -n Do not optimize code alignment\n\
6009 -q quieten some warnings\n"));
6010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6011 fprintf (stream, _("\
6014 #ifdef SVR4_COMMENT_CHARS
6015 fprintf (stream, _("\
6016 --divide do not treat `/' as a comment character\n"));
6018 fprintf (stream, _("\
6019 --divide ignored\n"));
6021 fprintf (stream, _("\
6022 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6023 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6024 core, core2, k6, athlon, k8, generic32, generic64\n"));
6030 x86_64_target_format (void)
6032 if (strcmp (default_arch, "x86_64") == 0)
6034 set_code_flag (CODE_64BIT);
6035 return COFF_TARGET_FORMAT;
6037 else if (strcmp (default_arch, "i386") == 0)
6039 set_code_flag (CODE_32BIT);
6043 as_fatal (_("Unknown architecture"));
6048 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6049 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6051 /* Pick the target format to use. */
6054 i386_target_format ()
6056 if (!strcmp (default_arch, "x86_64"))
6058 set_code_flag (CODE_64BIT);
6059 if (cpu_arch_isa_flags == 0)
6060 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6061 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6063 if (cpu_arch_tune_flags == 0)
6064 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6065 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6068 else if (!strcmp (default_arch, "i386"))
6070 set_code_flag (CODE_32BIT);
6071 if (cpu_arch_isa_flags == 0)
6072 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6073 if (cpu_arch_tune_flags == 0)
6074 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6077 as_fatal (_("Unknown architecture"));
6078 switch (OUTPUT_FLAVOR)
6080 #ifdef OBJ_MAYBE_AOUT
6081 case bfd_target_aout_flavour:
6082 return AOUT_TARGET_FORMAT;
6084 #ifdef OBJ_MAYBE_COFF
6085 case bfd_target_coff_flavour:
6088 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6089 case bfd_target_elf_flavour:
6091 if (flag_code == CODE_64BIT)
6094 use_rela_relocations = 1;
6096 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6105 #endif /* OBJ_MAYBE_ more than one */
6107 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6108 void i386_elf_emit_arch_note ()
6110 if (IS_ELF && cpu_arch_name != NULL)
6113 asection *seg = now_seg;
6114 subsegT subseg = now_subseg;
6115 Elf_Internal_Note i_note;
6116 Elf_External_Note e_note;
6117 asection *note_secp;
6120 /* Create the .note section. */
6121 note_secp = subseg_new (".note", 0);
6122 bfd_set_section_flags (stdoutput,
6124 SEC_HAS_CONTENTS | SEC_READONLY);
6126 /* Process the arch string. */
6127 len = strlen (cpu_arch_name);
6129 i_note.namesz = len + 1;
6131 i_note.type = NT_ARCH;
6132 p = frag_more (sizeof (e_note.namesz));
6133 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6134 p = frag_more (sizeof (e_note.descsz));
6135 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6136 p = frag_more (sizeof (e_note.type));
6137 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6138 p = frag_more (len + 1);
6139 strcpy (p, cpu_arch_name);
6141 frag_align (2, 0, 0);
6143 subseg_set (seg, subseg);
6149 md_undefined_symbol (name)
6152 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6153 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6154 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6155 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6159 if (symbol_find (name))
6160 as_bad (_("GOT already in symbol table"));
6161 GOT_symbol = symbol_new (name, undefined_section,
6162 (valueT) 0, &zero_address_frag);
6169 /* Round up a section size to the appropriate boundary. */
6172 md_section_align (segment, size)
6173 segT segment ATTRIBUTE_UNUSED;
6176 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6177 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6179 /* For a.out, force the section size to be aligned. If we don't do
6180 this, BFD will align it for us, but it will not write out the
6181 final bytes of the section. This may be a bug in BFD, but it is
6182 easier to fix it here since that is how the other a.out targets
6186 align = bfd_get_section_alignment (stdoutput, segment);
6187 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6194 /* On the i386, PC-relative offsets are relative to the start of the
6195 next instruction. That is, the address of the offset, plus its
6196 size, since the offset is always the last part of the insn. */
6199 md_pcrel_from (fixP)
6202 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6209 int ignore ATTRIBUTE_UNUSED;
6213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6215 obj_elf_section_change_hook ();
6217 temp = get_absolute_expression ();
6218 subseg_set (bss_section, (subsegT) temp);
6219 demand_empty_rest_of_line ();
6225 i386_validate_fix (fixp)
6228 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6230 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6234 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6239 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6241 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6248 tc_gen_reloc (section, fixp)
6249 asection *section ATTRIBUTE_UNUSED;
6253 bfd_reloc_code_real_type code;
6255 switch (fixp->fx_r_type)
6257 case BFD_RELOC_X86_64_PLT32:
6258 case BFD_RELOC_X86_64_GOT32:
6259 case BFD_RELOC_X86_64_GOTPCREL:
6260 case BFD_RELOC_386_PLT32:
6261 case BFD_RELOC_386_GOT32:
6262 case BFD_RELOC_386_GOTOFF:
6263 case BFD_RELOC_386_GOTPC:
6264 case BFD_RELOC_386_TLS_GD:
6265 case BFD_RELOC_386_TLS_LDM:
6266 case BFD_RELOC_386_TLS_LDO_32:
6267 case BFD_RELOC_386_TLS_IE_32:
6268 case BFD_RELOC_386_TLS_IE:
6269 case BFD_RELOC_386_TLS_GOTIE:
6270 case BFD_RELOC_386_TLS_LE_32:
6271 case BFD_RELOC_386_TLS_LE:
6272 case BFD_RELOC_386_TLS_GOTDESC:
6273 case BFD_RELOC_386_TLS_DESC_CALL:
6274 case BFD_RELOC_X86_64_TLSGD:
6275 case BFD_RELOC_X86_64_TLSLD:
6276 case BFD_RELOC_X86_64_DTPOFF32:
6277 case BFD_RELOC_X86_64_DTPOFF64:
6278 case BFD_RELOC_X86_64_GOTTPOFF:
6279 case BFD_RELOC_X86_64_TPOFF32:
6280 case BFD_RELOC_X86_64_TPOFF64:
6281 case BFD_RELOC_X86_64_GOTOFF64:
6282 case BFD_RELOC_X86_64_GOTPC32:
6283 case BFD_RELOC_X86_64_GOT64:
6284 case BFD_RELOC_X86_64_GOTPCREL64:
6285 case BFD_RELOC_X86_64_GOTPC64:
6286 case BFD_RELOC_X86_64_GOTPLT64:
6287 case BFD_RELOC_X86_64_PLTOFF64:
6288 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6289 case BFD_RELOC_X86_64_TLSDESC_CALL:
6291 case BFD_RELOC_VTABLE_ENTRY:
6292 case BFD_RELOC_VTABLE_INHERIT:
6294 case BFD_RELOC_32_SECREL:
6296 code = fixp->fx_r_type;
6298 case BFD_RELOC_X86_64_32S:
6299 if (!fixp->fx_pcrel)
6301 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6302 code = fixp->fx_r_type;
6308 switch (fixp->fx_size)
6311 as_bad_where (fixp->fx_file, fixp->fx_line,
6312 _("can not do %d byte pc-relative relocation"),
6314 code = BFD_RELOC_32_PCREL;
6316 case 1: code = BFD_RELOC_8_PCREL; break;
6317 case 2: code = BFD_RELOC_16_PCREL; break;
6318 case 4: code = BFD_RELOC_32_PCREL; break;
6320 case 8: code = BFD_RELOC_64_PCREL; break;
6326 switch (fixp->fx_size)
6329 as_bad_where (fixp->fx_file, fixp->fx_line,
6330 _("can not do %d byte relocation"),
6332 code = BFD_RELOC_32;
6334 case 1: code = BFD_RELOC_8; break;
6335 case 2: code = BFD_RELOC_16; break;
6336 case 4: code = BFD_RELOC_32; break;
6338 case 8: code = BFD_RELOC_64; break;
6345 if ((code == BFD_RELOC_32
6346 || code == BFD_RELOC_32_PCREL
6347 || code == BFD_RELOC_X86_64_32S)
6349 && fixp->fx_addsy == GOT_symbol)
6352 code = BFD_RELOC_386_GOTPC;
6354 code = BFD_RELOC_X86_64_GOTPC32;
6356 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6358 && fixp->fx_addsy == GOT_symbol)
6360 code = BFD_RELOC_X86_64_GOTPC64;
6363 rel = (arelent *) xmalloc (sizeof (arelent));
6364 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6365 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6367 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6369 if (!use_rela_relocations)
6371 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6372 vtable entry to be used in the relocation's section offset. */
6373 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6374 rel->address = fixp->fx_offset;
6378 /* Use the rela in 64bit mode. */
6381 if (!fixp->fx_pcrel)
6382 rel->addend = fixp->fx_offset;
6386 case BFD_RELOC_X86_64_PLT32:
6387 case BFD_RELOC_X86_64_GOT32:
6388 case BFD_RELOC_X86_64_GOTPCREL:
6389 case BFD_RELOC_X86_64_TLSGD:
6390 case BFD_RELOC_X86_64_TLSLD:
6391 case BFD_RELOC_X86_64_GOTTPOFF:
6392 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6393 case BFD_RELOC_X86_64_TLSDESC_CALL:
6394 rel->addend = fixp->fx_offset - fixp->fx_size;
6397 rel->addend = (section->vma
6399 + fixp->fx_addnumber
6400 + md_pcrel_from (fixp));
6405 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6406 if (rel->howto == NULL)
6408 as_bad_where (fixp->fx_file, fixp->fx_line,
6409 _("cannot represent relocation type %s"),
6410 bfd_get_reloc_code_name (code));
6411 /* Set howto to a garbage value so that we can keep going. */
6412 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6413 assert (rel->howto != NULL);
6420 /* Parse operands using Intel syntax. This implements a recursive descent
6421 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6424 FIXME: We do not recognize the full operand grammar defined in the MASM
6425 documentation. In particular, all the structure/union and
6426 high-level macro operands are missing.
6428 Uppercase words are terminals, lower case words are non-terminals.
6429 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6430 bars '|' denote choices. Most grammar productions are implemented in
6431 functions called 'intel_<production>'.
6433 Initial production is 'expr'.
6439 binOp & | AND | \| | OR | ^ | XOR
6441 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6443 constant digits [[ radixOverride ]]
6445 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6483 => expr expr cmpOp e04
6486 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6487 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6489 hexdigit a | b | c | d | e | f
6490 | A | B | C | D | E | F
6496 mulOp * | / | % | MOD | << | SHL | >> | SHR
6500 register specialRegister
6504 segmentRegister CS | DS | ES | FS | GS | SS
6506 specialRegister CR0 | CR2 | CR3 | CR4
6507 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6508 | TR3 | TR4 | TR5 | TR6 | TR7
6510 We simplify the grammar in obvious places (e.g., register parsing is
6511 done by calling parse_register) and eliminate immediate left recursion
6512 to implement a recursive-descent parser.
6516 expr' cmpOp e04 expr'
6567 /* Parsing structure for the intel syntax parser. Used to implement the
6568 semantic actions for the operand grammar. */
6569 struct intel_parser_s
6571 char *op_string; /* The string being parsed. */
6572 int got_a_float; /* Whether the operand is a float. */
6573 int op_modifier; /* Operand modifier. */
6574 int is_mem; /* 1 if operand is memory reference. */
6575 int in_offset; /* >=1 if parsing operand of offset. */
6576 int in_bracket; /* >=1 if parsing operand in brackets. */
6577 const reg_entry *reg; /* Last register reference found. */
6578 char *disp; /* Displacement string being built. */
6579 char *next_operand; /* Resume point when splitting operands. */
6582 static struct intel_parser_s intel_parser;
6584 /* Token structure for parsing intel syntax. */
6587 int code; /* Token code. */
6588 const reg_entry *reg; /* Register entry for register tokens. */
6589 char *str; /* String representation. */
6592 static struct intel_token cur_token, prev_token;
6594 /* Token codes for the intel parser. Since T_SHORT is already used
6595 by COFF, undefine it first to prevent a warning. */
6614 /* Prototypes for intel parser functions. */
6615 static int intel_match_token PARAMS ((int code));
6616 static void intel_get_token PARAMS ((void));
6617 static void intel_putback_token PARAMS ((void));
6618 static int intel_expr PARAMS ((void));
6619 static int intel_e04 PARAMS ((void));
6620 static int intel_e05 PARAMS ((void));
6621 static int intel_e06 PARAMS ((void));
6622 static int intel_e09 PARAMS ((void));
6623 static int intel_bracket_expr PARAMS ((void));
6624 static int intel_e10 PARAMS ((void));
6625 static int intel_e11 PARAMS ((void));
6628 i386_intel_operand (operand_string, got_a_float)
6629 char *operand_string;
6635 p = intel_parser.op_string = xstrdup (operand_string);
6636 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6640 /* Initialize token holders. */
6641 cur_token.code = prev_token.code = T_NIL;
6642 cur_token.reg = prev_token.reg = NULL;
6643 cur_token.str = prev_token.str = NULL;
6645 /* Initialize parser structure. */
6646 intel_parser.got_a_float = got_a_float;
6647 intel_parser.op_modifier = 0;
6648 intel_parser.is_mem = 0;
6649 intel_parser.in_offset = 0;
6650 intel_parser.in_bracket = 0;
6651 intel_parser.reg = NULL;
6652 intel_parser.disp[0] = '\0';
6653 intel_parser.next_operand = NULL;
6655 /* Read the first token and start the parser. */
6657 ret = intel_expr ();
6662 if (cur_token.code != T_NIL)
6664 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6665 current_templates->start->name, cur_token.str);
6668 /* If we found a memory reference, hand it over to i386_displacement
6669 to fill in the rest of the operand fields. */
6670 else if (intel_parser.is_mem)
6672 if ((i.mem_operands == 1
6673 && (current_templates->start->opcode_modifier & IsString) == 0)
6674 || i.mem_operands == 2)
6676 as_bad (_("too many memory references for '%s'"),
6677 current_templates->start->name);
6682 char *s = intel_parser.disp;
6685 if (!quiet_warnings && intel_parser.is_mem < 0)
6686 /* See the comments in intel_bracket_expr. */
6687 as_warn (_("Treating `%s' as memory reference"), operand_string);
6689 /* Add the displacement expression. */
6691 ret = i386_displacement (s, s + strlen (s));
6694 /* Swap base and index in 16-bit memory operands like
6695 [si+bx]. Since i386_index_check is also used in AT&T
6696 mode we have to do that here. */
6699 && (i.base_reg->reg_type & Reg16)
6700 && (i.index_reg->reg_type & Reg16)
6701 && i.base_reg->reg_num >= 6
6702 && i.index_reg->reg_num < 6)
6704 const reg_entry *base = i.index_reg;
6706 i.index_reg = i.base_reg;
6709 ret = i386_index_check (operand_string);
6714 /* Constant and OFFSET expressions are handled by i386_immediate. */
6715 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6716 || intel_parser.reg == NULL)
6717 ret = i386_immediate (intel_parser.disp);
6719 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6721 if (!ret || !intel_parser.next_operand)
6723 intel_parser.op_string = intel_parser.next_operand;
6724 this_operand = i.operands++;
6728 free (intel_parser.disp);
6733 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6737 expr' cmpOp e04 expr'
6742 /* XXX Implement the comparison operators. */
6743 return intel_e04 ();
6760 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6761 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6763 if (cur_token.code == '+')
6765 else if (cur_token.code == '-')
6766 nregs = NUM_ADDRESS_REGS;
6770 strcat (intel_parser.disp, cur_token.str);
6771 intel_match_token (cur_token.code);
6782 int nregs = ~NUM_ADDRESS_REGS;
6789 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6793 str[0] = cur_token.code;
6795 strcat (intel_parser.disp, str);
6800 intel_match_token (cur_token.code);
6805 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6806 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6817 int nregs = ~NUM_ADDRESS_REGS;
6824 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6828 str[0] = cur_token.code;
6830 strcat (intel_parser.disp, str);
6832 else if (cur_token.code == T_SHL)
6833 strcat (intel_parser.disp, "<<");
6834 else if (cur_token.code == T_SHR)
6835 strcat (intel_parser.disp, ">>");
6839 intel_match_token (cur_token.code);
6844 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6845 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6863 int nregs = ~NUM_ADDRESS_REGS;
6868 /* Don't consume constants here. */
6869 if (cur_token.code == '+' || cur_token.code == '-')
6871 /* Need to look one token ahead - if the next token
6872 is a constant, the current token is its sign. */
6875 intel_match_token (cur_token.code);
6876 next_code = cur_token.code;
6877 intel_putback_token ();
6878 if (next_code == T_CONST)
6882 /* e09 OFFSET e09 */
6883 if (cur_token.code == T_OFFSET)
6886 ++intel_parser.in_offset;
6890 else if (cur_token.code == T_SHORT)
6891 intel_parser.op_modifier |= 1 << T_SHORT;
6894 else if (cur_token.code == '+')
6895 strcat (intel_parser.disp, "+");
6900 else if (cur_token.code == '-' || cur_token.code == '~')
6906 str[0] = cur_token.code;
6908 strcat (intel_parser.disp, str);
6915 intel_match_token (cur_token.code);
6923 /* e09' PTR e10 e09' */
6924 if (cur_token.code == T_PTR)
6928 if (prev_token.code == T_BYTE)
6929 suffix = BYTE_MNEM_SUFFIX;
6931 else if (prev_token.code == T_WORD)
6933 if (current_templates->start->name[0] == 'l'
6934 && current_templates->start->name[2] == 's'
6935 && current_templates->start->name[3] == 0)
6936 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6937 else if (intel_parser.got_a_float == 2) /* "fi..." */
6938 suffix = SHORT_MNEM_SUFFIX;
6940 suffix = WORD_MNEM_SUFFIX;
6943 else if (prev_token.code == T_DWORD)
6945 if (current_templates->start->name[0] == 'l'
6946 && current_templates->start->name[2] == 's'
6947 && current_templates->start->name[3] == 0)
6948 suffix = WORD_MNEM_SUFFIX;
6949 else if (flag_code == CODE_16BIT
6950 && (current_templates->start->opcode_modifier
6951 & (Jump | JumpDword)))
6952 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6953 else if (intel_parser.got_a_float == 1) /* "f..." */
6954 suffix = SHORT_MNEM_SUFFIX;
6956 suffix = LONG_MNEM_SUFFIX;
6959 else if (prev_token.code == T_FWORD)
6961 if (current_templates->start->name[0] == 'l'
6962 && current_templates->start->name[2] == 's'
6963 && current_templates->start->name[3] == 0)
6964 suffix = LONG_MNEM_SUFFIX;
6965 else if (!intel_parser.got_a_float)
6967 if (flag_code == CODE_16BIT)
6968 add_prefix (DATA_PREFIX_OPCODE);
6969 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6972 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6975 else if (prev_token.code == T_QWORD)
6977 if (intel_parser.got_a_float == 1) /* "f..." */
6978 suffix = LONG_MNEM_SUFFIX;
6980 suffix = QWORD_MNEM_SUFFIX;
6983 else if (prev_token.code == T_TBYTE)
6985 if (intel_parser.got_a_float == 1)
6986 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6988 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6991 else if (prev_token.code == T_XMMWORD)
6993 /* XXX ignored for now, but accepted since gcc uses it */
6999 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7003 /* Operands for jump/call using 'ptr' notation denote absolute
7005 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7006 i.types[this_operand] |= JumpAbsolute;
7008 if (current_templates->start->base_opcode == 0x8d /* lea */)
7012 else if (i.suffix != suffix)
7014 as_bad (_("Conflicting operand modifiers"));
7020 /* e09' : e10 e09' */
7021 else if (cur_token.code == ':')
7023 if (prev_token.code != T_REG)
7025 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7026 segment/group identifier (which we don't have), using comma
7027 as the operand separator there is even less consistent, since
7028 there all branches only have a single operand. */
7029 if (this_operand != 0
7030 || intel_parser.in_offset
7031 || intel_parser.in_bracket
7032 || (!(current_templates->start->opcode_modifier
7033 & (Jump|JumpDword|JumpInterSegment))
7034 && !(current_templates->start->operand_types[0]
7036 return intel_match_token (T_NIL);
7037 /* Remember the start of the 2nd operand and terminate 1st
7039 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7040 another expression), but it gets at least the simplest case
7041 (a plain number or symbol on the left side) right. */
7042 intel_parser.next_operand = intel_parser.op_string;
7043 *--intel_parser.op_string = '\0';
7044 return intel_match_token (':');
7052 intel_match_token (cur_token.code);
7058 --intel_parser.in_offset;
7061 if (NUM_ADDRESS_REGS > nregs)
7063 as_bad (_("Invalid operand to `OFFSET'"));
7066 intel_parser.op_modifier |= 1 << T_OFFSET;
7069 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7070 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7075 intel_bracket_expr ()
7077 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7078 const char *start = intel_parser.op_string;
7081 if (i.op[this_operand].regs)
7082 return intel_match_token (T_NIL);
7084 intel_match_token ('[');
7086 /* Mark as a memory operand only if it's not already known to be an
7087 offset expression. If it's an offset expression, we need to keep
7089 if (!intel_parser.in_offset)
7091 ++intel_parser.in_bracket;
7093 /* Operands for jump/call inside brackets denote absolute addresses. */
7094 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7095 i.types[this_operand] |= JumpAbsolute;
7097 /* Unfortunately gas always diverged from MASM in a respect that can't
7098 be easily fixed without risking to break code sequences likely to be
7099 encountered (the testsuite even check for this): MASM doesn't consider
7100 an expression inside brackets unconditionally as a memory reference.
7101 When that is e.g. a constant, an offset expression, or the sum of the
7102 two, this is still taken as a constant load. gas, however, always
7103 treated these as memory references. As a compromise, we'll try to make
7104 offset expressions inside brackets work the MASM way (since that's
7105 less likely to be found in real world code), but make constants alone
7106 continue to work the traditional gas way. In either case, issue a
7108 intel_parser.op_modifier &= ~was_offset;
7111 strcat (intel_parser.disp, "[");
7113 /* Add a '+' to the displacement string if necessary. */
7114 if (*intel_parser.disp != '\0'
7115 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7116 strcat (intel_parser.disp, "+");
7119 && (len = intel_parser.op_string - start - 1,
7120 intel_match_token (']')))
7122 /* Preserve brackets when the operand is an offset expression. */
7123 if (intel_parser.in_offset)
7124 strcat (intel_parser.disp, "]");
7127 --intel_parser.in_bracket;
7128 if (i.base_reg || i.index_reg)
7129 intel_parser.is_mem = 1;
7130 if (!intel_parser.is_mem)
7132 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7133 /* Defer the warning until all of the operand was parsed. */
7134 intel_parser.is_mem = -1;
7135 else if (!quiet_warnings)
7136 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7139 intel_parser.op_modifier |= was_offset;
7156 while (cur_token.code == '[')
7158 if (!intel_bracket_expr ())
7183 switch (cur_token.code)
7187 intel_match_token ('(');
7188 strcat (intel_parser.disp, "(");
7190 if (intel_expr () && intel_match_token (')'))
7192 strcat (intel_parser.disp, ")");
7199 return intel_bracket_expr ();
7204 strcat (intel_parser.disp, cur_token.str);
7205 intel_match_token (cur_token.code);
7207 /* Mark as a memory operand only if it's not already known to be an
7208 offset expression. */
7209 if (!intel_parser.in_offset)
7210 intel_parser.is_mem = 1;
7217 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7219 intel_match_token (T_REG);
7221 /* Check for segment change. */
7222 if (cur_token.code == ':')
7224 if (!(reg->reg_type & (SReg2 | SReg3)))
7226 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7229 else if (i.seg[i.mem_operands])
7230 as_warn (_("Extra segment override ignored"));
7233 if (!intel_parser.in_offset)
7234 intel_parser.is_mem = 1;
7235 switch (reg->reg_num)
7238 i.seg[i.mem_operands] = &es;
7241 i.seg[i.mem_operands] = &cs;
7244 i.seg[i.mem_operands] = &ss;
7247 i.seg[i.mem_operands] = &ds;
7250 i.seg[i.mem_operands] = &fs;
7253 i.seg[i.mem_operands] = &gs;
7259 /* Not a segment register. Check for register scaling. */
7260 else if (cur_token.code == '*')
7262 if (!intel_parser.in_bracket)
7264 as_bad (_("Register scaling only allowed in memory operands"));
7268 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7269 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7270 else if (i.index_reg)
7271 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7273 /* What follows must be a valid scale. */
7274 intel_match_token ('*');
7276 i.types[this_operand] |= BaseIndex;
7278 /* Set the scale after setting the register (otherwise,
7279 i386_scale will complain) */
7280 if (cur_token.code == '+' || cur_token.code == '-')
7282 char *str, sign = cur_token.code;
7283 intel_match_token (cur_token.code);
7284 if (cur_token.code != T_CONST)
7286 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7290 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7291 strcpy (str + 1, cur_token.str);
7293 if (!i386_scale (str))
7297 else if (!i386_scale (cur_token.str))
7299 intel_match_token (cur_token.code);
7302 /* No scaling. If this is a memory operand, the register is either a
7303 base register (first occurrence) or an index register (second
7305 else if (intel_parser.in_bracket)
7310 else if (!i.index_reg)
7314 as_bad (_("Too many register references in memory operand"));
7318 i.types[this_operand] |= BaseIndex;
7321 /* It's neither base nor index. */
7322 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7324 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7325 i.op[this_operand].regs = reg;
7330 as_bad (_("Invalid use of register"));
7334 /* Since registers are not part of the displacement string (except
7335 when we're parsing offset operands), we may need to remove any
7336 preceding '+' from the displacement string. */
7337 if (*intel_parser.disp != '\0'
7338 && !intel_parser.in_offset)
7340 char *s = intel_parser.disp;
7341 s += strlen (s) - 1;
7364 intel_match_token (cur_token.code);
7366 if (cur_token.code == T_PTR)
7369 /* It must have been an identifier. */
7370 intel_putback_token ();
7371 cur_token.code = T_ID;
7377 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7381 /* The identifier represents a memory reference only if it's not
7382 preceded by an offset modifier and if it's not an equate. */
7383 symbolP = symbol_find(cur_token.str);
7384 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7385 intel_parser.is_mem = 1;
7393 char *save_str, sign = 0;
7395 /* Allow constants that start with `+' or `-'. */
7396 if (cur_token.code == '-' || cur_token.code == '+')
7398 sign = cur_token.code;
7399 intel_match_token (cur_token.code);
7400 if (cur_token.code != T_CONST)
7402 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7408 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7409 strcpy (save_str + !!sign, cur_token.str);
7413 /* Get the next token to check for register scaling. */
7414 intel_match_token (cur_token.code);
7416 /* Check if this constant is a scaling factor for an index register. */
7417 if (cur_token.code == '*')
7419 if (intel_match_token ('*') && cur_token.code == T_REG)
7421 const reg_entry *reg = cur_token.reg;
7423 if (!intel_parser.in_bracket)
7425 as_bad (_("Register scaling only allowed in memory operands"));
7429 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7430 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7431 else if (i.index_reg)
7432 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7434 /* The constant is followed by `* reg', so it must be
7437 i.types[this_operand] |= BaseIndex;
7439 /* Set the scale after setting the register (otherwise,
7440 i386_scale will complain) */
7441 if (!i386_scale (save_str))
7443 intel_match_token (T_REG);
7445 /* Since registers are not part of the displacement
7446 string, we may need to remove any preceding '+' from
7447 the displacement string. */
7448 if (*intel_parser.disp != '\0')
7450 char *s = intel_parser.disp;
7451 s += strlen (s) - 1;
7461 /* The constant was not used for register scaling. Since we have
7462 already consumed the token following `*' we now need to put it
7463 back in the stream. */
7464 intel_putback_token ();
7467 /* Add the constant to the displacement string. */
7468 strcat (intel_parser.disp, save_str);
7475 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7479 /* Match the given token against cur_token. If they match, read the next
7480 token from the operand string. */
7482 intel_match_token (code)
7485 if (cur_token.code == code)
7492 as_bad (_("Unexpected token `%s'"), cur_token.str);
7497 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7502 const reg_entry *reg;
7503 struct intel_token new_token;
7505 new_token.code = T_NIL;
7506 new_token.reg = NULL;
7507 new_token.str = NULL;
7509 /* Free the memory allocated to the previous token and move
7510 cur_token to prev_token. */
7512 free (prev_token.str);
7514 prev_token = cur_token;
7516 /* Skip whitespace. */
7517 while (is_space_char (*intel_parser.op_string))
7518 intel_parser.op_string++;
7520 /* Return an empty token if we find nothing else on the line. */
7521 if (*intel_parser.op_string == '\0')
7523 cur_token = new_token;
7527 /* The new token cannot be larger than the remainder of the operand
7529 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7530 new_token.str[0] = '\0';
7532 if (strchr ("0123456789", *intel_parser.op_string))
7534 char *p = new_token.str;
7535 char *q = intel_parser.op_string;
7536 new_token.code = T_CONST;
7538 /* Allow any kind of identifier char to encompass floating point and
7539 hexadecimal numbers. */
7540 while (is_identifier_char (*q))
7544 /* Recognize special symbol names [0-9][bf]. */
7545 if (strlen (intel_parser.op_string) == 2
7546 && (intel_parser.op_string[1] == 'b'
7547 || intel_parser.op_string[1] == 'f'))
7548 new_token.code = T_ID;
7551 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7553 size_t len = end_op - intel_parser.op_string;
7555 new_token.code = T_REG;
7556 new_token.reg = reg;
7558 memcpy (new_token.str, intel_parser.op_string, len);
7559 new_token.str[len] = '\0';
7562 else if (is_identifier_char (*intel_parser.op_string))
7564 char *p = new_token.str;
7565 char *q = intel_parser.op_string;
7567 /* A '.' or '$' followed by an identifier char is an identifier.
7568 Otherwise, it's operator '.' followed by an expression. */
7569 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7571 new_token.code = '.';
7572 new_token.str[0] = '.';
7573 new_token.str[1] = '\0';
7577 while (is_identifier_char (*q) || *q == '@')
7581 if (strcasecmp (new_token.str, "NOT") == 0)
7582 new_token.code = '~';
7584 else if (strcasecmp (new_token.str, "MOD") == 0)
7585 new_token.code = '%';
7587 else if (strcasecmp (new_token.str, "AND") == 0)
7588 new_token.code = '&';
7590 else if (strcasecmp (new_token.str, "OR") == 0)
7591 new_token.code = '|';
7593 else if (strcasecmp (new_token.str, "XOR") == 0)
7594 new_token.code = '^';
7596 else if (strcasecmp (new_token.str, "SHL") == 0)
7597 new_token.code = T_SHL;
7599 else if (strcasecmp (new_token.str, "SHR") == 0)
7600 new_token.code = T_SHR;
7602 else if (strcasecmp (new_token.str, "BYTE") == 0)
7603 new_token.code = T_BYTE;
7605 else if (strcasecmp (new_token.str, "WORD") == 0)
7606 new_token.code = T_WORD;
7608 else if (strcasecmp (new_token.str, "DWORD") == 0)
7609 new_token.code = T_DWORD;
7611 else if (strcasecmp (new_token.str, "FWORD") == 0)
7612 new_token.code = T_FWORD;
7614 else if (strcasecmp (new_token.str, "QWORD") == 0)
7615 new_token.code = T_QWORD;
7617 else if (strcasecmp (new_token.str, "TBYTE") == 0
7618 /* XXX remove (gcc still uses it) */
7619 || strcasecmp (new_token.str, "XWORD") == 0)
7620 new_token.code = T_TBYTE;
7622 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7623 || strcasecmp (new_token.str, "OWORD") == 0)
7624 new_token.code = T_XMMWORD;
7626 else if (strcasecmp (new_token.str, "PTR") == 0)
7627 new_token.code = T_PTR;
7629 else if (strcasecmp (new_token.str, "SHORT") == 0)
7630 new_token.code = T_SHORT;
7632 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7634 new_token.code = T_OFFSET;
7636 /* ??? This is not mentioned in the MASM grammar but gcc
7637 makes use of it with -mintel-syntax. OFFSET may be
7638 followed by FLAT: */
7639 if (strncasecmp (q, " FLAT:", 6) == 0)
7640 strcat (new_token.str, " FLAT:");
7643 /* ??? This is not mentioned in the MASM grammar. */
7644 else if (strcasecmp (new_token.str, "FLAT") == 0)
7646 new_token.code = T_OFFSET;
7648 strcat (new_token.str, ":");
7650 as_bad (_("`:' expected"));
7654 new_token.code = T_ID;
7658 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7660 new_token.code = *intel_parser.op_string;
7661 new_token.str[0] = *intel_parser.op_string;
7662 new_token.str[1] = '\0';
7665 else if (strchr ("<>", *intel_parser.op_string)
7666 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7668 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7669 new_token.str[0] = *intel_parser.op_string;
7670 new_token.str[1] = *intel_parser.op_string;
7671 new_token.str[2] = '\0';
7675 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7677 intel_parser.op_string += strlen (new_token.str);
7678 cur_token = new_token;
7681 /* Put cur_token back into the token stream and make cur_token point to
7684 intel_putback_token ()
7686 if (cur_token.code != T_NIL)
7688 intel_parser.op_string -= strlen (cur_token.str);
7689 free (cur_token.str);
7691 cur_token = prev_token;
7693 /* Forget prev_token. */
7694 prev_token.code = T_NIL;
7695 prev_token.reg = NULL;
7696 prev_token.str = NULL;
7700 tc_x86_regname_to_dw2regnum (char *regname)
7702 unsigned int regnum;
7703 unsigned int regnames_count;
7704 static const char *const regnames_32[] =
7706 "eax", "ecx", "edx", "ebx",
7707 "esp", "ebp", "esi", "edi",
7708 "eip", "eflags", NULL,
7709 "st0", "st1", "st2", "st3",
7710 "st4", "st5", "st6", "st7",
7712 "xmm0", "xmm1", "xmm2", "xmm3",
7713 "xmm4", "xmm5", "xmm6", "xmm7",
7714 "mm0", "mm1", "mm2", "mm3",
7715 "mm4", "mm5", "mm6", "mm7",
7716 "fcw", "fsw", "mxcsr",
7717 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7720 static const char *const regnames_64[] =
7722 "rax", "rdx", "rcx", "rbx",
7723 "rsi", "rdi", "rbp", "rsp",
7724 "r8", "r9", "r10", "r11",
7725 "r12", "r13", "r14", "r15",
7727 "xmm0", "xmm1", "xmm2", "xmm3",
7728 "xmm4", "xmm5", "xmm6", "xmm7",
7729 "xmm8", "xmm9", "xmm10", "xmm11",
7730 "xmm12", "xmm13", "xmm14", "xmm15",
7731 "st0", "st1", "st2", "st3",
7732 "st4", "st5", "st6", "st7",
7733 "mm0", "mm1", "mm2", "mm3",
7734 "mm4", "mm5", "mm6", "mm7",
7736 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7737 "fs.base", "gs.base", NULL, NULL,
7739 "mxcsr", "fcw", "fsw"
7741 const char *const *regnames;
7743 if (flag_code == CODE_64BIT)
7745 regnames = regnames_64;
7746 regnames_count = ARRAY_SIZE (regnames_64);
7750 regnames = regnames_32;
7751 regnames_count = ARRAY_SIZE (regnames_32);
7754 for (regnum = 0; regnum < regnames_count; regnum++)
7755 if (regnames[regnum] != NULL
7756 && strcmp (regname, regnames[regnum]) == 0)
7763 tc_x86_frame_initial_instructions (void)
7765 static unsigned int sp_regno;
7768 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7771 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7772 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7776 i386_elf_section_type (const char *str, size_t len)
7778 if (flag_code == CODE_64BIT
7779 && len == sizeof ("unwind") - 1
7780 && strncmp (str, "unwind", 6) == 0)
7781 return SHT_X86_64_UNWIND;
7788 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7792 expr.X_op = O_secrel;
7793 expr.X_add_symbol = symbol;
7794 expr.X_add_number = 0;
7795 emit_expr (&expr, size);
7799 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7800 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7803 x86_64_section_letter (int letter, char **ptr_msg)
7805 if (flag_code == CODE_64BIT)
7808 return SHF_X86_64_LARGE;
7810 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7813 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7818 x86_64_section_word (char *str, size_t len)
7820 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7821 return SHF_X86_64_LARGE;
7827 handle_large_common (int small ATTRIBUTE_UNUSED)
7829 if (flag_code != CODE_64BIT)
7831 s_comm_internal (0, elf_common_parse);
7832 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7836 static segT lbss_section;
7837 asection *saved_com_section_ptr = elf_com_section_ptr;
7838 asection *saved_bss_section = bss_section;
7840 if (lbss_section == NULL)
7842 flagword applicable;
7844 subsegT subseg = now_subseg;
7846 /* The .lbss section is for local .largecomm symbols. */
7847 lbss_section = subseg_new (".lbss", 0);
7848 applicable = bfd_applicable_section_flags (stdoutput);
7849 bfd_set_section_flags (stdoutput, lbss_section,
7850 applicable & SEC_ALLOC);
7851 seg_info (lbss_section)->bss = 1;
7853 subseg_set (seg, subseg);
7856 elf_com_section_ptr = &_bfd_elf_large_com_section;
7857 bss_section = lbss_section;
7859 s_comm_internal (0, elf_common_parse);
7861 elf_com_section_ptr = saved_com_section_ptr;
7862 bss_section = saved_bss_section;
7865 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */