1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
268 unsupported_with_intel_mnemonic,
271 invalid_vsib_address,
272 invalid_vector_register_set,
273 unsupported_vector_index_register,
274 unsupported_broadcast,
277 mask_not_on_destination,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types[MAX_OPERANDS];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op[MAX_OPERANDS];
309 /* Flags for operands. */
310 unsigned int flags[MAX_OPERANDS];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry *base_reg;
319 const reg_entry *index_reg;
320 unsigned int log2_scale_factor;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry *seg[2];
326 /* Copied first memory operand string, for re-checking. */
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation *mask;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
354 /* Prefer load or store in encoding. */
357 dir_encoding_default = 0,
362 /* Prefer 8bit or 32bit displacement in encoding. */
365 disp_encoding_default = 0,
370 /* Prefer the REX byte in encoding. */
371 bfd_boolean rex_encoding;
373 /* Disable instruction size optimization. */
374 bfd_boolean no_optimize;
376 /* How to encode vector instructions. */
379 vex_encoding_default = 0,
386 const char *rep_prefix;
389 const char *hle_prefix;
391 /* Have BND prefix. */
392 const char *bnd_prefix;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix;
398 enum i386_error error;
401 typedef struct _i386_insn i386_insn;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable[] =
414 { rne, STRING_COMMA_LEN ("rn-sae") },
415 { rd, STRING_COMMA_LEN ("rd-sae") },
416 { ru, STRING_COMMA_LEN ("ru-sae") },
417 { rz, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars = "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars = "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars[] = "#/";
462 const char line_separator_chars[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars[256];
475 static char register_chars[256];
476 static char operand_chars[256];
477 static char identifier_chars[256];
478 static char digit_chars[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack[32];
496 static char *save_stack_p;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates *current_templates;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
510 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
512 /* Current operand we are working on. */
513 static int this_operand = -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code;
524 static unsigned int object_64bit;
525 static unsigned int disallow_64bit_reloc;
526 static int use_rela_relocations = 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi = I386_ABI;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj = 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared = 0;
553 /* 1 for intel syntax,
555 static int intel_syntax = 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic = !SYSV386_COMPAT;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix = 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592 static enum check_kind
598 sse_check, operand_check = check_warning;
601 1. Clear the REX_W bit with register operand if possible.
602 2. Above plus use 128bit vector instruction to clear the full vector
605 static int optimize = 0;
608 1. Clear the REX_W bit with register operand if possible.
609 2. Above plus use 128bit vector instruction to clear the full vector
611 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
614 static int optimize_for_space = 0;
616 /* Register prefix used for error message. */
617 static const char *register_prefix = "%";
619 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
620 leave, push, and pop instructions so that gcc has the same stack
621 frame as in 32 bit mode. */
622 static char stackop_size = '\0';
624 /* Non-zero to optimize code alignment. */
625 int optimize_align_code = 1;
627 /* Non-zero to quieten some warnings. */
628 static int quiet_warnings = 0;
631 static const char *cpu_arch_name = NULL;
632 static char *cpu_sub_arch_name = NULL;
634 /* CPU feature flags. */
635 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
637 /* If we have selected a cpu we are generating instructions for. */
638 static int cpu_arch_tune_set = 0;
640 /* Cpu we are generating instructions for. */
641 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
643 /* CPU feature flags of cpu we are generating instructions for. */
644 static i386_cpu_flags cpu_arch_tune_flags;
646 /* CPU instruction set architecture used. */
647 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
649 /* CPU feature flags of instruction set architecture used. */
650 i386_cpu_flags cpu_arch_isa_flags;
652 /* If set, conditional jumps are not automatically promoted to handle
653 larger than a byte offset. */
654 static unsigned int no_cond_jump_promotion = 0;
656 /* Encode SSE instructions with VEX prefix. */
657 static unsigned int sse2avx;
659 /* Encode scalar AVX instructions with specific vector length. */
666 /* Encode scalar EVEX LIG instructions with specific vector length. */
674 /* Encode EVEX WIG instructions with specific evex.w. */
681 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
682 static enum rc_type evexrcig = rne;
684 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
685 static symbolS *GOT_symbol;
687 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
688 unsigned int x86_dwarf2_return_column;
690 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
691 int x86_cie_data_alignment;
693 /* Interface to relax_segment.
694 There are 3 major relax states for 386 jump insns because the
695 different types of jumps add different sizes to frags when we're
696 figuring out what sort of jump to choose to reach a given label. */
699 #define UNCOND_JUMP 0
701 #define COND_JUMP86 2
706 #define SMALL16 (SMALL | CODE16)
708 #define BIG16 (BIG | CODE16)
712 #define INLINE __inline__
718 #define ENCODE_RELAX_STATE(type, size) \
719 ((relax_substateT) (((type) << 2) | (size)))
720 #define TYPE_FROM_RELAX_STATE(s) \
722 #define DISP_SIZE_FROM_RELAX_STATE(s) \
723 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
725 /* This table is used by relax_frag to promote short jumps to long
726 ones where necessary. SMALL (short) jumps may be promoted to BIG
727 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
728 don't allow a short jump in a 32 bit code segment to be promoted to
729 a 16 bit offset jump because it's slower (requires data size
730 prefix), and doesn't work, unless the destination is in the bottom
731 64k of the code segment (The top 16 bits of eip are zeroed). */
733 const relax_typeS md_relax_table[] =
736 1) most positive reach of this state,
737 2) most negative reach of this state,
738 3) how many bytes this mode will have in the variable part of the frag
739 4) which index into the table to try if we can't fit into this one. */
741 /* UNCOND_JUMP states. */
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
744 /* dword jmp adds 4 bytes to frag:
745 0 extra opcode bytes, 4 displacement bytes. */
747 /* word jmp adds 2 byte2 to frag:
748 0 extra opcode bytes, 2 displacement bytes. */
751 /* COND_JUMP states. */
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
754 /* dword conditionals adds 5 bytes to frag:
755 1 extra opcode byte, 4 displacement bytes. */
757 /* word conditionals add 3 bytes to frag:
758 1 extra opcode byte, 2 displacement bytes. */
761 /* COND_JUMP86 states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
764 /* dword conditionals adds 5 bytes to frag:
765 1 extra opcode byte, 4 displacement bytes. */
767 /* word conditionals add 4 bytes to frag:
768 1 displacement byte and a 3 byte long branch insn. */
772 static const arch_entry cpu_arch[] =
774 /* Do not replace the first two entries - i386_target_format()
775 relies on them being there in this order. */
776 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
777 CPU_GENERIC32_FLAGS, 0 },
778 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
779 CPU_GENERIC64_FLAGS, 0 },
780 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
786 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
788 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
790 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
792 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
794 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
796 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
797 CPU_PENTIUMPRO_FLAGS, 0 },
798 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
802 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
804 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
806 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
807 CPU_NOCONA_FLAGS, 0 },
808 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
812 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 1 },
814 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
815 CPU_CORE2_FLAGS, 0 },
816 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
817 CPU_COREI7_FLAGS, 0 },
818 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
820 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
822 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
823 CPU_IAMCU_FLAGS, 0 },
824 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
828 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
829 CPU_ATHLON_FLAGS, 0 },
830 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
836 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
837 CPU_AMDFAM10_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
839 CPU_BDVER1_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
841 CPU_BDVER2_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
843 CPU_BDVER3_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
845 CPU_BDVER4_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
847 CPU_ZNVER1_FLAGS, 0 },
848 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
849 CPU_ZNVER2_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
851 CPU_BTVER1_FLAGS, 0 },
852 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
853 CPU_BTVER2_FLAGS, 0 },
854 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
870 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
871 CPU_SSSE3_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_1_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_2_FLAGS, 0 },
878 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
882 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
883 CPU_AVX512F_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
885 CPU_AVX512CD_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
887 CPU_AVX512ER_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
889 CPU_AVX512PF_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
891 CPU_AVX512DQ_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
893 CPU_AVX512BW_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
895 CPU_AVX512VL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
899 CPU_VMFUNC_FLAGS, 0 },
900 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
903 CPU_XSAVE_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEOPT_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
907 CPU_XSAVEC_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
909 CPU_XSAVES_FLAGS, 0 },
910 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
912 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 0 },
914 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
915 CPU_PCLMUL_FLAGS, 1 },
916 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
917 CPU_FSGSBASE_FLAGS, 0 },
918 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
919 CPU_RDRND_FLAGS, 0 },
920 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
933 CPU_MOVBE_FLAGS, 0 },
934 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
938 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
939 CPU_LZCNT_FLAGS, 0 },
940 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
944 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
945 CPU_INVPCID_FLAGS, 0 },
946 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
947 CPU_CLFLUSH_FLAGS, 0 },
948 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
950 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
951 CPU_SYSCALL_FLAGS, 0 },
952 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
953 CPU_RDTSCP_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
955 CPU_3DNOW_FLAGS, 0 },
956 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
957 CPU_3DNOWA_FLAGS, 0 },
958 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
959 CPU_PADLOCK_FLAGS, 0 },
960 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
965 CPU_SSE4A_FLAGS, 0 },
966 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
975 CPU_RDSEED_FLAGS, 0 },
976 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
977 CPU_PRFCHW_FLAGS, 0 },
978 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
985 CPU_CLFLUSHOPT_FLAGS, 0 },
986 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
987 CPU_PREFETCHWT1_FLAGS, 0 },
988 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
992 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
993 CPU_AVX512IFMA_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
995 CPU_AVX512VBMI_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4FMAPS_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_4VNNIW_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VBMI2_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VNNI_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_BITALG_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1009 CPU_CLZERO_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1011 CPU_MWAITX_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1013 CPU_OSPKE_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1015 CPU_RDPID_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1017 CPU_PTWRITE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1020 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1021 CPU_SHSTK_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1023 CPU_GFNI_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1025 CPU_VAES_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1027 CPU_VPCLMULQDQ_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1029 CPU_WBNOINVD_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1031 CPU_PCONFIG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1033 CPU_WAITPKG_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1035 CPU_CLDEMOTE_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIRI_FLAGS, 0 },
1038 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1039 CPU_MOVDIR64B_FLAGS, 0 },
1042 static const noarch_entry cpu_noarch[] =
1044 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1045 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1046 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1047 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1048 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1049 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1050 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1052 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1055 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1056 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1057 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1071 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1072 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1073 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1074 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1075 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1076 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1080 /* Like s_lcomm_internal in gas/read.c but the alignment string
1081 is allowed to be optional. */
1084 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1091 && *input_line_pointer == ',')
1093 align = parse_align (needs_align - 1);
1095 if (align == (addressT) -1)
1110 bss_alloc (symbolP, size, align);
1115 pe_lcomm (int needs_align)
1117 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1121 const pseudo_typeS md_pseudo_table[] =
1123 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1124 {"align", s_align_bytes, 0},
1126 {"align", s_align_ptwo, 0},
1128 {"arch", set_cpu_arch, 0},
1132 {"lcomm", pe_lcomm, 1},
1134 {"ffloat", float_cons, 'f'},
1135 {"dfloat", float_cons, 'd'},
1136 {"tfloat", float_cons, 'x'},
1138 {"slong", signed_cons, 4},
1139 {"noopt", s_ignore, 0},
1140 {"optim", s_ignore, 0},
1141 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1142 {"code16", set_code_flag, CODE_16BIT},
1143 {"code32", set_code_flag, CODE_32BIT},
1145 {"code64", set_code_flag, CODE_64BIT},
1147 {"intel_syntax", set_intel_syntax, 1},
1148 {"att_syntax", set_intel_syntax, 0},
1149 {"intel_mnemonic", set_intel_mnemonic, 1},
1150 {"att_mnemonic", set_intel_mnemonic, 0},
1151 {"allow_index_reg", set_allow_index_reg, 1},
1152 {"disallow_index_reg", set_allow_index_reg, 0},
1153 {"sse_check", set_check, 0},
1154 {"operand_check", set_check, 1},
1155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1156 {"largecomm", handle_large_common, 0},
1158 {"file", dwarf2_directive_file, 0},
1159 {"loc", dwarf2_directive_loc, 0},
1160 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1163 {"secrel32", pe_directive_secrel, 0},
1168 /* For interface with expression (). */
1169 extern char *input_line_pointer;
1171 /* Hash table for instruction mnemonic lookup. */
1172 static struct hash_control *op_hash;
1174 /* Hash table for register lookup. */
1175 static struct hash_control *reg_hash;
1177 /* Various efficient no-op patterns for aligning code labels.
1178 Note: Don't try to assemble the instructions in the comments.
1179 0L and 0w are not legal. */
1180 static const unsigned char f32_1[] =
1182 static const unsigned char f32_2[] =
1183 {0x66,0x90}; /* xchg %ax,%ax */
1184 static const unsigned char f32_3[] =
1185 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1186 static const unsigned char f32_4[] =
1187 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1188 static const unsigned char f32_6[] =
1189 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1190 static const unsigned char f32_7[] =
1191 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1192 static const unsigned char f16_3[] =
1193 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1194 static const unsigned char f16_4[] =
1195 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1196 static const unsigned char jump_disp8[] =
1197 {0xeb}; /* jmp disp8 */
1198 static const unsigned char jump32_disp32[] =
1199 {0xe9}; /* jmp disp32 */
1200 static const unsigned char jump16_disp32[] =
1201 {0x66,0xe9}; /* jmp disp32 */
1202 /* 32-bit NOPs patterns. */
1203 static const unsigned char *const f32_patt[] = {
1204 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1206 /* 16-bit NOPs patterns. */
1207 static const unsigned char *const f16_patt[] = {
1208 f32_1, f32_2, f16_3, f16_4
1210 /* nopl (%[re]ax) */
1211 static const unsigned char alt_3[] =
1213 /* nopl 0(%[re]ax) */
1214 static const unsigned char alt_4[] =
1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_5[] =
1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_6[] =
1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
1223 static const unsigned char alt_7[] =
1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_8[] =
1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_9[] =
1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1232 static const unsigned char alt_10[] =
1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 /* data16 nopw %cs:0L(%eax,%eax,1) */
1235 static const unsigned char alt_11[] =
1236 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* 32-bit and 64-bit NOPs patterns. */
1238 static const unsigned char *const alt_patt[] = {
1239 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1240 alt_9, alt_10, alt_11
1243 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1244 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1247 i386_output_nops (char *where, const unsigned char *const *patt,
1248 int count, int max_single_nop_size)
1251 /* Place the longer NOP first. */
1254 const unsigned char *nops = patt[max_single_nop_size - 1];
1256 /* Use the smaller one if the requsted one isn't available. */
1259 max_single_nop_size--;
1260 nops = patt[max_single_nop_size - 1];
1263 last = count % max_single_nop_size;
1266 for (offset = 0; offset < count; offset += max_single_nop_size)
1267 memcpy (where + offset, nops, max_single_nop_size);
1271 nops = patt[last - 1];
1274 /* Use the smaller one plus one-byte NOP if the needed one
1277 nops = patt[last - 1];
1278 memcpy (where + offset, nops, last);
1279 where[offset + last] = *patt[0];
1282 memcpy (where + offset, nops, last);
1287 fits_in_imm7 (offsetT num)
1289 return (num & 0x7f) == num;
1293 fits_in_imm31 (offsetT num)
1295 return (num & 0x7fffffff) == num;
1298 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1299 single NOP instruction LIMIT. */
1302 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1304 const unsigned char *const *patt = NULL;
1305 int max_single_nop_size;
1306 /* Maximum number of NOPs before switching to jump over NOPs. */
1307 int max_number_of_nops;
1309 switch (fragP->fr_type)
1318 /* We need to decide which NOP sequence to use for 32bit and
1319 64bit. When -mtune= is used:
1321 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1322 PROCESSOR_GENERIC32, f32_patt will be used.
1323 2. For the rest, alt_patt will be used.
1325 When -mtune= isn't used, alt_patt will be used if
1326 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1329 When -march= or .arch is used, we can't use anything beyond
1330 cpu_arch_isa_flags. */
1332 if (flag_code == CODE_16BIT)
1335 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1336 /* Limit number of NOPs to 2 in 16-bit mode. */
1337 max_number_of_nops = 2;
1341 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1343 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1344 switch (cpu_arch_tune)
1346 case PROCESSOR_UNKNOWN:
1347 /* We use cpu_arch_isa_flags to check if we SHOULD
1348 optimize with nops. */
1349 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1354 case PROCESSOR_PENTIUM4:
1355 case PROCESSOR_NOCONA:
1356 case PROCESSOR_CORE:
1357 case PROCESSOR_CORE2:
1358 case PROCESSOR_COREI7:
1359 case PROCESSOR_L1OM:
1360 case PROCESSOR_K1OM:
1361 case PROCESSOR_GENERIC64:
1363 case PROCESSOR_ATHLON:
1365 case PROCESSOR_AMDFAM10:
1367 case PROCESSOR_ZNVER:
1371 case PROCESSOR_I386:
1372 case PROCESSOR_I486:
1373 case PROCESSOR_PENTIUM:
1374 case PROCESSOR_PENTIUMPRO:
1375 case PROCESSOR_IAMCU:
1376 case PROCESSOR_GENERIC32:
1383 switch (fragP->tc_frag_data.tune)
1385 case PROCESSOR_UNKNOWN:
1386 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1387 PROCESSOR_UNKNOWN. */
1391 case PROCESSOR_I386:
1392 case PROCESSOR_I486:
1393 case PROCESSOR_PENTIUM:
1394 case PROCESSOR_IAMCU:
1396 case PROCESSOR_ATHLON:
1398 case PROCESSOR_AMDFAM10:
1400 case PROCESSOR_ZNVER:
1402 case PROCESSOR_GENERIC32:
1403 /* We use cpu_arch_isa_flags to check if we CAN optimize
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 case PROCESSOR_PENTIUMPRO:
1411 case PROCESSOR_PENTIUM4:
1412 case PROCESSOR_NOCONA:
1413 case PROCESSOR_CORE:
1414 case PROCESSOR_CORE2:
1415 case PROCESSOR_COREI7:
1416 case PROCESSOR_L1OM:
1417 case PROCESSOR_K1OM:
1418 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1423 case PROCESSOR_GENERIC64:
1429 if (patt == f32_patt)
1431 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1432 /* Limit number of NOPs to 2 for older processors. */
1433 max_number_of_nops = 2;
1437 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1438 /* Limit number of NOPs to 7 for newer processors. */
1439 max_number_of_nops = 7;
1444 limit = max_single_nop_size;
1446 if (fragP->fr_type == rs_fill_nop)
1448 /* Output NOPs for .nop directive. */
1449 if (limit > max_single_nop_size)
1451 as_bad_where (fragP->fr_file, fragP->fr_line,
1452 _("invalid single nop size: %d "
1453 "(expect within [0, %d])"),
1454 limit, max_single_nop_size);
1459 fragP->fr_var = count;
1461 if ((count / max_single_nop_size) > max_number_of_nops)
1463 /* Generate jump over NOPs. */
1464 offsetT disp = count - 2;
1465 if (fits_in_imm7 (disp))
1467 /* Use "jmp disp8" if possible. */
1469 where[0] = jump_disp8[0];
1475 unsigned int size_of_jump;
1477 if (flag_code == CODE_16BIT)
1479 where[0] = jump16_disp32[0];
1480 where[1] = jump16_disp32[1];
1485 where[0] = jump32_disp32[0];
1489 count -= size_of_jump + 4;
1490 if (!fits_in_imm31 (count))
1492 as_bad_where (fragP->fr_file, fragP->fr_line,
1493 _("jump over nop padding out of range"));
1497 md_number_to_chars (where + size_of_jump, count, 4);
1498 where += size_of_jump + 4;
1502 /* Generate multiple NOPs. */
1503 i386_output_nops (where, patt, count, limit);
1507 operand_type_all_zero (const union i386_operand_type *x)
1509 switch (ARRAY_SIZE(x->array))
1520 return !x->array[0];
1527 operand_type_set (union i386_operand_type *x, unsigned int v)
1529 switch (ARRAY_SIZE(x->array))
1547 operand_type_equal (const union i386_operand_type *x,
1548 const union i386_operand_type *y)
1550 switch (ARRAY_SIZE(x->array))
1553 if (x->array[2] != y->array[2])
1557 if (x->array[1] != y->array[1])
1561 return x->array[0] == y->array[0];
1569 cpu_flags_all_zero (const union i386_cpu_flags *x)
1571 switch (ARRAY_SIZE(x->array))
1586 return !x->array[0];
1593 cpu_flags_equal (const union i386_cpu_flags *x,
1594 const union i386_cpu_flags *y)
1596 switch (ARRAY_SIZE(x->array))
1599 if (x->array[3] != y->array[3])
1603 if (x->array[2] != y->array[2])
1607 if (x->array[1] != y->array[1])
1611 return x->array[0] == y->array[0];
1619 cpu_flags_check_cpu64 (i386_cpu_flags f)
1621 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1622 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1625 static INLINE i386_cpu_flags
1626 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1628 switch (ARRAY_SIZE (x.array))
1631 x.array [3] &= y.array [3];
1634 x.array [2] &= y.array [2];
1637 x.array [1] &= y.array [1];
1640 x.array [0] &= y.array [0];
1648 static INLINE i386_cpu_flags
1649 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1651 switch (ARRAY_SIZE (x.array))
1654 x.array [3] |= y.array [3];
1657 x.array [2] |= y.array [2];
1660 x.array [1] |= y.array [1];
1663 x.array [0] |= y.array [0];
1671 static INLINE i386_cpu_flags
1672 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1674 switch (ARRAY_SIZE (x.array))
1677 x.array [3] &= ~y.array [3];
1680 x.array [2] &= ~y.array [2];
1683 x.array [1] &= ~y.array [1];
1686 x.array [0] &= ~y.array [0];
1694 #define CPU_FLAGS_ARCH_MATCH 0x1
1695 #define CPU_FLAGS_64BIT_MATCH 0x2
1697 #define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1700 /* Return CPU flags match bits. */
1703 cpu_flags_match (const insn_template *t)
1705 i386_cpu_flags x = t->cpu_flags;
1706 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1708 x.bitfield.cpu64 = 0;
1709 x.bitfield.cpuno64 = 0;
1711 if (cpu_flags_all_zero (&x))
1713 /* This instruction is available on all archs. */
1714 match |= CPU_FLAGS_ARCH_MATCH;
1718 /* This instruction is available only on some archs. */
1719 i386_cpu_flags cpu = cpu_arch_flags;
1721 /* AVX512VL is no standalone feature - match it and then strip it. */
1722 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1724 x.bitfield.cpuavx512vl = 0;
1726 cpu = cpu_flags_and (x, cpu);
1727 if (!cpu_flags_all_zero (&cpu))
1729 if (x.bitfield.cpuavx)
1731 /* We need to check a few extra flags with AVX. */
1732 if (cpu.bitfield.cpuavx
1733 && (!t->opcode_modifier.sse2avx || sse2avx)
1734 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1735 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1736 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1737 match |= CPU_FLAGS_ARCH_MATCH;
1739 else if (x.bitfield.cpuavx512f)
1741 /* We need to check a few extra flags with AVX512F. */
1742 if (cpu.bitfield.cpuavx512f
1743 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1744 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1745 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1746 match |= CPU_FLAGS_ARCH_MATCH;
1749 match |= CPU_FLAGS_ARCH_MATCH;
1755 static INLINE i386_operand_type
1756 operand_type_and (i386_operand_type x, i386_operand_type y)
1758 switch (ARRAY_SIZE (x.array))
1761 x.array [2] &= y.array [2];
1764 x.array [1] &= y.array [1];
1767 x.array [0] &= y.array [0];
1775 static INLINE i386_operand_type
1776 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1778 switch (ARRAY_SIZE (x.array))
1781 x.array [2] &= ~y.array [2];
1784 x.array [1] &= ~y.array [1];
1787 x.array [0] &= ~y.array [0];
1795 static INLINE i386_operand_type
1796 operand_type_or (i386_operand_type x, i386_operand_type y)
1798 switch (ARRAY_SIZE (x.array))
1801 x.array [2] |= y.array [2];
1804 x.array [1] |= y.array [1];
1807 x.array [0] |= y.array [0];
1815 static INLINE i386_operand_type
1816 operand_type_xor (i386_operand_type x, i386_operand_type y)
1818 switch (ARRAY_SIZE (x.array))
1821 x.array [2] ^= y.array [2];
1824 x.array [1] ^= y.array [1];
1827 x.array [0] ^= y.array [0];
1835 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1836 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1837 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1838 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1839 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1840 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1841 static const i386_operand_type anydisp
1842 = OPERAND_TYPE_ANYDISP;
1843 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1844 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1845 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1846 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1847 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1848 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1849 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1850 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1851 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1852 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1853 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1854 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1865 operand_type_check (i386_operand_type t, enum operand_type c)
1870 return t.bitfield.reg;
1873 return (t.bitfield.imm8
1877 || t.bitfield.imm32s
1878 || t.bitfield.imm64);
1881 return (t.bitfield.disp8
1882 || t.bitfield.disp16
1883 || t.bitfield.disp32
1884 || t.bitfield.disp32s
1885 || t.bitfield.disp64);
1888 return (t.bitfield.disp8
1889 || t.bitfield.disp16
1890 || t.bitfield.disp32
1891 || t.bitfield.disp32s
1892 || t.bitfield.disp64
1893 || t.bitfield.baseindex);
1902 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1903 between operand GIVEN and opeand WANTED for instruction template T. */
1906 match_operand_size (const insn_template *t, unsigned int wanted,
1909 return !((i.types[given].bitfield.byte
1910 && !t->operand_types[wanted].bitfield.byte)
1911 || (i.types[given].bitfield.word
1912 && !t->operand_types[wanted].bitfield.word)
1913 || (i.types[given].bitfield.dword
1914 && !t->operand_types[wanted].bitfield.dword)
1915 || (i.types[given].bitfield.qword
1916 && !t->operand_types[wanted].bitfield.qword)
1917 || (i.types[given].bitfield.tbyte
1918 && !t->operand_types[wanted].bitfield.tbyte));
1921 /* Return 1 if there is no conflict in SIMD register between operand
1922 GIVEN and opeand WANTED for instruction template T. */
1925 match_simd_size (const insn_template *t, unsigned int wanted,
1928 return !((i.types[given].bitfield.xmmword
1929 && !t->operand_types[wanted].bitfield.xmmword)
1930 || (i.types[given].bitfield.ymmword
1931 && !t->operand_types[wanted].bitfield.ymmword)
1932 || (i.types[given].bitfield.zmmword
1933 && !t->operand_types[wanted].bitfield.zmmword));
1936 /* Return 1 if there is no conflict in any size between operand GIVEN
1937 and opeand WANTED for instruction template T. */
1940 match_mem_size (const insn_template *t, unsigned int wanted,
1943 return (match_operand_size (t, wanted, given)
1944 && !((i.types[given].bitfield.unspecified
1946 && !t->operand_types[wanted].bitfield.unspecified)
1947 || (i.types[given].bitfield.fword
1948 && !t->operand_types[wanted].bitfield.fword)
1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1953 || ((t->operand_types[wanted].bitfield.regsimd
1954 && !t->opcode_modifier.broadcast
1955 && (t->operand_types[wanted].bitfield.byte
1956 || t->operand_types[wanted].bitfield.word
1957 || t->operand_types[wanted].bitfield.dword
1958 || t->operand_types[wanted].bitfield.qword))
1959 ? (i.types[given].bitfield.xmmword
1960 || i.types[given].bitfield.ymmword
1961 || i.types[given].bitfield.zmmword)
1962 : !match_simd_size(t, wanted, given))));
1965 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1966 operands for instruction template T, and it has MATCH_REVERSE set if there
1967 is no size conflict on any operands for the template with operands reversed
1968 (and the template allows for reversing in the first place). */
1970 #define MATCH_STRAIGHT 1
1971 #define MATCH_REVERSE 2
1973 static INLINE unsigned int
1974 operand_size_match (const insn_template *t)
1976 unsigned int j, match = MATCH_STRAIGHT;
1978 /* Don't check jump instructions. */
1979 if (t->opcode_modifier.jump
1980 || t->opcode_modifier.jumpbyte
1981 || t->opcode_modifier.jumpdword
1982 || t->opcode_modifier.jumpintersegment)
1985 /* Check memory and accumulator operand size. */
1986 for (j = 0; j < i.operands; j++)
1988 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1989 && t->operand_types[j].bitfield.anysize)
1992 if (t->operand_types[j].bitfield.reg
1993 && !match_operand_size (t, j, j))
1999 if (t->operand_types[j].bitfield.regsimd
2000 && !match_simd_size (t, j, j))
2006 if (t->operand_types[j].bitfield.acc
2007 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2013 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2020 if (!t->opcode_modifier.d)
2024 i.error = operand_size_mismatch;
2028 /* Check reverse. */
2029 gas_assert (i.operands == 2);
2031 for (j = 0; j < 2; j++)
2033 if ((t->operand_types[j].bitfield.reg
2034 || t->operand_types[j].bitfield.acc)
2035 && !match_operand_size (t, j, !j))
2038 if (i.types[!j].bitfield.mem
2039 && !match_mem_size (t, j, !j))
2043 return match | MATCH_REVERSE;
2047 operand_type_match (i386_operand_type overlap,
2048 i386_operand_type given)
2050 i386_operand_type temp = overlap;
2052 temp.bitfield.jumpabsolute = 0;
2053 temp.bitfield.unspecified = 0;
2054 temp.bitfield.byte = 0;
2055 temp.bitfield.word = 0;
2056 temp.bitfield.dword = 0;
2057 temp.bitfield.fword = 0;
2058 temp.bitfield.qword = 0;
2059 temp.bitfield.tbyte = 0;
2060 temp.bitfield.xmmword = 0;
2061 temp.bitfield.ymmword = 0;
2062 temp.bitfield.zmmword = 0;
2063 if (operand_type_all_zero (&temp))
2066 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2067 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2071 i.error = operand_type_mismatch;
2075 /* If given types g0 and g1 are registers they must be of the same type
2076 unless the expected operand type register overlap is null.
2077 Memory operand size of certain SIMD instructions is also being checked
2081 operand_type_register_match (i386_operand_type g0,
2082 i386_operand_type t0,
2083 i386_operand_type g1,
2084 i386_operand_type t1)
2086 if (!g0.bitfield.reg
2087 && !g0.bitfield.regsimd
2088 && (!operand_type_check (g0, anymem)
2089 || g0.bitfield.unspecified
2090 || !t0.bitfield.regsimd))
2093 if (!g1.bitfield.reg
2094 && !g1.bitfield.regsimd
2095 && (!operand_type_check (g1, anymem)
2096 || g1.bitfield.unspecified
2097 || !t1.bitfield.regsimd))
2100 if (g0.bitfield.byte == g1.bitfield.byte
2101 && g0.bitfield.word == g1.bitfield.word
2102 && g0.bitfield.dword == g1.bitfield.dword
2103 && g0.bitfield.qword == g1.bitfield.qword
2104 && g0.bitfield.xmmword == g1.bitfield.xmmword
2105 && g0.bitfield.ymmword == g1.bitfield.ymmword
2106 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2109 if (!(t0.bitfield.byte & t1.bitfield.byte)
2110 && !(t0.bitfield.word & t1.bitfield.word)
2111 && !(t0.bitfield.dword & t1.bitfield.dword)
2112 && !(t0.bitfield.qword & t1.bitfield.qword)
2113 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2114 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2115 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2118 i.error = register_type_mismatch;
2123 static INLINE unsigned int
2124 register_number (const reg_entry *r)
2126 unsigned int nr = r->reg_num;
2128 if (r->reg_flags & RegRex)
2131 if (r->reg_flags & RegVRex)
2137 static INLINE unsigned int
2138 mode_from_disp_size (i386_operand_type t)
2140 if (t.bitfield.disp8)
2142 else if (t.bitfield.disp16
2143 || t.bitfield.disp32
2144 || t.bitfield.disp32s)
2151 fits_in_signed_byte (addressT num)
2153 return num + 0x80 <= 0xff;
2157 fits_in_unsigned_byte (addressT num)
2163 fits_in_unsigned_word (addressT num)
2165 return num <= 0xffff;
2169 fits_in_signed_word (addressT num)
2171 return num + 0x8000 <= 0xffff;
2175 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2180 return num + 0x80000000 <= 0xffffffff;
2182 } /* fits_in_signed_long() */
2185 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2190 return num <= 0xffffffff;
2192 } /* fits_in_unsigned_long() */
2195 fits_in_disp8 (offsetT num)
2197 int shift = i.memshift;
2203 mask = (1 << shift) - 1;
2205 /* Return 0 if NUM isn't properly aligned. */
2209 /* Check if NUM will fit in 8bit after shift. */
2210 return fits_in_signed_byte (num >> shift);
2214 fits_in_imm4 (offsetT num)
2216 return (num & 0xf) == num;
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num)
2222 i386_operand_type t;
2224 operand_type_set (&t, 0);
2225 t.bitfield.imm64 = 1;
2227 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2234 t.bitfield.imm1 = 1;
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm8s = 1;
2237 t.bitfield.imm16 = 1;
2238 t.bitfield.imm32 = 1;
2239 t.bitfield.imm32s = 1;
2241 else if (fits_in_signed_byte (num))
2243 t.bitfield.imm8 = 1;
2244 t.bitfield.imm8s = 1;
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2249 else if (fits_in_unsigned_byte (num))
2251 t.bitfield.imm8 = 1;
2252 t.bitfield.imm16 = 1;
2253 t.bitfield.imm32 = 1;
2254 t.bitfield.imm32s = 1;
2256 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2258 t.bitfield.imm16 = 1;
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2262 else if (fits_in_signed_long (num))
2264 t.bitfield.imm32 = 1;
2265 t.bitfield.imm32s = 1;
2267 else if (fits_in_unsigned_long (num))
2268 t.bitfield.imm32 = 1;
2274 offset_in_range (offsetT val, int size)
2280 case 1: mask = ((addressT) 1 << 8) - 1; break;
2281 case 2: mask = ((addressT) 1 << 16) - 1; break;
2282 case 4: mask = ((addressT) 2 << 31) - 1; break;
2284 case 8: mask = ((addressT) 2 << 63) - 1; break;
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code != CODE_64BIT
2292 || i.prefix[ADDR_PREFIX])
2293 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2294 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2297 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2299 char buf1[40], buf2[40];
2301 sprint_value (buf1, val);
2302 sprint_value (buf2, val & mask);
2303 as_warn (_("%s shortened to %s"), buf1, buf2);
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix)
2329 enum PREFIX_GROUP ret = PREFIX_OTHER;
2332 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2333 && flag_code == CODE_64BIT)
2335 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2336 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2337 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2338 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2349 case DS_PREFIX_OPCODE:
2352 case CS_PREFIX_OPCODE:
2353 case ES_PREFIX_OPCODE:
2354 case FS_PREFIX_OPCODE:
2355 case GS_PREFIX_OPCODE:
2356 case SS_PREFIX_OPCODE:
2360 case REPNE_PREFIX_OPCODE:
2361 case REPE_PREFIX_OPCODE:
2366 case LOCK_PREFIX_OPCODE:
2375 case ADDR_PREFIX_OPCODE:
2379 case DATA_PREFIX_OPCODE:
2383 if (i.prefix[q] != 0)
2391 i.prefix[q] |= prefix;
2394 as_bad (_("same type of prefix used twice"));
2400 update_code_flag (int value, int check)
2402 PRINTF_LIKE ((*as_error));
2404 flag_code = (enum flag_code) value;
2405 if (flag_code == CODE_64BIT)
2407 cpu_arch_flags.bitfield.cpu64 = 1;
2408 cpu_arch_flags.bitfield.cpuno64 = 0;
2412 cpu_arch_flags.bitfield.cpu64 = 0;
2413 cpu_arch_flags.bitfield.cpuno64 = 1;
2415 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2418 as_error = as_fatal;
2421 (*as_error) (_("64bit mode not supported on `%s'."),
2422 cpu_arch_name ? cpu_arch_name : default_arch);
2424 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2427 as_error = as_fatal;
2430 (*as_error) (_("32bit mode not supported on `%s'."),
2431 cpu_arch_name ? cpu_arch_name : default_arch);
2433 stackop_size = '\0';
2437 set_code_flag (int value)
2439 update_code_flag (value, 0);
2443 set_16bit_gcc_code_flag (int new_code_flag)
2445 flag_code = (enum flag_code) new_code_flag;
2446 if (flag_code != CODE_16BIT)
2448 cpu_arch_flags.bitfield.cpu64 = 0;
2449 cpu_arch_flags.bitfield.cpuno64 = 1;
2450 stackop_size = LONG_MNEM_SUFFIX;
2454 set_intel_syntax (int syntax_flag)
2456 /* Find out if register prefixing is specified. */
2457 int ask_naked_reg = 0;
2460 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2463 int e = get_symbol_name (&string);
2465 if (strcmp (string, "prefix") == 0)
2467 else if (strcmp (string, "noprefix") == 0)
2470 as_bad (_("bad argument to syntax directive."));
2471 (void) restore_line_pointer (e);
2473 demand_empty_rest_of_line ();
2475 intel_syntax = syntax_flag;
2477 if (ask_naked_reg == 0)
2478 allow_naked_reg = (intel_syntax
2479 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2481 allow_naked_reg = (ask_naked_reg < 0);
2483 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2485 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2486 identifier_chars['$'] = intel_syntax ? '$' : 0;
2487 register_prefix = allow_naked_reg ? "" : "%";
2491 set_intel_mnemonic (int mnemonic_flag)
2493 intel_mnemonic = mnemonic_flag;
2497 set_allow_index_reg (int flag)
2499 allow_index_reg = flag;
2503 set_check (int what)
2505 enum check_kind *kind;
2510 kind = &operand_check;
2521 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2524 int e = get_symbol_name (&string);
2526 if (strcmp (string, "none") == 0)
2528 else if (strcmp (string, "warning") == 0)
2529 *kind = check_warning;
2530 else if (strcmp (string, "error") == 0)
2531 *kind = check_error;
2533 as_bad (_("bad argument to %s_check directive."), str);
2534 (void) restore_line_pointer (e);
2537 as_bad (_("missing argument for %s_check directive"), str);
2539 demand_empty_rest_of_line ();
2543 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2544 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2547 static const char *arch;
2549 /* Intel LIOM is only supported on ELF. */
2555 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2556 use default_arch. */
2557 arch = cpu_arch_name;
2559 arch = default_arch;
2562 /* If we are targeting Intel MCU, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2564 || new_flag.bitfield.cpuiamcu)
2567 /* If we are targeting Intel L1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2569 || new_flag.bitfield.cpul1om)
2572 /* If we are targeting Intel K1OM, we must enable it. */
2573 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2574 || new_flag.bitfield.cpuk1om)
2577 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2582 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2586 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2589 int e = get_symbol_name (&string);
2591 i386_cpu_flags flags;
2593 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2595 if (strcmp (string, cpu_arch[j].name) == 0)
2597 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2601 cpu_arch_name = cpu_arch[j].name;
2602 cpu_sub_arch_name = NULL;
2603 cpu_arch_flags = cpu_arch[j].flags;
2604 if (flag_code == CODE_64BIT)
2606 cpu_arch_flags.bitfield.cpu64 = 1;
2607 cpu_arch_flags.bitfield.cpuno64 = 0;
2611 cpu_arch_flags.bitfield.cpu64 = 0;
2612 cpu_arch_flags.bitfield.cpuno64 = 1;
2614 cpu_arch_isa = cpu_arch[j].type;
2615 cpu_arch_isa_flags = cpu_arch[j].flags;
2616 if (!cpu_arch_tune_set)
2618 cpu_arch_tune = cpu_arch_isa;
2619 cpu_arch_tune_flags = cpu_arch_isa_flags;
2624 flags = cpu_flags_or (cpu_arch_flags,
2627 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2629 if (cpu_sub_arch_name)
2631 char *name = cpu_sub_arch_name;
2632 cpu_sub_arch_name = concat (name,
2634 (const char *) NULL);
2638 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2639 cpu_arch_flags = flags;
2640 cpu_arch_isa_flags = flags;
2644 = cpu_flags_or (cpu_arch_isa_flags,
2646 (void) restore_line_pointer (e);
2647 demand_empty_rest_of_line ();
2652 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2654 /* Disable an ISA extension. */
2655 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2656 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2658 flags = cpu_flags_and_not (cpu_arch_flags,
2659 cpu_noarch[j].flags);
2660 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2662 if (cpu_sub_arch_name)
2664 char *name = cpu_sub_arch_name;
2665 cpu_sub_arch_name = concat (name, string,
2666 (const char *) NULL);
2670 cpu_sub_arch_name = xstrdup (string);
2671 cpu_arch_flags = flags;
2672 cpu_arch_isa_flags = flags;
2674 (void) restore_line_pointer (e);
2675 demand_empty_rest_of_line ();
2679 j = ARRAY_SIZE (cpu_arch);
2682 if (j >= ARRAY_SIZE (cpu_arch))
2683 as_bad (_("no such architecture: `%s'"), string);
2685 *input_line_pointer = e;
2688 as_bad (_("missing cpu architecture"));
2690 no_cond_jump_promotion = 0;
2691 if (*input_line_pointer == ','
2692 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2697 ++input_line_pointer;
2698 e = get_symbol_name (&string);
2700 if (strcmp (string, "nojumps") == 0)
2701 no_cond_jump_promotion = 1;
2702 else if (strcmp (string, "jumps") == 0)
2705 as_bad (_("no such architecture modifier: `%s'"), string);
2707 (void) restore_line_pointer (e);
2710 demand_empty_rest_of_line ();
2713 enum bfd_architecture
2716 if (cpu_arch_isa == PROCESSOR_L1OM)
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code != CODE_64BIT)
2720 as_fatal (_("Intel L1OM is 64bit ELF only"));
2721 return bfd_arch_l1om;
2723 else if (cpu_arch_isa == PROCESSOR_K1OM)
2725 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2726 || flag_code != CODE_64BIT)
2727 as_fatal (_("Intel K1OM is 64bit ELF only"));
2728 return bfd_arch_k1om;
2730 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2732 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2733 || flag_code == CODE_64BIT)
2734 as_fatal (_("Intel MCU is 32bit ELF only"));
2735 return bfd_arch_iamcu;
2738 return bfd_arch_i386;
2744 if (!strncmp (default_arch, "x86_64", 6))
2746 if (cpu_arch_isa == PROCESSOR_L1OM)
2748 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2749 || default_arch[6] != '\0')
2750 as_fatal (_("Intel L1OM is 64bit ELF only"));
2751 return bfd_mach_l1om;
2753 else if (cpu_arch_isa == PROCESSOR_K1OM)
2755 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2756 || default_arch[6] != '\0')
2757 as_fatal (_("Intel K1OM is 64bit ELF only"));
2758 return bfd_mach_k1om;
2760 else if (default_arch[6] == '\0')
2761 return bfd_mach_x86_64;
2763 return bfd_mach_x64_32;
2765 else if (!strcmp (default_arch, "i386")
2766 || !strcmp (default_arch, "iamcu"))
2768 if (cpu_arch_isa == PROCESSOR_IAMCU)
2770 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2771 as_fatal (_("Intel MCU is 32bit ELF only"));
2772 return bfd_mach_i386_iamcu;
2775 return bfd_mach_i386_i386;
2778 as_fatal (_("unknown architecture"));
2784 const char *hash_err;
2786 /* Support pseudo prefixes like {disp32}. */
2787 lex_type ['{'] = LEX_BEGIN_NAME;
2789 /* Initialize op_hash hash table. */
2790 op_hash = hash_new ();
2793 const insn_template *optab;
2794 templates *core_optab;
2796 /* Setup for loop. */
2798 core_optab = XNEW (templates);
2799 core_optab->start = optab;
2804 if (optab->name == NULL
2805 || strcmp (optab->name, (optab - 1)->name) != 0)
2807 /* different name --> ship out current template list;
2808 add to hash table; & begin anew. */
2809 core_optab->end = optab;
2810 hash_err = hash_insert (op_hash,
2812 (void *) core_optab);
2815 as_fatal (_("can't hash %s: %s"),
2819 if (optab->name == NULL)
2821 core_optab = XNEW (templates);
2822 core_optab->start = optab;
2827 /* Initialize reg_hash hash table. */
2828 reg_hash = hash_new ();
2830 const reg_entry *regtab;
2831 unsigned int regtab_size = i386_regtab_size;
2833 for (regtab = i386_regtab; regtab_size--; regtab++)
2835 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2837 as_fatal (_("can't hash %s: %s"),
2843 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2848 for (c = 0; c < 256; c++)
2853 mnemonic_chars[c] = c;
2854 register_chars[c] = c;
2855 operand_chars[c] = c;
2857 else if (ISLOWER (c))
2859 mnemonic_chars[c] = c;
2860 register_chars[c] = c;
2861 operand_chars[c] = c;
2863 else if (ISUPPER (c))
2865 mnemonic_chars[c] = TOLOWER (c);
2866 register_chars[c] = mnemonic_chars[c];
2867 operand_chars[c] = c;
2869 else if (c == '{' || c == '}')
2871 mnemonic_chars[c] = c;
2872 operand_chars[c] = c;
2875 if (ISALPHA (c) || ISDIGIT (c))
2876 identifier_chars[c] = c;
2879 identifier_chars[c] = c;
2880 operand_chars[c] = c;
2885 identifier_chars['@'] = '@';
2888 identifier_chars['?'] = '?';
2889 operand_chars['?'] = '?';
2891 digit_chars['-'] = '-';
2892 mnemonic_chars['_'] = '_';
2893 mnemonic_chars['-'] = '-';
2894 mnemonic_chars['.'] = '.';
2895 identifier_chars['_'] = '_';
2896 identifier_chars['.'] = '.';
2898 for (p = operand_special_chars; *p != '\0'; p++)
2899 operand_chars[(unsigned char) *p] = *p;
2902 if (flag_code == CODE_64BIT)
2904 #if defined (OBJ_COFF) && defined (TE_PE)
2905 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2908 x86_dwarf2_return_column = 16;
2910 x86_cie_data_alignment = -8;
2914 x86_dwarf2_return_column = 8;
2915 x86_cie_data_alignment = -4;
2920 i386_print_statistics (FILE *file)
2922 hash_print_statistics (file, "i386 opcode", op_hash);
2923 hash_print_statistics (file, "i386 register", reg_hash);
2928 /* Debugging routines for md_assemble. */
2929 static void pte (insn_template *);
2930 static void pt (i386_operand_type);
2931 static void pe (expressionS *);
2932 static void ps (symbolS *);
2935 pi (char *line, i386_insn *x)
2939 fprintf (stdout, "%s: template ", line);
2941 fprintf (stdout, " address: base %s index %s scale %x\n",
2942 x->base_reg ? x->base_reg->reg_name : "none",
2943 x->index_reg ? x->index_reg->reg_name : "none",
2944 x->log2_scale_factor);
2945 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2946 x->rm.mode, x->rm.reg, x->rm.regmem);
2947 fprintf (stdout, " sib: base %x index %x scale %x\n",
2948 x->sib.base, x->sib.index, x->sib.scale);
2949 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2950 (x->rex & REX_W) != 0,
2951 (x->rex & REX_R) != 0,
2952 (x->rex & REX_X) != 0,
2953 (x->rex & REX_B) != 0);
2954 for (j = 0; j < x->operands; j++)
2956 fprintf (stdout, " #%d: ", j + 1);
2958 fprintf (stdout, "\n");
2959 if (x->types[j].bitfield.reg
2960 || x->types[j].bitfield.regmmx
2961 || x->types[j].bitfield.regsimd
2962 || x->types[j].bitfield.sreg2
2963 || x->types[j].bitfield.sreg3
2964 || x->types[j].bitfield.control
2965 || x->types[j].bitfield.debug
2966 || x->types[j].bitfield.test)
2967 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2968 if (operand_type_check (x->types[j], imm))
2970 if (operand_type_check (x->types[j], disp))
2971 pe (x->op[j].disps);
2976 pte (insn_template *t)
2979 fprintf (stdout, " %d operands ", t->operands);
2980 fprintf (stdout, "opcode %x ", t->base_opcode);
2981 if (t->extension_opcode != None)
2982 fprintf (stdout, "ext %x ", t->extension_opcode);
2983 if (t->opcode_modifier.d)
2984 fprintf (stdout, "D");
2985 if (t->opcode_modifier.w)
2986 fprintf (stdout, "W");
2987 fprintf (stdout, "\n");
2988 for (j = 0; j < t->operands; j++)
2990 fprintf (stdout, " #%d type ", j + 1);
2991 pt (t->operand_types[j]);
2992 fprintf (stdout, "\n");
2999 fprintf (stdout, " operation %d\n", e->X_op);
3000 fprintf (stdout, " add_number %ld (%lx)\n",
3001 (long) e->X_add_number, (long) e->X_add_number);
3002 if (e->X_add_symbol)
3004 fprintf (stdout, " add_symbol ");
3005 ps (e->X_add_symbol);
3006 fprintf (stdout, "\n");
3010 fprintf (stdout, " op_symbol ");
3011 ps (e->X_op_symbol);
3012 fprintf (stdout, "\n");
3019 fprintf (stdout, "%s type %s%s",
3021 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3022 segment_name (S_GET_SEGMENT (s)));
3025 static struct type_name
3027 i386_operand_type mask;
3030 const type_names[] =
3032 { OPERAND_TYPE_REG8, "r8" },
3033 { OPERAND_TYPE_REG16, "r16" },
3034 { OPERAND_TYPE_REG32, "r32" },
3035 { OPERAND_TYPE_REG64, "r64" },
3036 { OPERAND_TYPE_IMM8, "i8" },
3037 { OPERAND_TYPE_IMM8, "i8s" },
3038 { OPERAND_TYPE_IMM16, "i16" },
3039 { OPERAND_TYPE_IMM32, "i32" },
3040 { OPERAND_TYPE_IMM32S, "i32s" },
3041 { OPERAND_TYPE_IMM64, "i64" },
3042 { OPERAND_TYPE_IMM1, "i1" },
3043 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3044 { OPERAND_TYPE_DISP8, "d8" },
3045 { OPERAND_TYPE_DISP16, "d16" },
3046 { OPERAND_TYPE_DISP32, "d32" },
3047 { OPERAND_TYPE_DISP32S, "d32s" },
3048 { OPERAND_TYPE_DISP64, "d64" },
3049 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3050 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3051 { OPERAND_TYPE_CONTROL, "control reg" },
3052 { OPERAND_TYPE_TEST, "test reg" },
3053 { OPERAND_TYPE_DEBUG, "debug reg" },
3054 { OPERAND_TYPE_FLOATREG, "FReg" },
3055 { OPERAND_TYPE_FLOATACC, "FAcc" },
3056 { OPERAND_TYPE_SREG2, "SReg2" },
3057 { OPERAND_TYPE_SREG3, "SReg3" },
3058 { OPERAND_TYPE_ACC, "Acc" },
3059 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3060 { OPERAND_TYPE_REGMMX, "rMMX" },
3061 { OPERAND_TYPE_REGXMM, "rXMM" },
3062 { OPERAND_TYPE_REGYMM, "rYMM" },
3063 { OPERAND_TYPE_REGZMM, "rZMM" },
3064 { OPERAND_TYPE_REGMASK, "Mask reg" },
3065 { OPERAND_TYPE_ESSEG, "es" },
3069 pt (i386_operand_type t)
3072 i386_operand_type a;
3074 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3076 a = operand_type_and (t, type_names[j].mask);
3077 if (!operand_type_all_zero (&a))
3078 fprintf (stdout, "%s, ", type_names[j].name);
3083 #endif /* DEBUG386 */
3085 static bfd_reloc_code_real_type
3086 reloc (unsigned int size,
3089 bfd_reloc_code_real_type other)
3091 if (other != NO_RELOC)
3093 reloc_howto_type *rel;
3098 case BFD_RELOC_X86_64_GOT32:
3099 return BFD_RELOC_X86_64_GOT64;
3101 case BFD_RELOC_X86_64_GOTPLT64:
3102 return BFD_RELOC_X86_64_GOTPLT64;
3104 case BFD_RELOC_X86_64_PLTOFF64:
3105 return BFD_RELOC_X86_64_PLTOFF64;
3107 case BFD_RELOC_X86_64_GOTPC32:
3108 other = BFD_RELOC_X86_64_GOTPC64;
3110 case BFD_RELOC_X86_64_GOTPCREL:
3111 other = BFD_RELOC_X86_64_GOTPCREL64;
3113 case BFD_RELOC_X86_64_TPOFF32:
3114 other = BFD_RELOC_X86_64_TPOFF64;
3116 case BFD_RELOC_X86_64_DTPOFF32:
3117 other = BFD_RELOC_X86_64_DTPOFF64;
3123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3124 if (other == BFD_RELOC_SIZE32)
3127 other = BFD_RELOC_SIZE64;
3130 as_bad (_("there are no pc-relative size relocations"));
3136 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3137 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3140 rel = bfd_reloc_type_lookup (stdoutput, other);
3142 as_bad (_("unknown relocation (%u)"), other);
3143 else if (size != bfd_get_reloc_size (rel))
3144 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3145 bfd_get_reloc_size (rel),
3147 else if (pcrel && !rel->pc_relative)
3148 as_bad (_("non-pc-relative relocation for pc-relative field"));
3149 else if ((rel->complain_on_overflow == complain_overflow_signed
3151 || (rel->complain_on_overflow == complain_overflow_unsigned
3153 as_bad (_("relocated field and relocation type differ in signedness"));
3162 as_bad (_("there are no unsigned pc-relative relocations"));
3165 case 1: return BFD_RELOC_8_PCREL;
3166 case 2: return BFD_RELOC_16_PCREL;
3167 case 4: return BFD_RELOC_32_PCREL;
3168 case 8: return BFD_RELOC_64_PCREL;
3170 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3177 case 4: return BFD_RELOC_X86_64_32S;
3182 case 1: return BFD_RELOC_8;
3183 case 2: return BFD_RELOC_16;
3184 case 4: return BFD_RELOC_32;
3185 case 8: return BFD_RELOC_64;
3187 as_bad (_("cannot do %s %u byte relocation"),
3188 sign > 0 ? "signed" : "unsigned", size);
3194 /* Here we decide which fixups can be adjusted to make them relative to
3195 the beginning of the section instead of the symbol. Basically we need
3196 to make sure that the dynamic relocations are done correctly, so in
3197 some cases we force the original symbol to be used. */
3200 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3206 /* Don't adjust pc-relative references to merge sections in 64-bit
3208 if (use_rela_relocations
3209 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3213 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3214 and changed later by validate_fix. */
3215 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3216 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3219 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3220 for size relocations. */
3221 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3222 || fixP->fx_r_type == BFD_RELOC_SIZE64
3223 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3224 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3225 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3226 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3235 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3236 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3249 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3250 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3251 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3252 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3253 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3260 intel_float_operand (const char *mnemonic)
3262 /* Note that the value returned is meaningful only for opcodes with (memory)
3263 operands, hence the code here is free to improperly handle opcodes that
3264 have no operands (for better performance and smaller code). */
3266 if (mnemonic[0] != 'f')
3267 return 0; /* non-math */
3269 switch (mnemonic[1])
3271 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3272 the fs segment override prefix not currently handled because no
3273 call path can make opcodes without operands get here */
3275 return 2 /* integer op */;
3277 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3278 return 3; /* fldcw/fldenv */
3281 if (mnemonic[2] != 'o' /* fnop */)
3282 return 3; /* non-waiting control op */
3285 if (mnemonic[2] == 's')
3286 return 3; /* frstor/frstpm */
3289 if (mnemonic[2] == 'a')
3290 return 3; /* fsave */
3291 if (mnemonic[2] == 't')
3293 switch (mnemonic[3])
3295 case 'c': /* fstcw */
3296 case 'd': /* fstdw */
3297 case 'e': /* fstenv */
3298 case 's': /* fsts[gw] */
3304 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3305 return 0; /* fxsave/fxrstor are not really math ops */
3312 /* Build the VEX prefix. */
3315 build_vex_prefix (const insn_template *t)
3317 unsigned int register_specifier;
3318 unsigned int implied_prefix;
3319 unsigned int vector_length;
3321 /* Check register specifier. */
3322 if (i.vex.register_specifier)
3324 register_specifier =
3325 ~register_number (i.vex.register_specifier) & 0xf;
3326 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3329 register_specifier = 0xf;
3331 /* Use 2-byte VEX prefix by swapping destination and source
3333 if (i.vec_encoding != vex_encoding_vex3
3334 && i.dir_encoding == dir_encoding_default
3335 && i.operands == i.reg_operands
3336 && i.tm.opcode_modifier.vexopcode == VEX0F
3337 && i.tm.opcode_modifier.load
3340 unsigned int xchg = i.operands - 1;
3341 union i386_op temp_op;
3342 i386_operand_type temp_type;
3344 temp_type = i.types[xchg];
3345 i.types[xchg] = i.types[0];
3346 i.types[0] = temp_type;
3347 temp_op = i.op[xchg];
3348 i.op[xchg] = i.op[0];
3351 gas_assert (i.rm.mode == 3);
3355 i.rm.regmem = i.rm.reg;
3358 /* Use the next insn. */
3362 if (i.tm.opcode_modifier.vex == VEXScalar)
3363 vector_length = avxscalar;
3364 else if (i.tm.opcode_modifier.vex == VEX256)
3370 /* Determine vector length from the last multi-length vector
3373 for (op = t->operands; op--;)
3374 if (t->operand_types[op].bitfield.xmmword
3375 && t->operand_types[op].bitfield.ymmword
3376 && i.types[op].bitfield.ymmword)
3383 switch ((i.tm.base_opcode >> 8) & 0xff)
3388 case DATA_PREFIX_OPCODE:
3391 case REPE_PREFIX_OPCODE:
3394 case REPNE_PREFIX_OPCODE:
3401 /* Use 2-byte VEX prefix if possible. */
3402 if (i.vec_encoding != vex_encoding_vex3
3403 && i.tm.opcode_modifier.vexopcode == VEX0F
3404 && i.tm.opcode_modifier.vexw != VEXW1
3405 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3407 /* 2-byte VEX prefix. */
3411 i.vex.bytes[0] = 0xc5;
3413 /* Check the REX.R bit. */
3414 r = (i.rex & REX_R) ? 0 : 1;
3415 i.vex.bytes[1] = (r << 7
3416 | register_specifier << 3
3417 | vector_length << 2
3422 /* 3-byte VEX prefix. */
3427 switch (i.tm.opcode_modifier.vexopcode)
3431 i.vex.bytes[0] = 0xc4;
3435 i.vex.bytes[0] = 0xc4;
3439 i.vex.bytes[0] = 0xc4;
3443 i.vex.bytes[0] = 0x8f;
3447 i.vex.bytes[0] = 0x8f;
3451 i.vex.bytes[0] = 0x8f;
3457 /* The high 3 bits of the second VEX byte are 1's compliment
3458 of RXB bits from REX. */
3459 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3461 /* Check the REX.W bit. */
3462 w = (i.rex & REX_W) ? 1 : 0;
3463 if (i.tm.opcode_modifier.vexw == VEXW1)
3466 i.vex.bytes[2] = (w << 7
3467 | register_specifier << 3
3468 | vector_length << 2
3473 static INLINE bfd_boolean
3474 is_evex_encoding (const insn_template *t)
3476 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3477 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3478 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3481 static INLINE bfd_boolean
3482 is_any_vex_encoding (const insn_template *t)
3484 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3485 || is_evex_encoding (t);
3488 /* Build the EVEX prefix. */
3491 build_evex_prefix (void)
3493 unsigned int register_specifier;
3494 unsigned int implied_prefix;
3496 rex_byte vrex_used = 0;
3498 /* Check register specifier. */
3499 if (i.vex.register_specifier)
3501 gas_assert ((i.vrex & REX_X) == 0);
3503 register_specifier = i.vex.register_specifier->reg_num;
3504 if ((i.vex.register_specifier->reg_flags & RegRex))
3505 register_specifier += 8;
3506 /* The upper 16 registers are encoded in the fourth byte of the
3508 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3509 i.vex.bytes[3] = 0x8;
3510 register_specifier = ~register_specifier & 0xf;
3514 register_specifier = 0xf;
3516 /* Encode upper 16 vector index register in the fourth byte of
3518 if (!(i.vrex & REX_X))
3519 i.vex.bytes[3] = 0x8;
3524 switch ((i.tm.base_opcode >> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE:
3532 case REPE_PREFIX_OPCODE:
3535 case REPNE_PREFIX_OPCODE:
3542 /* 4 byte EVEX prefix. */
3544 i.vex.bytes[0] = 0x62;
3547 switch (i.tm.opcode_modifier.vexopcode)
3563 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3565 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3567 /* The fifth bit of the second EVEX byte is 1's compliment of the
3568 REX_R bit in VREX. */
3569 if (!(i.vrex & REX_R))
3570 i.vex.bytes[1] |= 0x10;
3574 if ((i.reg_operands + i.imm_operands) == i.operands)
3576 /* When all operands are registers, the REX_X bit in REX is not
3577 used. We reuse it to encode the upper 16 registers, which is
3578 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3579 as 1's compliment. */
3580 if ((i.vrex & REX_B))
3583 i.vex.bytes[1] &= ~0x40;
3587 /* EVEX instructions shouldn't need the REX prefix. */
3588 i.vrex &= ~vrex_used;
3589 gas_assert (i.vrex == 0);
3591 /* Check the REX.W bit. */
3592 w = (i.rex & REX_W) ? 1 : 0;
3593 if (i.tm.opcode_modifier.vexw)
3595 if (i.tm.opcode_modifier.vexw == VEXW1)
3598 /* If w is not set it means we are dealing with WIG instruction. */
3601 if (evexwig == evexw1)
3605 /* Encode the U bit. */
3606 implied_prefix |= 0x4;
3608 /* The third byte of the EVEX prefix. */
3609 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3611 /* The fourth byte of the EVEX prefix. */
3612 /* The zeroing-masking bit. */
3613 if (i.mask && i.mask->zeroing)
3614 i.vex.bytes[3] |= 0x80;
3616 /* Don't always set the broadcast bit if there is no RC. */
3619 /* Encode the vector length. */
3620 unsigned int vec_length;
3622 if (!i.tm.opcode_modifier.evex
3623 || i.tm.opcode_modifier.evex == EVEXDYN)
3627 /* Determine vector length from the last multi-length vector
3630 for (op = i.operands; op--;)
3631 if (i.tm.operand_types[op].bitfield.xmmword
3632 + i.tm.operand_types[op].bitfield.ymmword
3633 + i.tm.operand_types[op].bitfield.zmmword > 1)
3635 if (i.types[op].bitfield.zmmword)
3637 i.tm.opcode_modifier.evex = EVEX512;
3640 else if (i.types[op].bitfield.ymmword)
3642 i.tm.opcode_modifier.evex = EVEX256;
3645 else if (i.types[op].bitfield.xmmword)
3647 i.tm.opcode_modifier.evex = EVEX128;
3650 else if (i.broadcast && (int) op == i.broadcast->operand)
3652 switch (i.broadcast->bytes)
3655 i.tm.opcode_modifier.evex = EVEX512;
3658 i.tm.opcode_modifier.evex = EVEX256;
3661 i.tm.opcode_modifier.evex = EVEX128;
3670 if (op >= MAX_OPERANDS)
3674 switch (i.tm.opcode_modifier.evex)
3676 case EVEXLIG: /* LL' is ignored */
3677 vec_length = evexlig << 5;
3680 vec_length = 0 << 5;
3683 vec_length = 1 << 5;
3686 vec_length = 2 << 5;
3692 i.vex.bytes[3] |= vec_length;
3693 /* Encode the broadcast bit. */
3695 i.vex.bytes[3] |= 0x10;
3699 if (i.rounding->type != saeonly)
3700 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3702 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3705 if (i.mask && i.mask->mask)
3706 i.vex.bytes[3] |= i.mask->mask->reg_num;
3710 process_immext (void)
3714 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3717 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3718 with an opcode suffix which is coded in the same place as an
3719 8-bit immediate field would be.
3720 Here we check those operands and remove them afterwards. */
3723 for (x = 0; x < i.operands; x++)
3724 if (register_number (i.op[x].regs) != x)
3725 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3726 register_prefix, i.op[x].regs->reg_name, x + 1,
3732 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3734 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3735 suffix which is coded in the same place as an 8-bit immediate
3737 Here we check those operands and remove them afterwards. */
3740 if (i.operands != 3)
3743 for (x = 0; x < 2; x++)
3744 if (register_number (i.op[x].regs) != x)
3745 goto bad_register_operand;
3747 /* Check for third operand for mwaitx/monitorx insn. */
3748 if (register_number (i.op[x].regs)
3749 != (x + (i.tm.extension_opcode == 0xfb)))
3751 bad_register_operand:
3752 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3753 register_prefix, i.op[x].regs->reg_name, x+1,
3760 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3761 which is coded in the same place as an 8-bit immediate field
3762 would be. Here we fake an 8-bit immediate operand from the
3763 opcode suffix stored in tm.extension_opcode.
3765 AVX instructions also use this encoding, for some of
3766 3 argument instructions. */
3768 gas_assert (i.imm_operands <= 1
3770 || (is_any_vex_encoding (&i.tm)
3771 && i.operands <= 4)));
3773 exp = &im_expressions[i.imm_operands++];
3774 i.op[i.operands].imms = exp;
3775 i.types[i.operands] = imm8;
3777 exp->X_op = O_constant;
3778 exp->X_add_number = i.tm.extension_opcode;
3779 i.tm.extension_opcode = None;
3786 switch (i.tm.opcode_modifier.hleprefixok)
3791 as_bad (_("invalid instruction `%s' after `%s'"),
3792 i.tm.name, i.hle_prefix);
3795 if (i.prefix[LOCK_PREFIX])
3797 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3801 case HLEPrefixRelease:
3802 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3804 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3808 if (i.mem_operands == 0
3809 || !operand_type_check (i.types[i.operands - 1], anymem))
3811 as_bad (_("memory destination needed for instruction `%s'"
3812 " after `xrelease'"), i.tm.name);
3819 /* Try the shortest encoding by shortening operand size. */
3822 optimize_encoding (void)
3826 if (optimize_for_space
3827 && i.reg_operands == 1
3828 && i.imm_operands == 1
3829 && !i.types[1].bitfield.byte
3830 && i.op[0].imms->X_op == O_constant
3831 && fits_in_imm7 (i.op[0].imms->X_add_number)
3832 && ((i.tm.base_opcode == 0xa8
3833 && i.tm.extension_opcode == None)
3834 || (i.tm.base_opcode == 0xf6
3835 && i.tm.extension_opcode == 0x0)))
3838 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3840 unsigned int base_regnum = i.op[1].regs->reg_num;
3841 if (flag_code == CODE_64BIT || base_regnum < 4)
3843 i.types[1].bitfield.byte = 1;
3844 /* Ignore the suffix. */
3846 if (base_regnum >= 4
3847 && !(i.op[1].regs->reg_flags & RegRex))
3849 /* Handle SP, BP, SI and DI registers. */
3850 if (i.types[1].bitfield.word)
3852 else if (i.types[1].bitfield.dword)
3860 else if (flag_code == CODE_64BIT
3861 && ((i.types[1].bitfield.qword
3862 && i.reg_operands == 1
3863 && i.imm_operands == 1
3864 && i.op[0].imms->X_op == O_constant
3865 && ((i.tm.base_opcode == 0xb0
3866 && i.tm.extension_opcode == None
3867 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3868 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3869 && (((i.tm.base_opcode == 0x24
3870 || i.tm.base_opcode == 0xa8)
3871 && i.tm.extension_opcode == None)
3872 || (i.tm.base_opcode == 0x80
3873 && i.tm.extension_opcode == 0x4)
3874 || ((i.tm.base_opcode == 0xf6
3875 || i.tm.base_opcode == 0xc6)
3876 && i.tm.extension_opcode == 0x0)))))
3877 || (i.types[0].bitfield.qword
3878 && ((i.reg_operands == 2
3879 && i.op[0].regs == i.op[1].regs
3880 && ((i.tm.base_opcode == 0x30
3881 || i.tm.base_opcode == 0x28)
3882 && i.tm.extension_opcode == None))
3883 || (i.reg_operands == 1
3885 && i.tm.base_opcode == 0x30
3886 && i.tm.extension_opcode == None)))))
3889 andq $imm31, %r64 -> andl $imm31, %r32
3890 testq $imm31, %r64 -> testl $imm31, %r32
3891 xorq %r64, %r64 -> xorl %r32, %r32
3892 subq %r64, %r64 -> subl %r32, %r32
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3896 i.tm.opcode_modifier.norex64 = 1;
3897 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3900 movq $imm31, %r64 -> movl $imm31, %r32
3901 movq $imm32, %r64 -> movl $imm32, %r32
3903 i.tm.operand_types[0].bitfield.imm32 = 1;
3904 i.tm.operand_types[0].bitfield.imm32s = 0;
3905 i.tm.operand_types[0].bitfield.imm64 = 0;
3906 i.types[0].bitfield.imm32 = 1;
3907 i.types[0].bitfield.imm32s = 0;
3908 i.types[0].bitfield.imm64 = 0;
3909 i.types[1].bitfield.dword = 1;
3910 i.types[1].bitfield.qword = 0;
3911 if (i.tm.base_opcode == 0xc6)
3914 movq $imm31, %r64 -> movl $imm31, %r32
3916 i.tm.base_opcode = 0xb0;
3917 i.tm.extension_opcode = None;
3918 i.tm.opcode_modifier.shortform = 1;
3919 i.tm.opcode_modifier.modrm = 0;
3923 else if (optimize > 1
3924 && i.reg_operands == 3
3925 && i.op[0].regs == i.op[1].regs
3926 && !i.types[2].bitfield.xmmword
3927 && (i.tm.opcode_modifier.vex
3928 || ((!i.mask || i.mask->zeroing)
3930 && is_evex_encoding (&i.tm)
3931 && (i.vec_encoding != vex_encoding_evex
3932 || i.tm.cpu_flags.bitfield.cpuavx512vl
3933 || (i.tm.operand_types[2].bitfield.zmmword
3934 && i.types[2].bitfield.ymmword)
3935 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3936 && ((i.tm.base_opcode == 0x55
3937 || i.tm.base_opcode == 0x6655
3938 || i.tm.base_opcode == 0x66df
3939 || i.tm.base_opcode == 0x57
3940 || i.tm.base_opcode == 0x6657
3941 || i.tm.base_opcode == 0x66ef
3942 || i.tm.base_opcode == 0x66f8
3943 || i.tm.base_opcode == 0x66f9
3944 || i.tm.base_opcode == 0x66fa
3945 || i.tm.base_opcode == 0x66fb)
3946 && i.tm.extension_opcode == None))
3949 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3951 EVEX VOP %zmmM, %zmmM, %zmmN
3952 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3953 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3954 EVEX VOP %ymmM, %ymmM, %ymmN
3955 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3956 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3957 VEX VOP %ymmM, %ymmM, %ymmN
3958 -> VEX VOP %xmmM, %xmmM, %xmmN
3959 VOP, one of vpandn and vpxor:
3960 VEX VOP %ymmM, %ymmM, %ymmN
3961 -> VEX VOP %xmmM, %xmmM, %xmmN
3962 VOP, one of vpandnd and vpandnq:
3963 EVEX VOP %zmmM, %zmmM, %zmmN
3964 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3965 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3966 EVEX VOP %ymmM, %ymmM, %ymmN
3967 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3968 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3969 VOP, one of vpxord and vpxorq:
3970 EVEX VOP %zmmM, %zmmM, %zmmN
3971 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3972 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3973 EVEX VOP %ymmM, %ymmM, %ymmN
3974 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3975 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3977 if (is_evex_encoding (&i.tm))
3979 if (i.vec_encoding == vex_encoding_evex)
3980 i.tm.opcode_modifier.evex = EVEX128;
3983 i.tm.opcode_modifier.vex = VEX128;
3984 i.tm.opcode_modifier.vexw = VEXW0;
3985 i.tm.opcode_modifier.evex = 0;
3989 i.tm.opcode_modifier.vex = VEX128;
3991 if (i.tm.opcode_modifier.vex)
3992 for (j = 0; j < 3; j++)
3994 i.types[j].bitfield.xmmword = 1;
3995 i.types[j].bitfield.ymmword = 0;
4000 /* This is the guts of the machine-dependent assembler. LINE points to a
4001 machine dependent instruction. This function is supposed to emit
4002 the frags/bytes it assembles to. */
4005 md_assemble (char *line)
4008 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4009 const insn_template *t;
4011 /* Initialize globals. */
4012 memset (&i, '\0', sizeof (i));
4013 for (j = 0; j < MAX_OPERANDS; j++)
4014 i.reloc[j] = NO_RELOC;
4015 memset (disp_expressions, '\0', sizeof (disp_expressions));
4016 memset (im_expressions, '\0', sizeof (im_expressions));
4017 save_stack_p = save_stack;
4019 /* First parse an instruction mnemonic & call i386_operand for the operands.
4020 We assume that the scrubber has arranged it so that line[0] is the valid
4021 start of a (possibly prefixed) mnemonic. */
4023 line = parse_insn (line, mnemonic);
4026 mnem_suffix = i.suffix;
4028 line = parse_operands (line, mnemonic);
4030 xfree (i.memop1_string);
4031 i.memop1_string = NULL;
4035 /* Now we've parsed the mnemonic into a set of templates, and have the
4036 operands at hand. */
4038 /* All intel opcodes have reversed operands except for "bound" and
4039 "enter". We also don't reverse intersegment "jmp" and "call"
4040 instructions with 2 immediate operands so that the immediate segment
4041 precedes the offset, as it does when in AT&T mode. */
4044 && (strcmp (mnemonic, "bound") != 0)
4045 && (strcmp (mnemonic, "invlpga") != 0)
4046 && !(operand_type_check (i.types[0], imm)
4047 && operand_type_check (i.types[1], imm)))
4050 /* The order of the immediates should be reversed
4051 for 2 immediates extrq and insertq instructions */
4052 if (i.imm_operands == 2
4053 && (strcmp (mnemonic, "extrq") == 0
4054 || strcmp (mnemonic, "insertq") == 0))
4055 swap_2_operands (0, 1);
4060 /* Don't optimize displacement for movabs since it only takes 64bit
4063 && i.disp_encoding != disp_encoding_32bit
4064 && (flag_code != CODE_64BIT
4065 || strcmp (mnemonic, "movabs") != 0))
4068 /* Next, we find a template that matches the given insn,
4069 making sure the overlap of the given operands types is consistent
4070 with the template operand types. */
4072 if (!(t = match_template (mnem_suffix)))
4075 if (sse_check != check_none
4076 && !i.tm.opcode_modifier.noavx
4077 && !i.tm.cpu_flags.bitfield.cpuavx
4078 && (i.tm.cpu_flags.bitfield.cpusse
4079 || i.tm.cpu_flags.bitfield.cpusse2
4080 || i.tm.cpu_flags.bitfield.cpusse3
4081 || i.tm.cpu_flags.bitfield.cpussse3
4082 || i.tm.cpu_flags.bitfield.cpusse4_1
4083 || i.tm.cpu_flags.bitfield.cpusse4_2
4084 || i.tm.cpu_flags.bitfield.cpupclmul
4085 || i.tm.cpu_flags.bitfield.cpuaes
4086 || i.tm.cpu_flags.bitfield.cpugfni))
4088 (sse_check == check_warning
4090 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4093 /* Zap movzx and movsx suffix. The suffix has been set from
4094 "word ptr" or "byte ptr" on the source operand in Intel syntax
4095 or extracted from mnemonic in AT&T syntax. But we'll use
4096 the destination register to choose the suffix for encoding. */
4097 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4099 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4100 there is no suffix, the default will be byte extension. */
4101 if (i.reg_operands != 2
4104 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4109 if (i.tm.opcode_modifier.fwait)
4110 if (!add_prefix (FWAIT_OPCODE))
4113 /* Check if REP prefix is OK. */
4114 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4116 as_bad (_("invalid instruction `%s' after `%s'"),
4117 i.tm.name, i.rep_prefix);
4121 /* Check for lock without a lockable instruction. Destination operand
4122 must be memory unless it is xchg (0x86). */
4123 if (i.prefix[LOCK_PREFIX]
4124 && (!i.tm.opcode_modifier.islockable
4125 || i.mem_operands == 0
4126 || (i.tm.base_opcode != 0x86
4127 && !operand_type_check (i.types[i.operands - 1], anymem))))
4129 as_bad (_("expecting lockable instruction after `lock'"));
4133 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4134 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4136 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4140 /* Check if HLE prefix is OK. */
4141 if (i.hle_prefix && !check_hle ())
4144 /* Check BND prefix. */
4145 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4146 as_bad (_("expecting valid branch instruction after `bnd'"));
4148 /* Check NOTRACK prefix. */
4149 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4150 as_bad (_("expecting indirect branch instruction after `notrack'"));
4152 if (i.tm.cpu_flags.bitfield.cpumpx)
4154 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4155 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4156 else if (flag_code != CODE_16BIT
4157 ? i.prefix[ADDR_PREFIX]
4158 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4159 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4162 /* Insert BND prefix. */
4163 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4165 if (!i.prefix[BND_PREFIX])
4166 add_prefix (BND_PREFIX_OPCODE);
4167 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4169 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4170 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4174 /* Check string instruction segment overrides. */
4175 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4177 if (!check_string ())
4179 i.disp_operands = 0;
4182 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4183 optimize_encoding ();
4185 if (!process_suffix ())
4188 /* Update operand types. */
4189 for (j = 0; j < i.operands; j++)
4190 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4192 /* Make still unresolved immediate matches conform to size of immediate
4193 given in i.suffix. */
4194 if (!finalize_imm ())
4197 if (i.types[0].bitfield.imm1)
4198 i.imm_operands = 0; /* kludge for shift insns. */
4200 /* We only need to check those implicit registers for instructions
4201 with 3 operands or less. */
4202 if (i.operands <= 3)
4203 for (j = 0; j < i.operands; j++)
4204 if (i.types[j].bitfield.inoutportreg
4205 || i.types[j].bitfield.shiftcount
4206 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4209 /* ImmExt should be processed after SSE2AVX. */
4210 if (!i.tm.opcode_modifier.sse2avx
4211 && i.tm.opcode_modifier.immext)
4214 /* For insns with operands there are more diddles to do to the opcode. */
4217 if (!process_operands ())
4220 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4222 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4223 as_warn (_("translating to `%sp'"), i.tm.name);
4226 if (is_any_vex_encoding (&i.tm))
4228 if (flag_code == CODE_16BIT)
4230 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4235 if (i.tm.opcode_modifier.vex)
4236 build_vex_prefix (t);
4238 build_evex_prefix ();
4241 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4242 instructions may define INT_OPCODE as well, so avoid this corner
4243 case for those instructions that use MODRM. */
4244 if (i.tm.base_opcode == INT_OPCODE
4245 && !i.tm.opcode_modifier.modrm
4246 && i.op[0].imms->X_add_number == 3)
4248 i.tm.base_opcode = INT3_OPCODE;
4252 if ((i.tm.opcode_modifier.jump
4253 || i.tm.opcode_modifier.jumpbyte
4254 || i.tm.opcode_modifier.jumpdword)
4255 && i.op[0].disps->X_op == O_constant)
4257 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4258 the absolute address given by the constant. Since ix86 jumps and
4259 calls are pc relative, we need to generate a reloc. */
4260 i.op[0].disps->X_add_symbol = &abs_symbol;
4261 i.op[0].disps->X_op = O_symbol;
4264 if (i.tm.opcode_modifier.rex64)
4267 /* For 8 bit registers we need an empty rex prefix. Also if the
4268 instruction already has a prefix, we need to convert old
4269 registers to new ones. */
4271 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4272 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4273 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4274 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4275 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4276 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4281 i.rex |= REX_OPCODE;
4282 for (x = 0; x < 2; x++)
4284 /* Look for 8 bit operand that uses old registers. */
4285 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4286 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4288 /* In case it is "hi" register, give up. */
4289 if (i.op[x].regs->reg_num > 3)
4290 as_bad (_("can't encode register '%s%s' in an "
4291 "instruction requiring REX prefix."),
4292 register_prefix, i.op[x].regs->reg_name);
4294 /* Otherwise it is equivalent to the extended register.
4295 Since the encoding doesn't change this is merely
4296 cosmetic cleanup for debug output. */
4298 i.op[x].regs = i.op[x].regs + 8;
4303 if (i.rex == 0 && i.rex_encoding)
4305 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4306 that uses legacy register. If it is "hi" register, don't add
4307 the REX_OPCODE byte. */
4309 for (x = 0; x < 2; x++)
4310 if (i.types[x].bitfield.reg
4311 && i.types[x].bitfield.byte
4312 && (i.op[x].regs->reg_flags & RegRex64) == 0
4313 && i.op[x].regs->reg_num > 3)
4315 i.rex_encoding = FALSE;
4324 add_prefix (REX_OPCODE | i.rex);
4326 /* We are ready to output the insn. */
4331 parse_insn (char *line, char *mnemonic)
4334 char *token_start = l;
4337 const insn_template *t;
4343 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4348 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4350 as_bad (_("no such instruction: `%s'"), token_start);
4355 if (!is_space_char (*l)
4356 && *l != END_OF_INSN
4358 || (*l != PREFIX_SEPARATOR
4361 as_bad (_("invalid character %s in mnemonic"),
4362 output_invalid (*l));
4365 if (token_start == l)
4367 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4368 as_bad (_("expecting prefix; got nothing"));
4370 as_bad (_("expecting mnemonic; got nothing"));
4374 /* Look up instruction (or prefix) via hash table. */
4375 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4377 if (*l != END_OF_INSN
4378 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4379 && current_templates
4380 && current_templates->start->opcode_modifier.isprefix)
4382 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4384 as_bad ((flag_code != CODE_64BIT
4385 ? _("`%s' is only supported in 64-bit mode")
4386 : _("`%s' is not supported in 64-bit mode")),
4387 current_templates->start->name);
4390 /* If we are in 16-bit mode, do not allow addr16 or data16.
4391 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4392 if ((current_templates->start->opcode_modifier.size16
4393 || current_templates->start->opcode_modifier.size32)
4394 && flag_code != CODE_64BIT
4395 && (current_templates->start->opcode_modifier.size32
4396 ^ (flag_code == CODE_16BIT)))
4398 as_bad (_("redundant %s prefix"),
4399 current_templates->start->name);
4402 if (current_templates->start->opcode_length == 0)
4404 /* Handle pseudo prefixes. */
4405 switch (current_templates->start->base_opcode)
4409 i.disp_encoding = disp_encoding_8bit;
4413 i.disp_encoding = disp_encoding_32bit;
4417 i.dir_encoding = dir_encoding_load;
4421 i.dir_encoding = dir_encoding_store;
4425 i.vec_encoding = vex_encoding_vex2;
4429 i.vec_encoding = vex_encoding_vex3;
4433 i.vec_encoding = vex_encoding_evex;
4437 i.rex_encoding = TRUE;
4441 i.no_optimize = TRUE;
4449 /* Add prefix, checking for repeated prefixes. */
4450 switch (add_prefix (current_templates->start->base_opcode))
4455 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4456 i.notrack_prefix = current_templates->start->name;
4459 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4460 i.hle_prefix = current_templates->start->name;
4461 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4462 i.bnd_prefix = current_templates->start->name;
4464 i.rep_prefix = current_templates->start->name;
4470 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4477 if (!current_templates)
4479 /* Check if we should swap operand or force 32bit displacement in
4481 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4482 i.dir_encoding = dir_encoding_store;
4483 else if (mnem_p - 3 == dot_p
4486 i.disp_encoding = disp_encoding_8bit;
4487 else if (mnem_p - 4 == dot_p
4491 i.disp_encoding = disp_encoding_32bit;
4496 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4499 if (!current_templates)
4502 /* See if we can get a match by trimming off a suffix. */
4505 case WORD_MNEM_SUFFIX:
4506 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4507 i.suffix = SHORT_MNEM_SUFFIX;
4510 case BYTE_MNEM_SUFFIX:
4511 case QWORD_MNEM_SUFFIX:
4512 i.suffix = mnem_p[-1];
4514 current_templates = (const templates *) hash_find (op_hash,
4517 case SHORT_MNEM_SUFFIX:
4518 case LONG_MNEM_SUFFIX:
4521 i.suffix = mnem_p[-1];
4523 current_templates = (const templates *) hash_find (op_hash,
4532 if (intel_float_operand (mnemonic) == 1)
4533 i.suffix = SHORT_MNEM_SUFFIX;
4535 i.suffix = LONG_MNEM_SUFFIX;
4537 current_templates = (const templates *) hash_find (op_hash,
4542 if (!current_templates)
4544 as_bad (_("no such instruction: `%s'"), token_start);
4549 if (current_templates->start->opcode_modifier.jump
4550 || current_templates->start->opcode_modifier.jumpbyte)
4552 /* Check for a branch hint. We allow ",pt" and ",pn" for
4553 predict taken and predict not taken respectively.
4554 I'm not sure that branch hints actually do anything on loop
4555 and jcxz insns (JumpByte) for current Pentium4 chips. They
4556 may work in the future and it doesn't hurt to accept them
4558 if (l[0] == ',' && l[1] == 'p')
4562 if (!add_prefix (DS_PREFIX_OPCODE))
4566 else if (l[2] == 'n')
4568 if (!add_prefix (CS_PREFIX_OPCODE))
4574 /* Any other comma loses. */
4577 as_bad (_("invalid character %s in mnemonic"),
4578 output_invalid (*l));
4582 /* Check if instruction is supported on specified architecture. */
4584 for (t = current_templates->start; t < current_templates->end; ++t)
4586 supported |= cpu_flags_match (t);
4587 if (supported == CPU_FLAGS_PERFECT_MATCH)
4589 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4590 as_warn (_("use .code16 to ensure correct addressing mode"));
4596 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4597 as_bad (flag_code == CODE_64BIT
4598 ? _("`%s' is not supported in 64-bit mode")
4599 : _("`%s' is only supported in 64-bit mode"),
4600 current_templates->start->name);
4602 as_bad (_("`%s' is not supported on `%s%s'"),
4603 current_templates->start->name,
4604 cpu_arch_name ? cpu_arch_name : default_arch,
4605 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4611 parse_operands (char *l, const char *mnemonic)
4615 /* 1 if operand is pending after ','. */
4616 unsigned int expecting_operand = 0;
4618 /* Non-zero if operand parens not balanced. */
4619 unsigned int paren_not_balanced;
4621 while (*l != END_OF_INSN)
4623 /* Skip optional white space before operand. */
4624 if (is_space_char (*l))
4626 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4628 as_bad (_("invalid character %s before operand %d"),
4629 output_invalid (*l),
4633 token_start = l; /* After white space. */
4634 paren_not_balanced = 0;
4635 while (paren_not_balanced || *l != ',')
4637 if (*l == END_OF_INSN)
4639 if (paren_not_balanced)
4642 as_bad (_("unbalanced parenthesis in operand %d."),
4645 as_bad (_("unbalanced brackets in operand %d."),
4650 break; /* we are done */
4652 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4654 as_bad (_("invalid character %s in operand %d"),
4655 output_invalid (*l),
4662 ++paren_not_balanced;
4664 --paren_not_balanced;
4669 ++paren_not_balanced;
4671 --paren_not_balanced;
4675 if (l != token_start)
4676 { /* Yes, we've read in another operand. */
4677 unsigned int operand_ok;
4678 this_operand = i.operands++;
4679 if (i.operands > MAX_OPERANDS)
4681 as_bad (_("spurious operands; (%d operands/instruction max)"),
4685 i.types[this_operand].bitfield.unspecified = 1;
4686 /* Now parse operand adding info to 'i' as we go along. */
4687 END_STRING_AND_SAVE (l);
4689 if (i.mem_operands > 1)
4691 as_bad (_("too many memory references for `%s'"),
4698 i386_intel_operand (token_start,
4699 intel_float_operand (mnemonic));
4701 operand_ok = i386_att_operand (token_start);
4703 RESTORE_END_STRING (l);
4709 if (expecting_operand)
4711 expecting_operand_after_comma:
4712 as_bad (_("expecting operand after ','; got nothing"));
4717 as_bad (_("expecting operand before ','; got nothing"));
4722 /* Now *l must be either ',' or END_OF_INSN. */
4725 if (*++l == END_OF_INSN)
4727 /* Just skip it, if it's \n complain. */
4728 goto expecting_operand_after_comma;
4730 expecting_operand = 1;
4737 swap_2_operands (int xchg1, int xchg2)
4739 union i386_op temp_op;
4740 i386_operand_type temp_type;
4741 enum bfd_reloc_code_real temp_reloc;
4743 temp_type = i.types[xchg2];
4744 i.types[xchg2] = i.types[xchg1];
4745 i.types[xchg1] = temp_type;
4746 temp_op = i.op[xchg2];
4747 i.op[xchg2] = i.op[xchg1];
4748 i.op[xchg1] = temp_op;
4749 temp_reloc = i.reloc[xchg2];
4750 i.reloc[xchg2] = i.reloc[xchg1];
4751 i.reloc[xchg1] = temp_reloc;
4755 if (i.mask->operand == xchg1)
4756 i.mask->operand = xchg2;
4757 else if (i.mask->operand == xchg2)
4758 i.mask->operand = xchg1;
4762 if (i.broadcast->operand == xchg1)
4763 i.broadcast->operand = xchg2;
4764 else if (i.broadcast->operand == xchg2)
4765 i.broadcast->operand = xchg1;
4769 if (i.rounding->operand == xchg1)
4770 i.rounding->operand = xchg2;
4771 else if (i.rounding->operand == xchg2)
4772 i.rounding->operand = xchg1;
4777 swap_operands (void)
4783 swap_2_operands (1, i.operands - 2);
4787 swap_2_operands (0, i.operands - 1);
4793 if (i.mem_operands == 2)
4795 const seg_entry *temp_seg;
4796 temp_seg = i.seg[0];
4797 i.seg[0] = i.seg[1];
4798 i.seg[1] = temp_seg;
4802 /* Try to ensure constant immediates are represented in the smallest
4807 char guess_suffix = 0;
4811 guess_suffix = i.suffix;
4812 else if (i.reg_operands)
4814 /* Figure out a suffix from the last register operand specified.
4815 We can't do this properly yet, ie. excluding InOutPortReg,
4816 but the following works for instructions with immediates.
4817 In any case, we can't set i.suffix yet. */
4818 for (op = i.operands; --op >= 0;)
4819 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4821 guess_suffix = BYTE_MNEM_SUFFIX;
4824 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4826 guess_suffix = WORD_MNEM_SUFFIX;
4829 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4831 guess_suffix = LONG_MNEM_SUFFIX;
4834 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4836 guess_suffix = QWORD_MNEM_SUFFIX;
4840 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4841 guess_suffix = WORD_MNEM_SUFFIX;
4843 for (op = i.operands; --op >= 0;)
4844 if (operand_type_check (i.types[op], imm))
4846 switch (i.op[op].imms->X_op)
4849 /* If a suffix is given, this operand may be shortened. */
4850 switch (guess_suffix)
4852 case LONG_MNEM_SUFFIX:
4853 i.types[op].bitfield.imm32 = 1;
4854 i.types[op].bitfield.imm64 = 1;
4856 case WORD_MNEM_SUFFIX:
4857 i.types[op].bitfield.imm16 = 1;
4858 i.types[op].bitfield.imm32 = 1;
4859 i.types[op].bitfield.imm32s = 1;
4860 i.types[op].bitfield.imm64 = 1;
4862 case BYTE_MNEM_SUFFIX:
4863 i.types[op].bitfield.imm8 = 1;
4864 i.types[op].bitfield.imm8s = 1;
4865 i.types[op].bitfield.imm16 = 1;
4866 i.types[op].bitfield.imm32 = 1;
4867 i.types[op].bitfield.imm32s = 1;
4868 i.types[op].bitfield.imm64 = 1;
4872 /* If this operand is at most 16 bits, convert it
4873 to a signed 16 bit number before trying to see
4874 whether it will fit in an even smaller size.
4875 This allows a 16-bit operand such as $0xffe0 to
4876 be recognised as within Imm8S range. */
4877 if ((i.types[op].bitfield.imm16)
4878 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4880 i.op[op].imms->X_add_number =
4881 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4884 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4885 if ((i.types[op].bitfield.imm32)
4886 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4889 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4890 ^ ((offsetT) 1 << 31))
4891 - ((offsetT) 1 << 31));
4895 = operand_type_or (i.types[op],
4896 smallest_imm_type (i.op[op].imms->X_add_number));
4898 /* We must avoid matching of Imm32 templates when 64bit
4899 only immediate is available. */
4900 if (guess_suffix == QWORD_MNEM_SUFFIX)
4901 i.types[op].bitfield.imm32 = 0;
4908 /* Symbols and expressions. */
4910 /* Convert symbolic operand to proper sizes for matching, but don't
4911 prevent matching a set of insns that only supports sizes other
4912 than those matching the insn suffix. */
4914 i386_operand_type mask, allowed;
4915 const insn_template *t;
4917 operand_type_set (&mask, 0);
4918 operand_type_set (&allowed, 0);
4920 for (t = current_templates->start;
4921 t < current_templates->end;
4923 allowed = operand_type_or (allowed,
4924 t->operand_types[op]);
4925 switch (guess_suffix)
4927 case QWORD_MNEM_SUFFIX:
4928 mask.bitfield.imm64 = 1;
4929 mask.bitfield.imm32s = 1;
4931 case LONG_MNEM_SUFFIX:
4932 mask.bitfield.imm32 = 1;
4934 case WORD_MNEM_SUFFIX:
4935 mask.bitfield.imm16 = 1;
4937 case BYTE_MNEM_SUFFIX:
4938 mask.bitfield.imm8 = 1;
4943 allowed = operand_type_and (mask, allowed);
4944 if (!operand_type_all_zero (&allowed))
4945 i.types[op] = operand_type_and (i.types[op], mask);
4952 /* Try to use the smallest displacement type too. */
4954 optimize_disp (void)
4958 for (op = i.operands; --op >= 0;)
4959 if (operand_type_check (i.types[op], disp))
4961 if (i.op[op].disps->X_op == O_constant)
4963 offsetT op_disp = i.op[op].disps->X_add_number;
4965 if (i.types[op].bitfield.disp16
4966 && (op_disp & ~(offsetT) 0xffff) == 0)
4968 /* If this operand is at most 16 bits, convert
4969 to a signed 16 bit number and don't use 64bit
4971 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4972 i.types[op].bitfield.disp64 = 0;
4975 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4976 if (i.types[op].bitfield.disp32
4977 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4979 /* If this operand is at most 32 bits, convert
4980 to a signed 32 bit number and don't use 64bit
4982 op_disp &= (((offsetT) 2 << 31) - 1);
4983 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4984 i.types[op].bitfield.disp64 = 0;
4987 if (!op_disp && i.types[op].bitfield.baseindex)
4989 i.types[op].bitfield.disp8 = 0;
4990 i.types[op].bitfield.disp16 = 0;
4991 i.types[op].bitfield.disp32 = 0;
4992 i.types[op].bitfield.disp32s = 0;
4993 i.types[op].bitfield.disp64 = 0;
4997 else if (flag_code == CODE_64BIT)
4999 if (fits_in_signed_long (op_disp))
5001 i.types[op].bitfield.disp64 = 0;
5002 i.types[op].bitfield.disp32s = 1;
5004 if (i.prefix[ADDR_PREFIX]
5005 && fits_in_unsigned_long (op_disp))
5006 i.types[op].bitfield.disp32 = 1;
5008 if ((i.types[op].bitfield.disp32
5009 || i.types[op].bitfield.disp32s
5010 || i.types[op].bitfield.disp16)
5011 && fits_in_disp8 (op_disp))
5012 i.types[op].bitfield.disp8 = 1;
5014 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5015 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5017 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5018 i.op[op].disps, 0, i.reloc[op]);
5019 i.types[op].bitfield.disp8 = 0;
5020 i.types[op].bitfield.disp16 = 0;
5021 i.types[op].bitfield.disp32 = 0;
5022 i.types[op].bitfield.disp32s = 0;
5023 i.types[op].bitfield.disp64 = 0;
5026 /* We only support 64bit displacement on constants. */
5027 i.types[op].bitfield.disp64 = 0;
5031 /* Return 1 if there is a match in broadcast bytes between operand
5032 GIVEN and instruction template T. */
5035 match_broadcast_size (const insn_template *t, unsigned int given)
5037 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5038 && i.types[given].bitfield.byte)
5039 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5040 && i.types[given].bitfield.word)
5041 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5042 && i.types[given].bitfield.dword)
5043 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5044 && i.types[given].bitfield.qword));
5047 /* Check if operands are valid for the instruction. */
5050 check_VecOperands (const insn_template *t)
5054 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5056 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5057 any one operand are implicity requiring AVX512VL support if the actual
5058 operand size is YMMword or XMMword. Since this function runs after
5059 template matching, there's no need to check for YMMword/XMMword in
5061 cpu = cpu_flags_and (t->cpu_flags, avx512);
5062 if (!cpu_flags_all_zero (&cpu)
5063 && !t->cpu_flags.bitfield.cpuavx512vl
5064 && !cpu_arch_flags.bitfield.cpuavx512vl)
5066 for (op = 0; op < t->operands; ++op)
5068 if (t->operand_types[op].bitfield.zmmword
5069 && (i.types[op].bitfield.ymmword
5070 || i.types[op].bitfield.xmmword))
5072 i.error = unsupported;
5078 /* Without VSIB byte, we can't have a vector register for index. */
5079 if (!t->opcode_modifier.vecsib
5081 && (i.index_reg->reg_type.bitfield.xmmword
5082 || i.index_reg->reg_type.bitfield.ymmword
5083 || i.index_reg->reg_type.bitfield.zmmword))
5085 i.error = unsupported_vector_index_register;
5089 /* Check if default mask is allowed. */
5090 if (t->opcode_modifier.nodefmask
5091 && (!i.mask || i.mask->mask->reg_num == 0))
5093 i.error = no_default_mask;
5097 /* For VSIB byte, we need a vector register for index, and all vector
5098 registers must be distinct. */
5099 if (t->opcode_modifier.vecsib)
5102 || !((t->opcode_modifier.vecsib == VecSIB128
5103 && i.index_reg->reg_type.bitfield.xmmword)
5104 || (t->opcode_modifier.vecsib == VecSIB256
5105 && i.index_reg->reg_type.bitfield.ymmword)
5106 || (t->opcode_modifier.vecsib == VecSIB512
5107 && i.index_reg->reg_type.bitfield.zmmword)))
5109 i.error = invalid_vsib_address;
5113 gas_assert (i.reg_operands == 2 || i.mask);
5114 if (i.reg_operands == 2 && !i.mask)
5116 gas_assert (i.types[0].bitfield.regsimd);
5117 gas_assert (i.types[0].bitfield.xmmword
5118 || i.types[0].bitfield.ymmword);
5119 gas_assert (i.types[2].bitfield.regsimd);
5120 gas_assert (i.types[2].bitfield.xmmword
5121 || i.types[2].bitfield.ymmword);
5122 if (operand_check == check_none)
5124 if (register_number (i.op[0].regs)
5125 != register_number (i.index_reg)
5126 && register_number (i.op[2].regs)
5127 != register_number (i.index_reg)
5128 && register_number (i.op[0].regs)
5129 != register_number (i.op[2].regs))
5131 if (operand_check == check_error)
5133 i.error = invalid_vector_register_set;
5136 as_warn (_("mask, index, and destination registers should be distinct"));
5138 else if (i.reg_operands == 1 && i.mask)
5140 if (i.types[1].bitfield.regsimd
5141 && (i.types[1].bitfield.xmmword
5142 || i.types[1].bitfield.ymmword
5143 || i.types[1].bitfield.zmmword)
5144 && (register_number (i.op[1].regs)
5145 == register_number (i.index_reg)))
5147 if (operand_check == check_error)
5149 i.error = invalid_vector_register_set;
5152 if (operand_check != check_none)
5153 as_warn (_("index and destination registers should be distinct"));
5158 /* Check if broadcast is supported by the instruction and is applied
5159 to the memory operand. */
5162 i386_operand_type type, overlap;
5164 /* Check if specified broadcast is supported in this instruction,
5165 and its broadcast bytes match the memory operand. */
5166 op = i.broadcast->operand;
5167 if (!t->opcode_modifier.broadcast
5168 || !i.types[op].bitfield.mem
5169 || (!i.types[op].bitfield.unspecified
5170 && !match_broadcast_size (t, op)))
5173 i.error = unsupported_broadcast;
5177 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5178 * i.broadcast->type);
5179 operand_type_set (&type, 0);
5180 switch (i.broadcast->bytes)
5183 type.bitfield.word = 1;
5186 type.bitfield.dword = 1;
5189 type.bitfield.qword = 1;
5192 type.bitfield.xmmword = 1;
5195 type.bitfield.ymmword = 1;
5198 type.bitfield.zmmword = 1;
5204 overlap = operand_type_and (type, t->operand_types[op]);
5205 if (operand_type_all_zero (&overlap))
5208 if (t->opcode_modifier.checkregsize)
5212 type.bitfield.baseindex = 1;
5213 for (j = 0; j < i.operands; ++j)
5216 && !operand_type_register_match(i.types[j],
5217 t->operand_types[j],
5219 t->operand_types[op]))
5224 /* If broadcast is supported in this instruction, we need to check if
5225 operand of one-element size isn't specified without broadcast. */
5226 else if (t->opcode_modifier.broadcast && i.mem_operands)
5228 /* Find memory operand. */
5229 for (op = 0; op < i.operands; op++)
5230 if (operand_type_check (i.types[op], anymem))
5232 gas_assert (op < i.operands);
5233 /* Check size of the memory operand. */
5234 if (match_broadcast_size (t, op))
5236 i.error = broadcast_needed;
5241 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5243 /* Check if requested masking is supported. */
5246 switch (t->opcode_modifier.masking)
5250 case MERGING_MASKING:
5251 if (i.mask->zeroing)
5254 i.error = unsupported_masking;
5258 case DYNAMIC_MASKING:
5259 /* Memory destinations allow only merging masking. */
5260 if (i.mask->zeroing && i.mem_operands)
5262 /* Find memory operand. */
5263 for (op = 0; op < i.operands; op++)
5264 if (i.types[op].bitfield.mem)
5266 gas_assert (op < i.operands);
5267 if (op == i.operands - 1)
5269 i.error = unsupported_masking;
5279 /* Check if masking is applied to dest operand. */
5280 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5282 i.error = mask_not_on_destination;
5289 if ((i.rounding->type != saeonly
5290 && !t->opcode_modifier.staticrounding)
5291 || (i.rounding->type == saeonly
5292 && (t->opcode_modifier.staticrounding
5293 || !t->opcode_modifier.sae)))
5295 i.error = unsupported_rc_sae;
5298 /* If the instruction has several immediate operands and one of
5299 them is rounding, the rounding operand should be the last
5300 immediate operand. */
5301 if (i.imm_operands > 1
5302 && i.rounding->operand != (int) (i.imm_operands - 1))
5304 i.error = rc_sae_operand_not_last_imm;
5309 /* Check vector Disp8 operand. */
5310 if (t->opcode_modifier.disp8memshift
5311 && i.disp_encoding != disp_encoding_32bit)
5314 i.memshift = t->opcode_modifier.broadcast - 1;
5315 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5316 i.memshift = t->opcode_modifier.disp8memshift;
5319 const i386_operand_type *type = NULL;
5322 for (op = 0; op < i.operands; op++)
5323 if (operand_type_check (i.types[op], anymem))
5325 if (t->opcode_modifier.evex == EVEXLIG)
5326 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5327 else if (t->operand_types[op].bitfield.xmmword
5328 + t->operand_types[op].bitfield.ymmword
5329 + t->operand_types[op].bitfield.zmmword <= 1)
5330 type = &t->operand_types[op];
5331 else if (!i.types[op].bitfield.unspecified)
5332 type = &i.types[op];
5334 else if (i.types[op].bitfield.regsimd
5335 && t->opcode_modifier.evex != EVEXLIG)
5337 if (i.types[op].bitfield.zmmword)
5339 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5341 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5347 if (type->bitfield.zmmword)
5349 else if (type->bitfield.ymmword)
5351 else if (type->bitfield.xmmword)
5355 /* For the check in fits_in_disp8(). */
5356 if (i.memshift == 0)
5360 for (op = 0; op < i.operands; op++)
5361 if (operand_type_check (i.types[op], disp)
5362 && i.op[op].disps->X_op == O_constant)
5364 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5366 i.types[op].bitfield.disp8 = 1;
5369 i.types[op].bitfield.disp8 = 0;
5378 /* Check if operands are valid for the instruction. Update VEX
5382 VEX_check_operands (const insn_template *t)
5384 if (i.vec_encoding == vex_encoding_evex)
5386 /* This instruction must be encoded with EVEX prefix. */
5387 if (!is_evex_encoding (t))
5389 i.error = unsupported;
5395 if (!t->opcode_modifier.vex)
5397 /* This instruction template doesn't have VEX prefix. */
5398 if (i.vec_encoding != vex_encoding_default)
5400 i.error = unsupported;
5406 /* Only check VEX_Imm4, which must be the first operand. */
5407 if (t->operand_types[0].bitfield.vec_imm4)
5409 if (i.op[0].imms->X_op != O_constant
5410 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5416 /* Turn off Imm8 so that update_imm won't complain. */
5417 i.types[0] = vec_imm4;
5423 static const insn_template *
5424 match_template (char mnem_suffix)
5426 /* Points to template once we've found it. */
5427 const insn_template *t;
5428 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5429 i386_operand_type overlap4;
5430 unsigned int found_reverse_match;
5431 i386_opcode_modifier suffix_check, mnemsuf_check;
5432 i386_operand_type operand_types [MAX_OPERANDS];
5433 int addr_prefix_disp;
5435 unsigned int found_cpu_match, size_match;
5436 unsigned int check_register;
5437 enum i386_error specific_error = 0;
5439 #if MAX_OPERANDS != 5
5440 # error "MAX_OPERANDS must be 5."
5443 found_reverse_match = 0;
5444 addr_prefix_disp = -1;
5446 memset (&suffix_check, 0, sizeof (suffix_check));
5447 if (intel_syntax && i.broadcast)
5449 else if (i.suffix == BYTE_MNEM_SUFFIX)
5450 suffix_check.no_bsuf = 1;
5451 else if (i.suffix == WORD_MNEM_SUFFIX)
5452 suffix_check.no_wsuf = 1;
5453 else if (i.suffix == SHORT_MNEM_SUFFIX)
5454 suffix_check.no_ssuf = 1;
5455 else if (i.suffix == LONG_MNEM_SUFFIX)
5456 suffix_check.no_lsuf = 1;
5457 else if (i.suffix == QWORD_MNEM_SUFFIX)
5458 suffix_check.no_qsuf = 1;
5459 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5460 suffix_check.no_ldsuf = 1;
5462 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5465 switch (mnem_suffix)
5467 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5468 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5469 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5470 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5471 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5475 /* Must have right number of operands. */
5476 i.error = number_of_operands_mismatch;
5478 for (t = current_templates->start; t < current_templates->end; t++)
5480 addr_prefix_disp = -1;
5482 if (i.operands != t->operands)
5485 /* Check processor support. */
5486 i.error = unsupported;
5487 found_cpu_match = (cpu_flags_match (t)
5488 == CPU_FLAGS_PERFECT_MATCH);
5489 if (!found_cpu_match)
5492 /* Check AT&T mnemonic. */
5493 i.error = unsupported_with_intel_mnemonic;
5494 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5497 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5498 i.error = unsupported_syntax;
5499 if ((intel_syntax && t->opcode_modifier.attsyntax)
5500 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5501 || (intel64 && t->opcode_modifier.amd64)
5502 || (!intel64 && t->opcode_modifier.intel64))
5505 /* Check the suffix, except for some instructions in intel mode. */
5506 i.error = invalid_instruction_suffix;
5507 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5508 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5509 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5510 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5511 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5512 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5513 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5515 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5516 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5517 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5518 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5519 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5520 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5521 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5524 size_match = operand_size_match (t);
5528 for (j = 0; j < MAX_OPERANDS; j++)
5529 operand_types[j] = t->operand_types[j];
5531 /* In general, don't allow 64-bit operands in 32-bit mode. */
5532 if (i.suffix == QWORD_MNEM_SUFFIX
5533 && flag_code != CODE_64BIT
5535 ? (!t->opcode_modifier.ignoresize
5536 && !t->opcode_modifier.broadcast
5537 && !intel_float_operand (t->name))
5538 : intel_float_operand (t->name) != 2)
5539 && ((!operand_types[0].bitfield.regmmx
5540 && !operand_types[0].bitfield.regsimd)
5541 || (!operand_types[t->operands > 1].bitfield.regmmx
5542 && !operand_types[t->operands > 1].bitfield.regsimd))
5543 && (t->base_opcode != 0x0fc7
5544 || t->extension_opcode != 1 /* cmpxchg8b */))
5547 /* In general, don't allow 32-bit operands on pre-386. */
5548 else if (i.suffix == LONG_MNEM_SUFFIX
5549 && !cpu_arch_flags.bitfield.cpui386
5551 ? (!t->opcode_modifier.ignoresize
5552 && !intel_float_operand (t->name))
5553 : intel_float_operand (t->name) != 2)
5554 && ((!operand_types[0].bitfield.regmmx
5555 && !operand_types[0].bitfield.regsimd)
5556 || (!operand_types[t->operands > 1].bitfield.regmmx
5557 && !operand_types[t->operands > 1].bitfield.regsimd)))
5560 /* Do not verify operands when there are none. */
5564 /* We've found a match; break out of loop. */
5568 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5569 into Disp32/Disp16/Disp32 operand. */
5570 if (i.prefix[ADDR_PREFIX] != 0)
5572 /* There should be only one Disp operand. */
5576 for (j = 0; j < MAX_OPERANDS; j++)
5578 if (operand_types[j].bitfield.disp16)
5580 addr_prefix_disp = j;
5581 operand_types[j].bitfield.disp32 = 1;
5582 operand_types[j].bitfield.disp16 = 0;
5588 for (j = 0; j < MAX_OPERANDS; j++)
5590 if (operand_types[j].bitfield.disp32)
5592 addr_prefix_disp = j;
5593 operand_types[j].bitfield.disp32 = 0;
5594 operand_types[j].bitfield.disp16 = 1;
5600 for (j = 0; j < MAX_OPERANDS; j++)
5602 if (operand_types[j].bitfield.disp64)
5604 addr_prefix_disp = j;
5605 operand_types[j].bitfield.disp64 = 0;
5606 operand_types[j].bitfield.disp32 = 1;
5614 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5615 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5618 /* We check register size if needed. */
5619 if (t->opcode_modifier.checkregsize)
5621 check_register = (1 << t->operands) - 1;
5623 check_register &= ~(1 << i.broadcast->operand);
5628 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5629 switch (t->operands)
5632 if (!operand_type_match (overlap0, i.types[0]))
5636 /* xchg %eax, %eax is a special case. It is an alias for nop
5637 only in 32bit mode and we can use opcode 0x90. In 64bit
5638 mode, we can't use 0x90 for xchg %eax, %eax since it should
5639 zero-extend %eax to %rax. */
5640 if (flag_code == CODE_64BIT
5641 && t->base_opcode == 0x90
5642 && operand_type_equal (&i.types [0], &acc32)
5643 && operand_type_equal (&i.types [1], &acc32))
5645 /* xrelease mov %eax, <disp> is another special case. It must not
5646 match the accumulator-only encoding of mov. */
5647 if (flag_code != CODE_64BIT
5649 && t->base_opcode == 0xa0
5650 && i.types[0].bitfield.acc
5651 && operand_type_check (i.types[1], anymem))
5653 if (!(size_match & MATCH_STRAIGHT))
5655 /* If we want store form, we reverse direction of operands. */
5656 if (i.dir_encoding == dir_encoding_store
5657 && t->opcode_modifier.d)
5662 /* If we want store form, we skip the current load. */
5663 if (i.dir_encoding == dir_encoding_store
5664 && i.mem_operands == 0
5665 && t->opcode_modifier.load)
5670 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5671 if (!operand_type_match (overlap0, i.types[0])
5672 || !operand_type_match (overlap1, i.types[1])
5673 || ((check_register & 3) == 3
5674 && !operand_type_register_match (i.types[0],
5679 /* Check if other direction is valid ... */
5680 if (!t->opcode_modifier.d)
5684 if (!(size_match & MATCH_REVERSE))
5686 /* Try reversing direction of operands. */
5687 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5688 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5689 if (!operand_type_match (overlap0, i.types[0])
5690 || !operand_type_match (overlap1, i.types[1])
5692 && !operand_type_register_match (i.types[0],
5697 /* Does not match either direction. */
5700 /* found_reverse_match holds which of D or FloatR
5702 if (!t->opcode_modifier.d)
5703 found_reverse_match = 0;
5704 else if (operand_types[0].bitfield.tbyte)
5705 found_reverse_match = Opcode_FloatD;
5707 found_reverse_match = Opcode_D;
5708 if (t->opcode_modifier.floatr)
5709 found_reverse_match |= Opcode_FloatR;
5713 /* Found a forward 2 operand match here. */
5714 switch (t->operands)
5717 overlap4 = operand_type_and (i.types[4],
5721 overlap3 = operand_type_and (i.types[3],
5725 overlap2 = operand_type_and (i.types[2],
5730 switch (t->operands)
5733 if (!operand_type_match (overlap4, i.types[4])
5734 || !operand_type_register_match (i.types[3],
5741 if (!operand_type_match (overlap3, i.types[3])
5742 || ((check_register & 0xa) == 0xa
5743 && !operand_type_register_match (i.types[1],
5747 || ((check_register & 0xc) == 0xc
5748 && !operand_type_register_match (i.types[2],
5755 /* Here we make use of the fact that there are no
5756 reverse match 3 operand instructions. */
5757 if (!operand_type_match (overlap2, i.types[2])
5758 || ((check_register & 5) == 5
5759 && !operand_type_register_match (i.types[0],
5763 || ((check_register & 6) == 6
5764 && !operand_type_register_match (i.types[1],
5772 /* Found either forward/reverse 2, 3 or 4 operand match here:
5773 slip through to break. */
5775 if (!found_cpu_match)
5777 found_reverse_match = 0;
5781 /* Check if vector and VEX operands are valid. */
5782 if (check_VecOperands (t) || VEX_check_operands (t))
5784 specific_error = i.error;
5788 /* We've found a match; break out of loop. */
5792 if (t == current_templates->end)
5794 /* We found no match. */
5795 const char *err_msg;
5796 switch (specific_error ? specific_error : i.error)
5800 case operand_size_mismatch:
5801 err_msg = _("operand size mismatch");
5803 case operand_type_mismatch:
5804 err_msg = _("operand type mismatch");
5806 case register_type_mismatch:
5807 err_msg = _("register type mismatch");
5809 case number_of_operands_mismatch:
5810 err_msg = _("number of operands mismatch");
5812 case invalid_instruction_suffix:
5813 err_msg = _("invalid instruction suffix");
5816 err_msg = _("constant doesn't fit in 4 bits");
5818 case unsupported_with_intel_mnemonic:
5819 err_msg = _("unsupported with Intel mnemonic");
5821 case unsupported_syntax:
5822 err_msg = _("unsupported syntax");
5825 as_bad (_("unsupported instruction `%s'"),
5826 current_templates->start->name);
5828 case invalid_vsib_address:
5829 err_msg = _("invalid VSIB address");
5831 case invalid_vector_register_set:
5832 err_msg = _("mask, index, and destination registers must be distinct");
5834 case unsupported_vector_index_register:
5835 err_msg = _("unsupported vector index register");
5837 case unsupported_broadcast:
5838 err_msg = _("unsupported broadcast");
5840 case broadcast_needed:
5841 err_msg = _("broadcast is needed for operand of such type");
5843 case unsupported_masking:
5844 err_msg = _("unsupported masking");
5846 case mask_not_on_destination:
5847 err_msg = _("mask not on destination operand");
5849 case no_default_mask:
5850 err_msg = _("default mask isn't allowed");
5852 case unsupported_rc_sae:
5853 err_msg = _("unsupported static rounding/sae");
5855 case rc_sae_operand_not_last_imm:
5857 err_msg = _("RC/SAE operand must precede immediate operands");
5859 err_msg = _("RC/SAE operand must follow immediate operands");
5861 case invalid_register_operand:
5862 err_msg = _("invalid register operand");
5865 as_bad (_("%s for `%s'"), err_msg,
5866 current_templates->start->name);
5870 if (!quiet_warnings)
5873 && (i.types[0].bitfield.jumpabsolute
5874 != operand_types[0].bitfield.jumpabsolute))
5876 as_warn (_("indirect %s without `*'"), t->name);
5879 if (t->opcode_modifier.isprefix
5880 && t->opcode_modifier.ignoresize)
5882 /* Warn them that a data or address size prefix doesn't
5883 affect assembly of the next line of code. */
5884 as_warn (_("stand-alone `%s' prefix"), t->name);
5888 /* Copy the template we found. */
5891 if (addr_prefix_disp != -1)
5892 i.tm.operand_types[addr_prefix_disp]
5893 = operand_types[addr_prefix_disp];
5895 if (found_reverse_match)
5897 /* If we found a reverse match we must alter the opcode
5898 direction bit. found_reverse_match holds bits to change
5899 (different for int & float insns). */
5901 i.tm.base_opcode ^= found_reverse_match;
5903 i.tm.operand_types[0] = operand_types[1];
5904 i.tm.operand_types[1] = operand_types[0];
5913 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5914 if (i.tm.operand_types[mem_op].bitfield.esseg)
5916 if (i.seg[0] != NULL && i.seg[0] != &es)
5918 as_bad (_("`%s' operand %d must use `%ses' segment"),
5924 /* There's only ever one segment override allowed per instruction.
5925 This instruction possibly has a legal segment override on the
5926 second operand, so copy the segment to where non-string
5927 instructions store it, allowing common code. */
5928 i.seg[0] = i.seg[1];
5930 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5932 if (i.seg[1] != NULL && i.seg[1] != &es)
5934 as_bad (_("`%s' operand %d must use `%ses' segment"),
5945 process_suffix (void)
5947 /* If matched instruction specifies an explicit instruction mnemonic
5949 if (i.tm.opcode_modifier.size16)
5950 i.suffix = WORD_MNEM_SUFFIX;
5951 else if (i.tm.opcode_modifier.size32)
5952 i.suffix = LONG_MNEM_SUFFIX;
5953 else if (i.tm.opcode_modifier.size64)
5954 i.suffix = QWORD_MNEM_SUFFIX;
5955 else if (i.reg_operands)
5957 /* If there's no instruction mnemonic suffix we try to invent one
5958 based on register operands. */
5961 /* We take i.suffix from the last register operand specified,
5962 Destination register type is more significant than source
5963 register type. crc32 in SSE4.2 prefers source register
5965 if (i.tm.base_opcode == 0xf20f38f1)
5967 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5968 i.suffix = WORD_MNEM_SUFFIX;
5969 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5970 i.suffix = LONG_MNEM_SUFFIX;
5971 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5972 i.suffix = QWORD_MNEM_SUFFIX;
5974 else if (i.tm.base_opcode == 0xf20f38f0)
5976 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5977 i.suffix = BYTE_MNEM_SUFFIX;
5984 if (i.tm.base_opcode == 0xf20f38f1
5985 || i.tm.base_opcode == 0xf20f38f0)
5987 /* We have to know the operand size for crc32. */
5988 as_bad (_("ambiguous memory operand size for `%s`"),
5993 for (op = i.operands; --op >= 0;)
5994 if (!i.tm.operand_types[op].bitfield.inoutportreg
5995 && !i.tm.operand_types[op].bitfield.shiftcount)
5997 if (!i.types[op].bitfield.reg)
5999 if (i.types[op].bitfield.byte)
6000 i.suffix = BYTE_MNEM_SUFFIX;
6001 else if (i.types[op].bitfield.word)
6002 i.suffix = WORD_MNEM_SUFFIX;
6003 else if (i.types[op].bitfield.dword)
6004 i.suffix = LONG_MNEM_SUFFIX;
6005 else if (i.types[op].bitfield.qword)
6006 i.suffix = QWORD_MNEM_SUFFIX;
6013 else if (i.suffix == BYTE_MNEM_SUFFIX)
6016 && i.tm.opcode_modifier.ignoresize
6017 && i.tm.opcode_modifier.no_bsuf)
6019 else if (!check_byte_reg ())
6022 else if (i.suffix == LONG_MNEM_SUFFIX)
6025 && i.tm.opcode_modifier.ignoresize
6026 && i.tm.opcode_modifier.no_lsuf
6027 && !i.tm.opcode_modifier.todword
6028 && !i.tm.opcode_modifier.toqword)
6030 else if (!check_long_reg ())
6033 else if (i.suffix == QWORD_MNEM_SUFFIX)
6036 && i.tm.opcode_modifier.ignoresize
6037 && i.tm.opcode_modifier.no_qsuf
6038 && !i.tm.opcode_modifier.todword
6039 && !i.tm.opcode_modifier.toqword)
6041 else if (!check_qword_reg ())
6044 else if (i.suffix == WORD_MNEM_SUFFIX)
6047 && i.tm.opcode_modifier.ignoresize
6048 && i.tm.opcode_modifier.no_wsuf)
6050 else if (!check_word_reg ())
6053 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6054 /* Do nothing if the instruction is going to ignore the prefix. */
6059 else if (i.tm.opcode_modifier.defaultsize
6061 /* exclude fldenv/frstor/fsave/fstenv */
6062 && i.tm.opcode_modifier.no_ssuf)
6064 i.suffix = stackop_size;
6066 else if (intel_syntax
6068 && (i.tm.operand_types[0].bitfield.jumpabsolute
6069 || i.tm.opcode_modifier.jumpbyte
6070 || i.tm.opcode_modifier.jumpintersegment
6071 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6072 && i.tm.extension_opcode <= 3)))
6077 if (!i.tm.opcode_modifier.no_qsuf)
6079 i.suffix = QWORD_MNEM_SUFFIX;
6084 if (!i.tm.opcode_modifier.no_lsuf)
6085 i.suffix = LONG_MNEM_SUFFIX;
6088 if (!i.tm.opcode_modifier.no_wsuf)
6089 i.suffix = WORD_MNEM_SUFFIX;
6098 if (i.tm.opcode_modifier.w)
6100 as_bad (_("no instruction mnemonic suffix given and "
6101 "no register operands; can't size instruction"));
6107 unsigned int suffixes;
6109 suffixes = !i.tm.opcode_modifier.no_bsuf;
6110 if (!i.tm.opcode_modifier.no_wsuf)
6112 if (!i.tm.opcode_modifier.no_lsuf)
6114 if (!i.tm.opcode_modifier.no_ldsuf)
6116 if (!i.tm.opcode_modifier.no_ssuf)
6118 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6121 /* There are more than suffix matches. */
6122 if (i.tm.opcode_modifier.w
6123 || ((suffixes & (suffixes - 1))
6124 && !i.tm.opcode_modifier.defaultsize
6125 && !i.tm.opcode_modifier.ignoresize))
6127 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6133 /* Change the opcode based on the operand size given by i.suffix. */
6136 /* Size floating point instruction. */
6137 case LONG_MNEM_SUFFIX:
6138 if (i.tm.opcode_modifier.floatmf)
6140 i.tm.base_opcode ^= 4;
6144 case WORD_MNEM_SUFFIX:
6145 case QWORD_MNEM_SUFFIX:
6146 /* It's not a byte, select word/dword operation. */
6147 if (i.tm.opcode_modifier.w)
6149 if (i.tm.opcode_modifier.shortform)
6150 i.tm.base_opcode |= 8;
6152 i.tm.base_opcode |= 1;
6155 case SHORT_MNEM_SUFFIX:
6156 /* Now select between word & dword operations via the operand
6157 size prefix, except for instructions that will ignore this
6159 if (i.reg_operands > 0
6160 && i.types[0].bitfield.reg
6161 && i.tm.opcode_modifier.addrprefixopreg
6162 && (i.tm.opcode_modifier.immext
6163 || i.operands == 1))
6165 /* The address size override prefix changes the size of the
6167 if ((flag_code == CODE_32BIT
6168 && i.op[0].regs->reg_type.bitfield.word)
6169 || (flag_code != CODE_32BIT
6170 && i.op[0].regs->reg_type.bitfield.dword))
6171 if (!add_prefix (ADDR_PREFIX_OPCODE))
6174 else if (i.suffix != QWORD_MNEM_SUFFIX
6175 && !i.tm.opcode_modifier.ignoresize
6176 && !i.tm.opcode_modifier.floatmf
6177 && !i.tm.opcode_modifier.vex
6178 && !i.tm.opcode_modifier.vexopcode
6179 && !is_evex_encoding (&i.tm)
6180 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6181 || (flag_code == CODE_64BIT
6182 && i.tm.opcode_modifier.jumpbyte)))
6184 unsigned int prefix = DATA_PREFIX_OPCODE;
6186 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6187 prefix = ADDR_PREFIX_OPCODE;
6189 if (!add_prefix (prefix))
6193 /* Set mode64 for an operand. */
6194 if (i.suffix == QWORD_MNEM_SUFFIX
6195 && flag_code == CODE_64BIT
6196 && !i.tm.opcode_modifier.norex64
6197 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6199 && ! (i.operands == 2
6200 && i.tm.base_opcode == 0x90
6201 && i.tm.extension_opcode == None
6202 && operand_type_equal (&i.types [0], &acc64)
6203 && operand_type_equal (&i.types [1], &acc64)))
6209 if (i.reg_operands != 0
6211 && i.tm.opcode_modifier.addrprefixopreg
6212 && !i.tm.opcode_modifier.immext)
6214 /* Check invalid register operand when the address size override
6215 prefix changes the size of register operands. */
6217 enum { need_word, need_dword, need_qword } need;
6219 if (flag_code == CODE_32BIT)
6220 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6223 if (i.prefix[ADDR_PREFIX])
6226 need = flag_code == CODE_64BIT ? need_qword : need_word;
6229 for (op = 0; op < i.operands; op++)
6230 if (i.types[op].bitfield.reg
6231 && ((need == need_word
6232 && !i.op[op].regs->reg_type.bitfield.word)
6233 || (need == need_dword
6234 && !i.op[op].regs->reg_type.bitfield.dword)
6235 || (need == need_qword
6236 && !i.op[op].regs->reg_type.bitfield.qword)))
6238 as_bad (_("invalid register operand size for `%s'"),
6248 check_byte_reg (void)
6252 for (op = i.operands; --op >= 0;)
6254 /* Skip non-register operands. */
6255 if (!i.types[op].bitfield.reg)
6258 /* If this is an eight bit register, it's OK. If it's the 16 or
6259 32 bit version of an eight bit register, we will just use the
6260 low portion, and that's OK too. */
6261 if (i.types[op].bitfield.byte)
6264 /* I/O port address operands are OK too. */
6265 if (i.tm.operand_types[op].bitfield.inoutportreg)
6268 /* crc32 doesn't generate this warning. */
6269 if (i.tm.base_opcode == 0xf20f38f0)
6272 if ((i.types[op].bitfield.word
6273 || i.types[op].bitfield.dword
6274 || i.types[op].bitfield.qword)
6275 && i.op[op].regs->reg_num < 4
6276 /* Prohibit these changes in 64bit mode, since the lowering
6277 would be more complicated. */
6278 && flag_code != CODE_64BIT)
6280 #if REGISTER_WARNINGS
6281 if (!quiet_warnings)
6282 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6284 (i.op[op].regs + (i.types[op].bitfield.word
6285 ? REGNAM_AL - REGNAM_AX
6286 : REGNAM_AL - REGNAM_EAX))->reg_name,
6288 i.op[op].regs->reg_name,
6293 /* Any other register is bad. */
6294 if (i.types[op].bitfield.reg
6295 || i.types[op].bitfield.regmmx
6296 || i.types[op].bitfield.regsimd
6297 || i.types[op].bitfield.sreg2
6298 || i.types[op].bitfield.sreg3
6299 || i.types[op].bitfield.control
6300 || i.types[op].bitfield.debug
6301 || i.types[op].bitfield.test)
6303 as_bad (_("`%s%s' not allowed with `%s%c'"),
6305 i.op[op].regs->reg_name,
6315 check_long_reg (void)
6319 for (op = i.operands; --op >= 0;)
6320 /* Skip non-register operands. */
6321 if (!i.types[op].bitfield.reg)
6323 /* Reject eight bit registers, except where the template requires
6324 them. (eg. movzb) */
6325 else if (i.types[op].bitfield.byte
6326 && (i.tm.operand_types[op].bitfield.reg
6327 || i.tm.operand_types[op].bitfield.acc)
6328 && (i.tm.operand_types[op].bitfield.word
6329 || i.tm.operand_types[op].bitfield.dword))
6331 as_bad (_("`%s%s' not allowed with `%s%c'"),
6333 i.op[op].regs->reg_name,
6338 /* Warn if the e prefix on a general reg is missing. */
6339 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6340 && i.types[op].bitfield.word
6341 && (i.tm.operand_types[op].bitfield.reg
6342 || i.tm.operand_types[op].bitfield.acc)
6343 && i.tm.operand_types[op].bitfield.dword)
6345 /* Prohibit these changes in the 64bit mode, since the
6346 lowering is more complicated. */
6347 if (flag_code == CODE_64BIT)
6349 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6350 register_prefix, i.op[op].regs->reg_name,
6354 #if REGISTER_WARNINGS
6355 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6357 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6358 register_prefix, i.op[op].regs->reg_name, i.suffix);
6361 /* Warn if the r prefix on a general reg is present. */
6362 else if (i.types[op].bitfield.qword
6363 && (i.tm.operand_types[op].bitfield.reg
6364 || i.tm.operand_types[op].bitfield.acc)
6365 && i.tm.operand_types[op].bitfield.dword)
6368 && i.tm.opcode_modifier.toqword
6369 && !i.types[0].bitfield.regsimd)
6371 /* Convert to QWORD. We want REX byte. */
6372 i.suffix = QWORD_MNEM_SUFFIX;
6376 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6377 register_prefix, i.op[op].regs->reg_name,
6386 check_qword_reg (void)
6390 for (op = i.operands; --op >= 0; )
6391 /* Skip non-register operands. */
6392 if (!i.types[op].bitfield.reg)
6394 /* Reject eight bit registers, except where the template requires
6395 them. (eg. movzb) */
6396 else if (i.types[op].bitfield.byte
6397 && (i.tm.operand_types[op].bitfield.reg
6398 || i.tm.operand_types[op].bitfield.acc)
6399 && (i.tm.operand_types[op].bitfield.word
6400 || i.tm.operand_types[op].bitfield.dword))
6402 as_bad (_("`%s%s' not allowed with `%s%c'"),
6404 i.op[op].regs->reg_name,
6409 /* Warn if the r prefix on a general reg is missing. */
6410 else if ((i.types[op].bitfield.word
6411 || i.types[op].bitfield.dword)
6412 && (i.tm.operand_types[op].bitfield.reg
6413 || i.tm.operand_types[op].bitfield.acc)
6414 && i.tm.operand_types[op].bitfield.qword)
6416 /* Prohibit these changes in the 64bit mode, since the
6417 lowering is more complicated. */
6419 && i.tm.opcode_modifier.todword
6420 && !i.types[0].bitfield.regsimd)
6422 /* Convert to DWORD. We don't want REX byte. */
6423 i.suffix = LONG_MNEM_SUFFIX;
6427 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6428 register_prefix, i.op[op].regs->reg_name,
6437 check_word_reg (void)
6440 for (op = i.operands; --op >= 0;)
6441 /* Skip non-register operands. */
6442 if (!i.types[op].bitfield.reg)
6444 /* Reject eight bit registers, except where the template requires
6445 them. (eg. movzb) */
6446 else if (i.types[op].bitfield.byte
6447 && (i.tm.operand_types[op].bitfield.reg
6448 || i.tm.operand_types[op].bitfield.acc)
6449 && (i.tm.operand_types[op].bitfield.word
6450 || i.tm.operand_types[op].bitfield.dword))
6452 as_bad (_("`%s%s' not allowed with `%s%c'"),
6454 i.op[op].regs->reg_name,
6459 /* Warn if the e or r prefix on a general reg is present. */
6460 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6461 && (i.types[op].bitfield.dword
6462 || i.types[op].bitfield.qword)
6463 && (i.tm.operand_types[op].bitfield.reg
6464 || i.tm.operand_types[op].bitfield.acc)
6465 && i.tm.operand_types[op].bitfield.word)
6467 /* Prohibit these changes in the 64bit mode, since the
6468 lowering is more complicated. */
6469 if (flag_code == CODE_64BIT)
6471 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6472 register_prefix, i.op[op].regs->reg_name,
6476 #if REGISTER_WARNINGS
6477 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6479 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6480 register_prefix, i.op[op].regs->reg_name, i.suffix);
6487 update_imm (unsigned int j)
6489 i386_operand_type overlap = i.types[j];
6490 if ((overlap.bitfield.imm8
6491 || overlap.bitfield.imm8s
6492 || overlap.bitfield.imm16
6493 || overlap.bitfield.imm32
6494 || overlap.bitfield.imm32s
6495 || overlap.bitfield.imm64)
6496 && !operand_type_equal (&overlap, &imm8)
6497 && !operand_type_equal (&overlap, &imm8s)
6498 && !operand_type_equal (&overlap, &imm16)
6499 && !operand_type_equal (&overlap, &imm32)
6500 && !operand_type_equal (&overlap, &imm32s)
6501 && !operand_type_equal (&overlap, &imm64))
6505 i386_operand_type temp;
6507 operand_type_set (&temp, 0);
6508 if (i.suffix == BYTE_MNEM_SUFFIX)
6510 temp.bitfield.imm8 = overlap.bitfield.imm8;
6511 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6513 else if (i.suffix == WORD_MNEM_SUFFIX)
6514 temp.bitfield.imm16 = overlap.bitfield.imm16;
6515 else if (i.suffix == QWORD_MNEM_SUFFIX)
6517 temp.bitfield.imm64 = overlap.bitfield.imm64;
6518 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6521 temp.bitfield.imm32 = overlap.bitfield.imm32;
6524 else if (operand_type_equal (&overlap, &imm16_32_32s)
6525 || operand_type_equal (&overlap, &imm16_32)
6526 || operand_type_equal (&overlap, &imm16_32s))
6528 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6533 if (!operand_type_equal (&overlap, &imm8)
6534 && !operand_type_equal (&overlap, &imm8s)
6535 && !operand_type_equal (&overlap, &imm16)
6536 && !operand_type_equal (&overlap, &imm32)
6537 && !operand_type_equal (&overlap, &imm32s)
6538 && !operand_type_equal (&overlap, &imm64))
6540 as_bad (_("no instruction mnemonic suffix given; "
6541 "can't determine immediate size"));
6545 i.types[j] = overlap;
6555 /* Update the first 2 immediate operands. */
6556 n = i.operands > 2 ? 2 : i.operands;
6559 for (j = 0; j < n; j++)
6560 if (update_imm (j) == 0)
6563 /* The 3rd operand can't be immediate operand. */
6564 gas_assert (operand_type_check (i.types[2], imm) == 0);
6571 process_operands (void)
6573 /* Default segment register this instruction will use for memory
6574 accesses. 0 means unknown. This is only for optimizing out
6575 unnecessary segment overrides. */
6576 const seg_entry *default_seg = 0;
6578 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6580 unsigned int dupl = i.operands;
6581 unsigned int dest = dupl - 1;
6584 /* The destination must be an xmm register. */
6585 gas_assert (i.reg_operands
6586 && MAX_OPERANDS > dupl
6587 && operand_type_equal (&i.types[dest], ®xmm));
6589 if (i.tm.operand_types[0].bitfield.acc
6590 && i.tm.operand_types[0].bitfield.xmmword)
6592 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6594 /* Keep xmm0 for instructions with VEX prefix and 3
6596 i.tm.operand_types[0].bitfield.acc = 0;
6597 i.tm.operand_types[0].bitfield.regsimd = 1;
6602 /* We remove the first xmm0 and keep the number of
6603 operands unchanged, which in fact duplicates the
6605 for (j = 1; j < i.operands; j++)
6607 i.op[j - 1] = i.op[j];
6608 i.types[j - 1] = i.types[j];
6609 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6613 else if (i.tm.opcode_modifier.implicit1stxmm0)
6615 gas_assert ((MAX_OPERANDS - 1) > dupl
6616 && (i.tm.opcode_modifier.vexsources
6619 /* Add the implicit xmm0 for instructions with VEX prefix
6621 for (j = i.operands; j > 0; j--)
6623 i.op[j] = i.op[j - 1];
6624 i.types[j] = i.types[j - 1];
6625 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6628 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6629 i.types[0] = regxmm;
6630 i.tm.operand_types[0] = regxmm;
6633 i.reg_operands += 2;
6638 i.op[dupl] = i.op[dest];
6639 i.types[dupl] = i.types[dest];
6640 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6649 i.op[dupl] = i.op[dest];
6650 i.types[dupl] = i.types[dest];
6651 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6654 if (i.tm.opcode_modifier.immext)
6657 else if (i.tm.operand_types[0].bitfield.acc
6658 && i.tm.operand_types[0].bitfield.xmmword)
6662 for (j = 1; j < i.operands; j++)
6664 i.op[j - 1] = i.op[j];
6665 i.types[j - 1] = i.types[j];
6667 /* We need to adjust fields in i.tm since they are used by
6668 build_modrm_byte. */
6669 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6676 else if (i.tm.opcode_modifier.implicitquadgroup)
6678 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6680 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6681 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6682 regnum = register_number (i.op[1].regs);
6683 first_reg_in_group = regnum & ~3;
6684 last_reg_in_group = first_reg_in_group + 3;
6685 if (regnum != first_reg_in_group)
6686 as_warn (_("source register `%s%s' implicitly denotes"
6687 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6688 register_prefix, i.op[1].regs->reg_name,
6689 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6690 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6693 else if (i.tm.opcode_modifier.regkludge)
6695 /* The imul $imm, %reg instruction is converted into
6696 imul $imm, %reg, %reg, and the clr %reg instruction
6697 is converted into xor %reg, %reg. */
6699 unsigned int first_reg_op;
6701 if (operand_type_check (i.types[0], reg))
6705 /* Pretend we saw the extra register operand. */
6706 gas_assert (i.reg_operands == 1
6707 && i.op[first_reg_op + 1].regs == 0);
6708 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6709 i.types[first_reg_op + 1] = i.types[first_reg_op];
6714 if (i.tm.opcode_modifier.shortform)
6716 if (i.types[0].bitfield.sreg2
6717 || i.types[0].bitfield.sreg3)
6719 if (i.tm.base_opcode == POP_SEG_SHORT
6720 && i.op[0].regs->reg_num == 1)
6722 as_bad (_("you can't `pop %scs'"), register_prefix);
6725 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6726 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6731 /* The register or float register operand is in operand
6735 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6736 || operand_type_check (i.types[0], reg))
6740 /* Register goes in low 3 bits of opcode. */
6741 i.tm.base_opcode |= i.op[op].regs->reg_num;
6742 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6744 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6746 /* Warn about some common errors, but press on regardless.
6747 The first case can be generated by gcc (<= 2.8.1). */
6748 if (i.operands == 2)
6750 /* Reversed arguments on faddp, fsubp, etc. */
6751 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6752 register_prefix, i.op[!intel_syntax].regs->reg_name,
6753 register_prefix, i.op[intel_syntax].regs->reg_name);
6757 /* Extraneous `l' suffix on fp insn. */
6758 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6759 register_prefix, i.op[0].regs->reg_name);
6764 else if (i.tm.opcode_modifier.modrm)
6766 /* The opcode is completed (modulo i.tm.extension_opcode which
6767 must be put into the modrm byte). Now, we make the modrm and
6768 index base bytes based on all the info we've collected. */
6770 default_seg = build_modrm_byte ();
6772 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6776 else if (i.tm.opcode_modifier.isstring)
6778 /* For the string instructions that allow a segment override
6779 on one of their operands, the default segment is ds. */
6783 if (i.tm.base_opcode == 0x8d /* lea */
6786 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6788 /* If a segment was explicitly specified, and the specified segment
6789 is not the default, use an opcode prefix to select it. If we
6790 never figured out what the default segment is, then default_seg
6791 will be zero at this point, and the specified segment prefix will
6793 if ((i.seg[0]) && (i.seg[0] != default_seg))
6795 if (!add_prefix (i.seg[0]->seg_prefix))
6801 static const seg_entry *
6802 build_modrm_byte (void)
6804 const seg_entry *default_seg = 0;
6805 unsigned int source, dest;
6808 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6811 unsigned int nds, reg_slot;
6814 dest = i.operands - 1;
6817 /* There are 2 kinds of instructions:
6818 1. 5 operands: 4 register operands or 3 register operands
6819 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6820 VexW0 or VexW1. The destination must be either XMM, YMM or
6822 2. 4 operands: 4 register operands or 3 register operands
6823 plus 1 memory operand, with VexXDS. */
6824 gas_assert ((i.reg_operands == 4
6825 || (i.reg_operands == 3 && i.mem_operands == 1))
6826 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6827 && i.tm.opcode_modifier.vexw
6828 && i.tm.operand_types[dest].bitfield.regsimd);
6830 /* If VexW1 is set, the first non-immediate operand is the source and
6831 the second non-immediate one is encoded in the immediate operand. */
6832 if (i.tm.opcode_modifier.vexw == VEXW1)
6834 source = i.imm_operands;
6835 reg_slot = i.imm_operands + 1;
6839 source = i.imm_operands + 1;
6840 reg_slot = i.imm_operands;
6843 if (i.imm_operands == 0)
6845 /* When there is no immediate operand, generate an 8bit
6846 immediate operand to encode the first operand. */
6847 exp = &im_expressions[i.imm_operands++];
6848 i.op[i.operands].imms = exp;
6849 i.types[i.operands] = imm8;
6852 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6853 exp->X_op = O_constant;
6854 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6855 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6859 unsigned int imm_slot;
6861 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6863 if (i.tm.opcode_modifier.immext)
6865 /* When ImmExt is set, the immediate byte is the last
6867 imm_slot = i.operands - 1;
6875 /* Turn on Imm8 so that output_imm will generate it. */
6876 i.types[imm_slot].bitfield.imm8 = 1;
6879 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6880 i.op[imm_slot].imms->X_add_number
6881 |= register_number (i.op[reg_slot].regs) << 4;
6882 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6885 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6886 i.vex.register_specifier = i.op[nds].regs;
6891 /* i.reg_operands MUST be the number of real register operands;
6892 implicit registers do not count. If there are 3 register
6893 operands, it must be a instruction with VexNDS. For a
6894 instruction with VexNDD, the destination register is encoded
6895 in VEX prefix. If there are 4 register operands, it must be
6896 a instruction with VEX prefix and 3 sources. */
6897 if (i.mem_operands == 0
6898 && ((i.reg_operands == 2
6899 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6900 || (i.reg_operands == 3
6901 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6902 || (i.reg_operands == 4 && vex_3_sources)))
6910 /* When there are 3 operands, one of them may be immediate,
6911 which may be the first or the last operand. Otherwise,
6912 the first operand must be shift count register (cl) or it
6913 is an instruction with VexNDS. */
6914 gas_assert (i.imm_operands == 1
6915 || (i.imm_operands == 0
6916 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6917 || i.types[0].bitfield.shiftcount)));
6918 if (operand_type_check (i.types[0], imm)
6919 || i.types[0].bitfield.shiftcount)
6925 /* When there are 4 operands, the first two must be 8bit
6926 immediate operands. The source operand will be the 3rd
6929 For instructions with VexNDS, if the first operand
6930 an imm8, the source operand is the 2nd one. If the last
6931 operand is imm8, the source operand is the first one. */
6932 gas_assert ((i.imm_operands == 2
6933 && i.types[0].bitfield.imm8
6934 && i.types[1].bitfield.imm8)
6935 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6936 && i.imm_operands == 1
6937 && (i.types[0].bitfield.imm8
6938 || i.types[i.operands - 1].bitfield.imm8
6940 if (i.imm_operands == 2)
6944 if (i.types[0].bitfield.imm8)
6951 if (is_evex_encoding (&i.tm))
6953 /* For EVEX instructions, when there are 5 operands, the
6954 first one must be immediate operand. If the second one
6955 is immediate operand, the source operand is the 3th
6956 one. If the last one is immediate operand, the source
6957 operand is the 2nd one. */
6958 gas_assert (i.imm_operands == 2
6959 && i.tm.opcode_modifier.sae
6960 && operand_type_check (i.types[0], imm));
6961 if (operand_type_check (i.types[1], imm))
6963 else if (operand_type_check (i.types[4], imm))
6977 /* RC/SAE operand could be between DEST and SRC. That happens
6978 when one operand is GPR and the other one is XMM/YMM/ZMM
6980 if (i.rounding && i.rounding->operand == (int) dest)
6983 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6985 /* For instructions with VexNDS, the register-only source
6986 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6987 register. It is encoded in VEX prefix. We need to
6988 clear RegMem bit before calling operand_type_equal. */
6990 i386_operand_type op;
6993 /* Check register-only source operand when two source
6994 operands are swapped. */
6995 if (!i.tm.operand_types[source].bitfield.baseindex
6996 && i.tm.operand_types[dest].bitfield.baseindex)
7004 op = i.tm.operand_types[vvvv];
7005 op.bitfield.regmem = 0;
7006 if ((dest + 1) >= i.operands
7007 || ((!op.bitfield.reg
7008 || (!op.bitfield.dword && !op.bitfield.qword))
7009 && !op.bitfield.regsimd
7010 && !operand_type_equal (&op, ®mask)))
7012 i.vex.register_specifier = i.op[vvvv].regs;
7018 /* One of the register operands will be encoded in the i.tm.reg
7019 field, the other in the combined i.tm.mode and i.tm.regmem
7020 fields. If no form of this instruction supports a memory
7021 destination operand, then we assume the source operand may
7022 sometimes be a memory operand and so we need to store the
7023 destination in the i.rm.reg field. */
7024 if (!i.tm.operand_types[dest].bitfield.regmem
7025 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7027 i.rm.reg = i.op[dest].regs->reg_num;
7028 i.rm.regmem = i.op[source].regs->reg_num;
7029 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7031 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7033 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7035 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7040 i.rm.reg = i.op[source].regs->reg_num;
7041 i.rm.regmem = i.op[dest].regs->reg_num;
7042 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7044 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7046 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7048 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7051 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7053 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7056 add_prefix (LOCK_PREFIX_OPCODE);
7060 { /* If it's not 2 reg operands... */
7065 unsigned int fake_zero_displacement = 0;
7068 for (op = 0; op < i.operands; op++)
7069 if (operand_type_check (i.types[op], anymem))
7071 gas_assert (op < i.operands);
7073 if (i.tm.opcode_modifier.vecsib)
7075 if (i.index_reg->reg_num == RegEiz
7076 || i.index_reg->reg_num == RegRiz)
7079 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7082 i.sib.base = NO_BASE_REGISTER;
7083 i.sib.scale = i.log2_scale_factor;
7084 i.types[op].bitfield.disp8 = 0;
7085 i.types[op].bitfield.disp16 = 0;
7086 i.types[op].bitfield.disp64 = 0;
7087 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7089 /* Must be 32 bit */
7090 i.types[op].bitfield.disp32 = 1;
7091 i.types[op].bitfield.disp32s = 0;
7095 i.types[op].bitfield.disp32 = 0;
7096 i.types[op].bitfield.disp32s = 1;
7099 i.sib.index = i.index_reg->reg_num;
7100 if ((i.index_reg->reg_flags & RegRex) != 0)
7102 if ((i.index_reg->reg_flags & RegVRex) != 0)
7108 if (i.base_reg == 0)
7111 if (!i.disp_operands)
7112 fake_zero_displacement = 1;
7113 if (i.index_reg == 0)
7115 i386_operand_type newdisp;
7117 gas_assert (!i.tm.opcode_modifier.vecsib);
7118 /* Operand is just <disp> */
7119 if (flag_code == CODE_64BIT)
7121 /* 64bit mode overwrites the 32bit absolute
7122 addressing by RIP relative addressing and
7123 absolute addressing is encoded by one of the
7124 redundant SIB forms. */
7125 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7126 i.sib.base = NO_BASE_REGISTER;
7127 i.sib.index = NO_INDEX_REGISTER;
7128 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7130 else if ((flag_code == CODE_16BIT)
7131 ^ (i.prefix[ADDR_PREFIX] != 0))
7133 i.rm.regmem = NO_BASE_REGISTER_16;
7138 i.rm.regmem = NO_BASE_REGISTER;
7141 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7142 i.types[op] = operand_type_or (i.types[op], newdisp);
7144 else if (!i.tm.opcode_modifier.vecsib)
7146 /* !i.base_reg && i.index_reg */
7147 if (i.index_reg->reg_num == RegEiz
7148 || i.index_reg->reg_num == RegRiz)
7149 i.sib.index = NO_INDEX_REGISTER;
7151 i.sib.index = i.index_reg->reg_num;
7152 i.sib.base = NO_BASE_REGISTER;
7153 i.sib.scale = i.log2_scale_factor;
7154 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7155 i.types[op].bitfield.disp8 = 0;
7156 i.types[op].bitfield.disp16 = 0;
7157 i.types[op].bitfield.disp64 = 0;
7158 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7160 /* Must be 32 bit */
7161 i.types[op].bitfield.disp32 = 1;
7162 i.types[op].bitfield.disp32s = 0;
7166 i.types[op].bitfield.disp32 = 0;
7167 i.types[op].bitfield.disp32s = 1;
7169 if ((i.index_reg->reg_flags & RegRex) != 0)
7173 /* RIP addressing for 64bit mode. */
7174 else if (i.base_reg->reg_num == RegRip ||
7175 i.base_reg->reg_num == RegEip)
7177 gas_assert (!i.tm.opcode_modifier.vecsib);
7178 i.rm.regmem = NO_BASE_REGISTER;
7179 i.types[op].bitfield.disp8 = 0;
7180 i.types[op].bitfield.disp16 = 0;
7181 i.types[op].bitfield.disp32 = 0;
7182 i.types[op].bitfield.disp32s = 1;
7183 i.types[op].bitfield.disp64 = 0;
7184 i.flags[op] |= Operand_PCrel;
7185 if (! i.disp_operands)
7186 fake_zero_displacement = 1;
7188 else if (i.base_reg->reg_type.bitfield.word)
7190 gas_assert (!i.tm.opcode_modifier.vecsib);
7191 switch (i.base_reg->reg_num)
7194 if (i.index_reg == 0)
7196 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7197 i.rm.regmem = i.index_reg->reg_num - 6;
7201 if (i.index_reg == 0)
7204 if (operand_type_check (i.types[op], disp) == 0)
7206 /* fake (%bp) into 0(%bp) */
7207 i.types[op].bitfield.disp8 = 1;
7208 fake_zero_displacement = 1;
7211 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7212 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7214 default: /* (%si) -> 4 or (%di) -> 5 */
7215 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7217 i.rm.mode = mode_from_disp_size (i.types[op]);
7219 else /* i.base_reg and 32/64 bit mode */
7221 if (flag_code == CODE_64BIT
7222 && operand_type_check (i.types[op], disp))
7224 i.types[op].bitfield.disp16 = 0;
7225 i.types[op].bitfield.disp64 = 0;
7226 if (i.prefix[ADDR_PREFIX] == 0)
7228 i.types[op].bitfield.disp32 = 0;
7229 i.types[op].bitfield.disp32s = 1;
7233 i.types[op].bitfield.disp32 = 1;
7234 i.types[op].bitfield.disp32s = 0;
7238 if (!i.tm.opcode_modifier.vecsib)
7239 i.rm.regmem = i.base_reg->reg_num;
7240 if ((i.base_reg->reg_flags & RegRex) != 0)
7242 i.sib.base = i.base_reg->reg_num;
7243 /* x86-64 ignores REX prefix bit here to avoid decoder
7245 if (!(i.base_reg->reg_flags & RegRex)
7246 && (i.base_reg->reg_num == EBP_REG_NUM
7247 || i.base_reg->reg_num == ESP_REG_NUM))
7249 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7251 fake_zero_displacement = 1;
7252 i.types[op].bitfield.disp8 = 1;
7254 i.sib.scale = i.log2_scale_factor;
7255 if (i.index_reg == 0)
7257 gas_assert (!i.tm.opcode_modifier.vecsib);
7258 /* <disp>(%esp) becomes two byte modrm with no index
7259 register. We've already stored the code for esp
7260 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7261 Any base register besides %esp will not use the
7262 extra modrm byte. */
7263 i.sib.index = NO_INDEX_REGISTER;
7265 else if (!i.tm.opcode_modifier.vecsib)
7267 if (i.index_reg->reg_num == RegEiz
7268 || i.index_reg->reg_num == RegRiz)
7269 i.sib.index = NO_INDEX_REGISTER;
7271 i.sib.index = i.index_reg->reg_num;
7272 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7273 if ((i.index_reg->reg_flags & RegRex) != 0)
7278 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7279 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7283 if (!fake_zero_displacement
7287 fake_zero_displacement = 1;
7288 if (i.disp_encoding == disp_encoding_8bit)
7289 i.types[op].bitfield.disp8 = 1;
7291 i.types[op].bitfield.disp32 = 1;
7293 i.rm.mode = mode_from_disp_size (i.types[op]);
7297 if (fake_zero_displacement)
7299 /* Fakes a zero displacement assuming that i.types[op]
7300 holds the correct displacement size. */
7303 gas_assert (i.op[op].disps == 0);
7304 exp = &disp_expressions[i.disp_operands++];
7305 i.op[op].disps = exp;
7306 exp->X_op = O_constant;
7307 exp->X_add_number = 0;
7308 exp->X_add_symbol = (symbolS *) 0;
7309 exp->X_op_symbol = (symbolS *) 0;
7317 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7319 if (operand_type_check (i.types[0], imm))
7320 i.vex.register_specifier = NULL;
7323 /* VEX.vvvv encodes one of the sources when the first
7324 operand is not an immediate. */
7325 if (i.tm.opcode_modifier.vexw == VEXW0)
7326 i.vex.register_specifier = i.op[0].regs;
7328 i.vex.register_specifier = i.op[1].regs;
7331 /* Destination is a XMM register encoded in the ModRM.reg
7333 i.rm.reg = i.op[2].regs->reg_num;
7334 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7337 /* ModRM.rm and VEX.B encodes the other source. */
7338 if (!i.mem_operands)
7342 if (i.tm.opcode_modifier.vexw == VEXW0)
7343 i.rm.regmem = i.op[1].regs->reg_num;
7345 i.rm.regmem = i.op[0].regs->reg_num;
7347 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7351 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7353 i.vex.register_specifier = i.op[2].regs;
7354 if (!i.mem_operands)
7357 i.rm.regmem = i.op[1].regs->reg_num;
7358 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7362 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7363 (if any) based on i.tm.extension_opcode. Again, we must be
7364 careful to make sure that segment/control/debug/test/MMX
7365 registers are coded into the i.rm.reg field. */
7366 else if (i.reg_operands)
7369 unsigned int vex_reg = ~0;
7371 for (op = 0; op < i.operands; op++)
7372 if (i.types[op].bitfield.reg
7373 || i.types[op].bitfield.regmmx
7374 || i.types[op].bitfield.regsimd
7375 || i.types[op].bitfield.regbnd
7376 || i.types[op].bitfield.regmask
7377 || i.types[op].bitfield.sreg2
7378 || i.types[op].bitfield.sreg3
7379 || i.types[op].bitfield.control
7380 || i.types[op].bitfield.debug
7381 || i.types[op].bitfield.test)
7386 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7388 /* For instructions with VexNDS, the register-only
7389 source operand is encoded in VEX prefix. */
7390 gas_assert (mem != (unsigned int) ~0);
7395 gas_assert (op < i.operands);
7399 /* Check register-only source operand when two source
7400 operands are swapped. */
7401 if (!i.tm.operand_types[op].bitfield.baseindex
7402 && i.tm.operand_types[op + 1].bitfield.baseindex)
7406 gas_assert (mem == (vex_reg + 1)
7407 && op < i.operands);
7412 gas_assert (vex_reg < i.operands);
7416 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7418 /* For instructions with VexNDD, the register destination
7419 is encoded in VEX prefix. */
7420 if (i.mem_operands == 0)
7422 /* There is no memory operand. */
7423 gas_assert ((op + 2) == i.operands);
7428 /* There are only 2 non-immediate operands. */
7429 gas_assert (op < i.imm_operands + 2
7430 && i.operands == i.imm_operands + 2);
7431 vex_reg = i.imm_operands + 1;
7435 gas_assert (op < i.operands);
7437 if (vex_reg != (unsigned int) ~0)
7439 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7441 if ((!type->bitfield.reg
7442 || (!type->bitfield.dword && !type->bitfield.qword))
7443 && !type->bitfield.regsimd
7444 && !operand_type_equal (type, ®mask))
7447 i.vex.register_specifier = i.op[vex_reg].regs;
7450 /* Don't set OP operand twice. */
7453 /* If there is an extension opcode to put here, the
7454 register number must be put into the regmem field. */
7455 if (i.tm.extension_opcode != None)
7457 i.rm.regmem = i.op[op].regs->reg_num;
7458 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7460 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7465 i.rm.reg = i.op[op].regs->reg_num;
7466 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7468 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7473 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7474 must set it to 3 to indicate this is a register operand
7475 in the regmem field. */
7476 if (!i.mem_operands)
7480 /* Fill in i.rm.reg field with extension opcode (if any). */
7481 if (i.tm.extension_opcode != None)
7482 i.rm.reg = i.tm.extension_opcode;
7488 output_branch (void)
7494 relax_substateT subtype;
7498 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7499 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7502 if (i.prefix[DATA_PREFIX] != 0)
7508 /* Pentium4 branch hints. */
7509 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7510 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7515 if (i.prefix[REX_PREFIX] != 0)
7521 /* BND prefixed jump. */
7522 if (i.prefix[BND_PREFIX] != 0)
7524 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7528 if (i.prefixes != 0 && !intel_syntax)
7529 as_warn (_("skipping prefixes on this instruction"));
7531 /* It's always a symbol; End frag & setup for relax.
7532 Make sure there is enough room in this frag for the largest
7533 instruction we may generate in md_convert_frag. This is 2
7534 bytes for the opcode and room for the prefix and largest
7536 frag_grow (prefix + 2 + 4);
7537 /* Prefix and 1 opcode byte go in fr_fix. */
7538 p = frag_more (prefix + 1);
7539 if (i.prefix[DATA_PREFIX] != 0)
7540 *p++ = DATA_PREFIX_OPCODE;
7541 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7542 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7543 *p++ = i.prefix[SEG_PREFIX];
7544 if (i.prefix[REX_PREFIX] != 0)
7545 *p++ = i.prefix[REX_PREFIX];
7546 *p = i.tm.base_opcode;
7548 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7549 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7550 else if (cpu_arch_flags.bitfield.cpui386)
7551 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7553 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7556 sym = i.op[0].disps->X_add_symbol;
7557 off = i.op[0].disps->X_add_number;
7559 if (i.op[0].disps->X_op != O_constant
7560 && i.op[0].disps->X_op != O_symbol)
7562 /* Handle complex expressions. */
7563 sym = make_expr_symbol (i.op[0].disps);
7567 /* 1 possible extra opcode + 4 byte displacement go in var part.
7568 Pass reloc in fr_var. */
7569 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7573 /* Return TRUE iff PLT32 relocation should be used for branching to
7577 need_plt32_p (symbolS *s)
7579 /* PLT32 relocation is ELF only. */
7583 /* Since there is no need to prepare for PLT branch on x86-64, we
7584 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7585 be used as a marker for 32-bit PC-relative branches. */
7589 /* Weak or undefined symbol need PLT32 relocation. */
7590 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7593 /* Non-global symbol doesn't need PLT32 relocation. */
7594 if (! S_IS_EXTERNAL (s))
7597 /* Other global symbols need PLT32 relocation. NB: Symbol with
7598 non-default visibilities are treated as normal global symbol
7599 so that PLT32 relocation can be used as a marker for 32-bit
7600 PC-relative branches. It is useful for linker relaxation. */
7611 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7613 if (i.tm.opcode_modifier.jumpbyte)
7615 /* This is a loop or jecxz type instruction. */
7617 if (i.prefix[ADDR_PREFIX] != 0)
7619 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7622 /* Pentium4 branch hints. */
7623 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7624 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7626 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7635 if (flag_code == CODE_16BIT)
7638 if (i.prefix[DATA_PREFIX] != 0)
7640 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7650 if (i.prefix[REX_PREFIX] != 0)
7652 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7656 /* BND prefixed jump. */
7657 if (i.prefix[BND_PREFIX] != 0)
7659 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7663 if (i.prefixes != 0 && !intel_syntax)
7664 as_warn (_("skipping prefixes on this instruction"));
7666 p = frag_more (i.tm.opcode_length + size);
7667 switch (i.tm.opcode_length)
7670 *p++ = i.tm.base_opcode >> 8;
7673 *p++ = i.tm.base_opcode;
7679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7681 && jump_reloc == NO_RELOC
7682 && need_plt32_p (i.op[0].disps->X_add_symbol))
7683 jump_reloc = BFD_RELOC_X86_64_PLT32;
7686 jump_reloc = reloc (size, 1, 1, jump_reloc);
7688 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7689 i.op[0].disps, 1, jump_reloc);
7691 /* All jumps handled here are signed, but don't use a signed limit
7692 check for 32 and 16 bit jumps as we want to allow wrap around at
7693 4G and 64k respectively. */
7695 fixP->fx_signed = 1;
7699 output_interseg_jump (void)
7707 if (flag_code == CODE_16BIT)
7711 if (i.prefix[DATA_PREFIX] != 0)
7717 if (i.prefix[REX_PREFIX] != 0)
7727 if (i.prefixes != 0 && !intel_syntax)
7728 as_warn (_("skipping prefixes on this instruction"));
7730 /* 1 opcode; 2 segment; offset */
7731 p = frag_more (prefix + 1 + 2 + size);
7733 if (i.prefix[DATA_PREFIX] != 0)
7734 *p++ = DATA_PREFIX_OPCODE;
7736 if (i.prefix[REX_PREFIX] != 0)
7737 *p++ = i.prefix[REX_PREFIX];
7739 *p++ = i.tm.base_opcode;
7740 if (i.op[1].imms->X_op == O_constant)
7742 offsetT n = i.op[1].imms->X_add_number;
7745 && !fits_in_unsigned_word (n)
7746 && !fits_in_signed_word (n))
7748 as_bad (_("16-bit jump out of range"));
7751 md_number_to_chars (p, n, size);
7754 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7755 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7756 if (i.op[0].imms->X_op != O_constant)
7757 as_bad (_("can't handle non absolute segment in `%s'"),
7759 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7765 fragS *insn_start_frag;
7766 offsetT insn_start_off;
7768 /* Tie dwarf2 debug info to the address at the start of the insn.
7769 We can't do this after the insn has been output as the current
7770 frag may have been closed off. eg. by frag_var. */
7771 dwarf2_emit_insn (0);
7773 insn_start_frag = frag_now;
7774 insn_start_off = frag_now_fix ();
7777 if (i.tm.opcode_modifier.jump)
7779 else if (i.tm.opcode_modifier.jumpbyte
7780 || i.tm.opcode_modifier.jumpdword)
7782 else if (i.tm.opcode_modifier.jumpintersegment)
7783 output_interseg_jump ();
7786 /* Output normal instructions here. */
7790 unsigned int prefix;
7793 && i.tm.base_opcode == 0xfae
7795 && i.imm_operands == 1
7796 && (i.op[0].imms->X_add_number == 0xe8
7797 || i.op[0].imms->X_add_number == 0xf0
7798 || i.op[0].imms->X_add_number == 0xf8))
7800 /* Encode lfence, mfence, and sfence as
7801 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7802 offsetT val = 0x240483f0ULL;
7804 md_number_to_chars (p, val, 5);
7808 /* Some processors fail on LOCK prefix. This options makes
7809 assembler ignore LOCK prefix and serves as a workaround. */
7810 if (omit_lock_prefix)
7812 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7814 i.prefix[LOCK_PREFIX] = 0;
7817 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7818 don't need the explicit prefix. */
7819 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7821 switch (i.tm.opcode_length)
7824 if (i.tm.base_opcode & 0xff000000)
7826 prefix = (i.tm.base_opcode >> 24) & 0xff;
7827 add_prefix (prefix);
7831 if ((i.tm.base_opcode & 0xff0000) != 0)
7833 prefix = (i.tm.base_opcode >> 16) & 0xff;
7834 if (!i.tm.cpu_flags.bitfield.cpupadlock
7835 || prefix != REPE_PREFIX_OPCODE
7836 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7837 add_prefix (prefix);
7843 /* Check for pseudo prefixes. */
7844 as_bad_where (insn_start_frag->fr_file,
7845 insn_start_frag->fr_line,
7846 _("pseudo prefix without instruction"));
7852 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7853 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7854 R_X86_64_GOTTPOFF relocation so that linker can safely
7855 perform IE->LE optimization. */
7856 if (x86_elf_abi == X86_64_X32_ABI
7858 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7859 && i.prefix[REX_PREFIX] == 0)
7860 add_prefix (REX_OPCODE);
7863 /* The prefix bytes. */
7864 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7866 FRAG_APPEND_1_CHAR (*q);
7870 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7875 /* REX byte is encoded in VEX prefix. */
7879 FRAG_APPEND_1_CHAR (*q);
7882 /* There should be no other prefixes for instructions
7887 /* For EVEX instructions i.vrex should become 0 after
7888 build_evex_prefix. For VEX instructions upper 16 registers
7889 aren't available, so VREX should be 0. */
7892 /* Now the VEX prefix. */
7893 p = frag_more (i.vex.length);
7894 for (j = 0; j < i.vex.length; j++)
7895 p[j] = i.vex.bytes[j];
7898 /* Now the opcode; be careful about word order here! */
7899 if (i.tm.opcode_length == 1)
7901 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7905 switch (i.tm.opcode_length)
7909 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7910 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7914 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7924 /* Put out high byte first: can't use md_number_to_chars! */
7925 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7926 *p = i.tm.base_opcode & 0xff;
7929 /* Now the modrm byte and sib byte (if present). */
7930 if (i.tm.opcode_modifier.modrm)
7932 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7935 /* If i.rm.regmem == ESP (4)
7936 && i.rm.mode != (Register mode)
7938 ==> need second modrm byte. */
7939 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7941 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7942 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7944 | i.sib.scale << 6));
7947 if (i.disp_operands)
7948 output_disp (insn_start_frag, insn_start_off);
7951 output_imm (insn_start_frag, insn_start_off);
7957 pi ("" /*line*/, &i);
7959 #endif /* DEBUG386 */
7962 /* Return the size of the displacement operand N. */
7965 disp_size (unsigned int n)
7969 if (i.types[n].bitfield.disp64)
7971 else if (i.types[n].bitfield.disp8)
7973 else if (i.types[n].bitfield.disp16)
7978 /* Return the size of the immediate operand N. */
7981 imm_size (unsigned int n)
7984 if (i.types[n].bitfield.imm64)
7986 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7988 else if (i.types[n].bitfield.imm16)
7994 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7999 for (n = 0; n < i.operands; n++)
8001 if (operand_type_check (i.types[n], disp))
8003 if (i.op[n].disps->X_op == O_constant)
8005 int size = disp_size (n);
8006 offsetT val = i.op[n].disps->X_add_number;
8008 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8010 p = frag_more (size);
8011 md_number_to_chars (p, val, size);
8015 enum bfd_reloc_code_real reloc_type;
8016 int size = disp_size (n);
8017 int sign = i.types[n].bitfield.disp32s;
8018 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8021 /* We can't have 8 bit displacement here. */
8022 gas_assert (!i.types[n].bitfield.disp8);
8024 /* The PC relative address is computed relative
8025 to the instruction boundary, so in case immediate
8026 fields follows, we need to adjust the value. */
8027 if (pcrel && i.imm_operands)
8032 for (n1 = 0; n1 < i.operands; n1++)
8033 if (operand_type_check (i.types[n1], imm))
8035 /* Only one immediate is allowed for PC
8036 relative address. */
8037 gas_assert (sz == 0);
8039 i.op[n].disps->X_add_number -= sz;
8041 /* We should find the immediate. */
8042 gas_assert (sz != 0);
8045 p = frag_more (size);
8046 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8048 && GOT_symbol == i.op[n].disps->X_add_symbol
8049 && (((reloc_type == BFD_RELOC_32
8050 || reloc_type == BFD_RELOC_X86_64_32S
8051 || (reloc_type == BFD_RELOC_64
8053 && (i.op[n].disps->X_op == O_symbol
8054 || (i.op[n].disps->X_op == O_add
8055 && ((symbol_get_value_expression
8056 (i.op[n].disps->X_op_symbol)->X_op)
8058 || reloc_type == BFD_RELOC_32_PCREL))
8062 if (insn_start_frag == frag_now)
8063 add = (p - frag_now->fr_literal) - insn_start_off;
8068 add = insn_start_frag->fr_fix - insn_start_off;
8069 for (fr = insn_start_frag->fr_next;
8070 fr && fr != frag_now; fr = fr->fr_next)
8072 add += p - frag_now->fr_literal;
8077 reloc_type = BFD_RELOC_386_GOTPC;
8078 i.op[n].imms->X_add_number += add;
8080 else if (reloc_type == BFD_RELOC_64)
8081 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8083 /* Don't do the adjustment for x86-64, as there
8084 the pcrel addressing is relative to the _next_
8085 insn, and that is taken care of in other code. */
8086 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8088 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8089 size, i.op[n].disps, pcrel,
8091 /* Check for "call/jmp *mem", "mov mem, %reg",
8092 "test %reg, mem" and "binop mem, %reg" where binop
8093 is one of adc, add, and, cmp, or, sbb, sub, xor
8094 instructions. Always generate R_386_GOT32X for
8095 "sym*GOT" operand in 32-bit mode. */
8096 if ((generate_relax_relocations
8099 && i.rm.regmem == 5))
8101 || (i.rm.mode == 0 && i.rm.regmem == 5))
8102 && ((i.operands == 1
8103 && i.tm.base_opcode == 0xff
8104 && (i.rm.reg == 2 || i.rm.reg == 4))
8106 && (i.tm.base_opcode == 0x8b
8107 || i.tm.base_opcode == 0x85
8108 || (i.tm.base_opcode & 0xc7) == 0x03))))
8112 fixP->fx_tcbit = i.rex != 0;
8114 && (i.base_reg->reg_num == RegRip
8115 || i.base_reg->reg_num == RegEip))
8116 fixP->fx_tcbit2 = 1;
8119 fixP->fx_tcbit2 = 1;
8127 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8132 for (n = 0; n < i.operands; n++)
8134 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8135 if (i.rounding && (int) n == i.rounding->operand)
8138 if (operand_type_check (i.types[n], imm))
8140 if (i.op[n].imms->X_op == O_constant)
8142 int size = imm_size (n);
8145 val = offset_in_range (i.op[n].imms->X_add_number,
8147 p = frag_more (size);
8148 md_number_to_chars (p, val, size);
8152 /* Not absolute_section.
8153 Need a 32-bit fixup (don't support 8bit
8154 non-absolute imms). Try to support other
8156 enum bfd_reloc_code_real reloc_type;
8157 int size = imm_size (n);
8160 if (i.types[n].bitfield.imm32s
8161 && (i.suffix == QWORD_MNEM_SUFFIX
8162 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8167 p = frag_more (size);
8168 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8170 /* This is tough to explain. We end up with this one if we
8171 * have operands that look like
8172 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8173 * obtain the absolute address of the GOT, and it is strongly
8174 * preferable from a performance point of view to avoid using
8175 * a runtime relocation for this. The actual sequence of
8176 * instructions often look something like:
8181 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8183 * The call and pop essentially return the absolute address
8184 * of the label .L66 and store it in %ebx. The linker itself
8185 * will ultimately change the first operand of the addl so
8186 * that %ebx points to the GOT, but to keep things simple, the
8187 * .o file must have this operand set so that it generates not
8188 * the absolute address of .L66, but the absolute address of
8189 * itself. This allows the linker itself simply treat a GOTPC
8190 * relocation as asking for a pcrel offset to the GOT to be
8191 * added in, and the addend of the relocation is stored in the
8192 * operand field for the instruction itself.
8194 * Our job here is to fix the operand so that it would add
8195 * the correct offset so that %ebx would point to itself. The
8196 * thing that is tricky is that .-.L66 will point to the
8197 * beginning of the instruction, so we need to further modify
8198 * the operand so that it will point to itself. There are
8199 * other cases where you have something like:
8201 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8203 * and here no correction would be required. Internally in
8204 * the assembler we treat operands of this form as not being
8205 * pcrel since the '.' is explicitly mentioned, and I wonder
8206 * whether it would simplify matters to do it this way. Who
8207 * knows. In earlier versions of the PIC patches, the
8208 * pcrel_adjust field was used to store the correction, but
8209 * since the expression is not pcrel, I felt it would be
8210 * confusing to do it this way. */
8212 if ((reloc_type == BFD_RELOC_32
8213 || reloc_type == BFD_RELOC_X86_64_32S
8214 || reloc_type == BFD_RELOC_64)
8216 && GOT_symbol == i.op[n].imms->X_add_symbol
8217 && (i.op[n].imms->X_op == O_symbol
8218 || (i.op[n].imms->X_op == O_add
8219 && ((symbol_get_value_expression
8220 (i.op[n].imms->X_op_symbol)->X_op)
8225 if (insn_start_frag == frag_now)
8226 add = (p - frag_now->fr_literal) - insn_start_off;
8231 add = insn_start_frag->fr_fix - insn_start_off;
8232 for (fr = insn_start_frag->fr_next;
8233 fr && fr != frag_now; fr = fr->fr_next)
8235 add += p - frag_now->fr_literal;
8239 reloc_type = BFD_RELOC_386_GOTPC;
8241 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8243 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8244 i.op[n].imms->X_add_number += add;
8246 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8247 i.op[n].imms, 0, reloc_type);
8253 /* x86_cons_fix_new is called via the expression parsing code when a
8254 reloc is needed. We use this hook to get the correct .got reloc. */
8255 static int cons_sign = -1;
8258 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8259 expressionS *exp, bfd_reloc_code_real_type r)
8261 r = reloc (len, 0, cons_sign, r);
8264 if (exp->X_op == O_secrel)
8266 exp->X_op = O_symbol;
8267 r = BFD_RELOC_32_SECREL;
8271 fix_new_exp (frag, off, len, exp, 0, r);
8274 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8275 purpose of the `.dc.a' internal pseudo-op. */
8278 x86_address_bytes (void)
8280 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8282 return stdoutput->arch_info->bits_per_address / 8;
8285 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8287 # define lex_got(reloc, adjust, types) NULL
8289 /* Parse operands of the form
8290 <symbol>@GOTOFF+<nnn>
8291 and similar .plt or .got references.
8293 If we find one, set up the correct relocation in RELOC and copy the
8294 input string, minus the `@GOTOFF' into a malloc'd buffer for
8295 parsing by the calling routine. Return this buffer, and if ADJUST
8296 is non-null set it to the length of the string we removed from the
8297 input line. Otherwise return NULL. */
8299 lex_got (enum bfd_reloc_code_real *rel,
8301 i386_operand_type *types)
8303 /* Some of the relocations depend on the size of what field is to
8304 be relocated. But in our callers i386_immediate and i386_displacement
8305 we don't yet know the operand size (this will be set by insn
8306 matching). Hence we record the word32 relocation here,
8307 and adjust the reloc according to the real size in reloc(). */
8308 static const struct {
8311 const enum bfd_reloc_code_real rel[2];
8312 const i386_operand_type types64;
8314 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8315 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8317 OPERAND_TYPE_IMM32_64 },
8319 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8320 BFD_RELOC_X86_64_PLTOFF64 },
8321 OPERAND_TYPE_IMM64 },
8322 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8323 BFD_RELOC_X86_64_PLT32 },
8324 OPERAND_TYPE_IMM32_32S_DISP32 },
8325 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8326 BFD_RELOC_X86_64_GOTPLT64 },
8327 OPERAND_TYPE_IMM64_DISP64 },
8328 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8329 BFD_RELOC_X86_64_GOTOFF64 },
8330 OPERAND_TYPE_IMM64_DISP64 },
8331 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8332 BFD_RELOC_X86_64_GOTPCREL },
8333 OPERAND_TYPE_IMM32_32S_DISP32 },
8334 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8335 BFD_RELOC_X86_64_TLSGD },
8336 OPERAND_TYPE_IMM32_32S_DISP32 },
8337 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8338 _dummy_first_bfd_reloc_code_real },
8339 OPERAND_TYPE_NONE },
8340 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8341 BFD_RELOC_X86_64_TLSLD },
8342 OPERAND_TYPE_IMM32_32S_DISP32 },
8343 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8344 BFD_RELOC_X86_64_GOTTPOFF },
8345 OPERAND_TYPE_IMM32_32S_DISP32 },
8346 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8347 BFD_RELOC_X86_64_TPOFF32 },
8348 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8349 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8350 _dummy_first_bfd_reloc_code_real },
8351 OPERAND_TYPE_NONE },
8352 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8353 BFD_RELOC_X86_64_DTPOFF32 },
8354 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8355 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8356 _dummy_first_bfd_reloc_code_real },
8357 OPERAND_TYPE_NONE },
8358 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8359 _dummy_first_bfd_reloc_code_real },
8360 OPERAND_TYPE_NONE },
8361 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8362 BFD_RELOC_X86_64_GOT32 },
8363 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8364 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8365 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8366 OPERAND_TYPE_IMM32_32S_DISP32 },
8367 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8368 BFD_RELOC_X86_64_TLSDESC_CALL },
8369 OPERAND_TYPE_IMM32_32S_DISP32 },
8374 #if defined (OBJ_MAYBE_ELF)
8379 for (cp = input_line_pointer; *cp != '@'; cp++)
8380 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8383 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8385 int len = gotrel[j].len;
8386 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8388 if (gotrel[j].rel[object_64bit] != 0)
8391 char *tmpbuf, *past_reloc;
8393 *rel = gotrel[j].rel[object_64bit];
8397 if (flag_code != CODE_64BIT)
8399 types->bitfield.imm32 = 1;
8400 types->bitfield.disp32 = 1;
8403 *types = gotrel[j].types64;
8406 if (j != 0 && GOT_symbol == NULL)
8407 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8409 /* The length of the first part of our input line. */
8410 first = cp - input_line_pointer;
8412 /* The second part goes from after the reloc token until
8413 (and including) an end_of_line char or comma. */
8414 past_reloc = cp + 1 + len;
8416 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8418 second = cp + 1 - past_reloc;
8420 /* Allocate and copy string. The trailing NUL shouldn't
8421 be necessary, but be safe. */
8422 tmpbuf = XNEWVEC (char, first + second + 2);
8423 memcpy (tmpbuf, input_line_pointer, first);
8424 if (second != 0 && *past_reloc != ' ')
8425 /* Replace the relocation token with ' ', so that
8426 errors like foo@GOTOFF1 will be detected. */
8427 tmpbuf[first++] = ' ';
8429 /* Increment length by 1 if the relocation token is
8434 memcpy (tmpbuf + first, past_reloc, second);
8435 tmpbuf[first + second] = '\0';
8439 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8440 gotrel[j].str, 1 << (5 + object_64bit));
8445 /* Might be a symbol version string. Don't as_bad here. */
8454 /* Parse operands of the form
8455 <symbol>@SECREL32+<nnn>
8457 If we find one, set up the correct relocation in RELOC and copy the
8458 input string, minus the `@SECREL32' into a malloc'd buffer for
8459 parsing by the calling routine. Return this buffer, and if ADJUST
8460 is non-null set it to the length of the string we removed from the
8461 input line. Otherwise return NULL.
8463 This function is copied from the ELF version above adjusted for PE targets. */
8466 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8467 int *adjust ATTRIBUTE_UNUSED,
8468 i386_operand_type *types)
8474 const enum bfd_reloc_code_real rel[2];
8475 const i386_operand_type types64;
8479 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8480 BFD_RELOC_32_SECREL },
8481 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8487 for (cp = input_line_pointer; *cp != '@'; cp++)
8488 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8491 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8493 int len = gotrel[j].len;
8495 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8497 if (gotrel[j].rel[object_64bit] != 0)
8500 char *tmpbuf, *past_reloc;
8502 *rel = gotrel[j].rel[object_64bit];
8508 if (flag_code != CODE_64BIT)
8510 types->bitfield.imm32 = 1;
8511 types->bitfield.disp32 = 1;
8514 *types = gotrel[j].types64;
8517 /* The length of the first part of our input line. */
8518 first = cp - input_line_pointer;
8520 /* The second part goes from after the reloc token until
8521 (and including) an end_of_line char or comma. */
8522 past_reloc = cp + 1 + len;
8524 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8526 second = cp + 1 - past_reloc;
8528 /* Allocate and copy string. The trailing NUL shouldn't
8529 be necessary, but be safe. */
8530 tmpbuf = XNEWVEC (char, first + second + 2);
8531 memcpy (tmpbuf, input_line_pointer, first);
8532 if (second != 0 && *past_reloc != ' ')
8533 /* Replace the relocation token with ' ', so that
8534 errors like foo@SECLREL321 will be detected. */
8535 tmpbuf[first++] = ' ';
8536 memcpy (tmpbuf + first, past_reloc, second);
8537 tmpbuf[first + second] = '\0';
8541 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8542 gotrel[j].str, 1 << (5 + object_64bit));
8547 /* Might be a symbol version string. Don't as_bad here. */
8553 bfd_reloc_code_real_type
8554 x86_cons (expressionS *exp, int size)
8556 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8558 intel_syntax = -intel_syntax;
8561 if (size == 4 || (object_64bit && size == 8))
8563 /* Handle @GOTOFF and the like in an expression. */
8565 char *gotfree_input_line;
8568 save = input_line_pointer;
8569 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8570 if (gotfree_input_line)
8571 input_line_pointer = gotfree_input_line;
8575 if (gotfree_input_line)
8577 /* expression () has merrily parsed up to the end of line,
8578 or a comma - in the wrong buffer. Transfer how far
8579 input_line_pointer has moved to the right buffer. */
8580 input_line_pointer = (save
8581 + (input_line_pointer - gotfree_input_line)
8583 free (gotfree_input_line);
8584 if (exp->X_op == O_constant
8585 || exp->X_op == O_absent
8586 || exp->X_op == O_illegal
8587 || exp->X_op == O_register
8588 || exp->X_op == O_big)
8590 char c = *input_line_pointer;
8591 *input_line_pointer = 0;
8592 as_bad (_("missing or invalid expression `%s'"), save);
8593 *input_line_pointer = c;
8600 intel_syntax = -intel_syntax;
8603 i386_intel_simplify (exp);
8609 signed_cons (int size)
8611 if (flag_code == CODE_64BIT)
8619 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8626 if (exp.X_op == O_symbol)
8627 exp.X_op = O_secrel;
8629 emit_expr (&exp, 4);
8631 while (*input_line_pointer++ == ',');
8633 input_line_pointer--;
8634 demand_empty_rest_of_line ();
8638 /* Handle Vector operations. */
8641 check_VecOperations (char *op_string, char *op_end)
8643 const reg_entry *mask;
8648 && (op_end == NULL || op_string < op_end))
8651 if (*op_string == '{')
8655 /* Check broadcasts. */
8656 if (strncmp (op_string, "1to", 3) == 0)
8661 goto duplicated_vec_op;
8664 if (*op_string == '8')
8666 else if (*op_string == '4')
8668 else if (*op_string == '2')
8670 else if (*op_string == '1'
8671 && *(op_string+1) == '6')
8678 as_bad (_("Unsupported broadcast: `%s'"), saved);
8683 broadcast_op.type = bcst_type;
8684 broadcast_op.operand = this_operand;
8685 broadcast_op.bytes = 0;
8686 i.broadcast = &broadcast_op;
8688 /* Check masking operation. */
8689 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8691 /* k0 can't be used for write mask. */
8692 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8694 as_bad (_("`%s%s' can't be used for write mask"),
8695 register_prefix, mask->reg_name);
8701 mask_op.mask = mask;
8702 mask_op.zeroing = 0;
8703 mask_op.operand = this_operand;
8709 goto duplicated_vec_op;
8711 i.mask->mask = mask;
8713 /* Only "{z}" is allowed here. No need to check
8714 zeroing mask explicitly. */
8715 if (i.mask->operand != this_operand)
8717 as_bad (_("invalid write mask `%s'"), saved);
8724 /* Check zeroing-flag for masking operation. */
8725 else if (*op_string == 'z')
8729 mask_op.mask = NULL;
8730 mask_op.zeroing = 1;
8731 mask_op.operand = this_operand;
8736 if (i.mask->zeroing)
8739 as_bad (_("duplicated `%s'"), saved);
8743 i.mask->zeroing = 1;
8745 /* Only "{%k}" is allowed here. No need to check mask
8746 register explicitly. */
8747 if (i.mask->operand != this_operand)
8749 as_bad (_("invalid zeroing-masking `%s'"),
8758 goto unknown_vec_op;
8760 if (*op_string != '}')
8762 as_bad (_("missing `}' in `%s'"), saved);
8767 /* Strip whitespace since the addition of pseudo prefixes
8768 changed how the scrubber treats '{'. */
8769 if (is_space_char (*op_string))
8775 /* We don't know this one. */
8776 as_bad (_("unknown vector operation: `%s'"), saved);
8780 if (i.mask && i.mask->zeroing && !i.mask->mask)
8782 as_bad (_("zeroing-masking only allowed with write mask"));
8790 i386_immediate (char *imm_start)
8792 char *save_input_line_pointer;
8793 char *gotfree_input_line;
8796 i386_operand_type types;
8798 operand_type_set (&types, ~0);
8800 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8802 as_bad (_("at most %d immediate operands are allowed"),
8803 MAX_IMMEDIATE_OPERANDS);
8807 exp = &im_expressions[i.imm_operands++];
8808 i.op[this_operand].imms = exp;
8810 if (is_space_char (*imm_start))
8813 save_input_line_pointer = input_line_pointer;
8814 input_line_pointer = imm_start;
8816 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8817 if (gotfree_input_line)
8818 input_line_pointer = gotfree_input_line;
8820 exp_seg = expression (exp);
8824 /* Handle vector operations. */
8825 if (*input_line_pointer == '{')
8827 input_line_pointer = check_VecOperations (input_line_pointer,
8829 if (input_line_pointer == NULL)
8833 if (*input_line_pointer)
8834 as_bad (_("junk `%s' after expression"), input_line_pointer);
8836 input_line_pointer = save_input_line_pointer;
8837 if (gotfree_input_line)
8839 free (gotfree_input_line);
8841 if (exp->X_op == O_constant || exp->X_op == O_register)
8842 exp->X_op = O_illegal;
8845 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8849 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8850 i386_operand_type types, const char *imm_start)
8852 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8855 as_bad (_("missing or invalid immediate expression `%s'"),
8859 else if (exp->X_op == O_constant)
8861 /* Size it properly later. */
8862 i.types[this_operand].bitfield.imm64 = 1;
8863 /* If not 64bit, sign extend val. */
8864 if (flag_code != CODE_64BIT
8865 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8867 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8869 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8870 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8871 && exp_seg != absolute_section
8872 && exp_seg != text_section
8873 && exp_seg != data_section
8874 && exp_seg != bss_section
8875 && exp_seg != undefined_section
8876 && !bfd_is_com_section (exp_seg))
8878 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8882 else if (!intel_syntax && exp_seg == reg_section)
8885 as_bad (_("illegal immediate register operand %s"), imm_start);
8890 /* This is an address. The size of the address will be
8891 determined later, depending on destination register,
8892 suffix, or the default for the section. */
8893 i.types[this_operand].bitfield.imm8 = 1;
8894 i.types[this_operand].bitfield.imm16 = 1;
8895 i.types[this_operand].bitfield.imm32 = 1;
8896 i.types[this_operand].bitfield.imm32s = 1;
8897 i.types[this_operand].bitfield.imm64 = 1;
8898 i.types[this_operand] = operand_type_and (i.types[this_operand],
8906 i386_scale (char *scale)
8909 char *save = input_line_pointer;
8911 input_line_pointer = scale;
8912 val = get_absolute_expression ();
8917 i.log2_scale_factor = 0;
8920 i.log2_scale_factor = 1;
8923 i.log2_scale_factor = 2;
8926 i.log2_scale_factor = 3;
8930 char sep = *input_line_pointer;
8932 *input_line_pointer = '\0';
8933 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8935 *input_line_pointer = sep;
8936 input_line_pointer = save;
8940 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8942 as_warn (_("scale factor of %d without an index register"),
8943 1 << i.log2_scale_factor);
8944 i.log2_scale_factor = 0;
8946 scale = input_line_pointer;
8947 input_line_pointer = save;
8952 i386_displacement (char *disp_start, char *disp_end)
8956 char *save_input_line_pointer;
8957 char *gotfree_input_line;
8959 i386_operand_type bigdisp, types = anydisp;
8962 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8964 as_bad (_("at most %d displacement operands are allowed"),
8965 MAX_MEMORY_OPERANDS);
8969 operand_type_set (&bigdisp, 0);
8970 if ((i.types[this_operand].bitfield.jumpabsolute)
8971 || (!current_templates->start->opcode_modifier.jump
8972 && !current_templates->start->opcode_modifier.jumpdword))
8974 bigdisp.bitfield.disp32 = 1;
8975 override = (i.prefix[ADDR_PREFIX] != 0);
8976 if (flag_code == CODE_64BIT)
8980 bigdisp.bitfield.disp32s = 1;
8981 bigdisp.bitfield.disp64 = 1;
8984 else if ((flag_code == CODE_16BIT) ^ override)
8986 bigdisp.bitfield.disp32 = 0;
8987 bigdisp.bitfield.disp16 = 1;
8992 /* For PC-relative branches, the width of the displacement
8993 is dependent upon data size, not address size. */
8994 override = (i.prefix[DATA_PREFIX] != 0);
8995 if (flag_code == CODE_64BIT)
8997 if (override || i.suffix == WORD_MNEM_SUFFIX)
8998 bigdisp.bitfield.disp16 = 1;
9001 bigdisp.bitfield.disp32 = 1;
9002 bigdisp.bitfield.disp32s = 1;
9008 override = (i.suffix == (flag_code != CODE_16BIT
9010 : LONG_MNEM_SUFFIX));
9011 bigdisp.bitfield.disp32 = 1;
9012 if ((flag_code == CODE_16BIT) ^ override)
9014 bigdisp.bitfield.disp32 = 0;
9015 bigdisp.bitfield.disp16 = 1;
9019 i.types[this_operand] = operand_type_or (i.types[this_operand],
9022 exp = &disp_expressions[i.disp_operands];
9023 i.op[this_operand].disps = exp;
9025 save_input_line_pointer = input_line_pointer;
9026 input_line_pointer = disp_start;
9027 END_STRING_AND_SAVE (disp_end);
9029 #ifndef GCC_ASM_O_HACK
9030 #define GCC_ASM_O_HACK 0
9033 END_STRING_AND_SAVE (disp_end + 1);
9034 if (i.types[this_operand].bitfield.baseIndex
9035 && displacement_string_end[-1] == '+')
9037 /* This hack is to avoid a warning when using the "o"
9038 constraint within gcc asm statements.
9041 #define _set_tssldt_desc(n,addr,limit,type) \
9042 __asm__ __volatile__ ( \
9044 "movw %w1,2+%0\n\t" \
9046 "movb %b1,4+%0\n\t" \
9047 "movb %4,5+%0\n\t" \
9048 "movb $0,6+%0\n\t" \
9049 "movb %h1,7+%0\n\t" \
9051 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9053 This works great except that the output assembler ends
9054 up looking a bit weird if it turns out that there is
9055 no offset. You end up producing code that looks like:
9068 So here we provide the missing zero. */
9070 *displacement_string_end = '0';
9073 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9074 if (gotfree_input_line)
9075 input_line_pointer = gotfree_input_line;
9077 exp_seg = expression (exp);
9080 if (*input_line_pointer)
9081 as_bad (_("junk `%s' after expression"), input_line_pointer);
9083 RESTORE_END_STRING (disp_end + 1);
9085 input_line_pointer = save_input_line_pointer;
9086 if (gotfree_input_line)
9088 free (gotfree_input_line);
9090 if (exp->X_op == O_constant || exp->X_op == O_register)
9091 exp->X_op = O_illegal;
9094 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9096 RESTORE_END_STRING (disp_end);
9102 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9103 i386_operand_type types, const char *disp_start)
9105 i386_operand_type bigdisp;
9108 /* We do this to make sure that the section symbol is in
9109 the symbol table. We will ultimately change the relocation
9110 to be relative to the beginning of the section. */
9111 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9112 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9113 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9115 if (exp->X_op != O_symbol)
9118 if (S_IS_LOCAL (exp->X_add_symbol)
9119 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9120 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9121 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9122 exp->X_op = O_subtract;
9123 exp->X_op_symbol = GOT_symbol;
9124 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9125 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9126 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9127 i.reloc[this_operand] = BFD_RELOC_64;
9129 i.reloc[this_operand] = BFD_RELOC_32;
9132 else if (exp->X_op == O_absent
9133 || exp->X_op == O_illegal
9134 || exp->X_op == O_big)
9137 as_bad (_("missing or invalid displacement expression `%s'"),
9142 else if (flag_code == CODE_64BIT
9143 && !i.prefix[ADDR_PREFIX]
9144 && exp->X_op == O_constant)
9146 /* Since displacement is signed extended to 64bit, don't allow
9147 disp32 and turn off disp32s if they are out of range. */
9148 i.types[this_operand].bitfield.disp32 = 0;
9149 if (!fits_in_signed_long (exp->X_add_number))
9151 i.types[this_operand].bitfield.disp32s = 0;
9152 if (i.types[this_operand].bitfield.baseindex)
9154 as_bad (_("0x%lx out range of signed 32bit displacement"),
9155 (long) exp->X_add_number);
9161 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9162 else if (exp->X_op != O_constant
9163 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9164 && exp_seg != absolute_section
9165 && exp_seg != text_section
9166 && exp_seg != data_section
9167 && exp_seg != bss_section
9168 && exp_seg != undefined_section
9169 && !bfd_is_com_section (exp_seg))
9171 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9176 /* Check if this is a displacement only operand. */
9177 bigdisp = i.types[this_operand];
9178 bigdisp.bitfield.disp8 = 0;
9179 bigdisp.bitfield.disp16 = 0;
9180 bigdisp.bitfield.disp32 = 0;
9181 bigdisp.bitfield.disp32s = 0;
9182 bigdisp.bitfield.disp64 = 0;
9183 if (operand_type_all_zero (&bigdisp))
9184 i.types[this_operand] = operand_type_and (i.types[this_operand],
9190 /* Return the active addressing mode, taking address override and
9191 registers forming the address into consideration. Update the
9192 address override prefix if necessary. */
9194 static enum flag_code
9195 i386_addressing_mode (void)
9197 enum flag_code addr_mode;
9199 if (i.prefix[ADDR_PREFIX])
9200 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9203 addr_mode = flag_code;
9205 #if INFER_ADDR_PREFIX
9206 if (i.mem_operands == 0)
9208 /* Infer address prefix from the first memory operand. */
9209 const reg_entry *addr_reg = i.base_reg;
9211 if (addr_reg == NULL)
9212 addr_reg = i.index_reg;
9216 if (addr_reg->reg_num == RegEip
9217 || addr_reg->reg_num == RegEiz
9218 || addr_reg->reg_type.bitfield.dword)
9219 addr_mode = CODE_32BIT;
9220 else if (flag_code != CODE_64BIT
9221 && addr_reg->reg_type.bitfield.word)
9222 addr_mode = CODE_16BIT;
9224 if (addr_mode != flag_code)
9226 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9228 /* Change the size of any displacement too. At most one
9229 of Disp16 or Disp32 is set.
9230 FIXME. There doesn't seem to be any real need for
9231 separate Disp16 and Disp32 flags. The same goes for
9232 Imm16 and Imm32. Removing them would probably clean
9233 up the code quite a lot. */
9234 if (flag_code != CODE_64BIT
9235 && (i.types[this_operand].bitfield.disp16
9236 || i.types[this_operand].bitfield.disp32))
9237 i.types[this_operand]
9238 = operand_type_xor (i.types[this_operand], disp16_32);
9248 /* Make sure the memory operand we've been dealt is valid.
9249 Return 1 on success, 0 on a failure. */
9252 i386_index_check (const char *operand_string)
9254 const char *kind = "base/index";
9255 enum flag_code addr_mode = i386_addressing_mode ();
9257 if (current_templates->start->opcode_modifier.isstring
9258 && !current_templates->start->opcode_modifier.immext
9259 && (current_templates->end[-1].opcode_modifier.isstring
9262 /* Memory operands of string insns are special in that they only allow
9263 a single register (rDI, rSI, or rBX) as their memory address. */
9264 const reg_entry *expected_reg;
9265 static const char *di_si[][2] =
9271 static const char *bx[] = { "ebx", "bx", "rbx" };
9273 kind = "string address";
9275 if (current_templates->start->opcode_modifier.repprefixok)
9277 i386_operand_type type = current_templates->end[-1].operand_types[0];
9279 if (!type.bitfield.baseindex
9280 || ((!i.mem_operands != !intel_syntax)
9281 && current_templates->end[-1].operand_types[1]
9282 .bitfield.baseindex))
9283 type = current_templates->end[-1].operand_types[1];
9284 expected_reg = hash_find (reg_hash,
9285 di_si[addr_mode][type.bitfield.esseg]);
9289 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9291 if (i.base_reg != expected_reg
9293 || operand_type_check (i.types[this_operand], disp))
9295 /* The second memory operand must have the same size as
9299 && !((addr_mode == CODE_64BIT
9300 && i.base_reg->reg_type.bitfield.qword)
9301 || (addr_mode == CODE_32BIT
9302 ? i.base_reg->reg_type.bitfield.dword
9303 : i.base_reg->reg_type.bitfield.word)))
9306 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9308 intel_syntax ? '[' : '(',
9310 expected_reg->reg_name,
9311 intel_syntax ? ']' : ')');
9318 as_bad (_("`%s' is not a valid %s expression"),
9319 operand_string, kind);
9324 if (addr_mode != CODE_16BIT)
9326 /* 32-bit/64-bit checks. */
9328 && (addr_mode == CODE_64BIT
9329 ? !i.base_reg->reg_type.bitfield.qword
9330 : !i.base_reg->reg_type.bitfield.dword)
9332 || (i.base_reg->reg_num
9333 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9335 && !i.index_reg->reg_type.bitfield.xmmword
9336 && !i.index_reg->reg_type.bitfield.ymmword
9337 && !i.index_reg->reg_type.bitfield.zmmword
9338 && ((addr_mode == CODE_64BIT
9339 ? !(i.index_reg->reg_type.bitfield.qword
9340 || i.index_reg->reg_num == RegRiz)
9341 : !(i.index_reg->reg_type.bitfield.dword
9342 || i.index_reg->reg_num == RegEiz))
9343 || !i.index_reg->reg_type.bitfield.baseindex)))
9346 /* bndmk, bndldx, and bndstx have special restrictions. */
9347 if (current_templates->start->base_opcode == 0xf30f1b
9348 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9350 /* They cannot use RIP-relative addressing. */
9351 if (i.base_reg && i.base_reg->reg_num == RegRip)
9353 as_bad (_("`%s' cannot be used here"), operand_string);
9357 /* bndldx and bndstx ignore their scale factor. */
9358 if (current_templates->start->base_opcode != 0xf30f1b
9359 && i.log2_scale_factor)
9360 as_warn (_("register scaling is being ignored here"));
9365 /* 16-bit checks. */
9367 && (!i.base_reg->reg_type.bitfield.word
9368 || !i.base_reg->reg_type.bitfield.baseindex))
9370 && (!i.index_reg->reg_type.bitfield.word
9371 || !i.index_reg->reg_type.bitfield.baseindex
9373 && i.base_reg->reg_num < 6
9374 && i.index_reg->reg_num >= 6
9375 && i.log2_scale_factor == 0))))
9382 /* Handle vector immediates. */
9385 RC_SAE_immediate (const char *imm_start)
9387 unsigned int match_found, j;
9388 const char *pstr = imm_start;
9396 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9398 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9402 rc_op.type = RC_NamesTable[j].type;
9403 rc_op.operand = this_operand;
9404 i.rounding = &rc_op;
9408 as_bad (_("duplicated `%s'"), imm_start);
9411 pstr += RC_NamesTable[j].len;
9421 as_bad (_("Missing '}': '%s'"), imm_start);
9424 /* RC/SAE immediate string should contain nothing more. */;
9427 as_bad (_("Junk after '}': '%s'"), imm_start);
9431 exp = &im_expressions[i.imm_operands++];
9432 i.op[this_operand].imms = exp;
9434 exp->X_op = O_constant;
9435 exp->X_add_number = 0;
9436 exp->X_add_symbol = (symbolS *) 0;
9437 exp->X_op_symbol = (symbolS *) 0;
9439 i.types[this_operand].bitfield.imm8 = 1;
9443 /* Only string instructions can have a second memory operand, so
9444 reduce current_templates to just those if it contains any. */
9446 maybe_adjust_templates (void)
9448 const insn_template *t;
9450 gas_assert (i.mem_operands == 1);
9452 for (t = current_templates->start; t < current_templates->end; ++t)
9453 if (t->opcode_modifier.isstring)
9456 if (t < current_templates->end)
9458 static templates aux_templates;
9459 bfd_boolean recheck;
9461 aux_templates.start = t;
9462 for (; t < current_templates->end; ++t)
9463 if (!t->opcode_modifier.isstring)
9465 aux_templates.end = t;
9467 /* Determine whether to re-check the first memory operand. */
9468 recheck = (aux_templates.start != current_templates->start
9469 || t != current_templates->end);
9471 current_templates = &aux_templates;
9476 if (i.memop1_string != NULL
9477 && i386_index_check (i.memop1_string) == 0)
9486 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9490 i386_att_operand (char *operand_string)
9494 char *op_string = operand_string;
9496 if (is_space_char (*op_string))
9499 /* We check for an absolute prefix (differentiating,
9500 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9501 if (*op_string == ABSOLUTE_PREFIX)
9504 if (is_space_char (*op_string))
9506 i.types[this_operand].bitfield.jumpabsolute = 1;
9509 /* Check if operand is a register. */
9510 if ((r = parse_register (op_string, &end_op)) != NULL)
9512 i386_operand_type temp;
9514 /* Check for a segment override by searching for ':' after a
9515 segment register. */
9517 if (is_space_char (*op_string))
9519 if (*op_string == ':'
9520 && (r->reg_type.bitfield.sreg2
9521 || r->reg_type.bitfield.sreg3))
9526 i.seg[i.mem_operands] = &es;
9529 i.seg[i.mem_operands] = &cs;
9532 i.seg[i.mem_operands] = &ss;
9535 i.seg[i.mem_operands] = &ds;
9538 i.seg[i.mem_operands] = &fs;
9541 i.seg[i.mem_operands] = &gs;
9545 /* Skip the ':' and whitespace. */
9547 if (is_space_char (*op_string))
9550 if (!is_digit_char (*op_string)
9551 && !is_identifier_char (*op_string)
9552 && *op_string != '('
9553 && *op_string != ABSOLUTE_PREFIX)
9555 as_bad (_("bad memory operand `%s'"), op_string);
9558 /* Handle case of %es:*foo. */
9559 if (*op_string == ABSOLUTE_PREFIX)
9562 if (is_space_char (*op_string))
9564 i.types[this_operand].bitfield.jumpabsolute = 1;
9566 goto do_memory_reference;
9569 /* Handle vector operations. */
9570 if (*op_string == '{')
9572 op_string = check_VecOperations (op_string, NULL);
9573 if (op_string == NULL)
9579 as_bad (_("junk `%s' after register"), op_string);
9583 temp.bitfield.baseindex = 0;
9584 i.types[this_operand] = operand_type_or (i.types[this_operand],
9586 i.types[this_operand].bitfield.unspecified = 0;
9587 i.op[this_operand].regs = r;
9590 else if (*op_string == REGISTER_PREFIX)
9592 as_bad (_("bad register name `%s'"), op_string);
9595 else if (*op_string == IMMEDIATE_PREFIX)
9598 if (i.types[this_operand].bitfield.jumpabsolute)
9600 as_bad (_("immediate operand illegal with absolute jump"));
9603 if (!i386_immediate (op_string))
9606 else if (RC_SAE_immediate (operand_string))
9608 /* If it is a RC or SAE immediate, do nothing. */
9611 else if (is_digit_char (*op_string)
9612 || is_identifier_char (*op_string)
9613 || *op_string == '"'
9614 || *op_string == '(')
9616 /* This is a memory reference of some sort. */
9619 /* Start and end of displacement string expression (if found). */
9620 char *displacement_string_start;
9621 char *displacement_string_end;
9624 do_memory_reference:
9625 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9627 if ((i.mem_operands == 1
9628 && !current_templates->start->opcode_modifier.isstring)
9629 || i.mem_operands == 2)
9631 as_bad (_("too many memory references for `%s'"),
9632 current_templates->start->name);
9636 /* Check for base index form. We detect the base index form by
9637 looking for an ')' at the end of the operand, searching
9638 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9640 base_string = op_string + strlen (op_string);
9642 /* Handle vector operations. */
9643 vop_start = strchr (op_string, '{');
9644 if (vop_start && vop_start < base_string)
9646 if (check_VecOperations (vop_start, base_string) == NULL)
9648 base_string = vop_start;
9652 if (is_space_char (*base_string))
9655 /* If we only have a displacement, set-up for it to be parsed later. */
9656 displacement_string_start = op_string;
9657 displacement_string_end = base_string + 1;
9659 if (*base_string == ')')
9662 unsigned int parens_balanced = 1;
9663 /* We've already checked that the number of left & right ()'s are
9664 equal, so this loop will not be infinite. */
9668 if (*base_string == ')')
9670 if (*base_string == '(')
9673 while (parens_balanced);
9675 temp_string = base_string;
9677 /* Skip past '(' and whitespace. */
9679 if (is_space_char (*base_string))
9682 if (*base_string == ','
9683 || ((i.base_reg = parse_register (base_string, &end_op))
9686 displacement_string_end = temp_string;
9688 i.types[this_operand].bitfield.baseindex = 1;
9692 base_string = end_op;
9693 if (is_space_char (*base_string))
9697 /* There may be an index reg or scale factor here. */
9698 if (*base_string == ',')
9701 if (is_space_char (*base_string))
9704 if ((i.index_reg = parse_register (base_string, &end_op))
9707 base_string = end_op;
9708 if (is_space_char (*base_string))
9710 if (*base_string == ',')
9713 if (is_space_char (*base_string))
9716 else if (*base_string != ')')
9718 as_bad (_("expecting `,' or `)' "
9719 "after index register in `%s'"),
9724 else if (*base_string == REGISTER_PREFIX)
9726 end_op = strchr (base_string, ',');
9729 as_bad (_("bad register name `%s'"), base_string);
9733 /* Check for scale factor. */
9734 if (*base_string != ')')
9736 char *end_scale = i386_scale (base_string);
9741 base_string = end_scale;
9742 if (is_space_char (*base_string))
9744 if (*base_string != ')')
9746 as_bad (_("expecting `)' "
9747 "after scale factor in `%s'"),
9752 else if (!i.index_reg)
9754 as_bad (_("expecting index register or scale factor "
9755 "after `,'; got '%c'"),
9760 else if (*base_string != ')')
9762 as_bad (_("expecting `,' or `)' "
9763 "after base register in `%s'"),
9768 else if (*base_string == REGISTER_PREFIX)
9770 end_op = strchr (base_string, ',');
9773 as_bad (_("bad register name `%s'"), base_string);
9778 /* If there's an expression beginning the operand, parse it,
9779 assuming displacement_string_start and
9780 displacement_string_end are meaningful. */
9781 if (displacement_string_start != displacement_string_end)
9783 if (!i386_displacement (displacement_string_start,
9784 displacement_string_end))
9788 /* Special case for (%dx) while doing input/output op. */
9790 && i.base_reg->reg_type.bitfield.inoutportreg
9792 && i.log2_scale_factor == 0
9793 && i.seg[i.mem_operands] == 0
9794 && !operand_type_check (i.types[this_operand], disp))
9796 i.types[this_operand] = i.base_reg->reg_type;
9800 if (i386_index_check (operand_string) == 0)
9802 i.types[this_operand].bitfield.mem = 1;
9803 if (i.mem_operands == 0)
9804 i.memop1_string = xstrdup (operand_string);
9809 /* It's not a memory operand; argh! */
9810 as_bad (_("invalid char %s beginning operand %d `%s'"),
9811 output_invalid (*op_string),
9816 return 1; /* Normal return. */
9819 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9820 that an rs_machine_dependent frag may reach. */
9823 i386_frag_max_var (fragS *frag)
9825 /* The only relaxable frags are for jumps.
9826 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9827 gas_assert (frag->fr_type == rs_machine_dependent);
9828 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9831 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9833 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9835 /* STT_GNU_IFUNC symbol must go through PLT. */
9836 if ((symbol_get_bfdsym (fr_symbol)->flags
9837 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9840 if (!S_IS_EXTERNAL (fr_symbol))
9841 /* Symbol may be weak or local. */
9842 return !S_IS_WEAK (fr_symbol);
9844 /* Global symbols with non-default visibility can't be preempted. */
9845 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9848 if (fr_var != NO_RELOC)
9849 switch ((enum bfd_reloc_code_real) fr_var)
9851 case BFD_RELOC_386_PLT32:
9852 case BFD_RELOC_X86_64_PLT32:
9853 /* Symbol with PLT relocation may be preempted. */
9859 /* Global symbols with default visibility in a shared library may be
9860 preempted by another definition. */
9865 /* md_estimate_size_before_relax()
9867 Called just before relax() for rs_machine_dependent frags. The x86
9868 assembler uses these frags to handle variable size jump
9871 Any symbol that is now undefined will not become defined.
9872 Return the correct fr_subtype in the frag.
9873 Return the initial "guess for variable size of frag" to caller.
9874 The guess is actually the growth beyond the fixed part. Whatever
9875 we do to grow the fixed or variable part contributes to our
9879 md_estimate_size_before_relax (fragS *fragP, segT segment)
9881 /* We've already got fragP->fr_subtype right; all we have to do is
9882 check for un-relaxable symbols. On an ELF system, we can't relax
9883 an externally visible symbol, because it may be overridden by a
9885 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9886 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9888 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9891 #if defined (OBJ_COFF) && defined (TE_PE)
9892 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9893 && S_IS_WEAK (fragP->fr_symbol))
9897 /* Symbol is undefined in this segment, or we need to keep a
9898 reloc so that weak symbols can be overridden. */
9899 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9900 enum bfd_reloc_code_real reloc_type;
9901 unsigned char *opcode;
9904 if (fragP->fr_var != NO_RELOC)
9905 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9907 reloc_type = BFD_RELOC_16_PCREL;
9908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9909 else if (need_plt32_p (fragP->fr_symbol))
9910 reloc_type = BFD_RELOC_X86_64_PLT32;
9913 reloc_type = BFD_RELOC_32_PCREL;
9915 old_fr_fix = fragP->fr_fix;
9916 opcode = (unsigned char *) fragP->fr_opcode;
9918 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9921 /* Make jmp (0xeb) a (d)word displacement jump. */
9923 fragP->fr_fix += size;
9924 fix_new (fragP, old_fr_fix, size,
9926 fragP->fr_offset, 1,
9932 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9934 /* Negate the condition, and branch past an
9935 unconditional jump. */
9938 /* Insert an unconditional jump. */
9940 /* We added two extra opcode bytes, and have a two byte
9942 fragP->fr_fix += 2 + 2;
9943 fix_new (fragP, old_fr_fix + 2, 2,
9945 fragP->fr_offset, 1,
9952 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9957 fixP = fix_new (fragP, old_fr_fix, 1,
9959 fragP->fr_offset, 1,
9961 fixP->fx_signed = 1;
9965 /* This changes the byte-displacement jump 0x7N
9966 to the (d)word-displacement jump 0x0f,0x8N. */
9967 opcode[1] = opcode[0] + 0x10;
9968 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9969 /* We've added an opcode byte. */
9970 fragP->fr_fix += 1 + size;
9971 fix_new (fragP, old_fr_fix + 1, size,
9973 fragP->fr_offset, 1,
9978 BAD_CASE (fragP->fr_subtype);
9982 return fragP->fr_fix - old_fr_fix;
9985 /* Guess size depending on current relax state. Initially the relax
9986 state will correspond to a short jump and we return 1, because
9987 the variable part of the frag (the branch offset) is one byte
9988 long. However, we can relax a section more than once and in that
9989 case we must either set fr_subtype back to the unrelaxed state,
9990 or return the value for the appropriate branch. */
9991 return md_relax_table[fragP->fr_subtype].rlx_length;
9994 /* Called after relax() is finished.
9996 In: Address of frag.
9997 fr_type == rs_machine_dependent.
9998 fr_subtype is what the address relaxed to.
10000 Out: Any fixSs and constants are set up.
10001 Caller will turn frag into a ".space 0". */
10004 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10007 unsigned char *opcode;
10008 unsigned char *where_to_put_displacement = NULL;
10009 offsetT target_address;
10010 offsetT opcode_address;
10011 unsigned int extension = 0;
10012 offsetT displacement_from_opcode_start;
10014 opcode = (unsigned char *) fragP->fr_opcode;
10016 /* Address we want to reach in file space. */
10017 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10019 /* Address opcode resides at in file space. */
10020 opcode_address = fragP->fr_address + fragP->fr_fix;
10022 /* Displacement from opcode start to fill into instruction. */
10023 displacement_from_opcode_start = target_address - opcode_address;
10025 if ((fragP->fr_subtype & BIG) == 0)
10027 /* Don't have to change opcode. */
10028 extension = 1; /* 1 opcode + 1 displacement */
10029 where_to_put_displacement = &opcode[1];
10033 if (no_cond_jump_promotion
10034 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10035 as_warn_where (fragP->fr_file, fragP->fr_line,
10036 _("long jump required"));
10038 switch (fragP->fr_subtype)
10040 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10041 extension = 4; /* 1 opcode + 4 displacement */
10043 where_to_put_displacement = &opcode[1];
10046 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10047 extension = 2; /* 1 opcode + 2 displacement */
10049 where_to_put_displacement = &opcode[1];
10052 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10053 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10054 extension = 5; /* 2 opcode + 4 displacement */
10055 opcode[1] = opcode[0] + 0x10;
10056 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10057 where_to_put_displacement = &opcode[2];
10060 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10061 extension = 3; /* 2 opcode + 2 displacement */
10062 opcode[1] = opcode[0] + 0x10;
10063 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10064 where_to_put_displacement = &opcode[2];
10067 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10072 where_to_put_displacement = &opcode[3];
10076 BAD_CASE (fragP->fr_subtype);
10081 /* If size if less then four we are sure that the operand fits,
10082 but if it's 4, then it could be that the displacement is larger
10084 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10086 && ((addressT) (displacement_from_opcode_start - extension
10087 + ((addressT) 1 << 31))
10088 > (((addressT) 2 << 31) - 1)))
10090 as_bad_where (fragP->fr_file, fragP->fr_line,
10091 _("jump target out of range"));
10092 /* Make us emit 0. */
10093 displacement_from_opcode_start = extension;
10095 /* Now put displacement after opcode. */
10096 md_number_to_chars ((char *) where_to_put_displacement,
10097 (valueT) (displacement_from_opcode_start - extension),
10098 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10099 fragP->fr_fix += extension;
10102 /* Apply a fixup (fixP) to segment data, once it has been determined
10103 by our caller that we have all the info we need to fix it up.
10105 Parameter valP is the pointer to the value of the bits.
10107 On the 386, immediates, displacements, and data pointers are all in
10108 the same (little-endian) format, so we don't need to care about which
10109 we are handling. */
10112 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10114 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10115 valueT value = *valP;
10117 #if !defined (TE_Mach)
10118 if (fixP->fx_pcrel)
10120 switch (fixP->fx_r_type)
10126 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10129 case BFD_RELOC_X86_64_32S:
10130 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10133 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10136 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10141 if (fixP->fx_addsy != NULL
10142 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10143 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10144 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10145 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10146 && !use_rela_relocations)
10148 /* This is a hack. There should be a better way to handle this.
10149 This covers for the fact that bfd_install_relocation will
10150 subtract the current location (for partial_inplace, PC relative
10151 relocations); see more below. */
10155 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10158 value += fixP->fx_where + fixP->fx_frag->fr_address;
10160 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10163 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10165 if ((sym_seg == seg
10166 || (symbol_section_p (fixP->fx_addsy)
10167 && sym_seg != absolute_section))
10168 && !generic_force_reloc (fixP))
10170 /* Yes, we add the values in twice. This is because
10171 bfd_install_relocation subtracts them out again. I think
10172 bfd_install_relocation is broken, but I don't dare change
10174 value += fixP->fx_where + fixP->fx_frag->fr_address;
10178 #if defined (OBJ_COFF) && defined (TE_PE)
10179 /* For some reason, the PE format does not store a
10180 section address offset for a PC relative symbol. */
10181 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10182 || S_IS_WEAK (fixP->fx_addsy))
10183 value += md_pcrel_from (fixP);
10186 #if defined (OBJ_COFF) && defined (TE_PE)
10187 if (fixP->fx_addsy != NULL
10188 && S_IS_WEAK (fixP->fx_addsy)
10189 /* PR 16858: Do not modify weak function references. */
10190 && ! fixP->fx_pcrel)
10192 #if !defined (TE_PEP)
10193 /* For x86 PE weak function symbols are neither PC-relative
10194 nor do they set S_IS_FUNCTION. So the only reliable way
10195 to detect them is to check the flags of their containing
10197 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10198 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10202 value -= S_GET_VALUE (fixP->fx_addsy);
10206 /* Fix a few things - the dynamic linker expects certain values here,
10207 and we must not disappoint it. */
10208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10209 if (IS_ELF && fixP->fx_addsy)
10210 switch (fixP->fx_r_type)
10212 case BFD_RELOC_386_PLT32:
10213 case BFD_RELOC_X86_64_PLT32:
10214 /* Make the jump instruction point to the address of the operand. At
10215 runtime we merely add the offset to the actual PLT entry. */
10219 case BFD_RELOC_386_TLS_GD:
10220 case BFD_RELOC_386_TLS_LDM:
10221 case BFD_RELOC_386_TLS_IE_32:
10222 case BFD_RELOC_386_TLS_IE:
10223 case BFD_RELOC_386_TLS_GOTIE:
10224 case BFD_RELOC_386_TLS_GOTDESC:
10225 case BFD_RELOC_X86_64_TLSGD:
10226 case BFD_RELOC_X86_64_TLSLD:
10227 case BFD_RELOC_X86_64_GOTTPOFF:
10228 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10229 value = 0; /* Fully resolved at runtime. No addend. */
10231 case BFD_RELOC_386_TLS_LE:
10232 case BFD_RELOC_386_TLS_LDO_32:
10233 case BFD_RELOC_386_TLS_LE_32:
10234 case BFD_RELOC_X86_64_DTPOFF32:
10235 case BFD_RELOC_X86_64_DTPOFF64:
10236 case BFD_RELOC_X86_64_TPOFF32:
10237 case BFD_RELOC_X86_64_TPOFF64:
10238 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10241 case BFD_RELOC_386_TLS_DESC_CALL:
10242 case BFD_RELOC_X86_64_TLSDESC_CALL:
10243 value = 0; /* Fully resolved at runtime. No addend. */
10244 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10248 case BFD_RELOC_VTABLE_INHERIT:
10249 case BFD_RELOC_VTABLE_ENTRY:
10256 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10258 #endif /* !defined (TE_Mach) */
10260 /* Are we finished with this relocation now? */
10261 if (fixP->fx_addsy == NULL)
10263 #if defined (OBJ_COFF) && defined (TE_PE)
10264 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10267 /* Remember value for tc_gen_reloc. */
10268 fixP->fx_addnumber = value;
10269 /* Clear out the frag for now. */
10273 else if (use_rela_relocations)
10275 fixP->fx_no_overflow = 1;
10276 /* Remember value for tc_gen_reloc. */
10277 fixP->fx_addnumber = value;
10281 md_number_to_chars (p, value, fixP->fx_size);
10285 md_atof (int type, char *litP, int *sizeP)
10287 /* This outputs the LITTLENUMs in REVERSE order;
10288 in accord with the bigendian 386. */
10289 return ieee_md_atof (type, litP, sizeP, FALSE);
10292 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10295 output_invalid (int c)
10298 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10301 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10302 "(0x%x)", (unsigned char) c);
10303 return output_invalid_buf;
10306 /* REG_STRING starts *before* REGISTER_PREFIX. */
10308 static const reg_entry *
10309 parse_real_register (char *reg_string, char **end_op)
10311 char *s = reg_string;
10313 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10314 const reg_entry *r;
10316 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10317 if (*s == REGISTER_PREFIX)
10320 if (is_space_char (*s))
10323 p = reg_name_given;
10324 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10326 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10327 return (const reg_entry *) NULL;
10331 /* For naked regs, make sure that we are not dealing with an identifier.
10332 This prevents confusing an identifier like `eax_var' with register
10334 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10335 return (const reg_entry *) NULL;
10339 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10341 /* Handle floating point regs, allowing spaces in the (i) part. */
10342 if (r == i386_regtab /* %st is first entry of table */)
10344 if (!cpu_arch_flags.bitfield.cpu8087
10345 && !cpu_arch_flags.bitfield.cpu287
10346 && !cpu_arch_flags.bitfield.cpu387)
10347 return (const reg_entry *) NULL;
10349 if (is_space_char (*s))
10354 if (is_space_char (*s))
10356 if (*s >= '0' && *s <= '7')
10358 int fpr = *s - '0';
10360 if (is_space_char (*s))
10365 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10370 /* We have "%st(" then garbage. */
10371 return (const reg_entry *) NULL;
10375 if (r == NULL || allow_pseudo_reg)
10378 if (operand_type_all_zero (&r->reg_type))
10379 return (const reg_entry *) NULL;
10381 if ((r->reg_type.bitfield.dword
10382 || r->reg_type.bitfield.sreg3
10383 || r->reg_type.bitfield.control
10384 || r->reg_type.bitfield.debug
10385 || r->reg_type.bitfield.test)
10386 && !cpu_arch_flags.bitfield.cpui386)
10387 return (const reg_entry *) NULL;
10389 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10390 return (const reg_entry *) NULL;
10392 if (!cpu_arch_flags.bitfield.cpuavx512f)
10394 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10395 return (const reg_entry *) NULL;
10397 if (!cpu_arch_flags.bitfield.cpuavx)
10399 if (r->reg_type.bitfield.ymmword)
10400 return (const reg_entry *) NULL;
10402 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10403 return (const reg_entry *) NULL;
10407 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10408 return (const reg_entry *) NULL;
10410 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10411 if (!allow_index_reg
10412 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10413 return (const reg_entry *) NULL;
10415 /* Upper 16 vector registers are only available with VREX in 64bit
10416 mode, and require EVEX encoding. */
10417 if (r->reg_flags & RegVRex)
10419 if (!cpu_arch_flags.bitfield.cpuavx512f
10420 || flag_code != CODE_64BIT)
10421 return (const reg_entry *) NULL;
10423 i.vec_encoding = vex_encoding_evex;
10426 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10427 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10428 && flag_code != CODE_64BIT)
10429 return (const reg_entry *) NULL;
10431 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10432 return (const reg_entry *) NULL;
10437 /* REG_STRING starts *before* REGISTER_PREFIX. */
10439 static const reg_entry *
10440 parse_register (char *reg_string, char **end_op)
10442 const reg_entry *r;
10444 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10445 r = parse_real_register (reg_string, end_op);
10450 char *save = input_line_pointer;
10454 input_line_pointer = reg_string;
10455 c = get_symbol_name (®_string);
10456 symbolP = symbol_find (reg_string);
10457 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10459 const expressionS *e = symbol_get_value_expression (symbolP);
10461 know (e->X_op == O_register);
10462 know (e->X_add_number >= 0
10463 && (valueT) e->X_add_number < i386_regtab_size);
10464 r = i386_regtab + e->X_add_number;
10465 if ((r->reg_flags & RegVRex))
10466 i.vec_encoding = vex_encoding_evex;
10467 *end_op = input_line_pointer;
10469 *input_line_pointer = c;
10470 input_line_pointer = save;
10476 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10478 const reg_entry *r;
10479 char *end = input_line_pointer;
10482 r = parse_register (name, &input_line_pointer);
10483 if (r && end <= input_line_pointer)
10485 *nextcharP = *input_line_pointer;
10486 *input_line_pointer = 0;
10487 e->X_op = O_register;
10488 e->X_add_number = r - i386_regtab;
10491 input_line_pointer = end;
10493 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10497 md_operand (expressionS *e)
10500 const reg_entry *r;
10502 switch (*input_line_pointer)
10504 case REGISTER_PREFIX:
10505 r = parse_real_register (input_line_pointer, &end);
10508 e->X_op = O_register;
10509 e->X_add_number = r - i386_regtab;
10510 input_line_pointer = end;
10515 gas_assert (intel_syntax);
10516 end = input_line_pointer++;
10518 if (*input_line_pointer == ']')
10520 ++input_line_pointer;
10521 e->X_op_symbol = make_expr_symbol (e);
10522 e->X_add_symbol = NULL;
10523 e->X_add_number = 0;
10528 e->X_op = O_absent;
10529 input_line_pointer = end;
10536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10537 const char *md_shortopts = "kVQ:sqnO::";
10539 const char *md_shortopts = "qnO::";
10542 #define OPTION_32 (OPTION_MD_BASE + 0)
10543 #define OPTION_64 (OPTION_MD_BASE + 1)
10544 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10545 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10546 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10547 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10548 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10549 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10550 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10551 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10552 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10553 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10554 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10555 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10556 #define OPTION_X32 (OPTION_MD_BASE + 14)
10557 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10558 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10559 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10560 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10561 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10562 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10563 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10564 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10565 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10566 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10568 struct option md_longopts[] =
10570 {"32", no_argument, NULL, OPTION_32},
10571 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10572 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10573 {"64", no_argument, NULL, OPTION_64},
10575 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10576 {"x32", no_argument, NULL, OPTION_X32},
10577 {"mshared", no_argument, NULL, OPTION_MSHARED},
10579 {"divide", no_argument, NULL, OPTION_DIVIDE},
10580 {"march", required_argument, NULL, OPTION_MARCH},
10581 {"mtune", required_argument, NULL, OPTION_MTUNE},
10582 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10583 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10584 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10585 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10586 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10587 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10588 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10589 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10590 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10591 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10592 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10593 # if defined (TE_PE) || defined (TE_PEP)
10594 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10596 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10597 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10598 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10599 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10600 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10601 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10602 {NULL, no_argument, NULL, 0}
10604 size_t md_longopts_size = sizeof (md_longopts);
10607 md_parse_option (int c, const char *arg)
10610 char *arch, *next, *saved;
10615 optimize_align_code = 0;
10619 quiet_warnings = 1;
10622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10623 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10624 should be emitted or not. FIXME: Not implemented. */
10628 /* -V: SVR4 argument to print version ID. */
10630 print_version_id ();
10633 /* -k: Ignore for FreeBSD compatibility. */
10638 /* -s: On i386 Solaris, this tells the native assembler to use
10639 .stab instead of .stab.excl. We always use .stab anyhow. */
10642 case OPTION_MSHARED:
10646 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10647 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10650 const char **list, **l;
10652 list = bfd_target_list ();
10653 for (l = list; *l != NULL; l++)
10654 if (CONST_STRNEQ (*l, "elf64-x86-64")
10655 || strcmp (*l, "coff-x86-64") == 0
10656 || strcmp (*l, "pe-x86-64") == 0
10657 || strcmp (*l, "pei-x86-64") == 0
10658 || strcmp (*l, "mach-o-x86-64") == 0)
10660 default_arch = "x86_64";
10664 as_fatal (_("no compiled in support for x86_64"));
10670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10674 const char **list, **l;
10676 list = bfd_target_list ();
10677 for (l = list; *l != NULL; l++)
10678 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10680 default_arch = "x86_64:32";
10684 as_fatal (_("no compiled in support for 32bit x86_64"));
10688 as_fatal (_("32bit x86_64 is only supported for ELF"));
10693 default_arch = "i386";
10696 case OPTION_DIVIDE:
10697 #ifdef SVR4_COMMENT_CHARS
10702 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10704 for (s = i386_comment_chars; *s != '\0'; s++)
10708 i386_comment_chars = n;
10714 saved = xstrdup (arg);
10716 /* Allow -march=+nosse. */
10722 as_fatal (_("invalid -march= option: `%s'"), arg);
10723 next = strchr (arch, '+');
10726 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10728 if (strcmp (arch, cpu_arch [j].name) == 0)
10731 if (! cpu_arch[j].flags.bitfield.cpui386)
10734 cpu_arch_name = cpu_arch[j].name;
10735 cpu_sub_arch_name = NULL;
10736 cpu_arch_flags = cpu_arch[j].flags;
10737 cpu_arch_isa = cpu_arch[j].type;
10738 cpu_arch_isa_flags = cpu_arch[j].flags;
10739 if (!cpu_arch_tune_set)
10741 cpu_arch_tune = cpu_arch_isa;
10742 cpu_arch_tune_flags = cpu_arch_isa_flags;
10746 else if (*cpu_arch [j].name == '.'
10747 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10749 /* ISA extension. */
10750 i386_cpu_flags flags;
10752 flags = cpu_flags_or (cpu_arch_flags,
10753 cpu_arch[j].flags);
10755 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10757 if (cpu_sub_arch_name)
10759 char *name = cpu_sub_arch_name;
10760 cpu_sub_arch_name = concat (name,
10762 (const char *) NULL);
10766 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10767 cpu_arch_flags = flags;
10768 cpu_arch_isa_flags = flags;
10772 = cpu_flags_or (cpu_arch_isa_flags,
10773 cpu_arch[j].flags);
10778 if (j >= ARRAY_SIZE (cpu_arch))
10780 /* Disable an ISA extension. */
10781 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10782 if (strcmp (arch, cpu_noarch [j].name) == 0)
10784 i386_cpu_flags flags;
10786 flags = cpu_flags_and_not (cpu_arch_flags,
10787 cpu_noarch[j].flags);
10788 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10790 if (cpu_sub_arch_name)
10792 char *name = cpu_sub_arch_name;
10793 cpu_sub_arch_name = concat (arch,
10794 (const char *) NULL);
10798 cpu_sub_arch_name = xstrdup (arch);
10799 cpu_arch_flags = flags;
10800 cpu_arch_isa_flags = flags;
10805 if (j >= ARRAY_SIZE (cpu_noarch))
10806 j = ARRAY_SIZE (cpu_arch);
10809 if (j >= ARRAY_SIZE (cpu_arch))
10810 as_fatal (_("invalid -march= option: `%s'"), arg);
10814 while (next != NULL);
10820 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10821 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10823 if (strcmp (arg, cpu_arch [j].name) == 0)
10825 cpu_arch_tune_set = 1;
10826 cpu_arch_tune = cpu_arch [j].type;
10827 cpu_arch_tune_flags = cpu_arch[j].flags;
10831 if (j >= ARRAY_SIZE (cpu_arch))
10832 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10835 case OPTION_MMNEMONIC:
10836 if (strcasecmp (arg, "att") == 0)
10837 intel_mnemonic = 0;
10838 else if (strcasecmp (arg, "intel") == 0)
10839 intel_mnemonic = 1;
10841 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10844 case OPTION_MSYNTAX:
10845 if (strcasecmp (arg, "att") == 0)
10847 else if (strcasecmp (arg, "intel") == 0)
10850 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10853 case OPTION_MINDEX_REG:
10854 allow_index_reg = 1;
10857 case OPTION_MNAKED_REG:
10858 allow_naked_reg = 1;
10861 case OPTION_MSSE2AVX:
10865 case OPTION_MSSE_CHECK:
10866 if (strcasecmp (arg, "error") == 0)
10867 sse_check = check_error;
10868 else if (strcasecmp (arg, "warning") == 0)
10869 sse_check = check_warning;
10870 else if (strcasecmp (arg, "none") == 0)
10871 sse_check = check_none;
10873 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10876 case OPTION_MOPERAND_CHECK:
10877 if (strcasecmp (arg, "error") == 0)
10878 operand_check = check_error;
10879 else if (strcasecmp (arg, "warning") == 0)
10880 operand_check = check_warning;
10881 else if (strcasecmp (arg, "none") == 0)
10882 operand_check = check_none;
10884 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10887 case OPTION_MAVXSCALAR:
10888 if (strcasecmp (arg, "128") == 0)
10889 avxscalar = vex128;
10890 else if (strcasecmp (arg, "256") == 0)
10891 avxscalar = vex256;
10893 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10896 case OPTION_MADD_BND_PREFIX:
10897 add_bnd_prefix = 1;
10900 case OPTION_MEVEXLIG:
10901 if (strcmp (arg, "128") == 0)
10902 evexlig = evexl128;
10903 else if (strcmp (arg, "256") == 0)
10904 evexlig = evexl256;
10905 else if (strcmp (arg, "512") == 0)
10906 evexlig = evexl512;
10908 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10911 case OPTION_MEVEXRCIG:
10912 if (strcmp (arg, "rne") == 0)
10914 else if (strcmp (arg, "rd") == 0)
10916 else if (strcmp (arg, "ru") == 0)
10918 else if (strcmp (arg, "rz") == 0)
10921 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10924 case OPTION_MEVEXWIG:
10925 if (strcmp (arg, "0") == 0)
10927 else if (strcmp (arg, "1") == 0)
10930 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10933 # if defined (TE_PE) || defined (TE_PEP)
10934 case OPTION_MBIG_OBJ:
10939 case OPTION_MOMIT_LOCK_PREFIX:
10940 if (strcasecmp (arg, "yes") == 0)
10941 omit_lock_prefix = 1;
10942 else if (strcasecmp (arg, "no") == 0)
10943 omit_lock_prefix = 0;
10945 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10948 case OPTION_MFENCE_AS_LOCK_ADD:
10949 if (strcasecmp (arg, "yes") == 0)
10951 else if (strcasecmp (arg, "no") == 0)
10954 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10957 case OPTION_MRELAX_RELOCATIONS:
10958 if (strcasecmp (arg, "yes") == 0)
10959 generate_relax_relocations = 1;
10960 else if (strcasecmp (arg, "no") == 0)
10961 generate_relax_relocations = 0;
10963 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10966 case OPTION_MAMD64:
10970 case OPTION_MINTEL64:
10978 /* Turn off -Os. */
10979 optimize_for_space = 0;
10981 else if (*arg == 's')
10983 optimize_for_space = 1;
10984 /* Turn on all encoding optimizations. */
10989 optimize = atoi (arg);
10990 /* Turn off -Os. */
10991 optimize_for_space = 0;
11001 #define MESSAGE_TEMPLATE \
11005 output_message (FILE *stream, char *p, char *message, char *start,
11006 int *left_p, const char *name, int len)
11008 int size = sizeof (MESSAGE_TEMPLATE);
11009 int left = *left_p;
11011 /* Reserve 2 spaces for ", " or ",\0" */
11014 /* Check if there is any room. */
11022 p = mempcpy (p, name, len);
11026 /* Output the current message now and start a new one. */
11029 fprintf (stream, "%s\n", message);
11031 left = size - (start - message) - len - 2;
11033 gas_assert (left >= 0);
11035 p = mempcpy (p, name, len);
11043 show_arch (FILE *stream, int ext, int check)
11045 static char message[] = MESSAGE_TEMPLATE;
11046 char *start = message + 27;
11048 int size = sizeof (MESSAGE_TEMPLATE);
11055 left = size - (start - message);
11056 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11058 /* Should it be skipped? */
11059 if (cpu_arch [j].skip)
11062 name = cpu_arch [j].name;
11063 len = cpu_arch [j].len;
11066 /* It is an extension. Skip if we aren't asked to show it. */
11077 /* It is an processor. Skip if we show only extension. */
11080 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11082 /* It is an impossible processor - skip. */
11086 p = output_message (stream, p, message, start, &left, name, len);
11089 /* Display disabled extensions. */
11091 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11093 name = cpu_noarch [j].name;
11094 len = cpu_noarch [j].len;
11095 p = output_message (stream, p, message, start, &left, name,
11100 fprintf (stream, "%s\n", message);
11104 md_show_usage (FILE *stream)
11106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11107 fprintf (stream, _("\
11109 -V print assembler version number\n\
11112 fprintf (stream, _("\
11113 -n Do not optimize code alignment\n\
11114 -q quieten some warnings\n"));
11115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11116 fprintf (stream, _("\
11119 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11120 || defined (TE_PE) || defined (TE_PEP))
11121 fprintf (stream, _("\
11122 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11124 #ifdef SVR4_COMMENT_CHARS
11125 fprintf (stream, _("\
11126 --divide do not treat `/' as a comment character\n"));
11128 fprintf (stream, _("\
11129 --divide ignored\n"));
11131 fprintf (stream, _("\
11132 -march=CPU[,+EXTENSION...]\n\
11133 generate code for CPU and EXTENSION, CPU is one of:\n"));
11134 show_arch (stream, 0, 1);
11135 fprintf (stream, _("\
11136 EXTENSION is combination of:\n"));
11137 show_arch (stream, 1, 0);
11138 fprintf (stream, _("\
11139 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11140 show_arch (stream, 0, 0);
11141 fprintf (stream, _("\
11142 -msse2avx encode SSE instructions with VEX prefix\n"));
11143 fprintf (stream, _("\
11144 -msse-check=[none|error|warning]\n\
11145 check SSE instructions\n"));
11146 fprintf (stream, _("\
11147 -moperand-check=[none|error|warning]\n\
11148 check operand combinations for validity\n"));
11149 fprintf (stream, _("\
11150 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11152 fprintf (stream, _("\
11153 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11155 fprintf (stream, _("\
11156 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11157 for EVEX.W bit ignored instructions\n"));
11158 fprintf (stream, _("\
11159 -mevexrcig=[rne|rd|ru|rz]\n\
11160 encode EVEX instructions with specific EVEX.RC value\n\
11161 for SAE-only ignored instructions\n"));
11162 fprintf (stream, _("\
11163 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11164 fprintf (stream, _("\
11165 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11166 fprintf (stream, _("\
11167 -mindex-reg support pseudo index registers\n"));
11168 fprintf (stream, _("\
11169 -mnaked-reg don't require `%%' prefix for registers\n"));
11170 fprintf (stream, _("\
11171 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11172 fprintf (stream, _("\
11173 -mshared disable branch optimization for shared code\n"));
11174 # if defined (TE_PE) || defined (TE_PEP)
11175 fprintf (stream, _("\
11176 -mbig-obj generate big object files\n"));
11178 fprintf (stream, _("\
11179 -momit-lock-prefix=[no|yes]\n\
11180 strip all lock prefixes\n"));
11181 fprintf (stream, _("\
11182 -mfence-as-lock-add=[no|yes]\n\
11183 encode lfence, mfence and sfence as\n\
11184 lock addl $0x0, (%%{re}sp)\n"));
11185 fprintf (stream, _("\
11186 -mrelax-relocations=[no|yes]\n\
11187 generate relax relocations\n"));
11188 fprintf (stream, _("\
11189 -mamd64 accept only AMD64 ISA\n"));
11190 fprintf (stream, _("\
11191 -mintel64 accept only Intel64 ISA\n"));
11194 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11195 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11196 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11198 /* Pick the target format to use. */
11201 i386_target_format (void)
11203 if (!strncmp (default_arch, "x86_64", 6))
11205 update_code_flag (CODE_64BIT, 1);
11206 if (default_arch[6] == '\0')
11207 x86_elf_abi = X86_64_ABI;
11209 x86_elf_abi = X86_64_X32_ABI;
11211 else if (!strcmp (default_arch, "i386"))
11212 update_code_flag (CODE_32BIT, 1);
11213 else if (!strcmp (default_arch, "iamcu"))
11215 update_code_flag (CODE_32BIT, 1);
11216 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11218 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11219 cpu_arch_name = "iamcu";
11220 cpu_sub_arch_name = NULL;
11221 cpu_arch_flags = iamcu_flags;
11222 cpu_arch_isa = PROCESSOR_IAMCU;
11223 cpu_arch_isa_flags = iamcu_flags;
11224 if (!cpu_arch_tune_set)
11226 cpu_arch_tune = cpu_arch_isa;
11227 cpu_arch_tune_flags = cpu_arch_isa_flags;
11230 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11231 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11235 as_fatal (_("unknown architecture"));
11237 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11238 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11239 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11240 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11242 switch (OUTPUT_FLAVOR)
11244 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11245 case bfd_target_aout_flavour:
11246 return AOUT_TARGET_FORMAT;
11248 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11249 # if defined (TE_PE) || defined (TE_PEP)
11250 case bfd_target_coff_flavour:
11251 if (flag_code == CODE_64BIT)
11252 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11255 # elif defined (TE_GO32)
11256 case bfd_target_coff_flavour:
11257 return "coff-go32";
11259 case bfd_target_coff_flavour:
11260 return "coff-i386";
11263 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11264 case bfd_target_elf_flavour:
11266 const char *format;
11268 switch (x86_elf_abi)
11271 format = ELF_TARGET_FORMAT;
11274 use_rela_relocations = 1;
11276 format = ELF_TARGET_FORMAT64;
11278 case X86_64_X32_ABI:
11279 use_rela_relocations = 1;
11281 disallow_64bit_reloc = 1;
11282 format = ELF_TARGET_FORMAT32;
11285 if (cpu_arch_isa == PROCESSOR_L1OM)
11287 if (x86_elf_abi != X86_64_ABI)
11288 as_fatal (_("Intel L1OM is 64bit only"));
11289 return ELF_TARGET_L1OM_FORMAT;
11291 else if (cpu_arch_isa == PROCESSOR_K1OM)
11293 if (x86_elf_abi != X86_64_ABI)
11294 as_fatal (_("Intel K1OM is 64bit only"));
11295 return ELF_TARGET_K1OM_FORMAT;
11297 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11299 if (x86_elf_abi != I386_ABI)
11300 as_fatal (_("Intel MCU is 32bit only"));
11301 return ELF_TARGET_IAMCU_FORMAT;
11307 #if defined (OBJ_MACH_O)
11308 case bfd_target_mach_o_flavour:
11309 if (flag_code == CODE_64BIT)
11311 use_rela_relocations = 1;
11313 return "mach-o-x86-64";
11316 return "mach-o-i386";
11324 #endif /* OBJ_MAYBE_ more than one */
11327 md_undefined_symbol (char *name)
11329 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11330 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11331 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11332 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11336 if (symbol_find (name))
11337 as_bad (_("GOT already in symbol table"));
11338 GOT_symbol = symbol_new (name, undefined_section,
11339 (valueT) 0, &zero_address_frag);
11346 /* Round up a section size to the appropriate boundary. */
11349 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11351 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11352 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11354 /* For a.out, force the section size to be aligned. If we don't do
11355 this, BFD will align it for us, but it will not write out the
11356 final bytes of the section. This may be a bug in BFD, but it is
11357 easier to fix it here since that is how the other a.out targets
11361 align = bfd_get_section_alignment (stdoutput, segment);
11362 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11369 /* On the i386, PC-relative offsets are relative to the start of the
11370 next instruction. That is, the address of the offset, plus its
11371 size, since the offset is always the last part of the insn. */
11374 md_pcrel_from (fixS *fixP)
11376 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11382 s_bss (int ignore ATTRIBUTE_UNUSED)
11386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11388 obj_elf_section_change_hook ();
11390 temp = get_absolute_expression ();
11391 subseg_set (bss_section, (subsegT) temp);
11392 demand_empty_rest_of_line ();
11398 i386_validate_fix (fixS *fixp)
11400 if (fixp->fx_subsy)
11402 if (fixp->fx_subsy == GOT_symbol)
11404 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11409 if (fixp->fx_tcbit2)
11410 fixp->fx_r_type = (fixp->fx_tcbit
11411 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11412 : BFD_RELOC_X86_64_GOTPCRELX);
11415 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11420 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11422 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11424 fixp->fx_subsy = 0;
11427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11428 else if (!object_64bit)
11430 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11431 && fixp->fx_tcbit2)
11432 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11438 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11441 bfd_reloc_code_real_type code;
11443 switch (fixp->fx_r_type)
11445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11446 case BFD_RELOC_SIZE32:
11447 case BFD_RELOC_SIZE64:
11448 if (S_IS_DEFINED (fixp->fx_addsy)
11449 && !S_IS_EXTERNAL (fixp->fx_addsy))
11451 /* Resolve size relocation against local symbol to size of
11452 the symbol plus addend. */
11453 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11454 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11455 && !fits_in_unsigned_long (value))
11456 as_bad_where (fixp->fx_file, fixp->fx_line,
11457 _("symbol size computation overflow"));
11458 fixp->fx_addsy = NULL;
11459 fixp->fx_subsy = NULL;
11460 md_apply_fix (fixp, (valueT *) &value, NULL);
11464 /* Fall through. */
11466 case BFD_RELOC_X86_64_PLT32:
11467 case BFD_RELOC_X86_64_GOT32:
11468 case BFD_RELOC_X86_64_GOTPCREL:
11469 case BFD_RELOC_X86_64_GOTPCRELX:
11470 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11471 case BFD_RELOC_386_PLT32:
11472 case BFD_RELOC_386_GOT32:
11473 case BFD_RELOC_386_GOT32X:
11474 case BFD_RELOC_386_GOTOFF:
11475 case BFD_RELOC_386_GOTPC:
11476 case BFD_RELOC_386_TLS_GD:
11477 case BFD_RELOC_386_TLS_LDM:
11478 case BFD_RELOC_386_TLS_LDO_32:
11479 case BFD_RELOC_386_TLS_IE_32:
11480 case BFD_RELOC_386_TLS_IE:
11481 case BFD_RELOC_386_TLS_GOTIE:
11482 case BFD_RELOC_386_TLS_LE_32:
11483 case BFD_RELOC_386_TLS_LE:
11484 case BFD_RELOC_386_TLS_GOTDESC:
11485 case BFD_RELOC_386_TLS_DESC_CALL:
11486 case BFD_RELOC_X86_64_TLSGD:
11487 case BFD_RELOC_X86_64_TLSLD:
11488 case BFD_RELOC_X86_64_DTPOFF32:
11489 case BFD_RELOC_X86_64_DTPOFF64:
11490 case BFD_RELOC_X86_64_GOTTPOFF:
11491 case BFD_RELOC_X86_64_TPOFF32:
11492 case BFD_RELOC_X86_64_TPOFF64:
11493 case BFD_RELOC_X86_64_GOTOFF64:
11494 case BFD_RELOC_X86_64_GOTPC32:
11495 case BFD_RELOC_X86_64_GOT64:
11496 case BFD_RELOC_X86_64_GOTPCREL64:
11497 case BFD_RELOC_X86_64_GOTPC64:
11498 case BFD_RELOC_X86_64_GOTPLT64:
11499 case BFD_RELOC_X86_64_PLTOFF64:
11500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11501 case BFD_RELOC_X86_64_TLSDESC_CALL:
11502 case BFD_RELOC_RVA:
11503 case BFD_RELOC_VTABLE_ENTRY:
11504 case BFD_RELOC_VTABLE_INHERIT:
11506 case BFD_RELOC_32_SECREL:
11508 code = fixp->fx_r_type;
11510 case BFD_RELOC_X86_64_32S:
11511 if (!fixp->fx_pcrel)
11513 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11514 code = fixp->fx_r_type;
11517 /* Fall through. */
11519 if (fixp->fx_pcrel)
11521 switch (fixp->fx_size)
11524 as_bad_where (fixp->fx_file, fixp->fx_line,
11525 _("can not do %d byte pc-relative relocation"),
11527 code = BFD_RELOC_32_PCREL;
11529 case 1: code = BFD_RELOC_8_PCREL; break;
11530 case 2: code = BFD_RELOC_16_PCREL; break;
11531 case 4: code = BFD_RELOC_32_PCREL; break;
11533 case 8: code = BFD_RELOC_64_PCREL; break;
11539 switch (fixp->fx_size)
11542 as_bad_where (fixp->fx_file, fixp->fx_line,
11543 _("can not do %d byte relocation"),
11545 code = BFD_RELOC_32;
11547 case 1: code = BFD_RELOC_8; break;
11548 case 2: code = BFD_RELOC_16; break;
11549 case 4: code = BFD_RELOC_32; break;
11551 case 8: code = BFD_RELOC_64; break;
11558 if ((code == BFD_RELOC_32
11559 || code == BFD_RELOC_32_PCREL
11560 || code == BFD_RELOC_X86_64_32S)
11562 && fixp->fx_addsy == GOT_symbol)
11565 code = BFD_RELOC_386_GOTPC;
11567 code = BFD_RELOC_X86_64_GOTPC32;
11569 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11571 && fixp->fx_addsy == GOT_symbol)
11573 code = BFD_RELOC_X86_64_GOTPC64;
11576 rel = XNEW (arelent);
11577 rel->sym_ptr_ptr = XNEW (asymbol *);
11578 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11580 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11582 if (!use_rela_relocations)
11584 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11585 vtable entry to be used in the relocation's section offset. */
11586 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11587 rel->address = fixp->fx_offset;
11588 #if defined (OBJ_COFF) && defined (TE_PE)
11589 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11590 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11595 /* Use the rela in 64bit mode. */
11598 if (disallow_64bit_reloc)
11601 case BFD_RELOC_X86_64_DTPOFF64:
11602 case BFD_RELOC_X86_64_TPOFF64:
11603 case BFD_RELOC_64_PCREL:
11604 case BFD_RELOC_X86_64_GOTOFF64:
11605 case BFD_RELOC_X86_64_GOT64:
11606 case BFD_RELOC_X86_64_GOTPCREL64:
11607 case BFD_RELOC_X86_64_GOTPC64:
11608 case BFD_RELOC_X86_64_GOTPLT64:
11609 case BFD_RELOC_X86_64_PLTOFF64:
11610 as_bad_where (fixp->fx_file, fixp->fx_line,
11611 _("cannot represent relocation type %s in x32 mode"),
11612 bfd_get_reloc_code_name (code));
11618 if (!fixp->fx_pcrel)
11619 rel->addend = fixp->fx_offset;
11623 case BFD_RELOC_X86_64_PLT32:
11624 case BFD_RELOC_X86_64_GOT32:
11625 case BFD_RELOC_X86_64_GOTPCREL:
11626 case BFD_RELOC_X86_64_GOTPCRELX:
11627 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11628 case BFD_RELOC_X86_64_TLSGD:
11629 case BFD_RELOC_X86_64_TLSLD:
11630 case BFD_RELOC_X86_64_GOTTPOFF:
11631 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11632 case BFD_RELOC_X86_64_TLSDESC_CALL:
11633 rel->addend = fixp->fx_offset - fixp->fx_size;
11636 rel->addend = (section->vma
11638 + fixp->fx_addnumber
11639 + md_pcrel_from (fixp));
11644 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11645 if (rel->howto == NULL)
11647 as_bad_where (fixp->fx_file, fixp->fx_line,
11648 _("cannot represent relocation type %s"),
11649 bfd_get_reloc_code_name (code));
11650 /* Set howto to a garbage value so that we can keep going. */
11651 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11652 gas_assert (rel->howto != NULL);
11658 #include "tc-i386-intel.c"
11661 tc_x86_parse_to_dw2regnum (expressionS *exp)
11663 int saved_naked_reg;
11664 char saved_register_dot;
11666 saved_naked_reg = allow_naked_reg;
11667 allow_naked_reg = 1;
11668 saved_register_dot = register_chars['.'];
11669 register_chars['.'] = '.';
11670 allow_pseudo_reg = 1;
11671 expression_and_evaluate (exp);
11672 allow_pseudo_reg = 0;
11673 register_chars['.'] = saved_register_dot;
11674 allow_naked_reg = saved_naked_reg;
11676 if (exp->X_op == O_register && exp->X_add_number >= 0)
11678 if ((addressT) exp->X_add_number < i386_regtab_size)
11680 exp->X_op = O_constant;
11681 exp->X_add_number = i386_regtab[exp->X_add_number]
11682 .dw2_regnum[flag_code >> 1];
11685 exp->X_op = O_illegal;
11690 tc_x86_frame_initial_instructions (void)
11692 static unsigned int sp_regno[2];
11694 if (!sp_regno[flag_code >> 1])
11696 char *saved_input = input_line_pointer;
11697 char sp[][4] = {"esp", "rsp"};
11700 input_line_pointer = sp[flag_code >> 1];
11701 tc_x86_parse_to_dw2regnum (&exp);
11702 gas_assert (exp.X_op == O_constant);
11703 sp_regno[flag_code >> 1] = exp.X_add_number;
11704 input_line_pointer = saved_input;
11707 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11708 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11712 x86_dwarf2_addr_size (void)
11714 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11715 if (x86_elf_abi == X86_64_X32_ABI)
11718 return bfd_arch_bits_per_address (stdoutput) / 8;
11722 i386_elf_section_type (const char *str, size_t len)
11724 if (flag_code == CODE_64BIT
11725 && len == sizeof ("unwind") - 1
11726 && strncmp (str, "unwind", 6) == 0)
11727 return SHT_X86_64_UNWIND;
11734 i386_solaris_fix_up_eh_frame (segT sec)
11736 if (flag_code == CODE_64BIT)
11737 elf_section_type (sec) = SHT_X86_64_UNWIND;
11743 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11747 exp.X_op = O_secrel;
11748 exp.X_add_symbol = symbol;
11749 exp.X_add_number = 0;
11750 emit_expr (&exp, size);
11754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11755 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11758 x86_64_section_letter (int letter, const char **ptr_msg)
11760 if (flag_code == CODE_64BIT)
11763 return SHF_X86_64_LARGE;
11765 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11768 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11773 x86_64_section_word (char *str, size_t len)
11775 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11776 return SHF_X86_64_LARGE;
11782 handle_large_common (int small ATTRIBUTE_UNUSED)
11784 if (flag_code != CODE_64BIT)
11786 s_comm_internal (0, elf_common_parse);
11787 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11791 static segT lbss_section;
11792 asection *saved_com_section_ptr = elf_com_section_ptr;
11793 asection *saved_bss_section = bss_section;
11795 if (lbss_section == NULL)
11797 flagword applicable;
11798 segT seg = now_seg;
11799 subsegT subseg = now_subseg;
11801 /* The .lbss section is for local .largecomm symbols. */
11802 lbss_section = subseg_new (".lbss", 0);
11803 applicable = bfd_applicable_section_flags (stdoutput);
11804 bfd_set_section_flags (stdoutput, lbss_section,
11805 applicable & SEC_ALLOC);
11806 seg_info (lbss_section)->bss = 1;
11808 subseg_set (seg, subseg);
11811 elf_com_section_ptr = &_bfd_elf_large_com_section;
11812 bss_section = lbss_section;
11814 s_comm_internal (0, elf_common_parse);
11816 elf_com_section_ptr = saved_com_section_ptr;
11817 bss_section = saved_bss_section;
11820 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */