1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
196 static const char *default_arch = DEFAULT_ARCH;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
269 unsupported_with_intel_mnemonic,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
279 mask_not_on_destination,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op[MAX_OPERANDS];
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default = 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default = 0,
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
378 /* How to encode vector instructions. */
381 vex_encoding_default = 0,
388 const char *rep_prefix;
391 const char *hle_prefix;
393 /* Have BND prefix. */
394 const char *bnd_prefix;
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
400 enum i386_error error;
403 typedef struct _i386_insn i386_insn;
405 /* Link RC type with corresponding string, that'll be looked for in
414 static const struct RC_name RC_NamesTable[] =
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
465 const char line_separator_chars[] = ";";
467 /* Chars that can be used to separate mant from exp in floating point
469 const char EXP_CHARS[] = "eE";
471 /* Chars that mean this number is a floating point constant
474 const char FLT_CHARS[] = "fFdDxX";
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
505 /* The instruction we're assembling. */
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
515 /* Current operand we are working on. */
516 static int this_operand = -1;
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
535 /* The ELF ABI to use. */
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
556 /* 1 for intel syntax,
558 static int intel_syntax = 0;
560 /* 1 for Intel64 ISA,
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
580 static int add_bnd_prefix = 0;
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
593 /* 1 if the assembler should generate relax relocations. */
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
598 static enum check_kind
604 sse_check, operand_check = check_warning;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
611 static int optimize = 0;
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
620 static int optimize_for_space = 0;
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
665 /* Encode scalar AVX instructions with specific vector length. */
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
680 /* Encode EVEX WIG instructions with specific evex.w. */
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
705 #define UNCOND_JUMP 0
707 #define COND_JUMP86 2
712 #define SMALL16 (SMALL | CODE16)
714 #define BIG16 (BIG | CODE16)
718 #define INLINE __inline__
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
739 const relax_typeS md_relax_table[] =
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
778 static const arch_entry cpu_arch[] =
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1038 static const noarch_entry cpu_noarch[] =
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1085 && *input_line_pointer == ',')
1087 align = parse_align (needs_align - 1);
1089 if (align == (addressT) -1)
1104 bss_alloc (symbolP, size, align);
1109 pe_lcomm (int needs_align)
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1115 const pseudo_typeS md_pseudo_table[] =
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1120 {"align", s_align_ptwo, 0},
1122 {"arch", set_cpu_arch, 0},
1126 {"lcomm", pe_lcomm, 1},
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1139 {"code64", set_code_flag, CODE_64BIT},
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1157 {"secrel32", pe_directive_secrel, 0},
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1234 alt_9, alt_10, alt_11
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1241 i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1245 /* Place the longer NOP first. */
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1250 /* Use the smaller one if the requsted one isn't available. */
1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
1257 last = count % max_single_nop_size;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1265 nops = patt[last - 1];
1268 /* Use the smaller one plus one-byte NOP if the needed one
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1276 memcpy (where + offset, nops, last);
1281 fits_in_imm7 (offsetT num)
1283 return (num & 0x7f) == num;
1287 fits_in_imm31 (offsetT num)
1289 return (num & 0x7fffffff) == num;
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1296 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1298 const unsigned char *const *patt = NULL;
1299 int max_single_nop_size;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
1303 switch (fragP->fr_type)
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1326 if (flag_code == CODE_16BIT)
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
1350 case PROCESSOR_CORE:
1351 case PROCESSOR_CORE2:
1352 case PROCESSOR_COREI7:
1353 case PROCESSOR_L1OM:
1354 case PROCESSOR_K1OM:
1355 case PROCESSOR_GENERIC64:
1357 case PROCESSOR_ATHLON:
1359 case PROCESSOR_AMDFAM10:
1361 case PROCESSOR_ZNVER:
1365 case PROCESSOR_I386:
1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
1368 case PROCESSOR_PENTIUMPRO:
1369 case PROCESSOR_IAMCU:
1370 case PROCESSOR_GENERIC32:
1377 switch (fragP->tc_frag_data.tune)
1379 case PROCESSOR_UNKNOWN:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1385 case PROCESSOR_I386:
1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
1388 case PROCESSOR_IAMCU:
1390 case PROCESSOR_ATHLON:
1392 case PROCESSOR_AMDFAM10:
1394 case PROCESSOR_ZNVER:
1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
1408 case PROCESSOR_CORE2:
1409 case PROCESSOR_COREI7:
1410 case PROCESSOR_L1OM:
1411 case PROCESSOR_K1OM:
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1417 case PROCESSOR_GENERIC64:
1423 if (patt == f32_patt)
1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1438 limit = max_single_nop_size;
1440 if (fragP->fr_type == rs_fill_nop)
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1453 fragP->fr_var = count;
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1461 /* Use "jmp disp8" if possible. */
1463 where[0] = jump_disp8[0];
1469 unsigned int size_of_jump;
1471 if (flag_code == CODE_16BIT)
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1479 where[0] = jump32_disp32[0];
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
1501 operand_type_all_zero (const union i386_operand_type *x)
1503 switch (ARRAY_SIZE(x->array))
1514 return !x->array[0];
1521 operand_type_set (union i386_operand_type *x, unsigned int v)
1523 switch (ARRAY_SIZE(x->array))
1541 operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
1544 switch (ARRAY_SIZE(x->array))
1547 if (x->array[2] != y->array[2])
1551 if (x->array[1] != y->array[1])
1555 return x->array[0] == y->array[0];
1563 cpu_flags_all_zero (const union i386_cpu_flags *x)
1565 switch (ARRAY_SIZE(x->array))
1580 return !x->array[0];
1587 cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1590 switch (ARRAY_SIZE(x->array))
1593 if (x->array[3] != y->array[3])
1597 if (x->array[2] != y->array[2])
1601 if (x->array[1] != y->array[1])
1605 return x->array[0] == y->array[0];
1613 cpu_flags_check_cpu64 (i386_cpu_flags f)
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1622 switch (ARRAY_SIZE (x.array))
1625 x.array [3] &= y.array [3];
1628 x.array [2] &= y.array [2];
1631 x.array [1] &= y.array [1];
1634 x.array [0] &= y.array [0];
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1645 switch (ARRAY_SIZE (x.array))
1648 x.array [3] |= y.array [3];
1651 x.array [2] |= y.array [2];
1654 x.array [1] |= y.array [1];
1657 x.array [0] |= y.array [0];
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1668 switch (ARRAY_SIZE (x.array))
1671 x.array [3] &= ~y.array [3];
1674 x.array [2] &= ~y.array [2];
1677 x.array [1] &= ~y.array [1];
1680 x.array [0] &= ~y.array [0];
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1691 #define CPU_FLAGS_PERFECT_MATCH \
1692 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1694 /* Return CPU flags match bits. */
1697 cpu_flags_match (const insn_template *t)
1699 i386_cpu_flags x = t->cpu_flags;
1700 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1702 x.bitfield.cpu64 = 0;
1703 x.bitfield.cpuno64 = 0;
1705 if (cpu_flags_all_zero (&x))
1707 /* This instruction is available on all archs. */
1708 match |= CPU_FLAGS_ARCH_MATCH;
1712 /* This instruction is available only on some archs. */
1713 i386_cpu_flags cpu = cpu_arch_flags;
1715 /* AVX512VL is no standalone feature - match it and then strip it. */
1716 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1718 x.bitfield.cpuavx512vl = 0;
1720 cpu = cpu_flags_and (x, cpu);
1721 if (!cpu_flags_all_zero (&cpu))
1723 if (x.bitfield.cpuavx)
1725 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1726 if (cpu.bitfield.cpuavx
1727 && (!t->opcode_modifier.sse2avx || sse2avx)
1728 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1729 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1730 match |= CPU_FLAGS_ARCH_MATCH;
1733 match |= CPU_FLAGS_ARCH_MATCH;
1739 static INLINE i386_operand_type
1740 operand_type_and (i386_operand_type x, i386_operand_type y)
1742 switch (ARRAY_SIZE (x.array))
1745 x.array [2] &= y.array [2];
1748 x.array [1] &= y.array [1];
1751 x.array [0] &= y.array [0];
1759 static INLINE i386_operand_type
1760 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1762 switch (ARRAY_SIZE (x.array))
1765 x.array [2] &= ~y.array [2];
1768 x.array [1] &= ~y.array [1];
1771 x.array [0] &= ~y.array [0];
1779 static INLINE i386_operand_type
1780 operand_type_or (i386_operand_type x, i386_operand_type y)
1782 switch (ARRAY_SIZE (x.array))
1785 x.array [2] |= y.array [2];
1788 x.array [1] |= y.array [1];
1791 x.array [0] |= y.array [0];
1799 static INLINE i386_operand_type
1800 operand_type_xor (i386_operand_type x, i386_operand_type y)
1802 switch (ARRAY_SIZE (x.array))
1805 x.array [2] ^= y.array [2];
1808 x.array [1] ^= y.array [1];
1811 x.array [0] ^= y.array [0];
1819 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1820 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1821 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1822 static const i386_operand_type inoutportreg
1823 = OPERAND_TYPE_INOUTPORTREG;
1824 static const i386_operand_type reg16_inoutportreg
1825 = OPERAND_TYPE_REG16_INOUTPORTREG;
1826 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1827 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1828 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1829 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1830 static const i386_operand_type anydisp
1831 = OPERAND_TYPE_ANYDISP;
1832 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1833 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1834 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1835 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1836 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1837 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1838 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1839 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1840 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1841 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1842 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1843 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1854 operand_type_check (i386_operand_type t, enum operand_type c)
1859 return t.bitfield.reg;
1862 return (t.bitfield.imm8
1866 || t.bitfield.imm32s
1867 || t.bitfield.imm64);
1870 return (t.bitfield.disp8
1871 || t.bitfield.disp16
1872 || t.bitfield.disp32
1873 || t.bitfield.disp32s
1874 || t.bitfield.disp64);
1877 return (t.bitfield.disp8
1878 || t.bitfield.disp16
1879 || t.bitfield.disp32
1880 || t.bitfield.disp32s
1881 || t.bitfield.disp64
1882 || t.bitfield.baseindex);
1891 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1892 operand J for instruction template T. */
1895 match_reg_size (const insn_template *t, unsigned int j)
1897 return !((i.types[j].bitfield.byte
1898 && !t->operand_types[j].bitfield.byte)
1899 || (i.types[j].bitfield.word
1900 && !t->operand_types[j].bitfield.word)
1901 || (i.types[j].bitfield.dword
1902 && !t->operand_types[j].bitfield.dword)
1903 || (i.types[j].bitfield.qword
1904 && !t->operand_types[j].bitfield.qword)
1905 || (i.types[j].bitfield.tbyte
1906 && !t->operand_types[j].bitfield.tbyte));
1909 /* Return 1 if there is no conflict in SIMD register on
1910 operand J for instruction template T. */
1913 match_simd_size (const insn_template *t, unsigned int j)
1915 return !((i.types[j].bitfield.xmmword
1916 && !t->operand_types[j].bitfield.xmmword)
1917 || (i.types[j].bitfield.ymmword
1918 && !t->operand_types[j].bitfield.ymmword)
1919 || (i.types[j].bitfield.zmmword
1920 && !t->operand_types[j].bitfield.zmmword));
1923 /* Return 1 if there is no conflict in any size on operand J for
1924 instruction template T. */
1927 match_mem_size (const insn_template *t, unsigned int j)
1929 return (match_reg_size (t, j)
1930 && !((i.types[j].bitfield.unspecified
1932 && !t->operand_types[j].bitfield.unspecified)
1933 || (i.types[j].bitfield.fword
1934 && !t->operand_types[j].bitfield.fword)
1935 /* For scalar opcode templates to allow register and memory
1936 operands at the same time, some special casing is needed
1938 || ((t->operand_types[j].bitfield.regsimd
1939 && !t->opcode_modifier.broadcast
1940 && (t->operand_types[j].bitfield.dword
1941 || t->operand_types[j].bitfield.qword))
1942 ? (i.types[j].bitfield.xmmword
1943 || i.types[j].bitfield.ymmword
1944 || i.types[j].bitfield.zmmword)
1945 : !match_simd_size(t, j))));
1948 /* Return 1 if there is no size conflict on any operands for
1949 instruction template T. */
1952 operand_size_match (const insn_template *t)
1957 /* Don't check jump instructions. */
1958 if (t->opcode_modifier.jump
1959 || t->opcode_modifier.jumpbyte
1960 || t->opcode_modifier.jumpdword
1961 || t->opcode_modifier.jumpintersegment)
1964 /* Check memory and accumulator operand size. */
1965 for (j = 0; j < i.operands; j++)
1967 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1968 && t->operand_types[j].bitfield.anysize)
1971 if (t->operand_types[j].bitfield.reg
1972 && !match_reg_size (t, j))
1978 if (t->operand_types[j].bitfield.regsimd
1979 && !match_simd_size (t, j))
1985 if (t->operand_types[j].bitfield.acc
1986 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1992 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2001 else if (!t->opcode_modifier.d)
2004 i.error = operand_size_mismatch;
2008 /* Check reverse. */
2009 gas_assert (i.operands == 2);
2012 for (j = 0; j < 2; j++)
2014 if ((t->operand_types[j].bitfield.reg
2015 || t->operand_types[j].bitfield.acc)
2016 && !match_reg_size (t, j ? 0 : 1))
2019 if (i.types[j].bitfield.mem
2020 && !match_mem_size (t, j ? 0 : 1))
2028 operand_type_match (i386_operand_type overlap,
2029 i386_operand_type given)
2031 i386_operand_type temp = overlap;
2033 temp.bitfield.jumpabsolute = 0;
2034 temp.bitfield.unspecified = 0;
2035 temp.bitfield.byte = 0;
2036 temp.bitfield.word = 0;
2037 temp.bitfield.dword = 0;
2038 temp.bitfield.fword = 0;
2039 temp.bitfield.qword = 0;
2040 temp.bitfield.tbyte = 0;
2041 temp.bitfield.xmmword = 0;
2042 temp.bitfield.ymmword = 0;
2043 temp.bitfield.zmmword = 0;
2044 if (operand_type_all_zero (&temp))
2047 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2048 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2052 i.error = operand_type_mismatch;
2056 /* If given types g0 and g1 are registers they must be of the same type
2057 unless the expected operand type register overlap is null.
2058 Memory operand size of certain SIMD instructions is also being checked
2062 operand_type_register_match (i386_operand_type g0,
2063 i386_operand_type t0,
2064 i386_operand_type g1,
2065 i386_operand_type t1)
2067 if (!g0.bitfield.reg
2068 && !g0.bitfield.regsimd
2069 && (!operand_type_check (g0, anymem)
2070 || g0.bitfield.unspecified
2071 || !t0.bitfield.regsimd))
2074 if (!g1.bitfield.reg
2075 && !g1.bitfield.regsimd
2076 && (!operand_type_check (g1, anymem)
2077 || g1.bitfield.unspecified
2078 || !t1.bitfield.regsimd))
2081 if (g0.bitfield.byte == g1.bitfield.byte
2082 && g0.bitfield.word == g1.bitfield.word
2083 && g0.bitfield.dword == g1.bitfield.dword
2084 && g0.bitfield.qword == g1.bitfield.qword
2085 && g0.bitfield.xmmword == g1.bitfield.xmmword
2086 && g0.bitfield.ymmword == g1.bitfield.ymmword
2087 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2090 if (!(t0.bitfield.byte & t1.bitfield.byte)
2091 && !(t0.bitfield.word & t1.bitfield.word)
2092 && !(t0.bitfield.dword & t1.bitfield.dword)
2093 && !(t0.bitfield.qword & t1.bitfield.qword)
2094 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2095 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2096 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2099 i.error = register_type_mismatch;
2104 static INLINE unsigned int
2105 register_number (const reg_entry *r)
2107 unsigned int nr = r->reg_num;
2109 if (r->reg_flags & RegRex)
2112 if (r->reg_flags & RegVRex)
2118 static INLINE unsigned int
2119 mode_from_disp_size (i386_operand_type t)
2121 if (t.bitfield.disp8)
2123 else if (t.bitfield.disp16
2124 || t.bitfield.disp32
2125 || t.bitfield.disp32s)
2132 fits_in_signed_byte (addressT num)
2134 return num + 0x80 <= 0xff;
2138 fits_in_unsigned_byte (addressT num)
2144 fits_in_unsigned_word (addressT num)
2146 return num <= 0xffff;
2150 fits_in_signed_word (addressT num)
2152 return num + 0x8000 <= 0xffff;
2156 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2161 return num + 0x80000000 <= 0xffffffff;
2163 } /* fits_in_signed_long() */
2166 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2171 return num <= 0xffffffff;
2173 } /* fits_in_unsigned_long() */
2176 fits_in_disp8 (offsetT num)
2178 int shift = i.memshift;
2184 mask = (1 << shift) - 1;
2186 /* Return 0 if NUM isn't properly aligned. */
2190 /* Check if NUM will fit in 8bit after shift. */
2191 return fits_in_signed_byte (num >> shift);
2195 fits_in_imm4 (offsetT num)
2197 return (num & 0xf) == num;
2200 static i386_operand_type
2201 smallest_imm_type (offsetT num)
2203 i386_operand_type t;
2205 operand_type_set (&t, 0);
2206 t.bitfield.imm64 = 1;
2208 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2210 /* This code is disabled on the 486 because all the Imm1 forms
2211 in the opcode table are slower on the i486. They're the
2212 versions with the implicitly specified single-position
2213 displacement, which has another syntax if you really want to
2215 t.bitfield.imm1 = 1;
2216 t.bitfield.imm8 = 1;
2217 t.bitfield.imm8s = 1;
2218 t.bitfield.imm16 = 1;
2219 t.bitfield.imm32 = 1;
2220 t.bitfield.imm32s = 1;
2222 else if (fits_in_signed_byte (num))
2224 t.bitfield.imm8 = 1;
2225 t.bitfield.imm8s = 1;
2226 t.bitfield.imm16 = 1;
2227 t.bitfield.imm32 = 1;
2228 t.bitfield.imm32s = 1;
2230 else if (fits_in_unsigned_byte (num))
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2237 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2239 t.bitfield.imm16 = 1;
2240 t.bitfield.imm32 = 1;
2241 t.bitfield.imm32s = 1;
2243 else if (fits_in_signed_long (num))
2245 t.bitfield.imm32 = 1;
2246 t.bitfield.imm32s = 1;
2248 else if (fits_in_unsigned_long (num))
2249 t.bitfield.imm32 = 1;
2255 offset_in_range (offsetT val, int size)
2261 case 1: mask = ((addressT) 1 << 8) - 1; break;
2262 case 2: mask = ((addressT) 1 << 16) - 1; break;
2263 case 4: mask = ((addressT) 2 << 31) - 1; break;
2265 case 8: mask = ((addressT) 2 << 63) - 1; break;
2271 /* If BFD64, sign extend val for 32bit address mode. */
2272 if (flag_code != CODE_64BIT
2273 || i.prefix[ADDR_PREFIX])
2274 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2275 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2278 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2280 char buf1[40], buf2[40];
2282 sprint_value (buf1, val);
2283 sprint_value (buf2, val & mask);
2284 as_warn (_("%s shortened to %s"), buf1, buf2);
2299 a. PREFIX_EXIST if attempting to add a prefix where one from the
2300 same class already exists.
2301 b. PREFIX_LOCK if lock prefix is added.
2302 c. PREFIX_REP if rep/repne prefix is added.
2303 d. PREFIX_DS if ds prefix is added.
2304 e. PREFIX_OTHER if other prefix is added.
2307 static enum PREFIX_GROUP
2308 add_prefix (unsigned int prefix)
2310 enum PREFIX_GROUP ret = PREFIX_OTHER;
2313 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2314 && flag_code == CODE_64BIT)
2316 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2317 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2318 && (prefix & (REX_R | REX_X | REX_B))))
2329 case DS_PREFIX_OPCODE:
2332 case CS_PREFIX_OPCODE:
2333 case ES_PREFIX_OPCODE:
2334 case FS_PREFIX_OPCODE:
2335 case GS_PREFIX_OPCODE:
2336 case SS_PREFIX_OPCODE:
2340 case REPNE_PREFIX_OPCODE:
2341 case REPE_PREFIX_OPCODE:
2346 case LOCK_PREFIX_OPCODE:
2355 case ADDR_PREFIX_OPCODE:
2359 case DATA_PREFIX_OPCODE:
2363 if (i.prefix[q] != 0)
2371 i.prefix[q] |= prefix;
2374 as_bad (_("same type of prefix used twice"));
2380 update_code_flag (int value, int check)
2382 PRINTF_LIKE ((*as_error));
2384 flag_code = (enum flag_code) value;
2385 if (flag_code == CODE_64BIT)
2387 cpu_arch_flags.bitfield.cpu64 = 1;
2388 cpu_arch_flags.bitfield.cpuno64 = 0;
2392 cpu_arch_flags.bitfield.cpu64 = 0;
2393 cpu_arch_flags.bitfield.cpuno64 = 1;
2395 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2398 as_error = as_fatal;
2401 (*as_error) (_("64bit mode not supported on `%s'."),
2402 cpu_arch_name ? cpu_arch_name : default_arch);
2404 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2407 as_error = as_fatal;
2410 (*as_error) (_("32bit mode not supported on `%s'."),
2411 cpu_arch_name ? cpu_arch_name : default_arch);
2413 stackop_size = '\0';
2417 set_code_flag (int value)
2419 update_code_flag (value, 0);
2423 set_16bit_gcc_code_flag (int new_code_flag)
2425 flag_code = (enum flag_code) new_code_flag;
2426 if (flag_code != CODE_16BIT)
2428 cpu_arch_flags.bitfield.cpu64 = 0;
2429 cpu_arch_flags.bitfield.cpuno64 = 1;
2430 stackop_size = LONG_MNEM_SUFFIX;
2434 set_intel_syntax (int syntax_flag)
2436 /* Find out if register prefixing is specified. */
2437 int ask_naked_reg = 0;
2440 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2443 int e = get_symbol_name (&string);
2445 if (strcmp (string, "prefix") == 0)
2447 else if (strcmp (string, "noprefix") == 0)
2450 as_bad (_("bad argument to syntax directive."));
2451 (void) restore_line_pointer (e);
2453 demand_empty_rest_of_line ();
2455 intel_syntax = syntax_flag;
2457 if (ask_naked_reg == 0)
2458 allow_naked_reg = (intel_syntax
2459 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2461 allow_naked_reg = (ask_naked_reg < 0);
2463 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2465 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2466 identifier_chars['$'] = intel_syntax ? '$' : 0;
2467 register_prefix = allow_naked_reg ? "" : "%";
2471 set_intel_mnemonic (int mnemonic_flag)
2473 intel_mnemonic = mnemonic_flag;
2477 set_allow_index_reg (int flag)
2479 allow_index_reg = flag;
2483 set_check (int what)
2485 enum check_kind *kind;
2490 kind = &operand_check;
2501 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2504 int e = get_symbol_name (&string);
2506 if (strcmp (string, "none") == 0)
2508 else if (strcmp (string, "warning") == 0)
2509 *kind = check_warning;
2510 else if (strcmp (string, "error") == 0)
2511 *kind = check_error;
2513 as_bad (_("bad argument to %s_check directive."), str);
2514 (void) restore_line_pointer (e);
2517 as_bad (_("missing argument for %s_check directive"), str);
2519 demand_empty_rest_of_line ();
2523 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2524 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2527 static const char *arch;
2529 /* Intel LIOM is only supported on ELF. */
2535 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2536 use default_arch. */
2537 arch = cpu_arch_name;
2539 arch = default_arch;
2542 /* If we are targeting Intel MCU, we must enable it. */
2543 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2544 || new_flag.bitfield.cpuiamcu)
2547 /* If we are targeting Intel L1OM, we must enable it. */
2548 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2549 || new_flag.bitfield.cpul1om)
2552 /* If we are targeting Intel K1OM, we must enable it. */
2553 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2554 || new_flag.bitfield.cpuk1om)
2557 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2562 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2566 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2569 int e = get_symbol_name (&string);
2571 i386_cpu_flags flags;
2573 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2575 if (strcmp (string, cpu_arch[j].name) == 0)
2577 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2581 cpu_arch_name = cpu_arch[j].name;
2582 cpu_sub_arch_name = NULL;
2583 cpu_arch_flags = cpu_arch[j].flags;
2584 if (flag_code == CODE_64BIT)
2586 cpu_arch_flags.bitfield.cpu64 = 1;
2587 cpu_arch_flags.bitfield.cpuno64 = 0;
2591 cpu_arch_flags.bitfield.cpu64 = 0;
2592 cpu_arch_flags.bitfield.cpuno64 = 1;
2594 cpu_arch_isa = cpu_arch[j].type;
2595 cpu_arch_isa_flags = cpu_arch[j].flags;
2596 if (!cpu_arch_tune_set)
2598 cpu_arch_tune = cpu_arch_isa;
2599 cpu_arch_tune_flags = cpu_arch_isa_flags;
2604 flags = cpu_flags_or (cpu_arch_flags,
2607 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2609 if (cpu_sub_arch_name)
2611 char *name = cpu_sub_arch_name;
2612 cpu_sub_arch_name = concat (name,
2614 (const char *) NULL);
2618 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2619 cpu_arch_flags = flags;
2620 cpu_arch_isa_flags = flags;
2622 (void) restore_line_pointer (e);
2623 demand_empty_rest_of_line ();
2628 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2630 /* Disable an ISA extension. */
2631 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2632 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2634 flags = cpu_flags_and_not (cpu_arch_flags,
2635 cpu_noarch[j].flags);
2636 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2638 if (cpu_sub_arch_name)
2640 char *name = cpu_sub_arch_name;
2641 cpu_sub_arch_name = concat (name, string,
2642 (const char *) NULL);
2646 cpu_sub_arch_name = xstrdup (string);
2647 cpu_arch_flags = flags;
2648 cpu_arch_isa_flags = flags;
2650 (void) restore_line_pointer (e);
2651 demand_empty_rest_of_line ();
2655 j = ARRAY_SIZE (cpu_arch);
2658 if (j >= ARRAY_SIZE (cpu_arch))
2659 as_bad (_("no such architecture: `%s'"), string);
2661 *input_line_pointer = e;
2664 as_bad (_("missing cpu architecture"));
2666 no_cond_jump_promotion = 0;
2667 if (*input_line_pointer == ','
2668 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2673 ++input_line_pointer;
2674 e = get_symbol_name (&string);
2676 if (strcmp (string, "nojumps") == 0)
2677 no_cond_jump_promotion = 1;
2678 else if (strcmp (string, "jumps") == 0)
2681 as_bad (_("no such architecture modifier: `%s'"), string);
2683 (void) restore_line_pointer (e);
2686 demand_empty_rest_of_line ();
2689 enum bfd_architecture
2692 if (cpu_arch_isa == PROCESSOR_L1OM)
2694 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2695 || flag_code != CODE_64BIT)
2696 as_fatal (_("Intel L1OM is 64bit ELF only"));
2697 return bfd_arch_l1om;
2699 else if (cpu_arch_isa == PROCESSOR_K1OM)
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel K1OM is 64bit ELF only"));
2704 return bfd_arch_k1om;
2706 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code == CODE_64BIT)
2710 as_fatal (_("Intel MCU is 32bit ELF only"));
2711 return bfd_arch_iamcu;
2714 return bfd_arch_i386;
2720 if (!strncmp (default_arch, "x86_64", 6))
2722 if (cpu_arch_isa == PROCESSOR_L1OM)
2724 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2725 || default_arch[6] != '\0')
2726 as_fatal (_("Intel L1OM is 64bit ELF only"));
2727 return bfd_mach_l1om;
2729 else if (cpu_arch_isa == PROCESSOR_K1OM)
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
2733 as_fatal (_("Intel K1OM is 64bit ELF only"));
2734 return bfd_mach_k1om;
2736 else if (default_arch[6] == '\0')
2737 return bfd_mach_x86_64;
2739 return bfd_mach_x64_32;
2741 else if (!strcmp (default_arch, "i386")
2742 || !strcmp (default_arch, "iamcu"))
2744 if (cpu_arch_isa == PROCESSOR_IAMCU)
2746 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2747 as_fatal (_("Intel MCU is 32bit ELF only"));
2748 return bfd_mach_i386_iamcu;
2751 return bfd_mach_i386_i386;
2754 as_fatal (_("unknown architecture"));
2760 const char *hash_err;
2762 /* Support pseudo prefixes like {disp32}. */
2763 lex_type ['{'] = LEX_BEGIN_NAME;
2765 /* Initialize op_hash hash table. */
2766 op_hash = hash_new ();
2769 const insn_template *optab;
2770 templates *core_optab;
2772 /* Setup for loop. */
2774 core_optab = XNEW (templates);
2775 core_optab->start = optab;
2780 if (optab->name == NULL
2781 || strcmp (optab->name, (optab - 1)->name) != 0)
2783 /* different name --> ship out current template list;
2784 add to hash table; & begin anew. */
2785 core_optab->end = optab;
2786 hash_err = hash_insert (op_hash,
2788 (void *) core_optab);
2791 as_fatal (_("can't hash %s: %s"),
2795 if (optab->name == NULL)
2797 core_optab = XNEW (templates);
2798 core_optab->start = optab;
2803 /* Initialize reg_hash hash table. */
2804 reg_hash = hash_new ();
2806 const reg_entry *regtab;
2807 unsigned int regtab_size = i386_regtab_size;
2809 for (regtab = i386_regtab; regtab_size--; regtab++)
2811 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2813 as_fatal (_("can't hash %s: %s"),
2819 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2824 for (c = 0; c < 256; c++)
2829 mnemonic_chars[c] = c;
2830 register_chars[c] = c;
2831 operand_chars[c] = c;
2833 else if (ISLOWER (c))
2835 mnemonic_chars[c] = c;
2836 register_chars[c] = c;
2837 operand_chars[c] = c;
2839 else if (ISUPPER (c))
2841 mnemonic_chars[c] = TOLOWER (c);
2842 register_chars[c] = mnemonic_chars[c];
2843 operand_chars[c] = c;
2845 else if (c == '{' || c == '}')
2847 mnemonic_chars[c] = c;
2848 operand_chars[c] = c;
2851 if (ISALPHA (c) || ISDIGIT (c))
2852 identifier_chars[c] = c;
2855 identifier_chars[c] = c;
2856 operand_chars[c] = c;
2861 identifier_chars['@'] = '@';
2864 identifier_chars['?'] = '?';
2865 operand_chars['?'] = '?';
2867 digit_chars['-'] = '-';
2868 mnemonic_chars['_'] = '_';
2869 mnemonic_chars['-'] = '-';
2870 mnemonic_chars['.'] = '.';
2871 identifier_chars['_'] = '_';
2872 identifier_chars['.'] = '.';
2874 for (p = operand_special_chars; *p != '\0'; p++)
2875 operand_chars[(unsigned char) *p] = *p;
2878 if (flag_code == CODE_64BIT)
2880 #if defined (OBJ_COFF) && defined (TE_PE)
2881 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2884 x86_dwarf2_return_column = 16;
2886 x86_cie_data_alignment = -8;
2890 x86_dwarf2_return_column = 8;
2891 x86_cie_data_alignment = -4;
2896 i386_print_statistics (FILE *file)
2898 hash_print_statistics (file, "i386 opcode", op_hash);
2899 hash_print_statistics (file, "i386 register", reg_hash);
2904 /* Debugging routines for md_assemble. */
2905 static void pte (insn_template *);
2906 static void pt (i386_operand_type);
2907 static void pe (expressionS *);
2908 static void ps (symbolS *);
2911 pi (char *line, i386_insn *x)
2915 fprintf (stdout, "%s: template ", line);
2917 fprintf (stdout, " address: base %s index %s scale %x\n",
2918 x->base_reg ? x->base_reg->reg_name : "none",
2919 x->index_reg ? x->index_reg->reg_name : "none",
2920 x->log2_scale_factor);
2921 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2922 x->rm.mode, x->rm.reg, x->rm.regmem);
2923 fprintf (stdout, " sib: base %x index %x scale %x\n",
2924 x->sib.base, x->sib.index, x->sib.scale);
2925 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2926 (x->rex & REX_W) != 0,
2927 (x->rex & REX_R) != 0,
2928 (x->rex & REX_X) != 0,
2929 (x->rex & REX_B) != 0);
2930 for (j = 0; j < x->operands; j++)
2932 fprintf (stdout, " #%d: ", j + 1);
2934 fprintf (stdout, "\n");
2935 if (x->types[j].bitfield.reg
2936 || x->types[j].bitfield.regmmx
2937 || x->types[j].bitfield.regsimd
2938 || x->types[j].bitfield.sreg2
2939 || x->types[j].bitfield.sreg3
2940 || x->types[j].bitfield.control
2941 || x->types[j].bitfield.debug
2942 || x->types[j].bitfield.test)
2943 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2944 if (operand_type_check (x->types[j], imm))
2946 if (operand_type_check (x->types[j], disp))
2947 pe (x->op[j].disps);
2952 pte (insn_template *t)
2955 fprintf (stdout, " %d operands ", t->operands);
2956 fprintf (stdout, "opcode %x ", t->base_opcode);
2957 if (t->extension_opcode != None)
2958 fprintf (stdout, "ext %x ", t->extension_opcode);
2959 if (t->opcode_modifier.d)
2960 fprintf (stdout, "D");
2961 if (t->opcode_modifier.w)
2962 fprintf (stdout, "W");
2963 fprintf (stdout, "\n");
2964 for (j = 0; j < t->operands; j++)
2966 fprintf (stdout, " #%d type ", j + 1);
2967 pt (t->operand_types[j]);
2968 fprintf (stdout, "\n");
2975 fprintf (stdout, " operation %d\n", e->X_op);
2976 fprintf (stdout, " add_number %ld (%lx)\n",
2977 (long) e->X_add_number, (long) e->X_add_number);
2978 if (e->X_add_symbol)
2980 fprintf (stdout, " add_symbol ");
2981 ps (e->X_add_symbol);
2982 fprintf (stdout, "\n");
2986 fprintf (stdout, " op_symbol ");
2987 ps (e->X_op_symbol);
2988 fprintf (stdout, "\n");
2995 fprintf (stdout, "%s type %s%s",
2997 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2998 segment_name (S_GET_SEGMENT (s)));
3001 static struct type_name
3003 i386_operand_type mask;
3006 const type_names[] =
3008 { OPERAND_TYPE_REG8, "r8" },
3009 { OPERAND_TYPE_REG16, "r16" },
3010 { OPERAND_TYPE_REG32, "r32" },
3011 { OPERAND_TYPE_REG64, "r64" },
3012 { OPERAND_TYPE_IMM8, "i8" },
3013 { OPERAND_TYPE_IMM8, "i8s" },
3014 { OPERAND_TYPE_IMM16, "i16" },
3015 { OPERAND_TYPE_IMM32, "i32" },
3016 { OPERAND_TYPE_IMM32S, "i32s" },
3017 { OPERAND_TYPE_IMM64, "i64" },
3018 { OPERAND_TYPE_IMM1, "i1" },
3019 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3020 { OPERAND_TYPE_DISP8, "d8" },
3021 { OPERAND_TYPE_DISP16, "d16" },
3022 { OPERAND_TYPE_DISP32, "d32" },
3023 { OPERAND_TYPE_DISP32S, "d32s" },
3024 { OPERAND_TYPE_DISP64, "d64" },
3025 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3026 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3027 { OPERAND_TYPE_CONTROL, "control reg" },
3028 { OPERAND_TYPE_TEST, "test reg" },
3029 { OPERAND_TYPE_DEBUG, "debug reg" },
3030 { OPERAND_TYPE_FLOATREG, "FReg" },
3031 { OPERAND_TYPE_FLOATACC, "FAcc" },
3032 { OPERAND_TYPE_SREG2, "SReg2" },
3033 { OPERAND_TYPE_SREG3, "SReg3" },
3034 { OPERAND_TYPE_ACC, "Acc" },
3035 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3036 { OPERAND_TYPE_REGMMX, "rMMX" },
3037 { OPERAND_TYPE_REGXMM, "rXMM" },
3038 { OPERAND_TYPE_REGYMM, "rYMM" },
3039 { OPERAND_TYPE_REGZMM, "rZMM" },
3040 { OPERAND_TYPE_REGMASK, "Mask reg" },
3041 { OPERAND_TYPE_ESSEG, "es" },
3045 pt (i386_operand_type t)
3048 i386_operand_type a;
3050 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3052 a = operand_type_and (t, type_names[j].mask);
3053 if (!operand_type_all_zero (&a))
3054 fprintf (stdout, "%s, ", type_names[j].name);
3059 #endif /* DEBUG386 */
3061 static bfd_reloc_code_real_type
3062 reloc (unsigned int size,
3065 bfd_reloc_code_real_type other)
3067 if (other != NO_RELOC)
3069 reloc_howto_type *rel;
3074 case BFD_RELOC_X86_64_GOT32:
3075 return BFD_RELOC_X86_64_GOT64;
3077 case BFD_RELOC_X86_64_GOTPLT64:
3078 return BFD_RELOC_X86_64_GOTPLT64;
3080 case BFD_RELOC_X86_64_PLTOFF64:
3081 return BFD_RELOC_X86_64_PLTOFF64;
3083 case BFD_RELOC_X86_64_GOTPC32:
3084 other = BFD_RELOC_X86_64_GOTPC64;
3086 case BFD_RELOC_X86_64_GOTPCREL:
3087 other = BFD_RELOC_X86_64_GOTPCREL64;
3089 case BFD_RELOC_X86_64_TPOFF32:
3090 other = BFD_RELOC_X86_64_TPOFF64;
3092 case BFD_RELOC_X86_64_DTPOFF32:
3093 other = BFD_RELOC_X86_64_DTPOFF64;
3099 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3100 if (other == BFD_RELOC_SIZE32)
3103 other = BFD_RELOC_SIZE64;
3106 as_bad (_("there are no pc-relative size relocations"));
3112 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3113 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3116 rel = bfd_reloc_type_lookup (stdoutput, other);
3118 as_bad (_("unknown relocation (%u)"), other);
3119 else if (size != bfd_get_reloc_size (rel))
3120 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3121 bfd_get_reloc_size (rel),
3123 else if (pcrel && !rel->pc_relative)
3124 as_bad (_("non-pc-relative relocation for pc-relative field"));
3125 else if ((rel->complain_on_overflow == complain_overflow_signed
3127 || (rel->complain_on_overflow == complain_overflow_unsigned
3129 as_bad (_("relocated field and relocation type differ in signedness"));
3138 as_bad (_("there are no unsigned pc-relative relocations"));
3141 case 1: return BFD_RELOC_8_PCREL;
3142 case 2: return BFD_RELOC_16_PCREL;
3143 case 4: return BFD_RELOC_32_PCREL;
3144 case 8: return BFD_RELOC_64_PCREL;
3146 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3153 case 4: return BFD_RELOC_X86_64_32S;
3158 case 1: return BFD_RELOC_8;
3159 case 2: return BFD_RELOC_16;
3160 case 4: return BFD_RELOC_32;
3161 case 8: return BFD_RELOC_64;
3163 as_bad (_("cannot do %s %u byte relocation"),
3164 sign > 0 ? "signed" : "unsigned", size);
3170 /* Here we decide which fixups can be adjusted to make them relative to
3171 the beginning of the section instead of the symbol. Basically we need
3172 to make sure that the dynamic relocations are done correctly, so in
3173 some cases we force the original symbol to be used. */
3176 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3182 /* Don't adjust pc-relative references to merge sections in 64-bit
3184 if (use_rela_relocations
3185 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3189 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3190 and changed later by validate_fix. */
3191 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3192 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3195 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3196 for size relocations. */
3197 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3198 || fixP->fx_r_type == BFD_RELOC_SIZE64
3199 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3200 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3201 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3202 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3203 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3204 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3205 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3206 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3207 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3208 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3209 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3213 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3214 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3215 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3216 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3217 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3218 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3219 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3228 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3229 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3236 intel_float_operand (const char *mnemonic)
3238 /* Note that the value returned is meaningful only for opcodes with (memory)
3239 operands, hence the code here is free to improperly handle opcodes that
3240 have no operands (for better performance and smaller code). */
3242 if (mnemonic[0] != 'f')
3243 return 0; /* non-math */
3245 switch (mnemonic[1])
3247 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3248 the fs segment override prefix not currently handled because no
3249 call path can make opcodes without operands get here */
3251 return 2 /* integer op */;
3253 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3254 return 3; /* fldcw/fldenv */
3257 if (mnemonic[2] != 'o' /* fnop */)
3258 return 3; /* non-waiting control op */
3261 if (mnemonic[2] == 's')
3262 return 3; /* frstor/frstpm */
3265 if (mnemonic[2] == 'a')
3266 return 3; /* fsave */
3267 if (mnemonic[2] == 't')
3269 switch (mnemonic[3])
3271 case 'c': /* fstcw */
3272 case 'd': /* fstdw */
3273 case 'e': /* fstenv */
3274 case 's': /* fsts[gw] */
3280 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3281 return 0; /* fxsave/fxrstor are not really math ops */
3288 /* Build the VEX prefix. */
3291 build_vex_prefix (const insn_template *t)
3293 unsigned int register_specifier;
3294 unsigned int implied_prefix;
3295 unsigned int vector_length;
3297 /* Check register specifier. */
3298 if (i.vex.register_specifier)
3300 register_specifier =
3301 ~register_number (i.vex.register_specifier) & 0xf;
3302 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3305 register_specifier = 0xf;
3307 /* Use 2-byte VEX prefix by swapping destination and source
3309 if (i.vec_encoding != vex_encoding_vex3
3310 && i.dir_encoding == dir_encoding_default
3311 && i.operands == i.reg_operands
3312 && i.tm.opcode_modifier.vexopcode == VEX0F
3313 && i.tm.opcode_modifier.load
3316 unsigned int xchg = i.operands - 1;
3317 union i386_op temp_op;
3318 i386_operand_type temp_type;
3320 temp_type = i.types[xchg];
3321 i.types[xchg] = i.types[0];
3322 i.types[0] = temp_type;
3323 temp_op = i.op[xchg];
3324 i.op[xchg] = i.op[0];
3327 gas_assert (i.rm.mode == 3);
3331 i.rm.regmem = i.rm.reg;
3334 /* Use the next insn. */
3338 if (i.tm.opcode_modifier.vex == VEXScalar)
3339 vector_length = avxscalar;
3340 else if (i.tm.opcode_modifier.vex == VEX256)
3347 for (op = 0; op < t->operands; ++op)
3348 if (t->operand_types[op].bitfield.xmmword
3349 && t->operand_types[op].bitfield.ymmword
3350 && i.types[op].bitfield.ymmword)
3357 switch ((i.tm.base_opcode >> 8) & 0xff)
3362 case DATA_PREFIX_OPCODE:
3365 case REPE_PREFIX_OPCODE:
3368 case REPNE_PREFIX_OPCODE:
3375 /* Use 2-byte VEX prefix if possible. */
3376 if (i.vec_encoding != vex_encoding_vex3
3377 && i.tm.opcode_modifier.vexopcode == VEX0F
3378 && i.tm.opcode_modifier.vexw != VEXW1
3379 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3381 /* 2-byte VEX prefix. */
3385 i.vex.bytes[0] = 0xc5;
3387 /* Check the REX.R bit. */
3388 r = (i.rex & REX_R) ? 0 : 1;
3389 i.vex.bytes[1] = (r << 7
3390 | register_specifier << 3
3391 | vector_length << 2
3396 /* 3-byte VEX prefix. */
3401 switch (i.tm.opcode_modifier.vexopcode)
3405 i.vex.bytes[0] = 0xc4;
3409 i.vex.bytes[0] = 0xc4;
3413 i.vex.bytes[0] = 0xc4;
3417 i.vex.bytes[0] = 0x8f;
3421 i.vex.bytes[0] = 0x8f;
3425 i.vex.bytes[0] = 0x8f;
3431 /* The high 3 bits of the second VEX byte are 1's compliment
3432 of RXB bits from REX. */
3433 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3435 /* Check the REX.W bit. */
3436 w = (i.rex & REX_W) ? 1 : 0;
3437 if (i.tm.opcode_modifier.vexw == VEXW1)
3440 i.vex.bytes[2] = (w << 7
3441 | register_specifier << 3
3442 | vector_length << 2
3447 /* Build the EVEX prefix. */
3450 build_evex_prefix (void)
3452 unsigned int register_specifier;
3453 unsigned int implied_prefix;
3455 rex_byte vrex_used = 0;
3457 /* Check register specifier. */
3458 if (i.vex.register_specifier)
3460 gas_assert ((i.vrex & REX_X) == 0);
3462 register_specifier = i.vex.register_specifier->reg_num;
3463 if ((i.vex.register_specifier->reg_flags & RegRex))
3464 register_specifier += 8;
3465 /* The upper 16 registers are encoded in the fourth byte of the
3467 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3468 i.vex.bytes[3] = 0x8;
3469 register_specifier = ~register_specifier & 0xf;
3473 register_specifier = 0xf;
3475 /* Encode upper 16 vector index register in the fourth byte of
3477 if (!(i.vrex & REX_X))
3478 i.vex.bytes[3] = 0x8;
3483 switch ((i.tm.base_opcode >> 8) & 0xff)
3488 case DATA_PREFIX_OPCODE:
3491 case REPE_PREFIX_OPCODE:
3494 case REPNE_PREFIX_OPCODE:
3501 /* 4 byte EVEX prefix. */
3503 i.vex.bytes[0] = 0x62;
3506 switch (i.tm.opcode_modifier.vexopcode)
3522 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3524 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3526 /* The fifth bit of the second EVEX byte is 1's compliment of the
3527 REX_R bit in VREX. */
3528 if (!(i.vrex & REX_R))
3529 i.vex.bytes[1] |= 0x10;
3533 if ((i.reg_operands + i.imm_operands) == i.operands)
3535 /* When all operands are registers, the REX_X bit in REX is not
3536 used. We reuse it to encode the upper 16 registers, which is
3537 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3538 as 1's compliment. */
3539 if ((i.vrex & REX_B))
3542 i.vex.bytes[1] &= ~0x40;
3546 /* EVEX instructions shouldn't need the REX prefix. */
3547 i.vrex &= ~vrex_used;
3548 gas_assert (i.vrex == 0);
3550 /* Check the REX.W bit. */
3551 w = (i.rex & REX_W) ? 1 : 0;
3552 if (i.tm.opcode_modifier.vexw)
3554 if (i.tm.opcode_modifier.vexw == VEXW1)
3557 /* If w is not set it means we are dealing with WIG instruction. */
3560 if (evexwig == evexw1)
3564 /* Encode the U bit. */
3565 implied_prefix |= 0x4;
3567 /* The third byte of the EVEX prefix. */
3568 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3570 /* The fourth byte of the EVEX prefix. */
3571 /* The zeroing-masking bit. */
3572 if (i.mask && i.mask->zeroing)
3573 i.vex.bytes[3] |= 0x80;
3575 /* Don't always set the broadcast bit if there is no RC. */
3578 /* Encode the vector length. */
3579 unsigned int vec_length;
3581 switch (i.tm.opcode_modifier.evex)
3583 case EVEXLIG: /* LL' is ignored */
3584 vec_length = evexlig << 5;
3587 vec_length = 0 << 5;
3590 vec_length = 1 << 5;
3593 vec_length = 2 << 5;
3599 i.vex.bytes[3] |= vec_length;
3600 /* Encode the broadcast bit. */
3602 i.vex.bytes[3] |= 0x10;
3606 if (i.rounding->type != saeonly)
3607 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3609 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3612 if (i.mask && i.mask->mask)
3613 i.vex.bytes[3] |= i.mask->mask->reg_num;
3617 process_immext (void)
3621 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3624 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3625 with an opcode suffix which is coded in the same place as an
3626 8-bit immediate field would be.
3627 Here we check those operands and remove them afterwards. */
3630 for (x = 0; x < i.operands; x++)
3631 if (register_number (i.op[x].regs) != x)
3632 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3633 register_prefix, i.op[x].regs->reg_name, x + 1,
3639 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3641 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3642 suffix which is coded in the same place as an 8-bit immediate
3644 Here we check those operands and remove them afterwards. */
3647 if (i.operands != 3)
3650 for (x = 0; x < 2; x++)
3651 if (register_number (i.op[x].regs) != x)
3652 goto bad_register_operand;
3654 /* Check for third operand for mwaitx/monitorx insn. */
3655 if (register_number (i.op[x].regs)
3656 != (x + (i.tm.extension_opcode == 0xfb)))
3658 bad_register_operand:
3659 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3660 register_prefix, i.op[x].regs->reg_name, x+1,
3667 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3668 which is coded in the same place as an 8-bit immediate field
3669 would be. Here we fake an 8-bit immediate operand from the
3670 opcode suffix stored in tm.extension_opcode.
3672 AVX instructions also use this encoding, for some of
3673 3 argument instructions. */
3675 gas_assert (i.imm_operands <= 1
3677 || ((i.tm.opcode_modifier.vex
3678 || i.tm.opcode_modifier.evex)
3679 && i.operands <= 4)));
3681 exp = &im_expressions[i.imm_operands++];
3682 i.op[i.operands].imms = exp;
3683 i.types[i.operands] = imm8;
3685 exp->X_op = O_constant;
3686 exp->X_add_number = i.tm.extension_opcode;
3687 i.tm.extension_opcode = None;
3694 switch (i.tm.opcode_modifier.hleprefixok)
3699 as_bad (_("invalid instruction `%s' after `%s'"),
3700 i.tm.name, i.hle_prefix);
3703 if (i.prefix[LOCK_PREFIX])
3705 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3709 case HLEPrefixRelease:
3710 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3712 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3716 if (i.mem_operands == 0
3717 || !operand_type_check (i.types[i.operands - 1], anymem))
3719 as_bad (_("memory destination needed for instruction `%s'"
3720 " after `xrelease'"), i.tm.name);
3727 /* Try the shortest encoding by shortening operand size. */
3730 optimize_encoding (void)
3734 if (optimize_for_space
3735 && i.reg_operands == 1
3736 && i.imm_operands == 1
3737 && !i.types[1].bitfield.byte
3738 && i.op[0].imms->X_op == O_constant
3739 && fits_in_imm7 (i.op[0].imms->X_add_number)
3740 && ((i.tm.base_opcode == 0xa8
3741 && i.tm.extension_opcode == None)
3742 || (i.tm.base_opcode == 0xf6
3743 && i.tm.extension_opcode == 0x0)))
3746 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3748 unsigned int base_regnum = i.op[1].regs->reg_num;
3749 if (flag_code == CODE_64BIT || base_regnum < 4)
3751 i.types[1].bitfield.byte = 1;
3752 /* Ignore the suffix. */
3754 if (base_regnum >= 4
3755 && !(i.op[1].regs->reg_flags & RegRex))
3757 /* Handle SP, BP, SI and DI registers. */
3758 if (i.types[1].bitfield.word)
3760 else if (i.types[1].bitfield.dword)
3768 else if (flag_code == CODE_64BIT
3769 && ((i.reg_operands == 1
3770 && i.imm_operands == 1
3771 && i.op[0].imms->X_op == O_constant
3772 && ((i.tm.base_opcode == 0xb0
3773 && i.tm.extension_opcode == None
3774 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3775 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3776 && (((i.tm.base_opcode == 0x24
3777 || i.tm.base_opcode == 0xa8)
3778 && i.tm.extension_opcode == None)
3779 || (i.tm.base_opcode == 0x80
3780 && i.tm.extension_opcode == 0x4)
3781 || ((i.tm.base_opcode == 0xf6
3782 || i.tm.base_opcode == 0xc6)
3783 && i.tm.extension_opcode == 0x0)))))
3784 || (i.reg_operands == 2
3785 && i.op[0].regs == i.op[1].regs
3786 && ((i.tm.base_opcode == 0x30
3787 || i.tm.base_opcode == 0x28)
3788 && i.tm.extension_opcode == None)))
3789 && i.types[1].bitfield.qword)
3792 andq $imm31, %r64 -> andl $imm31, %r32
3793 testq $imm31, %r64 -> testl $imm31, %r32
3794 xorq %r64, %r64 -> xorl %r32, %r32
3795 subq %r64, %r64 -> subl %r32, %r32
3796 movq $imm31, %r64 -> movl $imm31, %r32
3797 movq $imm32, %r64 -> movl $imm32, %r32
3799 i.tm.opcode_modifier.norex64 = 1;
3800 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3803 movq $imm31, %r64 -> movl $imm31, %r32
3804 movq $imm32, %r64 -> movl $imm32, %r32
3806 i.tm.operand_types[0].bitfield.imm32 = 1;
3807 i.tm.operand_types[0].bitfield.imm32s = 0;
3808 i.tm.operand_types[0].bitfield.imm64 = 0;
3809 i.types[0].bitfield.imm32 = 1;
3810 i.types[0].bitfield.imm32s = 0;
3811 i.types[0].bitfield.imm64 = 0;
3812 i.types[1].bitfield.dword = 1;
3813 i.types[1].bitfield.qword = 0;
3814 if (i.tm.base_opcode == 0xc6)
3817 movq $imm31, %r64 -> movl $imm31, %r32
3819 i.tm.base_opcode = 0xb0;
3820 i.tm.extension_opcode = None;
3821 i.tm.opcode_modifier.shortform = 1;
3822 i.tm.opcode_modifier.modrm = 0;
3826 else if (optimize > 1
3827 && i.reg_operands == 3
3828 && i.op[0].regs == i.op[1].regs
3829 && !i.types[2].bitfield.xmmword
3830 && (i.tm.opcode_modifier.vex
3833 && i.tm.opcode_modifier.evex
3834 && cpu_arch_flags.bitfield.cpuavx512vl))
3835 && ((i.tm.base_opcode == 0x55
3836 || i.tm.base_opcode == 0x6655
3837 || i.tm.base_opcode == 0x66df
3838 || i.tm.base_opcode == 0x57
3839 || i.tm.base_opcode == 0x6657
3840 || i.tm.base_opcode == 0x66ef
3841 || i.tm.base_opcode == 0x66f8
3842 || i.tm.base_opcode == 0x66f9
3843 || i.tm.base_opcode == 0x66fa
3844 || i.tm.base_opcode == 0x66fb)
3845 && i.tm.extension_opcode == None))
3848 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3850 EVEX VOP %zmmM, %zmmM, %zmmN
3851 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3852 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3853 EVEX VOP %ymmM, %ymmM, %ymmN
3854 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3855 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3856 VEX VOP %ymmM, %ymmM, %ymmN
3857 -> VEX VOP %xmmM, %xmmM, %xmmN
3858 VOP, one of vpandn and vpxor:
3859 VEX VOP %ymmM, %ymmM, %ymmN
3860 -> VEX VOP %xmmM, %xmmM, %xmmN
3861 VOP, one of vpandnd and vpandnq:
3862 EVEX VOP %zmmM, %zmmM, %zmmN
3863 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3864 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3865 EVEX VOP %ymmM, %ymmM, %ymmN
3866 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3867 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3868 VOP, one of vpxord and vpxorq:
3869 EVEX VOP %zmmM, %zmmM, %zmmN
3870 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3871 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3872 EVEX VOP %ymmM, %ymmM, %ymmN
3873 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3876 if (i.tm.opcode_modifier.evex)
3878 /* If only lower 16 vector registers are used, we can use
3880 for (j = 0; j < 3; j++)
3881 if (register_number (i.op[j].regs) > 15)
3885 i.tm.opcode_modifier.evex = EVEX128;
3888 i.tm.opcode_modifier.vex = VEX128;
3889 i.tm.opcode_modifier.vexw = VEXW0;
3890 i.tm.opcode_modifier.evex = 0;
3894 i.tm.opcode_modifier.vex = VEX128;
3896 if (i.tm.opcode_modifier.vex)
3897 for (j = 0; j < 3; j++)
3899 i.types[j].bitfield.xmmword = 1;
3900 i.types[j].bitfield.ymmword = 0;
3905 /* This is the guts of the machine-dependent assembler. LINE points to a
3906 machine dependent instruction. This function is supposed to emit
3907 the frags/bytes it assembles to. */
3910 md_assemble (char *line)
3913 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3914 const insn_template *t;
3916 /* Initialize globals. */
3917 memset (&i, '\0', sizeof (i));
3918 for (j = 0; j < MAX_OPERANDS; j++)
3919 i.reloc[j] = NO_RELOC;
3920 memset (disp_expressions, '\0', sizeof (disp_expressions));
3921 memset (im_expressions, '\0', sizeof (im_expressions));
3922 save_stack_p = save_stack;
3924 /* First parse an instruction mnemonic & call i386_operand for the operands.
3925 We assume that the scrubber has arranged it so that line[0] is the valid
3926 start of a (possibly prefixed) mnemonic. */
3928 line = parse_insn (line, mnemonic);
3931 mnem_suffix = i.suffix;
3933 line = parse_operands (line, mnemonic);
3935 xfree (i.memop1_string);
3936 i.memop1_string = NULL;
3940 /* Now we've parsed the mnemonic into a set of templates, and have the
3941 operands at hand. */
3943 /* All intel opcodes have reversed operands except for "bound" and
3944 "enter". We also don't reverse intersegment "jmp" and "call"
3945 instructions with 2 immediate operands so that the immediate segment
3946 precedes the offset, as it does when in AT&T mode. */
3949 && (strcmp (mnemonic, "bound") != 0)
3950 && (strcmp (mnemonic, "invlpga") != 0)
3951 && !(operand_type_check (i.types[0], imm)
3952 && operand_type_check (i.types[1], imm)))
3955 /* The order of the immediates should be reversed
3956 for 2 immediates extrq and insertq instructions */
3957 if (i.imm_operands == 2
3958 && (strcmp (mnemonic, "extrq") == 0
3959 || strcmp (mnemonic, "insertq") == 0))
3960 swap_2_operands (0, 1);
3965 /* Don't optimize displacement for movabs since it only takes 64bit
3968 && i.disp_encoding != disp_encoding_32bit
3969 && (flag_code != CODE_64BIT
3970 || strcmp (mnemonic, "movabs") != 0))
3973 /* Next, we find a template that matches the given insn,
3974 making sure the overlap of the given operands types is consistent
3975 with the template operand types. */
3977 if (!(t = match_template (mnem_suffix)))
3980 if (sse_check != check_none
3981 && !i.tm.opcode_modifier.noavx
3982 && !i.tm.cpu_flags.bitfield.cpuavx
3983 && (i.tm.cpu_flags.bitfield.cpusse
3984 || i.tm.cpu_flags.bitfield.cpusse2
3985 || i.tm.cpu_flags.bitfield.cpusse3
3986 || i.tm.cpu_flags.bitfield.cpussse3
3987 || i.tm.cpu_flags.bitfield.cpusse4_1
3988 || i.tm.cpu_flags.bitfield.cpusse4_2
3989 || i.tm.cpu_flags.bitfield.cpupclmul
3990 || i.tm.cpu_flags.bitfield.cpuaes
3991 || i.tm.cpu_flags.bitfield.cpugfni))
3993 (sse_check == check_warning
3995 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3998 /* Zap movzx and movsx suffix. The suffix has been set from
3999 "word ptr" or "byte ptr" on the source operand in Intel syntax
4000 or extracted from mnemonic in AT&T syntax. But we'll use
4001 the destination register to choose the suffix for encoding. */
4002 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4004 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4005 there is no suffix, the default will be byte extension. */
4006 if (i.reg_operands != 2
4009 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4014 if (i.tm.opcode_modifier.fwait)
4015 if (!add_prefix (FWAIT_OPCODE))
4018 /* Check if REP prefix is OK. */
4019 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4021 as_bad (_("invalid instruction `%s' after `%s'"),
4022 i.tm.name, i.rep_prefix);
4026 /* Check for lock without a lockable instruction. Destination operand
4027 must be memory unless it is xchg (0x86). */
4028 if (i.prefix[LOCK_PREFIX]
4029 && (!i.tm.opcode_modifier.islockable
4030 || i.mem_operands == 0
4031 || (i.tm.base_opcode != 0x86
4032 && !operand_type_check (i.types[i.operands - 1], anymem))))
4034 as_bad (_("expecting lockable instruction after `lock'"));
4038 /* Check if HLE prefix is OK. */
4039 if (i.hle_prefix && !check_hle ())
4042 /* Check BND prefix. */
4043 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4044 as_bad (_("expecting valid branch instruction after `bnd'"));
4046 /* Check NOTRACK prefix. */
4047 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4048 as_bad (_("expecting indirect branch instruction after `notrack'"));
4050 if (i.tm.cpu_flags.bitfield.cpumpx)
4052 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4053 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4054 else if (flag_code != CODE_16BIT
4055 ? i.prefix[ADDR_PREFIX]
4056 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4057 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4060 /* Insert BND prefix. */
4062 && i.tm.opcode_modifier.bndprefixok
4063 && !i.prefix[BND_PREFIX])
4064 add_prefix (BND_PREFIX_OPCODE);
4066 /* Check string instruction segment overrides. */
4067 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4069 if (!check_string ())
4071 i.disp_operands = 0;
4074 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4075 optimize_encoding ();
4077 if (!process_suffix ())
4080 /* Update operand types. */
4081 for (j = 0; j < i.operands; j++)
4082 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4084 /* Make still unresolved immediate matches conform to size of immediate
4085 given in i.suffix. */
4086 if (!finalize_imm ())
4089 if (i.types[0].bitfield.imm1)
4090 i.imm_operands = 0; /* kludge for shift insns. */
4092 /* We only need to check those implicit registers for instructions
4093 with 3 operands or less. */
4094 if (i.operands <= 3)
4095 for (j = 0; j < i.operands; j++)
4096 if (i.types[j].bitfield.inoutportreg
4097 || i.types[j].bitfield.shiftcount
4098 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4101 /* ImmExt should be processed after SSE2AVX. */
4102 if (!i.tm.opcode_modifier.sse2avx
4103 && i.tm.opcode_modifier.immext)
4106 /* For insns with operands there are more diddles to do to the opcode. */
4109 if (!process_operands ())
4112 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4114 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4115 as_warn (_("translating to `%sp'"), i.tm.name);
4118 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4120 if (flag_code == CODE_16BIT)
4122 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4127 if (i.tm.opcode_modifier.vex)
4128 build_vex_prefix (t);
4130 build_evex_prefix ();
4133 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4134 instructions may define INT_OPCODE as well, so avoid this corner
4135 case for those instructions that use MODRM. */
4136 if (i.tm.base_opcode == INT_OPCODE
4137 && !i.tm.opcode_modifier.modrm
4138 && i.op[0].imms->X_add_number == 3)
4140 i.tm.base_opcode = INT3_OPCODE;
4144 if ((i.tm.opcode_modifier.jump
4145 || i.tm.opcode_modifier.jumpbyte
4146 || i.tm.opcode_modifier.jumpdword)
4147 && i.op[0].disps->X_op == O_constant)
4149 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4150 the absolute address given by the constant. Since ix86 jumps and
4151 calls are pc relative, we need to generate a reloc. */
4152 i.op[0].disps->X_add_symbol = &abs_symbol;
4153 i.op[0].disps->X_op = O_symbol;
4156 if (i.tm.opcode_modifier.rex64)
4159 /* For 8 bit registers we need an empty rex prefix. Also if the
4160 instruction already has a prefix, we need to convert old
4161 registers to new ones. */
4163 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4164 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4165 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4166 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4167 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4168 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4173 i.rex |= REX_OPCODE;
4174 for (x = 0; x < 2; x++)
4176 /* Look for 8 bit operand that uses old registers. */
4177 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4178 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4180 /* In case it is "hi" register, give up. */
4181 if (i.op[x].regs->reg_num > 3)
4182 as_bad (_("can't encode register '%s%s' in an "
4183 "instruction requiring REX prefix."),
4184 register_prefix, i.op[x].regs->reg_name);
4186 /* Otherwise it is equivalent to the extended register.
4187 Since the encoding doesn't change this is merely
4188 cosmetic cleanup for debug output. */
4190 i.op[x].regs = i.op[x].regs + 8;
4195 if (i.rex == 0 && i.rex_encoding)
4197 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4198 that uses legacy register. If it is "hi" register, don't add
4199 the REX_OPCODE byte. */
4201 for (x = 0; x < 2; x++)
4202 if (i.types[x].bitfield.reg
4203 && i.types[x].bitfield.byte
4204 && (i.op[x].regs->reg_flags & RegRex64) == 0
4205 && i.op[x].regs->reg_num > 3)
4207 i.rex_encoding = FALSE;
4216 add_prefix (REX_OPCODE | i.rex);
4218 /* We are ready to output the insn. */
4223 parse_insn (char *line, char *mnemonic)
4226 char *token_start = l;
4229 const insn_template *t;
4235 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4240 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4242 as_bad (_("no such instruction: `%s'"), token_start);
4247 if (!is_space_char (*l)
4248 && *l != END_OF_INSN
4250 || (*l != PREFIX_SEPARATOR
4253 as_bad (_("invalid character %s in mnemonic"),
4254 output_invalid (*l));
4257 if (token_start == l)
4259 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4260 as_bad (_("expecting prefix; got nothing"));
4262 as_bad (_("expecting mnemonic; got nothing"));
4266 /* Look up instruction (or prefix) via hash table. */
4267 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4269 if (*l != END_OF_INSN
4270 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4271 && current_templates
4272 && current_templates->start->opcode_modifier.isprefix)
4274 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4276 as_bad ((flag_code != CODE_64BIT
4277 ? _("`%s' is only supported in 64-bit mode")
4278 : _("`%s' is not supported in 64-bit mode")),
4279 current_templates->start->name);
4282 /* If we are in 16-bit mode, do not allow addr16 or data16.
4283 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4284 if ((current_templates->start->opcode_modifier.size16
4285 || current_templates->start->opcode_modifier.size32)
4286 && flag_code != CODE_64BIT
4287 && (current_templates->start->opcode_modifier.size32
4288 ^ (flag_code == CODE_16BIT)))
4290 as_bad (_("redundant %s prefix"),
4291 current_templates->start->name);
4294 if (current_templates->start->opcode_length == 0)
4296 /* Handle pseudo prefixes. */
4297 switch (current_templates->start->base_opcode)
4301 i.disp_encoding = disp_encoding_8bit;
4305 i.disp_encoding = disp_encoding_32bit;
4309 i.dir_encoding = dir_encoding_load;
4313 i.dir_encoding = dir_encoding_store;
4317 i.vec_encoding = vex_encoding_vex2;
4321 i.vec_encoding = vex_encoding_vex3;
4325 i.vec_encoding = vex_encoding_evex;
4329 i.rex_encoding = TRUE;
4333 i.no_optimize = TRUE;
4341 /* Add prefix, checking for repeated prefixes. */
4342 switch (add_prefix (current_templates->start->base_opcode))
4347 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4348 i.notrack_prefix = current_templates->start->name;
4351 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4352 i.hle_prefix = current_templates->start->name;
4353 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4354 i.bnd_prefix = current_templates->start->name;
4356 i.rep_prefix = current_templates->start->name;
4362 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4369 if (!current_templates)
4371 /* Check if we should swap operand or force 32bit displacement in
4373 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4374 i.dir_encoding = dir_encoding_store;
4375 else if (mnem_p - 3 == dot_p
4378 i.disp_encoding = disp_encoding_8bit;
4379 else if (mnem_p - 4 == dot_p
4383 i.disp_encoding = disp_encoding_32bit;
4388 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4391 if (!current_templates)
4394 /* See if we can get a match by trimming off a suffix. */
4397 case WORD_MNEM_SUFFIX:
4398 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4399 i.suffix = SHORT_MNEM_SUFFIX;
4402 case BYTE_MNEM_SUFFIX:
4403 case QWORD_MNEM_SUFFIX:
4404 i.suffix = mnem_p[-1];
4406 current_templates = (const templates *) hash_find (op_hash,
4409 case SHORT_MNEM_SUFFIX:
4410 case LONG_MNEM_SUFFIX:
4413 i.suffix = mnem_p[-1];
4415 current_templates = (const templates *) hash_find (op_hash,
4424 if (intel_float_operand (mnemonic) == 1)
4425 i.suffix = SHORT_MNEM_SUFFIX;
4427 i.suffix = LONG_MNEM_SUFFIX;
4429 current_templates = (const templates *) hash_find (op_hash,
4434 if (!current_templates)
4436 as_bad (_("no such instruction: `%s'"), token_start);
4441 if (current_templates->start->opcode_modifier.jump
4442 || current_templates->start->opcode_modifier.jumpbyte)
4444 /* Check for a branch hint. We allow ",pt" and ",pn" for
4445 predict taken and predict not taken respectively.
4446 I'm not sure that branch hints actually do anything on loop
4447 and jcxz insns (JumpByte) for current Pentium4 chips. They
4448 may work in the future and it doesn't hurt to accept them
4450 if (l[0] == ',' && l[1] == 'p')
4454 if (!add_prefix (DS_PREFIX_OPCODE))
4458 else if (l[2] == 'n')
4460 if (!add_prefix (CS_PREFIX_OPCODE))
4466 /* Any other comma loses. */
4469 as_bad (_("invalid character %s in mnemonic"),
4470 output_invalid (*l));
4474 /* Check if instruction is supported on specified architecture. */
4476 for (t = current_templates->start; t < current_templates->end; ++t)
4478 supported |= cpu_flags_match (t);
4479 if (supported == CPU_FLAGS_PERFECT_MATCH)
4483 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4485 as_bad (flag_code == CODE_64BIT
4486 ? _("`%s' is not supported in 64-bit mode")
4487 : _("`%s' is only supported in 64-bit mode"),
4488 current_templates->start->name);
4491 if (supported != CPU_FLAGS_PERFECT_MATCH)
4493 as_bad (_("`%s' is not supported on `%s%s'"),
4494 current_templates->start->name,
4495 cpu_arch_name ? cpu_arch_name : default_arch,
4496 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4501 if (!cpu_arch_flags.bitfield.cpui386
4502 && (flag_code != CODE_16BIT))
4504 as_warn (_("use .code16 to ensure correct addressing mode"));
4511 parse_operands (char *l, const char *mnemonic)
4515 /* 1 if operand is pending after ','. */
4516 unsigned int expecting_operand = 0;
4518 /* Non-zero if operand parens not balanced. */
4519 unsigned int paren_not_balanced;
4521 while (*l != END_OF_INSN)
4523 /* Skip optional white space before operand. */
4524 if (is_space_char (*l))
4526 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4528 as_bad (_("invalid character %s before operand %d"),
4529 output_invalid (*l),
4533 token_start = l; /* After white space. */
4534 paren_not_balanced = 0;
4535 while (paren_not_balanced || *l != ',')
4537 if (*l == END_OF_INSN)
4539 if (paren_not_balanced)
4542 as_bad (_("unbalanced parenthesis in operand %d."),
4545 as_bad (_("unbalanced brackets in operand %d."),
4550 break; /* we are done */
4552 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4554 as_bad (_("invalid character %s in operand %d"),
4555 output_invalid (*l),
4562 ++paren_not_balanced;
4564 --paren_not_balanced;
4569 ++paren_not_balanced;
4571 --paren_not_balanced;
4575 if (l != token_start)
4576 { /* Yes, we've read in another operand. */
4577 unsigned int operand_ok;
4578 this_operand = i.operands++;
4579 if (i.operands > MAX_OPERANDS)
4581 as_bad (_("spurious operands; (%d operands/instruction max)"),
4585 i.types[this_operand].bitfield.unspecified = 1;
4586 /* Now parse operand adding info to 'i' as we go along. */
4587 END_STRING_AND_SAVE (l);
4591 i386_intel_operand (token_start,
4592 intel_float_operand (mnemonic));
4594 operand_ok = i386_att_operand (token_start);
4596 RESTORE_END_STRING (l);
4602 if (expecting_operand)
4604 expecting_operand_after_comma:
4605 as_bad (_("expecting operand after ','; got nothing"));
4610 as_bad (_("expecting operand before ','; got nothing"));
4615 /* Now *l must be either ',' or END_OF_INSN. */
4618 if (*++l == END_OF_INSN)
4620 /* Just skip it, if it's \n complain. */
4621 goto expecting_operand_after_comma;
4623 expecting_operand = 1;
4630 swap_2_operands (int xchg1, int xchg2)
4632 union i386_op temp_op;
4633 i386_operand_type temp_type;
4634 enum bfd_reloc_code_real temp_reloc;
4636 temp_type = i.types[xchg2];
4637 i.types[xchg2] = i.types[xchg1];
4638 i.types[xchg1] = temp_type;
4639 temp_op = i.op[xchg2];
4640 i.op[xchg2] = i.op[xchg1];
4641 i.op[xchg1] = temp_op;
4642 temp_reloc = i.reloc[xchg2];
4643 i.reloc[xchg2] = i.reloc[xchg1];
4644 i.reloc[xchg1] = temp_reloc;
4648 if (i.mask->operand == xchg1)
4649 i.mask->operand = xchg2;
4650 else if (i.mask->operand == xchg2)
4651 i.mask->operand = xchg1;
4655 if (i.broadcast->operand == xchg1)
4656 i.broadcast->operand = xchg2;
4657 else if (i.broadcast->operand == xchg2)
4658 i.broadcast->operand = xchg1;
4662 if (i.rounding->operand == xchg1)
4663 i.rounding->operand = xchg2;
4664 else if (i.rounding->operand == xchg2)
4665 i.rounding->operand = xchg1;
4670 swap_operands (void)
4676 swap_2_operands (1, i.operands - 2);
4680 swap_2_operands (0, i.operands - 1);
4686 if (i.mem_operands == 2)
4688 const seg_entry *temp_seg;
4689 temp_seg = i.seg[0];
4690 i.seg[0] = i.seg[1];
4691 i.seg[1] = temp_seg;
4695 /* Try to ensure constant immediates are represented in the smallest
4700 char guess_suffix = 0;
4704 guess_suffix = i.suffix;
4705 else if (i.reg_operands)
4707 /* Figure out a suffix from the last register operand specified.
4708 We can't do this properly yet, ie. excluding InOutPortReg,
4709 but the following works for instructions with immediates.
4710 In any case, we can't set i.suffix yet. */
4711 for (op = i.operands; --op >= 0;)
4712 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4714 guess_suffix = BYTE_MNEM_SUFFIX;
4717 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4719 guess_suffix = WORD_MNEM_SUFFIX;
4722 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4724 guess_suffix = LONG_MNEM_SUFFIX;
4727 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4729 guess_suffix = QWORD_MNEM_SUFFIX;
4733 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4734 guess_suffix = WORD_MNEM_SUFFIX;
4736 for (op = i.operands; --op >= 0;)
4737 if (operand_type_check (i.types[op], imm))
4739 switch (i.op[op].imms->X_op)
4742 /* If a suffix is given, this operand may be shortened. */
4743 switch (guess_suffix)
4745 case LONG_MNEM_SUFFIX:
4746 i.types[op].bitfield.imm32 = 1;
4747 i.types[op].bitfield.imm64 = 1;
4749 case WORD_MNEM_SUFFIX:
4750 i.types[op].bitfield.imm16 = 1;
4751 i.types[op].bitfield.imm32 = 1;
4752 i.types[op].bitfield.imm32s = 1;
4753 i.types[op].bitfield.imm64 = 1;
4755 case BYTE_MNEM_SUFFIX:
4756 i.types[op].bitfield.imm8 = 1;
4757 i.types[op].bitfield.imm8s = 1;
4758 i.types[op].bitfield.imm16 = 1;
4759 i.types[op].bitfield.imm32 = 1;
4760 i.types[op].bitfield.imm32s = 1;
4761 i.types[op].bitfield.imm64 = 1;
4765 /* If this operand is at most 16 bits, convert it
4766 to a signed 16 bit number before trying to see
4767 whether it will fit in an even smaller size.
4768 This allows a 16-bit operand such as $0xffe0 to
4769 be recognised as within Imm8S range. */
4770 if ((i.types[op].bitfield.imm16)
4771 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4773 i.op[op].imms->X_add_number =
4774 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4777 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4778 if ((i.types[op].bitfield.imm32)
4779 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4782 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4783 ^ ((offsetT) 1 << 31))
4784 - ((offsetT) 1 << 31));
4788 = operand_type_or (i.types[op],
4789 smallest_imm_type (i.op[op].imms->X_add_number));
4791 /* We must avoid matching of Imm32 templates when 64bit
4792 only immediate is available. */
4793 if (guess_suffix == QWORD_MNEM_SUFFIX)
4794 i.types[op].bitfield.imm32 = 0;
4801 /* Symbols and expressions. */
4803 /* Convert symbolic operand to proper sizes for matching, but don't
4804 prevent matching a set of insns that only supports sizes other
4805 than those matching the insn suffix. */
4807 i386_operand_type mask, allowed;
4808 const insn_template *t;
4810 operand_type_set (&mask, 0);
4811 operand_type_set (&allowed, 0);
4813 for (t = current_templates->start;
4814 t < current_templates->end;
4816 allowed = operand_type_or (allowed,
4817 t->operand_types[op]);
4818 switch (guess_suffix)
4820 case QWORD_MNEM_SUFFIX:
4821 mask.bitfield.imm64 = 1;
4822 mask.bitfield.imm32s = 1;
4824 case LONG_MNEM_SUFFIX:
4825 mask.bitfield.imm32 = 1;
4827 case WORD_MNEM_SUFFIX:
4828 mask.bitfield.imm16 = 1;
4830 case BYTE_MNEM_SUFFIX:
4831 mask.bitfield.imm8 = 1;
4836 allowed = operand_type_and (mask, allowed);
4837 if (!operand_type_all_zero (&allowed))
4838 i.types[op] = operand_type_and (i.types[op], mask);
4845 /* Try to use the smallest displacement type too. */
4847 optimize_disp (void)
4851 for (op = i.operands; --op >= 0;)
4852 if (operand_type_check (i.types[op], disp))
4854 if (i.op[op].disps->X_op == O_constant)
4856 offsetT op_disp = i.op[op].disps->X_add_number;
4858 if (i.types[op].bitfield.disp16
4859 && (op_disp & ~(offsetT) 0xffff) == 0)
4861 /* If this operand is at most 16 bits, convert
4862 to a signed 16 bit number and don't use 64bit
4864 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4865 i.types[op].bitfield.disp64 = 0;
4868 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4869 if (i.types[op].bitfield.disp32
4870 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4872 /* If this operand is at most 32 bits, convert
4873 to a signed 32 bit number and don't use 64bit
4875 op_disp &= (((offsetT) 2 << 31) - 1);
4876 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4877 i.types[op].bitfield.disp64 = 0;
4880 if (!op_disp && i.types[op].bitfield.baseindex)
4882 i.types[op].bitfield.disp8 = 0;
4883 i.types[op].bitfield.disp16 = 0;
4884 i.types[op].bitfield.disp32 = 0;
4885 i.types[op].bitfield.disp32s = 0;
4886 i.types[op].bitfield.disp64 = 0;
4890 else if (flag_code == CODE_64BIT)
4892 if (fits_in_signed_long (op_disp))
4894 i.types[op].bitfield.disp64 = 0;
4895 i.types[op].bitfield.disp32s = 1;
4897 if (i.prefix[ADDR_PREFIX]
4898 && fits_in_unsigned_long (op_disp))
4899 i.types[op].bitfield.disp32 = 1;
4901 if ((i.types[op].bitfield.disp32
4902 || i.types[op].bitfield.disp32s
4903 || i.types[op].bitfield.disp16)
4904 && fits_in_disp8 (op_disp))
4905 i.types[op].bitfield.disp8 = 1;
4907 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4908 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4910 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4911 i.op[op].disps, 0, i.reloc[op]);
4912 i.types[op].bitfield.disp8 = 0;
4913 i.types[op].bitfield.disp16 = 0;
4914 i.types[op].bitfield.disp32 = 0;
4915 i.types[op].bitfield.disp32s = 0;
4916 i.types[op].bitfield.disp64 = 0;
4919 /* We only support 64bit displacement on constants. */
4920 i.types[op].bitfield.disp64 = 0;
4924 /* Check if operands are valid for the instruction. */
4927 check_VecOperands (const insn_template *t)
4931 /* Without VSIB byte, we can't have a vector register for index. */
4932 if (!t->opcode_modifier.vecsib
4934 && (i.index_reg->reg_type.bitfield.xmmword
4935 || i.index_reg->reg_type.bitfield.ymmword
4936 || i.index_reg->reg_type.bitfield.zmmword))
4938 i.error = unsupported_vector_index_register;
4942 /* Check if default mask is allowed. */
4943 if (t->opcode_modifier.nodefmask
4944 && (!i.mask || i.mask->mask->reg_num == 0))
4946 i.error = no_default_mask;
4950 /* For VSIB byte, we need a vector register for index, and all vector
4951 registers must be distinct. */
4952 if (t->opcode_modifier.vecsib)
4955 || !((t->opcode_modifier.vecsib == VecSIB128
4956 && i.index_reg->reg_type.bitfield.xmmword)
4957 || (t->opcode_modifier.vecsib == VecSIB256
4958 && i.index_reg->reg_type.bitfield.ymmword)
4959 || (t->opcode_modifier.vecsib == VecSIB512
4960 && i.index_reg->reg_type.bitfield.zmmword)))
4962 i.error = invalid_vsib_address;
4966 gas_assert (i.reg_operands == 2 || i.mask);
4967 if (i.reg_operands == 2 && !i.mask)
4969 gas_assert (i.types[0].bitfield.regsimd);
4970 gas_assert (i.types[0].bitfield.xmmword
4971 || i.types[0].bitfield.ymmword);
4972 gas_assert (i.types[2].bitfield.regsimd);
4973 gas_assert (i.types[2].bitfield.xmmword
4974 || i.types[2].bitfield.ymmword);
4975 if (operand_check == check_none)
4977 if (register_number (i.op[0].regs)
4978 != register_number (i.index_reg)
4979 && register_number (i.op[2].regs)
4980 != register_number (i.index_reg)
4981 && register_number (i.op[0].regs)
4982 != register_number (i.op[2].regs))
4984 if (operand_check == check_error)
4986 i.error = invalid_vector_register_set;
4989 as_warn (_("mask, index, and destination registers should be distinct"));
4991 else if (i.reg_operands == 1 && i.mask)
4993 if (i.types[1].bitfield.regsimd
4994 && (i.types[1].bitfield.xmmword
4995 || i.types[1].bitfield.ymmword
4996 || i.types[1].bitfield.zmmword)
4997 && (register_number (i.op[1].regs)
4998 == register_number (i.index_reg)))
5000 if (operand_check == check_error)
5002 i.error = invalid_vector_register_set;
5005 if (operand_check != check_none)
5006 as_warn (_("index and destination registers should be distinct"));
5011 /* Check if broadcast is supported by the instruction and is applied
5012 to the memory operand. */
5015 int broadcasted_opnd_size;
5017 /* Check if specified broadcast is supported in this instruction,
5018 and it's applied to memory operand of DWORD or QWORD type,
5019 depending on VecESize. */
5020 if (i.broadcast->type != t->opcode_modifier.broadcast
5021 || !i.types[i.broadcast->operand].bitfield.mem
5022 || (t->opcode_modifier.vecesize == 0
5023 && !i.types[i.broadcast->operand].bitfield.dword
5024 && !i.types[i.broadcast->operand].bitfield.unspecified)
5025 || (t->opcode_modifier.vecesize == 1
5026 && !i.types[i.broadcast->operand].bitfield.qword
5027 && !i.types[i.broadcast->operand].bitfield.unspecified))
5030 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5031 if (i.broadcast->type == BROADCAST_1TO16)
5032 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5033 else if (i.broadcast->type == BROADCAST_1TO8)
5034 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5035 else if (i.broadcast->type == BROADCAST_1TO4)
5036 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5037 else if (i.broadcast->type == BROADCAST_1TO2)
5038 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5042 if ((broadcasted_opnd_size == 256
5043 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5044 || (broadcasted_opnd_size == 512
5045 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5048 i.error = unsupported_broadcast;
5052 /* If broadcast is supported in this instruction, we need to check if
5053 operand of one-element size isn't specified without broadcast. */
5054 else if (t->opcode_modifier.broadcast && i.mem_operands)
5056 /* Find memory operand. */
5057 for (op = 0; op < i.operands; op++)
5058 if (operand_type_check (i.types[op], anymem))
5060 gas_assert (op < i.operands);
5061 /* Check size of the memory operand. */
5062 if ((t->opcode_modifier.vecesize == 0
5063 && i.types[op].bitfield.dword)
5064 || (t->opcode_modifier.vecesize == 1
5065 && i.types[op].bitfield.qword))
5067 i.error = broadcast_needed;
5072 /* Check if requested masking is supported. */
5074 && (!t->opcode_modifier.masking
5076 && t->opcode_modifier.masking == MERGING_MASKING)))
5078 i.error = unsupported_masking;
5082 /* Check if masking is applied to dest operand. */
5083 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5085 i.error = mask_not_on_destination;
5092 if ((i.rounding->type != saeonly
5093 && !t->opcode_modifier.staticrounding)
5094 || (i.rounding->type == saeonly
5095 && (t->opcode_modifier.staticrounding
5096 || !t->opcode_modifier.sae)))
5098 i.error = unsupported_rc_sae;
5101 /* If the instruction has several immediate operands and one of
5102 them is rounding, the rounding operand should be the last
5103 immediate operand. */
5104 if (i.imm_operands > 1
5105 && i.rounding->operand != (int) (i.imm_operands - 1))
5107 i.error = rc_sae_operand_not_last_imm;
5112 /* Check vector Disp8 operand. */
5113 if (t->opcode_modifier.disp8memshift
5114 && i.disp_encoding != disp_encoding_32bit)
5117 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5119 i.memshift = t->opcode_modifier.disp8memshift;
5121 for (op = 0; op < i.operands; op++)
5122 if (operand_type_check (i.types[op], disp)
5123 && i.op[op].disps->X_op == O_constant)
5125 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5127 i.types[op].bitfield.disp8 = 1;
5130 i.types[op].bitfield.disp8 = 0;
5139 /* Check if operands are valid for the instruction. Update VEX
5143 VEX_check_operands (const insn_template *t)
5145 if (i.vec_encoding == vex_encoding_evex)
5147 /* This instruction must be encoded with EVEX prefix. */
5148 if (!t->opcode_modifier.evex)
5150 i.error = unsupported;
5156 if (!t->opcode_modifier.vex)
5158 /* This instruction template doesn't have VEX prefix. */
5159 if (i.vec_encoding != vex_encoding_default)
5161 i.error = unsupported;
5167 /* Only check VEX_Imm4, which must be the first operand. */
5168 if (t->operand_types[0].bitfield.vec_imm4)
5170 if (i.op[0].imms->X_op != O_constant
5171 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5177 /* Turn off Imm8 so that update_imm won't complain. */
5178 i.types[0] = vec_imm4;
5184 static const insn_template *
5185 match_template (char mnem_suffix)
5187 /* Points to template once we've found it. */
5188 const insn_template *t;
5189 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5190 i386_operand_type overlap4;
5191 unsigned int found_reverse_match;
5192 i386_opcode_modifier suffix_check, mnemsuf_check;
5193 i386_operand_type operand_types [MAX_OPERANDS];
5194 int addr_prefix_disp;
5196 unsigned int found_cpu_match;
5197 unsigned int check_register;
5198 enum i386_error specific_error = 0;
5200 #if MAX_OPERANDS != 5
5201 # error "MAX_OPERANDS must be 5."
5204 found_reverse_match = 0;
5205 addr_prefix_disp = -1;
5207 memset (&suffix_check, 0, sizeof (suffix_check));
5208 if (i.suffix == BYTE_MNEM_SUFFIX)
5209 suffix_check.no_bsuf = 1;
5210 else if (i.suffix == WORD_MNEM_SUFFIX)
5211 suffix_check.no_wsuf = 1;
5212 else if (i.suffix == SHORT_MNEM_SUFFIX)
5213 suffix_check.no_ssuf = 1;
5214 else if (i.suffix == LONG_MNEM_SUFFIX)
5215 suffix_check.no_lsuf = 1;
5216 else if (i.suffix == QWORD_MNEM_SUFFIX)
5217 suffix_check.no_qsuf = 1;
5218 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5219 suffix_check.no_ldsuf = 1;
5221 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5224 switch (mnem_suffix)
5226 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5227 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5228 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5229 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5230 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5234 /* Must have right number of operands. */
5235 i.error = number_of_operands_mismatch;
5237 for (t = current_templates->start; t < current_templates->end; t++)
5239 addr_prefix_disp = -1;
5241 if (i.operands != t->operands)
5244 /* Check processor support. */
5245 i.error = unsupported;
5246 found_cpu_match = (cpu_flags_match (t)
5247 == CPU_FLAGS_PERFECT_MATCH);
5248 if (!found_cpu_match)
5251 /* Check old gcc support. */
5252 i.error = old_gcc_only;
5253 if (!old_gcc && t->opcode_modifier.oldgcc)
5256 /* Check AT&T mnemonic. */
5257 i.error = unsupported_with_intel_mnemonic;
5258 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5261 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5262 i.error = unsupported_syntax;
5263 if ((intel_syntax && t->opcode_modifier.attsyntax)
5264 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5265 || (intel64 && t->opcode_modifier.amd64)
5266 || (!intel64 && t->opcode_modifier.intel64))
5269 /* Check the suffix, except for some instructions in intel mode. */
5270 i.error = invalid_instruction_suffix;
5271 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5272 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5273 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5274 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5275 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5276 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5277 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5279 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5280 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5281 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5282 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5283 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5284 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5285 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5288 if (!operand_size_match (t))
5291 for (j = 0; j < MAX_OPERANDS; j++)
5292 operand_types[j] = t->operand_types[j];
5294 /* In general, don't allow 64-bit operands in 32-bit mode. */
5295 if (i.suffix == QWORD_MNEM_SUFFIX
5296 && flag_code != CODE_64BIT
5298 ? (!t->opcode_modifier.ignoresize
5299 && !intel_float_operand (t->name))
5300 : intel_float_operand (t->name) != 2)
5301 && ((!operand_types[0].bitfield.regmmx
5302 && !operand_types[0].bitfield.regsimd)
5303 || (!operand_types[t->operands > 1].bitfield.regmmx
5304 && !operand_types[t->operands > 1].bitfield.regsimd))
5305 && (t->base_opcode != 0x0fc7
5306 || t->extension_opcode != 1 /* cmpxchg8b */))
5309 /* In general, don't allow 32-bit operands on pre-386. */
5310 else if (i.suffix == LONG_MNEM_SUFFIX
5311 && !cpu_arch_flags.bitfield.cpui386
5313 ? (!t->opcode_modifier.ignoresize
5314 && !intel_float_operand (t->name))
5315 : intel_float_operand (t->name) != 2)
5316 && ((!operand_types[0].bitfield.regmmx
5317 && !operand_types[0].bitfield.regsimd)
5318 || (!operand_types[t->operands > 1].bitfield.regmmx
5319 && !operand_types[t->operands > 1].bitfield.regsimd)))
5322 /* Do not verify operands when there are none. */
5326 /* We've found a match; break out of loop. */
5330 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5331 into Disp32/Disp16/Disp32 operand. */
5332 if (i.prefix[ADDR_PREFIX] != 0)
5334 /* There should be only one Disp operand. */
5338 for (j = 0; j < MAX_OPERANDS; j++)
5340 if (operand_types[j].bitfield.disp16)
5342 addr_prefix_disp = j;
5343 operand_types[j].bitfield.disp32 = 1;
5344 operand_types[j].bitfield.disp16 = 0;
5350 for (j = 0; j < MAX_OPERANDS; j++)
5352 if (operand_types[j].bitfield.disp32)
5354 addr_prefix_disp = j;
5355 operand_types[j].bitfield.disp32 = 0;
5356 operand_types[j].bitfield.disp16 = 1;
5362 for (j = 0; j < MAX_OPERANDS; j++)
5364 if (operand_types[j].bitfield.disp64)
5366 addr_prefix_disp = j;
5367 operand_types[j].bitfield.disp64 = 0;
5368 operand_types[j].bitfield.disp32 = 1;
5376 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5377 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5380 /* We check register size if needed. */
5381 check_register = t->opcode_modifier.checkregsize;
5382 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5383 switch (t->operands)
5386 if (!operand_type_match (overlap0, i.types[0]))
5390 /* xchg %eax, %eax is a special case. It is an alias for nop
5391 only in 32bit mode and we can use opcode 0x90. In 64bit
5392 mode, we can't use 0x90 for xchg %eax, %eax since it should
5393 zero-extend %eax to %rax. */
5394 if (flag_code == CODE_64BIT
5395 && t->base_opcode == 0x90
5396 && operand_type_equal (&i.types [0], &acc32)
5397 && operand_type_equal (&i.types [1], &acc32))
5399 /* If we want store form, we reverse direction of operands. */
5400 if (i.dir_encoding == dir_encoding_store
5401 && t->opcode_modifier.d)
5406 /* If we want store form, we skip the current load. */
5407 if (i.dir_encoding == dir_encoding_store
5408 && i.mem_operands == 0
5409 && t->opcode_modifier.load)
5414 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5415 if (!operand_type_match (overlap0, i.types[0])
5416 || !operand_type_match (overlap1, i.types[1])
5418 && !operand_type_register_match (i.types[0],
5423 /* Check if other direction is valid ... */
5424 if (!t->opcode_modifier.d)
5428 /* Try reversing direction of operands. */
5429 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5430 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5431 if (!operand_type_match (overlap0, i.types[0])
5432 || !operand_type_match (overlap1, i.types[1])
5434 && !operand_type_register_match (i.types[0],
5439 /* Does not match either direction. */
5442 /* found_reverse_match holds which of D or FloatR
5444 if (!t->opcode_modifier.d)
5445 found_reverse_match = 0;
5446 else if (operand_types[0].bitfield.tbyte)
5447 found_reverse_match = Opcode_FloatD;
5449 found_reverse_match = Opcode_D;
5450 if (t->opcode_modifier.floatr)
5451 found_reverse_match |= Opcode_FloatR;
5455 /* Found a forward 2 operand match here. */
5456 switch (t->operands)
5459 overlap4 = operand_type_and (i.types[4],
5463 overlap3 = operand_type_and (i.types[3],
5467 overlap2 = operand_type_and (i.types[2],
5472 switch (t->operands)
5475 if (!operand_type_match (overlap4, i.types[4])
5476 || !operand_type_register_match (i.types[3],
5483 if (!operand_type_match (overlap3, i.types[3])
5485 && !operand_type_register_match (i.types[2],
5492 /* Here we make use of the fact that there are no
5493 reverse match 3 operand instructions, and all 3
5494 operand instructions only need to be checked for
5495 register consistency between operands 2 and 3. */
5496 if (!operand_type_match (overlap2, i.types[2])
5498 && !operand_type_register_match (i.types[1],
5506 /* Found either forward/reverse 2, 3 or 4 operand match here:
5507 slip through to break. */
5509 if (!found_cpu_match)
5511 found_reverse_match = 0;
5515 /* Check if vector and VEX operands are valid. */
5516 if (check_VecOperands (t) || VEX_check_operands (t))
5518 specific_error = i.error;
5522 /* We've found a match; break out of loop. */
5526 if (t == current_templates->end)
5528 /* We found no match. */
5529 const char *err_msg;
5530 switch (specific_error ? specific_error : i.error)
5534 case operand_size_mismatch:
5535 err_msg = _("operand size mismatch");
5537 case operand_type_mismatch:
5538 err_msg = _("operand type mismatch");
5540 case register_type_mismatch:
5541 err_msg = _("register type mismatch");
5543 case number_of_operands_mismatch:
5544 err_msg = _("number of operands mismatch");
5546 case invalid_instruction_suffix:
5547 err_msg = _("invalid instruction suffix");
5550 err_msg = _("constant doesn't fit in 4 bits");
5553 err_msg = _("only supported with old gcc");
5555 case unsupported_with_intel_mnemonic:
5556 err_msg = _("unsupported with Intel mnemonic");
5558 case unsupported_syntax:
5559 err_msg = _("unsupported syntax");
5562 as_bad (_("unsupported instruction `%s'"),
5563 current_templates->start->name);
5565 case invalid_vsib_address:
5566 err_msg = _("invalid VSIB address");
5568 case invalid_vector_register_set:
5569 err_msg = _("mask, index, and destination registers must be distinct");
5571 case unsupported_vector_index_register:
5572 err_msg = _("unsupported vector index register");
5574 case unsupported_broadcast:
5575 err_msg = _("unsupported broadcast");
5577 case broadcast_not_on_src_operand:
5578 err_msg = _("broadcast not on source memory operand");
5580 case broadcast_needed:
5581 err_msg = _("broadcast is needed for operand of such type");
5583 case unsupported_masking:
5584 err_msg = _("unsupported masking");
5586 case mask_not_on_destination:
5587 err_msg = _("mask not on destination operand");
5589 case no_default_mask:
5590 err_msg = _("default mask isn't allowed");
5592 case unsupported_rc_sae:
5593 err_msg = _("unsupported static rounding/sae");
5595 case rc_sae_operand_not_last_imm:
5597 err_msg = _("RC/SAE operand must precede immediate operands");
5599 err_msg = _("RC/SAE operand must follow immediate operands");
5601 case invalid_register_operand:
5602 err_msg = _("invalid register operand");
5605 as_bad (_("%s for `%s'"), err_msg,
5606 current_templates->start->name);
5610 if (!quiet_warnings)
5613 && (i.types[0].bitfield.jumpabsolute
5614 != operand_types[0].bitfield.jumpabsolute))
5616 as_warn (_("indirect %s without `*'"), t->name);
5619 if (t->opcode_modifier.isprefix
5620 && t->opcode_modifier.ignoresize)
5622 /* Warn them that a data or address size prefix doesn't
5623 affect assembly of the next line of code. */
5624 as_warn (_("stand-alone `%s' prefix"), t->name);
5628 /* Copy the template we found. */
5631 if (addr_prefix_disp != -1)
5632 i.tm.operand_types[addr_prefix_disp]
5633 = operand_types[addr_prefix_disp];
5635 if (found_reverse_match)
5637 /* If we found a reverse match we must alter the opcode
5638 direction bit. found_reverse_match holds bits to change
5639 (different for int & float insns). */
5641 i.tm.base_opcode ^= found_reverse_match;
5643 i.tm.operand_types[0] = operand_types[1];
5644 i.tm.operand_types[1] = operand_types[0];
5653 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5654 if (i.tm.operand_types[mem_op].bitfield.esseg)
5656 if (i.seg[0] != NULL && i.seg[0] != &es)
5658 as_bad (_("`%s' operand %d must use `%ses' segment"),
5664 /* There's only ever one segment override allowed per instruction.
5665 This instruction possibly has a legal segment override on the
5666 second operand, so copy the segment to where non-string
5667 instructions store it, allowing common code. */
5668 i.seg[0] = i.seg[1];
5670 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5672 if (i.seg[1] != NULL && i.seg[1] != &es)
5674 as_bad (_("`%s' operand %d must use `%ses' segment"),
5685 process_suffix (void)
5687 /* If matched instruction specifies an explicit instruction mnemonic
5689 if (i.tm.opcode_modifier.size16)
5690 i.suffix = WORD_MNEM_SUFFIX;
5691 else if (i.tm.opcode_modifier.size32)
5692 i.suffix = LONG_MNEM_SUFFIX;
5693 else if (i.tm.opcode_modifier.size64)
5694 i.suffix = QWORD_MNEM_SUFFIX;
5695 else if (i.reg_operands)
5697 /* If there's no instruction mnemonic suffix we try to invent one
5698 based on register operands. */
5701 /* We take i.suffix from the last register operand specified,
5702 Destination register type is more significant than source
5703 register type. crc32 in SSE4.2 prefers source register
5705 if (i.tm.base_opcode == 0xf20f38f1)
5707 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5708 i.suffix = WORD_MNEM_SUFFIX;
5709 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5710 i.suffix = LONG_MNEM_SUFFIX;
5711 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5712 i.suffix = QWORD_MNEM_SUFFIX;
5714 else if (i.tm.base_opcode == 0xf20f38f0)
5716 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5717 i.suffix = BYTE_MNEM_SUFFIX;
5724 if (i.tm.base_opcode == 0xf20f38f1
5725 || i.tm.base_opcode == 0xf20f38f0)
5727 /* We have to know the operand size for crc32. */
5728 as_bad (_("ambiguous memory operand size for `%s`"),
5733 for (op = i.operands; --op >= 0;)
5734 if (!i.tm.operand_types[op].bitfield.inoutportreg
5735 && !i.tm.operand_types[op].bitfield.shiftcount)
5737 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5739 i.suffix = BYTE_MNEM_SUFFIX;
5742 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5744 i.suffix = WORD_MNEM_SUFFIX;
5747 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5749 i.suffix = LONG_MNEM_SUFFIX;
5752 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5754 i.suffix = QWORD_MNEM_SUFFIX;
5760 else if (i.suffix == BYTE_MNEM_SUFFIX)
5763 && i.tm.opcode_modifier.ignoresize
5764 && i.tm.opcode_modifier.no_bsuf)
5766 else if (!check_byte_reg ())
5769 else if (i.suffix == LONG_MNEM_SUFFIX)
5772 && i.tm.opcode_modifier.ignoresize
5773 && i.tm.opcode_modifier.no_lsuf)
5775 else if (!check_long_reg ())
5778 else if (i.suffix == QWORD_MNEM_SUFFIX)
5781 && i.tm.opcode_modifier.ignoresize
5782 && i.tm.opcode_modifier.no_qsuf)
5784 else if (!check_qword_reg ())
5787 else if (i.suffix == WORD_MNEM_SUFFIX)
5790 && i.tm.opcode_modifier.ignoresize
5791 && i.tm.opcode_modifier.no_wsuf)
5793 else if (!check_word_reg ())
5796 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5797 || i.suffix == YMMWORD_MNEM_SUFFIX
5798 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5800 /* Skip if the instruction has x/y/z suffix. match_template
5801 should check if it is a valid suffix. */
5803 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5804 /* Do nothing if the instruction is going to ignore the prefix. */
5809 else if (i.tm.opcode_modifier.defaultsize
5811 /* exclude fldenv/frstor/fsave/fstenv */
5812 && i.tm.opcode_modifier.no_ssuf)
5814 i.suffix = stackop_size;
5816 else if (intel_syntax
5818 && (i.tm.operand_types[0].bitfield.jumpabsolute
5819 || i.tm.opcode_modifier.jumpbyte
5820 || i.tm.opcode_modifier.jumpintersegment
5821 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5822 && i.tm.extension_opcode <= 3)))
5827 if (!i.tm.opcode_modifier.no_qsuf)
5829 i.suffix = QWORD_MNEM_SUFFIX;
5834 if (!i.tm.opcode_modifier.no_lsuf)
5835 i.suffix = LONG_MNEM_SUFFIX;
5838 if (!i.tm.opcode_modifier.no_wsuf)
5839 i.suffix = WORD_MNEM_SUFFIX;
5848 if (i.tm.opcode_modifier.w)
5850 as_bad (_("no instruction mnemonic suffix given and "
5851 "no register operands; can't size instruction"));
5857 unsigned int suffixes;
5859 suffixes = !i.tm.opcode_modifier.no_bsuf;
5860 if (!i.tm.opcode_modifier.no_wsuf)
5862 if (!i.tm.opcode_modifier.no_lsuf)
5864 if (!i.tm.opcode_modifier.no_ldsuf)
5866 if (!i.tm.opcode_modifier.no_ssuf)
5868 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5871 /* There are more than suffix matches. */
5872 if (i.tm.opcode_modifier.w
5873 || ((suffixes & (suffixes - 1))
5874 && !i.tm.opcode_modifier.defaultsize
5875 && !i.tm.opcode_modifier.ignoresize))
5877 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5883 /* Change the opcode based on the operand size given by i.suffix;
5884 We don't need to change things for byte insns. */
5887 && i.suffix != BYTE_MNEM_SUFFIX
5888 && i.suffix != XMMWORD_MNEM_SUFFIX
5889 && i.suffix != YMMWORD_MNEM_SUFFIX
5890 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5892 /* It's not a byte, select word/dword operation. */
5893 if (i.tm.opcode_modifier.w)
5895 if (i.tm.opcode_modifier.shortform)
5896 i.tm.base_opcode |= 8;
5898 i.tm.base_opcode |= 1;
5901 /* Now select between word & dword operations via the operand
5902 size prefix, except for instructions that will ignore this
5904 if (i.tm.opcode_modifier.addrprefixop0)
5906 /* The address size override prefix changes the size of the
5908 if ((flag_code == CODE_32BIT
5909 && i.op->regs[0].reg_type.bitfield.word)
5910 || (flag_code != CODE_32BIT
5911 && i.op->regs[0].reg_type.bitfield.dword))
5912 if (!add_prefix (ADDR_PREFIX_OPCODE))
5915 else if (i.suffix != QWORD_MNEM_SUFFIX
5916 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5917 && !i.tm.opcode_modifier.ignoresize
5918 && !i.tm.opcode_modifier.floatmf
5919 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5920 || (flag_code == CODE_64BIT
5921 && i.tm.opcode_modifier.jumpbyte)))
5923 unsigned int prefix = DATA_PREFIX_OPCODE;
5925 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5926 prefix = ADDR_PREFIX_OPCODE;
5928 if (!add_prefix (prefix))
5932 /* Set mode64 for an operand. */
5933 if (i.suffix == QWORD_MNEM_SUFFIX
5934 && flag_code == CODE_64BIT
5935 && !i.tm.opcode_modifier.norex64)
5937 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5938 need rex64. cmpxchg8b is also a special case. */
5939 if (! (i.operands == 2
5940 && i.tm.base_opcode == 0x90
5941 && i.tm.extension_opcode == None
5942 && operand_type_equal (&i.types [0], &acc64)
5943 && operand_type_equal (&i.types [1], &acc64))
5944 && ! (i.operands == 1
5945 && i.tm.base_opcode == 0xfc7
5946 && i.tm.extension_opcode == 1
5947 && !operand_type_check (i.types [0], reg)
5948 && operand_type_check (i.types [0], anymem)))
5952 /* Size floating point instruction. */
5953 if (i.suffix == LONG_MNEM_SUFFIX)
5954 if (i.tm.opcode_modifier.floatmf)
5955 i.tm.base_opcode ^= 4;
5962 check_byte_reg (void)
5966 for (op = i.operands; --op >= 0;)
5968 /* Skip non-register operands. */
5969 if (!i.types[op].bitfield.reg)
5972 /* If this is an eight bit register, it's OK. If it's the 16 or
5973 32 bit version of an eight bit register, we will just use the
5974 low portion, and that's OK too. */
5975 if (i.types[op].bitfield.byte)
5978 /* I/O port address operands are OK too. */
5979 if (i.tm.operand_types[op].bitfield.inoutportreg)
5982 /* crc32 doesn't generate this warning. */
5983 if (i.tm.base_opcode == 0xf20f38f0)
5986 if ((i.types[op].bitfield.word
5987 || i.types[op].bitfield.dword
5988 || i.types[op].bitfield.qword)
5989 && i.op[op].regs->reg_num < 4
5990 /* Prohibit these changes in 64bit mode, since the lowering
5991 would be more complicated. */
5992 && flag_code != CODE_64BIT)
5994 #if REGISTER_WARNINGS
5995 if (!quiet_warnings)
5996 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5998 (i.op[op].regs + (i.types[op].bitfield.word
5999 ? REGNAM_AL - REGNAM_AX
6000 : REGNAM_AL - REGNAM_EAX))->reg_name,
6002 i.op[op].regs->reg_name,
6007 /* Any other register is bad. */
6008 if (i.types[op].bitfield.reg
6009 || i.types[op].bitfield.regmmx
6010 || i.types[op].bitfield.regsimd
6011 || i.types[op].bitfield.sreg2
6012 || i.types[op].bitfield.sreg3
6013 || i.types[op].bitfield.control
6014 || i.types[op].bitfield.debug
6015 || i.types[op].bitfield.test)
6017 as_bad (_("`%s%s' not allowed with `%s%c'"),
6019 i.op[op].regs->reg_name,
6029 check_long_reg (void)
6033 for (op = i.operands; --op >= 0;)
6034 /* Skip non-register operands. */
6035 if (!i.types[op].bitfield.reg)
6037 /* Reject eight bit registers, except where the template requires
6038 them. (eg. movzb) */
6039 else if (i.types[op].bitfield.byte
6040 && (i.tm.operand_types[op].bitfield.reg
6041 || i.tm.operand_types[op].bitfield.acc)
6042 && (i.tm.operand_types[op].bitfield.word
6043 || i.tm.operand_types[op].bitfield.dword))
6045 as_bad (_("`%s%s' not allowed with `%s%c'"),
6047 i.op[op].regs->reg_name,
6052 /* Warn if the e prefix on a general reg is missing. */
6053 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6054 && i.types[op].bitfield.word
6055 && (i.tm.operand_types[op].bitfield.reg
6056 || i.tm.operand_types[op].bitfield.acc)
6057 && i.tm.operand_types[op].bitfield.dword)
6059 /* Prohibit these changes in the 64bit mode, since the
6060 lowering is more complicated. */
6061 if (flag_code == CODE_64BIT)
6063 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6064 register_prefix, i.op[op].regs->reg_name,
6068 #if REGISTER_WARNINGS
6069 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6071 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6072 register_prefix, i.op[op].regs->reg_name, i.suffix);
6075 /* Warn if the r prefix on a general reg is present. */
6076 else if (i.types[op].bitfield.qword
6077 && (i.tm.operand_types[op].bitfield.reg
6078 || i.tm.operand_types[op].bitfield.acc)
6079 && i.tm.operand_types[op].bitfield.dword)
6082 && i.tm.opcode_modifier.toqword
6083 && !i.types[0].bitfield.regsimd)
6085 /* Convert to QWORD. We want REX byte. */
6086 i.suffix = QWORD_MNEM_SUFFIX;
6090 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6091 register_prefix, i.op[op].regs->reg_name,
6100 check_qword_reg (void)
6104 for (op = i.operands; --op >= 0; )
6105 /* Skip non-register operands. */
6106 if (!i.types[op].bitfield.reg)
6108 /* Reject eight bit registers, except where the template requires
6109 them. (eg. movzb) */
6110 else if (i.types[op].bitfield.byte
6111 && (i.tm.operand_types[op].bitfield.reg
6112 || i.tm.operand_types[op].bitfield.acc)
6113 && (i.tm.operand_types[op].bitfield.word
6114 || i.tm.operand_types[op].bitfield.dword))
6116 as_bad (_("`%s%s' not allowed with `%s%c'"),
6118 i.op[op].regs->reg_name,
6123 /* Warn if the r prefix on a general reg is missing. */
6124 else if ((i.types[op].bitfield.word
6125 || i.types[op].bitfield.dword)
6126 && (i.tm.operand_types[op].bitfield.reg
6127 || i.tm.operand_types[op].bitfield.acc)
6128 && i.tm.operand_types[op].bitfield.qword)
6130 /* Prohibit these changes in the 64bit mode, since the
6131 lowering is more complicated. */
6133 && i.tm.opcode_modifier.todword
6134 && !i.types[0].bitfield.regsimd)
6136 /* Convert to DWORD. We don't want REX byte. */
6137 i.suffix = LONG_MNEM_SUFFIX;
6141 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6142 register_prefix, i.op[op].regs->reg_name,
6151 check_word_reg (void)
6154 for (op = i.operands; --op >= 0;)
6155 /* Skip non-register operands. */
6156 if (!i.types[op].bitfield.reg)
6158 /* Reject eight bit registers, except where the template requires
6159 them. (eg. movzb) */
6160 else if (i.types[op].bitfield.byte
6161 && (i.tm.operand_types[op].bitfield.reg
6162 || i.tm.operand_types[op].bitfield.acc)
6163 && (i.tm.operand_types[op].bitfield.word
6164 || i.tm.operand_types[op].bitfield.dword))
6166 as_bad (_("`%s%s' not allowed with `%s%c'"),
6168 i.op[op].regs->reg_name,
6173 /* Warn if the e or r prefix on a general reg is present. */
6174 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6175 && (i.types[op].bitfield.dword
6176 || i.types[op].bitfield.qword)
6177 && (i.tm.operand_types[op].bitfield.reg
6178 || i.tm.operand_types[op].bitfield.acc)
6179 && i.tm.operand_types[op].bitfield.word)
6181 /* Prohibit these changes in the 64bit mode, since the
6182 lowering is more complicated. */
6183 if (flag_code == CODE_64BIT)
6185 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6186 register_prefix, i.op[op].regs->reg_name,
6190 #if REGISTER_WARNINGS
6191 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6193 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6194 register_prefix, i.op[op].regs->reg_name, i.suffix);
6201 update_imm (unsigned int j)
6203 i386_operand_type overlap = i.types[j];
6204 if ((overlap.bitfield.imm8
6205 || overlap.bitfield.imm8s
6206 || overlap.bitfield.imm16
6207 || overlap.bitfield.imm32
6208 || overlap.bitfield.imm32s
6209 || overlap.bitfield.imm64)
6210 && !operand_type_equal (&overlap, &imm8)
6211 && !operand_type_equal (&overlap, &imm8s)
6212 && !operand_type_equal (&overlap, &imm16)
6213 && !operand_type_equal (&overlap, &imm32)
6214 && !operand_type_equal (&overlap, &imm32s)
6215 && !operand_type_equal (&overlap, &imm64))
6219 i386_operand_type temp;
6221 operand_type_set (&temp, 0);
6222 if (i.suffix == BYTE_MNEM_SUFFIX)
6224 temp.bitfield.imm8 = overlap.bitfield.imm8;
6225 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6227 else if (i.suffix == WORD_MNEM_SUFFIX)
6228 temp.bitfield.imm16 = overlap.bitfield.imm16;
6229 else if (i.suffix == QWORD_MNEM_SUFFIX)
6231 temp.bitfield.imm64 = overlap.bitfield.imm64;
6232 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6235 temp.bitfield.imm32 = overlap.bitfield.imm32;
6238 else if (operand_type_equal (&overlap, &imm16_32_32s)
6239 || operand_type_equal (&overlap, &imm16_32)
6240 || operand_type_equal (&overlap, &imm16_32s))
6242 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6247 if (!operand_type_equal (&overlap, &imm8)
6248 && !operand_type_equal (&overlap, &imm8s)
6249 && !operand_type_equal (&overlap, &imm16)
6250 && !operand_type_equal (&overlap, &imm32)
6251 && !operand_type_equal (&overlap, &imm32s)
6252 && !operand_type_equal (&overlap, &imm64))
6254 as_bad (_("no instruction mnemonic suffix given; "
6255 "can't determine immediate size"));
6259 i.types[j] = overlap;
6269 /* Update the first 2 immediate operands. */
6270 n = i.operands > 2 ? 2 : i.operands;
6273 for (j = 0; j < n; j++)
6274 if (update_imm (j) == 0)
6277 /* The 3rd operand can't be immediate operand. */
6278 gas_assert (operand_type_check (i.types[2], imm) == 0);
6285 process_operands (void)
6287 /* Default segment register this instruction will use for memory
6288 accesses. 0 means unknown. This is only for optimizing out
6289 unnecessary segment overrides. */
6290 const seg_entry *default_seg = 0;
6292 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6294 unsigned int dupl = i.operands;
6295 unsigned int dest = dupl - 1;
6298 /* The destination must be an xmm register. */
6299 gas_assert (i.reg_operands
6300 && MAX_OPERANDS > dupl
6301 && operand_type_equal (&i.types[dest], ®xmm));
6303 if (i.tm.operand_types[0].bitfield.acc
6304 && i.tm.operand_types[0].bitfield.xmmword)
6306 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6308 /* Keep xmm0 for instructions with VEX prefix and 3
6310 i.tm.operand_types[0].bitfield.acc = 0;
6311 i.tm.operand_types[0].bitfield.regsimd = 1;
6316 /* We remove the first xmm0 and keep the number of
6317 operands unchanged, which in fact duplicates the
6319 for (j = 1; j < i.operands; j++)
6321 i.op[j - 1] = i.op[j];
6322 i.types[j - 1] = i.types[j];
6323 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6327 else if (i.tm.opcode_modifier.implicit1stxmm0)
6329 gas_assert ((MAX_OPERANDS - 1) > dupl
6330 && (i.tm.opcode_modifier.vexsources
6333 /* Add the implicit xmm0 for instructions with VEX prefix
6335 for (j = i.operands; j > 0; j--)
6337 i.op[j] = i.op[j - 1];
6338 i.types[j] = i.types[j - 1];
6339 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6342 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6343 i.types[0] = regxmm;
6344 i.tm.operand_types[0] = regxmm;
6347 i.reg_operands += 2;
6352 i.op[dupl] = i.op[dest];
6353 i.types[dupl] = i.types[dest];
6354 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6363 i.op[dupl] = i.op[dest];
6364 i.types[dupl] = i.types[dest];
6365 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6368 if (i.tm.opcode_modifier.immext)
6371 else if (i.tm.operand_types[0].bitfield.acc
6372 && i.tm.operand_types[0].bitfield.xmmword)
6376 for (j = 1; j < i.operands; j++)
6378 i.op[j - 1] = i.op[j];
6379 i.types[j - 1] = i.types[j];
6381 /* We need to adjust fields in i.tm since they are used by
6382 build_modrm_byte. */
6383 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6390 else if (i.tm.opcode_modifier.implicitquadgroup)
6392 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6394 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6395 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6396 regnum = register_number (i.op[1].regs);
6397 first_reg_in_group = regnum & ~3;
6398 last_reg_in_group = first_reg_in_group + 3;
6399 if (regnum != first_reg_in_group)
6400 as_warn (_("source register `%s%s' implicitly denotes"
6401 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6402 register_prefix, i.op[1].regs->reg_name,
6403 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6404 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6407 else if (i.tm.opcode_modifier.regkludge)
6409 /* The imul $imm, %reg instruction is converted into
6410 imul $imm, %reg, %reg, and the clr %reg instruction
6411 is converted into xor %reg, %reg. */
6413 unsigned int first_reg_op;
6415 if (operand_type_check (i.types[0], reg))
6419 /* Pretend we saw the extra register operand. */
6420 gas_assert (i.reg_operands == 1
6421 && i.op[first_reg_op + 1].regs == 0);
6422 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6423 i.types[first_reg_op + 1] = i.types[first_reg_op];
6428 if (i.tm.opcode_modifier.shortform)
6430 if (i.types[0].bitfield.sreg2
6431 || i.types[0].bitfield.sreg3)
6433 if (i.tm.base_opcode == POP_SEG_SHORT
6434 && i.op[0].regs->reg_num == 1)
6436 as_bad (_("you can't `pop %scs'"), register_prefix);
6439 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6440 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6445 /* The register or float register operand is in operand
6449 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6450 || operand_type_check (i.types[0], reg))
6454 /* Register goes in low 3 bits of opcode. */
6455 i.tm.base_opcode |= i.op[op].regs->reg_num;
6456 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6458 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6460 /* Warn about some common errors, but press on regardless.
6461 The first case can be generated by gcc (<= 2.8.1). */
6462 if (i.operands == 2)
6464 /* Reversed arguments on faddp, fsubp, etc. */
6465 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6466 register_prefix, i.op[!intel_syntax].regs->reg_name,
6467 register_prefix, i.op[intel_syntax].regs->reg_name);
6471 /* Extraneous `l' suffix on fp insn. */
6472 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6473 register_prefix, i.op[0].regs->reg_name);
6478 else if (i.tm.opcode_modifier.modrm)
6480 /* The opcode is completed (modulo i.tm.extension_opcode which
6481 must be put into the modrm byte). Now, we make the modrm and
6482 index base bytes based on all the info we've collected. */
6484 default_seg = build_modrm_byte ();
6486 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6490 else if (i.tm.opcode_modifier.isstring)
6492 /* For the string instructions that allow a segment override
6493 on one of their operands, the default segment is ds. */
6497 if (i.tm.base_opcode == 0x8d /* lea */
6500 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6502 /* If a segment was explicitly specified, and the specified segment
6503 is not the default, use an opcode prefix to select it. If we
6504 never figured out what the default segment is, then default_seg
6505 will be zero at this point, and the specified segment prefix will
6507 if ((i.seg[0]) && (i.seg[0] != default_seg))
6509 if (!add_prefix (i.seg[0]->seg_prefix))
6515 static const seg_entry *
6516 build_modrm_byte (void)
6518 const seg_entry *default_seg = 0;
6519 unsigned int source, dest;
6522 /* The first operand of instructions with VEX prefix and 3 sources
6523 must be VEX_Imm4. */
6524 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6527 unsigned int nds, reg_slot;
6530 if (i.tm.opcode_modifier.veximmext
6531 && i.tm.opcode_modifier.immext)
6533 dest = i.operands - 2;
6534 gas_assert (dest == 3);
6537 dest = i.operands - 1;
6540 /* There are 2 kinds of instructions:
6541 1. 5 operands: 4 register operands or 3 register operands
6542 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6543 VexW0 or VexW1. The destination must be either XMM, YMM or
6545 2. 4 operands: 4 register operands or 3 register operands
6546 plus 1 memory operand, VexXDS, and VexImmExt */
6547 gas_assert ((i.reg_operands == 4
6548 || (i.reg_operands == 3 && i.mem_operands == 1))
6549 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6550 && (i.tm.opcode_modifier.veximmext
6551 || (i.imm_operands == 1
6552 && i.types[0].bitfield.vec_imm4
6553 && (i.tm.opcode_modifier.vexw == VEXW0
6554 || i.tm.opcode_modifier.vexw == VEXW1)
6555 && i.tm.operand_types[dest].bitfield.regsimd)));
6557 if (i.imm_operands == 0)
6559 /* When there is no immediate operand, generate an 8bit
6560 immediate operand to encode the first operand. */
6561 exp = &im_expressions[i.imm_operands++];
6562 i.op[i.operands].imms = exp;
6563 i.types[i.operands] = imm8;
6565 /* If VexW1 is set, the first operand is the source and
6566 the second operand is encoded in the immediate operand. */
6567 if (i.tm.opcode_modifier.vexw == VEXW1)
6578 /* FMA swaps REG and NDS. */
6579 if (i.tm.cpu_flags.bitfield.cpufma)
6587 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6588 exp->X_op = O_constant;
6589 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6590 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6594 unsigned int imm_slot;
6596 if (i.tm.opcode_modifier.vexw == VEXW0)
6598 /* If VexW0 is set, the third operand is the source and
6599 the second operand is encoded in the immediate
6606 /* VexW1 is set, the second operand is the source and
6607 the third operand is encoded in the immediate
6613 if (i.tm.opcode_modifier.immext)
6615 /* When ImmExt is set, the immediate byte is the last
6617 imm_slot = i.operands - 1;
6625 /* Turn on Imm8 so that output_imm will generate it. */
6626 i.types[imm_slot].bitfield.imm8 = 1;
6629 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6630 i.op[imm_slot].imms->X_add_number
6631 |= register_number (i.op[reg_slot].regs) << 4;
6632 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6635 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6636 i.vex.register_specifier = i.op[nds].regs;
6641 /* i.reg_operands MUST be the number of real register operands;
6642 implicit registers do not count. If there are 3 register
6643 operands, it must be a instruction with VexNDS. For a
6644 instruction with VexNDD, the destination register is encoded
6645 in VEX prefix. If there are 4 register operands, it must be
6646 a instruction with VEX prefix and 3 sources. */
6647 if (i.mem_operands == 0
6648 && ((i.reg_operands == 2
6649 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6650 || (i.reg_operands == 3
6651 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6652 || (i.reg_operands == 4 && vex_3_sources)))
6660 /* When there are 3 operands, one of them may be immediate,
6661 which may be the first or the last operand. Otherwise,
6662 the first operand must be shift count register (cl) or it
6663 is an instruction with VexNDS. */
6664 gas_assert (i.imm_operands == 1
6665 || (i.imm_operands == 0
6666 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6667 || i.types[0].bitfield.shiftcount)));
6668 if (operand_type_check (i.types[0], imm)
6669 || i.types[0].bitfield.shiftcount)
6675 /* When there are 4 operands, the first two must be 8bit
6676 immediate operands. The source operand will be the 3rd
6679 For instructions with VexNDS, if the first operand
6680 an imm8, the source operand is the 2nd one. If the last
6681 operand is imm8, the source operand is the first one. */
6682 gas_assert ((i.imm_operands == 2
6683 && i.types[0].bitfield.imm8
6684 && i.types[1].bitfield.imm8)
6685 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6686 && i.imm_operands == 1
6687 && (i.types[0].bitfield.imm8
6688 || i.types[i.operands - 1].bitfield.imm8
6690 if (i.imm_operands == 2)
6694 if (i.types[0].bitfield.imm8)
6701 if (i.tm.opcode_modifier.evex)
6703 /* For EVEX instructions, when there are 5 operands, the
6704 first one must be immediate operand. If the second one
6705 is immediate operand, the source operand is the 3th
6706 one. If the last one is immediate operand, the source
6707 operand is the 2nd one. */
6708 gas_assert (i.imm_operands == 2
6709 && i.tm.opcode_modifier.sae
6710 && operand_type_check (i.types[0], imm));
6711 if (operand_type_check (i.types[1], imm))
6713 else if (operand_type_check (i.types[4], imm))
6727 /* RC/SAE operand could be between DEST and SRC. That happens
6728 when one operand is GPR and the other one is XMM/YMM/ZMM
6730 if (i.rounding && i.rounding->operand == (int) dest)
6733 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6735 /* For instructions with VexNDS, the register-only source
6736 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6737 register. It is encoded in VEX prefix. We need to
6738 clear RegMem bit before calling operand_type_equal. */
6740 i386_operand_type op;
6743 /* Check register-only source operand when two source
6744 operands are swapped. */
6745 if (!i.tm.operand_types[source].bitfield.baseindex
6746 && i.tm.operand_types[dest].bitfield.baseindex)
6754 op = i.tm.operand_types[vvvv];
6755 op.bitfield.regmem = 0;
6756 if ((dest + 1) >= i.operands
6757 || ((!op.bitfield.reg
6758 || (!op.bitfield.dword && !op.bitfield.qword))
6759 && !op.bitfield.regsimd
6760 && !operand_type_equal (&op, ®mask)))
6762 i.vex.register_specifier = i.op[vvvv].regs;
6768 /* One of the register operands will be encoded in the i.tm.reg
6769 field, the other in the combined i.tm.mode and i.tm.regmem
6770 fields. If no form of this instruction supports a memory
6771 destination operand, then we assume the source operand may
6772 sometimes be a memory operand and so we need to store the
6773 destination in the i.rm.reg field. */
6774 if (!i.tm.operand_types[dest].bitfield.regmem
6775 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6777 i.rm.reg = i.op[dest].regs->reg_num;
6778 i.rm.regmem = i.op[source].regs->reg_num;
6779 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6781 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6783 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6785 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6790 i.rm.reg = i.op[source].regs->reg_num;
6791 i.rm.regmem = i.op[dest].regs->reg_num;
6792 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6794 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6796 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6798 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6801 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6803 if (!i.types[0].bitfield.control
6804 && !i.types[1].bitfield.control)
6806 i.rex &= ~(REX_R | REX_B);
6807 add_prefix (LOCK_PREFIX_OPCODE);
6811 { /* If it's not 2 reg operands... */
6816 unsigned int fake_zero_displacement = 0;
6819 for (op = 0; op < i.operands; op++)
6820 if (operand_type_check (i.types[op], anymem))
6822 gas_assert (op < i.operands);
6824 if (i.tm.opcode_modifier.vecsib)
6826 if (i.index_reg->reg_num == RegEiz
6827 || i.index_reg->reg_num == RegRiz)
6830 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6833 i.sib.base = NO_BASE_REGISTER;
6834 i.sib.scale = i.log2_scale_factor;
6835 i.types[op].bitfield.disp8 = 0;
6836 i.types[op].bitfield.disp16 = 0;
6837 i.types[op].bitfield.disp64 = 0;
6838 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6840 /* Must be 32 bit */
6841 i.types[op].bitfield.disp32 = 1;
6842 i.types[op].bitfield.disp32s = 0;
6846 i.types[op].bitfield.disp32 = 0;
6847 i.types[op].bitfield.disp32s = 1;
6850 i.sib.index = i.index_reg->reg_num;
6851 if ((i.index_reg->reg_flags & RegRex) != 0)
6853 if ((i.index_reg->reg_flags & RegVRex) != 0)
6859 if (i.base_reg == 0)
6862 if (!i.disp_operands)
6863 fake_zero_displacement = 1;
6864 if (i.index_reg == 0)
6866 i386_operand_type newdisp;
6868 gas_assert (!i.tm.opcode_modifier.vecsib);
6869 /* Operand is just <disp> */
6870 if (flag_code == CODE_64BIT)
6872 /* 64bit mode overwrites the 32bit absolute
6873 addressing by RIP relative addressing and
6874 absolute addressing is encoded by one of the
6875 redundant SIB forms. */
6876 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6877 i.sib.base = NO_BASE_REGISTER;
6878 i.sib.index = NO_INDEX_REGISTER;
6879 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6881 else if ((flag_code == CODE_16BIT)
6882 ^ (i.prefix[ADDR_PREFIX] != 0))
6884 i.rm.regmem = NO_BASE_REGISTER_16;
6889 i.rm.regmem = NO_BASE_REGISTER;
6892 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6893 i.types[op] = operand_type_or (i.types[op], newdisp);
6895 else if (!i.tm.opcode_modifier.vecsib)
6897 /* !i.base_reg && i.index_reg */
6898 if (i.index_reg->reg_num == RegEiz
6899 || i.index_reg->reg_num == RegRiz)
6900 i.sib.index = NO_INDEX_REGISTER;
6902 i.sib.index = i.index_reg->reg_num;
6903 i.sib.base = NO_BASE_REGISTER;
6904 i.sib.scale = i.log2_scale_factor;
6905 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6906 i.types[op].bitfield.disp8 = 0;
6907 i.types[op].bitfield.disp16 = 0;
6908 i.types[op].bitfield.disp64 = 0;
6909 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6911 /* Must be 32 bit */
6912 i.types[op].bitfield.disp32 = 1;
6913 i.types[op].bitfield.disp32s = 0;
6917 i.types[op].bitfield.disp32 = 0;
6918 i.types[op].bitfield.disp32s = 1;
6920 if ((i.index_reg->reg_flags & RegRex) != 0)
6924 /* RIP addressing for 64bit mode. */
6925 else if (i.base_reg->reg_num == RegRip ||
6926 i.base_reg->reg_num == RegEip)
6928 gas_assert (!i.tm.opcode_modifier.vecsib);
6929 i.rm.regmem = NO_BASE_REGISTER;
6930 i.types[op].bitfield.disp8 = 0;
6931 i.types[op].bitfield.disp16 = 0;
6932 i.types[op].bitfield.disp32 = 0;
6933 i.types[op].bitfield.disp32s = 1;
6934 i.types[op].bitfield.disp64 = 0;
6935 i.flags[op] |= Operand_PCrel;
6936 if (! i.disp_operands)
6937 fake_zero_displacement = 1;
6939 else if (i.base_reg->reg_type.bitfield.word)
6941 gas_assert (!i.tm.opcode_modifier.vecsib);
6942 switch (i.base_reg->reg_num)
6945 if (i.index_reg == 0)
6947 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6948 i.rm.regmem = i.index_reg->reg_num - 6;
6952 if (i.index_reg == 0)
6955 if (operand_type_check (i.types[op], disp) == 0)
6957 /* fake (%bp) into 0(%bp) */
6958 i.types[op].bitfield.disp8 = 1;
6959 fake_zero_displacement = 1;
6962 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6963 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6965 default: /* (%si) -> 4 or (%di) -> 5 */
6966 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6968 i.rm.mode = mode_from_disp_size (i.types[op]);
6970 else /* i.base_reg and 32/64 bit mode */
6972 if (flag_code == CODE_64BIT
6973 && operand_type_check (i.types[op], disp))
6975 i.types[op].bitfield.disp16 = 0;
6976 i.types[op].bitfield.disp64 = 0;
6977 if (i.prefix[ADDR_PREFIX] == 0)
6979 i.types[op].bitfield.disp32 = 0;
6980 i.types[op].bitfield.disp32s = 1;
6984 i.types[op].bitfield.disp32 = 1;
6985 i.types[op].bitfield.disp32s = 0;
6989 if (!i.tm.opcode_modifier.vecsib)
6990 i.rm.regmem = i.base_reg->reg_num;
6991 if ((i.base_reg->reg_flags & RegRex) != 0)
6993 i.sib.base = i.base_reg->reg_num;
6994 /* x86-64 ignores REX prefix bit here to avoid decoder
6996 if (!(i.base_reg->reg_flags & RegRex)
6997 && (i.base_reg->reg_num == EBP_REG_NUM
6998 || i.base_reg->reg_num == ESP_REG_NUM))
7000 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7002 fake_zero_displacement = 1;
7003 i.types[op].bitfield.disp8 = 1;
7005 i.sib.scale = i.log2_scale_factor;
7006 if (i.index_reg == 0)
7008 gas_assert (!i.tm.opcode_modifier.vecsib);
7009 /* <disp>(%esp) becomes two byte modrm with no index
7010 register. We've already stored the code for esp
7011 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7012 Any base register besides %esp will not use the
7013 extra modrm byte. */
7014 i.sib.index = NO_INDEX_REGISTER;
7016 else if (!i.tm.opcode_modifier.vecsib)
7018 if (i.index_reg->reg_num == RegEiz
7019 || i.index_reg->reg_num == RegRiz)
7020 i.sib.index = NO_INDEX_REGISTER;
7022 i.sib.index = i.index_reg->reg_num;
7023 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7024 if ((i.index_reg->reg_flags & RegRex) != 0)
7029 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7030 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7034 if (!fake_zero_displacement
7038 fake_zero_displacement = 1;
7039 if (i.disp_encoding == disp_encoding_8bit)
7040 i.types[op].bitfield.disp8 = 1;
7042 i.types[op].bitfield.disp32 = 1;
7044 i.rm.mode = mode_from_disp_size (i.types[op]);
7048 if (fake_zero_displacement)
7050 /* Fakes a zero displacement assuming that i.types[op]
7051 holds the correct displacement size. */
7054 gas_assert (i.op[op].disps == 0);
7055 exp = &disp_expressions[i.disp_operands++];
7056 i.op[op].disps = exp;
7057 exp->X_op = O_constant;
7058 exp->X_add_number = 0;
7059 exp->X_add_symbol = (symbolS *) 0;
7060 exp->X_op_symbol = (symbolS *) 0;
7068 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7070 if (operand_type_check (i.types[0], imm))
7071 i.vex.register_specifier = NULL;
7074 /* VEX.vvvv encodes one of the sources when the first
7075 operand is not an immediate. */
7076 if (i.tm.opcode_modifier.vexw == VEXW0)
7077 i.vex.register_specifier = i.op[0].regs;
7079 i.vex.register_specifier = i.op[1].regs;
7082 /* Destination is a XMM register encoded in the ModRM.reg
7084 i.rm.reg = i.op[2].regs->reg_num;
7085 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7088 /* ModRM.rm and VEX.B encodes the other source. */
7089 if (!i.mem_operands)
7093 if (i.tm.opcode_modifier.vexw == VEXW0)
7094 i.rm.regmem = i.op[1].regs->reg_num;
7096 i.rm.regmem = i.op[0].regs->reg_num;
7098 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7102 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7104 i.vex.register_specifier = i.op[2].regs;
7105 if (!i.mem_operands)
7108 i.rm.regmem = i.op[1].regs->reg_num;
7109 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7113 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7114 (if any) based on i.tm.extension_opcode. Again, we must be
7115 careful to make sure that segment/control/debug/test/MMX
7116 registers are coded into the i.rm.reg field. */
7117 else if (i.reg_operands)
7120 unsigned int vex_reg = ~0;
7122 for (op = 0; op < i.operands; op++)
7123 if (i.types[op].bitfield.reg
7124 || i.types[op].bitfield.regmmx
7125 || i.types[op].bitfield.regsimd
7126 || i.types[op].bitfield.regbnd
7127 || i.types[op].bitfield.regmask
7128 || i.types[op].bitfield.sreg2
7129 || i.types[op].bitfield.sreg3
7130 || i.types[op].bitfield.control
7131 || i.types[op].bitfield.debug
7132 || i.types[op].bitfield.test)
7137 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7139 /* For instructions with VexNDS, the register-only
7140 source operand is encoded in VEX prefix. */
7141 gas_assert (mem != (unsigned int) ~0);
7146 gas_assert (op < i.operands);
7150 /* Check register-only source operand when two source
7151 operands are swapped. */
7152 if (!i.tm.operand_types[op].bitfield.baseindex
7153 && i.tm.operand_types[op + 1].bitfield.baseindex)
7157 gas_assert (mem == (vex_reg + 1)
7158 && op < i.operands);
7163 gas_assert (vex_reg < i.operands);
7167 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7169 /* For instructions with VexNDD, the register destination
7170 is encoded in VEX prefix. */
7171 if (i.mem_operands == 0)
7173 /* There is no memory operand. */
7174 gas_assert ((op + 2) == i.operands);
7179 /* There are only 2 operands. */
7180 gas_assert (op < 2 && i.operands == 2);
7185 gas_assert (op < i.operands);
7187 if (vex_reg != (unsigned int) ~0)
7189 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7191 if ((!type->bitfield.reg
7192 || (!type->bitfield.dword && !type->bitfield.qword))
7193 && !type->bitfield.regsimd
7194 && !operand_type_equal (type, ®mask))
7197 i.vex.register_specifier = i.op[vex_reg].regs;
7200 /* Don't set OP operand twice. */
7203 /* If there is an extension opcode to put here, the
7204 register number must be put into the regmem field. */
7205 if (i.tm.extension_opcode != None)
7207 i.rm.regmem = i.op[op].regs->reg_num;
7208 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7210 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7215 i.rm.reg = i.op[op].regs->reg_num;
7216 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7218 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7223 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7224 must set it to 3 to indicate this is a register operand
7225 in the regmem field. */
7226 if (!i.mem_operands)
7230 /* Fill in i.rm.reg field with extension opcode (if any). */
7231 if (i.tm.extension_opcode != None)
7232 i.rm.reg = i.tm.extension_opcode;
7238 output_branch (void)
7244 relax_substateT subtype;
7248 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7249 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7252 if (i.prefix[DATA_PREFIX] != 0)
7258 /* Pentium4 branch hints. */
7259 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7260 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7265 if (i.prefix[REX_PREFIX] != 0)
7271 /* BND prefixed jump. */
7272 if (i.prefix[BND_PREFIX] != 0)
7274 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7278 if (i.prefixes != 0 && !intel_syntax)
7279 as_warn (_("skipping prefixes on this instruction"));
7281 /* It's always a symbol; End frag & setup for relax.
7282 Make sure there is enough room in this frag for the largest
7283 instruction we may generate in md_convert_frag. This is 2
7284 bytes for the opcode and room for the prefix and largest
7286 frag_grow (prefix + 2 + 4);
7287 /* Prefix and 1 opcode byte go in fr_fix. */
7288 p = frag_more (prefix + 1);
7289 if (i.prefix[DATA_PREFIX] != 0)
7290 *p++ = DATA_PREFIX_OPCODE;
7291 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7292 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7293 *p++ = i.prefix[SEG_PREFIX];
7294 if (i.prefix[REX_PREFIX] != 0)
7295 *p++ = i.prefix[REX_PREFIX];
7296 *p = i.tm.base_opcode;
7298 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7299 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7300 else if (cpu_arch_flags.bitfield.cpui386)
7301 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7303 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7306 sym = i.op[0].disps->X_add_symbol;
7307 off = i.op[0].disps->X_add_number;
7309 if (i.op[0].disps->X_op != O_constant
7310 && i.op[0].disps->X_op != O_symbol)
7312 /* Handle complex expressions. */
7313 sym = make_expr_symbol (i.op[0].disps);
7317 /* 1 possible extra opcode + 4 byte displacement go in var part.
7318 Pass reloc in fr_var. */
7319 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7323 /* Return TRUE iff PLT32 relocation should be used for branching to
7327 need_plt32_p (symbolS *s)
7329 /* PLT32 relocation is ELF only. */
7333 /* Since there is no need to prepare for PLT branch on x86-64, we
7334 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7335 be used as a marker for 32-bit PC-relative branches. */
7339 /* Weak or undefined symbol need PLT32 relocation. */
7340 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7343 /* Non-global symbol doesn't need PLT32 relocation. */
7344 if (! S_IS_EXTERNAL (s))
7347 /* Other global symbols need PLT32 relocation. NB: Symbol with
7348 non-default visibilities are treated as normal global symbol
7349 so that PLT32 relocation can be used as a marker for 32-bit
7350 PC-relative branches. It is useful for linker relaxation. */
7361 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7363 if (i.tm.opcode_modifier.jumpbyte)
7365 /* This is a loop or jecxz type instruction. */
7367 if (i.prefix[ADDR_PREFIX] != 0)
7369 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7372 /* Pentium4 branch hints. */
7373 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7374 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7376 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7385 if (flag_code == CODE_16BIT)
7388 if (i.prefix[DATA_PREFIX] != 0)
7390 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7400 if (i.prefix[REX_PREFIX] != 0)
7402 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7406 /* BND prefixed jump. */
7407 if (i.prefix[BND_PREFIX] != 0)
7409 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7413 if (i.prefixes != 0 && !intel_syntax)
7414 as_warn (_("skipping prefixes on this instruction"));
7416 p = frag_more (i.tm.opcode_length + size);
7417 switch (i.tm.opcode_length)
7420 *p++ = i.tm.base_opcode >> 8;
7423 *p++ = i.tm.base_opcode;
7429 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7431 && jump_reloc == NO_RELOC
7432 && need_plt32_p (i.op[0].disps->X_add_symbol))
7433 jump_reloc = BFD_RELOC_X86_64_PLT32;
7436 jump_reloc = reloc (size, 1, 1, jump_reloc);
7438 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7439 i.op[0].disps, 1, jump_reloc);
7441 /* All jumps handled here are signed, but don't use a signed limit
7442 check for 32 and 16 bit jumps as we want to allow wrap around at
7443 4G and 64k respectively. */
7445 fixP->fx_signed = 1;
7449 output_interseg_jump (void)
7457 if (flag_code == CODE_16BIT)
7461 if (i.prefix[DATA_PREFIX] != 0)
7467 if (i.prefix[REX_PREFIX] != 0)
7477 if (i.prefixes != 0 && !intel_syntax)
7478 as_warn (_("skipping prefixes on this instruction"));
7480 /* 1 opcode; 2 segment; offset */
7481 p = frag_more (prefix + 1 + 2 + size);
7483 if (i.prefix[DATA_PREFIX] != 0)
7484 *p++ = DATA_PREFIX_OPCODE;
7486 if (i.prefix[REX_PREFIX] != 0)
7487 *p++ = i.prefix[REX_PREFIX];
7489 *p++ = i.tm.base_opcode;
7490 if (i.op[1].imms->X_op == O_constant)
7492 offsetT n = i.op[1].imms->X_add_number;
7495 && !fits_in_unsigned_word (n)
7496 && !fits_in_signed_word (n))
7498 as_bad (_("16-bit jump out of range"));
7501 md_number_to_chars (p, n, size);
7504 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7505 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7506 if (i.op[0].imms->X_op != O_constant)
7507 as_bad (_("can't handle non absolute segment in `%s'"),
7509 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7515 fragS *insn_start_frag;
7516 offsetT insn_start_off;
7518 /* Tie dwarf2 debug info to the address at the start of the insn.
7519 We can't do this after the insn has been output as the current
7520 frag may have been closed off. eg. by frag_var. */
7521 dwarf2_emit_insn (0);
7523 insn_start_frag = frag_now;
7524 insn_start_off = frag_now_fix ();
7527 if (i.tm.opcode_modifier.jump)
7529 else if (i.tm.opcode_modifier.jumpbyte
7530 || i.tm.opcode_modifier.jumpdword)
7532 else if (i.tm.opcode_modifier.jumpintersegment)
7533 output_interseg_jump ();
7536 /* Output normal instructions here. */
7540 unsigned int prefix;
7543 && i.tm.base_opcode == 0xfae
7545 && i.imm_operands == 1
7546 && (i.op[0].imms->X_add_number == 0xe8
7547 || i.op[0].imms->X_add_number == 0xf0
7548 || i.op[0].imms->X_add_number == 0xf8))
7550 /* Encode lfence, mfence, and sfence as
7551 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7552 offsetT val = 0x240483f0ULL;
7554 md_number_to_chars (p, val, 5);
7558 /* Some processors fail on LOCK prefix. This options makes
7559 assembler ignore LOCK prefix and serves as a workaround. */
7560 if (omit_lock_prefix)
7562 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7564 i.prefix[LOCK_PREFIX] = 0;
7567 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7568 don't need the explicit prefix. */
7569 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7571 switch (i.tm.opcode_length)
7574 if (i.tm.base_opcode & 0xff000000)
7576 prefix = (i.tm.base_opcode >> 24) & 0xff;
7581 if ((i.tm.base_opcode & 0xff0000) != 0)
7583 prefix = (i.tm.base_opcode >> 16) & 0xff;
7584 if (i.tm.cpu_flags.bitfield.cpupadlock)
7587 if (prefix != REPE_PREFIX_OPCODE
7588 || (i.prefix[REP_PREFIX]
7589 != REPE_PREFIX_OPCODE))
7590 add_prefix (prefix);
7593 add_prefix (prefix);
7599 /* Check for pseudo prefixes. */
7600 as_bad_where (insn_start_frag->fr_file,
7601 insn_start_frag->fr_line,
7602 _("pseudo prefix without instruction"));
7608 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7609 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7610 R_X86_64_GOTTPOFF relocation so that linker can safely
7611 perform IE->LE optimization. */
7612 if (x86_elf_abi == X86_64_X32_ABI
7614 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7615 && i.prefix[REX_PREFIX] == 0)
7616 add_prefix (REX_OPCODE);
7619 /* The prefix bytes. */
7620 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7622 FRAG_APPEND_1_CHAR (*q);
7626 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7631 /* REX byte is encoded in VEX prefix. */
7635 FRAG_APPEND_1_CHAR (*q);
7638 /* There should be no other prefixes for instructions
7643 /* For EVEX instructions i.vrex should become 0 after
7644 build_evex_prefix. For VEX instructions upper 16 registers
7645 aren't available, so VREX should be 0. */
7648 /* Now the VEX prefix. */
7649 p = frag_more (i.vex.length);
7650 for (j = 0; j < i.vex.length; j++)
7651 p[j] = i.vex.bytes[j];
7654 /* Now the opcode; be careful about word order here! */
7655 if (i.tm.opcode_length == 1)
7657 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7661 switch (i.tm.opcode_length)
7665 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7666 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7670 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7680 /* Put out high byte first: can't use md_number_to_chars! */
7681 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7682 *p = i.tm.base_opcode & 0xff;
7685 /* Now the modrm byte and sib byte (if present). */
7686 if (i.tm.opcode_modifier.modrm)
7688 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7691 /* If i.rm.regmem == ESP (4)
7692 && i.rm.mode != (Register mode)
7694 ==> need second modrm byte. */
7695 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7697 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7698 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7700 | i.sib.scale << 6));
7703 if (i.disp_operands)
7704 output_disp (insn_start_frag, insn_start_off);
7707 output_imm (insn_start_frag, insn_start_off);
7713 pi ("" /*line*/, &i);
7715 #endif /* DEBUG386 */
7718 /* Return the size of the displacement operand N. */
7721 disp_size (unsigned int n)
7725 if (i.types[n].bitfield.disp64)
7727 else if (i.types[n].bitfield.disp8)
7729 else if (i.types[n].bitfield.disp16)
7734 /* Return the size of the immediate operand N. */
7737 imm_size (unsigned int n)
7740 if (i.types[n].bitfield.imm64)
7742 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7744 else if (i.types[n].bitfield.imm16)
7750 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7755 for (n = 0; n < i.operands; n++)
7757 if (operand_type_check (i.types[n], disp))
7759 if (i.op[n].disps->X_op == O_constant)
7761 int size = disp_size (n);
7762 offsetT val = i.op[n].disps->X_add_number;
7764 val = offset_in_range (val >> i.memshift, size);
7765 p = frag_more (size);
7766 md_number_to_chars (p, val, size);
7770 enum bfd_reloc_code_real reloc_type;
7771 int size = disp_size (n);
7772 int sign = i.types[n].bitfield.disp32s;
7773 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7776 /* We can't have 8 bit displacement here. */
7777 gas_assert (!i.types[n].bitfield.disp8);
7779 /* The PC relative address is computed relative
7780 to the instruction boundary, so in case immediate
7781 fields follows, we need to adjust the value. */
7782 if (pcrel && i.imm_operands)
7787 for (n1 = 0; n1 < i.operands; n1++)
7788 if (operand_type_check (i.types[n1], imm))
7790 /* Only one immediate is allowed for PC
7791 relative address. */
7792 gas_assert (sz == 0);
7794 i.op[n].disps->X_add_number -= sz;
7796 /* We should find the immediate. */
7797 gas_assert (sz != 0);
7800 p = frag_more (size);
7801 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7803 && GOT_symbol == i.op[n].disps->X_add_symbol
7804 && (((reloc_type == BFD_RELOC_32
7805 || reloc_type == BFD_RELOC_X86_64_32S
7806 || (reloc_type == BFD_RELOC_64
7808 && (i.op[n].disps->X_op == O_symbol
7809 || (i.op[n].disps->X_op == O_add
7810 && ((symbol_get_value_expression
7811 (i.op[n].disps->X_op_symbol)->X_op)
7813 || reloc_type == BFD_RELOC_32_PCREL))
7817 if (insn_start_frag == frag_now)
7818 add = (p - frag_now->fr_literal) - insn_start_off;
7823 add = insn_start_frag->fr_fix - insn_start_off;
7824 for (fr = insn_start_frag->fr_next;
7825 fr && fr != frag_now; fr = fr->fr_next)
7827 add += p - frag_now->fr_literal;
7832 reloc_type = BFD_RELOC_386_GOTPC;
7833 i.op[n].imms->X_add_number += add;
7835 else if (reloc_type == BFD_RELOC_64)
7836 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7838 /* Don't do the adjustment for x86-64, as there
7839 the pcrel addressing is relative to the _next_
7840 insn, and that is taken care of in other code. */
7841 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7843 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7844 size, i.op[n].disps, pcrel,
7846 /* Check for "call/jmp *mem", "mov mem, %reg",
7847 "test %reg, mem" and "binop mem, %reg" where binop
7848 is one of adc, add, and, cmp, or, sbb, sub, xor
7849 instructions. Always generate R_386_GOT32X for
7850 "sym*GOT" operand in 32-bit mode. */
7851 if ((generate_relax_relocations
7854 && i.rm.regmem == 5))
7856 || (i.rm.mode == 0 && i.rm.regmem == 5))
7857 && ((i.operands == 1
7858 && i.tm.base_opcode == 0xff
7859 && (i.rm.reg == 2 || i.rm.reg == 4))
7861 && (i.tm.base_opcode == 0x8b
7862 || i.tm.base_opcode == 0x85
7863 || (i.tm.base_opcode & 0xc7) == 0x03))))
7867 fixP->fx_tcbit = i.rex != 0;
7869 && (i.base_reg->reg_num == RegRip
7870 || i.base_reg->reg_num == RegEip))
7871 fixP->fx_tcbit2 = 1;
7874 fixP->fx_tcbit2 = 1;
7882 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7887 for (n = 0; n < i.operands; n++)
7889 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7890 if (i.rounding && (int) n == i.rounding->operand)
7893 if (operand_type_check (i.types[n], imm))
7895 if (i.op[n].imms->X_op == O_constant)
7897 int size = imm_size (n);
7900 val = offset_in_range (i.op[n].imms->X_add_number,
7902 p = frag_more (size);
7903 md_number_to_chars (p, val, size);
7907 /* Not absolute_section.
7908 Need a 32-bit fixup (don't support 8bit
7909 non-absolute imms). Try to support other
7911 enum bfd_reloc_code_real reloc_type;
7912 int size = imm_size (n);
7915 if (i.types[n].bitfield.imm32s
7916 && (i.suffix == QWORD_MNEM_SUFFIX
7917 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7922 p = frag_more (size);
7923 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7925 /* This is tough to explain. We end up with this one if we
7926 * have operands that look like
7927 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7928 * obtain the absolute address of the GOT, and it is strongly
7929 * preferable from a performance point of view to avoid using
7930 * a runtime relocation for this. The actual sequence of
7931 * instructions often look something like:
7936 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7938 * The call and pop essentially return the absolute address
7939 * of the label .L66 and store it in %ebx. The linker itself
7940 * will ultimately change the first operand of the addl so
7941 * that %ebx points to the GOT, but to keep things simple, the
7942 * .o file must have this operand set so that it generates not
7943 * the absolute address of .L66, but the absolute address of
7944 * itself. This allows the linker itself simply treat a GOTPC
7945 * relocation as asking for a pcrel offset to the GOT to be
7946 * added in, and the addend of the relocation is stored in the
7947 * operand field for the instruction itself.
7949 * Our job here is to fix the operand so that it would add
7950 * the correct offset so that %ebx would point to itself. The
7951 * thing that is tricky is that .-.L66 will point to the
7952 * beginning of the instruction, so we need to further modify
7953 * the operand so that it will point to itself. There are
7954 * other cases where you have something like:
7956 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7958 * and here no correction would be required. Internally in
7959 * the assembler we treat operands of this form as not being
7960 * pcrel since the '.' is explicitly mentioned, and I wonder
7961 * whether it would simplify matters to do it this way. Who
7962 * knows. In earlier versions of the PIC patches, the
7963 * pcrel_adjust field was used to store the correction, but
7964 * since the expression is not pcrel, I felt it would be
7965 * confusing to do it this way. */
7967 if ((reloc_type == BFD_RELOC_32
7968 || reloc_type == BFD_RELOC_X86_64_32S
7969 || reloc_type == BFD_RELOC_64)
7971 && GOT_symbol == i.op[n].imms->X_add_symbol
7972 && (i.op[n].imms->X_op == O_symbol
7973 || (i.op[n].imms->X_op == O_add
7974 && ((symbol_get_value_expression
7975 (i.op[n].imms->X_op_symbol)->X_op)
7980 if (insn_start_frag == frag_now)
7981 add = (p - frag_now->fr_literal) - insn_start_off;
7986 add = insn_start_frag->fr_fix - insn_start_off;
7987 for (fr = insn_start_frag->fr_next;
7988 fr && fr != frag_now; fr = fr->fr_next)
7990 add += p - frag_now->fr_literal;
7994 reloc_type = BFD_RELOC_386_GOTPC;
7996 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7998 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7999 i.op[n].imms->X_add_number += add;
8001 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8002 i.op[n].imms, 0, reloc_type);
8008 /* x86_cons_fix_new is called via the expression parsing code when a
8009 reloc is needed. We use this hook to get the correct .got reloc. */
8010 static int cons_sign = -1;
8013 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8014 expressionS *exp, bfd_reloc_code_real_type r)
8016 r = reloc (len, 0, cons_sign, r);
8019 if (exp->X_op == O_secrel)
8021 exp->X_op = O_symbol;
8022 r = BFD_RELOC_32_SECREL;
8026 fix_new_exp (frag, off, len, exp, 0, r);
8029 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8030 purpose of the `.dc.a' internal pseudo-op. */
8033 x86_address_bytes (void)
8035 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8037 return stdoutput->arch_info->bits_per_address / 8;
8040 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8042 # define lex_got(reloc, adjust, types) NULL
8044 /* Parse operands of the form
8045 <symbol>@GOTOFF+<nnn>
8046 and similar .plt or .got references.
8048 If we find one, set up the correct relocation in RELOC and copy the
8049 input string, minus the `@GOTOFF' into a malloc'd buffer for
8050 parsing by the calling routine. Return this buffer, and if ADJUST
8051 is non-null set it to the length of the string we removed from the
8052 input line. Otherwise return NULL. */
8054 lex_got (enum bfd_reloc_code_real *rel,
8056 i386_operand_type *types)
8058 /* Some of the relocations depend on the size of what field is to
8059 be relocated. But in our callers i386_immediate and i386_displacement
8060 we don't yet know the operand size (this will be set by insn
8061 matching). Hence we record the word32 relocation here,
8062 and adjust the reloc according to the real size in reloc(). */
8063 static const struct {
8066 const enum bfd_reloc_code_real rel[2];
8067 const i386_operand_type types64;
8069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8070 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8072 OPERAND_TYPE_IMM32_64 },
8074 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8075 BFD_RELOC_X86_64_PLTOFF64 },
8076 OPERAND_TYPE_IMM64 },
8077 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8078 BFD_RELOC_X86_64_PLT32 },
8079 OPERAND_TYPE_IMM32_32S_DISP32 },
8080 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8081 BFD_RELOC_X86_64_GOTPLT64 },
8082 OPERAND_TYPE_IMM64_DISP64 },
8083 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8084 BFD_RELOC_X86_64_GOTOFF64 },
8085 OPERAND_TYPE_IMM64_DISP64 },
8086 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8087 BFD_RELOC_X86_64_GOTPCREL },
8088 OPERAND_TYPE_IMM32_32S_DISP32 },
8089 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8090 BFD_RELOC_X86_64_TLSGD },
8091 OPERAND_TYPE_IMM32_32S_DISP32 },
8092 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8093 _dummy_first_bfd_reloc_code_real },
8094 OPERAND_TYPE_NONE },
8095 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8096 BFD_RELOC_X86_64_TLSLD },
8097 OPERAND_TYPE_IMM32_32S_DISP32 },
8098 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8099 BFD_RELOC_X86_64_GOTTPOFF },
8100 OPERAND_TYPE_IMM32_32S_DISP32 },
8101 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8102 BFD_RELOC_X86_64_TPOFF32 },
8103 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8104 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8105 _dummy_first_bfd_reloc_code_real },
8106 OPERAND_TYPE_NONE },
8107 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8108 BFD_RELOC_X86_64_DTPOFF32 },
8109 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8110 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8111 _dummy_first_bfd_reloc_code_real },
8112 OPERAND_TYPE_NONE },
8113 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8114 _dummy_first_bfd_reloc_code_real },
8115 OPERAND_TYPE_NONE },
8116 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8117 BFD_RELOC_X86_64_GOT32 },
8118 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8119 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8120 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8121 OPERAND_TYPE_IMM32_32S_DISP32 },
8122 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8123 BFD_RELOC_X86_64_TLSDESC_CALL },
8124 OPERAND_TYPE_IMM32_32S_DISP32 },
8129 #if defined (OBJ_MAYBE_ELF)
8134 for (cp = input_line_pointer; *cp != '@'; cp++)
8135 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8138 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8140 int len = gotrel[j].len;
8141 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8143 if (gotrel[j].rel[object_64bit] != 0)
8146 char *tmpbuf, *past_reloc;
8148 *rel = gotrel[j].rel[object_64bit];
8152 if (flag_code != CODE_64BIT)
8154 types->bitfield.imm32 = 1;
8155 types->bitfield.disp32 = 1;
8158 *types = gotrel[j].types64;
8161 if (j != 0 && GOT_symbol == NULL)
8162 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8164 /* The length of the first part of our input line. */
8165 first = cp - input_line_pointer;
8167 /* The second part goes from after the reloc token until
8168 (and including) an end_of_line char or comma. */
8169 past_reloc = cp + 1 + len;
8171 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8173 second = cp + 1 - past_reloc;
8175 /* Allocate and copy string. The trailing NUL shouldn't
8176 be necessary, but be safe. */
8177 tmpbuf = XNEWVEC (char, first + second + 2);
8178 memcpy (tmpbuf, input_line_pointer, first);
8179 if (second != 0 && *past_reloc != ' ')
8180 /* Replace the relocation token with ' ', so that
8181 errors like foo@GOTOFF1 will be detected. */
8182 tmpbuf[first++] = ' ';
8184 /* Increment length by 1 if the relocation token is
8189 memcpy (tmpbuf + first, past_reloc, second);
8190 tmpbuf[first + second] = '\0';
8194 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8195 gotrel[j].str, 1 << (5 + object_64bit));
8200 /* Might be a symbol version string. Don't as_bad here. */
8209 /* Parse operands of the form
8210 <symbol>@SECREL32+<nnn>
8212 If we find one, set up the correct relocation in RELOC and copy the
8213 input string, minus the `@SECREL32' into a malloc'd buffer for
8214 parsing by the calling routine. Return this buffer, and if ADJUST
8215 is non-null set it to the length of the string we removed from the
8216 input line. Otherwise return NULL.
8218 This function is copied from the ELF version above adjusted for PE targets. */
8221 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8222 int *adjust ATTRIBUTE_UNUSED,
8223 i386_operand_type *types)
8229 const enum bfd_reloc_code_real rel[2];
8230 const i386_operand_type types64;
8234 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8235 BFD_RELOC_32_SECREL },
8236 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8242 for (cp = input_line_pointer; *cp != '@'; cp++)
8243 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8246 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8248 int len = gotrel[j].len;
8250 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8252 if (gotrel[j].rel[object_64bit] != 0)
8255 char *tmpbuf, *past_reloc;
8257 *rel = gotrel[j].rel[object_64bit];
8263 if (flag_code != CODE_64BIT)
8265 types->bitfield.imm32 = 1;
8266 types->bitfield.disp32 = 1;
8269 *types = gotrel[j].types64;
8272 /* The length of the first part of our input line. */
8273 first = cp - input_line_pointer;
8275 /* The second part goes from after the reloc token until
8276 (and including) an end_of_line char or comma. */
8277 past_reloc = cp + 1 + len;
8279 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8281 second = cp + 1 - past_reloc;
8283 /* Allocate and copy string. The trailing NUL shouldn't
8284 be necessary, but be safe. */
8285 tmpbuf = XNEWVEC (char, first + second + 2);
8286 memcpy (tmpbuf, input_line_pointer, first);
8287 if (second != 0 && *past_reloc != ' ')
8288 /* Replace the relocation token with ' ', so that
8289 errors like foo@SECLREL321 will be detected. */
8290 tmpbuf[first++] = ' ';
8291 memcpy (tmpbuf + first, past_reloc, second);
8292 tmpbuf[first + second] = '\0';
8296 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8297 gotrel[j].str, 1 << (5 + object_64bit));
8302 /* Might be a symbol version string. Don't as_bad here. */
8308 bfd_reloc_code_real_type
8309 x86_cons (expressionS *exp, int size)
8311 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8313 intel_syntax = -intel_syntax;
8316 if (size == 4 || (object_64bit && size == 8))
8318 /* Handle @GOTOFF and the like in an expression. */
8320 char *gotfree_input_line;
8323 save = input_line_pointer;
8324 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8325 if (gotfree_input_line)
8326 input_line_pointer = gotfree_input_line;
8330 if (gotfree_input_line)
8332 /* expression () has merrily parsed up to the end of line,
8333 or a comma - in the wrong buffer. Transfer how far
8334 input_line_pointer has moved to the right buffer. */
8335 input_line_pointer = (save
8336 + (input_line_pointer - gotfree_input_line)
8338 free (gotfree_input_line);
8339 if (exp->X_op == O_constant
8340 || exp->X_op == O_absent
8341 || exp->X_op == O_illegal
8342 || exp->X_op == O_register
8343 || exp->X_op == O_big)
8345 char c = *input_line_pointer;
8346 *input_line_pointer = 0;
8347 as_bad (_("missing or invalid expression `%s'"), save);
8348 *input_line_pointer = c;
8355 intel_syntax = -intel_syntax;
8358 i386_intel_simplify (exp);
8364 signed_cons (int size)
8366 if (flag_code == CODE_64BIT)
8374 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8381 if (exp.X_op == O_symbol)
8382 exp.X_op = O_secrel;
8384 emit_expr (&exp, 4);
8386 while (*input_line_pointer++ == ',');
8388 input_line_pointer--;
8389 demand_empty_rest_of_line ();
8393 /* Handle Vector operations. */
8396 check_VecOperations (char *op_string, char *op_end)
8398 const reg_entry *mask;
8403 && (op_end == NULL || op_string < op_end))
8406 if (*op_string == '{')
8410 /* Check broadcasts. */
8411 if (strncmp (op_string, "1to", 3) == 0)
8416 goto duplicated_vec_op;
8419 if (*op_string == '8')
8420 bcst_type = BROADCAST_1TO8;
8421 else if (*op_string == '4')
8422 bcst_type = BROADCAST_1TO4;
8423 else if (*op_string == '2')
8424 bcst_type = BROADCAST_1TO2;
8425 else if (*op_string == '1'
8426 && *(op_string+1) == '6')
8428 bcst_type = BROADCAST_1TO16;
8433 as_bad (_("Unsupported broadcast: `%s'"), saved);
8438 broadcast_op.type = bcst_type;
8439 broadcast_op.operand = this_operand;
8440 i.broadcast = &broadcast_op;
8442 /* Check masking operation. */
8443 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8445 /* k0 can't be used for write mask. */
8446 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8448 as_bad (_("`%s%s' can't be used for write mask"),
8449 register_prefix, mask->reg_name);
8455 mask_op.mask = mask;
8456 mask_op.zeroing = 0;
8457 mask_op.operand = this_operand;
8463 goto duplicated_vec_op;
8465 i.mask->mask = mask;
8467 /* Only "{z}" is allowed here. No need to check
8468 zeroing mask explicitly. */
8469 if (i.mask->operand != this_operand)
8471 as_bad (_("invalid write mask `%s'"), saved);
8478 /* Check zeroing-flag for masking operation. */
8479 else if (*op_string == 'z')
8483 mask_op.mask = NULL;
8484 mask_op.zeroing = 1;
8485 mask_op.operand = this_operand;
8490 if (i.mask->zeroing)
8493 as_bad (_("duplicated `%s'"), saved);
8497 i.mask->zeroing = 1;
8499 /* Only "{%k}" is allowed here. No need to check mask
8500 register explicitly. */
8501 if (i.mask->operand != this_operand)
8503 as_bad (_("invalid zeroing-masking `%s'"),
8512 goto unknown_vec_op;
8514 if (*op_string != '}')
8516 as_bad (_("missing `}' in `%s'"), saved);
8523 /* We don't know this one. */
8524 as_bad (_("unknown vector operation: `%s'"), saved);
8528 if (i.mask && i.mask->zeroing && !i.mask->mask)
8530 as_bad (_("zeroing-masking only allowed with write mask"));
8538 i386_immediate (char *imm_start)
8540 char *save_input_line_pointer;
8541 char *gotfree_input_line;
8544 i386_operand_type types;
8546 operand_type_set (&types, ~0);
8548 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8550 as_bad (_("at most %d immediate operands are allowed"),
8551 MAX_IMMEDIATE_OPERANDS);
8555 exp = &im_expressions[i.imm_operands++];
8556 i.op[this_operand].imms = exp;
8558 if (is_space_char (*imm_start))
8561 save_input_line_pointer = input_line_pointer;
8562 input_line_pointer = imm_start;
8564 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8565 if (gotfree_input_line)
8566 input_line_pointer = gotfree_input_line;
8568 exp_seg = expression (exp);
8572 /* Handle vector operations. */
8573 if (*input_line_pointer == '{')
8575 input_line_pointer = check_VecOperations (input_line_pointer,
8577 if (input_line_pointer == NULL)
8581 if (*input_line_pointer)
8582 as_bad (_("junk `%s' after expression"), input_line_pointer);
8584 input_line_pointer = save_input_line_pointer;
8585 if (gotfree_input_line)
8587 free (gotfree_input_line);
8589 if (exp->X_op == O_constant || exp->X_op == O_register)
8590 exp->X_op = O_illegal;
8593 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8597 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8598 i386_operand_type types, const char *imm_start)
8600 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8603 as_bad (_("missing or invalid immediate expression `%s'"),
8607 else if (exp->X_op == O_constant)
8609 /* Size it properly later. */
8610 i.types[this_operand].bitfield.imm64 = 1;
8611 /* If not 64bit, sign extend val. */
8612 if (flag_code != CODE_64BIT
8613 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8615 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8617 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8618 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8619 && exp_seg != absolute_section
8620 && exp_seg != text_section
8621 && exp_seg != data_section
8622 && exp_seg != bss_section
8623 && exp_seg != undefined_section
8624 && !bfd_is_com_section (exp_seg))
8626 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8630 else if (!intel_syntax && exp_seg == reg_section)
8633 as_bad (_("illegal immediate register operand %s"), imm_start);
8638 /* This is an address. The size of the address will be
8639 determined later, depending on destination register,
8640 suffix, or the default for the section. */
8641 i.types[this_operand].bitfield.imm8 = 1;
8642 i.types[this_operand].bitfield.imm16 = 1;
8643 i.types[this_operand].bitfield.imm32 = 1;
8644 i.types[this_operand].bitfield.imm32s = 1;
8645 i.types[this_operand].bitfield.imm64 = 1;
8646 i.types[this_operand] = operand_type_and (i.types[this_operand],
8654 i386_scale (char *scale)
8657 char *save = input_line_pointer;
8659 input_line_pointer = scale;
8660 val = get_absolute_expression ();
8665 i.log2_scale_factor = 0;
8668 i.log2_scale_factor = 1;
8671 i.log2_scale_factor = 2;
8674 i.log2_scale_factor = 3;
8678 char sep = *input_line_pointer;
8680 *input_line_pointer = '\0';
8681 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8683 *input_line_pointer = sep;
8684 input_line_pointer = save;
8688 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8690 as_warn (_("scale factor of %d without an index register"),
8691 1 << i.log2_scale_factor);
8692 i.log2_scale_factor = 0;
8694 scale = input_line_pointer;
8695 input_line_pointer = save;
8700 i386_displacement (char *disp_start, char *disp_end)
8704 char *save_input_line_pointer;
8705 char *gotfree_input_line;
8707 i386_operand_type bigdisp, types = anydisp;
8710 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8712 as_bad (_("at most %d displacement operands are allowed"),
8713 MAX_MEMORY_OPERANDS);
8717 operand_type_set (&bigdisp, 0);
8718 if ((i.types[this_operand].bitfield.jumpabsolute)
8719 || (!current_templates->start->opcode_modifier.jump
8720 && !current_templates->start->opcode_modifier.jumpdword))
8722 bigdisp.bitfield.disp32 = 1;
8723 override = (i.prefix[ADDR_PREFIX] != 0);
8724 if (flag_code == CODE_64BIT)
8728 bigdisp.bitfield.disp32s = 1;
8729 bigdisp.bitfield.disp64 = 1;
8732 else if ((flag_code == CODE_16BIT) ^ override)
8734 bigdisp.bitfield.disp32 = 0;
8735 bigdisp.bitfield.disp16 = 1;
8740 /* For PC-relative branches, the width of the displacement
8741 is dependent upon data size, not address size. */
8742 override = (i.prefix[DATA_PREFIX] != 0);
8743 if (flag_code == CODE_64BIT)
8745 if (override || i.suffix == WORD_MNEM_SUFFIX)
8746 bigdisp.bitfield.disp16 = 1;
8749 bigdisp.bitfield.disp32 = 1;
8750 bigdisp.bitfield.disp32s = 1;
8756 override = (i.suffix == (flag_code != CODE_16BIT
8758 : LONG_MNEM_SUFFIX));
8759 bigdisp.bitfield.disp32 = 1;
8760 if ((flag_code == CODE_16BIT) ^ override)
8762 bigdisp.bitfield.disp32 = 0;
8763 bigdisp.bitfield.disp16 = 1;
8767 i.types[this_operand] = operand_type_or (i.types[this_operand],
8770 exp = &disp_expressions[i.disp_operands];
8771 i.op[this_operand].disps = exp;
8773 save_input_line_pointer = input_line_pointer;
8774 input_line_pointer = disp_start;
8775 END_STRING_AND_SAVE (disp_end);
8777 #ifndef GCC_ASM_O_HACK
8778 #define GCC_ASM_O_HACK 0
8781 END_STRING_AND_SAVE (disp_end + 1);
8782 if (i.types[this_operand].bitfield.baseIndex
8783 && displacement_string_end[-1] == '+')
8785 /* This hack is to avoid a warning when using the "o"
8786 constraint within gcc asm statements.
8789 #define _set_tssldt_desc(n,addr,limit,type) \
8790 __asm__ __volatile__ ( \
8792 "movw %w1,2+%0\n\t" \
8794 "movb %b1,4+%0\n\t" \
8795 "movb %4,5+%0\n\t" \
8796 "movb $0,6+%0\n\t" \
8797 "movb %h1,7+%0\n\t" \
8799 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8801 This works great except that the output assembler ends
8802 up looking a bit weird if it turns out that there is
8803 no offset. You end up producing code that looks like:
8816 So here we provide the missing zero. */
8818 *displacement_string_end = '0';
8821 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8822 if (gotfree_input_line)
8823 input_line_pointer = gotfree_input_line;
8825 exp_seg = expression (exp);
8828 if (*input_line_pointer)
8829 as_bad (_("junk `%s' after expression"), input_line_pointer);
8831 RESTORE_END_STRING (disp_end + 1);
8833 input_line_pointer = save_input_line_pointer;
8834 if (gotfree_input_line)
8836 free (gotfree_input_line);
8838 if (exp->X_op == O_constant || exp->X_op == O_register)
8839 exp->X_op = O_illegal;
8842 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8844 RESTORE_END_STRING (disp_end);
8850 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8851 i386_operand_type types, const char *disp_start)
8853 i386_operand_type bigdisp;
8856 /* We do this to make sure that the section symbol is in
8857 the symbol table. We will ultimately change the relocation
8858 to be relative to the beginning of the section. */
8859 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8860 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8861 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8863 if (exp->X_op != O_symbol)
8866 if (S_IS_LOCAL (exp->X_add_symbol)
8867 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8868 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8869 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8870 exp->X_op = O_subtract;
8871 exp->X_op_symbol = GOT_symbol;
8872 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8873 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8874 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8875 i.reloc[this_operand] = BFD_RELOC_64;
8877 i.reloc[this_operand] = BFD_RELOC_32;
8880 else if (exp->X_op == O_absent
8881 || exp->X_op == O_illegal
8882 || exp->X_op == O_big)
8885 as_bad (_("missing or invalid displacement expression `%s'"),
8890 else if (flag_code == CODE_64BIT
8891 && !i.prefix[ADDR_PREFIX]
8892 && exp->X_op == O_constant)
8894 /* Since displacement is signed extended to 64bit, don't allow
8895 disp32 and turn off disp32s if they are out of range. */
8896 i.types[this_operand].bitfield.disp32 = 0;
8897 if (!fits_in_signed_long (exp->X_add_number))
8899 i.types[this_operand].bitfield.disp32s = 0;
8900 if (i.types[this_operand].bitfield.baseindex)
8902 as_bad (_("0x%lx out range of signed 32bit displacement"),
8903 (long) exp->X_add_number);
8909 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8910 else if (exp->X_op != O_constant
8911 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8912 && exp_seg != absolute_section
8913 && exp_seg != text_section
8914 && exp_seg != data_section
8915 && exp_seg != bss_section
8916 && exp_seg != undefined_section
8917 && !bfd_is_com_section (exp_seg))
8919 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8924 /* Check if this is a displacement only operand. */
8925 bigdisp = i.types[this_operand];
8926 bigdisp.bitfield.disp8 = 0;
8927 bigdisp.bitfield.disp16 = 0;
8928 bigdisp.bitfield.disp32 = 0;
8929 bigdisp.bitfield.disp32s = 0;
8930 bigdisp.bitfield.disp64 = 0;
8931 if (operand_type_all_zero (&bigdisp))
8932 i.types[this_operand] = operand_type_and (i.types[this_operand],
8938 /* Return the active addressing mode, taking address override and
8939 registers forming the address into consideration. Update the
8940 address override prefix if necessary. */
8942 static enum flag_code
8943 i386_addressing_mode (void)
8945 enum flag_code addr_mode;
8947 if (i.prefix[ADDR_PREFIX])
8948 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8951 addr_mode = flag_code;
8953 #if INFER_ADDR_PREFIX
8954 if (i.mem_operands == 0)
8956 /* Infer address prefix from the first memory operand. */
8957 const reg_entry *addr_reg = i.base_reg;
8959 if (addr_reg == NULL)
8960 addr_reg = i.index_reg;
8964 if (addr_reg->reg_num == RegEip
8965 || addr_reg->reg_num == RegEiz
8966 || addr_reg->reg_type.bitfield.dword)
8967 addr_mode = CODE_32BIT;
8968 else if (flag_code != CODE_64BIT
8969 && addr_reg->reg_type.bitfield.word)
8970 addr_mode = CODE_16BIT;
8972 if (addr_mode != flag_code)
8974 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8976 /* Change the size of any displacement too. At most one
8977 of Disp16 or Disp32 is set.
8978 FIXME. There doesn't seem to be any real need for
8979 separate Disp16 and Disp32 flags. The same goes for
8980 Imm16 and Imm32. Removing them would probably clean
8981 up the code quite a lot. */
8982 if (flag_code != CODE_64BIT
8983 && (i.types[this_operand].bitfield.disp16
8984 || i.types[this_operand].bitfield.disp32))
8985 i.types[this_operand]
8986 = operand_type_xor (i.types[this_operand], disp16_32);
8996 /* Make sure the memory operand we've been dealt is valid.
8997 Return 1 on success, 0 on a failure. */
9000 i386_index_check (const char *operand_string)
9002 const char *kind = "base/index";
9003 enum flag_code addr_mode = i386_addressing_mode ();
9005 if (current_templates->start->opcode_modifier.isstring
9006 && !current_templates->start->opcode_modifier.immext
9007 && (current_templates->end[-1].opcode_modifier.isstring
9010 /* Memory operands of string insns are special in that they only allow
9011 a single register (rDI, rSI, or rBX) as their memory address. */
9012 const reg_entry *expected_reg;
9013 static const char *di_si[][2] =
9019 static const char *bx[] = { "ebx", "bx", "rbx" };
9021 kind = "string address";
9023 if (current_templates->start->opcode_modifier.repprefixok)
9025 i386_operand_type type = current_templates->end[-1].operand_types[0];
9027 if (!type.bitfield.baseindex
9028 || ((!i.mem_operands != !intel_syntax)
9029 && current_templates->end[-1].operand_types[1]
9030 .bitfield.baseindex))
9031 type = current_templates->end[-1].operand_types[1];
9032 expected_reg = hash_find (reg_hash,
9033 di_si[addr_mode][type.bitfield.esseg]);
9037 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9039 if (i.base_reg != expected_reg
9041 || operand_type_check (i.types[this_operand], disp))
9043 /* The second memory operand must have the same size as
9047 && !((addr_mode == CODE_64BIT
9048 && i.base_reg->reg_type.bitfield.qword)
9049 || (addr_mode == CODE_32BIT
9050 ? i.base_reg->reg_type.bitfield.dword
9051 : i.base_reg->reg_type.bitfield.word)))
9054 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9056 intel_syntax ? '[' : '(',
9058 expected_reg->reg_name,
9059 intel_syntax ? ']' : ')');
9066 as_bad (_("`%s' is not a valid %s expression"),
9067 operand_string, kind);
9072 if (addr_mode != CODE_16BIT)
9074 /* 32-bit/64-bit checks. */
9076 && (addr_mode == CODE_64BIT
9077 ? !i.base_reg->reg_type.bitfield.qword
9078 : !i.base_reg->reg_type.bitfield.dword)
9080 || (i.base_reg->reg_num
9081 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9083 && !i.index_reg->reg_type.bitfield.xmmword
9084 && !i.index_reg->reg_type.bitfield.ymmword
9085 && !i.index_reg->reg_type.bitfield.zmmword
9086 && ((addr_mode == CODE_64BIT
9087 ? !(i.index_reg->reg_type.bitfield.qword
9088 || i.index_reg->reg_num == RegRiz)
9089 : !(i.index_reg->reg_type.bitfield.dword
9090 || i.index_reg->reg_num == RegEiz))
9091 || !i.index_reg->reg_type.bitfield.baseindex)))
9094 /* bndmk, bndldx, and bndstx have special restrictions. */
9095 if (current_templates->start->base_opcode == 0xf30f1b
9096 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9098 /* They cannot use RIP-relative addressing. */
9099 if (i.base_reg && i.base_reg->reg_num == RegRip)
9101 as_bad (_("`%s' cannot be used here"), operand_string);
9105 /* bndldx and bndstx ignore their scale factor. */
9106 if (current_templates->start->base_opcode != 0xf30f1b
9107 && i.log2_scale_factor)
9108 as_warn (_("register scaling is being ignored here"));
9113 /* 16-bit checks. */
9115 && (!i.base_reg->reg_type.bitfield.word
9116 || !i.base_reg->reg_type.bitfield.baseindex))
9118 && (!i.index_reg->reg_type.bitfield.word
9119 || !i.index_reg->reg_type.bitfield.baseindex
9121 && i.base_reg->reg_num < 6
9122 && i.index_reg->reg_num >= 6
9123 && i.log2_scale_factor == 0))))
9130 /* Handle vector immediates. */
9133 RC_SAE_immediate (const char *imm_start)
9135 unsigned int match_found, j;
9136 const char *pstr = imm_start;
9144 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9146 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9150 rc_op.type = RC_NamesTable[j].type;
9151 rc_op.operand = this_operand;
9152 i.rounding = &rc_op;
9156 as_bad (_("duplicated `%s'"), imm_start);
9159 pstr += RC_NamesTable[j].len;
9169 as_bad (_("Missing '}': '%s'"), imm_start);
9172 /* RC/SAE immediate string should contain nothing more. */;
9175 as_bad (_("Junk after '}': '%s'"), imm_start);
9179 exp = &im_expressions[i.imm_operands++];
9180 i.op[this_operand].imms = exp;
9182 exp->X_op = O_constant;
9183 exp->X_add_number = 0;
9184 exp->X_add_symbol = (symbolS *) 0;
9185 exp->X_op_symbol = (symbolS *) 0;
9187 i.types[this_operand].bitfield.imm8 = 1;
9191 /* Only string instructions can have a second memory operand, so
9192 reduce current_templates to just those if it contains any. */
9194 maybe_adjust_templates (void)
9196 const insn_template *t;
9198 gas_assert (i.mem_operands == 1);
9200 for (t = current_templates->start; t < current_templates->end; ++t)
9201 if (t->opcode_modifier.isstring)
9204 if (t < current_templates->end)
9206 static templates aux_templates;
9207 bfd_boolean recheck;
9209 aux_templates.start = t;
9210 for (; t < current_templates->end; ++t)
9211 if (!t->opcode_modifier.isstring)
9213 aux_templates.end = t;
9215 /* Determine whether to re-check the first memory operand. */
9216 recheck = (aux_templates.start != current_templates->start
9217 || t != current_templates->end);
9219 current_templates = &aux_templates;
9224 if (i.memop1_string != NULL
9225 && i386_index_check (i.memop1_string) == 0)
9234 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9238 i386_att_operand (char *operand_string)
9242 char *op_string = operand_string;
9244 if (is_space_char (*op_string))
9247 /* We check for an absolute prefix (differentiating,
9248 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9249 if (*op_string == ABSOLUTE_PREFIX)
9252 if (is_space_char (*op_string))
9254 i.types[this_operand].bitfield.jumpabsolute = 1;
9257 /* Check if operand is a register. */
9258 if ((r = parse_register (op_string, &end_op)) != NULL)
9260 i386_operand_type temp;
9262 /* Check for a segment override by searching for ':' after a
9263 segment register. */
9265 if (is_space_char (*op_string))
9267 if (*op_string == ':'
9268 && (r->reg_type.bitfield.sreg2
9269 || r->reg_type.bitfield.sreg3))
9274 i.seg[i.mem_operands] = &es;
9277 i.seg[i.mem_operands] = &cs;
9280 i.seg[i.mem_operands] = &ss;
9283 i.seg[i.mem_operands] = &ds;
9286 i.seg[i.mem_operands] = &fs;
9289 i.seg[i.mem_operands] = &gs;
9293 /* Skip the ':' and whitespace. */
9295 if (is_space_char (*op_string))
9298 if (!is_digit_char (*op_string)
9299 && !is_identifier_char (*op_string)
9300 && *op_string != '('
9301 && *op_string != ABSOLUTE_PREFIX)
9303 as_bad (_("bad memory operand `%s'"), op_string);
9306 /* Handle case of %es:*foo. */
9307 if (*op_string == ABSOLUTE_PREFIX)
9310 if (is_space_char (*op_string))
9312 i.types[this_operand].bitfield.jumpabsolute = 1;
9314 goto do_memory_reference;
9317 /* Handle vector operations. */
9318 if (*op_string == '{')
9320 op_string = check_VecOperations (op_string, NULL);
9321 if (op_string == NULL)
9327 as_bad (_("junk `%s' after register"), op_string);
9331 temp.bitfield.baseindex = 0;
9332 i.types[this_operand] = operand_type_or (i.types[this_operand],
9334 i.types[this_operand].bitfield.unspecified = 0;
9335 i.op[this_operand].regs = r;
9338 else if (*op_string == REGISTER_PREFIX)
9340 as_bad (_("bad register name `%s'"), op_string);
9343 else if (*op_string == IMMEDIATE_PREFIX)
9346 if (i.types[this_operand].bitfield.jumpabsolute)
9348 as_bad (_("immediate operand illegal with absolute jump"));
9351 if (!i386_immediate (op_string))
9354 else if (RC_SAE_immediate (operand_string))
9356 /* If it is a RC or SAE immediate, do nothing. */
9359 else if (is_digit_char (*op_string)
9360 || is_identifier_char (*op_string)
9361 || *op_string == '"'
9362 || *op_string == '(')
9364 /* This is a memory reference of some sort. */
9367 /* Start and end of displacement string expression (if found). */
9368 char *displacement_string_start;
9369 char *displacement_string_end;
9372 do_memory_reference:
9373 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9375 if ((i.mem_operands == 1
9376 && !current_templates->start->opcode_modifier.isstring)
9377 || i.mem_operands == 2)
9379 as_bad (_("too many memory references for `%s'"),
9380 current_templates->start->name);
9384 /* Check for base index form. We detect the base index form by
9385 looking for an ')' at the end of the operand, searching
9386 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9388 base_string = op_string + strlen (op_string);
9390 /* Handle vector operations. */
9391 vop_start = strchr (op_string, '{');
9392 if (vop_start && vop_start < base_string)
9394 if (check_VecOperations (vop_start, base_string) == NULL)
9396 base_string = vop_start;
9400 if (is_space_char (*base_string))
9403 /* If we only have a displacement, set-up for it to be parsed later. */
9404 displacement_string_start = op_string;
9405 displacement_string_end = base_string + 1;
9407 if (*base_string == ')')
9410 unsigned int parens_balanced = 1;
9411 /* We've already checked that the number of left & right ()'s are
9412 equal, so this loop will not be infinite. */
9416 if (*base_string == ')')
9418 if (*base_string == '(')
9421 while (parens_balanced);
9423 temp_string = base_string;
9425 /* Skip past '(' and whitespace. */
9427 if (is_space_char (*base_string))
9430 if (*base_string == ','
9431 || ((i.base_reg = parse_register (base_string, &end_op))
9434 displacement_string_end = temp_string;
9436 i.types[this_operand].bitfield.baseindex = 1;
9440 base_string = end_op;
9441 if (is_space_char (*base_string))
9445 /* There may be an index reg or scale factor here. */
9446 if (*base_string == ',')
9449 if (is_space_char (*base_string))
9452 if ((i.index_reg = parse_register (base_string, &end_op))
9455 base_string = end_op;
9456 if (is_space_char (*base_string))
9458 if (*base_string == ',')
9461 if (is_space_char (*base_string))
9464 else if (*base_string != ')')
9466 as_bad (_("expecting `,' or `)' "
9467 "after index register in `%s'"),
9472 else if (*base_string == REGISTER_PREFIX)
9474 end_op = strchr (base_string, ',');
9477 as_bad (_("bad register name `%s'"), base_string);
9481 /* Check for scale factor. */
9482 if (*base_string != ')')
9484 char *end_scale = i386_scale (base_string);
9489 base_string = end_scale;
9490 if (is_space_char (*base_string))
9492 if (*base_string != ')')
9494 as_bad (_("expecting `)' "
9495 "after scale factor in `%s'"),
9500 else if (!i.index_reg)
9502 as_bad (_("expecting index register or scale factor "
9503 "after `,'; got '%c'"),
9508 else if (*base_string != ')')
9510 as_bad (_("expecting `,' or `)' "
9511 "after base register in `%s'"),
9516 else if (*base_string == REGISTER_PREFIX)
9518 end_op = strchr (base_string, ',');
9521 as_bad (_("bad register name `%s'"), base_string);
9526 /* If there's an expression beginning the operand, parse it,
9527 assuming displacement_string_start and
9528 displacement_string_end are meaningful. */
9529 if (displacement_string_start != displacement_string_end)
9531 if (!i386_displacement (displacement_string_start,
9532 displacement_string_end))
9536 /* Special case for (%dx) while doing input/output op. */
9538 && operand_type_equal (&i.base_reg->reg_type,
9539 ®16_inoutportreg)
9541 && i.log2_scale_factor == 0
9542 && i.seg[i.mem_operands] == 0
9543 && !operand_type_check (i.types[this_operand], disp))
9545 i.types[this_operand] = inoutportreg;
9549 if (i386_index_check (operand_string) == 0)
9551 i.types[this_operand].bitfield.mem = 1;
9552 if (i.mem_operands == 0)
9553 i.memop1_string = xstrdup (operand_string);
9558 /* It's not a memory operand; argh! */
9559 as_bad (_("invalid char %s beginning operand %d `%s'"),
9560 output_invalid (*op_string),
9565 return 1; /* Normal return. */
9568 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9569 that an rs_machine_dependent frag may reach. */
9572 i386_frag_max_var (fragS *frag)
9574 /* The only relaxable frags are for jumps.
9575 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9576 gas_assert (frag->fr_type == rs_machine_dependent);
9577 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9582 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9584 /* STT_GNU_IFUNC symbol must go through PLT. */
9585 if ((symbol_get_bfdsym (fr_symbol)->flags
9586 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9589 if (!S_IS_EXTERNAL (fr_symbol))
9590 /* Symbol may be weak or local. */
9591 return !S_IS_WEAK (fr_symbol);
9593 /* Global symbols with non-default visibility can't be preempted. */
9594 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9597 if (fr_var != NO_RELOC)
9598 switch ((enum bfd_reloc_code_real) fr_var)
9600 case BFD_RELOC_386_PLT32:
9601 case BFD_RELOC_X86_64_PLT32:
9602 /* Symbol with PLT relocation may be preempted. */
9608 /* Global symbols with default visibility in a shared library may be
9609 preempted by another definition. */
9614 /* md_estimate_size_before_relax()
9616 Called just before relax() for rs_machine_dependent frags. The x86
9617 assembler uses these frags to handle variable size jump
9620 Any symbol that is now undefined will not become defined.
9621 Return the correct fr_subtype in the frag.
9622 Return the initial "guess for variable size of frag" to caller.
9623 The guess is actually the growth beyond the fixed part. Whatever
9624 we do to grow the fixed or variable part contributes to our
9628 md_estimate_size_before_relax (fragS *fragP, segT segment)
9630 /* We've already got fragP->fr_subtype right; all we have to do is
9631 check for un-relaxable symbols. On an ELF system, we can't relax
9632 an externally visible symbol, because it may be overridden by a
9634 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9635 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9637 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9640 #if defined (OBJ_COFF) && defined (TE_PE)
9641 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9642 && S_IS_WEAK (fragP->fr_symbol))
9646 /* Symbol is undefined in this segment, or we need to keep a
9647 reloc so that weak symbols can be overridden. */
9648 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9649 enum bfd_reloc_code_real reloc_type;
9650 unsigned char *opcode;
9653 if (fragP->fr_var != NO_RELOC)
9654 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9656 reloc_type = BFD_RELOC_16_PCREL;
9657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9658 else if (need_plt32_p (fragP->fr_symbol))
9659 reloc_type = BFD_RELOC_X86_64_PLT32;
9662 reloc_type = BFD_RELOC_32_PCREL;
9664 old_fr_fix = fragP->fr_fix;
9665 opcode = (unsigned char *) fragP->fr_opcode;
9667 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9670 /* Make jmp (0xeb) a (d)word displacement jump. */
9672 fragP->fr_fix += size;
9673 fix_new (fragP, old_fr_fix, size,
9675 fragP->fr_offset, 1,
9681 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9683 /* Negate the condition, and branch past an
9684 unconditional jump. */
9687 /* Insert an unconditional jump. */
9689 /* We added two extra opcode bytes, and have a two byte
9691 fragP->fr_fix += 2 + 2;
9692 fix_new (fragP, old_fr_fix + 2, 2,
9694 fragP->fr_offset, 1,
9701 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9706 fixP = fix_new (fragP, old_fr_fix, 1,
9708 fragP->fr_offset, 1,
9710 fixP->fx_signed = 1;
9714 /* This changes the byte-displacement jump 0x7N
9715 to the (d)word-displacement jump 0x0f,0x8N. */
9716 opcode[1] = opcode[0] + 0x10;
9717 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9718 /* We've added an opcode byte. */
9719 fragP->fr_fix += 1 + size;
9720 fix_new (fragP, old_fr_fix + 1, size,
9722 fragP->fr_offset, 1,
9727 BAD_CASE (fragP->fr_subtype);
9731 return fragP->fr_fix - old_fr_fix;
9734 /* Guess size depending on current relax state. Initially the relax
9735 state will correspond to a short jump and we return 1, because
9736 the variable part of the frag (the branch offset) is one byte
9737 long. However, we can relax a section more than once and in that
9738 case we must either set fr_subtype back to the unrelaxed state,
9739 or return the value for the appropriate branch. */
9740 return md_relax_table[fragP->fr_subtype].rlx_length;
9743 /* Called after relax() is finished.
9745 In: Address of frag.
9746 fr_type == rs_machine_dependent.
9747 fr_subtype is what the address relaxed to.
9749 Out: Any fixSs and constants are set up.
9750 Caller will turn frag into a ".space 0". */
9753 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9756 unsigned char *opcode;
9757 unsigned char *where_to_put_displacement = NULL;
9758 offsetT target_address;
9759 offsetT opcode_address;
9760 unsigned int extension = 0;
9761 offsetT displacement_from_opcode_start;
9763 opcode = (unsigned char *) fragP->fr_opcode;
9765 /* Address we want to reach in file space. */
9766 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9768 /* Address opcode resides at in file space. */
9769 opcode_address = fragP->fr_address + fragP->fr_fix;
9771 /* Displacement from opcode start to fill into instruction. */
9772 displacement_from_opcode_start = target_address - opcode_address;
9774 if ((fragP->fr_subtype & BIG) == 0)
9776 /* Don't have to change opcode. */
9777 extension = 1; /* 1 opcode + 1 displacement */
9778 where_to_put_displacement = &opcode[1];
9782 if (no_cond_jump_promotion
9783 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9784 as_warn_where (fragP->fr_file, fragP->fr_line,
9785 _("long jump required"));
9787 switch (fragP->fr_subtype)
9789 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9790 extension = 4; /* 1 opcode + 4 displacement */
9792 where_to_put_displacement = &opcode[1];
9795 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9796 extension = 2; /* 1 opcode + 2 displacement */
9798 where_to_put_displacement = &opcode[1];
9801 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9802 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9803 extension = 5; /* 2 opcode + 4 displacement */
9804 opcode[1] = opcode[0] + 0x10;
9805 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9806 where_to_put_displacement = &opcode[2];
9809 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9810 extension = 3; /* 2 opcode + 2 displacement */
9811 opcode[1] = opcode[0] + 0x10;
9812 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9813 where_to_put_displacement = &opcode[2];
9816 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9821 where_to_put_displacement = &opcode[3];
9825 BAD_CASE (fragP->fr_subtype);
9830 /* If size if less then four we are sure that the operand fits,
9831 but if it's 4, then it could be that the displacement is larger
9833 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9835 && ((addressT) (displacement_from_opcode_start - extension
9836 + ((addressT) 1 << 31))
9837 > (((addressT) 2 << 31) - 1)))
9839 as_bad_where (fragP->fr_file, fragP->fr_line,
9840 _("jump target out of range"));
9841 /* Make us emit 0. */
9842 displacement_from_opcode_start = extension;
9844 /* Now put displacement after opcode. */
9845 md_number_to_chars ((char *) where_to_put_displacement,
9846 (valueT) (displacement_from_opcode_start - extension),
9847 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9848 fragP->fr_fix += extension;
9851 /* Apply a fixup (fixP) to segment data, once it has been determined
9852 by our caller that we have all the info we need to fix it up.
9854 Parameter valP is the pointer to the value of the bits.
9856 On the 386, immediates, displacements, and data pointers are all in
9857 the same (little-endian) format, so we don't need to care about which
9861 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9863 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9864 valueT value = *valP;
9866 #if !defined (TE_Mach)
9869 switch (fixP->fx_r_type)
9875 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9878 case BFD_RELOC_X86_64_32S:
9879 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9882 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9885 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9890 if (fixP->fx_addsy != NULL
9891 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9892 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9893 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9894 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9895 && !use_rela_relocations)
9897 /* This is a hack. There should be a better way to handle this.
9898 This covers for the fact that bfd_install_relocation will
9899 subtract the current location (for partial_inplace, PC relative
9900 relocations); see more below. */
9904 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9907 value += fixP->fx_where + fixP->fx_frag->fr_address;
9909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9912 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9915 || (symbol_section_p (fixP->fx_addsy)
9916 && sym_seg != absolute_section))
9917 && !generic_force_reloc (fixP))
9919 /* Yes, we add the values in twice. This is because
9920 bfd_install_relocation subtracts them out again. I think
9921 bfd_install_relocation is broken, but I don't dare change
9923 value += fixP->fx_where + fixP->fx_frag->fr_address;
9927 #if defined (OBJ_COFF) && defined (TE_PE)
9928 /* For some reason, the PE format does not store a
9929 section address offset for a PC relative symbol. */
9930 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9931 || S_IS_WEAK (fixP->fx_addsy))
9932 value += md_pcrel_from (fixP);
9935 #if defined (OBJ_COFF) && defined (TE_PE)
9936 if (fixP->fx_addsy != NULL
9937 && S_IS_WEAK (fixP->fx_addsy)
9938 /* PR 16858: Do not modify weak function references. */
9939 && ! fixP->fx_pcrel)
9941 #if !defined (TE_PEP)
9942 /* For x86 PE weak function symbols are neither PC-relative
9943 nor do they set S_IS_FUNCTION. So the only reliable way
9944 to detect them is to check the flags of their containing
9946 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9947 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9951 value -= S_GET_VALUE (fixP->fx_addsy);
9955 /* Fix a few things - the dynamic linker expects certain values here,
9956 and we must not disappoint it. */
9957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9958 if (IS_ELF && fixP->fx_addsy)
9959 switch (fixP->fx_r_type)
9961 case BFD_RELOC_386_PLT32:
9962 case BFD_RELOC_X86_64_PLT32:
9963 /* Make the jump instruction point to the address of the operand. At
9964 runtime we merely add the offset to the actual PLT entry. */
9968 case BFD_RELOC_386_TLS_GD:
9969 case BFD_RELOC_386_TLS_LDM:
9970 case BFD_RELOC_386_TLS_IE_32:
9971 case BFD_RELOC_386_TLS_IE:
9972 case BFD_RELOC_386_TLS_GOTIE:
9973 case BFD_RELOC_386_TLS_GOTDESC:
9974 case BFD_RELOC_X86_64_TLSGD:
9975 case BFD_RELOC_X86_64_TLSLD:
9976 case BFD_RELOC_X86_64_GOTTPOFF:
9977 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9978 value = 0; /* Fully resolved at runtime. No addend. */
9980 case BFD_RELOC_386_TLS_LE:
9981 case BFD_RELOC_386_TLS_LDO_32:
9982 case BFD_RELOC_386_TLS_LE_32:
9983 case BFD_RELOC_X86_64_DTPOFF32:
9984 case BFD_RELOC_X86_64_DTPOFF64:
9985 case BFD_RELOC_X86_64_TPOFF32:
9986 case BFD_RELOC_X86_64_TPOFF64:
9987 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9990 case BFD_RELOC_386_TLS_DESC_CALL:
9991 case BFD_RELOC_X86_64_TLSDESC_CALL:
9992 value = 0; /* Fully resolved at runtime. No addend. */
9993 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9997 case BFD_RELOC_VTABLE_INHERIT:
9998 case BFD_RELOC_VTABLE_ENTRY:
10005 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10007 #endif /* !defined (TE_Mach) */
10009 /* Are we finished with this relocation now? */
10010 if (fixP->fx_addsy == NULL)
10012 #if defined (OBJ_COFF) && defined (TE_PE)
10013 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10016 /* Remember value for tc_gen_reloc. */
10017 fixP->fx_addnumber = value;
10018 /* Clear out the frag for now. */
10022 else if (use_rela_relocations)
10024 fixP->fx_no_overflow = 1;
10025 /* Remember value for tc_gen_reloc. */
10026 fixP->fx_addnumber = value;
10030 md_number_to_chars (p, value, fixP->fx_size);
10034 md_atof (int type, char *litP, int *sizeP)
10036 /* This outputs the LITTLENUMs in REVERSE order;
10037 in accord with the bigendian 386. */
10038 return ieee_md_atof (type, litP, sizeP, FALSE);
10041 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10044 output_invalid (int c)
10047 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10050 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10051 "(0x%x)", (unsigned char) c);
10052 return output_invalid_buf;
10055 /* REG_STRING starts *before* REGISTER_PREFIX. */
10057 static const reg_entry *
10058 parse_real_register (char *reg_string, char **end_op)
10060 char *s = reg_string;
10062 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10063 const reg_entry *r;
10065 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10066 if (*s == REGISTER_PREFIX)
10069 if (is_space_char (*s))
10072 p = reg_name_given;
10073 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10075 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10076 return (const reg_entry *) NULL;
10080 /* For naked regs, make sure that we are not dealing with an identifier.
10081 This prevents confusing an identifier like `eax_var' with register
10083 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10084 return (const reg_entry *) NULL;
10088 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10090 /* Handle floating point regs, allowing spaces in the (i) part. */
10091 if (r == i386_regtab /* %st is first entry of table */)
10093 if (is_space_char (*s))
10098 if (is_space_char (*s))
10100 if (*s >= '0' && *s <= '7')
10102 int fpr = *s - '0';
10104 if (is_space_char (*s))
10109 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10114 /* We have "%st(" then garbage. */
10115 return (const reg_entry *) NULL;
10119 if (r == NULL || allow_pseudo_reg)
10122 if (operand_type_all_zero (&r->reg_type))
10123 return (const reg_entry *) NULL;
10125 if ((r->reg_type.bitfield.dword
10126 || r->reg_type.bitfield.sreg3
10127 || r->reg_type.bitfield.control
10128 || r->reg_type.bitfield.debug
10129 || r->reg_type.bitfield.test)
10130 && !cpu_arch_flags.bitfield.cpui386)
10131 return (const reg_entry *) NULL;
10133 if (r->reg_type.bitfield.tbyte
10134 && !cpu_arch_flags.bitfield.cpu8087
10135 && !cpu_arch_flags.bitfield.cpu287
10136 && !cpu_arch_flags.bitfield.cpu387)
10137 return (const reg_entry *) NULL;
10139 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10140 return (const reg_entry *) NULL;
10142 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10143 return (const reg_entry *) NULL;
10145 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10146 return (const reg_entry *) NULL;
10148 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10149 return (const reg_entry *) NULL;
10151 if (r->reg_type.bitfield.regmask
10152 && !cpu_arch_flags.bitfield.cpuregmask)
10153 return (const reg_entry *) NULL;
10155 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10156 if (!allow_index_reg
10157 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10158 return (const reg_entry *) NULL;
10160 /* Upper 16 vector register is only available with VREX in 64bit
10162 if ((r->reg_flags & RegVRex))
10164 if (i.vec_encoding == vex_encoding_default)
10165 i.vec_encoding = vex_encoding_evex;
10167 if (!cpu_arch_flags.bitfield.cpuvrex
10168 || i.vec_encoding != vex_encoding_evex
10169 || flag_code != CODE_64BIT)
10170 return (const reg_entry *) NULL;
10173 if (((r->reg_flags & (RegRex64 | RegRex))
10174 || r->reg_type.bitfield.qword)
10175 && (!cpu_arch_flags.bitfield.cpulm
10176 || !operand_type_equal (&r->reg_type, &control))
10177 && flag_code != CODE_64BIT)
10178 return (const reg_entry *) NULL;
10180 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10181 return (const reg_entry *) NULL;
10186 /* REG_STRING starts *before* REGISTER_PREFIX. */
10188 static const reg_entry *
10189 parse_register (char *reg_string, char **end_op)
10191 const reg_entry *r;
10193 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10194 r = parse_real_register (reg_string, end_op);
10199 char *save = input_line_pointer;
10203 input_line_pointer = reg_string;
10204 c = get_symbol_name (®_string);
10205 symbolP = symbol_find (reg_string);
10206 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10208 const expressionS *e = symbol_get_value_expression (symbolP);
10210 know (e->X_op == O_register);
10211 know (e->X_add_number >= 0
10212 && (valueT) e->X_add_number < i386_regtab_size);
10213 r = i386_regtab + e->X_add_number;
10214 if ((r->reg_flags & RegVRex))
10215 i.vec_encoding = vex_encoding_evex;
10216 *end_op = input_line_pointer;
10218 *input_line_pointer = c;
10219 input_line_pointer = save;
10225 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10227 const reg_entry *r;
10228 char *end = input_line_pointer;
10231 r = parse_register (name, &input_line_pointer);
10232 if (r && end <= input_line_pointer)
10234 *nextcharP = *input_line_pointer;
10235 *input_line_pointer = 0;
10236 e->X_op = O_register;
10237 e->X_add_number = r - i386_regtab;
10240 input_line_pointer = end;
10242 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10246 md_operand (expressionS *e)
10249 const reg_entry *r;
10251 switch (*input_line_pointer)
10253 case REGISTER_PREFIX:
10254 r = parse_real_register (input_line_pointer, &end);
10257 e->X_op = O_register;
10258 e->X_add_number = r - i386_regtab;
10259 input_line_pointer = end;
10264 gas_assert (intel_syntax);
10265 end = input_line_pointer++;
10267 if (*input_line_pointer == ']')
10269 ++input_line_pointer;
10270 e->X_op_symbol = make_expr_symbol (e);
10271 e->X_add_symbol = NULL;
10272 e->X_add_number = 0;
10277 e->X_op = O_absent;
10278 input_line_pointer = end;
10285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10286 const char *md_shortopts = "kVQ:sqnO::";
10288 const char *md_shortopts = "qnO::";
10291 #define OPTION_32 (OPTION_MD_BASE + 0)
10292 #define OPTION_64 (OPTION_MD_BASE + 1)
10293 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10294 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10295 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10296 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10297 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10298 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10299 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10300 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10301 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10302 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10303 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10304 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10305 #define OPTION_X32 (OPTION_MD_BASE + 14)
10306 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10307 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10308 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10309 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10310 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10311 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10312 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10313 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10314 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10315 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10316 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10318 struct option md_longopts[] =
10320 {"32", no_argument, NULL, OPTION_32},
10321 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10322 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10323 {"64", no_argument, NULL, OPTION_64},
10325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10326 {"x32", no_argument, NULL, OPTION_X32},
10327 {"mshared", no_argument, NULL, OPTION_MSHARED},
10329 {"divide", no_argument, NULL, OPTION_DIVIDE},
10330 {"march", required_argument, NULL, OPTION_MARCH},
10331 {"mtune", required_argument, NULL, OPTION_MTUNE},
10332 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10333 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10334 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10335 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10336 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10337 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10338 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10339 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10340 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10341 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10342 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10343 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10344 # if defined (TE_PE) || defined (TE_PEP)
10345 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10347 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10348 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10349 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10350 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10351 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10352 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10353 {NULL, no_argument, NULL, 0}
10355 size_t md_longopts_size = sizeof (md_longopts);
10358 md_parse_option (int c, const char *arg)
10361 char *arch, *next, *saved;
10366 optimize_align_code = 0;
10370 quiet_warnings = 1;
10373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10374 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10375 should be emitted or not. FIXME: Not implemented. */
10379 /* -V: SVR4 argument to print version ID. */
10381 print_version_id ();
10384 /* -k: Ignore for FreeBSD compatibility. */
10389 /* -s: On i386 Solaris, this tells the native assembler to use
10390 .stab instead of .stab.excl. We always use .stab anyhow. */
10393 case OPTION_MSHARED:
10397 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10398 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10401 const char **list, **l;
10403 list = bfd_target_list ();
10404 for (l = list; *l != NULL; l++)
10405 if (CONST_STRNEQ (*l, "elf64-x86-64")
10406 || strcmp (*l, "coff-x86-64") == 0
10407 || strcmp (*l, "pe-x86-64") == 0
10408 || strcmp (*l, "pei-x86-64") == 0
10409 || strcmp (*l, "mach-o-x86-64") == 0)
10411 default_arch = "x86_64";
10415 as_fatal (_("no compiled in support for x86_64"));
10421 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10425 const char **list, **l;
10427 list = bfd_target_list ();
10428 for (l = list; *l != NULL; l++)
10429 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10431 default_arch = "x86_64:32";
10435 as_fatal (_("no compiled in support for 32bit x86_64"));
10439 as_fatal (_("32bit x86_64 is only supported for ELF"));
10444 default_arch = "i386";
10447 case OPTION_DIVIDE:
10448 #ifdef SVR4_COMMENT_CHARS
10453 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10455 for (s = i386_comment_chars; *s != '\0'; s++)
10459 i386_comment_chars = n;
10465 saved = xstrdup (arg);
10467 /* Allow -march=+nosse. */
10473 as_fatal (_("invalid -march= option: `%s'"), arg);
10474 next = strchr (arch, '+');
10477 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10479 if (strcmp (arch, cpu_arch [j].name) == 0)
10482 if (! cpu_arch[j].flags.bitfield.cpui386)
10485 cpu_arch_name = cpu_arch[j].name;
10486 cpu_sub_arch_name = NULL;
10487 cpu_arch_flags = cpu_arch[j].flags;
10488 cpu_arch_isa = cpu_arch[j].type;
10489 cpu_arch_isa_flags = cpu_arch[j].flags;
10490 if (!cpu_arch_tune_set)
10492 cpu_arch_tune = cpu_arch_isa;
10493 cpu_arch_tune_flags = cpu_arch_isa_flags;
10497 else if (*cpu_arch [j].name == '.'
10498 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10500 /* ISA extension. */
10501 i386_cpu_flags flags;
10503 flags = cpu_flags_or (cpu_arch_flags,
10504 cpu_arch[j].flags);
10506 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10508 if (cpu_sub_arch_name)
10510 char *name = cpu_sub_arch_name;
10511 cpu_sub_arch_name = concat (name,
10513 (const char *) NULL);
10517 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10518 cpu_arch_flags = flags;
10519 cpu_arch_isa_flags = flags;
10525 if (j >= ARRAY_SIZE (cpu_arch))
10527 /* Disable an ISA extension. */
10528 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10529 if (strcmp (arch, cpu_noarch [j].name) == 0)
10531 i386_cpu_flags flags;
10533 flags = cpu_flags_and_not (cpu_arch_flags,
10534 cpu_noarch[j].flags);
10535 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10537 if (cpu_sub_arch_name)
10539 char *name = cpu_sub_arch_name;
10540 cpu_sub_arch_name = concat (arch,
10541 (const char *) NULL);
10545 cpu_sub_arch_name = xstrdup (arch);
10546 cpu_arch_flags = flags;
10547 cpu_arch_isa_flags = flags;
10552 if (j >= ARRAY_SIZE (cpu_noarch))
10553 j = ARRAY_SIZE (cpu_arch);
10556 if (j >= ARRAY_SIZE (cpu_arch))
10557 as_fatal (_("invalid -march= option: `%s'"), arg);
10561 while (next != NULL);
10567 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10568 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10570 if (strcmp (arg, cpu_arch [j].name) == 0)
10572 cpu_arch_tune_set = 1;
10573 cpu_arch_tune = cpu_arch [j].type;
10574 cpu_arch_tune_flags = cpu_arch[j].flags;
10578 if (j >= ARRAY_SIZE (cpu_arch))
10579 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10582 case OPTION_MMNEMONIC:
10583 if (strcasecmp (arg, "att") == 0)
10584 intel_mnemonic = 0;
10585 else if (strcasecmp (arg, "intel") == 0)
10586 intel_mnemonic = 1;
10588 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10591 case OPTION_MSYNTAX:
10592 if (strcasecmp (arg, "att") == 0)
10594 else if (strcasecmp (arg, "intel") == 0)
10597 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10600 case OPTION_MINDEX_REG:
10601 allow_index_reg = 1;
10604 case OPTION_MNAKED_REG:
10605 allow_naked_reg = 1;
10608 case OPTION_MOLD_GCC:
10612 case OPTION_MSSE2AVX:
10616 case OPTION_MSSE_CHECK:
10617 if (strcasecmp (arg, "error") == 0)
10618 sse_check = check_error;
10619 else if (strcasecmp (arg, "warning") == 0)
10620 sse_check = check_warning;
10621 else if (strcasecmp (arg, "none") == 0)
10622 sse_check = check_none;
10624 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10627 case OPTION_MOPERAND_CHECK:
10628 if (strcasecmp (arg, "error") == 0)
10629 operand_check = check_error;
10630 else if (strcasecmp (arg, "warning") == 0)
10631 operand_check = check_warning;
10632 else if (strcasecmp (arg, "none") == 0)
10633 operand_check = check_none;
10635 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10638 case OPTION_MAVXSCALAR:
10639 if (strcasecmp (arg, "128") == 0)
10640 avxscalar = vex128;
10641 else if (strcasecmp (arg, "256") == 0)
10642 avxscalar = vex256;
10644 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10647 case OPTION_MADD_BND_PREFIX:
10648 add_bnd_prefix = 1;
10651 case OPTION_MEVEXLIG:
10652 if (strcmp (arg, "128") == 0)
10653 evexlig = evexl128;
10654 else if (strcmp (arg, "256") == 0)
10655 evexlig = evexl256;
10656 else if (strcmp (arg, "512") == 0)
10657 evexlig = evexl512;
10659 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10662 case OPTION_MEVEXRCIG:
10663 if (strcmp (arg, "rne") == 0)
10665 else if (strcmp (arg, "rd") == 0)
10667 else if (strcmp (arg, "ru") == 0)
10669 else if (strcmp (arg, "rz") == 0)
10672 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10675 case OPTION_MEVEXWIG:
10676 if (strcmp (arg, "0") == 0)
10678 else if (strcmp (arg, "1") == 0)
10681 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10684 # if defined (TE_PE) || defined (TE_PEP)
10685 case OPTION_MBIG_OBJ:
10690 case OPTION_MOMIT_LOCK_PREFIX:
10691 if (strcasecmp (arg, "yes") == 0)
10692 omit_lock_prefix = 1;
10693 else if (strcasecmp (arg, "no") == 0)
10694 omit_lock_prefix = 0;
10696 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10699 case OPTION_MFENCE_AS_LOCK_ADD:
10700 if (strcasecmp (arg, "yes") == 0)
10702 else if (strcasecmp (arg, "no") == 0)
10705 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10708 case OPTION_MRELAX_RELOCATIONS:
10709 if (strcasecmp (arg, "yes") == 0)
10710 generate_relax_relocations = 1;
10711 else if (strcasecmp (arg, "no") == 0)
10712 generate_relax_relocations = 0;
10714 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10717 case OPTION_MAMD64:
10721 case OPTION_MINTEL64:
10729 /* Turn off -Os. */
10730 optimize_for_space = 0;
10732 else if (*arg == 's')
10734 optimize_for_space = 1;
10735 /* Turn on all encoding optimizations. */
10740 optimize = atoi (arg);
10741 /* Turn off -Os. */
10742 optimize_for_space = 0;
10752 #define MESSAGE_TEMPLATE \
10756 output_message (FILE *stream, char *p, char *message, char *start,
10757 int *left_p, const char *name, int len)
10759 int size = sizeof (MESSAGE_TEMPLATE);
10760 int left = *left_p;
10762 /* Reserve 2 spaces for ", " or ",\0" */
10765 /* Check if there is any room. */
10773 p = mempcpy (p, name, len);
10777 /* Output the current message now and start a new one. */
10780 fprintf (stream, "%s\n", message);
10782 left = size - (start - message) - len - 2;
10784 gas_assert (left >= 0);
10786 p = mempcpy (p, name, len);
10794 show_arch (FILE *stream, int ext, int check)
10796 static char message[] = MESSAGE_TEMPLATE;
10797 char *start = message + 27;
10799 int size = sizeof (MESSAGE_TEMPLATE);
10806 left = size - (start - message);
10807 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10809 /* Should it be skipped? */
10810 if (cpu_arch [j].skip)
10813 name = cpu_arch [j].name;
10814 len = cpu_arch [j].len;
10817 /* It is an extension. Skip if we aren't asked to show it. */
10828 /* It is an processor. Skip if we show only extension. */
10831 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10833 /* It is an impossible processor - skip. */
10837 p = output_message (stream, p, message, start, &left, name, len);
10840 /* Display disabled extensions. */
10842 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10844 name = cpu_noarch [j].name;
10845 len = cpu_noarch [j].len;
10846 p = output_message (stream, p, message, start, &left, name,
10851 fprintf (stream, "%s\n", message);
10855 md_show_usage (FILE *stream)
10857 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10858 fprintf (stream, _("\
10860 -V print assembler version number\n\
10863 fprintf (stream, _("\
10864 -n Do not optimize code alignment\n\
10865 -q quieten some warnings\n"));
10866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10867 fprintf (stream, _("\
10870 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10871 || defined (TE_PE) || defined (TE_PEP))
10872 fprintf (stream, _("\
10873 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10875 #ifdef SVR4_COMMENT_CHARS
10876 fprintf (stream, _("\
10877 --divide do not treat `/' as a comment character\n"));
10879 fprintf (stream, _("\
10880 --divide ignored\n"));
10882 fprintf (stream, _("\
10883 -march=CPU[,+EXTENSION...]\n\
10884 generate code for CPU and EXTENSION, CPU is one of:\n"));
10885 show_arch (stream, 0, 1);
10886 fprintf (stream, _("\
10887 EXTENSION is combination of:\n"));
10888 show_arch (stream, 1, 0);
10889 fprintf (stream, _("\
10890 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10891 show_arch (stream, 0, 0);
10892 fprintf (stream, _("\
10893 -msse2avx encode SSE instructions with VEX prefix\n"));
10894 fprintf (stream, _("\
10895 -msse-check=[none|error|warning]\n\
10896 check SSE instructions\n"));
10897 fprintf (stream, _("\
10898 -moperand-check=[none|error|warning]\n\
10899 check operand combinations for validity\n"));
10900 fprintf (stream, _("\
10901 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10903 fprintf (stream, _("\
10904 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10906 fprintf (stream, _("\
10907 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10908 for EVEX.W bit ignored instructions\n"));
10909 fprintf (stream, _("\
10910 -mevexrcig=[rne|rd|ru|rz]\n\
10911 encode EVEX instructions with specific EVEX.RC value\n\
10912 for SAE-only ignored instructions\n"));
10913 fprintf (stream, _("\
10914 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10915 fprintf (stream, _("\
10916 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10917 fprintf (stream, _("\
10918 -mindex-reg support pseudo index registers\n"));
10919 fprintf (stream, _("\
10920 -mnaked-reg don't require `%%' prefix for registers\n"));
10921 fprintf (stream, _("\
10922 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10923 fprintf (stream, _("\
10924 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10925 fprintf (stream, _("\
10926 -mshared disable branch optimization for shared code\n"));
10927 # if defined (TE_PE) || defined (TE_PEP)
10928 fprintf (stream, _("\
10929 -mbig-obj generate big object files\n"));
10931 fprintf (stream, _("\
10932 -momit-lock-prefix=[no|yes]\n\
10933 strip all lock prefixes\n"));
10934 fprintf (stream, _("\
10935 -mfence-as-lock-add=[no|yes]\n\
10936 encode lfence, mfence and sfence as\n\
10937 lock addl $0x0, (%%{re}sp)\n"));
10938 fprintf (stream, _("\
10939 -mrelax-relocations=[no|yes]\n\
10940 generate relax relocations\n"));
10941 fprintf (stream, _("\
10942 -mamd64 accept only AMD64 ISA\n"));
10943 fprintf (stream, _("\
10944 -mintel64 accept only Intel64 ISA\n"));
10947 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10948 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10949 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10951 /* Pick the target format to use. */
10954 i386_target_format (void)
10956 if (!strncmp (default_arch, "x86_64", 6))
10958 update_code_flag (CODE_64BIT, 1);
10959 if (default_arch[6] == '\0')
10960 x86_elf_abi = X86_64_ABI;
10962 x86_elf_abi = X86_64_X32_ABI;
10964 else if (!strcmp (default_arch, "i386"))
10965 update_code_flag (CODE_32BIT, 1);
10966 else if (!strcmp (default_arch, "iamcu"))
10968 update_code_flag (CODE_32BIT, 1);
10969 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10971 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10972 cpu_arch_name = "iamcu";
10973 cpu_sub_arch_name = NULL;
10974 cpu_arch_flags = iamcu_flags;
10975 cpu_arch_isa = PROCESSOR_IAMCU;
10976 cpu_arch_isa_flags = iamcu_flags;
10977 if (!cpu_arch_tune_set)
10979 cpu_arch_tune = cpu_arch_isa;
10980 cpu_arch_tune_flags = cpu_arch_isa_flags;
10983 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10984 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10988 as_fatal (_("unknown architecture"));
10990 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10991 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10992 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10993 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10995 switch (OUTPUT_FLAVOR)
10997 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10998 case bfd_target_aout_flavour:
10999 return AOUT_TARGET_FORMAT;
11001 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11002 # if defined (TE_PE) || defined (TE_PEP)
11003 case bfd_target_coff_flavour:
11004 if (flag_code == CODE_64BIT)
11005 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11008 # elif defined (TE_GO32)
11009 case bfd_target_coff_flavour:
11010 return "coff-go32";
11012 case bfd_target_coff_flavour:
11013 return "coff-i386";
11016 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11017 case bfd_target_elf_flavour:
11019 const char *format;
11021 switch (x86_elf_abi)
11024 format = ELF_TARGET_FORMAT;
11027 use_rela_relocations = 1;
11029 format = ELF_TARGET_FORMAT64;
11031 case X86_64_X32_ABI:
11032 use_rela_relocations = 1;
11034 disallow_64bit_reloc = 1;
11035 format = ELF_TARGET_FORMAT32;
11038 if (cpu_arch_isa == PROCESSOR_L1OM)
11040 if (x86_elf_abi != X86_64_ABI)
11041 as_fatal (_("Intel L1OM is 64bit only"));
11042 return ELF_TARGET_L1OM_FORMAT;
11044 else if (cpu_arch_isa == PROCESSOR_K1OM)
11046 if (x86_elf_abi != X86_64_ABI)
11047 as_fatal (_("Intel K1OM is 64bit only"));
11048 return ELF_TARGET_K1OM_FORMAT;
11050 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11052 if (x86_elf_abi != I386_ABI)
11053 as_fatal (_("Intel MCU is 32bit only"));
11054 return ELF_TARGET_IAMCU_FORMAT;
11060 #if defined (OBJ_MACH_O)
11061 case bfd_target_mach_o_flavour:
11062 if (flag_code == CODE_64BIT)
11064 use_rela_relocations = 1;
11066 return "mach-o-x86-64";
11069 return "mach-o-i386";
11077 #endif /* OBJ_MAYBE_ more than one */
11080 md_undefined_symbol (char *name)
11082 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11083 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11084 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11085 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11089 if (symbol_find (name))
11090 as_bad (_("GOT already in symbol table"));
11091 GOT_symbol = symbol_new (name, undefined_section,
11092 (valueT) 0, &zero_address_frag);
11099 /* Round up a section size to the appropriate boundary. */
11102 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11104 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11105 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11107 /* For a.out, force the section size to be aligned. If we don't do
11108 this, BFD will align it for us, but it will not write out the
11109 final bytes of the section. This may be a bug in BFD, but it is
11110 easier to fix it here since that is how the other a.out targets
11114 align = bfd_get_section_alignment (stdoutput, segment);
11115 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11122 /* On the i386, PC-relative offsets are relative to the start of the
11123 next instruction. That is, the address of the offset, plus its
11124 size, since the offset is always the last part of the insn. */
11127 md_pcrel_from (fixS *fixP)
11129 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11135 s_bss (int ignore ATTRIBUTE_UNUSED)
11139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11141 obj_elf_section_change_hook ();
11143 temp = get_absolute_expression ();
11144 subseg_set (bss_section, (subsegT) temp);
11145 demand_empty_rest_of_line ();
11151 i386_validate_fix (fixS *fixp)
11153 if (fixp->fx_subsy)
11155 if (fixp->fx_subsy == GOT_symbol)
11157 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11162 if (fixp->fx_tcbit2)
11163 fixp->fx_r_type = (fixp->fx_tcbit
11164 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11165 : BFD_RELOC_X86_64_GOTPCRELX);
11168 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11173 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11175 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11177 fixp->fx_subsy = 0;
11180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11181 else if (!object_64bit)
11183 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11184 && fixp->fx_tcbit2)
11185 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11191 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11194 bfd_reloc_code_real_type code;
11196 switch (fixp->fx_r_type)
11198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11199 case BFD_RELOC_SIZE32:
11200 case BFD_RELOC_SIZE64:
11201 if (S_IS_DEFINED (fixp->fx_addsy)
11202 && !S_IS_EXTERNAL (fixp->fx_addsy))
11204 /* Resolve size relocation against local symbol to size of
11205 the symbol plus addend. */
11206 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11207 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11208 && !fits_in_unsigned_long (value))
11209 as_bad_where (fixp->fx_file, fixp->fx_line,
11210 _("symbol size computation overflow"));
11211 fixp->fx_addsy = NULL;
11212 fixp->fx_subsy = NULL;
11213 md_apply_fix (fixp, (valueT *) &value, NULL);
11217 /* Fall through. */
11219 case BFD_RELOC_X86_64_PLT32:
11220 case BFD_RELOC_X86_64_GOT32:
11221 case BFD_RELOC_X86_64_GOTPCREL:
11222 case BFD_RELOC_X86_64_GOTPCRELX:
11223 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11224 case BFD_RELOC_386_PLT32:
11225 case BFD_RELOC_386_GOT32:
11226 case BFD_RELOC_386_GOT32X:
11227 case BFD_RELOC_386_GOTOFF:
11228 case BFD_RELOC_386_GOTPC:
11229 case BFD_RELOC_386_TLS_GD:
11230 case BFD_RELOC_386_TLS_LDM:
11231 case BFD_RELOC_386_TLS_LDO_32:
11232 case BFD_RELOC_386_TLS_IE_32:
11233 case BFD_RELOC_386_TLS_IE:
11234 case BFD_RELOC_386_TLS_GOTIE:
11235 case BFD_RELOC_386_TLS_LE_32:
11236 case BFD_RELOC_386_TLS_LE:
11237 case BFD_RELOC_386_TLS_GOTDESC:
11238 case BFD_RELOC_386_TLS_DESC_CALL:
11239 case BFD_RELOC_X86_64_TLSGD:
11240 case BFD_RELOC_X86_64_TLSLD:
11241 case BFD_RELOC_X86_64_DTPOFF32:
11242 case BFD_RELOC_X86_64_DTPOFF64:
11243 case BFD_RELOC_X86_64_GOTTPOFF:
11244 case BFD_RELOC_X86_64_TPOFF32:
11245 case BFD_RELOC_X86_64_TPOFF64:
11246 case BFD_RELOC_X86_64_GOTOFF64:
11247 case BFD_RELOC_X86_64_GOTPC32:
11248 case BFD_RELOC_X86_64_GOT64:
11249 case BFD_RELOC_X86_64_GOTPCREL64:
11250 case BFD_RELOC_X86_64_GOTPC64:
11251 case BFD_RELOC_X86_64_GOTPLT64:
11252 case BFD_RELOC_X86_64_PLTOFF64:
11253 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11254 case BFD_RELOC_X86_64_TLSDESC_CALL:
11255 case BFD_RELOC_RVA:
11256 case BFD_RELOC_VTABLE_ENTRY:
11257 case BFD_RELOC_VTABLE_INHERIT:
11259 case BFD_RELOC_32_SECREL:
11261 code = fixp->fx_r_type;
11263 case BFD_RELOC_X86_64_32S:
11264 if (!fixp->fx_pcrel)
11266 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11267 code = fixp->fx_r_type;
11270 /* Fall through. */
11272 if (fixp->fx_pcrel)
11274 switch (fixp->fx_size)
11277 as_bad_where (fixp->fx_file, fixp->fx_line,
11278 _("can not do %d byte pc-relative relocation"),
11280 code = BFD_RELOC_32_PCREL;
11282 case 1: code = BFD_RELOC_8_PCREL; break;
11283 case 2: code = BFD_RELOC_16_PCREL; break;
11284 case 4: code = BFD_RELOC_32_PCREL; break;
11286 case 8: code = BFD_RELOC_64_PCREL; break;
11292 switch (fixp->fx_size)
11295 as_bad_where (fixp->fx_file, fixp->fx_line,
11296 _("can not do %d byte relocation"),
11298 code = BFD_RELOC_32;
11300 case 1: code = BFD_RELOC_8; break;
11301 case 2: code = BFD_RELOC_16; break;
11302 case 4: code = BFD_RELOC_32; break;
11304 case 8: code = BFD_RELOC_64; break;
11311 if ((code == BFD_RELOC_32
11312 || code == BFD_RELOC_32_PCREL
11313 || code == BFD_RELOC_X86_64_32S)
11315 && fixp->fx_addsy == GOT_symbol)
11318 code = BFD_RELOC_386_GOTPC;
11320 code = BFD_RELOC_X86_64_GOTPC32;
11322 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11324 && fixp->fx_addsy == GOT_symbol)
11326 code = BFD_RELOC_X86_64_GOTPC64;
11329 rel = XNEW (arelent);
11330 rel->sym_ptr_ptr = XNEW (asymbol *);
11331 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11333 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11335 if (!use_rela_relocations)
11337 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11338 vtable entry to be used in the relocation's section offset. */
11339 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11340 rel->address = fixp->fx_offset;
11341 #if defined (OBJ_COFF) && defined (TE_PE)
11342 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11343 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11348 /* Use the rela in 64bit mode. */
11351 if (disallow_64bit_reloc)
11354 case BFD_RELOC_X86_64_DTPOFF64:
11355 case BFD_RELOC_X86_64_TPOFF64:
11356 case BFD_RELOC_64_PCREL:
11357 case BFD_RELOC_X86_64_GOTOFF64:
11358 case BFD_RELOC_X86_64_GOT64:
11359 case BFD_RELOC_X86_64_GOTPCREL64:
11360 case BFD_RELOC_X86_64_GOTPC64:
11361 case BFD_RELOC_X86_64_GOTPLT64:
11362 case BFD_RELOC_X86_64_PLTOFF64:
11363 as_bad_where (fixp->fx_file, fixp->fx_line,
11364 _("cannot represent relocation type %s in x32 mode"),
11365 bfd_get_reloc_code_name (code));
11371 if (!fixp->fx_pcrel)
11372 rel->addend = fixp->fx_offset;
11376 case BFD_RELOC_X86_64_PLT32:
11377 case BFD_RELOC_X86_64_GOT32:
11378 case BFD_RELOC_X86_64_GOTPCREL:
11379 case BFD_RELOC_X86_64_GOTPCRELX:
11380 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11381 case BFD_RELOC_X86_64_TLSGD:
11382 case BFD_RELOC_X86_64_TLSLD:
11383 case BFD_RELOC_X86_64_GOTTPOFF:
11384 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11385 case BFD_RELOC_X86_64_TLSDESC_CALL:
11386 rel->addend = fixp->fx_offset - fixp->fx_size;
11389 rel->addend = (section->vma
11391 + fixp->fx_addnumber
11392 + md_pcrel_from (fixp));
11397 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11398 if (rel->howto == NULL)
11400 as_bad_where (fixp->fx_file, fixp->fx_line,
11401 _("cannot represent relocation type %s"),
11402 bfd_get_reloc_code_name (code));
11403 /* Set howto to a garbage value so that we can keep going. */
11404 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11405 gas_assert (rel->howto != NULL);
11411 #include "tc-i386-intel.c"
11414 tc_x86_parse_to_dw2regnum (expressionS *exp)
11416 int saved_naked_reg;
11417 char saved_register_dot;
11419 saved_naked_reg = allow_naked_reg;
11420 allow_naked_reg = 1;
11421 saved_register_dot = register_chars['.'];
11422 register_chars['.'] = '.';
11423 allow_pseudo_reg = 1;
11424 expression_and_evaluate (exp);
11425 allow_pseudo_reg = 0;
11426 register_chars['.'] = saved_register_dot;
11427 allow_naked_reg = saved_naked_reg;
11429 if (exp->X_op == O_register && exp->X_add_number >= 0)
11431 if ((addressT) exp->X_add_number < i386_regtab_size)
11433 exp->X_op = O_constant;
11434 exp->X_add_number = i386_regtab[exp->X_add_number]
11435 .dw2_regnum[flag_code >> 1];
11438 exp->X_op = O_illegal;
11443 tc_x86_frame_initial_instructions (void)
11445 static unsigned int sp_regno[2];
11447 if (!sp_regno[flag_code >> 1])
11449 char *saved_input = input_line_pointer;
11450 char sp[][4] = {"esp", "rsp"};
11453 input_line_pointer = sp[flag_code >> 1];
11454 tc_x86_parse_to_dw2regnum (&exp);
11455 gas_assert (exp.X_op == O_constant);
11456 sp_regno[flag_code >> 1] = exp.X_add_number;
11457 input_line_pointer = saved_input;
11460 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11461 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11465 x86_dwarf2_addr_size (void)
11467 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11468 if (x86_elf_abi == X86_64_X32_ABI)
11471 return bfd_arch_bits_per_address (stdoutput) / 8;
11475 i386_elf_section_type (const char *str, size_t len)
11477 if (flag_code == CODE_64BIT
11478 && len == sizeof ("unwind") - 1
11479 && strncmp (str, "unwind", 6) == 0)
11480 return SHT_X86_64_UNWIND;
11487 i386_solaris_fix_up_eh_frame (segT sec)
11489 if (flag_code == CODE_64BIT)
11490 elf_section_type (sec) = SHT_X86_64_UNWIND;
11496 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11500 exp.X_op = O_secrel;
11501 exp.X_add_symbol = symbol;
11502 exp.X_add_number = 0;
11503 emit_expr (&exp, size);
11507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11508 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11511 x86_64_section_letter (int letter, const char **ptr_msg)
11513 if (flag_code == CODE_64BIT)
11516 return SHF_X86_64_LARGE;
11518 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11521 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11526 x86_64_section_word (char *str, size_t len)
11528 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11529 return SHF_X86_64_LARGE;
11535 handle_large_common (int small ATTRIBUTE_UNUSED)
11537 if (flag_code != CODE_64BIT)
11539 s_comm_internal (0, elf_common_parse);
11540 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11544 static segT lbss_section;
11545 asection *saved_com_section_ptr = elf_com_section_ptr;
11546 asection *saved_bss_section = bss_section;
11548 if (lbss_section == NULL)
11550 flagword applicable;
11551 segT seg = now_seg;
11552 subsegT subseg = now_subseg;
11554 /* The .lbss section is for local .largecomm symbols. */
11555 lbss_section = subseg_new (".lbss", 0);
11556 applicable = bfd_applicable_section_flags (stdoutput);
11557 bfd_set_section_flags (stdoutput, lbss_section,
11558 applicable & SEC_ALLOC);
11559 seg_info (lbss_section)->bss = 1;
11561 subseg_set (seg, subseg);
11564 elf_com_section_ptr = &_bfd_elf_large_com_section;
11565 bss_section = lbss_section;
11567 s_comm_internal (0, elf_common_parse);
11569 elf_com_section_ptr = saved_com_section_ptr;
11570 bss_section = saved_bss_section;
11573 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */