1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
847 CPU_BTVER1_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
849 CPU_BTVER2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
867 CPU_SSSE3_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
869 CPU_SSE4_1_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
879 CPU_AVX512F_FLAGS, 0 },
880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
881 CPU_AVX512CD_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
883 CPU_AVX512ER_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
885 CPU_AVX512PF_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
887 CPU_AVX512DQ_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
889 CPU_AVX512BW_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
891 CPU_AVX512VL_FLAGS, 0 },
892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
895 CPU_VMFUNC_FLAGS, 0 },
896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
899 CPU_XSAVE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
901 CPU_XSAVEOPT_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
905 CPU_XSAVES_FLAGS, 0 },
906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
909 CPU_PCLMUL_FLAGS, 0 },
910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 1 },
912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
913 CPU_FSGSBASE_FLAGS, 0 },
914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
915 CPU_RDRND_FLAGS, 0 },
916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
929 CPU_MOVBE_FLAGS, 0 },
930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
935 CPU_LZCNT_FLAGS, 0 },
936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
941 CPU_INVPCID_FLAGS, 0 },
942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
943 CPU_CLFLUSH_FLAGS, 0 },
944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
947 CPU_SYSCALL_FLAGS, 0 },
948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
949 CPU_RDTSCP_FLAGS, 0 },
950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
951 CPU_3DNOW_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
953 CPU_3DNOWA_FLAGS, 0 },
954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
955 CPU_PADLOCK_FLAGS, 0 },
956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
961 CPU_SSE4A_FLAGS, 0 },
962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
971 CPU_RDSEED_FLAGS, 0 },
972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
973 CPU_PRFCHW_FLAGS, 0 },
974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
981 CPU_CLFLUSHOPT_FLAGS, 0 },
982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
983 CPU_PREFETCHWT1_FLAGS, 0 },
984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
989 CPU_AVX512IFMA_FLAGS, 0 },
990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
991 CPU_AVX512VBMI_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
993 CPU_AVX512_4FMAPS_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4VNNIW_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VBMI2_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VNNI_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_BITALG_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1005 CPU_CLZERO_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1007 CPU_MWAITX_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1009 CPU_OSPKE_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1011 CPU_RDPID_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1013 CPU_PTWRITE_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1017 CPU_SHSTK_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1019 CPU_GFNI_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1021 CPU_VAES_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1023 CPU_VPCLMULQDQ_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1025 CPU_WBNOINVD_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1027 CPU_PCONFIG_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1029 CPU_WAITPKG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1031 CPU_CLDEMOTE_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1033 CPU_MOVDIRI_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIR64B_FLAGS, 0 },
1038 static const noarch_entry cpu_noarch[] =
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1071 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1072 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1076 /* Like s_lcomm_internal in gas/read.c but the alignment string
1077 is allowed to be optional. */
1080 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1087 && *input_line_pointer == ',')
1089 align = parse_align (needs_align - 1);
1091 if (align == (addressT) -1)
1106 bss_alloc (symbolP, size, align);
1111 pe_lcomm (int needs_align)
1113 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1117 const pseudo_typeS md_pseudo_table[] =
1119 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1120 {"align", s_align_bytes, 0},
1122 {"align", s_align_ptwo, 0},
1124 {"arch", set_cpu_arch, 0},
1128 {"lcomm", pe_lcomm, 1},
1130 {"ffloat", float_cons, 'f'},
1131 {"dfloat", float_cons, 'd'},
1132 {"tfloat", float_cons, 'x'},
1134 {"slong", signed_cons, 4},
1135 {"noopt", s_ignore, 0},
1136 {"optim", s_ignore, 0},
1137 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1138 {"code16", set_code_flag, CODE_16BIT},
1139 {"code32", set_code_flag, CODE_32BIT},
1141 {"code64", set_code_flag, CODE_64BIT},
1143 {"intel_syntax", set_intel_syntax, 1},
1144 {"att_syntax", set_intel_syntax, 0},
1145 {"intel_mnemonic", set_intel_mnemonic, 1},
1146 {"att_mnemonic", set_intel_mnemonic, 0},
1147 {"allow_index_reg", set_allow_index_reg, 1},
1148 {"disallow_index_reg", set_allow_index_reg, 0},
1149 {"sse_check", set_check, 0},
1150 {"operand_check", set_check, 1},
1151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1152 {"largecomm", handle_large_common, 0},
1154 {"file", dwarf2_directive_file, 0},
1155 {"loc", dwarf2_directive_loc, 0},
1156 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1159 {"secrel32", pe_directive_secrel, 0},
1164 /* For interface with expression (). */
1165 extern char *input_line_pointer;
1167 /* Hash table for instruction mnemonic lookup. */
1168 static struct hash_control *op_hash;
1170 /* Hash table for register lookup. */
1171 static struct hash_control *reg_hash;
1173 /* Various efficient no-op patterns for aligning code labels.
1174 Note: Don't try to assemble the instructions in the comments.
1175 0L and 0w are not legal. */
1176 static const unsigned char f32_1[] =
1178 static const unsigned char f32_2[] =
1179 {0x66,0x90}; /* xchg %ax,%ax */
1180 static const unsigned char f32_3[] =
1181 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1182 static const unsigned char f32_4[] =
1183 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1184 static const unsigned char f32_6[] =
1185 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1186 static const unsigned char f32_7[] =
1187 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1188 static const unsigned char f16_3[] =
1189 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1190 static const unsigned char f16_4[] =
1191 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1192 static const unsigned char jump_disp8[] =
1193 {0xeb}; /* jmp disp8 */
1194 static const unsigned char jump32_disp32[] =
1195 {0xe9}; /* jmp disp32 */
1196 static const unsigned char jump16_disp32[] =
1197 {0x66,0xe9}; /* jmp disp32 */
1198 /* 32-bit NOPs patterns. */
1199 static const unsigned char *const f32_patt[] = {
1200 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1202 /* 16-bit NOPs patterns. */
1203 static const unsigned char *const f16_patt[] = {
1204 f32_1, f32_2, f16_3, f16_4
1206 /* nopl (%[re]ax) */
1207 static const unsigned char alt_3[] =
1209 /* nopl 0(%[re]ax) */
1210 static const unsigned char alt_4[] =
1211 {0x0f,0x1f,0x40,0x00};
1212 /* nopl 0(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_5[] =
1214 {0x0f,0x1f,0x44,0x00,0x00};
1215 /* nopw 0(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_6[] =
1217 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1218 /* nopl 0L(%[re]ax) */
1219 static const unsigned char alt_7[] =
1220 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1221 /* nopl 0L(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_8[] =
1223 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* nopw 0L(%[re]ax,%[re]ax,1) */
1225 static const unsigned char alt_9[] =
1226 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1227 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1228 static const unsigned char alt_10[] =
1229 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1230 /* data16 nopw %cs:0L(%eax,%eax,1) */
1231 static const unsigned char alt_11[] =
1232 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1233 /* 32-bit and 64-bit NOPs patterns. */
1234 static const unsigned char *const alt_patt[] = {
1235 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1236 alt_9, alt_10, alt_11
1239 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1240 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1243 i386_output_nops (char *where, const unsigned char *const *patt,
1244 int count, int max_single_nop_size)
1247 /* Place the longer NOP first. */
1250 const unsigned char *nops = patt[max_single_nop_size - 1];
1252 /* Use the smaller one if the requsted one isn't available. */
1255 max_single_nop_size--;
1256 nops = patt[max_single_nop_size - 1];
1259 last = count % max_single_nop_size;
1262 for (offset = 0; offset < count; offset += max_single_nop_size)
1263 memcpy (where + offset, nops, max_single_nop_size);
1267 nops = patt[last - 1];
1270 /* Use the smaller one plus one-byte NOP if the needed one
1273 nops = patt[last - 1];
1274 memcpy (where + offset, nops, last);
1275 where[offset + last] = *patt[0];
1278 memcpy (where + offset, nops, last);
1283 fits_in_imm7 (offsetT num)
1285 return (num & 0x7f) == num;
1289 fits_in_imm31 (offsetT num)
1291 return (num & 0x7fffffff) == num;
1294 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1295 single NOP instruction LIMIT. */
1298 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1300 const unsigned char *const *patt = NULL;
1301 int max_single_nop_size;
1302 /* Maximum number of NOPs before switching to jump over NOPs. */
1303 int max_number_of_nops;
1305 switch (fragP->fr_type)
1314 /* We need to decide which NOP sequence to use for 32bit and
1315 64bit. When -mtune= is used:
1317 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1318 PROCESSOR_GENERIC32, f32_patt will be used.
1319 2. For the rest, alt_patt will be used.
1321 When -mtune= isn't used, alt_patt will be used if
1322 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1325 When -march= or .arch is used, we can't use anything beyond
1326 cpu_arch_isa_flags. */
1328 if (flag_code == CODE_16BIT)
1331 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1332 /* Limit number of NOPs to 2 in 16-bit mode. */
1333 max_number_of_nops = 2;
1337 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1339 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1340 switch (cpu_arch_tune)
1342 case PROCESSOR_UNKNOWN:
1343 /* We use cpu_arch_isa_flags to check if we SHOULD
1344 optimize with nops. */
1345 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1350 case PROCESSOR_PENTIUM4:
1351 case PROCESSOR_NOCONA:
1352 case PROCESSOR_CORE:
1353 case PROCESSOR_CORE2:
1354 case PROCESSOR_COREI7:
1355 case PROCESSOR_L1OM:
1356 case PROCESSOR_K1OM:
1357 case PROCESSOR_GENERIC64:
1359 case PROCESSOR_ATHLON:
1361 case PROCESSOR_AMDFAM10:
1363 case PROCESSOR_ZNVER:
1367 case PROCESSOR_I386:
1368 case PROCESSOR_I486:
1369 case PROCESSOR_PENTIUM:
1370 case PROCESSOR_PENTIUMPRO:
1371 case PROCESSOR_IAMCU:
1372 case PROCESSOR_GENERIC32:
1379 switch (fragP->tc_frag_data.tune)
1381 case PROCESSOR_UNKNOWN:
1382 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1383 PROCESSOR_UNKNOWN. */
1387 case PROCESSOR_I386:
1388 case PROCESSOR_I486:
1389 case PROCESSOR_PENTIUM:
1390 case PROCESSOR_IAMCU:
1392 case PROCESSOR_ATHLON:
1394 case PROCESSOR_AMDFAM10:
1396 case PROCESSOR_ZNVER:
1398 case PROCESSOR_GENERIC32:
1399 /* We use cpu_arch_isa_flags to check if we CAN optimize
1401 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1406 case PROCESSOR_PENTIUMPRO:
1407 case PROCESSOR_PENTIUM4:
1408 case PROCESSOR_NOCONA:
1409 case PROCESSOR_CORE:
1410 case PROCESSOR_CORE2:
1411 case PROCESSOR_COREI7:
1412 case PROCESSOR_L1OM:
1413 case PROCESSOR_K1OM:
1414 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1419 case PROCESSOR_GENERIC64:
1425 if (patt == f32_patt)
1427 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1428 /* Limit number of NOPs to 2 for older processors. */
1429 max_number_of_nops = 2;
1433 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1434 /* Limit number of NOPs to 7 for newer processors. */
1435 max_number_of_nops = 7;
1440 limit = max_single_nop_size;
1442 if (fragP->fr_type == rs_fill_nop)
1444 /* Output NOPs for .nop directive. */
1445 if (limit > max_single_nop_size)
1447 as_bad_where (fragP->fr_file, fragP->fr_line,
1448 _("invalid single nop size: %d "
1449 "(expect within [0, %d])"),
1450 limit, max_single_nop_size);
1455 fragP->fr_var = count;
1457 if ((count / max_single_nop_size) > max_number_of_nops)
1459 /* Generate jump over NOPs. */
1460 offsetT disp = count - 2;
1461 if (fits_in_imm7 (disp))
1463 /* Use "jmp disp8" if possible. */
1465 where[0] = jump_disp8[0];
1471 unsigned int size_of_jump;
1473 if (flag_code == CODE_16BIT)
1475 where[0] = jump16_disp32[0];
1476 where[1] = jump16_disp32[1];
1481 where[0] = jump32_disp32[0];
1485 count -= size_of_jump + 4;
1486 if (!fits_in_imm31 (count))
1488 as_bad_where (fragP->fr_file, fragP->fr_line,
1489 _("jump over nop padding out of range"));
1493 md_number_to_chars (where + size_of_jump, count, 4);
1494 where += size_of_jump + 4;
1498 /* Generate multiple NOPs. */
1499 i386_output_nops (where, patt, count, limit);
1503 operand_type_all_zero (const union i386_operand_type *x)
1505 switch (ARRAY_SIZE(x->array))
1516 return !x->array[0];
1523 operand_type_set (union i386_operand_type *x, unsigned int v)
1525 switch (ARRAY_SIZE(x->array))
1543 operand_type_equal (const union i386_operand_type *x,
1544 const union i386_operand_type *y)
1546 switch (ARRAY_SIZE(x->array))
1549 if (x->array[2] != y->array[2])
1553 if (x->array[1] != y->array[1])
1557 return x->array[0] == y->array[0];
1565 cpu_flags_all_zero (const union i386_cpu_flags *x)
1567 switch (ARRAY_SIZE(x->array))
1582 return !x->array[0];
1589 cpu_flags_equal (const union i386_cpu_flags *x,
1590 const union i386_cpu_flags *y)
1592 switch (ARRAY_SIZE(x->array))
1595 if (x->array[3] != y->array[3])
1599 if (x->array[2] != y->array[2])
1603 if (x->array[1] != y->array[1])
1607 return x->array[0] == y->array[0];
1615 cpu_flags_check_cpu64 (i386_cpu_flags f)
1617 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1618 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1621 static INLINE i386_cpu_flags
1622 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1624 switch (ARRAY_SIZE (x.array))
1627 x.array [3] &= y.array [3];
1630 x.array [2] &= y.array [2];
1633 x.array [1] &= y.array [1];
1636 x.array [0] &= y.array [0];
1644 static INLINE i386_cpu_flags
1645 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1647 switch (ARRAY_SIZE (x.array))
1650 x.array [3] |= y.array [3];
1653 x.array [2] |= y.array [2];
1656 x.array [1] |= y.array [1];
1659 x.array [0] |= y.array [0];
1667 static INLINE i386_cpu_flags
1668 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1670 switch (ARRAY_SIZE (x.array))
1673 x.array [3] &= ~y.array [3];
1676 x.array [2] &= ~y.array [2];
1679 x.array [1] &= ~y.array [1];
1682 x.array [0] &= ~y.array [0];
1690 #define CPU_FLAGS_ARCH_MATCH 0x1
1691 #define CPU_FLAGS_64BIT_MATCH 0x2
1693 #define CPU_FLAGS_PERFECT_MATCH \
1694 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1696 /* Return CPU flags match bits. */
1699 cpu_flags_match (const insn_template *t)
1701 i386_cpu_flags x = t->cpu_flags;
1702 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1704 x.bitfield.cpu64 = 0;
1705 x.bitfield.cpuno64 = 0;
1707 if (cpu_flags_all_zero (&x))
1709 /* This instruction is available on all archs. */
1710 match |= CPU_FLAGS_ARCH_MATCH;
1714 /* This instruction is available only on some archs. */
1715 i386_cpu_flags cpu = cpu_arch_flags;
1717 /* AVX512VL is no standalone feature - match it and then strip it. */
1718 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1720 x.bitfield.cpuavx512vl = 0;
1722 cpu = cpu_flags_and (x, cpu);
1723 if (!cpu_flags_all_zero (&cpu))
1725 if (x.bitfield.cpuavx)
1727 /* We need to check a few extra flags with AVX. */
1728 if (cpu.bitfield.cpuavx
1729 && (!t->opcode_modifier.sse2avx || sse2avx)
1730 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1731 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1732 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1735 else if (x.bitfield.cpuavx512f)
1737 /* We need to check a few extra flags with AVX512F. */
1738 if (cpu.bitfield.cpuavx512f
1739 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1740 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1741 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1742 match |= CPU_FLAGS_ARCH_MATCH;
1745 match |= CPU_FLAGS_ARCH_MATCH;
1751 static INLINE i386_operand_type
1752 operand_type_and (i386_operand_type x, i386_operand_type y)
1754 switch (ARRAY_SIZE (x.array))
1757 x.array [2] &= y.array [2];
1760 x.array [1] &= y.array [1];
1763 x.array [0] &= y.array [0];
1771 static INLINE i386_operand_type
1772 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1774 switch (ARRAY_SIZE (x.array))
1777 x.array [2] &= ~y.array [2];
1780 x.array [1] &= ~y.array [1];
1783 x.array [0] &= ~y.array [0];
1791 static INLINE i386_operand_type
1792 operand_type_or (i386_operand_type x, i386_operand_type y)
1794 switch (ARRAY_SIZE (x.array))
1797 x.array [2] |= y.array [2];
1800 x.array [1] |= y.array [1];
1803 x.array [0] |= y.array [0];
1811 static INLINE i386_operand_type
1812 operand_type_xor (i386_operand_type x, i386_operand_type y)
1814 switch (ARRAY_SIZE (x.array))
1817 x.array [2] ^= y.array [2];
1820 x.array [1] ^= y.array [1];
1823 x.array [0] ^= y.array [0];
1831 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1832 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1833 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1834 static const i386_operand_type inoutportreg
1835 = OPERAND_TYPE_INOUTPORTREG;
1836 static const i386_operand_type reg16_inoutportreg
1837 = OPERAND_TYPE_REG16_INOUTPORTREG;
1838 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1839 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1840 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1841 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1842 static const i386_operand_type anydisp
1843 = OPERAND_TYPE_ANYDISP;
1844 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1845 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1846 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1847 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1848 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1849 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1850 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1851 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1852 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1853 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1854 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1855 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1866 operand_type_check (i386_operand_type t, enum operand_type c)
1871 return t.bitfield.reg;
1874 return (t.bitfield.imm8
1878 || t.bitfield.imm32s
1879 || t.bitfield.imm64);
1882 return (t.bitfield.disp8
1883 || t.bitfield.disp16
1884 || t.bitfield.disp32
1885 || t.bitfield.disp32s
1886 || t.bitfield.disp64);
1889 return (t.bitfield.disp8
1890 || t.bitfield.disp16
1891 || t.bitfield.disp32
1892 || t.bitfield.disp32s
1893 || t.bitfield.disp64
1894 || t.bitfield.baseindex);
1903 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1904 operand J for instruction template T. */
1907 match_reg_size (const insn_template *t, unsigned int j)
1909 return !((i.types[j].bitfield.byte
1910 && !t->operand_types[j].bitfield.byte)
1911 || (i.types[j].bitfield.word
1912 && !t->operand_types[j].bitfield.word)
1913 || (i.types[j].bitfield.dword
1914 && !t->operand_types[j].bitfield.dword)
1915 || (i.types[j].bitfield.qword
1916 && !t->operand_types[j].bitfield.qword)
1917 || (i.types[j].bitfield.tbyte
1918 && !t->operand_types[j].bitfield.tbyte));
1921 /* Return 1 if there is no conflict in SIMD register on
1922 operand J for instruction template T. */
1925 match_simd_size (const insn_template *t, unsigned int j)
1927 return !((i.types[j].bitfield.xmmword
1928 && !t->operand_types[j].bitfield.xmmword)
1929 || (i.types[j].bitfield.ymmword
1930 && !t->operand_types[j].bitfield.ymmword)
1931 || (i.types[j].bitfield.zmmword
1932 && !t->operand_types[j].bitfield.zmmword));
1935 /* Return 1 if there is no conflict in any size on operand J for
1936 instruction template T. */
1939 match_mem_size (const insn_template *t, unsigned int j)
1941 return (match_reg_size (t, j)
1942 && !((i.types[j].bitfield.unspecified
1944 && !t->operand_types[j].bitfield.unspecified)
1945 || (i.types[j].bitfield.fword
1946 && !t->operand_types[j].bitfield.fword)
1947 /* For scalar opcode templates to allow register and memory
1948 operands at the same time, some special casing is needed
1949 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1950 down-conversion vpmov*. */
1951 || ((t->operand_types[j].bitfield.regsimd
1952 && !t->opcode_modifier.broadcast
1953 && (t->operand_types[j].bitfield.byte
1954 || t->operand_types[j].bitfield.word
1955 || t->operand_types[j].bitfield.dword
1956 || t->operand_types[j].bitfield.qword))
1957 ? (i.types[j].bitfield.xmmword
1958 || i.types[j].bitfield.ymmword
1959 || i.types[j].bitfield.zmmword)
1960 : !match_simd_size(t, j))));
1963 /* Return 1 if there is no size conflict on any operands for
1964 instruction template T. */
1967 operand_size_match (const insn_template *t)
1972 /* Don't check jump instructions. */
1973 if (t->opcode_modifier.jump
1974 || t->opcode_modifier.jumpbyte
1975 || t->opcode_modifier.jumpdword
1976 || t->opcode_modifier.jumpintersegment)
1979 /* Check memory and accumulator operand size. */
1980 for (j = 0; j < i.operands; j++)
1982 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1983 && t->operand_types[j].bitfield.anysize)
1986 if (t->operand_types[j].bitfield.reg
1987 && !match_reg_size (t, j))
1993 if (t->operand_types[j].bitfield.regsimd
1994 && !match_simd_size (t, j))
2000 if (t->operand_types[j].bitfield.acc
2001 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2007 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2016 else if (!t->opcode_modifier.d)
2019 i.error = operand_size_mismatch;
2023 /* Check reverse. */
2024 gas_assert (i.operands == 2);
2027 for (j = 0; j < 2; j++)
2029 if ((t->operand_types[j].bitfield.reg
2030 || t->operand_types[j].bitfield.acc)
2031 && !match_reg_size (t, j ? 0 : 1))
2034 if (i.types[j].bitfield.mem
2035 && !match_mem_size (t, j ? 0 : 1))
2043 operand_type_match (i386_operand_type overlap,
2044 i386_operand_type given)
2046 i386_operand_type temp = overlap;
2048 temp.bitfield.jumpabsolute = 0;
2049 temp.bitfield.unspecified = 0;
2050 temp.bitfield.byte = 0;
2051 temp.bitfield.word = 0;
2052 temp.bitfield.dword = 0;
2053 temp.bitfield.fword = 0;
2054 temp.bitfield.qword = 0;
2055 temp.bitfield.tbyte = 0;
2056 temp.bitfield.xmmword = 0;
2057 temp.bitfield.ymmword = 0;
2058 temp.bitfield.zmmword = 0;
2059 if (operand_type_all_zero (&temp))
2062 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2063 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2067 i.error = operand_type_mismatch;
2071 /* If given types g0 and g1 are registers they must be of the same type
2072 unless the expected operand type register overlap is null.
2073 Memory operand size of certain SIMD instructions is also being checked
2077 operand_type_register_match (i386_operand_type g0,
2078 i386_operand_type t0,
2079 i386_operand_type g1,
2080 i386_operand_type t1)
2082 if (!g0.bitfield.reg
2083 && !g0.bitfield.regsimd
2084 && (!operand_type_check (g0, anymem)
2085 || g0.bitfield.unspecified
2086 || !t0.bitfield.regsimd))
2089 if (!g1.bitfield.reg
2090 && !g1.bitfield.regsimd
2091 && (!operand_type_check (g1, anymem)
2092 || g1.bitfield.unspecified
2093 || !t1.bitfield.regsimd))
2096 if (g0.bitfield.byte == g1.bitfield.byte
2097 && g0.bitfield.word == g1.bitfield.word
2098 && g0.bitfield.dword == g1.bitfield.dword
2099 && g0.bitfield.qword == g1.bitfield.qword
2100 && g0.bitfield.xmmword == g1.bitfield.xmmword
2101 && g0.bitfield.ymmword == g1.bitfield.ymmword
2102 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2105 if (!(t0.bitfield.byte & t1.bitfield.byte)
2106 && !(t0.bitfield.word & t1.bitfield.word)
2107 && !(t0.bitfield.dword & t1.bitfield.dword)
2108 && !(t0.bitfield.qword & t1.bitfield.qword)
2109 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2110 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2111 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2114 i.error = register_type_mismatch;
2119 static INLINE unsigned int
2120 register_number (const reg_entry *r)
2122 unsigned int nr = r->reg_num;
2124 if (r->reg_flags & RegRex)
2127 if (r->reg_flags & RegVRex)
2133 static INLINE unsigned int
2134 mode_from_disp_size (i386_operand_type t)
2136 if (t.bitfield.disp8)
2138 else if (t.bitfield.disp16
2139 || t.bitfield.disp32
2140 || t.bitfield.disp32s)
2147 fits_in_signed_byte (addressT num)
2149 return num + 0x80 <= 0xff;
2153 fits_in_unsigned_byte (addressT num)
2159 fits_in_unsigned_word (addressT num)
2161 return num <= 0xffff;
2165 fits_in_signed_word (addressT num)
2167 return num + 0x8000 <= 0xffff;
2171 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2176 return num + 0x80000000 <= 0xffffffff;
2178 } /* fits_in_signed_long() */
2181 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2186 return num <= 0xffffffff;
2188 } /* fits_in_unsigned_long() */
2191 fits_in_disp8 (offsetT num)
2193 int shift = i.memshift;
2199 mask = (1 << shift) - 1;
2201 /* Return 0 if NUM isn't properly aligned. */
2205 /* Check if NUM will fit in 8bit after shift. */
2206 return fits_in_signed_byte (num >> shift);
2210 fits_in_imm4 (offsetT num)
2212 return (num & 0xf) == num;
2215 static i386_operand_type
2216 smallest_imm_type (offsetT num)
2218 i386_operand_type t;
2220 operand_type_set (&t, 0);
2221 t.bitfield.imm64 = 1;
2223 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2225 /* This code is disabled on the 486 because all the Imm1 forms
2226 in the opcode table are slower on the i486. They're the
2227 versions with the implicitly specified single-position
2228 displacement, which has another syntax if you really want to
2230 t.bitfield.imm1 = 1;
2231 t.bitfield.imm8 = 1;
2232 t.bitfield.imm8s = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2237 else if (fits_in_signed_byte (num))
2239 t.bitfield.imm8 = 1;
2240 t.bitfield.imm8s = 1;
2241 t.bitfield.imm16 = 1;
2242 t.bitfield.imm32 = 1;
2243 t.bitfield.imm32s = 1;
2245 else if (fits_in_unsigned_byte (num))
2247 t.bitfield.imm8 = 1;
2248 t.bitfield.imm16 = 1;
2249 t.bitfield.imm32 = 1;
2250 t.bitfield.imm32s = 1;
2252 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2254 t.bitfield.imm16 = 1;
2255 t.bitfield.imm32 = 1;
2256 t.bitfield.imm32s = 1;
2258 else if (fits_in_signed_long (num))
2260 t.bitfield.imm32 = 1;
2261 t.bitfield.imm32s = 1;
2263 else if (fits_in_unsigned_long (num))
2264 t.bitfield.imm32 = 1;
2270 offset_in_range (offsetT val, int size)
2276 case 1: mask = ((addressT) 1 << 8) - 1; break;
2277 case 2: mask = ((addressT) 1 << 16) - 1; break;
2278 case 4: mask = ((addressT) 2 << 31) - 1; break;
2280 case 8: mask = ((addressT) 2 << 63) - 1; break;
2286 /* If BFD64, sign extend val for 32bit address mode. */
2287 if (flag_code != CODE_64BIT
2288 || i.prefix[ADDR_PREFIX])
2289 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2290 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2293 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2295 char buf1[40], buf2[40];
2297 sprint_value (buf1, val);
2298 sprint_value (buf2, val & mask);
2299 as_warn (_("%s shortened to %s"), buf1, buf2);
2314 a. PREFIX_EXIST if attempting to add a prefix where one from the
2315 same class already exists.
2316 b. PREFIX_LOCK if lock prefix is added.
2317 c. PREFIX_REP if rep/repne prefix is added.
2318 d. PREFIX_DS if ds prefix is added.
2319 e. PREFIX_OTHER if other prefix is added.
2322 static enum PREFIX_GROUP
2323 add_prefix (unsigned int prefix)
2325 enum PREFIX_GROUP ret = PREFIX_OTHER;
2328 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2329 && flag_code == CODE_64BIT)
2331 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2332 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2333 && (prefix & (REX_R | REX_X | REX_B))))
2344 case DS_PREFIX_OPCODE:
2347 case CS_PREFIX_OPCODE:
2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
2361 case LOCK_PREFIX_OPCODE:
2370 case ADDR_PREFIX_OPCODE:
2374 case DATA_PREFIX_OPCODE:
2378 if (i.prefix[q] != 0)
2386 i.prefix[q] |= prefix;
2389 as_bad (_("same type of prefix used twice"));
2395 update_code_flag (int value, int check)
2397 PRINTF_LIKE ((*as_error));
2399 flag_code = (enum flag_code) value;
2400 if (flag_code == CODE_64BIT)
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2413 as_error = as_fatal;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2422 as_error = as_fatal;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
2428 stackop_size = '\0';
2432 set_code_flag (int value)
2434 update_code_flag (value, 0);
2438 set_16bit_gcc_code_flag (int new_code_flag)
2440 flag_code = (enum flag_code) new_code_flag;
2441 if (flag_code != CODE_16BIT)
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
2445 stackop_size = LONG_MNEM_SUFFIX;
2449 set_intel_syntax (int syntax_flag)
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2458 int e = get_symbol_name (&string);
2460 if (strcmp (string, "prefix") == 0)
2462 else if (strcmp (string, "noprefix") == 0)
2465 as_bad (_("bad argument to syntax directive."));
2466 (void) restore_line_pointer (e);
2468 demand_empty_rest_of_line ();
2470 intel_syntax = syntax_flag;
2472 if (ask_naked_reg == 0)
2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2476 allow_naked_reg = (ask_naked_reg < 0);
2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
2482 register_prefix = allow_naked_reg ? "" : "%";
2486 set_intel_mnemonic (int mnemonic_flag)
2488 intel_mnemonic = mnemonic_flag;
2492 set_allow_index_reg (int flag)
2494 allow_index_reg = flag;
2498 set_check (int what)
2500 enum check_kind *kind;
2505 kind = &operand_check;
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2519 int e = get_symbol_name (&string);
2521 if (strcmp (string, "none") == 0)
2523 else if (strcmp (string, "warning") == 0)
2524 *kind = check_warning;
2525 else if (strcmp (string, "error") == 0)
2526 *kind = check_error;
2528 as_bad (_("bad argument to %s_check directive."), str);
2529 (void) restore_line_pointer (e);
2532 as_bad (_("missing argument for %s_check directive"), str);
2534 demand_empty_rest_of_line ();
2538 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2544 /* Intel LIOM is only supported on ELF. */
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2554 arch = default_arch;
2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2562 /* If we are targeting Intel L1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2564 || new_flag.bitfield.cpul1om)
2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2577 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2584 int e = get_symbol_name (&string);
2586 i386_cpu_flags flags;
2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2590 if (strcmp (string, cpu_arch[j].name) == 0)
2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2596 cpu_arch_name = cpu_arch[j].name;
2597 cpu_sub_arch_name = NULL;
2598 cpu_arch_flags = cpu_arch[j].flags;
2599 if (flag_code == CODE_64BIT)
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
2611 if (!cpu_arch_tune_set)
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2619 flags = cpu_flags_or (cpu_arch_flags,
2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2624 if (cpu_sub_arch_name)
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
2629 (const char *) NULL);
2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2634 cpu_arch_flags = flags;
2635 cpu_arch_isa_flags = flags;
2639 = cpu_flags_or (cpu_arch_isa_flags,
2641 (void) restore_line_pointer (e);
2642 demand_empty_rest_of_line ();
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2649 /* Disable an ISA extension. */
2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2657 if (cpu_sub_arch_name)
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2674 j = ARRAY_SIZE (cpu_arch);
2677 if (j >= ARRAY_SIZE (cpu_arch))
2678 as_bad (_("no such architecture: `%s'"), string);
2680 *input_line_pointer = e;
2683 as_bad (_("missing cpu architecture"));
2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2702 (void) restore_line_pointer (e);
2705 demand_empty_rest_of_line ();
2708 enum bfd_architecture
2711 if (cpu_arch_isa == PROCESSOR_L1OM)
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2733 return bfd_arch_i386;
2739 if (!strncmp (default_arch, "x86_64", 6))
2741 if (cpu_arch_isa == PROCESSOR_L1OM)
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2755 else if (default_arch[6] == '\0')
2756 return bfd_mach_x86_64;
2758 return bfd_mach_x64_32;
2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2770 return bfd_mach_i386_i386;
2773 as_fatal (_("unknown architecture"));
2779 const char *hash_err;
2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2784 /* Initialize op_hash hash table. */
2785 op_hash = hash_new ();
2788 const insn_template *optab;
2789 templates *core_optab;
2791 /* Setup for loop. */
2793 core_optab = XNEW (templates);
2794 core_optab->start = optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2802 /* different name --> ship out current template list;
2803 add to hash table; & begin anew. */
2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2807 (void *) core_optab);
2810 as_fatal (_("can't hash %s: %s"),
2814 if (optab->name == NULL)
2816 core_optab = XNEW (templates);
2817 core_optab->start = optab;
2822 /* Initialize reg_hash hash table. */
2823 reg_hash = hash_new ();
2825 const reg_entry *regtab;
2826 unsigned int regtab_size = i386_regtab_size;
2828 for (regtab = i386_regtab; regtab_size--; regtab++)
2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2832 as_fatal (_("can't hash %s: %s"),
2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2843 for (c = 0; c < 256; c++)
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2852 else if (ISLOWER (c))
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2858 else if (ISUPPER (c))
2860 mnemonic_chars[c] = TOLOWER (c);
2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2864 else if (c == '{' || c == '}')
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2870 if (ISALPHA (c) || ISDIGIT (c))
2871 identifier_chars[c] = c;
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2880 identifier_chars['@'] = '@';
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
2886 digit_chars['-'] = '-';
2887 mnemonic_chars['_'] = '_';
2888 mnemonic_chars['-'] = '-';
2889 mnemonic_chars['.'] = '.';
2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2897 if (flag_code == CODE_64BIT)
2899 #if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2903 x86_dwarf2_return_column = 16;
2905 x86_cie_data_alignment = -8;
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2915 i386_print_statistics (FILE *file)
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2923 /* Debugging routines for md_assemble. */
2924 static void pte (insn_template *);
2925 static void pt (i386_operand_type);
2926 static void pe (expressionS *);
2927 static void ps (symbolS *);
2930 pi (char *line, i386_insn *x)
2934 fprintf (stdout, "%s: template ", line);
2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2941 x->rm.mode, x->rm.reg, x->rm.regmem);
2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
2949 for (j = 0; j < x->operands; j++)
2951 fprintf (stdout, " #%d: ", j + 1);
2953 fprintf (stdout, "\n");
2954 if (x->types[j].bitfield.reg
2955 || x->types[j].bitfield.regmmx
2956 || x->types[j].bitfield.regsimd
2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
2971 pte (insn_template *t)
2974 fprintf (stdout, " %d operands ", t->operands);
2975 fprintf (stdout, "opcode %x ", t->base_opcode);
2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
2978 if (t->opcode_modifier.d)
2979 fprintf (stdout, "D");
2980 if (t->opcode_modifier.w)
2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
2983 for (j = 0; j < t->operands; j++)
2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
2987 fprintf (stdout, "\n");
2994 fprintf (stdout, " operation %d\n", e->X_op);
2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
2997 if (e->X_add_symbol)
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3014 fprintf (stdout, "%s type %s%s",
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3020 static struct type_name
3022 i386_operand_type mask;
3025 const type_names[] =
3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
3057 { OPERAND_TYPE_REGYMM, "rYMM" },
3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
3060 { OPERAND_TYPE_ESSEG, "es" },
3064 pt (i386_operand_type t)
3067 i386_operand_type a;
3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3071 a = operand_type_and (t, type_names[j].mask);
3072 if (!operand_type_all_zero (&a))
3073 fprintf (stdout, "%s, ", type_names[j].name);
3078 #endif /* DEBUG386 */
3080 static bfd_reloc_code_real_type
3081 reloc (unsigned int size,
3084 bfd_reloc_code_real_type other)
3086 if (other != NO_RELOC)
3088 reloc_howto_type *rel;
3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3119 if (other == BFD_RELOC_SIZE32)
3122 other = BFD_RELOC_SIZE64;
3125 as_bad (_("there are no pc-relative size relocations"));
3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3137 as_bad (_("unknown relocation (%u)"), other);
3138 else if (size != bfd_get_reloc_size (rel))
3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3140 bfd_get_reloc_size (rel),
3142 else if (pcrel && !rel->pc_relative)
3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3146 || (rel->complain_on_overflow == complain_overflow_unsigned
3148 as_bad (_("relocated field and relocation type differ in signedness"));
3157 as_bad (_("there are no unsigned pc-relative relocations"));
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
3162 case 4: return BFD_RELOC_32_PCREL;
3163 case 8: return BFD_RELOC_64_PCREL;
3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3172 case 4: return BFD_RELOC_X86_64_32S;
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
3189 /* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3195 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3255 intel_float_operand (const char *mnemonic)
3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3264 switch (mnemonic[1])
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3270 return 2 /* integer op */;
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3288 switch (mnemonic[3])
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3307 /* Build the VEX prefix. */
3310 build_vex_prefix (const insn_template *t)
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3324 register_specifier = 0xf;
3326 /* Use 2-byte VEX prefix by swapping destination and source
3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
3330 && i.operands == i.reg_operands
3331 && i.tm.opcode_modifier.vexopcode == VEX0F
3332 && i.tm.opcode_modifier.load
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3346 gas_assert (i.rm.mode == 3);
3350 i.rm.regmem = i.rm.reg;
3353 /* Use the next insn. */
3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
3359 else if (i.tm.opcode_modifier.vex == VEX256)
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3381 case DATA_PREFIX_OPCODE:
3384 case REPE_PREFIX_OPCODE:
3387 case REPNE_PREFIX_OPCODE:
3394 /* Use 2-byte VEX prefix if possible. */
3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
3397 && i.tm.opcode_modifier.vexw != VEXW1
3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3400 /* 2-byte VEX prefix. */
3404 i.vex.bytes[0] = 0xc5;
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3415 /* 3-byte VEX prefix. */
3420 switch (i.tm.opcode_modifier.vexopcode)
3424 i.vex.bytes[0] = 0xc4;
3428 i.vex.bytes[0] = 0xc4;
3432 i.vex.bytes[0] = 0xc4;
3436 i.vex.bytes[0] = 0x8f;
3440 i.vex.bytes[0] = 0x8f;
3444 i.vex.bytes[0] = 0x8f;
3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3466 static INLINE bfd_boolean
3467 is_evex_encoding (const insn_template *t)
3469 return t->opcode_modifier.evex
3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3474 /* Build the EVEX prefix. */
3477 build_evex_prefix (void)
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3482 rex_byte vrex_used = 0;
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3487 gas_assert ((i.vrex & REX_X) == 0);
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3500 register_specifier = 0xf;
3502 /* Encode upper 16 vector index register in the fourth byte of
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3515 case DATA_PREFIX_OPCODE:
3518 case REPE_PREFIX_OPCODE:
3521 case REPNE_PREFIX_OPCODE:
3528 /* 4 byte EVEX prefix. */
3530 i.vex.bytes[0] = 0x62;
3533 switch (i.tm.opcode_modifier.vexopcode)
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3569 i.vex.bytes[1] &= ~0x40;
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3584 /* If w is not set it means we are dealing with WIG instruction. */
3587 if (evexwig == evexw1)
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3602 /* Don't always set the broadcast bit if there is no RC. */
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
3631 switch (i.tm.opcode_modifier.evex)
3633 case EVEXLIG: /* LL' is ignored */
3634 vec_length = evexlig << 5;
3637 vec_length = 0 << 5;
3640 vec_length = 1 << 5;
3643 vec_length = 2 << 5;
3649 i.vex.bytes[3] |= vec_length;
3650 /* Encode the broadcast bit. */
3652 i.vex.bytes[3] |= 0x10;
3656 if (i.rounding->type != saeonly)
3657 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3659 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3662 if (i.mask && i.mask->mask)
3663 i.vex.bytes[3] |= i.mask->mask->reg_num;
3667 process_immext (void)
3671 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3674 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3675 with an opcode suffix which is coded in the same place as an
3676 8-bit immediate field would be.
3677 Here we check those operands and remove them afterwards. */
3680 for (x = 0; x < i.operands; x++)
3681 if (register_number (i.op[x].regs) != x)
3682 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3683 register_prefix, i.op[x].regs->reg_name, x + 1,
3689 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3691 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3692 suffix which is coded in the same place as an 8-bit immediate
3694 Here we check those operands and remove them afterwards. */
3697 if (i.operands != 3)
3700 for (x = 0; x < 2; x++)
3701 if (register_number (i.op[x].regs) != x)
3702 goto bad_register_operand;
3704 /* Check for third operand for mwaitx/monitorx insn. */
3705 if (register_number (i.op[x].regs)
3706 != (x + (i.tm.extension_opcode == 0xfb)))
3708 bad_register_operand:
3709 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3710 register_prefix, i.op[x].regs->reg_name, x+1,
3717 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3718 which is coded in the same place as an 8-bit immediate field
3719 would be. Here we fake an 8-bit immediate operand from the
3720 opcode suffix stored in tm.extension_opcode.
3722 AVX instructions also use this encoding, for some of
3723 3 argument instructions. */
3725 gas_assert (i.imm_operands <= 1
3727 || ((i.tm.opcode_modifier.vex
3728 || i.tm.opcode_modifier.vexopcode
3729 || is_evex_encoding (&i.tm))
3730 && i.operands <= 4)));
3732 exp = &im_expressions[i.imm_operands++];
3733 i.op[i.operands].imms = exp;
3734 i.types[i.operands] = imm8;
3736 exp->X_op = O_constant;
3737 exp->X_add_number = i.tm.extension_opcode;
3738 i.tm.extension_opcode = None;
3745 switch (i.tm.opcode_modifier.hleprefixok)
3750 as_bad (_("invalid instruction `%s' after `%s'"),
3751 i.tm.name, i.hle_prefix);
3754 if (i.prefix[LOCK_PREFIX])
3756 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3760 case HLEPrefixRelease:
3761 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3763 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3767 if (i.mem_operands == 0
3768 || !operand_type_check (i.types[i.operands - 1], anymem))
3770 as_bad (_("memory destination needed for instruction `%s'"
3771 " after `xrelease'"), i.tm.name);
3778 /* Try the shortest encoding by shortening operand size. */
3781 optimize_encoding (void)
3785 if (optimize_for_space
3786 && i.reg_operands == 1
3787 && i.imm_operands == 1
3788 && !i.types[1].bitfield.byte
3789 && i.op[0].imms->X_op == O_constant
3790 && fits_in_imm7 (i.op[0].imms->X_add_number)
3791 && ((i.tm.base_opcode == 0xa8
3792 && i.tm.extension_opcode == None)
3793 || (i.tm.base_opcode == 0xf6
3794 && i.tm.extension_opcode == 0x0)))
3797 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3799 unsigned int base_regnum = i.op[1].regs->reg_num;
3800 if (flag_code == CODE_64BIT || base_regnum < 4)
3802 i.types[1].bitfield.byte = 1;
3803 /* Ignore the suffix. */
3805 if (base_regnum >= 4
3806 && !(i.op[1].regs->reg_flags & RegRex))
3808 /* Handle SP, BP, SI and DI registers. */
3809 if (i.types[1].bitfield.word)
3811 else if (i.types[1].bitfield.dword)
3819 else if (flag_code == CODE_64BIT
3820 && ((i.types[1].bitfield.qword
3821 && i.reg_operands == 1
3822 && i.imm_operands == 1
3823 && i.op[0].imms->X_op == O_constant
3824 && ((i.tm.base_opcode == 0xb0
3825 && i.tm.extension_opcode == None
3826 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3827 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3828 && (((i.tm.base_opcode == 0x24
3829 || i.tm.base_opcode == 0xa8)
3830 && i.tm.extension_opcode == None)
3831 || (i.tm.base_opcode == 0x80
3832 && i.tm.extension_opcode == 0x4)
3833 || ((i.tm.base_opcode == 0xf6
3834 || i.tm.base_opcode == 0xc6)
3835 && i.tm.extension_opcode == 0x0)))))
3836 || (i.types[0].bitfield.qword
3837 && ((i.reg_operands == 2
3838 && i.op[0].regs == i.op[1].regs
3839 && ((i.tm.base_opcode == 0x30
3840 || i.tm.base_opcode == 0x28)
3841 && i.tm.extension_opcode == None))
3842 || (i.reg_operands == 1
3844 && i.tm.base_opcode == 0x30
3845 && i.tm.extension_opcode == None)))))
3848 andq $imm31, %r64 -> andl $imm31, %r32
3849 testq $imm31, %r64 -> testl $imm31, %r32
3850 xorq %r64, %r64 -> xorl %r32, %r32
3851 subq %r64, %r64 -> subl %r32, %r32
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3855 i.tm.opcode_modifier.norex64 = 1;
3856 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3859 movq $imm31, %r64 -> movl $imm31, %r32
3860 movq $imm32, %r64 -> movl $imm32, %r32
3862 i.tm.operand_types[0].bitfield.imm32 = 1;
3863 i.tm.operand_types[0].bitfield.imm32s = 0;
3864 i.tm.operand_types[0].bitfield.imm64 = 0;
3865 i.types[0].bitfield.imm32 = 1;
3866 i.types[0].bitfield.imm32s = 0;
3867 i.types[0].bitfield.imm64 = 0;
3868 i.types[1].bitfield.dword = 1;
3869 i.types[1].bitfield.qword = 0;
3870 if (i.tm.base_opcode == 0xc6)
3873 movq $imm31, %r64 -> movl $imm31, %r32
3875 i.tm.base_opcode = 0xb0;
3876 i.tm.extension_opcode = None;
3877 i.tm.opcode_modifier.shortform = 1;
3878 i.tm.opcode_modifier.modrm = 0;
3882 else if (optimize > 1
3883 && i.reg_operands == 3
3884 && i.op[0].regs == i.op[1].regs
3885 && !i.types[2].bitfield.xmmword
3886 && (i.tm.opcode_modifier.vex
3887 || ((!i.mask || i.mask->zeroing)
3889 && is_evex_encoding (&i.tm)
3890 && (i.vec_encoding != vex_encoding_evex
3891 || i.tm.cpu_flags.bitfield.cpuavx512vl
3892 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3893 && ((i.tm.base_opcode == 0x55
3894 || i.tm.base_opcode == 0x6655
3895 || i.tm.base_opcode == 0x66df
3896 || i.tm.base_opcode == 0x57
3897 || i.tm.base_opcode == 0x6657
3898 || i.tm.base_opcode == 0x66ef
3899 || i.tm.base_opcode == 0x66f8
3900 || i.tm.base_opcode == 0x66f9
3901 || i.tm.base_opcode == 0x66fa
3902 || i.tm.base_opcode == 0x66fb)
3903 && i.tm.extension_opcode == None))
3906 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 VEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX VOP %xmmM, %xmmM, %xmmN
3916 VOP, one of vpandn and vpxor:
3917 VEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX VOP %xmmM, %xmmM, %xmmN
3919 VOP, one of vpandnd and vpandnq:
3920 EVEX VOP %zmmM, %zmmM, %zmmN
3921 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3922 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3923 EVEX VOP %ymmM, %ymmM, %ymmN
3924 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3925 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3926 VOP, one of vpxord and vpxorq:
3927 EVEX VOP %zmmM, %zmmM, %zmmN
3928 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3929 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3930 EVEX VOP %ymmM, %ymmM, %ymmN
3931 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3934 if (is_evex_encoding (&i.tm))
3936 if (i.vec_encoding == vex_encoding_evex)
3937 i.tm.opcode_modifier.evex = EVEX128;
3940 i.tm.opcode_modifier.vex = VEX128;
3941 i.tm.opcode_modifier.vexw = VEXW0;
3942 i.tm.opcode_modifier.evex = 0;
3946 i.tm.opcode_modifier.vex = VEX128;
3948 if (i.tm.opcode_modifier.vex)
3949 for (j = 0; j < 3; j++)
3951 i.types[j].bitfield.xmmword = 1;
3952 i.types[j].bitfield.ymmword = 0;
3957 /* This is the guts of the machine-dependent assembler. LINE points to a
3958 machine dependent instruction. This function is supposed to emit
3959 the frags/bytes it assembles to. */
3962 md_assemble (char *line)
3965 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3966 const insn_template *t;
3968 /* Initialize globals. */
3969 memset (&i, '\0', sizeof (i));
3970 for (j = 0; j < MAX_OPERANDS; j++)
3971 i.reloc[j] = NO_RELOC;
3972 memset (disp_expressions, '\0', sizeof (disp_expressions));
3973 memset (im_expressions, '\0', sizeof (im_expressions));
3974 save_stack_p = save_stack;
3976 /* First parse an instruction mnemonic & call i386_operand for the operands.
3977 We assume that the scrubber has arranged it so that line[0] is the valid
3978 start of a (possibly prefixed) mnemonic. */
3980 line = parse_insn (line, mnemonic);
3983 mnem_suffix = i.suffix;
3985 line = parse_operands (line, mnemonic);
3987 xfree (i.memop1_string);
3988 i.memop1_string = NULL;
3992 /* Now we've parsed the mnemonic into a set of templates, and have the
3993 operands at hand. */
3995 /* All intel opcodes have reversed operands except for "bound" and
3996 "enter". We also don't reverse intersegment "jmp" and "call"
3997 instructions with 2 immediate operands so that the immediate segment
3998 precedes the offset, as it does when in AT&T mode. */
4001 && (strcmp (mnemonic, "bound") != 0)
4002 && (strcmp (mnemonic, "invlpga") != 0)
4003 && !(operand_type_check (i.types[0], imm)
4004 && operand_type_check (i.types[1], imm)))
4007 /* The order of the immediates should be reversed
4008 for 2 immediates extrq and insertq instructions */
4009 if (i.imm_operands == 2
4010 && (strcmp (mnemonic, "extrq") == 0
4011 || strcmp (mnemonic, "insertq") == 0))
4012 swap_2_operands (0, 1);
4017 /* Don't optimize displacement for movabs since it only takes 64bit
4020 && i.disp_encoding != disp_encoding_32bit
4021 && (flag_code != CODE_64BIT
4022 || strcmp (mnemonic, "movabs") != 0))
4025 /* Next, we find a template that matches the given insn,
4026 making sure the overlap of the given operands types is consistent
4027 with the template operand types. */
4029 if (!(t = match_template (mnem_suffix)))
4032 if (sse_check != check_none
4033 && !i.tm.opcode_modifier.noavx
4034 && !i.tm.cpu_flags.bitfield.cpuavx
4035 && (i.tm.cpu_flags.bitfield.cpusse
4036 || i.tm.cpu_flags.bitfield.cpusse2
4037 || i.tm.cpu_flags.bitfield.cpusse3
4038 || i.tm.cpu_flags.bitfield.cpussse3
4039 || i.tm.cpu_flags.bitfield.cpusse4_1
4040 || i.tm.cpu_flags.bitfield.cpusse4_2
4041 || i.tm.cpu_flags.bitfield.cpupclmul
4042 || i.tm.cpu_flags.bitfield.cpuaes
4043 || i.tm.cpu_flags.bitfield.cpugfni))
4045 (sse_check == check_warning
4047 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4050 /* Zap movzx and movsx suffix. The suffix has been set from
4051 "word ptr" or "byte ptr" on the source operand in Intel syntax
4052 or extracted from mnemonic in AT&T syntax. But we'll use
4053 the destination register to choose the suffix for encoding. */
4054 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4056 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4057 there is no suffix, the default will be byte extension. */
4058 if (i.reg_operands != 2
4061 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4066 if (i.tm.opcode_modifier.fwait)
4067 if (!add_prefix (FWAIT_OPCODE))
4070 /* Check if REP prefix is OK. */
4071 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4073 as_bad (_("invalid instruction `%s' after `%s'"),
4074 i.tm.name, i.rep_prefix);
4078 /* Check for lock without a lockable instruction. Destination operand
4079 must be memory unless it is xchg (0x86). */
4080 if (i.prefix[LOCK_PREFIX]
4081 && (!i.tm.opcode_modifier.islockable
4082 || i.mem_operands == 0
4083 || (i.tm.base_opcode != 0x86
4084 && !operand_type_check (i.types[i.operands - 1], anymem))))
4086 as_bad (_("expecting lockable instruction after `lock'"));
4090 /* Check if HLE prefix is OK. */
4091 if (i.hle_prefix && !check_hle ())
4094 /* Check BND prefix. */
4095 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4096 as_bad (_("expecting valid branch instruction after `bnd'"));
4098 /* Check NOTRACK prefix. */
4099 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4100 as_bad (_("expecting indirect branch instruction after `notrack'"));
4102 if (i.tm.cpu_flags.bitfield.cpumpx)
4104 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4105 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4106 else if (flag_code != CODE_16BIT
4107 ? i.prefix[ADDR_PREFIX]
4108 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4109 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4112 /* Insert BND prefix. */
4114 && i.tm.opcode_modifier.bndprefixok
4115 && !i.prefix[BND_PREFIX])
4116 add_prefix (BND_PREFIX_OPCODE);
4118 /* Check string instruction segment overrides. */
4119 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4121 if (!check_string ())
4123 i.disp_operands = 0;
4126 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4127 optimize_encoding ();
4129 if (!process_suffix ())
4132 /* Update operand types. */
4133 for (j = 0; j < i.operands; j++)
4134 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4136 /* Make still unresolved immediate matches conform to size of immediate
4137 given in i.suffix. */
4138 if (!finalize_imm ())
4141 if (i.types[0].bitfield.imm1)
4142 i.imm_operands = 0; /* kludge for shift insns. */
4144 /* We only need to check those implicit registers for instructions
4145 with 3 operands or less. */
4146 if (i.operands <= 3)
4147 for (j = 0; j < i.operands; j++)
4148 if (i.types[j].bitfield.inoutportreg
4149 || i.types[j].bitfield.shiftcount
4150 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4153 /* ImmExt should be processed after SSE2AVX. */
4154 if (!i.tm.opcode_modifier.sse2avx
4155 && i.tm.opcode_modifier.immext)
4158 /* For insns with operands there are more diddles to do to the opcode. */
4161 if (!process_operands ())
4164 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4166 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4167 as_warn (_("translating to `%sp'"), i.tm.name);
4170 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4171 || is_evex_encoding (&i.tm))
4173 if (flag_code == CODE_16BIT)
4175 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4180 if (i.tm.opcode_modifier.vex)
4181 build_vex_prefix (t);
4183 build_evex_prefix ();
4186 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4187 instructions may define INT_OPCODE as well, so avoid this corner
4188 case for those instructions that use MODRM. */
4189 if (i.tm.base_opcode == INT_OPCODE
4190 && !i.tm.opcode_modifier.modrm
4191 && i.op[0].imms->X_add_number == 3)
4193 i.tm.base_opcode = INT3_OPCODE;
4197 if ((i.tm.opcode_modifier.jump
4198 || i.tm.opcode_modifier.jumpbyte
4199 || i.tm.opcode_modifier.jumpdword)
4200 && i.op[0].disps->X_op == O_constant)
4202 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4203 the absolute address given by the constant. Since ix86 jumps and
4204 calls are pc relative, we need to generate a reloc. */
4205 i.op[0].disps->X_add_symbol = &abs_symbol;
4206 i.op[0].disps->X_op = O_symbol;
4209 if (i.tm.opcode_modifier.rex64)
4212 /* For 8 bit registers we need an empty rex prefix. Also if the
4213 instruction already has a prefix, we need to convert old
4214 registers to new ones. */
4216 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4217 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4218 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4219 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4220 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4221 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4226 i.rex |= REX_OPCODE;
4227 for (x = 0; x < 2; x++)
4229 /* Look for 8 bit operand that uses old registers. */
4230 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4231 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4233 /* In case it is "hi" register, give up. */
4234 if (i.op[x].regs->reg_num > 3)
4235 as_bad (_("can't encode register '%s%s' in an "
4236 "instruction requiring REX prefix."),
4237 register_prefix, i.op[x].regs->reg_name);
4239 /* Otherwise it is equivalent to the extended register.
4240 Since the encoding doesn't change this is merely
4241 cosmetic cleanup for debug output. */
4243 i.op[x].regs = i.op[x].regs + 8;
4248 if (i.rex == 0 && i.rex_encoding)
4250 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4251 that uses legacy register. If it is "hi" register, don't add
4252 the REX_OPCODE byte. */
4254 for (x = 0; x < 2; x++)
4255 if (i.types[x].bitfield.reg
4256 && i.types[x].bitfield.byte
4257 && (i.op[x].regs->reg_flags & RegRex64) == 0
4258 && i.op[x].regs->reg_num > 3)
4260 i.rex_encoding = FALSE;
4269 add_prefix (REX_OPCODE | i.rex);
4271 /* We are ready to output the insn. */
4276 parse_insn (char *line, char *mnemonic)
4279 char *token_start = l;
4282 const insn_template *t;
4288 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4293 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4295 as_bad (_("no such instruction: `%s'"), token_start);
4300 if (!is_space_char (*l)
4301 && *l != END_OF_INSN
4303 || (*l != PREFIX_SEPARATOR
4306 as_bad (_("invalid character %s in mnemonic"),
4307 output_invalid (*l));
4310 if (token_start == l)
4312 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4313 as_bad (_("expecting prefix; got nothing"));
4315 as_bad (_("expecting mnemonic; got nothing"));
4319 /* Look up instruction (or prefix) via hash table. */
4320 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4322 if (*l != END_OF_INSN
4323 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4324 && current_templates
4325 && current_templates->start->opcode_modifier.isprefix)
4327 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4329 as_bad ((flag_code != CODE_64BIT
4330 ? _("`%s' is only supported in 64-bit mode")
4331 : _("`%s' is not supported in 64-bit mode")),
4332 current_templates->start->name);
4335 /* If we are in 16-bit mode, do not allow addr16 or data16.
4336 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4337 if ((current_templates->start->opcode_modifier.size16
4338 || current_templates->start->opcode_modifier.size32)
4339 && flag_code != CODE_64BIT
4340 && (current_templates->start->opcode_modifier.size32
4341 ^ (flag_code == CODE_16BIT)))
4343 as_bad (_("redundant %s prefix"),
4344 current_templates->start->name);
4347 if (current_templates->start->opcode_length == 0)
4349 /* Handle pseudo prefixes. */
4350 switch (current_templates->start->base_opcode)
4354 i.disp_encoding = disp_encoding_8bit;
4358 i.disp_encoding = disp_encoding_32bit;
4362 i.dir_encoding = dir_encoding_load;
4366 i.dir_encoding = dir_encoding_store;
4370 i.vec_encoding = vex_encoding_vex2;
4374 i.vec_encoding = vex_encoding_vex3;
4378 i.vec_encoding = vex_encoding_evex;
4382 i.rex_encoding = TRUE;
4386 i.no_optimize = TRUE;
4394 /* Add prefix, checking for repeated prefixes. */
4395 switch (add_prefix (current_templates->start->base_opcode))
4400 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4401 i.notrack_prefix = current_templates->start->name;
4404 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4405 i.hle_prefix = current_templates->start->name;
4406 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4407 i.bnd_prefix = current_templates->start->name;
4409 i.rep_prefix = current_templates->start->name;
4415 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4422 if (!current_templates)
4424 /* Check if we should swap operand or force 32bit displacement in
4426 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4427 i.dir_encoding = dir_encoding_store;
4428 else if (mnem_p - 3 == dot_p
4431 i.disp_encoding = disp_encoding_8bit;
4432 else if (mnem_p - 4 == dot_p
4436 i.disp_encoding = disp_encoding_32bit;
4441 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4444 if (!current_templates)
4447 /* See if we can get a match by trimming off a suffix. */
4450 case WORD_MNEM_SUFFIX:
4451 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4452 i.suffix = SHORT_MNEM_SUFFIX;
4455 case BYTE_MNEM_SUFFIX:
4456 case QWORD_MNEM_SUFFIX:
4457 i.suffix = mnem_p[-1];
4459 current_templates = (const templates *) hash_find (op_hash,
4462 case SHORT_MNEM_SUFFIX:
4463 case LONG_MNEM_SUFFIX:
4466 i.suffix = mnem_p[-1];
4468 current_templates = (const templates *) hash_find (op_hash,
4477 if (intel_float_operand (mnemonic) == 1)
4478 i.suffix = SHORT_MNEM_SUFFIX;
4480 i.suffix = LONG_MNEM_SUFFIX;
4482 current_templates = (const templates *) hash_find (op_hash,
4487 if (!current_templates)
4489 as_bad (_("no such instruction: `%s'"), token_start);
4494 if (current_templates->start->opcode_modifier.jump
4495 || current_templates->start->opcode_modifier.jumpbyte)
4497 /* Check for a branch hint. We allow ",pt" and ",pn" for
4498 predict taken and predict not taken respectively.
4499 I'm not sure that branch hints actually do anything on loop
4500 and jcxz insns (JumpByte) for current Pentium4 chips. They
4501 may work in the future and it doesn't hurt to accept them
4503 if (l[0] == ',' && l[1] == 'p')
4507 if (!add_prefix (DS_PREFIX_OPCODE))
4511 else if (l[2] == 'n')
4513 if (!add_prefix (CS_PREFIX_OPCODE))
4519 /* Any other comma loses. */
4522 as_bad (_("invalid character %s in mnemonic"),
4523 output_invalid (*l));
4527 /* Check if instruction is supported on specified architecture. */
4529 for (t = current_templates->start; t < current_templates->end; ++t)
4531 supported |= cpu_flags_match (t);
4532 if (supported == CPU_FLAGS_PERFECT_MATCH)
4534 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4535 as_warn (_("use .code16 to ensure correct addressing mode"));
4541 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4542 as_bad (flag_code == CODE_64BIT
4543 ? _("`%s' is not supported in 64-bit mode")
4544 : _("`%s' is only supported in 64-bit mode"),
4545 current_templates->start->name);
4547 as_bad (_("`%s' is not supported on `%s%s'"),
4548 current_templates->start->name,
4549 cpu_arch_name ? cpu_arch_name : default_arch,
4550 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4556 parse_operands (char *l, const char *mnemonic)
4560 /* 1 if operand is pending after ','. */
4561 unsigned int expecting_operand = 0;
4563 /* Non-zero if operand parens not balanced. */
4564 unsigned int paren_not_balanced;
4566 while (*l != END_OF_INSN)
4568 /* Skip optional white space before operand. */
4569 if (is_space_char (*l))
4571 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4573 as_bad (_("invalid character %s before operand %d"),
4574 output_invalid (*l),
4578 token_start = l; /* After white space. */
4579 paren_not_balanced = 0;
4580 while (paren_not_balanced || *l != ',')
4582 if (*l == END_OF_INSN)
4584 if (paren_not_balanced)
4587 as_bad (_("unbalanced parenthesis in operand %d."),
4590 as_bad (_("unbalanced brackets in operand %d."),
4595 break; /* we are done */
4597 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4599 as_bad (_("invalid character %s in operand %d"),
4600 output_invalid (*l),
4607 ++paren_not_balanced;
4609 --paren_not_balanced;
4614 ++paren_not_balanced;
4616 --paren_not_balanced;
4620 if (l != token_start)
4621 { /* Yes, we've read in another operand. */
4622 unsigned int operand_ok;
4623 this_operand = i.operands++;
4624 if (i.operands > MAX_OPERANDS)
4626 as_bad (_("spurious operands; (%d operands/instruction max)"),
4630 i.types[this_operand].bitfield.unspecified = 1;
4631 /* Now parse operand adding info to 'i' as we go along. */
4632 END_STRING_AND_SAVE (l);
4636 i386_intel_operand (token_start,
4637 intel_float_operand (mnemonic));
4639 operand_ok = i386_att_operand (token_start);
4641 RESTORE_END_STRING (l);
4647 if (expecting_operand)
4649 expecting_operand_after_comma:
4650 as_bad (_("expecting operand after ','; got nothing"));
4655 as_bad (_("expecting operand before ','; got nothing"));
4660 /* Now *l must be either ',' or END_OF_INSN. */
4663 if (*++l == END_OF_INSN)
4665 /* Just skip it, if it's \n complain. */
4666 goto expecting_operand_after_comma;
4668 expecting_operand = 1;
4675 swap_2_operands (int xchg1, int xchg2)
4677 union i386_op temp_op;
4678 i386_operand_type temp_type;
4679 enum bfd_reloc_code_real temp_reloc;
4681 temp_type = i.types[xchg2];
4682 i.types[xchg2] = i.types[xchg1];
4683 i.types[xchg1] = temp_type;
4684 temp_op = i.op[xchg2];
4685 i.op[xchg2] = i.op[xchg1];
4686 i.op[xchg1] = temp_op;
4687 temp_reloc = i.reloc[xchg2];
4688 i.reloc[xchg2] = i.reloc[xchg1];
4689 i.reloc[xchg1] = temp_reloc;
4693 if (i.mask->operand == xchg1)
4694 i.mask->operand = xchg2;
4695 else if (i.mask->operand == xchg2)
4696 i.mask->operand = xchg1;
4700 if (i.broadcast->operand == xchg1)
4701 i.broadcast->operand = xchg2;
4702 else if (i.broadcast->operand == xchg2)
4703 i.broadcast->operand = xchg1;
4707 if (i.rounding->operand == xchg1)
4708 i.rounding->operand = xchg2;
4709 else if (i.rounding->operand == xchg2)
4710 i.rounding->operand = xchg1;
4715 swap_operands (void)
4721 swap_2_operands (1, i.operands - 2);
4725 swap_2_operands (0, i.operands - 1);
4731 if (i.mem_operands == 2)
4733 const seg_entry *temp_seg;
4734 temp_seg = i.seg[0];
4735 i.seg[0] = i.seg[1];
4736 i.seg[1] = temp_seg;
4740 /* Try to ensure constant immediates are represented in the smallest
4745 char guess_suffix = 0;
4749 guess_suffix = i.suffix;
4750 else if (i.reg_operands)
4752 /* Figure out a suffix from the last register operand specified.
4753 We can't do this properly yet, ie. excluding InOutPortReg,
4754 but the following works for instructions with immediates.
4755 In any case, we can't set i.suffix yet. */
4756 for (op = i.operands; --op >= 0;)
4757 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4759 guess_suffix = BYTE_MNEM_SUFFIX;
4762 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4764 guess_suffix = WORD_MNEM_SUFFIX;
4767 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4769 guess_suffix = LONG_MNEM_SUFFIX;
4772 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4774 guess_suffix = QWORD_MNEM_SUFFIX;
4778 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4779 guess_suffix = WORD_MNEM_SUFFIX;
4781 for (op = i.operands; --op >= 0;)
4782 if (operand_type_check (i.types[op], imm))
4784 switch (i.op[op].imms->X_op)
4787 /* If a suffix is given, this operand may be shortened. */
4788 switch (guess_suffix)
4790 case LONG_MNEM_SUFFIX:
4791 i.types[op].bitfield.imm32 = 1;
4792 i.types[op].bitfield.imm64 = 1;
4794 case WORD_MNEM_SUFFIX:
4795 i.types[op].bitfield.imm16 = 1;
4796 i.types[op].bitfield.imm32 = 1;
4797 i.types[op].bitfield.imm32s = 1;
4798 i.types[op].bitfield.imm64 = 1;
4800 case BYTE_MNEM_SUFFIX:
4801 i.types[op].bitfield.imm8 = 1;
4802 i.types[op].bitfield.imm8s = 1;
4803 i.types[op].bitfield.imm16 = 1;
4804 i.types[op].bitfield.imm32 = 1;
4805 i.types[op].bitfield.imm32s = 1;
4806 i.types[op].bitfield.imm64 = 1;
4810 /* If this operand is at most 16 bits, convert it
4811 to a signed 16 bit number before trying to see
4812 whether it will fit in an even smaller size.
4813 This allows a 16-bit operand such as $0xffe0 to
4814 be recognised as within Imm8S range. */
4815 if ((i.types[op].bitfield.imm16)
4816 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4818 i.op[op].imms->X_add_number =
4819 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4822 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4823 if ((i.types[op].bitfield.imm32)
4824 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4827 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4828 ^ ((offsetT) 1 << 31))
4829 - ((offsetT) 1 << 31));
4833 = operand_type_or (i.types[op],
4834 smallest_imm_type (i.op[op].imms->X_add_number));
4836 /* We must avoid matching of Imm32 templates when 64bit
4837 only immediate is available. */
4838 if (guess_suffix == QWORD_MNEM_SUFFIX)
4839 i.types[op].bitfield.imm32 = 0;
4846 /* Symbols and expressions. */
4848 /* Convert symbolic operand to proper sizes for matching, but don't
4849 prevent matching a set of insns that only supports sizes other
4850 than those matching the insn suffix. */
4852 i386_operand_type mask, allowed;
4853 const insn_template *t;
4855 operand_type_set (&mask, 0);
4856 operand_type_set (&allowed, 0);
4858 for (t = current_templates->start;
4859 t < current_templates->end;
4861 allowed = operand_type_or (allowed,
4862 t->operand_types[op]);
4863 switch (guess_suffix)
4865 case QWORD_MNEM_SUFFIX:
4866 mask.bitfield.imm64 = 1;
4867 mask.bitfield.imm32s = 1;
4869 case LONG_MNEM_SUFFIX:
4870 mask.bitfield.imm32 = 1;
4872 case WORD_MNEM_SUFFIX:
4873 mask.bitfield.imm16 = 1;
4875 case BYTE_MNEM_SUFFIX:
4876 mask.bitfield.imm8 = 1;
4881 allowed = operand_type_and (mask, allowed);
4882 if (!operand_type_all_zero (&allowed))
4883 i.types[op] = operand_type_and (i.types[op], mask);
4890 /* Try to use the smallest displacement type too. */
4892 optimize_disp (void)
4896 for (op = i.operands; --op >= 0;)
4897 if (operand_type_check (i.types[op], disp))
4899 if (i.op[op].disps->X_op == O_constant)
4901 offsetT op_disp = i.op[op].disps->X_add_number;
4903 if (i.types[op].bitfield.disp16
4904 && (op_disp & ~(offsetT) 0xffff) == 0)
4906 /* If this operand is at most 16 bits, convert
4907 to a signed 16 bit number and don't use 64bit
4909 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4910 i.types[op].bitfield.disp64 = 0;
4913 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4914 if (i.types[op].bitfield.disp32
4915 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4917 /* If this operand is at most 32 bits, convert
4918 to a signed 32 bit number and don't use 64bit
4920 op_disp &= (((offsetT) 2 << 31) - 1);
4921 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4922 i.types[op].bitfield.disp64 = 0;
4925 if (!op_disp && i.types[op].bitfield.baseindex)
4927 i.types[op].bitfield.disp8 = 0;
4928 i.types[op].bitfield.disp16 = 0;
4929 i.types[op].bitfield.disp32 = 0;
4930 i.types[op].bitfield.disp32s = 0;
4931 i.types[op].bitfield.disp64 = 0;
4935 else if (flag_code == CODE_64BIT)
4937 if (fits_in_signed_long (op_disp))
4939 i.types[op].bitfield.disp64 = 0;
4940 i.types[op].bitfield.disp32s = 1;
4942 if (i.prefix[ADDR_PREFIX]
4943 && fits_in_unsigned_long (op_disp))
4944 i.types[op].bitfield.disp32 = 1;
4946 if ((i.types[op].bitfield.disp32
4947 || i.types[op].bitfield.disp32s
4948 || i.types[op].bitfield.disp16)
4949 && fits_in_disp8 (op_disp))
4950 i.types[op].bitfield.disp8 = 1;
4952 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4953 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4955 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4956 i.op[op].disps, 0, i.reloc[op]);
4957 i.types[op].bitfield.disp8 = 0;
4958 i.types[op].bitfield.disp16 = 0;
4959 i.types[op].bitfield.disp32 = 0;
4960 i.types[op].bitfield.disp32s = 0;
4961 i.types[op].bitfield.disp64 = 0;
4964 /* We only support 64bit displacement on constants. */
4965 i.types[op].bitfield.disp64 = 0;
4969 /* Check if operands are valid for the instruction. */
4972 check_VecOperands (const insn_template *t)
4976 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4978 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4979 any one operand are implicity requiring AVX512VL support if the actual
4980 operand size is YMMword or XMMword. Since this function runs after
4981 template matching, there's no need to check for YMMword/XMMword in
4983 cpu = cpu_flags_and (t->cpu_flags, avx512);
4984 if (!cpu_flags_all_zero (&cpu)
4985 && !t->cpu_flags.bitfield.cpuavx512vl
4986 && !cpu_arch_flags.bitfield.cpuavx512vl)
4988 for (op = 0; op < t->operands; ++op)
4990 if (t->operand_types[op].bitfield.zmmword
4991 && (i.types[op].bitfield.ymmword
4992 || i.types[op].bitfield.xmmword))
4994 i.error = unsupported;
5000 /* Without VSIB byte, we can't have a vector register for index. */
5001 if (!t->opcode_modifier.vecsib
5003 && (i.index_reg->reg_type.bitfield.xmmword
5004 || i.index_reg->reg_type.bitfield.ymmword
5005 || i.index_reg->reg_type.bitfield.zmmword))
5007 i.error = unsupported_vector_index_register;
5011 /* Check if default mask is allowed. */
5012 if (t->opcode_modifier.nodefmask
5013 && (!i.mask || i.mask->mask->reg_num == 0))
5015 i.error = no_default_mask;
5019 /* For VSIB byte, we need a vector register for index, and all vector
5020 registers must be distinct. */
5021 if (t->opcode_modifier.vecsib)
5024 || !((t->opcode_modifier.vecsib == VecSIB128
5025 && i.index_reg->reg_type.bitfield.xmmword)
5026 || (t->opcode_modifier.vecsib == VecSIB256
5027 && i.index_reg->reg_type.bitfield.ymmword)
5028 || (t->opcode_modifier.vecsib == VecSIB512
5029 && i.index_reg->reg_type.bitfield.zmmword)))
5031 i.error = invalid_vsib_address;
5035 gas_assert (i.reg_operands == 2 || i.mask);
5036 if (i.reg_operands == 2 && !i.mask)
5038 gas_assert (i.types[0].bitfield.regsimd);
5039 gas_assert (i.types[0].bitfield.xmmword
5040 || i.types[0].bitfield.ymmword);
5041 gas_assert (i.types[2].bitfield.regsimd);
5042 gas_assert (i.types[2].bitfield.xmmword
5043 || i.types[2].bitfield.ymmword);
5044 if (operand_check == check_none)
5046 if (register_number (i.op[0].regs)
5047 != register_number (i.index_reg)
5048 && register_number (i.op[2].regs)
5049 != register_number (i.index_reg)
5050 && register_number (i.op[0].regs)
5051 != register_number (i.op[2].regs))
5053 if (operand_check == check_error)
5055 i.error = invalid_vector_register_set;
5058 as_warn (_("mask, index, and destination registers should be distinct"));
5060 else if (i.reg_operands == 1 && i.mask)
5062 if (i.types[1].bitfield.regsimd
5063 && (i.types[1].bitfield.xmmword
5064 || i.types[1].bitfield.ymmword
5065 || i.types[1].bitfield.zmmword)
5066 && (register_number (i.op[1].regs)
5067 == register_number (i.index_reg)))
5069 if (operand_check == check_error)
5071 i.error = invalid_vector_register_set;
5074 if (operand_check != check_none)
5075 as_warn (_("index and destination registers should be distinct"));
5080 /* Check if broadcast is supported by the instruction and is applied
5081 to the memory operand. */
5084 i386_operand_type type, overlap;
5086 /* Check if specified broadcast is supported in this instruction,
5087 and it's applied to memory operand of DWORD or QWORD type. */
5088 op = i.broadcast->operand;
5089 if (!t->opcode_modifier.broadcast
5090 || !i.types[op].bitfield.mem
5091 || (!i.types[op].bitfield.unspecified
5092 && (t->operand_types[op].bitfield.dword
5093 ? !i.types[op].bitfield.dword
5094 : !i.types[op].bitfield.qword)))
5097 i.error = unsupported_broadcast;
5101 operand_type_set (&type, 0);
5102 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5105 type.bitfield.qword = 1;
5108 type.bitfield.xmmword = 1;
5111 type.bitfield.ymmword = 1;
5114 type.bitfield.zmmword = 1;
5120 overlap = operand_type_and (type, t->operand_types[op]);
5121 if (operand_type_all_zero (&overlap))
5124 if (t->opcode_modifier.checkregsize)
5128 type.bitfield.baseindex = 1;
5129 for (j = 0; j < i.operands; ++j)
5132 && !operand_type_register_match(i.types[j],
5133 t->operand_types[j],
5135 t->operand_types[op]))
5140 /* If broadcast is supported in this instruction, we need to check if
5141 operand of one-element size isn't specified without broadcast. */
5142 else if (t->opcode_modifier.broadcast && i.mem_operands)
5144 /* Find memory operand. */
5145 for (op = 0; op < i.operands; op++)
5146 if (operand_type_check (i.types[op], anymem))
5148 gas_assert (op < i.operands);
5149 /* Check size of the memory operand. */
5150 if (t->operand_types[op].bitfield.dword
5151 ? i.types[op].bitfield.dword
5152 : i.types[op].bitfield.qword)
5154 i.error = broadcast_needed;
5159 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5161 /* Check if requested masking is supported. */
5163 && (!t->opcode_modifier.masking
5165 && t->opcode_modifier.masking == MERGING_MASKING)))
5167 i.error = unsupported_masking;
5171 /* Check if masking is applied to dest operand. */
5172 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5174 i.error = mask_not_on_destination;
5181 if ((i.rounding->type != saeonly
5182 && !t->opcode_modifier.staticrounding)
5183 || (i.rounding->type == saeonly
5184 && (t->opcode_modifier.staticrounding
5185 || !t->opcode_modifier.sae)))
5187 i.error = unsupported_rc_sae;
5190 /* If the instruction has several immediate operands and one of
5191 them is rounding, the rounding operand should be the last
5192 immediate operand. */
5193 if (i.imm_operands > 1
5194 && i.rounding->operand != (int) (i.imm_operands - 1))
5196 i.error = rc_sae_operand_not_last_imm;
5201 /* Check vector Disp8 operand. */
5202 if (t->opcode_modifier.disp8memshift
5203 && i.disp_encoding != disp_encoding_32bit)
5206 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5208 i.memshift = t->opcode_modifier.disp8memshift;
5210 for (op = 0; op < i.operands; op++)
5211 if (operand_type_check (i.types[op], disp)
5212 && i.op[op].disps->X_op == O_constant)
5214 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5216 i.types[op].bitfield.disp8 = 1;
5219 i.types[op].bitfield.disp8 = 0;
5228 /* Check if operands are valid for the instruction. Update VEX
5232 VEX_check_operands (const insn_template *t)
5234 if (i.vec_encoding == vex_encoding_evex)
5236 /* This instruction must be encoded with EVEX prefix. */
5237 if (!is_evex_encoding (t))
5239 i.error = unsupported;
5245 if (!t->opcode_modifier.vex)
5247 /* This instruction template doesn't have VEX prefix. */
5248 if (i.vec_encoding != vex_encoding_default)
5250 i.error = unsupported;
5256 /* Only check VEX_Imm4, which must be the first operand. */
5257 if (t->operand_types[0].bitfield.vec_imm4)
5259 if (i.op[0].imms->X_op != O_constant
5260 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5266 /* Turn off Imm8 so that update_imm won't complain. */
5267 i.types[0] = vec_imm4;
5273 static const insn_template *
5274 match_template (char mnem_suffix)
5276 /* Points to template once we've found it. */
5277 const insn_template *t;
5278 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5279 i386_operand_type overlap4;
5280 unsigned int found_reverse_match;
5281 i386_opcode_modifier suffix_check, mnemsuf_check;
5282 i386_operand_type operand_types [MAX_OPERANDS];
5283 int addr_prefix_disp;
5285 unsigned int found_cpu_match;
5286 unsigned int check_register;
5287 enum i386_error specific_error = 0;
5289 #if MAX_OPERANDS != 5
5290 # error "MAX_OPERANDS must be 5."
5293 found_reverse_match = 0;
5294 addr_prefix_disp = -1;
5296 memset (&suffix_check, 0, sizeof (suffix_check));
5297 if (intel_syntax && i.broadcast)
5299 else if (i.suffix == BYTE_MNEM_SUFFIX)
5300 suffix_check.no_bsuf = 1;
5301 else if (i.suffix == WORD_MNEM_SUFFIX)
5302 suffix_check.no_wsuf = 1;
5303 else if (i.suffix == SHORT_MNEM_SUFFIX)
5304 suffix_check.no_ssuf = 1;
5305 else if (i.suffix == LONG_MNEM_SUFFIX)
5306 suffix_check.no_lsuf = 1;
5307 else if (i.suffix == QWORD_MNEM_SUFFIX)
5308 suffix_check.no_qsuf = 1;
5309 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5310 suffix_check.no_ldsuf = 1;
5312 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5315 switch (mnem_suffix)
5317 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5318 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5319 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5320 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5321 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5325 /* Must have right number of operands. */
5326 i.error = number_of_operands_mismatch;
5328 for (t = current_templates->start; t < current_templates->end; t++)
5330 addr_prefix_disp = -1;
5332 if (i.operands != t->operands)
5335 /* Check processor support. */
5336 i.error = unsupported;
5337 found_cpu_match = (cpu_flags_match (t)
5338 == CPU_FLAGS_PERFECT_MATCH);
5339 if (!found_cpu_match)
5342 /* Check AT&T mnemonic. */
5343 i.error = unsupported_with_intel_mnemonic;
5344 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5347 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5348 i.error = unsupported_syntax;
5349 if ((intel_syntax && t->opcode_modifier.attsyntax)
5350 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5351 || (intel64 && t->opcode_modifier.amd64)
5352 || (!intel64 && t->opcode_modifier.intel64))
5355 /* Check the suffix, except for some instructions in intel mode. */
5356 i.error = invalid_instruction_suffix;
5357 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5358 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5359 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5360 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5361 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5362 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5363 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5365 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5366 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5367 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5368 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5369 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5370 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5371 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5374 if (!operand_size_match (t))
5377 for (j = 0; j < MAX_OPERANDS; j++)
5378 operand_types[j] = t->operand_types[j];
5380 /* In general, don't allow 64-bit operands in 32-bit mode. */
5381 if (i.suffix == QWORD_MNEM_SUFFIX
5382 && flag_code != CODE_64BIT
5384 ? (!t->opcode_modifier.ignoresize
5385 && !intel_float_operand (t->name))
5386 : intel_float_operand (t->name) != 2)
5387 && ((!operand_types[0].bitfield.regmmx
5388 && !operand_types[0].bitfield.regsimd)
5389 || (!operand_types[t->operands > 1].bitfield.regmmx
5390 && !operand_types[t->operands > 1].bitfield.regsimd))
5391 && (t->base_opcode != 0x0fc7
5392 || t->extension_opcode != 1 /* cmpxchg8b */))
5395 /* In general, don't allow 32-bit operands on pre-386. */
5396 else if (i.suffix == LONG_MNEM_SUFFIX
5397 && !cpu_arch_flags.bitfield.cpui386
5399 ? (!t->opcode_modifier.ignoresize
5400 && !intel_float_operand (t->name))
5401 : intel_float_operand (t->name) != 2)
5402 && ((!operand_types[0].bitfield.regmmx
5403 && !operand_types[0].bitfield.regsimd)
5404 || (!operand_types[t->operands > 1].bitfield.regmmx
5405 && !operand_types[t->operands > 1].bitfield.regsimd)))
5408 /* Do not verify operands when there are none. */
5412 /* We've found a match; break out of loop. */
5416 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5417 into Disp32/Disp16/Disp32 operand. */
5418 if (i.prefix[ADDR_PREFIX] != 0)
5420 /* There should be only one Disp operand. */
5424 for (j = 0; j < MAX_OPERANDS; j++)
5426 if (operand_types[j].bitfield.disp16)
5428 addr_prefix_disp = j;
5429 operand_types[j].bitfield.disp32 = 1;
5430 operand_types[j].bitfield.disp16 = 0;
5436 for (j = 0; j < MAX_OPERANDS; j++)
5438 if (operand_types[j].bitfield.disp32)
5440 addr_prefix_disp = j;
5441 operand_types[j].bitfield.disp32 = 0;
5442 operand_types[j].bitfield.disp16 = 1;
5448 for (j = 0; j < MAX_OPERANDS; j++)
5450 if (operand_types[j].bitfield.disp64)
5452 addr_prefix_disp = j;
5453 operand_types[j].bitfield.disp64 = 0;
5454 operand_types[j].bitfield.disp32 = 1;
5462 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5463 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5466 /* We check register size if needed. */
5467 if (t->opcode_modifier.checkregsize)
5469 check_register = (1 << t->operands) - 1;
5471 check_register &= ~(1 << i.broadcast->operand);
5476 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5477 switch (t->operands)
5480 if (!operand_type_match (overlap0, i.types[0]))
5484 /* xchg %eax, %eax is a special case. It is an alias for nop
5485 only in 32bit mode and we can use opcode 0x90. In 64bit
5486 mode, we can't use 0x90 for xchg %eax, %eax since it should
5487 zero-extend %eax to %rax. */
5488 if (flag_code == CODE_64BIT
5489 && t->base_opcode == 0x90
5490 && operand_type_equal (&i.types [0], &acc32)
5491 && operand_type_equal (&i.types [1], &acc32))
5493 /* xrelease mov %eax, <disp> is another special case. It must not
5494 match the accumulator-only encoding of mov. */
5495 if (flag_code != CODE_64BIT
5497 && t->base_opcode == 0xa0
5498 && i.types[0].bitfield.acc
5499 && operand_type_check (i.types[1], anymem))
5501 /* If we want store form, we reverse direction of operands. */
5502 if (i.dir_encoding == dir_encoding_store
5503 && t->opcode_modifier.d)
5508 /* If we want store form, we skip the current load. */
5509 if (i.dir_encoding == dir_encoding_store
5510 && i.mem_operands == 0
5511 && t->opcode_modifier.load)
5516 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5517 if (!operand_type_match (overlap0, i.types[0])
5518 || !operand_type_match (overlap1, i.types[1])
5519 || ((check_register & 3) == 3
5520 && !operand_type_register_match (i.types[0],
5525 /* Check if other direction is valid ... */
5526 if (!t->opcode_modifier.d)
5530 /* Try reversing direction of operands. */
5531 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5532 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5533 if (!operand_type_match (overlap0, i.types[0])
5534 || !operand_type_match (overlap1, i.types[1])
5536 && !operand_type_register_match (i.types[0],
5541 /* Does not match either direction. */
5544 /* found_reverse_match holds which of D or FloatR
5546 if (!t->opcode_modifier.d)
5547 found_reverse_match = 0;
5548 else if (operand_types[0].bitfield.tbyte)
5549 found_reverse_match = Opcode_FloatD;
5551 found_reverse_match = Opcode_D;
5552 if (t->opcode_modifier.floatr)
5553 found_reverse_match |= Opcode_FloatR;
5557 /* Found a forward 2 operand match here. */
5558 switch (t->operands)
5561 overlap4 = operand_type_and (i.types[4],
5565 overlap3 = operand_type_and (i.types[3],
5569 overlap2 = operand_type_and (i.types[2],
5574 switch (t->operands)
5577 if (!operand_type_match (overlap4, i.types[4])
5578 || !operand_type_register_match (i.types[3],
5585 if (!operand_type_match (overlap3, i.types[3])
5586 || ((check_register & 0xa) == 0xa
5587 && !operand_type_register_match (i.types[1],
5591 || ((check_register & 0xc) == 0xc
5592 && !operand_type_register_match (i.types[2],
5599 /* Here we make use of the fact that there are no
5600 reverse match 3 operand instructions. */
5601 if (!operand_type_match (overlap2, i.types[2])
5602 || ((check_register & 5) == 5
5603 && !operand_type_register_match (i.types[0],
5607 || ((check_register & 6) == 6
5608 && !operand_type_register_match (i.types[1],
5616 /* Found either forward/reverse 2, 3 or 4 operand match here:
5617 slip through to break. */
5619 if (!found_cpu_match)
5621 found_reverse_match = 0;
5625 /* Check if vector and VEX operands are valid. */
5626 if (check_VecOperands (t) || VEX_check_operands (t))
5628 specific_error = i.error;
5632 /* We've found a match; break out of loop. */
5636 if (t == current_templates->end)
5638 /* We found no match. */
5639 const char *err_msg;
5640 switch (specific_error ? specific_error : i.error)
5644 case operand_size_mismatch:
5645 err_msg = _("operand size mismatch");
5647 case operand_type_mismatch:
5648 err_msg = _("operand type mismatch");
5650 case register_type_mismatch:
5651 err_msg = _("register type mismatch");
5653 case number_of_operands_mismatch:
5654 err_msg = _("number of operands mismatch");
5656 case invalid_instruction_suffix:
5657 err_msg = _("invalid instruction suffix");
5660 err_msg = _("constant doesn't fit in 4 bits");
5662 case unsupported_with_intel_mnemonic:
5663 err_msg = _("unsupported with Intel mnemonic");
5665 case unsupported_syntax:
5666 err_msg = _("unsupported syntax");
5669 as_bad (_("unsupported instruction `%s'"),
5670 current_templates->start->name);
5672 case invalid_vsib_address:
5673 err_msg = _("invalid VSIB address");
5675 case invalid_vector_register_set:
5676 err_msg = _("mask, index, and destination registers must be distinct");
5678 case unsupported_vector_index_register:
5679 err_msg = _("unsupported vector index register");
5681 case unsupported_broadcast:
5682 err_msg = _("unsupported broadcast");
5684 case broadcast_not_on_src_operand:
5685 err_msg = _("broadcast not on source memory operand");
5687 case broadcast_needed:
5688 err_msg = _("broadcast is needed for operand of such type");
5690 case unsupported_masking:
5691 err_msg = _("unsupported masking");
5693 case mask_not_on_destination:
5694 err_msg = _("mask not on destination operand");
5696 case no_default_mask:
5697 err_msg = _("default mask isn't allowed");
5699 case unsupported_rc_sae:
5700 err_msg = _("unsupported static rounding/sae");
5702 case rc_sae_operand_not_last_imm:
5704 err_msg = _("RC/SAE operand must precede immediate operands");
5706 err_msg = _("RC/SAE operand must follow immediate operands");
5708 case invalid_register_operand:
5709 err_msg = _("invalid register operand");
5712 as_bad (_("%s for `%s'"), err_msg,
5713 current_templates->start->name);
5717 if (!quiet_warnings)
5720 && (i.types[0].bitfield.jumpabsolute
5721 != operand_types[0].bitfield.jumpabsolute))
5723 as_warn (_("indirect %s without `*'"), t->name);
5726 if (t->opcode_modifier.isprefix
5727 && t->opcode_modifier.ignoresize)
5729 /* Warn them that a data or address size prefix doesn't
5730 affect assembly of the next line of code. */
5731 as_warn (_("stand-alone `%s' prefix"), t->name);
5735 /* Copy the template we found. */
5738 if (addr_prefix_disp != -1)
5739 i.tm.operand_types[addr_prefix_disp]
5740 = operand_types[addr_prefix_disp];
5742 if (found_reverse_match)
5744 /* If we found a reverse match we must alter the opcode
5745 direction bit. found_reverse_match holds bits to change
5746 (different for int & float insns). */
5748 i.tm.base_opcode ^= found_reverse_match;
5750 i.tm.operand_types[0] = operand_types[1];
5751 i.tm.operand_types[1] = operand_types[0];
5760 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5761 if (i.tm.operand_types[mem_op].bitfield.esseg)
5763 if (i.seg[0] != NULL && i.seg[0] != &es)
5765 as_bad (_("`%s' operand %d must use `%ses' segment"),
5771 /* There's only ever one segment override allowed per instruction.
5772 This instruction possibly has a legal segment override on the
5773 second operand, so copy the segment to where non-string
5774 instructions store it, allowing common code. */
5775 i.seg[0] = i.seg[1];
5777 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5779 if (i.seg[1] != NULL && i.seg[1] != &es)
5781 as_bad (_("`%s' operand %d must use `%ses' segment"),
5792 process_suffix (void)
5794 /* If matched instruction specifies an explicit instruction mnemonic
5796 if (i.tm.opcode_modifier.size16)
5797 i.suffix = WORD_MNEM_SUFFIX;
5798 else if (i.tm.opcode_modifier.size32)
5799 i.suffix = LONG_MNEM_SUFFIX;
5800 else if (i.tm.opcode_modifier.size64)
5801 i.suffix = QWORD_MNEM_SUFFIX;
5802 else if (i.reg_operands)
5804 /* If there's no instruction mnemonic suffix we try to invent one
5805 based on register operands. */
5808 /* We take i.suffix from the last register operand specified,
5809 Destination register type is more significant than source
5810 register type. crc32 in SSE4.2 prefers source register
5812 if (i.tm.base_opcode == 0xf20f38f1)
5814 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5815 i.suffix = WORD_MNEM_SUFFIX;
5816 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5817 i.suffix = LONG_MNEM_SUFFIX;
5818 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5819 i.suffix = QWORD_MNEM_SUFFIX;
5821 else if (i.tm.base_opcode == 0xf20f38f0)
5823 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5824 i.suffix = BYTE_MNEM_SUFFIX;
5831 if (i.tm.base_opcode == 0xf20f38f1
5832 || i.tm.base_opcode == 0xf20f38f0)
5834 /* We have to know the operand size for crc32. */
5835 as_bad (_("ambiguous memory operand size for `%s`"),
5840 for (op = i.operands; --op >= 0;)
5841 if (!i.tm.operand_types[op].bitfield.inoutportreg
5842 && !i.tm.operand_types[op].bitfield.shiftcount)
5844 if (!i.types[op].bitfield.reg)
5846 if (i.types[op].bitfield.byte)
5847 i.suffix = BYTE_MNEM_SUFFIX;
5848 else if (i.types[op].bitfield.word)
5849 i.suffix = WORD_MNEM_SUFFIX;
5850 else if (i.types[op].bitfield.dword)
5851 i.suffix = LONG_MNEM_SUFFIX;
5852 else if (i.types[op].bitfield.qword)
5853 i.suffix = QWORD_MNEM_SUFFIX;
5860 else if (i.suffix == BYTE_MNEM_SUFFIX)
5863 && i.tm.opcode_modifier.ignoresize
5864 && i.tm.opcode_modifier.no_bsuf)
5866 else if (!check_byte_reg ())
5869 else if (i.suffix == LONG_MNEM_SUFFIX)
5872 && i.tm.opcode_modifier.ignoresize
5873 && i.tm.opcode_modifier.no_lsuf
5874 && !i.tm.opcode_modifier.todword
5875 && !i.tm.opcode_modifier.toqword)
5877 else if (!check_long_reg ())
5880 else if (i.suffix == QWORD_MNEM_SUFFIX)
5883 && i.tm.opcode_modifier.ignoresize
5884 && i.tm.opcode_modifier.no_qsuf
5885 && !i.tm.opcode_modifier.todword
5886 && !i.tm.opcode_modifier.toqword)
5888 else if (!check_qword_reg ())
5891 else if (i.suffix == WORD_MNEM_SUFFIX)
5894 && i.tm.opcode_modifier.ignoresize
5895 && i.tm.opcode_modifier.no_wsuf)
5897 else if (!check_word_reg ())
5900 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5901 /* Do nothing if the instruction is going to ignore the prefix. */
5906 else if (i.tm.opcode_modifier.defaultsize
5908 /* exclude fldenv/frstor/fsave/fstenv */
5909 && i.tm.opcode_modifier.no_ssuf)
5911 i.suffix = stackop_size;
5913 else if (intel_syntax
5915 && (i.tm.operand_types[0].bitfield.jumpabsolute
5916 || i.tm.opcode_modifier.jumpbyte
5917 || i.tm.opcode_modifier.jumpintersegment
5918 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5919 && i.tm.extension_opcode <= 3)))
5924 if (!i.tm.opcode_modifier.no_qsuf)
5926 i.suffix = QWORD_MNEM_SUFFIX;
5931 if (!i.tm.opcode_modifier.no_lsuf)
5932 i.suffix = LONG_MNEM_SUFFIX;
5935 if (!i.tm.opcode_modifier.no_wsuf)
5936 i.suffix = WORD_MNEM_SUFFIX;
5945 if (i.tm.opcode_modifier.w)
5947 as_bad (_("no instruction mnemonic suffix given and "
5948 "no register operands; can't size instruction"));
5954 unsigned int suffixes;
5956 suffixes = !i.tm.opcode_modifier.no_bsuf;
5957 if (!i.tm.opcode_modifier.no_wsuf)
5959 if (!i.tm.opcode_modifier.no_lsuf)
5961 if (!i.tm.opcode_modifier.no_ldsuf)
5963 if (!i.tm.opcode_modifier.no_ssuf)
5965 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5968 /* There are more than suffix matches. */
5969 if (i.tm.opcode_modifier.w
5970 || ((suffixes & (suffixes - 1))
5971 && !i.tm.opcode_modifier.defaultsize
5972 && !i.tm.opcode_modifier.ignoresize))
5974 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5980 /* Change the opcode based on the operand size given by i.suffix. */
5983 /* Size floating point instruction. */
5984 case LONG_MNEM_SUFFIX:
5985 if (i.tm.opcode_modifier.floatmf)
5987 i.tm.base_opcode ^= 4;
5991 case WORD_MNEM_SUFFIX:
5992 case QWORD_MNEM_SUFFIX:
5993 /* It's not a byte, select word/dword operation. */
5994 if (i.tm.opcode_modifier.w)
5996 if (i.tm.opcode_modifier.shortform)
5997 i.tm.base_opcode |= 8;
5999 i.tm.base_opcode |= 1;
6002 case SHORT_MNEM_SUFFIX:
6003 /* Now select between word & dword operations via the operand
6004 size prefix, except for instructions that will ignore this
6006 if (i.tm.opcode_modifier.addrprefixop0)
6008 /* The address size override prefix changes the size of the
6010 if ((flag_code == CODE_32BIT
6011 && i.op->regs[0].reg_type.bitfield.word)
6012 || (flag_code != CODE_32BIT
6013 && i.op->regs[0].reg_type.bitfield.dword))
6014 if (!add_prefix (ADDR_PREFIX_OPCODE))
6017 else if (i.suffix != QWORD_MNEM_SUFFIX
6018 && !i.tm.opcode_modifier.ignoresize
6019 && !i.tm.opcode_modifier.floatmf
6020 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6021 || (flag_code == CODE_64BIT
6022 && i.tm.opcode_modifier.jumpbyte)))
6024 unsigned int prefix = DATA_PREFIX_OPCODE;
6026 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6027 prefix = ADDR_PREFIX_OPCODE;
6029 if (!add_prefix (prefix))
6033 /* Set mode64 for an operand. */
6034 if (i.suffix == QWORD_MNEM_SUFFIX
6035 && flag_code == CODE_64BIT
6036 && !i.tm.opcode_modifier.norex64
6037 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6039 && ! (i.operands == 2
6040 && i.tm.base_opcode == 0x90
6041 && i.tm.extension_opcode == None
6042 && operand_type_equal (&i.types [0], &acc64)
6043 && operand_type_equal (&i.types [1], &acc64)))
6049 if (i.tm.opcode_modifier.addrprefixopreg
6050 && i.reg_operands != 0
6053 /* Check invalid register operand when the address size override
6054 prefix changes the size of register operands. */
6056 enum { need_word, need_dword, need_qword } need;
6058 if (flag_code == CODE_32BIT)
6059 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6062 if (i.prefix[ADDR_PREFIX])
6065 need = flag_code == CODE_64BIT ? need_qword : need_word;
6068 for (op = 0; op < i.operands; op++)
6069 if (i.types[op].bitfield.reg
6070 && ((need == need_word
6071 && !i.op[op].regs->reg_type.bitfield.word)
6072 || (need == need_dword
6073 && !i.op[op].regs->reg_type.bitfield.dword)
6074 || (need == need_qword
6075 && !i.op[op].regs->reg_type.bitfield.qword)))
6077 as_bad (_("invalid register operand size for `%s'"),
6087 check_byte_reg (void)
6091 for (op = i.operands; --op >= 0;)
6093 /* Skip non-register operands. */
6094 if (!i.types[op].bitfield.reg)
6097 /* If this is an eight bit register, it's OK. If it's the 16 or
6098 32 bit version of an eight bit register, we will just use the
6099 low portion, and that's OK too. */
6100 if (i.types[op].bitfield.byte)
6103 /* I/O port address operands are OK too. */
6104 if (i.tm.operand_types[op].bitfield.inoutportreg)
6107 /* crc32 doesn't generate this warning. */
6108 if (i.tm.base_opcode == 0xf20f38f0)
6111 if ((i.types[op].bitfield.word
6112 || i.types[op].bitfield.dword
6113 || i.types[op].bitfield.qword)
6114 && i.op[op].regs->reg_num < 4
6115 /* Prohibit these changes in 64bit mode, since the lowering
6116 would be more complicated. */
6117 && flag_code != CODE_64BIT)
6119 #if REGISTER_WARNINGS
6120 if (!quiet_warnings)
6121 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6123 (i.op[op].regs + (i.types[op].bitfield.word
6124 ? REGNAM_AL - REGNAM_AX
6125 : REGNAM_AL - REGNAM_EAX))->reg_name,
6127 i.op[op].regs->reg_name,
6132 /* Any other register is bad. */
6133 if (i.types[op].bitfield.reg
6134 || i.types[op].bitfield.regmmx
6135 || i.types[op].bitfield.regsimd
6136 || i.types[op].bitfield.sreg2
6137 || i.types[op].bitfield.sreg3
6138 || i.types[op].bitfield.control
6139 || i.types[op].bitfield.debug
6140 || i.types[op].bitfield.test)
6142 as_bad (_("`%s%s' not allowed with `%s%c'"),
6144 i.op[op].regs->reg_name,
6154 check_long_reg (void)
6158 for (op = i.operands; --op >= 0;)
6159 /* Skip non-register operands. */
6160 if (!i.types[op].bitfield.reg)
6162 /* Reject eight bit registers, except where the template requires
6163 them. (eg. movzb) */
6164 else if (i.types[op].bitfield.byte
6165 && (i.tm.operand_types[op].bitfield.reg
6166 || i.tm.operand_types[op].bitfield.acc)
6167 && (i.tm.operand_types[op].bitfield.word
6168 || i.tm.operand_types[op].bitfield.dword))
6170 as_bad (_("`%s%s' not allowed with `%s%c'"),
6172 i.op[op].regs->reg_name,
6177 /* Warn if the e prefix on a general reg is missing. */
6178 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6179 && i.types[op].bitfield.word
6180 && (i.tm.operand_types[op].bitfield.reg
6181 || i.tm.operand_types[op].bitfield.acc)
6182 && i.tm.operand_types[op].bitfield.dword)
6184 /* Prohibit these changes in the 64bit mode, since the
6185 lowering is more complicated. */
6186 if (flag_code == CODE_64BIT)
6188 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6189 register_prefix, i.op[op].regs->reg_name,
6193 #if REGISTER_WARNINGS
6194 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6196 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6197 register_prefix, i.op[op].regs->reg_name, i.suffix);
6200 /* Warn if the r prefix on a general reg is present. */
6201 else if (i.types[op].bitfield.qword
6202 && (i.tm.operand_types[op].bitfield.reg
6203 || i.tm.operand_types[op].bitfield.acc)
6204 && i.tm.operand_types[op].bitfield.dword)
6207 && i.tm.opcode_modifier.toqword
6208 && !i.types[0].bitfield.regsimd)
6210 /* Convert to QWORD. We want REX byte. */
6211 i.suffix = QWORD_MNEM_SUFFIX;
6215 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6216 register_prefix, i.op[op].regs->reg_name,
6225 check_qword_reg (void)
6229 for (op = i.operands; --op >= 0; )
6230 /* Skip non-register operands. */
6231 if (!i.types[op].bitfield.reg)
6233 /* Reject eight bit registers, except where the template requires
6234 them. (eg. movzb) */
6235 else if (i.types[op].bitfield.byte
6236 && (i.tm.operand_types[op].bitfield.reg
6237 || i.tm.operand_types[op].bitfield.acc)
6238 && (i.tm.operand_types[op].bitfield.word
6239 || i.tm.operand_types[op].bitfield.dword))
6241 as_bad (_("`%s%s' not allowed with `%s%c'"),
6243 i.op[op].regs->reg_name,
6248 /* Warn if the r prefix on a general reg is missing. */
6249 else if ((i.types[op].bitfield.word
6250 || i.types[op].bitfield.dword)
6251 && (i.tm.operand_types[op].bitfield.reg
6252 || i.tm.operand_types[op].bitfield.acc)
6253 && i.tm.operand_types[op].bitfield.qword)
6255 /* Prohibit these changes in the 64bit mode, since the
6256 lowering is more complicated. */
6258 && i.tm.opcode_modifier.todword
6259 && !i.types[0].bitfield.regsimd)
6261 /* Convert to DWORD. We don't want REX byte. */
6262 i.suffix = LONG_MNEM_SUFFIX;
6266 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6267 register_prefix, i.op[op].regs->reg_name,
6276 check_word_reg (void)
6279 for (op = i.operands; --op >= 0;)
6280 /* Skip non-register operands. */
6281 if (!i.types[op].bitfield.reg)
6283 /* Reject eight bit registers, except where the template requires
6284 them. (eg. movzb) */
6285 else if (i.types[op].bitfield.byte
6286 && (i.tm.operand_types[op].bitfield.reg
6287 || i.tm.operand_types[op].bitfield.acc)
6288 && (i.tm.operand_types[op].bitfield.word
6289 || i.tm.operand_types[op].bitfield.dword))
6291 as_bad (_("`%s%s' not allowed with `%s%c'"),
6293 i.op[op].regs->reg_name,
6298 /* Warn if the e or r prefix on a general reg is present. */
6299 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6300 && (i.types[op].bitfield.dword
6301 || i.types[op].bitfield.qword)
6302 && (i.tm.operand_types[op].bitfield.reg
6303 || i.tm.operand_types[op].bitfield.acc)
6304 && i.tm.operand_types[op].bitfield.word)
6306 /* Prohibit these changes in the 64bit mode, since the
6307 lowering is more complicated. */
6308 if (flag_code == CODE_64BIT)
6310 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6311 register_prefix, i.op[op].regs->reg_name,
6315 #if REGISTER_WARNINGS
6316 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6318 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6319 register_prefix, i.op[op].regs->reg_name, i.suffix);
6326 update_imm (unsigned int j)
6328 i386_operand_type overlap = i.types[j];
6329 if ((overlap.bitfield.imm8
6330 || overlap.bitfield.imm8s
6331 || overlap.bitfield.imm16
6332 || overlap.bitfield.imm32
6333 || overlap.bitfield.imm32s
6334 || overlap.bitfield.imm64)
6335 && !operand_type_equal (&overlap, &imm8)
6336 && !operand_type_equal (&overlap, &imm8s)
6337 && !operand_type_equal (&overlap, &imm16)
6338 && !operand_type_equal (&overlap, &imm32)
6339 && !operand_type_equal (&overlap, &imm32s)
6340 && !operand_type_equal (&overlap, &imm64))
6344 i386_operand_type temp;
6346 operand_type_set (&temp, 0);
6347 if (i.suffix == BYTE_MNEM_SUFFIX)
6349 temp.bitfield.imm8 = overlap.bitfield.imm8;
6350 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6352 else if (i.suffix == WORD_MNEM_SUFFIX)
6353 temp.bitfield.imm16 = overlap.bitfield.imm16;
6354 else if (i.suffix == QWORD_MNEM_SUFFIX)
6356 temp.bitfield.imm64 = overlap.bitfield.imm64;
6357 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6360 temp.bitfield.imm32 = overlap.bitfield.imm32;
6363 else if (operand_type_equal (&overlap, &imm16_32_32s)
6364 || operand_type_equal (&overlap, &imm16_32)
6365 || operand_type_equal (&overlap, &imm16_32s))
6367 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6372 if (!operand_type_equal (&overlap, &imm8)
6373 && !operand_type_equal (&overlap, &imm8s)
6374 && !operand_type_equal (&overlap, &imm16)
6375 && !operand_type_equal (&overlap, &imm32)
6376 && !operand_type_equal (&overlap, &imm32s)
6377 && !operand_type_equal (&overlap, &imm64))
6379 as_bad (_("no instruction mnemonic suffix given; "
6380 "can't determine immediate size"));
6384 i.types[j] = overlap;
6394 /* Update the first 2 immediate operands. */
6395 n = i.operands > 2 ? 2 : i.operands;
6398 for (j = 0; j < n; j++)
6399 if (update_imm (j) == 0)
6402 /* The 3rd operand can't be immediate operand. */
6403 gas_assert (operand_type_check (i.types[2], imm) == 0);
6410 process_operands (void)
6412 /* Default segment register this instruction will use for memory
6413 accesses. 0 means unknown. This is only for optimizing out
6414 unnecessary segment overrides. */
6415 const seg_entry *default_seg = 0;
6417 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6419 unsigned int dupl = i.operands;
6420 unsigned int dest = dupl - 1;
6423 /* The destination must be an xmm register. */
6424 gas_assert (i.reg_operands
6425 && MAX_OPERANDS > dupl
6426 && operand_type_equal (&i.types[dest], ®xmm));
6428 if (i.tm.operand_types[0].bitfield.acc
6429 && i.tm.operand_types[0].bitfield.xmmword)
6431 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6433 /* Keep xmm0 for instructions with VEX prefix and 3
6435 i.tm.operand_types[0].bitfield.acc = 0;
6436 i.tm.operand_types[0].bitfield.regsimd = 1;
6441 /* We remove the first xmm0 and keep the number of
6442 operands unchanged, which in fact duplicates the
6444 for (j = 1; j < i.operands; j++)
6446 i.op[j - 1] = i.op[j];
6447 i.types[j - 1] = i.types[j];
6448 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6452 else if (i.tm.opcode_modifier.implicit1stxmm0)
6454 gas_assert ((MAX_OPERANDS - 1) > dupl
6455 && (i.tm.opcode_modifier.vexsources
6458 /* Add the implicit xmm0 for instructions with VEX prefix
6460 for (j = i.operands; j > 0; j--)
6462 i.op[j] = i.op[j - 1];
6463 i.types[j] = i.types[j - 1];
6464 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6467 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6468 i.types[0] = regxmm;
6469 i.tm.operand_types[0] = regxmm;
6472 i.reg_operands += 2;
6477 i.op[dupl] = i.op[dest];
6478 i.types[dupl] = i.types[dest];
6479 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6488 i.op[dupl] = i.op[dest];
6489 i.types[dupl] = i.types[dest];
6490 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6493 if (i.tm.opcode_modifier.immext)
6496 else if (i.tm.operand_types[0].bitfield.acc
6497 && i.tm.operand_types[0].bitfield.xmmword)
6501 for (j = 1; j < i.operands; j++)
6503 i.op[j - 1] = i.op[j];
6504 i.types[j - 1] = i.types[j];
6506 /* We need to adjust fields in i.tm since they are used by
6507 build_modrm_byte. */
6508 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6515 else if (i.tm.opcode_modifier.implicitquadgroup)
6517 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6519 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6520 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6521 regnum = register_number (i.op[1].regs);
6522 first_reg_in_group = regnum & ~3;
6523 last_reg_in_group = first_reg_in_group + 3;
6524 if (regnum != first_reg_in_group)
6525 as_warn (_("source register `%s%s' implicitly denotes"
6526 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6527 register_prefix, i.op[1].regs->reg_name,
6528 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6529 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6532 else if (i.tm.opcode_modifier.regkludge)
6534 /* The imul $imm, %reg instruction is converted into
6535 imul $imm, %reg, %reg, and the clr %reg instruction
6536 is converted into xor %reg, %reg. */
6538 unsigned int first_reg_op;
6540 if (operand_type_check (i.types[0], reg))
6544 /* Pretend we saw the extra register operand. */
6545 gas_assert (i.reg_operands == 1
6546 && i.op[first_reg_op + 1].regs == 0);
6547 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6548 i.types[first_reg_op + 1] = i.types[first_reg_op];
6553 if (i.tm.opcode_modifier.shortform)
6555 if (i.types[0].bitfield.sreg2
6556 || i.types[0].bitfield.sreg3)
6558 if (i.tm.base_opcode == POP_SEG_SHORT
6559 && i.op[0].regs->reg_num == 1)
6561 as_bad (_("you can't `pop %scs'"), register_prefix);
6564 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6565 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6570 /* The register or float register operand is in operand
6574 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6575 || operand_type_check (i.types[0], reg))
6579 /* Register goes in low 3 bits of opcode. */
6580 i.tm.base_opcode |= i.op[op].regs->reg_num;
6581 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6583 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6585 /* Warn about some common errors, but press on regardless.
6586 The first case can be generated by gcc (<= 2.8.1). */
6587 if (i.operands == 2)
6589 /* Reversed arguments on faddp, fsubp, etc. */
6590 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6591 register_prefix, i.op[!intel_syntax].regs->reg_name,
6592 register_prefix, i.op[intel_syntax].regs->reg_name);
6596 /* Extraneous `l' suffix on fp insn. */
6597 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6598 register_prefix, i.op[0].regs->reg_name);
6603 else if (i.tm.opcode_modifier.modrm)
6605 /* The opcode is completed (modulo i.tm.extension_opcode which
6606 must be put into the modrm byte). Now, we make the modrm and
6607 index base bytes based on all the info we've collected. */
6609 default_seg = build_modrm_byte ();
6611 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6615 else if (i.tm.opcode_modifier.isstring)
6617 /* For the string instructions that allow a segment override
6618 on one of their operands, the default segment is ds. */
6622 if (i.tm.base_opcode == 0x8d /* lea */
6625 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6627 /* If a segment was explicitly specified, and the specified segment
6628 is not the default, use an opcode prefix to select it. If we
6629 never figured out what the default segment is, then default_seg
6630 will be zero at this point, and the specified segment prefix will
6632 if ((i.seg[0]) && (i.seg[0] != default_seg))
6634 if (!add_prefix (i.seg[0]->seg_prefix))
6640 static const seg_entry *
6641 build_modrm_byte (void)
6643 const seg_entry *default_seg = 0;
6644 unsigned int source, dest;
6647 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6650 unsigned int nds, reg_slot;
6653 dest = i.operands - 1;
6656 /* There are 2 kinds of instructions:
6657 1. 5 operands: 4 register operands or 3 register operands
6658 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6659 VexW0 or VexW1. The destination must be either XMM, YMM or
6661 2. 4 operands: 4 register operands or 3 register operands
6662 plus 1 memory operand, with VexXDS. */
6663 gas_assert ((i.reg_operands == 4
6664 || (i.reg_operands == 3 && i.mem_operands == 1))
6665 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6666 && i.tm.opcode_modifier.vexw
6667 && i.tm.operand_types[dest].bitfield.regsimd);
6669 /* If VexW1 is set, the first non-immediate operand is the source and
6670 the second non-immediate one is encoded in the immediate operand. */
6671 if (i.tm.opcode_modifier.vexw == VEXW1)
6673 source = i.imm_operands;
6674 reg_slot = i.imm_operands + 1;
6678 source = i.imm_operands + 1;
6679 reg_slot = i.imm_operands;
6682 if (i.imm_operands == 0)
6684 /* When there is no immediate operand, generate an 8bit
6685 immediate operand to encode the first operand. */
6686 exp = &im_expressions[i.imm_operands++];
6687 i.op[i.operands].imms = exp;
6688 i.types[i.operands] = imm8;
6691 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6692 exp->X_op = O_constant;
6693 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6694 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6698 unsigned int imm_slot;
6700 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6702 if (i.tm.opcode_modifier.immext)
6704 /* When ImmExt is set, the immediate byte is the last
6706 imm_slot = i.operands - 1;
6714 /* Turn on Imm8 so that output_imm will generate it. */
6715 i.types[imm_slot].bitfield.imm8 = 1;
6718 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6719 i.op[imm_slot].imms->X_add_number
6720 |= register_number (i.op[reg_slot].regs) << 4;
6721 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6724 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6725 i.vex.register_specifier = i.op[nds].regs;
6730 /* i.reg_operands MUST be the number of real register operands;
6731 implicit registers do not count. If there are 3 register
6732 operands, it must be a instruction with VexNDS. For a
6733 instruction with VexNDD, the destination register is encoded
6734 in VEX prefix. If there are 4 register operands, it must be
6735 a instruction with VEX prefix and 3 sources. */
6736 if (i.mem_operands == 0
6737 && ((i.reg_operands == 2
6738 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6739 || (i.reg_operands == 3
6740 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6741 || (i.reg_operands == 4 && vex_3_sources)))
6749 /* When there are 3 operands, one of them may be immediate,
6750 which may be the first or the last operand. Otherwise,
6751 the first operand must be shift count register (cl) or it
6752 is an instruction with VexNDS. */
6753 gas_assert (i.imm_operands == 1
6754 || (i.imm_operands == 0
6755 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6756 || i.types[0].bitfield.shiftcount)));
6757 if (operand_type_check (i.types[0], imm)
6758 || i.types[0].bitfield.shiftcount)
6764 /* When there are 4 operands, the first two must be 8bit
6765 immediate operands. The source operand will be the 3rd
6768 For instructions with VexNDS, if the first operand
6769 an imm8, the source operand is the 2nd one. If the last
6770 operand is imm8, the source operand is the first one. */
6771 gas_assert ((i.imm_operands == 2
6772 && i.types[0].bitfield.imm8
6773 && i.types[1].bitfield.imm8)
6774 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6775 && i.imm_operands == 1
6776 && (i.types[0].bitfield.imm8
6777 || i.types[i.operands - 1].bitfield.imm8
6779 if (i.imm_operands == 2)
6783 if (i.types[0].bitfield.imm8)
6790 if (is_evex_encoding (&i.tm))
6792 /* For EVEX instructions, when there are 5 operands, the
6793 first one must be immediate operand. If the second one
6794 is immediate operand, the source operand is the 3th
6795 one. If the last one is immediate operand, the source
6796 operand is the 2nd one. */
6797 gas_assert (i.imm_operands == 2
6798 && i.tm.opcode_modifier.sae
6799 && operand_type_check (i.types[0], imm));
6800 if (operand_type_check (i.types[1], imm))
6802 else if (operand_type_check (i.types[4], imm))
6816 /* RC/SAE operand could be between DEST and SRC. That happens
6817 when one operand is GPR and the other one is XMM/YMM/ZMM
6819 if (i.rounding && i.rounding->operand == (int) dest)
6822 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6824 /* For instructions with VexNDS, the register-only source
6825 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6826 register. It is encoded in VEX prefix. We need to
6827 clear RegMem bit before calling operand_type_equal. */
6829 i386_operand_type op;
6832 /* Check register-only source operand when two source
6833 operands are swapped. */
6834 if (!i.tm.operand_types[source].bitfield.baseindex
6835 && i.tm.operand_types[dest].bitfield.baseindex)
6843 op = i.tm.operand_types[vvvv];
6844 op.bitfield.regmem = 0;
6845 if ((dest + 1) >= i.operands
6846 || ((!op.bitfield.reg
6847 || (!op.bitfield.dword && !op.bitfield.qword))
6848 && !op.bitfield.regsimd
6849 && !operand_type_equal (&op, ®mask)))
6851 i.vex.register_specifier = i.op[vvvv].regs;
6857 /* One of the register operands will be encoded in the i.tm.reg
6858 field, the other in the combined i.tm.mode and i.tm.regmem
6859 fields. If no form of this instruction supports a memory
6860 destination operand, then we assume the source operand may
6861 sometimes be a memory operand and so we need to store the
6862 destination in the i.rm.reg field. */
6863 if (!i.tm.operand_types[dest].bitfield.regmem
6864 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6866 i.rm.reg = i.op[dest].regs->reg_num;
6867 i.rm.regmem = i.op[source].regs->reg_num;
6868 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6870 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6872 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6874 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6879 i.rm.reg = i.op[source].regs->reg_num;
6880 i.rm.regmem = i.op[dest].regs->reg_num;
6881 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6883 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6885 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6887 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6890 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6892 if (!i.types[0].bitfield.control
6893 && !i.types[1].bitfield.control)
6895 i.rex &= ~(REX_R | REX_B);
6896 add_prefix (LOCK_PREFIX_OPCODE);
6900 { /* If it's not 2 reg operands... */
6905 unsigned int fake_zero_displacement = 0;
6908 for (op = 0; op < i.operands; op++)
6909 if (operand_type_check (i.types[op], anymem))
6911 gas_assert (op < i.operands);
6913 if (i.tm.opcode_modifier.vecsib)
6915 if (i.index_reg->reg_num == RegEiz
6916 || i.index_reg->reg_num == RegRiz)
6919 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6922 i.sib.base = NO_BASE_REGISTER;
6923 i.sib.scale = i.log2_scale_factor;
6924 i.types[op].bitfield.disp8 = 0;
6925 i.types[op].bitfield.disp16 = 0;
6926 i.types[op].bitfield.disp64 = 0;
6927 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6929 /* Must be 32 bit */
6930 i.types[op].bitfield.disp32 = 1;
6931 i.types[op].bitfield.disp32s = 0;
6935 i.types[op].bitfield.disp32 = 0;
6936 i.types[op].bitfield.disp32s = 1;
6939 i.sib.index = i.index_reg->reg_num;
6940 if ((i.index_reg->reg_flags & RegRex) != 0)
6942 if ((i.index_reg->reg_flags & RegVRex) != 0)
6948 if (i.base_reg == 0)
6951 if (!i.disp_operands)
6952 fake_zero_displacement = 1;
6953 if (i.index_reg == 0)
6955 i386_operand_type newdisp;
6957 gas_assert (!i.tm.opcode_modifier.vecsib);
6958 /* Operand is just <disp> */
6959 if (flag_code == CODE_64BIT)
6961 /* 64bit mode overwrites the 32bit absolute
6962 addressing by RIP relative addressing and
6963 absolute addressing is encoded by one of the
6964 redundant SIB forms. */
6965 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6966 i.sib.base = NO_BASE_REGISTER;
6967 i.sib.index = NO_INDEX_REGISTER;
6968 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6970 else if ((flag_code == CODE_16BIT)
6971 ^ (i.prefix[ADDR_PREFIX] != 0))
6973 i.rm.regmem = NO_BASE_REGISTER_16;
6978 i.rm.regmem = NO_BASE_REGISTER;
6981 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6982 i.types[op] = operand_type_or (i.types[op], newdisp);
6984 else if (!i.tm.opcode_modifier.vecsib)
6986 /* !i.base_reg && i.index_reg */
6987 if (i.index_reg->reg_num == RegEiz
6988 || i.index_reg->reg_num == RegRiz)
6989 i.sib.index = NO_INDEX_REGISTER;
6991 i.sib.index = i.index_reg->reg_num;
6992 i.sib.base = NO_BASE_REGISTER;
6993 i.sib.scale = i.log2_scale_factor;
6994 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6995 i.types[op].bitfield.disp8 = 0;
6996 i.types[op].bitfield.disp16 = 0;
6997 i.types[op].bitfield.disp64 = 0;
6998 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7000 /* Must be 32 bit */
7001 i.types[op].bitfield.disp32 = 1;
7002 i.types[op].bitfield.disp32s = 0;
7006 i.types[op].bitfield.disp32 = 0;
7007 i.types[op].bitfield.disp32s = 1;
7009 if ((i.index_reg->reg_flags & RegRex) != 0)
7013 /* RIP addressing for 64bit mode. */
7014 else if (i.base_reg->reg_num == RegRip ||
7015 i.base_reg->reg_num == RegEip)
7017 gas_assert (!i.tm.opcode_modifier.vecsib);
7018 i.rm.regmem = NO_BASE_REGISTER;
7019 i.types[op].bitfield.disp8 = 0;
7020 i.types[op].bitfield.disp16 = 0;
7021 i.types[op].bitfield.disp32 = 0;
7022 i.types[op].bitfield.disp32s = 1;
7023 i.types[op].bitfield.disp64 = 0;
7024 i.flags[op] |= Operand_PCrel;
7025 if (! i.disp_operands)
7026 fake_zero_displacement = 1;
7028 else if (i.base_reg->reg_type.bitfield.word)
7030 gas_assert (!i.tm.opcode_modifier.vecsib);
7031 switch (i.base_reg->reg_num)
7034 if (i.index_reg == 0)
7036 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7037 i.rm.regmem = i.index_reg->reg_num - 6;
7041 if (i.index_reg == 0)
7044 if (operand_type_check (i.types[op], disp) == 0)
7046 /* fake (%bp) into 0(%bp) */
7047 i.types[op].bitfield.disp8 = 1;
7048 fake_zero_displacement = 1;
7051 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7052 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7054 default: /* (%si) -> 4 or (%di) -> 5 */
7055 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7057 i.rm.mode = mode_from_disp_size (i.types[op]);
7059 else /* i.base_reg and 32/64 bit mode */
7061 if (flag_code == CODE_64BIT
7062 && operand_type_check (i.types[op], disp))
7064 i.types[op].bitfield.disp16 = 0;
7065 i.types[op].bitfield.disp64 = 0;
7066 if (i.prefix[ADDR_PREFIX] == 0)
7068 i.types[op].bitfield.disp32 = 0;
7069 i.types[op].bitfield.disp32s = 1;
7073 i.types[op].bitfield.disp32 = 1;
7074 i.types[op].bitfield.disp32s = 0;
7078 if (!i.tm.opcode_modifier.vecsib)
7079 i.rm.regmem = i.base_reg->reg_num;
7080 if ((i.base_reg->reg_flags & RegRex) != 0)
7082 i.sib.base = i.base_reg->reg_num;
7083 /* x86-64 ignores REX prefix bit here to avoid decoder
7085 if (!(i.base_reg->reg_flags & RegRex)
7086 && (i.base_reg->reg_num == EBP_REG_NUM
7087 || i.base_reg->reg_num == ESP_REG_NUM))
7089 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7091 fake_zero_displacement = 1;
7092 i.types[op].bitfield.disp8 = 1;
7094 i.sib.scale = i.log2_scale_factor;
7095 if (i.index_reg == 0)
7097 gas_assert (!i.tm.opcode_modifier.vecsib);
7098 /* <disp>(%esp) becomes two byte modrm with no index
7099 register. We've already stored the code for esp
7100 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7101 Any base register besides %esp will not use the
7102 extra modrm byte. */
7103 i.sib.index = NO_INDEX_REGISTER;
7105 else if (!i.tm.opcode_modifier.vecsib)
7107 if (i.index_reg->reg_num == RegEiz
7108 || i.index_reg->reg_num == RegRiz)
7109 i.sib.index = NO_INDEX_REGISTER;
7111 i.sib.index = i.index_reg->reg_num;
7112 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7113 if ((i.index_reg->reg_flags & RegRex) != 0)
7118 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7119 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7123 if (!fake_zero_displacement
7127 fake_zero_displacement = 1;
7128 if (i.disp_encoding == disp_encoding_8bit)
7129 i.types[op].bitfield.disp8 = 1;
7131 i.types[op].bitfield.disp32 = 1;
7133 i.rm.mode = mode_from_disp_size (i.types[op]);
7137 if (fake_zero_displacement)
7139 /* Fakes a zero displacement assuming that i.types[op]
7140 holds the correct displacement size. */
7143 gas_assert (i.op[op].disps == 0);
7144 exp = &disp_expressions[i.disp_operands++];
7145 i.op[op].disps = exp;
7146 exp->X_op = O_constant;
7147 exp->X_add_number = 0;
7148 exp->X_add_symbol = (symbolS *) 0;
7149 exp->X_op_symbol = (symbolS *) 0;
7157 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7159 if (operand_type_check (i.types[0], imm))
7160 i.vex.register_specifier = NULL;
7163 /* VEX.vvvv encodes one of the sources when the first
7164 operand is not an immediate. */
7165 if (i.tm.opcode_modifier.vexw == VEXW0)
7166 i.vex.register_specifier = i.op[0].regs;
7168 i.vex.register_specifier = i.op[1].regs;
7171 /* Destination is a XMM register encoded in the ModRM.reg
7173 i.rm.reg = i.op[2].regs->reg_num;
7174 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7177 /* ModRM.rm and VEX.B encodes the other source. */
7178 if (!i.mem_operands)
7182 if (i.tm.opcode_modifier.vexw == VEXW0)
7183 i.rm.regmem = i.op[1].regs->reg_num;
7185 i.rm.regmem = i.op[0].regs->reg_num;
7187 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7191 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7193 i.vex.register_specifier = i.op[2].regs;
7194 if (!i.mem_operands)
7197 i.rm.regmem = i.op[1].regs->reg_num;
7198 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7202 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7203 (if any) based on i.tm.extension_opcode. Again, we must be
7204 careful to make sure that segment/control/debug/test/MMX
7205 registers are coded into the i.rm.reg field. */
7206 else if (i.reg_operands)
7209 unsigned int vex_reg = ~0;
7211 for (op = 0; op < i.operands; op++)
7212 if (i.types[op].bitfield.reg
7213 || i.types[op].bitfield.regmmx
7214 || i.types[op].bitfield.regsimd
7215 || i.types[op].bitfield.regbnd
7216 || i.types[op].bitfield.regmask
7217 || i.types[op].bitfield.sreg2
7218 || i.types[op].bitfield.sreg3
7219 || i.types[op].bitfield.control
7220 || i.types[op].bitfield.debug
7221 || i.types[op].bitfield.test)
7226 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7228 /* For instructions with VexNDS, the register-only
7229 source operand is encoded in VEX prefix. */
7230 gas_assert (mem != (unsigned int) ~0);
7235 gas_assert (op < i.operands);
7239 /* Check register-only source operand when two source
7240 operands are swapped. */
7241 if (!i.tm.operand_types[op].bitfield.baseindex
7242 && i.tm.operand_types[op + 1].bitfield.baseindex)
7246 gas_assert (mem == (vex_reg + 1)
7247 && op < i.operands);
7252 gas_assert (vex_reg < i.operands);
7256 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7258 /* For instructions with VexNDD, the register destination
7259 is encoded in VEX prefix. */
7260 if (i.mem_operands == 0)
7262 /* There is no memory operand. */
7263 gas_assert ((op + 2) == i.operands);
7268 /* There are only 2 non-immediate operands. */
7269 gas_assert (op < i.imm_operands + 2
7270 && i.operands == i.imm_operands + 2);
7271 vex_reg = i.imm_operands + 1;
7275 gas_assert (op < i.operands);
7277 if (vex_reg != (unsigned int) ~0)
7279 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7281 if ((!type->bitfield.reg
7282 || (!type->bitfield.dword && !type->bitfield.qword))
7283 && !type->bitfield.regsimd
7284 && !operand_type_equal (type, ®mask))
7287 i.vex.register_specifier = i.op[vex_reg].regs;
7290 /* Don't set OP operand twice. */
7293 /* If there is an extension opcode to put here, the
7294 register number must be put into the regmem field. */
7295 if (i.tm.extension_opcode != None)
7297 i.rm.regmem = i.op[op].regs->reg_num;
7298 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7300 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7305 i.rm.reg = i.op[op].regs->reg_num;
7306 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7308 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7313 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7314 must set it to 3 to indicate this is a register operand
7315 in the regmem field. */
7316 if (!i.mem_operands)
7320 /* Fill in i.rm.reg field with extension opcode (if any). */
7321 if (i.tm.extension_opcode != None)
7322 i.rm.reg = i.tm.extension_opcode;
7328 output_branch (void)
7334 relax_substateT subtype;
7338 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7339 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7342 if (i.prefix[DATA_PREFIX] != 0)
7348 /* Pentium4 branch hints. */
7349 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7350 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7355 if (i.prefix[REX_PREFIX] != 0)
7361 /* BND prefixed jump. */
7362 if (i.prefix[BND_PREFIX] != 0)
7364 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7368 if (i.prefixes != 0 && !intel_syntax)
7369 as_warn (_("skipping prefixes on this instruction"));
7371 /* It's always a symbol; End frag & setup for relax.
7372 Make sure there is enough room in this frag for the largest
7373 instruction we may generate in md_convert_frag. This is 2
7374 bytes for the opcode and room for the prefix and largest
7376 frag_grow (prefix + 2 + 4);
7377 /* Prefix and 1 opcode byte go in fr_fix. */
7378 p = frag_more (prefix + 1);
7379 if (i.prefix[DATA_PREFIX] != 0)
7380 *p++ = DATA_PREFIX_OPCODE;
7381 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7382 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7383 *p++ = i.prefix[SEG_PREFIX];
7384 if (i.prefix[REX_PREFIX] != 0)
7385 *p++ = i.prefix[REX_PREFIX];
7386 *p = i.tm.base_opcode;
7388 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7389 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7390 else if (cpu_arch_flags.bitfield.cpui386)
7391 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7393 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7396 sym = i.op[0].disps->X_add_symbol;
7397 off = i.op[0].disps->X_add_number;
7399 if (i.op[0].disps->X_op != O_constant
7400 && i.op[0].disps->X_op != O_symbol)
7402 /* Handle complex expressions. */
7403 sym = make_expr_symbol (i.op[0].disps);
7407 /* 1 possible extra opcode + 4 byte displacement go in var part.
7408 Pass reloc in fr_var. */
7409 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7412 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7413 /* Return TRUE iff PLT32 relocation should be used for branching to
7417 need_plt32_p (symbolS *s)
7419 /* PLT32 relocation is ELF only. */
7423 /* Since there is no need to prepare for PLT branch on x86-64, we
7424 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7425 be used as a marker for 32-bit PC-relative branches. */
7429 /* Weak or undefined symbol need PLT32 relocation. */
7430 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7433 /* Non-global symbol doesn't need PLT32 relocation. */
7434 if (! S_IS_EXTERNAL (s))
7437 /* Other global symbols need PLT32 relocation. NB: Symbol with
7438 non-default visibilities are treated as normal global symbol
7439 so that PLT32 relocation can be used as a marker for 32-bit
7440 PC-relative branches. It is useful for linker relaxation. */
7451 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7453 if (i.tm.opcode_modifier.jumpbyte)
7455 /* This is a loop or jecxz type instruction. */
7457 if (i.prefix[ADDR_PREFIX] != 0)
7459 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7462 /* Pentium4 branch hints. */
7463 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7464 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7466 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7475 if (flag_code == CODE_16BIT)
7478 if (i.prefix[DATA_PREFIX] != 0)
7480 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7490 if (i.prefix[REX_PREFIX] != 0)
7492 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7496 /* BND prefixed jump. */
7497 if (i.prefix[BND_PREFIX] != 0)
7499 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7503 if (i.prefixes != 0 && !intel_syntax)
7504 as_warn (_("skipping prefixes on this instruction"));
7506 p = frag_more (i.tm.opcode_length + size);
7507 switch (i.tm.opcode_length)
7510 *p++ = i.tm.base_opcode >> 8;
7513 *p++ = i.tm.base_opcode;
7519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7521 && jump_reloc == NO_RELOC
7522 && need_plt32_p (i.op[0].disps->X_add_symbol))
7523 jump_reloc = BFD_RELOC_X86_64_PLT32;
7526 jump_reloc = reloc (size, 1, 1, jump_reloc);
7528 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7529 i.op[0].disps, 1, jump_reloc);
7531 /* All jumps handled here are signed, but don't use a signed limit
7532 check for 32 and 16 bit jumps as we want to allow wrap around at
7533 4G and 64k respectively. */
7535 fixP->fx_signed = 1;
7539 output_interseg_jump (void)
7547 if (flag_code == CODE_16BIT)
7551 if (i.prefix[DATA_PREFIX] != 0)
7557 if (i.prefix[REX_PREFIX] != 0)
7567 if (i.prefixes != 0 && !intel_syntax)
7568 as_warn (_("skipping prefixes on this instruction"));
7570 /* 1 opcode; 2 segment; offset */
7571 p = frag_more (prefix + 1 + 2 + size);
7573 if (i.prefix[DATA_PREFIX] != 0)
7574 *p++ = DATA_PREFIX_OPCODE;
7576 if (i.prefix[REX_PREFIX] != 0)
7577 *p++ = i.prefix[REX_PREFIX];
7579 *p++ = i.tm.base_opcode;
7580 if (i.op[1].imms->X_op == O_constant)
7582 offsetT n = i.op[1].imms->X_add_number;
7585 && !fits_in_unsigned_word (n)
7586 && !fits_in_signed_word (n))
7588 as_bad (_("16-bit jump out of range"));
7591 md_number_to_chars (p, n, size);
7594 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7595 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7596 if (i.op[0].imms->X_op != O_constant)
7597 as_bad (_("can't handle non absolute segment in `%s'"),
7599 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7605 fragS *insn_start_frag;
7606 offsetT insn_start_off;
7608 /* Tie dwarf2 debug info to the address at the start of the insn.
7609 We can't do this after the insn has been output as the current
7610 frag may have been closed off. eg. by frag_var. */
7611 dwarf2_emit_insn (0);
7613 insn_start_frag = frag_now;
7614 insn_start_off = frag_now_fix ();
7617 if (i.tm.opcode_modifier.jump)
7619 else if (i.tm.opcode_modifier.jumpbyte
7620 || i.tm.opcode_modifier.jumpdword)
7622 else if (i.tm.opcode_modifier.jumpintersegment)
7623 output_interseg_jump ();
7626 /* Output normal instructions here. */
7630 unsigned int prefix;
7633 && i.tm.base_opcode == 0xfae
7635 && i.imm_operands == 1
7636 && (i.op[0].imms->X_add_number == 0xe8
7637 || i.op[0].imms->X_add_number == 0xf0
7638 || i.op[0].imms->X_add_number == 0xf8))
7640 /* Encode lfence, mfence, and sfence as
7641 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7642 offsetT val = 0x240483f0ULL;
7644 md_number_to_chars (p, val, 5);
7648 /* Some processors fail on LOCK prefix. This options makes
7649 assembler ignore LOCK prefix and serves as a workaround. */
7650 if (omit_lock_prefix)
7652 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7654 i.prefix[LOCK_PREFIX] = 0;
7657 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7658 don't need the explicit prefix. */
7659 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7661 switch (i.tm.opcode_length)
7664 if (i.tm.base_opcode & 0xff000000)
7666 prefix = (i.tm.base_opcode >> 24) & 0xff;
7671 if ((i.tm.base_opcode & 0xff0000) != 0)
7673 prefix = (i.tm.base_opcode >> 16) & 0xff;
7674 if (i.tm.cpu_flags.bitfield.cpupadlock)
7677 if (prefix != REPE_PREFIX_OPCODE
7678 || (i.prefix[REP_PREFIX]
7679 != REPE_PREFIX_OPCODE))
7680 add_prefix (prefix);
7683 add_prefix (prefix);
7689 /* Check for pseudo prefixes. */
7690 as_bad_where (insn_start_frag->fr_file,
7691 insn_start_frag->fr_line,
7692 _("pseudo prefix without instruction"));
7698 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7699 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7700 R_X86_64_GOTTPOFF relocation so that linker can safely
7701 perform IE->LE optimization. */
7702 if (x86_elf_abi == X86_64_X32_ABI
7704 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7705 && i.prefix[REX_PREFIX] == 0)
7706 add_prefix (REX_OPCODE);
7709 /* The prefix bytes. */
7710 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7712 FRAG_APPEND_1_CHAR (*q);
7716 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7721 /* REX byte is encoded in VEX prefix. */
7725 FRAG_APPEND_1_CHAR (*q);
7728 /* There should be no other prefixes for instructions
7733 /* For EVEX instructions i.vrex should become 0 after
7734 build_evex_prefix. For VEX instructions upper 16 registers
7735 aren't available, so VREX should be 0. */
7738 /* Now the VEX prefix. */
7739 p = frag_more (i.vex.length);
7740 for (j = 0; j < i.vex.length; j++)
7741 p[j] = i.vex.bytes[j];
7744 /* Now the opcode; be careful about word order here! */
7745 if (i.tm.opcode_length == 1)
7747 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7751 switch (i.tm.opcode_length)
7755 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7756 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7760 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7770 /* Put out high byte first: can't use md_number_to_chars! */
7771 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7772 *p = i.tm.base_opcode & 0xff;
7775 /* Now the modrm byte and sib byte (if present). */
7776 if (i.tm.opcode_modifier.modrm)
7778 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7781 /* If i.rm.regmem == ESP (4)
7782 && i.rm.mode != (Register mode)
7784 ==> need second modrm byte. */
7785 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7787 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7788 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7790 | i.sib.scale << 6));
7793 if (i.disp_operands)
7794 output_disp (insn_start_frag, insn_start_off);
7797 output_imm (insn_start_frag, insn_start_off);
7803 pi ("" /*line*/, &i);
7805 #endif /* DEBUG386 */
7808 /* Return the size of the displacement operand N. */
7811 disp_size (unsigned int n)
7815 if (i.types[n].bitfield.disp64)
7817 else if (i.types[n].bitfield.disp8)
7819 else if (i.types[n].bitfield.disp16)
7824 /* Return the size of the immediate operand N. */
7827 imm_size (unsigned int n)
7830 if (i.types[n].bitfield.imm64)
7832 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7834 else if (i.types[n].bitfield.imm16)
7840 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7845 for (n = 0; n < i.operands; n++)
7847 if (operand_type_check (i.types[n], disp))
7849 if (i.op[n].disps->X_op == O_constant)
7851 int size = disp_size (n);
7852 offsetT val = i.op[n].disps->X_add_number;
7854 val = offset_in_range (val >> i.memshift, size);
7855 p = frag_more (size);
7856 md_number_to_chars (p, val, size);
7860 enum bfd_reloc_code_real reloc_type;
7861 int size = disp_size (n);
7862 int sign = i.types[n].bitfield.disp32s;
7863 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7866 /* We can't have 8 bit displacement here. */
7867 gas_assert (!i.types[n].bitfield.disp8);
7869 /* The PC relative address is computed relative
7870 to the instruction boundary, so in case immediate
7871 fields follows, we need to adjust the value. */
7872 if (pcrel && i.imm_operands)
7877 for (n1 = 0; n1 < i.operands; n1++)
7878 if (operand_type_check (i.types[n1], imm))
7880 /* Only one immediate is allowed for PC
7881 relative address. */
7882 gas_assert (sz == 0);
7884 i.op[n].disps->X_add_number -= sz;
7886 /* We should find the immediate. */
7887 gas_assert (sz != 0);
7890 p = frag_more (size);
7891 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7893 && GOT_symbol == i.op[n].disps->X_add_symbol
7894 && (((reloc_type == BFD_RELOC_32
7895 || reloc_type == BFD_RELOC_X86_64_32S
7896 || (reloc_type == BFD_RELOC_64
7898 && (i.op[n].disps->X_op == O_symbol
7899 || (i.op[n].disps->X_op == O_add
7900 && ((symbol_get_value_expression
7901 (i.op[n].disps->X_op_symbol)->X_op)
7903 || reloc_type == BFD_RELOC_32_PCREL))
7907 if (insn_start_frag == frag_now)
7908 add = (p - frag_now->fr_literal) - insn_start_off;
7913 add = insn_start_frag->fr_fix - insn_start_off;
7914 for (fr = insn_start_frag->fr_next;
7915 fr && fr != frag_now; fr = fr->fr_next)
7917 add += p - frag_now->fr_literal;
7922 reloc_type = BFD_RELOC_386_GOTPC;
7923 i.op[n].imms->X_add_number += add;
7925 else if (reloc_type == BFD_RELOC_64)
7926 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7928 /* Don't do the adjustment for x86-64, as there
7929 the pcrel addressing is relative to the _next_
7930 insn, and that is taken care of in other code. */
7931 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7933 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7934 size, i.op[n].disps, pcrel,
7936 /* Check for "call/jmp *mem", "mov mem, %reg",
7937 "test %reg, mem" and "binop mem, %reg" where binop
7938 is one of adc, add, and, cmp, or, sbb, sub, xor
7939 instructions. Always generate R_386_GOT32X for
7940 "sym*GOT" operand in 32-bit mode. */
7941 if ((generate_relax_relocations
7944 && i.rm.regmem == 5))
7946 || (i.rm.mode == 0 && i.rm.regmem == 5))
7947 && ((i.operands == 1
7948 && i.tm.base_opcode == 0xff
7949 && (i.rm.reg == 2 || i.rm.reg == 4))
7951 && (i.tm.base_opcode == 0x8b
7952 || i.tm.base_opcode == 0x85
7953 || (i.tm.base_opcode & 0xc7) == 0x03))))
7957 fixP->fx_tcbit = i.rex != 0;
7959 && (i.base_reg->reg_num == RegRip
7960 || i.base_reg->reg_num == RegEip))
7961 fixP->fx_tcbit2 = 1;
7964 fixP->fx_tcbit2 = 1;
7972 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7977 for (n = 0; n < i.operands; n++)
7979 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7980 if (i.rounding && (int) n == i.rounding->operand)
7983 if (operand_type_check (i.types[n], imm))
7985 if (i.op[n].imms->X_op == O_constant)
7987 int size = imm_size (n);
7990 val = offset_in_range (i.op[n].imms->X_add_number,
7992 p = frag_more (size);
7993 md_number_to_chars (p, val, size);
7997 /* Not absolute_section.
7998 Need a 32-bit fixup (don't support 8bit
7999 non-absolute imms). Try to support other
8001 enum bfd_reloc_code_real reloc_type;
8002 int size = imm_size (n);
8005 if (i.types[n].bitfield.imm32s
8006 && (i.suffix == QWORD_MNEM_SUFFIX
8007 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8012 p = frag_more (size);
8013 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8015 /* This is tough to explain. We end up with this one if we
8016 * have operands that look like
8017 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8018 * obtain the absolute address of the GOT, and it is strongly
8019 * preferable from a performance point of view to avoid using
8020 * a runtime relocation for this. The actual sequence of
8021 * instructions often look something like:
8026 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8028 * The call and pop essentially return the absolute address
8029 * of the label .L66 and store it in %ebx. The linker itself
8030 * will ultimately change the first operand of the addl so
8031 * that %ebx points to the GOT, but to keep things simple, the
8032 * .o file must have this operand set so that it generates not
8033 * the absolute address of .L66, but the absolute address of
8034 * itself. This allows the linker itself simply treat a GOTPC
8035 * relocation as asking for a pcrel offset to the GOT to be
8036 * added in, and the addend of the relocation is stored in the
8037 * operand field for the instruction itself.
8039 * Our job here is to fix the operand so that it would add
8040 * the correct offset so that %ebx would point to itself. The
8041 * thing that is tricky is that .-.L66 will point to the
8042 * beginning of the instruction, so we need to further modify
8043 * the operand so that it will point to itself. There are
8044 * other cases where you have something like:
8046 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8048 * and here no correction would be required. Internally in
8049 * the assembler we treat operands of this form as not being
8050 * pcrel since the '.' is explicitly mentioned, and I wonder
8051 * whether it would simplify matters to do it this way. Who
8052 * knows. In earlier versions of the PIC patches, the
8053 * pcrel_adjust field was used to store the correction, but
8054 * since the expression is not pcrel, I felt it would be
8055 * confusing to do it this way. */
8057 if ((reloc_type == BFD_RELOC_32
8058 || reloc_type == BFD_RELOC_X86_64_32S
8059 || reloc_type == BFD_RELOC_64)
8061 && GOT_symbol == i.op[n].imms->X_add_symbol
8062 && (i.op[n].imms->X_op == O_symbol
8063 || (i.op[n].imms->X_op == O_add
8064 && ((symbol_get_value_expression
8065 (i.op[n].imms->X_op_symbol)->X_op)
8070 if (insn_start_frag == frag_now)
8071 add = (p - frag_now->fr_literal) - insn_start_off;
8076 add = insn_start_frag->fr_fix - insn_start_off;
8077 for (fr = insn_start_frag->fr_next;
8078 fr && fr != frag_now; fr = fr->fr_next)
8080 add += p - frag_now->fr_literal;
8084 reloc_type = BFD_RELOC_386_GOTPC;
8086 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8088 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8089 i.op[n].imms->X_add_number += add;
8091 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8092 i.op[n].imms, 0, reloc_type);
8098 /* x86_cons_fix_new is called via the expression parsing code when a
8099 reloc is needed. We use this hook to get the correct .got reloc. */
8100 static int cons_sign = -1;
8103 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8104 expressionS *exp, bfd_reloc_code_real_type r)
8106 r = reloc (len, 0, cons_sign, r);
8109 if (exp->X_op == O_secrel)
8111 exp->X_op = O_symbol;
8112 r = BFD_RELOC_32_SECREL;
8116 fix_new_exp (frag, off, len, exp, 0, r);
8119 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8120 purpose of the `.dc.a' internal pseudo-op. */
8123 x86_address_bytes (void)
8125 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8127 return stdoutput->arch_info->bits_per_address / 8;
8130 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8132 # define lex_got(reloc, adjust, types) NULL
8134 /* Parse operands of the form
8135 <symbol>@GOTOFF+<nnn>
8136 and similar .plt or .got references.
8138 If we find one, set up the correct relocation in RELOC and copy the
8139 input string, minus the `@GOTOFF' into a malloc'd buffer for
8140 parsing by the calling routine. Return this buffer, and if ADJUST
8141 is non-null set it to the length of the string we removed from the
8142 input line. Otherwise return NULL. */
8144 lex_got (enum bfd_reloc_code_real *rel,
8146 i386_operand_type *types)
8148 /* Some of the relocations depend on the size of what field is to
8149 be relocated. But in our callers i386_immediate and i386_displacement
8150 we don't yet know the operand size (this will be set by insn
8151 matching). Hence we record the word32 relocation here,
8152 and adjust the reloc according to the real size in reloc(). */
8153 static const struct {
8156 const enum bfd_reloc_code_real rel[2];
8157 const i386_operand_type types64;
8159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8160 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8162 OPERAND_TYPE_IMM32_64 },
8164 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8165 BFD_RELOC_X86_64_PLTOFF64 },
8166 OPERAND_TYPE_IMM64 },
8167 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8168 BFD_RELOC_X86_64_PLT32 },
8169 OPERAND_TYPE_IMM32_32S_DISP32 },
8170 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8171 BFD_RELOC_X86_64_GOTPLT64 },
8172 OPERAND_TYPE_IMM64_DISP64 },
8173 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8174 BFD_RELOC_X86_64_GOTOFF64 },
8175 OPERAND_TYPE_IMM64_DISP64 },
8176 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8177 BFD_RELOC_X86_64_GOTPCREL },
8178 OPERAND_TYPE_IMM32_32S_DISP32 },
8179 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8180 BFD_RELOC_X86_64_TLSGD },
8181 OPERAND_TYPE_IMM32_32S_DISP32 },
8182 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8183 _dummy_first_bfd_reloc_code_real },
8184 OPERAND_TYPE_NONE },
8185 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8186 BFD_RELOC_X86_64_TLSLD },
8187 OPERAND_TYPE_IMM32_32S_DISP32 },
8188 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8189 BFD_RELOC_X86_64_GOTTPOFF },
8190 OPERAND_TYPE_IMM32_32S_DISP32 },
8191 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8192 BFD_RELOC_X86_64_TPOFF32 },
8193 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8194 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8195 _dummy_first_bfd_reloc_code_real },
8196 OPERAND_TYPE_NONE },
8197 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8198 BFD_RELOC_X86_64_DTPOFF32 },
8199 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8200 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8201 _dummy_first_bfd_reloc_code_real },
8202 OPERAND_TYPE_NONE },
8203 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8204 _dummy_first_bfd_reloc_code_real },
8205 OPERAND_TYPE_NONE },
8206 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8207 BFD_RELOC_X86_64_GOT32 },
8208 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8209 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8210 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8211 OPERAND_TYPE_IMM32_32S_DISP32 },
8212 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8213 BFD_RELOC_X86_64_TLSDESC_CALL },
8214 OPERAND_TYPE_IMM32_32S_DISP32 },
8219 #if defined (OBJ_MAYBE_ELF)
8224 for (cp = input_line_pointer; *cp != '@'; cp++)
8225 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8228 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8230 int len = gotrel[j].len;
8231 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8233 if (gotrel[j].rel[object_64bit] != 0)
8236 char *tmpbuf, *past_reloc;
8238 *rel = gotrel[j].rel[object_64bit];
8242 if (flag_code != CODE_64BIT)
8244 types->bitfield.imm32 = 1;
8245 types->bitfield.disp32 = 1;
8248 *types = gotrel[j].types64;
8251 if (j != 0 && GOT_symbol == NULL)
8252 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8254 /* The length of the first part of our input line. */
8255 first = cp - input_line_pointer;
8257 /* The second part goes from after the reloc token until
8258 (and including) an end_of_line char or comma. */
8259 past_reloc = cp + 1 + len;
8261 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8263 second = cp + 1 - past_reloc;
8265 /* Allocate and copy string. The trailing NUL shouldn't
8266 be necessary, but be safe. */
8267 tmpbuf = XNEWVEC (char, first + second + 2);
8268 memcpy (tmpbuf, input_line_pointer, first);
8269 if (second != 0 && *past_reloc != ' ')
8270 /* Replace the relocation token with ' ', so that
8271 errors like foo@GOTOFF1 will be detected. */
8272 tmpbuf[first++] = ' ';
8274 /* Increment length by 1 if the relocation token is
8279 memcpy (tmpbuf + first, past_reloc, second);
8280 tmpbuf[first + second] = '\0';
8284 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8285 gotrel[j].str, 1 << (5 + object_64bit));
8290 /* Might be a symbol version string. Don't as_bad here. */
8299 /* Parse operands of the form
8300 <symbol>@SECREL32+<nnn>
8302 If we find one, set up the correct relocation in RELOC and copy the
8303 input string, minus the `@SECREL32' into a malloc'd buffer for
8304 parsing by the calling routine. Return this buffer, and if ADJUST
8305 is non-null set it to the length of the string we removed from the
8306 input line. Otherwise return NULL.
8308 This function is copied from the ELF version above adjusted for PE targets. */
8311 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8312 int *adjust ATTRIBUTE_UNUSED,
8313 i386_operand_type *types)
8319 const enum bfd_reloc_code_real rel[2];
8320 const i386_operand_type types64;
8324 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8325 BFD_RELOC_32_SECREL },
8326 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8332 for (cp = input_line_pointer; *cp != '@'; cp++)
8333 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8336 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8338 int len = gotrel[j].len;
8340 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8342 if (gotrel[j].rel[object_64bit] != 0)
8345 char *tmpbuf, *past_reloc;
8347 *rel = gotrel[j].rel[object_64bit];
8353 if (flag_code != CODE_64BIT)
8355 types->bitfield.imm32 = 1;
8356 types->bitfield.disp32 = 1;
8359 *types = gotrel[j].types64;
8362 /* The length of the first part of our input line. */
8363 first = cp - input_line_pointer;
8365 /* The second part goes from after the reloc token until
8366 (and including) an end_of_line char or comma. */
8367 past_reloc = cp + 1 + len;
8369 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8371 second = cp + 1 - past_reloc;
8373 /* Allocate and copy string. The trailing NUL shouldn't
8374 be necessary, but be safe. */
8375 tmpbuf = XNEWVEC (char, first + second + 2);
8376 memcpy (tmpbuf, input_line_pointer, first);
8377 if (second != 0 && *past_reloc != ' ')
8378 /* Replace the relocation token with ' ', so that
8379 errors like foo@SECLREL321 will be detected. */
8380 tmpbuf[first++] = ' ';
8381 memcpy (tmpbuf + first, past_reloc, second);
8382 tmpbuf[first + second] = '\0';
8386 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8387 gotrel[j].str, 1 << (5 + object_64bit));
8392 /* Might be a symbol version string. Don't as_bad here. */
8398 bfd_reloc_code_real_type
8399 x86_cons (expressionS *exp, int size)
8401 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8403 intel_syntax = -intel_syntax;
8406 if (size == 4 || (object_64bit && size == 8))
8408 /* Handle @GOTOFF and the like in an expression. */
8410 char *gotfree_input_line;
8413 save = input_line_pointer;
8414 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8415 if (gotfree_input_line)
8416 input_line_pointer = gotfree_input_line;
8420 if (gotfree_input_line)
8422 /* expression () has merrily parsed up to the end of line,
8423 or a comma - in the wrong buffer. Transfer how far
8424 input_line_pointer has moved to the right buffer. */
8425 input_line_pointer = (save
8426 + (input_line_pointer - gotfree_input_line)
8428 free (gotfree_input_line);
8429 if (exp->X_op == O_constant
8430 || exp->X_op == O_absent
8431 || exp->X_op == O_illegal
8432 || exp->X_op == O_register
8433 || exp->X_op == O_big)
8435 char c = *input_line_pointer;
8436 *input_line_pointer = 0;
8437 as_bad (_("missing or invalid expression `%s'"), save);
8438 *input_line_pointer = c;
8445 intel_syntax = -intel_syntax;
8448 i386_intel_simplify (exp);
8454 signed_cons (int size)
8456 if (flag_code == CODE_64BIT)
8464 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8471 if (exp.X_op == O_symbol)
8472 exp.X_op = O_secrel;
8474 emit_expr (&exp, 4);
8476 while (*input_line_pointer++ == ',');
8478 input_line_pointer--;
8479 demand_empty_rest_of_line ();
8483 /* Handle Vector operations. */
8486 check_VecOperations (char *op_string, char *op_end)
8488 const reg_entry *mask;
8493 && (op_end == NULL || op_string < op_end))
8496 if (*op_string == '{')
8500 /* Check broadcasts. */
8501 if (strncmp (op_string, "1to", 3) == 0)
8506 goto duplicated_vec_op;
8509 if (*op_string == '8')
8511 else if (*op_string == '4')
8513 else if (*op_string == '2')
8515 else if (*op_string == '1'
8516 && *(op_string+1) == '6')
8523 as_bad (_("Unsupported broadcast: `%s'"), saved);
8528 broadcast_op.type = bcst_type;
8529 broadcast_op.operand = this_operand;
8530 i.broadcast = &broadcast_op;
8532 /* Check masking operation. */
8533 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8535 /* k0 can't be used for write mask. */
8536 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8538 as_bad (_("`%s%s' can't be used for write mask"),
8539 register_prefix, mask->reg_name);
8545 mask_op.mask = mask;
8546 mask_op.zeroing = 0;
8547 mask_op.operand = this_operand;
8553 goto duplicated_vec_op;
8555 i.mask->mask = mask;
8557 /* Only "{z}" is allowed here. No need to check
8558 zeroing mask explicitly. */
8559 if (i.mask->operand != this_operand)
8561 as_bad (_("invalid write mask `%s'"), saved);
8568 /* Check zeroing-flag for masking operation. */
8569 else if (*op_string == 'z')
8573 mask_op.mask = NULL;
8574 mask_op.zeroing = 1;
8575 mask_op.operand = this_operand;
8580 if (i.mask->zeroing)
8583 as_bad (_("duplicated `%s'"), saved);
8587 i.mask->zeroing = 1;
8589 /* Only "{%k}" is allowed here. No need to check mask
8590 register explicitly. */
8591 if (i.mask->operand != this_operand)
8593 as_bad (_("invalid zeroing-masking `%s'"),
8602 goto unknown_vec_op;
8604 if (*op_string != '}')
8606 as_bad (_("missing `}' in `%s'"), saved);
8611 /* Strip whitespace since the addition of pseudo prefixes
8612 changed how the scrubber treats '{'. */
8613 if (is_space_char (*op_string))
8619 /* We don't know this one. */
8620 as_bad (_("unknown vector operation: `%s'"), saved);
8624 if (i.mask && i.mask->zeroing && !i.mask->mask)
8626 as_bad (_("zeroing-masking only allowed with write mask"));
8634 i386_immediate (char *imm_start)
8636 char *save_input_line_pointer;
8637 char *gotfree_input_line;
8640 i386_operand_type types;
8642 operand_type_set (&types, ~0);
8644 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8646 as_bad (_("at most %d immediate operands are allowed"),
8647 MAX_IMMEDIATE_OPERANDS);
8651 exp = &im_expressions[i.imm_operands++];
8652 i.op[this_operand].imms = exp;
8654 if (is_space_char (*imm_start))
8657 save_input_line_pointer = input_line_pointer;
8658 input_line_pointer = imm_start;
8660 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8661 if (gotfree_input_line)
8662 input_line_pointer = gotfree_input_line;
8664 exp_seg = expression (exp);
8668 /* Handle vector operations. */
8669 if (*input_line_pointer == '{')
8671 input_line_pointer = check_VecOperations (input_line_pointer,
8673 if (input_line_pointer == NULL)
8677 if (*input_line_pointer)
8678 as_bad (_("junk `%s' after expression"), input_line_pointer);
8680 input_line_pointer = save_input_line_pointer;
8681 if (gotfree_input_line)
8683 free (gotfree_input_line);
8685 if (exp->X_op == O_constant || exp->X_op == O_register)
8686 exp->X_op = O_illegal;
8689 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8693 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8694 i386_operand_type types, const char *imm_start)
8696 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8699 as_bad (_("missing or invalid immediate expression `%s'"),
8703 else if (exp->X_op == O_constant)
8705 /* Size it properly later. */
8706 i.types[this_operand].bitfield.imm64 = 1;
8707 /* If not 64bit, sign extend val. */
8708 if (flag_code != CODE_64BIT
8709 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8711 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8713 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8714 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8715 && exp_seg != absolute_section
8716 && exp_seg != text_section
8717 && exp_seg != data_section
8718 && exp_seg != bss_section
8719 && exp_seg != undefined_section
8720 && !bfd_is_com_section (exp_seg))
8722 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8726 else if (!intel_syntax && exp_seg == reg_section)
8729 as_bad (_("illegal immediate register operand %s"), imm_start);
8734 /* This is an address. The size of the address will be
8735 determined later, depending on destination register,
8736 suffix, or the default for the section. */
8737 i.types[this_operand].bitfield.imm8 = 1;
8738 i.types[this_operand].bitfield.imm16 = 1;
8739 i.types[this_operand].bitfield.imm32 = 1;
8740 i.types[this_operand].bitfield.imm32s = 1;
8741 i.types[this_operand].bitfield.imm64 = 1;
8742 i.types[this_operand] = operand_type_and (i.types[this_operand],
8750 i386_scale (char *scale)
8753 char *save = input_line_pointer;
8755 input_line_pointer = scale;
8756 val = get_absolute_expression ();
8761 i.log2_scale_factor = 0;
8764 i.log2_scale_factor = 1;
8767 i.log2_scale_factor = 2;
8770 i.log2_scale_factor = 3;
8774 char sep = *input_line_pointer;
8776 *input_line_pointer = '\0';
8777 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8779 *input_line_pointer = sep;
8780 input_line_pointer = save;
8784 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8786 as_warn (_("scale factor of %d without an index register"),
8787 1 << i.log2_scale_factor);
8788 i.log2_scale_factor = 0;
8790 scale = input_line_pointer;
8791 input_line_pointer = save;
8796 i386_displacement (char *disp_start, char *disp_end)
8800 char *save_input_line_pointer;
8801 char *gotfree_input_line;
8803 i386_operand_type bigdisp, types = anydisp;
8806 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8808 as_bad (_("at most %d displacement operands are allowed"),
8809 MAX_MEMORY_OPERANDS);
8813 operand_type_set (&bigdisp, 0);
8814 if ((i.types[this_operand].bitfield.jumpabsolute)
8815 || (!current_templates->start->opcode_modifier.jump
8816 && !current_templates->start->opcode_modifier.jumpdword))
8818 bigdisp.bitfield.disp32 = 1;
8819 override = (i.prefix[ADDR_PREFIX] != 0);
8820 if (flag_code == CODE_64BIT)
8824 bigdisp.bitfield.disp32s = 1;
8825 bigdisp.bitfield.disp64 = 1;
8828 else if ((flag_code == CODE_16BIT) ^ override)
8830 bigdisp.bitfield.disp32 = 0;
8831 bigdisp.bitfield.disp16 = 1;
8836 /* For PC-relative branches, the width of the displacement
8837 is dependent upon data size, not address size. */
8838 override = (i.prefix[DATA_PREFIX] != 0);
8839 if (flag_code == CODE_64BIT)
8841 if (override || i.suffix == WORD_MNEM_SUFFIX)
8842 bigdisp.bitfield.disp16 = 1;
8845 bigdisp.bitfield.disp32 = 1;
8846 bigdisp.bitfield.disp32s = 1;
8852 override = (i.suffix == (flag_code != CODE_16BIT
8854 : LONG_MNEM_SUFFIX));
8855 bigdisp.bitfield.disp32 = 1;
8856 if ((flag_code == CODE_16BIT) ^ override)
8858 bigdisp.bitfield.disp32 = 0;
8859 bigdisp.bitfield.disp16 = 1;
8863 i.types[this_operand] = operand_type_or (i.types[this_operand],
8866 exp = &disp_expressions[i.disp_operands];
8867 i.op[this_operand].disps = exp;
8869 save_input_line_pointer = input_line_pointer;
8870 input_line_pointer = disp_start;
8871 END_STRING_AND_SAVE (disp_end);
8873 #ifndef GCC_ASM_O_HACK
8874 #define GCC_ASM_O_HACK 0
8877 END_STRING_AND_SAVE (disp_end + 1);
8878 if (i.types[this_operand].bitfield.baseIndex
8879 && displacement_string_end[-1] == '+')
8881 /* This hack is to avoid a warning when using the "o"
8882 constraint within gcc asm statements.
8885 #define _set_tssldt_desc(n,addr,limit,type) \
8886 __asm__ __volatile__ ( \
8888 "movw %w1,2+%0\n\t" \
8890 "movb %b1,4+%0\n\t" \
8891 "movb %4,5+%0\n\t" \
8892 "movb $0,6+%0\n\t" \
8893 "movb %h1,7+%0\n\t" \
8895 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8897 This works great except that the output assembler ends
8898 up looking a bit weird if it turns out that there is
8899 no offset. You end up producing code that looks like:
8912 So here we provide the missing zero. */
8914 *displacement_string_end = '0';
8917 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8918 if (gotfree_input_line)
8919 input_line_pointer = gotfree_input_line;
8921 exp_seg = expression (exp);
8924 if (*input_line_pointer)
8925 as_bad (_("junk `%s' after expression"), input_line_pointer);
8927 RESTORE_END_STRING (disp_end + 1);
8929 input_line_pointer = save_input_line_pointer;
8930 if (gotfree_input_line)
8932 free (gotfree_input_line);
8934 if (exp->X_op == O_constant || exp->X_op == O_register)
8935 exp->X_op = O_illegal;
8938 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8940 RESTORE_END_STRING (disp_end);
8946 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8947 i386_operand_type types, const char *disp_start)
8949 i386_operand_type bigdisp;
8952 /* We do this to make sure that the section symbol is in
8953 the symbol table. We will ultimately change the relocation
8954 to be relative to the beginning of the section. */
8955 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8956 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8957 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8959 if (exp->X_op != O_symbol)
8962 if (S_IS_LOCAL (exp->X_add_symbol)
8963 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8964 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8965 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8966 exp->X_op = O_subtract;
8967 exp->X_op_symbol = GOT_symbol;
8968 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8969 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8970 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8971 i.reloc[this_operand] = BFD_RELOC_64;
8973 i.reloc[this_operand] = BFD_RELOC_32;
8976 else if (exp->X_op == O_absent
8977 || exp->X_op == O_illegal
8978 || exp->X_op == O_big)
8981 as_bad (_("missing or invalid displacement expression `%s'"),
8986 else if (flag_code == CODE_64BIT
8987 && !i.prefix[ADDR_PREFIX]
8988 && exp->X_op == O_constant)
8990 /* Since displacement is signed extended to 64bit, don't allow
8991 disp32 and turn off disp32s if they are out of range. */
8992 i.types[this_operand].bitfield.disp32 = 0;
8993 if (!fits_in_signed_long (exp->X_add_number))
8995 i.types[this_operand].bitfield.disp32s = 0;
8996 if (i.types[this_operand].bitfield.baseindex)
8998 as_bad (_("0x%lx out range of signed 32bit displacement"),
8999 (long) exp->X_add_number);
9005 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9006 else if (exp->X_op != O_constant
9007 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9008 && exp_seg != absolute_section
9009 && exp_seg != text_section
9010 && exp_seg != data_section
9011 && exp_seg != bss_section
9012 && exp_seg != undefined_section
9013 && !bfd_is_com_section (exp_seg))
9015 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9020 /* Check if this is a displacement only operand. */
9021 bigdisp = i.types[this_operand];
9022 bigdisp.bitfield.disp8 = 0;
9023 bigdisp.bitfield.disp16 = 0;
9024 bigdisp.bitfield.disp32 = 0;
9025 bigdisp.bitfield.disp32s = 0;
9026 bigdisp.bitfield.disp64 = 0;
9027 if (operand_type_all_zero (&bigdisp))
9028 i.types[this_operand] = operand_type_and (i.types[this_operand],
9034 /* Return the active addressing mode, taking address override and
9035 registers forming the address into consideration. Update the
9036 address override prefix if necessary. */
9038 static enum flag_code
9039 i386_addressing_mode (void)
9041 enum flag_code addr_mode;
9043 if (i.prefix[ADDR_PREFIX])
9044 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9047 addr_mode = flag_code;
9049 #if INFER_ADDR_PREFIX
9050 if (i.mem_operands == 0)
9052 /* Infer address prefix from the first memory operand. */
9053 const reg_entry *addr_reg = i.base_reg;
9055 if (addr_reg == NULL)
9056 addr_reg = i.index_reg;
9060 if (addr_reg->reg_num == RegEip
9061 || addr_reg->reg_num == RegEiz
9062 || addr_reg->reg_type.bitfield.dword)
9063 addr_mode = CODE_32BIT;
9064 else if (flag_code != CODE_64BIT
9065 && addr_reg->reg_type.bitfield.word)
9066 addr_mode = CODE_16BIT;
9068 if (addr_mode != flag_code)
9070 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9072 /* Change the size of any displacement too. At most one
9073 of Disp16 or Disp32 is set.
9074 FIXME. There doesn't seem to be any real need for
9075 separate Disp16 and Disp32 flags. The same goes for
9076 Imm16 and Imm32. Removing them would probably clean
9077 up the code quite a lot. */
9078 if (flag_code != CODE_64BIT
9079 && (i.types[this_operand].bitfield.disp16
9080 || i.types[this_operand].bitfield.disp32))
9081 i.types[this_operand]
9082 = operand_type_xor (i.types[this_operand], disp16_32);
9092 /* Make sure the memory operand we've been dealt is valid.
9093 Return 1 on success, 0 on a failure. */
9096 i386_index_check (const char *operand_string)
9098 const char *kind = "base/index";
9099 enum flag_code addr_mode = i386_addressing_mode ();
9101 if (current_templates->start->opcode_modifier.isstring
9102 && !current_templates->start->opcode_modifier.immext
9103 && (current_templates->end[-1].opcode_modifier.isstring
9106 /* Memory operands of string insns are special in that they only allow
9107 a single register (rDI, rSI, or rBX) as their memory address. */
9108 const reg_entry *expected_reg;
9109 static const char *di_si[][2] =
9115 static const char *bx[] = { "ebx", "bx", "rbx" };
9117 kind = "string address";
9119 if (current_templates->start->opcode_modifier.repprefixok)
9121 i386_operand_type type = current_templates->end[-1].operand_types[0];
9123 if (!type.bitfield.baseindex
9124 || ((!i.mem_operands != !intel_syntax)
9125 && current_templates->end[-1].operand_types[1]
9126 .bitfield.baseindex))
9127 type = current_templates->end[-1].operand_types[1];
9128 expected_reg = hash_find (reg_hash,
9129 di_si[addr_mode][type.bitfield.esseg]);
9133 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9135 if (i.base_reg != expected_reg
9137 || operand_type_check (i.types[this_operand], disp))
9139 /* The second memory operand must have the same size as
9143 && !((addr_mode == CODE_64BIT
9144 && i.base_reg->reg_type.bitfield.qword)
9145 || (addr_mode == CODE_32BIT
9146 ? i.base_reg->reg_type.bitfield.dword
9147 : i.base_reg->reg_type.bitfield.word)))
9150 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9152 intel_syntax ? '[' : '(',
9154 expected_reg->reg_name,
9155 intel_syntax ? ']' : ')');
9162 as_bad (_("`%s' is not a valid %s expression"),
9163 operand_string, kind);
9168 if (addr_mode != CODE_16BIT)
9170 /* 32-bit/64-bit checks. */
9172 && (addr_mode == CODE_64BIT
9173 ? !i.base_reg->reg_type.bitfield.qword
9174 : !i.base_reg->reg_type.bitfield.dword)
9176 || (i.base_reg->reg_num
9177 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9179 && !i.index_reg->reg_type.bitfield.xmmword
9180 && !i.index_reg->reg_type.bitfield.ymmword
9181 && !i.index_reg->reg_type.bitfield.zmmword
9182 && ((addr_mode == CODE_64BIT
9183 ? !(i.index_reg->reg_type.bitfield.qword
9184 || i.index_reg->reg_num == RegRiz)
9185 : !(i.index_reg->reg_type.bitfield.dword
9186 || i.index_reg->reg_num == RegEiz))
9187 || !i.index_reg->reg_type.bitfield.baseindex)))
9190 /* bndmk, bndldx, and bndstx have special restrictions. */
9191 if (current_templates->start->base_opcode == 0xf30f1b
9192 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9194 /* They cannot use RIP-relative addressing. */
9195 if (i.base_reg && i.base_reg->reg_num == RegRip)
9197 as_bad (_("`%s' cannot be used here"), operand_string);
9201 /* bndldx and bndstx ignore their scale factor. */
9202 if (current_templates->start->base_opcode != 0xf30f1b
9203 && i.log2_scale_factor)
9204 as_warn (_("register scaling is being ignored here"));
9209 /* 16-bit checks. */
9211 && (!i.base_reg->reg_type.bitfield.word
9212 || !i.base_reg->reg_type.bitfield.baseindex))
9214 && (!i.index_reg->reg_type.bitfield.word
9215 || !i.index_reg->reg_type.bitfield.baseindex
9217 && i.base_reg->reg_num < 6
9218 && i.index_reg->reg_num >= 6
9219 && i.log2_scale_factor == 0))))
9226 /* Handle vector immediates. */
9229 RC_SAE_immediate (const char *imm_start)
9231 unsigned int match_found, j;
9232 const char *pstr = imm_start;
9240 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9242 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9246 rc_op.type = RC_NamesTable[j].type;
9247 rc_op.operand = this_operand;
9248 i.rounding = &rc_op;
9252 as_bad (_("duplicated `%s'"), imm_start);
9255 pstr += RC_NamesTable[j].len;
9265 as_bad (_("Missing '}': '%s'"), imm_start);
9268 /* RC/SAE immediate string should contain nothing more. */;
9271 as_bad (_("Junk after '}': '%s'"), imm_start);
9275 exp = &im_expressions[i.imm_operands++];
9276 i.op[this_operand].imms = exp;
9278 exp->X_op = O_constant;
9279 exp->X_add_number = 0;
9280 exp->X_add_symbol = (symbolS *) 0;
9281 exp->X_op_symbol = (symbolS *) 0;
9283 i.types[this_operand].bitfield.imm8 = 1;
9287 /* Only string instructions can have a second memory operand, so
9288 reduce current_templates to just those if it contains any. */
9290 maybe_adjust_templates (void)
9292 const insn_template *t;
9294 gas_assert (i.mem_operands == 1);
9296 for (t = current_templates->start; t < current_templates->end; ++t)
9297 if (t->opcode_modifier.isstring)
9300 if (t < current_templates->end)
9302 static templates aux_templates;
9303 bfd_boolean recheck;
9305 aux_templates.start = t;
9306 for (; t < current_templates->end; ++t)
9307 if (!t->opcode_modifier.isstring)
9309 aux_templates.end = t;
9311 /* Determine whether to re-check the first memory operand. */
9312 recheck = (aux_templates.start != current_templates->start
9313 || t != current_templates->end);
9315 current_templates = &aux_templates;
9320 if (i.memop1_string != NULL
9321 && i386_index_check (i.memop1_string) == 0)
9330 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9334 i386_att_operand (char *operand_string)
9338 char *op_string = operand_string;
9340 if (is_space_char (*op_string))
9343 /* We check for an absolute prefix (differentiating,
9344 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9345 if (*op_string == ABSOLUTE_PREFIX)
9348 if (is_space_char (*op_string))
9350 i.types[this_operand].bitfield.jumpabsolute = 1;
9353 /* Check if operand is a register. */
9354 if ((r = parse_register (op_string, &end_op)) != NULL)
9356 i386_operand_type temp;
9358 /* Check for a segment override by searching for ':' after a
9359 segment register. */
9361 if (is_space_char (*op_string))
9363 if (*op_string == ':'
9364 && (r->reg_type.bitfield.sreg2
9365 || r->reg_type.bitfield.sreg3))
9370 i.seg[i.mem_operands] = &es;
9373 i.seg[i.mem_operands] = &cs;
9376 i.seg[i.mem_operands] = &ss;
9379 i.seg[i.mem_operands] = &ds;
9382 i.seg[i.mem_operands] = &fs;
9385 i.seg[i.mem_operands] = &gs;
9389 /* Skip the ':' and whitespace. */
9391 if (is_space_char (*op_string))
9394 if (!is_digit_char (*op_string)
9395 && !is_identifier_char (*op_string)
9396 && *op_string != '('
9397 && *op_string != ABSOLUTE_PREFIX)
9399 as_bad (_("bad memory operand `%s'"), op_string);
9402 /* Handle case of %es:*foo. */
9403 if (*op_string == ABSOLUTE_PREFIX)
9406 if (is_space_char (*op_string))
9408 i.types[this_operand].bitfield.jumpabsolute = 1;
9410 goto do_memory_reference;
9413 /* Handle vector operations. */
9414 if (*op_string == '{')
9416 op_string = check_VecOperations (op_string, NULL);
9417 if (op_string == NULL)
9423 as_bad (_("junk `%s' after register"), op_string);
9427 temp.bitfield.baseindex = 0;
9428 i.types[this_operand] = operand_type_or (i.types[this_operand],
9430 i.types[this_operand].bitfield.unspecified = 0;
9431 i.op[this_operand].regs = r;
9434 else if (*op_string == REGISTER_PREFIX)
9436 as_bad (_("bad register name `%s'"), op_string);
9439 else if (*op_string == IMMEDIATE_PREFIX)
9442 if (i.types[this_operand].bitfield.jumpabsolute)
9444 as_bad (_("immediate operand illegal with absolute jump"));
9447 if (!i386_immediate (op_string))
9450 else if (RC_SAE_immediate (operand_string))
9452 /* If it is a RC or SAE immediate, do nothing. */
9455 else if (is_digit_char (*op_string)
9456 || is_identifier_char (*op_string)
9457 || *op_string == '"'
9458 || *op_string == '(')
9460 /* This is a memory reference of some sort. */
9463 /* Start and end of displacement string expression (if found). */
9464 char *displacement_string_start;
9465 char *displacement_string_end;
9468 do_memory_reference:
9469 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9471 if ((i.mem_operands == 1
9472 && !current_templates->start->opcode_modifier.isstring)
9473 || i.mem_operands == 2)
9475 as_bad (_("too many memory references for `%s'"),
9476 current_templates->start->name);
9480 /* Check for base index form. We detect the base index form by
9481 looking for an ')' at the end of the operand, searching
9482 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9484 base_string = op_string + strlen (op_string);
9486 /* Handle vector operations. */
9487 vop_start = strchr (op_string, '{');
9488 if (vop_start && vop_start < base_string)
9490 if (check_VecOperations (vop_start, base_string) == NULL)
9492 base_string = vop_start;
9496 if (is_space_char (*base_string))
9499 /* If we only have a displacement, set-up for it to be parsed later. */
9500 displacement_string_start = op_string;
9501 displacement_string_end = base_string + 1;
9503 if (*base_string == ')')
9506 unsigned int parens_balanced = 1;
9507 /* We've already checked that the number of left & right ()'s are
9508 equal, so this loop will not be infinite. */
9512 if (*base_string == ')')
9514 if (*base_string == '(')
9517 while (parens_balanced);
9519 temp_string = base_string;
9521 /* Skip past '(' and whitespace. */
9523 if (is_space_char (*base_string))
9526 if (*base_string == ','
9527 || ((i.base_reg = parse_register (base_string, &end_op))
9530 displacement_string_end = temp_string;
9532 i.types[this_operand].bitfield.baseindex = 1;
9536 base_string = end_op;
9537 if (is_space_char (*base_string))
9541 /* There may be an index reg or scale factor here. */
9542 if (*base_string == ',')
9545 if (is_space_char (*base_string))
9548 if ((i.index_reg = parse_register (base_string, &end_op))
9551 base_string = end_op;
9552 if (is_space_char (*base_string))
9554 if (*base_string == ',')
9557 if (is_space_char (*base_string))
9560 else if (*base_string != ')')
9562 as_bad (_("expecting `,' or `)' "
9563 "after index register in `%s'"),
9568 else if (*base_string == REGISTER_PREFIX)
9570 end_op = strchr (base_string, ',');
9573 as_bad (_("bad register name `%s'"), base_string);
9577 /* Check for scale factor. */
9578 if (*base_string != ')')
9580 char *end_scale = i386_scale (base_string);
9585 base_string = end_scale;
9586 if (is_space_char (*base_string))
9588 if (*base_string != ')')
9590 as_bad (_("expecting `)' "
9591 "after scale factor in `%s'"),
9596 else if (!i.index_reg)
9598 as_bad (_("expecting index register or scale factor "
9599 "after `,'; got '%c'"),
9604 else if (*base_string != ')')
9606 as_bad (_("expecting `,' or `)' "
9607 "after base register in `%s'"),
9612 else if (*base_string == REGISTER_PREFIX)
9614 end_op = strchr (base_string, ',');
9617 as_bad (_("bad register name `%s'"), base_string);
9622 /* If there's an expression beginning the operand, parse it,
9623 assuming displacement_string_start and
9624 displacement_string_end are meaningful. */
9625 if (displacement_string_start != displacement_string_end)
9627 if (!i386_displacement (displacement_string_start,
9628 displacement_string_end))
9632 /* Special case for (%dx) while doing input/output op. */
9634 && operand_type_equal (&i.base_reg->reg_type,
9635 ®16_inoutportreg)
9637 && i.log2_scale_factor == 0
9638 && i.seg[i.mem_operands] == 0
9639 && !operand_type_check (i.types[this_operand], disp))
9641 i.types[this_operand] = inoutportreg;
9645 if (i386_index_check (operand_string) == 0)
9647 i.types[this_operand].bitfield.mem = 1;
9648 if (i.mem_operands == 0)
9649 i.memop1_string = xstrdup (operand_string);
9654 /* It's not a memory operand; argh! */
9655 as_bad (_("invalid char %s beginning operand %d `%s'"),
9656 output_invalid (*op_string),
9661 return 1; /* Normal return. */
9664 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9665 that an rs_machine_dependent frag may reach. */
9668 i386_frag_max_var (fragS *frag)
9670 /* The only relaxable frags are for jumps.
9671 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9672 gas_assert (frag->fr_type == rs_machine_dependent);
9673 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9676 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9678 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9680 /* STT_GNU_IFUNC symbol must go through PLT. */
9681 if ((symbol_get_bfdsym (fr_symbol)->flags
9682 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9685 if (!S_IS_EXTERNAL (fr_symbol))
9686 /* Symbol may be weak or local. */
9687 return !S_IS_WEAK (fr_symbol);
9689 /* Global symbols with non-default visibility can't be preempted. */
9690 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9693 if (fr_var != NO_RELOC)
9694 switch ((enum bfd_reloc_code_real) fr_var)
9696 case BFD_RELOC_386_PLT32:
9697 case BFD_RELOC_X86_64_PLT32:
9698 /* Symbol with PLT relocation may be preempted. */
9704 /* Global symbols with default visibility in a shared library may be
9705 preempted by another definition. */
9710 /* md_estimate_size_before_relax()
9712 Called just before relax() for rs_machine_dependent frags. The x86
9713 assembler uses these frags to handle variable size jump
9716 Any symbol that is now undefined will not become defined.
9717 Return the correct fr_subtype in the frag.
9718 Return the initial "guess for variable size of frag" to caller.
9719 The guess is actually the growth beyond the fixed part. Whatever
9720 we do to grow the fixed or variable part contributes to our
9724 md_estimate_size_before_relax (fragS *fragP, segT segment)
9726 /* We've already got fragP->fr_subtype right; all we have to do is
9727 check for un-relaxable symbols. On an ELF system, we can't relax
9728 an externally visible symbol, because it may be overridden by a
9730 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9731 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9733 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9736 #if defined (OBJ_COFF) && defined (TE_PE)
9737 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9738 && S_IS_WEAK (fragP->fr_symbol))
9742 /* Symbol is undefined in this segment, or we need to keep a
9743 reloc so that weak symbols can be overridden. */
9744 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9745 enum bfd_reloc_code_real reloc_type;
9746 unsigned char *opcode;
9749 if (fragP->fr_var != NO_RELOC)
9750 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9752 reloc_type = BFD_RELOC_16_PCREL;
9753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9754 else if (need_plt32_p (fragP->fr_symbol))
9755 reloc_type = BFD_RELOC_X86_64_PLT32;
9758 reloc_type = BFD_RELOC_32_PCREL;
9760 old_fr_fix = fragP->fr_fix;
9761 opcode = (unsigned char *) fragP->fr_opcode;
9763 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9766 /* Make jmp (0xeb) a (d)word displacement jump. */
9768 fragP->fr_fix += size;
9769 fix_new (fragP, old_fr_fix, size,
9771 fragP->fr_offset, 1,
9777 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9779 /* Negate the condition, and branch past an
9780 unconditional jump. */
9783 /* Insert an unconditional jump. */
9785 /* We added two extra opcode bytes, and have a two byte
9787 fragP->fr_fix += 2 + 2;
9788 fix_new (fragP, old_fr_fix + 2, 2,
9790 fragP->fr_offset, 1,
9797 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9802 fixP = fix_new (fragP, old_fr_fix, 1,
9804 fragP->fr_offset, 1,
9806 fixP->fx_signed = 1;
9810 /* This changes the byte-displacement jump 0x7N
9811 to the (d)word-displacement jump 0x0f,0x8N. */
9812 opcode[1] = opcode[0] + 0x10;
9813 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9814 /* We've added an opcode byte. */
9815 fragP->fr_fix += 1 + size;
9816 fix_new (fragP, old_fr_fix + 1, size,
9818 fragP->fr_offset, 1,
9823 BAD_CASE (fragP->fr_subtype);
9827 return fragP->fr_fix - old_fr_fix;
9830 /* Guess size depending on current relax state. Initially the relax
9831 state will correspond to a short jump and we return 1, because
9832 the variable part of the frag (the branch offset) is one byte
9833 long. However, we can relax a section more than once and in that
9834 case we must either set fr_subtype back to the unrelaxed state,
9835 or return the value for the appropriate branch. */
9836 return md_relax_table[fragP->fr_subtype].rlx_length;
9839 /* Called after relax() is finished.
9841 In: Address of frag.
9842 fr_type == rs_machine_dependent.
9843 fr_subtype is what the address relaxed to.
9845 Out: Any fixSs and constants are set up.
9846 Caller will turn frag into a ".space 0". */
9849 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9852 unsigned char *opcode;
9853 unsigned char *where_to_put_displacement = NULL;
9854 offsetT target_address;
9855 offsetT opcode_address;
9856 unsigned int extension = 0;
9857 offsetT displacement_from_opcode_start;
9859 opcode = (unsigned char *) fragP->fr_opcode;
9861 /* Address we want to reach in file space. */
9862 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9864 /* Address opcode resides at in file space. */
9865 opcode_address = fragP->fr_address + fragP->fr_fix;
9867 /* Displacement from opcode start to fill into instruction. */
9868 displacement_from_opcode_start = target_address - opcode_address;
9870 if ((fragP->fr_subtype & BIG) == 0)
9872 /* Don't have to change opcode. */
9873 extension = 1; /* 1 opcode + 1 displacement */
9874 where_to_put_displacement = &opcode[1];
9878 if (no_cond_jump_promotion
9879 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9880 as_warn_where (fragP->fr_file, fragP->fr_line,
9881 _("long jump required"));
9883 switch (fragP->fr_subtype)
9885 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9886 extension = 4; /* 1 opcode + 4 displacement */
9888 where_to_put_displacement = &opcode[1];
9891 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9892 extension = 2; /* 1 opcode + 2 displacement */
9894 where_to_put_displacement = &opcode[1];
9897 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9898 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9899 extension = 5; /* 2 opcode + 4 displacement */
9900 opcode[1] = opcode[0] + 0x10;
9901 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9902 where_to_put_displacement = &opcode[2];
9905 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9906 extension = 3; /* 2 opcode + 2 displacement */
9907 opcode[1] = opcode[0] + 0x10;
9908 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9909 where_to_put_displacement = &opcode[2];
9912 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9917 where_to_put_displacement = &opcode[3];
9921 BAD_CASE (fragP->fr_subtype);
9926 /* If size if less then four we are sure that the operand fits,
9927 but if it's 4, then it could be that the displacement is larger
9929 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9931 && ((addressT) (displacement_from_opcode_start - extension
9932 + ((addressT) 1 << 31))
9933 > (((addressT) 2 << 31) - 1)))
9935 as_bad_where (fragP->fr_file, fragP->fr_line,
9936 _("jump target out of range"));
9937 /* Make us emit 0. */
9938 displacement_from_opcode_start = extension;
9940 /* Now put displacement after opcode. */
9941 md_number_to_chars ((char *) where_to_put_displacement,
9942 (valueT) (displacement_from_opcode_start - extension),
9943 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9944 fragP->fr_fix += extension;
9947 /* Apply a fixup (fixP) to segment data, once it has been determined
9948 by our caller that we have all the info we need to fix it up.
9950 Parameter valP is the pointer to the value of the bits.
9952 On the 386, immediates, displacements, and data pointers are all in
9953 the same (little-endian) format, so we don't need to care about which
9957 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9959 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9960 valueT value = *valP;
9962 #if !defined (TE_Mach)
9965 switch (fixP->fx_r_type)
9971 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9974 case BFD_RELOC_X86_64_32S:
9975 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9978 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9981 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9986 if (fixP->fx_addsy != NULL
9987 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9988 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9989 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9990 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9991 && !use_rela_relocations)
9993 /* This is a hack. There should be a better way to handle this.
9994 This covers for the fact that bfd_install_relocation will
9995 subtract the current location (for partial_inplace, PC relative
9996 relocations); see more below. */
10000 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10003 value += fixP->fx_where + fixP->fx_frag->fr_address;
10005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10008 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10010 if ((sym_seg == seg
10011 || (symbol_section_p (fixP->fx_addsy)
10012 && sym_seg != absolute_section))
10013 && !generic_force_reloc (fixP))
10015 /* Yes, we add the values in twice. This is because
10016 bfd_install_relocation subtracts them out again. I think
10017 bfd_install_relocation is broken, but I don't dare change
10019 value += fixP->fx_where + fixP->fx_frag->fr_address;
10023 #if defined (OBJ_COFF) && defined (TE_PE)
10024 /* For some reason, the PE format does not store a
10025 section address offset for a PC relative symbol. */
10026 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10027 || S_IS_WEAK (fixP->fx_addsy))
10028 value += md_pcrel_from (fixP);
10031 #if defined (OBJ_COFF) && defined (TE_PE)
10032 if (fixP->fx_addsy != NULL
10033 && S_IS_WEAK (fixP->fx_addsy)
10034 /* PR 16858: Do not modify weak function references. */
10035 && ! fixP->fx_pcrel)
10037 #if !defined (TE_PEP)
10038 /* For x86 PE weak function symbols are neither PC-relative
10039 nor do they set S_IS_FUNCTION. So the only reliable way
10040 to detect them is to check the flags of their containing
10042 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10043 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10047 value -= S_GET_VALUE (fixP->fx_addsy);
10051 /* Fix a few things - the dynamic linker expects certain values here,
10052 and we must not disappoint it. */
10053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10054 if (IS_ELF && fixP->fx_addsy)
10055 switch (fixP->fx_r_type)
10057 case BFD_RELOC_386_PLT32:
10058 case BFD_RELOC_X86_64_PLT32:
10059 /* Make the jump instruction point to the address of the operand. At
10060 runtime we merely add the offset to the actual PLT entry. */
10064 case BFD_RELOC_386_TLS_GD:
10065 case BFD_RELOC_386_TLS_LDM:
10066 case BFD_RELOC_386_TLS_IE_32:
10067 case BFD_RELOC_386_TLS_IE:
10068 case BFD_RELOC_386_TLS_GOTIE:
10069 case BFD_RELOC_386_TLS_GOTDESC:
10070 case BFD_RELOC_X86_64_TLSGD:
10071 case BFD_RELOC_X86_64_TLSLD:
10072 case BFD_RELOC_X86_64_GOTTPOFF:
10073 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10074 value = 0; /* Fully resolved at runtime. No addend. */
10076 case BFD_RELOC_386_TLS_LE:
10077 case BFD_RELOC_386_TLS_LDO_32:
10078 case BFD_RELOC_386_TLS_LE_32:
10079 case BFD_RELOC_X86_64_DTPOFF32:
10080 case BFD_RELOC_X86_64_DTPOFF64:
10081 case BFD_RELOC_X86_64_TPOFF32:
10082 case BFD_RELOC_X86_64_TPOFF64:
10083 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10086 case BFD_RELOC_386_TLS_DESC_CALL:
10087 case BFD_RELOC_X86_64_TLSDESC_CALL:
10088 value = 0; /* Fully resolved at runtime. No addend. */
10089 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10093 case BFD_RELOC_VTABLE_INHERIT:
10094 case BFD_RELOC_VTABLE_ENTRY:
10101 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10103 #endif /* !defined (TE_Mach) */
10105 /* Are we finished with this relocation now? */
10106 if (fixP->fx_addsy == NULL)
10108 #if defined (OBJ_COFF) && defined (TE_PE)
10109 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10112 /* Remember value for tc_gen_reloc. */
10113 fixP->fx_addnumber = value;
10114 /* Clear out the frag for now. */
10118 else if (use_rela_relocations)
10120 fixP->fx_no_overflow = 1;
10121 /* Remember value for tc_gen_reloc. */
10122 fixP->fx_addnumber = value;
10126 md_number_to_chars (p, value, fixP->fx_size);
10130 md_atof (int type, char *litP, int *sizeP)
10132 /* This outputs the LITTLENUMs in REVERSE order;
10133 in accord with the bigendian 386. */
10134 return ieee_md_atof (type, litP, sizeP, FALSE);
10137 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10140 output_invalid (int c)
10143 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10146 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10147 "(0x%x)", (unsigned char) c);
10148 return output_invalid_buf;
10151 /* REG_STRING starts *before* REGISTER_PREFIX. */
10153 static const reg_entry *
10154 parse_real_register (char *reg_string, char **end_op)
10156 char *s = reg_string;
10158 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10159 const reg_entry *r;
10161 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10162 if (*s == REGISTER_PREFIX)
10165 if (is_space_char (*s))
10168 p = reg_name_given;
10169 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10171 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10172 return (const reg_entry *) NULL;
10176 /* For naked regs, make sure that we are not dealing with an identifier.
10177 This prevents confusing an identifier like `eax_var' with register
10179 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10180 return (const reg_entry *) NULL;
10184 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10186 /* Handle floating point regs, allowing spaces in the (i) part. */
10187 if (r == i386_regtab /* %st is first entry of table */)
10189 if (!cpu_arch_flags.bitfield.cpu8087
10190 && !cpu_arch_flags.bitfield.cpu287
10191 && !cpu_arch_flags.bitfield.cpu387)
10192 return (const reg_entry *) NULL;
10194 if (is_space_char (*s))
10199 if (is_space_char (*s))
10201 if (*s >= '0' && *s <= '7')
10203 int fpr = *s - '0';
10205 if (is_space_char (*s))
10210 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10215 /* We have "%st(" then garbage. */
10216 return (const reg_entry *) NULL;
10220 if (r == NULL || allow_pseudo_reg)
10223 if (operand_type_all_zero (&r->reg_type))
10224 return (const reg_entry *) NULL;
10226 if ((r->reg_type.bitfield.dword
10227 || r->reg_type.bitfield.sreg3
10228 || r->reg_type.bitfield.control
10229 || r->reg_type.bitfield.debug
10230 || r->reg_type.bitfield.test)
10231 && !cpu_arch_flags.bitfield.cpui386)
10232 return (const reg_entry *) NULL;
10234 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10235 return (const reg_entry *) NULL;
10237 if (!cpu_arch_flags.bitfield.cpuavx512f)
10239 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10240 return (const reg_entry *) NULL;
10242 if (!cpu_arch_flags.bitfield.cpuavx)
10244 if (r->reg_type.bitfield.ymmword)
10245 return (const reg_entry *) NULL;
10247 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10248 return (const reg_entry *) NULL;
10252 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10253 return (const reg_entry *) NULL;
10255 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10256 if (!allow_index_reg
10257 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10258 return (const reg_entry *) NULL;
10260 /* Upper 16 vector registers are only available with VREX in 64bit
10261 mode, and require EVEX encoding. */
10262 if (r->reg_flags & RegVRex)
10264 if (!cpu_arch_flags.bitfield.cpuvrex
10265 || flag_code != CODE_64BIT)
10266 return (const reg_entry *) NULL;
10268 i.vec_encoding = vex_encoding_evex;
10271 if (((r->reg_flags & (RegRex64 | RegRex))
10272 || r->reg_type.bitfield.qword)
10273 && (!cpu_arch_flags.bitfield.cpulm
10274 || !operand_type_equal (&r->reg_type, &control))
10275 && flag_code != CODE_64BIT)
10276 return (const reg_entry *) NULL;
10278 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10279 return (const reg_entry *) NULL;
10284 /* REG_STRING starts *before* REGISTER_PREFIX. */
10286 static const reg_entry *
10287 parse_register (char *reg_string, char **end_op)
10289 const reg_entry *r;
10291 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10292 r = parse_real_register (reg_string, end_op);
10297 char *save = input_line_pointer;
10301 input_line_pointer = reg_string;
10302 c = get_symbol_name (®_string);
10303 symbolP = symbol_find (reg_string);
10304 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10306 const expressionS *e = symbol_get_value_expression (symbolP);
10308 know (e->X_op == O_register);
10309 know (e->X_add_number >= 0
10310 && (valueT) e->X_add_number < i386_regtab_size);
10311 r = i386_regtab + e->X_add_number;
10312 if ((r->reg_flags & RegVRex))
10313 i.vec_encoding = vex_encoding_evex;
10314 *end_op = input_line_pointer;
10316 *input_line_pointer = c;
10317 input_line_pointer = save;
10323 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10325 const reg_entry *r;
10326 char *end = input_line_pointer;
10329 r = parse_register (name, &input_line_pointer);
10330 if (r && end <= input_line_pointer)
10332 *nextcharP = *input_line_pointer;
10333 *input_line_pointer = 0;
10334 e->X_op = O_register;
10335 e->X_add_number = r - i386_regtab;
10338 input_line_pointer = end;
10340 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10344 md_operand (expressionS *e)
10347 const reg_entry *r;
10349 switch (*input_line_pointer)
10351 case REGISTER_PREFIX:
10352 r = parse_real_register (input_line_pointer, &end);
10355 e->X_op = O_register;
10356 e->X_add_number = r - i386_regtab;
10357 input_line_pointer = end;
10362 gas_assert (intel_syntax);
10363 end = input_line_pointer++;
10365 if (*input_line_pointer == ']')
10367 ++input_line_pointer;
10368 e->X_op_symbol = make_expr_symbol (e);
10369 e->X_add_symbol = NULL;
10370 e->X_add_number = 0;
10375 e->X_op = O_absent;
10376 input_line_pointer = end;
10383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10384 const char *md_shortopts = "kVQ:sqnO::";
10386 const char *md_shortopts = "qnO::";
10389 #define OPTION_32 (OPTION_MD_BASE + 0)
10390 #define OPTION_64 (OPTION_MD_BASE + 1)
10391 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10392 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10393 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10394 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10395 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10396 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10397 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10398 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10399 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10400 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10401 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10402 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10403 #define OPTION_X32 (OPTION_MD_BASE + 14)
10404 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10405 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10406 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10407 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10408 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10409 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10410 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10411 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10412 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10413 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10415 struct option md_longopts[] =
10417 {"32", no_argument, NULL, OPTION_32},
10418 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10419 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10420 {"64", no_argument, NULL, OPTION_64},
10422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10423 {"x32", no_argument, NULL, OPTION_X32},
10424 {"mshared", no_argument, NULL, OPTION_MSHARED},
10426 {"divide", no_argument, NULL, OPTION_DIVIDE},
10427 {"march", required_argument, NULL, OPTION_MARCH},
10428 {"mtune", required_argument, NULL, OPTION_MTUNE},
10429 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10430 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10431 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10432 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10433 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10434 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10435 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10436 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10437 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10438 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10439 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10440 # if defined (TE_PE) || defined (TE_PEP)
10441 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10443 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10444 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10445 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10446 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10447 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10448 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10449 {NULL, no_argument, NULL, 0}
10451 size_t md_longopts_size = sizeof (md_longopts);
10454 md_parse_option (int c, const char *arg)
10457 char *arch, *next, *saved;
10462 optimize_align_code = 0;
10466 quiet_warnings = 1;
10469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10470 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10471 should be emitted or not. FIXME: Not implemented. */
10475 /* -V: SVR4 argument to print version ID. */
10477 print_version_id ();
10480 /* -k: Ignore for FreeBSD compatibility. */
10485 /* -s: On i386 Solaris, this tells the native assembler to use
10486 .stab instead of .stab.excl. We always use .stab anyhow. */
10489 case OPTION_MSHARED:
10493 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10494 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10497 const char **list, **l;
10499 list = bfd_target_list ();
10500 for (l = list; *l != NULL; l++)
10501 if (CONST_STRNEQ (*l, "elf64-x86-64")
10502 || strcmp (*l, "coff-x86-64") == 0
10503 || strcmp (*l, "pe-x86-64") == 0
10504 || strcmp (*l, "pei-x86-64") == 0
10505 || strcmp (*l, "mach-o-x86-64") == 0)
10507 default_arch = "x86_64";
10511 as_fatal (_("no compiled in support for x86_64"));
10517 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10521 const char **list, **l;
10523 list = bfd_target_list ();
10524 for (l = list; *l != NULL; l++)
10525 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10527 default_arch = "x86_64:32";
10531 as_fatal (_("no compiled in support for 32bit x86_64"));
10535 as_fatal (_("32bit x86_64 is only supported for ELF"));
10540 default_arch = "i386";
10543 case OPTION_DIVIDE:
10544 #ifdef SVR4_COMMENT_CHARS
10549 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10551 for (s = i386_comment_chars; *s != '\0'; s++)
10555 i386_comment_chars = n;
10561 saved = xstrdup (arg);
10563 /* Allow -march=+nosse. */
10569 as_fatal (_("invalid -march= option: `%s'"), arg);
10570 next = strchr (arch, '+');
10573 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10575 if (strcmp (arch, cpu_arch [j].name) == 0)
10578 if (! cpu_arch[j].flags.bitfield.cpui386)
10581 cpu_arch_name = cpu_arch[j].name;
10582 cpu_sub_arch_name = NULL;
10583 cpu_arch_flags = cpu_arch[j].flags;
10584 cpu_arch_isa = cpu_arch[j].type;
10585 cpu_arch_isa_flags = cpu_arch[j].flags;
10586 if (!cpu_arch_tune_set)
10588 cpu_arch_tune = cpu_arch_isa;
10589 cpu_arch_tune_flags = cpu_arch_isa_flags;
10593 else if (*cpu_arch [j].name == '.'
10594 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10596 /* ISA extension. */
10597 i386_cpu_flags flags;
10599 flags = cpu_flags_or (cpu_arch_flags,
10600 cpu_arch[j].flags);
10602 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10604 if (cpu_sub_arch_name)
10606 char *name = cpu_sub_arch_name;
10607 cpu_sub_arch_name = concat (name,
10609 (const char *) NULL);
10613 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10614 cpu_arch_flags = flags;
10615 cpu_arch_isa_flags = flags;
10619 = cpu_flags_or (cpu_arch_isa_flags,
10620 cpu_arch[j].flags);
10625 if (j >= ARRAY_SIZE (cpu_arch))
10627 /* Disable an ISA extension. */
10628 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10629 if (strcmp (arch, cpu_noarch [j].name) == 0)
10631 i386_cpu_flags flags;
10633 flags = cpu_flags_and_not (cpu_arch_flags,
10634 cpu_noarch[j].flags);
10635 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10637 if (cpu_sub_arch_name)
10639 char *name = cpu_sub_arch_name;
10640 cpu_sub_arch_name = concat (arch,
10641 (const char *) NULL);
10645 cpu_sub_arch_name = xstrdup (arch);
10646 cpu_arch_flags = flags;
10647 cpu_arch_isa_flags = flags;
10652 if (j >= ARRAY_SIZE (cpu_noarch))
10653 j = ARRAY_SIZE (cpu_arch);
10656 if (j >= ARRAY_SIZE (cpu_arch))
10657 as_fatal (_("invalid -march= option: `%s'"), arg);
10661 while (next != NULL);
10667 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10668 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10670 if (strcmp (arg, cpu_arch [j].name) == 0)
10672 cpu_arch_tune_set = 1;
10673 cpu_arch_tune = cpu_arch [j].type;
10674 cpu_arch_tune_flags = cpu_arch[j].flags;
10678 if (j >= ARRAY_SIZE (cpu_arch))
10679 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10682 case OPTION_MMNEMONIC:
10683 if (strcasecmp (arg, "att") == 0)
10684 intel_mnemonic = 0;
10685 else if (strcasecmp (arg, "intel") == 0)
10686 intel_mnemonic = 1;
10688 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10691 case OPTION_MSYNTAX:
10692 if (strcasecmp (arg, "att") == 0)
10694 else if (strcasecmp (arg, "intel") == 0)
10697 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10700 case OPTION_MINDEX_REG:
10701 allow_index_reg = 1;
10704 case OPTION_MNAKED_REG:
10705 allow_naked_reg = 1;
10708 case OPTION_MSSE2AVX:
10712 case OPTION_MSSE_CHECK:
10713 if (strcasecmp (arg, "error") == 0)
10714 sse_check = check_error;
10715 else if (strcasecmp (arg, "warning") == 0)
10716 sse_check = check_warning;
10717 else if (strcasecmp (arg, "none") == 0)
10718 sse_check = check_none;
10720 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10723 case OPTION_MOPERAND_CHECK:
10724 if (strcasecmp (arg, "error") == 0)
10725 operand_check = check_error;
10726 else if (strcasecmp (arg, "warning") == 0)
10727 operand_check = check_warning;
10728 else if (strcasecmp (arg, "none") == 0)
10729 operand_check = check_none;
10731 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10734 case OPTION_MAVXSCALAR:
10735 if (strcasecmp (arg, "128") == 0)
10736 avxscalar = vex128;
10737 else if (strcasecmp (arg, "256") == 0)
10738 avxscalar = vex256;
10740 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10743 case OPTION_MADD_BND_PREFIX:
10744 add_bnd_prefix = 1;
10747 case OPTION_MEVEXLIG:
10748 if (strcmp (arg, "128") == 0)
10749 evexlig = evexl128;
10750 else if (strcmp (arg, "256") == 0)
10751 evexlig = evexl256;
10752 else if (strcmp (arg, "512") == 0)
10753 evexlig = evexl512;
10755 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10758 case OPTION_MEVEXRCIG:
10759 if (strcmp (arg, "rne") == 0)
10761 else if (strcmp (arg, "rd") == 0)
10763 else if (strcmp (arg, "ru") == 0)
10765 else if (strcmp (arg, "rz") == 0)
10768 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10771 case OPTION_MEVEXWIG:
10772 if (strcmp (arg, "0") == 0)
10774 else if (strcmp (arg, "1") == 0)
10777 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10780 # if defined (TE_PE) || defined (TE_PEP)
10781 case OPTION_MBIG_OBJ:
10786 case OPTION_MOMIT_LOCK_PREFIX:
10787 if (strcasecmp (arg, "yes") == 0)
10788 omit_lock_prefix = 1;
10789 else if (strcasecmp (arg, "no") == 0)
10790 omit_lock_prefix = 0;
10792 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10795 case OPTION_MFENCE_AS_LOCK_ADD:
10796 if (strcasecmp (arg, "yes") == 0)
10798 else if (strcasecmp (arg, "no") == 0)
10801 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10804 case OPTION_MRELAX_RELOCATIONS:
10805 if (strcasecmp (arg, "yes") == 0)
10806 generate_relax_relocations = 1;
10807 else if (strcasecmp (arg, "no") == 0)
10808 generate_relax_relocations = 0;
10810 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10813 case OPTION_MAMD64:
10817 case OPTION_MINTEL64:
10825 /* Turn off -Os. */
10826 optimize_for_space = 0;
10828 else if (*arg == 's')
10830 optimize_for_space = 1;
10831 /* Turn on all encoding optimizations. */
10836 optimize = atoi (arg);
10837 /* Turn off -Os. */
10838 optimize_for_space = 0;
10848 #define MESSAGE_TEMPLATE \
10852 output_message (FILE *stream, char *p, char *message, char *start,
10853 int *left_p, const char *name, int len)
10855 int size = sizeof (MESSAGE_TEMPLATE);
10856 int left = *left_p;
10858 /* Reserve 2 spaces for ", " or ",\0" */
10861 /* Check if there is any room. */
10869 p = mempcpy (p, name, len);
10873 /* Output the current message now and start a new one. */
10876 fprintf (stream, "%s\n", message);
10878 left = size - (start - message) - len - 2;
10880 gas_assert (left >= 0);
10882 p = mempcpy (p, name, len);
10890 show_arch (FILE *stream, int ext, int check)
10892 static char message[] = MESSAGE_TEMPLATE;
10893 char *start = message + 27;
10895 int size = sizeof (MESSAGE_TEMPLATE);
10902 left = size - (start - message);
10903 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10905 /* Should it be skipped? */
10906 if (cpu_arch [j].skip)
10909 name = cpu_arch [j].name;
10910 len = cpu_arch [j].len;
10913 /* It is an extension. Skip if we aren't asked to show it. */
10924 /* It is an processor. Skip if we show only extension. */
10927 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10929 /* It is an impossible processor - skip. */
10933 p = output_message (stream, p, message, start, &left, name, len);
10936 /* Display disabled extensions. */
10938 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10940 name = cpu_noarch [j].name;
10941 len = cpu_noarch [j].len;
10942 p = output_message (stream, p, message, start, &left, name,
10947 fprintf (stream, "%s\n", message);
10951 md_show_usage (FILE *stream)
10953 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10954 fprintf (stream, _("\
10956 -V print assembler version number\n\
10959 fprintf (stream, _("\
10960 -n Do not optimize code alignment\n\
10961 -q quieten some warnings\n"));
10962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10963 fprintf (stream, _("\
10966 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10967 || defined (TE_PE) || defined (TE_PEP))
10968 fprintf (stream, _("\
10969 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10971 #ifdef SVR4_COMMENT_CHARS
10972 fprintf (stream, _("\
10973 --divide do not treat `/' as a comment character\n"));
10975 fprintf (stream, _("\
10976 --divide ignored\n"));
10978 fprintf (stream, _("\
10979 -march=CPU[,+EXTENSION...]\n\
10980 generate code for CPU and EXTENSION, CPU is one of:\n"));
10981 show_arch (stream, 0, 1);
10982 fprintf (stream, _("\
10983 EXTENSION is combination of:\n"));
10984 show_arch (stream, 1, 0);
10985 fprintf (stream, _("\
10986 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10987 show_arch (stream, 0, 0);
10988 fprintf (stream, _("\
10989 -msse2avx encode SSE instructions with VEX prefix\n"));
10990 fprintf (stream, _("\
10991 -msse-check=[none|error|warning]\n\
10992 check SSE instructions\n"));
10993 fprintf (stream, _("\
10994 -moperand-check=[none|error|warning]\n\
10995 check operand combinations for validity\n"));
10996 fprintf (stream, _("\
10997 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10999 fprintf (stream, _("\
11000 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11002 fprintf (stream, _("\
11003 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11004 for EVEX.W bit ignored instructions\n"));
11005 fprintf (stream, _("\
11006 -mevexrcig=[rne|rd|ru|rz]\n\
11007 encode EVEX instructions with specific EVEX.RC value\n\
11008 for SAE-only ignored instructions\n"));
11009 fprintf (stream, _("\
11010 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11011 fprintf (stream, _("\
11012 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11013 fprintf (stream, _("\
11014 -mindex-reg support pseudo index registers\n"));
11015 fprintf (stream, _("\
11016 -mnaked-reg don't require `%%' prefix for registers\n"));
11017 fprintf (stream, _("\
11018 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11019 fprintf (stream, _("\
11020 -mshared disable branch optimization for shared code\n"));
11021 # if defined (TE_PE) || defined (TE_PEP)
11022 fprintf (stream, _("\
11023 -mbig-obj generate big object files\n"));
11025 fprintf (stream, _("\
11026 -momit-lock-prefix=[no|yes]\n\
11027 strip all lock prefixes\n"));
11028 fprintf (stream, _("\
11029 -mfence-as-lock-add=[no|yes]\n\
11030 encode lfence, mfence and sfence as\n\
11031 lock addl $0x0, (%%{re}sp)\n"));
11032 fprintf (stream, _("\
11033 -mrelax-relocations=[no|yes]\n\
11034 generate relax relocations\n"));
11035 fprintf (stream, _("\
11036 -mamd64 accept only AMD64 ISA\n"));
11037 fprintf (stream, _("\
11038 -mintel64 accept only Intel64 ISA\n"));
11041 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11042 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11043 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11045 /* Pick the target format to use. */
11048 i386_target_format (void)
11050 if (!strncmp (default_arch, "x86_64", 6))
11052 update_code_flag (CODE_64BIT, 1);
11053 if (default_arch[6] == '\0')
11054 x86_elf_abi = X86_64_ABI;
11056 x86_elf_abi = X86_64_X32_ABI;
11058 else if (!strcmp (default_arch, "i386"))
11059 update_code_flag (CODE_32BIT, 1);
11060 else if (!strcmp (default_arch, "iamcu"))
11062 update_code_flag (CODE_32BIT, 1);
11063 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11065 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11066 cpu_arch_name = "iamcu";
11067 cpu_sub_arch_name = NULL;
11068 cpu_arch_flags = iamcu_flags;
11069 cpu_arch_isa = PROCESSOR_IAMCU;
11070 cpu_arch_isa_flags = iamcu_flags;
11071 if (!cpu_arch_tune_set)
11073 cpu_arch_tune = cpu_arch_isa;
11074 cpu_arch_tune_flags = cpu_arch_isa_flags;
11077 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11078 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11082 as_fatal (_("unknown architecture"));
11084 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11085 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11086 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11087 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11089 switch (OUTPUT_FLAVOR)
11091 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11092 case bfd_target_aout_flavour:
11093 return AOUT_TARGET_FORMAT;
11095 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11096 # if defined (TE_PE) || defined (TE_PEP)
11097 case bfd_target_coff_flavour:
11098 if (flag_code == CODE_64BIT)
11099 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11102 # elif defined (TE_GO32)
11103 case bfd_target_coff_flavour:
11104 return "coff-go32";
11106 case bfd_target_coff_flavour:
11107 return "coff-i386";
11110 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11111 case bfd_target_elf_flavour:
11113 const char *format;
11115 switch (x86_elf_abi)
11118 format = ELF_TARGET_FORMAT;
11121 use_rela_relocations = 1;
11123 format = ELF_TARGET_FORMAT64;
11125 case X86_64_X32_ABI:
11126 use_rela_relocations = 1;
11128 disallow_64bit_reloc = 1;
11129 format = ELF_TARGET_FORMAT32;
11132 if (cpu_arch_isa == PROCESSOR_L1OM)
11134 if (x86_elf_abi != X86_64_ABI)
11135 as_fatal (_("Intel L1OM is 64bit only"));
11136 return ELF_TARGET_L1OM_FORMAT;
11138 else if (cpu_arch_isa == PROCESSOR_K1OM)
11140 if (x86_elf_abi != X86_64_ABI)
11141 as_fatal (_("Intel K1OM is 64bit only"));
11142 return ELF_TARGET_K1OM_FORMAT;
11144 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11146 if (x86_elf_abi != I386_ABI)
11147 as_fatal (_("Intel MCU is 32bit only"));
11148 return ELF_TARGET_IAMCU_FORMAT;
11154 #if defined (OBJ_MACH_O)
11155 case bfd_target_mach_o_flavour:
11156 if (flag_code == CODE_64BIT)
11158 use_rela_relocations = 1;
11160 return "mach-o-x86-64";
11163 return "mach-o-i386";
11171 #endif /* OBJ_MAYBE_ more than one */
11174 md_undefined_symbol (char *name)
11176 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11177 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11178 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11179 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11183 if (symbol_find (name))
11184 as_bad (_("GOT already in symbol table"));
11185 GOT_symbol = symbol_new (name, undefined_section,
11186 (valueT) 0, &zero_address_frag);
11193 /* Round up a section size to the appropriate boundary. */
11196 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11198 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11199 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11201 /* For a.out, force the section size to be aligned. If we don't do
11202 this, BFD will align it for us, but it will not write out the
11203 final bytes of the section. This may be a bug in BFD, but it is
11204 easier to fix it here since that is how the other a.out targets
11208 align = bfd_get_section_alignment (stdoutput, segment);
11209 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11216 /* On the i386, PC-relative offsets are relative to the start of the
11217 next instruction. That is, the address of the offset, plus its
11218 size, since the offset is always the last part of the insn. */
11221 md_pcrel_from (fixS *fixP)
11223 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11229 s_bss (int ignore ATTRIBUTE_UNUSED)
11233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11235 obj_elf_section_change_hook ();
11237 temp = get_absolute_expression ();
11238 subseg_set (bss_section, (subsegT) temp);
11239 demand_empty_rest_of_line ();
11245 i386_validate_fix (fixS *fixp)
11247 if (fixp->fx_subsy)
11249 if (fixp->fx_subsy == GOT_symbol)
11251 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11255 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11256 if (fixp->fx_tcbit2)
11257 fixp->fx_r_type = (fixp->fx_tcbit
11258 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11259 : BFD_RELOC_X86_64_GOTPCRELX);
11262 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11267 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11269 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11271 fixp->fx_subsy = 0;
11274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11275 else if (!object_64bit)
11277 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11278 && fixp->fx_tcbit2)
11279 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11285 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11288 bfd_reloc_code_real_type code;
11290 switch (fixp->fx_r_type)
11292 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11293 case BFD_RELOC_SIZE32:
11294 case BFD_RELOC_SIZE64:
11295 if (S_IS_DEFINED (fixp->fx_addsy)
11296 && !S_IS_EXTERNAL (fixp->fx_addsy))
11298 /* Resolve size relocation against local symbol to size of
11299 the symbol plus addend. */
11300 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11301 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11302 && !fits_in_unsigned_long (value))
11303 as_bad_where (fixp->fx_file, fixp->fx_line,
11304 _("symbol size computation overflow"));
11305 fixp->fx_addsy = NULL;
11306 fixp->fx_subsy = NULL;
11307 md_apply_fix (fixp, (valueT *) &value, NULL);
11311 /* Fall through. */
11313 case BFD_RELOC_X86_64_PLT32:
11314 case BFD_RELOC_X86_64_GOT32:
11315 case BFD_RELOC_X86_64_GOTPCREL:
11316 case BFD_RELOC_X86_64_GOTPCRELX:
11317 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11318 case BFD_RELOC_386_PLT32:
11319 case BFD_RELOC_386_GOT32:
11320 case BFD_RELOC_386_GOT32X:
11321 case BFD_RELOC_386_GOTOFF:
11322 case BFD_RELOC_386_GOTPC:
11323 case BFD_RELOC_386_TLS_GD:
11324 case BFD_RELOC_386_TLS_LDM:
11325 case BFD_RELOC_386_TLS_LDO_32:
11326 case BFD_RELOC_386_TLS_IE_32:
11327 case BFD_RELOC_386_TLS_IE:
11328 case BFD_RELOC_386_TLS_GOTIE:
11329 case BFD_RELOC_386_TLS_LE_32:
11330 case BFD_RELOC_386_TLS_LE:
11331 case BFD_RELOC_386_TLS_GOTDESC:
11332 case BFD_RELOC_386_TLS_DESC_CALL:
11333 case BFD_RELOC_X86_64_TLSGD:
11334 case BFD_RELOC_X86_64_TLSLD:
11335 case BFD_RELOC_X86_64_DTPOFF32:
11336 case BFD_RELOC_X86_64_DTPOFF64:
11337 case BFD_RELOC_X86_64_GOTTPOFF:
11338 case BFD_RELOC_X86_64_TPOFF32:
11339 case BFD_RELOC_X86_64_TPOFF64:
11340 case BFD_RELOC_X86_64_GOTOFF64:
11341 case BFD_RELOC_X86_64_GOTPC32:
11342 case BFD_RELOC_X86_64_GOT64:
11343 case BFD_RELOC_X86_64_GOTPCREL64:
11344 case BFD_RELOC_X86_64_GOTPC64:
11345 case BFD_RELOC_X86_64_GOTPLT64:
11346 case BFD_RELOC_X86_64_PLTOFF64:
11347 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11348 case BFD_RELOC_X86_64_TLSDESC_CALL:
11349 case BFD_RELOC_RVA:
11350 case BFD_RELOC_VTABLE_ENTRY:
11351 case BFD_RELOC_VTABLE_INHERIT:
11353 case BFD_RELOC_32_SECREL:
11355 code = fixp->fx_r_type;
11357 case BFD_RELOC_X86_64_32S:
11358 if (!fixp->fx_pcrel)
11360 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11361 code = fixp->fx_r_type;
11364 /* Fall through. */
11366 if (fixp->fx_pcrel)
11368 switch (fixp->fx_size)
11371 as_bad_where (fixp->fx_file, fixp->fx_line,
11372 _("can not do %d byte pc-relative relocation"),
11374 code = BFD_RELOC_32_PCREL;
11376 case 1: code = BFD_RELOC_8_PCREL; break;
11377 case 2: code = BFD_RELOC_16_PCREL; break;
11378 case 4: code = BFD_RELOC_32_PCREL; break;
11380 case 8: code = BFD_RELOC_64_PCREL; break;
11386 switch (fixp->fx_size)
11389 as_bad_where (fixp->fx_file, fixp->fx_line,
11390 _("can not do %d byte relocation"),
11392 code = BFD_RELOC_32;
11394 case 1: code = BFD_RELOC_8; break;
11395 case 2: code = BFD_RELOC_16; break;
11396 case 4: code = BFD_RELOC_32; break;
11398 case 8: code = BFD_RELOC_64; break;
11405 if ((code == BFD_RELOC_32
11406 || code == BFD_RELOC_32_PCREL
11407 || code == BFD_RELOC_X86_64_32S)
11409 && fixp->fx_addsy == GOT_symbol)
11412 code = BFD_RELOC_386_GOTPC;
11414 code = BFD_RELOC_X86_64_GOTPC32;
11416 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11418 && fixp->fx_addsy == GOT_symbol)
11420 code = BFD_RELOC_X86_64_GOTPC64;
11423 rel = XNEW (arelent);
11424 rel->sym_ptr_ptr = XNEW (asymbol *);
11425 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11427 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11429 if (!use_rela_relocations)
11431 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11432 vtable entry to be used in the relocation's section offset. */
11433 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11434 rel->address = fixp->fx_offset;
11435 #if defined (OBJ_COFF) && defined (TE_PE)
11436 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11437 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11442 /* Use the rela in 64bit mode. */
11445 if (disallow_64bit_reloc)
11448 case BFD_RELOC_X86_64_DTPOFF64:
11449 case BFD_RELOC_X86_64_TPOFF64:
11450 case BFD_RELOC_64_PCREL:
11451 case BFD_RELOC_X86_64_GOTOFF64:
11452 case BFD_RELOC_X86_64_GOT64:
11453 case BFD_RELOC_X86_64_GOTPCREL64:
11454 case BFD_RELOC_X86_64_GOTPC64:
11455 case BFD_RELOC_X86_64_GOTPLT64:
11456 case BFD_RELOC_X86_64_PLTOFF64:
11457 as_bad_where (fixp->fx_file, fixp->fx_line,
11458 _("cannot represent relocation type %s in x32 mode"),
11459 bfd_get_reloc_code_name (code));
11465 if (!fixp->fx_pcrel)
11466 rel->addend = fixp->fx_offset;
11470 case BFD_RELOC_X86_64_PLT32:
11471 case BFD_RELOC_X86_64_GOT32:
11472 case BFD_RELOC_X86_64_GOTPCREL:
11473 case BFD_RELOC_X86_64_GOTPCRELX:
11474 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11475 case BFD_RELOC_X86_64_TLSGD:
11476 case BFD_RELOC_X86_64_TLSLD:
11477 case BFD_RELOC_X86_64_GOTTPOFF:
11478 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11479 case BFD_RELOC_X86_64_TLSDESC_CALL:
11480 rel->addend = fixp->fx_offset - fixp->fx_size;
11483 rel->addend = (section->vma
11485 + fixp->fx_addnumber
11486 + md_pcrel_from (fixp));
11491 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11492 if (rel->howto == NULL)
11494 as_bad_where (fixp->fx_file, fixp->fx_line,
11495 _("cannot represent relocation type %s"),
11496 bfd_get_reloc_code_name (code));
11497 /* Set howto to a garbage value so that we can keep going. */
11498 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11499 gas_assert (rel->howto != NULL);
11505 #include "tc-i386-intel.c"
11508 tc_x86_parse_to_dw2regnum (expressionS *exp)
11510 int saved_naked_reg;
11511 char saved_register_dot;
11513 saved_naked_reg = allow_naked_reg;
11514 allow_naked_reg = 1;
11515 saved_register_dot = register_chars['.'];
11516 register_chars['.'] = '.';
11517 allow_pseudo_reg = 1;
11518 expression_and_evaluate (exp);
11519 allow_pseudo_reg = 0;
11520 register_chars['.'] = saved_register_dot;
11521 allow_naked_reg = saved_naked_reg;
11523 if (exp->X_op == O_register && exp->X_add_number >= 0)
11525 if ((addressT) exp->X_add_number < i386_regtab_size)
11527 exp->X_op = O_constant;
11528 exp->X_add_number = i386_regtab[exp->X_add_number]
11529 .dw2_regnum[flag_code >> 1];
11532 exp->X_op = O_illegal;
11537 tc_x86_frame_initial_instructions (void)
11539 static unsigned int sp_regno[2];
11541 if (!sp_regno[flag_code >> 1])
11543 char *saved_input = input_line_pointer;
11544 char sp[][4] = {"esp", "rsp"};
11547 input_line_pointer = sp[flag_code >> 1];
11548 tc_x86_parse_to_dw2regnum (&exp);
11549 gas_assert (exp.X_op == O_constant);
11550 sp_regno[flag_code >> 1] = exp.X_add_number;
11551 input_line_pointer = saved_input;
11554 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11555 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11559 x86_dwarf2_addr_size (void)
11561 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11562 if (x86_elf_abi == X86_64_X32_ABI)
11565 return bfd_arch_bits_per_address (stdoutput) / 8;
11569 i386_elf_section_type (const char *str, size_t len)
11571 if (flag_code == CODE_64BIT
11572 && len == sizeof ("unwind") - 1
11573 && strncmp (str, "unwind", 6) == 0)
11574 return SHT_X86_64_UNWIND;
11581 i386_solaris_fix_up_eh_frame (segT sec)
11583 if (flag_code == CODE_64BIT)
11584 elf_section_type (sec) = SHT_X86_64_UNWIND;
11590 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11594 exp.X_op = O_secrel;
11595 exp.X_add_symbol = symbol;
11596 exp.X_add_number = 0;
11597 emit_expr (&exp, size);
11601 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11602 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11605 x86_64_section_letter (int letter, const char **ptr_msg)
11607 if (flag_code == CODE_64BIT)
11610 return SHF_X86_64_LARGE;
11612 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11615 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11620 x86_64_section_word (char *str, size_t len)
11622 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11623 return SHF_X86_64_LARGE;
11629 handle_large_common (int small ATTRIBUTE_UNUSED)
11631 if (flag_code != CODE_64BIT)
11633 s_comm_internal (0, elf_common_parse);
11634 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11638 static segT lbss_section;
11639 asection *saved_com_section_ptr = elf_com_section_ptr;
11640 asection *saved_bss_section = bss_section;
11642 if (lbss_section == NULL)
11644 flagword applicable;
11645 segT seg = now_seg;
11646 subsegT subseg = now_subseg;
11648 /* The .lbss section is for local .largecomm symbols. */
11649 lbss_section = subseg_new (".lbss", 0);
11650 applicable = bfd_applicable_section_flags (stdoutput);
11651 bfd_set_section_flags (stdoutput, lbss_section,
11652 applicable & SEC_ALLOC);
11653 seg_info (lbss_section)->bss = 1;
11655 subseg_set (seg, subseg);
11658 elf_com_section_ptr = &_bfd_elf_large_com_section;
11659 bss_section = lbss_section;
11661 s_comm_internal (0, elf_common_parse);
11663 elf_com_section_ptr = saved_com_section_ptr;
11664 bss_section = saved_bss_section;
11667 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */