1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template *start;
102 const insn_template *end;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name; /* arch name */
131 unsigned int len; /* arch string length */
132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
134 unsigned int skip; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c);
150 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
152 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS *);
157 static int i386_intel_parse_name (const char *, expressionS *);
158 static const reg_entry *parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template *match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry *build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS *, offsetT);
177 static void output_disp (fragS *, offsetT);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED);
185 static const char *default_arch = DEFAULT_ARCH;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry *regs;
209 operand_size_mismatch,
210 operand_type_mismatch,
211 register_type_mismatch,
212 number_of_operands_mismatch,
213 invalid_instruction_suffix,
216 unsupported_with_intel_mnemonic,
223 /* TM holds the template for the insn were currently assembling. */
226 /* SUFFIX holds the instruction size suffix for byte, word, dword
227 or qword, if given. */
230 /* OPERANDS gives the number of given operands. */
231 unsigned int operands;
233 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
234 of given register, displacement, memory operands and immediate
236 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
238 /* TYPES [i] is the type (see above #defines) which tells us how to
239 use OP[i] for the corresponding operand. */
240 i386_operand_type types[MAX_OPERANDS];
242 /* Displacement expression, immediate expression, or register for each
244 union i386_op op[MAX_OPERANDS];
246 /* Flags for operands. */
247 unsigned int flags[MAX_OPERANDS];
248 #define Operand_PCrel 1
250 /* Relocation type for operand */
251 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
253 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
254 the base index byte below. */
255 const reg_entry *base_reg;
256 const reg_entry *index_reg;
257 unsigned int log2_scale_factor;
259 /* SEG gives the seg_entries of this insn. They are zero unless
260 explicit segment overrides are given. */
261 const seg_entry *seg[2];
263 /* PREFIX holds all the given prefix opcodes (usually null).
264 PREFIXES is the number of prefix opcodes. */
265 unsigned int prefixes;
266 unsigned char prefix[MAX_PREFIXES];
268 /* RM and SIB are the modrm byte and the sib byte where the
269 addressing modes of this insn are encoded. */
275 /* Swap operand in encoding. */
276 unsigned int swap_operand;
279 enum i386_error error;
282 typedef struct _i386_insn i386_insn;
284 /* List of chars besides those in app.c:symbol_chars that can start an
285 operand. Used to prevent the scrubber eating vital white-space. */
286 const char extra_symbol_chars[] = "*%-(["
295 #if (defined (TE_I386AIX) \
296 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
297 && !defined (TE_GNU) \
298 && !defined (TE_LINUX) \
299 && !defined (TE_NETWARE) \
300 && !defined (TE_FreeBSD) \
301 && !defined (TE_NetBSD)))
302 /* This array holds the chars that always start a comment. If the
303 pre-processor is disabled, these aren't very useful. The option
304 --divide will remove '/' from this list. */
305 const char *i386_comment_chars = "#/";
306 #define SVR4_COMMENT_CHARS 1
307 #define PREFIX_SEPARATOR '\\'
310 const char *i386_comment_chars = "#";
311 #define PREFIX_SEPARATOR '/'
314 /* This array holds the chars that only start a comment at the beginning of
315 a line. If the line seems to have the form '# 123 filename'
316 .line and .file directives will appear in the pre-processed output.
317 Note that input_file.c hand checks for '#' at the beginning of the
318 first line of the input file. This is because the compiler outputs
319 #NO_APP at the beginning of its output.
320 Also note that comments started like this one will always work if
321 '/' isn't otherwise defined. */
322 const char line_comment_chars[] = "#/";
324 const char line_separator_chars[] = ";";
326 /* Chars that can be used to separate mant from exp in floating point
328 const char EXP_CHARS[] = "eE";
330 /* Chars that mean this number is a floating point constant
333 const char FLT_CHARS[] = "fFdDxX";
335 /* Tables for lexical analysis. */
336 static char mnemonic_chars[256];
337 static char register_chars[256];
338 static char operand_chars[256];
339 static char identifier_chars[256];
340 static char digit_chars[256];
342 /* Lexical macros. */
343 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
344 #define is_operand_char(x) (operand_chars[(unsigned char) x])
345 #define is_register_char(x) (register_chars[(unsigned char) x])
346 #define is_space_char(x) ((x) == ' ')
347 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
348 #define is_digit_char(x) (digit_chars[(unsigned char) x])
350 /* All non-digit non-letter characters that may occur in an operand. */
351 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
353 /* md_assemble() always leaves the strings it's passed unaltered. To
354 effect this we maintain a stack of saved characters that we've smashed
355 with '\0's (indicating end of strings for various sub-fields of the
356 assembler instruction). */
357 static char save_stack[32];
358 static char *save_stack_p;
359 #define END_STRING_AND_SAVE(s) \
360 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
361 #define RESTORE_END_STRING(s) \
362 do { *(s) = *--save_stack_p; } while (0)
364 /* The instruction we're assembling. */
367 /* Possible templates for current insn. */
368 static const templates *current_templates;
370 /* Per instruction expressionS buffers: max displacements & immediates. */
371 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
372 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
374 /* Current operand we are working on. */
375 static int this_operand = -1;
377 /* We support four different modes. FLAG_CODE variable is used to distinguish
385 static enum flag_code flag_code;
386 static unsigned int object_64bit;
387 static int use_rela_relocations = 0;
389 /* The names used to print error messages. */
390 static const char *flag_code_names[] =
397 /* 1 for intel syntax,
399 static int intel_syntax = 0;
401 /* 1 for intel mnemonic,
402 0 if att mnemonic. */
403 static int intel_mnemonic = !SYSV386_COMPAT;
405 /* 1 if support old (<= 2.8.1) versions of gcc. */
406 static int old_gcc = OLDGCC_COMPAT;
408 /* 1 if pseudo registers are permitted. */
409 static int allow_pseudo_reg = 0;
411 /* 1 if register prefix % not required. */
412 static int allow_naked_reg = 0;
414 /* 1 if pseudo index register, eiz/riz, is allowed . */
415 static int allow_index_reg = 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix = "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size = '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code = 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings = 0;
440 static const char *cpu_arch_name = NULL;
441 static char *cpu_sub_arch_name = NULL;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set = 0;
449 /* Cpu we are generating instructions for. */
450 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags;
455 /* CPU instruction set architecture used. */
456 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
458 /* CPU feature flags of instruction set architecture used. */
459 i386_cpu_flags cpu_arch_isa_flags;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion = 0;
465 /* Encode SSE instructions with VEX prefix. */
466 static unsigned int sse2avx;
468 /* Encode scalar AVX instructions with specific vector length. */
475 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
476 static symbolS *GOT_symbol;
478 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
479 unsigned int x86_dwarf2_return_column;
481 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
482 int x86_cie_data_alignment;
484 /* Interface to relax_segment.
485 There are 3 major relax states for 386 jump insns because the
486 different types of jumps add different sizes to frags when we're
487 figuring out what sort of jump to choose to reach a given label. */
490 #define UNCOND_JUMP 0
492 #define COND_JUMP86 2
497 #define SMALL16 (SMALL | CODE16)
499 #define BIG16 (BIG | CODE16)
503 #define INLINE __inline__
509 #define ENCODE_RELAX_STATE(type, size) \
510 ((relax_substateT) (((type) << 2) | (size)))
511 #define TYPE_FROM_RELAX_STATE(s) \
513 #define DISP_SIZE_FROM_RELAX_STATE(s) \
514 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
516 /* This table is used by relax_frag to promote short jumps to long
517 ones where necessary. SMALL (short) jumps may be promoted to BIG
518 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
519 don't allow a short jump in a 32 bit code segment to be promoted to
520 a 16 bit offset jump because it's slower (requires data size
521 prefix), and doesn't work, unless the destination is in the bottom
522 64k of the code segment (The top 16 bits of eip are zeroed). */
524 const relax_typeS md_relax_table[] =
527 1) most positive reach of this state,
528 2) most negative reach of this state,
529 3) how many bytes this mode will have in the variable part of the frag
530 4) which index into the table to try if we can't fit into this one. */
532 /* UNCOND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
535 /* dword jmp adds 4 bytes to frag:
536 0 extra opcode bytes, 4 displacement bytes. */
538 /* word jmp adds 2 byte2 to frag:
539 0 extra opcode bytes, 2 displacement bytes. */
542 /* COND_JUMP states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 3 bytes to frag:
549 1 extra opcode byte, 2 displacement bytes. */
552 /* COND_JUMP86 states. */
553 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
555 /* dword conditionals adds 5 bytes to frag:
556 1 extra opcode byte, 4 displacement bytes. */
558 /* word conditionals add 4 bytes to frag:
559 1 displacement byte and a 3 byte long branch insn. */
563 static const arch_entry cpu_arch[] =
565 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
566 CPU_GENERIC32_FLAGS, 0 },
567 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
568 CPU_GENERIC64_FLAGS, 0 },
569 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
571 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
573 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
575 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
577 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
579 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
581 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
583 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
585 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
587 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
589 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
591 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
593 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
595 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
596 CPU_NOCONA_FLAGS, 0 },
597 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
599 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
601 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS, 1 },
603 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
604 CPU_CORE2_FLAGS, 0 },
605 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
606 CPU_COREI7_FLAGS, 0 },
607 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
609 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
611 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
613 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
614 CPU_ATHLON_FLAGS, 0 },
615 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
617 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
619 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
621 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
622 CPU_AMDFAM10_FLAGS, 0 },
623 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
624 CPU_BDVER1_FLAGS, 0 },
625 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
627 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
629 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
631 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
632 CPU_ANY87_FLAGS, 0 },
633 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
635 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
636 CPU_3DNOWA_FLAGS, 0 },
637 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
639 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
641 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
643 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
644 CPU_SSSE3_FLAGS, 0 },
645 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
646 CPU_SSE4_1_FLAGS, 0 },
647 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
648 CPU_SSE4_2_FLAGS, 0 },
649 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
650 CPU_SSE4_2_FLAGS, 0 },
651 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
652 CPU_ANY_SSE_FLAGS, 0 },
653 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
655 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
656 CPU_ANY_AVX_FLAGS, 0 },
657 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
659 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
661 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
662 CPU_XSAVE_FLAGS, 0 },
663 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
665 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
666 CPU_PCLMUL_FLAGS, 0 },
667 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
668 CPU_PCLMUL_FLAGS, 1 },
669 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
671 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
673 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
675 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
677 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
678 CPU_MOVBE_FLAGS, 0 },
679 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
681 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
682 CPU_CLFLUSH_FLAGS, 0 },
683 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
684 CPU_SYSCALL_FLAGS, 0 },
685 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
686 CPU_RDTSCP_FLAGS, 0 },
687 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
688 CPU_3DNOW_FLAGS, 0 },
689 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
690 CPU_3DNOWA_FLAGS, 0 },
691 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
692 CPU_PADLOCK_FLAGS, 0 },
693 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
695 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
697 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
698 CPU_SSE4A_FLAGS, 0 },
699 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
704 /* Like s_lcomm_internal in gas/read.c but the alignment string
705 is allowed to be optional. */
708 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
715 && *input_line_pointer == ',')
717 align = parse_align (needs_align - 1);
719 if (align == (addressT) -1)
734 bss_alloc (symbolP, size, align);
739 pe_lcomm (int needs_align)
741 s_comm_internal (needs_align * 2, pe_lcomm_internal);
745 const pseudo_typeS md_pseudo_table[] =
747 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
748 {"align", s_align_bytes, 0},
750 {"align", s_align_ptwo, 0},
752 {"arch", set_cpu_arch, 0},
756 {"lcomm", pe_lcomm, 1},
758 {"ffloat", float_cons, 'f'},
759 {"dfloat", float_cons, 'd'},
760 {"tfloat", float_cons, 'x'},
762 {"slong", signed_cons, 4},
763 {"noopt", s_ignore, 0},
764 {"optim", s_ignore, 0},
765 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
766 {"code16", set_code_flag, CODE_16BIT},
767 {"code32", set_code_flag, CODE_32BIT},
768 {"code64", set_code_flag, CODE_64BIT},
769 {"intel_syntax", set_intel_syntax, 1},
770 {"att_syntax", set_intel_syntax, 0},
771 {"intel_mnemonic", set_intel_mnemonic, 1},
772 {"att_mnemonic", set_intel_mnemonic, 0},
773 {"allow_index_reg", set_allow_index_reg, 1},
774 {"disallow_index_reg", set_allow_index_reg, 0},
775 {"sse_check", set_sse_check, 0},
776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
777 {"largecomm", handle_large_common, 0},
779 {"file", (void (*) (int)) dwarf2_directive_file, 0},
780 {"loc", dwarf2_directive_loc, 0},
781 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
784 {"secrel32", pe_directive_secrel, 0},
789 /* For interface with expression (). */
790 extern char *input_line_pointer;
792 /* Hash table for instruction mnemonic lookup. */
793 static struct hash_control *op_hash;
795 /* Hash table for register lookup. */
796 static struct hash_control *reg_hash;
799 i386_align_code (fragS *fragP, int count)
801 /* Various efficient no-op patterns for aligning code labels.
802 Note: Don't try to assemble the instructions in the comments.
803 0L and 0w are not legal. */
804 static const char f32_1[] =
806 static const char f32_2[] =
807 {0x66,0x90}; /* xchg %ax,%ax */
808 static const char f32_3[] =
809 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
810 static const char f32_4[] =
811 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
812 static const char f32_5[] =
814 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
815 static const char f32_6[] =
816 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
817 static const char f32_7[] =
818 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
819 static const char f32_8[] =
821 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
822 static const char f32_9[] =
823 {0x89,0xf6, /* movl %esi,%esi */
824 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
825 static const char f32_10[] =
826 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
827 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
828 static const char f32_11[] =
829 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
830 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
831 static const char f32_12[] =
832 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
833 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
834 static const char f32_13[] =
835 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
836 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
837 static const char f32_14[] =
838 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
839 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
840 static const char f16_3[] =
841 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
842 static const char f16_4[] =
843 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
844 static const char f16_5[] =
846 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
847 static const char f16_6[] =
848 {0x89,0xf6, /* mov %si,%si */
849 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
850 static const char f16_7[] =
851 {0x8d,0x74,0x00, /* lea 0(%si),%si */
852 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
853 static const char f16_8[] =
854 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
855 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
856 static const char jump_31[] =
857 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
858 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
859 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
860 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
861 static const char *const f32_patt[] = {
862 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
863 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
865 static const char *const f16_patt[] = {
866 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
869 static const char alt_3[] =
871 /* nopl 0(%[re]ax) */
872 static const char alt_4[] =
873 {0x0f,0x1f,0x40,0x00};
874 /* nopl 0(%[re]ax,%[re]ax,1) */
875 static const char alt_5[] =
876 {0x0f,0x1f,0x44,0x00,0x00};
877 /* nopw 0(%[re]ax,%[re]ax,1) */
878 static const char alt_6[] =
879 {0x66,0x0f,0x1f,0x44,0x00,0x00};
880 /* nopl 0L(%[re]ax) */
881 static const char alt_7[] =
882 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
883 /* nopl 0L(%[re]ax,%[re]ax,1) */
884 static const char alt_8[] =
885 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 /* nopw 0L(%[re]ax,%[re]ax,1) */
887 static const char alt_9[] =
888 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_10[] =
891 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_11[] =
896 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_12[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 nopw %cs:0L(%[re]ax,%[re]ax,1) */
908 static const char alt_long_13[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
917 nopw %cs:0L(%[re]ax,%[re]ax,1) */
918 static const char alt_long_14[] =
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 nopw %cs:0L(%[re]ax,%[re]ax,1) */
930 static const char alt_long_15[] =
936 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
937 /* nopl 0(%[re]ax,%[re]ax,1)
938 nopw 0(%[re]ax,%[re]ax,1) */
939 static const char alt_short_11[] =
940 {0x0f,0x1f,0x44,0x00,0x00,
941 0x66,0x0f,0x1f,0x44,0x00,0x00};
942 /* nopw 0(%[re]ax,%[re]ax,1)
943 nopw 0(%[re]ax,%[re]ax,1) */
944 static const char alt_short_12[] =
945 {0x66,0x0f,0x1f,0x44,0x00,0x00,
946 0x66,0x0f,0x1f,0x44,0x00,0x00};
947 /* nopw 0(%[re]ax,%[re]ax,1)
949 static const char alt_short_13[] =
950 {0x66,0x0f,0x1f,0x44,0x00,0x00,
951 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
954 static const char alt_short_14[] =
955 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
956 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
958 nopl 0L(%[re]ax,%[re]ax,1) */
959 static const char alt_short_15[] =
960 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
961 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
962 static const char *const alt_short_patt[] = {
963 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
964 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
965 alt_short_14, alt_short_15
967 static const char *const alt_long_patt[] = {
968 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
969 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
970 alt_long_14, alt_long_15
973 /* Only align for at least a positive non-zero boundary. */
974 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
977 /* We need to decide which NOP sequence to use for 32bit and
978 64bit. When -mtune= is used:
980 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
981 PROCESSOR_GENERIC32, f32_patt will be used.
982 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
983 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
984 PROCESSOR_GENERIC64, alt_long_patt will be used.
985 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
986 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
989 When -mtune= isn't used, alt_long_patt will be used if
990 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
993 When -march= or .arch is used, we can't use anything beyond
994 cpu_arch_isa_flags. */
996 if (flag_code == CODE_16BIT)
1000 memcpy (fragP->fr_literal + fragP->fr_fix,
1002 /* Adjust jump offset. */
1003 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1006 memcpy (fragP->fr_literal + fragP->fr_fix,
1007 f16_patt[count - 1], count);
1011 const char *const *patt = NULL;
1013 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1015 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1016 switch (cpu_arch_tune)
1018 case PROCESSOR_UNKNOWN:
1019 /* We use cpu_arch_isa_flags to check if we SHOULD
1020 optimize for Cpu686. */
1021 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1022 patt = alt_long_patt;
1026 case PROCESSOR_PENTIUMPRO:
1027 case PROCESSOR_PENTIUM4:
1028 case PROCESSOR_NOCONA:
1029 case PROCESSOR_CORE:
1030 case PROCESSOR_CORE2:
1031 case PROCESSOR_COREI7:
1032 case PROCESSOR_L1OM:
1033 case PROCESSOR_GENERIC64:
1034 patt = alt_long_patt;
1037 case PROCESSOR_ATHLON:
1039 case PROCESSOR_AMDFAM10:
1040 case PROCESSOR_BDVER1:
1041 patt = alt_short_patt;
1043 case PROCESSOR_I386:
1044 case PROCESSOR_I486:
1045 case PROCESSOR_PENTIUM:
1046 case PROCESSOR_GENERIC32:
1053 switch (fragP->tc_frag_data.tune)
1055 case PROCESSOR_UNKNOWN:
1056 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1057 PROCESSOR_UNKNOWN. */
1061 case PROCESSOR_I386:
1062 case PROCESSOR_I486:
1063 case PROCESSOR_PENTIUM:
1065 case PROCESSOR_ATHLON:
1067 case PROCESSOR_AMDFAM10:
1068 case PROCESSOR_BDVER1:
1069 case PROCESSOR_GENERIC32:
1070 /* We use cpu_arch_isa_flags to check if we CAN optimize
1072 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1073 patt = alt_short_patt;
1077 case PROCESSOR_PENTIUMPRO:
1078 case PROCESSOR_PENTIUM4:
1079 case PROCESSOR_NOCONA:
1080 case PROCESSOR_CORE:
1081 case PROCESSOR_CORE2:
1082 case PROCESSOR_COREI7:
1083 case PROCESSOR_L1OM:
1084 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1085 patt = alt_long_patt;
1089 case PROCESSOR_GENERIC64:
1090 patt = alt_long_patt;
1095 if (patt == f32_patt)
1097 /* If the padding is less than 15 bytes, we use the normal
1098 ones. Otherwise, we use a jump instruction and adjust
1102 /* For 64bit, the limit is 3 bytes. */
1103 if (flag_code == CODE_64BIT
1104 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1109 memcpy (fragP->fr_literal + fragP->fr_fix,
1110 patt[count - 1], count);
1113 memcpy (fragP->fr_literal + fragP->fr_fix,
1115 /* Adjust jump offset. */
1116 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1121 /* Maximum length of an instruction is 15 byte. If the
1122 padding is greater than 15 bytes and we don't use jump,
1123 we have to break it into smaller pieces. */
1124 int padding = count;
1125 while (padding > 15)
1128 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1133 memcpy (fragP->fr_literal + fragP->fr_fix,
1134 patt [padding - 1], padding);
1137 fragP->fr_var = count;
1141 operand_type_all_zero (const union i386_operand_type *x)
1143 switch (ARRAY_SIZE(x->array))
1152 return !x->array[0];
1159 operand_type_set (union i386_operand_type *x, unsigned int v)
1161 switch (ARRAY_SIZE(x->array))
1176 operand_type_equal (const union i386_operand_type *x,
1177 const union i386_operand_type *y)
1179 switch (ARRAY_SIZE(x->array))
1182 if (x->array[2] != y->array[2])
1185 if (x->array[1] != y->array[1])
1188 return x->array[0] == y->array[0];
1196 cpu_flags_all_zero (const union i386_cpu_flags *x)
1198 switch (ARRAY_SIZE(x->array))
1207 return !x->array[0];
1214 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1216 switch (ARRAY_SIZE(x->array))
1231 cpu_flags_equal (const union i386_cpu_flags *x,
1232 const union i386_cpu_flags *y)
1234 switch (ARRAY_SIZE(x->array))
1237 if (x->array[2] != y->array[2])
1240 if (x->array[1] != y->array[1])
1243 return x->array[0] == y->array[0];
1251 cpu_flags_check_cpu64 (i386_cpu_flags f)
1253 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1254 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1260 switch (ARRAY_SIZE (x.array))
1263 x.array [2] &= y.array [2];
1265 x.array [1] &= y.array [1];
1267 x.array [0] &= y.array [0];
1275 static INLINE i386_cpu_flags
1276 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1278 switch (ARRAY_SIZE (x.array))
1281 x.array [2] |= y.array [2];
1283 x.array [1] |= y.array [1];
1285 x.array [0] |= y.array [0];
1293 static INLINE i386_cpu_flags
1294 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1296 switch (ARRAY_SIZE (x.array))
1299 x.array [2] &= ~y.array [2];
1301 x.array [1] &= ~y.array [1];
1303 x.array [0] &= ~y.array [0];
1311 #define CPU_FLAGS_ARCH_MATCH 0x1
1312 #define CPU_FLAGS_64BIT_MATCH 0x2
1313 #define CPU_FLAGS_AES_MATCH 0x4
1314 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1315 #define CPU_FLAGS_AVX_MATCH 0x10
1317 #define CPU_FLAGS_32BIT_MATCH \
1318 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1319 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1320 #define CPU_FLAGS_PERFECT_MATCH \
1321 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1323 /* Return CPU flags match bits. */
1326 cpu_flags_match (const insn_template *t)
1328 i386_cpu_flags x = t->cpu_flags;
1329 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1331 x.bitfield.cpu64 = 0;
1332 x.bitfield.cpuno64 = 0;
1334 if (cpu_flags_all_zero (&x))
1336 /* This instruction is available on all archs. */
1337 match |= CPU_FLAGS_32BIT_MATCH;
1341 /* This instruction is available only on some archs. */
1342 i386_cpu_flags cpu = cpu_arch_flags;
1344 cpu.bitfield.cpu64 = 0;
1345 cpu.bitfield.cpuno64 = 0;
1346 cpu = cpu_flags_and (x, cpu);
1347 if (!cpu_flags_all_zero (&cpu))
1349 if (x.bitfield.cpuavx)
1351 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1352 if (cpu.bitfield.cpuavx)
1354 /* Check SSE2AVX. */
1355 if (!t->opcode_modifier.sse2avx|| sse2avx)
1357 match |= (CPU_FLAGS_ARCH_MATCH
1358 | CPU_FLAGS_AVX_MATCH);
1360 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1361 match |= CPU_FLAGS_AES_MATCH;
1363 if (!x.bitfield.cpupclmul
1364 || cpu.bitfield.cpupclmul)
1365 match |= CPU_FLAGS_PCLMUL_MATCH;
1369 match |= CPU_FLAGS_ARCH_MATCH;
1372 match |= CPU_FLAGS_32BIT_MATCH;
1378 static INLINE i386_operand_type
1379 operand_type_and (i386_operand_type x, i386_operand_type y)
1381 switch (ARRAY_SIZE (x.array))
1384 x.array [2] &= y.array [2];
1386 x.array [1] &= y.array [1];
1388 x.array [0] &= y.array [0];
1396 static INLINE i386_operand_type
1397 operand_type_or (i386_operand_type x, i386_operand_type y)
1399 switch (ARRAY_SIZE (x.array))
1402 x.array [2] |= y.array [2];
1404 x.array [1] |= y.array [1];
1406 x.array [0] |= y.array [0];
1414 static INLINE i386_operand_type
1415 operand_type_xor (i386_operand_type x, i386_operand_type y)
1417 switch (ARRAY_SIZE (x.array))
1420 x.array [2] ^= y.array [2];
1422 x.array [1] ^= y.array [1];
1424 x.array [0] ^= y.array [0];
1432 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1433 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1434 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1435 static const i386_operand_type inoutportreg
1436 = OPERAND_TYPE_INOUTPORTREG;
1437 static const i386_operand_type reg16_inoutportreg
1438 = OPERAND_TYPE_REG16_INOUTPORTREG;
1439 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1440 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1441 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1442 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1443 static const i386_operand_type anydisp
1444 = OPERAND_TYPE_ANYDISP;
1445 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1446 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1447 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1448 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1449 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1450 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1451 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1452 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1453 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1454 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1455 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1456 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1467 operand_type_check (i386_operand_type t, enum operand_type c)
1472 return (t.bitfield.reg8
1475 || t.bitfield.reg64);
1478 return (t.bitfield.imm8
1482 || t.bitfield.imm32s
1483 || t.bitfield.imm64);
1486 return (t.bitfield.disp8
1487 || t.bitfield.disp16
1488 || t.bitfield.disp32
1489 || t.bitfield.disp32s
1490 || t.bitfield.disp64);
1493 return (t.bitfield.disp8
1494 || t.bitfield.disp16
1495 || t.bitfield.disp32
1496 || t.bitfield.disp32s
1497 || t.bitfield.disp64
1498 || t.bitfield.baseindex);
1507 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1508 operand J for instruction template T. */
1511 match_reg_size (const insn_template *t, unsigned int j)
1513 return !((i.types[j].bitfield.byte
1514 && !t->operand_types[j].bitfield.byte)
1515 || (i.types[j].bitfield.word
1516 && !t->operand_types[j].bitfield.word)
1517 || (i.types[j].bitfield.dword
1518 && !t->operand_types[j].bitfield.dword)
1519 || (i.types[j].bitfield.qword
1520 && !t->operand_types[j].bitfield.qword));
1523 /* Return 1 if there is no conflict in any size on operand J for
1524 instruction template T. */
1527 match_mem_size (const insn_template *t, unsigned int j)
1529 return (match_reg_size (t, j)
1530 && !((i.types[j].bitfield.unspecified
1531 && !t->operand_types[j].bitfield.unspecified)
1532 || (i.types[j].bitfield.fword
1533 && !t->operand_types[j].bitfield.fword)
1534 || (i.types[j].bitfield.tbyte
1535 && !t->operand_types[j].bitfield.tbyte)
1536 || (i.types[j].bitfield.xmmword
1537 && !t->operand_types[j].bitfield.xmmword)
1538 || (i.types[j].bitfield.ymmword
1539 && !t->operand_types[j].bitfield.ymmword)));
1542 /* Return 1 if there is no size conflict on any operands for
1543 instruction template T. */
1546 operand_size_match (const insn_template *t)
1551 /* Don't check jump instructions. */
1552 if (t->opcode_modifier.jump
1553 || t->opcode_modifier.jumpbyte
1554 || t->opcode_modifier.jumpdword
1555 || t->opcode_modifier.jumpintersegment)
1558 /* Check memory and accumulator operand size. */
1559 for (j = 0; j < i.operands; j++)
1561 if (t->operand_types[j].bitfield.anysize)
1564 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1570 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1579 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1582 i.error = operand_size_mismatch;
1586 /* Check reverse. */
1587 gas_assert (i.operands == 2);
1590 for (j = 0; j < 2; j++)
1592 if (t->operand_types[j].bitfield.acc
1593 && !match_reg_size (t, j ? 0 : 1))
1596 if (i.types[j].bitfield.mem
1597 && !match_mem_size (t, j ? 0 : 1))
1605 operand_type_match (i386_operand_type overlap,
1606 i386_operand_type given)
1608 i386_operand_type temp = overlap;
1610 temp.bitfield.jumpabsolute = 0;
1611 temp.bitfield.unspecified = 0;
1612 temp.bitfield.byte = 0;
1613 temp.bitfield.word = 0;
1614 temp.bitfield.dword = 0;
1615 temp.bitfield.fword = 0;
1616 temp.bitfield.qword = 0;
1617 temp.bitfield.tbyte = 0;
1618 temp.bitfield.xmmword = 0;
1619 temp.bitfield.ymmword = 0;
1620 if (operand_type_all_zero (&temp))
1623 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1624 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1628 i.error = operand_type_mismatch;
1632 /* If given types g0 and g1 are registers they must be of the same type
1633 unless the expected operand type register overlap is null.
1634 Note that Acc in a template matches every size of reg. */
1637 operand_type_register_match (i386_operand_type m0,
1638 i386_operand_type g0,
1639 i386_operand_type t0,
1640 i386_operand_type m1,
1641 i386_operand_type g1,
1642 i386_operand_type t1)
1644 if (!operand_type_check (g0, reg))
1647 if (!operand_type_check (g1, reg))
1650 if (g0.bitfield.reg8 == g1.bitfield.reg8
1651 && g0.bitfield.reg16 == g1.bitfield.reg16
1652 && g0.bitfield.reg32 == g1.bitfield.reg32
1653 && g0.bitfield.reg64 == g1.bitfield.reg64)
1656 if (m0.bitfield.acc)
1658 t0.bitfield.reg8 = 1;
1659 t0.bitfield.reg16 = 1;
1660 t0.bitfield.reg32 = 1;
1661 t0.bitfield.reg64 = 1;
1664 if (m1.bitfield.acc)
1666 t1.bitfield.reg8 = 1;
1667 t1.bitfield.reg16 = 1;
1668 t1.bitfield.reg32 = 1;
1669 t1.bitfield.reg64 = 1;
1672 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1673 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1674 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1675 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1678 i.error = register_type_mismatch;
1683 static INLINE unsigned int
1684 mode_from_disp_size (i386_operand_type t)
1686 if (t.bitfield.disp8)
1688 else if (t.bitfield.disp16
1689 || t.bitfield.disp32
1690 || t.bitfield.disp32s)
1697 fits_in_signed_byte (offsetT num)
1699 return (num >= -128) && (num <= 127);
1703 fits_in_unsigned_byte (offsetT num)
1705 return (num & 0xff) == num;
1709 fits_in_unsigned_word (offsetT num)
1711 return (num & 0xffff) == num;
1715 fits_in_signed_word (offsetT num)
1717 return (-32768 <= num) && (num <= 32767);
1721 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1726 return (!(((offsetT) -1 << 31) & num)
1727 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1729 } /* fits_in_signed_long() */
1732 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1737 return (num & (((offsetT) 2 << 31) - 1)) == num;
1739 } /* fits_in_unsigned_long() */
1742 fits_in_imm4 (offsetT num)
1744 return (num & 0xf) == num;
1747 static i386_operand_type
1748 smallest_imm_type (offsetT num)
1750 i386_operand_type t;
1752 operand_type_set (&t, 0);
1753 t.bitfield.imm64 = 1;
1755 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1757 /* This code is disabled on the 486 because all the Imm1 forms
1758 in the opcode table are slower on the i486. They're the
1759 versions with the implicitly specified single-position
1760 displacement, which has another syntax if you really want to
1762 t.bitfield.imm1 = 1;
1763 t.bitfield.imm8 = 1;
1764 t.bitfield.imm8s = 1;
1765 t.bitfield.imm16 = 1;
1766 t.bitfield.imm32 = 1;
1767 t.bitfield.imm32s = 1;
1769 else if (fits_in_signed_byte (num))
1771 t.bitfield.imm8 = 1;
1772 t.bitfield.imm8s = 1;
1773 t.bitfield.imm16 = 1;
1774 t.bitfield.imm32 = 1;
1775 t.bitfield.imm32s = 1;
1777 else if (fits_in_unsigned_byte (num))
1779 t.bitfield.imm8 = 1;
1780 t.bitfield.imm16 = 1;
1781 t.bitfield.imm32 = 1;
1782 t.bitfield.imm32s = 1;
1784 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1786 t.bitfield.imm16 = 1;
1787 t.bitfield.imm32 = 1;
1788 t.bitfield.imm32s = 1;
1790 else if (fits_in_signed_long (num))
1792 t.bitfield.imm32 = 1;
1793 t.bitfield.imm32s = 1;
1795 else if (fits_in_unsigned_long (num))
1796 t.bitfield.imm32 = 1;
1802 offset_in_range (offsetT val, int size)
1808 case 1: mask = ((addressT) 1 << 8) - 1; break;
1809 case 2: mask = ((addressT) 1 << 16) - 1; break;
1810 case 4: mask = ((addressT) 2 << 31) - 1; break;
1812 case 8: mask = ((addressT) 2 << 63) - 1; break;
1818 /* If BFD64, sign extend val for 32bit address mode. */
1819 if (flag_code != CODE_64BIT
1820 || i.prefix[ADDR_PREFIX])
1821 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1822 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1825 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1827 char buf1[40], buf2[40];
1829 sprint_value (buf1, val);
1830 sprint_value (buf2, val & mask);
1831 as_warn (_("%s shortened to %s"), buf1, buf2);
1845 a. PREFIX_EXIST if attempting to add a prefix where one from the
1846 same class already exists.
1847 b. PREFIX_LOCK if lock prefix is added.
1848 c. PREFIX_REP if rep/repne prefix is added.
1849 d. PREFIX_OTHER if other prefix is added.
1852 static enum PREFIX_GROUP
1853 add_prefix (unsigned int prefix)
1855 enum PREFIX_GROUP ret = PREFIX_OTHER;
1858 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1859 && flag_code == CODE_64BIT)
1861 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1862 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1863 && (prefix & (REX_R | REX_X | REX_B))))
1874 case CS_PREFIX_OPCODE:
1875 case DS_PREFIX_OPCODE:
1876 case ES_PREFIX_OPCODE:
1877 case FS_PREFIX_OPCODE:
1878 case GS_PREFIX_OPCODE:
1879 case SS_PREFIX_OPCODE:
1883 case REPNE_PREFIX_OPCODE:
1884 case REPE_PREFIX_OPCODE:
1889 case LOCK_PREFIX_OPCODE:
1898 case ADDR_PREFIX_OPCODE:
1902 case DATA_PREFIX_OPCODE:
1906 if (i.prefix[q] != 0)
1914 i.prefix[q] |= prefix;
1917 as_bad (_("same type of prefix used twice"));
1923 set_code_flag (int value)
1925 flag_code = (enum flag_code) value;
1926 if (flag_code == CODE_64BIT)
1928 cpu_arch_flags.bitfield.cpu64 = 1;
1929 cpu_arch_flags.bitfield.cpuno64 = 0;
1933 cpu_arch_flags.bitfield.cpu64 = 0;
1934 cpu_arch_flags.bitfield.cpuno64 = 1;
1936 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1938 as_bad (_("64bit mode not supported on this CPU."));
1940 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1942 as_bad (_("32bit mode not supported on this CPU."));
1944 stackop_size = '\0';
1948 set_16bit_gcc_code_flag (int new_code_flag)
1950 flag_code = (enum flag_code) new_code_flag;
1951 if (flag_code != CODE_16BIT)
1953 cpu_arch_flags.bitfield.cpu64 = 0;
1954 cpu_arch_flags.bitfield.cpuno64 = 1;
1955 stackop_size = LONG_MNEM_SUFFIX;
1959 set_intel_syntax (int syntax_flag)
1961 /* Find out if register prefixing is specified. */
1962 int ask_naked_reg = 0;
1965 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1967 char *string = input_line_pointer;
1968 int e = get_symbol_end ();
1970 if (strcmp (string, "prefix") == 0)
1972 else if (strcmp (string, "noprefix") == 0)
1975 as_bad (_("bad argument to syntax directive."));
1976 *input_line_pointer = e;
1978 demand_empty_rest_of_line ();
1980 intel_syntax = syntax_flag;
1982 if (ask_naked_reg == 0)
1983 allow_naked_reg = (intel_syntax
1984 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1986 allow_naked_reg = (ask_naked_reg < 0);
1988 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
1990 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1991 identifier_chars['$'] = intel_syntax ? '$' : 0;
1992 register_prefix = allow_naked_reg ? "" : "%";
1996 set_intel_mnemonic (int mnemonic_flag)
1998 intel_mnemonic = mnemonic_flag;
2002 set_allow_index_reg (int flag)
2004 allow_index_reg = flag;
2008 set_sse_check (int dummy ATTRIBUTE_UNUSED)
2012 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2014 char *string = input_line_pointer;
2015 int e = get_symbol_end ();
2017 if (strcmp (string, "none") == 0)
2018 sse_check = sse_check_none;
2019 else if (strcmp (string, "warning") == 0)
2020 sse_check = sse_check_warning;
2021 else if (strcmp (string, "error") == 0)
2022 sse_check = sse_check_error;
2024 as_bad (_("bad argument to sse_check directive."));
2025 *input_line_pointer = e;
2028 as_bad (_("missing argument for sse_check directive"));
2030 demand_empty_rest_of_line ();
2034 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2035 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2037 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2038 static const char *arch;
2040 /* Intel LIOM is only supported on ELF. */
2046 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2047 use default_arch. */
2048 arch = cpu_arch_name;
2050 arch = default_arch;
2053 /* If we are targeting Intel L1OM, we must enable it. */
2054 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2055 || new_flag.bitfield.cpul1om)
2058 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2063 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2067 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2069 char *string = input_line_pointer;
2070 int e = get_symbol_end ();
2072 i386_cpu_flags flags;
2074 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2076 if (strcmp (string, cpu_arch[j].name) == 0)
2078 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2082 cpu_arch_name = cpu_arch[j].name;
2083 cpu_sub_arch_name = NULL;
2084 cpu_arch_flags = cpu_arch[j].flags;
2085 if (flag_code == CODE_64BIT)
2087 cpu_arch_flags.bitfield.cpu64 = 1;
2088 cpu_arch_flags.bitfield.cpuno64 = 0;
2092 cpu_arch_flags.bitfield.cpu64 = 0;
2093 cpu_arch_flags.bitfield.cpuno64 = 1;
2095 cpu_arch_isa = cpu_arch[j].type;
2096 cpu_arch_isa_flags = cpu_arch[j].flags;
2097 if (!cpu_arch_tune_set)
2099 cpu_arch_tune = cpu_arch_isa;
2100 cpu_arch_tune_flags = cpu_arch_isa_flags;
2105 if (strncmp (string + 1, "no", 2))
2106 flags = cpu_flags_or (cpu_arch_flags,
2109 flags = cpu_flags_and_not (cpu_arch_flags,
2111 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2113 if (cpu_sub_arch_name)
2115 char *name = cpu_sub_arch_name;
2116 cpu_sub_arch_name = concat (name,
2118 (const char *) NULL);
2122 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2123 cpu_arch_flags = flags;
2125 *input_line_pointer = e;
2126 demand_empty_rest_of_line ();
2130 if (j >= ARRAY_SIZE (cpu_arch))
2131 as_bad (_("no such architecture: `%s'"), string);
2133 *input_line_pointer = e;
2136 as_bad (_("missing cpu architecture"));
2138 no_cond_jump_promotion = 0;
2139 if (*input_line_pointer == ','
2140 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2142 char *string = ++input_line_pointer;
2143 int e = get_symbol_end ();
2145 if (strcmp (string, "nojumps") == 0)
2146 no_cond_jump_promotion = 1;
2147 else if (strcmp (string, "jumps") == 0)
2150 as_bad (_("no such architecture modifier: `%s'"), string);
2152 *input_line_pointer = e;
2155 demand_empty_rest_of_line ();
2158 enum bfd_architecture
2161 if (cpu_arch_isa == PROCESSOR_L1OM)
2163 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2164 || flag_code != CODE_64BIT)
2165 as_fatal (_("Intel L1OM is 64bit ELF only"));
2166 return bfd_arch_l1om;
2169 return bfd_arch_i386;
2175 if (!strcmp (default_arch, "x86_64"))
2177 if (cpu_arch_isa == PROCESSOR_L1OM)
2179 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2180 as_fatal (_("Intel L1OM is 64bit ELF only"));
2181 return bfd_mach_l1om;
2184 return bfd_mach_x86_64;
2186 else if (!strcmp (default_arch, "i386"))
2187 return bfd_mach_i386_i386;
2189 as_fatal (_("Unknown architecture"));
2195 const char *hash_err;
2197 /* Initialize op_hash hash table. */
2198 op_hash = hash_new ();
2201 const insn_template *optab;
2202 templates *core_optab;
2204 /* Setup for loop. */
2206 core_optab = (templates *) xmalloc (sizeof (templates));
2207 core_optab->start = optab;
2212 if (optab->name == NULL
2213 || strcmp (optab->name, (optab - 1)->name) != 0)
2215 /* different name --> ship out current template list;
2216 add to hash table; & begin anew. */
2217 core_optab->end = optab;
2218 hash_err = hash_insert (op_hash,
2220 (void *) core_optab);
2223 as_fatal (_("Internal Error: Can't hash %s: %s"),
2227 if (optab->name == NULL)
2229 core_optab = (templates *) xmalloc (sizeof (templates));
2230 core_optab->start = optab;
2235 /* Initialize reg_hash hash table. */
2236 reg_hash = hash_new ();
2238 const reg_entry *regtab;
2239 unsigned int regtab_size = i386_regtab_size;
2241 for (regtab = i386_regtab; regtab_size--; regtab++)
2243 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2245 as_fatal (_("Internal Error: Can't hash %s: %s"),
2251 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2256 for (c = 0; c < 256; c++)
2261 mnemonic_chars[c] = c;
2262 register_chars[c] = c;
2263 operand_chars[c] = c;
2265 else if (ISLOWER (c))
2267 mnemonic_chars[c] = c;
2268 register_chars[c] = c;
2269 operand_chars[c] = c;
2271 else if (ISUPPER (c))
2273 mnemonic_chars[c] = TOLOWER (c);
2274 register_chars[c] = mnemonic_chars[c];
2275 operand_chars[c] = c;
2278 if (ISALPHA (c) || ISDIGIT (c))
2279 identifier_chars[c] = c;
2282 identifier_chars[c] = c;
2283 operand_chars[c] = c;
2288 identifier_chars['@'] = '@';
2291 identifier_chars['?'] = '?';
2292 operand_chars['?'] = '?';
2294 digit_chars['-'] = '-';
2295 mnemonic_chars['_'] = '_';
2296 mnemonic_chars['-'] = '-';
2297 mnemonic_chars['.'] = '.';
2298 identifier_chars['_'] = '_';
2299 identifier_chars['.'] = '.';
2301 for (p = operand_special_chars; *p != '\0'; p++)
2302 operand_chars[(unsigned char) *p] = *p;
2305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2308 record_alignment (text_section, 2);
2309 record_alignment (data_section, 2);
2310 record_alignment (bss_section, 2);
2314 if (flag_code == CODE_64BIT)
2316 x86_dwarf2_return_column = 16;
2317 x86_cie_data_alignment = -8;
2321 x86_dwarf2_return_column = 8;
2322 x86_cie_data_alignment = -4;
2327 i386_print_statistics (FILE *file)
2329 hash_print_statistics (file, "i386 opcode", op_hash);
2330 hash_print_statistics (file, "i386 register", reg_hash);
2335 /* Debugging routines for md_assemble. */
2336 static void pte (insn_template *);
2337 static void pt (i386_operand_type);
2338 static void pe (expressionS *);
2339 static void ps (symbolS *);
2342 pi (char *line, i386_insn *x)
2346 fprintf (stdout, "%s: template ", line);
2348 fprintf (stdout, " address: base %s index %s scale %x\n",
2349 x->base_reg ? x->base_reg->reg_name : "none",
2350 x->index_reg ? x->index_reg->reg_name : "none",
2351 x->log2_scale_factor);
2352 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2353 x->rm.mode, x->rm.reg, x->rm.regmem);
2354 fprintf (stdout, " sib: base %x index %x scale %x\n",
2355 x->sib.base, x->sib.index, x->sib.scale);
2356 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2357 (x->rex & REX_W) != 0,
2358 (x->rex & REX_R) != 0,
2359 (x->rex & REX_X) != 0,
2360 (x->rex & REX_B) != 0);
2361 for (i = 0; i < x->operands; i++)
2363 fprintf (stdout, " #%d: ", i + 1);
2365 fprintf (stdout, "\n");
2366 if (x->types[i].bitfield.reg8
2367 || x->types[i].bitfield.reg16
2368 || x->types[i].bitfield.reg32
2369 || x->types[i].bitfield.reg64
2370 || x->types[i].bitfield.regmmx
2371 || x->types[i].bitfield.regxmm
2372 || x->types[i].bitfield.regymm
2373 || x->types[i].bitfield.sreg2
2374 || x->types[i].bitfield.sreg3
2375 || x->types[i].bitfield.control
2376 || x->types[i].bitfield.debug
2377 || x->types[i].bitfield.test)
2378 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2379 if (operand_type_check (x->types[i], imm))
2381 if (operand_type_check (x->types[i], disp))
2382 pe (x->op[i].disps);
2387 pte (insn_template *t)
2390 fprintf (stdout, " %d operands ", t->operands);
2391 fprintf (stdout, "opcode %x ", t->base_opcode);
2392 if (t->extension_opcode != None)
2393 fprintf (stdout, "ext %x ", t->extension_opcode);
2394 if (t->opcode_modifier.d)
2395 fprintf (stdout, "D");
2396 if (t->opcode_modifier.w)
2397 fprintf (stdout, "W");
2398 fprintf (stdout, "\n");
2399 for (i = 0; i < t->operands; i++)
2401 fprintf (stdout, " #%d type ", i + 1);
2402 pt (t->operand_types[i]);
2403 fprintf (stdout, "\n");
2410 fprintf (stdout, " operation %d\n", e->X_op);
2411 fprintf (stdout, " add_number %ld (%lx)\n",
2412 (long) e->X_add_number, (long) e->X_add_number);
2413 if (e->X_add_symbol)
2415 fprintf (stdout, " add_symbol ");
2416 ps (e->X_add_symbol);
2417 fprintf (stdout, "\n");
2421 fprintf (stdout, " op_symbol ");
2422 ps (e->X_op_symbol);
2423 fprintf (stdout, "\n");
2430 fprintf (stdout, "%s type %s%s",
2432 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2433 segment_name (S_GET_SEGMENT (s)));
2436 static struct type_name
2438 i386_operand_type mask;
2441 const type_names[] =
2443 { OPERAND_TYPE_REG8, "r8" },
2444 { OPERAND_TYPE_REG16, "r16" },
2445 { OPERAND_TYPE_REG32, "r32" },
2446 { OPERAND_TYPE_REG64, "r64" },
2447 { OPERAND_TYPE_IMM8, "i8" },
2448 { OPERAND_TYPE_IMM8, "i8s" },
2449 { OPERAND_TYPE_IMM16, "i16" },
2450 { OPERAND_TYPE_IMM32, "i32" },
2451 { OPERAND_TYPE_IMM32S, "i32s" },
2452 { OPERAND_TYPE_IMM64, "i64" },
2453 { OPERAND_TYPE_IMM1, "i1" },
2454 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2455 { OPERAND_TYPE_DISP8, "d8" },
2456 { OPERAND_TYPE_DISP16, "d16" },
2457 { OPERAND_TYPE_DISP32, "d32" },
2458 { OPERAND_TYPE_DISP32S, "d32s" },
2459 { OPERAND_TYPE_DISP64, "d64" },
2460 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2461 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2462 { OPERAND_TYPE_CONTROL, "control reg" },
2463 { OPERAND_TYPE_TEST, "test reg" },
2464 { OPERAND_TYPE_DEBUG, "debug reg" },
2465 { OPERAND_TYPE_FLOATREG, "FReg" },
2466 { OPERAND_TYPE_FLOATACC, "FAcc" },
2467 { OPERAND_TYPE_SREG2, "SReg2" },
2468 { OPERAND_TYPE_SREG3, "SReg3" },
2469 { OPERAND_TYPE_ACC, "Acc" },
2470 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2471 { OPERAND_TYPE_REGMMX, "rMMX" },
2472 { OPERAND_TYPE_REGXMM, "rXMM" },
2473 { OPERAND_TYPE_REGYMM, "rYMM" },
2474 { OPERAND_TYPE_ESSEG, "es" },
2478 pt (i386_operand_type t)
2481 i386_operand_type a;
2483 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2485 a = operand_type_and (t, type_names[j].mask);
2486 if (!operand_type_all_zero (&a))
2487 fprintf (stdout, "%s, ", type_names[j].name);
2492 #endif /* DEBUG386 */
2494 static bfd_reloc_code_real_type
2495 reloc (unsigned int size,
2498 bfd_reloc_code_real_type other)
2500 if (other != NO_RELOC)
2502 reloc_howto_type *rel;
2507 case BFD_RELOC_X86_64_GOT32:
2508 return BFD_RELOC_X86_64_GOT64;
2510 case BFD_RELOC_X86_64_PLTOFF64:
2511 return BFD_RELOC_X86_64_PLTOFF64;
2513 case BFD_RELOC_X86_64_GOTPC32:
2514 other = BFD_RELOC_X86_64_GOTPC64;
2516 case BFD_RELOC_X86_64_GOTPCREL:
2517 other = BFD_RELOC_X86_64_GOTPCREL64;
2519 case BFD_RELOC_X86_64_TPOFF32:
2520 other = BFD_RELOC_X86_64_TPOFF64;
2522 case BFD_RELOC_X86_64_DTPOFF32:
2523 other = BFD_RELOC_X86_64_DTPOFF64;
2529 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2530 if (size == 4 && flag_code != CODE_64BIT)
2533 rel = bfd_reloc_type_lookup (stdoutput, other);
2535 as_bad (_("unknown relocation (%u)"), other);
2536 else if (size != bfd_get_reloc_size (rel))
2537 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2538 bfd_get_reloc_size (rel),
2540 else if (pcrel && !rel->pc_relative)
2541 as_bad (_("non-pc-relative relocation for pc-relative field"));
2542 else if ((rel->complain_on_overflow == complain_overflow_signed
2544 || (rel->complain_on_overflow == complain_overflow_unsigned
2546 as_bad (_("relocated field and relocation type differ in signedness"));
2555 as_bad (_("there are no unsigned pc-relative relocations"));
2558 case 1: return BFD_RELOC_8_PCREL;
2559 case 2: return BFD_RELOC_16_PCREL;
2560 case 4: return BFD_RELOC_32_PCREL;
2561 case 8: return BFD_RELOC_64_PCREL;
2563 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2570 case 4: return BFD_RELOC_X86_64_32S;
2575 case 1: return BFD_RELOC_8;
2576 case 2: return BFD_RELOC_16;
2577 case 4: return BFD_RELOC_32;
2578 case 8: return BFD_RELOC_64;
2580 as_bad (_("cannot do %s %u byte relocation"),
2581 sign > 0 ? "signed" : "unsigned", size);
2587 /* Here we decide which fixups can be adjusted to make them relative to
2588 the beginning of the section instead of the symbol. Basically we need
2589 to make sure that the dynamic relocations are done correctly, so in
2590 some cases we force the original symbol to be used. */
2593 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2599 /* Don't adjust pc-relative references to merge sections in 64-bit
2601 if (use_rela_relocations
2602 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2606 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2607 and changed later by validate_fix. */
2608 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2609 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2612 /* adjust_reloc_syms doesn't know about the GOT. */
2613 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2614 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2615 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2616 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2618 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2619 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2620 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2621 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2622 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2623 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2624 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2625 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2626 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2628 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2629 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2630 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2631 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2632 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2633 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2634 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2635 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2636 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2637 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2638 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2639 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2640 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2647 intel_float_operand (const char *mnemonic)
2649 /* Note that the value returned is meaningful only for opcodes with (memory)
2650 operands, hence the code here is free to improperly handle opcodes that
2651 have no operands (for better performance and smaller code). */
2653 if (mnemonic[0] != 'f')
2654 return 0; /* non-math */
2656 switch (mnemonic[1])
2658 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2659 the fs segment override prefix not currently handled because no
2660 call path can make opcodes without operands get here */
2662 return 2 /* integer op */;
2664 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2665 return 3; /* fldcw/fldenv */
2668 if (mnemonic[2] != 'o' /* fnop */)
2669 return 3; /* non-waiting control op */
2672 if (mnemonic[2] == 's')
2673 return 3; /* frstor/frstpm */
2676 if (mnemonic[2] == 'a')
2677 return 3; /* fsave */
2678 if (mnemonic[2] == 't')
2680 switch (mnemonic[3])
2682 case 'c': /* fstcw */
2683 case 'd': /* fstdw */
2684 case 'e': /* fstenv */
2685 case 's': /* fsts[gw] */
2691 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2692 return 0; /* fxsave/fxrstor are not really math ops */
2699 /* Build the VEX prefix. */
2702 build_vex_prefix (const insn_template *t)
2704 unsigned int register_specifier;
2705 unsigned int implied_prefix;
2706 unsigned int vector_length;
2708 /* Check register specifier. */
2709 if (i.vex.register_specifier)
2711 register_specifier = i.vex.register_specifier->reg_num;
2712 if ((i.vex.register_specifier->reg_flags & RegRex))
2713 register_specifier += 8;
2714 register_specifier = ~register_specifier & 0xf;
2717 register_specifier = 0xf;
2719 /* Use 2-byte VEX prefix by swappping destination and source
2722 && i.operands == i.reg_operands
2723 && i.tm.opcode_modifier.vexopcode == VEX0F
2724 && i.tm.opcode_modifier.s
2727 unsigned int xchg = i.operands - 1;
2728 union i386_op temp_op;
2729 i386_operand_type temp_type;
2731 temp_type = i.types[xchg];
2732 i.types[xchg] = i.types[0];
2733 i.types[0] = temp_type;
2734 temp_op = i.op[xchg];
2735 i.op[xchg] = i.op[0];
2738 gas_assert (i.rm.mode == 3);
2742 i.rm.regmem = i.rm.reg;
2745 /* Use the next insn. */
2749 if (i.tm.opcode_modifier.vex == VEXScalar)
2750 vector_length = avxscalar;
2752 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
2754 switch ((i.tm.base_opcode >> 8) & 0xff)
2759 case DATA_PREFIX_OPCODE:
2762 case REPE_PREFIX_OPCODE:
2765 case REPNE_PREFIX_OPCODE:
2772 /* Use 2-byte VEX prefix if possible. */
2773 if (i.tm.opcode_modifier.vexopcode == VEX0F
2774 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2776 /* 2-byte VEX prefix. */
2780 i.vex.bytes[0] = 0xc5;
2782 /* Check the REX.R bit. */
2783 r = (i.rex & REX_R) ? 0 : 1;
2784 i.vex.bytes[1] = (r << 7
2785 | register_specifier << 3
2786 | vector_length << 2
2791 /* 3-byte VEX prefix. */
2796 switch (i.tm.opcode_modifier.vexopcode)
2800 i.vex.bytes[0] = 0xc4;
2804 i.vex.bytes[0] = 0xc4;
2808 i.vex.bytes[0] = 0xc4;
2812 i.vex.bytes[0] = 0x8f;
2816 i.vex.bytes[0] = 0x8f;
2820 i.vex.bytes[0] = 0x8f;
2826 /* The high 3 bits of the second VEX byte are 1's compliment
2827 of RXB bits from REX. */
2828 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2830 /* Check the REX.W bit. */
2831 w = (i.rex & REX_W) ? 1 : 0;
2832 if (i.tm.opcode_modifier.vexw)
2837 if (i.tm.opcode_modifier.vexw == VEXW1)
2841 i.vex.bytes[2] = (w << 7
2842 | register_specifier << 3
2843 | vector_length << 2
2849 process_immext (void)
2853 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2855 /* SSE3 Instructions have the fixed operands with an opcode
2856 suffix which is coded in the same place as an 8-bit immediate
2857 field would be. Here we check those operands and remove them
2861 for (x = 0; x < i.operands; x++)
2862 if (i.op[x].regs->reg_num != x)
2863 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2864 register_prefix, i.op[x].regs->reg_name, x + 1,
2870 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2871 which is coded in the same place as an 8-bit immediate field
2872 would be. Here we fake an 8-bit immediate operand from the
2873 opcode suffix stored in tm.extension_opcode.
2875 AVX instructions also use this encoding, for some of
2876 3 argument instructions. */
2878 gas_assert (i.imm_operands == 0
2880 || (i.tm.opcode_modifier.vex
2881 && i.operands <= 4)));
2883 exp = &im_expressions[i.imm_operands++];
2884 i.op[i.operands].imms = exp;
2885 i.types[i.operands] = imm8;
2887 exp->X_op = O_constant;
2888 exp->X_add_number = i.tm.extension_opcode;
2889 i.tm.extension_opcode = None;
2892 /* This is the guts of the machine-dependent assembler. LINE points to a
2893 machine dependent instruction. This function is supposed to emit
2894 the frags/bytes it assembles to. */
2897 md_assemble (char *line)
2900 char mnemonic[MAX_MNEM_SIZE];
2901 const insn_template *t;
2903 /* Initialize globals. */
2904 memset (&i, '\0', sizeof (i));
2905 for (j = 0; j < MAX_OPERANDS; j++)
2906 i.reloc[j] = NO_RELOC;
2907 memset (disp_expressions, '\0', sizeof (disp_expressions));
2908 memset (im_expressions, '\0', sizeof (im_expressions));
2909 save_stack_p = save_stack;
2911 /* First parse an instruction mnemonic & call i386_operand for the operands.
2912 We assume that the scrubber has arranged it so that line[0] is the valid
2913 start of a (possibly prefixed) mnemonic. */
2915 line = parse_insn (line, mnemonic);
2919 line = parse_operands (line, mnemonic);
2924 /* Now we've parsed the mnemonic into a set of templates, and have the
2925 operands at hand. */
2927 /* All intel opcodes have reversed operands except for "bound" and
2928 "enter". We also don't reverse intersegment "jmp" and "call"
2929 instructions with 2 immediate operands so that the immediate segment
2930 precedes the offset, as it does when in AT&T mode. */
2933 && (strcmp (mnemonic, "bound") != 0)
2934 && (strcmp (mnemonic, "invlpga") != 0)
2935 && !(operand_type_check (i.types[0], imm)
2936 && operand_type_check (i.types[1], imm)))
2939 /* The order of the immediates should be reversed
2940 for 2 immediates extrq and insertq instructions */
2941 if (i.imm_operands == 2
2942 && (strcmp (mnemonic, "extrq") == 0
2943 || strcmp (mnemonic, "insertq") == 0))
2944 swap_2_operands (0, 1);
2949 /* Don't optimize displacement for movabs since it only takes 64bit
2952 && (flag_code != CODE_64BIT
2953 || strcmp (mnemonic, "movabs") != 0))
2956 /* Next, we find a template that matches the given insn,
2957 making sure the overlap of the given operands types is consistent
2958 with the template operand types. */
2960 if (!(t = match_template ()))
2963 if (sse_check != sse_check_none
2964 && !i.tm.opcode_modifier.noavx
2965 && (i.tm.cpu_flags.bitfield.cpusse
2966 || i.tm.cpu_flags.bitfield.cpusse2
2967 || i.tm.cpu_flags.bitfield.cpusse3
2968 || i.tm.cpu_flags.bitfield.cpussse3
2969 || i.tm.cpu_flags.bitfield.cpusse4_1
2970 || i.tm.cpu_flags.bitfield.cpusse4_2))
2972 (sse_check == sse_check_warning
2974 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2977 /* Zap movzx and movsx suffix. The suffix has been set from
2978 "word ptr" or "byte ptr" on the source operand in Intel syntax
2979 or extracted from mnemonic in AT&T syntax. But we'll use
2980 the destination register to choose the suffix for encoding. */
2981 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2983 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2984 there is no suffix, the default will be byte extension. */
2985 if (i.reg_operands != 2
2988 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2993 if (i.tm.opcode_modifier.fwait)
2994 if (!add_prefix (FWAIT_OPCODE))
2997 /* Check for lock without a lockable instruction. Destination operand
2998 must be memory unless it is xchg (0x86). */
2999 if (i.prefix[LOCK_PREFIX]
3000 && (!i.tm.opcode_modifier.islockable
3001 || i.mem_operands == 0
3002 || (i.tm.base_opcode != 0x86
3003 && !operand_type_check (i.types[i.operands - 1], anymem))))
3005 as_bad (_("expecting lockable instruction after `lock'"));
3009 /* Check string instruction segment overrides. */
3010 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3012 if (!check_string ())
3014 i.disp_operands = 0;
3017 if (!process_suffix ())
3020 /* Update operand types. */
3021 for (j = 0; j < i.operands; j++)
3022 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3024 /* Make still unresolved immediate matches conform to size of immediate
3025 given in i.suffix. */
3026 if (!finalize_imm ())
3029 if (i.types[0].bitfield.imm1)
3030 i.imm_operands = 0; /* kludge for shift insns. */
3032 /* We only need to check those implicit registers for instructions
3033 with 3 operands or less. */
3034 if (i.operands <= 3)
3035 for (j = 0; j < i.operands; j++)
3036 if (i.types[j].bitfield.inoutportreg
3037 || i.types[j].bitfield.shiftcount
3038 || i.types[j].bitfield.acc
3039 || i.types[j].bitfield.floatacc)
3042 /* ImmExt should be processed after SSE2AVX. */
3043 if (!i.tm.opcode_modifier.sse2avx
3044 && i.tm.opcode_modifier.immext)
3047 /* For insns with operands there are more diddles to do to the opcode. */
3050 if (!process_operands ())
3053 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3055 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3056 as_warn (_("translating to `%sp'"), i.tm.name);
3059 if (i.tm.opcode_modifier.vex)
3060 build_vex_prefix (t);
3062 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3063 instructions may define INT_OPCODE as well, so avoid this corner
3064 case for those instructions that use MODRM. */
3065 if (i.tm.base_opcode == INT_OPCODE
3066 && !i.tm.opcode_modifier.modrm
3067 && i.op[0].imms->X_add_number == 3)
3069 i.tm.base_opcode = INT3_OPCODE;
3073 if ((i.tm.opcode_modifier.jump
3074 || i.tm.opcode_modifier.jumpbyte
3075 || i.tm.opcode_modifier.jumpdword)
3076 && i.op[0].disps->X_op == O_constant)
3078 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3079 the absolute address given by the constant. Since ix86 jumps and
3080 calls are pc relative, we need to generate a reloc. */
3081 i.op[0].disps->X_add_symbol = &abs_symbol;
3082 i.op[0].disps->X_op = O_symbol;
3085 if (i.tm.opcode_modifier.rex64)
3088 /* For 8 bit registers we need an empty rex prefix. Also if the
3089 instruction already has a prefix, we need to convert old
3090 registers to new ones. */
3092 if ((i.types[0].bitfield.reg8
3093 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3094 || (i.types[1].bitfield.reg8
3095 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3096 || ((i.types[0].bitfield.reg8
3097 || i.types[1].bitfield.reg8)
3102 i.rex |= REX_OPCODE;
3103 for (x = 0; x < 2; x++)
3105 /* Look for 8 bit operand that uses old registers. */
3106 if (i.types[x].bitfield.reg8
3107 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3109 /* In case it is "hi" register, give up. */
3110 if (i.op[x].regs->reg_num > 3)
3111 as_bad (_("can't encode register '%s%s' in an "
3112 "instruction requiring REX prefix."),
3113 register_prefix, i.op[x].regs->reg_name);
3115 /* Otherwise it is equivalent to the extended register.
3116 Since the encoding doesn't change this is merely
3117 cosmetic cleanup for debug output. */
3119 i.op[x].regs = i.op[x].regs + 8;
3125 add_prefix (REX_OPCODE | i.rex);
3127 /* We are ready to output the insn. */
3132 parse_insn (char *line, char *mnemonic)
3135 char *token_start = l;
3138 const insn_template *t;
3141 /* Non-zero if we found a prefix only acceptable with string insns. */
3142 const char *expecting_string_instruction = NULL;
3147 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3152 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3154 as_bad (_("no such instruction: `%s'"), token_start);
3159 if (!is_space_char (*l)
3160 && *l != END_OF_INSN
3162 || (*l != PREFIX_SEPARATOR
3165 as_bad (_("invalid character %s in mnemonic"),
3166 output_invalid (*l));
3169 if (token_start == l)
3171 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3172 as_bad (_("expecting prefix; got nothing"));
3174 as_bad (_("expecting mnemonic; got nothing"));
3178 /* Look up instruction (or prefix) via hash table. */
3179 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3181 if (*l != END_OF_INSN
3182 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3183 && current_templates
3184 && current_templates->start->opcode_modifier.isprefix)
3186 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3188 as_bad ((flag_code != CODE_64BIT
3189 ? _("`%s' is only supported in 64-bit mode")
3190 : _("`%s' is not supported in 64-bit mode")),
3191 current_templates->start->name);
3194 /* If we are in 16-bit mode, do not allow addr16 or data16.
3195 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3196 if ((current_templates->start->opcode_modifier.size16
3197 || current_templates->start->opcode_modifier.size32)
3198 && flag_code != CODE_64BIT
3199 && (current_templates->start->opcode_modifier.size32
3200 ^ (flag_code == CODE_16BIT)))
3202 as_bad (_("redundant %s prefix"),
3203 current_templates->start->name);
3206 /* Add prefix, checking for repeated prefixes. */
3207 switch (add_prefix (current_templates->start->base_opcode))
3212 expecting_string_instruction = current_templates->start->name;
3217 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3224 if (!current_templates)
3226 /* Check if we should swap operand in encoding. */
3227 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3233 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3236 if (!current_templates)
3239 /* See if we can get a match by trimming off a suffix. */
3242 case WORD_MNEM_SUFFIX:
3243 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3244 i.suffix = SHORT_MNEM_SUFFIX;
3246 case BYTE_MNEM_SUFFIX:
3247 case QWORD_MNEM_SUFFIX:
3248 i.suffix = mnem_p[-1];
3250 current_templates = (const templates *) hash_find (op_hash,
3253 case SHORT_MNEM_SUFFIX:
3254 case LONG_MNEM_SUFFIX:
3257 i.suffix = mnem_p[-1];
3259 current_templates = (const templates *) hash_find (op_hash,
3268 if (intel_float_operand (mnemonic) == 1)
3269 i.suffix = SHORT_MNEM_SUFFIX;
3271 i.suffix = LONG_MNEM_SUFFIX;
3273 current_templates = (const templates *) hash_find (op_hash,
3278 if (!current_templates)
3280 as_bad (_("no such instruction: `%s'"), token_start);
3285 if (current_templates->start->opcode_modifier.jump
3286 || current_templates->start->opcode_modifier.jumpbyte)
3288 /* Check for a branch hint. We allow ",pt" and ",pn" for
3289 predict taken and predict not taken respectively.
3290 I'm not sure that branch hints actually do anything on loop
3291 and jcxz insns (JumpByte) for current Pentium4 chips. They
3292 may work in the future and it doesn't hurt to accept them
3294 if (l[0] == ',' && l[1] == 'p')
3298 if (!add_prefix (DS_PREFIX_OPCODE))
3302 else if (l[2] == 'n')
3304 if (!add_prefix (CS_PREFIX_OPCODE))
3310 /* Any other comma loses. */
3313 as_bad (_("invalid character %s in mnemonic"),
3314 output_invalid (*l));
3318 /* Check if instruction is supported on specified architecture. */
3320 for (t = current_templates->start; t < current_templates->end; ++t)
3322 supported |= cpu_flags_match (t);
3323 if (supported == CPU_FLAGS_PERFECT_MATCH)
3327 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3329 as_bad (flag_code == CODE_64BIT
3330 ? _("`%s' is not supported in 64-bit mode")
3331 : _("`%s' is only supported in 64-bit mode"),
3332 current_templates->start->name);
3335 if (supported != CPU_FLAGS_PERFECT_MATCH)
3337 as_bad (_("`%s' is not supported on `%s%s'"),
3338 current_templates->start->name,
3339 cpu_arch_name ? cpu_arch_name : default_arch,
3340 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3345 if (!cpu_arch_flags.bitfield.cpui386
3346 && (flag_code != CODE_16BIT))
3348 as_warn (_("use .code16 to ensure correct addressing mode"));
3351 /* Check for rep/repne without a string instruction. */
3352 if (expecting_string_instruction)
3354 static templates override;
3356 for (t = current_templates->start; t < current_templates->end; ++t)
3357 if (t->opcode_modifier.isstring)
3359 if (t >= current_templates->end)
3361 as_bad (_("expecting string instruction after `%s'"),
3362 expecting_string_instruction);
3365 for (override.start = t; t < current_templates->end; ++t)
3366 if (!t->opcode_modifier.isstring)
3369 current_templates = &override;
3376 parse_operands (char *l, const char *mnemonic)
3380 /* 1 if operand is pending after ','. */
3381 unsigned int expecting_operand = 0;
3383 /* Non-zero if operand parens not balanced. */
3384 unsigned int paren_not_balanced;
3386 while (*l != END_OF_INSN)
3388 /* Skip optional white space before operand. */
3389 if (is_space_char (*l))
3391 if (!is_operand_char (*l) && *l != END_OF_INSN)
3393 as_bad (_("invalid character %s before operand %d"),
3394 output_invalid (*l),
3398 token_start = l; /* after white space */
3399 paren_not_balanced = 0;
3400 while (paren_not_balanced || *l != ',')
3402 if (*l == END_OF_INSN)
3404 if (paren_not_balanced)
3407 as_bad (_("unbalanced parenthesis in operand %d."),
3410 as_bad (_("unbalanced brackets in operand %d."),
3415 break; /* we are done */
3417 else if (!is_operand_char (*l) && !is_space_char (*l))
3419 as_bad (_("invalid character %s in operand %d"),
3420 output_invalid (*l),
3427 ++paren_not_balanced;
3429 --paren_not_balanced;
3434 ++paren_not_balanced;
3436 --paren_not_balanced;
3440 if (l != token_start)
3441 { /* Yes, we've read in another operand. */
3442 unsigned int operand_ok;
3443 this_operand = i.operands++;
3444 i.types[this_operand].bitfield.unspecified = 1;
3445 if (i.operands > MAX_OPERANDS)
3447 as_bad (_("spurious operands; (%d operands/instruction max)"),
3451 /* Now parse operand adding info to 'i' as we go along. */
3452 END_STRING_AND_SAVE (l);
3456 i386_intel_operand (token_start,
3457 intel_float_operand (mnemonic));
3459 operand_ok = i386_att_operand (token_start);
3461 RESTORE_END_STRING (l);
3467 if (expecting_operand)
3469 expecting_operand_after_comma:
3470 as_bad (_("expecting operand after ','; got nothing"));
3475 as_bad (_("expecting operand before ','; got nothing"));
3480 /* Now *l must be either ',' or END_OF_INSN. */
3483 if (*++l == END_OF_INSN)
3485 /* Just skip it, if it's \n complain. */
3486 goto expecting_operand_after_comma;
3488 expecting_operand = 1;
3495 swap_2_operands (int xchg1, int xchg2)
3497 union i386_op temp_op;
3498 i386_operand_type temp_type;
3499 enum bfd_reloc_code_real temp_reloc;
3501 temp_type = i.types[xchg2];
3502 i.types[xchg2] = i.types[xchg1];
3503 i.types[xchg1] = temp_type;
3504 temp_op = i.op[xchg2];
3505 i.op[xchg2] = i.op[xchg1];
3506 i.op[xchg1] = temp_op;
3507 temp_reloc = i.reloc[xchg2];
3508 i.reloc[xchg2] = i.reloc[xchg1];
3509 i.reloc[xchg1] = temp_reloc;
3513 swap_operands (void)
3519 swap_2_operands (1, i.operands - 2);
3522 swap_2_operands (0, i.operands - 1);
3528 if (i.mem_operands == 2)
3530 const seg_entry *temp_seg;
3531 temp_seg = i.seg[0];
3532 i.seg[0] = i.seg[1];
3533 i.seg[1] = temp_seg;
3537 /* The X_md field is set to register number plus 1 to indicate register
3538 expression in Intel syntax. */
3540 i386_is_register (const expressionS *e)
3542 return e->X_op == O_register || e->X_md;
3545 /* Try to ensure constant immediates are represented in the smallest
3550 char guess_suffix = 0;
3554 guess_suffix = i.suffix;
3555 else if (i.reg_operands)
3557 /* Figure out a suffix from the last register operand specified.
3558 We can't do this properly yet, ie. excluding InOutPortReg,
3559 but the following works for instructions with immediates.
3560 In any case, we can't set i.suffix yet. */
3561 for (op = i.operands; --op >= 0;)
3562 if (i.types[op].bitfield.reg8)
3564 guess_suffix = BYTE_MNEM_SUFFIX;
3567 else if (i.types[op].bitfield.reg16)
3569 guess_suffix = WORD_MNEM_SUFFIX;
3572 else if (i.types[op].bitfield.reg32)
3574 guess_suffix = LONG_MNEM_SUFFIX;
3577 else if (i.types[op].bitfield.reg64)
3579 guess_suffix = QWORD_MNEM_SUFFIX;
3583 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3584 guess_suffix = WORD_MNEM_SUFFIX;
3586 for (op = i.operands; --op >= 0;)
3587 if (operand_type_check (i.types[op], imm))
3589 switch (i.op[op].imms->X_op)
3592 /* If a suffix is given, this operand may be shortened. */
3593 switch (guess_suffix)
3595 case LONG_MNEM_SUFFIX:
3596 i.types[op].bitfield.imm32 = 1;
3597 i.types[op].bitfield.imm64 = 1;
3599 case WORD_MNEM_SUFFIX:
3600 i.types[op].bitfield.imm16 = 1;
3601 i.types[op].bitfield.imm32 = 1;
3602 i.types[op].bitfield.imm32s = 1;
3603 i.types[op].bitfield.imm64 = 1;
3605 case BYTE_MNEM_SUFFIX:
3606 i.types[op].bitfield.imm8 = 1;
3607 i.types[op].bitfield.imm8s = 1;
3608 i.types[op].bitfield.imm16 = 1;
3609 i.types[op].bitfield.imm32 = 1;
3610 i.types[op].bitfield.imm32s = 1;
3611 i.types[op].bitfield.imm64 = 1;
3615 /* If this operand is at most 16 bits, convert it
3616 to a signed 16 bit number before trying to see
3617 whether it will fit in an even smaller size.
3618 This allows a 16-bit operand such as $0xffe0 to
3619 be recognised as within Imm8S range. */
3620 if ((i.types[op].bitfield.imm16)
3621 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3623 i.op[op].imms->X_add_number =
3624 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3626 if ((i.types[op].bitfield.imm32)
3627 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3630 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3631 ^ ((offsetT) 1 << 31))
3632 - ((offsetT) 1 << 31));
3635 = operand_type_or (i.types[op],
3636 smallest_imm_type (i.op[op].imms->X_add_number));
3638 /* We must avoid matching of Imm32 templates when 64bit
3639 only immediate is available. */
3640 if (guess_suffix == QWORD_MNEM_SUFFIX)
3641 i.types[op].bitfield.imm32 = 0;
3648 /* Symbols and expressions. */
3650 /* Convert symbolic operand to proper sizes for matching, but don't
3651 prevent matching a set of insns that only supports sizes other
3652 than those matching the insn suffix. */
3654 i386_operand_type mask, allowed;
3655 const insn_template *t;
3657 operand_type_set (&mask, 0);
3658 operand_type_set (&allowed, 0);
3660 for (t = current_templates->start;
3661 t < current_templates->end;
3663 allowed = operand_type_or (allowed,
3664 t->operand_types[op]);
3665 switch (guess_suffix)
3667 case QWORD_MNEM_SUFFIX:
3668 mask.bitfield.imm64 = 1;
3669 mask.bitfield.imm32s = 1;
3671 case LONG_MNEM_SUFFIX:
3672 mask.bitfield.imm32 = 1;
3674 case WORD_MNEM_SUFFIX:
3675 mask.bitfield.imm16 = 1;
3677 case BYTE_MNEM_SUFFIX:
3678 mask.bitfield.imm8 = 1;
3683 allowed = operand_type_and (mask, allowed);
3684 if (!operand_type_all_zero (&allowed))
3685 i.types[op] = operand_type_and (i.types[op], mask);
3692 /* Try to use the smallest displacement type too. */
3694 optimize_disp (void)
3698 for (op = i.operands; --op >= 0;)
3699 if (operand_type_check (i.types[op], disp))
3701 if (i.op[op].disps->X_op == O_constant)
3703 offsetT op_disp = i.op[op].disps->X_add_number;
3705 if (i.types[op].bitfield.disp16
3706 && (op_disp & ~(offsetT) 0xffff) == 0)
3708 /* If this operand is at most 16 bits, convert
3709 to a signed 16 bit number and don't use 64bit
3711 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
3712 i.types[op].bitfield.disp64 = 0;
3714 if (i.types[op].bitfield.disp32
3715 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3717 /* If this operand is at most 32 bits, convert
3718 to a signed 32 bit number and don't use 64bit
3720 op_disp &= (((offsetT) 2 << 31) - 1);
3721 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3722 i.types[op].bitfield.disp64 = 0;
3724 if (!op_disp && i.types[op].bitfield.baseindex)
3726 i.types[op].bitfield.disp8 = 0;
3727 i.types[op].bitfield.disp16 = 0;
3728 i.types[op].bitfield.disp32 = 0;
3729 i.types[op].bitfield.disp32s = 0;
3730 i.types[op].bitfield.disp64 = 0;
3734 else if (flag_code == CODE_64BIT)
3736 if (fits_in_signed_long (op_disp))
3738 i.types[op].bitfield.disp64 = 0;
3739 i.types[op].bitfield.disp32s = 1;
3741 if (i.prefix[ADDR_PREFIX]
3742 && fits_in_unsigned_long (op_disp))
3743 i.types[op].bitfield.disp32 = 1;
3745 if ((i.types[op].bitfield.disp32
3746 || i.types[op].bitfield.disp32s
3747 || i.types[op].bitfield.disp16)
3748 && fits_in_signed_byte (op_disp))
3749 i.types[op].bitfield.disp8 = 1;
3751 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3752 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3754 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3755 i.op[op].disps, 0, i.reloc[op]);
3756 i.types[op].bitfield.disp8 = 0;
3757 i.types[op].bitfield.disp16 = 0;
3758 i.types[op].bitfield.disp32 = 0;
3759 i.types[op].bitfield.disp32s = 0;
3760 i.types[op].bitfield.disp64 = 0;
3763 /* We only support 64bit displacement on constants. */
3764 i.types[op].bitfield.disp64 = 0;
3768 /* Check if operands are valid for the instrucrtion. Update VEX
3772 VEX_check_operands (const insn_template *t)
3774 if (!t->opcode_modifier.vex)
3777 /* Only check VEX_Imm4, which must be the first operand. */
3778 if (t->operand_types[0].bitfield.vec_imm4)
3780 if (i.op[0].imms->X_op != O_constant
3781 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3787 /* Turn off Imm8 so that update_imm won't complain. */
3788 i.types[0] = vec_imm4;
3794 static const insn_template *
3795 match_template (void)
3797 /* Points to template once we've found it. */
3798 const insn_template *t;
3799 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3800 i386_operand_type overlap4;
3801 unsigned int found_reverse_match;
3802 i386_opcode_modifier suffix_check;
3803 i386_operand_type operand_types [MAX_OPERANDS];
3804 int addr_prefix_disp;
3806 unsigned int found_cpu_match;
3807 unsigned int check_register;
3809 #if MAX_OPERANDS != 5
3810 # error "MAX_OPERANDS must be 5."
3813 found_reverse_match = 0;
3814 addr_prefix_disp = -1;
3816 memset (&suffix_check, 0, sizeof (suffix_check));
3817 if (i.suffix == BYTE_MNEM_SUFFIX)
3818 suffix_check.no_bsuf = 1;
3819 else if (i.suffix == WORD_MNEM_SUFFIX)
3820 suffix_check.no_wsuf = 1;
3821 else if (i.suffix == SHORT_MNEM_SUFFIX)
3822 suffix_check.no_ssuf = 1;
3823 else if (i.suffix == LONG_MNEM_SUFFIX)
3824 suffix_check.no_lsuf = 1;
3825 else if (i.suffix == QWORD_MNEM_SUFFIX)
3826 suffix_check.no_qsuf = 1;
3827 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3828 suffix_check.no_ldsuf = 1;
3830 for (t = current_templates->start; t < current_templates->end; t++)
3832 addr_prefix_disp = -1;
3834 /* Must have right number of operands. */
3835 i.error = number_of_operands_mismatch;
3836 if (i.operands != t->operands)
3839 /* Check processor support. */
3840 i.error = unsupported;
3841 found_cpu_match = (cpu_flags_match (t)
3842 == CPU_FLAGS_PERFECT_MATCH);
3843 if (!found_cpu_match)
3846 /* Check old gcc support. */
3847 i.error = old_gcc_only;
3848 if (!old_gcc && t->opcode_modifier.oldgcc)
3851 /* Check AT&T mnemonic. */
3852 i.error = unsupported_with_intel_mnemonic;
3853 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3856 /* Check AT&T/Intel syntax. */
3857 i.error = unsupported_syntax;
3858 if ((intel_syntax && t->opcode_modifier.attsyntax)
3859 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3862 /* Check the suffix, except for some instructions in intel mode. */
3863 i.error = invalid_instruction_suffix;
3864 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3865 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3866 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3867 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3868 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3869 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3870 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3873 if (!operand_size_match (t))
3876 for (j = 0; j < MAX_OPERANDS; j++)
3877 operand_types[j] = t->operand_types[j];
3879 /* In general, don't allow 64-bit operands in 32-bit mode. */
3880 if (i.suffix == QWORD_MNEM_SUFFIX
3881 && flag_code != CODE_64BIT
3883 ? (!t->opcode_modifier.ignoresize
3884 && !intel_float_operand (t->name))
3885 : intel_float_operand (t->name) != 2)
3886 && ((!operand_types[0].bitfield.regmmx
3887 && !operand_types[0].bitfield.regxmm
3888 && !operand_types[0].bitfield.regymm)
3889 || (!operand_types[t->operands > 1].bitfield.regmmx
3890 && !!operand_types[t->operands > 1].bitfield.regxmm
3891 && !!operand_types[t->operands > 1].bitfield.regymm))
3892 && (t->base_opcode != 0x0fc7
3893 || t->extension_opcode != 1 /* cmpxchg8b */))
3896 /* In general, don't allow 32-bit operands on pre-386. */
3897 else if (i.suffix == LONG_MNEM_SUFFIX
3898 && !cpu_arch_flags.bitfield.cpui386
3900 ? (!t->opcode_modifier.ignoresize
3901 && !intel_float_operand (t->name))
3902 : intel_float_operand (t->name) != 2)
3903 && ((!operand_types[0].bitfield.regmmx
3904 && !operand_types[0].bitfield.regxmm)
3905 || (!operand_types[t->operands > 1].bitfield.regmmx
3906 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3909 /* Do not verify operands when there are none. */
3913 /* We've found a match; break out of loop. */
3917 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3918 into Disp32/Disp16/Disp32 operand. */
3919 if (i.prefix[ADDR_PREFIX] != 0)
3921 /* There should be only one Disp operand. */
3925 for (j = 0; j < MAX_OPERANDS; j++)
3927 if (operand_types[j].bitfield.disp16)
3929 addr_prefix_disp = j;
3930 operand_types[j].bitfield.disp32 = 1;
3931 operand_types[j].bitfield.disp16 = 0;
3937 for (j = 0; j < MAX_OPERANDS; j++)
3939 if (operand_types[j].bitfield.disp32)
3941 addr_prefix_disp = j;
3942 operand_types[j].bitfield.disp32 = 0;
3943 operand_types[j].bitfield.disp16 = 1;
3949 for (j = 0; j < MAX_OPERANDS; j++)
3951 if (operand_types[j].bitfield.disp64)
3953 addr_prefix_disp = j;
3954 operand_types[j].bitfield.disp64 = 0;
3955 operand_types[j].bitfield.disp32 = 1;
3963 /* We check register size only if size of operands can be
3964 encoded the canonical way. */
3965 check_register = t->opcode_modifier.w;
3966 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3967 switch (t->operands)
3970 if (!operand_type_match (overlap0, i.types[0]))
3974 /* xchg %eax, %eax is a special case. It is an aliase for nop
3975 only in 32bit mode and we can use opcode 0x90. In 64bit
3976 mode, we can't use 0x90 for xchg %eax, %eax since it should
3977 zero-extend %eax to %rax. */
3978 if (flag_code == CODE_64BIT
3979 && t->base_opcode == 0x90
3980 && operand_type_equal (&i.types [0], &acc32)
3981 && operand_type_equal (&i.types [1], &acc32))
3985 /* If we swap operand in encoding, we either match
3986 the next one or reverse direction of operands. */
3987 if (t->opcode_modifier.s)
3989 else if (t->opcode_modifier.d)
3994 /* If we swap operand in encoding, we match the next one. */
3995 if (i.swap_operand && t->opcode_modifier.s)
3999 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4000 if (!operand_type_match (overlap0, i.types[0])
4001 || !operand_type_match (overlap1, i.types[1])
4003 && !operand_type_register_match (overlap0, i.types[0],
4005 overlap1, i.types[1],
4008 /* Check if other direction is valid ... */
4009 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4013 /* Try reversing direction of operands. */
4014 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4015 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4016 if (!operand_type_match (overlap0, i.types[0])
4017 || !operand_type_match (overlap1, i.types[1])
4019 && !operand_type_register_match (overlap0,
4026 /* Does not match either direction. */
4029 /* found_reverse_match holds which of D or FloatDR
4031 if (t->opcode_modifier.d)
4032 found_reverse_match = Opcode_D;
4033 else if (t->opcode_modifier.floatd)
4034 found_reverse_match = Opcode_FloatD;
4036 found_reverse_match = 0;
4037 if (t->opcode_modifier.floatr)
4038 found_reverse_match |= Opcode_FloatR;
4042 /* Found a forward 2 operand match here. */
4043 switch (t->operands)
4046 overlap4 = operand_type_and (i.types[4],
4049 overlap3 = operand_type_and (i.types[3],
4052 overlap2 = operand_type_and (i.types[2],
4057 switch (t->operands)
4060 if (!operand_type_match (overlap4, i.types[4])
4061 || !operand_type_register_match (overlap3,
4069 if (!operand_type_match (overlap3, i.types[3])
4071 && !operand_type_register_match (overlap2,
4079 /* Here we make use of the fact that there are no
4080 reverse match 3 operand instructions, and all 3
4081 operand instructions only need to be checked for
4082 register consistency between operands 2 and 3. */
4083 if (!operand_type_match (overlap2, i.types[2])
4085 && !operand_type_register_match (overlap1,
4095 /* Found either forward/reverse 2, 3 or 4 operand match here:
4096 slip through to break. */
4098 if (!found_cpu_match)
4100 found_reverse_match = 0;
4104 /* Check if VEX operands are valid. */
4105 if (VEX_check_operands (t))
4108 /* We've found a match; break out of loop. */
4112 if (t == current_templates->end)
4114 /* We found no match. */
4115 const char *err_msg;
4120 case operand_size_mismatch:
4121 err_msg = _("operand size mismatch");
4123 case operand_type_mismatch:
4124 err_msg = _("operand type mismatch");
4126 case register_type_mismatch:
4127 err_msg = _("register type mismatch");
4129 case number_of_operands_mismatch:
4130 err_msg = _("number of operands mismatch");
4132 case invalid_instruction_suffix:
4133 err_msg = _("invalid instruction suffix");
4136 err_msg = _("Imm4 isn't the first operand");
4139 err_msg = _("only supported with old gcc");
4141 case unsupported_with_intel_mnemonic:
4142 err_msg = _("unsupported with Intel mnemonic");
4144 case unsupported_syntax:
4145 err_msg = _("unsupported syntax");
4148 err_msg = _("unsupported");
4151 as_bad (_("%s for `%s'"), err_msg,
4152 current_templates->start->name);
4156 if (!quiet_warnings)
4159 && (i.types[0].bitfield.jumpabsolute
4160 != operand_types[0].bitfield.jumpabsolute))
4162 as_warn (_("indirect %s without `*'"), t->name);
4165 if (t->opcode_modifier.isprefix
4166 && t->opcode_modifier.ignoresize)
4168 /* Warn them that a data or address size prefix doesn't
4169 affect assembly of the next line of code. */
4170 as_warn (_("stand-alone `%s' prefix"), t->name);
4174 /* Copy the template we found. */
4177 if (addr_prefix_disp != -1)
4178 i.tm.operand_types[addr_prefix_disp]
4179 = operand_types[addr_prefix_disp];
4181 if (found_reverse_match)
4183 /* If we found a reverse match we must alter the opcode
4184 direction bit. found_reverse_match holds bits to change
4185 (different for int & float insns). */
4187 i.tm.base_opcode ^= found_reverse_match;
4189 i.tm.operand_types[0] = operand_types[1];
4190 i.tm.operand_types[1] = operand_types[0];
4199 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4200 if (i.tm.operand_types[mem_op].bitfield.esseg)
4202 if (i.seg[0] != NULL && i.seg[0] != &es)
4204 as_bad (_("`%s' operand %d must use `%ses' segment"),
4210 /* There's only ever one segment override allowed per instruction.
4211 This instruction possibly has a legal segment override on the
4212 second operand, so copy the segment to where non-string
4213 instructions store it, allowing common code. */
4214 i.seg[0] = i.seg[1];
4216 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
4218 if (i.seg[1] != NULL && i.seg[1] != &es)
4220 as_bad (_("`%s' operand %d must use `%ses' segment"),
4231 process_suffix (void)
4233 /* If matched instruction specifies an explicit instruction mnemonic
4235 if (i.tm.opcode_modifier.size16)
4236 i.suffix = WORD_MNEM_SUFFIX;
4237 else if (i.tm.opcode_modifier.size32)
4238 i.suffix = LONG_MNEM_SUFFIX;
4239 else if (i.tm.opcode_modifier.size64)
4240 i.suffix = QWORD_MNEM_SUFFIX;
4241 else if (i.reg_operands)
4243 /* If there's no instruction mnemonic suffix we try to invent one
4244 based on register operands. */
4247 /* We take i.suffix from the last register operand specified,
4248 Destination register type is more significant than source
4249 register type. crc32 in SSE4.2 prefers source register
4251 if (i.tm.base_opcode == 0xf20f38f1)
4253 if (i.types[0].bitfield.reg16)
4254 i.suffix = WORD_MNEM_SUFFIX;
4255 else if (i.types[0].bitfield.reg32)
4256 i.suffix = LONG_MNEM_SUFFIX;
4257 else if (i.types[0].bitfield.reg64)
4258 i.suffix = QWORD_MNEM_SUFFIX;
4260 else if (i.tm.base_opcode == 0xf20f38f0)
4262 if (i.types[0].bitfield.reg8)
4263 i.suffix = BYTE_MNEM_SUFFIX;
4270 if (i.tm.base_opcode == 0xf20f38f1
4271 || i.tm.base_opcode == 0xf20f38f0)
4273 /* We have to know the operand size for crc32. */
4274 as_bad (_("ambiguous memory operand size for `%s`"),
4279 for (op = i.operands; --op >= 0;)
4280 if (!i.tm.operand_types[op].bitfield.inoutportreg)
4282 if (i.types[op].bitfield.reg8)
4284 i.suffix = BYTE_MNEM_SUFFIX;
4287 else if (i.types[op].bitfield.reg16)
4289 i.suffix = WORD_MNEM_SUFFIX;
4292 else if (i.types[op].bitfield.reg32)
4294 i.suffix = LONG_MNEM_SUFFIX;
4297 else if (i.types[op].bitfield.reg64)
4299 i.suffix = QWORD_MNEM_SUFFIX;
4305 else if (i.suffix == BYTE_MNEM_SUFFIX)
4308 && i.tm.opcode_modifier.ignoresize
4309 && i.tm.opcode_modifier.no_bsuf)
4311 else if (!check_byte_reg ())
4314 else if (i.suffix == LONG_MNEM_SUFFIX)
4317 && i.tm.opcode_modifier.ignoresize
4318 && i.tm.opcode_modifier.no_lsuf)
4320 else if (!check_long_reg ())
4323 else if (i.suffix == QWORD_MNEM_SUFFIX)
4326 && i.tm.opcode_modifier.ignoresize
4327 && i.tm.opcode_modifier.no_qsuf)
4329 else if (!check_qword_reg ())
4332 else if (i.suffix == WORD_MNEM_SUFFIX)
4335 && i.tm.opcode_modifier.ignoresize
4336 && i.tm.opcode_modifier.no_wsuf)
4338 else if (!check_word_reg ())
4341 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4342 || i.suffix == YMMWORD_MNEM_SUFFIX)
4344 /* Skip if the instruction has x/y suffix. match_template
4345 should check if it is a valid suffix. */
4347 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
4348 /* Do nothing if the instruction is going to ignore the prefix. */
4353 else if (i.tm.opcode_modifier.defaultsize
4355 /* exclude fldenv/frstor/fsave/fstenv */
4356 && i.tm.opcode_modifier.no_ssuf)
4358 i.suffix = stackop_size;
4360 else if (intel_syntax
4362 && (i.tm.operand_types[0].bitfield.jumpabsolute
4363 || i.tm.opcode_modifier.jumpbyte
4364 || i.tm.opcode_modifier.jumpintersegment
4365 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4366 && i.tm.extension_opcode <= 3)))
4371 if (!i.tm.opcode_modifier.no_qsuf)
4373 i.suffix = QWORD_MNEM_SUFFIX;
4377 if (!i.tm.opcode_modifier.no_lsuf)
4378 i.suffix = LONG_MNEM_SUFFIX;
4381 if (!i.tm.opcode_modifier.no_wsuf)
4382 i.suffix = WORD_MNEM_SUFFIX;
4391 if (i.tm.opcode_modifier.w)
4393 as_bad (_("no instruction mnemonic suffix given and "
4394 "no register operands; can't size instruction"));
4400 unsigned int suffixes;
4402 suffixes = !i.tm.opcode_modifier.no_bsuf;
4403 if (!i.tm.opcode_modifier.no_wsuf)
4405 if (!i.tm.opcode_modifier.no_lsuf)
4407 if (!i.tm.opcode_modifier.no_ldsuf)
4409 if (!i.tm.opcode_modifier.no_ssuf)
4411 if (!i.tm.opcode_modifier.no_qsuf)
4414 /* There are more than suffix matches. */
4415 if (i.tm.opcode_modifier.w
4416 || ((suffixes & (suffixes - 1))
4417 && !i.tm.opcode_modifier.defaultsize
4418 && !i.tm.opcode_modifier.ignoresize))
4420 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4426 /* Change the opcode based on the operand size given by i.suffix;
4427 We don't need to change things for byte insns. */
4430 && i.suffix != BYTE_MNEM_SUFFIX
4431 && i.suffix != XMMWORD_MNEM_SUFFIX
4432 && i.suffix != YMMWORD_MNEM_SUFFIX)
4434 /* It's not a byte, select word/dword operation. */
4435 if (i.tm.opcode_modifier.w)
4437 if (i.tm.opcode_modifier.shortform)
4438 i.tm.base_opcode |= 8;
4440 i.tm.base_opcode |= 1;
4443 /* Now select between word & dword operations via the operand
4444 size prefix, except for instructions that will ignore this
4446 if (i.tm.opcode_modifier.addrprefixop0)
4448 /* The address size override prefix changes the size of the
4450 if ((flag_code == CODE_32BIT
4451 && i.op->regs[0].reg_type.bitfield.reg16)
4452 || (flag_code != CODE_32BIT
4453 && i.op->regs[0].reg_type.bitfield.reg32))
4454 if (!add_prefix (ADDR_PREFIX_OPCODE))
4457 else if (i.suffix != QWORD_MNEM_SUFFIX
4458 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
4459 && !i.tm.opcode_modifier.ignoresize
4460 && !i.tm.opcode_modifier.floatmf
4461 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4462 || (flag_code == CODE_64BIT
4463 && i.tm.opcode_modifier.jumpbyte)))
4465 unsigned int prefix = DATA_PREFIX_OPCODE;
4467 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
4468 prefix = ADDR_PREFIX_OPCODE;
4470 if (!add_prefix (prefix))
4474 /* Set mode64 for an operand. */
4475 if (i.suffix == QWORD_MNEM_SUFFIX
4476 && flag_code == CODE_64BIT
4477 && !i.tm.opcode_modifier.norex64)
4479 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4480 need rex64. cmpxchg8b is also a special case. */
4481 if (! (i.operands == 2
4482 && i.tm.base_opcode == 0x90
4483 && i.tm.extension_opcode == None
4484 && operand_type_equal (&i.types [0], &acc64)
4485 && operand_type_equal (&i.types [1], &acc64))
4486 && ! (i.operands == 1
4487 && i.tm.base_opcode == 0xfc7
4488 && i.tm.extension_opcode == 1
4489 && !operand_type_check (i.types [0], reg)
4490 && operand_type_check (i.types [0], anymem)))
4494 /* Size floating point instruction. */
4495 if (i.suffix == LONG_MNEM_SUFFIX)
4496 if (i.tm.opcode_modifier.floatmf)
4497 i.tm.base_opcode ^= 4;
4504 check_byte_reg (void)
4508 for (op = i.operands; --op >= 0;)
4510 /* If this is an eight bit register, it's OK. If it's the 16 or
4511 32 bit version of an eight bit register, we will just use the
4512 low portion, and that's OK too. */
4513 if (i.types[op].bitfield.reg8)
4516 /* crc32 doesn't generate this warning. */
4517 if (i.tm.base_opcode == 0xf20f38f0)
4520 if ((i.types[op].bitfield.reg16
4521 || i.types[op].bitfield.reg32
4522 || i.types[op].bitfield.reg64)
4523 && i.op[op].regs->reg_num < 4)
4525 /* Prohibit these changes in the 64bit mode, since the
4526 lowering is more complicated. */
4527 if (flag_code == CODE_64BIT
4528 && !i.tm.operand_types[op].bitfield.inoutportreg)
4530 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4531 register_prefix, i.op[op].regs->reg_name,
4535 #if REGISTER_WARNINGS
4537 && !i.tm.operand_types[op].bitfield.inoutportreg)
4538 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4540 (i.op[op].regs + (i.types[op].bitfield.reg16
4541 ? REGNAM_AL - REGNAM_AX
4542 : REGNAM_AL - REGNAM_EAX))->reg_name,
4544 i.op[op].regs->reg_name,
4549 /* Any other register is bad. */
4550 if (i.types[op].bitfield.reg16
4551 || i.types[op].bitfield.reg32
4552 || i.types[op].bitfield.reg64
4553 || i.types[op].bitfield.regmmx
4554 || i.types[op].bitfield.regxmm
4555 || i.types[op].bitfield.regymm
4556 || i.types[op].bitfield.sreg2
4557 || i.types[op].bitfield.sreg3
4558 || i.types[op].bitfield.control
4559 || i.types[op].bitfield.debug
4560 || i.types[op].bitfield.test
4561 || i.types[op].bitfield.floatreg
4562 || i.types[op].bitfield.floatacc)
4564 as_bad (_("`%s%s' not allowed with `%s%c'"),
4566 i.op[op].regs->reg_name,
4576 check_long_reg (void)
4580 for (op = i.operands; --op >= 0;)
4581 /* Reject eight bit registers, except where the template requires
4582 them. (eg. movzb) */
4583 if (i.types[op].bitfield.reg8
4584 && (i.tm.operand_types[op].bitfield.reg16
4585 || i.tm.operand_types[op].bitfield.reg32
4586 || i.tm.operand_types[op].bitfield.acc))
4588 as_bad (_("`%s%s' not allowed with `%s%c'"),
4590 i.op[op].regs->reg_name,
4595 /* Warn if the e prefix on a general reg is missing. */
4596 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4597 && i.types[op].bitfield.reg16
4598 && (i.tm.operand_types[op].bitfield.reg32
4599 || i.tm.operand_types[op].bitfield.acc))
4601 /* Prohibit these changes in the 64bit mode, since the
4602 lowering is more complicated. */
4603 if (flag_code == CODE_64BIT)
4605 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4606 register_prefix, i.op[op].regs->reg_name,
4610 #if REGISTER_WARNINGS
4612 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4614 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
4616 i.op[op].regs->reg_name,
4620 /* Warn if the r prefix on a general reg is missing. */
4621 else if (i.types[op].bitfield.reg64
4622 && (i.tm.operand_types[op].bitfield.reg32
4623 || i.tm.operand_types[op].bitfield.acc))
4626 && i.tm.opcode_modifier.toqword
4627 && !i.types[0].bitfield.regxmm)
4629 /* Convert to QWORD. We want REX byte. */
4630 i.suffix = QWORD_MNEM_SUFFIX;
4634 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4635 register_prefix, i.op[op].regs->reg_name,
4644 check_qword_reg (void)
4648 for (op = i.operands; --op >= 0; )
4649 /* Reject eight bit registers, except where the template requires
4650 them. (eg. movzb) */
4651 if (i.types[op].bitfield.reg8
4652 && (i.tm.operand_types[op].bitfield.reg16
4653 || i.tm.operand_types[op].bitfield.reg32
4654 || i.tm.operand_types[op].bitfield.acc))
4656 as_bad (_("`%s%s' not allowed with `%s%c'"),
4658 i.op[op].regs->reg_name,
4663 /* Warn if the e prefix on a general reg is missing. */
4664 else if ((i.types[op].bitfield.reg16
4665 || i.types[op].bitfield.reg32)
4666 && (i.tm.operand_types[op].bitfield.reg32
4667 || i.tm.operand_types[op].bitfield.acc))
4669 /* Prohibit these changes in the 64bit mode, since the
4670 lowering is more complicated. */
4672 && i.tm.opcode_modifier.todword
4673 && !i.types[0].bitfield.regxmm)
4675 /* Convert to DWORD. We don't want REX byte. */
4676 i.suffix = LONG_MNEM_SUFFIX;
4680 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4681 register_prefix, i.op[op].regs->reg_name,
4690 check_word_reg (void)
4693 for (op = i.operands; --op >= 0;)
4694 /* Reject eight bit registers, except where the template requires
4695 them. (eg. movzb) */
4696 if (i.types[op].bitfield.reg8
4697 && (i.tm.operand_types[op].bitfield.reg16
4698 || i.tm.operand_types[op].bitfield.reg32
4699 || i.tm.operand_types[op].bitfield.acc))
4701 as_bad (_("`%s%s' not allowed with `%s%c'"),
4703 i.op[op].regs->reg_name,
4708 /* Warn if the e prefix on a general reg is present. */
4709 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4710 && i.types[op].bitfield.reg32
4711 && (i.tm.operand_types[op].bitfield.reg16
4712 || i.tm.operand_types[op].bitfield.acc))
4714 /* Prohibit these changes in the 64bit mode, since the
4715 lowering is more complicated. */
4716 if (flag_code == CODE_64BIT)
4718 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4719 register_prefix, i.op[op].regs->reg_name,
4724 #if REGISTER_WARNINGS
4725 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4727 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4729 i.op[op].regs->reg_name,
4737 update_imm (unsigned int j)
4739 i386_operand_type overlap = i.types[j];
4740 if ((overlap.bitfield.imm8
4741 || overlap.bitfield.imm8s
4742 || overlap.bitfield.imm16
4743 || overlap.bitfield.imm32
4744 || overlap.bitfield.imm32s
4745 || overlap.bitfield.imm64)
4746 && !operand_type_equal (&overlap, &imm8)
4747 && !operand_type_equal (&overlap, &imm8s)
4748 && !operand_type_equal (&overlap, &imm16)
4749 && !operand_type_equal (&overlap, &imm32)
4750 && !operand_type_equal (&overlap, &imm32s)
4751 && !operand_type_equal (&overlap, &imm64))
4755 i386_operand_type temp;
4757 operand_type_set (&temp, 0);
4758 if (i.suffix == BYTE_MNEM_SUFFIX)
4760 temp.bitfield.imm8 = overlap.bitfield.imm8;
4761 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4763 else if (i.suffix == WORD_MNEM_SUFFIX)
4764 temp.bitfield.imm16 = overlap.bitfield.imm16;
4765 else if (i.suffix == QWORD_MNEM_SUFFIX)
4767 temp.bitfield.imm64 = overlap.bitfield.imm64;
4768 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4771 temp.bitfield.imm32 = overlap.bitfield.imm32;
4774 else if (operand_type_equal (&overlap, &imm16_32_32s)
4775 || operand_type_equal (&overlap, &imm16_32)
4776 || operand_type_equal (&overlap, &imm16_32s))
4778 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4783 if (!operand_type_equal (&overlap, &imm8)
4784 && !operand_type_equal (&overlap, &imm8s)
4785 && !operand_type_equal (&overlap, &imm16)
4786 && !operand_type_equal (&overlap, &imm32)
4787 && !operand_type_equal (&overlap, &imm32s)
4788 && !operand_type_equal (&overlap, &imm64))
4790 as_bad (_("no instruction mnemonic suffix given; "
4791 "can't determine immediate size"));
4795 i.types[j] = overlap;
4805 /* Update the first 2 immediate operands. */
4806 n = i.operands > 2 ? 2 : i.operands;
4809 for (j = 0; j < n; j++)
4810 if (update_imm (j) == 0)
4813 /* The 3rd operand can't be immediate operand. */
4814 gas_assert (operand_type_check (i.types[2], imm) == 0);
4821 bad_implicit_operand (int xmm)
4823 const char *ireg = xmm ? "xmm0" : "ymm0";
4826 as_bad (_("the last operand of `%s' must be `%s%s'"),
4827 i.tm.name, register_prefix, ireg);
4829 as_bad (_("the first operand of `%s' must be `%s%s'"),
4830 i.tm.name, register_prefix, ireg);
4835 process_operands (void)
4837 /* Default segment register this instruction will use for memory
4838 accesses. 0 means unknown. This is only for optimizing out
4839 unnecessary segment overrides. */
4840 const seg_entry *default_seg = 0;
4842 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
4844 unsigned int dupl = i.operands;
4845 unsigned int dest = dupl - 1;
4848 /* The destination must be an xmm register. */
4849 gas_assert (i.reg_operands
4850 && MAX_OPERANDS > dupl
4851 && operand_type_equal (&i.types[dest], ®xmm));
4853 if (i.tm.opcode_modifier.firstxmm0)
4855 /* The first operand is implicit and must be xmm0. */
4856 gas_assert (operand_type_equal (&i.types[0], ®xmm));
4857 if (i.op[0].regs->reg_num != 0)
4858 return bad_implicit_operand (1);
4860 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
4862 /* Keep xmm0 for instructions with VEX prefix and 3
4868 /* We remove the first xmm0 and keep the number of
4869 operands unchanged, which in fact duplicates the
4871 for (j = 1; j < i.operands; j++)
4873 i.op[j - 1] = i.op[j];
4874 i.types[j - 1] = i.types[j];
4875 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4879 else if (i.tm.opcode_modifier.implicit1stxmm0)
4881 gas_assert ((MAX_OPERANDS - 1) > dupl
4882 && (i.tm.opcode_modifier.vexsources
4885 /* Add the implicit xmm0 for instructions with VEX prefix
4887 for (j = i.operands; j > 0; j--)
4889 i.op[j] = i.op[j - 1];
4890 i.types[j] = i.types[j - 1];
4891 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4894 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4895 i.types[0] = regxmm;
4896 i.tm.operand_types[0] = regxmm;
4899 i.reg_operands += 2;
4904 i.op[dupl] = i.op[dest];
4905 i.types[dupl] = i.types[dest];
4906 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
4915 i.op[dupl] = i.op[dest];
4916 i.types[dupl] = i.types[dest];
4917 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
4920 if (i.tm.opcode_modifier.immext)
4923 else if (i.tm.opcode_modifier.firstxmm0)
4927 /* The first operand is implicit and must be xmm0/ymm0. */
4928 gas_assert (i.reg_operands
4929 && (operand_type_equal (&i.types[0], ®xmm)
4930 || operand_type_equal (&i.types[0], ®ymm)));
4931 if (i.op[0].regs->reg_num != 0)
4932 return bad_implicit_operand (i.types[0].bitfield.regxmm);
4934 for (j = 1; j < i.operands; j++)
4936 i.op[j - 1] = i.op[j];
4937 i.types[j - 1] = i.types[j];
4939 /* We need to adjust fields in i.tm since they are used by
4940 build_modrm_byte. */
4941 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4948 else if (i.tm.opcode_modifier.regkludge)
4950 /* The imul $imm, %reg instruction is converted into
4951 imul $imm, %reg, %reg, and the clr %reg instruction
4952 is converted into xor %reg, %reg. */
4954 unsigned int first_reg_op;
4956 if (operand_type_check (i.types[0], reg))
4960 /* Pretend we saw the extra register operand. */
4961 gas_assert (i.reg_operands == 1
4962 && i.op[first_reg_op + 1].regs == 0);
4963 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4964 i.types[first_reg_op + 1] = i.types[first_reg_op];
4969 if (i.tm.opcode_modifier.shortform)
4971 if (i.types[0].bitfield.sreg2
4972 || i.types[0].bitfield.sreg3)
4974 if (i.tm.base_opcode == POP_SEG_SHORT
4975 && i.op[0].regs->reg_num == 1)
4977 as_bad (_("you can't `pop %scs'"), register_prefix);
4980 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4981 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4986 /* The register or float register operand is in operand
4990 if (i.types[0].bitfield.floatreg
4991 || operand_type_check (i.types[0], reg))
4995 /* Register goes in low 3 bits of opcode. */
4996 i.tm.base_opcode |= i.op[op].regs->reg_num;
4997 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4999 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5001 /* Warn about some common errors, but press on regardless.
5002 The first case can be generated by gcc (<= 2.8.1). */
5003 if (i.operands == 2)
5005 /* Reversed arguments on faddp, fsubp, etc. */
5006 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5007 register_prefix, i.op[!intel_syntax].regs->reg_name,
5008 register_prefix, i.op[intel_syntax].regs->reg_name);
5012 /* Extraneous `l' suffix on fp insn. */
5013 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5014 register_prefix, i.op[0].regs->reg_name);
5019 else if (i.tm.opcode_modifier.modrm)
5021 /* The opcode is completed (modulo i.tm.extension_opcode which
5022 must be put into the modrm byte). Now, we make the modrm and
5023 index base bytes based on all the info we've collected. */
5025 default_seg = build_modrm_byte ();
5027 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5031 else if (i.tm.opcode_modifier.isstring)
5033 /* For the string instructions that allow a segment override
5034 on one of their operands, the default segment is ds. */
5038 if (i.tm.base_opcode == 0x8d /* lea */
5041 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5043 /* If a segment was explicitly specified, and the specified segment
5044 is not the default, use an opcode prefix to select it. If we
5045 never figured out what the default segment is, then default_seg
5046 will be zero at this point, and the specified segment prefix will
5048 if ((i.seg[0]) && (i.seg[0] != default_seg))
5050 if (!add_prefix (i.seg[0]->seg_prefix))
5056 static const seg_entry *
5057 build_modrm_byte (void)
5059 const seg_entry *default_seg = 0;
5060 unsigned int source, dest;
5063 /* The first operand of instructions with VEX prefix and 3 sources
5064 must be VEX_Imm4. */
5065 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5068 unsigned int nds, reg_slot;
5071 if (i.tm.opcode_modifier.veximmext
5072 && i.tm.opcode_modifier.immext)
5074 dest = i.operands - 2;
5075 gas_assert (dest == 3);
5078 dest = i.operands - 1;
5081 /* There are 2 kinds of instructions:
5082 1. 5 operands: 4 register operands or 3 register operands
5083 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5084 VexW0 or VexW1. The destination must be either XMM or YMM
5086 2. 4 operands: 4 register operands or 3 register operands
5087 plus 1 memory operand, VexXDS, and VexImmExt */
5088 gas_assert ((i.reg_operands == 4
5089 || (i.reg_operands == 3 && i.mem_operands == 1))
5090 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5091 && (i.tm.opcode_modifier.veximmext
5092 || (i.imm_operands == 1
5093 && i.types[0].bitfield.vec_imm4
5094 && (i.tm.opcode_modifier.vexw == VEXW0
5095 || i.tm.opcode_modifier.vexw == VEXW1)
5096 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5097 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)))));
5099 if (i.imm_operands == 0)
5101 /* When there is no immediate operand, generate an 8bit
5102 immediate operand to encode the first operand. */
5103 exp = &im_expressions[i.imm_operands++];
5104 i.op[i.operands].imms = exp;
5105 i.types[i.operands] = imm8;
5107 /* If VexW1 is set, the first operand is the source and
5108 the second operand is encoded in the immediate operand. */
5109 if (i.tm.opcode_modifier.vexw == VEXW1)
5120 /* FMA swaps REG and NDS. */
5121 if (i.tm.cpu_flags.bitfield.cpufma)
5129 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5131 || operand_type_equal (&i.tm.operand_types[reg_slot],
5133 exp->X_op = O_constant;
5135 = ((i.op[reg_slot].regs->reg_num
5136 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5141 unsigned int imm_slot;
5143 if (i.tm.opcode_modifier.vexw == VEXW0)
5145 /* If VexW0 is set, the third operand is the source and
5146 the second operand is encoded in the immediate
5153 /* VexW1 is set, the second operand is the source and
5154 the third operand is encoded in the immediate
5160 if (i.tm.opcode_modifier.immext)
5162 /* When ImmExt is set, the immdiate byte is the last
5164 imm_slot = i.operands - 1;
5172 /* Turn on Imm8 so that output_imm will generate it. */
5173 i.types[imm_slot].bitfield.imm8 = 1;
5176 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5178 || operand_type_equal (&i.tm.operand_types[reg_slot],
5180 i.op[imm_slot].imms->X_add_number
5181 |= ((i.op[reg_slot].regs->reg_num
5182 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5186 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
5187 || operand_type_equal (&i.tm.operand_types[nds],
5189 i.vex.register_specifier = i.op[nds].regs;
5194 /* i.reg_operands MUST be the number of real register operands;
5195 implicit registers do not count. If there are 3 register
5196 operands, it must be a instruction with VexNDS. For a
5197 instruction with VexNDD, the destination register is encoded
5198 in VEX prefix. If there are 4 register operands, it must be
5199 a instruction with VEX prefix and 3 sources. */
5200 if (i.mem_operands == 0
5201 && ((i.reg_operands == 2
5202 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
5203 || (i.reg_operands == 3
5204 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
5205 || (i.reg_operands == 4 && vex_3_sources)))
5213 /* When there are 3 operands, one of them may be immediate,
5214 which may be the first or the last operand. Otherwise,
5215 the first operand must be shift count register (cl) or it
5216 is an instruction with VexNDS. */
5217 gas_assert (i.imm_operands == 1
5218 || (i.imm_operands == 0
5219 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
5220 || i.types[0].bitfield.shiftcount)));
5221 if (operand_type_check (i.types[0], imm)
5222 || i.types[0].bitfield.shiftcount)
5228 /* When there are 4 operands, the first two must be 8bit
5229 immediate operands. The source operand will be the 3rd
5232 For instructions with VexNDS, if the first operand
5233 an imm8, the source operand is the 2nd one. If the last
5234 operand is imm8, the source operand is the first one. */
5235 gas_assert ((i.imm_operands == 2
5236 && i.types[0].bitfield.imm8
5237 && i.types[1].bitfield.imm8)
5238 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
5239 && i.imm_operands == 1
5240 && (i.types[0].bitfield.imm8
5241 || i.types[i.operands - 1].bitfield.imm8)));
5242 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
5244 if (i.types[0].bitfield.imm8)
5262 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
5264 /* For instructions with VexNDS, the register-only
5265 source operand must be XMM or YMM register. It is
5266 encoded in VEX prefix. We need to clear RegMem bit
5267 before calling operand_type_equal. */
5268 i386_operand_type op = i.tm.operand_types[dest];
5269 op.bitfield.regmem = 0;
5270 if ((dest + 1) >= i.operands
5271 || (!operand_type_equal (&op, ®xmm)
5272 && !operand_type_equal (&op, ®ymm)))
5274 i.vex.register_specifier = i.op[dest].regs;
5280 /* One of the register operands will be encoded in the i.tm.reg
5281 field, the other in the combined i.tm.mode and i.tm.regmem
5282 fields. If no form of this instruction supports a memory
5283 destination operand, then we assume the source operand may
5284 sometimes be a memory operand and so we need to store the
5285 destination in the i.rm.reg field. */
5286 if (!i.tm.operand_types[dest].bitfield.regmem
5287 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
5289 i.rm.reg = i.op[dest].regs->reg_num;
5290 i.rm.regmem = i.op[source].regs->reg_num;
5291 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5293 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5298 i.rm.reg = i.op[source].regs->reg_num;
5299 i.rm.regmem = i.op[dest].regs->reg_num;
5300 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5302 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5305 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
5307 if (!i.types[0].bitfield.control
5308 && !i.types[1].bitfield.control)
5310 i.rex &= ~(REX_R | REX_B);
5311 add_prefix (LOCK_PREFIX_OPCODE);
5315 { /* If it's not 2 reg operands... */
5320 unsigned int fake_zero_displacement = 0;
5323 for (op = 0; op < i.operands; op++)
5324 if (operand_type_check (i.types[op], anymem))
5326 gas_assert (op < i.operands);
5330 if (i.base_reg == 0)
5333 if (!i.disp_operands)
5334 fake_zero_displacement = 1;
5335 if (i.index_reg == 0)
5337 /* Operand is just <disp> */
5338 if (flag_code == CODE_64BIT)
5340 /* 64bit mode overwrites the 32bit absolute
5341 addressing by RIP relative addressing and
5342 absolute addressing is encoded by one of the
5343 redundant SIB forms. */
5344 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5345 i.sib.base = NO_BASE_REGISTER;
5346 i.sib.index = NO_INDEX_REGISTER;
5347 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
5348 ? disp32s : disp32);
5350 else if ((flag_code == CODE_16BIT)
5351 ^ (i.prefix[ADDR_PREFIX] != 0))
5353 i.rm.regmem = NO_BASE_REGISTER_16;
5354 i.types[op] = disp16;
5358 i.rm.regmem = NO_BASE_REGISTER;
5359 i.types[op] = disp32;
5362 else /* !i.base_reg && i.index_reg */
5364 if (i.index_reg->reg_num == RegEiz
5365 || i.index_reg->reg_num == RegRiz)
5366 i.sib.index = NO_INDEX_REGISTER;
5368 i.sib.index = i.index_reg->reg_num;
5369 i.sib.base = NO_BASE_REGISTER;
5370 i.sib.scale = i.log2_scale_factor;
5371 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5372 i.types[op].bitfield.disp8 = 0;
5373 i.types[op].bitfield.disp16 = 0;
5374 i.types[op].bitfield.disp64 = 0;
5375 if (flag_code != CODE_64BIT)
5377 /* Must be 32 bit */
5378 i.types[op].bitfield.disp32 = 1;
5379 i.types[op].bitfield.disp32s = 0;
5383 i.types[op].bitfield.disp32 = 0;
5384 i.types[op].bitfield.disp32s = 1;
5386 if ((i.index_reg->reg_flags & RegRex) != 0)
5390 /* RIP addressing for 64bit mode. */
5391 else if (i.base_reg->reg_num == RegRip ||
5392 i.base_reg->reg_num == RegEip)
5394 i.rm.regmem = NO_BASE_REGISTER;
5395 i.types[op].bitfield.disp8 = 0;
5396 i.types[op].bitfield.disp16 = 0;
5397 i.types[op].bitfield.disp32 = 0;
5398 i.types[op].bitfield.disp32s = 1;
5399 i.types[op].bitfield.disp64 = 0;
5400 i.flags[op] |= Operand_PCrel;
5401 if (! i.disp_operands)
5402 fake_zero_displacement = 1;
5404 else if (i.base_reg->reg_type.bitfield.reg16)
5406 switch (i.base_reg->reg_num)
5409 if (i.index_reg == 0)
5411 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5412 i.rm.regmem = i.index_reg->reg_num - 6;
5416 if (i.index_reg == 0)
5419 if (operand_type_check (i.types[op], disp) == 0)
5421 /* fake (%bp) into 0(%bp) */
5422 i.types[op].bitfield.disp8 = 1;
5423 fake_zero_displacement = 1;
5426 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5427 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5429 default: /* (%si) -> 4 or (%di) -> 5 */
5430 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5432 i.rm.mode = mode_from_disp_size (i.types[op]);
5434 else /* i.base_reg and 32/64 bit mode */
5436 if (flag_code == CODE_64BIT
5437 && operand_type_check (i.types[op], disp))
5439 i386_operand_type temp;
5440 operand_type_set (&temp, 0);
5441 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5443 if (i.prefix[ADDR_PREFIX] == 0)
5444 i.types[op].bitfield.disp32s = 1;
5446 i.types[op].bitfield.disp32 = 1;
5449 i.rm.regmem = i.base_reg->reg_num;
5450 if ((i.base_reg->reg_flags & RegRex) != 0)
5452 i.sib.base = i.base_reg->reg_num;
5453 /* x86-64 ignores REX prefix bit here to avoid decoder
5455 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5458 if (i.disp_operands == 0)
5460 fake_zero_displacement = 1;
5461 i.types[op].bitfield.disp8 = 1;
5464 else if (i.base_reg->reg_num == ESP_REG_NUM)
5468 i.sib.scale = i.log2_scale_factor;
5469 if (i.index_reg == 0)
5471 /* <disp>(%esp) becomes two byte modrm with no index
5472 register. We've already stored the code for esp
5473 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5474 Any base register besides %esp will not use the
5475 extra modrm byte. */
5476 i.sib.index = NO_INDEX_REGISTER;
5480 if (i.index_reg->reg_num == RegEiz
5481 || i.index_reg->reg_num == RegRiz)
5482 i.sib.index = NO_INDEX_REGISTER;
5484 i.sib.index = i.index_reg->reg_num;
5485 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5486 if ((i.index_reg->reg_flags & RegRex) != 0)
5491 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5492 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5495 i.rm.mode = mode_from_disp_size (i.types[op]);
5498 if (fake_zero_displacement)
5500 /* Fakes a zero displacement assuming that i.types[op]
5501 holds the correct displacement size. */
5504 gas_assert (i.op[op].disps == 0);
5505 exp = &disp_expressions[i.disp_operands++];
5506 i.op[op].disps = exp;
5507 exp->X_op = O_constant;
5508 exp->X_add_number = 0;
5509 exp->X_add_symbol = (symbolS *) 0;
5510 exp->X_op_symbol = (symbolS *) 0;
5518 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5520 if (operand_type_check (i.types[0], imm))
5521 i.vex.register_specifier = NULL;
5524 /* VEX.vvvv encodes one of the sources when the first
5525 operand is not an immediate. */
5526 if (i.tm.opcode_modifier.vexw == VEXW0)
5527 i.vex.register_specifier = i.op[0].regs;
5529 i.vex.register_specifier = i.op[1].regs;
5532 /* Destination is a XMM register encoded in the ModRM.reg
5534 i.rm.reg = i.op[2].regs->reg_num;
5535 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5538 /* ModRM.rm and VEX.B encodes the other source. */
5539 if (!i.mem_operands)
5543 if (i.tm.opcode_modifier.vexw == VEXW0)
5544 i.rm.regmem = i.op[1].regs->reg_num;
5546 i.rm.regmem = i.op[0].regs->reg_num;
5548 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5552 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
5554 i.vex.register_specifier = i.op[2].regs;
5555 if (!i.mem_operands)
5558 i.rm.regmem = i.op[1].regs->reg_num;
5559 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5563 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5564 (if any) based on i.tm.extension_opcode. Again, we must be
5565 careful to make sure that segment/control/debug/test/MMX
5566 registers are coded into the i.rm.reg field. */
5567 else if (i.reg_operands)
5570 unsigned int vex_reg = ~0;
5572 for (op = 0; op < i.operands; op++)
5573 if (i.types[op].bitfield.reg8
5574 || i.types[op].bitfield.reg16
5575 || i.types[op].bitfield.reg32
5576 || i.types[op].bitfield.reg64
5577 || i.types[op].bitfield.regmmx
5578 || i.types[op].bitfield.regxmm
5579 || i.types[op].bitfield.regymm
5580 || i.types[op].bitfield.sreg2
5581 || i.types[op].bitfield.sreg3
5582 || i.types[op].bitfield.control
5583 || i.types[op].bitfield.debug
5584 || i.types[op].bitfield.test)
5589 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
5591 /* For instructions with VexNDS, the register-only
5592 source operand is encoded in VEX prefix. */
5593 gas_assert (mem != (unsigned int) ~0);
5598 gas_assert (op < i.operands);
5603 gas_assert (vex_reg < i.operands);
5606 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
5608 /* For instructions with VexNDD, there should be
5609 no memory operand and the register destination
5610 is encoded in VEX prefix. */
5611 gas_assert (i.mem_operands == 0
5612 && (op + 2) == i.operands);
5616 gas_assert (op < i.operands);
5618 if (vex_reg != (unsigned int) ~0)
5620 gas_assert (i.reg_operands == 2);
5622 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5624 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5628 i.vex.register_specifier = i.op[vex_reg].regs;
5631 /* Don't set OP operand twice. */
5634 /* If there is an extension opcode to put here, the
5635 register number must be put into the regmem field. */
5636 if (i.tm.extension_opcode != None)
5638 i.rm.regmem = i.op[op].regs->reg_num;
5639 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5644 i.rm.reg = i.op[op].regs->reg_num;
5645 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5650 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5651 must set it to 3 to indicate this is a register operand
5652 in the regmem field. */
5653 if (!i.mem_operands)
5657 /* Fill in i.rm.reg field with extension opcode (if any). */
5658 if (i.tm.extension_opcode != None)
5659 i.rm.reg = i.tm.extension_opcode;
5665 output_branch (void)
5670 relax_substateT subtype;
5675 if (flag_code == CODE_16BIT)
5679 if (i.prefix[DATA_PREFIX] != 0)
5685 /* Pentium4 branch hints. */
5686 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5687 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5692 if (i.prefix[REX_PREFIX] != 0)
5698 if (i.prefixes != 0 && !intel_syntax)
5699 as_warn (_("skipping prefixes on this instruction"));
5701 /* It's always a symbol; End frag & setup for relax.
5702 Make sure there is enough room in this frag for the largest
5703 instruction we may generate in md_convert_frag. This is 2
5704 bytes for the opcode and room for the prefix and largest
5706 frag_grow (prefix + 2 + 4);
5707 /* Prefix and 1 opcode byte go in fr_fix. */
5708 p = frag_more (prefix + 1);
5709 if (i.prefix[DATA_PREFIX] != 0)
5710 *p++ = DATA_PREFIX_OPCODE;
5711 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5712 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5713 *p++ = i.prefix[SEG_PREFIX];
5714 if (i.prefix[REX_PREFIX] != 0)
5715 *p++ = i.prefix[REX_PREFIX];
5716 *p = i.tm.base_opcode;
5718 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5719 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5720 else if (cpu_arch_flags.bitfield.cpui386)
5721 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5723 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5726 sym = i.op[0].disps->X_add_symbol;
5727 off = i.op[0].disps->X_add_number;
5729 if (i.op[0].disps->X_op != O_constant
5730 && i.op[0].disps->X_op != O_symbol)
5732 /* Handle complex expressions. */
5733 sym = make_expr_symbol (i.op[0].disps);
5737 /* 1 possible extra opcode + 4 byte displacement go in var part.
5738 Pass reloc in fr_var. */
5739 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5749 if (i.tm.opcode_modifier.jumpbyte)
5751 /* This is a loop or jecxz type instruction. */
5753 if (i.prefix[ADDR_PREFIX] != 0)
5755 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5758 /* Pentium4 branch hints. */
5759 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5760 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5762 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5771 if (flag_code == CODE_16BIT)
5774 if (i.prefix[DATA_PREFIX] != 0)
5776 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5786 if (i.prefix[REX_PREFIX] != 0)
5788 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5792 if (i.prefixes != 0 && !intel_syntax)
5793 as_warn (_("skipping prefixes on this instruction"));
5795 p = frag_more (1 + size);
5796 *p++ = i.tm.base_opcode;
5798 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5799 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5801 /* All jumps handled here are signed, but don't use a signed limit
5802 check for 32 and 16 bit jumps as we want to allow wrap around at
5803 4G and 64k respectively. */
5805 fixP->fx_signed = 1;
5809 output_interseg_jump (void)
5817 if (flag_code == CODE_16BIT)
5821 if (i.prefix[DATA_PREFIX] != 0)
5827 if (i.prefix[REX_PREFIX] != 0)
5837 if (i.prefixes != 0 && !intel_syntax)
5838 as_warn (_("skipping prefixes on this instruction"));
5840 /* 1 opcode; 2 segment; offset */
5841 p = frag_more (prefix + 1 + 2 + size);
5843 if (i.prefix[DATA_PREFIX] != 0)
5844 *p++ = DATA_PREFIX_OPCODE;
5846 if (i.prefix[REX_PREFIX] != 0)
5847 *p++ = i.prefix[REX_PREFIX];
5849 *p++ = i.tm.base_opcode;
5850 if (i.op[1].imms->X_op == O_constant)
5852 offsetT n = i.op[1].imms->X_add_number;
5855 && !fits_in_unsigned_word (n)
5856 && !fits_in_signed_word (n))
5858 as_bad (_("16-bit jump out of range"));
5861 md_number_to_chars (p, n, size);
5864 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5865 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5866 if (i.op[0].imms->X_op != O_constant)
5867 as_bad (_("can't handle non absolute segment in `%s'"),
5869 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5875 fragS *insn_start_frag;
5876 offsetT insn_start_off;
5878 /* Tie dwarf2 debug info to the address at the start of the insn.
5879 We can't do this after the insn has been output as the current
5880 frag may have been closed off. eg. by frag_var. */
5881 dwarf2_emit_insn (0);
5883 insn_start_frag = frag_now;
5884 insn_start_off = frag_now_fix ();
5887 if (i.tm.opcode_modifier.jump)
5889 else if (i.tm.opcode_modifier.jumpbyte
5890 || i.tm.opcode_modifier.jumpdword)
5892 else if (i.tm.opcode_modifier.jumpintersegment)
5893 output_interseg_jump ();
5896 /* Output normal instructions here. */
5900 unsigned int prefix;
5902 /* Since the VEX prefix contains the implicit prefix, we don't
5903 need the explicit prefix. */
5904 if (!i.tm.opcode_modifier.vex)
5906 switch (i.tm.opcode_length)
5909 if (i.tm.base_opcode & 0xff000000)
5911 prefix = (i.tm.base_opcode >> 24) & 0xff;
5916 if ((i.tm.base_opcode & 0xff0000) != 0)
5918 prefix = (i.tm.base_opcode >> 16) & 0xff;
5919 if (i.tm.cpu_flags.bitfield.cpupadlock)
5922 if (prefix != REPE_PREFIX_OPCODE
5923 || (i.prefix[REP_PREFIX]
5924 != REPE_PREFIX_OPCODE))
5925 add_prefix (prefix);
5928 add_prefix (prefix);
5937 /* The prefix bytes. */
5938 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5940 FRAG_APPEND_1_CHAR (*q);
5943 if (i.tm.opcode_modifier.vex)
5945 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5950 /* REX byte is encoded in VEX prefix. */
5954 FRAG_APPEND_1_CHAR (*q);
5957 /* There should be no other prefixes for instructions
5962 /* Now the VEX prefix. */
5963 p = frag_more (i.vex.length);
5964 for (j = 0; j < i.vex.length; j++)
5965 p[j] = i.vex.bytes[j];
5968 /* Now the opcode; be careful about word order here! */
5969 if (i.tm.opcode_length == 1)
5971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5975 switch (i.tm.opcode_length)
5979 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5989 /* Put out high byte first: can't use md_number_to_chars! */
5990 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5991 *p = i.tm.base_opcode & 0xff;
5994 /* Now the modrm byte and sib byte (if present). */
5995 if (i.tm.opcode_modifier.modrm)
5997 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6000 /* If i.rm.regmem == ESP (4)
6001 && i.rm.mode != (Register mode)
6003 ==> need second modrm byte. */
6004 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6006 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
6007 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6009 | i.sib.scale << 6));
6012 if (i.disp_operands)
6013 output_disp (insn_start_frag, insn_start_off);
6016 output_imm (insn_start_frag, insn_start_off);
6022 pi ("" /*line*/, &i);
6024 #endif /* DEBUG386 */
6027 /* Return the size of the displacement operand N. */
6030 disp_size (unsigned int n)
6033 if (i.types[n].bitfield.disp64)
6035 else if (i.types[n].bitfield.disp8)
6037 else if (i.types[n].bitfield.disp16)
6042 /* Return the size of the immediate operand N. */
6045 imm_size (unsigned int n)
6048 if (i.types[n].bitfield.imm64)
6050 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6052 else if (i.types[n].bitfield.imm16)
6058 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
6063 for (n = 0; n < i.operands; n++)
6065 if (operand_type_check (i.types[n], disp))
6067 if (i.op[n].disps->X_op == O_constant)
6069 int size = disp_size (n);
6072 val = offset_in_range (i.op[n].disps->X_add_number,
6074 p = frag_more (size);
6075 md_number_to_chars (p, val, size);
6079 enum bfd_reloc_code_real reloc_type;
6080 int size = disp_size (n);
6081 int sign = i.types[n].bitfield.disp32s;
6082 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6084 /* We can't have 8 bit displacement here. */
6085 gas_assert (!i.types[n].bitfield.disp8);
6087 /* The PC relative address is computed relative
6088 to the instruction boundary, so in case immediate
6089 fields follows, we need to adjust the value. */
6090 if (pcrel && i.imm_operands)
6095 for (n1 = 0; n1 < i.operands; n1++)
6096 if (operand_type_check (i.types[n1], imm))
6098 /* Only one immediate is allowed for PC
6099 relative address. */
6100 gas_assert (sz == 0);
6102 i.op[n].disps->X_add_number -= sz;
6104 /* We should find the immediate. */
6105 gas_assert (sz != 0);
6108 p = frag_more (size);
6109 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
6111 && GOT_symbol == i.op[n].disps->X_add_symbol
6112 && (((reloc_type == BFD_RELOC_32
6113 || reloc_type == BFD_RELOC_X86_64_32S
6114 || (reloc_type == BFD_RELOC_64
6116 && (i.op[n].disps->X_op == O_symbol
6117 || (i.op[n].disps->X_op == O_add
6118 && ((symbol_get_value_expression
6119 (i.op[n].disps->X_op_symbol)->X_op)
6121 || reloc_type == BFD_RELOC_32_PCREL))
6125 if (insn_start_frag == frag_now)
6126 add = (p - frag_now->fr_literal) - insn_start_off;
6131 add = insn_start_frag->fr_fix - insn_start_off;
6132 for (fr = insn_start_frag->fr_next;
6133 fr && fr != frag_now; fr = fr->fr_next)
6135 add += p - frag_now->fr_literal;
6140 reloc_type = BFD_RELOC_386_GOTPC;
6141 i.op[n].imms->X_add_number += add;
6143 else if (reloc_type == BFD_RELOC_64)
6144 reloc_type = BFD_RELOC_X86_64_GOTPC64;
6146 /* Don't do the adjustment for x86-64, as there
6147 the pcrel addressing is relative to the _next_
6148 insn, and that is taken care of in other code. */
6149 reloc_type = BFD_RELOC_X86_64_GOTPC32;
6151 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6152 i.op[n].disps, pcrel, reloc_type);
6159 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
6164 for (n = 0; n < i.operands; n++)
6166 if (operand_type_check (i.types[n], imm))
6168 if (i.op[n].imms->X_op == O_constant)
6170 int size = imm_size (n);
6173 val = offset_in_range (i.op[n].imms->X_add_number,
6175 p = frag_more (size);
6176 md_number_to_chars (p, val, size);
6180 /* Not absolute_section.
6181 Need a 32-bit fixup (don't support 8bit
6182 non-absolute imms). Try to support other
6184 enum bfd_reloc_code_real reloc_type;
6185 int size = imm_size (n);
6188 if (i.types[n].bitfield.imm32s
6189 && (i.suffix == QWORD_MNEM_SUFFIX
6190 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
6195 p = frag_more (size);
6196 reloc_type = reloc (size, 0, sign, i.reloc[n]);
6198 /* This is tough to explain. We end up with this one if we
6199 * have operands that look like
6200 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6201 * obtain the absolute address of the GOT, and it is strongly
6202 * preferable from a performance point of view to avoid using
6203 * a runtime relocation for this. The actual sequence of
6204 * instructions often look something like:
6209 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6211 * The call and pop essentially return the absolute address
6212 * of the label .L66 and store it in %ebx. The linker itself
6213 * will ultimately change the first operand of the addl so
6214 * that %ebx points to the GOT, but to keep things simple, the
6215 * .o file must have this operand set so that it generates not
6216 * the absolute address of .L66, but the absolute address of
6217 * itself. This allows the linker itself simply treat a GOTPC
6218 * relocation as asking for a pcrel offset to the GOT to be
6219 * added in, and the addend of the relocation is stored in the
6220 * operand field for the instruction itself.
6222 * Our job here is to fix the operand so that it would add
6223 * the correct offset so that %ebx would point to itself. The
6224 * thing that is tricky is that .-.L66 will point to the
6225 * beginning of the instruction, so we need to further modify
6226 * the operand so that it will point to itself. There are
6227 * other cases where you have something like:
6229 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6231 * and here no correction would be required. Internally in
6232 * the assembler we treat operands of this form as not being
6233 * pcrel since the '.' is explicitly mentioned, and I wonder
6234 * whether it would simplify matters to do it this way. Who
6235 * knows. In earlier versions of the PIC patches, the
6236 * pcrel_adjust field was used to store the correction, but
6237 * since the expression is not pcrel, I felt it would be
6238 * confusing to do it this way. */
6240 if ((reloc_type == BFD_RELOC_32
6241 || reloc_type == BFD_RELOC_X86_64_32S
6242 || reloc_type == BFD_RELOC_64)
6244 && GOT_symbol == i.op[n].imms->X_add_symbol
6245 && (i.op[n].imms->X_op == O_symbol
6246 || (i.op[n].imms->X_op == O_add
6247 && ((symbol_get_value_expression
6248 (i.op[n].imms->X_op_symbol)->X_op)
6253 if (insn_start_frag == frag_now)
6254 add = (p - frag_now->fr_literal) - insn_start_off;
6259 add = insn_start_frag->fr_fix - insn_start_off;
6260 for (fr = insn_start_frag->fr_next;
6261 fr && fr != frag_now; fr = fr->fr_next)
6263 add += p - frag_now->fr_literal;
6267 reloc_type = BFD_RELOC_386_GOTPC;
6269 reloc_type = BFD_RELOC_X86_64_GOTPC32;
6271 reloc_type = BFD_RELOC_X86_64_GOTPC64;
6272 i.op[n].imms->X_add_number += add;
6274 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6275 i.op[n].imms, 0, reloc_type);
6281 /* x86_cons_fix_new is called via the expression parsing code when a
6282 reloc is needed. We use this hook to get the correct .got reloc. */
6283 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6284 static int cons_sign = -1;
6287 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
6290 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6292 got_reloc = NO_RELOC;
6295 if (exp->X_op == O_secrel)
6297 exp->X_op = O_symbol;
6298 r = BFD_RELOC_32_SECREL;
6302 fix_new_exp (frag, off, len, exp, 0, r);
6305 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6306 # define lex_got(reloc, adjust, types) NULL
6308 /* Parse operands of the form
6309 <symbol>@GOTOFF+<nnn>
6310 and similar .plt or .got references.
6312 If we find one, set up the correct relocation in RELOC and copy the
6313 input string, minus the `@GOTOFF' into a malloc'd buffer for
6314 parsing by the calling routine. Return this buffer, and if ADJUST
6315 is non-null set it to the length of the string we removed from the
6316 input line. Otherwise return NULL. */
6318 lex_got (enum bfd_reloc_code_real *rel,
6320 i386_operand_type *types)
6322 /* Some of the relocations depend on the size of what field is to
6323 be relocated. But in our callers i386_immediate and i386_displacement
6324 we don't yet know the operand size (this will be set by insn
6325 matching). Hence we record the word32 relocation here,
6326 and adjust the reloc according to the real size in reloc(). */
6327 static const struct {
6330 const enum bfd_reloc_code_real rel[2];
6331 const i386_operand_type types64;
6333 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6334 BFD_RELOC_X86_64_PLTOFF64 },
6335 OPERAND_TYPE_IMM64 },
6336 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6337 BFD_RELOC_X86_64_PLT32 },
6338 OPERAND_TYPE_IMM32_32S_DISP32 },
6339 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6340 BFD_RELOC_X86_64_GOTPLT64 },
6341 OPERAND_TYPE_IMM64_DISP64 },
6342 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6343 BFD_RELOC_X86_64_GOTOFF64 },
6344 OPERAND_TYPE_IMM64_DISP64 },
6345 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6346 BFD_RELOC_X86_64_GOTPCREL },
6347 OPERAND_TYPE_IMM32_32S_DISP32 },
6348 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6349 BFD_RELOC_X86_64_TLSGD },
6350 OPERAND_TYPE_IMM32_32S_DISP32 },
6351 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6352 _dummy_first_bfd_reloc_code_real },
6353 OPERAND_TYPE_NONE },
6354 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6355 BFD_RELOC_X86_64_TLSLD },
6356 OPERAND_TYPE_IMM32_32S_DISP32 },
6357 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6358 BFD_RELOC_X86_64_GOTTPOFF },
6359 OPERAND_TYPE_IMM32_32S_DISP32 },
6360 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6361 BFD_RELOC_X86_64_TPOFF32 },
6362 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6363 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6364 _dummy_first_bfd_reloc_code_real },
6365 OPERAND_TYPE_NONE },
6366 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6367 BFD_RELOC_X86_64_DTPOFF32 },
6368 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6369 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6370 _dummy_first_bfd_reloc_code_real },
6371 OPERAND_TYPE_NONE },
6372 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6373 _dummy_first_bfd_reloc_code_real },
6374 OPERAND_TYPE_NONE },
6375 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6376 BFD_RELOC_X86_64_GOT32 },
6377 OPERAND_TYPE_IMM32_32S_64_DISP32 },
6378 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6379 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
6380 OPERAND_TYPE_IMM32_32S_DISP32 },
6381 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6382 BFD_RELOC_X86_64_TLSDESC_CALL },
6383 OPERAND_TYPE_IMM32_32S_DISP32 },
6391 for (cp = input_line_pointer; *cp != '@'; cp++)
6392 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6395 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6397 int len = gotrel[j].len;
6398 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6400 if (gotrel[j].rel[object_64bit] != 0)
6403 char *tmpbuf, *past_reloc;
6405 *rel = gotrel[j].rel[object_64bit];
6411 if (flag_code != CODE_64BIT)
6413 types->bitfield.imm32 = 1;
6414 types->bitfield.disp32 = 1;
6417 *types = gotrel[j].types64;
6420 if (GOT_symbol == NULL)
6421 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6423 /* The length of the first part of our input line. */
6424 first = cp - input_line_pointer;
6426 /* The second part goes from after the reloc token until
6427 (and including) an end_of_line char or comma. */
6428 past_reloc = cp + 1 + len;
6430 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6432 second = cp + 1 - past_reloc;
6434 /* Allocate and copy string. The trailing NUL shouldn't
6435 be necessary, but be safe. */
6436 tmpbuf = (char *) xmalloc (first + second + 2);
6437 memcpy (tmpbuf, input_line_pointer, first);
6438 if (second != 0 && *past_reloc != ' ')
6439 /* Replace the relocation token with ' ', so that
6440 errors like foo@GOTOFF1 will be detected. */
6441 tmpbuf[first++] = ' ';
6442 memcpy (tmpbuf + first, past_reloc, second);
6443 tmpbuf[first + second] = '\0';
6447 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6448 gotrel[j].str, 1 << (5 + object_64bit));
6453 /* Might be a symbol version string. Don't as_bad here. */
6458 x86_cons (expressionS *exp, int size)
6460 intel_syntax = -intel_syntax;
6463 if (size == 4 || (object_64bit && size == 8))
6465 /* Handle @GOTOFF and the like in an expression. */
6467 char *gotfree_input_line;
6470 save = input_line_pointer;
6471 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
6472 if (gotfree_input_line)
6473 input_line_pointer = gotfree_input_line;
6477 if (gotfree_input_line)
6479 /* expression () has merrily parsed up to the end of line,
6480 or a comma - in the wrong buffer. Transfer how far
6481 input_line_pointer has moved to the right buffer. */
6482 input_line_pointer = (save
6483 + (input_line_pointer - gotfree_input_line)
6485 free (gotfree_input_line);
6486 if (exp->X_op == O_constant
6487 || exp->X_op == O_absent
6488 || exp->X_op == O_illegal
6489 || i386_is_register (exp)
6490 || exp->X_op == O_big)
6492 char c = *input_line_pointer;
6493 *input_line_pointer = 0;
6494 as_bad (_("missing or invalid expression `%s'"), save);
6495 *input_line_pointer = c;
6502 intel_syntax = -intel_syntax;
6505 i386_intel_simplify (exp);
6510 signed_cons (int size)
6512 if (flag_code == CODE_64BIT)
6520 pe_directive_secrel (dummy)
6521 int dummy ATTRIBUTE_UNUSED;
6528 if (exp.X_op == O_symbol)
6529 exp.X_op = O_secrel;
6531 emit_expr (&exp, 4);
6533 while (*input_line_pointer++ == ',');
6535 input_line_pointer--;
6536 demand_empty_rest_of_line ();
6541 i386_immediate (char *imm_start)
6543 char *save_input_line_pointer;
6544 char *gotfree_input_line;
6547 i386_operand_type types;
6549 operand_type_set (&types, ~0);
6551 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6553 as_bad (_("at most %d immediate operands are allowed"),
6554 MAX_IMMEDIATE_OPERANDS);
6558 exp = &im_expressions[i.imm_operands++];
6559 i.op[this_operand].imms = exp;
6561 if (is_space_char (*imm_start))
6564 save_input_line_pointer = input_line_pointer;
6565 input_line_pointer = imm_start;
6567 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6568 if (gotfree_input_line)
6569 input_line_pointer = gotfree_input_line;
6571 exp_seg = expression (exp);
6574 if (*input_line_pointer)
6575 as_bad (_("junk `%s' after expression"), input_line_pointer);
6577 input_line_pointer = save_input_line_pointer;
6578 if (gotfree_input_line)
6580 free (gotfree_input_line);
6582 if (exp->X_op == O_constant || exp->X_op == O_register)
6583 exp->X_op = O_illegal;
6586 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6590 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6591 i386_operand_type types, const char *imm_start)
6593 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
6596 as_bad (_("missing or invalid immediate expression `%s'"),
6600 else if (exp->X_op == O_constant)
6602 /* Size it properly later. */
6603 i.types[this_operand].bitfield.imm64 = 1;
6604 /* If BFD64, sign extend val. */
6605 if (!use_rela_relocations
6606 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6608 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
6610 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6611 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
6612 && exp_seg != absolute_section
6613 && exp_seg != text_section
6614 && exp_seg != data_section
6615 && exp_seg != bss_section
6616 && exp_seg != undefined_section
6617 && !bfd_is_com_section (exp_seg))
6619 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6623 else if (!intel_syntax && exp->X_op == O_register)
6626 as_bad (_("illegal immediate register operand %s"), imm_start);
6631 /* This is an address. The size of the address will be
6632 determined later, depending on destination register,
6633 suffix, or the default for the section. */
6634 i.types[this_operand].bitfield.imm8 = 1;
6635 i.types[this_operand].bitfield.imm16 = 1;
6636 i.types[this_operand].bitfield.imm32 = 1;
6637 i.types[this_operand].bitfield.imm32s = 1;
6638 i.types[this_operand].bitfield.imm64 = 1;
6639 i.types[this_operand] = operand_type_and (i.types[this_operand],
6647 i386_scale (char *scale)
6650 char *save = input_line_pointer;
6652 input_line_pointer = scale;
6653 val = get_absolute_expression ();
6658 i.log2_scale_factor = 0;
6661 i.log2_scale_factor = 1;
6664 i.log2_scale_factor = 2;
6667 i.log2_scale_factor = 3;
6671 char sep = *input_line_pointer;
6673 *input_line_pointer = '\0';
6674 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6676 *input_line_pointer = sep;
6677 input_line_pointer = save;
6681 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6683 as_warn (_("scale factor of %d without an index register"),
6684 1 << i.log2_scale_factor);
6685 i.log2_scale_factor = 0;
6687 scale = input_line_pointer;
6688 input_line_pointer = save;
6693 i386_displacement (char *disp_start, char *disp_end)
6697 char *save_input_line_pointer;
6698 char *gotfree_input_line;
6700 i386_operand_type bigdisp, types = anydisp;
6703 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6705 as_bad (_("at most %d displacement operands are allowed"),
6706 MAX_MEMORY_OPERANDS);
6710 operand_type_set (&bigdisp, 0);
6711 if ((i.types[this_operand].bitfield.jumpabsolute)
6712 || (!current_templates->start->opcode_modifier.jump
6713 && !current_templates->start->opcode_modifier.jumpdword))
6715 bigdisp.bitfield.disp32 = 1;
6716 override = (i.prefix[ADDR_PREFIX] != 0);
6717 if (flag_code == CODE_64BIT)
6721 bigdisp.bitfield.disp32s = 1;
6722 bigdisp.bitfield.disp64 = 1;
6725 else if ((flag_code == CODE_16BIT) ^ override)
6727 bigdisp.bitfield.disp32 = 0;
6728 bigdisp.bitfield.disp16 = 1;
6733 /* For PC-relative branches, the width of the displacement
6734 is dependent upon data size, not address size. */
6735 override = (i.prefix[DATA_PREFIX] != 0);
6736 if (flag_code == CODE_64BIT)
6738 if (override || i.suffix == WORD_MNEM_SUFFIX)
6739 bigdisp.bitfield.disp16 = 1;
6742 bigdisp.bitfield.disp32 = 1;
6743 bigdisp.bitfield.disp32s = 1;
6749 override = (i.suffix == (flag_code != CODE_16BIT
6751 : LONG_MNEM_SUFFIX));
6752 bigdisp.bitfield.disp32 = 1;
6753 if ((flag_code == CODE_16BIT) ^ override)
6755 bigdisp.bitfield.disp32 = 0;
6756 bigdisp.bitfield.disp16 = 1;
6760 i.types[this_operand] = operand_type_or (i.types[this_operand],
6763 exp = &disp_expressions[i.disp_operands];
6764 i.op[this_operand].disps = exp;
6766 save_input_line_pointer = input_line_pointer;
6767 input_line_pointer = disp_start;
6768 END_STRING_AND_SAVE (disp_end);
6770 #ifndef GCC_ASM_O_HACK
6771 #define GCC_ASM_O_HACK 0
6774 END_STRING_AND_SAVE (disp_end + 1);
6775 if (i.types[this_operand].bitfield.baseIndex
6776 && displacement_string_end[-1] == '+')
6778 /* This hack is to avoid a warning when using the "o"
6779 constraint within gcc asm statements.
6782 #define _set_tssldt_desc(n,addr,limit,type) \
6783 __asm__ __volatile__ ( \
6785 "movw %w1,2+%0\n\t" \
6787 "movb %b1,4+%0\n\t" \
6788 "movb %4,5+%0\n\t" \
6789 "movb $0,6+%0\n\t" \
6790 "movb %h1,7+%0\n\t" \
6792 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6794 This works great except that the output assembler ends
6795 up looking a bit weird if it turns out that there is
6796 no offset. You end up producing code that looks like:
6809 So here we provide the missing zero. */
6811 *displacement_string_end = '0';
6814 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6815 if (gotfree_input_line)
6816 input_line_pointer = gotfree_input_line;
6818 exp_seg = expression (exp);
6821 if (*input_line_pointer)
6822 as_bad (_("junk `%s' after expression"), input_line_pointer);
6824 RESTORE_END_STRING (disp_end + 1);
6826 input_line_pointer = save_input_line_pointer;
6827 if (gotfree_input_line)
6829 free (gotfree_input_line);
6831 if (exp->X_op == O_constant || exp->X_op == O_register)
6832 exp->X_op = O_illegal;
6835 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6837 RESTORE_END_STRING (disp_end);
6843 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6844 i386_operand_type types, const char *disp_start)
6846 i386_operand_type bigdisp;
6849 /* We do this to make sure that the section symbol is in
6850 the symbol table. We will ultimately change the relocation
6851 to be relative to the beginning of the section. */
6852 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6853 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6854 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6856 if (exp->X_op != O_symbol)
6859 if (S_IS_LOCAL (exp->X_add_symbol)
6860 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6861 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6862 exp->X_op = O_subtract;
6863 exp->X_op_symbol = GOT_symbol;
6864 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6865 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6866 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6867 i.reloc[this_operand] = BFD_RELOC_64;
6869 i.reloc[this_operand] = BFD_RELOC_32;
6872 else if (exp->X_op == O_absent
6873 || exp->X_op == O_illegal
6874 || exp->X_op == O_big)
6877 as_bad (_("missing or invalid displacement expression `%s'"),
6882 else if (flag_code == CODE_64BIT
6883 && !i.prefix[ADDR_PREFIX]
6884 && exp->X_op == O_constant)
6886 /* Since displacement is signed extended to 64bit, don't allow
6887 disp32 and turn off disp32s if they are out of range. */
6888 i.types[this_operand].bitfield.disp32 = 0;
6889 if (!fits_in_signed_long (exp->X_add_number))
6891 i.types[this_operand].bitfield.disp32s = 0;
6892 if (i.types[this_operand].bitfield.baseindex)
6894 as_bad (_("0x%lx out range of signed 32bit displacement"),
6895 (long) exp->X_add_number);
6901 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6902 else if (exp->X_op != O_constant
6903 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6904 && exp_seg != absolute_section
6905 && exp_seg != text_section
6906 && exp_seg != data_section
6907 && exp_seg != bss_section
6908 && exp_seg != undefined_section
6909 && !bfd_is_com_section (exp_seg))
6911 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6916 /* Check if this is a displacement only operand. */
6917 bigdisp = i.types[this_operand];
6918 bigdisp.bitfield.disp8 = 0;
6919 bigdisp.bitfield.disp16 = 0;
6920 bigdisp.bitfield.disp32 = 0;
6921 bigdisp.bitfield.disp32s = 0;
6922 bigdisp.bitfield.disp64 = 0;
6923 if (operand_type_all_zero (&bigdisp))
6924 i.types[this_operand] = operand_type_and (i.types[this_operand],
6930 /* Make sure the memory operand we've been dealt is valid.
6931 Return 1 on success, 0 on a failure. */
6934 i386_index_check (const char *operand_string)
6937 const char *kind = "base/index";
6938 #if INFER_ADDR_PREFIX
6944 if (current_templates->start->opcode_modifier.isstring
6945 && !current_templates->start->opcode_modifier.immext
6946 && (current_templates->end[-1].opcode_modifier.isstring
6949 /* Memory operands of string insns are special in that they only allow
6950 a single register (rDI, rSI, or rBX) as their memory address. */
6951 unsigned int expected;
6953 kind = "string address";
6955 if (current_templates->start->opcode_modifier.w)
6957 i386_operand_type type = current_templates->end[-1].operand_types[0];
6959 if (!type.bitfield.baseindex
6960 || ((!i.mem_operands != !intel_syntax)
6961 && current_templates->end[-1].operand_types[1]
6962 .bitfield.baseindex))
6963 type = current_templates->end[-1].operand_types[1];
6964 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6967 expected = 3 /* rBX */;
6969 if (!i.base_reg || i.index_reg
6970 || operand_type_check (i.types[this_operand], disp))
6972 else if (!(flag_code == CODE_64BIT
6973 ? i.prefix[ADDR_PREFIX]
6974 ? i.base_reg->reg_type.bitfield.reg32
6975 : i.base_reg->reg_type.bitfield.reg64
6976 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6977 ? i.base_reg->reg_type.bitfield.reg32
6978 : i.base_reg->reg_type.bitfield.reg16))
6980 else if (i.base_reg->reg_num != expected)
6987 for (j = 0; j < i386_regtab_size; ++j)
6988 if ((flag_code == CODE_64BIT
6989 ? i.prefix[ADDR_PREFIX]
6990 ? i386_regtab[j].reg_type.bitfield.reg32
6991 : i386_regtab[j].reg_type.bitfield.reg64
6992 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6993 ? i386_regtab[j].reg_type.bitfield.reg32
6994 : i386_regtab[j].reg_type.bitfield.reg16)
6995 && i386_regtab[j].reg_num == expected)
6997 gas_assert (j < i386_regtab_size);
6998 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7000 intel_syntax ? '[' : '(',
7002 i386_regtab[j].reg_name,
7003 intel_syntax ? ']' : ')');
7007 else if (flag_code == CODE_64BIT)
7010 && ((i.prefix[ADDR_PREFIX] == 0
7011 && !i.base_reg->reg_type.bitfield.reg64)
7012 || (i.prefix[ADDR_PREFIX]
7013 && !i.base_reg->reg_type.bitfield.reg32))
7015 || i.base_reg->reg_num !=
7016 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
7018 && (!i.index_reg->reg_type.bitfield.baseindex
7019 || (i.prefix[ADDR_PREFIX] == 0
7020 && i.index_reg->reg_num != RegRiz
7021 && !i.index_reg->reg_type.bitfield.reg64
7023 || (i.prefix[ADDR_PREFIX]
7024 && i.index_reg->reg_num != RegEiz
7025 && !i.index_reg->reg_type.bitfield.reg32))))
7030 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7034 && (!i.base_reg->reg_type.bitfield.reg16
7035 || !i.base_reg->reg_type.bitfield.baseindex))
7037 && (!i.index_reg->reg_type.bitfield.reg16
7038 || !i.index_reg->reg_type.bitfield.baseindex
7040 && i.base_reg->reg_num < 6
7041 && i.index_reg->reg_num >= 6
7042 && i.log2_scale_factor == 0))))
7049 && !i.base_reg->reg_type.bitfield.reg32)
7051 && ((!i.index_reg->reg_type.bitfield.reg32
7052 && i.index_reg->reg_num != RegEiz)
7053 || !i.index_reg->reg_type.bitfield.baseindex)))
7059 #if INFER_ADDR_PREFIX
7060 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
7062 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7064 /* Change the size of any displacement too. At most one of
7065 Disp16 or Disp32 is set.
7066 FIXME. There doesn't seem to be any real need for separate
7067 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7068 Removing them would probably clean up the code quite a lot. */
7069 if (flag_code != CODE_64BIT
7070 && (i.types[this_operand].bitfield.disp16
7071 || i.types[this_operand].bitfield.disp32))
7072 i.types[this_operand]
7073 = operand_type_xor (i.types[this_operand], disp16_32);
7078 as_bad (_("`%s' is not a valid %s expression"),
7083 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7085 flag_code_names[i.prefix[ADDR_PREFIX]
7086 ? flag_code == CODE_32BIT
7095 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7099 i386_att_operand (char *operand_string)
7103 char *op_string = operand_string;
7105 if (is_space_char (*op_string))
7108 /* We check for an absolute prefix (differentiating,
7109 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7110 if (*op_string == ABSOLUTE_PREFIX)
7113 if (is_space_char (*op_string))
7115 i.types[this_operand].bitfield.jumpabsolute = 1;
7118 /* Check if operand is a register. */
7119 if ((r = parse_register (op_string, &end_op)) != NULL)
7121 i386_operand_type temp;
7123 /* Check for a segment override by searching for ':' after a
7124 segment register. */
7126 if (is_space_char (*op_string))
7128 if (*op_string == ':'
7129 && (r->reg_type.bitfield.sreg2
7130 || r->reg_type.bitfield.sreg3))
7135 i.seg[i.mem_operands] = &es;
7138 i.seg[i.mem_operands] = &cs;
7141 i.seg[i.mem_operands] = &ss;
7144 i.seg[i.mem_operands] = &ds;
7147 i.seg[i.mem_operands] = &fs;
7150 i.seg[i.mem_operands] = &gs;
7154 /* Skip the ':' and whitespace. */
7156 if (is_space_char (*op_string))
7159 if (!is_digit_char (*op_string)
7160 && !is_identifier_char (*op_string)
7161 && *op_string != '('
7162 && *op_string != ABSOLUTE_PREFIX)
7164 as_bad (_("bad memory operand `%s'"), op_string);
7167 /* Handle case of %es:*foo. */
7168 if (*op_string == ABSOLUTE_PREFIX)
7171 if (is_space_char (*op_string))
7173 i.types[this_operand].bitfield.jumpabsolute = 1;
7175 goto do_memory_reference;
7179 as_bad (_("junk `%s' after register"), op_string);
7183 temp.bitfield.baseindex = 0;
7184 i.types[this_operand] = operand_type_or (i.types[this_operand],
7186 i.types[this_operand].bitfield.unspecified = 0;
7187 i.op[this_operand].regs = r;
7190 else if (*op_string == REGISTER_PREFIX)
7192 as_bad (_("bad register name `%s'"), op_string);
7195 else if (*op_string == IMMEDIATE_PREFIX)
7198 if (i.types[this_operand].bitfield.jumpabsolute)
7200 as_bad (_("immediate operand illegal with absolute jump"));
7203 if (!i386_immediate (op_string))
7206 else if (is_digit_char (*op_string)
7207 || is_identifier_char (*op_string)
7208 || *op_string == '(')
7210 /* This is a memory reference of some sort. */
7213 /* Start and end of displacement string expression (if found). */
7214 char *displacement_string_start;
7215 char *displacement_string_end;
7217 do_memory_reference:
7218 if ((i.mem_operands == 1
7219 && !current_templates->start->opcode_modifier.isstring)
7220 || i.mem_operands == 2)
7222 as_bad (_("too many memory references for `%s'"),
7223 current_templates->start->name);
7227 /* Check for base index form. We detect the base index form by
7228 looking for an ')' at the end of the operand, searching
7229 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7231 base_string = op_string + strlen (op_string);
7234 if (is_space_char (*base_string))
7237 /* If we only have a displacement, set-up for it to be parsed later. */
7238 displacement_string_start = op_string;
7239 displacement_string_end = base_string + 1;
7241 if (*base_string == ')')
7244 unsigned int parens_balanced = 1;
7245 /* We've already checked that the number of left & right ()'s are
7246 equal, so this loop will not be infinite. */
7250 if (*base_string == ')')
7252 if (*base_string == '(')
7255 while (parens_balanced);
7257 temp_string = base_string;
7259 /* Skip past '(' and whitespace. */
7261 if (is_space_char (*base_string))
7264 if (*base_string == ','
7265 || ((i.base_reg = parse_register (base_string, &end_op))
7268 displacement_string_end = temp_string;
7270 i.types[this_operand].bitfield.baseindex = 1;
7274 base_string = end_op;
7275 if (is_space_char (*base_string))
7279 /* There may be an index reg or scale factor here. */
7280 if (*base_string == ',')
7283 if (is_space_char (*base_string))
7286 if ((i.index_reg = parse_register (base_string, &end_op))
7289 base_string = end_op;
7290 if (is_space_char (*base_string))
7292 if (*base_string == ',')
7295 if (is_space_char (*base_string))
7298 else if (*base_string != ')')
7300 as_bad (_("expecting `,' or `)' "
7301 "after index register in `%s'"),
7306 else if (*base_string == REGISTER_PREFIX)
7308 as_bad (_("bad register name `%s'"), base_string);
7312 /* Check for scale factor. */
7313 if (*base_string != ')')
7315 char *end_scale = i386_scale (base_string);
7320 base_string = end_scale;
7321 if (is_space_char (*base_string))
7323 if (*base_string != ')')
7325 as_bad (_("expecting `)' "
7326 "after scale factor in `%s'"),
7331 else if (!i.index_reg)
7333 as_bad (_("expecting index register or scale factor "
7334 "after `,'; got '%c'"),
7339 else if (*base_string != ')')
7341 as_bad (_("expecting `,' or `)' "
7342 "after base register in `%s'"),
7347 else if (*base_string == REGISTER_PREFIX)
7349 as_bad (_("bad register name `%s'"), base_string);
7354 /* If there's an expression beginning the operand, parse it,
7355 assuming displacement_string_start and
7356 displacement_string_end are meaningful. */
7357 if (displacement_string_start != displacement_string_end)
7359 if (!i386_displacement (displacement_string_start,
7360 displacement_string_end))
7364 /* Special case for (%dx) while doing input/output op. */
7366 && operand_type_equal (&i.base_reg->reg_type,
7367 ®16_inoutportreg)
7369 && i.log2_scale_factor == 0
7370 && i.seg[i.mem_operands] == 0
7371 && !operand_type_check (i.types[this_operand], disp))
7373 i.types[this_operand] = inoutportreg;
7377 if (i386_index_check (operand_string) == 0)
7379 i.types[this_operand].bitfield.mem = 1;
7384 /* It's not a memory operand; argh! */
7385 as_bad (_("invalid char %s beginning operand %d `%s'"),
7386 output_invalid (*op_string),
7391 return 1; /* Normal return. */
7394 /* md_estimate_size_before_relax()
7396 Called just before relax() for rs_machine_dependent frags. The x86
7397 assembler uses these frags to handle variable size jump
7400 Any symbol that is now undefined will not become defined.
7401 Return the correct fr_subtype in the frag.
7402 Return the initial "guess for variable size of frag" to caller.
7403 The guess is actually the growth beyond the fixed part. Whatever
7404 we do to grow the fixed or variable part contributes to our
7408 md_estimate_size_before_relax (fragP, segment)
7412 /* We've already got fragP->fr_subtype right; all we have to do is
7413 check for un-relaxable symbols. On an ELF system, we can't relax
7414 an externally visible symbol, because it may be overridden by a
7416 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
7417 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7419 && (S_IS_EXTERNAL (fragP->fr_symbol)
7420 || S_IS_WEAK (fragP->fr_symbol)
7421 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7422 & BSF_GNU_INDIRECT_FUNCTION))))
7424 #if defined (OBJ_COFF) && defined (TE_PE)
7425 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
7426 && S_IS_WEAK (fragP->fr_symbol))
7430 /* Symbol is undefined in this segment, or we need to keep a
7431 reloc so that weak symbols can be overridden. */
7432 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
7433 enum bfd_reloc_code_real reloc_type;
7434 unsigned char *opcode;
7437 if (fragP->fr_var != NO_RELOC)
7438 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
7440 reloc_type = BFD_RELOC_16_PCREL;
7442 reloc_type = BFD_RELOC_32_PCREL;
7444 old_fr_fix = fragP->fr_fix;
7445 opcode = (unsigned char *) fragP->fr_opcode;
7447 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
7450 /* Make jmp (0xeb) a (d)word displacement jump. */
7452 fragP->fr_fix += size;
7453 fix_new (fragP, old_fr_fix, size,
7455 fragP->fr_offset, 1,
7461 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
7463 /* Negate the condition, and branch past an
7464 unconditional jump. */
7467 /* Insert an unconditional jump. */
7469 /* We added two extra opcode bytes, and have a two byte
7471 fragP->fr_fix += 2 + 2;
7472 fix_new (fragP, old_fr_fix + 2, 2,
7474 fragP->fr_offset, 1,
7481 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7486 fixP = fix_new (fragP, old_fr_fix, 1,
7488 fragP->fr_offset, 1,
7490 fixP->fx_signed = 1;
7494 /* This changes the byte-displacement jump 0x7N
7495 to the (d)word-displacement jump 0x0f,0x8N. */
7496 opcode[1] = opcode[0] + 0x10;
7497 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7498 /* We've added an opcode byte. */
7499 fragP->fr_fix += 1 + size;
7500 fix_new (fragP, old_fr_fix + 1, size,
7502 fragP->fr_offset, 1,
7507 BAD_CASE (fragP->fr_subtype);
7511 return fragP->fr_fix - old_fr_fix;
7514 /* Guess size depending on current relax state. Initially the relax
7515 state will correspond to a short jump and we return 1, because
7516 the variable part of the frag (the branch offset) is one byte
7517 long. However, we can relax a section more than once and in that
7518 case we must either set fr_subtype back to the unrelaxed state,
7519 or return the value for the appropriate branch. */
7520 return md_relax_table[fragP->fr_subtype].rlx_length;
7523 /* Called after relax() is finished.
7525 In: Address of frag.
7526 fr_type == rs_machine_dependent.
7527 fr_subtype is what the address relaxed to.
7529 Out: Any fixSs and constants are set up.
7530 Caller will turn frag into a ".space 0". */
7533 md_convert_frag (abfd, sec, fragP)
7534 bfd *abfd ATTRIBUTE_UNUSED;
7535 segT sec ATTRIBUTE_UNUSED;
7538 unsigned char *opcode;
7539 unsigned char *where_to_put_displacement = NULL;
7540 offsetT target_address;
7541 offsetT opcode_address;
7542 unsigned int extension = 0;
7543 offsetT displacement_from_opcode_start;
7545 opcode = (unsigned char *) fragP->fr_opcode;
7547 /* Address we want to reach in file space. */
7548 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
7550 /* Address opcode resides at in file space. */
7551 opcode_address = fragP->fr_address + fragP->fr_fix;
7553 /* Displacement from opcode start to fill into instruction. */
7554 displacement_from_opcode_start = target_address - opcode_address;
7556 if ((fragP->fr_subtype & BIG) == 0)
7558 /* Don't have to change opcode. */
7559 extension = 1; /* 1 opcode + 1 displacement */
7560 where_to_put_displacement = &opcode[1];
7564 if (no_cond_jump_promotion
7565 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
7566 as_warn_where (fragP->fr_file, fragP->fr_line,
7567 _("long jump required"));
7569 switch (fragP->fr_subtype)
7571 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7572 extension = 4; /* 1 opcode + 4 displacement */
7574 where_to_put_displacement = &opcode[1];
7577 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7578 extension = 2; /* 1 opcode + 2 displacement */
7580 where_to_put_displacement = &opcode[1];
7583 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7584 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7585 extension = 5; /* 2 opcode + 4 displacement */
7586 opcode[1] = opcode[0] + 0x10;
7587 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7588 where_to_put_displacement = &opcode[2];
7591 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7592 extension = 3; /* 2 opcode + 2 displacement */
7593 opcode[1] = opcode[0] + 0x10;
7594 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7595 where_to_put_displacement = &opcode[2];
7598 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7603 where_to_put_displacement = &opcode[3];
7607 BAD_CASE (fragP->fr_subtype);
7612 /* If size if less then four we are sure that the operand fits,
7613 but if it's 4, then it could be that the displacement is larger
7615 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7617 && ((addressT) (displacement_from_opcode_start - extension
7618 + ((addressT) 1 << 31))
7619 > (((addressT) 2 << 31) - 1)))
7621 as_bad_where (fragP->fr_file, fragP->fr_line,
7622 _("jump target out of range"));
7623 /* Make us emit 0. */
7624 displacement_from_opcode_start = extension;
7626 /* Now put displacement after opcode. */
7627 md_number_to_chars ((char *) where_to_put_displacement,
7628 (valueT) (displacement_from_opcode_start - extension),
7629 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
7630 fragP->fr_fix += extension;
7633 /* Apply a fixup (fixS) to segment data, once it has been determined
7634 by our caller that we have all the info we need to fix it up.
7636 On the 386, immediates, displacements, and data pointers are all in
7637 the same (little-endian) format, so we don't need to care about which
7641 md_apply_fix (fixP, valP, seg)
7642 /* The fix we're to put in. */
7644 /* Pointer to the value of the bits. */
7646 /* Segment fix is from. */
7647 segT seg ATTRIBUTE_UNUSED;
7649 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
7650 valueT value = *valP;
7652 #if !defined (TE_Mach)
7655 switch (fixP->fx_r_type)
7661 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7664 case BFD_RELOC_X86_64_32S:
7665 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7668 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7671 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7676 if (fixP->fx_addsy != NULL
7677 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
7678 || fixP->fx_r_type == BFD_RELOC_64_PCREL
7679 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7680 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7681 && !use_rela_relocations)
7683 /* This is a hack. There should be a better way to handle this.
7684 This covers for the fact that bfd_install_relocation will
7685 subtract the current location (for partial_inplace, PC relative
7686 relocations); see more below. */
7690 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7693 value += fixP->fx_where + fixP->fx_frag->fr_address;
7695 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7698 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
7701 || (symbol_section_p (fixP->fx_addsy)
7702 && sym_seg != absolute_section))
7703 && !generic_force_reloc (fixP))
7705 /* Yes, we add the values in twice. This is because
7706 bfd_install_relocation subtracts them out again. I think
7707 bfd_install_relocation is broken, but I don't dare change
7709 value += fixP->fx_where + fixP->fx_frag->fr_address;
7713 #if defined (OBJ_COFF) && defined (TE_PE)
7714 /* For some reason, the PE format does not store a
7715 section address offset for a PC relative symbol. */
7716 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7717 || S_IS_WEAK (fixP->fx_addsy))
7718 value += md_pcrel_from (fixP);
7721 #if defined (OBJ_COFF) && defined (TE_PE)
7722 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7724 value -= S_GET_VALUE (fixP->fx_addsy);
7728 /* Fix a few things - the dynamic linker expects certain values here,
7729 and we must not disappoint it. */
7730 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7731 if (IS_ELF && fixP->fx_addsy)
7732 switch (fixP->fx_r_type)
7734 case BFD_RELOC_386_PLT32:
7735 case BFD_RELOC_X86_64_PLT32:
7736 /* Make the jump instruction point to the address of the operand. At
7737 runtime we merely add the offset to the actual PLT entry. */
7741 case BFD_RELOC_386_TLS_GD:
7742 case BFD_RELOC_386_TLS_LDM:
7743 case BFD_RELOC_386_TLS_IE_32:
7744 case BFD_RELOC_386_TLS_IE:
7745 case BFD_RELOC_386_TLS_GOTIE:
7746 case BFD_RELOC_386_TLS_GOTDESC:
7747 case BFD_RELOC_X86_64_TLSGD:
7748 case BFD_RELOC_X86_64_TLSLD:
7749 case BFD_RELOC_X86_64_GOTTPOFF:
7750 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7751 value = 0; /* Fully resolved at runtime. No addend. */
7753 case BFD_RELOC_386_TLS_LE:
7754 case BFD_RELOC_386_TLS_LDO_32:
7755 case BFD_RELOC_386_TLS_LE_32:
7756 case BFD_RELOC_X86_64_DTPOFF32:
7757 case BFD_RELOC_X86_64_DTPOFF64:
7758 case BFD_RELOC_X86_64_TPOFF32:
7759 case BFD_RELOC_X86_64_TPOFF64:
7760 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7763 case BFD_RELOC_386_TLS_DESC_CALL:
7764 case BFD_RELOC_X86_64_TLSDESC_CALL:
7765 value = 0; /* Fully resolved at runtime. No addend. */
7766 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7770 case BFD_RELOC_386_GOT32:
7771 case BFD_RELOC_X86_64_GOT32:
7772 value = 0; /* Fully resolved at runtime. No addend. */
7775 case BFD_RELOC_VTABLE_INHERIT:
7776 case BFD_RELOC_VTABLE_ENTRY:
7783 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7785 #endif /* !defined (TE_Mach) */
7787 /* Are we finished with this relocation now? */
7788 if (fixP->fx_addsy == NULL)
7790 #if defined (OBJ_COFF) && defined (TE_PE)
7791 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7794 /* Remember value for tc_gen_reloc. */
7795 fixP->fx_addnumber = value;
7796 /* Clear out the frag for now. */
7800 else if (use_rela_relocations)
7802 fixP->fx_no_overflow = 1;
7803 /* Remember value for tc_gen_reloc. */
7804 fixP->fx_addnumber = value;
7808 md_number_to_chars (p, value, fixP->fx_size);
7812 md_atof (int type, char *litP, int *sizeP)
7814 /* This outputs the LITTLENUMs in REVERSE order;
7815 in accord with the bigendian 386. */
7816 return ieee_md_atof (type, litP, sizeP, FALSE);
7819 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7822 output_invalid (int c)
7825 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7828 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7829 "(0x%x)", (unsigned char) c);
7830 return output_invalid_buf;
7833 /* REG_STRING starts *before* REGISTER_PREFIX. */
7835 static const reg_entry *
7836 parse_real_register (char *reg_string, char **end_op)
7838 char *s = reg_string;
7840 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7843 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7844 if (*s == REGISTER_PREFIX)
7847 if (is_space_char (*s))
7851 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7853 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7854 return (const reg_entry *) NULL;
7858 /* For naked regs, make sure that we are not dealing with an identifier.
7859 This prevents confusing an identifier like `eax_var' with register
7861 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7862 return (const reg_entry *) NULL;
7866 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7868 /* Handle floating point regs, allowing spaces in the (i) part. */
7869 if (r == i386_regtab /* %st is first entry of table */)
7871 if (is_space_char (*s))
7876 if (is_space_char (*s))
7878 if (*s >= '0' && *s <= '7')
7882 if (is_space_char (*s))
7887 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
7892 /* We have "%st(" then garbage. */
7893 return (const reg_entry *) NULL;
7897 if (r == NULL || allow_pseudo_reg)
7900 if (operand_type_all_zero (&r->reg_type))
7901 return (const reg_entry *) NULL;
7903 if ((r->reg_type.bitfield.reg32
7904 || r->reg_type.bitfield.sreg3
7905 || r->reg_type.bitfield.control
7906 || r->reg_type.bitfield.debug
7907 || r->reg_type.bitfield.test)
7908 && !cpu_arch_flags.bitfield.cpui386)
7909 return (const reg_entry *) NULL;
7911 if (r->reg_type.bitfield.floatreg
7912 && !cpu_arch_flags.bitfield.cpu8087
7913 && !cpu_arch_flags.bitfield.cpu287
7914 && !cpu_arch_flags.bitfield.cpu387)
7915 return (const reg_entry *) NULL;
7917 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7918 return (const reg_entry *) NULL;
7920 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7921 return (const reg_entry *) NULL;
7923 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7924 return (const reg_entry *) NULL;
7926 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7927 if (!allow_index_reg
7928 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7929 return (const reg_entry *) NULL;
7931 if (((r->reg_flags & (RegRex64 | RegRex))
7932 || r->reg_type.bitfield.reg64)
7933 && (!cpu_arch_flags.bitfield.cpulm
7934 || !operand_type_equal (&r->reg_type, &control))
7935 && flag_code != CODE_64BIT)
7936 return (const reg_entry *) NULL;
7938 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7939 return (const reg_entry *) NULL;
7944 /* REG_STRING starts *before* REGISTER_PREFIX. */
7946 static const reg_entry *
7947 parse_register (char *reg_string, char **end_op)
7951 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7952 r = parse_real_register (reg_string, end_op);
7957 char *save = input_line_pointer;
7961 input_line_pointer = reg_string;
7962 c = get_symbol_end ();
7963 symbolP = symbol_find (reg_string);
7964 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7966 const expressionS *e = symbol_get_value_expression (symbolP);
7968 know (i386_is_register (e));
7969 know (e->X_add_number >= 0
7970 && (valueT) e->X_add_number < i386_regtab_size);
7971 r = i386_regtab + e->X_add_number;
7972 *end_op = input_line_pointer;
7974 *input_line_pointer = c;
7975 input_line_pointer = save;
7981 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7984 char *end = input_line_pointer;
7987 r = parse_register (name, &input_line_pointer);
7988 if (r && end <= input_line_pointer)
7990 *nextcharP = *input_line_pointer;
7991 *input_line_pointer = 0;
7992 e->X_op = O_register;
7993 e->X_add_number = r - i386_regtab;
7996 input_line_pointer = end;
7998 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
8002 md_operand (expressionS *e)
8007 switch (*input_line_pointer)
8009 case REGISTER_PREFIX:
8010 r = parse_real_register (input_line_pointer, &end);
8013 e->X_op = O_register;
8014 e->X_add_number = r - i386_regtab;
8015 input_line_pointer = end;
8020 gas_assert (intel_syntax);
8021 end = input_line_pointer++;
8023 if (*input_line_pointer == ']')
8025 ++input_line_pointer;
8026 e->X_op_symbol = make_expr_symbol (e);
8027 e->X_add_symbol = NULL;
8028 e->X_add_number = 0;
8034 input_line_pointer = end;
8041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8042 const char *md_shortopts = "kVQ:sqn";
8044 const char *md_shortopts = "qn";
8047 #define OPTION_32 (OPTION_MD_BASE + 0)
8048 #define OPTION_64 (OPTION_MD_BASE + 1)
8049 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8050 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8051 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8052 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8053 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8054 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8055 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8056 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8057 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8058 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8059 #define OPTION_MAVXSCALAR (OPTION_MSSE_CHECK + 11)
8061 struct option md_longopts[] =
8063 {"32", no_argument, NULL, OPTION_32},
8064 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8065 || defined (TE_PE) || defined (TE_PEP))
8066 {"64", no_argument, NULL, OPTION_64},
8068 {"divide", no_argument, NULL, OPTION_DIVIDE},
8069 {"march", required_argument, NULL, OPTION_MARCH},
8070 {"mtune", required_argument, NULL, OPTION_MTUNE},
8071 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8072 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8073 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8074 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8075 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
8076 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
8077 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
8078 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
8079 {NULL, no_argument, NULL, 0}
8081 size_t md_longopts_size = sizeof (md_longopts);
8084 md_parse_option (int c, char *arg)
8092 optimize_align_code = 0;
8099 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8100 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8101 should be emitted or not. FIXME: Not implemented. */
8105 /* -V: SVR4 argument to print version ID. */
8107 print_version_id ();
8110 /* -k: Ignore for FreeBSD compatibility. */
8115 /* -s: On i386 Solaris, this tells the native assembler to use
8116 .stab instead of .stab.excl. We always use .stab anyhow. */
8119 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8120 || defined (TE_PE) || defined (TE_PEP))
8123 const char **list, **l;
8125 list = bfd_target_list ();
8126 for (l = list; *l != NULL; l++)
8127 if (CONST_STRNEQ (*l, "elf64-x86-64")
8128 || strcmp (*l, "coff-x86-64") == 0
8129 || strcmp (*l, "pe-x86-64") == 0
8130 || strcmp (*l, "pei-x86-64") == 0)
8132 default_arch = "x86_64";
8136 as_fatal (_("No compiled in support for x86_64"));
8143 default_arch = "i386";
8147 #ifdef SVR4_COMMENT_CHARS
8152 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8154 for (s = i386_comment_chars; *s != '\0'; s++)
8158 i386_comment_chars = n;
8164 arch = xstrdup (arg);
8168 as_fatal (_("Invalid -march= option: `%s'"), arg);
8169 next = strchr (arch, '+');
8172 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8174 if (strcmp (arch, cpu_arch [j].name) == 0)
8177 cpu_arch_name = cpu_arch[j].name;
8178 cpu_sub_arch_name = NULL;
8179 cpu_arch_flags = cpu_arch[j].flags;
8180 cpu_arch_isa = cpu_arch[j].type;
8181 cpu_arch_isa_flags = cpu_arch[j].flags;
8182 if (!cpu_arch_tune_set)
8184 cpu_arch_tune = cpu_arch_isa;
8185 cpu_arch_tune_flags = cpu_arch_isa_flags;
8189 else if (*cpu_arch [j].name == '.'
8190 && strcmp (arch, cpu_arch [j].name + 1) == 0)
8192 /* ISA entension. */
8193 i386_cpu_flags flags;
8195 if (strncmp (arch, "no", 2))
8196 flags = cpu_flags_or (cpu_arch_flags,
8199 flags = cpu_flags_and_not (cpu_arch_flags,
8201 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
8203 if (cpu_sub_arch_name)
8205 char *name = cpu_sub_arch_name;
8206 cpu_sub_arch_name = concat (name,
8208 (const char *) NULL);
8212 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
8213 cpu_arch_flags = flags;
8219 if (j >= ARRAY_SIZE (cpu_arch))
8220 as_fatal (_("Invalid -march= option: `%s'"), arg);
8224 while (next != NULL );
8229 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8230 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8232 if (strcmp (arg, cpu_arch [j].name) == 0)
8234 cpu_arch_tune_set = 1;
8235 cpu_arch_tune = cpu_arch [j].type;
8236 cpu_arch_tune_flags = cpu_arch[j].flags;
8240 if (j >= ARRAY_SIZE (cpu_arch))
8241 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8244 case OPTION_MMNEMONIC:
8245 if (strcasecmp (arg, "att") == 0)
8247 else if (strcasecmp (arg, "intel") == 0)
8250 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8253 case OPTION_MSYNTAX:
8254 if (strcasecmp (arg, "att") == 0)
8256 else if (strcasecmp (arg, "intel") == 0)
8259 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8262 case OPTION_MINDEX_REG:
8263 allow_index_reg = 1;
8266 case OPTION_MNAKED_REG:
8267 allow_naked_reg = 1;
8270 case OPTION_MOLD_GCC:
8274 case OPTION_MSSE2AVX:
8278 case OPTION_MSSE_CHECK:
8279 if (strcasecmp (arg, "error") == 0)
8280 sse_check = sse_check_error;
8281 else if (strcasecmp (arg, "warning") == 0)
8282 sse_check = sse_check_warning;
8283 else if (strcasecmp (arg, "none") == 0)
8284 sse_check = sse_check_none;
8286 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8289 case OPTION_MAVXSCALAR:
8290 if (strcasecmp (arg, "128") == 0)
8292 else if (strcasecmp (arg, "256") == 0)
8295 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8304 #define MESSAGE_TEMPLATE \
8308 show_arch (FILE *stream, int ext)
8310 static char message[] = MESSAGE_TEMPLATE;
8311 char *start = message + 27;
8313 int size = sizeof (MESSAGE_TEMPLATE);
8320 left = size - (start - message);
8321 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8323 /* Should it be skipped? */
8324 if (cpu_arch [j].skip)
8327 name = cpu_arch [j].name;
8328 len = cpu_arch [j].len;
8331 /* It is an extension. Skip if we aren't asked to show it. */
8342 /* It is an processor. Skip if we show only extension. */
8346 /* Reserve 2 spaces for ", " or ",\0" */
8349 /* Check if there is any room. */
8357 p = mempcpy (p, name, len);
8361 /* Output the current message now and start a new one. */
8364 fprintf (stream, "%s\n", message);
8366 left = size - (start - message) - len - 2;
8368 gas_assert (left >= 0);
8370 p = mempcpy (p, name, len);
8375 fprintf (stream, "%s\n", message);
8379 md_show_usage (FILE *stream)
8381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8382 fprintf (stream, _("\
8384 -V print assembler version number\n\
8387 fprintf (stream, _("\
8388 -n Do not optimize code alignment\n\
8389 -q quieten some warnings\n"));
8390 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8391 fprintf (stream, _("\
8394 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8395 || defined (TE_PE) || defined (TE_PEP))
8396 fprintf (stream, _("\
8397 --32/--64 generate 32bit/64bit code\n"));
8399 #ifdef SVR4_COMMENT_CHARS
8400 fprintf (stream, _("\
8401 --divide do not treat `/' as a comment character\n"));
8403 fprintf (stream, _("\
8404 --divide ignored\n"));
8406 fprintf (stream, _("\
8407 -march=CPU[,+EXTENSION...]\n\
8408 generate code for CPU and EXTENSION, CPU is one of:\n"));
8409 show_arch (stream, 0);
8410 fprintf (stream, _("\
8411 EXTENSION is combination of:\n"));
8412 show_arch (stream, 1);
8413 fprintf (stream, _("\
8414 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8415 show_arch (stream, 0);
8416 fprintf (stream, _("\
8417 -msse2avx encode SSE instructions with VEX prefix\n"));
8418 fprintf (stream, _("\
8419 -msse-check=[none|error|warning]\n\
8420 check SSE instructions\n"));
8421 fprintf (stream, _("\
8422 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8424 fprintf (stream, _("\
8425 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8426 fprintf (stream, _("\
8427 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8428 fprintf (stream, _("\
8429 -mindex-reg support pseudo index registers\n"));
8430 fprintf (stream, _("\
8431 -mnaked-reg don't require `%%' prefix for registers\n"));
8432 fprintf (stream, _("\
8433 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8436 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8437 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8438 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8440 /* Pick the target format to use. */
8443 i386_target_format (void)
8445 if (!strcmp (default_arch, "x86_64"))
8447 set_code_flag (CODE_64BIT);
8448 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8450 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8451 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8452 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8453 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8454 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8455 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8456 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
8457 cpu_arch_isa_flags.bitfield.cpummx= 1;
8458 cpu_arch_isa_flags.bitfield.cpusse = 1;
8459 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8460 cpu_arch_isa_flags.bitfield.cpulm = 1;
8462 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8464 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8465 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8466 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8467 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8468 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8469 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8470 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
8471 cpu_arch_tune_flags.bitfield.cpummx= 1;
8472 cpu_arch_tune_flags.bitfield.cpusse = 1;
8473 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8476 else if (!strcmp (default_arch, "i386"))
8478 set_code_flag (CODE_32BIT);
8479 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8481 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8482 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8483 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8485 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8487 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8488 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8489 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8493 as_fatal (_("Unknown architecture"));
8494 switch (OUTPUT_FLAVOR)
8496 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8497 case bfd_target_aout_flavour:
8498 return AOUT_TARGET_FORMAT;
8500 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8501 # if defined (TE_PE) || defined (TE_PEP)
8502 case bfd_target_coff_flavour:
8503 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8504 # elif defined (TE_GO32)
8505 case bfd_target_coff_flavour:
8508 case bfd_target_coff_flavour:
8512 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8513 case bfd_target_elf_flavour:
8515 if (flag_code == CODE_64BIT)
8518 use_rela_relocations = 1;
8520 if (cpu_arch_isa == PROCESSOR_L1OM)
8522 if (flag_code != CODE_64BIT)
8523 as_fatal (_("Intel L1OM is 64bit only"));
8524 return ELF_TARGET_L1OM_FORMAT;
8527 return (flag_code == CODE_64BIT
8528 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
8531 #if defined (OBJ_MACH_O)
8532 case bfd_target_mach_o_flavour:
8533 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
8541 #endif /* OBJ_MAYBE_ more than one */
8543 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8545 i386_elf_emit_arch_note (void)
8547 if (IS_ELF && cpu_arch_name != NULL)
8550 asection *seg = now_seg;
8551 subsegT subseg = now_subseg;
8552 Elf_Internal_Note i_note;
8553 Elf_External_Note e_note;
8554 asection *note_secp;
8557 /* Create the .note section. */
8558 note_secp = subseg_new (".note", 0);
8559 bfd_set_section_flags (stdoutput,
8561 SEC_HAS_CONTENTS | SEC_READONLY);
8563 /* Process the arch string. */
8564 len = strlen (cpu_arch_name);
8566 i_note.namesz = len + 1;
8568 i_note.type = NT_ARCH;
8569 p = frag_more (sizeof (e_note.namesz));
8570 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8571 p = frag_more (sizeof (e_note.descsz));
8572 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8573 p = frag_more (sizeof (e_note.type));
8574 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8575 p = frag_more (len + 1);
8576 strcpy (p, cpu_arch_name);
8578 frag_align (2, 0, 0);
8580 subseg_set (seg, subseg);
8586 md_undefined_symbol (name)
8589 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8590 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8591 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8592 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
8596 if (symbol_find (name))
8597 as_bad (_("GOT already in symbol table"));
8598 GOT_symbol = symbol_new (name, undefined_section,
8599 (valueT) 0, &zero_address_frag);
8606 /* Round up a section size to the appropriate boundary. */
8609 md_section_align (segment, size)
8610 segT segment ATTRIBUTE_UNUSED;
8613 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8614 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8616 /* For a.out, force the section size to be aligned. If we don't do
8617 this, BFD will align it for us, but it will not write out the
8618 final bytes of the section. This may be a bug in BFD, but it is
8619 easier to fix it here since that is how the other a.out targets
8623 align = bfd_get_section_alignment (stdoutput, segment);
8624 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8631 /* On the i386, PC-relative offsets are relative to the start of the
8632 next instruction. That is, the address of the offset, plus its
8633 size, since the offset is always the last part of the insn. */
8636 md_pcrel_from (fixS *fixP)
8638 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8644 s_bss (int ignore ATTRIBUTE_UNUSED)
8648 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8650 obj_elf_section_change_hook ();
8652 temp = get_absolute_expression ();
8653 subseg_set (bss_section, (subsegT) temp);
8654 demand_empty_rest_of_line ();
8660 i386_validate_fix (fixS *fixp)
8662 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8664 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8668 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8673 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8675 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
8682 tc_gen_reloc (section, fixp)
8683 asection *section ATTRIBUTE_UNUSED;
8687 bfd_reloc_code_real_type code;
8689 switch (fixp->fx_r_type)
8691 case BFD_RELOC_X86_64_PLT32:
8692 case BFD_RELOC_X86_64_GOT32:
8693 case BFD_RELOC_X86_64_GOTPCREL:
8694 case BFD_RELOC_386_PLT32:
8695 case BFD_RELOC_386_GOT32:
8696 case BFD_RELOC_386_GOTOFF:
8697 case BFD_RELOC_386_GOTPC:
8698 case BFD_RELOC_386_TLS_GD:
8699 case BFD_RELOC_386_TLS_LDM:
8700 case BFD_RELOC_386_TLS_LDO_32:
8701 case BFD_RELOC_386_TLS_IE_32:
8702 case BFD_RELOC_386_TLS_IE:
8703 case BFD_RELOC_386_TLS_GOTIE:
8704 case BFD_RELOC_386_TLS_LE_32:
8705 case BFD_RELOC_386_TLS_LE:
8706 case BFD_RELOC_386_TLS_GOTDESC:
8707 case BFD_RELOC_386_TLS_DESC_CALL:
8708 case BFD_RELOC_X86_64_TLSGD:
8709 case BFD_RELOC_X86_64_TLSLD:
8710 case BFD_RELOC_X86_64_DTPOFF32:
8711 case BFD_RELOC_X86_64_DTPOFF64:
8712 case BFD_RELOC_X86_64_GOTTPOFF:
8713 case BFD_RELOC_X86_64_TPOFF32:
8714 case BFD_RELOC_X86_64_TPOFF64:
8715 case BFD_RELOC_X86_64_GOTOFF64:
8716 case BFD_RELOC_X86_64_GOTPC32:
8717 case BFD_RELOC_X86_64_GOT64:
8718 case BFD_RELOC_X86_64_GOTPCREL64:
8719 case BFD_RELOC_X86_64_GOTPC64:
8720 case BFD_RELOC_X86_64_GOTPLT64:
8721 case BFD_RELOC_X86_64_PLTOFF64:
8722 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8723 case BFD_RELOC_X86_64_TLSDESC_CALL:
8725 case BFD_RELOC_VTABLE_ENTRY:
8726 case BFD_RELOC_VTABLE_INHERIT:
8728 case BFD_RELOC_32_SECREL:
8730 code = fixp->fx_r_type;
8732 case BFD_RELOC_X86_64_32S:
8733 if (!fixp->fx_pcrel)
8735 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8736 code = fixp->fx_r_type;
8742 switch (fixp->fx_size)
8745 as_bad_where (fixp->fx_file, fixp->fx_line,
8746 _("can not do %d byte pc-relative relocation"),
8748 code = BFD_RELOC_32_PCREL;
8750 case 1: code = BFD_RELOC_8_PCREL; break;
8751 case 2: code = BFD_RELOC_16_PCREL; break;
8752 case 4: code = BFD_RELOC_32_PCREL; break;
8754 case 8: code = BFD_RELOC_64_PCREL; break;
8760 switch (fixp->fx_size)
8763 as_bad_where (fixp->fx_file, fixp->fx_line,
8764 _("can not do %d byte relocation"),
8766 code = BFD_RELOC_32;
8768 case 1: code = BFD_RELOC_8; break;
8769 case 2: code = BFD_RELOC_16; break;
8770 case 4: code = BFD_RELOC_32; break;
8772 case 8: code = BFD_RELOC_64; break;
8779 if ((code == BFD_RELOC_32
8780 || code == BFD_RELOC_32_PCREL
8781 || code == BFD_RELOC_X86_64_32S)
8783 && fixp->fx_addsy == GOT_symbol)
8786 code = BFD_RELOC_386_GOTPC;
8788 code = BFD_RELOC_X86_64_GOTPC32;
8790 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8792 && fixp->fx_addsy == GOT_symbol)
8794 code = BFD_RELOC_X86_64_GOTPC64;
8797 rel = (arelent *) xmalloc (sizeof (arelent));
8798 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8799 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8801 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
8803 if (!use_rela_relocations)
8805 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8806 vtable entry to be used in the relocation's section offset. */
8807 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8808 rel->address = fixp->fx_offset;
8809 #if defined (OBJ_COFF) && defined (TE_PE)
8810 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8811 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8816 /* Use the rela in 64bit mode. */
8819 if (!fixp->fx_pcrel)
8820 rel->addend = fixp->fx_offset;
8824 case BFD_RELOC_X86_64_PLT32:
8825 case BFD_RELOC_X86_64_GOT32:
8826 case BFD_RELOC_X86_64_GOTPCREL:
8827 case BFD_RELOC_X86_64_TLSGD:
8828 case BFD_RELOC_X86_64_TLSLD:
8829 case BFD_RELOC_X86_64_GOTTPOFF:
8830 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8831 case BFD_RELOC_X86_64_TLSDESC_CALL:
8832 rel->addend = fixp->fx_offset - fixp->fx_size;
8835 rel->addend = (section->vma
8837 + fixp->fx_addnumber
8838 + md_pcrel_from (fixp));
8843 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8844 if (rel->howto == NULL)
8846 as_bad_where (fixp->fx_file, fixp->fx_line,
8847 _("cannot represent relocation type %s"),
8848 bfd_get_reloc_code_name (code));
8849 /* Set howto to a garbage value so that we can keep going. */
8850 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8851 gas_assert (rel->howto != NULL);
8857 #include "tc-i386-intel.c"
8860 tc_x86_parse_to_dw2regnum (expressionS *exp)
8862 int saved_naked_reg;
8863 char saved_register_dot;
8865 saved_naked_reg = allow_naked_reg;
8866 allow_naked_reg = 1;
8867 saved_register_dot = register_chars['.'];
8868 register_chars['.'] = '.';
8869 allow_pseudo_reg = 1;
8870 expression_and_evaluate (exp);
8871 allow_pseudo_reg = 0;
8872 register_chars['.'] = saved_register_dot;
8873 allow_naked_reg = saved_naked_reg;
8875 if (i386_is_register (exp) && exp->X_add_number >= 0)
8877 if ((addressT) exp->X_add_number < i386_regtab_size)
8879 exp->X_op = O_constant;
8880 exp->X_add_number = i386_regtab[exp->X_add_number]
8881 .dw2_regnum[flag_code >> 1];
8884 exp->X_op = O_illegal;
8889 tc_x86_frame_initial_instructions (void)
8891 static unsigned int sp_regno[2];
8893 if (!sp_regno[flag_code >> 1])
8895 char *saved_input = input_line_pointer;
8896 char sp[][4] = {"esp", "rsp"};
8899 input_line_pointer = sp[flag_code >> 1];
8900 tc_x86_parse_to_dw2regnum (&exp);
8901 gas_assert (exp.X_op == O_constant);
8902 sp_regno[flag_code >> 1] = exp.X_add_number;
8903 input_line_pointer = saved_input;
8906 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
8907 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8911 i386_elf_section_type (const char *str, size_t len)
8913 if (flag_code == CODE_64BIT
8914 && len == sizeof ("unwind") - 1
8915 && strncmp (str, "unwind", 6) == 0)
8916 return SHT_X86_64_UNWIND;
8923 i386_solaris_fix_up_eh_frame (segT sec)
8925 if (flag_code == CODE_64BIT)
8926 elf_section_type (sec) = SHT_X86_64_UNWIND;
8932 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8936 exp.X_op = O_secrel;
8937 exp.X_add_symbol = symbol;
8938 exp.X_add_number = 0;
8939 emit_expr (&exp, size);
8943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8944 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8947 x86_64_section_letter (int letter, char **ptr_msg)
8949 if (flag_code == CODE_64BIT)
8952 return SHF_X86_64_LARGE;
8954 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8957 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8962 x86_64_section_word (char *str, size_t len)
8964 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8965 return SHF_X86_64_LARGE;
8971 handle_large_common (int small ATTRIBUTE_UNUSED)
8973 if (flag_code != CODE_64BIT)
8975 s_comm_internal (0, elf_common_parse);
8976 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8980 static segT lbss_section;
8981 asection *saved_com_section_ptr = elf_com_section_ptr;
8982 asection *saved_bss_section = bss_section;
8984 if (lbss_section == NULL)
8986 flagword applicable;
8988 subsegT subseg = now_subseg;
8990 /* The .lbss section is for local .largecomm symbols. */
8991 lbss_section = subseg_new (".lbss", 0);
8992 applicable = bfd_applicable_section_flags (stdoutput);
8993 bfd_set_section_flags (stdoutput, lbss_section,
8994 applicable & SEC_ALLOC);
8995 seg_info (lbss_section)->bss = 1;
8997 subseg_set (seg, subseg);
9000 elf_com_section_ptr = &_bfd_elf_large_com_section;
9001 bss_section = lbss_section;
9003 s_comm_internal (0, elf_common_parse);
9005 elf_com_section_ptr = saved_com_section_ptr;
9006 bss_section = saved_bss_section;
9009 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */