1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
847 CPU_BTVER1_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
849 CPU_BTVER2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
867 CPU_SSSE3_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
869 CPU_SSE4_1_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
879 CPU_AVX512F_FLAGS, 0 },
880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
881 CPU_AVX512CD_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
883 CPU_AVX512ER_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
885 CPU_AVX512PF_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
887 CPU_AVX512DQ_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
889 CPU_AVX512BW_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
891 CPU_AVX512VL_FLAGS, 0 },
892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
895 CPU_VMFUNC_FLAGS, 0 },
896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
899 CPU_XSAVE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
901 CPU_XSAVEOPT_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
905 CPU_XSAVES_FLAGS, 0 },
906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
909 CPU_PCLMUL_FLAGS, 0 },
910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 1 },
912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
913 CPU_FSGSBASE_FLAGS, 0 },
914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
915 CPU_RDRND_FLAGS, 0 },
916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
929 CPU_MOVBE_FLAGS, 0 },
930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
935 CPU_LZCNT_FLAGS, 0 },
936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
941 CPU_INVPCID_FLAGS, 0 },
942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
943 CPU_CLFLUSH_FLAGS, 0 },
944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
947 CPU_SYSCALL_FLAGS, 0 },
948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
949 CPU_RDTSCP_FLAGS, 0 },
950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
951 CPU_3DNOW_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
953 CPU_3DNOWA_FLAGS, 0 },
954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
955 CPU_PADLOCK_FLAGS, 0 },
956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
961 CPU_SSE4A_FLAGS, 0 },
962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
971 CPU_RDSEED_FLAGS, 0 },
972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
973 CPU_PRFCHW_FLAGS, 0 },
974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
981 CPU_CLFLUSHOPT_FLAGS, 0 },
982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
983 CPU_PREFETCHWT1_FLAGS, 0 },
984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
989 CPU_AVX512IFMA_FLAGS, 0 },
990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
991 CPU_AVX512VBMI_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
993 CPU_AVX512_4FMAPS_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4VNNIW_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VBMI2_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VNNI_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_BITALG_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1005 CPU_CLZERO_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1007 CPU_MWAITX_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1009 CPU_OSPKE_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1011 CPU_RDPID_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1013 CPU_PTWRITE_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1017 CPU_SHSTK_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1019 CPU_GFNI_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1021 CPU_VAES_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1023 CPU_VPCLMULQDQ_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1025 CPU_WBNOINVD_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1027 CPU_PCONFIG_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1029 CPU_WAITPKG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1031 CPU_CLDEMOTE_FLAGS, 0 },
1034 static const noarch_entry cpu_noarch[] =
1036 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1037 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1038 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1039 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1040 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1041 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1042 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1043 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1044 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1048 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1049 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1065 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1066 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1070 /* Like s_lcomm_internal in gas/read.c but the alignment string
1071 is allowed to be optional. */
1074 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1081 && *input_line_pointer == ',')
1083 align = parse_align (needs_align - 1);
1085 if (align == (addressT) -1)
1100 bss_alloc (symbolP, size, align);
1105 pe_lcomm (int needs_align)
1107 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1111 const pseudo_typeS md_pseudo_table[] =
1113 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1114 {"align", s_align_bytes, 0},
1116 {"align", s_align_ptwo, 0},
1118 {"arch", set_cpu_arch, 0},
1122 {"lcomm", pe_lcomm, 1},
1124 {"ffloat", float_cons, 'f'},
1125 {"dfloat", float_cons, 'd'},
1126 {"tfloat", float_cons, 'x'},
1128 {"slong", signed_cons, 4},
1129 {"noopt", s_ignore, 0},
1130 {"optim", s_ignore, 0},
1131 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1132 {"code16", set_code_flag, CODE_16BIT},
1133 {"code32", set_code_flag, CODE_32BIT},
1135 {"code64", set_code_flag, CODE_64BIT},
1137 {"intel_syntax", set_intel_syntax, 1},
1138 {"att_syntax", set_intel_syntax, 0},
1139 {"intel_mnemonic", set_intel_mnemonic, 1},
1140 {"att_mnemonic", set_intel_mnemonic, 0},
1141 {"allow_index_reg", set_allow_index_reg, 1},
1142 {"disallow_index_reg", set_allow_index_reg, 0},
1143 {"sse_check", set_check, 0},
1144 {"operand_check", set_check, 1},
1145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1146 {"largecomm", handle_large_common, 0},
1148 {"file", dwarf2_directive_file, 0},
1149 {"loc", dwarf2_directive_loc, 0},
1150 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1153 {"secrel32", pe_directive_secrel, 0},
1158 /* For interface with expression (). */
1159 extern char *input_line_pointer;
1161 /* Hash table for instruction mnemonic lookup. */
1162 static struct hash_control *op_hash;
1164 /* Hash table for register lookup. */
1165 static struct hash_control *reg_hash;
1167 /* Various efficient no-op patterns for aligning code labels.
1168 Note: Don't try to assemble the instructions in the comments.
1169 0L and 0w are not legal. */
1170 static const unsigned char f32_1[] =
1172 static const unsigned char f32_2[] =
1173 {0x66,0x90}; /* xchg %ax,%ax */
1174 static const unsigned char f32_3[] =
1175 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1176 static const unsigned char f32_4[] =
1177 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1178 static const unsigned char f32_6[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1180 static const unsigned char f32_7[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1182 static const unsigned char f16_3[] =
1183 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1184 static const unsigned char f16_4[] =
1185 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1186 static const unsigned char jump_disp8[] =
1187 {0xeb}; /* jmp disp8 */
1188 static const unsigned char jump32_disp32[] =
1189 {0xe9}; /* jmp disp32 */
1190 static const unsigned char jump16_disp32[] =
1191 {0x66,0xe9}; /* jmp disp32 */
1192 /* 32-bit NOPs patterns. */
1193 static const unsigned char *const f32_patt[] = {
1194 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1196 /* 16-bit NOPs patterns. */
1197 static const unsigned char *const f16_patt[] = {
1198 f32_1, f32_2, f16_3, f16_4
1200 /* nopl (%[re]ax) */
1201 static const unsigned char alt_3[] =
1203 /* nopl 0(%[re]ax) */
1204 static const unsigned char alt_4[] =
1205 {0x0f,0x1f,0x40,0x00};
1206 /* nopl 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_5[] =
1208 {0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopw 0(%[re]ax,%[re]ax,1) */
1210 static const unsigned char alt_6[] =
1211 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1212 /* nopl 0L(%[re]ax) */
1213 static const unsigned char alt_7[] =
1214 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1215 /* nopl 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_8[] =
1217 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw 0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_9[] =
1220 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_10[] =
1223 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* data16 nopw %cs:0L(%eax,%eax,1) */
1225 static const unsigned char alt_11[] =
1226 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1227 /* 32-bit and 64-bit NOPs patterns. */
1228 static const unsigned char *const alt_patt[] = {
1229 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1230 alt_9, alt_10, alt_11
1233 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1234 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1237 i386_output_nops (char *where, const unsigned char *const *patt,
1238 int count, int max_single_nop_size)
1241 /* Place the longer NOP first. */
1244 const unsigned char *nops = patt[max_single_nop_size - 1];
1246 /* Use the smaller one if the requsted one isn't available. */
1249 max_single_nop_size--;
1250 nops = patt[max_single_nop_size - 1];
1253 last = count % max_single_nop_size;
1256 for (offset = 0; offset < count; offset += max_single_nop_size)
1257 memcpy (where + offset, nops, max_single_nop_size);
1261 nops = patt[last - 1];
1264 /* Use the smaller one plus one-byte NOP if the needed one
1267 nops = patt[last - 1];
1268 memcpy (where + offset, nops, last);
1269 where[offset + last] = *patt[0];
1272 memcpy (where + offset, nops, last);
1277 fits_in_imm7 (offsetT num)
1279 return (num & 0x7f) == num;
1283 fits_in_imm31 (offsetT num)
1285 return (num & 0x7fffffff) == num;
1288 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1289 single NOP instruction LIMIT. */
1292 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1294 const unsigned char *const *patt = NULL;
1295 int max_single_nop_size;
1296 /* Maximum number of NOPs before switching to jump over NOPs. */
1297 int max_number_of_nops;
1299 switch (fragP->fr_type)
1308 /* We need to decide which NOP sequence to use for 32bit and
1309 64bit. When -mtune= is used:
1311 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1312 PROCESSOR_GENERIC32, f32_patt will be used.
1313 2. For the rest, alt_patt will be used.
1315 When -mtune= isn't used, alt_patt will be used if
1316 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1319 When -march= or .arch is used, we can't use anything beyond
1320 cpu_arch_isa_flags. */
1322 if (flag_code == CODE_16BIT)
1325 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1326 /* Limit number of NOPs to 2 in 16-bit mode. */
1327 max_number_of_nops = 2;
1331 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1333 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1334 switch (cpu_arch_tune)
1336 case PROCESSOR_UNKNOWN:
1337 /* We use cpu_arch_isa_flags to check if we SHOULD
1338 optimize with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1344 case PROCESSOR_PENTIUM4:
1345 case PROCESSOR_NOCONA:
1346 case PROCESSOR_CORE:
1347 case PROCESSOR_CORE2:
1348 case PROCESSOR_COREI7:
1349 case PROCESSOR_L1OM:
1350 case PROCESSOR_K1OM:
1351 case PROCESSOR_GENERIC64:
1353 case PROCESSOR_ATHLON:
1355 case PROCESSOR_AMDFAM10:
1357 case PROCESSOR_ZNVER:
1361 case PROCESSOR_I386:
1362 case PROCESSOR_I486:
1363 case PROCESSOR_PENTIUM:
1364 case PROCESSOR_PENTIUMPRO:
1365 case PROCESSOR_IAMCU:
1366 case PROCESSOR_GENERIC32:
1373 switch (fragP->tc_frag_data.tune)
1375 case PROCESSOR_UNKNOWN:
1376 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1377 PROCESSOR_UNKNOWN. */
1381 case PROCESSOR_I386:
1382 case PROCESSOR_I486:
1383 case PROCESSOR_PENTIUM:
1384 case PROCESSOR_IAMCU:
1386 case PROCESSOR_ATHLON:
1388 case PROCESSOR_AMDFAM10:
1390 case PROCESSOR_ZNVER:
1392 case PROCESSOR_GENERIC32:
1393 /* We use cpu_arch_isa_flags to check if we CAN optimize
1395 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1400 case PROCESSOR_PENTIUMPRO:
1401 case PROCESSOR_PENTIUM4:
1402 case PROCESSOR_NOCONA:
1403 case PROCESSOR_CORE:
1404 case PROCESSOR_CORE2:
1405 case PROCESSOR_COREI7:
1406 case PROCESSOR_L1OM:
1407 case PROCESSOR_K1OM:
1408 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1413 case PROCESSOR_GENERIC64:
1419 if (patt == f32_patt)
1421 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1422 /* Limit number of NOPs to 2 for older processors. */
1423 max_number_of_nops = 2;
1427 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1428 /* Limit number of NOPs to 7 for newer processors. */
1429 max_number_of_nops = 7;
1434 limit = max_single_nop_size;
1436 if (fragP->fr_type == rs_fill_nop)
1438 /* Output NOPs for .nop directive. */
1439 if (limit > max_single_nop_size)
1441 as_bad_where (fragP->fr_file, fragP->fr_line,
1442 _("invalid single nop size: %d "
1443 "(expect within [0, %d])"),
1444 limit, max_single_nop_size);
1449 fragP->fr_var = count;
1451 if ((count / max_single_nop_size) > max_number_of_nops)
1453 /* Generate jump over NOPs. */
1454 offsetT disp = count - 2;
1455 if (fits_in_imm7 (disp))
1457 /* Use "jmp disp8" if possible. */
1459 where[0] = jump_disp8[0];
1465 unsigned int size_of_jump;
1467 if (flag_code == CODE_16BIT)
1469 where[0] = jump16_disp32[0];
1470 where[1] = jump16_disp32[1];
1475 where[0] = jump32_disp32[0];
1479 count -= size_of_jump + 4;
1480 if (!fits_in_imm31 (count))
1482 as_bad_where (fragP->fr_file, fragP->fr_line,
1483 _("jump over nop padding out of range"));
1487 md_number_to_chars (where + size_of_jump, count, 4);
1488 where += size_of_jump + 4;
1492 /* Generate multiple NOPs. */
1493 i386_output_nops (where, patt, count, limit);
1497 operand_type_all_zero (const union i386_operand_type *x)
1499 switch (ARRAY_SIZE(x->array))
1510 return !x->array[0];
1517 operand_type_set (union i386_operand_type *x, unsigned int v)
1519 switch (ARRAY_SIZE(x->array))
1537 operand_type_equal (const union i386_operand_type *x,
1538 const union i386_operand_type *y)
1540 switch (ARRAY_SIZE(x->array))
1543 if (x->array[2] != y->array[2])
1547 if (x->array[1] != y->array[1])
1551 return x->array[0] == y->array[0];
1559 cpu_flags_all_zero (const union i386_cpu_flags *x)
1561 switch (ARRAY_SIZE(x->array))
1576 return !x->array[0];
1583 cpu_flags_equal (const union i386_cpu_flags *x,
1584 const union i386_cpu_flags *y)
1586 switch (ARRAY_SIZE(x->array))
1589 if (x->array[3] != y->array[3])
1593 if (x->array[2] != y->array[2])
1597 if (x->array[1] != y->array[1])
1601 return x->array[0] == y->array[0];
1609 cpu_flags_check_cpu64 (i386_cpu_flags f)
1611 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1612 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1615 static INLINE i386_cpu_flags
1616 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1618 switch (ARRAY_SIZE (x.array))
1621 x.array [3] &= y.array [3];
1624 x.array [2] &= y.array [2];
1627 x.array [1] &= y.array [1];
1630 x.array [0] &= y.array [0];
1638 static INLINE i386_cpu_flags
1639 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1641 switch (ARRAY_SIZE (x.array))
1644 x.array [3] |= y.array [3];
1647 x.array [2] |= y.array [2];
1650 x.array [1] |= y.array [1];
1653 x.array [0] |= y.array [0];
1661 static INLINE i386_cpu_flags
1662 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1664 switch (ARRAY_SIZE (x.array))
1667 x.array [3] &= ~y.array [3];
1670 x.array [2] &= ~y.array [2];
1673 x.array [1] &= ~y.array [1];
1676 x.array [0] &= ~y.array [0];
1684 #define CPU_FLAGS_ARCH_MATCH 0x1
1685 #define CPU_FLAGS_64BIT_MATCH 0x2
1687 #define CPU_FLAGS_PERFECT_MATCH \
1688 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1690 /* Return CPU flags match bits. */
1693 cpu_flags_match (const insn_template *t)
1695 i386_cpu_flags x = t->cpu_flags;
1696 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1698 x.bitfield.cpu64 = 0;
1699 x.bitfield.cpuno64 = 0;
1701 if (cpu_flags_all_zero (&x))
1703 /* This instruction is available on all archs. */
1704 match |= CPU_FLAGS_ARCH_MATCH;
1708 /* This instruction is available only on some archs. */
1709 i386_cpu_flags cpu = cpu_arch_flags;
1711 /* AVX512VL is no standalone feature - match it and then strip it. */
1712 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1714 x.bitfield.cpuavx512vl = 0;
1716 cpu = cpu_flags_and (x, cpu);
1717 if (!cpu_flags_all_zero (&cpu))
1719 if (x.bitfield.cpuavx)
1721 /* We need to check a few extra flags with AVX. */
1722 if (cpu.bitfield.cpuavx
1723 && (!t->opcode_modifier.sse2avx || sse2avx)
1724 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1725 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1726 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1727 match |= CPU_FLAGS_ARCH_MATCH;
1729 else if (x.bitfield.cpuavx512f)
1731 /* We need to check a few extra flags with AVX512F. */
1732 if (cpu.bitfield.cpuavx512f
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1735 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1736 match |= CPU_FLAGS_ARCH_MATCH;
1739 match |= CPU_FLAGS_ARCH_MATCH;
1745 static INLINE i386_operand_type
1746 operand_type_and (i386_operand_type x, i386_operand_type y)
1748 switch (ARRAY_SIZE (x.array))
1751 x.array [2] &= y.array [2];
1754 x.array [1] &= y.array [1];
1757 x.array [0] &= y.array [0];
1765 static INLINE i386_operand_type
1766 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1768 switch (ARRAY_SIZE (x.array))
1771 x.array [2] &= ~y.array [2];
1774 x.array [1] &= ~y.array [1];
1777 x.array [0] &= ~y.array [0];
1785 static INLINE i386_operand_type
1786 operand_type_or (i386_operand_type x, i386_operand_type y)
1788 switch (ARRAY_SIZE (x.array))
1791 x.array [2] |= y.array [2];
1794 x.array [1] |= y.array [1];
1797 x.array [0] |= y.array [0];
1805 static INLINE i386_operand_type
1806 operand_type_xor (i386_operand_type x, i386_operand_type y)
1808 switch (ARRAY_SIZE (x.array))
1811 x.array [2] ^= y.array [2];
1814 x.array [1] ^= y.array [1];
1817 x.array [0] ^= y.array [0];
1825 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1826 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1827 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1828 static const i386_operand_type inoutportreg
1829 = OPERAND_TYPE_INOUTPORTREG;
1830 static const i386_operand_type reg16_inoutportreg
1831 = OPERAND_TYPE_REG16_INOUTPORTREG;
1832 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1833 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1834 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1835 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1836 static const i386_operand_type anydisp
1837 = OPERAND_TYPE_ANYDISP;
1838 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1839 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1840 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1841 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1842 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1843 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1844 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1845 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1846 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1847 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1848 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1849 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1860 operand_type_check (i386_operand_type t, enum operand_type c)
1865 return t.bitfield.reg;
1868 return (t.bitfield.imm8
1872 || t.bitfield.imm32s
1873 || t.bitfield.imm64);
1876 return (t.bitfield.disp8
1877 || t.bitfield.disp16
1878 || t.bitfield.disp32
1879 || t.bitfield.disp32s
1880 || t.bitfield.disp64);
1883 return (t.bitfield.disp8
1884 || t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s
1887 || t.bitfield.disp64
1888 || t.bitfield.baseindex);
1897 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1898 operand J for instruction template T. */
1901 match_reg_size (const insn_template *t, unsigned int j)
1903 return !((i.types[j].bitfield.byte
1904 && !t->operand_types[j].bitfield.byte)
1905 || (i.types[j].bitfield.word
1906 && !t->operand_types[j].bitfield.word)
1907 || (i.types[j].bitfield.dword
1908 && !t->operand_types[j].bitfield.dword)
1909 || (i.types[j].bitfield.qword
1910 && !t->operand_types[j].bitfield.qword)
1911 || (i.types[j].bitfield.tbyte
1912 && !t->operand_types[j].bitfield.tbyte));
1915 /* Return 1 if there is no conflict in SIMD register on
1916 operand J for instruction template T. */
1919 match_simd_size (const insn_template *t, unsigned int j)
1921 return !((i.types[j].bitfield.xmmword
1922 && !t->operand_types[j].bitfield.xmmword)
1923 || (i.types[j].bitfield.ymmword
1924 && !t->operand_types[j].bitfield.ymmword)
1925 || (i.types[j].bitfield.zmmword
1926 && !t->operand_types[j].bitfield.zmmword));
1929 /* Return 1 if there is no conflict in any size on operand J for
1930 instruction template T. */
1933 match_mem_size (const insn_template *t, unsigned int j)
1935 return (match_reg_size (t, j)
1936 && !((i.types[j].bitfield.unspecified
1938 && !t->operand_types[j].bitfield.unspecified)
1939 || (i.types[j].bitfield.fword
1940 && !t->operand_types[j].bitfield.fword)
1941 /* For scalar opcode templates to allow register and memory
1942 operands at the same time, some special casing is needed
1943 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1944 down-conversion vpmov*. */
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.byte
1948 || t->operand_types[j].bitfield.word
1949 || t->operand_types[j].bitfield.dword
1950 || t->operand_types[j].bitfield.qword))
1951 ? (i.types[j].bitfield.xmmword
1952 || i.types[j].bitfield.ymmword
1953 || i.types[j].bitfield.zmmword)
1954 : !match_simd_size(t, j))));
1957 /* Return 1 if there is no size conflict on any operands for
1958 instruction template T. */
1961 operand_size_match (const insn_template *t)
1966 /* Don't check jump instructions. */
1967 if (t->opcode_modifier.jump
1968 || t->opcode_modifier.jumpbyte
1969 || t->opcode_modifier.jumpdword
1970 || t->opcode_modifier.jumpintersegment)
1973 /* Check memory and accumulator operand size. */
1974 for (j = 0; j < i.operands; j++)
1976 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1977 && t->operand_types[j].bitfield.anysize)
1980 if (t->operand_types[j].bitfield.reg
1981 && !match_reg_size (t, j))
1987 if (t->operand_types[j].bitfield.regsimd
1988 && !match_simd_size (t, j))
1994 if (t->operand_types[j].bitfield.acc
1995 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2001 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2010 else if (!t->opcode_modifier.d)
2013 i.error = operand_size_mismatch;
2017 /* Check reverse. */
2018 gas_assert (i.operands == 2);
2021 for (j = 0; j < 2; j++)
2023 if ((t->operand_types[j].bitfield.reg
2024 || t->operand_types[j].bitfield.acc)
2025 && !match_reg_size (t, j ? 0 : 1))
2028 if (i.types[j].bitfield.mem
2029 && !match_mem_size (t, j ? 0 : 1))
2037 operand_type_match (i386_operand_type overlap,
2038 i386_operand_type given)
2040 i386_operand_type temp = overlap;
2042 temp.bitfield.jumpabsolute = 0;
2043 temp.bitfield.unspecified = 0;
2044 temp.bitfield.byte = 0;
2045 temp.bitfield.word = 0;
2046 temp.bitfield.dword = 0;
2047 temp.bitfield.fword = 0;
2048 temp.bitfield.qword = 0;
2049 temp.bitfield.tbyte = 0;
2050 temp.bitfield.xmmword = 0;
2051 temp.bitfield.ymmword = 0;
2052 temp.bitfield.zmmword = 0;
2053 if (operand_type_all_zero (&temp))
2056 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2057 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2061 i.error = operand_type_mismatch;
2065 /* If given types g0 and g1 are registers they must be of the same type
2066 unless the expected operand type register overlap is null.
2067 Memory operand size of certain SIMD instructions is also being checked
2071 operand_type_register_match (i386_operand_type g0,
2072 i386_operand_type t0,
2073 i386_operand_type g1,
2074 i386_operand_type t1)
2076 if (!g0.bitfield.reg
2077 && !g0.bitfield.regsimd
2078 && (!operand_type_check (g0, anymem)
2079 || g0.bitfield.unspecified
2080 || !t0.bitfield.regsimd))
2083 if (!g1.bitfield.reg
2084 && !g1.bitfield.regsimd
2085 && (!operand_type_check (g1, anymem)
2086 || g1.bitfield.unspecified
2087 || !t1.bitfield.regsimd))
2090 if (g0.bitfield.byte == g1.bitfield.byte
2091 && g0.bitfield.word == g1.bitfield.word
2092 && g0.bitfield.dword == g1.bitfield.dword
2093 && g0.bitfield.qword == g1.bitfield.qword
2094 && g0.bitfield.xmmword == g1.bitfield.xmmword
2095 && g0.bitfield.ymmword == g1.bitfield.ymmword
2096 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2099 if (!(t0.bitfield.byte & t1.bitfield.byte)
2100 && !(t0.bitfield.word & t1.bitfield.word)
2101 && !(t0.bitfield.dword & t1.bitfield.dword)
2102 && !(t0.bitfield.qword & t1.bitfield.qword)
2103 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2104 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2105 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2108 i.error = register_type_mismatch;
2113 static INLINE unsigned int
2114 register_number (const reg_entry *r)
2116 unsigned int nr = r->reg_num;
2118 if (r->reg_flags & RegRex)
2121 if (r->reg_flags & RegVRex)
2127 static INLINE unsigned int
2128 mode_from_disp_size (i386_operand_type t)
2130 if (t.bitfield.disp8)
2132 else if (t.bitfield.disp16
2133 || t.bitfield.disp32
2134 || t.bitfield.disp32s)
2141 fits_in_signed_byte (addressT num)
2143 return num + 0x80 <= 0xff;
2147 fits_in_unsigned_byte (addressT num)
2153 fits_in_unsigned_word (addressT num)
2155 return num <= 0xffff;
2159 fits_in_signed_word (addressT num)
2161 return num + 0x8000 <= 0xffff;
2165 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2170 return num + 0x80000000 <= 0xffffffff;
2172 } /* fits_in_signed_long() */
2175 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2180 return num <= 0xffffffff;
2182 } /* fits_in_unsigned_long() */
2185 fits_in_disp8 (offsetT num)
2187 int shift = i.memshift;
2193 mask = (1 << shift) - 1;
2195 /* Return 0 if NUM isn't properly aligned. */
2199 /* Check if NUM will fit in 8bit after shift. */
2200 return fits_in_signed_byte (num >> shift);
2204 fits_in_imm4 (offsetT num)
2206 return (num & 0xf) == num;
2209 static i386_operand_type
2210 smallest_imm_type (offsetT num)
2212 i386_operand_type t;
2214 operand_type_set (&t, 0);
2215 t.bitfield.imm64 = 1;
2217 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2219 /* This code is disabled on the 486 because all the Imm1 forms
2220 in the opcode table are slower on the i486. They're the
2221 versions with the implicitly specified single-position
2222 displacement, which has another syntax if you really want to
2224 t.bitfield.imm1 = 1;
2225 t.bitfield.imm8 = 1;
2226 t.bitfield.imm8s = 1;
2227 t.bitfield.imm16 = 1;
2228 t.bitfield.imm32 = 1;
2229 t.bitfield.imm32s = 1;
2231 else if (fits_in_signed_byte (num))
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2239 else if (fits_in_unsigned_byte (num))
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2246 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2248 t.bitfield.imm16 = 1;
2249 t.bitfield.imm32 = 1;
2250 t.bitfield.imm32s = 1;
2252 else if (fits_in_signed_long (num))
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2257 else if (fits_in_unsigned_long (num))
2258 t.bitfield.imm32 = 1;
2264 offset_in_range (offsetT val, int size)
2270 case 1: mask = ((addressT) 1 << 8) - 1; break;
2271 case 2: mask = ((addressT) 1 << 16) - 1; break;
2272 case 4: mask = ((addressT) 2 << 31) - 1; break;
2274 case 8: mask = ((addressT) 2 << 63) - 1; break;
2280 /* If BFD64, sign extend val for 32bit address mode. */
2281 if (flag_code != CODE_64BIT
2282 || i.prefix[ADDR_PREFIX])
2283 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2284 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2287 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2289 char buf1[40], buf2[40];
2291 sprint_value (buf1, val);
2292 sprint_value (buf2, val & mask);
2293 as_warn (_("%s shortened to %s"), buf1, buf2);
2308 a. PREFIX_EXIST if attempting to add a prefix where one from the
2309 same class already exists.
2310 b. PREFIX_LOCK if lock prefix is added.
2311 c. PREFIX_REP if rep/repne prefix is added.
2312 d. PREFIX_DS if ds prefix is added.
2313 e. PREFIX_OTHER if other prefix is added.
2316 static enum PREFIX_GROUP
2317 add_prefix (unsigned int prefix)
2319 enum PREFIX_GROUP ret = PREFIX_OTHER;
2322 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2323 && flag_code == CODE_64BIT)
2325 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2326 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2327 && (prefix & (REX_R | REX_X | REX_B))))
2338 case DS_PREFIX_OPCODE:
2341 case CS_PREFIX_OPCODE:
2342 case ES_PREFIX_OPCODE:
2343 case FS_PREFIX_OPCODE:
2344 case GS_PREFIX_OPCODE:
2345 case SS_PREFIX_OPCODE:
2349 case REPNE_PREFIX_OPCODE:
2350 case REPE_PREFIX_OPCODE:
2355 case LOCK_PREFIX_OPCODE:
2364 case ADDR_PREFIX_OPCODE:
2368 case DATA_PREFIX_OPCODE:
2372 if (i.prefix[q] != 0)
2380 i.prefix[q] |= prefix;
2383 as_bad (_("same type of prefix used twice"));
2389 update_code_flag (int value, int check)
2391 PRINTF_LIKE ((*as_error));
2393 flag_code = (enum flag_code) value;
2394 if (flag_code == CODE_64BIT)
2396 cpu_arch_flags.bitfield.cpu64 = 1;
2397 cpu_arch_flags.bitfield.cpuno64 = 0;
2401 cpu_arch_flags.bitfield.cpu64 = 0;
2402 cpu_arch_flags.bitfield.cpuno64 = 1;
2404 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2407 as_error = as_fatal;
2410 (*as_error) (_("64bit mode not supported on `%s'."),
2411 cpu_arch_name ? cpu_arch_name : default_arch);
2413 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2416 as_error = as_fatal;
2419 (*as_error) (_("32bit mode not supported on `%s'."),
2420 cpu_arch_name ? cpu_arch_name : default_arch);
2422 stackop_size = '\0';
2426 set_code_flag (int value)
2428 update_code_flag (value, 0);
2432 set_16bit_gcc_code_flag (int new_code_flag)
2434 flag_code = (enum flag_code) new_code_flag;
2435 if (flag_code != CODE_16BIT)
2437 cpu_arch_flags.bitfield.cpu64 = 0;
2438 cpu_arch_flags.bitfield.cpuno64 = 1;
2439 stackop_size = LONG_MNEM_SUFFIX;
2443 set_intel_syntax (int syntax_flag)
2445 /* Find out if register prefixing is specified. */
2446 int ask_naked_reg = 0;
2449 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2452 int e = get_symbol_name (&string);
2454 if (strcmp (string, "prefix") == 0)
2456 else if (strcmp (string, "noprefix") == 0)
2459 as_bad (_("bad argument to syntax directive."));
2460 (void) restore_line_pointer (e);
2462 demand_empty_rest_of_line ();
2464 intel_syntax = syntax_flag;
2466 if (ask_naked_reg == 0)
2467 allow_naked_reg = (intel_syntax
2468 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2470 allow_naked_reg = (ask_naked_reg < 0);
2472 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2474 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2475 identifier_chars['$'] = intel_syntax ? '$' : 0;
2476 register_prefix = allow_naked_reg ? "" : "%";
2480 set_intel_mnemonic (int mnemonic_flag)
2482 intel_mnemonic = mnemonic_flag;
2486 set_allow_index_reg (int flag)
2488 allow_index_reg = flag;
2492 set_check (int what)
2494 enum check_kind *kind;
2499 kind = &operand_check;
2510 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2513 int e = get_symbol_name (&string);
2515 if (strcmp (string, "none") == 0)
2517 else if (strcmp (string, "warning") == 0)
2518 *kind = check_warning;
2519 else if (strcmp (string, "error") == 0)
2520 *kind = check_error;
2522 as_bad (_("bad argument to %s_check directive."), str);
2523 (void) restore_line_pointer (e);
2526 as_bad (_("missing argument for %s_check directive"), str);
2528 demand_empty_rest_of_line ();
2532 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2533 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2536 static const char *arch;
2538 /* Intel LIOM is only supported on ELF. */
2544 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2545 use default_arch. */
2546 arch = cpu_arch_name;
2548 arch = default_arch;
2551 /* If we are targeting Intel MCU, we must enable it. */
2552 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2553 || new_flag.bitfield.cpuiamcu)
2556 /* If we are targeting Intel L1OM, we must enable it. */
2557 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2558 || new_flag.bitfield.cpul1om)
2561 /* If we are targeting Intel K1OM, we must enable it. */
2562 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2563 || new_flag.bitfield.cpuk1om)
2566 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2571 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2575 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2578 int e = get_symbol_name (&string);
2580 i386_cpu_flags flags;
2582 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2584 if (strcmp (string, cpu_arch[j].name) == 0)
2586 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2590 cpu_arch_name = cpu_arch[j].name;
2591 cpu_sub_arch_name = NULL;
2592 cpu_arch_flags = cpu_arch[j].flags;
2593 if (flag_code == CODE_64BIT)
2595 cpu_arch_flags.bitfield.cpu64 = 1;
2596 cpu_arch_flags.bitfield.cpuno64 = 0;
2600 cpu_arch_flags.bitfield.cpu64 = 0;
2601 cpu_arch_flags.bitfield.cpuno64 = 1;
2603 cpu_arch_isa = cpu_arch[j].type;
2604 cpu_arch_isa_flags = cpu_arch[j].flags;
2605 if (!cpu_arch_tune_set)
2607 cpu_arch_tune = cpu_arch_isa;
2608 cpu_arch_tune_flags = cpu_arch_isa_flags;
2613 flags = cpu_flags_or (cpu_arch_flags,
2616 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2618 if (cpu_sub_arch_name)
2620 char *name = cpu_sub_arch_name;
2621 cpu_sub_arch_name = concat (name,
2623 (const char *) NULL);
2627 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2628 cpu_arch_flags = flags;
2629 cpu_arch_isa_flags = flags;
2633 = cpu_flags_or (cpu_arch_isa_flags,
2635 (void) restore_line_pointer (e);
2636 demand_empty_rest_of_line ();
2641 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2643 /* Disable an ISA extension. */
2644 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2645 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2647 flags = cpu_flags_and_not (cpu_arch_flags,
2648 cpu_noarch[j].flags);
2649 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2651 if (cpu_sub_arch_name)
2653 char *name = cpu_sub_arch_name;
2654 cpu_sub_arch_name = concat (name, string,
2655 (const char *) NULL);
2659 cpu_sub_arch_name = xstrdup (string);
2660 cpu_arch_flags = flags;
2661 cpu_arch_isa_flags = flags;
2663 (void) restore_line_pointer (e);
2664 demand_empty_rest_of_line ();
2668 j = ARRAY_SIZE (cpu_arch);
2671 if (j >= ARRAY_SIZE (cpu_arch))
2672 as_bad (_("no such architecture: `%s'"), string);
2674 *input_line_pointer = e;
2677 as_bad (_("missing cpu architecture"));
2679 no_cond_jump_promotion = 0;
2680 if (*input_line_pointer == ','
2681 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2686 ++input_line_pointer;
2687 e = get_symbol_name (&string);
2689 if (strcmp (string, "nojumps") == 0)
2690 no_cond_jump_promotion = 1;
2691 else if (strcmp (string, "jumps") == 0)
2694 as_bad (_("no such architecture modifier: `%s'"), string);
2696 (void) restore_line_pointer (e);
2699 demand_empty_rest_of_line ();
2702 enum bfd_architecture
2705 if (cpu_arch_isa == PROCESSOR_L1OM)
2707 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2708 || flag_code != CODE_64BIT)
2709 as_fatal (_("Intel L1OM is 64bit ELF only"));
2710 return bfd_arch_l1om;
2712 else if (cpu_arch_isa == PROCESSOR_K1OM)
2714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2715 || flag_code != CODE_64BIT)
2716 as_fatal (_("Intel K1OM is 64bit ELF only"));
2717 return bfd_arch_k1om;
2719 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2721 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2722 || flag_code == CODE_64BIT)
2723 as_fatal (_("Intel MCU is 32bit ELF only"));
2724 return bfd_arch_iamcu;
2727 return bfd_arch_i386;
2733 if (!strncmp (default_arch, "x86_64", 6))
2735 if (cpu_arch_isa == PROCESSOR_L1OM)
2737 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2738 || default_arch[6] != '\0')
2739 as_fatal (_("Intel L1OM is 64bit ELF only"));
2740 return bfd_mach_l1om;
2742 else if (cpu_arch_isa == PROCESSOR_K1OM)
2744 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2745 || default_arch[6] != '\0')
2746 as_fatal (_("Intel K1OM is 64bit ELF only"));
2747 return bfd_mach_k1om;
2749 else if (default_arch[6] == '\0')
2750 return bfd_mach_x86_64;
2752 return bfd_mach_x64_32;
2754 else if (!strcmp (default_arch, "i386")
2755 || !strcmp (default_arch, "iamcu"))
2757 if (cpu_arch_isa == PROCESSOR_IAMCU)
2759 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2760 as_fatal (_("Intel MCU is 32bit ELF only"));
2761 return bfd_mach_i386_iamcu;
2764 return bfd_mach_i386_i386;
2767 as_fatal (_("unknown architecture"));
2773 const char *hash_err;
2775 /* Support pseudo prefixes like {disp32}. */
2776 lex_type ['{'] = LEX_BEGIN_NAME;
2778 /* Initialize op_hash hash table. */
2779 op_hash = hash_new ();
2782 const insn_template *optab;
2783 templates *core_optab;
2785 /* Setup for loop. */
2787 core_optab = XNEW (templates);
2788 core_optab->start = optab;
2793 if (optab->name == NULL
2794 || strcmp (optab->name, (optab - 1)->name) != 0)
2796 /* different name --> ship out current template list;
2797 add to hash table; & begin anew. */
2798 core_optab->end = optab;
2799 hash_err = hash_insert (op_hash,
2801 (void *) core_optab);
2804 as_fatal (_("can't hash %s: %s"),
2808 if (optab->name == NULL)
2810 core_optab = XNEW (templates);
2811 core_optab->start = optab;
2816 /* Initialize reg_hash hash table. */
2817 reg_hash = hash_new ();
2819 const reg_entry *regtab;
2820 unsigned int regtab_size = i386_regtab_size;
2822 for (regtab = i386_regtab; regtab_size--; regtab++)
2824 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2826 as_fatal (_("can't hash %s: %s"),
2832 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2837 for (c = 0; c < 256; c++)
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2846 else if (ISLOWER (c))
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2852 else if (ISUPPER (c))
2854 mnemonic_chars[c] = TOLOWER (c);
2855 register_chars[c] = mnemonic_chars[c];
2856 operand_chars[c] = c;
2858 else if (c == '{' || c == '}')
2860 mnemonic_chars[c] = c;
2861 operand_chars[c] = c;
2864 if (ISALPHA (c) || ISDIGIT (c))
2865 identifier_chars[c] = c;
2868 identifier_chars[c] = c;
2869 operand_chars[c] = c;
2874 identifier_chars['@'] = '@';
2877 identifier_chars['?'] = '?';
2878 operand_chars['?'] = '?';
2880 digit_chars['-'] = '-';
2881 mnemonic_chars['_'] = '_';
2882 mnemonic_chars['-'] = '-';
2883 mnemonic_chars['.'] = '.';
2884 identifier_chars['_'] = '_';
2885 identifier_chars['.'] = '.';
2887 for (p = operand_special_chars; *p != '\0'; p++)
2888 operand_chars[(unsigned char) *p] = *p;
2891 if (flag_code == CODE_64BIT)
2893 #if defined (OBJ_COFF) && defined (TE_PE)
2894 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2897 x86_dwarf2_return_column = 16;
2899 x86_cie_data_alignment = -8;
2903 x86_dwarf2_return_column = 8;
2904 x86_cie_data_alignment = -4;
2909 i386_print_statistics (FILE *file)
2911 hash_print_statistics (file, "i386 opcode", op_hash);
2912 hash_print_statistics (file, "i386 register", reg_hash);
2917 /* Debugging routines for md_assemble. */
2918 static void pte (insn_template *);
2919 static void pt (i386_operand_type);
2920 static void pe (expressionS *);
2921 static void ps (symbolS *);
2924 pi (char *line, i386_insn *x)
2928 fprintf (stdout, "%s: template ", line);
2930 fprintf (stdout, " address: base %s index %s scale %x\n",
2931 x->base_reg ? x->base_reg->reg_name : "none",
2932 x->index_reg ? x->index_reg->reg_name : "none",
2933 x->log2_scale_factor);
2934 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2935 x->rm.mode, x->rm.reg, x->rm.regmem);
2936 fprintf (stdout, " sib: base %x index %x scale %x\n",
2937 x->sib.base, x->sib.index, x->sib.scale);
2938 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2939 (x->rex & REX_W) != 0,
2940 (x->rex & REX_R) != 0,
2941 (x->rex & REX_X) != 0,
2942 (x->rex & REX_B) != 0);
2943 for (j = 0; j < x->operands; j++)
2945 fprintf (stdout, " #%d: ", j + 1);
2947 fprintf (stdout, "\n");
2948 if (x->types[j].bitfield.reg
2949 || x->types[j].bitfield.regmmx
2950 || x->types[j].bitfield.regsimd
2951 || x->types[j].bitfield.sreg2
2952 || x->types[j].bitfield.sreg3
2953 || x->types[j].bitfield.control
2954 || x->types[j].bitfield.debug
2955 || x->types[j].bitfield.test)
2956 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2957 if (operand_type_check (x->types[j], imm))
2959 if (operand_type_check (x->types[j], disp))
2960 pe (x->op[j].disps);
2965 pte (insn_template *t)
2968 fprintf (stdout, " %d operands ", t->operands);
2969 fprintf (stdout, "opcode %x ", t->base_opcode);
2970 if (t->extension_opcode != None)
2971 fprintf (stdout, "ext %x ", t->extension_opcode);
2972 if (t->opcode_modifier.d)
2973 fprintf (stdout, "D");
2974 if (t->opcode_modifier.w)
2975 fprintf (stdout, "W");
2976 fprintf (stdout, "\n");
2977 for (j = 0; j < t->operands; j++)
2979 fprintf (stdout, " #%d type ", j + 1);
2980 pt (t->operand_types[j]);
2981 fprintf (stdout, "\n");
2988 fprintf (stdout, " operation %d\n", e->X_op);
2989 fprintf (stdout, " add_number %ld (%lx)\n",
2990 (long) e->X_add_number, (long) e->X_add_number);
2991 if (e->X_add_symbol)
2993 fprintf (stdout, " add_symbol ");
2994 ps (e->X_add_symbol);
2995 fprintf (stdout, "\n");
2999 fprintf (stdout, " op_symbol ");
3000 ps (e->X_op_symbol);
3001 fprintf (stdout, "\n");
3008 fprintf (stdout, "%s type %s%s",
3010 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3011 segment_name (S_GET_SEGMENT (s)));
3014 static struct type_name
3016 i386_operand_type mask;
3019 const type_names[] =
3021 { OPERAND_TYPE_REG8, "r8" },
3022 { OPERAND_TYPE_REG16, "r16" },
3023 { OPERAND_TYPE_REG32, "r32" },
3024 { OPERAND_TYPE_REG64, "r64" },
3025 { OPERAND_TYPE_IMM8, "i8" },
3026 { OPERAND_TYPE_IMM8, "i8s" },
3027 { OPERAND_TYPE_IMM16, "i16" },
3028 { OPERAND_TYPE_IMM32, "i32" },
3029 { OPERAND_TYPE_IMM32S, "i32s" },
3030 { OPERAND_TYPE_IMM64, "i64" },
3031 { OPERAND_TYPE_IMM1, "i1" },
3032 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3033 { OPERAND_TYPE_DISP8, "d8" },
3034 { OPERAND_TYPE_DISP16, "d16" },
3035 { OPERAND_TYPE_DISP32, "d32" },
3036 { OPERAND_TYPE_DISP32S, "d32s" },
3037 { OPERAND_TYPE_DISP64, "d64" },
3038 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3039 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3040 { OPERAND_TYPE_CONTROL, "control reg" },
3041 { OPERAND_TYPE_TEST, "test reg" },
3042 { OPERAND_TYPE_DEBUG, "debug reg" },
3043 { OPERAND_TYPE_FLOATREG, "FReg" },
3044 { OPERAND_TYPE_FLOATACC, "FAcc" },
3045 { OPERAND_TYPE_SREG2, "SReg2" },
3046 { OPERAND_TYPE_SREG3, "SReg3" },
3047 { OPERAND_TYPE_ACC, "Acc" },
3048 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3049 { OPERAND_TYPE_REGMMX, "rMMX" },
3050 { OPERAND_TYPE_REGXMM, "rXMM" },
3051 { OPERAND_TYPE_REGYMM, "rYMM" },
3052 { OPERAND_TYPE_REGZMM, "rZMM" },
3053 { OPERAND_TYPE_REGMASK, "Mask reg" },
3054 { OPERAND_TYPE_ESSEG, "es" },
3058 pt (i386_operand_type t)
3061 i386_operand_type a;
3063 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3065 a = operand_type_and (t, type_names[j].mask);
3066 if (!operand_type_all_zero (&a))
3067 fprintf (stdout, "%s, ", type_names[j].name);
3072 #endif /* DEBUG386 */
3074 static bfd_reloc_code_real_type
3075 reloc (unsigned int size,
3078 bfd_reloc_code_real_type other)
3080 if (other != NO_RELOC)
3082 reloc_howto_type *rel;
3087 case BFD_RELOC_X86_64_GOT32:
3088 return BFD_RELOC_X86_64_GOT64;
3090 case BFD_RELOC_X86_64_GOTPLT64:
3091 return BFD_RELOC_X86_64_GOTPLT64;
3093 case BFD_RELOC_X86_64_PLTOFF64:
3094 return BFD_RELOC_X86_64_PLTOFF64;
3096 case BFD_RELOC_X86_64_GOTPC32:
3097 other = BFD_RELOC_X86_64_GOTPC64;
3099 case BFD_RELOC_X86_64_GOTPCREL:
3100 other = BFD_RELOC_X86_64_GOTPCREL64;
3102 case BFD_RELOC_X86_64_TPOFF32:
3103 other = BFD_RELOC_X86_64_TPOFF64;
3105 case BFD_RELOC_X86_64_DTPOFF32:
3106 other = BFD_RELOC_X86_64_DTPOFF64;
3112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3113 if (other == BFD_RELOC_SIZE32)
3116 other = BFD_RELOC_SIZE64;
3119 as_bad (_("there are no pc-relative size relocations"));
3125 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3126 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3129 rel = bfd_reloc_type_lookup (stdoutput, other);
3131 as_bad (_("unknown relocation (%u)"), other);
3132 else if (size != bfd_get_reloc_size (rel))
3133 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3134 bfd_get_reloc_size (rel),
3136 else if (pcrel && !rel->pc_relative)
3137 as_bad (_("non-pc-relative relocation for pc-relative field"));
3138 else if ((rel->complain_on_overflow == complain_overflow_signed
3140 || (rel->complain_on_overflow == complain_overflow_unsigned
3142 as_bad (_("relocated field and relocation type differ in signedness"));
3151 as_bad (_("there are no unsigned pc-relative relocations"));
3154 case 1: return BFD_RELOC_8_PCREL;
3155 case 2: return BFD_RELOC_16_PCREL;
3156 case 4: return BFD_RELOC_32_PCREL;
3157 case 8: return BFD_RELOC_64_PCREL;
3159 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3166 case 4: return BFD_RELOC_X86_64_32S;
3171 case 1: return BFD_RELOC_8;
3172 case 2: return BFD_RELOC_16;
3173 case 4: return BFD_RELOC_32;
3174 case 8: return BFD_RELOC_64;
3176 as_bad (_("cannot do %s %u byte relocation"),
3177 sign > 0 ? "signed" : "unsigned", size);
3183 /* Here we decide which fixups can be adjusted to make them relative to
3184 the beginning of the section instead of the symbol. Basically we need
3185 to make sure that the dynamic relocations are done correctly, so in
3186 some cases we force the original symbol to be used. */
3189 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3195 /* Don't adjust pc-relative references to merge sections in 64-bit
3197 if (use_rela_relocations
3198 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3202 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3203 and changed later by validate_fix. */
3204 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3205 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3208 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3209 for size relocations. */
3210 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3211 || fixP->fx_r_type == BFD_RELOC_SIZE64
3212 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3213 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3214 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3215 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3241 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3242 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3249 intel_float_operand (const char *mnemonic)
3251 /* Note that the value returned is meaningful only for opcodes with (memory)
3252 operands, hence the code here is free to improperly handle opcodes that
3253 have no operands (for better performance and smaller code). */
3255 if (mnemonic[0] != 'f')
3256 return 0; /* non-math */
3258 switch (mnemonic[1])
3260 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3261 the fs segment override prefix not currently handled because no
3262 call path can make opcodes without operands get here */
3264 return 2 /* integer op */;
3266 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3267 return 3; /* fldcw/fldenv */
3270 if (mnemonic[2] != 'o' /* fnop */)
3271 return 3; /* non-waiting control op */
3274 if (mnemonic[2] == 's')
3275 return 3; /* frstor/frstpm */
3278 if (mnemonic[2] == 'a')
3279 return 3; /* fsave */
3280 if (mnemonic[2] == 't')
3282 switch (mnemonic[3])
3284 case 'c': /* fstcw */
3285 case 'd': /* fstdw */
3286 case 'e': /* fstenv */
3287 case 's': /* fsts[gw] */
3293 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3294 return 0; /* fxsave/fxrstor are not really math ops */
3301 /* Build the VEX prefix. */
3304 build_vex_prefix (const insn_template *t)
3306 unsigned int register_specifier;
3307 unsigned int implied_prefix;
3308 unsigned int vector_length;
3310 /* Check register specifier. */
3311 if (i.vex.register_specifier)
3313 register_specifier =
3314 ~register_number (i.vex.register_specifier) & 0xf;
3315 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3318 register_specifier = 0xf;
3320 /* Use 2-byte VEX prefix by swapping destination and source
3322 if (i.vec_encoding != vex_encoding_vex3
3323 && i.dir_encoding == dir_encoding_default
3324 && i.operands == i.reg_operands
3325 && i.tm.opcode_modifier.vexopcode == VEX0F
3326 && i.tm.opcode_modifier.load
3329 unsigned int xchg = i.operands - 1;
3330 union i386_op temp_op;
3331 i386_operand_type temp_type;
3333 temp_type = i.types[xchg];
3334 i.types[xchg] = i.types[0];
3335 i.types[0] = temp_type;
3336 temp_op = i.op[xchg];
3337 i.op[xchg] = i.op[0];
3340 gas_assert (i.rm.mode == 3);
3344 i.rm.regmem = i.rm.reg;
3347 /* Use the next insn. */
3351 if (i.tm.opcode_modifier.vex == VEXScalar)
3352 vector_length = avxscalar;
3353 else if (i.tm.opcode_modifier.vex == VEX256)
3360 for (op = 0; op < t->operands; ++op)
3361 if (t->operand_types[op].bitfield.xmmword
3362 && t->operand_types[op].bitfield.ymmword
3363 && i.types[op].bitfield.ymmword)
3370 switch ((i.tm.base_opcode >> 8) & 0xff)
3375 case DATA_PREFIX_OPCODE:
3378 case REPE_PREFIX_OPCODE:
3381 case REPNE_PREFIX_OPCODE:
3388 /* Use 2-byte VEX prefix if possible. */
3389 if (i.vec_encoding != vex_encoding_vex3
3390 && i.tm.opcode_modifier.vexopcode == VEX0F
3391 && i.tm.opcode_modifier.vexw != VEXW1
3392 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3394 /* 2-byte VEX prefix. */
3398 i.vex.bytes[0] = 0xc5;
3400 /* Check the REX.R bit. */
3401 r = (i.rex & REX_R) ? 0 : 1;
3402 i.vex.bytes[1] = (r << 7
3403 | register_specifier << 3
3404 | vector_length << 2
3409 /* 3-byte VEX prefix. */
3414 switch (i.tm.opcode_modifier.vexopcode)
3418 i.vex.bytes[0] = 0xc4;
3422 i.vex.bytes[0] = 0xc4;
3426 i.vex.bytes[0] = 0xc4;
3430 i.vex.bytes[0] = 0x8f;
3434 i.vex.bytes[0] = 0x8f;
3438 i.vex.bytes[0] = 0x8f;
3444 /* The high 3 bits of the second VEX byte are 1's compliment
3445 of RXB bits from REX. */
3446 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3448 /* Check the REX.W bit. */
3449 w = (i.rex & REX_W) ? 1 : 0;
3450 if (i.tm.opcode_modifier.vexw == VEXW1)
3453 i.vex.bytes[2] = (w << 7
3454 | register_specifier << 3
3455 | vector_length << 2
3460 static INLINE bfd_boolean
3461 is_evex_encoding (const insn_template *t)
3463 return t->opcode_modifier.evex
3464 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3465 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3468 /* Build the EVEX prefix. */
3471 build_evex_prefix (void)
3473 unsigned int register_specifier;
3474 unsigned int implied_prefix;
3476 rex_byte vrex_used = 0;
3478 /* Check register specifier. */
3479 if (i.vex.register_specifier)
3481 gas_assert ((i.vrex & REX_X) == 0);
3483 register_specifier = i.vex.register_specifier->reg_num;
3484 if ((i.vex.register_specifier->reg_flags & RegRex))
3485 register_specifier += 8;
3486 /* The upper 16 registers are encoded in the fourth byte of the
3488 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3489 i.vex.bytes[3] = 0x8;
3490 register_specifier = ~register_specifier & 0xf;
3494 register_specifier = 0xf;
3496 /* Encode upper 16 vector index register in the fourth byte of
3498 if (!(i.vrex & REX_X))
3499 i.vex.bytes[3] = 0x8;
3504 switch ((i.tm.base_opcode >> 8) & 0xff)
3509 case DATA_PREFIX_OPCODE:
3512 case REPE_PREFIX_OPCODE:
3515 case REPNE_PREFIX_OPCODE:
3522 /* 4 byte EVEX prefix. */
3524 i.vex.bytes[0] = 0x62;
3527 switch (i.tm.opcode_modifier.vexopcode)
3543 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3545 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3547 /* The fifth bit of the second EVEX byte is 1's compliment of the
3548 REX_R bit in VREX. */
3549 if (!(i.vrex & REX_R))
3550 i.vex.bytes[1] |= 0x10;
3554 if ((i.reg_operands + i.imm_operands) == i.operands)
3556 /* When all operands are registers, the REX_X bit in REX is not
3557 used. We reuse it to encode the upper 16 registers, which is
3558 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3559 as 1's compliment. */
3560 if ((i.vrex & REX_B))
3563 i.vex.bytes[1] &= ~0x40;
3567 /* EVEX instructions shouldn't need the REX prefix. */
3568 i.vrex &= ~vrex_used;
3569 gas_assert (i.vrex == 0);
3571 /* Check the REX.W bit. */
3572 w = (i.rex & REX_W) ? 1 : 0;
3573 if (i.tm.opcode_modifier.vexw)
3575 if (i.tm.opcode_modifier.vexw == VEXW1)
3578 /* If w is not set it means we are dealing with WIG instruction. */
3581 if (evexwig == evexw1)
3585 /* Encode the U bit. */
3586 implied_prefix |= 0x4;
3588 /* The third byte of the EVEX prefix. */
3589 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3591 /* The fourth byte of the EVEX prefix. */
3592 /* The zeroing-masking bit. */
3593 if (i.mask && i.mask->zeroing)
3594 i.vex.bytes[3] |= 0x80;
3596 /* Don't always set the broadcast bit if there is no RC. */
3599 /* Encode the vector length. */
3600 unsigned int vec_length;
3602 if (!i.tm.opcode_modifier.evex
3603 || i.tm.opcode_modifier.evex == EVEXDYN)
3608 for (op = 0; op < i.tm.operands; ++op)
3609 if (i.tm.operand_types[op].bitfield.xmmword
3610 + i.tm.operand_types[op].bitfield.ymmword
3611 + i.tm.operand_types[op].bitfield.zmmword > 1)
3613 if (i.types[op].bitfield.zmmword)
3614 i.tm.opcode_modifier.evex = EVEX512;
3615 else if (i.types[op].bitfield.ymmword)
3616 i.tm.opcode_modifier.evex = EVEX256;
3617 else if (i.types[op].bitfield.xmmword)
3618 i.tm.opcode_modifier.evex = EVEX128;
3625 switch (i.tm.opcode_modifier.evex)
3627 case EVEXLIG: /* LL' is ignored */
3628 vec_length = evexlig << 5;
3631 vec_length = 0 << 5;
3634 vec_length = 1 << 5;
3637 vec_length = 2 << 5;
3643 i.vex.bytes[3] |= vec_length;
3644 /* Encode the broadcast bit. */
3646 i.vex.bytes[3] |= 0x10;
3650 if (i.rounding->type != saeonly)
3651 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3653 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3656 if (i.mask && i.mask->mask)
3657 i.vex.bytes[3] |= i.mask->mask->reg_num;
3661 process_immext (void)
3665 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3668 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3669 with an opcode suffix which is coded in the same place as an
3670 8-bit immediate field would be.
3671 Here we check those operands and remove them afterwards. */
3674 for (x = 0; x < i.operands; x++)
3675 if (register_number (i.op[x].regs) != x)
3676 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3677 register_prefix, i.op[x].regs->reg_name, x + 1,
3683 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3685 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3686 suffix which is coded in the same place as an 8-bit immediate
3688 Here we check those operands and remove them afterwards. */
3691 if (i.operands != 3)
3694 for (x = 0; x < 2; x++)
3695 if (register_number (i.op[x].regs) != x)
3696 goto bad_register_operand;
3698 /* Check for third operand for mwaitx/monitorx insn. */
3699 if (register_number (i.op[x].regs)
3700 != (x + (i.tm.extension_opcode == 0xfb)))
3702 bad_register_operand:
3703 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3704 register_prefix, i.op[x].regs->reg_name, x+1,
3711 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3712 which is coded in the same place as an 8-bit immediate field
3713 would be. Here we fake an 8-bit immediate operand from the
3714 opcode suffix stored in tm.extension_opcode.
3716 AVX instructions also use this encoding, for some of
3717 3 argument instructions. */
3719 gas_assert (i.imm_operands <= 1
3721 || ((i.tm.opcode_modifier.vex
3722 || i.tm.opcode_modifier.vexopcode
3723 || is_evex_encoding (&i.tm))
3724 && i.operands <= 4)));
3726 exp = &im_expressions[i.imm_operands++];
3727 i.op[i.operands].imms = exp;
3728 i.types[i.operands] = imm8;
3730 exp->X_op = O_constant;
3731 exp->X_add_number = i.tm.extension_opcode;
3732 i.tm.extension_opcode = None;
3739 switch (i.tm.opcode_modifier.hleprefixok)
3744 as_bad (_("invalid instruction `%s' after `%s'"),
3745 i.tm.name, i.hle_prefix);
3748 if (i.prefix[LOCK_PREFIX])
3750 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3754 case HLEPrefixRelease:
3755 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3757 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3761 if (i.mem_operands == 0
3762 || !operand_type_check (i.types[i.operands - 1], anymem))
3764 as_bad (_("memory destination needed for instruction `%s'"
3765 " after `xrelease'"), i.tm.name);
3772 /* Try the shortest encoding by shortening operand size. */
3775 optimize_encoding (void)
3779 if (optimize_for_space
3780 && i.reg_operands == 1
3781 && i.imm_operands == 1
3782 && !i.types[1].bitfield.byte
3783 && i.op[0].imms->X_op == O_constant
3784 && fits_in_imm7 (i.op[0].imms->X_add_number)
3785 && ((i.tm.base_opcode == 0xa8
3786 && i.tm.extension_opcode == None)
3787 || (i.tm.base_opcode == 0xf6
3788 && i.tm.extension_opcode == 0x0)))
3791 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3793 unsigned int base_regnum = i.op[1].regs->reg_num;
3794 if (flag_code == CODE_64BIT || base_regnum < 4)
3796 i.types[1].bitfield.byte = 1;
3797 /* Ignore the suffix. */
3799 if (base_regnum >= 4
3800 && !(i.op[1].regs->reg_flags & RegRex))
3802 /* Handle SP, BP, SI and DI registers. */
3803 if (i.types[1].bitfield.word)
3805 else if (i.types[1].bitfield.dword)
3813 else if (flag_code == CODE_64BIT
3814 && ((i.types[1].bitfield.qword
3815 && i.reg_operands == 1
3816 && i.imm_operands == 1
3817 && i.op[0].imms->X_op == O_constant
3818 && ((i.tm.base_opcode == 0xb0
3819 && i.tm.extension_opcode == None
3820 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3821 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3822 && (((i.tm.base_opcode == 0x24
3823 || i.tm.base_opcode == 0xa8)
3824 && i.tm.extension_opcode == None)
3825 || (i.tm.base_opcode == 0x80
3826 && i.tm.extension_opcode == 0x4)
3827 || ((i.tm.base_opcode == 0xf6
3828 || i.tm.base_opcode == 0xc6)
3829 && i.tm.extension_opcode == 0x0)))))
3830 || (i.types[0].bitfield.qword
3831 && ((i.reg_operands == 2
3832 && i.op[0].regs == i.op[1].regs
3833 && ((i.tm.base_opcode == 0x30
3834 || i.tm.base_opcode == 0x28)
3835 && i.tm.extension_opcode == None))
3836 || (i.reg_operands == 1
3838 && i.tm.base_opcode == 0x30
3839 && i.tm.extension_opcode == None)))))
3842 andq $imm31, %r64 -> andl $imm31, %r32
3843 testq $imm31, %r64 -> testl $imm31, %r32
3844 xorq %r64, %r64 -> xorl %r32, %r32
3845 subq %r64, %r64 -> subl %r32, %r32
3846 movq $imm31, %r64 -> movl $imm31, %r32
3847 movq $imm32, %r64 -> movl $imm32, %r32
3849 i.tm.opcode_modifier.norex64 = 1;
3850 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3853 movq $imm31, %r64 -> movl $imm31, %r32
3854 movq $imm32, %r64 -> movl $imm32, %r32
3856 i.tm.operand_types[0].bitfield.imm32 = 1;
3857 i.tm.operand_types[0].bitfield.imm32s = 0;
3858 i.tm.operand_types[0].bitfield.imm64 = 0;
3859 i.types[0].bitfield.imm32 = 1;
3860 i.types[0].bitfield.imm32s = 0;
3861 i.types[0].bitfield.imm64 = 0;
3862 i.types[1].bitfield.dword = 1;
3863 i.types[1].bitfield.qword = 0;
3864 if (i.tm.base_opcode == 0xc6)
3867 movq $imm31, %r64 -> movl $imm31, %r32
3869 i.tm.base_opcode = 0xb0;
3870 i.tm.extension_opcode = None;
3871 i.tm.opcode_modifier.shortform = 1;
3872 i.tm.opcode_modifier.modrm = 0;
3876 else if (optimize > 1
3877 && i.reg_operands == 3
3878 && i.op[0].regs == i.op[1].regs
3879 && !i.types[2].bitfield.xmmword
3880 && (i.tm.opcode_modifier.vex
3881 || ((!i.mask || i.mask->zeroing)
3883 && is_evex_encoding (&i.tm)
3884 && (i.vec_encoding != vex_encoding_evex
3885 || i.tm.cpu_flags.bitfield.cpuavx512vl
3886 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3887 && ((i.tm.base_opcode == 0x55
3888 || i.tm.base_opcode == 0x6655
3889 || i.tm.base_opcode == 0x66df
3890 || i.tm.base_opcode == 0x57
3891 || i.tm.base_opcode == 0x6657
3892 || i.tm.base_opcode == 0x66ef
3893 || i.tm.base_opcode == 0x66f8
3894 || i.tm.base_opcode == 0x66f9
3895 || i.tm.base_opcode == 0x66fa
3896 || i.tm.base_opcode == 0x66fb)
3897 && i.tm.extension_opcode == None))
3900 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3902 EVEX VOP %zmmM, %zmmM, %zmmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 EVEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3907 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandn and vpxor:
3911 VEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN
3913 VOP, one of vpandnd and vpandnq:
3914 EVEX VOP %zmmM, %zmmM, %zmmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 EVEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3919 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3920 VOP, one of vpxord and vpxorq:
3921 EVEX VOP %zmmM, %zmmM, %zmmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 EVEX VOP %ymmM, %ymmM, %ymmN
3925 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3926 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 if (is_evex_encoding (&i.tm))
3930 if (i.vec_encoding == vex_encoding_evex)
3931 i.tm.opcode_modifier.evex = EVEX128;
3934 i.tm.opcode_modifier.vex = VEX128;
3935 i.tm.opcode_modifier.vexw = VEXW0;
3936 i.tm.opcode_modifier.evex = 0;
3940 i.tm.opcode_modifier.vex = VEX128;
3942 if (i.tm.opcode_modifier.vex)
3943 for (j = 0; j < 3; j++)
3945 i.types[j].bitfield.xmmword = 1;
3946 i.types[j].bitfield.ymmword = 0;
3951 /* This is the guts of the machine-dependent assembler. LINE points to a
3952 machine dependent instruction. This function is supposed to emit
3953 the frags/bytes it assembles to. */
3956 md_assemble (char *line)
3959 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3960 const insn_template *t;
3962 /* Initialize globals. */
3963 memset (&i, '\0', sizeof (i));
3964 for (j = 0; j < MAX_OPERANDS; j++)
3965 i.reloc[j] = NO_RELOC;
3966 memset (disp_expressions, '\0', sizeof (disp_expressions));
3967 memset (im_expressions, '\0', sizeof (im_expressions));
3968 save_stack_p = save_stack;
3970 /* First parse an instruction mnemonic & call i386_operand for the operands.
3971 We assume that the scrubber has arranged it so that line[0] is the valid
3972 start of a (possibly prefixed) mnemonic. */
3974 line = parse_insn (line, mnemonic);
3977 mnem_suffix = i.suffix;
3979 line = parse_operands (line, mnemonic);
3981 xfree (i.memop1_string);
3982 i.memop1_string = NULL;
3986 /* Now we've parsed the mnemonic into a set of templates, and have the
3987 operands at hand. */
3989 /* All intel opcodes have reversed operands except for "bound" and
3990 "enter". We also don't reverse intersegment "jmp" and "call"
3991 instructions with 2 immediate operands so that the immediate segment
3992 precedes the offset, as it does when in AT&T mode. */
3995 && (strcmp (mnemonic, "bound") != 0)
3996 && (strcmp (mnemonic, "invlpga") != 0)
3997 && !(operand_type_check (i.types[0], imm)
3998 && operand_type_check (i.types[1], imm)))
4001 /* The order of the immediates should be reversed
4002 for 2 immediates extrq and insertq instructions */
4003 if (i.imm_operands == 2
4004 && (strcmp (mnemonic, "extrq") == 0
4005 || strcmp (mnemonic, "insertq") == 0))
4006 swap_2_operands (0, 1);
4011 /* Don't optimize displacement for movabs since it only takes 64bit
4014 && i.disp_encoding != disp_encoding_32bit
4015 && (flag_code != CODE_64BIT
4016 || strcmp (mnemonic, "movabs") != 0))
4019 /* Next, we find a template that matches the given insn,
4020 making sure the overlap of the given operands types is consistent
4021 with the template operand types. */
4023 if (!(t = match_template (mnem_suffix)))
4026 if (sse_check != check_none
4027 && !i.tm.opcode_modifier.noavx
4028 && !i.tm.cpu_flags.bitfield.cpuavx
4029 && (i.tm.cpu_flags.bitfield.cpusse
4030 || i.tm.cpu_flags.bitfield.cpusse2
4031 || i.tm.cpu_flags.bitfield.cpusse3
4032 || i.tm.cpu_flags.bitfield.cpussse3
4033 || i.tm.cpu_flags.bitfield.cpusse4_1
4034 || i.tm.cpu_flags.bitfield.cpusse4_2
4035 || i.tm.cpu_flags.bitfield.cpupclmul
4036 || i.tm.cpu_flags.bitfield.cpuaes
4037 || i.tm.cpu_flags.bitfield.cpugfni))
4039 (sse_check == check_warning
4041 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4044 /* Zap movzx and movsx suffix. The suffix has been set from
4045 "word ptr" or "byte ptr" on the source operand in Intel syntax
4046 or extracted from mnemonic in AT&T syntax. But we'll use
4047 the destination register to choose the suffix for encoding. */
4048 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4051 there is no suffix, the default will be byte extension. */
4052 if (i.reg_operands != 2
4055 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4060 if (i.tm.opcode_modifier.fwait)
4061 if (!add_prefix (FWAIT_OPCODE))
4064 /* Check if REP prefix is OK. */
4065 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4067 as_bad (_("invalid instruction `%s' after `%s'"),
4068 i.tm.name, i.rep_prefix);
4072 /* Check for lock without a lockable instruction. Destination operand
4073 must be memory unless it is xchg (0x86). */
4074 if (i.prefix[LOCK_PREFIX]
4075 && (!i.tm.opcode_modifier.islockable
4076 || i.mem_operands == 0
4077 || (i.tm.base_opcode != 0x86
4078 && !operand_type_check (i.types[i.operands - 1], anymem))))
4080 as_bad (_("expecting lockable instruction after `lock'"));
4084 /* Check if HLE prefix is OK. */
4085 if (i.hle_prefix && !check_hle ())
4088 /* Check BND prefix. */
4089 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4090 as_bad (_("expecting valid branch instruction after `bnd'"));
4092 /* Check NOTRACK prefix. */
4093 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4094 as_bad (_("expecting indirect branch instruction after `notrack'"));
4096 if (i.tm.cpu_flags.bitfield.cpumpx)
4098 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4099 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4100 else if (flag_code != CODE_16BIT
4101 ? i.prefix[ADDR_PREFIX]
4102 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4103 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4106 /* Insert BND prefix. */
4108 && i.tm.opcode_modifier.bndprefixok
4109 && !i.prefix[BND_PREFIX])
4110 add_prefix (BND_PREFIX_OPCODE);
4112 /* Check string instruction segment overrides. */
4113 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4115 if (!check_string ())
4117 i.disp_operands = 0;
4120 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4121 optimize_encoding ();
4123 if (!process_suffix ())
4126 /* Update operand types. */
4127 for (j = 0; j < i.operands; j++)
4128 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4130 /* Make still unresolved immediate matches conform to size of immediate
4131 given in i.suffix. */
4132 if (!finalize_imm ())
4135 if (i.types[0].bitfield.imm1)
4136 i.imm_operands = 0; /* kludge for shift insns. */
4138 /* We only need to check those implicit registers for instructions
4139 with 3 operands or less. */
4140 if (i.operands <= 3)
4141 for (j = 0; j < i.operands; j++)
4142 if (i.types[j].bitfield.inoutportreg
4143 || i.types[j].bitfield.shiftcount
4144 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4147 /* ImmExt should be processed after SSE2AVX. */
4148 if (!i.tm.opcode_modifier.sse2avx
4149 && i.tm.opcode_modifier.immext)
4152 /* For insns with operands there are more diddles to do to the opcode. */
4155 if (!process_operands ())
4158 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4160 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4161 as_warn (_("translating to `%sp'"), i.tm.name);
4164 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4165 || is_evex_encoding (&i.tm))
4167 if (flag_code == CODE_16BIT)
4169 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4174 if (i.tm.opcode_modifier.vex)
4175 build_vex_prefix (t);
4177 build_evex_prefix ();
4180 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4181 instructions may define INT_OPCODE as well, so avoid this corner
4182 case for those instructions that use MODRM. */
4183 if (i.tm.base_opcode == INT_OPCODE
4184 && !i.tm.opcode_modifier.modrm
4185 && i.op[0].imms->X_add_number == 3)
4187 i.tm.base_opcode = INT3_OPCODE;
4191 if ((i.tm.opcode_modifier.jump
4192 || i.tm.opcode_modifier.jumpbyte
4193 || i.tm.opcode_modifier.jumpdword)
4194 && i.op[0].disps->X_op == O_constant)
4196 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4197 the absolute address given by the constant. Since ix86 jumps and
4198 calls are pc relative, we need to generate a reloc. */
4199 i.op[0].disps->X_add_symbol = &abs_symbol;
4200 i.op[0].disps->X_op = O_symbol;
4203 if (i.tm.opcode_modifier.rex64)
4206 /* For 8 bit registers we need an empty rex prefix. Also if the
4207 instruction already has a prefix, we need to convert old
4208 registers to new ones. */
4210 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4211 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4213 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4214 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4215 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4220 i.rex |= REX_OPCODE;
4221 for (x = 0; x < 2; x++)
4223 /* Look for 8 bit operand that uses old registers. */
4224 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4225 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4227 /* In case it is "hi" register, give up. */
4228 if (i.op[x].regs->reg_num > 3)
4229 as_bad (_("can't encode register '%s%s' in an "
4230 "instruction requiring REX prefix."),
4231 register_prefix, i.op[x].regs->reg_name);
4233 /* Otherwise it is equivalent to the extended register.
4234 Since the encoding doesn't change this is merely
4235 cosmetic cleanup for debug output. */
4237 i.op[x].regs = i.op[x].regs + 8;
4242 if (i.rex == 0 && i.rex_encoding)
4244 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4245 that uses legacy register. If it is "hi" register, don't add
4246 the REX_OPCODE byte. */
4248 for (x = 0; x < 2; x++)
4249 if (i.types[x].bitfield.reg
4250 && i.types[x].bitfield.byte
4251 && (i.op[x].regs->reg_flags & RegRex64) == 0
4252 && i.op[x].regs->reg_num > 3)
4254 i.rex_encoding = FALSE;
4263 add_prefix (REX_OPCODE | i.rex);
4265 /* We are ready to output the insn. */
4270 parse_insn (char *line, char *mnemonic)
4273 char *token_start = l;
4276 const insn_template *t;
4282 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4287 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4289 as_bad (_("no such instruction: `%s'"), token_start);
4294 if (!is_space_char (*l)
4295 && *l != END_OF_INSN
4297 || (*l != PREFIX_SEPARATOR
4300 as_bad (_("invalid character %s in mnemonic"),
4301 output_invalid (*l));
4304 if (token_start == l)
4306 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4307 as_bad (_("expecting prefix; got nothing"));
4309 as_bad (_("expecting mnemonic; got nothing"));
4313 /* Look up instruction (or prefix) via hash table. */
4314 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4316 if (*l != END_OF_INSN
4317 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4318 && current_templates
4319 && current_templates->start->opcode_modifier.isprefix)
4321 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4323 as_bad ((flag_code != CODE_64BIT
4324 ? _("`%s' is only supported in 64-bit mode")
4325 : _("`%s' is not supported in 64-bit mode")),
4326 current_templates->start->name);
4329 /* If we are in 16-bit mode, do not allow addr16 or data16.
4330 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4331 if ((current_templates->start->opcode_modifier.size16
4332 || current_templates->start->opcode_modifier.size32)
4333 && flag_code != CODE_64BIT
4334 && (current_templates->start->opcode_modifier.size32
4335 ^ (flag_code == CODE_16BIT)))
4337 as_bad (_("redundant %s prefix"),
4338 current_templates->start->name);
4341 if (current_templates->start->opcode_length == 0)
4343 /* Handle pseudo prefixes. */
4344 switch (current_templates->start->base_opcode)
4348 i.disp_encoding = disp_encoding_8bit;
4352 i.disp_encoding = disp_encoding_32bit;
4356 i.dir_encoding = dir_encoding_load;
4360 i.dir_encoding = dir_encoding_store;
4364 i.vec_encoding = vex_encoding_vex2;
4368 i.vec_encoding = vex_encoding_vex3;
4372 i.vec_encoding = vex_encoding_evex;
4376 i.rex_encoding = TRUE;
4380 i.no_optimize = TRUE;
4388 /* Add prefix, checking for repeated prefixes. */
4389 switch (add_prefix (current_templates->start->base_opcode))
4394 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4395 i.notrack_prefix = current_templates->start->name;
4398 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4399 i.hle_prefix = current_templates->start->name;
4400 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4401 i.bnd_prefix = current_templates->start->name;
4403 i.rep_prefix = current_templates->start->name;
4409 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4416 if (!current_templates)
4418 /* Check if we should swap operand or force 32bit displacement in
4420 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4421 i.dir_encoding = dir_encoding_store;
4422 else if (mnem_p - 3 == dot_p
4425 i.disp_encoding = disp_encoding_8bit;
4426 else if (mnem_p - 4 == dot_p
4430 i.disp_encoding = disp_encoding_32bit;
4435 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4438 if (!current_templates)
4441 /* See if we can get a match by trimming off a suffix. */
4444 case WORD_MNEM_SUFFIX:
4445 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4446 i.suffix = SHORT_MNEM_SUFFIX;
4449 case BYTE_MNEM_SUFFIX:
4450 case QWORD_MNEM_SUFFIX:
4451 i.suffix = mnem_p[-1];
4453 current_templates = (const templates *) hash_find (op_hash,
4456 case SHORT_MNEM_SUFFIX:
4457 case LONG_MNEM_SUFFIX:
4460 i.suffix = mnem_p[-1];
4462 current_templates = (const templates *) hash_find (op_hash,
4471 if (intel_float_operand (mnemonic) == 1)
4472 i.suffix = SHORT_MNEM_SUFFIX;
4474 i.suffix = LONG_MNEM_SUFFIX;
4476 current_templates = (const templates *) hash_find (op_hash,
4481 if (!current_templates)
4483 as_bad (_("no such instruction: `%s'"), token_start);
4488 if (current_templates->start->opcode_modifier.jump
4489 || current_templates->start->opcode_modifier.jumpbyte)
4491 /* Check for a branch hint. We allow ",pt" and ",pn" for
4492 predict taken and predict not taken respectively.
4493 I'm not sure that branch hints actually do anything on loop
4494 and jcxz insns (JumpByte) for current Pentium4 chips. They
4495 may work in the future and it doesn't hurt to accept them
4497 if (l[0] == ',' && l[1] == 'p')
4501 if (!add_prefix (DS_PREFIX_OPCODE))
4505 else if (l[2] == 'n')
4507 if (!add_prefix (CS_PREFIX_OPCODE))
4513 /* Any other comma loses. */
4516 as_bad (_("invalid character %s in mnemonic"),
4517 output_invalid (*l));
4521 /* Check if instruction is supported on specified architecture. */
4523 for (t = current_templates->start; t < current_templates->end; ++t)
4525 supported |= cpu_flags_match (t);
4526 if (supported == CPU_FLAGS_PERFECT_MATCH)
4528 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4529 as_warn (_("use .code16 to ensure correct addressing mode"));
4535 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4536 as_bad (flag_code == CODE_64BIT
4537 ? _("`%s' is not supported in 64-bit mode")
4538 : _("`%s' is only supported in 64-bit mode"),
4539 current_templates->start->name);
4541 as_bad (_("`%s' is not supported on `%s%s'"),
4542 current_templates->start->name,
4543 cpu_arch_name ? cpu_arch_name : default_arch,
4544 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4550 parse_operands (char *l, const char *mnemonic)
4554 /* 1 if operand is pending after ','. */
4555 unsigned int expecting_operand = 0;
4557 /* Non-zero if operand parens not balanced. */
4558 unsigned int paren_not_balanced;
4560 while (*l != END_OF_INSN)
4562 /* Skip optional white space before operand. */
4563 if (is_space_char (*l))
4565 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4567 as_bad (_("invalid character %s before operand %d"),
4568 output_invalid (*l),
4572 token_start = l; /* After white space. */
4573 paren_not_balanced = 0;
4574 while (paren_not_balanced || *l != ',')
4576 if (*l == END_OF_INSN)
4578 if (paren_not_balanced)
4581 as_bad (_("unbalanced parenthesis in operand %d."),
4584 as_bad (_("unbalanced brackets in operand %d."),
4589 break; /* we are done */
4591 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4593 as_bad (_("invalid character %s in operand %d"),
4594 output_invalid (*l),
4601 ++paren_not_balanced;
4603 --paren_not_balanced;
4608 ++paren_not_balanced;
4610 --paren_not_balanced;
4614 if (l != token_start)
4615 { /* Yes, we've read in another operand. */
4616 unsigned int operand_ok;
4617 this_operand = i.operands++;
4618 if (i.operands > MAX_OPERANDS)
4620 as_bad (_("spurious operands; (%d operands/instruction max)"),
4624 i.types[this_operand].bitfield.unspecified = 1;
4625 /* Now parse operand adding info to 'i' as we go along. */
4626 END_STRING_AND_SAVE (l);
4630 i386_intel_operand (token_start,
4631 intel_float_operand (mnemonic));
4633 operand_ok = i386_att_operand (token_start);
4635 RESTORE_END_STRING (l);
4641 if (expecting_operand)
4643 expecting_operand_after_comma:
4644 as_bad (_("expecting operand after ','; got nothing"));
4649 as_bad (_("expecting operand before ','; got nothing"));
4654 /* Now *l must be either ',' or END_OF_INSN. */
4657 if (*++l == END_OF_INSN)
4659 /* Just skip it, if it's \n complain. */
4660 goto expecting_operand_after_comma;
4662 expecting_operand = 1;
4669 swap_2_operands (int xchg1, int xchg2)
4671 union i386_op temp_op;
4672 i386_operand_type temp_type;
4673 enum bfd_reloc_code_real temp_reloc;
4675 temp_type = i.types[xchg2];
4676 i.types[xchg2] = i.types[xchg1];
4677 i.types[xchg1] = temp_type;
4678 temp_op = i.op[xchg2];
4679 i.op[xchg2] = i.op[xchg1];
4680 i.op[xchg1] = temp_op;
4681 temp_reloc = i.reloc[xchg2];
4682 i.reloc[xchg2] = i.reloc[xchg1];
4683 i.reloc[xchg1] = temp_reloc;
4687 if (i.mask->operand == xchg1)
4688 i.mask->operand = xchg2;
4689 else if (i.mask->operand == xchg2)
4690 i.mask->operand = xchg1;
4694 if (i.broadcast->operand == xchg1)
4695 i.broadcast->operand = xchg2;
4696 else if (i.broadcast->operand == xchg2)
4697 i.broadcast->operand = xchg1;
4701 if (i.rounding->operand == xchg1)
4702 i.rounding->operand = xchg2;
4703 else if (i.rounding->operand == xchg2)
4704 i.rounding->operand = xchg1;
4709 swap_operands (void)
4715 swap_2_operands (1, i.operands - 2);
4719 swap_2_operands (0, i.operands - 1);
4725 if (i.mem_operands == 2)
4727 const seg_entry *temp_seg;
4728 temp_seg = i.seg[0];
4729 i.seg[0] = i.seg[1];
4730 i.seg[1] = temp_seg;
4734 /* Try to ensure constant immediates are represented in the smallest
4739 char guess_suffix = 0;
4743 guess_suffix = i.suffix;
4744 else if (i.reg_operands)
4746 /* Figure out a suffix from the last register operand specified.
4747 We can't do this properly yet, ie. excluding InOutPortReg,
4748 but the following works for instructions with immediates.
4749 In any case, we can't set i.suffix yet. */
4750 for (op = i.operands; --op >= 0;)
4751 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4753 guess_suffix = BYTE_MNEM_SUFFIX;
4756 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4758 guess_suffix = WORD_MNEM_SUFFIX;
4761 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4763 guess_suffix = LONG_MNEM_SUFFIX;
4766 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4768 guess_suffix = QWORD_MNEM_SUFFIX;
4772 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4773 guess_suffix = WORD_MNEM_SUFFIX;
4775 for (op = i.operands; --op >= 0;)
4776 if (operand_type_check (i.types[op], imm))
4778 switch (i.op[op].imms->X_op)
4781 /* If a suffix is given, this operand may be shortened. */
4782 switch (guess_suffix)
4784 case LONG_MNEM_SUFFIX:
4785 i.types[op].bitfield.imm32 = 1;
4786 i.types[op].bitfield.imm64 = 1;
4788 case WORD_MNEM_SUFFIX:
4789 i.types[op].bitfield.imm16 = 1;
4790 i.types[op].bitfield.imm32 = 1;
4791 i.types[op].bitfield.imm32s = 1;
4792 i.types[op].bitfield.imm64 = 1;
4794 case BYTE_MNEM_SUFFIX:
4795 i.types[op].bitfield.imm8 = 1;
4796 i.types[op].bitfield.imm8s = 1;
4797 i.types[op].bitfield.imm16 = 1;
4798 i.types[op].bitfield.imm32 = 1;
4799 i.types[op].bitfield.imm32s = 1;
4800 i.types[op].bitfield.imm64 = 1;
4804 /* If this operand is at most 16 bits, convert it
4805 to a signed 16 bit number before trying to see
4806 whether it will fit in an even smaller size.
4807 This allows a 16-bit operand such as $0xffe0 to
4808 be recognised as within Imm8S range. */
4809 if ((i.types[op].bitfield.imm16)
4810 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4812 i.op[op].imms->X_add_number =
4813 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4816 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4817 if ((i.types[op].bitfield.imm32)
4818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4822 ^ ((offsetT) 1 << 31))
4823 - ((offsetT) 1 << 31));
4827 = operand_type_or (i.types[op],
4828 smallest_imm_type (i.op[op].imms->X_add_number));
4830 /* We must avoid matching of Imm32 templates when 64bit
4831 only immediate is available. */
4832 if (guess_suffix == QWORD_MNEM_SUFFIX)
4833 i.types[op].bitfield.imm32 = 0;
4840 /* Symbols and expressions. */
4842 /* Convert symbolic operand to proper sizes for matching, but don't
4843 prevent matching a set of insns that only supports sizes other
4844 than those matching the insn suffix. */
4846 i386_operand_type mask, allowed;
4847 const insn_template *t;
4849 operand_type_set (&mask, 0);
4850 operand_type_set (&allowed, 0);
4852 for (t = current_templates->start;
4853 t < current_templates->end;
4855 allowed = operand_type_or (allowed,
4856 t->operand_types[op]);
4857 switch (guess_suffix)
4859 case QWORD_MNEM_SUFFIX:
4860 mask.bitfield.imm64 = 1;
4861 mask.bitfield.imm32s = 1;
4863 case LONG_MNEM_SUFFIX:
4864 mask.bitfield.imm32 = 1;
4866 case WORD_MNEM_SUFFIX:
4867 mask.bitfield.imm16 = 1;
4869 case BYTE_MNEM_SUFFIX:
4870 mask.bitfield.imm8 = 1;
4875 allowed = operand_type_and (mask, allowed);
4876 if (!operand_type_all_zero (&allowed))
4877 i.types[op] = operand_type_and (i.types[op], mask);
4884 /* Try to use the smallest displacement type too. */
4886 optimize_disp (void)
4890 for (op = i.operands; --op >= 0;)
4891 if (operand_type_check (i.types[op], disp))
4893 if (i.op[op].disps->X_op == O_constant)
4895 offsetT op_disp = i.op[op].disps->X_add_number;
4897 if (i.types[op].bitfield.disp16
4898 && (op_disp & ~(offsetT) 0xffff) == 0)
4900 /* If this operand is at most 16 bits, convert
4901 to a signed 16 bit number and don't use 64bit
4903 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4904 i.types[op].bitfield.disp64 = 0;
4907 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4908 if (i.types[op].bitfield.disp32
4909 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4911 /* If this operand is at most 32 bits, convert
4912 to a signed 32 bit number and don't use 64bit
4914 op_disp &= (((offsetT) 2 << 31) - 1);
4915 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4916 i.types[op].bitfield.disp64 = 0;
4919 if (!op_disp && i.types[op].bitfield.baseindex)
4921 i.types[op].bitfield.disp8 = 0;
4922 i.types[op].bitfield.disp16 = 0;
4923 i.types[op].bitfield.disp32 = 0;
4924 i.types[op].bitfield.disp32s = 0;
4925 i.types[op].bitfield.disp64 = 0;
4929 else if (flag_code == CODE_64BIT)
4931 if (fits_in_signed_long (op_disp))
4933 i.types[op].bitfield.disp64 = 0;
4934 i.types[op].bitfield.disp32s = 1;
4936 if (i.prefix[ADDR_PREFIX]
4937 && fits_in_unsigned_long (op_disp))
4938 i.types[op].bitfield.disp32 = 1;
4940 if ((i.types[op].bitfield.disp32
4941 || i.types[op].bitfield.disp32s
4942 || i.types[op].bitfield.disp16)
4943 && fits_in_disp8 (op_disp))
4944 i.types[op].bitfield.disp8 = 1;
4946 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4947 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4949 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4950 i.op[op].disps, 0, i.reloc[op]);
4951 i.types[op].bitfield.disp8 = 0;
4952 i.types[op].bitfield.disp16 = 0;
4953 i.types[op].bitfield.disp32 = 0;
4954 i.types[op].bitfield.disp32s = 0;
4955 i.types[op].bitfield.disp64 = 0;
4958 /* We only support 64bit displacement on constants. */
4959 i.types[op].bitfield.disp64 = 0;
4963 /* Check if operands are valid for the instruction. */
4966 check_VecOperands (const insn_template *t)
4970 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4972 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4973 any one operand are implicity requiring AVX512VL support if the actual
4974 operand size is YMMword or XMMword. Since this function runs after
4975 template matching, there's no need to check for YMMword/XMMword in
4977 cpu = cpu_flags_and (t->cpu_flags, avx512);
4978 if (!cpu_flags_all_zero (&cpu)
4979 && !t->cpu_flags.bitfield.cpuavx512vl
4980 && !cpu_arch_flags.bitfield.cpuavx512vl)
4982 for (op = 0; op < t->operands; ++op)
4984 if (t->operand_types[op].bitfield.zmmword
4985 && (i.types[op].bitfield.ymmword
4986 || i.types[op].bitfield.xmmword))
4988 i.error = unsupported;
4994 /* Without VSIB byte, we can't have a vector register for index. */
4995 if (!t->opcode_modifier.vecsib
4997 && (i.index_reg->reg_type.bitfield.xmmword
4998 || i.index_reg->reg_type.bitfield.ymmword
4999 || i.index_reg->reg_type.bitfield.zmmword))
5001 i.error = unsupported_vector_index_register;
5005 /* Check if default mask is allowed. */
5006 if (t->opcode_modifier.nodefmask
5007 && (!i.mask || i.mask->mask->reg_num == 0))
5009 i.error = no_default_mask;
5013 /* For VSIB byte, we need a vector register for index, and all vector
5014 registers must be distinct. */
5015 if (t->opcode_modifier.vecsib)
5018 || !((t->opcode_modifier.vecsib == VecSIB128
5019 && i.index_reg->reg_type.bitfield.xmmword)
5020 || (t->opcode_modifier.vecsib == VecSIB256
5021 && i.index_reg->reg_type.bitfield.ymmword)
5022 || (t->opcode_modifier.vecsib == VecSIB512
5023 && i.index_reg->reg_type.bitfield.zmmword)))
5025 i.error = invalid_vsib_address;
5029 gas_assert (i.reg_operands == 2 || i.mask);
5030 if (i.reg_operands == 2 && !i.mask)
5032 gas_assert (i.types[0].bitfield.regsimd);
5033 gas_assert (i.types[0].bitfield.xmmword
5034 || i.types[0].bitfield.ymmword);
5035 gas_assert (i.types[2].bitfield.regsimd);
5036 gas_assert (i.types[2].bitfield.xmmword
5037 || i.types[2].bitfield.ymmword);
5038 if (operand_check == check_none)
5040 if (register_number (i.op[0].regs)
5041 != register_number (i.index_reg)
5042 && register_number (i.op[2].regs)
5043 != register_number (i.index_reg)
5044 && register_number (i.op[0].regs)
5045 != register_number (i.op[2].regs))
5047 if (operand_check == check_error)
5049 i.error = invalid_vector_register_set;
5052 as_warn (_("mask, index, and destination registers should be distinct"));
5054 else if (i.reg_operands == 1 && i.mask)
5056 if (i.types[1].bitfield.regsimd
5057 && (i.types[1].bitfield.xmmword
5058 || i.types[1].bitfield.ymmword
5059 || i.types[1].bitfield.zmmword)
5060 && (register_number (i.op[1].regs)
5061 == register_number (i.index_reg)))
5063 if (operand_check == check_error)
5065 i.error = invalid_vector_register_set;
5068 if (operand_check != check_none)
5069 as_warn (_("index and destination registers should be distinct"));
5074 /* Check if broadcast is supported by the instruction and is applied
5075 to the memory operand. */
5078 i386_operand_type type, overlap;
5080 /* Check if specified broadcast is supported in this instruction,
5081 and it's applied to memory operand of DWORD or QWORD type. */
5082 op = i.broadcast->operand;
5083 if (!t->opcode_modifier.broadcast
5084 || !i.types[op].bitfield.mem
5085 || (!i.types[op].bitfield.unspecified
5086 && (t->operand_types[op].bitfield.dword
5087 ? !i.types[op].bitfield.dword
5088 : !i.types[op].bitfield.qword)))
5091 i.error = unsupported_broadcast;
5095 operand_type_set (&type, 0);
5096 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5099 type.bitfield.qword = 1;
5102 type.bitfield.xmmword = 1;
5105 type.bitfield.ymmword = 1;
5108 type.bitfield.zmmword = 1;
5114 overlap = operand_type_and (type, t->operand_types[op]);
5115 if (operand_type_all_zero (&overlap))
5118 if (t->opcode_modifier.checkregsize)
5122 type.bitfield.baseindex = 1;
5123 for (j = 0; j < i.operands; ++j)
5126 && !operand_type_register_match(i.types[j],
5127 t->operand_types[j],
5129 t->operand_types[op]))
5134 /* If broadcast is supported in this instruction, we need to check if
5135 operand of one-element size isn't specified without broadcast. */
5136 else if (t->opcode_modifier.broadcast && i.mem_operands)
5138 /* Find memory operand. */
5139 for (op = 0; op < i.operands; op++)
5140 if (operand_type_check (i.types[op], anymem))
5142 gas_assert (op < i.operands);
5143 /* Check size of the memory operand. */
5144 if (t->operand_types[op].bitfield.dword
5145 ? i.types[op].bitfield.dword
5146 : i.types[op].bitfield.qword)
5148 i.error = broadcast_needed;
5153 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5155 /* Check if requested masking is supported. */
5157 && (!t->opcode_modifier.masking
5159 && t->opcode_modifier.masking == MERGING_MASKING)))
5161 i.error = unsupported_masking;
5165 /* Check if masking is applied to dest operand. */
5166 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5168 i.error = mask_not_on_destination;
5175 if ((i.rounding->type != saeonly
5176 && !t->opcode_modifier.staticrounding)
5177 || (i.rounding->type == saeonly
5178 && (t->opcode_modifier.staticrounding
5179 || !t->opcode_modifier.sae)))
5181 i.error = unsupported_rc_sae;
5184 /* If the instruction has several immediate operands and one of
5185 them is rounding, the rounding operand should be the last
5186 immediate operand. */
5187 if (i.imm_operands > 1
5188 && i.rounding->operand != (int) (i.imm_operands - 1))
5190 i.error = rc_sae_operand_not_last_imm;
5195 /* Check vector Disp8 operand. */
5196 if (t->opcode_modifier.disp8memshift
5197 && i.disp_encoding != disp_encoding_32bit)
5200 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5202 i.memshift = t->opcode_modifier.disp8memshift;
5204 for (op = 0; op < i.operands; op++)
5205 if (operand_type_check (i.types[op], disp)
5206 && i.op[op].disps->X_op == O_constant)
5208 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5210 i.types[op].bitfield.disp8 = 1;
5213 i.types[op].bitfield.disp8 = 0;
5222 /* Check if operands are valid for the instruction. Update VEX
5226 VEX_check_operands (const insn_template *t)
5228 if (i.vec_encoding == vex_encoding_evex)
5230 /* This instruction must be encoded with EVEX prefix. */
5231 if (!is_evex_encoding (t))
5233 i.error = unsupported;
5239 if (!t->opcode_modifier.vex)
5241 /* This instruction template doesn't have VEX prefix. */
5242 if (i.vec_encoding != vex_encoding_default)
5244 i.error = unsupported;
5250 /* Only check VEX_Imm4, which must be the first operand. */
5251 if (t->operand_types[0].bitfield.vec_imm4)
5253 if (i.op[0].imms->X_op != O_constant
5254 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5260 /* Turn off Imm8 so that update_imm won't complain. */
5261 i.types[0] = vec_imm4;
5267 static const insn_template *
5268 match_template (char mnem_suffix)
5270 /* Points to template once we've found it. */
5271 const insn_template *t;
5272 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5273 i386_operand_type overlap4;
5274 unsigned int found_reverse_match;
5275 i386_opcode_modifier suffix_check, mnemsuf_check;
5276 i386_operand_type operand_types [MAX_OPERANDS];
5277 int addr_prefix_disp;
5279 unsigned int found_cpu_match;
5280 unsigned int check_register;
5281 enum i386_error specific_error = 0;
5283 #if MAX_OPERANDS != 5
5284 # error "MAX_OPERANDS must be 5."
5287 found_reverse_match = 0;
5288 addr_prefix_disp = -1;
5290 memset (&suffix_check, 0, sizeof (suffix_check));
5291 if (intel_syntax && i.broadcast)
5293 else if (i.suffix == BYTE_MNEM_SUFFIX)
5294 suffix_check.no_bsuf = 1;
5295 else if (i.suffix == WORD_MNEM_SUFFIX)
5296 suffix_check.no_wsuf = 1;
5297 else if (i.suffix == SHORT_MNEM_SUFFIX)
5298 suffix_check.no_ssuf = 1;
5299 else if (i.suffix == LONG_MNEM_SUFFIX)
5300 suffix_check.no_lsuf = 1;
5301 else if (i.suffix == QWORD_MNEM_SUFFIX)
5302 suffix_check.no_qsuf = 1;
5303 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5304 suffix_check.no_ldsuf = 1;
5306 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5309 switch (mnem_suffix)
5311 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5312 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5313 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5314 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5315 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5319 /* Must have right number of operands. */
5320 i.error = number_of_operands_mismatch;
5322 for (t = current_templates->start; t < current_templates->end; t++)
5324 addr_prefix_disp = -1;
5326 if (i.operands != t->operands)
5329 /* Check processor support. */
5330 i.error = unsupported;
5331 found_cpu_match = (cpu_flags_match (t)
5332 == CPU_FLAGS_PERFECT_MATCH);
5333 if (!found_cpu_match)
5336 /* Check AT&T mnemonic. */
5337 i.error = unsupported_with_intel_mnemonic;
5338 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5341 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5342 i.error = unsupported_syntax;
5343 if ((intel_syntax && t->opcode_modifier.attsyntax)
5344 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5345 || (intel64 && t->opcode_modifier.amd64)
5346 || (!intel64 && t->opcode_modifier.intel64))
5349 /* Check the suffix, except for some instructions in intel mode. */
5350 i.error = invalid_instruction_suffix;
5351 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5352 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5353 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5354 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5355 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5356 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5357 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5359 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5360 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5361 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5362 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5363 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5364 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5365 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5368 if (!operand_size_match (t))
5371 for (j = 0; j < MAX_OPERANDS; j++)
5372 operand_types[j] = t->operand_types[j];
5374 /* In general, don't allow 64-bit operands in 32-bit mode. */
5375 if (i.suffix == QWORD_MNEM_SUFFIX
5376 && flag_code != CODE_64BIT
5378 ? (!t->opcode_modifier.ignoresize
5379 && !intel_float_operand (t->name))
5380 : intel_float_operand (t->name) != 2)
5381 && ((!operand_types[0].bitfield.regmmx
5382 && !operand_types[0].bitfield.regsimd)
5383 || (!operand_types[t->operands > 1].bitfield.regmmx
5384 && !operand_types[t->operands > 1].bitfield.regsimd))
5385 && (t->base_opcode != 0x0fc7
5386 || t->extension_opcode != 1 /* cmpxchg8b */))
5389 /* In general, don't allow 32-bit operands on pre-386. */
5390 else if (i.suffix == LONG_MNEM_SUFFIX
5391 && !cpu_arch_flags.bitfield.cpui386
5393 ? (!t->opcode_modifier.ignoresize
5394 && !intel_float_operand (t->name))
5395 : intel_float_operand (t->name) != 2)
5396 && ((!operand_types[0].bitfield.regmmx
5397 && !operand_types[0].bitfield.regsimd)
5398 || (!operand_types[t->operands > 1].bitfield.regmmx
5399 && !operand_types[t->operands > 1].bitfield.regsimd)))
5402 /* Do not verify operands when there are none. */
5406 /* We've found a match; break out of loop. */
5410 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5411 into Disp32/Disp16/Disp32 operand. */
5412 if (i.prefix[ADDR_PREFIX] != 0)
5414 /* There should be only one Disp operand. */
5418 for (j = 0; j < MAX_OPERANDS; j++)
5420 if (operand_types[j].bitfield.disp16)
5422 addr_prefix_disp = j;
5423 operand_types[j].bitfield.disp32 = 1;
5424 operand_types[j].bitfield.disp16 = 0;
5430 for (j = 0; j < MAX_OPERANDS; j++)
5432 if (operand_types[j].bitfield.disp32)
5434 addr_prefix_disp = j;
5435 operand_types[j].bitfield.disp32 = 0;
5436 operand_types[j].bitfield.disp16 = 1;
5442 for (j = 0; j < MAX_OPERANDS; j++)
5444 if (operand_types[j].bitfield.disp64)
5446 addr_prefix_disp = j;
5447 operand_types[j].bitfield.disp64 = 0;
5448 operand_types[j].bitfield.disp32 = 1;
5456 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5457 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5460 /* We check register size if needed. */
5461 if (t->opcode_modifier.checkregsize)
5463 check_register = (1 << t->operands) - 1;
5465 check_register &= ~(1 << i.broadcast->operand);
5470 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5471 switch (t->operands)
5474 if (!operand_type_match (overlap0, i.types[0]))
5478 /* xchg %eax, %eax is a special case. It is an alias for nop
5479 only in 32bit mode and we can use opcode 0x90. In 64bit
5480 mode, we can't use 0x90 for xchg %eax, %eax since it should
5481 zero-extend %eax to %rax. */
5482 if (flag_code == CODE_64BIT
5483 && t->base_opcode == 0x90
5484 && operand_type_equal (&i.types [0], &acc32)
5485 && operand_type_equal (&i.types [1], &acc32))
5487 /* xrelease mov %eax, <disp> is another special case. It must not
5488 match the accumulator-only encoding of mov. */
5489 if (flag_code != CODE_64BIT
5491 && t->base_opcode == 0xa0
5492 && i.types[0].bitfield.acc
5493 && operand_type_check (i.types[1], anymem))
5495 /* If we want store form, we reverse direction of operands. */
5496 if (i.dir_encoding == dir_encoding_store
5497 && t->opcode_modifier.d)
5502 /* If we want store form, we skip the current load. */
5503 if (i.dir_encoding == dir_encoding_store
5504 && i.mem_operands == 0
5505 && t->opcode_modifier.load)
5510 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5511 if (!operand_type_match (overlap0, i.types[0])
5512 || !operand_type_match (overlap1, i.types[1])
5513 || ((check_register & 3) == 3
5514 && !operand_type_register_match (i.types[0],
5519 /* Check if other direction is valid ... */
5520 if (!t->opcode_modifier.d)
5524 /* Try reversing direction of operands. */
5525 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5526 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5527 if (!operand_type_match (overlap0, i.types[0])
5528 || !operand_type_match (overlap1, i.types[1])
5530 && !operand_type_register_match (i.types[0],
5535 /* Does not match either direction. */
5538 /* found_reverse_match holds which of D or FloatR
5540 if (!t->opcode_modifier.d)
5541 found_reverse_match = 0;
5542 else if (operand_types[0].bitfield.tbyte)
5543 found_reverse_match = Opcode_FloatD;
5545 found_reverse_match = Opcode_D;
5546 if (t->opcode_modifier.floatr)
5547 found_reverse_match |= Opcode_FloatR;
5551 /* Found a forward 2 operand match here. */
5552 switch (t->operands)
5555 overlap4 = operand_type_and (i.types[4],
5559 overlap3 = operand_type_and (i.types[3],
5563 overlap2 = operand_type_and (i.types[2],
5568 switch (t->operands)
5571 if (!operand_type_match (overlap4, i.types[4])
5572 || !operand_type_register_match (i.types[3],
5579 if (!operand_type_match (overlap3, i.types[3])
5580 || ((check_register & 0xa) == 0xa
5581 && !operand_type_register_match (i.types[1],
5585 || ((check_register & 0xc) == 0xc
5586 && !operand_type_register_match (i.types[2],
5593 /* Here we make use of the fact that there are no
5594 reverse match 3 operand instructions. */
5595 if (!operand_type_match (overlap2, i.types[2])
5596 || ((check_register & 5) == 5
5597 && !operand_type_register_match (i.types[0],
5601 || ((check_register & 6) == 6
5602 && !operand_type_register_match (i.types[1],
5610 /* Found either forward/reverse 2, 3 or 4 operand match here:
5611 slip through to break. */
5613 if (!found_cpu_match)
5615 found_reverse_match = 0;
5619 /* Check if vector and VEX operands are valid. */
5620 if (check_VecOperands (t) || VEX_check_operands (t))
5622 specific_error = i.error;
5626 /* We've found a match; break out of loop. */
5630 if (t == current_templates->end)
5632 /* We found no match. */
5633 const char *err_msg;
5634 switch (specific_error ? specific_error : i.error)
5638 case operand_size_mismatch:
5639 err_msg = _("operand size mismatch");
5641 case operand_type_mismatch:
5642 err_msg = _("operand type mismatch");
5644 case register_type_mismatch:
5645 err_msg = _("register type mismatch");
5647 case number_of_operands_mismatch:
5648 err_msg = _("number of operands mismatch");
5650 case invalid_instruction_suffix:
5651 err_msg = _("invalid instruction suffix");
5654 err_msg = _("constant doesn't fit in 4 bits");
5656 case unsupported_with_intel_mnemonic:
5657 err_msg = _("unsupported with Intel mnemonic");
5659 case unsupported_syntax:
5660 err_msg = _("unsupported syntax");
5663 as_bad (_("unsupported instruction `%s'"),
5664 current_templates->start->name);
5666 case invalid_vsib_address:
5667 err_msg = _("invalid VSIB address");
5669 case invalid_vector_register_set:
5670 err_msg = _("mask, index, and destination registers must be distinct");
5672 case unsupported_vector_index_register:
5673 err_msg = _("unsupported vector index register");
5675 case unsupported_broadcast:
5676 err_msg = _("unsupported broadcast");
5678 case broadcast_not_on_src_operand:
5679 err_msg = _("broadcast not on source memory operand");
5681 case broadcast_needed:
5682 err_msg = _("broadcast is needed for operand of such type");
5684 case unsupported_masking:
5685 err_msg = _("unsupported masking");
5687 case mask_not_on_destination:
5688 err_msg = _("mask not on destination operand");
5690 case no_default_mask:
5691 err_msg = _("default mask isn't allowed");
5693 case unsupported_rc_sae:
5694 err_msg = _("unsupported static rounding/sae");
5696 case rc_sae_operand_not_last_imm:
5698 err_msg = _("RC/SAE operand must precede immediate operands");
5700 err_msg = _("RC/SAE operand must follow immediate operands");
5702 case invalid_register_operand:
5703 err_msg = _("invalid register operand");
5706 as_bad (_("%s for `%s'"), err_msg,
5707 current_templates->start->name);
5711 if (!quiet_warnings)
5714 && (i.types[0].bitfield.jumpabsolute
5715 != operand_types[0].bitfield.jumpabsolute))
5717 as_warn (_("indirect %s without `*'"), t->name);
5720 if (t->opcode_modifier.isprefix
5721 && t->opcode_modifier.ignoresize)
5723 /* Warn them that a data or address size prefix doesn't
5724 affect assembly of the next line of code. */
5725 as_warn (_("stand-alone `%s' prefix"), t->name);
5729 /* Copy the template we found. */
5732 if (addr_prefix_disp != -1)
5733 i.tm.operand_types[addr_prefix_disp]
5734 = operand_types[addr_prefix_disp];
5736 if (found_reverse_match)
5738 /* If we found a reverse match we must alter the opcode
5739 direction bit. found_reverse_match holds bits to change
5740 (different for int & float insns). */
5742 i.tm.base_opcode ^= found_reverse_match;
5744 i.tm.operand_types[0] = operand_types[1];
5745 i.tm.operand_types[1] = operand_types[0];
5754 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5755 if (i.tm.operand_types[mem_op].bitfield.esseg)
5757 if (i.seg[0] != NULL && i.seg[0] != &es)
5759 as_bad (_("`%s' operand %d must use `%ses' segment"),
5765 /* There's only ever one segment override allowed per instruction.
5766 This instruction possibly has a legal segment override on the
5767 second operand, so copy the segment to where non-string
5768 instructions store it, allowing common code. */
5769 i.seg[0] = i.seg[1];
5771 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5773 if (i.seg[1] != NULL && i.seg[1] != &es)
5775 as_bad (_("`%s' operand %d must use `%ses' segment"),
5786 process_suffix (void)
5788 /* If matched instruction specifies an explicit instruction mnemonic
5790 if (i.tm.opcode_modifier.size16)
5791 i.suffix = WORD_MNEM_SUFFIX;
5792 else if (i.tm.opcode_modifier.size32)
5793 i.suffix = LONG_MNEM_SUFFIX;
5794 else if (i.tm.opcode_modifier.size64)
5795 i.suffix = QWORD_MNEM_SUFFIX;
5796 else if (i.reg_operands)
5798 /* If there's no instruction mnemonic suffix we try to invent one
5799 based on register operands. */
5802 /* We take i.suffix from the last register operand specified,
5803 Destination register type is more significant than source
5804 register type. crc32 in SSE4.2 prefers source register
5806 if (i.tm.base_opcode == 0xf20f38f1)
5808 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5809 i.suffix = WORD_MNEM_SUFFIX;
5810 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5811 i.suffix = LONG_MNEM_SUFFIX;
5812 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5813 i.suffix = QWORD_MNEM_SUFFIX;
5815 else if (i.tm.base_opcode == 0xf20f38f0)
5817 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5818 i.suffix = BYTE_MNEM_SUFFIX;
5825 if (i.tm.base_opcode == 0xf20f38f1
5826 || i.tm.base_opcode == 0xf20f38f0)
5828 /* We have to know the operand size for crc32. */
5829 as_bad (_("ambiguous memory operand size for `%s`"),
5834 for (op = i.operands; --op >= 0;)
5835 if (!i.tm.operand_types[op].bitfield.inoutportreg
5836 && !i.tm.operand_types[op].bitfield.shiftcount)
5838 if (!i.types[op].bitfield.reg)
5840 if (i.types[op].bitfield.byte)
5841 i.suffix = BYTE_MNEM_SUFFIX;
5842 else if (i.types[op].bitfield.word)
5843 i.suffix = WORD_MNEM_SUFFIX;
5844 else if (i.types[op].bitfield.dword)
5845 i.suffix = LONG_MNEM_SUFFIX;
5846 else if (i.types[op].bitfield.qword)
5847 i.suffix = QWORD_MNEM_SUFFIX;
5854 else if (i.suffix == BYTE_MNEM_SUFFIX)
5857 && i.tm.opcode_modifier.ignoresize
5858 && i.tm.opcode_modifier.no_bsuf)
5860 else if (!check_byte_reg ())
5863 else if (i.suffix == LONG_MNEM_SUFFIX)
5866 && i.tm.opcode_modifier.ignoresize
5867 && i.tm.opcode_modifier.no_lsuf
5868 && !i.tm.opcode_modifier.todword
5869 && !i.tm.opcode_modifier.toqword)
5871 else if (!check_long_reg ())
5874 else if (i.suffix == QWORD_MNEM_SUFFIX)
5877 && i.tm.opcode_modifier.ignoresize
5878 && i.tm.opcode_modifier.no_qsuf
5879 && !i.tm.opcode_modifier.todword
5880 && !i.tm.opcode_modifier.toqword)
5882 else if (!check_qword_reg ())
5885 else if (i.suffix == WORD_MNEM_SUFFIX)
5888 && i.tm.opcode_modifier.ignoresize
5889 && i.tm.opcode_modifier.no_wsuf)
5891 else if (!check_word_reg ())
5894 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5895 /* Do nothing if the instruction is going to ignore the prefix. */
5900 else if (i.tm.opcode_modifier.defaultsize
5902 /* exclude fldenv/frstor/fsave/fstenv */
5903 && i.tm.opcode_modifier.no_ssuf)
5905 i.suffix = stackop_size;
5907 else if (intel_syntax
5909 && (i.tm.operand_types[0].bitfield.jumpabsolute
5910 || i.tm.opcode_modifier.jumpbyte
5911 || i.tm.opcode_modifier.jumpintersegment
5912 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5913 && i.tm.extension_opcode <= 3)))
5918 if (!i.tm.opcode_modifier.no_qsuf)
5920 i.suffix = QWORD_MNEM_SUFFIX;
5925 if (!i.tm.opcode_modifier.no_lsuf)
5926 i.suffix = LONG_MNEM_SUFFIX;
5929 if (!i.tm.opcode_modifier.no_wsuf)
5930 i.suffix = WORD_MNEM_SUFFIX;
5939 if (i.tm.opcode_modifier.w)
5941 as_bad (_("no instruction mnemonic suffix given and "
5942 "no register operands; can't size instruction"));
5948 unsigned int suffixes;
5950 suffixes = !i.tm.opcode_modifier.no_bsuf;
5951 if (!i.tm.opcode_modifier.no_wsuf)
5953 if (!i.tm.opcode_modifier.no_lsuf)
5955 if (!i.tm.opcode_modifier.no_ldsuf)
5957 if (!i.tm.opcode_modifier.no_ssuf)
5959 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5962 /* There are more than suffix matches. */
5963 if (i.tm.opcode_modifier.w
5964 || ((suffixes & (suffixes - 1))
5965 && !i.tm.opcode_modifier.defaultsize
5966 && !i.tm.opcode_modifier.ignoresize))
5968 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5974 /* Change the opcode based on the operand size given by i.suffix. */
5977 /* Size floating point instruction. */
5978 case LONG_MNEM_SUFFIX:
5979 if (i.tm.opcode_modifier.floatmf)
5981 i.tm.base_opcode ^= 4;
5985 case WORD_MNEM_SUFFIX:
5986 case QWORD_MNEM_SUFFIX:
5987 /* It's not a byte, select word/dword operation. */
5988 if (i.tm.opcode_modifier.w)
5990 if (i.tm.opcode_modifier.shortform)
5991 i.tm.base_opcode |= 8;
5993 i.tm.base_opcode |= 1;
5996 case SHORT_MNEM_SUFFIX:
5997 /* Now select between word & dword operations via the operand
5998 size prefix, except for instructions that will ignore this
6000 if (i.reg_operands > 0
6001 && i.types[0].bitfield.reg
6002 && i.tm.opcode_modifier.addrprefixopreg
6003 && (i.tm.opcode_modifier.immext
6004 || i.operands == 1))
6006 /* The address size override prefix changes the size of the
6008 if ((flag_code == CODE_32BIT
6009 && i.op[0].regs->reg_type.bitfield.word)
6010 || (flag_code != CODE_32BIT
6011 && i.op[0].regs->reg_type.bitfield.dword))
6012 if (!add_prefix (ADDR_PREFIX_OPCODE))
6015 else if (i.suffix != QWORD_MNEM_SUFFIX
6016 && !i.tm.opcode_modifier.ignoresize
6017 && !i.tm.opcode_modifier.floatmf
6018 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6019 || (flag_code == CODE_64BIT
6020 && i.tm.opcode_modifier.jumpbyte)))
6022 unsigned int prefix = DATA_PREFIX_OPCODE;
6024 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6025 prefix = ADDR_PREFIX_OPCODE;
6027 if (!add_prefix (prefix))
6031 /* Set mode64 for an operand. */
6032 if (i.suffix == QWORD_MNEM_SUFFIX
6033 && flag_code == CODE_64BIT
6034 && !i.tm.opcode_modifier.norex64
6035 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6037 && ! (i.operands == 2
6038 && i.tm.base_opcode == 0x90
6039 && i.tm.extension_opcode == None
6040 && operand_type_equal (&i.types [0], &acc64)
6041 && operand_type_equal (&i.types [1], &acc64)))
6051 check_byte_reg (void)
6055 for (op = i.operands; --op >= 0;)
6057 /* Skip non-register operands. */
6058 if (!i.types[op].bitfield.reg)
6061 /* If this is an eight bit register, it's OK. If it's the 16 or
6062 32 bit version of an eight bit register, we will just use the
6063 low portion, and that's OK too. */
6064 if (i.types[op].bitfield.byte)
6067 /* I/O port address operands are OK too. */
6068 if (i.tm.operand_types[op].bitfield.inoutportreg)
6071 /* crc32 doesn't generate this warning. */
6072 if (i.tm.base_opcode == 0xf20f38f0)
6075 if ((i.types[op].bitfield.word
6076 || i.types[op].bitfield.dword
6077 || i.types[op].bitfield.qword)
6078 && i.op[op].regs->reg_num < 4
6079 /* Prohibit these changes in 64bit mode, since the lowering
6080 would be more complicated. */
6081 && flag_code != CODE_64BIT)
6083 #if REGISTER_WARNINGS
6084 if (!quiet_warnings)
6085 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6087 (i.op[op].regs + (i.types[op].bitfield.word
6088 ? REGNAM_AL - REGNAM_AX
6089 : REGNAM_AL - REGNAM_EAX))->reg_name,
6091 i.op[op].regs->reg_name,
6096 /* Any other register is bad. */
6097 if (i.types[op].bitfield.reg
6098 || i.types[op].bitfield.regmmx
6099 || i.types[op].bitfield.regsimd
6100 || i.types[op].bitfield.sreg2
6101 || i.types[op].bitfield.sreg3
6102 || i.types[op].bitfield.control
6103 || i.types[op].bitfield.debug
6104 || i.types[op].bitfield.test)
6106 as_bad (_("`%s%s' not allowed with `%s%c'"),
6108 i.op[op].regs->reg_name,
6118 check_long_reg (void)
6122 for (op = i.operands; --op >= 0;)
6123 /* Skip non-register operands. */
6124 if (!i.types[op].bitfield.reg)
6126 /* Reject eight bit registers, except where the template requires
6127 them. (eg. movzb) */
6128 else if (i.types[op].bitfield.byte
6129 && (i.tm.operand_types[op].bitfield.reg
6130 || i.tm.operand_types[op].bitfield.acc)
6131 && (i.tm.operand_types[op].bitfield.word
6132 || i.tm.operand_types[op].bitfield.dword))
6134 as_bad (_("`%s%s' not allowed with `%s%c'"),
6136 i.op[op].regs->reg_name,
6141 /* Warn if the e prefix on a general reg is missing. */
6142 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6143 && i.types[op].bitfield.word
6144 && (i.tm.operand_types[op].bitfield.reg
6145 || i.tm.operand_types[op].bitfield.acc)
6146 && i.tm.operand_types[op].bitfield.dword)
6148 /* Prohibit these changes in the 64bit mode, since the
6149 lowering is more complicated. */
6150 if (flag_code == CODE_64BIT)
6152 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6153 register_prefix, i.op[op].regs->reg_name,
6157 #if REGISTER_WARNINGS
6158 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6160 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6161 register_prefix, i.op[op].regs->reg_name, i.suffix);
6164 /* Warn if the r prefix on a general reg is present. */
6165 else if (i.types[op].bitfield.qword
6166 && (i.tm.operand_types[op].bitfield.reg
6167 || i.tm.operand_types[op].bitfield.acc)
6168 && i.tm.operand_types[op].bitfield.dword)
6171 && i.tm.opcode_modifier.toqword
6172 && !i.types[0].bitfield.regsimd)
6174 /* Convert to QWORD. We want REX byte. */
6175 i.suffix = QWORD_MNEM_SUFFIX;
6179 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6180 register_prefix, i.op[op].regs->reg_name,
6189 check_qword_reg (void)
6193 for (op = i.operands; --op >= 0; )
6194 /* Skip non-register operands. */
6195 if (!i.types[op].bitfield.reg)
6197 /* Reject eight bit registers, except where the template requires
6198 them. (eg. movzb) */
6199 else if (i.types[op].bitfield.byte
6200 && (i.tm.operand_types[op].bitfield.reg
6201 || i.tm.operand_types[op].bitfield.acc)
6202 && (i.tm.operand_types[op].bitfield.word
6203 || i.tm.operand_types[op].bitfield.dword))
6205 as_bad (_("`%s%s' not allowed with `%s%c'"),
6207 i.op[op].regs->reg_name,
6212 /* Warn if the r prefix on a general reg is missing. */
6213 else if ((i.types[op].bitfield.word
6214 || i.types[op].bitfield.dword)
6215 && (i.tm.operand_types[op].bitfield.reg
6216 || i.tm.operand_types[op].bitfield.acc)
6217 && i.tm.operand_types[op].bitfield.qword)
6219 /* Prohibit these changes in the 64bit mode, since the
6220 lowering is more complicated. */
6222 && i.tm.opcode_modifier.todword
6223 && !i.types[0].bitfield.regsimd)
6225 /* Convert to DWORD. We don't want REX byte. */
6226 i.suffix = LONG_MNEM_SUFFIX;
6230 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6231 register_prefix, i.op[op].regs->reg_name,
6240 check_word_reg (void)
6243 for (op = i.operands; --op >= 0;)
6244 /* Skip non-register operands. */
6245 if (!i.types[op].bitfield.reg)
6247 /* Reject eight bit registers, except where the template requires
6248 them. (eg. movzb) */
6249 else if (i.types[op].bitfield.byte
6250 && (i.tm.operand_types[op].bitfield.reg
6251 || i.tm.operand_types[op].bitfield.acc)
6252 && (i.tm.operand_types[op].bitfield.word
6253 || i.tm.operand_types[op].bitfield.dword))
6255 as_bad (_("`%s%s' not allowed with `%s%c'"),
6257 i.op[op].regs->reg_name,
6262 /* Warn if the e or r prefix on a general reg is present. */
6263 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6264 && (i.types[op].bitfield.dword
6265 || i.types[op].bitfield.qword)
6266 && (i.tm.operand_types[op].bitfield.reg
6267 || i.tm.operand_types[op].bitfield.acc)
6268 && i.tm.operand_types[op].bitfield.word)
6270 /* Prohibit these changes in the 64bit mode, since the
6271 lowering is more complicated. */
6272 if (flag_code == CODE_64BIT)
6274 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6275 register_prefix, i.op[op].regs->reg_name,
6279 #if REGISTER_WARNINGS
6280 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6282 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6283 register_prefix, i.op[op].regs->reg_name, i.suffix);
6290 update_imm (unsigned int j)
6292 i386_operand_type overlap = i.types[j];
6293 if ((overlap.bitfield.imm8
6294 || overlap.bitfield.imm8s
6295 || overlap.bitfield.imm16
6296 || overlap.bitfield.imm32
6297 || overlap.bitfield.imm32s
6298 || overlap.bitfield.imm64)
6299 && !operand_type_equal (&overlap, &imm8)
6300 && !operand_type_equal (&overlap, &imm8s)
6301 && !operand_type_equal (&overlap, &imm16)
6302 && !operand_type_equal (&overlap, &imm32)
6303 && !operand_type_equal (&overlap, &imm32s)
6304 && !operand_type_equal (&overlap, &imm64))
6308 i386_operand_type temp;
6310 operand_type_set (&temp, 0);
6311 if (i.suffix == BYTE_MNEM_SUFFIX)
6313 temp.bitfield.imm8 = overlap.bitfield.imm8;
6314 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6316 else if (i.suffix == WORD_MNEM_SUFFIX)
6317 temp.bitfield.imm16 = overlap.bitfield.imm16;
6318 else if (i.suffix == QWORD_MNEM_SUFFIX)
6320 temp.bitfield.imm64 = overlap.bitfield.imm64;
6321 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6324 temp.bitfield.imm32 = overlap.bitfield.imm32;
6327 else if (operand_type_equal (&overlap, &imm16_32_32s)
6328 || operand_type_equal (&overlap, &imm16_32)
6329 || operand_type_equal (&overlap, &imm16_32s))
6331 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6336 if (!operand_type_equal (&overlap, &imm8)
6337 && !operand_type_equal (&overlap, &imm8s)
6338 && !operand_type_equal (&overlap, &imm16)
6339 && !operand_type_equal (&overlap, &imm32)
6340 && !operand_type_equal (&overlap, &imm32s)
6341 && !operand_type_equal (&overlap, &imm64))
6343 as_bad (_("no instruction mnemonic suffix given; "
6344 "can't determine immediate size"));
6348 i.types[j] = overlap;
6358 /* Update the first 2 immediate operands. */
6359 n = i.operands > 2 ? 2 : i.operands;
6362 for (j = 0; j < n; j++)
6363 if (update_imm (j) == 0)
6366 /* The 3rd operand can't be immediate operand. */
6367 gas_assert (operand_type_check (i.types[2], imm) == 0);
6374 process_operands (void)
6376 /* Default segment register this instruction will use for memory
6377 accesses. 0 means unknown. This is only for optimizing out
6378 unnecessary segment overrides. */
6379 const seg_entry *default_seg = 0;
6381 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6383 unsigned int dupl = i.operands;
6384 unsigned int dest = dupl - 1;
6387 /* The destination must be an xmm register. */
6388 gas_assert (i.reg_operands
6389 && MAX_OPERANDS > dupl
6390 && operand_type_equal (&i.types[dest], ®xmm));
6392 if (i.tm.operand_types[0].bitfield.acc
6393 && i.tm.operand_types[0].bitfield.xmmword)
6395 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6397 /* Keep xmm0 for instructions with VEX prefix and 3
6399 i.tm.operand_types[0].bitfield.acc = 0;
6400 i.tm.operand_types[0].bitfield.regsimd = 1;
6405 /* We remove the first xmm0 and keep the number of
6406 operands unchanged, which in fact duplicates the
6408 for (j = 1; j < i.operands; j++)
6410 i.op[j - 1] = i.op[j];
6411 i.types[j - 1] = i.types[j];
6412 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6416 else if (i.tm.opcode_modifier.implicit1stxmm0)
6418 gas_assert ((MAX_OPERANDS - 1) > dupl
6419 && (i.tm.opcode_modifier.vexsources
6422 /* Add the implicit xmm0 for instructions with VEX prefix
6424 for (j = i.operands; j > 0; j--)
6426 i.op[j] = i.op[j - 1];
6427 i.types[j] = i.types[j - 1];
6428 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6431 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6432 i.types[0] = regxmm;
6433 i.tm.operand_types[0] = regxmm;
6436 i.reg_operands += 2;
6441 i.op[dupl] = i.op[dest];
6442 i.types[dupl] = i.types[dest];
6443 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6452 i.op[dupl] = i.op[dest];
6453 i.types[dupl] = i.types[dest];
6454 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6457 if (i.tm.opcode_modifier.immext)
6460 else if (i.tm.operand_types[0].bitfield.acc
6461 && i.tm.operand_types[0].bitfield.xmmword)
6465 for (j = 1; j < i.operands; j++)
6467 i.op[j - 1] = i.op[j];
6468 i.types[j - 1] = i.types[j];
6470 /* We need to adjust fields in i.tm since they are used by
6471 build_modrm_byte. */
6472 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6479 else if (i.tm.opcode_modifier.implicitquadgroup)
6481 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6483 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6484 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6485 regnum = register_number (i.op[1].regs);
6486 first_reg_in_group = regnum & ~3;
6487 last_reg_in_group = first_reg_in_group + 3;
6488 if (regnum != first_reg_in_group)
6489 as_warn (_("source register `%s%s' implicitly denotes"
6490 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6491 register_prefix, i.op[1].regs->reg_name,
6492 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6493 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6496 else if (i.tm.opcode_modifier.regkludge)
6498 /* The imul $imm, %reg instruction is converted into
6499 imul $imm, %reg, %reg, and the clr %reg instruction
6500 is converted into xor %reg, %reg. */
6502 unsigned int first_reg_op;
6504 if (operand_type_check (i.types[0], reg))
6508 /* Pretend we saw the extra register operand. */
6509 gas_assert (i.reg_operands == 1
6510 && i.op[first_reg_op + 1].regs == 0);
6511 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6512 i.types[first_reg_op + 1] = i.types[first_reg_op];
6517 if (i.tm.opcode_modifier.shortform)
6519 if (i.types[0].bitfield.sreg2
6520 || i.types[0].bitfield.sreg3)
6522 if (i.tm.base_opcode == POP_SEG_SHORT
6523 && i.op[0].regs->reg_num == 1)
6525 as_bad (_("you can't `pop %scs'"), register_prefix);
6528 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6529 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6534 /* The register or float register operand is in operand
6538 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6539 || operand_type_check (i.types[0], reg))
6543 /* Register goes in low 3 bits of opcode. */
6544 i.tm.base_opcode |= i.op[op].regs->reg_num;
6545 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6547 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6549 /* Warn about some common errors, but press on regardless.
6550 The first case can be generated by gcc (<= 2.8.1). */
6551 if (i.operands == 2)
6553 /* Reversed arguments on faddp, fsubp, etc. */
6554 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6555 register_prefix, i.op[!intel_syntax].regs->reg_name,
6556 register_prefix, i.op[intel_syntax].regs->reg_name);
6560 /* Extraneous `l' suffix on fp insn. */
6561 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6562 register_prefix, i.op[0].regs->reg_name);
6567 else if (i.tm.opcode_modifier.modrm)
6569 /* The opcode is completed (modulo i.tm.extension_opcode which
6570 must be put into the modrm byte). Now, we make the modrm and
6571 index base bytes based on all the info we've collected. */
6573 default_seg = build_modrm_byte ();
6575 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6579 else if (i.tm.opcode_modifier.isstring)
6581 /* For the string instructions that allow a segment override
6582 on one of their operands, the default segment is ds. */
6586 if (i.tm.base_opcode == 0x8d /* lea */
6589 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6591 /* If a segment was explicitly specified, and the specified segment
6592 is not the default, use an opcode prefix to select it. If we
6593 never figured out what the default segment is, then default_seg
6594 will be zero at this point, and the specified segment prefix will
6596 if ((i.seg[0]) && (i.seg[0] != default_seg))
6598 if (!add_prefix (i.seg[0]->seg_prefix))
6604 static const seg_entry *
6605 build_modrm_byte (void)
6607 const seg_entry *default_seg = 0;
6608 unsigned int source, dest;
6611 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6614 unsigned int nds, reg_slot;
6617 dest = i.operands - 1;
6620 /* There are 2 kinds of instructions:
6621 1. 5 operands: 4 register operands or 3 register operands
6622 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6623 VexW0 or VexW1. The destination must be either XMM, YMM or
6625 2. 4 operands: 4 register operands or 3 register operands
6626 plus 1 memory operand, with VexXDS. */
6627 gas_assert ((i.reg_operands == 4
6628 || (i.reg_operands == 3 && i.mem_operands == 1))
6629 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6630 && i.tm.opcode_modifier.vexw
6631 && i.tm.operand_types[dest].bitfield.regsimd);
6633 /* If VexW1 is set, the first non-immediate operand is the source and
6634 the second non-immediate one is encoded in the immediate operand. */
6635 if (i.tm.opcode_modifier.vexw == VEXW1)
6637 source = i.imm_operands;
6638 reg_slot = i.imm_operands + 1;
6642 source = i.imm_operands + 1;
6643 reg_slot = i.imm_operands;
6646 if (i.imm_operands == 0)
6648 /* When there is no immediate operand, generate an 8bit
6649 immediate operand to encode the first operand. */
6650 exp = &im_expressions[i.imm_operands++];
6651 i.op[i.operands].imms = exp;
6652 i.types[i.operands] = imm8;
6655 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6656 exp->X_op = O_constant;
6657 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6658 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6662 unsigned int imm_slot;
6664 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6666 if (i.tm.opcode_modifier.immext)
6668 /* When ImmExt is set, the immediate byte is the last
6670 imm_slot = i.operands - 1;
6678 /* Turn on Imm8 so that output_imm will generate it. */
6679 i.types[imm_slot].bitfield.imm8 = 1;
6682 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6683 i.op[imm_slot].imms->X_add_number
6684 |= register_number (i.op[reg_slot].regs) << 4;
6685 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6688 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6689 i.vex.register_specifier = i.op[nds].regs;
6694 /* i.reg_operands MUST be the number of real register operands;
6695 implicit registers do not count. If there are 3 register
6696 operands, it must be a instruction with VexNDS. For a
6697 instruction with VexNDD, the destination register is encoded
6698 in VEX prefix. If there are 4 register operands, it must be
6699 a instruction with VEX prefix and 3 sources. */
6700 if (i.mem_operands == 0
6701 && ((i.reg_operands == 2
6702 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6703 || (i.reg_operands == 3
6704 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6705 || (i.reg_operands == 4 && vex_3_sources)))
6713 /* When there are 3 operands, one of them may be immediate,
6714 which may be the first or the last operand. Otherwise,
6715 the first operand must be shift count register (cl) or it
6716 is an instruction with VexNDS. */
6717 gas_assert (i.imm_operands == 1
6718 || (i.imm_operands == 0
6719 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6720 || i.types[0].bitfield.shiftcount)));
6721 if (operand_type_check (i.types[0], imm)
6722 || i.types[0].bitfield.shiftcount)
6728 /* When there are 4 operands, the first two must be 8bit
6729 immediate operands. The source operand will be the 3rd
6732 For instructions with VexNDS, if the first operand
6733 an imm8, the source operand is the 2nd one. If the last
6734 operand is imm8, the source operand is the first one. */
6735 gas_assert ((i.imm_operands == 2
6736 && i.types[0].bitfield.imm8
6737 && i.types[1].bitfield.imm8)
6738 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6739 && i.imm_operands == 1
6740 && (i.types[0].bitfield.imm8
6741 || i.types[i.operands - 1].bitfield.imm8
6743 if (i.imm_operands == 2)
6747 if (i.types[0].bitfield.imm8)
6754 if (is_evex_encoding (&i.tm))
6756 /* For EVEX instructions, when there are 5 operands, the
6757 first one must be immediate operand. If the second one
6758 is immediate operand, the source operand is the 3th
6759 one. If the last one is immediate operand, the source
6760 operand is the 2nd one. */
6761 gas_assert (i.imm_operands == 2
6762 && i.tm.opcode_modifier.sae
6763 && operand_type_check (i.types[0], imm));
6764 if (operand_type_check (i.types[1], imm))
6766 else if (operand_type_check (i.types[4], imm))
6780 /* RC/SAE operand could be between DEST and SRC. That happens
6781 when one operand is GPR and the other one is XMM/YMM/ZMM
6783 if (i.rounding && i.rounding->operand == (int) dest)
6786 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6788 /* For instructions with VexNDS, the register-only source
6789 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6790 register. It is encoded in VEX prefix. We need to
6791 clear RegMem bit before calling operand_type_equal. */
6793 i386_operand_type op;
6796 /* Check register-only source operand when two source
6797 operands are swapped. */
6798 if (!i.tm.operand_types[source].bitfield.baseindex
6799 && i.tm.operand_types[dest].bitfield.baseindex)
6807 op = i.tm.operand_types[vvvv];
6808 op.bitfield.regmem = 0;
6809 if ((dest + 1) >= i.operands
6810 || ((!op.bitfield.reg
6811 || (!op.bitfield.dword && !op.bitfield.qword))
6812 && !op.bitfield.regsimd
6813 && !operand_type_equal (&op, ®mask)))
6815 i.vex.register_specifier = i.op[vvvv].regs;
6821 /* One of the register operands will be encoded in the i.tm.reg
6822 field, the other in the combined i.tm.mode and i.tm.regmem
6823 fields. If no form of this instruction supports a memory
6824 destination operand, then we assume the source operand may
6825 sometimes be a memory operand and so we need to store the
6826 destination in the i.rm.reg field. */
6827 if (!i.tm.operand_types[dest].bitfield.regmem
6828 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6830 i.rm.reg = i.op[dest].regs->reg_num;
6831 i.rm.regmem = i.op[source].regs->reg_num;
6832 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6834 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6836 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6838 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6843 i.rm.reg = i.op[source].regs->reg_num;
6844 i.rm.regmem = i.op[dest].regs->reg_num;
6845 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6847 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6849 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6851 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6854 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6856 if (!i.types[0].bitfield.control
6857 && !i.types[1].bitfield.control)
6859 i.rex &= ~(REX_R | REX_B);
6860 add_prefix (LOCK_PREFIX_OPCODE);
6864 { /* If it's not 2 reg operands... */
6869 unsigned int fake_zero_displacement = 0;
6872 for (op = 0; op < i.operands; op++)
6873 if (operand_type_check (i.types[op], anymem))
6875 gas_assert (op < i.operands);
6877 if (i.tm.opcode_modifier.vecsib)
6879 if (i.index_reg->reg_num == RegEiz
6880 || i.index_reg->reg_num == RegRiz)
6883 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6886 i.sib.base = NO_BASE_REGISTER;
6887 i.sib.scale = i.log2_scale_factor;
6888 i.types[op].bitfield.disp8 = 0;
6889 i.types[op].bitfield.disp16 = 0;
6890 i.types[op].bitfield.disp64 = 0;
6891 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6893 /* Must be 32 bit */
6894 i.types[op].bitfield.disp32 = 1;
6895 i.types[op].bitfield.disp32s = 0;
6899 i.types[op].bitfield.disp32 = 0;
6900 i.types[op].bitfield.disp32s = 1;
6903 i.sib.index = i.index_reg->reg_num;
6904 if ((i.index_reg->reg_flags & RegRex) != 0)
6906 if ((i.index_reg->reg_flags & RegVRex) != 0)
6912 if (i.base_reg == 0)
6915 if (!i.disp_operands)
6916 fake_zero_displacement = 1;
6917 if (i.index_reg == 0)
6919 i386_operand_type newdisp;
6921 gas_assert (!i.tm.opcode_modifier.vecsib);
6922 /* Operand is just <disp> */
6923 if (flag_code == CODE_64BIT)
6925 /* 64bit mode overwrites the 32bit absolute
6926 addressing by RIP relative addressing and
6927 absolute addressing is encoded by one of the
6928 redundant SIB forms. */
6929 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6930 i.sib.base = NO_BASE_REGISTER;
6931 i.sib.index = NO_INDEX_REGISTER;
6932 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6934 else if ((flag_code == CODE_16BIT)
6935 ^ (i.prefix[ADDR_PREFIX] != 0))
6937 i.rm.regmem = NO_BASE_REGISTER_16;
6942 i.rm.regmem = NO_BASE_REGISTER;
6945 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6946 i.types[op] = operand_type_or (i.types[op], newdisp);
6948 else if (!i.tm.opcode_modifier.vecsib)
6950 /* !i.base_reg && i.index_reg */
6951 if (i.index_reg->reg_num == RegEiz
6952 || i.index_reg->reg_num == RegRiz)
6953 i.sib.index = NO_INDEX_REGISTER;
6955 i.sib.index = i.index_reg->reg_num;
6956 i.sib.base = NO_BASE_REGISTER;
6957 i.sib.scale = i.log2_scale_factor;
6958 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6959 i.types[op].bitfield.disp8 = 0;
6960 i.types[op].bitfield.disp16 = 0;
6961 i.types[op].bitfield.disp64 = 0;
6962 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6964 /* Must be 32 bit */
6965 i.types[op].bitfield.disp32 = 1;
6966 i.types[op].bitfield.disp32s = 0;
6970 i.types[op].bitfield.disp32 = 0;
6971 i.types[op].bitfield.disp32s = 1;
6973 if ((i.index_reg->reg_flags & RegRex) != 0)
6977 /* RIP addressing for 64bit mode. */
6978 else if (i.base_reg->reg_num == RegRip ||
6979 i.base_reg->reg_num == RegEip)
6981 gas_assert (!i.tm.opcode_modifier.vecsib);
6982 i.rm.regmem = NO_BASE_REGISTER;
6983 i.types[op].bitfield.disp8 = 0;
6984 i.types[op].bitfield.disp16 = 0;
6985 i.types[op].bitfield.disp32 = 0;
6986 i.types[op].bitfield.disp32s = 1;
6987 i.types[op].bitfield.disp64 = 0;
6988 i.flags[op] |= Operand_PCrel;
6989 if (! i.disp_operands)
6990 fake_zero_displacement = 1;
6992 else if (i.base_reg->reg_type.bitfield.word)
6994 gas_assert (!i.tm.opcode_modifier.vecsib);
6995 switch (i.base_reg->reg_num)
6998 if (i.index_reg == 0)
7000 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7001 i.rm.regmem = i.index_reg->reg_num - 6;
7005 if (i.index_reg == 0)
7008 if (operand_type_check (i.types[op], disp) == 0)
7010 /* fake (%bp) into 0(%bp) */
7011 i.types[op].bitfield.disp8 = 1;
7012 fake_zero_displacement = 1;
7015 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7016 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7018 default: /* (%si) -> 4 or (%di) -> 5 */
7019 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7021 i.rm.mode = mode_from_disp_size (i.types[op]);
7023 else /* i.base_reg and 32/64 bit mode */
7025 if (flag_code == CODE_64BIT
7026 && operand_type_check (i.types[op], disp))
7028 i.types[op].bitfield.disp16 = 0;
7029 i.types[op].bitfield.disp64 = 0;
7030 if (i.prefix[ADDR_PREFIX] == 0)
7032 i.types[op].bitfield.disp32 = 0;
7033 i.types[op].bitfield.disp32s = 1;
7037 i.types[op].bitfield.disp32 = 1;
7038 i.types[op].bitfield.disp32s = 0;
7042 if (!i.tm.opcode_modifier.vecsib)
7043 i.rm.regmem = i.base_reg->reg_num;
7044 if ((i.base_reg->reg_flags & RegRex) != 0)
7046 i.sib.base = i.base_reg->reg_num;
7047 /* x86-64 ignores REX prefix bit here to avoid decoder
7049 if (!(i.base_reg->reg_flags & RegRex)
7050 && (i.base_reg->reg_num == EBP_REG_NUM
7051 || i.base_reg->reg_num == ESP_REG_NUM))
7053 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7055 fake_zero_displacement = 1;
7056 i.types[op].bitfield.disp8 = 1;
7058 i.sib.scale = i.log2_scale_factor;
7059 if (i.index_reg == 0)
7061 gas_assert (!i.tm.opcode_modifier.vecsib);
7062 /* <disp>(%esp) becomes two byte modrm with no index
7063 register. We've already stored the code for esp
7064 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7065 Any base register besides %esp will not use the
7066 extra modrm byte. */
7067 i.sib.index = NO_INDEX_REGISTER;
7069 else if (!i.tm.opcode_modifier.vecsib)
7071 if (i.index_reg->reg_num == RegEiz
7072 || i.index_reg->reg_num == RegRiz)
7073 i.sib.index = NO_INDEX_REGISTER;
7075 i.sib.index = i.index_reg->reg_num;
7076 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7077 if ((i.index_reg->reg_flags & RegRex) != 0)
7082 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7083 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7087 if (!fake_zero_displacement
7091 fake_zero_displacement = 1;
7092 if (i.disp_encoding == disp_encoding_8bit)
7093 i.types[op].bitfield.disp8 = 1;
7095 i.types[op].bitfield.disp32 = 1;
7097 i.rm.mode = mode_from_disp_size (i.types[op]);
7101 if (fake_zero_displacement)
7103 /* Fakes a zero displacement assuming that i.types[op]
7104 holds the correct displacement size. */
7107 gas_assert (i.op[op].disps == 0);
7108 exp = &disp_expressions[i.disp_operands++];
7109 i.op[op].disps = exp;
7110 exp->X_op = O_constant;
7111 exp->X_add_number = 0;
7112 exp->X_add_symbol = (symbolS *) 0;
7113 exp->X_op_symbol = (symbolS *) 0;
7121 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7123 if (operand_type_check (i.types[0], imm))
7124 i.vex.register_specifier = NULL;
7127 /* VEX.vvvv encodes one of the sources when the first
7128 operand is not an immediate. */
7129 if (i.tm.opcode_modifier.vexw == VEXW0)
7130 i.vex.register_specifier = i.op[0].regs;
7132 i.vex.register_specifier = i.op[1].regs;
7135 /* Destination is a XMM register encoded in the ModRM.reg
7137 i.rm.reg = i.op[2].regs->reg_num;
7138 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7141 /* ModRM.rm and VEX.B encodes the other source. */
7142 if (!i.mem_operands)
7146 if (i.tm.opcode_modifier.vexw == VEXW0)
7147 i.rm.regmem = i.op[1].regs->reg_num;
7149 i.rm.regmem = i.op[0].regs->reg_num;
7151 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7155 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7157 i.vex.register_specifier = i.op[2].regs;
7158 if (!i.mem_operands)
7161 i.rm.regmem = i.op[1].regs->reg_num;
7162 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7166 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7167 (if any) based on i.tm.extension_opcode. Again, we must be
7168 careful to make sure that segment/control/debug/test/MMX
7169 registers are coded into the i.rm.reg field. */
7170 else if (i.reg_operands)
7173 unsigned int vex_reg = ~0;
7175 for (op = 0; op < i.operands; op++)
7176 if (i.types[op].bitfield.reg
7177 || i.types[op].bitfield.regmmx
7178 || i.types[op].bitfield.regsimd
7179 || i.types[op].bitfield.regbnd
7180 || i.types[op].bitfield.regmask
7181 || i.types[op].bitfield.sreg2
7182 || i.types[op].bitfield.sreg3
7183 || i.types[op].bitfield.control
7184 || i.types[op].bitfield.debug
7185 || i.types[op].bitfield.test)
7190 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7192 /* For instructions with VexNDS, the register-only
7193 source operand is encoded in VEX prefix. */
7194 gas_assert (mem != (unsigned int) ~0);
7199 gas_assert (op < i.operands);
7203 /* Check register-only source operand when two source
7204 operands are swapped. */
7205 if (!i.tm.operand_types[op].bitfield.baseindex
7206 && i.tm.operand_types[op + 1].bitfield.baseindex)
7210 gas_assert (mem == (vex_reg + 1)
7211 && op < i.operands);
7216 gas_assert (vex_reg < i.operands);
7220 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7222 /* For instructions with VexNDD, the register destination
7223 is encoded in VEX prefix. */
7224 if (i.mem_operands == 0)
7226 /* There is no memory operand. */
7227 gas_assert ((op + 2) == i.operands);
7232 /* There are only 2 non-immediate operands. */
7233 gas_assert (op < i.imm_operands + 2
7234 && i.operands == i.imm_operands + 2);
7235 vex_reg = i.imm_operands + 1;
7239 gas_assert (op < i.operands);
7241 if (vex_reg != (unsigned int) ~0)
7243 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7245 if ((!type->bitfield.reg
7246 || (!type->bitfield.dword && !type->bitfield.qword))
7247 && !type->bitfield.regsimd
7248 && !operand_type_equal (type, ®mask))
7251 i.vex.register_specifier = i.op[vex_reg].regs;
7254 /* Don't set OP operand twice. */
7257 /* If there is an extension opcode to put here, the
7258 register number must be put into the regmem field. */
7259 if (i.tm.extension_opcode != None)
7261 i.rm.regmem = i.op[op].regs->reg_num;
7262 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7264 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7269 i.rm.reg = i.op[op].regs->reg_num;
7270 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7272 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7277 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7278 must set it to 3 to indicate this is a register operand
7279 in the regmem field. */
7280 if (!i.mem_operands)
7284 /* Fill in i.rm.reg field with extension opcode (if any). */
7285 if (i.tm.extension_opcode != None)
7286 i.rm.reg = i.tm.extension_opcode;
7292 output_branch (void)
7298 relax_substateT subtype;
7302 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7303 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7306 if (i.prefix[DATA_PREFIX] != 0)
7312 /* Pentium4 branch hints. */
7313 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7314 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7319 if (i.prefix[REX_PREFIX] != 0)
7325 /* BND prefixed jump. */
7326 if (i.prefix[BND_PREFIX] != 0)
7328 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7332 if (i.prefixes != 0 && !intel_syntax)
7333 as_warn (_("skipping prefixes on this instruction"));
7335 /* It's always a symbol; End frag & setup for relax.
7336 Make sure there is enough room in this frag for the largest
7337 instruction we may generate in md_convert_frag. This is 2
7338 bytes for the opcode and room for the prefix and largest
7340 frag_grow (prefix + 2 + 4);
7341 /* Prefix and 1 opcode byte go in fr_fix. */
7342 p = frag_more (prefix + 1);
7343 if (i.prefix[DATA_PREFIX] != 0)
7344 *p++ = DATA_PREFIX_OPCODE;
7345 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7346 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7347 *p++ = i.prefix[SEG_PREFIX];
7348 if (i.prefix[REX_PREFIX] != 0)
7349 *p++ = i.prefix[REX_PREFIX];
7350 *p = i.tm.base_opcode;
7352 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7353 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7354 else if (cpu_arch_flags.bitfield.cpui386)
7355 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7357 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7360 sym = i.op[0].disps->X_add_symbol;
7361 off = i.op[0].disps->X_add_number;
7363 if (i.op[0].disps->X_op != O_constant
7364 && i.op[0].disps->X_op != O_symbol)
7366 /* Handle complex expressions. */
7367 sym = make_expr_symbol (i.op[0].disps);
7371 /* 1 possible extra opcode + 4 byte displacement go in var part.
7372 Pass reloc in fr_var. */
7373 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7377 /* Return TRUE iff PLT32 relocation should be used for branching to
7381 need_plt32_p (symbolS *s)
7383 /* PLT32 relocation is ELF only. */
7387 /* Since there is no need to prepare for PLT branch on x86-64, we
7388 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7389 be used as a marker for 32-bit PC-relative branches. */
7393 /* Weak or undefined symbol need PLT32 relocation. */
7394 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7397 /* Non-global symbol doesn't need PLT32 relocation. */
7398 if (! S_IS_EXTERNAL (s))
7401 /* Other global symbols need PLT32 relocation. NB: Symbol with
7402 non-default visibilities are treated as normal global symbol
7403 so that PLT32 relocation can be used as a marker for 32-bit
7404 PC-relative branches. It is useful for linker relaxation. */
7415 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7417 if (i.tm.opcode_modifier.jumpbyte)
7419 /* This is a loop or jecxz type instruction. */
7421 if (i.prefix[ADDR_PREFIX] != 0)
7423 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7426 /* Pentium4 branch hints. */
7427 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7428 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7430 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7439 if (flag_code == CODE_16BIT)
7442 if (i.prefix[DATA_PREFIX] != 0)
7444 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7454 if (i.prefix[REX_PREFIX] != 0)
7456 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7460 /* BND prefixed jump. */
7461 if (i.prefix[BND_PREFIX] != 0)
7463 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7467 if (i.prefixes != 0 && !intel_syntax)
7468 as_warn (_("skipping prefixes on this instruction"));
7470 p = frag_more (i.tm.opcode_length + size);
7471 switch (i.tm.opcode_length)
7474 *p++ = i.tm.base_opcode >> 8;
7477 *p++ = i.tm.base_opcode;
7483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7485 && jump_reloc == NO_RELOC
7486 && need_plt32_p (i.op[0].disps->X_add_symbol))
7487 jump_reloc = BFD_RELOC_X86_64_PLT32;
7490 jump_reloc = reloc (size, 1, 1, jump_reloc);
7492 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7493 i.op[0].disps, 1, jump_reloc);
7495 /* All jumps handled here are signed, but don't use a signed limit
7496 check for 32 and 16 bit jumps as we want to allow wrap around at
7497 4G and 64k respectively. */
7499 fixP->fx_signed = 1;
7503 output_interseg_jump (void)
7511 if (flag_code == CODE_16BIT)
7515 if (i.prefix[DATA_PREFIX] != 0)
7521 if (i.prefix[REX_PREFIX] != 0)
7531 if (i.prefixes != 0 && !intel_syntax)
7532 as_warn (_("skipping prefixes on this instruction"));
7534 /* 1 opcode; 2 segment; offset */
7535 p = frag_more (prefix + 1 + 2 + size);
7537 if (i.prefix[DATA_PREFIX] != 0)
7538 *p++ = DATA_PREFIX_OPCODE;
7540 if (i.prefix[REX_PREFIX] != 0)
7541 *p++ = i.prefix[REX_PREFIX];
7543 *p++ = i.tm.base_opcode;
7544 if (i.op[1].imms->X_op == O_constant)
7546 offsetT n = i.op[1].imms->X_add_number;
7549 && !fits_in_unsigned_word (n)
7550 && !fits_in_signed_word (n))
7552 as_bad (_("16-bit jump out of range"));
7555 md_number_to_chars (p, n, size);
7558 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7559 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7560 if (i.op[0].imms->X_op != O_constant)
7561 as_bad (_("can't handle non absolute segment in `%s'"),
7563 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7569 fragS *insn_start_frag;
7570 offsetT insn_start_off;
7572 /* Tie dwarf2 debug info to the address at the start of the insn.
7573 We can't do this after the insn has been output as the current
7574 frag may have been closed off. eg. by frag_var. */
7575 dwarf2_emit_insn (0);
7577 insn_start_frag = frag_now;
7578 insn_start_off = frag_now_fix ();
7581 if (i.tm.opcode_modifier.jump)
7583 else if (i.tm.opcode_modifier.jumpbyte
7584 || i.tm.opcode_modifier.jumpdword)
7586 else if (i.tm.opcode_modifier.jumpintersegment)
7587 output_interseg_jump ();
7590 /* Output normal instructions here. */
7594 unsigned int prefix;
7597 && i.tm.base_opcode == 0xfae
7599 && i.imm_operands == 1
7600 && (i.op[0].imms->X_add_number == 0xe8
7601 || i.op[0].imms->X_add_number == 0xf0
7602 || i.op[0].imms->X_add_number == 0xf8))
7604 /* Encode lfence, mfence, and sfence as
7605 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7606 offsetT val = 0x240483f0ULL;
7608 md_number_to_chars (p, val, 5);
7612 /* Some processors fail on LOCK prefix. This options makes
7613 assembler ignore LOCK prefix and serves as a workaround. */
7614 if (omit_lock_prefix)
7616 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7618 i.prefix[LOCK_PREFIX] = 0;
7621 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7622 don't need the explicit prefix. */
7623 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7625 switch (i.tm.opcode_length)
7628 if (i.tm.base_opcode & 0xff000000)
7630 prefix = (i.tm.base_opcode >> 24) & 0xff;
7635 if ((i.tm.base_opcode & 0xff0000) != 0)
7637 prefix = (i.tm.base_opcode >> 16) & 0xff;
7638 if (i.tm.cpu_flags.bitfield.cpupadlock)
7641 if (prefix != REPE_PREFIX_OPCODE
7642 || (i.prefix[REP_PREFIX]
7643 != REPE_PREFIX_OPCODE))
7644 add_prefix (prefix);
7647 add_prefix (prefix);
7653 /* Check for pseudo prefixes. */
7654 as_bad_where (insn_start_frag->fr_file,
7655 insn_start_frag->fr_line,
7656 _("pseudo prefix without instruction"));
7662 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7663 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7664 R_X86_64_GOTTPOFF relocation so that linker can safely
7665 perform IE->LE optimization. */
7666 if (x86_elf_abi == X86_64_X32_ABI
7668 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7669 && i.prefix[REX_PREFIX] == 0)
7670 add_prefix (REX_OPCODE);
7673 /* The prefix bytes. */
7674 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7676 FRAG_APPEND_1_CHAR (*q);
7680 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7685 /* REX byte is encoded in VEX prefix. */
7689 FRAG_APPEND_1_CHAR (*q);
7692 /* There should be no other prefixes for instructions
7697 /* For EVEX instructions i.vrex should become 0 after
7698 build_evex_prefix. For VEX instructions upper 16 registers
7699 aren't available, so VREX should be 0. */
7702 /* Now the VEX prefix. */
7703 p = frag_more (i.vex.length);
7704 for (j = 0; j < i.vex.length; j++)
7705 p[j] = i.vex.bytes[j];
7708 /* Now the opcode; be careful about word order here! */
7709 if (i.tm.opcode_length == 1)
7711 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7715 switch (i.tm.opcode_length)
7719 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7720 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7724 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7734 /* Put out high byte first: can't use md_number_to_chars! */
7735 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7736 *p = i.tm.base_opcode & 0xff;
7739 /* Now the modrm byte and sib byte (if present). */
7740 if (i.tm.opcode_modifier.modrm)
7742 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7745 /* If i.rm.regmem == ESP (4)
7746 && i.rm.mode != (Register mode)
7748 ==> need second modrm byte. */
7749 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7751 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7752 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7754 | i.sib.scale << 6));
7757 if (i.disp_operands)
7758 output_disp (insn_start_frag, insn_start_off);
7761 output_imm (insn_start_frag, insn_start_off);
7767 pi ("" /*line*/, &i);
7769 #endif /* DEBUG386 */
7772 /* Return the size of the displacement operand N. */
7775 disp_size (unsigned int n)
7779 if (i.types[n].bitfield.disp64)
7781 else if (i.types[n].bitfield.disp8)
7783 else if (i.types[n].bitfield.disp16)
7788 /* Return the size of the immediate operand N. */
7791 imm_size (unsigned int n)
7794 if (i.types[n].bitfield.imm64)
7796 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7798 else if (i.types[n].bitfield.imm16)
7804 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7809 for (n = 0; n < i.operands; n++)
7811 if (operand_type_check (i.types[n], disp))
7813 if (i.op[n].disps->X_op == O_constant)
7815 int size = disp_size (n);
7816 offsetT val = i.op[n].disps->X_add_number;
7818 val = offset_in_range (val >> i.memshift, size);
7819 p = frag_more (size);
7820 md_number_to_chars (p, val, size);
7824 enum bfd_reloc_code_real reloc_type;
7825 int size = disp_size (n);
7826 int sign = i.types[n].bitfield.disp32s;
7827 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7830 /* We can't have 8 bit displacement here. */
7831 gas_assert (!i.types[n].bitfield.disp8);
7833 /* The PC relative address is computed relative
7834 to the instruction boundary, so in case immediate
7835 fields follows, we need to adjust the value. */
7836 if (pcrel && i.imm_operands)
7841 for (n1 = 0; n1 < i.operands; n1++)
7842 if (operand_type_check (i.types[n1], imm))
7844 /* Only one immediate is allowed for PC
7845 relative address. */
7846 gas_assert (sz == 0);
7848 i.op[n].disps->X_add_number -= sz;
7850 /* We should find the immediate. */
7851 gas_assert (sz != 0);
7854 p = frag_more (size);
7855 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7857 && GOT_symbol == i.op[n].disps->X_add_symbol
7858 && (((reloc_type == BFD_RELOC_32
7859 || reloc_type == BFD_RELOC_X86_64_32S
7860 || (reloc_type == BFD_RELOC_64
7862 && (i.op[n].disps->X_op == O_symbol
7863 || (i.op[n].disps->X_op == O_add
7864 && ((symbol_get_value_expression
7865 (i.op[n].disps->X_op_symbol)->X_op)
7867 || reloc_type == BFD_RELOC_32_PCREL))
7871 if (insn_start_frag == frag_now)
7872 add = (p - frag_now->fr_literal) - insn_start_off;
7877 add = insn_start_frag->fr_fix - insn_start_off;
7878 for (fr = insn_start_frag->fr_next;
7879 fr && fr != frag_now; fr = fr->fr_next)
7881 add += p - frag_now->fr_literal;
7886 reloc_type = BFD_RELOC_386_GOTPC;
7887 i.op[n].imms->X_add_number += add;
7889 else if (reloc_type == BFD_RELOC_64)
7890 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7892 /* Don't do the adjustment for x86-64, as there
7893 the pcrel addressing is relative to the _next_
7894 insn, and that is taken care of in other code. */
7895 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7897 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7898 size, i.op[n].disps, pcrel,
7900 /* Check for "call/jmp *mem", "mov mem, %reg",
7901 "test %reg, mem" and "binop mem, %reg" where binop
7902 is one of adc, add, and, cmp, or, sbb, sub, xor
7903 instructions. Always generate R_386_GOT32X for
7904 "sym*GOT" operand in 32-bit mode. */
7905 if ((generate_relax_relocations
7908 && i.rm.regmem == 5))
7910 || (i.rm.mode == 0 && i.rm.regmem == 5))
7911 && ((i.operands == 1
7912 && i.tm.base_opcode == 0xff
7913 && (i.rm.reg == 2 || i.rm.reg == 4))
7915 && (i.tm.base_opcode == 0x8b
7916 || i.tm.base_opcode == 0x85
7917 || (i.tm.base_opcode & 0xc7) == 0x03))))
7921 fixP->fx_tcbit = i.rex != 0;
7923 && (i.base_reg->reg_num == RegRip
7924 || i.base_reg->reg_num == RegEip))
7925 fixP->fx_tcbit2 = 1;
7928 fixP->fx_tcbit2 = 1;
7936 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7941 for (n = 0; n < i.operands; n++)
7943 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7944 if (i.rounding && (int) n == i.rounding->operand)
7947 if (operand_type_check (i.types[n], imm))
7949 if (i.op[n].imms->X_op == O_constant)
7951 int size = imm_size (n);
7954 val = offset_in_range (i.op[n].imms->X_add_number,
7956 p = frag_more (size);
7957 md_number_to_chars (p, val, size);
7961 /* Not absolute_section.
7962 Need a 32-bit fixup (don't support 8bit
7963 non-absolute imms). Try to support other
7965 enum bfd_reloc_code_real reloc_type;
7966 int size = imm_size (n);
7969 if (i.types[n].bitfield.imm32s
7970 && (i.suffix == QWORD_MNEM_SUFFIX
7971 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7976 p = frag_more (size);
7977 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7979 /* This is tough to explain. We end up with this one if we
7980 * have operands that look like
7981 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7982 * obtain the absolute address of the GOT, and it is strongly
7983 * preferable from a performance point of view to avoid using
7984 * a runtime relocation for this. The actual sequence of
7985 * instructions often look something like:
7990 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7992 * The call and pop essentially return the absolute address
7993 * of the label .L66 and store it in %ebx. The linker itself
7994 * will ultimately change the first operand of the addl so
7995 * that %ebx points to the GOT, but to keep things simple, the
7996 * .o file must have this operand set so that it generates not
7997 * the absolute address of .L66, but the absolute address of
7998 * itself. This allows the linker itself simply treat a GOTPC
7999 * relocation as asking for a pcrel offset to the GOT to be
8000 * added in, and the addend of the relocation is stored in the
8001 * operand field for the instruction itself.
8003 * Our job here is to fix the operand so that it would add
8004 * the correct offset so that %ebx would point to itself. The
8005 * thing that is tricky is that .-.L66 will point to the
8006 * beginning of the instruction, so we need to further modify
8007 * the operand so that it will point to itself. There are
8008 * other cases where you have something like:
8010 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8012 * and here no correction would be required. Internally in
8013 * the assembler we treat operands of this form as not being
8014 * pcrel since the '.' is explicitly mentioned, and I wonder
8015 * whether it would simplify matters to do it this way. Who
8016 * knows. In earlier versions of the PIC patches, the
8017 * pcrel_adjust field was used to store the correction, but
8018 * since the expression is not pcrel, I felt it would be
8019 * confusing to do it this way. */
8021 if ((reloc_type == BFD_RELOC_32
8022 || reloc_type == BFD_RELOC_X86_64_32S
8023 || reloc_type == BFD_RELOC_64)
8025 && GOT_symbol == i.op[n].imms->X_add_symbol
8026 && (i.op[n].imms->X_op == O_symbol
8027 || (i.op[n].imms->X_op == O_add
8028 && ((symbol_get_value_expression
8029 (i.op[n].imms->X_op_symbol)->X_op)
8034 if (insn_start_frag == frag_now)
8035 add = (p - frag_now->fr_literal) - insn_start_off;
8040 add = insn_start_frag->fr_fix - insn_start_off;
8041 for (fr = insn_start_frag->fr_next;
8042 fr && fr != frag_now; fr = fr->fr_next)
8044 add += p - frag_now->fr_literal;
8048 reloc_type = BFD_RELOC_386_GOTPC;
8050 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8052 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8053 i.op[n].imms->X_add_number += add;
8055 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8056 i.op[n].imms, 0, reloc_type);
8062 /* x86_cons_fix_new is called via the expression parsing code when a
8063 reloc is needed. We use this hook to get the correct .got reloc. */
8064 static int cons_sign = -1;
8067 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8068 expressionS *exp, bfd_reloc_code_real_type r)
8070 r = reloc (len, 0, cons_sign, r);
8073 if (exp->X_op == O_secrel)
8075 exp->X_op = O_symbol;
8076 r = BFD_RELOC_32_SECREL;
8080 fix_new_exp (frag, off, len, exp, 0, r);
8083 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8084 purpose of the `.dc.a' internal pseudo-op. */
8087 x86_address_bytes (void)
8089 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8091 return stdoutput->arch_info->bits_per_address / 8;
8094 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8096 # define lex_got(reloc, adjust, types) NULL
8098 /* Parse operands of the form
8099 <symbol>@GOTOFF+<nnn>
8100 and similar .plt or .got references.
8102 If we find one, set up the correct relocation in RELOC and copy the
8103 input string, minus the `@GOTOFF' into a malloc'd buffer for
8104 parsing by the calling routine. Return this buffer, and if ADJUST
8105 is non-null set it to the length of the string we removed from the
8106 input line. Otherwise return NULL. */
8108 lex_got (enum bfd_reloc_code_real *rel,
8110 i386_operand_type *types)
8112 /* Some of the relocations depend on the size of what field is to
8113 be relocated. But in our callers i386_immediate and i386_displacement
8114 we don't yet know the operand size (this will be set by insn
8115 matching). Hence we record the word32 relocation here,
8116 and adjust the reloc according to the real size in reloc(). */
8117 static const struct {
8120 const enum bfd_reloc_code_real rel[2];
8121 const i386_operand_type types64;
8123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8124 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8126 OPERAND_TYPE_IMM32_64 },
8128 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8129 BFD_RELOC_X86_64_PLTOFF64 },
8130 OPERAND_TYPE_IMM64 },
8131 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8132 BFD_RELOC_X86_64_PLT32 },
8133 OPERAND_TYPE_IMM32_32S_DISP32 },
8134 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8135 BFD_RELOC_X86_64_GOTPLT64 },
8136 OPERAND_TYPE_IMM64_DISP64 },
8137 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8138 BFD_RELOC_X86_64_GOTOFF64 },
8139 OPERAND_TYPE_IMM64_DISP64 },
8140 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8141 BFD_RELOC_X86_64_GOTPCREL },
8142 OPERAND_TYPE_IMM32_32S_DISP32 },
8143 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8144 BFD_RELOC_X86_64_TLSGD },
8145 OPERAND_TYPE_IMM32_32S_DISP32 },
8146 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8147 _dummy_first_bfd_reloc_code_real },
8148 OPERAND_TYPE_NONE },
8149 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8150 BFD_RELOC_X86_64_TLSLD },
8151 OPERAND_TYPE_IMM32_32S_DISP32 },
8152 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8153 BFD_RELOC_X86_64_GOTTPOFF },
8154 OPERAND_TYPE_IMM32_32S_DISP32 },
8155 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8156 BFD_RELOC_X86_64_TPOFF32 },
8157 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8158 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8159 _dummy_first_bfd_reloc_code_real },
8160 OPERAND_TYPE_NONE },
8161 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8162 BFD_RELOC_X86_64_DTPOFF32 },
8163 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8164 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8165 _dummy_first_bfd_reloc_code_real },
8166 OPERAND_TYPE_NONE },
8167 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8168 _dummy_first_bfd_reloc_code_real },
8169 OPERAND_TYPE_NONE },
8170 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8171 BFD_RELOC_X86_64_GOT32 },
8172 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8173 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8174 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8175 OPERAND_TYPE_IMM32_32S_DISP32 },
8176 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8177 BFD_RELOC_X86_64_TLSDESC_CALL },
8178 OPERAND_TYPE_IMM32_32S_DISP32 },
8183 #if defined (OBJ_MAYBE_ELF)
8188 for (cp = input_line_pointer; *cp != '@'; cp++)
8189 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8192 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8194 int len = gotrel[j].len;
8195 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8197 if (gotrel[j].rel[object_64bit] != 0)
8200 char *tmpbuf, *past_reloc;
8202 *rel = gotrel[j].rel[object_64bit];
8206 if (flag_code != CODE_64BIT)
8208 types->bitfield.imm32 = 1;
8209 types->bitfield.disp32 = 1;
8212 *types = gotrel[j].types64;
8215 if (j != 0 && GOT_symbol == NULL)
8216 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8218 /* The length of the first part of our input line. */
8219 first = cp - input_line_pointer;
8221 /* The second part goes from after the reloc token until
8222 (and including) an end_of_line char or comma. */
8223 past_reloc = cp + 1 + len;
8225 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8227 second = cp + 1 - past_reloc;
8229 /* Allocate and copy string. The trailing NUL shouldn't
8230 be necessary, but be safe. */
8231 tmpbuf = XNEWVEC (char, first + second + 2);
8232 memcpy (tmpbuf, input_line_pointer, first);
8233 if (second != 0 && *past_reloc != ' ')
8234 /* Replace the relocation token with ' ', so that
8235 errors like foo@GOTOFF1 will be detected. */
8236 tmpbuf[first++] = ' ';
8238 /* Increment length by 1 if the relocation token is
8243 memcpy (tmpbuf + first, past_reloc, second);
8244 tmpbuf[first + second] = '\0';
8248 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8249 gotrel[j].str, 1 << (5 + object_64bit));
8254 /* Might be a symbol version string. Don't as_bad here. */
8263 /* Parse operands of the form
8264 <symbol>@SECREL32+<nnn>
8266 If we find one, set up the correct relocation in RELOC and copy the
8267 input string, minus the `@SECREL32' into a malloc'd buffer for
8268 parsing by the calling routine. Return this buffer, and if ADJUST
8269 is non-null set it to the length of the string we removed from the
8270 input line. Otherwise return NULL.
8272 This function is copied from the ELF version above adjusted for PE targets. */
8275 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8276 int *adjust ATTRIBUTE_UNUSED,
8277 i386_operand_type *types)
8283 const enum bfd_reloc_code_real rel[2];
8284 const i386_operand_type types64;
8288 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8289 BFD_RELOC_32_SECREL },
8290 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8296 for (cp = input_line_pointer; *cp != '@'; cp++)
8297 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8300 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8302 int len = gotrel[j].len;
8304 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8306 if (gotrel[j].rel[object_64bit] != 0)
8309 char *tmpbuf, *past_reloc;
8311 *rel = gotrel[j].rel[object_64bit];
8317 if (flag_code != CODE_64BIT)
8319 types->bitfield.imm32 = 1;
8320 types->bitfield.disp32 = 1;
8323 *types = gotrel[j].types64;
8326 /* The length of the first part of our input line. */
8327 first = cp - input_line_pointer;
8329 /* The second part goes from after the reloc token until
8330 (and including) an end_of_line char or comma. */
8331 past_reloc = cp + 1 + len;
8333 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8335 second = cp + 1 - past_reloc;
8337 /* Allocate and copy string. The trailing NUL shouldn't
8338 be necessary, but be safe. */
8339 tmpbuf = XNEWVEC (char, first + second + 2);
8340 memcpy (tmpbuf, input_line_pointer, first);
8341 if (second != 0 && *past_reloc != ' ')
8342 /* Replace the relocation token with ' ', so that
8343 errors like foo@SECLREL321 will be detected. */
8344 tmpbuf[first++] = ' ';
8345 memcpy (tmpbuf + first, past_reloc, second);
8346 tmpbuf[first + second] = '\0';
8350 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8351 gotrel[j].str, 1 << (5 + object_64bit));
8356 /* Might be a symbol version string. Don't as_bad here. */
8362 bfd_reloc_code_real_type
8363 x86_cons (expressionS *exp, int size)
8365 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8367 intel_syntax = -intel_syntax;
8370 if (size == 4 || (object_64bit && size == 8))
8372 /* Handle @GOTOFF and the like in an expression. */
8374 char *gotfree_input_line;
8377 save = input_line_pointer;
8378 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8379 if (gotfree_input_line)
8380 input_line_pointer = gotfree_input_line;
8384 if (gotfree_input_line)
8386 /* expression () has merrily parsed up to the end of line,
8387 or a comma - in the wrong buffer. Transfer how far
8388 input_line_pointer has moved to the right buffer. */
8389 input_line_pointer = (save
8390 + (input_line_pointer - gotfree_input_line)
8392 free (gotfree_input_line);
8393 if (exp->X_op == O_constant
8394 || exp->X_op == O_absent
8395 || exp->X_op == O_illegal
8396 || exp->X_op == O_register
8397 || exp->X_op == O_big)
8399 char c = *input_line_pointer;
8400 *input_line_pointer = 0;
8401 as_bad (_("missing or invalid expression `%s'"), save);
8402 *input_line_pointer = c;
8409 intel_syntax = -intel_syntax;
8412 i386_intel_simplify (exp);
8418 signed_cons (int size)
8420 if (flag_code == CODE_64BIT)
8428 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8435 if (exp.X_op == O_symbol)
8436 exp.X_op = O_secrel;
8438 emit_expr (&exp, 4);
8440 while (*input_line_pointer++ == ',');
8442 input_line_pointer--;
8443 demand_empty_rest_of_line ();
8447 /* Handle Vector operations. */
8450 check_VecOperations (char *op_string, char *op_end)
8452 const reg_entry *mask;
8457 && (op_end == NULL || op_string < op_end))
8460 if (*op_string == '{')
8464 /* Check broadcasts. */
8465 if (strncmp (op_string, "1to", 3) == 0)
8470 goto duplicated_vec_op;
8473 if (*op_string == '8')
8475 else if (*op_string == '4')
8477 else if (*op_string == '2')
8479 else if (*op_string == '1'
8480 && *(op_string+1) == '6')
8487 as_bad (_("Unsupported broadcast: `%s'"), saved);
8492 broadcast_op.type = bcst_type;
8493 broadcast_op.operand = this_operand;
8494 i.broadcast = &broadcast_op;
8496 /* Check masking operation. */
8497 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8499 /* k0 can't be used for write mask. */
8500 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8502 as_bad (_("`%s%s' can't be used for write mask"),
8503 register_prefix, mask->reg_name);
8509 mask_op.mask = mask;
8510 mask_op.zeroing = 0;
8511 mask_op.operand = this_operand;
8517 goto duplicated_vec_op;
8519 i.mask->mask = mask;
8521 /* Only "{z}" is allowed here. No need to check
8522 zeroing mask explicitly. */
8523 if (i.mask->operand != this_operand)
8525 as_bad (_("invalid write mask `%s'"), saved);
8532 /* Check zeroing-flag for masking operation. */
8533 else if (*op_string == 'z')
8537 mask_op.mask = NULL;
8538 mask_op.zeroing = 1;
8539 mask_op.operand = this_operand;
8544 if (i.mask->zeroing)
8547 as_bad (_("duplicated `%s'"), saved);
8551 i.mask->zeroing = 1;
8553 /* Only "{%k}" is allowed here. No need to check mask
8554 register explicitly. */
8555 if (i.mask->operand != this_operand)
8557 as_bad (_("invalid zeroing-masking `%s'"),
8566 goto unknown_vec_op;
8568 if (*op_string != '}')
8570 as_bad (_("missing `}' in `%s'"), saved);
8575 /* Strip whitespace since the addition of pseudo prefixes
8576 changed how the scrubber treats '{'. */
8577 if (is_space_char (*op_string))
8583 /* We don't know this one. */
8584 as_bad (_("unknown vector operation: `%s'"), saved);
8588 if (i.mask && i.mask->zeroing && !i.mask->mask)
8590 as_bad (_("zeroing-masking only allowed with write mask"));
8598 i386_immediate (char *imm_start)
8600 char *save_input_line_pointer;
8601 char *gotfree_input_line;
8604 i386_operand_type types;
8606 operand_type_set (&types, ~0);
8608 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8610 as_bad (_("at most %d immediate operands are allowed"),
8611 MAX_IMMEDIATE_OPERANDS);
8615 exp = &im_expressions[i.imm_operands++];
8616 i.op[this_operand].imms = exp;
8618 if (is_space_char (*imm_start))
8621 save_input_line_pointer = input_line_pointer;
8622 input_line_pointer = imm_start;
8624 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8625 if (gotfree_input_line)
8626 input_line_pointer = gotfree_input_line;
8628 exp_seg = expression (exp);
8632 /* Handle vector operations. */
8633 if (*input_line_pointer == '{')
8635 input_line_pointer = check_VecOperations (input_line_pointer,
8637 if (input_line_pointer == NULL)
8641 if (*input_line_pointer)
8642 as_bad (_("junk `%s' after expression"), input_line_pointer);
8644 input_line_pointer = save_input_line_pointer;
8645 if (gotfree_input_line)
8647 free (gotfree_input_line);
8649 if (exp->X_op == O_constant || exp->X_op == O_register)
8650 exp->X_op = O_illegal;
8653 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8657 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8658 i386_operand_type types, const char *imm_start)
8660 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8663 as_bad (_("missing or invalid immediate expression `%s'"),
8667 else if (exp->X_op == O_constant)
8669 /* Size it properly later. */
8670 i.types[this_operand].bitfield.imm64 = 1;
8671 /* If not 64bit, sign extend val. */
8672 if (flag_code != CODE_64BIT
8673 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8675 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8677 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8678 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8679 && exp_seg != absolute_section
8680 && exp_seg != text_section
8681 && exp_seg != data_section
8682 && exp_seg != bss_section
8683 && exp_seg != undefined_section
8684 && !bfd_is_com_section (exp_seg))
8686 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8690 else if (!intel_syntax && exp_seg == reg_section)
8693 as_bad (_("illegal immediate register operand %s"), imm_start);
8698 /* This is an address. The size of the address will be
8699 determined later, depending on destination register,
8700 suffix, or the default for the section. */
8701 i.types[this_operand].bitfield.imm8 = 1;
8702 i.types[this_operand].bitfield.imm16 = 1;
8703 i.types[this_operand].bitfield.imm32 = 1;
8704 i.types[this_operand].bitfield.imm32s = 1;
8705 i.types[this_operand].bitfield.imm64 = 1;
8706 i.types[this_operand] = operand_type_and (i.types[this_operand],
8714 i386_scale (char *scale)
8717 char *save = input_line_pointer;
8719 input_line_pointer = scale;
8720 val = get_absolute_expression ();
8725 i.log2_scale_factor = 0;
8728 i.log2_scale_factor = 1;
8731 i.log2_scale_factor = 2;
8734 i.log2_scale_factor = 3;
8738 char sep = *input_line_pointer;
8740 *input_line_pointer = '\0';
8741 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8743 *input_line_pointer = sep;
8744 input_line_pointer = save;
8748 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8750 as_warn (_("scale factor of %d without an index register"),
8751 1 << i.log2_scale_factor);
8752 i.log2_scale_factor = 0;
8754 scale = input_line_pointer;
8755 input_line_pointer = save;
8760 i386_displacement (char *disp_start, char *disp_end)
8764 char *save_input_line_pointer;
8765 char *gotfree_input_line;
8767 i386_operand_type bigdisp, types = anydisp;
8770 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8772 as_bad (_("at most %d displacement operands are allowed"),
8773 MAX_MEMORY_OPERANDS);
8777 operand_type_set (&bigdisp, 0);
8778 if ((i.types[this_operand].bitfield.jumpabsolute)
8779 || (!current_templates->start->opcode_modifier.jump
8780 && !current_templates->start->opcode_modifier.jumpdword))
8782 bigdisp.bitfield.disp32 = 1;
8783 override = (i.prefix[ADDR_PREFIX] != 0);
8784 if (flag_code == CODE_64BIT)
8788 bigdisp.bitfield.disp32s = 1;
8789 bigdisp.bitfield.disp64 = 1;
8792 else if ((flag_code == CODE_16BIT) ^ override)
8794 bigdisp.bitfield.disp32 = 0;
8795 bigdisp.bitfield.disp16 = 1;
8800 /* For PC-relative branches, the width of the displacement
8801 is dependent upon data size, not address size. */
8802 override = (i.prefix[DATA_PREFIX] != 0);
8803 if (flag_code == CODE_64BIT)
8805 if (override || i.suffix == WORD_MNEM_SUFFIX)
8806 bigdisp.bitfield.disp16 = 1;
8809 bigdisp.bitfield.disp32 = 1;
8810 bigdisp.bitfield.disp32s = 1;
8816 override = (i.suffix == (flag_code != CODE_16BIT
8818 : LONG_MNEM_SUFFIX));
8819 bigdisp.bitfield.disp32 = 1;
8820 if ((flag_code == CODE_16BIT) ^ override)
8822 bigdisp.bitfield.disp32 = 0;
8823 bigdisp.bitfield.disp16 = 1;
8827 i.types[this_operand] = operand_type_or (i.types[this_operand],
8830 exp = &disp_expressions[i.disp_operands];
8831 i.op[this_operand].disps = exp;
8833 save_input_line_pointer = input_line_pointer;
8834 input_line_pointer = disp_start;
8835 END_STRING_AND_SAVE (disp_end);
8837 #ifndef GCC_ASM_O_HACK
8838 #define GCC_ASM_O_HACK 0
8841 END_STRING_AND_SAVE (disp_end + 1);
8842 if (i.types[this_operand].bitfield.baseIndex
8843 && displacement_string_end[-1] == '+')
8845 /* This hack is to avoid a warning when using the "o"
8846 constraint within gcc asm statements.
8849 #define _set_tssldt_desc(n,addr,limit,type) \
8850 __asm__ __volatile__ ( \
8852 "movw %w1,2+%0\n\t" \
8854 "movb %b1,4+%0\n\t" \
8855 "movb %4,5+%0\n\t" \
8856 "movb $0,6+%0\n\t" \
8857 "movb %h1,7+%0\n\t" \
8859 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8861 This works great except that the output assembler ends
8862 up looking a bit weird if it turns out that there is
8863 no offset. You end up producing code that looks like:
8876 So here we provide the missing zero. */
8878 *displacement_string_end = '0';
8881 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8882 if (gotfree_input_line)
8883 input_line_pointer = gotfree_input_line;
8885 exp_seg = expression (exp);
8888 if (*input_line_pointer)
8889 as_bad (_("junk `%s' after expression"), input_line_pointer);
8891 RESTORE_END_STRING (disp_end + 1);
8893 input_line_pointer = save_input_line_pointer;
8894 if (gotfree_input_line)
8896 free (gotfree_input_line);
8898 if (exp->X_op == O_constant || exp->X_op == O_register)
8899 exp->X_op = O_illegal;
8902 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8904 RESTORE_END_STRING (disp_end);
8910 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8911 i386_operand_type types, const char *disp_start)
8913 i386_operand_type bigdisp;
8916 /* We do this to make sure that the section symbol is in
8917 the symbol table. We will ultimately change the relocation
8918 to be relative to the beginning of the section. */
8919 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8920 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8921 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8923 if (exp->X_op != O_symbol)
8926 if (S_IS_LOCAL (exp->X_add_symbol)
8927 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8928 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8929 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8930 exp->X_op = O_subtract;
8931 exp->X_op_symbol = GOT_symbol;
8932 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8933 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8934 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8935 i.reloc[this_operand] = BFD_RELOC_64;
8937 i.reloc[this_operand] = BFD_RELOC_32;
8940 else if (exp->X_op == O_absent
8941 || exp->X_op == O_illegal
8942 || exp->X_op == O_big)
8945 as_bad (_("missing or invalid displacement expression `%s'"),
8950 else if (flag_code == CODE_64BIT
8951 && !i.prefix[ADDR_PREFIX]
8952 && exp->X_op == O_constant)
8954 /* Since displacement is signed extended to 64bit, don't allow
8955 disp32 and turn off disp32s if they are out of range. */
8956 i.types[this_operand].bitfield.disp32 = 0;
8957 if (!fits_in_signed_long (exp->X_add_number))
8959 i.types[this_operand].bitfield.disp32s = 0;
8960 if (i.types[this_operand].bitfield.baseindex)
8962 as_bad (_("0x%lx out range of signed 32bit displacement"),
8963 (long) exp->X_add_number);
8969 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8970 else if (exp->X_op != O_constant
8971 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8972 && exp_seg != absolute_section
8973 && exp_seg != text_section
8974 && exp_seg != data_section
8975 && exp_seg != bss_section
8976 && exp_seg != undefined_section
8977 && !bfd_is_com_section (exp_seg))
8979 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8984 /* Check if this is a displacement only operand. */
8985 bigdisp = i.types[this_operand];
8986 bigdisp.bitfield.disp8 = 0;
8987 bigdisp.bitfield.disp16 = 0;
8988 bigdisp.bitfield.disp32 = 0;
8989 bigdisp.bitfield.disp32s = 0;
8990 bigdisp.bitfield.disp64 = 0;
8991 if (operand_type_all_zero (&bigdisp))
8992 i.types[this_operand] = operand_type_and (i.types[this_operand],
8998 /* Return the active addressing mode, taking address override and
8999 registers forming the address into consideration. Update the
9000 address override prefix if necessary. */
9002 static enum flag_code
9003 i386_addressing_mode (void)
9005 enum flag_code addr_mode;
9007 if (i.prefix[ADDR_PREFIX])
9008 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9011 addr_mode = flag_code;
9013 #if INFER_ADDR_PREFIX
9014 if (i.mem_operands == 0)
9016 /* Infer address prefix from the first memory operand. */
9017 const reg_entry *addr_reg = i.base_reg;
9019 if (addr_reg == NULL)
9020 addr_reg = i.index_reg;
9024 if (addr_reg->reg_num == RegEip
9025 || addr_reg->reg_num == RegEiz
9026 || addr_reg->reg_type.bitfield.dword)
9027 addr_mode = CODE_32BIT;
9028 else if (flag_code != CODE_64BIT
9029 && addr_reg->reg_type.bitfield.word)
9030 addr_mode = CODE_16BIT;
9032 if (addr_mode != flag_code)
9034 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9036 /* Change the size of any displacement too. At most one
9037 of Disp16 or Disp32 is set.
9038 FIXME. There doesn't seem to be any real need for
9039 separate Disp16 and Disp32 flags. The same goes for
9040 Imm16 and Imm32. Removing them would probably clean
9041 up the code quite a lot. */
9042 if (flag_code != CODE_64BIT
9043 && (i.types[this_operand].bitfield.disp16
9044 || i.types[this_operand].bitfield.disp32))
9045 i.types[this_operand]
9046 = operand_type_xor (i.types[this_operand], disp16_32);
9056 /* Make sure the memory operand we've been dealt is valid.
9057 Return 1 on success, 0 on a failure. */
9060 i386_index_check (const char *operand_string)
9062 const char *kind = "base/index";
9063 enum flag_code addr_mode = i386_addressing_mode ();
9065 if (current_templates->start->opcode_modifier.isstring
9066 && !current_templates->start->opcode_modifier.immext
9067 && (current_templates->end[-1].opcode_modifier.isstring
9070 /* Memory operands of string insns are special in that they only allow
9071 a single register (rDI, rSI, or rBX) as their memory address. */
9072 const reg_entry *expected_reg;
9073 static const char *di_si[][2] =
9079 static const char *bx[] = { "ebx", "bx", "rbx" };
9081 kind = "string address";
9083 if (current_templates->start->opcode_modifier.repprefixok)
9085 i386_operand_type type = current_templates->end[-1].operand_types[0];
9087 if (!type.bitfield.baseindex
9088 || ((!i.mem_operands != !intel_syntax)
9089 && current_templates->end[-1].operand_types[1]
9090 .bitfield.baseindex))
9091 type = current_templates->end[-1].operand_types[1];
9092 expected_reg = hash_find (reg_hash,
9093 di_si[addr_mode][type.bitfield.esseg]);
9097 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9099 if (i.base_reg != expected_reg
9101 || operand_type_check (i.types[this_operand], disp))
9103 /* The second memory operand must have the same size as
9107 && !((addr_mode == CODE_64BIT
9108 && i.base_reg->reg_type.bitfield.qword)
9109 || (addr_mode == CODE_32BIT
9110 ? i.base_reg->reg_type.bitfield.dword
9111 : i.base_reg->reg_type.bitfield.word)))
9114 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9116 intel_syntax ? '[' : '(',
9118 expected_reg->reg_name,
9119 intel_syntax ? ']' : ')');
9126 as_bad (_("`%s' is not a valid %s expression"),
9127 operand_string, kind);
9132 if (addr_mode != CODE_16BIT)
9134 /* 32-bit/64-bit checks. */
9136 && (addr_mode == CODE_64BIT
9137 ? !i.base_reg->reg_type.bitfield.qword
9138 : !i.base_reg->reg_type.bitfield.dword)
9140 || (i.base_reg->reg_num
9141 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9143 && !i.index_reg->reg_type.bitfield.xmmword
9144 && !i.index_reg->reg_type.bitfield.ymmword
9145 && !i.index_reg->reg_type.bitfield.zmmword
9146 && ((addr_mode == CODE_64BIT
9147 ? !(i.index_reg->reg_type.bitfield.qword
9148 || i.index_reg->reg_num == RegRiz)
9149 : !(i.index_reg->reg_type.bitfield.dword
9150 || i.index_reg->reg_num == RegEiz))
9151 || !i.index_reg->reg_type.bitfield.baseindex)))
9154 /* bndmk, bndldx, and bndstx have special restrictions. */
9155 if (current_templates->start->base_opcode == 0xf30f1b
9156 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9158 /* They cannot use RIP-relative addressing. */
9159 if (i.base_reg && i.base_reg->reg_num == RegRip)
9161 as_bad (_("`%s' cannot be used here"), operand_string);
9165 /* bndldx and bndstx ignore their scale factor. */
9166 if (current_templates->start->base_opcode != 0xf30f1b
9167 && i.log2_scale_factor)
9168 as_warn (_("register scaling is being ignored here"));
9173 /* 16-bit checks. */
9175 && (!i.base_reg->reg_type.bitfield.word
9176 || !i.base_reg->reg_type.bitfield.baseindex))
9178 && (!i.index_reg->reg_type.bitfield.word
9179 || !i.index_reg->reg_type.bitfield.baseindex
9181 && i.base_reg->reg_num < 6
9182 && i.index_reg->reg_num >= 6
9183 && i.log2_scale_factor == 0))))
9190 /* Handle vector immediates. */
9193 RC_SAE_immediate (const char *imm_start)
9195 unsigned int match_found, j;
9196 const char *pstr = imm_start;
9204 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9206 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9210 rc_op.type = RC_NamesTable[j].type;
9211 rc_op.operand = this_operand;
9212 i.rounding = &rc_op;
9216 as_bad (_("duplicated `%s'"), imm_start);
9219 pstr += RC_NamesTable[j].len;
9229 as_bad (_("Missing '}': '%s'"), imm_start);
9232 /* RC/SAE immediate string should contain nothing more. */;
9235 as_bad (_("Junk after '}': '%s'"), imm_start);
9239 exp = &im_expressions[i.imm_operands++];
9240 i.op[this_operand].imms = exp;
9242 exp->X_op = O_constant;
9243 exp->X_add_number = 0;
9244 exp->X_add_symbol = (symbolS *) 0;
9245 exp->X_op_symbol = (symbolS *) 0;
9247 i.types[this_operand].bitfield.imm8 = 1;
9251 /* Only string instructions can have a second memory operand, so
9252 reduce current_templates to just those if it contains any. */
9254 maybe_adjust_templates (void)
9256 const insn_template *t;
9258 gas_assert (i.mem_operands == 1);
9260 for (t = current_templates->start; t < current_templates->end; ++t)
9261 if (t->opcode_modifier.isstring)
9264 if (t < current_templates->end)
9266 static templates aux_templates;
9267 bfd_boolean recheck;
9269 aux_templates.start = t;
9270 for (; t < current_templates->end; ++t)
9271 if (!t->opcode_modifier.isstring)
9273 aux_templates.end = t;
9275 /* Determine whether to re-check the first memory operand. */
9276 recheck = (aux_templates.start != current_templates->start
9277 || t != current_templates->end);
9279 current_templates = &aux_templates;
9284 if (i.memop1_string != NULL
9285 && i386_index_check (i.memop1_string) == 0)
9294 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9298 i386_att_operand (char *operand_string)
9302 char *op_string = operand_string;
9304 if (is_space_char (*op_string))
9307 /* We check for an absolute prefix (differentiating,
9308 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9309 if (*op_string == ABSOLUTE_PREFIX)
9312 if (is_space_char (*op_string))
9314 i.types[this_operand].bitfield.jumpabsolute = 1;
9317 /* Check if operand is a register. */
9318 if ((r = parse_register (op_string, &end_op)) != NULL)
9320 i386_operand_type temp;
9322 /* Check for a segment override by searching for ':' after a
9323 segment register. */
9325 if (is_space_char (*op_string))
9327 if (*op_string == ':'
9328 && (r->reg_type.bitfield.sreg2
9329 || r->reg_type.bitfield.sreg3))
9334 i.seg[i.mem_operands] = &es;
9337 i.seg[i.mem_operands] = &cs;
9340 i.seg[i.mem_operands] = &ss;
9343 i.seg[i.mem_operands] = &ds;
9346 i.seg[i.mem_operands] = &fs;
9349 i.seg[i.mem_operands] = &gs;
9353 /* Skip the ':' and whitespace. */
9355 if (is_space_char (*op_string))
9358 if (!is_digit_char (*op_string)
9359 && !is_identifier_char (*op_string)
9360 && *op_string != '('
9361 && *op_string != ABSOLUTE_PREFIX)
9363 as_bad (_("bad memory operand `%s'"), op_string);
9366 /* Handle case of %es:*foo. */
9367 if (*op_string == ABSOLUTE_PREFIX)
9370 if (is_space_char (*op_string))
9372 i.types[this_operand].bitfield.jumpabsolute = 1;
9374 goto do_memory_reference;
9377 /* Handle vector operations. */
9378 if (*op_string == '{')
9380 op_string = check_VecOperations (op_string, NULL);
9381 if (op_string == NULL)
9387 as_bad (_("junk `%s' after register"), op_string);
9391 temp.bitfield.baseindex = 0;
9392 i.types[this_operand] = operand_type_or (i.types[this_operand],
9394 i.types[this_operand].bitfield.unspecified = 0;
9395 i.op[this_operand].regs = r;
9398 else if (*op_string == REGISTER_PREFIX)
9400 as_bad (_("bad register name `%s'"), op_string);
9403 else if (*op_string == IMMEDIATE_PREFIX)
9406 if (i.types[this_operand].bitfield.jumpabsolute)
9408 as_bad (_("immediate operand illegal with absolute jump"));
9411 if (!i386_immediate (op_string))
9414 else if (RC_SAE_immediate (operand_string))
9416 /* If it is a RC or SAE immediate, do nothing. */
9419 else if (is_digit_char (*op_string)
9420 || is_identifier_char (*op_string)
9421 || *op_string == '"'
9422 || *op_string == '(')
9424 /* This is a memory reference of some sort. */
9427 /* Start and end of displacement string expression (if found). */
9428 char *displacement_string_start;
9429 char *displacement_string_end;
9432 do_memory_reference:
9433 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9435 if ((i.mem_operands == 1
9436 && !current_templates->start->opcode_modifier.isstring)
9437 || i.mem_operands == 2)
9439 as_bad (_("too many memory references for `%s'"),
9440 current_templates->start->name);
9444 /* Check for base index form. We detect the base index form by
9445 looking for an ')' at the end of the operand, searching
9446 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9448 base_string = op_string + strlen (op_string);
9450 /* Handle vector operations. */
9451 vop_start = strchr (op_string, '{');
9452 if (vop_start && vop_start < base_string)
9454 if (check_VecOperations (vop_start, base_string) == NULL)
9456 base_string = vop_start;
9460 if (is_space_char (*base_string))
9463 /* If we only have a displacement, set-up for it to be parsed later. */
9464 displacement_string_start = op_string;
9465 displacement_string_end = base_string + 1;
9467 if (*base_string == ')')
9470 unsigned int parens_balanced = 1;
9471 /* We've already checked that the number of left & right ()'s are
9472 equal, so this loop will not be infinite. */
9476 if (*base_string == ')')
9478 if (*base_string == '(')
9481 while (parens_balanced);
9483 temp_string = base_string;
9485 /* Skip past '(' and whitespace. */
9487 if (is_space_char (*base_string))
9490 if (*base_string == ','
9491 || ((i.base_reg = parse_register (base_string, &end_op))
9494 displacement_string_end = temp_string;
9496 i.types[this_operand].bitfield.baseindex = 1;
9500 base_string = end_op;
9501 if (is_space_char (*base_string))
9505 /* There may be an index reg or scale factor here. */
9506 if (*base_string == ',')
9509 if (is_space_char (*base_string))
9512 if ((i.index_reg = parse_register (base_string, &end_op))
9515 base_string = end_op;
9516 if (is_space_char (*base_string))
9518 if (*base_string == ',')
9521 if (is_space_char (*base_string))
9524 else if (*base_string != ')')
9526 as_bad (_("expecting `,' or `)' "
9527 "after index register in `%s'"),
9532 else if (*base_string == REGISTER_PREFIX)
9534 end_op = strchr (base_string, ',');
9537 as_bad (_("bad register name `%s'"), base_string);
9541 /* Check for scale factor. */
9542 if (*base_string != ')')
9544 char *end_scale = i386_scale (base_string);
9549 base_string = end_scale;
9550 if (is_space_char (*base_string))
9552 if (*base_string != ')')
9554 as_bad (_("expecting `)' "
9555 "after scale factor in `%s'"),
9560 else if (!i.index_reg)
9562 as_bad (_("expecting index register or scale factor "
9563 "after `,'; got '%c'"),
9568 else if (*base_string != ')')
9570 as_bad (_("expecting `,' or `)' "
9571 "after base register in `%s'"),
9576 else if (*base_string == REGISTER_PREFIX)
9578 end_op = strchr (base_string, ',');
9581 as_bad (_("bad register name `%s'"), base_string);
9586 /* If there's an expression beginning the operand, parse it,
9587 assuming displacement_string_start and
9588 displacement_string_end are meaningful. */
9589 if (displacement_string_start != displacement_string_end)
9591 if (!i386_displacement (displacement_string_start,
9592 displacement_string_end))
9596 /* Special case for (%dx) while doing input/output op. */
9598 && operand_type_equal (&i.base_reg->reg_type,
9599 ®16_inoutportreg)
9601 && i.log2_scale_factor == 0
9602 && i.seg[i.mem_operands] == 0
9603 && !operand_type_check (i.types[this_operand], disp))
9605 i.types[this_operand] = inoutportreg;
9609 if (i386_index_check (operand_string) == 0)
9611 i.types[this_operand].bitfield.mem = 1;
9612 if (i.mem_operands == 0)
9613 i.memop1_string = xstrdup (operand_string);
9618 /* It's not a memory operand; argh! */
9619 as_bad (_("invalid char %s beginning operand %d `%s'"),
9620 output_invalid (*op_string),
9625 return 1; /* Normal return. */
9628 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9629 that an rs_machine_dependent frag may reach. */
9632 i386_frag_max_var (fragS *frag)
9634 /* The only relaxable frags are for jumps.
9635 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9636 gas_assert (frag->fr_type == rs_machine_dependent);
9637 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9640 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9642 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9644 /* STT_GNU_IFUNC symbol must go through PLT. */
9645 if ((symbol_get_bfdsym (fr_symbol)->flags
9646 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9649 if (!S_IS_EXTERNAL (fr_symbol))
9650 /* Symbol may be weak or local. */
9651 return !S_IS_WEAK (fr_symbol);
9653 /* Global symbols with non-default visibility can't be preempted. */
9654 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9657 if (fr_var != NO_RELOC)
9658 switch ((enum bfd_reloc_code_real) fr_var)
9660 case BFD_RELOC_386_PLT32:
9661 case BFD_RELOC_X86_64_PLT32:
9662 /* Symbol with PLT relocation may be preempted. */
9668 /* Global symbols with default visibility in a shared library may be
9669 preempted by another definition. */
9674 /* md_estimate_size_before_relax()
9676 Called just before relax() for rs_machine_dependent frags. The x86
9677 assembler uses these frags to handle variable size jump
9680 Any symbol that is now undefined will not become defined.
9681 Return the correct fr_subtype in the frag.
9682 Return the initial "guess for variable size of frag" to caller.
9683 The guess is actually the growth beyond the fixed part. Whatever
9684 we do to grow the fixed or variable part contributes to our
9688 md_estimate_size_before_relax (fragS *fragP, segT segment)
9690 /* We've already got fragP->fr_subtype right; all we have to do is
9691 check for un-relaxable symbols. On an ELF system, we can't relax
9692 an externally visible symbol, because it may be overridden by a
9694 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9695 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9697 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9700 #if defined (OBJ_COFF) && defined (TE_PE)
9701 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9702 && S_IS_WEAK (fragP->fr_symbol))
9706 /* Symbol is undefined in this segment, or we need to keep a
9707 reloc so that weak symbols can be overridden. */
9708 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9709 enum bfd_reloc_code_real reloc_type;
9710 unsigned char *opcode;
9713 if (fragP->fr_var != NO_RELOC)
9714 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9716 reloc_type = BFD_RELOC_16_PCREL;
9717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9718 else if (need_plt32_p (fragP->fr_symbol))
9719 reloc_type = BFD_RELOC_X86_64_PLT32;
9722 reloc_type = BFD_RELOC_32_PCREL;
9724 old_fr_fix = fragP->fr_fix;
9725 opcode = (unsigned char *) fragP->fr_opcode;
9727 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9730 /* Make jmp (0xeb) a (d)word displacement jump. */
9732 fragP->fr_fix += size;
9733 fix_new (fragP, old_fr_fix, size,
9735 fragP->fr_offset, 1,
9741 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9743 /* Negate the condition, and branch past an
9744 unconditional jump. */
9747 /* Insert an unconditional jump. */
9749 /* We added two extra opcode bytes, and have a two byte
9751 fragP->fr_fix += 2 + 2;
9752 fix_new (fragP, old_fr_fix + 2, 2,
9754 fragP->fr_offset, 1,
9761 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9766 fixP = fix_new (fragP, old_fr_fix, 1,
9768 fragP->fr_offset, 1,
9770 fixP->fx_signed = 1;
9774 /* This changes the byte-displacement jump 0x7N
9775 to the (d)word-displacement jump 0x0f,0x8N. */
9776 opcode[1] = opcode[0] + 0x10;
9777 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9778 /* We've added an opcode byte. */
9779 fragP->fr_fix += 1 + size;
9780 fix_new (fragP, old_fr_fix + 1, size,
9782 fragP->fr_offset, 1,
9787 BAD_CASE (fragP->fr_subtype);
9791 return fragP->fr_fix - old_fr_fix;
9794 /* Guess size depending on current relax state. Initially the relax
9795 state will correspond to a short jump and we return 1, because
9796 the variable part of the frag (the branch offset) is one byte
9797 long. However, we can relax a section more than once and in that
9798 case we must either set fr_subtype back to the unrelaxed state,
9799 or return the value for the appropriate branch. */
9800 return md_relax_table[fragP->fr_subtype].rlx_length;
9803 /* Called after relax() is finished.
9805 In: Address of frag.
9806 fr_type == rs_machine_dependent.
9807 fr_subtype is what the address relaxed to.
9809 Out: Any fixSs and constants are set up.
9810 Caller will turn frag into a ".space 0". */
9813 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9816 unsigned char *opcode;
9817 unsigned char *where_to_put_displacement = NULL;
9818 offsetT target_address;
9819 offsetT opcode_address;
9820 unsigned int extension = 0;
9821 offsetT displacement_from_opcode_start;
9823 opcode = (unsigned char *) fragP->fr_opcode;
9825 /* Address we want to reach in file space. */
9826 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9828 /* Address opcode resides at in file space. */
9829 opcode_address = fragP->fr_address + fragP->fr_fix;
9831 /* Displacement from opcode start to fill into instruction. */
9832 displacement_from_opcode_start = target_address - opcode_address;
9834 if ((fragP->fr_subtype & BIG) == 0)
9836 /* Don't have to change opcode. */
9837 extension = 1; /* 1 opcode + 1 displacement */
9838 where_to_put_displacement = &opcode[1];
9842 if (no_cond_jump_promotion
9843 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9844 as_warn_where (fragP->fr_file, fragP->fr_line,
9845 _("long jump required"));
9847 switch (fragP->fr_subtype)
9849 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9850 extension = 4; /* 1 opcode + 4 displacement */
9852 where_to_put_displacement = &opcode[1];
9855 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9856 extension = 2; /* 1 opcode + 2 displacement */
9858 where_to_put_displacement = &opcode[1];
9861 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9862 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9863 extension = 5; /* 2 opcode + 4 displacement */
9864 opcode[1] = opcode[0] + 0x10;
9865 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9866 where_to_put_displacement = &opcode[2];
9869 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9870 extension = 3; /* 2 opcode + 2 displacement */
9871 opcode[1] = opcode[0] + 0x10;
9872 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9873 where_to_put_displacement = &opcode[2];
9876 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9881 where_to_put_displacement = &opcode[3];
9885 BAD_CASE (fragP->fr_subtype);
9890 /* If size if less then four we are sure that the operand fits,
9891 but if it's 4, then it could be that the displacement is larger
9893 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9895 && ((addressT) (displacement_from_opcode_start - extension
9896 + ((addressT) 1 << 31))
9897 > (((addressT) 2 << 31) - 1)))
9899 as_bad_where (fragP->fr_file, fragP->fr_line,
9900 _("jump target out of range"));
9901 /* Make us emit 0. */
9902 displacement_from_opcode_start = extension;
9904 /* Now put displacement after opcode. */
9905 md_number_to_chars ((char *) where_to_put_displacement,
9906 (valueT) (displacement_from_opcode_start - extension),
9907 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9908 fragP->fr_fix += extension;
9911 /* Apply a fixup (fixP) to segment data, once it has been determined
9912 by our caller that we have all the info we need to fix it up.
9914 Parameter valP is the pointer to the value of the bits.
9916 On the 386, immediates, displacements, and data pointers are all in
9917 the same (little-endian) format, so we don't need to care about which
9921 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9923 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9924 valueT value = *valP;
9926 #if !defined (TE_Mach)
9929 switch (fixP->fx_r_type)
9935 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9938 case BFD_RELOC_X86_64_32S:
9939 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9942 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9945 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9950 if (fixP->fx_addsy != NULL
9951 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9952 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9953 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9954 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9955 && !use_rela_relocations)
9957 /* This is a hack. There should be a better way to handle this.
9958 This covers for the fact that bfd_install_relocation will
9959 subtract the current location (for partial_inplace, PC relative
9960 relocations); see more below. */
9964 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9967 value += fixP->fx_where + fixP->fx_frag->fr_address;
9969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9972 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9975 || (symbol_section_p (fixP->fx_addsy)
9976 && sym_seg != absolute_section))
9977 && !generic_force_reloc (fixP))
9979 /* Yes, we add the values in twice. This is because
9980 bfd_install_relocation subtracts them out again. I think
9981 bfd_install_relocation is broken, but I don't dare change
9983 value += fixP->fx_where + fixP->fx_frag->fr_address;
9987 #if defined (OBJ_COFF) && defined (TE_PE)
9988 /* For some reason, the PE format does not store a
9989 section address offset for a PC relative symbol. */
9990 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9991 || S_IS_WEAK (fixP->fx_addsy))
9992 value += md_pcrel_from (fixP);
9995 #if defined (OBJ_COFF) && defined (TE_PE)
9996 if (fixP->fx_addsy != NULL
9997 && S_IS_WEAK (fixP->fx_addsy)
9998 /* PR 16858: Do not modify weak function references. */
9999 && ! fixP->fx_pcrel)
10001 #if !defined (TE_PEP)
10002 /* For x86 PE weak function symbols are neither PC-relative
10003 nor do they set S_IS_FUNCTION. So the only reliable way
10004 to detect them is to check the flags of their containing
10006 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10007 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10011 value -= S_GET_VALUE (fixP->fx_addsy);
10015 /* Fix a few things - the dynamic linker expects certain values here,
10016 and we must not disappoint it. */
10017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10018 if (IS_ELF && fixP->fx_addsy)
10019 switch (fixP->fx_r_type)
10021 case BFD_RELOC_386_PLT32:
10022 case BFD_RELOC_X86_64_PLT32:
10023 /* Make the jump instruction point to the address of the operand. At
10024 runtime we merely add the offset to the actual PLT entry. */
10028 case BFD_RELOC_386_TLS_GD:
10029 case BFD_RELOC_386_TLS_LDM:
10030 case BFD_RELOC_386_TLS_IE_32:
10031 case BFD_RELOC_386_TLS_IE:
10032 case BFD_RELOC_386_TLS_GOTIE:
10033 case BFD_RELOC_386_TLS_GOTDESC:
10034 case BFD_RELOC_X86_64_TLSGD:
10035 case BFD_RELOC_X86_64_TLSLD:
10036 case BFD_RELOC_X86_64_GOTTPOFF:
10037 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10038 value = 0; /* Fully resolved at runtime. No addend. */
10040 case BFD_RELOC_386_TLS_LE:
10041 case BFD_RELOC_386_TLS_LDO_32:
10042 case BFD_RELOC_386_TLS_LE_32:
10043 case BFD_RELOC_X86_64_DTPOFF32:
10044 case BFD_RELOC_X86_64_DTPOFF64:
10045 case BFD_RELOC_X86_64_TPOFF32:
10046 case BFD_RELOC_X86_64_TPOFF64:
10047 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10050 case BFD_RELOC_386_TLS_DESC_CALL:
10051 case BFD_RELOC_X86_64_TLSDESC_CALL:
10052 value = 0; /* Fully resolved at runtime. No addend. */
10053 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10057 case BFD_RELOC_VTABLE_INHERIT:
10058 case BFD_RELOC_VTABLE_ENTRY:
10065 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10067 #endif /* !defined (TE_Mach) */
10069 /* Are we finished with this relocation now? */
10070 if (fixP->fx_addsy == NULL)
10072 #if defined (OBJ_COFF) && defined (TE_PE)
10073 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10076 /* Remember value for tc_gen_reloc. */
10077 fixP->fx_addnumber = value;
10078 /* Clear out the frag for now. */
10082 else if (use_rela_relocations)
10084 fixP->fx_no_overflow = 1;
10085 /* Remember value for tc_gen_reloc. */
10086 fixP->fx_addnumber = value;
10090 md_number_to_chars (p, value, fixP->fx_size);
10094 md_atof (int type, char *litP, int *sizeP)
10096 /* This outputs the LITTLENUMs in REVERSE order;
10097 in accord with the bigendian 386. */
10098 return ieee_md_atof (type, litP, sizeP, FALSE);
10101 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10104 output_invalid (int c)
10107 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10110 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10111 "(0x%x)", (unsigned char) c);
10112 return output_invalid_buf;
10115 /* REG_STRING starts *before* REGISTER_PREFIX. */
10117 static const reg_entry *
10118 parse_real_register (char *reg_string, char **end_op)
10120 char *s = reg_string;
10122 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10123 const reg_entry *r;
10125 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10126 if (*s == REGISTER_PREFIX)
10129 if (is_space_char (*s))
10132 p = reg_name_given;
10133 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10135 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10136 return (const reg_entry *) NULL;
10140 /* For naked regs, make sure that we are not dealing with an identifier.
10141 This prevents confusing an identifier like `eax_var' with register
10143 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10144 return (const reg_entry *) NULL;
10148 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10150 /* Handle floating point regs, allowing spaces in the (i) part. */
10151 if (r == i386_regtab /* %st is first entry of table */)
10153 if (!cpu_arch_flags.bitfield.cpu8087
10154 && !cpu_arch_flags.bitfield.cpu287
10155 && !cpu_arch_flags.bitfield.cpu387)
10156 return (const reg_entry *) NULL;
10158 if (is_space_char (*s))
10163 if (is_space_char (*s))
10165 if (*s >= '0' && *s <= '7')
10167 int fpr = *s - '0';
10169 if (is_space_char (*s))
10174 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10179 /* We have "%st(" then garbage. */
10180 return (const reg_entry *) NULL;
10184 if (r == NULL || allow_pseudo_reg)
10187 if (operand_type_all_zero (&r->reg_type))
10188 return (const reg_entry *) NULL;
10190 if ((r->reg_type.bitfield.dword
10191 || r->reg_type.bitfield.sreg3
10192 || r->reg_type.bitfield.control
10193 || r->reg_type.bitfield.debug
10194 || r->reg_type.bitfield.test)
10195 && !cpu_arch_flags.bitfield.cpui386)
10196 return (const reg_entry *) NULL;
10198 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10199 return (const reg_entry *) NULL;
10201 if (!cpu_arch_flags.bitfield.cpuavx512f)
10203 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10204 return (const reg_entry *) NULL;
10206 if (!cpu_arch_flags.bitfield.cpuavx)
10208 if (r->reg_type.bitfield.ymmword)
10209 return (const reg_entry *) NULL;
10211 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10212 return (const reg_entry *) NULL;
10216 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10217 return (const reg_entry *) NULL;
10219 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10220 if (!allow_index_reg
10221 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10222 return (const reg_entry *) NULL;
10224 /* Upper 16 vector registers are only available with VREX in 64bit
10225 mode, and require EVEX encoding. */
10226 if (r->reg_flags & RegVRex)
10228 if (!cpu_arch_flags.bitfield.cpuvrex
10229 || flag_code != CODE_64BIT)
10230 return (const reg_entry *) NULL;
10232 i.vec_encoding = vex_encoding_evex;
10235 if (((r->reg_flags & (RegRex64 | RegRex))
10236 || r->reg_type.bitfield.qword)
10237 && (!cpu_arch_flags.bitfield.cpulm
10238 || !operand_type_equal (&r->reg_type, &control))
10239 && flag_code != CODE_64BIT)
10240 return (const reg_entry *) NULL;
10242 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10243 return (const reg_entry *) NULL;
10248 /* REG_STRING starts *before* REGISTER_PREFIX. */
10250 static const reg_entry *
10251 parse_register (char *reg_string, char **end_op)
10253 const reg_entry *r;
10255 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10256 r = parse_real_register (reg_string, end_op);
10261 char *save = input_line_pointer;
10265 input_line_pointer = reg_string;
10266 c = get_symbol_name (®_string);
10267 symbolP = symbol_find (reg_string);
10268 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10270 const expressionS *e = symbol_get_value_expression (symbolP);
10272 know (e->X_op == O_register);
10273 know (e->X_add_number >= 0
10274 && (valueT) e->X_add_number < i386_regtab_size);
10275 r = i386_regtab + e->X_add_number;
10276 if ((r->reg_flags & RegVRex))
10277 i.vec_encoding = vex_encoding_evex;
10278 *end_op = input_line_pointer;
10280 *input_line_pointer = c;
10281 input_line_pointer = save;
10287 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10289 const reg_entry *r;
10290 char *end = input_line_pointer;
10293 r = parse_register (name, &input_line_pointer);
10294 if (r && end <= input_line_pointer)
10296 *nextcharP = *input_line_pointer;
10297 *input_line_pointer = 0;
10298 e->X_op = O_register;
10299 e->X_add_number = r - i386_regtab;
10302 input_line_pointer = end;
10304 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10308 md_operand (expressionS *e)
10311 const reg_entry *r;
10313 switch (*input_line_pointer)
10315 case REGISTER_PREFIX:
10316 r = parse_real_register (input_line_pointer, &end);
10319 e->X_op = O_register;
10320 e->X_add_number = r - i386_regtab;
10321 input_line_pointer = end;
10326 gas_assert (intel_syntax);
10327 end = input_line_pointer++;
10329 if (*input_line_pointer == ']')
10331 ++input_line_pointer;
10332 e->X_op_symbol = make_expr_symbol (e);
10333 e->X_add_symbol = NULL;
10334 e->X_add_number = 0;
10339 e->X_op = O_absent;
10340 input_line_pointer = end;
10347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10348 const char *md_shortopts = "kVQ:sqnO::";
10350 const char *md_shortopts = "qnO::";
10353 #define OPTION_32 (OPTION_MD_BASE + 0)
10354 #define OPTION_64 (OPTION_MD_BASE + 1)
10355 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10356 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10357 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10358 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10359 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10360 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10361 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10362 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10363 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10364 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10365 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10366 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10367 #define OPTION_X32 (OPTION_MD_BASE + 14)
10368 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10369 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10370 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10371 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10372 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10373 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10374 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10375 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10376 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10377 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10379 struct option md_longopts[] =
10381 {"32", no_argument, NULL, OPTION_32},
10382 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10383 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10384 {"64", no_argument, NULL, OPTION_64},
10386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10387 {"x32", no_argument, NULL, OPTION_X32},
10388 {"mshared", no_argument, NULL, OPTION_MSHARED},
10390 {"divide", no_argument, NULL, OPTION_DIVIDE},
10391 {"march", required_argument, NULL, OPTION_MARCH},
10392 {"mtune", required_argument, NULL, OPTION_MTUNE},
10393 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10394 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10395 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10396 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10397 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10398 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10399 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10400 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10401 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10402 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10403 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10404 # if defined (TE_PE) || defined (TE_PEP)
10405 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10407 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10408 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10409 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10410 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10411 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10412 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10413 {NULL, no_argument, NULL, 0}
10415 size_t md_longopts_size = sizeof (md_longopts);
10418 md_parse_option (int c, const char *arg)
10421 char *arch, *next, *saved;
10426 optimize_align_code = 0;
10430 quiet_warnings = 1;
10433 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10434 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10435 should be emitted or not. FIXME: Not implemented. */
10439 /* -V: SVR4 argument to print version ID. */
10441 print_version_id ();
10444 /* -k: Ignore for FreeBSD compatibility. */
10449 /* -s: On i386 Solaris, this tells the native assembler to use
10450 .stab instead of .stab.excl. We always use .stab anyhow. */
10453 case OPTION_MSHARED:
10457 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10458 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10461 const char **list, **l;
10463 list = bfd_target_list ();
10464 for (l = list; *l != NULL; l++)
10465 if (CONST_STRNEQ (*l, "elf64-x86-64")
10466 || strcmp (*l, "coff-x86-64") == 0
10467 || strcmp (*l, "pe-x86-64") == 0
10468 || strcmp (*l, "pei-x86-64") == 0
10469 || strcmp (*l, "mach-o-x86-64") == 0)
10471 default_arch = "x86_64";
10475 as_fatal (_("no compiled in support for x86_64"));
10481 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10485 const char **list, **l;
10487 list = bfd_target_list ();
10488 for (l = list; *l != NULL; l++)
10489 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10491 default_arch = "x86_64:32";
10495 as_fatal (_("no compiled in support for 32bit x86_64"));
10499 as_fatal (_("32bit x86_64 is only supported for ELF"));
10504 default_arch = "i386";
10507 case OPTION_DIVIDE:
10508 #ifdef SVR4_COMMENT_CHARS
10513 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10515 for (s = i386_comment_chars; *s != '\0'; s++)
10519 i386_comment_chars = n;
10525 saved = xstrdup (arg);
10527 /* Allow -march=+nosse. */
10533 as_fatal (_("invalid -march= option: `%s'"), arg);
10534 next = strchr (arch, '+');
10537 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10539 if (strcmp (arch, cpu_arch [j].name) == 0)
10542 if (! cpu_arch[j].flags.bitfield.cpui386)
10545 cpu_arch_name = cpu_arch[j].name;
10546 cpu_sub_arch_name = NULL;
10547 cpu_arch_flags = cpu_arch[j].flags;
10548 cpu_arch_isa = cpu_arch[j].type;
10549 cpu_arch_isa_flags = cpu_arch[j].flags;
10550 if (!cpu_arch_tune_set)
10552 cpu_arch_tune = cpu_arch_isa;
10553 cpu_arch_tune_flags = cpu_arch_isa_flags;
10557 else if (*cpu_arch [j].name == '.'
10558 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10560 /* ISA extension. */
10561 i386_cpu_flags flags;
10563 flags = cpu_flags_or (cpu_arch_flags,
10564 cpu_arch[j].flags);
10566 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10568 if (cpu_sub_arch_name)
10570 char *name = cpu_sub_arch_name;
10571 cpu_sub_arch_name = concat (name,
10573 (const char *) NULL);
10577 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10578 cpu_arch_flags = flags;
10579 cpu_arch_isa_flags = flags;
10583 = cpu_flags_or (cpu_arch_isa_flags,
10584 cpu_arch[j].flags);
10589 if (j >= ARRAY_SIZE (cpu_arch))
10591 /* Disable an ISA extension. */
10592 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10593 if (strcmp (arch, cpu_noarch [j].name) == 0)
10595 i386_cpu_flags flags;
10597 flags = cpu_flags_and_not (cpu_arch_flags,
10598 cpu_noarch[j].flags);
10599 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10601 if (cpu_sub_arch_name)
10603 char *name = cpu_sub_arch_name;
10604 cpu_sub_arch_name = concat (arch,
10605 (const char *) NULL);
10609 cpu_sub_arch_name = xstrdup (arch);
10610 cpu_arch_flags = flags;
10611 cpu_arch_isa_flags = flags;
10616 if (j >= ARRAY_SIZE (cpu_noarch))
10617 j = ARRAY_SIZE (cpu_arch);
10620 if (j >= ARRAY_SIZE (cpu_arch))
10621 as_fatal (_("invalid -march= option: `%s'"), arg);
10625 while (next != NULL);
10631 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10632 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10634 if (strcmp (arg, cpu_arch [j].name) == 0)
10636 cpu_arch_tune_set = 1;
10637 cpu_arch_tune = cpu_arch [j].type;
10638 cpu_arch_tune_flags = cpu_arch[j].flags;
10642 if (j >= ARRAY_SIZE (cpu_arch))
10643 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10646 case OPTION_MMNEMONIC:
10647 if (strcasecmp (arg, "att") == 0)
10648 intel_mnemonic = 0;
10649 else if (strcasecmp (arg, "intel") == 0)
10650 intel_mnemonic = 1;
10652 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10655 case OPTION_MSYNTAX:
10656 if (strcasecmp (arg, "att") == 0)
10658 else if (strcasecmp (arg, "intel") == 0)
10661 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10664 case OPTION_MINDEX_REG:
10665 allow_index_reg = 1;
10668 case OPTION_MNAKED_REG:
10669 allow_naked_reg = 1;
10672 case OPTION_MSSE2AVX:
10676 case OPTION_MSSE_CHECK:
10677 if (strcasecmp (arg, "error") == 0)
10678 sse_check = check_error;
10679 else if (strcasecmp (arg, "warning") == 0)
10680 sse_check = check_warning;
10681 else if (strcasecmp (arg, "none") == 0)
10682 sse_check = check_none;
10684 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10687 case OPTION_MOPERAND_CHECK:
10688 if (strcasecmp (arg, "error") == 0)
10689 operand_check = check_error;
10690 else if (strcasecmp (arg, "warning") == 0)
10691 operand_check = check_warning;
10692 else if (strcasecmp (arg, "none") == 0)
10693 operand_check = check_none;
10695 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10698 case OPTION_MAVXSCALAR:
10699 if (strcasecmp (arg, "128") == 0)
10700 avxscalar = vex128;
10701 else if (strcasecmp (arg, "256") == 0)
10702 avxscalar = vex256;
10704 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10707 case OPTION_MADD_BND_PREFIX:
10708 add_bnd_prefix = 1;
10711 case OPTION_MEVEXLIG:
10712 if (strcmp (arg, "128") == 0)
10713 evexlig = evexl128;
10714 else if (strcmp (arg, "256") == 0)
10715 evexlig = evexl256;
10716 else if (strcmp (arg, "512") == 0)
10717 evexlig = evexl512;
10719 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10722 case OPTION_MEVEXRCIG:
10723 if (strcmp (arg, "rne") == 0)
10725 else if (strcmp (arg, "rd") == 0)
10727 else if (strcmp (arg, "ru") == 0)
10729 else if (strcmp (arg, "rz") == 0)
10732 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10735 case OPTION_MEVEXWIG:
10736 if (strcmp (arg, "0") == 0)
10738 else if (strcmp (arg, "1") == 0)
10741 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10744 # if defined (TE_PE) || defined (TE_PEP)
10745 case OPTION_MBIG_OBJ:
10750 case OPTION_MOMIT_LOCK_PREFIX:
10751 if (strcasecmp (arg, "yes") == 0)
10752 omit_lock_prefix = 1;
10753 else if (strcasecmp (arg, "no") == 0)
10754 omit_lock_prefix = 0;
10756 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10759 case OPTION_MFENCE_AS_LOCK_ADD:
10760 if (strcasecmp (arg, "yes") == 0)
10762 else if (strcasecmp (arg, "no") == 0)
10765 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10768 case OPTION_MRELAX_RELOCATIONS:
10769 if (strcasecmp (arg, "yes") == 0)
10770 generate_relax_relocations = 1;
10771 else if (strcasecmp (arg, "no") == 0)
10772 generate_relax_relocations = 0;
10774 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10777 case OPTION_MAMD64:
10781 case OPTION_MINTEL64:
10789 /* Turn off -Os. */
10790 optimize_for_space = 0;
10792 else if (*arg == 's')
10794 optimize_for_space = 1;
10795 /* Turn on all encoding optimizations. */
10800 optimize = atoi (arg);
10801 /* Turn off -Os. */
10802 optimize_for_space = 0;
10812 #define MESSAGE_TEMPLATE \
10816 output_message (FILE *stream, char *p, char *message, char *start,
10817 int *left_p, const char *name, int len)
10819 int size = sizeof (MESSAGE_TEMPLATE);
10820 int left = *left_p;
10822 /* Reserve 2 spaces for ", " or ",\0" */
10825 /* Check if there is any room. */
10833 p = mempcpy (p, name, len);
10837 /* Output the current message now and start a new one. */
10840 fprintf (stream, "%s\n", message);
10842 left = size - (start - message) - len - 2;
10844 gas_assert (left >= 0);
10846 p = mempcpy (p, name, len);
10854 show_arch (FILE *stream, int ext, int check)
10856 static char message[] = MESSAGE_TEMPLATE;
10857 char *start = message + 27;
10859 int size = sizeof (MESSAGE_TEMPLATE);
10866 left = size - (start - message);
10867 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10869 /* Should it be skipped? */
10870 if (cpu_arch [j].skip)
10873 name = cpu_arch [j].name;
10874 len = cpu_arch [j].len;
10877 /* It is an extension. Skip if we aren't asked to show it. */
10888 /* It is an processor. Skip if we show only extension. */
10891 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10893 /* It is an impossible processor - skip. */
10897 p = output_message (stream, p, message, start, &left, name, len);
10900 /* Display disabled extensions. */
10902 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10904 name = cpu_noarch [j].name;
10905 len = cpu_noarch [j].len;
10906 p = output_message (stream, p, message, start, &left, name,
10911 fprintf (stream, "%s\n", message);
10915 md_show_usage (FILE *stream)
10917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10918 fprintf (stream, _("\
10920 -V print assembler version number\n\
10923 fprintf (stream, _("\
10924 -n Do not optimize code alignment\n\
10925 -q quieten some warnings\n"));
10926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10927 fprintf (stream, _("\
10930 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10931 || defined (TE_PE) || defined (TE_PEP))
10932 fprintf (stream, _("\
10933 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10935 #ifdef SVR4_COMMENT_CHARS
10936 fprintf (stream, _("\
10937 --divide do not treat `/' as a comment character\n"));
10939 fprintf (stream, _("\
10940 --divide ignored\n"));
10942 fprintf (stream, _("\
10943 -march=CPU[,+EXTENSION...]\n\
10944 generate code for CPU and EXTENSION, CPU is one of:\n"));
10945 show_arch (stream, 0, 1);
10946 fprintf (stream, _("\
10947 EXTENSION is combination of:\n"));
10948 show_arch (stream, 1, 0);
10949 fprintf (stream, _("\
10950 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10951 show_arch (stream, 0, 0);
10952 fprintf (stream, _("\
10953 -msse2avx encode SSE instructions with VEX prefix\n"));
10954 fprintf (stream, _("\
10955 -msse-check=[none|error|warning]\n\
10956 check SSE instructions\n"));
10957 fprintf (stream, _("\
10958 -moperand-check=[none|error|warning]\n\
10959 check operand combinations for validity\n"));
10960 fprintf (stream, _("\
10961 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10963 fprintf (stream, _("\
10964 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10966 fprintf (stream, _("\
10967 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10968 for EVEX.W bit ignored instructions\n"));
10969 fprintf (stream, _("\
10970 -mevexrcig=[rne|rd|ru|rz]\n\
10971 encode EVEX instructions with specific EVEX.RC value\n\
10972 for SAE-only ignored instructions\n"));
10973 fprintf (stream, _("\
10974 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10975 fprintf (stream, _("\
10976 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10977 fprintf (stream, _("\
10978 -mindex-reg support pseudo index registers\n"));
10979 fprintf (stream, _("\
10980 -mnaked-reg don't require `%%' prefix for registers\n"));
10981 fprintf (stream, _("\
10982 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10983 fprintf (stream, _("\
10984 -mshared disable branch optimization for shared code\n"));
10985 # if defined (TE_PE) || defined (TE_PEP)
10986 fprintf (stream, _("\
10987 -mbig-obj generate big object files\n"));
10989 fprintf (stream, _("\
10990 -momit-lock-prefix=[no|yes]\n\
10991 strip all lock prefixes\n"));
10992 fprintf (stream, _("\
10993 -mfence-as-lock-add=[no|yes]\n\
10994 encode lfence, mfence and sfence as\n\
10995 lock addl $0x0, (%%{re}sp)\n"));
10996 fprintf (stream, _("\
10997 -mrelax-relocations=[no|yes]\n\
10998 generate relax relocations\n"));
10999 fprintf (stream, _("\
11000 -mamd64 accept only AMD64 ISA\n"));
11001 fprintf (stream, _("\
11002 -mintel64 accept only Intel64 ISA\n"));
11005 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11006 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11007 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11009 /* Pick the target format to use. */
11012 i386_target_format (void)
11014 if (!strncmp (default_arch, "x86_64", 6))
11016 update_code_flag (CODE_64BIT, 1);
11017 if (default_arch[6] == '\0')
11018 x86_elf_abi = X86_64_ABI;
11020 x86_elf_abi = X86_64_X32_ABI;
11022 else if (!strcmp (default_arch, "i386"))
11023 update_code_flag (CODE_32BIT, 1);
11024 else if (!strcmp (default_arch, "iamcu"))
11026 update_code_flag (CODE_32BIT, 1);
11027 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11029 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11030 cpu_arch_name = "iamcu";
11031 cpu_sub_arch_name = NULL;
11032 cpu_arch_flags = iamcu_flags;
11033 cpu_arch_isa = PROCESSOR_IAMCU;
11034 cpu_arch_isa_flags = iamcu_flags;
11035 if (!cpu_arch_tune_set)
11037 cpu_arch_tune = cpu_arch_isa;
11038 cpu_arch_tune_flags = cpu_arch_isa_flags;
11041 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11042 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11046 as_fatal (_("unknown architecture"));
11048 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11049 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11050 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11051 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11053 switch (OUTPUT_FLAVOR)
11055 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11056 case bfd_target_aout_flavour:
11057 return AOUT_TARGET_FORMAT;
11059 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11060 # if defined (TE_PE) || defined (TE_PEP)
11061 case bfd_target_coff_flavour:
11062 if (flag_code == CODE_64BIT)
11063 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11066 # elif defined (TE_GO32)
11067 case bfd_target_coff_flavour:
11068 return "coff-go32";
11070 case bfd_target_coff_flavour:
11071 return "coff-i386";
11074 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11075 case bfd_target_elf_flavour:
11077 const char *format;
11079 switch (x86_elf_abi)
11082 format = ELF_TARGET_FORMAT;
11085 use_rela_relocations = 1;
11087 format = ELF_TARGET_FORMAT64;
11089 case X86_64_X32_ABI:
11090 use_rela_relocations = 1;
11092 disallow_64bit_reloc = 1;
11093 format = ELF_TARGET_FORMAT32;
11096 if (cpu_arch_isa == PROCESSOR_L1OM)
11098 if (x86_elf_abi != X86_64_ABI)
11099 as_fatal (_("Intel L1OM is 64bit only"));
11100 return ELF_TARGET_L1OM_FORMAT;
11102 else if (cpu_arch_isa == PROCESSOR_K1OM)
11104 if (x86_elf_abi != X86_64_ABI)
11105 as_fatal (_("Intel K1OM is 64bit only"));
11106 return ELF_TARGET_K1OM_FORMAT;
11108 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11110 if (x86_elf_abi != I386_ABI)
11111 as_fatal (_("Intel MCU is 32bit only"));
11112 return ELF_TARGET_IAMCU_FORMAT;
11118 #if defined (OBJ_MACH_O)
11119 case bfd_target_mach_o_flavour:
11120 if (flag_code == CODE_64BIT)
11122 use_rela_relocations = 1;
11124 return "mach-o-x86-64";
11127 return "mach-o-i386";
11135 #endif /* OBJ_MAYBE_ more than one */
11138 md_undefined_symbol (char *name)
11140 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11141 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11142 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11143 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11147 if (symbol_find (name))
11148 as_bad (_("GOT already in symbol table"));
11149 GOT_symbol = symbol_new (name, undefined_section,
11150 (valueT) 0, &zero_address_frag);
11157 /* Round up a section size to the appropriate boundary. */
11160 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11162 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11163 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11165 /* For a.out, force the section size to be aligned. If we don't do
11166 this, BFD will align it for us, but it will not write out the
11167 final bytes of the section. This may be a bug in BFD, but it is
11168 easier to fix it here since that is how the other a.out targets
11172 align = bfd_get_section_alignment (stdoutput, segment);
11173 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11180 /* On the i386, PC-relative offsets are relative to the start of the
11181 next instruction. That is, the address of the offset, plus its
11182 size, since the offset is always the last part of the insn. */
11185 md_pcrel_from (fixS *fixP)
11187 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11193 s_bss (int ignore ATTRIBUTE_UNUSED)
11197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11199 obj_elf_section_change_hook ();
11201 temp = get_absolute_expression ();
11202 subseg_set (bss_section, (subsegT) temp);
11203 demand_empty_rest_of_line ();
11209 i386_validate_fix (fixS *fixp)
11211 if (fixp->fx_subsy)
11213 if (fixp->fx_subsy == GOT_symbol)
11215 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11220 if (fixp->fx_tcbit2)
11221 fixp->fx_r_type = (fixp->fx_tcbit
11222 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11223 : BFD_RELOC_X86_64_GOTPCRELX);
11226 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11231 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11233 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11235 fixp->fx_subsy = 0;
11238 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11239 else if (!object_64bit)
11241 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11242 && fixp->fx_tcbit2)
11243 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11249 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11252 bfd_reloc_code_real_type code;
11254 switch (fixp->fx_r_type)
11256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11257 case BFD_RELOC_SIZE32:
11258 case BFD_RELOC_SIZE64:
11259 if (S_IS_DEFINED (fixp->fx_addsy)
11260 && !S_IS_EXTERNAL (fixp->fx_addsy))
11262 /* Resolve size relocation against local symbol to size of
11263 the symbol plus addend. */
11264 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11265 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11266 && !fits_in_unsigned_long (value))
11267 as_bad_where (fixp->fx_file, fixp->fx_line,
11268 _("symbol size computation overflow"));
11269 fixp->fx_addsy = NULL;
11270 fixp->fx_subsy = NULL;
11271 md_apply_fix (fixp, (valueT *) &value, NULL);
11275 /* Fall through. */
11277 case BFD_RELOC_X86_64_PLT32:
11278 case BFD_RELOC_X86_64_GOT32:
11279 case BFD_RELOC_X86_64_GOTPCREL:
11280 case BFD_RELOC_X86_64_GOTPCRELX:
11281 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11282 case BFD_RELOC_386_PLT32:
11283 case BFD_RELOC_386_GOT32:
11284 case BFD_RELOC_386_GOT32X:
11285 case BFD_RELOC_386_GOTOFF:
11286 case BFD_RELOC_386_GOTPC:
11287 case BFD_RELOC_386_TLS_GD:
11288 case BFD_RELOC_386_TLS_LDM:
11289 case BFD_RELOC_386_TLS_LDO_32:
11290 case BFD_RELOC_386_TLS_IE_32:
11291 case BFD_RELOC_386_TLS_IE:
11292 case BFD_RELOC_386_TLS_GOTIE:
11293 case BFD_RELOC_386_TLS_LE_32:
11294 case BFD_RELOC_386_TLS_LE:
11295 case BFD_RELOC_386_TLS_GOTDESC:
11296 case BFD_RELOC_386_TLS_DESC_CALL:
11297 case BFD_RELOC_X86_64_TLSGD:
11298 case BFD_RELOC_X86_64_TLSLD:
11299 case BFD_RELOC_X86_64_DTPOFF32:
11300 case BFD_RELOC_X86_64_DTPOFF64:
11301 case BFD_RELOC_X86_64_GOTTPOFF:
11302 case BFD_RELOC_X86_64_TPOFF32:
11303 case BFD_RELOC_X86_64_TPOFF64:
11304 case BFD_RELOC_X86_64_GOTOFF64:
11305 case BFD_RELOC_X86_64_GOTPC32:
11306 case BFD_RELOC_X86_64_GOT64:
11307 case BFD_RELOC_X86_64_GOTPCREL64:
11308 case BFD_RELOC_X86_64_GOTPC64:
11309 case BFD_RELOC_X86_64_GOTPLT64:
11310 case BFD_RELOC_X86_64_PLTOFF64:
11311 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11312 case BFD_RELOC_X86_64_TLSDESC_CALL:
11313 case BFD_RELOC_RVA:
11314 case BFD_RELOC_VTABLE_ENTRY:
11315 case BFD_RELOC_VTABLE_INHERIT:
11317 case BFD_RELOC_32_SECREL:
11319 code = fixp->fx_r_type;
11321 case BFD_RELOC_X86_64_32S:
11322 if (!fixp->fx_pcrel)
11324 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11325 code = fixp->fx_r_type;
11328 /* Fall through. */
11330 if (fixp->fx_pcrel)
11332 switch (fixp->fx_size)
11335 as_bad_where (fixp->fx_file, fixp->fx_line,
11336 _("can not do %d byte pc-relative relocation"),
11338 code = BFD_RELOC_32_PCREL;
11340 case 1: code = BFD_RELOC_8_PCREL; break;
11341 case 2: code = BFD_RELOC_16_PCREL; break;
11342 case 4: code = BFD_RELOC_32_PCREL; break;
11344 case 8: code = BFD_RELOC_64_PCREL; break;
11350 switch (fixp->fx_size)
11353 as_bad_where (fixp->fx_file, fixp->fx_line,
11354 _("can not do %d byte relocation"),
11356 code = BFD_RELOC_32;
11358 case 1: code = BFD_RELOC_8; break;
11359 case 2: code = BFD_RELOC_16; break;
11360 case 4: code = BFD_RELOC_32; break;
11362 case 8: code = BFD_RELOC_64; break;
11369 if ((code == BFD_RELOC_32
11370 || code == BFD_RELOC_32_PCREL
11371 || code == BFD_RELOC_X86_64_32S)
11373 && fixp->fx_addsy == GOT_symbol)
11376 code = BFD_RELOC_386_GOTPC;
11378 code = BFD_RELOC_X86_64_GOTPC32;
11380 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11382 && fixp->fx_addsy == GOT_symbol)
11384 code = BFD_RELOC_X86_64_GOTPC64;
11387 rel = XNEW (arelent);
11388 rel->sym_ptr_ptr = XNEW (asymbol *);
11389 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11391 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11393 if (!use_rela_relocations)
11395 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11396 vtable entry to be used in the relocation's section offset. */
11397 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11398 rel->address = fixp->fx_offset;
11399 #if defined (OBJ_COFF) && defined (TE_PE)
11400 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11401 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11406 /* Use the rela in 64bit mode. */
11409 if (disallow_64bit_reloc)
11412 case BFD_RELOC_X86_64_DTPOFF64:
11413 case BFD_RELOC_X86_64_TPOFF64:
11414 case BFD_RELOC_64_PCREL:
11415 case BFD_RELOC_X86_64_GOTOFF64:
11416 case BFD_RELOC_X86_64_GOT64:
11417 case BFD_RELOC_X86_64_GOTPCREL64:
11418 case BFD_RELOC_X86_64_GOTPC64:
11419 case BFD_RELOC_X86_64_GOTPLT64:
11420 case BFD_RELOC_X86_64_PLTOFF64:
11421 as_bad_where (fixp->fx_file, fixp->fx_line,
11422 _("cannot represent relocation type %s in x32 mode"),
11423 bfd_get_reloc_code_name (code));
11429 if (!fixp->fx_pcrel)
11430 rel->addend = fixp->fx_offset;
11434 case BFD_RELOC_X86_64_PLT32:
11435 case BFD_RELOC_X86_64_GOT32:
11436 case BFD_RELOC_X86_64_GOTPCREL:
11437 case BFD_RELOC_X86_64_GOTPCRELX:
11438 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11439 case BFD_RELOC_X86_64_TLSGD:
11440 case BFD_RELOC_X86_64_TLSLD:
11441 case BFD_RELOC_X86_64_GOTTPOFF:
11442 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11443 case BFD_RELOC_X86_64_TLSDESC_CALL:
11444 rel->addend = fixp->fx_offset - fixp->fx_size;
11447 rel->addend = (section->vma
11449 + fixp->fx_addnumber
11450 + md_pcrel_from (fixp));
11455 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11456 if (rel->howto == NULL)
11458 as_bad_where (fixp->fx_file, fixp->fx_line,
11459 _("cannot represent relocation type %s"),
11460 bfd_get_reloc_code_name (code));
11461 /* Set howto to a garbage value so that we can keep going. */
11462 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11463 gas_assert (rel->howto != NULL);
11469 #include "tc-i386-intel.c"
11472 tc_x86_parse_to_dw2regnum (expressionS *exp)
11474 int saved_naked_reg;
11475 char saved_register_dot;
11477 saved_naked_reg = allow_naked_reg;
11478 allow_naked_reg = 1;
11479 saved_register_dot = register_chars['.'];
11480 register_chars['.'] = '.';
11481 allow_pseudo_reg = 1;
11482 expression_and_evaluate (exp);
11483 allow_pseudo_reg = 0;
11484 register_chars['.'] = saved_register_dot;
11485 allow_naked_reg = saved_naked_reg;
11487 if (exp->X_op == O_register && exp->X_add_number >= 0)
11489 if ((addressT) exp->X_add_number < i386_regtab_size)
11491 exp->X_op = O_constant;
11492 exp->X_add_number = i386_regtab[exp->X_add_number]
11493 .dw2_regnum[flag_code >> 1];
11496 exp->X_op = O_illegal;
11501 tc_x86_frame_initial_instructions (void)
11503 static unsigned int sp_regno[2];
11505 if (!sp_regno[flag_code >> 1])
11507 char *saved_input = input_line_pointer;
11508 char sp[][4] = {"esp", "rsp"};
11511 input_line_pointer = sp[flag_code >> 1];
11512 tc_x86_parse_to_dw2regnum (&exp);
11513 gas_assert (exp.X_op == O_constant);
11514 sp_regno[flag_code >> 1] = exp.X_add_number;
11515 input_line_pointer = saved_input;
11518 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11519 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11523 x86_dwarf2_addr_size (void)
11525 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11526 if (x86_elf_abi == X86_64_X32_ABI)
11529 return bfd_arch_bits_per_address (stdoutput) / 8;
11533 i386_elf_section_type (const char *str, size_t len)
11535 if (flag_code == CODE_64BIT
11536 && len == sizeof ("unwind") - 1
11537 && strncmp (str, "unwind", 6) == 0)
11538 return SHT_X86_64_UNWIND;
11545 i386_solaris_fix_up_eh_frame (segT sec)
11547 if (flag_code == CODE_64BIT)
11548 elf_section_type (sec) = SHT_X86_64_UNWIND;
11554 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11558 exp.X_op = O_secrel;
11559 exp.X_add_symbol = symbol;
11560 exp.X_add_number = 0;
11561 emit_expr (&exp, size);
11565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11566 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11569 x86_64_section_letter (int letter, const char **ptr_msg)
11571 if (flag_code == CODE_64BIT)
11574 return SHF_X86_64_LARGE;
11576 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11579 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11584 x86_64_section_word (char *str, size_t len)
11586 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11587 return SHF_X86_64_LARGE;
11593 handle_large_common (int small ATTRIBUTE_UNUSED)
11595 if (flag_code != CODE_64BIT)
11597 s_comm_internal (0, elf_common_parse);
11598 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11602 static segT lbss_section;
11603 asection *saved_com_section_ptr = elf_com_section_ptr;
11604 asection *saved_bss_section = bss_section;
11606 if (lbss_section == NULL)
11608 flagword applicable;
11609 segT seg = now_seg;
11610 subsegT subseg = now_subseg;
11612 /* The .lbss section is for local .largecomm symbols. */
11613 lbss_section = subseg_new (".lbss", 0);
11614 applicable = bfd_applicable_section_flags (stdoutput);
11615 bfd_set_section_flags (stdoutput, lbss_section,
11616 applicable & SEC_ALLOC);
11617 seg_info (lbss_section)->bss = 1;
11619 subseg_set (seg, subseg);
11622 elf_com_section_ptr = &_bfd_elf_large_com_section;
11623 bss_section = lbss_section;
11625 s_comm_internal (0, elf_common_parse);
11627 elf_com_section_ptr = saved_com_section_ptr;
11628 bss_section = saved_bss_section;
11631 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */