1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if pseudo registers are permitted. */
417 static int allow_pseudo_reg = 0;
419 /* 1 if register prefix % not required. */
420 static int allow_naked_reg = 0;
422 /* 1 if pseudo index register, eiz/riz, is allowed . */
423 static int allow_index_reg = 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix = "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size = '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code = 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings = 0;
440 static const char *cpu_arch_name = NULL;
441 static char *cpu_sub_arch_name = NULL;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set = 0;
449 /* Cpu we are generating instructions for. */
450 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags;
455 /* CPU instruction set architecture used. */
456 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
458 /* CPU feature flags of instruction set architecture used. */
459 static i386_cpu_flags cpu_arch_isa_flags;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion = 0;
465 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
466 static symbolS *GOT_symbol;
468 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
469 unsigned int x86_dwarf2_return_column;
471 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472 int x86_cie_data_alignment;
474 /* Interface to relax_segment.
475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
480 #define UNCOND_JUMP 0
482 #define COND_JUMP86 2
487 #define SMALL16 (SMALL | CODE16)
489 #define BIG16 (BIG | CODE16)
493 #define INLINE __inline__
499 #define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501 #define TYPE_FROM_RELAX_STATE(s) \
503 #define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
506 /* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
514 const relax_typeS md_relax_table[] =
517 1) most positive reach of this state,
518 2) most negative reach of this state,
519 3) how many bytes this mode will have in the variable part of the frag
520 4) which index into the table to try if we can't fit into this one. */
522 /* UNCOND_JUMP states. */
523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
538 /* word conditionals add 3 bytes to frag:
539 1 extra opcode byte, 2 displacement bytes. */
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
553 static const arch_entry cpu_arch[] =
555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
561 { "i186", PROCESSOR_UNKNOWN,
563 { "i286", PROCESSOR_UNKNOWN,
565 { "i386", PROCESSOR_I386,
567 { "i486", PROCESSOR_I486,
569 { "i586", PROCESSOR_PENTIUM,
571 { "i686", PROCESSOR_PENTIUMPRO,
573 { "pentium", PROCESSOR_PENTIUM,
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
581 { "pentium4", PROCESSOR_PENTIUM4,
583 { "prescott", PROCESSOR_NOCONA,
585 { "nocona", PROCESSOR_NOCONA,
587 { "yonah", PROCESSOR_CORE,
589 { "core", PROCESSOR_CORE,
591 { "merom", PROCESSOR_CORE2,
593 { "core2", PROCESSOR_CORE2,
595 { "k6", PROCESSOR_K6,
597 { "k6_2", PROCESSOR_K6,
599 { "athlon", PROCESSOR_ATHLON,
601 { "sledgehammer", PROCESSOR_K8,
603 { "opteron", PROCESSOR_K8,
605 { "k8", PROCESSOR_K8,
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
611 { ".sse", PROCESSOR_UNKNOWN,
613 { ".sse2", PROCESSOR_UNKNOWN,
615 { ".sse3", PROCESSOR_UNKNOWN,
617 { ".ssse3", PROCESSOR_UNKNOWN,
619 { ".sse4.1", PROCESSOR_UNKNOWN,
621 { ".sse4.2", PROCESSOR_UNKNOWN,
623 { ".sse4", PROCESSOR_UNKNOWN,
625 { ".vmx", PROCESSOR_UNKNOWN,
627 { ".smx", PROCESSOR_UNKNOWN,
629 { ".xsave", PROCESSOR_UNKNOWN,
631 { ".3dnow", PROCESSOR_UNKNOWN,
633 { ".3dnowa", PROCESSOR_UNKNOWN,
635 { ".padlock", PROCESSOR_UNKNOWN,
637 { ".pacifica", PROCESSOR_UNKNOWN,
639 { ".svme", PROCESSOR_UNKNOWN,
641 { ".sse4a", PROCESSOR_UNKNOWN,
643 { ".abm", PROCESSOR_UNKNOWN,
645 { ".sse5", PROCESSOR_UNKNOWN,
649 const pseudo_typeS md_pseudo_table[] =
651 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
654 {"align", s_align_ptwo, 0},
656 {"arch", set_cpu_arch, 0},
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
664 {"slong", signed_cons, 4},
665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
685 {"secrel32", pe_directive_secrel, 0},
690 /* For interface with expression (). */
691 extern char *input_line_pointer;
693 /* Hash table for instruction mnemonic lookup. */
694 static struct hash_control *op_hash;
696 /* Hash table for register lookup. */
697 static struct hash_control *reg_hash;
700 i386_align_code (fragS *fragP, int count)
702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
705 static const char f32_1[] =
707 static const char f32_2[] =
708 {0x66,0x90}; /* xchg %ax,%ax */
709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
766 static const char *const f16_patt[] = {
767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
770 static const char alt_3[] =
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
896 if (flag_code == CODE_16BIT)
900 memcpy (fragP->fr_literal + fragP->fr_fix,
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
911 const char *const *patt = NULL;
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
921 if (cpu_arch_isa_flags.bitfield.cpui686)
922 patt = alt_long_patt;
926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
935 case PROCESSOR_ATHLON:
937 case PROCESSOR_AMDFAM10:
938 patt = alt_short_patt;
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
950 switch (cpu_arch_tune)
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
960 case PROCESSOR_PENTIUM:
962 case PROCESSOR_ATHLON:
964 case PROCESSOR_AMDFAM10:
965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
968 if (cpu_arch_isa_flags.bitfield.cpui686)
969 patt = alt_short_patt;
973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
977 case PROCESSOR_CORE2:
978 if (cpu_arch_isa_flags.bitfield.cpui686)
979 patt = alt_long_patt;
983 case PROCESSOR_GENERIC64:
984 patt = alt_long_patt;
989 if (patt == f32_patt)
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1023 fragP->fr_var = count;
1027 operand_type_all_zero (const union i386_operand_type *x)
1029 switch (ARRAY_SIZE(x->array))
1038 return !x->array[0];
1045 operand_type_set (union i386_operand_type *x, unsigned int v)
1047 switch (ARRAY_SIZE(x->array))
1062 operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
1065 switch (ARRAY_SIZE(x->array))
1068 if (x->array[2] != y->array[2])
1071 if (x->array[1] != y->array[1])
1074 return x->array[0] == y->array[0];
1082 cpu_flags_all_zero (const union i386_cpu_flags *x)
1084 switch (ARRAY_SIZE(x->array))
1093 return !x->array[0];
1100 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1102 switch (ARRAY_SIZE(x->array))
1117 cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1120 switch (ARRAY_SIZE(x->array))
1123 if (x->array[2] != y->array[2])
1126 if (x->array[1] != y->array[1])
1129 return x->array[0] == y->array[0];
1137 cpu_flags_check_cpu64 (i386_cpu_flags f)
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1143 static INLINE i386_cpu_flags
1144 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1146 switch (ARRAY_SIZE (x.array))
1149 x.array [2] &= y.array [2];
1151 x.array [1] &= y.array [1];
1153 x.array [0] &= y.array [0];
1161 static INLINE i386_cpu_flags
1162 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1164 switch (ARRAY_SIZE (x.array))
1167 x.array [2] |= y.array [2];
1169 x.array [1] |= y.array [1];
1171 x.array [0] |= y.array [0];
1179 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1183 cpu_flags_match (i386_cpu_flags x)
1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1190 if (cpu_flags_all_zero (&x))
1194 i386_cpu_flags cpu = cpu_arch_flags;
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
1204 static INLINE i386_operand_type
1205 operand_type_and (i386_operand_type x, i386_operand_type y)
1207 switch (ARRAY_SIZE (x.array))
1210 x.array [2] &= y.array [2];
1212 x.array [1] &= y.array [1];
1214 x.array [0] &= y.array [0];
1222 static INLINE i386_operand_type
1223 operand_type_or (i386_operand_type x, i386_operand_type y)
1225 switch (ARRAY_SIZE (x.array))
1228 x.array [2] |= y.array [2];
1230 x.array [1] |= y.array [1];
1232 x.array [0] |= y.array [0];
1240 static INLINE i386_operand_type
1241 operand_type_xor (i386_operand_type x, i386_operand_type y)
1243 switch (ARRAY_SIZE (x.array))
1246 x.array [2] ^= y.array [2];
1248 x.array [1] ^= y.array [1];
1250 x.array [0] ^= y.array [0];
1258 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1261 static const i386_operand_type inoutportreg
1262 = OPERAND_TYPE_INOUTPORTREG;
1263 static const i386_operand_type reg16_inoutportreg
1264 = OPERAND_TYPE_REG16_INOUTPORTREG;
1265 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1266 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1267 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1268 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1269 static const i386_operand_type anydisp
1270 = OPERAND_TYPE_ANYDISP;
1271 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1272 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1273 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1274 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1275 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1276 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1277 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1278 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1279 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1280 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1291 operand_type_check (i386_operand_type t, enum operand_type c)
1296 return (t.bitfield.reg8
1299 || t.bitfield.reg64);
1302 return (t.bitfield.imm8
1306 || t.bitfield.imm32s
1307 || t.bitfield.imm64);
1310 return (t.bitfield.disp8
1311 || t.bitfield.disp16
1312 || t.bitfield.disp32
1313 || t.bitfield.disp32s
1314 || t.bitfield.disp64);
1317 return (t.bitfield.disp8
1318 || t.bitfield.disp16
1319 || t.bitfield.disp32
1320 || t.bitfield.disp32s
1321 || t.bitfield.disp64
1322 || t.bitfield.baseindex);
1329 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1330 operand J for instruction template T. */
1333 match_reg_size (const template *t, unsigned int j)
1335 return !((i.types[j].bitfield.byte
1336 && !t->operand_types[j].bitfield.byte)
1337 || (i.types[j].bitfield.word
1338 && !t->operand_types[j].bitfield.word)
1339 || (i.types[j].bitfield.dword
1340 && !t->operand_types[j].bitfield.dword)
1341 || (i.types[j].bitfield.qword
1342 && !t->operand_types[j].bitfield.qword));
1345 /* Return 1 if there is no conflict in any size on operand J for
1346 instruction template T. */
1349 match_mem_size (const template *t, unsigned int j)
1351 return (match_reg_size (t, j)
1352 && !((i.types[j].bitfield.unspecified
1353 && !t->operand_types[j].bitfield.unspecified)
1354 || (i.types[j].bitfield.fword
1355 && !t->operand_types[j].bitfield.fword)
1356 || (i.types[j].bitfield.tbyte
1357 && !t->operand_types[j].bitfield.tbyte)
1358 || (i.types[j].bitfield.xmmword
1359 && !t->operand_types[j].bitfield.xmmword)));
1362 /* Return 1 if there is no size conflict on any operands for
1363 instruction template T. */
1366 operand_size_match (const template *t)
1371 /* Don't check jump instructions. */
1372 if (t->opcode_modifier.jump
1373 || t->opcode_modifier.jumpbyte
1374 || t->opcode_modifier.jumpdword
1375 || t->opcode_modifier.jumpintersegment)
1378 /* Check memory and accumulator operand size. */
1379 for (j = 0; j < i.operands; j++)
1381 if (t->operand_types[j].bitfield.anysize)
1384 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1390 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1398 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1401 /* Check reverse. */
1402 assert (i.operands == 2);
1405 for (j = 0; j < 2; j++)
1407 if (t->operand_types[j].bitfield.acc
1408 && !match_reg_size (t, j ? 0 : 1))
1414 if (i.types[j].bitfield.mem
1415 && !match_mem_size (t, j ? 0 : 1))
1426 operand_type_match (i386_operand_type overlap,
1427 i386_operand_type given)
1429 i386_operand_type temp = overlap;
1431 temp.bitfield.jumpabsolute = 0;
1432 temp.bitfield.unspecified = 0;
1433 temp.bitfield.byte = 0;
1434 temp.bitfield.word = 0;
1435 temp.bitfield.dword = 0;
1436 temp.bitfield.fword = 0;
1437 temp.bitfield.qword = 0;
1438 temp.bitfield.tbyte = 0;
1439 temp.bitfield.xmmword = 0;
1440 if (operand_type_all_zero (&temp))
1443 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1444 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1447 /* If given types g0 and g1 are registers they must be of the same type
1448 unless the expected operand type register overlap is null.
1449 Note that Acc in a template matches every size of reg. */
1452 operand_type_register_match (i386_operand_type m0,
1453 i386_operand_type g0,
1454 i386_operand_type t0,
1455 i386_operand_type m1,
1456 i386_operand_type g1,
1457 i386_operand_type t1)
1459 if (!operand_type_check (g0, reg))
1462 if (!operand_type_check (g1, reg))
1465 if (g0.bitfield.reg8 == g1.bitfield.reg8
1466 && g0.bitfield.reg16 == g1.bitfield.reg16
1467 && g0.bitfield.reg32 == g1.bitfield.reg32
1468 && g0.bitfield.reg64 == g1.bitfield.reg64)
1471 if (m0.bitfield.acc)
1473 t0.bitfield.reg8 = 1;
1474 t0.bitfield.reg16 = 1;
1475 t0.bitfield.reg32 = 1;
1476 t0.bitfield.reg64 = 1;
1479 if (m1.bitfield.acc)
1481 t1.bitfield.reg8 = 1;
1482 t1.bitfield.reg16 = 1;
1483 t1.bitfield.reg32 = 1;
1484 t1.bitfield.reg64 = 1;
1487 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1488 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1489 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1490 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1493 static INLINE unsigned int
1494 mode_from_disp_size (i386_operand_type t)
1496 if (t.bitfield.disp8)
1498 else if (t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s)
1507 fits_in_signed_byte (offsetT num)
1509 return (num >= -128) && (num <= 127);
1513 fits_in_unsigned_byte (offsetT num)
1515 return (num & 0xff) == num;
1519 fits_in_unsigned_word (offsetT num)
1521 return (num & 0xffff) == num;
1525 fits_in_signed_word (offsetT num)
1527 return (-32768 <= num) && (num <= 32767);
1531 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1536 return (!(((offsetT) -1 << 31) & num)
1537 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1539 } /* fits_in_signed_long() */
1542 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1547 return (num & (((offsetT) 2 << 31) - 1)) == num;
1549 } /* fits_in_unsigned_long() */
1551 static i386_operand_type
1552 smallest_imm_type (offsetT num)
1554 i386_operand_type t;
1556 operand_type_set (&t, 0);
1557 t.bitfield.imm64 = 1;
1559 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1561 /* This code is disabled on the 486 because all the Imm1 forms
1562 in the opcode table are slower on the i486. They're the
1563 versions with the implicitly specified single-position
1564 displacement, which has another syntax if you really want to
1566 t.bitfield.imm1 = 1;
1567 t.bitfield.imm8 = 1;
1568 t.bitfield.imm8s = 1;
1569 t.bitfield.imm16 = 1;
1570 t.bitfield.imm32 = 1;
1571 t.bitfield.imm32s = 1;
1573 else if (fits_in_signed_byte (num))
1575 t.bitfield.imm8 = 1;
1576 t.bitfield.imm8s = 1;
1577 t.bitfield.imm16 = 1;
1578 t.bitfield.imm32 = 1;
1579 t.bitfield.imm32s = 1;
1581 else if (fits_in_unsigned_byte (num))
1583 t.bitfield.imm8 = 1;
1584 t.bitfield.imm16 = 1;
1585 t.bitfield.imm32 = 1;
1586 t.bitfield.imm32s = 1;
1588 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1590 t.bitfield.imm16 = 1;
1591 t.bitfield.imm32 = 1;
1592 t.bitfield.imm32s = 1;
1594 else if (fits_in_signed_long (num))
1596 t.bitfield.imm32 = 1;
1597 t.bitfield.imm32s = 1;
1599 else if (fits_in_unsigned_long (num))
1600 t.bitfield.imm32 = 1;
1606 offset_in_range (offsetT val, int size)
1612 case 1: mask = ((addressT) 1 << 8) - 1; break;
1613 case 2: mask = ((addressT) 1 << 16) - 1; break;
1614 case 4: mask = ((addressT) 2 << 31) - 1; break;
1616 case 8: mask = ((addressT) 2 << 63) - 1; break;
1621 /* If BFD64, sign extend val. */
1622 if (!use_rela_relocations)
1623 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1624 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1626 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1628 char buf1[40], buf2[40];
1630 sprint_value (buf1, val);
1631 sprint_value (buf2, val & mask);
1632 as_warn (_("%s shortened to %s"), buf1, buf2);
1637 /* Returns 0 if attempting to add a prefix where one from the same
1638 class already exists, 1 if non rep/repne added, 2 if rep/repne
1641 add_prefix (unsigned int prefix)
1646 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1647 && flag_code == CODE_64BIT)
1649 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1650 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1651 && (prefix & (REX_R | REX_X | REX_B))))
1662 case CS_PREFIX_OPCODE:
1663 case DS_PREFIX_OPCODE:
1664 case ES_PREFIX_OPCODE:
1665 case FS_PREFIX_OPCODE:
1666 case GS_PREFIX_OPCODE:
1667 case SS_PREFIX_OPCODE:
1671 case REPNE_PREFIX_OPCODE:
1672 case REPE_PREFIX_OPCODE:
1675 case LOCK_PREFIX_OPCODE:
1683 case ADDR_PREFIX_OPCODE:
1687 case DATA_PREFIX_OPCODE:
1691 if (i.prefix[q] != 0)
1699 i.prefix[q] |= prefix;
1702 as_bad (_("same type of prefix used twice"));
1708 set_code_flag (int value)
1711 if (flag_code == CODE_64BIT)
1713 cpu_arch_flags.bitfield.cpu64 = 1;
1714 cpu_arch_flags.bitfield.cpuno64 = 0;
1718 cpu_arch_flags.bitfield.cpu64 = 0;
1719 cpu_arch_flags.bitfield.cpuno64 = 1;
1721 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1723 as_bad (_("64bit mode not supported on this CPU."));
1725 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1727 as_bad (_("32bit mode not supported on this CPU."));
1729 stackop_size = '\0';
1733 set_16bit_gcc_code_flag (int new_code_flag)
1735 flag_code = new_code_flag;
1736 if (flag_code != CODE_16BIT)
1738 cpu_arch_flags.bitfield.cpu64 = 0;
1739 cpu_arch_flags.bitfield.cpuno64 = 1;
1740 stackop_size = LONG_MNEM_SUFFIX;
1744 set_intel_syntax (int syntax_flag)
1746 /* Find out if register prefixing is specified. */
1747 int ask_naked_reg = 0;
1750 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1752 char *string = input_line_pointer;
1753 int e = get_symbol_end ();
1755 if (strcmp (string, "prefix") == 0)
1757 else if (strcmp (string, "noprefix") == 0)
1760 as_bad (_("bad argument to syntax directive."));
1761 *input_line_pointer = e;
1763 demand_empty_rest_of_line ();
1765 intel_syntax = syntax_flag;
1767 if (ask_naked_reg == 0)
1768 allow_naked_reg = (intel_syntax
1769 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1771 allow_naked_reg = (ask_naked_reg < 0);
1773 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1774 identifier_chars['$'] = intel_syntax ? '$' : 0;
1775 register_prefix = allow_naked_reg ? "" : "%";
1779 set_intel_mnemonic (int mnemonic_flag)
1781 intel_mnemonic = mnemonic_flag;
1785 set_allow_index_reg (int flag)
1787 allow_index_reg = flag;
1791 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1797 char *string = input_line_pointer;
1798 int e = get_symbol_end ();
1800 i386_cpu_flags flags;
1802 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1804 if (strcmp (string, cpu_arch[i].name) == 0)
1808 cpu_arch_name = cpu_arch[i].name;
1809 cpu_sub_arch_name = NULL;
1810 cpu_arch_flags = cpu_arch[i].flags;
1811 if (flag_code == CODE_64BIT)
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1821 cpu_arch_isa = cpu_arch[i].type;
1822 cpu_arch_isa_flags = cpu_arch[i].flags;
1823 if (!cpu_arch_tune_set)
1825 cpu_arch_tune = cpu_arch_isa;
1826 cpu_arch_tune_flags = cpu_arch_isa_flags;
1831 flags = cpu_flags_or (cpu_arch_flags,
1833 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1835 if (cpu_sub_arch_name)
1837 char *name = cpu_sub_arch_name;
1838 cpu_sub_arch_name = concat (name,
1840 (const char *) NULL);
1844 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1845 cpu_arch_flags = flags;
1847 *input_line_pointer = e;
1848 demand_empty_rest_of_line ();
1852 if (i >= ARRAY_SIZE (cpu_arch))
1853 as_bad (_("no such architecture: `%s'"), string);
1855 *input_line_pointer = e;
1858 as_bad (_("missing cpu architecture"));
1860 no_cond_jump_promotion = 0;
1861 if (*input_line_pointer == ','
1862 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1864 char *string = ++input_line_pointer;
1865 int e = get_symbol_end ();
1867 if (strcmp (string, "nojumps") == 0)
1868 no_cond_jump_promotion = 1;
1869 else if (strcmp (string, "jumps") == 0)
1872 as_bad (_("no such architecture modifier: `%s'"), string);
1874 *input_line_pointer = e;
1877 demand_empty_rest_of_line ();
1883 if (!strcmp (default_arch, "x86_64"))
1884 return bfd_mach_x86_64;
1885 else if (!strcmp (default_arch, "i386"))
1886 return bfd_mach_i386_i386;
1888 as_fatal (_("Unknown architecture"));
1894 const char *hash_err;
1896 /* Initialize op_hash hash table. */
1897 op_hash = hash_new ();
1900 const template *optab;
1901 templates *core_optab;
1903 /* Setup for loop. */
1905 core_optab = (templates *) xmalloc (sizeof (templates));
1906 core_optab->start = optab;
1911 if (optab->name == NULL
1912 || strcmp (optab->name, (optab - 1)->name) != 0)
1914 /* different name --> ship out current template list;
1915 add to hash table; & begin anew. */
1916 core_optab->end = optab;
1917 hash_err = hash_insert (op_hash,
1922 as_fatal (_("Internal Error: Can't hash %s: %s"),
1926 if (optab->name == NULL)
1928 core_optab = (templates *) xmalloc (sizeof (templates));
1929 core_optab->start = optab;
1934 /* Initialize reg_hash hash table. */
1935 reg_hash = hash_new ();
1937 const reg_entry *regtab;
1938 unsigned int regtab_size = i386_regtab_size;
1940 for (regtab = i386_regtab; regtab_size--; regtab++)
1942 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1944 as_fatal (_("Internal Error: Can't hash %s: %s"),
1950 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1955 for (c = 0; c < 256; c++)
1960 mnemonic_chars[c] = c;
1961 register_chars[c] = c;
1962 operand_chars[c] = c;
1964 else if (ISLOWER (c))
1966 mnemonic_chars[c] = c;
1967 register_chars[c] = c;
1968 operand_chars[c] = c;
1970 else if (ISUPPER (c))
1972 mnemonic_chars[c] = TOLOWER (c);
1973 register_chars[c] = mnemonic_chars[c];
1974 operand_chars[c] = c;
1977 if (ISALPHA (c) || ISDIGIT (c))
1978 identifier_chars[c] = c;
1981 identifier_chars[c] = c;
1982 operand_chars[c] = c;
1987 identifier_chars['@'] = '@';
1990 identifier_chars['?'] = '?';
1991 operand_chars['?'] = '?';
1993 digit_chars['-'] = '-';
1994 mnemonic_chars['-'] = '-';
1995 mnemonic_chars['.'] = '.';
1996 identifier_chars['_'] = '_';
1997 identifier_chars['.'] = '.';
1999 for (p = operand_special_chars; *p != '\0'; p++)
2000 operand_chars[(unsigned char) *p] = *p;
2003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2006 record_alignment (text_section, 2);
2007 record_alignment (data_section, 2);
2008 record_alignment (bss_section, 2);
2012 if (flag_code == CODE_64BIT)
2014 x86_dwarf2_return_column = 16;
2015 x86_cie_data_alignment = -8;
2019 x86_dwarf2_return_column = 8;
2020 x86_cie_data_alignment = -4;
2025 i386_print_statistics (FILE *file)
2027 hash_print_statistics (file, "i386 opcode", op_hash);
2028 hash_print_statistics (file, "i386 register", reg_hash);
2033 /* Debugging routines for md_assemble. */
2034 static void pte (template *);
2035 static void pt (i386_operand_type);
2036 static void pe (expressionS *);
2037 static void ps (symbolS *);
2040 pi (char *line, i386_insn *x)
2044 fprintf (stdout, "%s: template ", line);
2046 fprintf (stdout, " address: base %s index %s scale %x\n",
2047 x->base_reg ? x->base_reg->reg_name : "none",
2048 x->index_reg ? x->index_reg->reg_name : "none",
2049 x->log2_scale_factor);
2050 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2051 x->rm.mode, x->rm.reg, x->rm.regmem);
2052 fprintf (stdout, " sib: base %x index %x scale %x\n",
2053 x->sib.base, x->sib.index, x->sib.scale);
2054 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2055 (x->rex & REX_W) != 0,
2056 (x->rex & REX_R) != 0,
2057 (x->rex & REX_X) != 0,
2058 (x->rex & REX_B) != 0);
2059 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2060 x->drex.reg, x->drex.rex);
2061 for (i = 0; i < x->operands; i++)
2063 fprintf (stdout, " #%d: ", i + 1);
2065 fprintf (stdout, "\n");
2066 if (x->types[i].bitfield.reg8
2067 || x->types[i].bitfield.reg16
2068 || x->types[i].bitfield.reg32
2069 || x->types[i].bitfield.reg64
2070 || x->types[i].bitfield.regmmx
2071 || x->types[i].bitfield.regxmm
2072 || x->types[i].bitfield.sreg2
2073 || x->types[i].bitfield.sreg3
2074 || x->types[i].bitfield.control
2075 || x->types[i].bitfield.debug
2076 || x->types[i].bitfield.test)
2077 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2078 if (operand_type_check (x->types[i], imm))
2080 if (operand_type_check (x->types[i], disp))
2081 pe (x->op[i].disps);
2089 fprintf (stdout, " %d operands ", t->operands);
2090 fprintf (stdout, "opcode %x ", t->base_opcode);
2091 if (t->extension_opcode != None)
2092 fprintf (stdout, "ext %x ", t->extension_opcode);
2093 if (t->opcode_modifier.d)
2094 fprintf (stdout, "D");
2095 if (t->opcode_modifier.w)
2096 fprintf (stdout, "W");
2097 fprintf (stdout, "\n");
2098 for (i = 0; i < t->operands; i++)
2100 fprintf (stdout, " #%d type ", i + 1);
2101 pt (t->operand_types[i]);
2102 fprintf (stdout, "\n");
2109 fprintf (stdout, " operation %d\n", e->X_op);
2110 fprintf (stdout, " add_number %ld (%lx)\n",
2111 (long) e->X_add_number, (long) e->X_add_number);
2112 if (e->X_add_symbol)
2114 fprintf (stdout, " add_symbol ");
2115 ps (e->X_add_symbol);
2116 fprintf (stdout, "\n");
2120 fprintf (stdout, " op_symbol ");
2121 ps (e->X_op_symbol);
2122 fprintf (stdout, "\n");
2129 fprintf (stdout, "%s type %s%s",
2131 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2132 segment_name (S_GET_SEGMENT (s)));
2135 static struct type_name
2137 i386_operand_type mask;
2140 const type_names[] =
2142 { OPERAND_TYPE_REG8, "r8" },
2143 { OPERAND_TYPE_REG16, "r16" },
2144 { OPERAND_TYPE_REG32, "r32" },
2145 { OPERAND_TYPE_REG64, "r64" },
2146 { OPERAND_TYPE_IMM8, "i8" },
2147 { OPERAND_TYPE_IMM8, "i8s" },
2148 { OPERAND_TYPE_IMM16, "i16" },
2149 { OPERAND_TYPE_IMM32, "i32" },
2150 { OPERAND_TYPE_IMM32S, "i32s" },
2151 { OPERAND_TYPE_IMM64, "i64" },
2152 { OPERAND_TYPE_IMM1, "i1" },
2153 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2154 { OPERAND_TYPE_DISP8, "d8" },
2155 { OPERAND_TYPE_DISP16, "d16" },
2156 { OPERAND_TYPE_DISP32, "d32" },
2157 { OPERAND_TYPE_DISP32S, "d32s" },
2158 { OPERAND_TYPE_DISP64, "d64" },
2159 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2160 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2161 { OPERAND_TYPE_CONTROL, "control reg" },
2162 { OPERAND_TYPE_TEST, "test reg" },
2163 { OPERAND_TYPE_DEBUG, "debug reg" },
2164 { OPERAND_TYPE_FLOATREG, "FReg" },
2165 { OPERAND_TYPE_FLOATACC, "FAcc" },
2166 { OPERAND_TYPE_SREG2, "SReg2" },
2167 { OPERAND_TYPE_SREG3, "SReg3" },
2168 { OPERAND_TYPE_ACC, "Acc" },
2169 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2170 { OPERAND_TYPE_REGMMX, "rMMX" },
2171 { OPERAND_TYPE_REGXMM, "rXMM" },
2172 { OPERAND_TYPE_ESSEG, "es" },
2176 pt (i386_operand_type t)
2179 i386_operand_type a;
2181 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2183 a = operand_type_and (t, type_names[j].mask);
2184 if (!UINTS_ALL_ZERO (a))
2185 fprintf (stdout, "%s, ", type_names[j].name);
2190 #endif /* DEBUG386 */
2192 static bfd_reloc_code_real_type
2193 reloc (unsigned int size,
2196 bfd_reloc_code_real_type other)
2198 if (other != NO_RELOC)
2200 reloc_howto_type *reloc;
2205 case BFD_RELOC_X86_64_GOT32:
2206 return BFD_RELOC_X86_64_GOT64;
2208 case BFD_RELOC_X86_64_PLTOFF64:
2209 return BFD_RELOC_X86_64_PLTOFF64;
2211 case BFD_RELOC_X86_64_GOTPC32:
2212 other = BFD_RELOC_X86_64_GOTPC64;
2214 case BFD_RELOC_X86_64_GOTPCREL:
2215 other = BFD_RELOC_X86_64_GOTPCREL64;
2217 case BFD_RELOC_X86_64_TPOFF32:
2218 other = BFD_RELOC_X86_64_TPOFF64;
2220 case BFD_RELOC_X86_64_DTPOFF32:
2221 other = BFD_RELOC_X86_64_DTPOFF64;
2227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2228 if (size == 4 && flag_code != CODE_64BIT)
2231 reloc = bfd_reloc_type_lookup (stdoutput, other);
2233 as_bad (_("unknown relocation (%u)"), other);
2234 else if (size != bfd_get_reloc_size (reloc))
2235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2236 bfd_get_reloc_size (reloc),
2238 else if (pcrel && !reloc->pc_relative)
2239 as_bad (_("non-pc-relative relocation for pc-relative field"));
2240 else if ((reloc->complain_on_overflow == complain_overflow_signed
2242 || (reloc->complain_on_overflow == complain_overflow_unsigned
2244 as_bad (_("relocated field and relocation type differ in signedness"));
2253 as_bad (_("there are no unsigned pc-relative relocations"));
2256 case 1: return BFD_RELOC_8_PCREL;
2257 case 2: return BFD_RELOC_16_PCREL;
2258 case 4: return BFD_RELOC_32_PCREL;
2259 case 8: return BFD_RELOC_64_PCREL;
2261 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2268 case 4: return BFD_RELOC_X86_64_32S;
2273 case 1: return BFD_RELOC_8;
2274 case 2: return BFD_RELOC_16;
2275 case 4: return BFD_RELOC_32;
2276 case 8: return BFD_RELOC_64;
2278 as_bad (_("cannot do %s %u byte relocation"),
2279 sign > 0 ? "signed" : "unsigned", size);
2283 return BFD_RELOC_NONE;
2286 /* Here we decide which fixups can be adjusted to make them relative to
2287 the beginning of the section instead of the symbol. Basically we need
2288 to make sure that the dynamic relocations are done correctly, so in
2289 some cases we force the original symbol to be used. */
2292 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2298 /* Don't adjust pc-relative references to merge sections in 64-bit
2300 if (use_rela_relocations
2301 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2305 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2306 and changed later by validate_fix. */
2307 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2308 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2311 /* adjust_reloc_syms doesn't know about the GOT. */
2312 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2313 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2314 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2324 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2325 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2328 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2338 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2339 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2346 intel_float_operand (const char *mnemonic)
2348 /* Note that the value returned is meaningful only for opcodes with (memory)
2349 operands, hence the code here is free to improperly handle opcodes that
2350 have no operands (for better performance and smaller code). */
2352 if (mnemonic[0] != 'f')
2353 return 0; /* non-math */
2355 switch (mnemonic[1])
2357 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2358 the fs segment override prefix not currently handled because no
2359 call path can make opcodes without operands get here */
2361 return 2 /* integer op */;
2363 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2364 return 3; /* fldcw/fldenv */
2367 if (mnemonic[2] != 'o' /* fnop */)
2368 return 3; /* non-waiting control op */
2371 if (mnemonic[2] == 's')
2372 return 3; /* frstor/frstpm */
2375 if (mnemonic[2] == 'a')
2376 return 3; /* fsave */
2377 if (mnemonic[2] == 't')
2379 switch (mnemonic[3])
2381 case 'c': /* fstcw */
2382 case 'd': /* fstdw */
2383 case 'e': /* fstenv */
2384 case 's': /* fsts[gw] */
2390 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2391 return 0; /* fxsave/fxrstor are not really math ops */
2399 process_immext (void)
2403 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2405 /* SSE3 Instructions have the fixed operands with an opcode
2406 suffix which is coded in the same place as an 8-bit immediate
2407 field would be. Here we check those operands and remove them
2411 for (x = 0; x < i.operands; x++)
2412 if (i.op[x].regs->reg_num != x)
2413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2415 i.op[x].regs->reg_name,
2418 i.tm.name); i.operands = 0;
2421 /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
2422 which is coded in the same place as an 8-bit immediate field
2423 would be. Here we fake an 8-bit immediate operand from the
2424 opcode suffix stored in tm.extension_opcode.
2426 SSE5 also uses this encoding, for some of its 3 argument
2429 assert (i.imm_operands == 0
2431 || (i.tm.cpu_flags.bitfield.cpusse5
2432 && i.operands <= 3)));
2434 exp = &im_expressions[i.imm_operands++];
2435 i.op[i.operands].imms = exp;
2436 i.types[i.operands] = imm8;
2438 exp->X_op = O_constant;
2439 exp->X_add_number = i.tm.extension_opcode;
2440 i.tm.extension_opcode = None;
2443 /* This is the guts of the machine-dependent assembler. LINE points to a
2444 machine dependent instruction. This function is supposed to emit
2445 the frags/bytes it assembles to. */
2448 md_assemble (char *line)
2451 char mnemonic[MAX_MNEM_SIZE];
2453 /* Initialize globals. */
2454 memset (&i, '\0', sizeof (i));
2455 for (j = 0; j < MAX_OPERANDS; j++)
2456 i.reloc[j] = NO_RELOC;
2457 memset (disp_expressions, '\0', sizeof (disp_expressions));
2458 memset (im_expressions, '\0', sizeof (im_expressions));
2459 save_stack_p = save_stack;
2461 /* First parse an instruction mnemonic & call i386_operand for the operands.
2462 We assume that the scrubber has arranged it so that line[0] is the valid
2463 start of a (possibly prefixed) mnemonic. */
2465 line = parse_insn (line, mnemonic);
2469 line = parse_operands (line, mnemonic);
2473 /* Now we've parsed the mnemonic into a set of templates, and have the
2474 operands at hand. */
2476 /* All intel opcodes have reversed operands except for "bound" and
2477 "enter". We also don't reverse intersegment "jmp" and "call"
2478 instructions with 2 immediate operands so that the immediate segment
2479 precedes the offset, as it does when in AT&T mode. */
2482 && (strcmp (mnemonic, "bound") != 0)
2483 && (strcmp (mnemonic, "invlpga") != 0)
2484 && !(operand_type_check (i.types[0], imm)
2485 && operand_type_check (i.types[1], imm)))
2488 /* The order of the immediates should be reversed
2489 for 2 immediates extrq and insertq instructions */
2490 if (i.imm_operands == 2
2491 && (strcmp (mnemonic, "extrq") == 0
2492 || strcmp (mnemonic, "insertq") == 0))
2493 swap_2_operands (0, 1);
2498 /* Don't optimize displacement for movabs since it only takes 64bit
2501 && (flag_code != CODE_64BIT
2502 || strcmp (mnemonic, "movabs") != 0))
2505 /* Next, we find a template that matches the given insn,
2506 making sure the overlap of the given operands types is consistent
2507 with the template operand types. */
2509 if (!match_template ())
2512 /* Zap movzx and movsx suffix. The suffix has been set from
2513 "word ptr" or "byte ptr" on the source operand in Intel syntax
2514 or extracted from mnemonic in AT&T syntax. But we'll use
2515 the destination register to choose the suffix for encoding. */
2516 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2518 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2519 there is no suffix, the default will be byte extension. */
2520 if (i.reg_operands != 2
2523 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2528 if (i.tm.opcode_modifier.fwait)
2529 if (!add_prefix (FWAIT_OPCODE))
2532 /* Check string instruction segment overrides. */
2533 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2535 if (!check_string ())
2539 if (!process_suffix ())
2542 /* Make still unresolved immediate matches conform to size of immediate
2543 given in i.suffix. */
2544 if (!finalize_imm ())
2547 if (i.types[0].bitfield.imm1)
2548 i.imm_operands = 0; /* kludge for shift insns. */
2550 for (j = 0; j < 3; j++)
2551 if (i.types[j].bitfield.inoutportreg
2552 || i.types[j].bitfield.shiftcount
2553 || i.types[j].bitfield.acc
2554 || i.types[j].bitfield.floatacc)
2557 if (i.tm.opcode_modifier.immext)
2560 /* For insns with operands there are more diddles to do to the opcode. */
2563 if (!process_operands ())
2566 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2568 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2569 as_warn (_("translating to `%sp'"), i.tm.name);
2572 /* Handle conversion of 'int $3' --> special int3 insn. */
2573 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2575 i.tm.base_opcode = INT3_OPCODE;
2579 if ((i.tm.opcode_modifier.jump
2580 || i.tm.opcode_modifier.jumpbyte
2581 || i.tm.opcode_modifier.jumpdword)
2582 && i.op[0].disps->X_op == O_constant)
2584 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2585 the absolute address given by the constant. Since ix86 jumps and
2586 calls are pc relative, we need to generate a reloc. */
2587 i.op[0].disps->X_add_symbol = &abs_symbol;
2588 i.op[0].disps->X_op = O_symbol;
2591 if (i.tm.opcode_modifier.rex64)
2594 /* For 8 bit registers we need an empty rex prefix. Also if the
2595 instruction already has a prefix, we need to convert old
2596 registers to new ones. */
2598 if ((i.types[0].bitfield.reg8
2599 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2600 || (i.types[1].bitfield.reg8
2601 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2602 || ((i.types[0].bitfield.reg8
2603 || i.types[1].bitfield.reg8)
2608 i.rex |= REX_OPCODE;
2609 for (x = 0; x < 2; x++)
2611 /* Look for 8 bit operand that uses old registers. */
2612 if (i.types[x].bitfield.reg8
2613 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2615 /* In case it is "hi" register, give up. */
2616 if (i.op[x].regs->reg_num > 3)
2617 as_bad (_("can't encode register '%s%s' in an "
2618 "instruction requiring REX prefix."),
2619 register_prefix, i.op[x].regs->reg_name);
2621 /* Otherwise it is equivalent to the extended register.
2622 Since the encoding doesn't change this is merely
2623 cosmetic cleanup for debug output. */
2625 i.op[x].regs = i.op[x].regs + 8;
2630 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2632 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2637 else if (i.rex != 0)
2638 add_prefix (REX_OPCODE | i.rex);
2640 /* We are ready to output the insn. */
2645 parse_insn (char *line, char *mnemonic)
2648 char *token_start = l;
2653 /* Non-zero if we found a prefix only acceptable with string insns. */
2654 const char *expecting_string_instruction = NULL;
2659 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2662 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2664 as_bad (_("no such instruction: `%s'"), token_start);
2669 if (!is_space_char (*l)
2670 && *l != END_OF_INSN
2672 || (*l != PREFIX_SEPARATOR
2675 as_bad (_("invalid character %s in mnemonic"),
2676 output_invalid (*l));
2679 if (token_start == l)
2681 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2682 as_bad (_("expecting prefix; got nothing"));
2684 as_bad (_("expecting mnemonic; got nothing"));
2688 /* Look up instruction (or prefix) via hash table. */
2689 current_templates = hash_find (op_hash, mnemonic);
2691 if (*l != END_OF_INSN
2692 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2693 && current_templates
2694 && current_templates->start->opcode_modifier.isprefix)
2696 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2698 as_bad ((flag_code != CODE_64BIT
2699 ? _("`%s' is only supported in 64-bit mode")
2700 : _("`%s' is not supported in 64-bit mode")),
2701 current_templates->start->name);
2704 /* If we are in 16-bit mode, do not allow addr16 or data16.
2705 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2706 if ((current_templates->start->opcode_modifier.size16
2707 || current_templates->start->opcode_modifier.size32)
2708 && flag_code != CODE_64BIT
2709 && (current_templates->start->opcode_modifier.size32
2710 ^ (flag_code == CODE_16BIT)))
2712 as_bad (_("redundant %s prefix"),
2713 current_templates->start->name);
2716 /* Add prefix, checking for repeated prefixes. */
2717 switch (add_prefix (current_templates->start->base_opcode))
2722 expecting_string_instruction = current_templates->start->name;
2725 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2732 if (!current_templates)
2734 /* See if we can get a match by trimming off a suffix. */
2737 case WORD_MNEM_SUFFIX:
2738 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2739 i.suffix = SHORT_MNEM_SUFFIX;
2741 case BYTE_MNEM_SUFFIX:
2742 case QWORD_MNEM_SUFFIX:
2743 i.suffix = mnem_p[-1];
2745 current_templates = hash_find (op_hash, mnemonic);
2747 case SHORT_MNEM_SUFFIX:
2748 case LONG_MNEM_SUFFIX:
2751 i.suffix = mnem_p[-1];
2753 current_templates = hash_find (op_hash, mnemonic);
2761 if (intel_float_operand (mnemonic) == 1)
2762 i.suffix = SHORT_MNEM_SUFFIX;
2764 i.suffix = LONG_MNEM_SUFFIX;
2766 current_templates = hash_find (op_hash, mnemonic);
2770 if (!current_templates)
2772 as_bad (_("no such instruction: `%s'"), token_start);
2777 if (current_templates->start->opcode_modifier.jump
2778 || current_templates->start->opcode_modifier.jumpbyte)
2780 /* Check for a branch hint. We allow ",pt" and ",pn" for
2781 predict taken and predict not taken respectively.
2782 I'm not sure that branch hints actually do anything on loop
2783 and jcxz insns (JumpByte) for current Pentium4 chips. They
2784 may work in the future and it doesn't hurt to accept them
2786 if (l[0] == ',' && l[1] == 'p')
2790 if (!add_prefix (DS_PREFIX_OPCODE))
2794 else if (l[2] == 'n')
2796 if (!add_prefix (CS_PREFIX_OPCODE))
2802 /* Any other comma loses. */
2805 as_bad (_("invalid character %s in mnemonic"),
2806 output_invalid (*l));
2810 /* Check if instruction is supported on specified architecture. */
2812 for (t = current_templates->start; t < current_templates->end; ++t)
2814 supported |= cpu_flags_match (t->cpu_flags);
2819 if (!(supported & 2))
2821 as_bad (flag_code == CODE_64BIT
2822 ? _("`%s' is not supported in 64-bit mode")
2823 : _("`%s' is only supported in 64-bit mode"),
2824 current_templates->start->name);
2827 if (!(supported & 1))
2829 as_bad (_("`%s' is not supported on `%s%s'"),
2830 current_templates->start->name, cpu_arch_name,
2831 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2836 if (!cpu_arch_flags.bitfield.cpui386
2837 && (flag_code != CODE_16BIT))
2839 as_warn (_("use .code16 to ensure correct addressing mode"));
2842 /* Check for rep/repne without a string instruction. */
2843 if (expecting_string_instruction)
2845 static templates override;
2847 for (t = current_templates->start; t < current_templates->end; ++t)
2848 if (t->opcode_modifier.isstring)
2850 if (t >= current_templates->end)
2852 as_bad (_("expecting string instruction after `%s'"),
2853 expecting_string_instruction);
2856 for (override.start = t; t < current_templates->end; ++t)
2857 if (!t->opcode_modifier.isstring)
2860 current_templates = &override;
2867 parse_operands (char *l, const char *mnemonic)
2871 /* 1 if operand is pending after ','. */
2872 unsigned int expecting_operand = 0;
2874 /* Non-zero if operand parens not balanced. */
2875 unsigned int paren_not_balanced;
2877 while (*l != END_OF_INSN)
2879 /* Skip optional white space before operand. */
2880 if (is_space_char (*l))
2882 if (!is_operand_char (*l) && *l != END_OF_INSN)
2884 as_bad (_("invalid character %s before operand %d"),
2885 output_invalid (*l),
2889 token_start = l; /* after white space */
2890 paren_not_balanced = 0;
2891 while (paren_not_balanced || *l != ',')
2893 if (*l == END_OF_INSN)
2895 if (paren_not_balanced)
2898 as_bad (_("unbalanced parenthesis in operand %d."),
2901 as_bad (_("unbalanced brackets in operand %d."),
2906 break; /* we are done */
2908 else if (!is_operand_char (*l) && !is_space_char (*l))
2910 as_bad (_("invalid character %s in operand %d"),
2911 output_invalid (*l),
2918 ++paren_not_balanced;
2920 --paren_not_balanced;
2925 ++paren_not_balanced;
2927 --paren_not_balanced;
2931 if (l != token_start)
2932 { /* Yes, we've read in another operand. */
2933 unsigned int operand_ok;
2934 this_operand = i.operands++;
2935 i.types[this_operand].bitfield.unspecified = 1;
2936 if (i.operands > MAX_OPERANDS)
2938 as_bad (_("spurious operands; (%d operands/instruction max)"),
2942 /* Now parse operand adding info to 'i' as we go along. */
2943 END_STRING_AND_SAVE (l);
2947 i386_intel_operand (token_start,
2948 intel_float_operand (mnemonic));
2950 operand_ok = i386_att_operand (token_start);
2952 RESTORE_END_STRING (l);
2958 if (expecting_operand)
2960 expecting_operand_after_comma:
2961 as_bad (_("expecting operand after ','; got nothing"));
2966 as_bad (_("expecting operand before ','; got nothing"));
2971 /* Now *l must be either ',' or END_OF_INSN. */
2974 if (*++l == END_OF_INSN)
2976 /* Just skip it, if it's \n complain. */
2977 goto expecting_operand_after_comma;
2979 expecting_operand = 1;
2986 swap_2_operands (int xchg1, int xchg2)
2988 union i386_op temp_op;
2989 i386_operand_type temp_type;
2990 enum bfd_reloc_code_real temp_reloc;
2992 temp_type = i.types[xchg2];
2993 i.types[xchg2] = i.types[xchg1];
2994 i.types[xchg1] = temp_type;
2995 temp_op = i.op[xchg2];
2996 i.op[xchg2] = i.op[xchg1];
2997 i.op[xchg1] = temp_op;
2998 temp_reloc = i.reloc[xchg2];
2999 i.reloc[xchg2] = i.reloc[xchg1];
3000 i.reloc[xchg1] = temp_reloc;
3004 swap_operands (void)
3009 swap_2_operands (1, i.operands - 2);
3012 swap_2_operands (0, i.operands - 1);
3018 if (i.mem_operands == 2)
3020 const seg_entry *temp_seg;
3021 temp_seg = i.seg[0];
3022 i.seg[0] = i.seg[1];
3023 i.seg[1] = temp_seg;
3027 /* Try to ensure constant immediates are represented in the smallest
3032 char guess_suffix = 0;
3036 guess_suffix = i.suffix;
3037 else if (i.reg_operands)
3039 /* Figure out a suffix from the last register operand specified.
3040 We can't do this properly yet, ie. excluding InOutPortReg,
3041 but the following works for instructions with immediates.
3042 In any case, we can't set i.suffix yet. */
3043 for (op = i.operands; --op >= 0;)
3044 if (i.types[op].bitfield.reg8)
3046 guess_suffix = BYTE_MNEM_SUFFIX;
3049 else if (i.types[op].bitfield.reg16)
3051 guess_suffix = WORD_MNEM_SUFFIX;
3054 else if (i.types[op].bitfield.reg32)
3056 guess_suffix = LONG_MNEM_SUFFIX;
3059 else if (i.types[op].bitfield.reg64)
3061 guess_suffix = QWORD_MNEM_SUFFIX;
3065 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3066 guess_suffix = WORD_MNEM_SUFFIX;
3068 for (op = i.operands; --op >= 0;)
3069 if (operand_type_check (i.types[op], imm))
3071 switch (i.op[op].imms->X_op)
3074 /* If a suffix is given, this operand may be shortened. */
3075 switch (guess_suffix)
3077 case LONG_MNEM_SUFFIX:
3078 i.types[op].bitfield.imm32 = 1;
3079 i.types[op].bitfield.imm64 = 1;
3081 case WORD_MNEM_SUFFIX:
3082 i.types[op].bitfield.imm16 = 1;
3083 i.types[op].bitfield.imm32 = 1;
3084 i.types[op].bitfield.imm32s = 1;
3085 i.types[op].bitfield.imm64 = 1;
3087 case BYTE_MNEM_SUFFIX:
3088 i.types[op].bitfield.imm8 = 1;
3089 i.types[op].bitfield.imm8s = 1;
3090 i.types[op].bitfield.imm16 = 1;
3091 i.types[op].bitfield.imm32 = 1;
3092 i.types[op].bitfield.imm32s = 1;
3093 i.types[op].bitfield.imm64 = 1;
3097 /* If this operand is at most 16 bits, convert it
3098 to a signed 16 bit number before trying to see
3099 whether it will fit in an even smaller size.
3100 This allows a 16-bit operand such as $0xffe0 to
3101 be recognised as within Imm8S range. */
3102 if ((i.types[op].bitfield.imm16)
3103 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3105 i.op[op].imms->X_add_number =
3106 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3108 if ((i.types[op].bitfield.imm32)
3109 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3112 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3113 ^ ((offsetT) 1 << 31))
3114 - ((offsetT) 1 << 31));
3117 = operand_type_or (i.types[op],
3118 smallest_imm_type (i.op[op].imms->X_add_number));
3120 /* We must avoid matching of Imm32 templates when 64bit
3121 only immediate is available. */
3122 if (guess_suffix == QWORD_MNEM_SUFFIX)
3123 i.types[op].bitfield.imm32 = 0;
3130 /* Symbols and expressions. */
3132 /* Convert symbolic operand to proper sizes for matching, but don't
3133 prevent matching a set of insns that only supports sizes other
3134 than those matching the insn suffix. */
3136 i386_operand_type mask, allowed;
3139 operand_type_set (&mask, 0);
3140 operand_type_set (&allowed, 0);
3142 for (t = current_templates->start;
3143 t < current_templates->end;
3145 allowed = operand_type_or (allowed,
3146 t->operand_types[op]);
3147 switch (guess_suffix)
3149 case QWORD_MNEM_SUFFIX:
3150 mask.bitfield.imm64 = 1;
3151 mask.bitfield.imm32s = 1;
3153 case LONG_MNEM_SUFFIX:
3154 mask.bitfield.imm32 = 1;
3156 case WORD_MNEM_SUFFIX:
3157 mask.bitfield.imm16 = 1;
3159 case BYTE_MNEM_SUFFIX:
3160 mask.bitfield.imm8 = 1;
3165 allowed = operand_type_and (mask, allowed);
3166 if (!operand_type_all_zero (&allowed))
3167 i.types[op] = operand_type_and (i.types[op], mask);
3174 /* Try to use the smallest displacement type too. */
3176 optimize_disp (void)
3180 for (op = i.operands; --op >= 0;)
3181 if (operand_type_check (i.types[op], disp))
3183 if (i.op[op].disps->X_op == O_constant)
3185 offsetT disp = i.op[op].disps->X_add_number;
3187 if (i.types[op].bitfield.disp16
3188 && (disp & ~(offsetT) 0xffff) == 0)
3190 /* If this operand is at most 16 bits, convert
3191 to a signed 16 bit number and don't use 64bit
3193 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3194 i.types[op].bitfield.disp64 = 0;
3196 if (i.types[op].bitfield.disp32
3197 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3199 /* If this operand is at most 32 bits, convert
3200 to a signed 32 bit number and don't use 64bit
3202 disp &= (((offsetT) 2 << 31) - 1);
3203 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3204 i.types[op].bitfield.disp64 = 0;
3206 if (!disp && i.types[op].bitfield.baseindex)
3208 i.types[op].bitfield.disp8 = 0;
3209 i.types[op].bitfield.disp16 = 0;
3210 i.types[op].bitfield.disp32 = 0;
3211 i.types[op].bitfield.disp32s = 0;
3212 i.types[op].bitfield.disp64 = 0;
3216 else if (flag_code == CODE_64BIT)
3218 if (fits_in_signed_long (disp))
3220 i.types[op].bitfield.disp64 = 0;
3221 i.types[op].bitfield.disp32s = 1;
3223 if (fits_in_unsigned_long (disp))
3224 i.types[op].bitfield.disp32 = 1;
3226 if ((i.types[op].bitfield.disp32
3227 || i.types[op].bitfield.disp32s
3228 || i.types[op].bitfield.disp16)
3229 && fits_in_signed_byte (disp))
3230 i.types[op].bitfield.disp8 = 1;
3232 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3233 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3235 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3236 i.op[op].disps, 0, i.reloc[op]);
3237 i.types[op].bitfield.disp8 = 0;
3238 i.types[op].bitfield.disp16 = 0;
3239 i.types[op].bitfield.disp32 = 0;
3240 i.types[op].bitfield.disp32s = 0;
3241 i.types[op].bitfield.disp64 = 0;
3244 /* We only support 64bit displacement on constants. */
3245 i.types[op].bitfield.disp64 = 0;
3250 match_template (void)
3252 /* Points to template once we've found it. */
3254 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3255 unsigned int found_reverse_match;
3256 i386_opcode_modifier suffix_check;
3257 i386_operand_type operand_types [MAX_OPERANDS];
3258 int addr_prefix_disp;
3260 unsigned int found_cpu_match;
3261 unsigned int check_register;
3263 #if MAX_OPERANDS != 4
3264 # error "MAX_OPERANDS must be 4."
3267 found_reverse_match = 0;
3268 addr_prefix_disp = -1;
3270 memset (&suffix_check, 0, sizeof (suffix_check));
3271 if (i.suffix == BYTE_MNEM_SUFFIX)
3272 suffix_check.no_bsuf = 1;
3273 else if (i.suffix == WORD_MNEM_SUFFIX)
3274 suffix_check.no_wsuf = 1;
3275 else if (i.suffix == SHORT_MNEM_SUFFIX)
3276 suffix_check.no_ssuf = 1;
3277 else if (i.suffix == LONG_MNEM_SUFFIX)
3278 suffix_check.no_lsuf = 1;
3279 else if (i.suffix == QWORD_MNEM_SUFFIX)
3280 suffix_check.no_qsuf = 1;
3281 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3282 suffix_check.no_ldsuf = 1;
3284 for (t = current_templates->start; t < current_templates->end; t++)
3286 addr_prefix_disp = -1;
3288 /* Must have right number of operands. */
3289 if (i.operands != t->operands)
3292 /* Check processor support. */
3293 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3294 if (!found_cpu_match)
3297 /* Check old gcc support. */
3298 if (!old_gcc && t->opcode_modifier.oldgcc)
3301 /* Check AT&T mnemonic. */
3302 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3305 /* Check AT&T syntax Intel syntax. */
3306 if ((intel_syntax && t->opcode_modifier.attsyntax)
3307 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3310 /* Check the suffix, except for some instructions in intel mode. */
3311 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3312 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3313 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3314 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3315 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3316 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3317 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3320 if (!operand_size_match (t))
3323 for (j = 0; j < MAX_OPERANDS; j++)
3324 operand_types[j] = t->operand_types[j];
3326 /* In general, don't allow 64-bit operands in 32-bit mode. */
3327 if (i.suffix == QWORD_MNEM_SUFFIX
3328 && flag_code != CODE_64BIT
3330 ? (!t->opcode_modifier.ignoresize
3331 && !intel_float_operand (t->name))
3332 : intel_float_operand (t->name) != 2)
3333 && ((!operand_types[0].bitfield.regmmx
3334 && !operand_types[0].bitfield.regxmm)
3335 || (!operand_types[t->operands > 1].bitfield.regmmx
3336 && !!operand_types[t->operands > 1].bitfield.regxmm))
3337 && (t->base_opcode != 0x0fc7
3338 || t->extension_opcode != 1 /* cmpxchg8b */))
3341 /* Do not verify operands when there are none. */
3345 /* We've found a match; break out of loop. */
3349 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3350 into Disp32/Disp16/Disp32 operand. */
3351 if (i.prefix[ADDR_PREFIX] != 0)
3353 /* There should be only one Disp operand. */
3357 for (j = 0; j < MAX_OPERANDS; j++)
3359 if (operand_types[j].bitfield.disp16)
3361 addr_prefix_disp = j;
3362 operand_types[j].bitfield.disp32 = 1;
3363 operand_types[j].bitfield.disp16 = 0;
3369 for (j = 0; j < MAX_OPERANDS; j++)
3371 if (operand_types[j].bitfield.disp32)
3373 addr_prefix_disp = j;
3374 operand_types[j].bitfield.disp32 = 0;
3375 operand_types[j].bitfield.disp16 = 1;
3381 for (j = 0; j < MAX_OPERANDS; j++)
3383 if (operand_types[j].bitfield.disp64)
3385 addr_prefix_disp = j;
3386 operand_types[j].bitfield.disp64 = 0;
3387 operand_types[j].bitfield.disp32 = 1;
3395 /* We check register size only if size of operands can be
3396 encoded the canonical way. */
3397 check_register = t->opcode_modifier.w;
3398 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3399 switch (t->operands)
3402 if (!operand_type_match (overlap0, i.types[0]))
3406 /* xchg %eax, %eax is a special case. It is an aliase for nop
3407 only in 32bit mode and we can use opcode 0x90. In 64bit
3408 mode, we can't use 0x90 for xchg %eax, %eax since it should
3409 zero-extend %eax to %rax. */
3410 if (flag_code == CODE_64BIT
3411 && t->base_opcode == 0x90
3412 && operand_type_equal (&i.types [0], &acc32)
3413 && operand_type_equal (&i.types [1], &acc32))
3417 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3418 if (!operand_type_match (overlap0, i.types[0])
3419 || !operand_type_match (overlap1, i.types[1])
3421 && !operand_type_register_match (overlap0, i.types[0],
3423 overlap1, i.types[1],
3426 /* Check if other direction is valid ... */
3427 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3430 /* Try reversing direction of operands. */
3431 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3432 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3433 if (!operand_type_match (overlap0, i.types[0])
3434 || !operand_type_match (overlap1, i.types[1])
3436 && !operand_type_register_match (overlap0,
3443 /* Does not match either direction. */
3446 /* found_reverse_match holds which of D or FloatDR
3448 if (t->opcode_modifier.d)
3449 found_reverse_match = Opcode_D;
3450 else if (t->opcode_modifier.floatd)
3451 found_reverse_match = Opcode_FloatD;
3453 found_reverse_match = 0;
3454 if (t->opcode_modifier.floatr)
3455 found_reverse_match |= Opcode_FloatR;
3459 /* Found a forward 2 operand match here. */
3460 switch (t->operands)
3463 overlap3 = operand_type_and (i.types[3],
3466 overlap2 = operand_type_and (i.types[2],
3471 switch (t->operands)
3474 if (!operand_type_match (overlap3, i.types[3])
3476 && !operand_type_register_match (overlap2,
3484 /* Here we make use of the fact that there are no
3485 reverse match 3 operand instructions, and all 3
3486 operand instructions only need to be checked for
3487 register consistency between operands 2 and 3. */
3488 if (!operand_type_match (overlap2, i.types[2])
3490 && !operand_type_register_match (overlap1,
3500 /* Found either forward/reverse 2, 3 or 4 operand match here:
3501 slip through to break. */
3503 if (!found_cpu_match)
3505 found_reverse_match = 0;
3508 /* We've found a match; break out of loop. */
3512 if (t == current_templates->end)
3514 /* We found no match. */
3515 as_bad (_("suffix or operands invalid for `%s'"),
3516 current_templates->start->name);
3520 if (!quiet_warnings)
3523 && (i.types[0].bitfield.jumpabsolute
3524 != operand_types[0].bitfield.jumpabsolute))
3526 as_warn (_("indirect %s without `*'"), t->name);
3529 if (t->opcode_modifier.isprefix
3530 && t->opcode_modifier.ignoresize)
3532 /* Warn them that a data or address size prefix doesn't
3533 affect assembly of the next line of code. */
3534 as_warn (_("stand-alone `%s' prefix"), t->name);
3538 /* Copy the template we found. */
3541 if (addr_prefix_disp != -1)
3542 i.tm.operand_types[addr_prefix_disp]
3543 = operand_types[addr_prefix_disp];
3545 if (found_reverse_match)
3547 /* If we found a reverse match we must alter the opcode
3548 direction bit. found_reverse_match holds bits to change
3549 (different for int & float insns). */
3551 i.tm.base_opcode ^= found_reverse_match;
3553 i.tm.operand_types[0] = operand_types[1];
3554 i.tm.operand_types[1] = operand_types[0];
3563 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3564 if (i.tm.operand_types[mem_op].bitfield.esseg)
3566 if (i.seg[0] != NULL && i.seg[0] != &es)
3568 as_bad (_("`%s' operand %d must use `%%es' segment"),
3573 /* There's only ever one segment override allowed per instruction.
3574 This instruction possibly has a legal segment override on the
3575 second operand, so copy the segment to where non-string
3576 instructions store it, allowing common code. */
3577 i.seg[0] = i.seg[1];
3579 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3581 if (i.seg[1] != NULL && i.seg[1] != &es)
3583 as_bad (_("`%s' operand %d must use `%%es' segment"),
3593 process_suffix (void)
3595 /* If matched instruction specifies an explicit instruction mnemonic
3597 if (i.tm.opcode_modifier.size16)
3598 i.suffix = WORD_MNEM_SUFFIX;
3599 else if (i.tm.opcode_modifier.size32)
3600 i.suffix = LONG_MNEM_SUFFIX;
3601 else if (i.tm.opcode_modifier.size64)
3602 i.suffix = QWORD_MNEM_SUFFIX;
3603 else if (i.reg_operands)
3605 /* If there's no instruction mnemonic suffix we try to invent one
3606 based on register operands. */
3609 /* We take i.suffix from the last register operand specified,
3610 Destination register type is more significant than source
3611 register type. crc32 in SSE4.2 prefers source register
3613 if (i.tm.base_opcode == 0xf20f38f1)
3615 if (i.types[0].bitfield.reg16)
3616 i.suffix = WORD_MNEM_SUFFIX;
3617 else if (i.types[0].bitfield.reg32)
3618 i.suffix = LONG_MNEM_SUFFIX;
3619 else if (i.types[0].bitfield.reg64)
3620 i.suffix = QWORD_MNEM_SUFFIX;
3622 else if (i.tm.base_opcode == 0xf20f38f0)
3624 if (i.types[0].bitfield.reg8)
3625 i.suffix = BYTE_MNEM_SUFFIX;
3632 if (i.tm.base_opcode == 0xf20f38f1
3633 || i.tm.base_opcode == 0xf20f38f0)
3635 /* We have to know the operand size for crc32. */
3636 as_bad (_("ambiguous memory operand size for `%s`"),
3641 for (op = i.operands; --op >= 0;)
3642 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3644 if (i.types[op].bitfield.reg8)
3646 i.suffix = BYTE_MNEM_SUFFIX;
3649 else if (i.types[op].bitfield.reg16)
3651 i.suffix = WORD_MNEM_SUFFIX;
3654 else if (i.types[op].bitfield.reg32)
3656 i.suffix = LONG_MNEM_SUFFIX;
3659 else if (i.types[op].bitfield.reg64)
3661 i.suffix = QWORD_MNEM_SUFFIX;
3667 else if (i.suffix == BYTE_MNEM_SUFFIX)
3669 if (!check_byte_reg ())
3672 else if (i.suffix == LONG_MNEM_SUFFIX)
3674 if (!check_long_reg ())
3677 else if (i.suffix == QWORD_MNEM_SUFFIX)
3680 && i.tm.opcode_modifier.ignoresize
3681 && i.tm.opcode_modifier.no_qsuf)
3683 else if (!check_qword_reg ())
3686 else if (i.suffix == WORD_MNEM_SUFFIX)
3688 if (!check_word_reg ())
3691 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3693 /* Skip if the instruction has x suffix. match_template
3694 should check if it is a valid suffix. */
3696 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3697 /* Do nothing if the instruction is going to ignore the prefix. */
3702 else if (i.tm.opcode_modifier.defaultsize
3704 /* exclude fldenv/frstor/fsave/fstenv */
3705 && i.tm.opcode_modifier.no_ssuf)
3707 i.suffix = stackop_size;
3709 else if (intel_syntax
3711 && (i.tm.operand_types[0].bitfield.jumpabsolute
3712 || i.tm.opcode_modifier.jumpbyte
3713 || i.tm.opcode_modifier.jumpintersegment
3714 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3715 && i.tm.extension_opcode <= 3)))
3720 if (!i.tm.opcode_modifier.no_qsuf)
3722 i.suffix = QWORD_MNEM_SUFFIX;
3726 if (!i.tm.opcode_modifier.no_lsuf)
3727 i.suffix = LONG_MNEM_SUFFIX;
3730 if (!i.tm.opcode_modifier.no_wsuf)
3731 i.suffix = WORD_MNEM_SUFFIX;
3740 if (i.tm.opcode_modifier.w)
3742 as_bad (_("no instruction mnemonic suffix given and "
3743 "no register operands; can't size instruction"));
3749 unsigned int suffixes;
3751 suffixes = !i.tm.opcode_modifier.no_bsuf;
3752 if (!i.tm.opcode_modifier.no_wsuf)
3754 if (!i.tm.opcode_modifier.no_lsuf)
3756 if (!i.tm.opcode_modifier.no_ldsuf)
3758 if (!i.tm.opcode_modifier.no_ssuf)
3760 if (!i.tm.opcode_modifier.no_qsuf)
3763 /* There are more than suffix matches. */
3764 if (i.tm.opcode_modifier.w
3765 || ((suffixes & (suffixes - 1))
3766 && !i.tm.opcode_modifier.defaultsize
3767 && !i.tm.opcode_modifier.ignoresize))
3769 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3775 /* Change the opcode based on the operand size given by i.suffix;
3776 We don't need to change things for byte insns. */
3779 && i.suffix != BYTE_MNEM_SUFFIX
3780 && i.suffix != XMMWORD_MNEM_SUFFIX)
3782 /* It's not a byte, select word/dword operation. */
3783 if (i.tm.opcode_modifier.w)
3785 if (i.tm.opcode_modifier.shortform)
3786 i.tm.base_opcode |= 8;
3788 i.tm.base_opcode |= 1;
3791 /* Now select between word & dword operations via the operand
3792 size prefix, except for instructions that will ignore this
3794 if (i.tm.opcode_modifier.addrprefixop0)
3796 /* The address size override prefix changes the size of the
3798 if ((flag_code == CODE_32BIT
3799 && i.op->regs[0].reg_type.bitfield.reg16)
3800 || (flag_code != CODE_32BIT
3801 && i.op->regs[0].reg_type.bitfield.reg32))
3802 if (!add_prefix (ADDR_PREFIX_OPCODE))
3805 else if (i.suffix != QWORD_MNEM_SUFFIX
3806 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3807 && !i.tm.opcode_modifier.ignoresize
3808 && !i.tm.opcode_modifier.floatmf
3809 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3810 || (flag_code == CODE_64BIT
3811 && i.tm.opcode_modifier.jumpbyte)))
3813 unsigned int prefix = DATA_PREFIX_OPCODE;
3815 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3816 prefix = ADDR_PREFIX_OPCODE;
3818 if (!add_prefix (prefix))
3822 /* Set mode64 for an operand. */
3823 if (i.suffix == QWORD_MNEM_SUFFIX
3824 && flag_code == CODE_64BIT
3825 && !i.tm.opcode_modifier.norex64)
3827 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3828 need rex64. cmpxchg8b is also a special case. */
3829 if (! (i.operands == 2
3830 && i.tm.base_opcode == 0x90
3831 && i.tm.extension_opcode == None
3832 && operand_type_equal (&i.types [0], &acc64)
3833 && operand_type_equal (&i.types [1], &acc64))
3834 && ! (i.operands == 1
3835 && i.tm.base_opcode == 0xfc7
3836 && i.tm.extension_opcode == 1
3837 && !operand_type_check (i.types [0], reg)
3838 && operand_type_check (i.types [0], anymem)))
3842 /* Size floating point instruction. */
3843 if (i.suffix == LONG_MNEM_SUFFIX)
3844 if (i.tm.opcode_modifier.floatmf)
3845 i.tm.base_opcode ^= 4;
3852 check_byte_reg (void)
3856 for (op = i.operands; --op >= 0;)
3858 /* If this is an eight bit register, it's OK. If it's the 16 or
3859 32 bit version of an eight bit register, we will just use the
3860 low portion, and that's OK too. */
3861 if (i.types[op].bitfield.reg8)
3864 /* Don't generate this warning if not needed. */
3865 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3868 /* crc32 doesn't generate this warning. */
3869 if (i.tm.base_opcode == 0xf20f38f0)
3872 if ((i.types[op].bitfield.reg16
3873 || i.types[op].bitfield.reg32
3874 || i.types[op].bitfield.reg64)
3875 && i.op[op].regs->reg_num < 4)
3877 /* Prohibit these changes in the 64bit mode, since the
3878 lowering is more complicated. */
3879 if (flag_code == CODE_64BIT
3880 && !i.tm.operand_types[op].bitfield.inoutportreg)
3882 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3883 register_prefix, i.op[op].regs->reg_name,
3887 #if REGISTER_WARNINGS
3889 && !i.tm.operand_types[op].bitfield.inoutportreg)
3890 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3892 (i.op[op].regs + (i.types[op].bitfield.reg16
3893 ? REGNAM_AL - REGNAM_AX
3894 : REGNAM_AL - REGNAM_EAX))->reg_name,
3896 i.op[op].regs->reg_name,
3901 /* Any other register is bad. */
3902 if (i.types[op].bitfield.reg16
3903 || i.types[op].bitfield.reg32
3904 || i.types[op].bitfield.reg64
3905 || i.types[op].bitfield.regmmx
3906 || i.types[op].bitfield.regxmm
3907 || i.types[op].bitfield.sreg2
3908 || i.types[op].bitfield.sreg3
3909 || i.types[op].bitfield.control
3910 || i.types[op].bitfield.debug
3911 || i.types[op].bitfield.test
3912 || i.types[op].bitfield.floatreg
3913 || i.types[op].bitfield.floatacc)
3915 as_bad (_("`%s%s' not allowed with `%s%c'"),
3917 i.op[op].regs->reg_name,
3927 check_long_reg (void)
3931 for (op = i.operands; --op >= 0;)
3932 /* Reject eight bit registers, except where the template requires
3933 them. (eg. movzb) */
3934 if (i.types[op].bitfield.reg8
3935 && (i.tm.operand_types[op].bitfield.reg16
3936 || i.tm.operand_types[op].bitfield.reg32
3937 || i.tm.operand_types[op].bitfield.acc))
3939 as_bad (_("`%s%s' not allowed with `%s%c'"),
3941 i.op[op].regs->reg_name,
3946 /* Warn if the e prefix on a general reg is missing. */
3947 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3948 && i.types[op].bitfield.reg16
3949 && (i.tm.operand_types[op].bitfield.reg32
3950 || i.tm.operand_types[op].bitfield.acc))
3952 /* Prohibit these changes in the 64bit mode, since the
3953 lowering is more complicated. */
3954 if (flag_code == CODE_64BIT)
3956 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3957 register_prefix, i.op[op].regs->reg_name,
3961 #if REGISTER_WARNINGS
3963 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3965 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3967 i.op[op].regs->reg_name,
3971 /* Warn if the r prefix on a general reg is missing. */
3972 else if (i.types[op].bitfield.reg64
3973 && (i.tm.operand_types[op].bitfield.reg32
3974 || i.tm.operand_types[op].bitfield.acc))
3977 && i.tm.opcode_modifier.toqword
3978 && !i.types[0].bitfield.regxmm)
3980 /* Convert to QWORD. We want REX byte. */
3981 i.suffix = QWORD_MNEM_SUFFIX;
3985 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3986 register_prefix, i.op[op].regs->reg_name,
3995 check_qword_reg (void)
3999 for (op = i.operands; --op >= 0; )
4000 /* Reject eight bit registers, except where the template requires
4001 them. (eg. movzb) */
4002 if (i.types[op].bitfield.reg8
4003 && (i.tm.operand_types[op].bitfield.reg16
4004 || i.tm.operand_types[op].bitfield.reg32
4005 || i.tm.operand_types[op].bitfield.acc))
4007 as_bad (_("`%s%s' not allowed with `%s%c'"),
4009 i.op[op].regs->reg_name,
4014 /* Warn if the e prefix on a general reg is missing. */
4015 else if ((i.types[op].bitfield.reg16
4016 || i.types[op].bitfield.reg32)
4017 && (i.tm.operand_types[op].bitfield.reg32
4018 || i.tm.operand_types[op].bitfield.acc))
4020 /* Prohibit these changes in the 64bit mode, since the
4021 lowering is more complicated. */
4023 && i.tm.opcode_modifier.todword
4024 && !i.types[0].bitfield.regxmm)
4026 /* Convert to DWORD. We don't want REX byte. */
4027 i.suffix = LONG_MNEM_SUFFIX;
4031 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4032 register_prefix, i.op[op].regs->reg_name,
4041 check_word_reg (void)
4044 for (op = i.operands; --op >= 0;)
4045 /* Reject eight bit registers, except where the template requires
4046 them. (eg. movzb) */
4047 if (i.types[op].bitfield.reg8
4048 && (i.tm.operand_types[op].bitfield.reg16
4049 || i.tm.operand_types[op].bitfield.reg32
4050 || i.tm.operand_types[op].bitfield.acc))
4052 as_bad (_("`%s%s' not allowed with `%s%c'"),
4054 i.op[op].regs->reg_name,
4059 /* Warn if the e prefix on a general reg is present. */
4060 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4061 && i.types[op].bitfield.reg32
4062 && (i.tm.operand_types[op].bitfield.reg16
4063 || i.tm.operand_types[op].bitfield.acc))
4065 /* Prohibit these changes in the 64bit mode, since the
4066 lowering is more complicated. */
4067 if (flag_code == CODE_64BIT)
4069 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4070 register_prefix, i.op[op].regs->reg_name,
4075 #if REGISTER_WARNINGS
4076 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4078 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4080 i.op[op].regs->reg_name,
4088 update_imm (unsigned int j)
4090 i386_operand_type overlap;
4092 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4093 if ((overlap.bitfield.imm8
4094 || overlap.bitfield.imm8s
4095 || overlap.bitfield.imm16
4096 || overlap.bitfield.imm32
4097 || overlap.bitfield.imm32s
4098 || overlap.bitfield.imm64)
4099 && !operand_type_equal (&overlap, &imm8)
4100 && !operand_type_equal (&overlap, &imm8s)
4101 && !operand_type_equal (&overlap, &imm16)
4102 && !operand_type_equal (&overlap, &imm32)
4103 && !operand_type_equal (&overlap, &imm32s)
4104 && !operand_type_equal (&overlap, &imm64))
4108 i386_operand_type temp;
4110 operand_type_set (&temp, 0);
4111 if (i.suffix == BYTE_MNEM_SUFFIX)
4113 temp.bitfield.imm8 = overlap.bitfield.imm8;
4114 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4116 else if (i.suffix == WORD_MNEM_SUFFIX)
4117 temp.bitfield.imm16 = overlap.bitfield.imm16;
4118 else if (i.suffix == QWORD_MNEM_SUFFIX)
4120 temp.bitfield.imm64 = overlap.bitfield.imm64;
4121 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4124 temp.bitfield.imm32 = overlap.bitfield.imm32;
4127 else if (operand_type_equal (&overlap, &imm16_32_32s)
4128 || operand_type_equal (&overlap, &imm16_32)
4129 || operand_type_equal (&overlap, &imm16_32s))
4131 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4136 if (!operand_type_equal (&overlap, &imm8)
4137 && !operand_type_equal (&overlap, &imm8s)
4138 && !operand_type_equal (&overlap, &imm16)
4139 && !operand_type_equal (&overlap, &imm32)
4140 && !operand_type_equal (&overlap, &imm32s)
4141 && !operand_type_equal (&overlap, &imm64))
4143 as_bad (_("no instruction mnemonic suffix given; "
4144 "can't determine immediate size"));
4148 i.types[j] = overlap;
4158 for (j = 0; j < 2; j++)
4159 if (update_imm (j) == 0)
4162 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4163 assert (operand_type_check (i.types[2], imm) == 0);
4171 i.drex.modrm_reg = 0;
4172 i.drex.modrm_regmem = 0;
4174 /* SSE5 4 operand instructions must have the destination the same as
4175 one of the inputs. Figure out the destination register and cache
4176 it away in the drex field, and remember which fields to use for
4178 if (i.tm.opcode_modifier.drex
4179 && i.tm.opcode_modifier.drexv
4182 i.tm.extension_opcode = None;
4184 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4185 if (i.types[0].bitfield.regxmm != 0
4186 && i.types[1].bitfield.regxmm != 0
4187 && i.types[2].bitfield.regxmm != 0
4188 && i.types[3].bitfield.regxmm != 0
4189 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4190 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4192 /* Clear the arguments that are stored in drex. */
4193 operand_type_set (&i.types[0], 0);
4194 operand_type_set (&i.types[3], 0);
4195 i.reg_operands -= 2;
4197 /* There are two different ways to encode a 4 operand
4198 instruction with all registers that uses OC1 set to
4199 0 or 1. Favor setting OC1 to 0 since this mimics the
4200 actions of other SSE5 assemblers. Use modrm encoding 2
4201 for register/register. Include the high order bit that
4202 is normally stored in the REX byte in the register
4204 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4205 i.drex.modrm_reg = 2;
4206 i.drex.modrm_regmem = 1;
4207 i.drex.reg = (i.op[3].regs->reg_num
4208 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4211 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4212 else if (i.types[0].bitfield.regxmm != 0
4213 && i.types[1].bitfield.regxmm != 0
4214 && (i.types[2].bitfield.regxmm
4215 || operand_type_check (i.types[2], anymem))
4216 && i.types[3].bitfield.regxmm != 0
4217 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4218 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4220 /* clear the arguments that are stored in drex */
4221 operand_type_set (&i.types[0], 0);
4222 operand_type_set (&i.types[3], 0);
4223 i.reg_operands -= 2;
4225 /* Specify the modrm encoding for memory addressing. Include
4226 the high order bit that is normally stored in the REX byte
4227 in the register field. */
4228 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4229 i.drex.modrm_reg = 1;
4230 i.drex.modrm_regmem = 2;
4231 i.drex.reg = (i.op[3].regs->reg_num
4232 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4235 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4236 else if (i.types[0].bitfield.regxmm != 0
4237 && operand_type_check (i.types[1], anymem) != 0
4238 && i.types[2].bitfield.regxmm != 0
4239 && i.types[3].bitfield.regxmm != 0
4240 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4241 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4243 /* Clear the arguments that are stored in drex. */
4244 operand_type_set (&i.types[0], 0);
4245 operand_type_set (&i.types[3], 0);
4246 i.reg_operands -= 2;
4248 /* Specify the modrm encoding for memory addressing. Include
4249 the high order bit that is normally stored in the REX byte
4250 in the register field. */
4251 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4252 i.drex.modrm_reg = 2;
4253 i.drex.modrm_regmem = 1;
4254 i.drex.reg = (i.op[3].regs->reg_num
4255 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4258 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4259 else if (i.types[0].bitfield.regxmm != 0
4260 && i.types[1].bitfield.regxmm != 0
4261 && i.types[2].bitfield.regxmm != 0
4262 && i.types[3].bitfield.regxmm != 0
4263 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4264 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4266 /* clear the arguments that are stored in drex */
4267 operand_type_set (&i.types[2], 0);
4268 operand_type_set (&i.types[3], 0);
4269 i.reg_operands -= 2;
4271 /* There are two different ways to encode a 4 operand
4272 instruction with all registers that uses OC1 set to
4273 0 or 1. Favor setting OC1 to 0 since this mimics the
4274 actions of other SSE5 assemblers. Use modrm encoding
4275 2 for register/register. Include the high order bit that
4276 is normally stored in the REX byte in the register
4278 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4279 i.drex.modrm_reg = 1;
4280 i.drex.modrm_regmem = 0;
4282 /* Remember the register, including the upper bits */
4283 i.drex.reg = (i.op[3].regs->reg_num
4284 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4287 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4288 else if (i.types[0].bitfield.regxmm != 0
4289 && (i.types[1].bitfield.regxmm
4290 || operand_type_check (i.types[1], anymem))
4291 && i.types[2].bitfield.regxmm != 0
4292 && i.types[3].bitfield.regxmm != 0
4293 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4294 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4296 /* Clear the arguments that are stored in drex. */
4297 operand_type_set (&i.types[2], 0);
4298 operand_type_set (&i.types[3], 0);
4299 i.reg_operands -= 2;
4301 /* Specify the modrm encoding and remember the register
4302 including the bits normally stored in the REX byte. */
4303 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4304 i.drex.modrm_reg = 0;
4305 i.drex.modrm_regmem = 1;
4306 i.drex.reg = (i.op[3].regs->reg_num
4307 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4310 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4311 else if (operand_type_check (i.types[0], anymem) != 0
4312 && i.types[1].bitfield.regxmm != 0
4313 && i.types[2].bitfield.regxmm != 0
4314 && i.types[3].bitfield.regxmm != 0
4315 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4316 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4318 /* clear the arguments that are stored in drex */
4319 operand_type_set (&i.types[2], 0);
4320 operand_type_set (&i.types[3], 0);
4321 i.reg_operands -= 2;
4323 /* Specify the modrm encoding and remember the register
4324 including the bits normally stored in the REX byte. */
4325 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4326 i.drex.modrm_reg = 1;
4327 i.drex.modrm_regmem = 0;
4328 i.drex.reg = (i.op[3].regs->reg_num
4329 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4333 as_bad (_("Incorrect operands for the '%s' instruction"),
4337 /* SSE5 instructions with the DREX byte where the only memory operand
4338 is in the 2nd argument, and the first and last xmm register must
4339 match, and is encoded in the DREX byte. */
4340 else if (i.tm.opcode_modifier.drex
4341 && !i.tm.opcode_modifier.drexv
4344 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4345 if (i.types[0].bitfield.regxmm != 0
4346 && (i.types[1].bitfield.regxmm
4347 || operand_type_check(i.types[1], anymem))
4348 && i.types[2].bitfield.regxmm != 0
4349 && i.types[3].bitfield.regxmm != 0
4350 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4351 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4353 /* clear the arguments that are stored in drex */
4354 operand_type_set (&i.types[0], 0);
4355 operand_type_set (&i.types[3], 0);
4356 i.reg_operands -= 2;
4358 /* Specify the modrm encoding and remember the register
4359 including the high bit normally stored in the REX
4361 i.drex.modrm_reg = 2;
4362 i.drex.modrm_regmem = 1;
4363 i.drex.reg = (i.op[3].regs->reg_num
4364 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4368 as_bad (_("Incorrect operands for the '%s' instruction"),
4372 /* SSE5 3 operand instructions that the result is a register, being
4373 either operand can be a memory operand, using OC0 to note which
4374 one is the memory. */
4375 else if (i.tm.opcode_modifier.drex
4376 && i.tm.opcode_modifier.drexv
4379 i.tm.extension_opcode = None;
4381 /* Case 1: 3 operand insn, src1 = register. */
4382 if (i.types[0].bitfield.regxmm != 0
4383 && i.types[1].bitfield.regxmm != 0
4384 && i.types[2].bitfield.regxmm != 0)
4386 /* Clear the arguments that are stored in drex. */
4387 operand_type_set (&i.types[2], 0);
4390 /* Specify the modrm encoding and remember the register
4391 including the high bit normally stored in the REX byte. */
4392 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4393 i.drex.modrm_reg = 1;
4394 i.drex.modrm_regmem = 0;
4395 i.drex.reg = (i.op[2].regs->reg_num
4396 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4399 /* Case 2: 3 operand insn, src1 = memory. */
4400 else if (operand_type_check (i.types[0], anymem) != 0
4401 && i.types[1].bitfield.regxmm != 0
4402 && i.types[2].bitfield.regxmm != 0)
4404 /* Clear the arguments that are stored in drex. */
4405 operand_type_set (&i.types[2], 0);
4408 /* Specify the modrm encoding and remember the register
4409 including the high bit normally stored in the REX
4411 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4412 i.drex.modrm_reg = 1;
4413 i.drex.modrm_regmem = 0;
4414 i.drex.reg = (i.op[2].regs->reg_num
4415 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4418 /* Case 3: 3 operand insn, src2 = memory. */
4419 else if (i.types[0].bitfield.regxmm != 0
4420 && operand_type_check (i.types[1], anymem) != 0
4421 && i.types[2].bitfield.regxmm != 0)
4423 /* Clear the arguments that are stored in drex. */
4424 operand_type_set (&i.types[2], 0);
4427 /* Specify the modrm encoding and remember the register
4428 including the high bit normally stored in the REX byte. */
4429 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4430 i.drex.modrm_reg = 0;
4431 i.drex.modrm_regmem = 1;
4432 i.drex.reg = (i.op[2].regs->reg_num
4433 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4437 as_bad (_("Incorrect operands for the '%s' instruction"),
4441 /* SSE5 4 operand instructions that are the comparison instructions
4442 where the first operand is the immediate value of the comparison
4444 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4446 /* Case 1: 4 operand insn, src1 = reg/memory. */
4447 if (operand_type_check (i.types[0], imm) != 0
4448 && (i.types[1].bitfield.regxmm
4449 || operand_type_check (i.types[1], anymem))
4450 && i.types[2].bitfield.regxmm != 0
4451 && i.types[3].bitfield.regxmm != 0)
4453 /* clear the arguments that are stored in drex */
4454 operand_type_set (&i.types[3], 0);
4457 /* Specify the modrm encoding and remember the register
4458 including the high bit normally stored in the REX byte. */
4459 i.drex.modrm_reg = 2;
4460 i.drex.modrm_regmem = 1;
4461 i.drex.reg = (i.op[3].regs->reg_num
4462 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4465 /* Case 2: 3 operand insn with ImmExt that places the
4466 opcode_extension as an immediate argument. This is used for
4467 all of the varients of comparison that supplies the appropriate
4468 value as part of the instruction. */
4469 else if ((i.types[0].bitfield.regxmm
4470 || operand_type_check (i.types[0], anymem))
4471 && i.types[1].bitfield.regxmm != 0
4472 && i.types[2].bitfield.regxmm != 0
4473 && operand_type_check (i.types[3], imm) != 0)
4475 /* clear the arguments that are stored in drex */
4476 operand_type_set (&i.types[2], 0);
4479 /* Specify the modrm encoding and remember the register
4480 including the high bit normally stored in the REX byte. */
4481 i.drex.modrm_reg = 1;
4482 i.drex.modrm_regmem = 0;
4483 i.drex.reg = (i.op[2].regs->reg_num
4484 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4488 as_bad (_("Incorrect operands for the '%s' instruction"),
4492 else if (i.tm.opcode_modifier.drex
4493 || i.tm.opcode_modifier.drexv
4494 || i.tm.opcode_modifier.drexc)
4495 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4499 process_operands (void)
4501 /* Default segment register this instruction will use for memory
4502 accesses. 0 means unknown. This is only for optimizing out
4503 unnecessary segment overrides. */
4504 const seg_entry *default_seg = 0;
4506 /* Handle all of the DREX munging that SSE5 needs. */
4507 if (i.tm.opcode_modifier.drex
4508 || i.tm.opcode_modifier.drexv
4509 || i.tm.opcode_modifier.drexc)
4512 if (i.tm.opcode_modifier.firstxmm0)
4516 /* The first operand is implicit and must be xmm0. */
4517 assert (i.reg_operands
4518 && operand_type_equal (&i.types[0], ®xmm));
4519 if (i.op[0].regs->reg_num != 0)
4522 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4523 i.tm.name, register_prefix);
4525 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4526 i.tm.name, register_prefix);
4530 for (j = 1; j < i.operands; j++)
4532 i.op[j - 1] = i.op[j];
4533 i.types[j - 1] = i.types[j];
4535 /* We need to adjust fields in i.tm since they are used by
4536 build_modrm_byte. */
4537 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4544 else if (i.tm.opcode_modifier.regkludge)
4546 /* The imul $imm, %reg instruction is converted into
4547 imul $imm, %reg, %reg, and the clr %reg instruction
4548 is converted into xor %reg, %reg. */
4550 unsigned int first_reg_op;
4552 if (operand_type_check (i.types[0], reg))
4556 /* Pretend we saw the extra register operand. */
4557 assert (i.reg_operands == 1
4558 && i.op[first_reg_op + 1].regs == 0);
4559 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4560 i.types[first_reg_op + 1] = i.types[first_reg_op];
4565 if (i.tm.opcode_modifier.shortform)
4567 if (i.types[0].bitfield.sreg2
4568 || i.types[0].bitfield.sreg3)
4570 if (i.tm.base_opcode == POP_SEG_SHORT
4571 && i.op[0].regs->reg_num == 1)
4573 as_bad (_("you can't `pop %%cs'"));
4576 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4577 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4582 /* The register or float register operand is in operand
4586 if (i.types[0].bitfield.floatreg
4587 || operand_type_check (i.types[0], reg))
4591 /* Register goes in low 3 bits of opcode. */
4592 i.tm.base_opcode |= i.op[op].regs->reg_num;
4593 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4595 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4597 /* Warn about some common errors, but press on regardless.
4598 The first case can be generated by gcc (<= 2.8.1). */
4599 if (i.operands == 2)
4601 /* Reversed arguments on faddp, fsubp, etc. */
4602 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4603 register_prefix, i.op[1].regs->reg_name,
4604 register_prefix, i.op[0].regs->reg_name);
4608 /* Extraneous `l' suffix on fp insn. */
4609 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4610 register_prefix, i.op[0].regs->reg_name);
4615 else if (i.tm.opcode_modifier.modrm)
4617 /* The opcode is completed (modulo i.tm.extension_opcode which
4618 must be put into the modrm byte). Now, we make the modrm and
4619 index base bytes based on all the info we've collected. */
4621 default_seg = build_modrm_byte ();
4623 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4627 else if (i.tm.opcode_modifier.isstring)
4629 /* For the string instructions that allow a segment override
4630 on one of their operands, the default segment is ds. */
4634 if (i.tm.base_opcode == 0x8d /* lea */
4637 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4639 /* If a segment was explicitly specified, and the specified segment
4640 is not the default, use an opcode prefix to select it. If we
4641 never figured out what the default segment is, then default_seg
4642 will be zero at this point, and the specified segment prefix will
4644 if ((i.seg[0]) && (i.seg[0] != default_seg))
4646 if (!add_prefix (i.seg[0]->seg_prefix))
4652 static const seg_entry *
4653 build_modrm_byte (void)
4655 const seg_entry *default_seg = 0;
4657 /* SSE5 4 operand instructions are encoded in such a way that one of
4658 the inputs must match the destination register. Process_drex hides
4659 the 3rd argument in the drex field, so that by the time we get
4660 here, it looks to GAS as if this is a 2 operand instruction. */
4661 if ((i.tm.opcode_modifier.drex
4662 || i.tm.opcode_modifier.drexv
4663 || i.tm.opcode_modifier.drexc)
4664 && i.reg_operands == 2)
4666 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4667 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4669 i.rm.reg = reg->reg_num;
4670 i.rm.regmem = regmem->reg_num;
4672 if ((reg->reg_flags & RegRex) != 0)
4674 if ((regmem->reg_flags & RegRex) != 0)
4678 /* i.reg_operands MUST be the number of real register operands;
4679 implicit registers do not count. */
4680 else if (i.reg_operands == 2)
4682 unsigned int source, dest;
4690 /* When there are 3 operands, one of them may be immediate,
4691 which may be the first or the last operand. Otherwise,
4692 the first operand must be shift count register (cl). */
4693 assert (i.imm_operands == 1
4694 || (i.imm_operands == 0
4695 && i.types[0].bitfield.shiftcount));
4696 if (operand_type_check (i.types[0], imm)
4697 || i.types[0].bitfield.shiftcount)
4703 /* When there are 4 operands, the first two must be 8bit
4704 immediate operands. The source operand will be the 3rd
4706 assert (i.imm_operands == 2
4707 && i.types[0].bitfield.imm8
4708 && i.types[1].bitfield.imm8);
4718 /* One of the register operands will be encoded in the i.tm.reg
4719 field, the other in the combined i.tm.mode and i.tm.regmem
4720 fields. If no form of this instruction supports a memory
4721 destination operand, then we assume the source operand may
4722 sometimes be a memory operand and so we need to store the
4723 destination in the i.rm.reg field. */
4724 if (!i.tm.operand_types[dest].bitfield.regmem
4725 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4727 i.rm.reg = i.op[dest].regs->reg_num;
4728 i.rm.regmem = i.op[source].regs->reg_num;
4729 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4731 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4736 i.rm.reg = i.op[source].regs->reg_num;
4737 i.rm.regmem = i.op[dest].regs->reg_num;
4738 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4740 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4743 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4745 if (!i.types[0].bitfield.control
4746 && !i.types[1].bitfield.control)
4748 i.rex &= ~(REX_R | REX_B);
4749 add_prefix (LOCK_PREFIX_OPCODE);
4753 { /* If it's not 2 reg operands... */
4756 unsigned int fake_zero_displacement = 0;
4759 /* This has been precalculated for SSE5 instructions
4760 that have a DREX field earlier in process_drex. */
4761 if (i.tm.opcode_modifier.drex
4762 || i.tm.opcode_modifier.drexv
4763 || i.tm.opcode_modifier.drexc)
4764 op = i.drex.modrm_regmem;
4767 for (op = 0; op < i.operands; op++)
4768 if (operand_type_check (i.types[op], anymem))
4770 assert (op < i.operands);
4775 if (i.base_reg == 0)
4778 if (!i.disp_operands)
4779 fake_zero_displacement = 1;
4780 if (i.index_reg == 0)
4782 /* Operand is just <disp> */
4783 if (flag_code == CODE_64BIT)
4785 /* 64bit mode overwrites the 32bit absolute
4786 addressing by RIP relative addressing and
4787 absolute addressing is encoded by one of the
4788 redundant SIB forms. */
4789 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4790 i.sib.base = NO_BASE_REGISTER;
4791 i.sib.index = NO_INDEX_REGISTER;
4792 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4793 ? disp32s : disp32);
4795 else if ((flag_code == CODE_16BIT)
4796 ^ (i.prefix[ADDR_PREFIX] != 0))
4798 i.rm.regmem = NO_BASE_REGISTER_16;
4799 i.types[op] = disp16;
4803 i.rm.regmem = NO_BASE_REGISTER;
4804 i.types[op] = disp32;
4807 else /* !i.base_reg && i.index_reg */
4809 if (i.index_reg->reg_num == RegEiz
4810 || i.index_reg->reg_num == RegRiz)
4811 i.sib.index = NO_INDEX_REGISTER;
4813 i.sib.index = i.index_reg->reg_num;
4814 i.sib.base = NO_BASE_REGISTER;
4815 i.sib.scale = i.log2_scale_factor;
4816 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4817 i.types[op].bitfield.disp8 = 0;
4818 i.types[op].bitfield.disp16 = 0;
4819 i.types[op].bitfield.disp64 = 0;
4820 if (flag_code != CODE_64BIT)
4822 /* Must be 32 bit */
4823 i.types[op].bitfield.disp32 = 1;
4824 i.types[op].bitfield.disp32s = 0;
4828 i.types[op].bitfield.disp32 = 0;
4829 i.types[op].bitfield.disp32s = 1;
4831 if ((i.index_reg->reg_flags & RegRex) != 0)
4835 /* RIP addressing for 64bit mode. */
4836 else if (i.base_reg->reg_num == RegRip ||
4837 i.base_reg->reg_num == RegEip)
4839 i.rm.regmem = NO_BASE_REGISTER;
4840 i.types[op].bitfield.disp8 = 0;
4841 i.types[op].bitfield.disp16 = 0;
4842 i.types[op].bitfield.disp32 = 0;
4843 i.types[op].bitfield.disp32s = 1;
4844 i.types[op].bitfield.disp64 = 0;
4845 i.flags[op] |= Operand_PCrel;
4846 if (! i.disp_operands)
4847 fake_zero_displacement = 1;
4849 else if (i.base_reg->reg_type.bitfield.reg16)
4851 switch (i.base_reg->reg_num)
4854 if (i.index_reg == 0)
4856 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4857 i.rm.regmem = i.index_reg->reg_num - 6;
4861 if (i.index_reg == 0)
4864 if (operand_type_check (i.types[op], disp) == 0)
4866 /* fake (%bp) into 0(%bp) */
4867 i.types[op].bitfield.disp8 = 1;
4868 fake_zero_displacement = 1;
4871 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4872 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4874 default: /* (%si) -> 4 or (%di) -> 5 */
4875 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4877 i.rm.mode = mode_from_disp_size (i.types[op]);
4879 else /* i.base_reg and 32/64 bit mode */
4881 if (flag_code == CODE_64BIT
4882 && operand_type_check (i.types[op], disp))
4884 i386_operand_type temp;
4885 operand_type_set (&temp, 0);
4886 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4888 if (i.prefix[ADDR_PREFIX] == 0)
4889 i.types[op].bitfield.disp32s = 1;
4891 i.types[op].bitfield.disp32 = 1;
4894 i.rm.regmem = i.base_reg->reg_num;
4895 if ((i.base_reg->reg_flags & RegRex) != 0)
4897 i.sib.base = i.base_reg->reg_num;
4898 /* x86-64 ignores REX prefix bit here to avoid decoder
4900 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4903 if (i.disp_operands == 0)
4905 fake_zero_displacement = 1;
4906 i.types[op].bitfield.disp8 = 1;
4909 else if (i.base_reg->reg_num == ESP_REG_NUM)
4913 i.sib.scale = i.log2_scale_factor;
4914 if (i.index_reg == 0)
4916 /* <disp>(%esp) becomes two byte modrm with no index
4917 register. We've already stored the code for esp
4918 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4919 Any base register besides %esp will not use the
4920 extra modrm byte. */
4921 i.sib.index = NO_INDEX_REGISTER;
4925 if (i.index_reg->reg_num == RegEiz
4926 || i.index_reg->reg_num == RegRiz)
4927 i.sib.index = NO_INDEX_REGISTER;
4929 i.sib.index = i.index_reg->reg_num;
4930 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4931 if ((i.index_reg->reg_flags & RegRex) != 0)
4936 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4937 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4940 i.rm.mode = mode_from_disp_size (i.types[op]);
4943 if (fake_zero_displacement)
4945 /* Fakes a zero displacement assuming that i.types[op]
4946 holds the correct displacement size. */
4949 assert (i.op[op].disps == 0);
4950 exp = &disp_expressions[i.disp_operands++];
4951 i.op[op].disps = exp;
4952 exp->X_op = O_constant;
4953 exp->X_add_number = 0;
4954 exp->X_add_symbol = (symbolS *) 0;
4955 exp->X_op_symbol = (symbolS *) 0;
4959 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4960 (if any) based on i.tm.extension_opcode. Again, we must be
4961 careful to make sure that segment/control/debug/test/MMX
4962 registers are coded into the i.rm.reg field. */
4967 /* This has been precalculated for SSE5 instructions
4968 that have a DREX field earlier in process_drex. */
4969 if (i.tm.opcode_modifier.drex
4970 || i.tm.opcode_modifier.drexv
4971 || i.tm.opcode_modifier.drexc)
4973 op = i.drex.modrm_reg;
4974 i.rm.reg = i.op[op].regs->reg_num;
4975 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4980 for (op = 0; op < i.operands; op++)
4981 if (i.types[op].bitfield.reg8
4982 || i.types[op].bitfield.reg16
4983 || i.types[op].bitfield.reg32
4984 || i.types[op].bitfield.reg64
4985 || i.types[op].bitfield.regmmx
4986 || i.types[op].bitfield.regxmm
4987 || i.types[op].bitfield.sreg2
4988 || i.types[op].bitfield.sreg3
4989 || i.types[op].bitfield.control
4990 || i.types[op].bitfield.debug
4991 || i.types[op].bitfield.test)
4994 assert (op < i.operands);
4996 /* If there is an extension opcode to put here, the
4997 register number must be put into the regmem field. */
4998 if (i.tm.extension_opcode != None)
5000 i.rm.regmem = i.op[op].regs->reg_num;
5001 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5006 i.rm.reg = i.op[op].regs->reg_num;
5007 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5012 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5013 must set it to 3 to indicate this is a register operand
5014 in the regmem field. */
5015 if (!i.mem_operands)
5019 /* Fill in i.rm.reg field with extension opcode (if any). */
5020 if (i.tm.extension_opcode != None
5021 && !(i.tm.opcode_modifier.drex
5022 || i.tm.opcode_modifier.drexv
5023 || i.tm.opcode_modifier.drexc))
5024 i.rm.reg = i.tm.extension_opcode;
5030 output_branch (void)
5035 relax_substateT subtype;
5040 if (flag_code == CODE_16BIT)
5044 if (i.prefix[DATA_PREFIX] != 0)
5050 /* Pentium4 branch hints. */
5051 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5052 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5057 if (i.prefix[REX_PREFIX] != 0)
5063 if (i.prefixes != 0 && !intel_syntax)
5064 as_warn (_("skipping prefixes on this instruction"));
5066 /* It's always a symbol; End frag & setup for relax.
5067 Make sure there is enough room in this frag for the largest
5068 instruction we may generate in md_convert_frag. This is 2
5069 bytes for the opcode and room for the prefix and largest
5071 frag_grow (prefix + 2 + 4);
5072 /* Prefix and 1 opcode byte go in fr_fix. */
5073 p = frag_more (prefix + 1);
5074 if (i.prefix[DATA_PREFIX] != 0)
5075 *p++ = DATA_PREFIX_OPCODE;
5076 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5077 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5078 *p++ = i.prefix[SEG_PREFIX];
5079 if (i.prefix[REX_PREFIX] != 0)
5080 *p++ = i.prefix[REX_PREFIX];
5081 *p = i.tm.base_opcode;
5083 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5084 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5085 else if (cpu_arch_flags.bitfield.cpui386)
5086 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5088 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5091 sym = i.op[0].disps->X_add_symbol;
5092 off = i.op[0].disps->X_add_number;
5094 if (i.op[0].disps->X_op != O_constant
5095 && i.op[0].disps->X_op != O_symbol)
5097 /* Handle complex expressions. */
5098 sym = make_expr_symbol (i.op[0].disps);
5102 /* 1 possible extra opcode + 4 byte displacement go in var part.
5103 Pass reloc in fr_var. */
5104 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5114 if (i.tm.opcode_modifier.jumpbyte)
5116 /* This is a loop or jecxz type instruction. */
5118 if (i.prefix[ADDR_PREFIX] != 0)
5120 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5123 /* Pentium4 branch hints. */
5124 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5125 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5127 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5136 if (flag_code == CODE_16BIT)
5139 if (i.prefix[DATA_PREFIX] != 0)
5141 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5151 if (i.prefix[REX_PREFIX] != 0)
5153 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5157 if (i.prefixes != 0 && !intel_syntax)
5158 as_warn (_("skipping prefixes on this instruction"));
5160 p = frag_more (1 + size);
5161 *p++ = i.tm.base_opcode;
5163 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5164 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5166 /* All jumps handled here are signed, but don't use a signed limit
5167 check for 32 and 16 bit jumps as we want to allow wrap around at
5168 4G and 64k respectively. */
5170 fixP->fx_signed = 1;
5174 output_interseg_jump (void)
5182 if (flag_code == CODE_16BIT)
5186 if (i.prefix[DATA_PREFIX] != 0)
5192 if (i.prefix[REX_PREFIX] != 0)
5202 if (i.prefixes != 0 && !intel_syntax)
5203 as_warn (_("skipping prefixes on this instruction"));
5205 /* 1 opcode; 2 segment; offset */
5206 p = frag_more (prefix + 1 + 2 + size);
5208 if (i.prefix[DATA_PREFIX] != 0)
5209 *p++ = DATA_PREFIX_OPCODE;
5211 if (i.prefix[REX_PREFIX] != 0)
5212 *p++ = i.prefix[REX_PREFIX];
5214 *p++ = i.tm.base_opcode;
5215 if (i.op[1].imms->X_op == O_constant)
5217 offsetT n = i.op[1].imms->X_add_number;
5220 && !fits_in_unsigned_word (n)
5221 && !fits_in_signed_word (n))
5223 as_bad (_("16-bit jump out of range"));
5226 md_number_to_chars (p, n, size);
5229 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5230 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5231 if (i.op[0].imms->X_op != O_constant)
5232 as_bad (_("can't handle non absolute segment in `%s'"),
5234 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5240 fragS *insn_start_frag;
5241 offsetT insn_start_off;
5243 /* Tie dwarf2 debug info to the address at the start of the insn.
5244 We can't do this after the insn has been output as the current
5245 frag may have been closed off. eg. by frag_var. */
5246 dwarf2_emit_insn (0);
5248 insn_start_frag = frag_now;
5249 insn_start_off = frag_now_fix ();
5252 if (i.tm.opcode_modifier.jump)
5254 else if (i.tm.opcode_modifier.jumpbyte
5255 || i.tm.opcode_modifier.jumpdword)
5257 else if (i.tm.opcode_modifier.jumpintersegment)
5258 output_interseg_jump ();
5261 /* Output normal instructions here. */
5265 unsigned int prefix;
5267 switch (i.tm.opcode_length)
5270 if (i.tm.base_opcode & 0xff000000)
5272 prefix = (i.tm.base_opcode >> 24) & 0xff;
5277 if ((i.tm.base_opcode & 0xff0000) != 0)
5279 prefix = (i.tm.base_opcode >> 16) & 0xff;
5280 if (i.tm.cpu_flags.bitfield.cpupadlock)
5283 if (prefix != REPE_PREFIX_OPCODE
5284 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5285 add_prefix (prefix);
5288 add_prefix (prefix);
5297 /* The prefix bytes. */
5298 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5300 FRAG_APPEND_1_CHAR (*q);
5302 /* Now the opcode; be careful about word order here! */
5303 if (i.tm.opcode_length == 1)
5305 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5309 switch (i.tm.opcode_length)
5313 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5323 /* Put out high byte first: can't use md_number_to_chars! */
5324 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5325 *p = i.tm.base_opcode & 0xff;
5327 /* On SSE5, encode the OC1 bit in the DREX field if this
5328 encoding has multiple formats. */
5329 if (i.tm.opcode_modifier.drex
5330 && i.tm.opcode_modifier.drexv
5331 && DREX_OC1 (i.tm.extension_opcode))
5332 *p |= DREX_OC1_MASK;
5335 /* Now the modrm byte and sib byte (if present). */
5336 if (i.tm.opcode_modifier.modrm)
5338 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5341 /* If i.rm.regmem == ESP (4)
5342 && i.rm.mode != (Register mode)
5344 ==> need second modrm byte. */
5345 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5347 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5348 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5350 | i.sib.scale << 6));
5353 /* Write the DREX byte if needed. */
5354 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5357 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5359 /* Encode the OC0 bit if this encoding has multiple
5361 if ((i.tm.opcode_modifier.drex
5362 || i.tm.opcode_modifier.drexv)
5363 && DREX_OC0 (i.tm.extension_opcode))
5364 *p |= DREX_OC0_MASK;
5367 if (i.disp_operands)
5368 output_disp (insn_start_frag, insn_start_off);
5371 output_imm (insn_start_frag, insn_start_off);
5377 pi ("" /*line*/, &i);
5379 #endif /* DEBUG386 */
5382 /* Return the size of the displacement operand N. */
5385 disp_size (unsigned int n)
5388 if (i.types[n].bitfield.disp64)
5390 else if (i.types[n].bitfield.disp8)
5392 else if (i.types[n].bitfield.disp16)
5397 /* Return the size of the immediate operand N. */
5400 imm_size (unsigned int n)
5403 if (i.types[n].bitfield.imm64)
5405 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5407 else if (i.types[n].bitfield.imm16)
5413 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5418 for (n = 0; n < i.operands; n++)
5420 if (operand_type_check (i.types[n], disp))
5422 if (i.op[n].disps->X_op == O_constant)
5424 int size = disp_size (n);
5427 val = offset_in_range (i.op[n].disps->X_add_number,
5429 p = frag_more (size);
5430 md_number_to_chars (p, val, size);
5434 enum bfd_reloc_code_real reloc_type;
5435 int size = disp_size (n);
5436 int sign = i.types[n].bitfield.disp32s;
5437 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5439 /* We can't have 8 bit displacement here. */
5440 assert (!i.types[n].bitfield.disp8);
5442 /* The PC relative address is computed relative
5443 to the instruction boundary, so in case immediate
5444 fields follows, we need to adjust the value. */
5445 if (pcrel && i.imm_operands)
5450 for (n1 = 0; n1 < i.operands; n1++)
5451 if (operand_type_check (i.types[n1], imm))
5453 /* Only one immediate is allowed for PC
5454 relative address. */
5457 i.op[n].disps->X_add_number -= sz;
5459 /* We should find the immediate. */
5463 p = frag_more (size);
5464 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5466 && GOT_symbol == i.op[n].disps->X_add_symbol
5467 && (((reloc_type == BFD_RELOC_32
5468 || reloc_type == BFD_RELOC_X86_64_32S
5469 || (reloc_type == BFD_RELOC_64
5471 && (i.op[n].disps->X_op == O_symbol
5472 || (i.op[n].disps->X_op == O_add
5473 && ((symbol_get_value_expression
5474 (i.op[n].disps->X_op_symbol)->X_op)
5476 || reloc_type == BFD_RELOC_32_PCREL))
5480 if (insn_start_frag == frag_now)
5481 add = (p - frag_now->fr_literal) - insn_start_off;
5486 add = insn_start_frag->fr_fix - insn_start_off;
5487 for (fr = insn_start_frag->fr_next;
5488 fr && fr != frag_now; fr = fr->fr_next)
5490 add += p - frag_now->fr_literal;
5495 reloc_type = BFD_RELOC_386_GOTPC;
5496 i.op[n].imms->X_add_number += add;
5498 else if (reloc_type == BFD_RELOC_64)
5499 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5501 /* Don't do the adjustment for x86-64, as there
5502 the pcrel addressing is relative to the _next_
5503 insn, and that is taken care of in other code. */
5504 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5506 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5507 i.op[n].disps, pcrel, reloc_type);
5514 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5519 for (n = 0; n < i.operands; n++)
5521 if (operand_type_check (i.types[n], imm))
5523 if (i.op[n].imms->X_op == O_constant)
5525 int size = imm_size (n);
5528 val = offset_in_range (i.op[n].imms->X_add_number,
5530 p = frag_more (size);
5531 md_number_to_chars (p, val, size);
5535 /* Not absolute_section.
5536 Need a 32-bit fixup (don't support 8bit
5537 non-absolute imms). Try to support other
5539 enum bfd_reloc_code_real reloc_type;
5540 int size = imm_size (n);
5543 if (i.types[n].bitfield.imm32s
5544 && (i.suffix == QWORD_MNEM_SUFFIX
5545 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5550 p = frag_more (size);
5551 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5553 /* This is tough to explain. We end up with this one if we
5554 * have operands that look like
5555 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5556 * obtain the absolute address of the GOT, and it is strongly
5557 * preferable from a performance point of view to avoid using
5558 * a runtime relocation for this. The actual sequence of
5559 * instructions often look something like:
5564 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5566 * The call and pop essentially return the absolute address
5567 * of the label .L66 and store it in %ebx. The linker itself
5568 * will ultimately change the first operand of the addl so
5569 * that %ebx points to the GOT, but to keep things simple, the
5570 * .o file must have this operand set so that it generates not
5571 * the absolute address of .L66, but the absolute address of
5572 * itself. This allows the linker itself simply treat a GOTPC
5573 * relocation as asking for a pcrel offset to the GOT to be
5574 * added in, and the addend of the relocation is stored in the
5575 * operand field for the instruction itself.
5577 * Our job here is to fix the operand so that it would add
5578 * the correct offset so that %ebx would point to itself. The
5579 * thing that is tricky is that .-.L66 will point to the
5580 * beginning of the instruction, so we need to further modify
5581 * the operand so that it will point to itself. There are
5582 * other cases where you have something like:
5584 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5586 * and here no correction would be required. Internally in
5587 * the assembler we treat operands of this form as not being
5588 * pcrel since the '.' is explicitly mentioned, and I wonder
5589 * whether it would simplify matters to do it this way. Who
5590 * knows. In earlier versions of the PIC patches, the
5591 * pcrel_adjust field was used to store the correction, but
5592 * since the expression is not pcrel, I felt it would be
5593 * confusing to do it this way. */
5595 if ((reloc_type == BFD_RELOC_32
5596 || reloc_type == BFD_RELOC_X86_64_32S
5597 || reloc_type == BFD_RELOC_64)
5599 && GOT_symbol == i.op[n].imms->X_add_symbol
5600 && (i.op[n].imms->X_op == O_symbol
5601 || (i.op[n].imms->X_op == O_add
5602 && ((symbol_get_value_expression
5603 (i.op[n].imms->X_op_symbol)->X_op)
5608 if (insn_start_frag == frag_now)
5609 add = (p - frag_now->fr_literal) - insn_start_off;
5614 add = insn_start_frag->fr_fix - insn_start_off;
5615 for (fr = insn_start_frag->fr_next;
5616 fr && fr != frag_now; fr = fr->fr_next)
5618 add += p - frag_now->fr_literal;
5622 reloc_type = BFD_RELOC_386_GOTPC;
5624 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5626 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5627 i.op[n].imms->X_add_number += add;
5629 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5630 i.op[n].imms, 0, reloc_type);
5636 /* x86_cons_fix_new is called via the expression parsing code when a
5637 reloc is needed. We use this hook to get the correct .got reloc. */
5638 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5639 static int cons_sign = -1;
5642 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5645 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5647 got_reloc = NO_RELOC;
5650 if (exp->X_op == O_secrel)
5652 exp->X_op = O_symbol;
5653 r = BFD_RELOC_32_SECREL;
5657 fix_new_exp (frag, off, len, exp, 0, r);
5660 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5661 # define lex_got(reloc, adjust, types) NULL
5663 /* Parse operands of the form
5664 <symbol>@GOTOFF+<nnn>
5665 and similar .plt or .got references.
5667 If we find one, set up the correct relocation in RELOC and copy the
5668 input string, minus the `@GOTOFF' into a malloc'd buffer for
5669 parsing by the calling routine. Return this buffer, and if ADJUST
5670 is non-null set it to the length of the string we removed from the
5671 input line. Otherwise return NULL. */
5673 lex_got (enum bfd_reloc_code_real *reloc,
5675 i386_operand_type *types)
5677 /* Some of the relocations depend on the size of what field is to
5678 be relocated. But in our callers i386_immediate and i386_displacement
5679 we don't yet know the operand size (this will be set by insn
5680 matching). Hence we record the word32 relocation here,
5681 and adjust the reloc according to the real size in reloc(). */
5682 static const struct {
5684 const enum bfd_reloc_code_real rel[2];
5685 const i386_operand_type types64;
5688 BFD_RELOC_X86_64_PLTOFF64 },
5689 OPERAND_TYPE_IMM64 },
5690 { "PLT", { BFD_RELOC_386_PLT32,
5691 BFD_RELOC_X86_64_PLT32 },
5692 OPERAND_TYPE_IMM32_32S_DISP32 },
5694 BFD_RELOC_X86_64_GOTPLT64 },
5695 OPERAND_TYPE_IMM64_DISP64 },
5696 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5697 BFD_RELOC_X86_64_GOTOFF64 },
5698 OPERAND_TYPE_IMM64_DISP64 },
5700 BFD_RELOC_X86_64_GOTPCREL },
5701 OPERAND_TYPE_IMM32_32S_DISP32 },
5702 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5703 BFD_RELOC_X86_64_TLSGD },
5704 OPERAND_TYPE_IMM32_32S_DISP32 },
5705 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5707 OPERAND_TYPE_NONE },
5709 BFD_RELOC_X86_64_TLSLD },
5710 OPERAND_TYPE_IMM32_32S_DISP32 },
5711 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5712 BFD_RELOC_X86_64_GOTTPOFF },
5713 OPERAND_TYPE_IMM32_32S_DISP32 },
5714 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5715 BFD_RELOC_X86_64_TPOFF32 },
5716 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5717 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5719 OPERAND_TYPE_NONE },
5720 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5721 BFD_RELOC_X86_64_DTPOFF32 },
5723 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5724 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5726 OPERAND_TYPE_NONE },
5727 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5729 OPERAND_TYPE_NONE },
5730 { "GOT", { BFD_RELOC_386_GOT32,
5731 BFD_RELOC_X86_64_GOT32 },
5732 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5733 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5734 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5735 OPERAND_TYPE_IMM32_32S_DISP32 },
5736 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5737 BFD_RELOC_X86_64_TLSDESC_CALL },
5738 OPERAND_TYPE_IMM32_32S_DISP32 },
5746 for (cp = input_line_pointer; *cp != '@'; cp++)
5747 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5750 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5754 len = strlen (gotrel[j].str);
5755 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5757 if (gotrel[j].rel[object_64bit] != 0)
5760 char *tmpbuf, *past_reloc;
5762 *reloc = gotrel[j].rel[object_64bit];
5768 if (flag_code != CODE_64BIT)
5770 types->bitfield.imm32 = 1;
5771 types->bitfield.disp32 = 1;
5774 *types = gotrel[j].types64;
5777 if (GOT_symbol == NULL)
5778 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5780 /* The length of the first part of our input line. */
5781 first = cp - input_line_pointer;
5783 /* The second part goes from after the reloc token until
5784 (and including) an end_of_line char or comma. */
5785 past_reloc = cp + 1 + len;
5787 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5789 second = cp + 1 - past_reloc;
5791 /* Allocate and copy string. The trailing NUL shouldn't
5792 be necessary, but be safe. */
5793 tmpbuf = xmalloc (first + second + 2);
5794 memcpy (tmpbuf, input_line_pointer, first);
5795 if (second != 0 && *past_reloc != ' ')
5796 /* Replace the relocation token with ' ', so that
5797 errors like foo@GOTOFF1 will be detected. */
5798 tmpbuf[first++] = ' ';
5799 memcpy (tmpbuf + first, past_reloc, second);
5800 tmpbuf[first + second] = '\0';
5804 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5805 gotrel[j].str, 1 << (5 + object_64bit));
5810 /* Might be a symbol version string. Don't as_bad here. */
5815 x86_cons (expressionS *exp, int size)
5817 if (size == 4 || (object_64bit && size == 8))
5819 /* Handle @GOTOFF and the like in an expression. */
5821 char *gotfree_input_line;
5824 save = input_line_pointer;
5825 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5826 if (gotfree_input_line)
5827 input_line_pointer = gotfree_input_line;
5831 if (gotfree_input_line)
5833 /* expression () has merrily parsed up to the end of line,
5834 or a comma - in the wrong buffer. Transfer how far
5835 input_line_pointer has moved to the right buffer. */
5836 input_line_pointer = (save
5837 + (input_line_pointer - gotfree_input_line)
5839 free (gotfree_input_line);
5840 if (exp->X_op == O_constant
5841 || exp->X_op == O_absent
5842 || exp->X_op == O_illegal
5843 || exp->X_op == O_register
5844 || exp->X_op == O_big)
5846 char c = *input_line_pointer;
5847 *input_line_pointer = 0;
5848 as_bad (_("missing or invalid expression `%s'"), save);
5849 *input_line_pointer = c;
5858 static void signed_cons (int size)
5860 if (flag_code == CODE_64BIT)
5868 pe_directive_secrel (dummy)
5869 int dummy ATTRIBUTE_UNUSED;
5876 if (exp.X_op == O_symbol)
5877 exp.X_op = O_secrel;
5879 emit_expr (&exp, 4);
5881 while (*input_line_pointer++ == ',');
5883 input_line_pointer--;
5884 demand_empty_rest_of_line ();
5889 i386_immediate (char *imm_start)
5891 char *save_input_line_pointer;
5892 char *gotfree_input_line;
5895 i386_operand_type types;
5897 operand_type_set (&types, ~0);
5899 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5901 as_bad (_("at most %d immediate operands are allowed"),
5902 MAX_IMMEDIATE_OPERANDS);
5906 exp = &im_expressions[i.imm_operands++];
5907 i.op[this_operand].imms = exp;
5909 if (is_space_char (*imm_start))
5912 save_input_line_pointer = input_line_pointer;
5913 input_line_pointer = imm_start;
5915 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5916 if (gotfree_input_line)
5917 input_line_pointer = gotfree_input_line;
5919 exp_seg = expression (exp);
5922 if (*input_line_pointer)
5923 as_bad (_("junk `%s' after expression"), input_line_pointer);
5925 input_line_pointer = save_input_line_pointer;
5926 if (gotfree_input_line)
5927 free (gotfree_input_line);
5929 if (exp->X_op == O_absent
5930 || exp->X_op == O_illegal
5931 || exp->X_op == O_big
5932 || (gotfree_input_line
5933 && (exp->X_op == O_constant
5934 || exp->X_op == O_register)))
5936 as_bad (_("missing or invalid immediate expression `%s'"),
5940 else if (exp->X_op == O_constant)
5942 /* Size it properly later. */
5943 i.types[this_operand].bitfield.imm64 = 1;
5944 /* If BFD64, sign extend val. */
5945 if (!use_rela_relocations
5946 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5948 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5950 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5951 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5952 && exp_seg != absolute_section
5953 && exp_seg != text_section
5954 && exp_seg != data_section
5955 && exp_seg != bss_section
5956 && exp_seg != undefined_section
5957 && !bfd_is_com_section (exp_seg))
5959 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5963 else if (!intel_syntax && exp->X_op == O_register)
5965 as_bad (_("illegal immediate register operand %s"), imm_start);
5970 /* This is an address. The size of the address will be
5971 determined later, depending on destination register,
5972 suffix, or the default for the section. */
5973 i.types[this_operand].bitfield.imm8 = 1;
5974 i.types[this_operand].bitfield.imm16 = 1;
5975 i.types[this_operand].bitfield.imm32 = 1;
5976 i.types[this_operand].bitfield.imm32s = 1;
5977 i.types[this_operand].bitfield.imm64 = 1;
5978 i.types[this_operand] = operand_type_and (i.types[this_operand],
5986 i386_scale (char *scale)
5989 char *save = input_line_pointer;
5991 input_line_pointer = scale;
5992 val = get_absolute_expression ();
5997 i.log2_scale_factor = 0;
6000 i.log2_scale_factor = 1;
6003 i.log2_scale_factor = 2;
6006 i.log2_scale_factor = 3;
6010 char sep = *input_line_pointer;
6012 *input_line_pointer = '\0';
6013 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6015 *input_line_pointer = sep;
6016 input_line_pointer = save;
6020 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6022 as_warn (_("scale factor of %d without an index register"),
6023 1 << i.log2_scale_factor);
6024 i.log2_scale_factor = 0;
6026 scale = input_line_pointer;
6027 input_line_pointer = save;
6032 i386_displacement (char *disp_start, char *disp_end)
6036 char *save_input_line_pointer;
6037 char *gotfree_input_line;
6039 i386_operand_type bigdisp, types = anydisp;
6042 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6044 as_bad (_("at most %d displacement operands are allowed"),
6045 MAX_MEMORY_OPERANDS);
6049 operand_type_set (&bigdisp, 0);
6050 if ((i.types[this_operand].bitfield.jumpabsolute)
6051 || (!current_templates->start->opcode_modifier.jump
6052 && !current_templates->start->opcode_modifier.jumpdword))
6054 bigdisp.bitfield.disp32 = 1;
6055 override = (i.prefix[ADDR_PREFIX] != 0);
6056 if (flag_code == CODE_64BIT)
6060 bigdisp.bitfield.disp32s = 1;
6061 bigdisp.bitfield.disp64 = 1;
6064 else if ((flag_code == CODE_16BIT) ^ override)
6066 bigdisp.bitfield.disp32 = 0;
6067 bigdisp.bitfield.disp16 = 1;
6072 /* For PC-relative branches, the width of the displacement
6073 is dependent upon data size, not address size. */
6074 override = (i.prefix[DATA_PREFIX] != 0);
6075 if (flag_code == CODE_64BIT)
6077 if (override || i.suffix == WORD_MNEM_SUFFIX)
6078 bigdisp.bitfield.disp16 = 1;
6081 bigdisp.bitfield.disp32 = 1;
6082 bigdisp.bitfield.disp32s = 1;
6088 override = (i.suffix == (flag_code != CODE_16BIT
6090 : LONG_MNEM_SUFFIX));
6091 bigdisp.bitfield.disp32 = 1;
6092 if ((flag_code == CODE_16BIT) ^ override)
6094 bigdisp.bitfield.disp32 = 0;
6095 bigdisp.bitfield.disp16 = 1;
6099 i.types[this_operand] = operand_type_or (i.types[this_operand],
6102 exp = &disp_expressions[i.disp_operands];
6103 i.op[this_operand].disps = exp;
6105 save_input_line_pointer = input_line_pointer;
6106 input_line_pointer = disp_start;
6107 END_STRING_AND_SAVE (disp_end);
6109 #ifndef GCC_ASM_O_HACK
6110 #define GCC_ASM_O_HACK 0
6113 END_STRING_AND_SAVE (disp_end + 1);
6114 if (i.types[this_operand].bitfield.baseIndex
6115 && displacement_string_end[-1] == '+')
6117 /* This hack is to avoid a warning when using the "o"
6118 constraint within gcc asm statements.
6121 #define _set_tssldt_desc(n,addr,limit,type) \
6122 __asm__ __volatile__ ( \
6124 "movw %w1,2+%0\n\t" \
6126 "movb %b1,4+%0\n\t" \
6127 "movb %4,5+%0\n\t" \
6128 "movb $0,6+%0\n\t" \
6129 "movb %h1,7+%0\n\t" \
6131 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6133 This works great except that the output assembler ends
6134 up looking a bit weird if it turns out that there is
6135 no offset. You end up producing code that looks like:
6148 So here we provide the missing zero. */
6150 *displacement_string_end = '0';
6153 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6154 if (gotfree_input_line)
6155 input_line_pointer = gotfree_input_line;
6157 exp_seg = expression (exp);
6160 if (*input_line_pointer)
6161 as_bad (_("junk `%s' after expression"), input_line_pointer);
6163 RESTORE_END_STRING (disp_end + 1);
6165 input_line_pointer = save_input_line_pointer;
6166 if (gotfree_input_line)
6167 free (gotfree_input_line);
6170 /* We do this to make sure that the section symbol is in
6171 the symbol table. We will ultimately change the relocation
6172 to be relative to the beginning of the section. */
6173 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6174 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6175 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6177 if (exp->X_op != O_symbol)
6180 if (S_IS_LOCAL (exp->X_add_symbol)
6181 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6182 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6183 exp->X_op = O_subtract;
6184 exp->X_op_symbol = GOT_symbol;
6185 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6186 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6187 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6188 i.reloc[this_operand] = BFD_RELOC_64;
6190 i.reloc[this_operand] = BFD_RELOC_32;
6193 else if (exp->X_op == O_absent
6194 || exp->X_op == O_illegal
6195 || exp->X_op == O_big
6196 || (gotfree_input_line
6197 && (exp->X_op == O_constant
6198 || exp->X_op == O_register)))
6201 as_bad (_("missing or invalid displacement expression `%s'"),
6206 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6207 else if (exp->X_op != O_constant
6208 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6209 && exp_seg != absolute_section
6210 && exp_seg != text_section
6211 && exp_seg != data_section
6212 && exp_seg != bss_section
6213 && exp_seg != undefined_section
6214 && !bfd_is_com_section (exp_seg))
6216 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6221 RESTORE_END_STRING (disp_end);
6223 /* Check if this is a displacement only operand. */
6224 bigdisp = i.types[this_operand];
6225 bigdisp.bitfield.disp8 = 0;
6226 bigdisp.bitfield.disp16 = 0;
6227 bigdisp.bitfield.disp32 = 0;
6228 bigdisp.bitfield.disp32s = 0;
6229 bigdisp.bitfield.disp64 = 0;
6230 if (operand_type_all_zero (&bigdisp))
6231 i.types[this_operand] = operand_type_and (i.types[this_operand],
6237 /* Make sure the memory operand we've been dealt is valid.
6238 Return 1 on success, 0 on a failure. */
6241 i386_index_check (const char *operand_string)
6244 #if INFER_ADDR_PREFIX
6250 if (flag_code == CODE_64BIT)
6253 && ((i.prefix[ADDR_PREFIX] == 0
6254 && !i.base_reg->reg_type.bitfield.reg64)
6255 || (i.prefix[ADDR_PREFIX]
6256 && !i.base_reg->reg_type.bitfield.reg32))
6258 || i.base_reg->reg_num !=
6259 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6261 && (!i.index_reg->reg_type.bitfield.baseindex
6262 || (i.prefix[ADDR_PREFIX] == 0
6263 && i.index_reg->reg_num != RegRiz
6264 && !i.index_reg->reg_type.bitfield.reg64
6266 || (i.prefix[ADDR_PREFIX]
6267 && i.index_reg->reg_num != RegEiz
6268 && !i.index_reg->reg_type.bitfield.reg32))))
6273 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6277 && (!i.base_reg->reg_type.bitfield.reg16
6278 || !i.base_reg->reg_type.bitfield.baseindex))
6280 && (!i.index_reg->reg_type.bitfield.reg16
6281 || !i.index_reg->reg_type.bitfield.baseindex
6283 && i.base_reg->reg_num < 6
6284 && i.index_reg->reg_num >= 6
6285 && i.log2_scale_factor == 0))))
6292 && !i.base_reg->reg_type.bitfield.reg32)
6294 && ((!i.index_reg->reg_type.bitfield.reg32
6295 && i.index_reg->reg_num != RegEiz)
6296 || !i.index_reg->reg_type.bitfield.baseindex)))
6302 #if INFER_ADDR_PREFIX
6303 if (i.prefix[ADDR_PREFIX] == 0)
6305 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6307 /* Change the size of any displacement too. At most one of
6308 Disp16 or Disp32 is set.
6309 FIXME. There doesn't seem to be any real need for separate
6310 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6311 Removing them would probably clean up the code quite a lot. */
6312 if (flag_code != CODE_64BIT
6313 && (i.types[this_operand].bitfield.disp16
6314 || i.types[this_operand].bitfield.disp32))
6315 i.types[this_operand]
6316 = operand_type_xor (i.types[this_operand], disp16_32);
6321 as_bad (_("`%s' is not a valid base/index expression"),
6325 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6327 flag_code_names[flag_code]);
6332 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6336 i386_att_operand (char *operand_string)
6340 char *op_string = operand_string;
6342 if (is_space_char (*op_string))
6345 /* We check for an absolute prefix (differentiating,
6346 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6347 if (*op_string == ABSOLUTE_PREFIX)
6350 if (is_space_char (*op_string))
6352 i.types[this_operand].bitfield.jumpabsolute = 1;
6355 /* Check if operand is a register. */
6356 if ((r = parse_register (op_string, &end_op)) != NULL)
6358 i386_operand_type temp;
6360 /* Check for a segment override by searching for ':' after a
6361 segment register. */
6363 if (is_space_char (*op_string))
6365 if (*op_string == ':'
6366 && (r->reg_type.bitfield.sreg2
6367 || r->reg_type.bitfield.sreg3))
6372 i.seg[i.mem_operands] = &es;
6375 i.seg[i.mem_operands] = &cs;
6378 i.seg[i.mem_operands] = &ss;
6381 i.seg[i.mem_operands] = &ds;
6384 i.seg[i.mem_operands] = &fs;
6387 i.seg[i.mem_operands] = &gs;
6391 /* Skip the ':' and whitespace. */
6393 if (is_space_char (*op_string))
6396 if (!is_digit_char (*op_string)
6397 && !is_identifier_char (*op_string)
6398 && *op_string != '('
6399 && *op_string != ABSOLUTE_PREFIX)
6401 as_bad (_("bad memory operand `%s'"), op_string);
6404 /* Handle case of %es:*foo. */
6405 if (*op_string == ABSOLUTE_PREFIX)
6408 if (is_space_char (*op_string))
6410 i.types[this_operand].bitfield.jumpabsolute = 1;
6412 goto do_memory_reference;
6416 as_bad (_("junk `%s' after register"), op_string);
6420 temp.bitfield.baseindex = 0;
6421 i.types[this_operand] = operand_type_or (i.types[this_operand],
6423 i.types[this_operand].bitfield.unspecified = 0;
6424 i.op[this_operand].regs = r;
6427 else if (*op_string == REGISTER_PREFIX)
6429 as_bad (_("bad register name `%s'"), op_string);
6432 else if (*op_string == IMMEDIATE_PREFIX)
6435 if (i.types[this_operand].bitfield.jumpabsolute)
6437 as_bad (_("immediate operand illegal with absolute jump"));
6440 if (!i386_immediate (op_string))
6443 else if (is_digit_char (*op_string)
6444 || is_identifier_char (*op_string)
6445 || *op_string == '(')
6447 /* This is a memory reference of some sort. */
6450 /* Start and end of displacement string expression (if found). */
6451 char *displacement_string_start;
6452 char *displacement_string_end;
6454 do_memory_reference:
6455 if ((i.mem_operands == 1
6456 && !current_templates->start->opcode_modifier.isstring)
6457 || i.mem_operands == 2)
6459 as_bad (_("too many memory references for `%s'"),
6460 current_templates->start->name);
6464 /* Check for base index form. We detect the base index form by
6465 looking for an ')' at the end of the operand, searching
6466 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6468 base_string = op_string + strlen (op_string);
6471 if (is_space_char (*base_string))
6474 /* If we only have a displacement, set-up for it to be parsed later. */
6475 displacement_string_start = op_string;
6476 displacement_string_end = base_string + 1;
6478 if (*base_string == ')')
6481 unsigned int parens_balanced = 1;
6482 /* We've already checked that the number of left & right ()'s are
6483 equal, so this loop will not be infinite. */
6487 if (*base_string == ')')
6489 if (*base_string == '(')
6492 while (parens_balanced);
6494 temp_string = base_string;
6496 /* Skip past '(' and whitespace. */
6498 if (is_space_char (*base_string))
6501 if (*base_string == ','
6502 || ((i.base_reg = parse_register (base_string, &end_op))
6505 displacement_string_end = temp_string;
6507 i.types[this_operand].bitfield.baseindex = 1;
6511 base_string = end_op;
6512 if (is_space_char (*base_string))
6516 /* There may be an index reg or scale factor here. */
6517 if (*base_string == ',')
6520 if (is_space_char (*base_string))
6523 if ((i.index_reg = parse_register (base_string, &end_op))
6526 base_string = end_op;
6527 if (is_space_char (*base_string))
6529 if (*base_string == ',')
6532 if (is_space_char (*base_string))
6535 else if (*base_string != ')')
6537 as_bad (_("expecting `,' or `)' "
6538 "after index register in `%s'"),
6543 else if (*base_string == REGISTER_PREFIX)
6545 as_bad (_("bad register name `%s'"), base_string);
6549 /* Check for scale factor. */
6550 if (*base_string != ')')
6552 char *end_scale = i386_scale (base_string);
6557 base_string = end_scale;
6558 if (is_space_char (*base_string))
6560 if (*base_string != ')')
6562 as_bad (_("expecting `)' "
6563 "after scale factor in `%s'"),
6568 else if (!i.index_reg)
6570 as_bad (_("expecting index register or scale factor "
6571 "after `,'; got '%c'"),
6576 else if (*base_string != ')')
6578 as_bad (_("expecting `,' or `)' "
6579 "after base register in `%s'"),
6584 else if (*base_string == REGISTER_PREFIX)
6586 as_bad (_("bad register name `%s'"), base_string);
6591 /* If there's an expression beginning the operand, parse it,
6592 assuming displacement_string_start and
6593 displacement_string_end are meaningful. */
6594 if (displacement_string_start != displacement_string_end)
6596 if (!i386_displacement (displacement_string_start,
6597 displacement_string_end))
6601 /* Special case for (%dx) while doing input/output op. */
6603 && operand_type_equal (&i.base_reg->reg_type,
6604 ®16_inoutportreg)
6606 && i.log2_scale_factor == 0
6607 && i.seg[i.mem_operands] == 0
6608 && !operand_type_check (i.types[this_operand], disp))
6610 i.types[this_operand] = inoutportreg;
6614 if (i386_index_check (operand_string) == 0)
6616 i.types[this_operand].bitfield.mem = 1;
6621 /* It's not a memory operand; argh! */
6622 as_bad (_("invalid char %s beginning operand %d `%s'"),
6623 output_invalid (*op_string),
6628 return 1; /* Normal return. */
6631 /* md_estimate_size_before_relax()
6633 Called just before relax() for rs_machine_dependent frags. The x86
6634 assembler uses these frags to handle variable size jump
6637 Any symbol that is now undefined will not become defined.
6638 Return the correct fr_subtype in the frag.
6639 Return the initial "guess for variable size of frag" to caller.
6640 The guess is actually the growth beyond the fixed part. Whatever
6641 we do to grow the fixed or variable part contributes to our
6645 md_estimate_size_before_relax (fragP, segment)
6649 /* We've already got fragP->fr_subtype right; all we have to do is
6650 check for un-relaxable symbols. On an ELF system, we can't relax
6651 an externally visible symbol, because it may be overridden by a
6653 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6656 && (S_IS_EXTERNAL (fragP->fr_symbol)
6657 || S_IS_WEAK (fragP->fr_symbol)))
6661 /* Symbol is undefined in this segment, or we need to keep a
6662 reloc so that weak symbols can be overridden. */
6663 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6664 enum bfd_reloc_code_real reloc_type;
6665 unsigned char *opcode;
6668 if (fragP->fr_var != NO_RELOC)
6669 reloc_type = fragP->fr_var;
6671 reloc_type = BFD_RELOC_16_PCREL;
6673 reloc_type = BFD_RELOC_32_PCREL;
6675 old_fr_fix = fragP->fr_fix;
6676 opcode = (unsigned char *) fragP->fr_opcode;
6678 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6681 /* Make jmp (0xeb) a (d)word displacement jump. */
6683 fragP->fr_fix += size;
6684 fix_new (fragP, old_fr_fix, size,
6686 fragP->fr_offset, 1,
6692 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6694 /* Negate the condition, and branch past an
6695 unconditional jump. */
6698 /* Insert an unconditional jump. */
6700 /* We added two extra opcode bytes, and have a two byte
6702 fragP->fr_fix += 2 + 2;
6703 fix_new (fragP, old_fr_fix + 2, 2,
6705 fragP->fr_offset, 1,
6712 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6717 fixP = fix_new (fragP, old_fr_fix, 1,
6719 fragP->fr_offset, 1,
6721 fixP->fx_signed = 1;
6725 /* This changes the byte-displacement jump 0x7N
6726 to the (d)word-displacement jump 0x0f,0x8N. */
6727 opcode[1] = opcode[0] + 0x10;
6728 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6729 /* We've added an opcode byte. */
6730 fragP->fr_fix += 1 + size;
6731 fix_new (fragP, old_fr_fix + 1, size,
6733 fragP->fr_offset, 1,
6738 BAD_CASE (fragP->fr_subtype);
6742 return fragP->fr_fix - old_fr_fix;
6745 /* Guess size depending on current relax state. Initially the relax
6746 state will correspond to a short jump and we return 1, because
6747 the variable part of the frag (the branch offset) is one byte
6748 long. However, we can relax a section more than once and in that
6749 case we must either set fr_subtype back to the unrelaxed state,
6750 or return the value for the appropriate branch. */
6751 return md_relax_table[fragP->fr_subtype].rlx_length;
6754 /* Called after relax() is finished.
6756 In: Address of frag.
6757 fr_type == rs_machine_dependent.
6758 fr_subtype is what the address relaxed to.
6760 Out: Any fixSs and constants are set up.
6761 Caller will turn frag into a ".space 0". */
6764 md_convert_frag (abfd, sec, fragP)
6765 bfd *abfd ATTRIBUTE_UNUSED;
6766 segT sec ATTRIBUTE_UNUSED;
6769 unsigned char *opcode;
6770 unsigned char *where_to_put_displacement = NULL;
6771 offsetT target_address;
6772 offsetT opcode_address;
6773 unsigned int extension = 0;
6774 offsetT displacement_from_opcode_start;
6776 opcode = (unsigned char *) fragP->fr_opcode;
6778 /* Address we want to reach in file space. */
6779 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6781 /* Address opcode resides at in file space. */
6782 opcode_address = fragP->fr_address + fragP->fr_fix;
6784 /* Displacement from opcode start to fill into instruction. */
6785 displacement_from_opcode_start = target_address - opcode_address;
6787 if ((fragP->fr_subtype & BIG) == 0)
6789 /* Don't have to change opcode. */
6790 extension = 1; /* 1 opcode + 1 displacement */
6791 where_to_put_displacement = &opcode[1];
6795 if (no_cond_jump_promotion
6796 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6797 as_warn_where (fragP->fr_file, fragP->fr_line,
6798 _("long jump required"));
6800 switch (fragP->fr_subtype)
6802 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6803 extension = 4; /* 1 opcode + 4 displacement */
6805 where_to_put_displacement = &opcode[1];
6808 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6809 extension = 2; /* 1 opcode + 2 displacement */
6811 where_to_put_displacement = &opcode[1];
6814 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6815 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6816 extension = 5; /* 2 opcode + 4 displacement */
6817 opcode[1] = opcode[0] + 0x10;
6818 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6819 where_to_put_displacement = &opcode[2];
6822 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6823 extension = 3; /* 2 opcode + 2 displacement */
6824 opcode[1] = opcode[0] + 0x10;
6825 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6826 where_to_put_displacement = &opcode[2];
6829 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6834 where_to_put_displacement = &opcode[3];
6838 BAD_CASE (fragP->fr_subtype);
6843 /* If size if less then four we are sure that the operand fits,
6844 but if it's 4, then it could be that the displacement is larger
6846 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6848 && ((addressT) (displacement_from_opcode_start - extension
6849 + ((addressT) 1 << 31))
6850 > (((addressT) 2 << 31) - 1)))
6852 as_bad_where (fragP->fr_file, fragP->fr_line,
6853 _("jump target out of range"));
6854 /* Make us emit 0. */
6855 displacement_from_opcode_start = extension;
6857 /* Now put displacement after opcode. */
6858 md_number_to_chars ((char *) where_to_put_displacement,
6859 (valueT) (displacement_from_opcode_start - extension),
6860 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6861 fragP->fr_fix += extension;
6864 /* Apply a fixup (fixS) to segment data, once it has been determined
6865 by our caller that we have all the info we need to fix it up.
6867 On the 386, immediates, displacements, and data pointers are all in
6868 the same (little-endian) format, so we don't need to care about which
6872 md_apply_fix (fixP, valP, seg)
6873 /* The fix we're to put in. */
6875 /* Pointer to the value of the bits. */
6877 /* Segment fix is from. */
6878 segT seg ATTRIBUTE_UNUSED;
6880 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6881 valueT value = *valP;
6883 #if !defined (TE_Mach)
6886 switch (fixP->fx_r_type)
6892 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6895 case BFD_RELOC_X86_64_32S:
6896 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6899 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6902 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6907 if (fixP->fx_addsy != NULL
6908 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6909 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6910 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6911 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6912 && !use_rela_relocations)
6914 /* This is a hack. There should be a better way to handle this.
6915 This covers for the fact that bfd_install_relocation will
6916 subtract the current location (for partial_inplace, PC relative
6917 relocations); see more below. */
6921 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6924 value += fixP->fx_where + fixP->fx_frag->fr_address;
6926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6929 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6932 || (symbol_section_p (fixP->fx_addsy)
6933 && sym_seg != absolute_section))
6934 && !generic_force_reloc (fixP))
6936 /* Yes, we add the values in twice. This is because
6937 bfd_install_relocation subtracts them out again. I think
6938 bfd_install_relocation is broken, but I don't dare change
6940 value += fixP->fx_where + fixP->fx_frag->fr_address;
6944 #if defined (OBJ_COFF) && defined (TE_PE)
6945 /* For some reason, the PE format does not store a
6946 section address offset for a PC relative symbol. */
6947 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6948 || S_IS_WEAK (fixP->fx_addsy))
6949 value += md_pcrel_from (fixP);
6953 /* Fix a few things - the dynamic linker expects certain values here,
6954 and we must not disappoint it. */
6955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6956 if (IS_ELF && fixP->fx_addsy)
6957 switch (fixP->fx_r_type)
6959 case BFD_RELOC_386_PLT32:
6960 case BFD_RELOC_X86_64_PLT32:
6961 /* Make the jump instruction point to the address of the operand. At
6962 runtime we merely add the offset to the actual PLT entry. */
6966 case BFD_RELOC_386_TLS_GD:
6967 case BFD_RELOC_386_TLS_LDM:
6968 case BFD_RELOC_386_TLS_IE_32:
6969 case BFD_RELOC_386_TLS_IE:
6970 case BFD_RELOC_386_TLS_GOTIE:
6971 case BFD_RELOC_386_TLS_GOTDESC:
6972 case BFD_RELOC_X86_64_TLSGD:
6973 case BFD_RELOC_X86_64_TLSLD:
6974 case BFD_RELOC_X86_64_GOTTPOFF:
6975 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6976 value = 0; /* Fully resolved at runtime. No addend. */
6978 case BFD_RELOC_386_TLS_LE:
6979 case BFD_RELOC_386_TLS_LDO_32:
6980 case BFD_RELOC_386_TLS_LE_32:
6981 case BFD_RELOC_X86_64_DTPOFF32:
6982 case BFD_RELOC_X86_64_DTPOFF64:
6983 case BFD_RELOC_X86_64_TPOFF32:
6984 case BFD_RELOC_X86_64_TPOFF64:
6985 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6988 case BFD_RELOC_386_TLS_DESC_CALL:
6989 case BFD_RELOC_X86_64_TLSDESC_CALL:
6990 value = 0; /* Fully resolved at runtime. No addend. */
6991 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6995 case BFD_RELOC_386_GOT32:
6996 case BFD_RELOC_X86_64_GOT32:
6997 value = 0; /* Fully resolved at runtime. No addend. */
7000 case BFD_RELOC_VTABLE_INHERIT:
7001 case BFD_RELOC_VTABLE_ENTRY:
7008 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7010 #endif /* !defined (TE_Mach) */
7012 /* Are we finished with this relocation now? */
7013 if (fixP->fx_addsy == NULL)
7015 else if (use_rela_relocations)
7017 fixP->fx_no_overflow = 1;
7018 /* Remember value for tc_gen_reloc. */
7019 fixP->fx_addnumber = value;
7023 md_number_to_chars (p, value, fixP->fx_size);
7027 md_atof (int type, char *litP, int *sizeP)
7029 /* This outputs the LITTLENUMs in REVERSE order;
7030 in accord with the bigendian 386. */
7031 return ieee_md_atof (type, litP, sizeP, FALSE);
7034 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7037 output_invalid (int c)
7040 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7043 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7044 "(0x%x)", (unsigned char) c);
7045 return output_invalid_buf;
7048 /* REG_STRING starts *before* REGISTER_PREFIX. */
7050 static const reg_entry *
7051 parse_real_register (char *reg_string, char **end_op)
7053 char *s = reg_string;
7055 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7058 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7059 if (*s == REGISTER_PREFIX)
7062 if (is_space_char (*s))
7066 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7068 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7069 return (const reg_entry *) NULL;
7073 /* For naked regs, make sure that we are not dealing with an identifier.
7074 This prevents confusing an identifier like `eax_var' with register
7076 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7077 return (const reg_entry *) NULL;
7081 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7083 /* Handle floating point regs, allowing spaces in the (i) part. */
7084 if (r == i386_regtab /* %st is first entry of table */)
7086 if (is_space_char (*s))
7091 if (is_space_char (*s))
7093 if (*s >= '0' && *s <= '7')
7097 if (is_space_char (*s))
7102 r = hash_find (reg_hash, "st(0)");
7107 /* We have "%st(" then garbage. */
7108 return (const reg_entry *) NULL;
7112 if (r == NULL || allow_pseudo_reg)
7115 if (operand_type_all_zero (&r->reg_type))
7116 return (const reg_entry *) NULL;
7118 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7119 if (!allow_index_reg
7120 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7121 return (const reg_entry *) NULL;
7123 if (((r->reg_flags & (RegRex64 | RegRex))
7124 || r->reg_type.bitfield.reg64)
7125 && (!cpu_arch_flags.bitfield.cpulm
7126 || !operand_type_equal (&r->reg_type, &control))
7127 && flag_code != CODE_64BIT)
7128 return (const reg_entry *) NULL;
7130 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7131 return (const reg_entry *) NULL;
7136 /* REG_STRING starts *before* REGISTER_PREFIX. */
7138 static const reg_entry *
7139 parse_register (char *reg_string, char **end_op)
7143 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7144 r = parse_real_register (reg_string, end_op);
7149 char *save = input_line_pointer;
7153 input_line_pointer = reg_string;
7154 c = get_symbol_end ();
7155 symbolP = symbol_find (reg_string);
7156 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7158 const expressionS *e = symbol_get_value_expression (symbolP);
7160 know (e->X_op == O_register);
7161 know (e->X_add_number >= 0
7162 && (valueT) e->X_add_number < i386_regtab_size);
7163 r = i386_regtab + e->X_add_number;
7164 *end_op = input_line_pointer;
7166 *input_line_pointer = c;
7167 input_line_pointer = save;
7173 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7176 char *end = input_line_pointer;
7179 r = parse_register (name, &input_line_pointer);
7180 if (r && end <= input_line_pointer)
7182 *nextcharP = *input_line_pointer;
7183 *input_line_pointer = 0;
7184 e->X_op = O_register;
7185 e->X_add_number = r - i386_regtab;
7188 input_line_pointer = end;
7194 md_operand (expressionS *e)
7196 if (*input_line_pointer == REGISTER_PREFIX)
7199 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7203 e->X_op = O_register;
7204 e->X_add_number = r - i386_regtab;
7205 input_line_pointer = end;
7211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7212 const char *md_shortopts = "kVQ:sqn";
7214 const char *md_shortopts = "qn";
7217 #define OPTION_32 (OPTION_MD_BASE + 0)
7218 #define OPTION_64 (OPTION_MD_BASE + 1)
7219 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7220 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7221 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7222 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7223 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7224 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7225 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7226 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7228 struct option md_longopts[] =
7230 {"32", no_argument, NULL, OPTION_32},
7231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7232 {"64", no_argument, NULL, OPTION_64},
7234 {"divide", no_argument, NULL, OPTION_DIVIDE},
7235 {"march", required_argument, NULL, OPTION_MARCH},
7236 {"mtune", required_argument, NULL, OPTION_MTUNE},
7237 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7238 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7239 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7240 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7241 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7242 {NULL, no_argument, NULL, 0}
7244 size_t md_longopts_size = sizeof (md_longopts);
7247 md_parse_option (int c, char *arg)
7255 optimize_align_code = 0;
7262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7263 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7264 should be emitted or not. FIXME: Not implemented. */
7268 /* -V: SVR4 argument to print version ID. */
7270 print_version_id ();
7273 /* -k: Ignore for FreeBSD compatibility. */
7278 /* -s: On i386 Solaris, this tells the native assembler to use
7279 .stab instead of .stab.excl. We always use .stab anyhow. */
7282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7285 const char **list, **l;
7287 list = bfd_target_list ();
7288 for (l = list; *l != NULL; l++)
7289 if (CONST_STRNEQ (*l, "elf64-x86-64")
7290 || strcmp (*l, "coff-x86-64") == 0
7291 || strcmp (*l, "pe-x86-64") == 0
7292 || strcmp (*l, "pei-x86-64") == 0)
7294 default_arch = "x86_64";
7298 as_fatal (_("No compiled in support for x86_64"));
7305 default_arch = "i386";
7309 #ifdef SVR4_COMMENT_CHARS
7314 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7316 for (s = i386_comment_chars; *s != '\0'; s++)
7320 i386_comment_chars = n;
7326 arch = xstrdup (arg);
7330 as_fatal (_("Invalid -march= option: `%s'"), arg);
7331 next = strchr (arch, '+');
7334 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7336 if (strcmp (arch, cpu_arch [i].name) == 0)
7339 cpu_arch_name = cpu_arch[i].name;
7340 cpu_sub_arch_name = NULL;
7341 cpu_arch_flags = cpu_arch[i].flags;
7342 cpu_arch_isa = cpu_arch[i].type;
7343 cpu_arch_isa_flags = cpu_arch[i].flags;
7344 if (!cpu_arch_tune_set)
7346 cpu_arch_tune = cpu_arch_isa;
7347 cpu_arch_tune_flags = cpu_arch_isa_flags;
7351 else if (*cpu_arch [i].name == '.'
7352 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7354 /* ISA entension. */
7355 i386_cpu_flags flags;
7356 flags = cpu_flags_or (cpu_arch_flags,
7358 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7360 if (cpu_sub_arch_name)
7362 char *name = cpu_sub_arch_name;
7363 cpu_sub_arch_name = concat (name,
7365 (const char *) NULL);
7369 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7370 cpu_arch_flags = flags;
7376 if (i >= ARRAY_SIZE (cpu_arch))
7377 as_fatal (_("Invalid -march= option: `%s'"), arg);
7381 while (next != NULL );
7386 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7387 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7389 if (strcmp (arg, cpu_arch [i].name) == 0)
7391 cpu_arch_tune_set = 1;
7392 cpu_arch_tune = cpu_arch [i].type;
7393 cpu_arch_tune_flags = cpu_arch[i].flags;
7397 if (i >= ARRAY_SIZE (cpu_arch))
7398 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7401 case OPTION_MMNEMONIC:
7402 if (strcasecmp (arg, "att") == 0)
7404 else if (strcasecmp (arg, "intel") == 0)
7407 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7410 case OPTION_MSYNTAX:
7411 if (strcasecmp (arg, "att") == 0)
7413 else if (strcasecmp (arg, "intel") == 0)
7416 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7419 case OPTION_MINDEX_REG:
7420 allow_index_reg = 1;
7423 case OPTION_MNAKED_REG:
7424 allow_naked_reg = 1;
7427 case OPTION_MOLD_GCC:
7438 md_show_usage (stream)
7441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7442 fprintf (stream, _("\
7444 -V print assembler version number\n\
7447 fprintf (stream, _("\
7448 -n Do not optimize code alignment\n\
7449 -q quieten some warnings\n"));
7450 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7451 fprintf (stream, _("\
7454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7455 fprintf (stream, _("\
7456 --32/--64 generate 32bit/64bit code\n"));
7458 #ifdef SVR4_COMMENT_CHARS
7459 fprintf (stream, _("\
7460 --divide do not treat `/' as a comment character\n"));
7462 fprintf (stream, _("\
7463 --divide ignored\n"));
7465 fprintf (stream, _("\
7466 -march=CPU[,+EXTENSION...]\n\
7467 generate code for CPU and EXTENSION, CPU is one of:\n\
7468 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7469 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7470 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7471 generic32, generic64\n\
7472 EXTENSION is combination of:\n\
7473 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7474 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7476 fprintf (stream, _("\
7477 -mtune=CPU optimize for CPU, CPU is one of:\n\
7478 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7479 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7480 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7481 generic32, generic64\n"));
7482 fprintf (stream, _("\
7483 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7484 fprintf (stream, _("\
7485 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7486 fprintf (stream, _("\
7487 -mindex-reg support pseudo index registers\n"));
7488 fprintf (stream, _("\
7489 -mnaked-reg don't require `%%' prefix for registers\n"));
7490 fprintf (stream, _("\
7491 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7494 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7495 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7497 /* Pick the target format to use. */
7500 i386_target_format (void)
7502 if (!strcmp (default_arch, "x86_64"))
7504 set_code_flag (CODE_64BIT);
7505 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7507 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7508 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7509 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7510 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7511 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7512 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7513 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7514 cpu_arch_isa_flags.bitfield.cpummx= 1;
7515 cpu_arch_isa_flags.bitfield.cpusse = 1;
7516 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7518 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7520 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7521 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7522 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7523 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7524 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7525 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7526 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7527 cpu_arch_tune_flags.bitfield.cpummx= 1;
7528 cpu_arch_tune_flags.bitfield.cpusse = 1;
7529 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7532 else if (!strcmp (default_arch, "i386"))
7534 set_code_flag (CODE_32BIT);
7535 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7537 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7538 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7539 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7541 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7543 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7544 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7545 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7549 as_fatal (_("Unknown architecture"));
7550 switch (OUTPUT_FLAVOR)
7553 case bfd_target_coff_flavour:
7554 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7557 #ifdef OBJ_MAYBE_AOUT
7558 case bfd_target_aout_flavour:
7559 return AOUT_TARGET_FORMAT;
7561 #ifdef OBJ_MAYBE_COFF
7562 case bfd_target_coff_flavour:
7565 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7566 case bfd_target_elf_flavour:
7568 if (flag_code == CODE_64BIT)
7571 use_rela_relocations = 1;
7573 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7582 #endif /* OBJ_MAYBE_ more than one */
7584 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7586 i386_elf_emit_arch_note (void)
7588 if (IS_ELF && cpu_arch_name != NULL)
7591 asection *seg = now_seg;
7592 subsegT subseg = now_subseg;
7593 Elf_Internal_Note i_note;
7594 Elf_External_Note e_note;
7595 asection *note_secp;
7598 /* Create the .note section. */
7599 note_secp = subseg_new (".note", 0);
7600 bfd_set_section_flags (stdoutput,
7602 SEC_HAS_CONTENTS | SEC_READONLY);
7604 /* Process the arch string. */
7605 len = strlen (cpu_arch_name);
7607 i_note.namesz = len + 1;
7609 i_note.type = NT_ARCH;
7610 p = frag_more (sizeof (e_note.namesz));
7611 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7612 p = frag_more (sizeof (e_note.descsz));
7613 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7614 p = frag_more (sizeof (e_note.type));
7615 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7616 p = frag_more (len + 1);
7617 strcpy (p, cpu_arch_name);
7619 frag_align (2, 0, 0);
7621 subseg_set (seg, subseg);
7627 md_undefined_symbol (name)
7630 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7631 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7632 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7633 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7637 if (symbol_find (name))
7638 as_bad (_("GOT already in symbol table"));
7639 GOT_symbol = symbol_new (name, undefined_section,
7640 (valueT) 0, &zero_address_frag);
7647 /* Round up a section size to the appropriate boundary. */
7650 md_section_align (segment, size)
7651 segT segment ATTRIBUTE_UNUSED;
7654 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7655 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7657 /* For a.out, force the section size to be aligned. If we don't do
7658 this, BFD will align it for us, but it will not write out the
7659 final bytes of the section. This may be a bug in BFD, but it is
7660 easier to fix it here since that is how the other a.out targets
7664 align = bfd_get_section_alignment (stdoutput, segment);
7665 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7672 /* On the i386, PC-relative offsets are relative to the start of the
7673 next instruction. That is, the address of the offset, plus its
7674 size, since the offset is always the last part of the insn. */
7677 md_pcrel_from (fixS *fixP)
7679 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7685 s_bss (int ignore ATTRIBUTE_UNUSED)
7689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7691 obj_elf_section_change_hook ();
7693 temp = get_absolute_expression ();
7694 subseg_set (bss_section, (subsegT) temp);
7695 demand_empty_rest_of_line ();
7701 i386_validate_fix (fixS *fixp)
7703 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7705 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7709 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7714 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7716 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7723 tc_gen_reloc (section, fixp)
7724 asection *section ATTRIBUTE_UNUSED;
7728 bfd_reloc_code_real_type code;
7730 switch (fixp->fx_r_type)
7732 case BFD_RELOC_X86_64_PLT32:
7733 case BFD_RELOC_X86_64_GOT32:
7734 case BFD_RELOC_X86_64_GOTPCREL:
7735 case BFD_RELOC_386_PLT32:
7736 case BFD_RELOC_386_GOT32:
7737 case BFD_RELOC_386_GOTOFF:
7738 case BFD_RELOC_386_GOTPC:
7739 case BFD_RELOC_386_TLS_GD:
7740 case BFD_RELOC_386_TLS_LDM:
7741 case BFD_RELOC_386_TLS_LDO_32:
7742 case BFD_RELOC_386_TLS_IE_32:
7743 case BFD_RELOC_386_TLS_IE:
7744 case BFD_RELOC_386_TLS_GOTIE:
7745 case BFD_RELOC_386_TLS_LE_32:
7746 case BFD_RELOC_386_TLS_LE:
7747 case BFD_RELOC_386_TLS_GOTDESC:
7748 case BFD_RELOC_386_TLS_DESC_CALL:
7749 case BFD_RELOC_X86_64_TLSGD:
7750 case BFD_RELOC_X86_64_TLSLD:
7751 case BFD_RELOC_X86_64_DTPOFF32:
7752 case BFD_RELOC_X86_64_DTPOFF64:
7753 case BFD_RELOC_X86_64_GOTTPOFF:
7754 case BFD_RELOC_X86_64_TPOFF32:
7755 case BFD_RELOC_X86_64_TPOFF64:
7756 case BFD_RELOC_X86_64_GOTOFF64:
7757 case BFD_RELOC_X86_64_GOTPC32:
7758 case BFD_RELOC_X86_64_GOT64:
7759 case BFD_RELOC_X86_64_GOTPCREL64:
7760 case BFD_RELOC_X86_64_GOTPC64:
7761 case BFD_RELOC_X86_64_GOTPLT64:
7762 case BFD_RELOC_X86_64_PLTOFF64:
7763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7764 case BFD_RELOC_X86_64_TLSDESC_CALL:
7766 case BFD_RELOC_VTABLE_ENTRY:
7767 case BFD_RELOC_VTABLE_INHERIT:
7769 case BFD_RELOC_32_SECREL:
7771 code = fixp->fx_r_type;
7773 case BFD_RELOC_X86_64_32S:
7774 if (!fixp->fx_pcrel)
7776 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7777 code = fixp->fx_r_type;
7783 switch (fixp->fx_size)
7786 as_bad_where (fixp->fx_file, fixp->fx_line,
7787 _("can not do %d byte pc-relative relocation"),
7789 code = BFD_RELOC_32_PCREL;
7791 case 1: code = BFD_RELOC_8_PCREL; break;
7792 case 2: code = BFD_RELOC_16_PCREL; break;
7793 case 4: code = BFD_RELOC_32_PCREL; break;
7795 case 8: code = BFD_RELOC_64_PCREL; break;
7801 switch (fixp->fx_size)
7804 as_bad_where (fixp->fx_file, fixp->fx_line,
7805 _("can not do %d byte relocation"),
7807 code = BFD_RELOC_32;
7809 case 1: code = BFD_RELOC_8; break;
7810 case 2: code = BFD_RELOC_16; break;
7811 case 4: code = BFD_RELOC_32; break;
7813 case 8: code = BFD_RELOC_64; break;
7820 if ((code == BFD_RELOC_32
7821 || code == BFD_RELOC_32_PCREL
7822 || code == BFD_RELOC_X86_64_32S)
7824 && fixp->fx_addsy == GOT_symbol)
7827 code = BFD_RELOC_386_GOTPC;
7829 code = BFD_RELOC_X86_64_GOTPC32;
7831 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7833 && fixp->fx_addsy == GOT_symbol)
7835 code = BFD_RELOC_X86_64_GOTPC64;
7838 rel = (arelent *) xmalloc (sizeof (arelent));
7839 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7840 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7842 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7844 if (!use_rela_relocations)
7846 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7847 vtable entry to be used in the relocation's section offset. */
7848 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7849 rel->address = fixp->fx_offset;
7853 /* Use the rela in 64bit mode. */
7856 if (!fixp->fx_pcrel)
7857 rel->addend = fixp->fx_offset;
7861 case BFD_RELOC_X86_64_PLT32:
7862 case BFD_RELOC_X86_64_GOT32:
7863 case BFD_RELOC_X86_64_GOTPCREL:
7864 case BFD_RELOC_X86_64_TLSGD:
7865 case BFD_RELOC_X86_64_TLSLD:
7866 case BFD_RELOC_X86_64_GOTTPOFF:
7867 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7868 case BFD_RELOC_X86_64_TLSDESC_CALL:
7869 rel->addend = fixp->fx_offset - fixp->fx_size;
7872 rel->addend = (section->vma
7874 + fixp->fx_addnumber
7875 + md_pcrel_from (fixp));
7880 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7881 if (rel->howto == NULL)
7883 as_bad_where (fixp->fx_file, fixp->fx_line,
7884 _("cannot represent relocation type %s"),
7885 bfd_get_reloc_code_name (code));
7886 /* Set howto to a garbage value so that we can keep going. */
7887 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7888 assert (rel->howto != NULL);
7895 /* Parse operands using Intel syntax. This implements a recursive descent
7896 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7899 FIXME: We do not recognize the full operand grammar defined in the MASM
7900 documentation. In particular, all the structure/union and
7901 high-level macro operands are missing.
7903 Uppercase words are terminals, lower case words are non-terminals.
7904 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7905 bars '|' denote choices. Most grammar productions are implemented in
7906 functions called 'intel_<production>'.
7908 Initial production is 'expr'.
7914 binOp & | AND | \| | OR | ^ | XOR
7916 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7918 constant digits [[ radixOverride ]]
7920 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7958 => expr expr cmpOp e04
7961 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7962 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7964 hexdigit a | b | c | d | e | f
7965 | A | B | C | D | E | F
7971 mulOp * | / | % | MOD | << | SHL | >> | SHR
7975 register specialRegister
7979 segmentRegister CS | DS | ES | FS | GS | SS
7981 specialRegister CR0 | CR2 | CR3 | CR4
7982 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7983 | TR3 | TR4 | TR5 | TR6 | TR7
7985 We simplify the grammar in obvious places (e.g., register parsing is
7986 done by calling parse_register) and eliminate immediate left recursion
7987 to implement a recursive-descent parser.
7991 expr' cmpOp e04 expr'
8042 /* Parsing structure for the intel syntax parser. Used to implement the
8043 semantic actions for the operand grammar. */
8044 struct intel_parser_s
8046 char *op_string; /* The string being parsed. */
8047 int got_a_float; /* Whether the operand is a float. */
8048 int op_modifier; /* Operand modifier. */
8049 int is_mem; /* 1 if operand is memory reference. */
8050 int in_offset; /* >=1 if parsing operand of offset. */
8051 int in_bracket; /* >=1 if parsing operand in brackets. */
8052 const reg_entry *reg; /* Last register reference found. */
8053 char *disp; /* Displacement string being built. */
8054 char *next_operand; /* Resume point when splitting operands. */
8057 static struct intel_parser_s intel_parser;
8059 /* Token structure for parsing intel syntax. */
8062 int code; /* Token code. */
8063 const reg_entry *reg; /* Register entry for register tokens. */
8064 char *str; /* String representation. */
8067 static struct intel_token cur_token, prev_token;
8069 /* Token codes for the intel parser. Since T_SHORT is already used
8070 by COFF, undefine it first to prevent a warning. */
8089 /* Prototypes for intel parser functions. */
8090 static int intel_match_token (int);
8091 static void intel_putback_token (void);
8092 static void intel_get_token (void);
8093 static int intel_expr (void);
8094 static int intel_e04 (void);
8095 static int intel_e05 (void);
8096 static int intel_e06 (void);
8097 static int intel_e09 (void);
8098 static int intel_e10 (void);
8099 static int intel_e11 (void);
8102 i386_intel_operand (char *operand_string, int got_a_float)
8107 p = intel_parser.op_string = xstrdup (operand_string);
8108 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8112 /* Initialize token holders. */
8113 cur_token.code = prev_token.code = T_NIL;
8114 cur_token.reg = prev_token.reg = NULL;
8115 cur_token.str = prev_token.str = NULL;
8117 /* Initialize parser structure. */
8118 intel_parser.got_a_float = got_a_float;
8119 intel_parser.op_modifier = 0;
8120 intel_parser.is_mem = 0;
8121 intel_parser.in_offset = 0;
8122 intel_parser.in_bracket = 0;
8123 intel_parser.reg = NULL;
8124 intel_parser.disp[0] = '\0';
8125 intel_parser.next_operand = NULL;
8127 /* Read the first token and start the parser. */
8129 ret = intel_expr ();
8134 if (cur_token.code != T_NIL)
8136 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8137 current_templates->start->name, cur_token.str);
8140 /* If we found a memory reference, hand it over to i386_displacement
8141 to fill in the rest of the operand fields. */
8142 else if (intel_parser.is_mem)
8144 if ((i.mem_operands == 1
8145 && !current_templates->start->opcode_modifier.isstring)
8146 || i.mem_operands == 2)
8148 as_bad (_("too many memory references for '%s'"),
8149 current_templates->start->name);
8154 char *s = intel_parser.disp;
8155 i.types[this_operand].bitfield.mem = 1;
8158 if (!quiet_warnings && intel_parser.is_mem < 0)
8159 /* See the comments in intel_bracket_expr. */
8160 as_warn (_("Treating `%s' as memory reference"), operand_string);
8162 /* Add the displacement expression. */
8164 ret = i386_displacement (s, s + strlen (s));
8167 /* Swap base and index in 16-bit memory operands like
8168 [si+bx]. Since i386_index_check is also used in AT&T
8169 mode we have to do that here. */
8172 && i.base_reg->reg_type.bitfield.reg16
8173 && i.index_reg->reg_type.bitfield.reg16
8174 && i.base_reg->reg_num >= 6
8175 && i.index_reg->reg_num < 6)
8177 const reg_entry *base = i.index_reg;
8179 i.index_reg = i.base_reg;
8182 ret = i386_index_check (operand_string);
8187 /* Constant and OFFSET expressions are handled by i386_immediate. */
8188 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8189 || intel_parser.reg == NULL)
8191 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8193 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8194 as_warn (_("Segment override ignored"));
8195 i.seg[i.mem_operands] = NULL;
8197 ret = i386_immediate (intel_parser.disp);
8200 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8202 if (!ret || !intel_parser.next_operand)
8204 intel_parser.op_string = intel_parser.next_operand;
8205 this_operand = i.operands++;
8206 i.types[this_operand].bitfield.unspecified = 1;
8210 free (intel_parser.disp);
8215 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8219 expr' cmpOp e04 expr'
8224 /* XXX Implement the comparison operators. */
8225 return intel_e04 ();
8242 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8243 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8245 if (cur_token.code == '+')
8247 else if (cur_token.code == '-')
8248 nregs = NUM_ADDRESS_REGS;
8252 strcat (intel_parser.disp, cur_token.str);
8253 intel_match_token (cur_token.code);
8264 int nregs = ~NUM_ADDRESS_REGS;
8271 if (cur_token.code == '&'
8272 || cur_token.code == '|'
8273 || cur_token.code == '^')
8277 str[0] = cur_token.code;
8279 strcat (intel_parser.disp, str);
8284 intel_match_token (cur_token.code);
8289 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8290 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8301 int nregs = ~NUM_ADDRESS_REGS;
8308 if (cur_token.code == '*'
8309 || cur_token.code == '/'
8310 || cur_token.code == '%')
8314 str[0] = cur_token.code;
8316 strcat (intel_parser.disp, str);
8318 else if (cur_token.code == T_SHL)
8319 strcat (intel_parser.disp, "<<");
8320 else if (cur_token.code == T_SHR)
8321 strcat (intel_parser.disp, ">>");
8325 intel_match_token (cur_token.code);
8330 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8331 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8349 int nregs = ~NUM_ADDRESS_REGS;
8354 /* Don't consume constants here. */
8355 if (cur_token.code == '+' || cur_token.code == '-')
8357 /* Need to look one token ahead - if the next token
8358 is a constant, the current token is its sign. */
8361 intel_match_token (cur_token.code);
8362 next_code = cur_token.code;
8363 intel_putback_token ();
8364 if (next_code == T_CONST)
8368 /* e09 OFFSET e09 */
8369 if (cur_token.code == T_OFFSET)
8372 ++intel_parser.in_offset;
8376 else if (cur_token.code == T_SHORT)
8377 intel_parser.op_modifier |= 1 << T_SHORT;
8380 else if (cur_token.code == '+')
8381 strcat (intel_parser.disp, "+");
8386 else if (cur_token.code == '-' || cur_token.code == '~')
8392 str[0] = cur_token.code;
8394 strcat (intel_parser.disp, str);
8401 intel_match_token (cur_token.code);
8409 /* e09' PTR e10 e09' */
8410 if (cur_token.code == T_PTR)
8414 if (prev_token.code == T_BYTE)
8416 suffix = BYTE_MNEM_SUFFIX;
8417 i.types[this_operand].bitfield.byte = 1;
8420 else if (prev_token.code == T_WORD)
8422 if ((current_templates->start->name[0] == 'l'
8423 && current_templates->start->name[2] == 's'
8424 && current_templates->start->name[3] == 0)
8425 || current_templates->start->base_opcode == 0x62 /* bound */)
8426 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8427 else if (intel_parser.got_a_float == 2) /* "fi..." */
8428 suffix = SHORT_MNEM_SUFFIX;
8430 suffix = WORD_MNEM_SUFFIX;
8431 i.types[this_operand].bitfield.word = 1;
8434 else if (prev_token.code == T_DWORD)
8436 if ((current_templates->start->name[0] == 'l'
8437 && current_templates->start->name[2] == 's'
8438 && current_templates->start->name[3] == 0)
8439 || current_templates->start->base_opcode == 0x62 /* bound */)
8440 suffix = WORD_MNEM_SUFFIX;
8441 else if (flag_code == CODE_16BIT
8442 && (current_templates->start->opcode_modifier.jump
8443 || current_templates->start->opcode_modifier.jumpdword))
8444 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8445 else if (intel_parser.got_a_float == 1) /* "f..." */
8446 suffix = SHORT_MNEM_SUFFIX;
8448 suffix = LONG_MNEM_SUFFIX;
8449 i.types[this_operand].bitfield.dword = 1;
8452 else if (prev_token.code == T_FWORD)
8454 if (current_templates->start->name[0] == 'l'
8455 && current_templates->start->name[2] == 's'
8456 && current_templates->start->name[3] == 0)
8457 suffix = LONG_MNEM_SUFFIX;
8458 else if (!intel_parser.got_a_float)
8460 if (flag_code == CODE_16BIT)
8461 add_prefix (DATA_PREFIX_OPCODE);
8462 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8465 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8466 i.types[this_operand].bitfield.fword = 1;
8469 else if (prev_token.code == T_QWORD)
8471 if (current_templates->start->base_opcode == 0x62 /* bound */
8472 || intel_parser.got_a_float == 1) /* "f..." */
8473 suffix = LONG_MNEM_SUFFIX;
8475 suffix = QWORD_MNEM_SUFFIX;
8476 i.types[this_operand].bitfield.qword = 1;
8479 else if (prev_token.code == T_TBYTE)
8481 if (intel_parser.got_a_float == 1)
8482 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8484 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8487 else if (prev_token.code == T_XMMWORD)
8489 suffix = XMMWORD_MNEM_SUFFIX;
8490 i.types[this_operand].bitfield.xmmword = 1;
8495 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8499 i.types[this_operand].bitfield.unspecified = 0;
8501 /* Operands for jump/call using 'ptr' notation denote absolute
8503 if (current_templates->start->opcode_modifier.jump
8504 || current_templates->start->opcode_modifier.jumpdword)
8505 i.types[this_operand].bitfield.jumpabsolute = 1;
8507 if (current_templates->start->base_opcode == 0x8d /* lea */)
8511 else if (i.suffix != suffix)
8513 as_bad (_("Conflicting operand modifiers"));
8519 /* e09' : e10 e09' */
8520 else if (cur_token.code == ':')
8522 if (prev_token.code != T_REG)
8524 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8525 segment/group identifier (which we don't have), using comma
8526 as the operand separator there is even less consistent, since
8527 there all branches only have a single operand. */
8528 if (this_operand != 0
8529 || intel_parser.in_offset
8530 || intel_parser.in_bracket
8531 || (!current_templates->start->opcode_modifier.jump
8532 && !current_templates->start->opcode_modifier.jumpdword
8533 && !current_templates->start->opcode_modifier.jumpintersegment
8534 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8535 return intel_match_token (T_NIL);
8536 /* Remember the start of the 2nd operand and terminate 1st
8538 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8539 another expression), but it gets at least the simplest case
8540 (a plain number or symbol on the left side) right. */
8541 intel_parser.next_operand = intel_parser.op_string;
8542 *--intel_parser.op_string = '\0';
8543 return intel_match_token (':');
8551 intel_match_token (cur_token.code);
8557 --intel_parser.in_offset;
8560 if (NUM_ADDRESS_REGS > nregs)
8562 as_bad (_("Invalid operand to `OFFSET'"));
8565 intel_parser.op_modifier |= 1 << T_OFFSET;
8568 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8569 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8574 intel_bracket_expr (void)
8576 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8577 const char *start = intel_parser.op_string;
8580 if (i.op[this_operand].regs)
8581 return intel_match_token (T_NIL);
8583 intel_match_token ('[');
8585 /* Mark as a memory operand only if it's not already known to be an
8586 offset expression. If it's an offset expression, we need to keep
8588 if (!intel_parser.in_offset)
8590 ++intel_parser.in_bracket;
8592 /* Operands for jump/call inside brackets denote absolute addresses. */
8593 if (current_templates->start->opcode_modifier.jump
8594 || current_templates->start->opcode_modifier.jumpdword)
8595 i.types[this_operand].bitfield.jumpabsolute = 1;
8597 /* Unfortunately gas always diverged from MASM in a respect that can't
8598 be easily fixed without risking to break code sequences likely to be
8599 encountered (the testsuite even check for this): MASM doesn't consider
8600 an expression inside brackets unconditionally as a memory reference.
8601 When that is e.g. a constant, an offset expression, or the sum of the
8602 two, this is still taken as a constant load. gas, however, always
8603 treated these as memory references. As a compromise, we'll try to make
8604 offset expressions inside brackets work the MASM way (since that's
8605 less likely to be found in real world code), but make constants alone
8606 continue to work the traditional gas way. In either case, issue a
8608 intel_parser.op_modifier &= ~was_offset;
8611 strcat (intel_parser.disp, "[");
8613 /* Add a '+' to the displacement string if necessary. */
8614 if (*intel_parser.disp != '\0'
8615 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8616 strcat (intel_parser.disp, "+");
8619 && (len = intel_parser.op_string - start - 1,
8620 intel_match_token (']')))
8622 /* Preserve brackets when the operand is an offset expression. */
8623 if (intel_parser.in_offset)
8624 strcat (intel_parser.disp, "]");
8627 --intel_parser.in_bracket;
8628 if (i.base_reg || i.index_reg)
8629 intel_parser.is_mem = 1;
8630 if (!intel_parser.is_mem)
8632 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8633 /* Defer the warning until all of the operand was parsed. */
8634 intel_parser.is_mem = -1;
8635 else if (!quiet_warnings)
8636 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8637 len, start, len, start);
8640 intel_parser.op_modifier |= was_offset;
8657 while (cur_token.code == '[')
8659 if (!intel_bracket_expr ())
8684 switch (cur_token.code)
8688 intel_match_token ('(');
8689 strcat (intel_parser.disp, "(");
8691 if (intel_expr () && intel_match_token (')'))
8693 strcat (intel_parser.disp, ")");
8700 return intel_bracket_expr ();
8705 strcat (intel_parser.disp, cur_token.str);
8706 intel_match_token (cur_token.code);
8708 /* Mark as a memory operand only if it's not already known to be an
8709 offset expression. */
8710 if (!intel_parser.in_offset)
8711 intel_parser.is_mem = 1;
8718 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8720 intel_match_token (T_REG);
8722 /* Check for segment change. */
8723 if (cur_token.code == ':')
8725 if (!reg->reg_type.bitfield.sreg2
8726 && !reg->reg_type.bitfield.sreg3)
8728 as_bad (_("`%s' is not a valid segment register"),
8732 else if (i.mem_operands >= 2)
8733 as_warn (_("Segment override ignored"));
8734 else if (i.seg[i.mem_operands])
8735 as_warn (_("Extra segment override ignored"));
8738 if (!intel_parser.in_offset)
8739 intel_parser.is_mem = 1;
8740 switch (reg->reg_num)
8743 i.seg[i.mem_operands] = &es;
8746 i.seg[i.mem_operands] = &cs;
8749 i.seg[i.mem_operands] = &ss;
8752 i.seg[i.mem_operands] = &ds;
8755 i.seg[i.mem_operands] = &fs;
8758 i.seg[i.mem_operands] = &gs;
8764 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8766 as_bad (_("cannot use `FLAT' here"));
8770 /* Not a segment register. Check for register scaling. */
8771 else if (cur_token.code == '*')
8773 if (!intel_parser.in_bracket)
8775 as_bad (_("Register scaling only allowed in memory operands"));
8779 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8780 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8781 else if (i.index_reg)
8782 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8784 /* What follows must be a valid scale. */
8785 intel_match_token ('*');
8787 i.types[this_operand].bitfield.baseindex = 1;
8789 /* Set the scale after setting the register (otherwise,
8790 i386_scale will complain) */
8791 if (cur_token.code == '+' || cur_token.code == '-')
8793 char *str, sign = cur_token.code;
8794 intel_match_token (cur_token.code);
8795 if (cur_token.code != T_CONST)
8797 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8801 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8802 strcpy (str + 1, cur_token.str);
8804 if (!i386_scale (str))
8808 else if (!i386_scale (cur_token.str))
8810 intel_match_token (cur_token.code);
8813 /* No scaling. If this is a memory operand, the register is either a
8814 base register (first occurrence) or an index register (second
8816 else if (intel_parser.in_bracket)
8821 else if (!i.index_reg)
8825 as_bad (_("Too many register references in memory operand"));
8829 i.types[this_operand].bitfield.baseindex = 1;
8832 /* It's neither base nor index. */
8833 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8835 i386_operand_type temp = reg->reg_type;
8836 temp.bitfield.baseindex = 0;
8837 i.types[this_operand] = operand_type_or (i.types[this_operand],
8839 i.types[this_operand].bitfield.unspecified = 0;
8840 i.op[this_operand].regs = reg;
8845 as_bad (_("Invalid use of register"));
8849 /* Since registers are not part of the displacement string (except
8850 when we're parsing offset operands), we may need to remove any
8851 preceding '+' from the displacement string. */
8852 if (*intel_parser.disp != '\0'
8853 && !intel_parser.in_offset)
8855 char *s = intel_parser.disp;
8856 s += strlen (s) - 1;
8879 intel_match_token (cur_token.code);
8881 if (cur_token.code == T_PTR)
8884 /* It must have been an identifier. */
8885 intel_putback_token ();
8886 cur_token.code = T_ID;
8892 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8896 /* The identifier represents a memory reference only if it's not
8897 preceded by an offset modifier and if it's not an equate. */
8898 symbolP = symbol_find(cur_token.str);
8899 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8900 intel_parser.is_mem = 1;
8908 char *save_str, sign = 0;
8910 /* Allow constants that start with `+' or `-'. */
8911 if (cur_token.code == '-' || cur_token.code == '+')
8913 sign = cur_token.code;
8914 intel_match_token (cur_token.code);
8915 if (cur_token.code != T_CONST)
8917 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8923 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8924 strcpy (save_str + !!sign, cur_token.str);
8928 /* Get the next token to check for register scaling. */
8929 intel_match_token (cur_token.code);
8931 /* Check if this constant is a scaling factor for an
8933 if (cur_token.code == '*')
8935 if (intel_match_token ('*') && cur_token.code == T_REG)
8937 const reg_entry *reg = cur_token.reg;
8939 if (!intel_parser.in_bracket)
8941 as_bad (_("Register scaling only allowed "
8942 "in memory operands"));
8946 /* Disallow things like [1*si].
8947 sp and esp are invalid as index. */
8948 if (reg->reg_type.bitfield.reg16)
8949 reg = i386_regtab + REGNAM_AX + 4;
8950 else if (i.index_reg)
8951 reg = i386_regtab + REGNAM_EAX + 4;
8953 /* The constant is followed by `* reg', so it must be
8956 i.types[this_operand].bitfield.baseindex = 1;
8958 /* Set the scale after setting the register (otherwise,
8959 i386_scale will complain) */
8960 if (!i386_scale (save_str))
8962 intel_match_token (T_REG);
8964 /* Since registers are not part of the displacement
8965 string, we may need to remove any preceding '+' from
8966 the displacement string. */
8967 if (*intel_parser.disp != '\0')
8969 char *s = intel_parser.disp;
8970 s += strlen (s) - 1;
8980 /* The constant was not used for register scaling. Since we have
8981 already consumed the token following `*' we now need to put it
8982 back in the stream. */
8983 intel_putback_token ();
8986 /* Add the constant to the displacement string. */
8987 strcat (intel_parser.disp, save_str);
8994 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8998 /* Match the given token against cur_token. If they match, read the next
8999 token from the operand string. */
9001 intel_match_token (int code)
9003 if (cur_token.code == code)
9010 as_bad (_("Unexpected token `%s'"), cur_token.str);
9015 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9017 intel_get_token (void)
9020 const reg_entry *reg;
9021 struct intel_token new_token;
9023 new_token.code = T_NIL;
9024 new_token.reg = NULL;
9025 new_token.str = NULL;
9027 /* Free the memory allocated to the previous token and move
9028 cur_token to prev_token. */
9030 free (prev_token.str);
9032 prev_token = cur_token;
9034 /* Skip whitespace. */
9035 while (is_space_char (*intel_parser.op_string))
9036 intel_parser.op_string++;
9038 /* Return an empty token if we find nothing else on the line. */
9039 if (*intel_parser.op_string == '\0')
9041 cur_token = new_token;
9045 /* The new token cannot be larger than the remainder of the operand
9047 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
9048 new_token.str[0] = '\0';
9050 if (strchr ("0123456789", *intel_parser.op_string))
9052 char *p = new_token.str;
9053 char *q = intel_parser.op_string;
9054 new_token.code = T_CONST;
9056 /* Allow any kind of identifier char to encompass floating point and
9057 hexadecimal numbers. */
9058 while (is_identifier_char (*q))
9062 /* Recognize special symbol names [0-9][bf]. */
9063 if (strlen (intel_parser.op_string) == 2
9064 && (intel_parser.op_string[1] == 'b'
9065 || intel_parser.op_string[1] == 'f'))
9066 new_token.code = T_ID;
9069 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9071 size_t len = end_op - intel_parser.op_string;
9073 new_token.code = T_REG;
9074 new_token.reg = reg;
9076 memcpy (new_token.str, intel_parser.op_string, len);
9077 new_token.str[len] = '\0';
9080 else if (is_identifier_char (*intel_parser.op_string))
9082 char *p = new_token.str;
9083 char *q = intel_parser.op_string;
9085 /* A '.' or '$' followed by an identifier char is an identifier.
9086 Otherwise, it's operator '.' followed by an expression. */
9087 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9089 new_token.code = '.';
9090 new_token.str[0] = '.';
9091 new_token.str[1] = '\0';
9095 while (is_identifier_char (*q) || *q == '@')
9099 if (strcasecmp (new_token.str, "NOT") == 0)
9100 new_token.code = '~';
9102 else if (strcasecmp (new_token.str, "MOD") == 0)
9103 new_token.code = '%';
9105 else if (strcasecmp (new_token.str, "AND") == 0)
9106 new_token.code = '&';
9108 else if (strcasecmp (new_token.str, "OR") == 0)
9109 new_token.code = '|';
9111 else if (strcasecmp (new_token.str, "XOR") == 0)
9112 new_token.code = '^';
9114 else if (strcasecmp (new_token.str, "SHL") == 0)
9115 new_token.code = T_SHL;
9117 else if (strcasecmp (new_token.str, "SHR") == 0)
9118 new_token.code = T_SHR;
9120 else if (strcasecmp (new_token.str, "BYTE") == 0)
9121 new_token.code = T_BYTE;
9123 else if (strcasecmp (new_token.str, "WORD") == 0)
9124 new_token.code = T_WORD;
9126 else if (strcasecmp (new_token.str, "DWORD") == 0)
9127 new_token.code = T_DWORD;
9129 else if (strcasecmp (new_token.str, "FWORD") == 0)
9130 new_token.code = T_FWORD;
9132 else if (strcasecmp (new_token.str, "QWORD") == 0)
9133 new_token.code = T_QWORD;
9135 else if (strcasecmp (new_token.str, "TBYTE") == 0
9136 /* XXX remove (gcc still uses it) */
9137 || strcasecmp (new_token.str, "XWORD") == 0)
9138 new_token.code = T_TBYTE;
9140 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9141 || strcasecmp (new_token.str, "OWORD") == 0)
9142 new_token.code = T_XMMWORD;
9144 else if (strcasecmp (new_token.str, "PTR") == 0)
9145 new_token.code = T_PTR;
9147 else if (strcasecmp (new_token.str, "SHORT") == 0)
9148 new_token.code = T_SHORT;
9150 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9152 new_token.code = T_OFFSET;
9154 /* ??? This is not mentioned in the MASM grammar but gcc
9155 makes use of it with -mintel-syntax. OFFSET may be
9156 followed by FLAT: */
9157 if (strncasecmp (q, " FLAT:", 6) == 0)
9158 strcat (new_token.str, " FLAT:");
9162 new_token.code = T_ID;
9166 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9168 new_token.code = *intel_parser.op_string;
9169 new_token.str[0] = *intel_parser.op_string;
9170 new_token.str[1] = '\0';
9173 else if (strchr ("<>", *intel_parser.op_string)
9174 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9176 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9177 new_token.str[0] = *intel_parser.op_string;
9178 new_token.str[1] = *intel_parser.op_string;
9179 new_token.str[2] = '\0';
9183 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9185 intel_parser.op_string += strlen (new_token.str);
9186 cur_token = new_token;
9189 /* Put cur_token back into the token stream and make cur_token point to
9192 intel_putback_token (void)
9194 if (cur_token.code != T_NIL)
9196 intel_parser.op_string -= strlen (cur_token.str);
9197 free (cur_token.str);
9199 cur_token = prev_token;
9201 /* Forget prev_token. */
9202 prev_token.code = T_NIL;
9203 prev_token.reg = NULL;
9204 prev_token.str = NULL;
9208 tc_x86_parse_to_dw2regnum (expressionS *exp)
9210 int saved_naked_reg;
9211 char saved_register_dot;
9213 saved_naked_reg = allow_naked_reg;
9214 allow_naked_reg = 1;
9215 saved_register_dot = register_chars['.'];
9216 register_chars['.'] = '.';
9217 allow_pseudo_reg = 1;
9218 expression_and_evaluate (exp);
9219 allow_pseudo_reg = 0;
9220 register_chars['.'] = saved_register_dot;
9221 allow_naked_reg = saved_naked_reg;
9223 if (exp->X_op == O_register && exp->X_add_number >= 0)
9225 if ((addressT) exp->X_add_number < i386_regtab_size)
9227 exp->X_op = O_constant;
9228 exp->X_add_number = i386_regtab[exp->X_add_number]
9229 .dw2_regnum[flag_code >> 1];
9232 exp->X_op = O_illegal;
9237 tc_x86_frame_initial_instructions (void)
9239 static unsigned int sp_regno[2];
9241 if (!sp_regno[flag_code >> 1])
9243 char *saved_input = input_line_pointer;
9244 char sp[][4] = {"esp", "rsp"};
9247 input_line_pointer = sp[flag_code >> 1];
9248 tc_x86_parse_to_dw2regnum (&exp);
9249 assert (exp.X_op == O_constant);
9250 sp_regno[flag_code >> 1] = exp.X_add_number;
9251 input_line_pointer = saved_input;
9254 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9255 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9259 i386_elf_section_type (const char *str, size_t len)
9261 if (flag_code == CODE_64BIT
9262 && len == sizeof ("unwind") - 1
9263 && strncmp (str, "unwind", 6) == 0)
9264 return SHT_X86_64_UNWIND;
9271 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9275 expr.X_op = O_secrel;
9276 expr.X_add_symbol = symbol;
9277 expr.X_add_number = 0;
9278 emit_expr (&expr, size);
9282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9283 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9286 x86_64_section_letter (int letter, char **ptr_msg)
9288 if (flag_code == CODE_64BIT)
9291 return SHF_X86_64_LARGE;
9293 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9296 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9301 x86_64_section_word (char *str, size_t len)
9303 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9304 return SHF_X86_64_LARGE;
9310 handle_large_common (int small ATTRIBUTE_UNUSED)
9312 if (flag_code != CODE_64BIT)
9314 s_comm_internal (0, elf_common_parse);
9315 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9319 static segT lbss_section;
9320 asection *saved_com_section_ptr = elf_com_section_ptr;
9321 asection *saved_bss_section = bss_section;
9323 if (lbss_section == NULL)
9325 flagword applicable;
9327 subsegT subseg = now_subseg;
9329 /* The .lbss section is for local .largecomm symbols. */
9330 lbss_section = subseg_new (".lbss", 0);
9331 applicable = bfd_applicable_section_flags (stdoutput);
9332 bfd_set_section_flags (stdoutput, lbss_section,
9333 applicable & SEC_ALLOC);
9334 seg_info (lbss_section)->bss = 1;
9336 subseg_set (seg, subseg);
9339 elf_com_section_ptr = &_bfd_elf_large_com_section;
9340 bss_section = lbss_section;
9342 s_comm_internal (0, elf_common_parse);
9344 elf_com_section_ptr = saved_com_section_ptr;
9345 bss_section = saved_bss_section;
9348 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */