1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
200 static const char *default_arch = DEFAULT_ARCH;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry *mask;
224 unsigned int zeroing;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes[4];
253 /* Destination or source register specifier. */
254 const reg_entry *register_specifier;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry *regs;
269 operand_size_mismatch,
270 operand_type_mismatch,
271 register_type_mismatch,
272 number_of_operands_mismatch,
273 invalid_instruction_suffix,
275 unsupported_with_intel_mnemonic,
278 invalid_vsib_address,
279 invalid_vector_register_set,
280 unsupported_vector_index_register,
281 unsupported_broadcast,
284 mask_not_on_destination,
287 rc_sae_operand_not_last_imm,
288 invalid_register_operand,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types[MAX_OPERANDS];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op[MAX_OPERANDS];
316 /* Flags for operands. */
317 unsigned int flags[MAX_OPERANDS];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry *base_reg;
327 const reg_entry *index_reg;
328 unsigned int log2_scale_factor;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry *seg[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes;
340 unsigned char prefix[MAX_PREFIXES];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation *mask;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation *rounding;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation *broadcast;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default = 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default = 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize;
397 /* How to encode vector instructions. */
400 vex_encoding_default = 0,
407 const char *rep_prefix;
410 const char *hle_prefix;
412 /* Have BND prefix. */
413 const char *bnd_prefix;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix;
419 enum i386_error error;
422 typedef struct _i386_insn i386_insn;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable[] =
435 { rne, STRING_COMMA_LEN ("rn-sae") },
436 { rd, STRING_COMMA_LEN ("rd-sae") },
437 { ru, STRING_COMMA_LEN ("ru-sae") },
438 { rz, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars = "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars = "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars[] = "#/";
483 const char line_separator_chars[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars[256];
496 static char register_chars[256];
497 static char operand_chars[256];
498 static char identifier_chars[256];
499 static char digit_chars[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack[32];
517 static char *save_stack_p;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates *current_templates;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
531 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
533 /* Current operand we are working on. */
534 static int this_operand = -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code;
545 static unsigned int object_64bit;
546 static unsigned int disallow_64bit_reloc;
547 static int use_rela_relocations = 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi = I386_ABI;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj = 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared = 0;
574 /* 1 for intel syntax,
576 static int intel_syntax = 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic = !SYSV386_COMPAT;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg = 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg = 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix = 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg = 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix = 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence = 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
613 static enum check_kind
619 sse_check, operand_check = check_warning;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize = 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space = 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix = "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size = '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code = 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings = 0;
652 static const char *cpu_arch_name = NULL;
653 static char *cpu_sub_arch_name = NULL;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set = 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion = 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode scalar EVEX LIG instructions with specific vector length. */
695 /* Encode EVEX WIG instructions with specific evex.w. */
702 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
703 static enum rc_type evexrcig = rne;
705 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
706 static symbolS *GOT_symbol;
708 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
709 unsigned int x86_dwarf2_return_column;
711 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
712 int x86_cie_data_alignment;
714 /* Interface to relax_segment.
715 There are 3 major relax states for 386 jump insns because the
716 different types of jumps add different sizes to frags when we're
717 figuring out what sort of jump to choose to reach a given label. */
720 #define UNCOND_JUMP 0
722 #define COND_JUMP86 2
727 #define SMALL16 (SMALL | CODE16)
729 #define BIG16 (BIG | CODE16)
733 #define INLINE __inline__
739 #define ENCODE_RELAX_STATE(type, size) \
740 ((relax_substateT) (((type) << 2) | (size)))
741 #define TYPE_FROM_RELAX_STATE(s) \
743 #define DISP_SIZE_FROM_RELAX_STATE(s) \
744 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
746 /* This table is used by relax_frag to promote short jumps to long
747 ones where necessary. SMALL (short) jumps may be promoted to BIG
748 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
749 don't allow a short jump in a 32 bit code segment to be promoted to
750 a 16 bit offset jump because it's slower (requires data size
751 prefix), and doesn't work, unless the destination is in the bottom
752 64k of the code segment (The top 16 bits of eip are zeroed). */
754 const relax_typeS md_relax_table[] =
757 1) most positive reach of this state,
758 2) most negative reach of this state,
759 3) how many bytes this mode will have in the variable part of the frag
760 4) which index into the table to try if we can't fit into this one. */
762 /* UNCOND_JUMP states. */
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
764 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
765 /* dword jmp adds 4 bytes to frag:
766 0 extra opcode bytes, 4 displacement bytes. */
768 /* word jmp adds 2 byte2 to frag:
769 0 extra opcode bytes, 2 displacement bytes. */
772 /* COND_JUMP states. */
773 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
774 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
775 /* dword conditionals adds 5 bytes to frag:
776 1 extra opcode byte, 4 displacement bytes. */
778 /* word conditionals add 3 bytes to frag:
779 1 extra opcode byte, 2 displacement bytes. */
782 /* COND_JUMP86 states. */
783 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
785 /* dword conditionals adds 5 bytes to frag:
786 1 extra opcode byte, 4 displacement bytes. */
788 /* word conditionals add 4 bytes to frag:
789 1 displacement byte and a 3 byte long branch insn. */
793 static const arch_entry cpu_arch[] =
795 /* Do not replace the first two entries - i386_target_format()
796 relies on them being there in this order. */
797 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
798 CPU_GENERIC32_FLAGS, 0 },
799 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
800 CPU_GENERIC64_FLAGS, 0 },
801 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
803 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
805 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
807 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
809 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
811 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
813 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
815 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
817 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
818 CPU_PENTIUMPRO_FLAGS, 0 },
819 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
821 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
823 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
825 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
827 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
828 CPU_NOCONA_FLAGS, 0 },
829 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
831 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
833 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
834 CPU_CORE2_FLAGS, 1 },
835 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
836 CPU_CORE2_FLAGS, 0 },
837 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
838 CPU_COREI7_FLAGS, 0 },
839 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
841 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
843 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
844 CPU_IAMCU_FLAGS, 0 },
845 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
847 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
849 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
850 CPU_ATHLON_FLAGS, 0 },
851 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
853 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
855 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
857 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
858 CPU_AMDFAM10_FLAGS, 0 },
859 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
860 CPU_BDVER1_FLAGS, 0 },
861 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
862 CPU_BDVER2_FLAGS, 0 },
863 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
864 CPU_BDVER3_FLAGS, 0 },
865 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
866 CPU_BDVER4_FLAGS, 0 },
867 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
868 CPU_ZNVER1_FLAGS, 0 },
869 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
870 CPU_ZNVER2_FLAGS, 0 },
871 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
872 CPU_BTVER1_FLAGS, 0 },
873 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
874 CPU_BTVER2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
881 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
883 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
885 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
887 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
889 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
891 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
893 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
896 CPU_SSSE3_FLAGS, 0 },
897 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
898 CPU_SSE4_1_FLAGS, 0 },
899 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
900 CPU_SSE4_2_FLAGS, 0 },
901 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
902 CPU_SSE4_2_FLAGS, 0 },
903 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
905 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
907 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
908 CPU_AVX512F_FLAGS, 0 },
909 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
910 CPU_AVX512CD_FLAGS, 0 },
911 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
912 CPU_AVX512ER_FLAGS, 0 },
913 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
914 CPU_AVX512PF_FLAGS, 0 },
915 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
916 CPU_AVX512DQ_FLAGS, 0 },
917 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
918 CPU_AVX512BW_FLAGS, 0 },
919 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
920 CPU_AVX512VL_FLAGS, 0 },
921 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
924 CPU_VMFUNC_FLAGS, 0 },
925 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
928 CPU_XSAVE_FLAGS, 0 },
929 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
930 CPU_XSAVEOPT_FLAGS, 0 },
931 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
932 CPU_XSAVEC_FLAGS, 0 },
933 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
934 CPU_XSAVES_FLAGS, 0 },
935 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
937 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
938 CPU_PCLMUL_FLAGS, 0 },
939 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
940 CPU_PCLMUL_FLAGS, 1 },
941 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
942 CPU_FSGSBASE_FLAGS, 0 },
943 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
944 CPU_RDRND_FLAGS, 0 },
945 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
949 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
951 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
953 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
955 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
957 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
958 CPU_MOVBE_FLAGS, 0 },
959 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
963 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
964 CPU_LZCNT_FLAGS, 0 },
965 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
970 CPU_INVPCID_FLAGS, 0 },
971 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
972 CPU_CLFLUSH_FLAGS, 0 },
973 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
975 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
976 CPU_SYSCALL_FLAGS, 0 },
977 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
978 CPU_RDTSCP_FLAGS, 0 },
979 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
980 CPU_3DNOW_FLAGS, 0 },
981 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
982 CPU_3DNOWA_FLAGS, 0 },
983 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
984 CPU_PADLOCK_FLAGS, 0 },
985 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
990 CPU_SSE4A_FLAGS, 0 },
991 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
993 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
995 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
997 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
999 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1000 CPU_RDSEED_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1002 CPU_PRFCHW_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1004 CPU_SMAP_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1007 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1009 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1010 CPU_CLFLUSHOPT_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1012 CPU_PREFETCHWT1_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1015 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1016 CPU_CLWB_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1018 CPU_AVX512IFMA_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1020 CPU_AVX512VBMI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1022 CPU_AVX512_4FMAPS_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1024 CPU_AVX512_4VNNIW_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1026 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1028 CPU_AVX512_VBMI2_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1030 CPU_AVX512_VNNI_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1032 CPU_AVX512_BITALG_FLAGS, 0 },
1033 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1034 CPU_CLZERO_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1036 CPU_MWAITX_FLAGS, 0 },
1037 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1038 CPU_OSPKE_FLAGS, 0 },
1039 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1040 CPU_RDPID_FLAGS, 0 },
1041 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1042 CPU_PTWRITE_FLAGS, 0 },
1043 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1045 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1046 CPU_SHSTK_FLAGS, 0 },
1047 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1048 CPU_GFNI_FLAGS, 0 },
1049 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1050 CPU_VAES_FLAGS, 0 },
1051 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1052 CPU_VPCLMULQDQ_FLAGS, 0 },
1053 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1054 CPU_WBNOINVD_FLAGS, 0 },
1055 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1056 CPU_PCONFIG_FLAGS, 0 },
1057 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1058 CPU_WAITPKG_FLAGS, 0 },
1059 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1060 CPU_CLDEMOTE_FLAGS, 0 },
1061 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1062 CPU_MOVDIRI_FLAGS, 0 },
1063 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1064 CPU_MOVDIR64B_FLAGS, 0 },
1067 static const noarch_entry cpu_noarch[] =
1069 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1070 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1071 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1072 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1073 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1074 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1075 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1076 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1077 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1078 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1079 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1080 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1081 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1082 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1083 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1084 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1085 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1086 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1087 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1088 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1089 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1090 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1091 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1092 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1093 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1094 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1095 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1096 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1097 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1098 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1099 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1100 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1101 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1102 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1103 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1107 /* Like s_lcomm_internal in gas/read.c but the alignment string
1108 is allowed to be optional. */
1111 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1118 && *input_line_pointer == ',')
1120 align = parse_align (needs_align - 1);
1122 if (align == (addressT) -1)
1137 bss_alloc (symbolP, size, align);
1142 pe_lcomm (int needs_align)
1144 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1148 const pseudo_typeS md_pseudo_table[] =
1150 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1151 {"align", s_align_bytes, 0},
1153 {"align", s_align_ptwo, 0},
1155 {"arch", set_cpu_arch, 0},
1159 {"lcomm", pe_lcomm, 1},
1161 {"ffloat", float_cons, 'f'},
1162 {"dfloat", float_cons, 'd'},
1163 {"tfloat", float_cons, 'x'},
1165 {"slong", signed_cons, 4},
1166 {"noopt", s_ignore, 0},
1167 {"optim", s_ignore, 0},
1168 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1169 {"code16", set_code_flag, CODE_16BIT},
1170 {"code32", set_code_flag, CODE_32BIT},
1172 {"code64", set_code_flag, CODE_64BIT},
1174 {"intel_syntax", set_intel_syntax, 1},
1175 {"att_syntax", set_intel_syntax, 0},
1176 {"intel_mnemonic", set_intel_mnemonic, 1},
1177 {"att_mnemonic", set_intel_mnemonic, 0},
1178 {"allow_index_reg", set_allow_index_reg, 1},
1179 {"disallow_index_reg", set_allow_index_reg, 0},
1180 {"sse_check", set_check, 0},
1181 {"operand_check", set_check, 1},
1182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1183 {"largecomm", handle_large_common, 0},
1185 {"file", dwarf2_directive_file, 0},
1186 {"loc", dwarf2_directive_loc, 0},
1187 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1190 {"secrel32", pe_directive_secrel, 0},
1195 /* For interface with expression (). */
1196 extern char *input_line_pointer;
1198 /* Hash table for instruction mnemonic lookup. */
1199 static struct hash_control *op_hash;
1201 /* Hash table for register lookup. */
1202 static struct hash_control *reg_hash;
1204 /* Various efficient no-op patterns for aligning code labels.
1205 Note: Don't try to assemble the instructions in the comments.
1206 0L and 0w are not legal. */
1207 static const unsigned char f32_1[] =
1209 static const unsigned char f32_2[] =
1210 {0x66,0x90}; /* xchg %ax,%ax */
1211 static const unsigned char f32_3[] =
1212 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1213 static const unsigned char f32_4[] =
1214 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1215 static const unsigned char f32_6[] =
1216 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1217 static const unsigned char f32_7[] =
1218 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1219 static const unsigned char f16_3[] =
1220 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1221 static const unsigned char f16_4[] =
1222 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1223 static const unsigned char jump_disp8[] =
1224 {0xeb}; /* jmp disp8 */
1225 static const unsigned char jump32_disp32[] =
1226 {0xe9}; /* jmp disp32 */
1227 static const unsigned char jump16_disp32[] =
1228 {0x66,0xe9}; /* jmp disp32 */
1229 /* 32-bit NOPs patterns. */
1230 static const unsigned char *const f32_patt[] = {
1231 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1233 /* 16-bit NOPs patterns. */
1234 static const unsigned char *const f16_patt[] = {
1235 f32_1, f32_2, f16_3, f16_4
1237 /* nopl (%[re]ax) */
1238 static const unsigned char alt_3[] =
1240 /* nopl 0(%[re]ax) */
1241 static const unsigned char alt_4[] =
1242 {0x0f,0x1f,0x40,0x00};
1243 /* nopl 0(%[re]ax,%[re]ax,1) */
1244 static const unsigned char alt_5[] =
1245 {0x0f,0x1f,0x44,0x00,0x00};
1246 /* nopw 0(%[re]ax,%[re]ax,1) */
1247 static const unsigned char alt_6[] =
1248 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1249 /* nopl 0L(%[re]ax) */
1250 static const unsigned char alt_7[] =
1251 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1252 /* nopl 0L(%[re]ax,%[re]ax,1) */
1253 static const unsigned char alt_8[] =
1254 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1255 /* nopw 0L(%[re]ax,%[re]ax,1) */
1256 static const unsigned char alt_9[] =
1257 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1258 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1259 static const unsigned char alt_10[] =
1260 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1261 /* data16 nopw %cs:0L(%eax,%eax,1) */
1262 static const unsigned char alt_11[] =
1263 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1264 /* 32-bit and 64-bit NOPs patterns. */
1265 static const unsigned char *const alt_patt[] = {
1266 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1267 alt_9, alt_10, alt_11
1270 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1271 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1274 i386_output_nops (char *where, const unsigned char *const *patt,
1275 int count, int max_single_nop_size)
1278 /* Place the longer NOP first. */
1281 const unsigned char *nops = patt[max_single_nop_size - 1];
1283 /* Use the smaller one if the requsted one isn't available. */
1286 max_single_nop_size--;
1287 nops = patt[max_single_nop_size - 1];
1290 last = count % max_single_nop_size;
1293 for (offset = 0; offset < count; offset += max_single_nop_size)
1294 memcpy (where + offset, nops, max_single_nop_size);
1298 nops = patt[last - 1];
1301 /* Use the smaller one plus one-byte NOP if the needed one
1304 nops = patt[last - 1];
1305 memcpy (where + offset, nops, last);
1306 where[offset + last] = *patt[0];
1309 memcpy (where + offset, nops, last);
1314 fits_in_imm7 (offsetT num)
1316 return (num & 0x7f) == num;
1320 fits_in_imm31 (offsetT num)
1322 return (num & 0x7fffffff) == num;
1325 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1326 single NOP instruction LIMIT. */
1329 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1331 const unsigned char *const *patt = NULL;
1332 int max_single_nop_size;
1333 /* Maximum number of NOPs before switching to jump over NOPs. */
1334 int max_number_of_nops;
1336 switch (fragP->fr_type)
1345 /* We need to decide which NOP sequence to use for 32bit and
1346 64bit. When -mtune= is used:
1348 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1349 PROCESSOR_GENERIC32, f32_patt will be used.
1350 2. For the rest, alt_patt will be used.
1352 When -mtune= isn't used, alt_patt will be used if
1353 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1356 When -march= or .arch is used, we can't use anything beyond
1357 cpu_arch_isa_flags. */
1359 if (flag_code == CODE_16BIT)
1362 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1363 /* Limit number of NOPs to 2 in 16-bit mode. */
1364 max_number_of_nops = 2;
1368 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1370 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1371 switch (cpu_arch_tune)
1373 case PROCESSOR_UNKNOWN:
1374 /* We use cpu_arch_isa_flags to check if we SHOULD
1375 optimize with nops. */
1376 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1381 case PROCESSOR_PENTIUM4:
1382 case PROCESSOR_NOCONA:
1383 case PROCESSOR_CORE:
1384 case PROCESSOR_CORE2:
1385 case PROCESSOR_COREI7:
1386 case PROCESSOR_L1OM:
1387 case PROCESSOR_K1OM:
1388 case PROCESSOR_GENERIC64:
1390 case PROCESSOR_ATHLON:
1392 case PROCESSOR_AMDFAM10:
1394 case PROCESSOR_ZNVER:
1398 case PROCESSOR_I386:
1399 case PROCESSOR_I486:
1400 case PROCESSOR_PENTIUM:
1401 case PROCESSOR_PENTIUMPRO:
1402 case PROCESSOR_IAMCU:
1403 case PROCESSOR_GENERIC32:
1410 switch (fragP->tc_frag_data.tune)
1412 case PROCESSOR_UNKNOWN:
1413 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1414 PROCESSOR_UNKNOWN. */
1418 case PROCESSOR_I386:
1419 case PROCESSOR_I486:
1420 case PROCESSOR_PENTIUM:
1421 case PROCESSOR_IAMCU:
1423 case PROCESSOR_ATHLON:
1425 case PROCESSOR_AMDFAM10:
1427 case PROCESSOR_ZNVER:
1429 case PROCESSOR_GENERIC32:
1430 /* We use cpu_arch_isa_flags to check if we CAN optimize
1432 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1437 case PROCESSOR_PENTIUMPRO:
1438 case PROCESSOR_PENTIUM4:
1439 case PROCESSOR_NOCONA:
1440 case PROCESSOR_CORE:
1441 case PROCESSOR_CORE2:
1442 case PROCESSOR_COREI7:
1443 case PROCESSOR_L1OM:
1444 case PROCESSOR_K1OM:
1445 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1450 case PROCESSOR_GENERIC64:
1456 if (patt == f32_patt)
1458 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1459 /* Limit number of NOPs to 2 for older processors. */
1460 max_number_of_nops = 2;
1464 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1465 /* Limit number of NOPs to 7 for newer processors. */
1466 max_number_of_nops = 7;
1471 limit = max_single_nop_size;
1473 if (fragP->fr_type == rs_fill_nop)
1475 /* Output NOPs for .nop directive. */
1476 if (limit > max_single_nop_size)
1478 as_bad_where (fragP->fr_file, fragP->fr_line,
1479 _("invalid single nop size: %d "
1480 "(expect within [0, %d])"),
1481 limit, max_single_nop_size);
1486 fragP->fr_var = count;
1488 if ((count / max_single_nop_size) > max_number_of_nops)
1490 /* Generate jump over NOPs. */
1491 offsetT disp = count - 2;
1492 if (fits_in_imm7 (disp))
1494 /* Use "jmp disp8" if possible. */
1496 where[0] = jump_disp8[0];
1502 unsigned int size_of_jump;
1504 if (flag_code == CODE_16BIT)
1506 where[0] = jump16_disp32[0];
1507 where[1] = jump16_disp32[1];
1512 where[0] = jump32_disp32[0];
1516 count -= size_of_jump + 4;
1517 if (!fits_in_imm31 (count))
1519 as_bad_where (fragP->fr_file, fragP->fr_line,
1520 _("jump over nop padding out of range"));
1524 md_number_to_chars (where + size_of_jump, count, 4);
1525 where += size_of_jump + 4;
1529 /* Generate multiple NOPs. */
1530 i386_output_nops (where, patt, count, limit);
1534 operand_type_all_zero (const union i386_operand_type *x)
1536 switch (ARRAY_SIZE(x->array))
1547 return !x->array[0];
1554 operand_type_set (union i386_operand_type *x, unsigned int v)
1556 switch (ARRAY_SIZE(x->array))
1574 operand_type_equal (const union i386_operand_type *x,
1575 const union i386_operand_type *y)
1577 switch (ARRAY_SIZE(x->array))
1580 if (x->array[2] != y->array[2])
1584 if (x->array[1] != y->array[1])
1588 return x->array[0] == y->array[0];
1596 cpu_flags_all_zero (const union i386_cpu_flags *x)
1598 switch (ARRAY_SIZE(x->array))
1613 return !x->array[0];
1620 cpu_flags_equal (const union i386_cpu_flags *x,
1621 const union i386_cpu_flags *y)
1623 switch (ARRAY_SIZE(x->array))
1626 if (x->array[3] != y->array[3])
1630 if (x->array[2] != y->array[2])
1634 if (x->array[1] != y->array[1])
1638 return x->array[0] == y->array[0];
1646 cpu_flags_check_cpu64 (i386_cpu_flags f)
1648 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1649 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1652 static INLINE i386_cpu_flags
1653 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1655 switch (ARRAY_SIZE (x.array))
1658 x.array [3] &= y.array [3];
1661 x.array [2] &= y.array [2];
1664 x.array [1] &= y.array [1];
1667 x.array [0] &= y.array [0];
1675 static INLINE i386_cpu_flags
1676 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1678 switch (ARRAY_SIZE (x.array))
1681 x.array [3] |= y.array [3];
1684 x.array [2] |= y.array [2];
1687 x.array [1] |= y.array [1];
1690 x.array [0] |= y.array [0];
1698 static INLINE i386_cpu_flags
1699 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1701 switch (ARRAY_SIZE (x.array))
1704 x.array [3] &= ~y.array [3];
1707 x.array [2] &= ~y.array [2];
1710 x.array [1] &= ~y.array [1];
1713 x.array [0] &= ~y.array [0];
1721 #define CPU_FLAGS_ARCH_MATCH 0x1
1722 #define CPU_FLAGS_64BIT_MATCH 0x2
1724 #define CPU_FLAGS_PERFECT_MATCH \
1725 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1727 /* Return CPU flags match bits. */
1730 cpu_flags_match (const insn_template *t)
1732 i386_cpu_flags x = t->cpu_flags;
1733 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1735 x.bitfield.cpu64 = 0;
1736 x.bitfield.cpuno64 = 0;
1738 if (cpu_flags_all_zero (&x))
1740 /* This instruction is available on all archs. */
1741 match |= CPU_FLAGS_ARCH_MATCH;
1745 /* This instruction is available only on some archs. */
1746 i386_cpu_flags cpu = cpu_arch_flags;
1748 /* AVX512VL is no standalone feature - match it and then strip it. */
1749 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1751 x.bitfield.cpuavx512vl = 0;
1753 cpu = cpu_flags_and (x, cpu);
1754 if (!cpu_flags_all_zero (&cpu))
1756 if (x.bitfield.cpuavx)
1758 /* We need to check a few extra flags with AVX. */
1759 if (cpu.bitfield.cpuavx
1760 && (!t->opcode_modifier.sse2avx || sse2avx)
1761 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1762 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1763 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1764 match |= CPU_FLAGS_ARCH_MATCH;
1766 else if (x.bitfield.cpuavx512f)
1768 /* We need to check a few extra flags with AVX512F. */
1769 if (cpu.bitfield.cpuavx512f
1770 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1771 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1772 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1773 match |= CPU_FLAGS_ARCH_MATCH;
1776 match |= CPU_FLAGS_ARCH_MATCH;
1782 static INLINE i386_operand_type
1783 operand_type_and (i386_operand_type x, i386_operand_type y)
1785 switch (ARRAY_SIZE (x.array))
1788 x.array [2] &= y.array [2];
1791 x.array [1] &= y.array [1];
1794 x.array [0] &= y.array [0];
1802 static INLINE i386_operand_type
1803 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1805 switch (ARRAY_SIZE (x.array))
1808 x.array [2] &= ~y.array [2];
1811 x.array [1] &= ~y.array [1];
1814 x.array [0] &= ~y.array [0];
1822 static INLINE i386_operand_type
1823 operand_type_or (i386_operand_type x, i386_operand_type y)
1825 switch (ARRAY_SIZE (x.array))
1828 x.array [2] |= y.array [2];
1831 x.array [1] |= y.array [1];
1834 x.array [0] |= y.array [0];
1842 static INLINE i386_operand_type
1843 operand_type_xor (i386_operand_type x, i386_operand_type y)
1845 switch (ARRAY_SIZE (x.array))
1848 x.array [2] ^= y.array [2];
1851 x.array [1] ^= y.array [1];
1854 x.array [0] ^= y.array [0];
1862 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1863 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1864 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1865 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1866 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1867 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1868 static const i386_operand_type anydisp
1869 = OPERAND_TYPE_ANYDISP;
1870 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1871 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1872 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1873 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1874 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1875 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1876 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1877 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1878 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1879 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1880 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1881 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1892 operand_type_check (i386_operand_type t, enum operand_type c)
1897 return t.bitfield.reg;
1900 return (t.bitfield.imm8
1904 || t.bitfield.imm32s
1905 || t.bitfield.imm64);
1908 return (t.bitfield.disp8
1909 || t.bitfield.disp16
1910 || t.bitfield.disp32
1911 || t.bitfield.disp32s
1912 || t.bitfield.disp64);
1915 return (t.bitfield.disp8
1916 || t.bitfield.disp16
1917 || t.bitfield.disp32
1918 || t.bitfield.disp32s
1919 || t.bitfield.disp64
1920 || t.bitfield.baseindex);
1929 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1930 between operand GIVEN and opeand WANTED for instruction template T. */
1933 match_operand_size (const insn_template *t, unsigned int wanted,
1936 return !((i.types[given].bitfield.byte
1937 && !t->operand_types[wanted].bitfield.byte)
1938 || (i.types[given].bitfield.word
1939 && !t->operand_types[wanted].bitfield.word)
1940 || (i.types[given].bitfield.dword
1941 && !t->operand_types[wanted].bitfield.dword)
1942 || (i.types[given].bitfield.qword
1943 && !t->operand_types[wanted].bitfield.qword)
1944 || (i.types[given].bitfield.tbyte
1945 && !t->operand_types[wanted].bitfield.tbyte));
1948 /* Return 1 if there is no conflict in SIMD register between operand
1949 GIVEN and opeand WANTED for instruction template T. */
1952 match_simd_size (const insn_template *t, unsigned int wanted,
1955 return !((i.types[given].bitfield.xmmword
1956 && !t->operand_types[wanted].bitfield.xmmword)
1957 || (i.types[given].bitfield.ymmword
1958 && !t->operand_types[wanted].bitfield.ymmword)
1959 || (i.types[given].bitfield.zmmword
1960 && !t->operand_types[wanted].bitfield.zmmword));
1963 /* Return 1 if there is no conflict in any size between operand GIVEN
1964 and opeand WANTED for instruction template T. */
1967 match_mem_size (const insn_template *t, unsigned int wanted,
1970 return (match_operand_size (t, wanted, given)
1971 && !((i.types[given].bitfield.unspecified
1973 && !t->operand_types[wanted].bitfield.unspecified)
1974 || (i.types[given].bitfield.fword
1975 && !t->operand_types[wanted].bitfield.fword)
1976 /* For scalar opcode templates to allow register and memory
1977 operands at the same time, some special casing is needed
1978 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1979 down-conversion vpmov*. */
1980 || ((t->operand_types[wanted].bitfield.regsimd
1981 && !t->opcode_modifier.broadcast
1982 && (t->operand_types[wanted].bitfield.byte
1983 || t->operand_types[wanted].bitfield.word
1984 || t->operand_types[wanted].bitfield.dword
1985 || t->operand_types[wanted].bitfield.qword))
1986 ? (i.types[given].bitfield.xmmword
1987 || i.types[given].bitfield.ymmword
1988 || i.types[given].bitfield.zmmword)
1989 : !match_simd_size(t, wanted, given))));
1992 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1993 operands for instruction template T, and it has MATCH_REVERSE set if there
1994 is no size conflict on any operands for the template with operands reversed
1995 (and the template allows for reversing in the first place). */
1997 #define MATCH_STRAIGHT 1
1998 #define MATCH_REVERSE 2
2000 static INLINE unsigned int
2001 operand_size_match (const insn_template *t)
2003 unsigned int j, match = MATCH_STRAIGHT;
2005 /* Don't check jump instructions. */
2006 if (t->opcode_modifier.jump
2007 || t->opcode_modifier.jumpbyte
2008 || t->opcode_modifier.jumpdword
2009 || t->opcode_modifier.jumpintersegment)
2012 /* Check memory and accumulator operand size. */
2013 for (j = 0; j < i.operands; j++)
2015 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2016 && t->operand_types[j].bitfield.anysize)
2019 if (t->operand_types[j].bitfield.reg
2020 && !match_operand_size (t, j, j))
2026 if (t->operand_types[j].bitfield.regsimd
2027 && !match_simd_size (t, j, j))
2033 if (t->operand_types[j].bitfield.acc
2034 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2040 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2047 if (!t->opcode_modifier.d)
2051 i.error = operand_size_mismatch;
2055 /* Check reverse. */
2056 gas_assert (i.operands == 2);
2058 for (j = 0; j < 2; j++)
2060 if ((t->operand_types[j].bitfield.reg
2061 || t->operand_types[j].bitfield.acc)
2062 && !match_operand_size (t, j, !j))
2065 if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
2069 return match | MATCH_REVERSE;
2073 operand_type_match (i386_operand_type overlap,
2074 i386_operand_type given)
2076 i386_operand_type temp = overlap;
2078 temp.bitfield.jumpabsolute = 0;
2079 temp.bitfield.unspecified = 0;
2080 temp.bitfield.byte = 0;
2081 temp.bitfield.word = 0;
2082 temp.bitfield.dword = 0;
2083 temp.bitfield.fword = 0;
2084 temp.bitfield.qword = 0;
2085 temp.bitfield.tbyte = 0;
2086 temp.bitfield.xmmword = 0;
2087 temp.bitfield.ymmword = 0;
2088 temp.bitfield.zmmword = 0;
2089 if (operand_type_all_zero (&temp))
2092 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2093 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2097 i.error = operand_type_mismatch;
2101 /* If given types g0 and g1 are registers they must be of the same type
2102 unless the expected operand type register overlap is null.
2103 Memory operand size of certain SIMD instructions is also being checked
2107 operand_type_register_match (i386_operand_type g0,
2108 i386_operand_type t0,
2109 i386_operand_type g1,
2110 i386_operand_type t1)
2112 if (!g0.bitfield.reg
2113 && !g0.bitfield.regsimd
2114 && (!operand_type_check (g0, anymem)
2115 || g0.bitfield.unspecified
2116 || !t0.bitfield.regsimd))
2119 if (!g1.bitfield.reg
2120 && !g1.bitfield.regsimd
2121 && (!operand_type_check (g1, anymem)
2122 || g1.bitfield.unspecified
2123 || !t1.bitfield.regsimd))
2126 if (g0.bitfield.byte == g1.bitfield.byte
2127 && g0.bitfield.word == g1.bitfield.word
2128 && g0.bitfield.dword == g1.bitfield.dword
2129 && g0.bitfield.qword == g1.bitfield.qword
2130 && g0.bitfield.xmmword == g1.bitfield.xmmword
2131 && g0.bitfield.ymmword == g1.bitfield.ymmword
2132 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2135 if (!(t0.bitfield.byte & t1.bitfield.byte)
2136 && !(t0.bitfield.word & t1.bitfield.word)
2137 && !(t0.bitfield.dword & t1.bitfield.dword)
2138 && !(t0.bitfield.qword & t1.bitfield.qword)
2139 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2140 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2141 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2144 i.error = register_type_mismatch;
2149 static INLINE unsigned int
2150 register_number (const reg_entry *r)
2152 unsigned int nr = r->reg_num;
2154 if (r->reg_flags & RegRex)
2157 if (r->reg_flags & RegVRex)
2163 static INLINE unsigned int
2164 mode_from_disp_size (i386_operand_type t)
2166 if (t.bitfield.disp8)
2168 else if (t.bitfield.disp16
2169 || t.bitfield.disp32
2170 || t.bitfield.disp32s)
2177 fits_in_signed_byte (addressT num)
2179 return num + 0x80 <= 0xff;
2183 fits_in_unsigned_byte (addressT num)
2189 fits_in_unsigned_word (addressT num)
2191 return num <= 0xffff;
2195 fits_in_signed_word (addressT num)
2197 return num + 0x8000 <= 0xffff;
2201 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2206 return num + 0x80000000 <= 0xffffffff;
2208 } /* fits_in_signed_long() */
2211 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2216 return num <= 0xffffffff;
2218 } /* fits_in_unsigned_long() */
2221 fits_in_disp8 (offsetT num)
2223 int shift = i.memshift;
2229 mask = (1 << shift) - 1;
2231 /* Return 0 if NUM isn't properly aligned. */
2235 /* Check if NUM will fit in 8bit after shift. */
2236 return fits_in_signed_byte (num >> shift);
2240 fits_in_imm4 (offsetT num)
2242 return (num & 0xf) == num;
2245 static i386_operand_type
2246 smallest_imm_type (offsetT num)
2248 i386_operand_type t;
2250 operand_type_set (&t, 0);
2251 t.bitfield.imm64 = 1;
2253 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2255 /* This code is disabled on the 486 because all the Imm1 forms
2256 in the opcode table are slower on the i486. They're the
2257 versions with the implicitly specified single-position
2258 displacement, which has another syntax if you really want to
2260 t.bitfield.imm1 = 1;
2261 t.bitfield.imm8 = 1;
2262 t.bitfield.imm8s = 1;
2263 t.bitfield.imm16 = 1;
2264 t.bitfield.imm32 = 1;
2265 t.bitfield.imm32s = 1;
2267 else if (fits_in_signed_byte (num))
2269 t.bitfield.imm8 = 1;
2270 t.bitfield.imm8s = 1;
2271 t.bitfield.imm16 = 1;
2272 t.bitfield.imm32 = 1;
2273 t.bitfield.imm32s = 1;
2275 else if (fits_in_unsigned_byte (num))
2277 t.bitfield.imm8 = 1;
2278 t.bitfield.imm16 = 1;
2279 t.bitfield.imm32 = 1;
2280 t.bitfield.imm32s = 1;
2282 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2284 t.bitfield.imm16 = 1;
2285 t.bitfield.imm32 = 1;
2286 t.bitfield.imm32s = 1;
2288 else if (fits_in_signed_long (num))
2290 t.bitfield.imm32 = 1;
2291 t.bitfield.imm32s = 1;
2293 else if (fits_in_unsigned_long (num))
2294 t.bitfield.imm32 = 1;
2300 offset_in_range (offsetT val, int size)
2306 case 1: mask = ((addressT) 1 << 8) - 1; break;
2307 case 2: mask = ((addressT) 1 << 16) - 1; break;
2308 case 4: mask = ((addressT) 2 << 31) - 1; break;
2310 case 8: mask = ((addressT) 2 << 63) - 1; break;
2316 /* If BFD64, sign extend val for 32bit address mode. */
2317 if (flag_code != CODE_64BIT
2318 || i.prefix[ADDR_PREFIX])
2319 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2320 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2323 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2325 char buf1[40], buf2[40];
2327 sprint_value (buf1, val);
2328 sprint_value (buf2, val & mask);
2329 as_warn (_("%s shortened to %s"), buf1, buf2);
2344 a. PREFIX_EXIST if attempting to add a prefix where one from the
2345 same class already exists.
2346 b. PREFIX_LOCK if lock prefix is added.
2347 c. PREFIX_REP if rep/repne prefix is added.
2348 d. PREFIX_DS if ds prefix is added.
2349 e. PREFIX_OTHER if other prefix is added.
2352 static enum PREFIX_GROUP
2353 add_prefix (unsigned int prefix)
2355 enum PREFIX_GROUP ret = PREFIX_OTHER;
2358 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2359 && flag_code == CODE_64BIT)
2361 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2362 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2363 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2364 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2375 case DS_PREFIX_OPCODE:
2378 case CS_PREFIX_OPCODE:
2379 case ES_PREFIX_OPCODE:
2380 case FS_PREFIX_OPCODE:
2381 case GS_PREFIX_OPCODE:
2382 case SS_PREFIX_OPCODE:
2386 case REPNE_PREFIX_OPCODE:
2387 case REPE_PREFIX_OPCODE:
2392 case LOCK_PREFIX_OPCODE:
2401 case ADDR_PREFIX_OPCODE:
2405 case DATA_PREFIX_OPCODE:
2409 if (i.prefix[q] != 0)
2417 i.prefix[q] |= prefix;
2420 as_bad (_("same type of prefix used twice"));
2426 update_code_flag (int value, int check)
2428 PRINTF_LIKE ((*as_error));
2430 flag_code = (enum flag_code) value;
2431 if (flag_code == CODE_64BIT)
2433 cpu_arch_flags.bitfield.cpu64 = 1;
2434 cpu_arch_flags.bitfield.cpuno64 = 0;
2438 cpu_arch_flags.bitfield.cpu64 = 0;
2439 cpu_arch_flags.bitfield.cpuno64 = 1;
2441 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2444 as_error = as_fatal;
2447 (*as_error) (_("64bit mode not supported on `%s'."),
2448 cpu_arch_name ? cpu_arch_name : default_arch);
2450 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2453 as_error = as_fatal;
2456 (*as_error) (_("32bit mode not supported on `%s'."),
2457 cpu_arch_name ? cpu_arch_name : default_arch);
2459 stackop_size = '\0';
2463 set_code_flag (int value)
2465 update_code_flag (value, 0);
2469 set_16bit_gcc_code_flag (int new_code_flag)
2471 flag_code = (enum flag_code) new_code_flag;
2472 if (flag_code != CODE_16BIT)
2474 cpu_arch_flags.bitfield.cpu64 = 0;
2475 cpu_arch_flags.bitfield.cpuno64 = 1;
2476 stackop_size = LONG_MNEM_SUFFIX;
2480 set_intel_syntax (int syntax_flag)
2482 /* Find out if register prefixing is specified. */
2483 int ask_naked_reg = 0;
2486 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2489 int e = get_symbol_name (&string);
2491 if (strcmp (string, "prefix") == 0)
2493 else if (strcmp (string, "noprefix") == 0)
2496 as_bad (_("bad argument to syntax directive."));
2497 (void) restore_line_pointer (e);
2499 demand_empty_rest_of_line ();
2501 intel_syntax = syntax_flag;
2503 if (ask_naked_reg == 0)
2504 allow_naked_reg = (intel_syntax
2505 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2507 allow_naked_reg = (ask_naked_reg < 0);
2509 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2511 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2512 identifier_chars['$'] = intel_syntax ? '$' : 0;
2513 register_prefix = allow_naked_reg ? "" : "%";
2517 set_intel_mnemonic (int mnemonic_flag)
2519 intel_mnemonic = mnemonic_flag;
2523 set_allow_index_reg (int flag)
2525 allow_index_reg = flag;
2529 set_check (int what)
2531 enum check_kind *kind;
2536 kind = &operand_check;
2547 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2550 int e = get_symbol_name (&string);
2552 if (strcmp (string, "none") == 0)
2554 else if (strcmp (string, "warning") == 0)
2555 *kind = check_warning;
2556 else if (strcmp (string, "error") == 0)
2557 *kind = check_error;
2559 as_bad (_("bad argument to %s_check directive."), str);
2560 (void) restore_line_pointer (e);
2563 as_bad (_("missing argument for %s_check directive"), str);
2565 demand_empty_rest_of_line ();
2569 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2570 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2573 static const char *arch;
2575 /* Intel LIOM is only supported on ELF. */
2581 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2582 use default_arch. */
2583 arch = cpu_arch_name;
2585 arch = default_arch;
2588 /* If we are targeting Intel MCU, we must enable it. */
2589 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2590 || new_flag.bitfield.cpuiamcu)
2593 /* If we are targeting Intel L1OM, we must enable it. */
2594 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2595 || new_flag.bitfield.cpul1om)
2598 /* If we are targeting Intel K1OM, we must enable it. */
2599 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2600 || new_flag.bitfield.cpuk1om)
2603 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2608 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2612 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2615 int e = get_symbol_name (&string);
2617 i386_cpu_flags flags;
2619 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2621 if (strcmp (string, cpu_arch[j].name) == 0)
2623 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2627 cpu_arch_name = cpu_arch[j].name;
2628 cpu_sub_arch_name = NULL;
2629 cpu_arch_flags = cpu_arch[j].flags;
2630 if (flag_code == CODE_64BIT)
2632 cpu_arch_flags.bitfield.cpu64 = 1;
2633 cpu_arch_flags.bitfield.cpuno64 = 0;
2637 cpu_arch_flags.bitfield.cpu64 = 0;
2638 cpu_arch_flags.bitfield.cpuno64 = 1;
2640 cpu_arch_isa = cpu_arch[j].type;
2641 cpu_arch_isa_flags = cpu_arch[j].flags;
2642 if (!cpu_arch_tune_set)
2644 cpu_arch_tune = cpu_arch_isa;
2645 cpu_arch_tune_flags = cpu_arch_isa_flags;
2650 flags = cpu_flags_or (cpu_arch_flags,
2653 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2655 if (cpu_sub_arch_name)
2657 char *name = cpu_sub_arch_name;
2658 cpu_sub_arch_name = concat (name,
2660 (const char *) NULL);
2664 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2665 cpu_arch_flags = flags;
2666 cpu_arch_isa_flags = flags;
2670 = cpu_flags_or (cpu_arch_isa_flags,
2672 (void) restore_line_pointer (e);
2673 demand_empty_rest_of_line ();
2678 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2680 /* Disable an ISA extension. */
2681 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2682 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2684 flags = cpu_flags_and_not (cpu_arch_flags,
2685 cpu_noarch[j].flags);
2686 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2688 if (cpu_sub_arch_name)
2690 char *name = cpu_sub_arch_name;
2691 cpu_sub_arch_name = concat (name, string,
2692 (const char *) NULL);
2696 cpu_sub_arch_name = xstrdup (string);
2697 cpu_arch_flags = flags;
2698 cpu_arch_isa_flags = flags;
2700 (void) restore_line_pointer (e);
2701 demand_empty_rest_of_line ();
2705 j = ARRAY_SIZE (cpu_arch);
2708 if (j >= ARRAY_SIZE (cpu_arch))
2709 as_bad (_("no such architecture: `%s'"), string);
2711 *input_line_pointer = e;
2714 as_bad (_("missing cpu architecture"));
2716 no_cond_jump_promotion = 0;
2717 if (*input_line_pointer == ','
2718 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2723 ++input_line_pointer;
2724 e = get_symbol_name (&string);
2726 if (strcmp (string, "nojumps") == 0)
2727 no_cond_jump_promotion = 1;
2728 else if (strcmp (string, "jumps") == 0)
2731 as_bad (_("no such architecture modifier: `%s'"), string);
2733 (void) restore_line_pointer (e);
2736 demand_empty_rest_of_line ();
2739 enum bfd_architecture
2742 if (cpu_arch_isa == PROCESSOR_L1OM)
2744 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2745 || flag_code != CODE_64BIT)
2746 as_fatal (_("Intel L1OM is 64bit ELF only"));
2747 return bfd_arch_l1om;
2749 else if (cpu_arch_isa == PROCESSOR_K1OM)
2751 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2752 || flag_code != CODE_64BIT)
2753 as_fatal (_("Intel K1OM is 64bit ELF only"));
2754 return bfd_arch_k1om;
2756 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2758 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2759 || flag_code == CODE_64BIT)
2760 as_fatal (_("Intel MCU is 32bit ELF only"));
2761 return bfd_arch_iamcu;
2764 return bfd_arch_i386;
2770 if (!strncmp (default_arch, "x86_64", 6))
2772 if (cpu_arch_isa == PROCESSOR_L1OM)
2774 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2775 || default_arch[6] != '\0')
2776 as_fatal (_("Intel L1OM is 64bit ELF only"));
2777 return bfd_mach_l1om;
2779 else if (cpu_arch_isa == PROCESSOR_K1OM)
2781 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2782 || default_arch[6] != '\0')
2783 as_fatal (_("Intel K1OM is 64bit ELF only"));
2784 return bfd_mach_k1om;
2786 else if (default_arch[6] == '\0')
2787 return bfd_mach_x86_64;
2789 return bfd_mach_x64_32;
2791 else if (!strcmp (default_arch, "i386")
2792 || !strcmp (default_arch, "iamcu"))
2794 if (cpu_arch_isa == PROCESSOR_IAMCU)
2796 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2797 as_fatal (_("Intel MCU is 32bit ELF only"));
2798 return bfd_mach_i386_iamcu;
2801 return bfd_mach_i386_i386;
2804 as_fatal (_("unknown architecture"));
2810 const char *hash_err;
2812 /* Support pseudo prefixes like {disp32}. */
2813 lex_type ['{'] = LEX_BEGIN_NAME;
2815 /* Initialize op_hash hash table. */
2816 op_hash = hash_new ();
2819 const insn_template *optab;
2820 templates *core_optab;
2822 /* Setup for loop. */
2824 core_optab = XNEW (templates);
2825 core_optab->start = optab;
2830 if (optab->name == NULL
2831 || strcmp (optab->name, (optab - 1)->name) != 0)
2833 /* different name --> ship out current template list;
2834 add to hash table; & begin anew. */
2835 core_optab->end = optab;
2836 hash_err = hash_insert (op_hash,
2838 (void *) core_optab);
2841 as_fatal (_("can't hash %s: %s"),
2845 if (optab->name == NULL)
2847 core_optab = XNEW (templates);
2848 core_optab->start = optab;
2853 /* Initialize reg_hash hash table. */
2854 reg_hash = hash_new ();
2856 const reg_entry *regtab;
2857 unsigned int regtab_size = i386_regtab_size;
2859 for (regtab = i386_regtab; regtab_size--; regtab++)
2861 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2863 as_fatal (_("can't hash %s: %s"),
2869 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2874 for (c = 0; c < 256; c++)
2879 mnemonic_chars[c] = c;
2880 register_chars[c] = c;
2881 operand_chars[c] = c;
2883 else if (ISLOWER (c))
2885 mnemonic_chars[c] = c;
2886 register_chars[c] = c;
2887 operand_chars[c] = c;
2889 else if (ISUPPER (c))
2891 mnemonic_chars[c] = TOLOWER (c);
2892 register_chars[c] = mnemonic_chars[c];
2893 operand_chars[c] = c;
2895 else if (c == '{' || c == '}')
2897 mnemonic_chars[c] = c;
2898 operand_chars[c] = c;
2901 if (ISALPHA (c) || ISDIGIT (c))
2902 identifier_chars[c] = c;
2905 identifier_chars[c] = c;
2906 operand_chars[c] = c;
2911 identifier_chars['@'] = '@';
2914 identifier_chars['?'] = '?';
2915 operand_chars['?'] = '?';
2917 digit_chars['-'] = '-';
2918 mnemonic_chars['_'] = '_';
2919 mnemonic_chars['-'] = '-';
2920 mnemonic_chars['.'] = '.';
2921 identifier_chars['_'] = '_';
2922 identifier_chars['.'] = '.';
2924 for (p = operand_special_chars; *p != '\0'; p++)
2925 operand_chars[(unsigned char) *p] = *p;
2928 if (flag_code == CODE_64BIT)
2930 #if defined (OBJ_COFF) && defined (TE_PE)
2931 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2934 x86_dwarf2_return_column = 16;
2936 x86_cie_data_alignment = -8;
2940 x86_dwarf2_return_column = 8;
2941 x86_cie_data_alignment = -4;
2946 i386_print_statistics (FILE *file)
2948 hash_print_statistics (file, "i386 opcode", op_hash);
2949 hash_print_statistics (file, "i386 register", reg_hash);
2954 /* Debugging routines for md_assemble. */
2955 static void pte (insn_template *);
2956 static void pt (i386_operand_type);
2957 static void pe (expressionS *);
2958 static void ps (symbolS *);
2961 pi (char *line, i386_insn *x)
2965 fprintf (stdout, "%s: template ", line);
2967 fprintf (stdout, " address: base %s index %s scale %x\n",
2968 x->base_reg ? x->base_reg->reg_name : "none",
2969 x->index_reg ? x->index_reg->reg_name : "none",
2970 x->log2_scale_factor);
2971 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2972 x->rm.mode, x->rm.reg, x->rm.regmem);
2973 fprintf (stdout, " sib: base %x index %x scale %x\n",
2974 x->sib.base, x->sib.index, x->sib.scale);
2975 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2976 (x->rex & REX_W) != 0,
2977 (x->rex & REX_R) != 0,
2978 (x->rex & REX_X) != 0,
2979 (x->rex & REX_B) != 0);
2980 for (j = 0; j < x->operands; j++)
2982 fprintf (stdout, " #%d: ", j + 1);
2984 fprintf (stdout, "\n");
2985 if (x->types[j].bitfield.reg
2986 || x->types[j].bitfield.regmmx
2987 || x->types[j].bitfield.regsimd
2988 || x->types[j].bitfield.sreg2
2989 || x->types[j].bitfield.sreg3
2990 || x->types[j].bitfield.control
2991 || x->types[j].bitfield.debug
2992 || x->types[j].bitfield.test)
2993 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2994 if (operand_type_check (x->types[j], imm))
2996 if (operand_type_check (x->types[j], disp))
2997 pe (x->op[j].disps);
3002 pte (insn_template *t)
3005 fprintf (stdout, " %d operands ", t->operands);
3006 fprintf (stdout, "opcode %x ", t->base_opcode);
3007 if (t->extension_opcode != None)
3008 fprintf (stdout, "ext %x ", t->extension_opcode);
3009 if (t->opcode_modifier.d)
3010 fprintf (stdout, "D");
3011 if (t->opcode_modifier.w)
3012 fprintf (stdout, "W");
3013 fprintf (stdout, "\n");
3014 for (j = 0; j < t->operands; j++)
3016 fprintf (stdout, " #%d type ", j + 1);
3017 pt (t->operand_types[j]);
3018 fprintf (stdout, "\n");
3025 fprintf (stdout, " operation %d\n", e->X_op);
3026 fprintf (stdout, " add_number %ld (%lx)\n",
3027 (long) e->X_add_number, (long) e->X_add_number);
3028 if (e->X_add_symbol)
3030 fprintf (stdout, " add_symbol ");
3031 ps (e->X_add_symbol);
3032 fprintf (stdout, "\n");
3036 fprintf (stdout, " op_symbol ");
3037 ps (e->X_op_symbol);
3038 fprintf (stdout, "\n");
3045 fprintf (stdout, "%s type %s%s",
3047 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3048 segment_name (S_GET_SEGMENT (s)));
3051 static struct type_name
3053 i386_operand_type mask;
3056 const type_names[] =
3058 { OPERAND_TYPE_REG8, "r8" },
3059 { OPERAND_TYPE_REG16, "r16" },
3060 { OPERAND_TYPE_REG32, "r32" },
3061 { OPERAND_TYPE_REG64, "r64" },
3062 { OPERAND_TYPE_IMM8, "i8" },
3063 { OPERAND_TYPE_IMM8, "i8s" },
3064 { OPERAND_TYPE_IMM16, "i16" },
3065 { OPERAND_TYPE_IMM32, "i32" },
3066 { OPERAND_TYPE_IMM32S, "i32s" },
3067 { OPERAND_TYPE_IMM64, "i64" },
3068 { OPERAND_TYPE_IMM1, "i1" },
3069 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3070 { OPERAND_TYPE_DISP8, "d8" },
3071 { OPERAND_TYPE_DISP16, "d16" },
3072 { OPERAND_TYPE_DISP32, "d32" },
3073 { OPERAND_TYPE_DISP32S, "d32s" },
3074 { OPERAND_TYPE_DISP64, "d64" },
3075 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3076 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3077 { OPERAND_TYPE_CONTROL, "control reg" },
3078 { OPERAND_TYPE_TEST, "test reg" },
3079 { OPERAND_TYPE_DEBUG, "debug reg" },
3080 { OPERAND_TYPE_FLOATREG, "FReg" },
3081 { OPERAND_TYPE_FLOATACC, "FAcc" },
3082 { OPERAND_TYPE_SREG2, "SReg2" },
3083 { OPERAND_TYPE_SREG3, "SReg3" },
3084 { OPERAND_TYPE_ACC, "Acc" },
3085 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3086 { OPERAND_TYPE_REGMMX, "rMMX" },
3087 { OPERAND_TYPE_REGXMM, "rXMM" },
3088 { OPERAND_TYPE_REGYMM, "rYMM" },
3089 { OPERAND_TYPE_REGZMM, "rZMM" },
3090 { OPERAND_TYPE_REGMASK, "Mask reg" },
3091 { OPERAND_TYPE_ESSEG, "es" },
3095 pt (i386_operand_type t)
3098 i386_operand_type a;
3100 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3102 a = operand_type_and (t, type_names[j].mask);
3103 if (!operand_type_all_zero (&a))
3104 fprintf (stdout, "%s, ", type_names[j].name);
3109 #endif /* DEBUG386 */
3111 static bfd_reloc_code_real_type
3112 reloc (unsigned int size,
3115 bfd_reloc_code_real_type other)
3117 if (other != NO_RELOC)
3119 reloc_howto_type *rel;
3124 case BFD_RELOC_X86_64_GOT32:
3125 return BFD_RELOC_X86_64_GOT64;
3127 case BFD_RELOC_X86_64_GOTPLT64:
3128 return BFD_RELOC_X86_64_GOTPLT64;
3130 case BFD_RELOC_X86_64_PLTOFF64:
3131 return BFD_RELOC_X86_64_PLTOFF64;
3133 case BFD_RELOC_X86_64_GOTPC32:
3134 other = BFD_RELOC_X86_64_GOTPC64;
3136 case BFD_RELOC_X86_64_GOTPCREL:
3137 other = BFD_RELOC_X86_64_GOTPCREL64;
3139 case BFD_RELOC_X86_64_TPOFF32:
3140 other = BFD_RELOC_X86_64_TPOFF64;
3142 case BFD_RELOC_X86_64_DTPOFF32:
3143 other = BFD_RELOC_X86_64_DTPOFF64;
3149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3150 if (other == BFD_RELOC_SIZE32)
3153 other = BFD_RELOC_SIZE64;
3156 as_bad (_("there are no pc-relative size relocations"));
3162 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3163 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3166 rel = bfd_reloc_type_lookup (stdoutput, other);
3168 as_bad (_("unknown relocation (%u)"), other);
3169 else if (size != bfd_get_reloc_size (rel))
3170 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3171 bfd_get_reloc_size (rel),
3173 else if (pcrel && !rel->pc_relative)
3174 as_bad (_("non-pc-relative relocation for pc-relative field"));
3175 else if ((rel->complain_on_overflow == complain_overflow_signed
3177 || (rel->complain_on_overflow == complain_overflow_unsigned
3179 as_bad (_("relocated field and relocation type differ in signedness"));
3188 as_bad (_("there are no unsigned pc-relative relocations"));
3191 case 1: return BFD_RELOC_8_PCREL;
3192 case 2: return BFD_RELOC_16_PCREL;
3193 case 4: return BFD_RELOC_32_PCREL;
3194 case 8: return BFD_RELOC_64_PCREL;
3196 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3203 case 4: return BFD_RELOC_X86_64_32S;
3208 case 1: return BFD_RELOC_8;
3209 case 2: return BFD_RELOC_16;
3210 case 4: return BFD_RELOC_32;
3211 case 8: return BFD_RELOC_64;
3213 as_bad (_("cannot do %s %u byte relocation"),
3214 sign > 0 ? "signed" : "unsigned", size);
3220 /* Here we decide which fixups can be adjusted to make them relative to
3221 the beginning of the section instead of the symbol. Basically we need
3222 to make sure that the dynamic relocations are done correctly, so in
3223 some cases we force the original symbol to be used. */
3226 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3232 /* Don't adjust pc-relative references to merge sections in 64-bit
3234 if (use_rela_relocations
3235 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3239 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3240 and changed later by validate_fix. */
3241 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3242 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3245 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3246 for size relocations. */
3247 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3248 || fixP->fx_r_type == BFD_RELOC_SIZE64
3249 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3250 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3251 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3252 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3253 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3254 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3255 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3256 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3257 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3258 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3259 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3260 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3261 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3262 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3263 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3264 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3265 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3266 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3267 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3268 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3269 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3270 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3271 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3272 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3273 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3274 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3275 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3276 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3277 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3278 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3279 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3286 intel_float_operand (const char *mnemonic)
3288 /* Note that the value returned is meaningful only for opcodes with (memory)
3289 operands, hence the code here is free to improperly handle opcodes that
3290 have no operands (for better performance and smaller code). */
3292 if (mnemonic[0] != 'f')
3293 return 0; /* non-math */
3295 switch (mnemonic[1])
3297 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3298 the fs segment override prefix not currently handled because no
3299 call path can make opcodes without operands get here */
3301 return 2 /* integer op */;
3303 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3304 return 3; /* fldcw/fldenv */
3307 if (mnemonic[2] != 'o' /* fnop */)
3308 return 3; /* non-waiting control op */
3311 if (mnemonic[2] == 's')
3312 return 3; /* frstor/frstpm */
3315 if (mnemonic[2] == 'a')
3316 return 3; /* fsave */
3317 if (mnemonic[2] == 't')
3319 switch (mnemonic[3])
3321 case 'c': /* fstcw */
3322 case 'd': /* fstdw */
3323 case 'e': /* fstenv */
3324 case 's': /* fsts[gw] */
3330 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3331 return 0; /* fxsave/fxrstor are not really math ops */
3338 /* Build the VEX prefix. */
3341 build_vex_prefix (const insn_template *t)
3343 unsigned int register_specifier;
3344 unsigned int implied_prefix;
3345 unsigned int vector_length;
3347 /* Check register specifier. */
3348 if (i.vex.register_specifier)
3350 register_specifier =
3351 ~register_number (i.vex.register_specifier) & 0xf;
3352 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3355 register_specifier = 0xf;
3357 /* Use 2-byte VEX prefix by swapping destination and source
3359 if (i.vec_encoding != vex_encoding_vex3
3360 && i.dir_encoding == dir_encoding_default
3361 && i.operands == i.reg_operands
3362 && i.tm.opcode_modifier.vexopcode == VEX0F
3363 && i.tm.opcode_modifier.load
3366 unsigned int xchg = i.operands - 1;
3367 union i386_op temp_op;
3368 i386_operand_type temp_type;
3370 temp_type = i.types[xchg];
3371 i.types[xchg] = i.types[0];
3372 i.types[0] = temp_type;
3373 temp_op = i.op[xchg];
3374 i.op[xchg] = i.op[0];
3377 gas_assert (i.rm.mode == 3);
3381 i.rm.regmem = i.rm.reg;
3384 /* Use the next insn. */
3388 if (i.tm.opcode_modifier.vex == VEXScalar)
3389 vector_length = avxscalar;
3390 else if (i.tm.opcode_modifier.vex == VEX256)
3396 /* Determine vector length from the last multi-length vector
3399 for (op = t->operands; op--;)
3400 if (t->operand_types[op].bitfield.xmmword
3401 && t->operand_types[op].bitfield.ymmword
3402 && i.types[op].bitfield.ymmword)
3409 switch ((i.tm.base_opcode >> 8) & 0xff)
3414 case DATA_PREFIX_OPCODE:
3417 case REPE_PREFIX_OPCODE:
3420 case REPNE_PREFIX_OPCODE:
3427 /* Use 2-byte VEX prefix if possible. */
3428 if (i.vec_encoding != vex_encoding_vex3
3429 && i.tm.opcode_modifier.vexopcode == VEX0F
3430 && i.tm.opcode_modifier.vexw != VEXW1
3431 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3433 /* 2-byte VEX prefix. */
3437 i.vex.bytes[0] = 0xc5;
3439 /* Check the REX.R bit. */
3440 r = (i.rex & REX_R) ? 0 : 1;
3441 i.vex.bytes[1] = (r << 7
3442 | register_specifier << 3
3443 | vector_length << 2
3448 /* 3-byte VEX prefix. */
3453 switch (i.tm.opcode_modifier.vexopcode)
3457 i.vex.bytes[0] = 0xc4;
3461 i.vex.bytes[0] = 0xc4;
3465 i.vex.bytes[0] = 0xc4;
3469 i.vex.bytes[0] = 0x8f;
3473 i.vex.bytes[0] = 0x8f;
3477 i.vex.bytes[0] = 0x8f;
3483 /* The high 3 bits of the second VEX byte are 1's compliment
3484 of RXB bits from REX. */
3485 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3487 /* Check the REX.W bit. */
3488 w = (i.rex & REX_W) ? 1 : 0;
3489 if (i.tm.opcode_modifier.vexw == VEXW1)
3492 i.vex.bytes[2] = (w << 7
3493 | register_specifier << 3
3494 | vector_length << 2
3499 static INLINE bfd_boolean
3500 is_evex_encoding (const insn_template *t)
3502 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3503 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3504 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3507 static INLINE bfd_boolean
3508 is_any_vex_encoding (const insn_template *t)
3510 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3511 || is_evex_encoding (t);
3514 /* Build the EVEX prefix. */
3517 build_evex_prefix (void)
3519 unsigned int register_specifier;
3520 unsigned int implied_prefix;
3522 rex_byte vrex_used = 0;
3524 /* Check register specifier. */
3525 if (i.vex.register_specifier)
3527 gas_assert ((i.vrex & REX_X) == 0);
3529 register_specifier = i.vex.register_specifier->reg_num;
3530 if ((i.vex.register_specifier->reg_flags & RegRex))
3531 register_specifier += 8;
3532 /* The upper 16 registers are encoded in the fourth byte of the
3534 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3535 i.vex.bytes[3] = 0x8;
3536 register_specifier = ~register_specifier & 0xf;
3540 register_specifier = 0xf;
3542 /* Encode upper 16 vector index register in the fourth byte of
3544 if (!(i.vrex & REX_X))
3545 i.vex.bytes[3] = 0x8;
3550 switch ((i.tm.base_opcode >> 8) & 0xff)
3555 case DATA_PREFIX_OPCODE:
3558 case REPE_PREFIX_OPCODE:
3561 case REPNE_PREFIX_OPCODE:
3568 /* 4 byte EVEX prefix. */
3570 i.vex.bytes[0] = 0x62;
3573 switch (i.tm.opcode_modifier.vexopcode)
3589 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3591 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3593 /* The fifth bit of the second EVEX byte is 1's compliment of the
3594 REX_R bit in VREX. */
3595 if (!(i.vrex & REX_R))
3596 i.vex.bytes[1] |= 0x10;
3600 if ((i.reg_operands + i.imm_operands) == i.operands)
3602 /* When all operands are registers, the REX_X bit in REX is not
3603 used. We reuse it to encode the upper 16 registers, which is
3604 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3605 as 1's compliment. */
3606 if ((i.vrex & REX_B))
3609 i.vex.bytes[1] &= ~0x40;
3613 /* EVEX instructions shouldn't need the REX prefix. */
3614 i.vrex &= ~vrex_used;
3615 gas_assert (i.vrex == 0);
3617 /* Check the REX.W bit. */
3618 w = (i.rex & REX_W) ? 1 : 0;
3619 if (i.tm.opcode_modifier.vexw)
3621 if (i.tm.opcode_modifier.vexw == VEXW1)
3624 /* If w is not set it means we are dealing with WIG instruction. */
3627 if (evexwig == evexw1)
3631 /* Encode the U bit. */
3632 implied_prefix |= 0x4;
3634 /* The third byte of the EVEX prefix. */
3635 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3637 /* The fourth byte of the EVEX prefix. */
3638 /* The zeroing-masking bit. */
3639 if (i.mask && i.mask->zeroing)
3640 i.vex.bytes[3] |= 0x80;
3642 /* Don't always set the broadcast bit if there is no RC. */
3645 /* Encode the vector length. */
3646 unsigned int vec_length;
3648 if (!i.tm.opcode_modifier.evex
3649 || i.tm.opcode_modifier.evex == EVEXDYN)
3653 /* Determine vector length from the last multi-length vector
3656 for (op = i.operands; op--;)
3657 if (i.tm.operand_types[op].bitfield.xmmword
3658 + i.tm.operand_types[op].bitfield.ymmword
3659 + i.tm.operand_types[op].bitfield.zmmword > 1)
3661 if (i.types[op].bitfield.zmmword)
3663 i.tm.opcode_modifier.evex = EVEX512;
3666 else if (i.types[op].bitfield.ymmword)
3668 i.tm.opcode_modifier.evex = EVEX256;
3671 else if (i.types[op].bitfield.xmmword)
3673 i.tm.opcode_modifier.evex = EVEX128;
3676 else if (i.broadcast && (int) op == i.broadcast->operand)
3678 switch (i.broadcast->bytes)
3681 i.tm.opcode_modifier.evex = EVEX512;
3684 i.tm.opcode_modifier.evex = EVEX256;
3687 i.tm.opcode_modifier.evex = EVEX128;
3696 if (op >= MAX_OPERANDS)
3700 switch (i.tm.opcode_modifier.evex)
3702 case EVEXLIG: /* LL' is ignored */
3703 vec_length = evexlig << 5;
3706 vec_length = 0 << 5;
3709 vec_length = 1 << 5;
3712 vec_length = 2 << 5;
3718 i.vex.bytes[3] |= vec_length;
3719 /* Encode the broadcast bit. */
3721 i.vex.bytes[3] |= 0x10;
3725 if (i.rounding->type != saeonly)
3726 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3728 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3731 if (i.mask && i.mask->mask)
3732 i.vex.bytes[3] |= i.mask->mask->reg_num;
3736 process_immext (void)
3740 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3743 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3744 with an opcode suffix which is coded in the same place as an
3745 8-bit immediate field would be.
3746 Here we check those operands and remove them afterwards. */
3749 for (x = 0; x < i.operands; x++)
3750 if (register_number (i.op[x].regs) != x)
3751 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3752 register_prefix, i.op[x].regs->reg_name, x + 1,
3758 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3760 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3761 suffix which is coded in the same place as an 8-bit immediate
3763 Here we check those operands and remove them afterwards. */
3766 if (i.operands != 3)
3769 for (x = 0; x < 2; x++)
3770 if (register_number (i.op[x].regs) != x)
3771 goto bad_register_operand;
3773 /* Check for third operand for mwaitx/monitorx insn. */
3774 if (register_number (i.op[x].regs)
3775 != (x + (i.tm.extension_opcode == 0xfb)))
3777 bad_register_operand:
3778 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3779 register_prefix, i.op[x].regs->reg_name, x+1,
3786 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3787 which is coded in the same place as an 8-bit immediate field
3788 would be. Here we fake an 8-bit immediate operand from the
3789 opcode suffix stored in tm.extension_opcode.
3791 AVX instructions also use this encoding, for some of
3792 3 argument instructions. */
3794 gas_assert (i.imm_operands <= 1
3796 || (is_any_vex_encoding (&i.tm)
3797 && i.operands <= 4)));
3799 exp = &im_expressions[i.imm_operands++];
3800 i.op[i.operands].imms = exp;
3801 i.types[i.operands] = imm8;
3803 exp->X_op = O_constant;
3804 exp->X_add_number = i.tm.extension_opcode;
3805 i.tm.extension_opcode = None;
3812 switch (i.tm.opcode_modifier.hleprefixok)
3817 as_bad (_("invalid instruction `%s' after `%s'"),
3818 i.tm.name, i.hle_prefix);
3821 if (i.prefix[LOCK_PREFIX])
3823 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3827 case HLEPrefixRelease:
3828 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3830 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3834 if (i.mem_operands == 0
3835 || !operand_type_check (i.types[i.operands - 1], anymem))
3837 as_bad (_("memory destination needed for instruction `%s'"
3838 " after `xrelease'"), i.tm.name);
3845 /* Try the shortest encoding by shortening operand size. */
3848 optimize_encoding (void)
3852 if (optimize_for_space
3853 && i.reg_operands == 1
3854 && i.imm_operands == 1
3855 && !i.types[1].bitfield.byte
3856 && i.op[0].imms->X_op == O_constant
3857 && fits_in_imm7 (i.op[0].imms->X_add_number)
3858 && ((i.tm.base_opcode == 0xa8
3859 && i.tm.extension_opcode == None)
3860 || (i.tm.base_opcode == 0xf6
3861 && i.tm.extension_opcode == 0x0)))
3864 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3866 unsigned int base_regnum = i.op[1].regs->reg_num;
3867 if (flag_code == CODE_64BIT || base_regnum < 4)
3869 i.types[1].bitfield.byte = 1;
3870 /* Ignore the suffix. */
3872 if (base_regnum >= 4
3873 && !(i.op[1].regs->reg_flags & RegRex))
3875 /* Handle SP, BP, SI and DI registers. */
3876 if (i.types[1].bitfield.word)
3878 else if (i.types[1].bitfield.dword)
3886 else if (flag_code == CODE_64BIT
3887 && ((i.types[1].bitfield.qword
3888 && i.reg_operands == 1
3889 && i.imm_operands == 1
3890 && i.op[0].imms->X_op == O_constant
3891 && ((i.tm.base_opcode == 0xb0
3892 && i.tm.extension_opcode == None
3893 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3894 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3895 && (((i.tm.base_opcode == 0x24
3896 || i.tm.base_opcode == 0xa8)
3897 && i.tm.extension_opcode == None)
3898 || (i.tm.base_opcode == 0x80
3899 && i.tm.extension_opcode == 0x4)
3900 || ((i.tm.base_opcode == 0xf6
3901 || i.tm.base_opcode == 0xc6)
3902 && i.tm.extension_opcode == 0x0)))))
3903 || (i.types[0].bitfield.qword
3904 && ((i.reg_operands == 2
3905 && i.op[0].regs == i.op[1].regs
3906 && ((i.tm.base_opcode == 0x30
3907 || i.tm.base_opcode == 0x28)
3908 && i.tm.extension_opcode == None))
3909 || (i.reg_operands == 1
3911 && i.tm.base_opcode == 0x30
3912 && i.tm.extension_opcode == None)))))
3915 andq $imm31, %r64 -> andl $imm31, %r32
3916 testq $imm31, %r64 -> testl $imm31, %r32
3917 xorq %r64, %r64 -> xorl %r32, %r32
3918 subq %r64, %r64 -> subl %r32, %r32
3919 movq $imm31, %r64 -> movl $imm31, %r32
3920 movq $imm32, %r64 -> movl $imm32, %r32
3922 i.tm.opcode_modifier.norex64 = 1;
3923 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3926 movq $imm31, %r64 -> movl $imm31, %r32
3927 movq $imm32, %r64 -> movl $imm32, %r32
3929 i.tm.operand_types[0].bitfield.imm32 = 1;
3930 i.tm.operand_types[0].bitfield.imm32s = 0;
3931 i.tm.operand_types[0].bitfield.imm64 = 0;
3932 i.types[0].bitfield.imm32 = 1;
3933 i.types[0].bitfield.imm32s = 0;
3934 i.types[0].bitfield.imm64 = 0;
3935 i.types[1].bitfield.dword = 1;
3936 i.types[1].bitfield.qword = 0;
3937 if (i.tm.base_opcode == 0xc6)
3940 movq $imm31, %r64 -> movl $imm31, %r32
3942 i.tm.base_opcode = 0xb0;
3943 i.tm.extension_opcode = None;
3944 i.tm.opcode_modifier.shortform = 1;
3945 i.tm.opcode_modifier.modrm = 0;
3949 else if (optimize > 1
3950 && i.reg_operands == 3
3951 && i.op[0].regs == i.op[1].regs
3952 && !i.types[2].bitfield.xmmword
3953 && (i.tm.opcode_modifier.vex
3954 || ((!i.mask || i.mask->zeroing)
3956 && is_evex_encoding (&i.tm)
3957 && (i.vec_encoding != vex_encoding_evex
3958 || i.tm.cpu_flags.bitfield.cpuavx512vl
3959 || (i.tm.operand_types[2].bitfield.zmmword
3960 && i.types[2].bitfield.ymmword)
3961 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3962 && ((i.tm.base_opcode == 0x55
3963 || i.tm.base_opcode == 0x6655
3964 || i.tm.base_opcode == 0x66df
3965 || i.tm.base_opcode == 0x57
3966 || i.tm.base_opcode == 0x6657
3967 || i.tm.base_opcode == 0x66ef
3968 || i.tm.base_opcode == 0x66f8
3969 || i.tm.base_opcode == 0x66f9
3970 || i.tm.base_opcode == 0x66fa
3971 || i.tm.base_opcode == 0x66fb
3972 || i.tm.base_opcode == 0x42
3973 || i.tm.base_opcode == 0x6642
3974 || i.tm.base_opcode == 0x47
3975 || i.tm.base_opcode == 0x6647)
3976 && i.tm.extension_opcode == None))
3979 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3981 EVEX VOP %zmmM, %zmmM, %zmmN
3982 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3983 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3984 EVEX VOP %ymmM, %ymmM, %ymmN
3985 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3986 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3987 VEX VOP %ymmM, %ymmM, %ymmN
3988 -> VEX VOP %xmmM, %xmmM, %xmmN
3989 VOP, one of vpandn and vpxor:
3990 VEX VOP %ymmM, %ymmM, %ymmN
3991 -> VEX VOP %xmmM, %xmmM, %xmmN
3992 VOP, one of vpandnd and vpandnq:
3993 EVEX VOP %zmmM, %zmmM, %zmmN
3994 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3995 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3996 EVEX VOP %ymmM, %ymmM, %ymmN
3997 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3998 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3999 VOP, one of vpxord and vpxorq:
4000 EVEX VOP %zmmM, %zmmM, %zmmN
4001 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4002 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4003 EVEX VOP %ymmM, %ymmM, %ymmN
4004 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4005 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4006 VOP, one of kxord and kxorq:
4007 VEX VOP %kM, %kM, %kN
4008 -> VEX kxorw %kM, %kM, %kN
4009 VOP, one of kandnd and kandnq:
4010 VEX VOP %kM, %kM, %kN
4011 -> VEX kandnw %kM, %kM, %kN
4013 if (is_evex_encoding (&i.tm))
4015 if (i.vec_encoding == vex_encoding_evex)
4016 i.tm.opcode_modifier.evex = EVEX128;
4019 i.tm.opcode_modifier.vex = VEX128;
4020 i.tm.opcode_modifier.vexw = VEXW0;
4021 i.tm.opcode_modifier.evex = 0;
4024 else if (i.tm.operand_types[0].bitfield.regmask)
4026 i.tm.base_opcode &= 0xff;
4027 i.tm.opcode_modifier.vexw = VEXW0;
4030 i.tm.opcode_modifier.vex = VEX128;
4032 if (i.tm.opcode_modifier.vex)
4033 for (j = 0; j < 3; j++)
4035 i.types[j].bitfield.xmmword = 1;
4036 i.types[j].bitfield.ymmword = 0;
4041 /* This is the guts of the machine-dependent assembler. LINE points to a
4042 machine dependent instruction. This function is supposed to emit
4043 the frags/bytes it assembles to. */
4046 md_assemble (char *line)
4049 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4050 const insn_template *t;
4052 /* Initialize globals. */
4053 memset (&i, '\0', sizeof (i));
4054 for (j = 0; j < MAX_OPERANDS; j++)
4055 i.reloc[j] = NO_RELOC;
4056 memset (disp_expressions, '\0', sizeof (disp_expressions));
4057 memset (im_expressions, '\0', sizeof (im_expressions));
4058 save_stack_p = save_stack;
4060 /* First parse an instruction mnemonic & call i386_operand for the operands.
4061 We assume that the scrubber has arranged it so that line[0] is the valid
4062 start of a (possibly prefixed) mnemonic. */
4064 line = parse_insn (line, mnemonic);
4067 mnem_suffix = i.suffix;
4069 line = parse_operands (line, mnemonic);
4071 xfree (i.memop1_string);
4072 i.memop1_string = NULL;
4076 /* Now we've parsed the mnemonic into a set of templates, and have the
4077 operands at hand. */
4079 /* All intel opcodes have reversed operands except for "bound" and
4080 "enter". We also don't reverse intersegment "jmp" and "call"
4081 instructions with 2 immediate operands so that the immediate segment
4082 precedes the offset, as it does when in AT&T mode. */
4085 && (strcmp (mnemonic, "bound") != 0)
4086 && (strcmp (mnemonic, "invlpga") != 0)
4087 && !(operand_type_check (i.types[0], imm)
4088 && operand_type_check (i.types[1], imm)))
4091 /* The order of the immediates should be reversed
4092 for 2 immediates extrq and insertq instructions */
4093 if (i.imm_operands == 2
4094 && (strcmp (mnemonic, "extrq") == 0
4095 || strcmp (mnemonic, "insertq") == 0))
4096 swap_2_operands (0, 1);
4101 /* Don't optimize displacement for movabs since it only takes 64bit
4104 && i.disp_encoding != disp_encoding_32bit
4105 && (flag_code != CODE_64BIT
4106 || strcmp (mnemonic, "movabs") != 0))
4109 /* Next, we find a template that matches the given insn,
4110 making sure the overlap of the given operands types is consistent
4111 with the template operand types. */
4113 if (!(t = match_template (mnem_suffix)))
4116 if (sse_check != check_none
4117 && !i.tm.opcode_modifier.noavx
4118 && !i.tm.cpu_flags.bitfield.cpuavx
4119 && (i.tm.cpu_flags.bitfield.cpusse
4120 || i.tm.cpu_flags.bitfield.cpusse2
4121 || i.tm.cpu_flags.bitfield.cpusse3
4122 || i.tm.cpu_flags.bitfield.cpussse3
4123 || i.tm.cpu_flags.bitfield.cpusse4_1
4124 || i.tm.cpu_flags.bitfield.cpusse4_2
4125 || i.tm.cpu_flags.bitfield.cpupclmul
4126 || i.tm.cpu_flags.bitfield.cpuaes
4127 || i.tm.cpu_flags.bitfield.cpugfni))
4129 (sse_check == check_warning
4131 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4134 /* Zap movzx and movsx suffix. The suffix has been set from
4135 "word ptr" or "byte ptr" on the source operand in Intel syntax
4136 or extracted from mnemonic in AT&T syntax. But we'll use
4137 the destination register to choose the suffix for encoding. */
4138 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4140 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4141 there is no suffix, the default will be byte extension. */
4142 if (i.reg_operands != 2
4145 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4150 if (i.tm.opcode_modifier.fwait)
4151 if (!add_prefix (FWAIT_OPCODE))
4154 /* Check if REP prefix is OK. */
4155 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4157 as_bad (_("invalid instruction `%s' after `%s'"),
4158 i.tm.name, i.rep_prefix);
4162 /* Check for lock without a lockable instruction. Destination operand
4163 must be memory unless it is xchg (0x86). */
4164 if (i.prefix[LOCK_PREFIX]
4165 && (!i.tm.opcode_modifier.islockable
4166 || i.mem_operands == 0
4167 || (i.tm.base_opcode != 0x86
4168 && !operand_type_check (i.types[i.operands - 1], anymem))))
4170 as_bad (_("expecting lockable instruction after `lock'"));
4174 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4175 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4177 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4181 /* Check if HLE prefix is OK. */
4182 if (i.hle_prefix && !check_hle ())
4185 /* Check BND prefix. */
4186 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4187 as_bad (_("expecting valid branch instruction after `bnd'"));
4189 /* Check NOTRACK prefix. */
4190 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4191 as_bad (_("expecting indirect branch instruction after `notrack'"));
4193 if (i.tm.cpu_flags.bitfield.cpumpx)
4195 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4196 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4197 else if (flag_code != CODE_16BIT
4198 ? i.prefix[ADDR_PREFIX]
4199 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4200 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4203 /* Insert BND prefix. */
4204 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4206 if (!i.prefix[BND_PREFIX])
4207 add_prefix (BND_PREFIX_OPCODE);
4208 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4210 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4211 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4215 /* Check string instruction segment overrides. */
4216 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4218 if (!check_string ())
4220 i.disp_operands = 0;
4223 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4224 optimize_encoding ();
4226 if (!process_suffix ())
4229 /* Update operand types. */
4230 for (j = 0; j < i.operands; j++)
4231 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4233 /* Make still unresolved immediate matches conform to size of immediate
4234 given in i.suffix. */
4235 if (!finalize_imm ())
4238 if (i.types[0].bitfield.imm1)
4239 i.imm_operands = 0; /* kludge for shift insns. */
4241 /* We only need to check those implicit registers for instructions
4242 with 3 operands or less. */
4243 if (i.operands <= 3)
4244 for (j = 0; j < i.operands; j++)
4245 if (i.types[j].bitfield.inoutportreg
4246 || i.types[j].bitfield.shiftcount
4247 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4250 /* ImmExt should be processed after SSE2AVX. */
4251 if (!i.tm.opcode_modifier.sse2avx
4252 && i.tm.opcode_modifier.immext)
4255 /* For insns with operands there are more diddles to do to the opcode. */
4258 if (!process_operands ())
4261 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4263 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4264 as_warn (_("translating to `%sp'"), i.tm.name);
4267 if (is_any_vex_encoding (&i.tm))
4269 if (flag_code == CODE_16BIT)
4271 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4276 if (i.tm.opcode_modifier.vex)
4277 build_vex_prefix (t);
4279 build_evex_prefix ();
4282 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4283 instructions may define INT_OPCODE as well, so avoid this corner
4284 case for those instructions that use MODRM. */
4285 if (i.tm.base_opcode == INT_OPCODE
4286 && !i.tm.opcode_modifier.modrm
4287 && i.op[0].imms->X_add_number == 3)
4289 i.tm.base_opcode = INT3_OPCODE;
4293 if ((i.tm.opcode_modifier.jump
4294 || i.tm.opcode_modifier.jumpbyte
4295 || i.tm.opcode_modifier.jumpdword)
4296 && i.op[0].disps->X_op == O_constant)
4298 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4299 the absolute address given by the constant. Since ix86 jumps and
4300 calls are pc relative, we need to generate a reloc. */
4301 i.op[0].disps->X_add_symbol = &abs_symbol;
4302 i.op[0].disps->X_op = O_symbol;
4305 if (i.tm.opcode_modifier.rex64)
4308 /* For 8 bit registers we need an empty rex prefix. Also if the
4309 instruction already has a prefix, we need to convert old
4310 registers to new ones. */
4312 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4313 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4314 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4315 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4316 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4317 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4322 i.rex |= REX_OPCODE;
4323 for (x = 0; x < 2; x++)
4325 /* Look for 8 bit operand that uses old registers. */
4326 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4327 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4329 /* In case it is "hi" register, give up. */
4330 if (i.op[x].regs->reg_num > 3)
4331 as_bad (_("can't encode register '%s%s' in an "
4332 "instruction requiring REX prefix."),
4333 register_prefix, i.op[x].regs->reg_name);
4335 /* Otherwise it is equivalent to the extended register.
4336 Since the encoding doesn't change this is merely
4337 cosmetic cleanup for debug output. */
4339 i.op[x].regs = i.op[x].regs + 8;
4344 if (i.rex == 0 && i.rex_encoding)
4346 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4347 that uses legacy register. If it is "hi" register, don't add
4348 the REX_OPCODE byte. */
4350 for (x = 0; x < 2; x++)
4351 if (i.types[x].bitfield.reg
4352 && i.types[x].bitfield.byte
4353 && (i.op[x].regs->reg_flags & RegRex64) == 0
4354 && i.op[x].regs->reg_num > 3)
4356 i.rex_encoding = FALSE;
4365 add_prefix (REX_OPCODE | i.rex);
4367 /* We are ready to output the insn. */
4372 parse_insn (char *line, char *mnemonic)
4375 char *token_start = l;
4378 const insn_template *t;
4384 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4389 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4391 as_bad (_("no such instruction: `%s'"), token_start);
4396 if (!is_space_char (*l)
4397 && *l != END_OF_INSN
4399 || (*l != PREFIX_SEPARATOR
4402 as_bad (_("invalid character %s in mnemonic"),
4403 output_invalid (*l));
4406 if (token_start == l)
4408 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4409 as_bad (_("expecting prefix; got nothing"));
4411 as_bad (_("expecting mnemonic; got nothing"));
4415 /* Look up instruction (or prefix) via hash table. */
4416 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4418 if (*l != END_OF_INSN
4419 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4420 && current_templates
4421 && current_templates->start->opcode_modifier.isprefix)
4423 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4425 as_bad ((flag_code != CODE_64BIT
4426 ? _("`%s' is only supported in 64-bit mode")
4427 : _("`%s' is not supported in 64-bit mode")),
4428 current_templates->start->name);
4431 /* If we are in 16-bit mode, do not allow addr16 or data16.
4432 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4433 if ((current_templates->start->opcode_modifier.size16
4434 || current_templates->start->opcode_modifier.size32)
4435 && flag_code != CODE_64BIT
4436 && (current_templates->start->opcode_modifier.size32
4437 ^ (flag_code == CODE_16BIT)))
4439 as_bad (_("redundant %s prefix"),
4440 current_templates->start->name);
4443 if (current_templates->start->opcode_length == 0)
4445 /* Handle pseudo prefixes. */
4446 switch (current_templates->start->base_opcode)
4450 i.disp_encoding = disp_encoding_8bit;
4454 i.disp_encoding = disp_encoding_32bit;
4458 i.dir_encoding = dir_encoding_load;
4462 i.dir_encoding = dir_encoding_store;
4466 i.vec_encoding = vex_encoding_vex2;
4470 i.vec_encoding = vex_encoding_vex3;
4474 i.vec_encoding = vex_encoding_evex;
4478 i.rex_encoding = TRUE;
4482 i.no_optimize = TRUE;
4490 /* Add prefix, checking for repeated prefixes. */
4491 switch (add_prefix (current_templates->start->base_opcode))
4496 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4497 i.notrack_prefix = current_templates->start->name;
4500 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4501 i.hle_prefix = current_templates->start->name;
4502 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4503 i.bnd_prefix = current_templates->start->name;
4505 i.rep_prefix = current_templates->start->name;
4511 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4518 if (!current_templates)
4520 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4521 Check if we should swap operand or force 32bit displacement in
4523 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4524 i.dir_encoding = dir_encoding_swap;
4525 else if (mnem_p - 3 == dot_p
4528 i.disp_encoding = disp_encoding_8bit;
4529 else if (mnem_p - 4 == dot_p
4533 i.disp_encoding = disp_encoding_32bit;
4538 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4541 if (!current_templates)
4544 /* See if we can get a match by trimming off a suffix. */
4547 case WORD_MNEM_SUFFIX:
4548 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4549 i.suffix = SHORT_MNEM_SUFFIX;
4552 case BYTE_MNEM_SUFFIX:
4553 case QWORD_MNEM_SUFFIX:
4554 i.suffix = mnem_p[-1];
4556 current_templates = (const templates *) hash_find (op_hash,
4559 case SHORT_MNEM_SUFFIX:
4560 case LONG_MNEM_SUFFIX:
4563 i.suffix = mnem_p[-1];
4565 current_templates = (const templates *) hash_find (op_hash,
4574 if (intel_float_operand (mnemonic) == 1)
4575 i.suffix = SHORT_MNEM_SUFFIX;
4577 i.suffix = LONG_MNEM_SUFFIX;
4579 current_templates = (const templates *) hash_find (op_hash,
4584 if (!current_templates)
4586 as_bad (_("no such instruction: `%s'"), token_start);
4591 if (current_templates->start->opcode_modifier.jump
4592 || current_templates->start->opcode_modifier.jumpbyte)
4594 /* Check for a branch hint. We allow ",pt" and ",pn" for
4595 predict taken and predict not taken respectively.
4596 I'm not sure that branch hints actually do anything on loop
4597 and jcxz insns (JumpByte) for current Pentium4 chips. They
4598 may work in the future and it doesn't hurt to accept them
4600 if (l[0] == ',' && l[1] == 'p')
4604 if (!add_prefix (DS_PREFIX_OPCODE))
4608 else if (l[2] == 'n')
4610 if (!add_prefix (CS_PREFIX_OPCODE))
4616 /* Any other comma loses. */
4619 as_bad (_("invalid character %s in mnemonic"),
4620 output_invalid (*l));
4624 /* Check if instruction is supported on specified architecture. */
4626 for (t = current_templates->start; t < current_templates->end; ++t)
4628 supported |= cpu_flags_match (t);
4629 if (supported == CPU_FLAGS_PERFECT_MATCH)
4631 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4632 as_warn (_("use .code16 to ensure correct addressing mode"));
4638 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4639 as_bad (flag_code == CODE_64BIT
4640 ? _("`%s' is not supported in 64-bit mode")
4641 : _("`%s' is only supported in 64-bit mode"),
4642 current_templates->start->name);
4644 as_bad (_("`%s' is not supported on `%s%s'"),
4645 current_templates->start->name,
4646 cpu_arch_name ? cpu_arch_name : default_arch,
4647 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4653 parse_operands (char *l, const char *mnemonic)
4657 /* 1 if operand is pending after ','. */
4658 unsigned int expecting_operand = 0;
4660 /* Non-zero if operand parens not balanced. */
4661 unsigned int paren_not_balanced;
4663 while (*l != END_OF_INSN)
4665 /* Skip optional white space before operand. */
4666 if (is_space_char (*l))
4668 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4670 as_bad (_("invalid character %s before operand %d"),
4671 output_invalid (*l),
4675 token_start = l; /* After white space. */
4676 paren_not_balanced = 0;
4677 while (paren_not_balanced || *l != ',')
4679 if (*l == END_OF_INSN)
4681 if (paren_not_balanced)
4684 as_bad (_("unbalanced parenthesis in operand %d."),
4687 as_bad (_("unbalanced brackets in operand %d."),
4692 break; /* we are done */
4694 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4696 as_bad (_("invalid character %s in operand %d"),
4697 output_invalid (*l),
4704 ++paren_not_balanced;
4706 --paren_not_balanced;
4711 ++paren_not_balanced;
4713 --paren_not_balanced;
4717 if (l != token_start)
4718 { /* Yes, we've read in another operand. */
4719 unsigned int operand_ok;
4720 this_operand = i.operands++;
4721 if (i.operands > MAX_OPERANDS)
4723 as_bad (_("spurious operands; (%d operands/instruction max)"),
4727 i.types[this_operand].bitfield.unspecified = 1;
4728 /* Now parse operand adding info to 'i' as we go along. */
4729 END_STRING_AND_SAVE (l);
4731 if (i.mem_operands > 1)
4733 as_bad (_("too many memory references for `%s'"),
4740 i386_intel_operand (token_start,
4741 intel_float_operand (mnemonic));
4743 operand_ok = i386_att_operand (token_start);
4745 RESTORE_END_STRING (l);
4751 if (expecting_operand)
4753 expecting_operand_after_comma:
4754 as_bad (_("expecting operand after ','; got nothing"));
4759 as_bad (_("expecting operand before ','; got nothing"));
4764 /* Now *l must be either ',' or END_OF_INSN. */
4767 if (*++l == END_OF_INSN)
4769 /* Just skip it, if it's \n complain. */
4770 goto expecting_operand_after_comma;
4772 expecting_operand = 1;
4779 swap_2_operands (int xchg1, int xchg2)
4781 union i386_op temp_op;
4782 i386_operand_type temp_type;
4783 unsigned int temp_flags;
4784 enum bfd_reloc_code_real temp_reloc;
4786 temp_type = i.types[xchg2];
4787 i.types[xchg2] = i.types[xchg1];
4788 i.types[xchg1] = temp_type;
4790 temp_flags = i.flags[xchg2];
4791 i.flags[xchg2] = i.flags[xchg1];
4792 i.flags[xchg1] = temp_flags;
4794 temp_op = i.op[xchg2];
4795 i.op[xchg2] = i.op[xchg1];
4796 i.op[xchg1] = temp_op;
4798 temp_reloc = i.reloc[xchg2];
4799 i.reloc[xchg2] = i.reloc[xchg1];
4800 i.reloc[xchg1] = temp_reloc;
4804 if (i.mask->operand == xchg1)
4805 i.mask->operand = xchg2;
4806 else if (i.mask->operand == xchg2)
4807 i.mask->operand = xchg1;
4811 if (i.broadcast->operand == xchg1)
4812 i.broadcast->operand = xchg2;
4813 else if (i.broadcast->operand == xchg2)
4814 i.broadcast->operand = xchg1;
4818 if (i.rounding->operand == xchg1)
4819 i.rounding->operand = xchg2;
4820 else if (i.rounding->operand == xchg2)
4821 i.rounding->operand = xchg1;
4826 swap_operands (void)
4832 swap_2_operands (1, i.operands - 2);
4836 swap_2_operands (0, i.operands - 1);
4842 if (i.mem_operands == 2)
4844 const seg_entry *temp_seg;
4845 temp_seg = i.seg[0];
4846 i.seg[0] = i.seg[1];
4847 i.seg[1] = temp_seg;
4851 /* Try to ensure constant immediates are represented in the smallest
4856 char guess_suffix = 0;
4860 guess_suffix = i.suffix;
4861 else if (i.reg_operands)
4863 /* Figure out a suffix from the last register operand specified.
4864 We can't do this properly yet, ie. excluding InOutPortReg,
4865 but the following works for instructions with immediates.
4866 In any case, we can't set i.suffix yet. */
4867 for (op = i.operands; --op >= 0;)
4868 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4870 guess_suffix = BYTE_MNEM_SUFFIX;
4873 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4875 guess_suffix = WORD_MNEM_SUFFIX;
4878 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4880 guess_suffix = LONG_MNEM_SUFFIX;
4883 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4885 guess_suffix = QWORD_MNEM_SUFFIX;
4889 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4890 guess_suffix = WORD_MNEM_SUFFIX;
4892 for (op = i.operands; --op >= 0;)
4893 if (operand_type_check (i.types[op], imm))
4895 switch (i.op[op].imms->X_op)
4898 /* If a suffix is given, this operand may be shortened. */
4899 switch (guess_suffix)
4901 case LONG_MNEM_SUFFIX:
4902 i.types[op].bitfield.imm32 = 1;
4903 i.types[op].bitfield.imm64 = 1;
4905 case WORD_MNEM_SUFFIX:
4906 i.types[op].bitfield.imm16 = 1;
4907 i.types[op].bitfield.imm32 = 1;
4908 i.types[op].bitfield.imm32s = 1;
4909 i.types[op].bitfield.imm64 = 1;
4911 case BYTE_MNEM_SUFFIX:
4912 i.types[op].bitfield.imm8 = 1;
4913 i.types[op].bitfield.imm8s = 1;
4914 i.types[op].bitfield.imm16 = 1;
4915 i.types[op].bitfield.imm32 = 1;
4916 i.types[op].bitfield.imm32s = 1;
4917 i.types[op].bitfield.imm64 = 1;
4921 /* If this operand is at most 16 bits, convert it
4922 to a signed 16 bit number before trying to see
4923 whether it will fit in an even smaller size.
4924 This allows a 16-bit operand such as $0xffe0 to
4925 be recognised as within Imm8S range. */
4926 if ((i.types[op].bitfield.imm16)
4927 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4929 i.op[op].imms->X_add_number =
4930 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4933 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4934 if ((i.types[op].bitfield.imm32)
4935 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4938 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4939 ^ ((offsetT) 1 << 31))
4940 - ((offsetT) 1 << 31));
4944 = operand_type_or (i.types[op],
4945 smallest_imm_type (i.op[op].imms->X_add_number));
4947 /* We must avoid matching of Imm32 templates when 64bit
4948 only immediate is available. */
4949 if (guess_suffix == QWORD_MNEM_SUFFIX)
4950 i.types[op].bitfield.imm32 = 0;
4957 /* Symbols and expressions. */
4959 /* Convert symbolic operand to proper sizes for matching, but don't
4960 prevent matching a set of insns that only supports sizes other
4961 than those matching the insn suffix. */
4963 i386_operand_type mask, allowed;
4964 const insn_template *t;
4966 operand_type_set (&mask, 0);
4967 operand_type_set (&allowed, 0);
4969 for (t = current_templates->start;
4970 t < current_templates->end;
4972 allowed = operand_type_or (allowed,
4973 t->operand_types[op]);
4974 switch (guess_suffix)
4976 case QWORD_MNEM_SUFFIX:
4977 mask.bitfield.imm64 = 1;
4978 mask.bitfield.imm32s = 1;
4980 case LONG_MNEM_SUFFIX:
4981 mask.bitfield.imm32 = 1;
4983 case WORD_MNEM_SUFFIX:
4984 mask.bitfield.imm16 = 1;
4986 case BYTE_MNEM_SUFFIX:
4987 mask.bitfield.imm8 = 1;
4992 allowed = operand_type_and (mask, allowed);
4993 if (!operand_type_all_zero (&allowed))
4994 i.types[op] = operand_type_and (i.types[op], mask);
5001 /* Try to use the smallest displacement type too. */
5003 optimize_disp (void)
5007 for (op = i.operands; --op >= 0;)
5008 if (operand_type_check (i.types[op], disp))
5010 if (i.op[op].disps->X_op == O_constant)
5012 offsetT op_disp = i.op[op].disps->X_add_number;
5014 if (i.types[op].bitfield.disp16
5015 && (op_disp & ~(offsetT) 0xffff) == 0)
5017 /* If this operand is at most 16 bits, convert
5018 to a signed 16 bit number and don't use 64bit
5020 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5021 i.types[op].bitfield.disp64 = 0;
5024 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5025 if (i.types[op].bitfield.disp32
5026 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5028 /* If this operand is at most 32 bits, convert
5029 to a signed 32 bit number and don't use 64bit
5031 op_disp &= (((offsetT) 2 << 31) - 1);
5032 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5033 i.types[op].bitfield.disp64 = 0;
5036 if (!op_disp && i.types[op].bitfield.baseindex)
5038 i.types[op].bitfield.disp8 = 0;
5039 i.types[op].bitfield.disp16 = 0;
5040 i.types[op].bitfield.disp32 = 0;
5041 i.types[op].bitfield.disp32s = 0;
5042 i.types[op].bitfield.disp64 = 0;
5046 else if (flag_code == CODE_64BIT)
5048 if (fits_in_signed_long (op_disp))
5050 i.types[op].bitfield.disp64 = 0;
5051 i.types[op].bitfield.disp32s = 1;
5053 if (i.prefix[ADDR_PREFIX]
5054 && fits_in_unsigned_long (op_disp))
5055 i.types[op].bitfield.disp32 = 1;
5057 if ((i.types[op].bitfield.disp32
5058 || i.types[op].bitfield.disp32s
5059 || i.types[op].bitfield.disp16)
5060 && fits_in_disp8 (op_disp))
5061 i.types[op].bitfield.disp8 = 1;
5063 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5064 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5066 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5067 i.op[op].disps, 0, i.reloc[op]);
5068 i.types[op].bitfield.disp8 = 0;
5069 i.types[op].bitfield.disp16 = 0;
5070 i.types[op].bitfield.disp32 = 0;
5071 i.types[op].bitfield.disp32s = 0;
5072 i.types[op].bitfield.disp64 = 0;
5075 /* We only support 64bit displacement on constants. */
5076 i.types[op].bitfield.disp64 = 0;
5080 /* Return 1 if there is a match in broadcast bytes between operand
5081 GIVEN and instruction template T. */
5084 match_broadcast_size (const insn_template *t, unsigned int given)
5086 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5087 && i.types[given].bitfield.byte)
5088 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5089 && i.types[given].bitfield.word)
5090 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5091 && i.types[given].bitfield.dword)
5092 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5093 && i.types[given].bitfield.qword));
5096 /* Check if operands are valid for the instruction. */
5099 check_VecOperands (const insn_template *t)
5103 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5105 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5106 any one operand are implicity requiring AVX512VL support if the actual
5107 operand size is YMMword or XMMword. Since this function runs after
5108 template matching, there's no need to check for YMMword/XMMword in
5110 cpu = cpu_flags_and (t->cpu_flags, avx512);
5111 if (!cpu_flags_all_zero (&cpu)
5112 && !t->cpu_flags.bitfield.cpuavx512vl
5113 && !cpu_arch_flags.bitfield.cpuavx512vl)
5115 for (op = 0; op < t->operands; ++op)
5117 if (t->operand_types[op].bitfield.zmmword
5118 && (i.types[op].bitfield.ymmword
5119 || i.types[op].bitfield.xmmword))
5121 i.error = unsupported;
5127 /* Without VSIB byte, we can't have a vector register for index. */
5128 if (!t->opcode_modifier.vecsib
5130 && (i.index_reg->reg_type.bitfield.xmmword
5131 || i.index_reg->reg_type.bitfield.ymmword
5132 || i.index_reg->reg_type.bitfield.zmmword))
5134 i.error = unsupported_vector_index_register;
5138 /* Check if default mask is allowed. */
5139 if (t->opcode_modifier.nodefmask
5140 && (!i.mask || i.mask->mask->reg_num == 0))
5142 i.error = no_default_mask;
5146 /* For VSIB byte, we need a vector register for index, and all vector
5147 registers must be distinct. */
5148 if (t->opcode_modifier.vecsib)
5151 || !((t->opcode_modifier.vecsib == VecSIB128
5152 && i.index_reg->reg_type.bitfield.xmmword)
5153 || (t->opcode_modifier.vecsib == VecSIB256
5154 && i.index_reg->reg_type.bitfield.ymmword)
5155 || (t->opcode_modifier.vecsib == VecSIB512
5156 && i.index_reg->reg_type.bitfield.zmmword)))
5158 i.error = invalid_vsib_address;
5162 gas_assert (i.reg_operands == 2 || i.mask);
5163 if (i.reg_operands == 2 && !i.mask)
5165 gas_assert (i.types[0].bitfield.regsimd);
5166 gas_assert (i.types[0].bitfield.xmmword
5167 || i.types[0].bitfield.ymmword);
5168 gas_assert (i.types[2].bitfield.regsimd);
5169 gas_assert (i.types[2].bitfield.xmmword
5170 || i.types[2].bitfield.ymmword);
5171 if (operand_check == check_none)
5173 if (register_number (i.op[0].regs)
5174 != register_number (i.index_reg)
5175 && register_number (i.op[2].regs)
5176 != register_number (i.index_reg)
5177 && register_number (i.op[0].regs)
5178 != register_number (i.op[2].regs))
5180 if (operand_check == check_error)
5182 i.error = invalid_vector_register_set;
5185 as_warn (_("mask, index, and destination registers should be distinct"));
5187 else if (i.reg_operands == 1 && i.mask)
5189 if (i.types[1].bitfield.regsimd
5190 && (i.types[1].bitfield.xmmword
5191 || i.types[1].bitfield.ymmword
5192 || i.types[1].bitfield.zmmword)
5193 && (register_number (i.op[1].regs)
5194 == register_number (i.index_reg)))
5196 if (operand_check == check_error)
5198 i.error = invalid_vector_register_set;
5201 if (operand_check != check_none)
5202 as_warn (_("index and destination registers should be distinct"));
5207 /* Check if broadcast is supported by the instruction and is applied
5208 to the memory operand. */
5211 i386_operand_type type, overlap;
5213 /* Check if specified broadcast is supported in this instruction,
5214 and its broadcast bytes match the memory operand. */
5215 op = i.broadcast->operand;
5216 if (!t->opcode_modifier.broadcast
5217 || !(i.flags[op] & Operand_Mem)
5218 || (!i.types[op].bitfield.unspecified
5219 && !match_broadcast_size (t, op)))
5222 i.error = unsupported_broadcast;
5226 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5227 * i.broadcast->type);
5228 operand_type_set (&type, 0);
5229 switch (i.broadcast->bytes)
5232 type.bitfield.word = 1;
5235 type.bitfield.dword = 1;
5238 type.bitfield.qword = 1;
5241 type.bitfield.xmmword = 1;
5244 type.bitfield.ymmword = 1;
5247 type.bitfield.zmmword = 1;
5253 overlap = operand_type_and (type, t->operand_types[op]);
5254 if (operand_type_all_zero (&overlap))
5257 if (t->opcode_modifier.checkregsize)
5261 type.bitfield.baseindex = 1;
5262 for (j = 0; j < i.operands; ++j)
5265 && !operand_type_register_match(i.types[j],
5266 t->operand_types[j],
5268 t->operand_types[op]))
5273 /* If broadcast is supported in this instruction, we need to check if
5274 operand of one-element size isn't specified without broadcast. */
5275 else if (t->opcode_modifier.broadcast && i.mem_operands)
5277 /* Find memory operand. */
5278 for (op = 0; op < i.operands; op++)
5279 if (operand_type_check (i.types[op], anymem))
5281 gas_assert (op < i.operands);
5282 /* Check size of the memory operand. */
5283 if (match_broadcast_size (t, op))
5285 i.error = broadcast_needed;
5290 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5292 /* Check if requested masking is supported. */
5295 switch (t->opcode_modifier.masking)
5299 case MERGING_MASKING:
5300 if (i.mask->zeroing)
5303 i.error = unsupported_masking;
5307 case DYNAMIC_MASKING:
5308 /* Memory destinations allow only merging masking. */
5309 if (i.mask->zeroing && i.mem_operands)
5311 /* Find memory operand. */
5312 for (op = 0; op < i.operands; op++)
5313 if (i.flags[op] & Operand_Mem)
5315 gas_assert (op < i.operands);
5316 if (op == i.operands - 1)
5318 i.error = unsupported_masking;
5328 /* Check if masking is applied to dest operand. */
5329 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5331 i.error = mask_not_on_destination;
5338 if ((i.rounding->type != saeonly
5339 && !t->opcode_modifier.staticrounding)
5340 || (i.rounding->type == saeonly
5341 && (t->opcode_modifier.staticrounding
5342 || !t->opcode_modifier.sae)))
5344 i.error = unsupported_rc_sae;
5347 /* If the instruction has several immediate operands and one of
5348 them is rounding, the rounding operand should be the last
5349 immediate operand. */
5350 if (i.imm_operands > 1
5351 && i.rounding->operand != (int) (i.imm_operands - 1))
5353 i.error = rc_sae_operand_not_last_imm;
5358 /* Check vector Disp8 operand. */
5359 if (t->opcode_modifier.disp8memshift
5360 && i.disp_encoding != disp_encoding_32bit)
5363 i.memshift = t->opcode_modifier.broadcast - 1;
5364 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5365 i.memshift = t->opcode_modifier.disp8memshift;
5368 const i386_operand_type *type = NULL;
5371 for (op = 0; op < i.operands; op++)
5372 if (operand_type_check (i.types[op], anymem))
5374 if (t->opcode_modifier.evex == EVEXLIG)
5375 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5376 else if (t->operand_types[op].bitfield.xmmword
5377 + t->operand_types[op].bitfield.ymmword
5378 + t->operand_types[op].bitfield.zmmword <= 1)
5379 type = &t->operand_types[op];
5380 else if (!i.types[op].bitfield.unspecified)
5381 type = &i.types[op];
5383 else if (i.types[op].bitfield.regsimd
5384 && t->opcode_modifier.evex != EVEXLIG)
5386 if (i.types[op].bitfield.zmmword)
5388 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5390 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5396 if (type->bitfield.zmmword)
5398 else if (type->bitfield.ymmword)
5400 else if (type->bitfield.xmmword)
5404 /* For the check in fits_in_disp8(). */
5405 if (i.memshift == 0)
5409 for (op = 0; op < i.operands; op++)
5410 if (operand_type_check (i.types[op], disp)
5411 && i.op[op].disps->X_op == O_constant)
5413 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5415 i.types[op].bitfield.disp8 = 1;
5418 i.types[op].bitfield.disp8 = 0;
5427 /* Check if operands are valid for the instruction. Update VEX
5431 VEX_check_operands (const insn_template *t)
5433 if (i.vec_encoding == vex_encoding_evex)
5435 /* This instruction must be encoded with EVEX prefix. */
5436 if (!is_evex_encoding (t))
5438 i.error = unsupported;
5444 if (!t->opcode_modifier.vex)
5446 /* This instruction template doesn't have VEX prefix. */
5447 if (i.vec_encoding != vex_encoding_default)
5449 i.error = unsupported;
5455 /* Only check VEX_Imm4, which must be the first operand. */
5456 if (t->operand_types[0].bitfield.vec_imm4)
5458 if (i.op[0].imms->X_op != O_constant
5459 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5465 /* Turn off Imm8 so that update_imm won't complain. */
5466 i.types[0] = vec_imm4;
5472 static const insn_template *
5473 match_template (char mnem_suffix)
5475 /* Points to template once we've found it. */
5476 const insn_template *t;
5477 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5478 i386_operand_type overlap4;
5479 unsigned int found_reverse_match;
5480 i386_opcode_modifier suffix_check, mnemsuf_check;
5481 i386_operand_type operand_types [MAX_OPERANDS];
5482 int addr_prefix_disp;
5484 unsigned int found_cpu_match, size_match;
5485 unsigned int check_register;
5486 enum i386_error specific_error = 0;
5488 #if MAX_OPERANDS != 5
5489 # error "MAX_OPERANDS must be 5."
5492 found_reverse_match = 0;
5493 addr_prefix_disp = -1;
5495 memset (&suffix_check, 0, sizeof (suffix_check));
5496 if (intel_syntax && i.broadcast)
5498 else if (i.suffix == BYTE_MNEM_SUFFIX)
5499 suffix_check.no_bsuf = 1;
5500 else if (i.suffix == WORD_MNEM_SUFFIX)
5501 suffix_check.no_wsuf = 1;
5502 else if (i.suffix == SHORT_MNEM_SUFFIX)
5503 suffix_check.no_ssuf = 1;
5504 else if (i.suffix == LONG_MNEM_SUFFIX)
5505 suffix_check.no_lsuf = 1;
5506 else if (i.suffix == QWORD_MNEM_SUFFIX)
5507 suffix_check.no_qsuf = 1;
5508 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5509 suffix_check.no_ldsuf = 1;
5511 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5514 switch (mnem_suffix)
5516 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5517 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5518 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5519 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5520 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5524 /* Must have right number of operands. */
5525 i.error = number_of_operands_mismatch;
5527 for (t = current_templates->start; t < current_templates->end; t++)
5529 addr_prefix_disp = -1;
5531 if (i.operands != t->operands)
5534 /* Check processor support. */
5535 i.error = unsupported;
5536 found_cpu_match = (cpu_flags_match (t)
5537 == CPU_FLAGS_PERFECT_MATCH);
5538 if (!found_cpu_match)
5541 /* Check AT&T mnemonic. */
5542 i.error = unsupported_with_intel_mnemonic;
5543 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5546 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5547 i.error = unsupported_syntax;
5548 if ((intel_syntax && t->opcode_modifier.attsyntax)
5549 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5550 || (intel64 && t->opcode_modifier.amd64)
5551 || (!intel64 && t->opcode_modifier.intel64))
5554 /* Check the suffix, except for some instructions in intel mode. */
5555 i.error = invalid_instruction_suffix;
5556 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5557 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5558 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5559 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5560 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5561 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5562 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5564 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5565 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5566 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5567 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5568 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5569 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5570 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5573 size_match = operand_size_match (t);
5577 for (j = 0; j < MAX_OPERANDS; j++)
5578 operand_types[j] = t->operand_types[j];
5580 /* In general, don't allow 64-bit operands in 32-bit mode. */
5581 if (i.suffix == QWORD_MNEM_SUFFIX
5582 && flag_code != CODE_64BIT
5584 ? (!t->opcode_modifier.ignoresize
5585 && !t->opcode_modifier.broadcast
5586 && !intel_float_operand (t->name))
5587 : intel_float_operand (t->name) != 2)
5588 && ((!operand_types[0].bitfield.regmmx
5589 && !operand_types[0].bitfield.regsimd)
5590 || (!operand_types[t->operands > 1].bitfield.regmmx
5591 && !operand_types[t->operands > 1].bitfield.regsimd))
5592 && (t->base_opcode != 0x0fc7
5593 || t->extension_opcode != 1 /* cmpxchg8b */))
5596 /* In general, don't allow 32-bit operands on pre-386. */
5597 else if (i.suffix == LONG_MNEM_SUFFIX
5598 && !cpu_arch_flags.bitfield.cpui386
5600 ? (!t->opcode_modifier.ignoresize
5601 && !intel_float_operand (t->name))
5602 : intel_float_operand (t->name) != 2)
5603 && ((!operand_types[0].bitfield.regmmx
5604 && !operand_types[0].bitfield.regsimd)
5605 || (!operand_types[t->operands > 1].bitfield.regmmx
5606 && !operand_types[t->operands > 1].bitfield.regsimd)))
5609 /* Do not verify operands when there are none. */
5613 /* We've found a match; break out of loop. */
5617 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5618 into Disp32/Disp16/Disp32 operand. */
5619 if (i.prefix[ADDR_PREFIX] != 0)
5621 /* There should be only one Disp operand. */
5625 for (j = 0; j < MAX_OPERANDS; j++)
5627 if (operand_types[j].bitfield.disp16)
5629 addr_prefix_disp = j;
5630 operand_types[j].bitfield.disp32 = 1;
5631 operand_types[j].bitfield.disp16 = 0;
5637 for (j = 0; j < MAX_OPERANDS; j++)
5639 if (operand_types[j].bitfield.disp32)
5641 addr_prefix_disp = j;
5642 operand_types[j].bitfield.disp32 = 0;
5643 operand_types[j].bitfield.disp16 = 1;
5649 for (j = 0; j < MAX_OPERANDS; j++)
5651 if (operand_types[j].bitfield.disp64)
5653 addr_prefix_disp = j;
5654 operand_types[j].bitfield.disp64 = 0;
5655 operand_types[j].bitfield.disp32 = 1;
5663 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5664 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5667 /* We check register size if needed. */
5668 if (t->opcode_modifier.checkregsize)
5670 check_register = (1 << t->operands) - 1;
5672 check_register &= ~(1 << i.broadcast->operand);
5677 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5678 switch (t->operands)
5681 if (!operand_type_match (overlap0, i.types[0]))
5685 /* xchg %eax, %eax is a special case. It is an alias for nop
5686 only in 32bit mode and we can use opcode 0x90. In 64bit
5687 mode, we can't use 0x90 for xchg %eax, %eax since it should
5688 zero-extend %eax to %rax. */
5689 if (flag_code == CODE_64BIT
5690 && t->base_opcode == 0x90
5691 && operand_type_equal (&i.types [0], &acc32)
5692 && operand_type_equal (&i.types [1], &acc32))
5694 /* xrelease mov %eax, <disp> is another special case. It must not
5695 match the accumulator-only encoding of mov. */
5696 if (flag_code != CODE_64BIT
5698 && t->base_opcode == 0xa0
5699 && i.types[0].bitfield.acc
5700 && operand_type_check (i.types[1], anymem))
5702 if (!(size_match & MATCH_STRAIGHT))
5704 /* Reverse direction of operands if swapping is possible in the first
5705 place (operands need to be symmetric) and
5706 - the load form is requested, and the template is a store form,
5707 - the store form is requested, and the template is a load form,
5708 - the non-default (swapped) form is requested. */
5709 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
5710 if (t->opcode_modifier.d && i.reg_operands == 2
5711 && !operand_type_all_zero (&overlap1))
5712 switch (i.dir_encoding)
5714 case dir_encoding_load:
5715 if (operand_type_check (operand_types[i.operands - 1], anymem)
5716 || operand_types[i.operands - 1].bitfield.regmem)
5720 case dir_encoding_store:
5721 if (!operand_type_check (operand_types[i.operands - 1], anymem)
5722 && !operand_types[i.operands - 1].bitfield.regmem)
5726 case dir_encoding_swap:
5729 case dir_encoding_default:
5735 /* If we want store form, we skip the current load. */
5736 if ((i.dir_encoding == dir_encoding_store
5737 || i.dir_encoding == dir_encoding_swap)
5738 && i.mem_operands == 0
5739 && t->opcode_modifier.load)
5744 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5745 if (!operand_type_match (overlap0, i.types[0])
5746 || !operand_type_match (overlap1, i.types[1])
5747 || ((check_register & 3) == 3
5748 && !operand_type_register_match (i.types[0],
5753 /* Check if other direction is valid ... */
5754 if (!t->opcode_modifier.d)
5758 if (!(size_match & MATCH_REVERSE))
5760 /* Try reversing direction of operands. */
5761 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5762 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5763 if (!operand_type_match (overlap0, i.types[0])
5764 || !operand_type_match (overlap1, i.types[1])
5766 && !operand_type_register_match (i.types[0],
5771 /* Does not match either direction. */
5774 /* found_reverse_match holds which of D or FloatR
5776 if (!t->opcode_modifier.d)
5777 found_reverse_match = 0;
5778 else if (operand_types[0].bitfield.tbyte)
5779 found_reverse_match = Opcode_FloatD;
5781 found_reverse_match = Opcode_D;
5782 if (t->opcode_modifier.floatr)
5783 found_reverse_match |= Opcode_FloatR;
5787 /* Found a forward 2 operand match here. */
5788 switch (t->operands)
5791 overlap4 = operand_type_and (i.types[4],
5795 overlap3 = operand_type_and (i.types[3],
5799 overlap2 = operand_type_and (i.types[2],
5804 switch (t->operands)
5807 if (!operand_type_match (overlap4, i.types[4])
5808 || !operand_type_register_match (i.types[3],
5815 if (!operand_type_match (overlap3, i.types[3])
5816 || ((check_register & 0xa) == 0xa
5817 && !operand_type_register_match (i.types[1],
5821 || ((check_register & 0xc) == 0xc
5822 && !operand_type_register_match (i.types[2],
5829 /* Here we make use of the fact that there are no
5830 reverse match 3 operand instructions. */
5831 if (!operand_type_match (overlap2, i.types[2])
5832 || ((check_register & 5) == 5
5833 && !operand_type_register_match (i.types[0],
5837 || ((check_register & 6) == 6
5838 && !operand_type_register_match (i.types[1],
5846 /* Found either forward/reverse 2, 3 or 4 operand match here:
5847 slip through to break. */
5849 if (!found_cpu_match)
5851 found_reverse_match = 0;
5855 /* Check if vector and VEX operands are valid. */
5856 if (check_VecOperands (t) || VEX_check_operands (t))
5858 specific_error = i.error;
5862 /* We've found a match; break out of loop. */
5866 if (t == current_templates->end)
5868 /* We found no match. */
5869 const char *err_msg;
5870 switch (specific_error ? specific_error : i.error)
5874 case operand_size_mismatch:
5875 err_msg = _("operand size mismatch");
5877 case operand_type_mismatch:
5878 err_msg = _("operand type mismatch");
5880 case register_type_mismatch:
5881 err_msg = _("register type mismatch");
5883 case number_of_operands_mismatch:
5884 err_msg = _("number of operands mismatch");
5886 case invalid_instruction_suffix:
5887 err_msg = _("invalid instruction suffix");
5890 err_msg = _("constant doesn't fit in 4 bits");
5892 case unsupported_with_intel_mnemonic:
5893 err_msg = _("unsupported with Intel mnemonic");
5895 case unsupported_syntax:
5896 err_msg = _("unsupported syntax");
5899 as_bad (_("unsupported instruction `%s'"),
5900 current_templates->start->name);
5902 case invalid_vsib_address:
5903 err_msg = _("invalid VSIB address");
5905 case invalid_vector_register_set:
5906 err_msg = _("mask, index, and destination registers must be distinct");
5908 case unsupported_vector_index_register:
5909 err_msg = _("unsupported vector index register");
5911 case unsupported_broadcast:
5912 err_msg = _("unsupported broadcast");
5914 case broadcast_needed:
5915 err_msg = _("broadcast is needed for operand of such type");
5917 case unsupported_masking:
5918 err_msg = _("unsupported masking");
5920 case mask_not_on_destination:
5921 err_msg = _("mask not on destination operand");
5923 case no_default_mask:
5924 err_msg = _("default mask isn't allowed");
5926 case unsupported_rc_sae:
5927 err_msg = _("unsupported static rounding/sae");
5929 case rc_sae_operand_not_last_imm:
5931 err_msg = _("RC/SAE operand must precede immediate operands");
5933 err_msg = _("RC/SAE operand must follow immediate operands");
5935 case invalid_register_operand:
5936 err_msg = _("invalid register operand");
5939 as_bad (_("%s for `%s'"), err_msg,
5940 current_templates->start->name);
5944 if (!quiet_warnings)
5947 && (i.types[0].bitfield.jumpabsolute
5948 != operand_types[0].bitfield.jumpabsolute))
5950 as_warn (_("indirect %s without `*'"), t->name);
5953 if (t->opcode_modifier.isprefix
5954 && t->opcode_modifier.ignoresize)
5956 /* Warn them that a data or address size prefix doesn't
5957 affect assembly of the next line of code. */
5958 as_warn (_("stand-alone `%s' prefix"), t->name);
5962 /* Copy the template we found. */
5965 if (addr_prefix_disp != -1)
5966 i.tm.operand_types[addr_prefix_disp]
5967 = operand_types[addr_prefix_disp];
5969 if (found_reverse_match)
5971 /* If we found a reverse match we must alter the opcode
5972 direction bit. found_reverse_match holds bits to change
5973 (different for int & float insns). */
5975 i.tm.base_opcode ^= found_reverse_match;
5977 i.tm.operand_types[0] = operand_types[1];
5978 i.tm.operand_types[1] = operand_types[0];
5987 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5988 if (i.tm.operand_types[mem_op].bitfield.esseg)
5990 if (i.seg[0] != NULL && i.seg[0] != &es)
5992 as_bad (_("`%s' operand %d must use `%ses' segment"),
5998 /* There's only ever one segment override allowed per instruction.
5999 This instruction possibly has a legal segment override on the
6000 second operand, so copy the segment to where non-string
6001 instructions store it, allowing common code. */
6002 i.seg[0] = i.seg[1];
6004 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
6006 if (i.seg[1] != NULL && i.seg[1] != &es)
6008 as_bad (_("`%s' operand %d must use `%ses' segment"),
6019 process_suffix (void)
6021 /* If matched instruction specifies an explicit instruction mnemonic
6023 if (i.tm.opcode_modifier.size16)
6024 i.suffix = WORD_MNEM_SUFFIX;
6025 else if (i.tm.opcode_modifier.size32)
6026 i.suffix = LONG_MNEM_SUFFIX;
6027 else if (i.tm.opcode_modifier.size64)
6028 i.suffix = QWORD_MNEM_SUFFIX;
6029 else if (i.reg_operands)
6031 /* If there's no instruction mnemonic suffix we try to invent one
6032 based on register operands. */
6035 /* We take i.suffix from the last register operand specified,
6036 Destination register type is more significant than source
6037 register type. crc32 in SSE4.2 prefers source register
6039 if (i.tm.base_opcode == 0xf20f38f1)
6041 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
6042 i.suffix = WORD_MNEM_SUFFIX;
6043 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
6044 i.suffix = LONG_MNEM_SUFFIX;
6045 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
6046 i.suffix = QWORD_MNEM_SUFFIX;
6048 else if (i.tm.base_opcode == 0xf20f38f0)
6050 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
6051 i.suffix = BYTE_MNEM_SUFFIX;
6058 if (i.tm.base_opcode == 0xf20f38f1
6059 || i.tm.base_opcode == 0xf20f38f0)
6061 /* We have to know the operand size for crc32. */
6062 as_bad (_("ambiguous memory operand size for `%s`"),
6067 for (op = i.operands; --op >= 0;)
6068 if (!i.tm.operand_types[op].bitfield.inoutportreg
6069 && !i.tm.operand_types[op].bitfield.shiftcount)
6071 if (!i.types[op].bitfield.reg)
6073 if (i.types[op].bitfield.byte)
6074 i.suffix = BYTE_MNEM_SUFFIX;
6075 else if (i.types[op].bitfield.word)
6076 i.suffix = WORD_MNEM_SUFFIX;
6077 else if (i.types[op].bitfield.dword)
6078 i.suffix = LONG_MNEM_SUFFIX;
6079 else if (i.types[op].bitfield.qword)
6080 i.suffix = QWORD_MNEM_SUFFIX;
6087 else if (i.suffix == BYTE_MNEM_SUFFIX)
6090 && i.tm.opcode_modifier.ignoresize
6091 && i.tm.opcode_modifier.no_bsuf)
6093 else if (!check_byte_reg ())
6096 else if (i.suffix == LONG_MNEM_SUFFIX)
6099 && i.tm.opcode_modifier.ignoresize
6100 && i.tm.opcode_modifier.no_lsuf
6101 && !i.tm.opcode_modifier.todword
6102 && !i.tm.opcode_modifier.toqword)
6104 else if (!check_long_reg ())
6107 else if (i.suffix == QWORD_MNEM_SUFFIX)
6110 && i.tm.opcode_modifier.ignoresize
6111 && i.tm.opcode_modifier.no_qsuf
6112 && !i.tm.opcode_modifier.todword
6113 && !i.tm.opcode_modifier.toqword)
6115 else if (!check_qword_reg ())
6118 else if (i.suffix == WORD_MNEM_SUFFIX)
6121 && i.tm.opcode_modifier.ignoresize
6122 && i.tm.opcode_modifier.no_wsuf)
6124 else if (!check_word_reg ())
6127 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6128 /* Do nothing if the instruction is going to ignore the prefix. */
6133 else if (i.tm.opcode_modifier.defaultsize
6135 /* exclude fldenv/frstor/fsave/fstenv */
6136 && i.tm.opcode_modifier.no_ssuf)
6138 i.suffix = stackop_size;
6140 else if (intel_syntax
6142 && (i.tm.operand_types[0].bitfield.jumpabsolute
6143 || i.tm.opcode_modifier.jumpbyte
6144 || i.tm.opcode_modifier.jumpintersegment
6145 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6146 && i.tm.extension_opcode <= 3)))
6151 if (!i.tm.opcode_modifier.no_qsuf)
6153 i.suffix = QWORD_MNEM_SUFFIX;
6158 if (!i.tm.opcode_modifier.no_lsuf)
6159 i.suffix = LONG_MNEM_SUFFIX;
6162 if (!i.tm.opcode_modifier.no_wsuf)
6163 i.suffix = WORD_MNEM_SUFFIX;
6172 if (i.tm.opcode_modifier.w)
6174 as_bad (_("no instruction mnemonic suffix given and "
6175 "no register operands; can't size instruction"));
6181 unsigned int suffixes;
6183 suffixes = !i.tm.opcode_modifier.no_bsuf;
6184 if (!i.tm.opcode_modifier.no_wsuf)
6186 if (!i.tm.opcode_modifier.no_lsuf)
6188 if (!i.tm.opcode_modifier.no_ldsuf)
6190 if (!i.tm.opcode_modifier.no_ssuf)
6192 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6195 /* There are more than suffix matches. */
6196 if (i.tm.opcode_modifier.w
6197 || ((suffixes & (suffixes - 1))
6198 && !i.tm.opcode_modifier.defaultsize
6199 && !i.tm.opcode_modifier.ignoresize))
6201 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6207 /* Change the opcode based on the operand size given by i.suffix. */
6210 /* Size floating point instruction. */
6211 case LONG_MNEM_SUFFIX:
6212 if (i.tm.opcode_modifier.floatmf)
6214 i.tm.base_opcode ^= 4;
6218 case WORD_MNEM_SUFFIX:
6219 case QWORD_MNEM_SUFFIX:
6220 /* It's not a byte, select word/dword operation. */
6221 if (i.tm.opcode_modifier.w)
6223 if (i.tm.opcode_modifier.shortform)
6224 i.tm.base_opcode |= 8;
6226 i.tm.base_opcode |= 1;
6229 case SHORT_MNEM_SUFFIX:
6230 /* Now select between word & dword operations via the operand
6231 size prefix, except for instructions that will ignore this
6233 if (i.reg_operands > 0
6234 && i.types[0].bitfield.reg
6235 && i.tm.opcode_modifier.addrprefixopreg
6236 && (i.tm.opcode_modifier.immext
6237 || i.operands == 1))
6239 /* The address size override prefix changes the size of the
6241 if ((flag_code == CODE_32BIT
6242 && i.op[0].regs->reg_type.bitfield.word)
6243 || (flag_code != CODE_32BIT
6244 && i.op[0].regs->reg_type.bitfield.dword))
6245 if (!add_prefix (ADDR_PREFIX_OPCODE))
6248 else if (i.suffix != QWORD_MNEM_SUFFIX
6249 && !i.tm.opcode_modifier.ignoresize
6250 && !i.tm.opcode_modifier.floatmf
6251 && !i.tm.opcode_modifier.vex
6252 && !i.tm.opcode_modifier.vexopcode
6253 && !is_evex_encoding (&i.tm)
6254 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6255 || (flag_code == CODE_64BIT
6256 && i.tm.opcode_modifier.jumpbyte)))
6258 unsigned int prefix = DATA_PREFIX_OPCODE;
6260 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6261 prefix = ADDR_PREFIX_OPCODE;
6263 if (!add_prefix (prefix))
6267 /* Set mode64 for an operand. */
6268 if (i.suffix == QWORD_MNEM_SUFFIX
6269 && flag_code == CODE_64BIT
6270 && !i.tm.opcode_modifier.norex64
6271 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6273 && ! (i.operands == 2
6274 && i.tm.base_opcode == 0x90
6275 && i.tm.extension_opcode == None
6276 && operand_type_equal (&i.types [0], &acc64)
6277 && operand_type_equal (&i.types [1], &acc64)))
6283 if (i.reg_operands != 0
6285 && i.tm.opcode_modifier.addrprefixopreg
6286 && !i.tm.opcode_modifier.immext)
6288 /* Check invalid register operand when the address size override
6289 prefix changes the size of register operands. */
6291 enum { need_word, need_dword, need_qword } need;
6293 if (flag_code == CODE_32BIT)
6294 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6297 if (i.prefix[ADDR_PREFIX])
6300 need = flag_code == CODE_64BIT ? need_qword : need_word;
6303 for (op = 0; op < i.operands; op++)
6304 if (i.types[op].bitfield.reg
6305 && ((need == need_word
6306 && !i.op[op].regs->reg_type.bitfield.word)
6307 || (need == need_dword
6308 && !i.op[op].regs->reg_type.bitfield.dword)
6309 || (need == need_qword
6310 && !i.op[op].regs->reg_type.bitfield.qword)))
6312 as_bad (_("invalid register operand size for `%s'"),
6322 check_byte_reg (void)
6326 for (op = i.operands; --op >= 0;)
6328 /* Skip non-register operands. */
6329 if (!i.types[op].bitfield.reg)
6332 /* If this is an eight bit register, it's OK. If it's the 16 or
6333 32 bit version of an eight bit register, we will just use the
6334 low portion, and that's OK too. */
6335 if (i.types[op].bitfield.byte)
6338 /* I/O port address operands are OK too. */
6339 if (i.tm.operand_types[op].bitfield.inoutportreg)
6342 /* crc32 doesn't generate this warning. */
6343 if (i.tm.base_opcode == 0xf20f38f0)
6346 if ((i.types[op].bitfield.word
6347 || i.types[op].bitfield.dword
6348 || i.types[op].bitfield.qword)
6349 && i.op[op].regs->reg_num < 4
6350 /* Prohibit these changes in 64bit mode, since the lowering
6351 would be more complicated. */
6352 && flag_code != CODE_64BIT)
6354 #if REGISTER_WARNINGS
6355 if (!quiet_warnings)
6356 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6358 (i.op[op].regs + (i.types[op].bitfield.word
6359 ? REGNAM_AL - REGNAM_AX
6360 : REGNAM_AL - REGNAM_EAX))->reg_name,
6362 i.op[op].regs->reg_name,
6367 /* Any other register is bad. */
6368 if (i.types[op].bitfield.reg
6369 || i.types[op].bitfield.regmmx
6370 || i.types[op].bitfield.regsimd
6371 || i.types[op].bitfield.sreg2
6372 || i.types[op].bitfield.sreg3
6373 || i.types[op].bitfield.control
6374 || i.types[op].bitfield.debug
6375 || i.types[op].bitfield.test)
6377 as_bad (_("`%s%s' not allowed with `%s%c'"),
6379 i.op[op].regs->reg_name,
6389 check_long_reg (void)
6393 for (op = i.operands; --op >= 0;)
6394 /* Skip non-register operands. */
6395 if (!i.types[op].bitfield.reg)
6397 /* Reject eight bit registers, except where the template requires
6398 them. (eg. movzb) */
6399 else if (i.types[op].bitfield.byte
6400 && (i.tm.operand_types[op].bitfield.reg
6401 || i.tm.operand_types[op].bitfield.acc)
6402 && (i.tm.operand_types[op].bitfield.word
6403 || i.tm.operand_types[op].bitfield.dword))
6405 as_bad (_("`%s%s' not allowed with `%s%c'"),
6407 i.op[op].regs->reg_name,
6412 /* Warn if the e prefix on a general reg is missing. */
6413 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6414 && i.types[op].bitfield.word
6415 && (i.tm.operand_types[op].bitfield.reg
6416 || i.tm.operand_types[op].bitfield.acc)
6417 && i.tm.operand_types[op].bitfield.dword)
6419 /* Prohibit these changes in the 64bit mode, since the
6420 lowering is more complicated. */
6421 if (flag_code == CODE_64BIT)
6423 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6424 register_prefix, i.op[op].regs->reg_name,
6428 #if REGISTER_WARNINGS
6429 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6431 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6432 register_prefix, i.op[op].regs->reg_name, i.suffix);
6435 /* Warn if the r prefix on a general reg is present. */
6436 else if (i.types[op].bitfield.qword
6437 && (i.tm.operand_types[op].bitfield.reg
6438 || i.tm.operand_types[op].bitfield.acc)
6439 && i.tm.operand_types[op].bitfield.dword)
6442 && i.tm.opcode_modifier.toqword
6443 && !i.types[0].bitfield.regsimd)
6445 /* Convert to QWORD. We want REX byte. */
6446 i.suffix = QWORD_MNEM_SUFFIX;
6450 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6451 register_prefix, i.op[op].regs->reg_name,
6460 check_qword_reg (void)
6464 for (op = i.operands; --op >= 0; )
6465 /* Skip non-register operands. */
6466 if (!i.types[op].bitfield.reg)
6468 /* Reject eight bit registers, except where the template requires
6469 them. (eg. movzb) */
6470 else if (i.types[op].bitfield.byte
6471 && (i.tm.operand_types[op].bitfield.reg
6472 || i.tm.operand_types[op].bitfield.acc)
6473 && (i.tm.operand_types[op].bitfield.word
6474 || i.tm.operand_types[op].bitfield.dword))
6476 as_bad (_("`%s%s' not allowed with `%s%c'"),
6478 i.op[op].regs->reg_name,
6483 /* Warn if the r prefix on a general reg is missing. */
6484 else if ((i.types[op].bitfield.word
6485 || i.types[op].bitfield.dword)
6486 && (i.tm.operand_types[op].bitfield.reg
6487 || i.tm.operand_types[op].bitfield.acc)
6488 && i.tm.operand_types[op].bitfield.qword)
6490 /* Prohibit these changes in the 64bit mode, since the
6491 lowering is more complicated. */
6493 && i.tm.opcode_modifier.todword
6494 && !i.types[0].bitfield.regsimd)
6496 /* Convert to DWORD. We don't want REX byte. */
6497 i.suffix = LONG_MNEM_SUFFIX;
6501 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6502 register_prefix, i.op[op].regs->reg_name,
6511 check_word_reg (void)
6514 for (op = i.operands; --op >= 0;)
6515 /* Skip non-register operands. */
6516 if (!i.types[op].bitfield.reg)
6518 /* Reject eight bit registers, except where the template requires
6519 them. (eg. movzb) */
6520 else if (i.types[op].bitfield.byte
6521 && (i.tm.operand_types[op].bitfield.reg
6522 || i.tm.operand_types[op].bitfield.acc)
6523 && (i.tm.operand_types[op].bitfield.word
6524 || i.tm.operand_types[op].bitfield.dword))
6526 as_bad (_("`%s%s' not allowed with `%s%c'"),
6528 i.op[op].regs->reg_name,
6533 /* Warn if the e or r prefix on a general reg is present. */
6534 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6535 && (i.types[op].bitfield.dword
6536 || i.types[op].bitfield.qword)
6537 && (i.tm.operand_types[op].bitfield.reg
6538 || i.tm.operand_types[op].bitfield.acc)
6539 && i.tm.operand_types[op].bitfield.word)
6541 /* Prohibit these changes in the 64bit mode, since the
6542 lowering is more complicated. */
6543 if (flag_code == CODE_64BIT)
6545 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6546 register_prefix, i.op[op].regs->reg_name,
6550 #if REGISTER_WARNINGS
6551 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6553 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6554 register_prefix, i.op[op].regs->reg_name, i.suffix);
6561 update_imm (unsigned int j)
6563 i386_operand_type overlap = i.types[j];
6564 if ((overlap.bitfield.imm8
6565 || overlap.bitfield.imm8s
6566 || overlap.bitfield.imm16
6567 || overlap.bitfield.imm32
6568 || overlap.bitfield.imm32s
6569 || overlap.bitfield.imm64)
6570 && !operand_type_equal (&overlap, &imm8)
6571 && !operand_type_equal (&overlap, &imm8s)
6572 && !operand_type_equal (&overlap, &imm16)
6573 && !operand_type_equal (&overlap, &imm32)
6574 && !operand_type_equal (&overlap, &imm32s)
6575 && !operand_type_equal (&overlap, &imm64))
6579 i386_operand_type temp;
6581 operand_type_set (&temp, 0);
6582 if (i.suffix == BYTE_MNEM_SUFFIX)
6584 temp.bitfield.imm8 = overlap.bitfield.imm8;
6585 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6587 else if (i.suffix == WORD_MNEM_SUFFIX)
6588 temp.bitfield.imm16 = overlap.bitfield.imm16;
6589 else if (i.suffix == QWORD_MNEM_SUFFIX)
6591 temp.bitfield.imm64 = overlap.bitfield.imm64;
6592 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6595 temp.bitfield.imm32 = overlap.bitfield.imm32;
6598 else if (operand_type_equal (&overlap, &imm16_32_32s)
6599 || operand_type_equal (&overlap, &imm16_32)
6600 || operand_type_equal (&overlap, &imm16_32s))
6602 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6607 if (!operand_type_equal (&overlap, &imm8)
6608 && !operand_type_equal (&overlap, &imm8s)
6609 && !operand_type_equal (&overlap, &imm16)
6610 && !operand_type_equal (&overlap, &imm32)
6611 && !operand_type_equal (&overlap, &imm32s)
6612 && !operand_type_equal (&overlap, &imm64))
6614 as_bad (_("no instruction mnemonic suffix given; "
6615 "can't determine immediate size"));
6619 i.types[j] = overlap;
6629 /* Update the first 2 immediate operands. */
6630 n = i.operands > 2 ? 2 : i.operands;
6633 for (j = 0; j < n; j++)
6634 if (update_imm (j) == 0)
6637 /* The 3rd operand can't be immediate operand. */
6638 gas_assert (operand_type_check (i.types[2], imm) == 0);
6645 process_operands (void)
6647 /* Default segment register this instruction will use for memory
6648 accesses. 0 means unknown. This is only for optimizing out
6649 unnecessary segment overrides. */
6650 const seg_entry *default_seg = 0;
6652 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6654 unsigned int dupl = i.operands;
6655 unsigned int dest = dupl - 1;
6658 /* The destination must be an xmm register. */
6659 gas_assert (i.reg_operands
6660 && MAX_OPERANDS > dupl
6661 && operand_type_equal (&i.types[dest], ®xmm));
6663 if (i.tm.operand_types[0].bitfield.acc
6664 && i.tm.operand_types[0].bitfield.xmmword)
6666 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6668 /* Keep xmm0 for instructions with VEX prefix and 3
6670 i.tm.operand_types[0].bitfield.acc = 0;
6671 i.tm.operand_types[0].bitfield.regsimd = 1;
6676 /* We remove the first xmm0 and keep the number of
6677 operands unchanged, which in fact duplicates the
6679 for (j = 1; j < i.operands; j++)
6681 i.op[j - 1] = i.op[j];
6682 i.types[j - 1] = i.types[j];
6683 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6687 else if (i.tm.opcode_modifier.implicit1stxmm0)
6689 gas_assert ((MAX_OPERANDS - 1) > dupl
6690 && (i.tm.opcode_modifier.vexsources
6693 /* Add the implicit xmm0 for instructions with VEX prefix
6695 for (j = i.operands; j > 0; j--)
6697 i.op[j] = i.op[j - 1];
6698 i.types[j] = i.types[j - 1];
6699 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6702 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6703 i.types[0] = regxmm;
6704 i.tm.operand_types[0] = regxmm;
6707 i.reg_operands += 2;
6712 i.op[dupl] = i.op[dest];
6713 i.types[dupl] = i.types[dest];
6714 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6723 i.op[dupl] = i.op[dest];
6724 i.types[dupl] = i.types[dest];
6725 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6728 if (i.tm.opcode_modifier.immext)
6731 else if (i.tm.operand_types[0].bitfield.acc
6732 && i.tm.operand_types[0].bitfield.xmmword)
6736 for (j = 1; j < i.operands; j++)
6738 i.op[j - 1] = i.op[j];
6739 i.types[j - 1] = i.types[j];
6741 /* We need to adjust fields in i.tm since they are used by
6742 build_modrm_byte. */
6743 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6750 else if (i.tm.opcode_modifier.implicitquadgroup)
6752 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6754 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6755 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6756 regnum = register_number (i.op[1].regs);
6757 first_reg_in_group = regnum & ~3;
6758 last_reg_in_group = first_reg_in_group + 3;
6759 if (regnum != first_reg_in_group)
6760 as_warn (_("source register `%s%s' implicitly denotes"
6761 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6762 register_prefix, i.op[1].regs->reg_name,
6763 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6764 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6767 else if (i.tm.opcode_modifier.regkludge)
6769 /* The imul $imm, %reg instruction is converted into
6770 imul $imm, %reg, %reg, and the clr %reg instruction
6771 is converted into xor %reg, %reg. */
6773 unsigned int first_reg_op;
6775 if (operand_type_check (i.types[0], reg))
6779 /* Pretend we saw the extra register operand. */
6780 gas_assert (i.reg_operands == 1
6781 && i.op[first_reg_op + 1].regs == 0);
6782 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6783 i.types[first_reg_op + 1] = i.types[first_reg_op];
6788 if (i.tm.opcode_modifier.shortform)
6790 if (i.types[0].bitfield.sreg2
6791 || i.types[0].bitfield.sreg3)
6793 if (i.tm.base_opcode == POP_SEG_SHORT
6794 && i.op[0].regs->reg_num == 1)
6796 as_bad (_("you can't `pop %scs'"), register_prefix);
6799 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6800 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6805 /* The register or float register operand is in operand
6809 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6810 || operand_type_check (i.types[0], reg))
6814 /* Register goes in low 3 bits of opcode. */
6815 i.tm.base_opcode |= i.op[op].regs->reg_num;
6816 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6818 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6820 /* Warn about some common errors, but press on regardless.
6821 The first case can be generated by gcc (<= 2.8.1). */
6822 if (i.operands == 2)
6824 /* Reversed arguments on faddp, fsubp, etc. */
6825 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6826 register_prefix, i.op[!intel_syntax].regs->reg_name,
6827 register_prefix, i.op[intel_syntax].regs->reg_name);
6831 /* Extraneous `l' suffix on fp insn. */
6832 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6833 register_prefix, i.op[0].regs->reg_name);
6838 else if (i.tm.opcode_modifier.modrm)
6840 /* The opcode is completed (modulo i.tm.extension_opcode which
6841 must be put into the modrm byte). Now, we make the modrm and
6842 index base bytes based on all the info we've collected. */
6844 default_seg = build_modrm_byte ();
6846 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6850 else if (i.tm.opcode_modifier.isstring)
6852 /* For the string instructions that allow a segment override
6853 on one of their operands, the default segment is ds. */
6857 if (i.tm.base_opcode == 0x8d /* lea */
6860 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6862 /* If a segment was explicitly specified, and the specified segment
6863 is not the default, use an opcode prefix to select it. If we
6864 never figured out what the default segment is, then default_seg
6865 will be zero at this point, and the specified segment prefix will
6867 if ((i.seg[0]) && (i.seg[0] != default_seg))
6869 if (!add_prefix (i.seg[0]->seg_prefix))
6875 static const seg_entry *
6876 build_modrm_byte (void)
6878 const seg_entry *default_seg = 0;
6879 unsigned int source, dest;
6882 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6885 unsigned int nds, reg_slot;
6888 dest = i.operands - 1;
6891 /* There are 2 kinds of instructions:
6892 1. 5 operands: 4 register operands or 3 register operands
6893 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6894 VexW0 or VexW1. The destination must be either XMM, YMM or
6896 2. 4 operands: 4 register operands or 3 register operands
6897 plus 1 memory operand, with VexXDS. */
6898 gas_assert ((i.reg_operands == 4
6899 || (i.reg_operands == 3 && i.mem_operands == 1))
6900 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6901 && i.tm.opcode_modifier.vexw
6902 && i.tm.operand_types[dest].bitfield.regsimd);
6904 /* If VexW1 is set, the first non-immediate operand is the source and
6905 the second non-immediate one is encoded in the immediate operand. */
6906 if (i.tm.opcode_modifier.vexw == VEXW1)
6908 source = i.imm_operands;
6909 reg_slot = i.imm_operands + 1;
6913 source = i.imm_operands + 1;
6914 reg_slot = i.imm_operands;
6917 if (i.imm_operands == 0)
6919 /* When there is no immediate operand, generate an 8bit
6920 immediate operand to encode the first operand. */
6921 exp = &im_expressions[i.imm_operands++];
6922 i.op[i.operands].imms = exp;
6923 i.types[i.operands] = imm8;
6926 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6927 exp->X_op = O_constant;
6928 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6929 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6933 unsigned int imm_slot;
6935 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6937 if (i.tm.opcode_modifier.immext)
6939 /* When ImmExt is set, the immediate byte is the last
6941 imm_slot = i.operands - 1;
6949 /* Turn on Imm8 so that output_imm will generate it. */
6950 i.types[imm_slot].bitfield.imm8 = 1;
6953 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6954 i.op[imm_slot].imms->X_add_number
6955 |= register_number (i.op[reg_slot].regs) << 4;
6956 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6959 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6960 i.vex.register_specifier = i.op[nds].regs;
6965 /* i.reg_operands MUST be the number of real register operands;
6966 implicit registers do not count. If there are 3 register
6967 operands, it must be a instruction with VexNDS. For a
6968 instruction with VexNDD, the destination register is encoded
6969 in VEX prefix. If there are 4 register operands, it must be
6970 a instruction with VEX prefix and 3 sources. */
6971 if (i.mem_operands == 0
6972 && ((i.reg_operands == 2
6973 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6974 || (i.reg_operands == 3
6975 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6976 || (i.reg_operands == 4 && vex_3_sources)))
6984 /* When there are 3 operands, one of them may be immediate,
6985 which may be the first or the last operand. Otherwise,
6986 the first operand must be shift count register (cl) or it
6987 is an instruction with VexNDS. */
6988 gas_assert (i.imm_operands == 1
6989 || (i.imm_operands == 0
6990 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6991 || i.types[0].bitfield.shiftcount)));
6992 if (operand_type_check (i.types[0], imm)
6993 || i.types[0].bitfield.shiftcount)
6999 /* When there are 4 operands, the first two must be 8bit
7000 immediate operands. The source operand will be the 3rd
7003 For instructions with VexNDS, if the first operand
7004 an imm8, the source operand is the 2nd one. If the last
7005 operand is imm8, the source operand is the first one. */
7006 gas_assert ((i.imm_operands == 2
7007 && i.types[0].bitfield.imm8
7008 && i.types[1].bitfield.imm8)
7009 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7010 && i.imm_operands == 1
7011 && (i.types[0].bitfield.imm8
7012 || i.types[i.operands - 1].bitfield.imm8
7014 if (i.imm_operands == 2)
7018 if (i.types[0].bitfield.imm8)
7025 if (is_evex_encoding (&i.tm))
7027 /* For EVEX instructions, when there are 5 operands, the
7028 first one must be immediate operand. If the second one
7029 is immediate operand, the source operand is the 3th
7030 one. If the last one is immediate operand, the source
7031 operand is the 2nd one. */
7032 gas_assert (i.imm_operands == 2
7033 && i.tm.opcode_modifier.sae
7034 && operand_type_check (i.types[0], imm));
7035 if (operand_type_check (i.types[1], imm))
7037 else if (operand_type_check (i.types[4], imm))
7051 /* RC/SAE operand could be between DEST and SRC. That happens
7052 when one operand is GPR and the other one is XMM/YMM/ZMM
7054 if (i.rounding && i.rounding->operand == (int) dest)
7057 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7059 /* For instructions with VexNDS, the register-only source
7060 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7061 register. It is encoded in VEX prefix. We need to
7062 clear RegMem bit before calling operand_type_equal. */
7064 i386_operand_type op;
7067 /* Check register-only source operand when two source
7068 operands are swapped. */
7069 if (!i.tm.operand_types[source].bitfield.baseindex
7070 && i.tm.operand_types[dest].bitfield.baseindex)
7078 op = i.tm.operand_types[vvvv];
7079 op.bitfield.regmem = 0;
7080 if ((dest + 1) >= i.operands
7081 || ((!op.bitfield.reg
7082 || (!op.bitfield.dword && !op.bitfield.qword))
7083 && !op.bitfield.regsimd
7084 && !operand_type_equal (&op, ®mask)))
7086 i.vex.register_specifier = i.op[vvvv].regs;
7092 /* One of the register operands will be encoded in the i.tm.reg
7093 field, the other in the combined i.tm.mode and i.tm.regmem
7094 fields. If no form of this instruction supports a memory
7095 destination operand, then we assume the source operand may
7096 sometimes be a memory operand and so we need to store the
7097 destination in the i.rm.reg field. */
7098 if (!i.tm.operand_types[dest].bitfield.regmem
7099 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7101 i.rm.reg = i.op[dest].regs->reg_num;
7102 i.rm.regmem = i.op[source].regs->reg_num;
7103 if (i.op[dest].regs->reg_type.bitfield.regmmx
7104 || i.op[source].regs->reg_type.bitfield.regmmx)
7105 i.has_regmmx = TRUE;
7106 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7107 || i.op[source].regs->reg_type.bitfield.regsimd)
7109 if (i.types[dest].bitfield.zmmword
7110 || i.types[source].bitfield.zmmword)
7111 i.has_regzmm = TRUE;
7112 else if (i.types[dest].bitfield.ymmword
7113 || i.types[source].bitfield.ymmword)
7114 i.has_regymm = TRUE;
7116 i.has_regxmm = TRUE;
7118 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7120 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7122 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7124 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7129 i.rm.reg = i.op[source].regs->reg_num;
7130 i.rm.regmem = i.op[dest].regs->reg_num;
7131 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7133 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7135 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7137 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7140 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7142 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7145 add_prefix (LOCK_PREFIX_OPCODE);
7149 { /* If it's not 2 reg operands... */
7154 unsigned int fake_zero_displacement = 0;
7157 for (op = 0; op < i.operands; op++)
7158 if (operand_type_check (i.types[op], anymem))
7160 gas_assert (op < i.operands);
7162 if (i.tm.opcode_modifier.vecsib)
7164 if (i.index_reg->reg_num == RegIZ)
7167 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7170 i.sib.base = NO_BASE_REGISTER;
7171 i.sib.scale = i.log2_scale_factor;
7172 i.types[op].bitfield.disp8 = 0;
7173 i.types[op].bitfield.disp16 = 0;
7174 i.types[op].bitfield.disp64 = 0;
7175 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7177 /* Must be 32 bit */
7178 i.types[op].bitfield.disp32 = 1;
7179 i.types[op].bitfield.disp32s = 0;
7183 i.types[op].bitfield.disp32 = 0;
7184 i.types[op].bitfield.disp32s = 1;
7187 i.sib.index = i.index_reg->reg_num;
7188 if ((i.index_reg->reg_flags & RegRex) != 0)
7190 if ((i.index_reg->reg_flags & RegVRex) != 0)
7196 if (i.base_reg == 0)
7199 if (!i.disp_operands)
7200 fake_zero_displacement = 1;
7201 if (i.index_reg == 0)
7203 i386_operand_type newdisp;
7205 gas_assert (!i.tm.opcode_modifier.vecsib);
7206 /* Operand is just <disp> */
7207 if (flag_code == CODE_64BIT)
7209 /* 64bit mode overwrites the 32bit absolute
7210 addressing by RIP relative addressing and
7211 absolute addressing is encoded by one of the
7212 redundant SIB forms. */
7213 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7214 i.sib.base = NO_BASE_REGISTER;
7215 i.sib.index = NO_INDEX_REGISTER;
7216 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7218 else if ((flag_code == CODE_16BIT)
7219 ^ (i.prefix[ADDR_PREFIX] != 0))
7221 i.rm.regmem = NO_BASE_REGISTER_16;
7226 i.rm.regmem = NO_BASE_REGISTER;
7229 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7230 i.types[op] = operand_type_or (i.types[op], newdisp);
7232 else if (!i.tm.opcode_modifier.vecsib)
7234 /* !i.base_reg && i.index_reg */
7235 if (i.index_reg->reg_num == RegIZ)
7236 i.sib.index = NO_INDEX_REGISTER;
7238 i.sib.index = i.index_reg->reg_num;
7239 i.sib.base = NO_BASE_REGISTER;
7240 i.sib.scale = i.log2_scale_factor;
7241 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7242 i.types[op].bitfield.disp8 = 0;
7243 i.types[op].bitfield.disp16 = 0;
7244 i.types[op].bitfield.disp64 = 0;
7245 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7247 /* Must be 32 bit */
7248 i.types[op].bitfield.disp32 = 1;
7249 i.types[op].bitfield.disp32s = 0;
7253 i.types[op].bitfield.disp32 = 0;
7254 i.types[op].bitfield.disp32s = 1;
7256 if ((i.index_reg->reg_flags & RegRex) != 0)
7260 /* RIP addressing for 64bit mode. */
7261 else if (i.base_reg->reg_num == RegIP)
7263 gas_assert (!i.tm.opcode_modifier.vecsib);
7264 i.rm.regmem = NO_BASE_REGISTER;
7265 i.types[op].bitfield.disp8 = 0;
7266 i.types[op].bitfield.disp16 = 0;
7267 i.types[op].bitfield.disp32 = 0;
7268 i.types[op].bitfield.disp32s = 1;
7269 i.types[op].bitfield.disp64 = 0;
7270 i.flags[op] |= Operand_PCrel;
7271 if (! i.disp_operands)
7272 fake_zero_displacement = 1;
7274 else if (i.base_reg->reg_type.bitfield.word)
7276 gas_assert (!i.tm.opcode_modifier.vecsib);
7277 switch (i.base_reg->reg_num)
7280 if (i.index_reg == 0)
7282 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7283 i.rm.regmem = i.index_reg->reg_num - 6;
7287 if (i.index_reg == 0)
7290 if (operand_type_check (i.types[op], disp) == 0)
7292 /* fake (%bp) into 0(%bp) */
7293 i.types[op].bitfield.disp8 = 1;
7294 fake_zero_displacement = 1;
7297 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7298 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7300 default: /* (%si) -> 4 or (%di) -> 5 */
7301 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7303 i.rm.mode = mode_from_disp_size (i.types[op]);
7305 else /* i.base_reg and 32/64 bit mode */
7307 if (flag_code == CODE_64BIT
7308 && operand_type_check (i.types[op], disp))
7310 i.types[op].bitfield.disp16 = 0;
7311 i.types[op].bitfield.disp64 = 0;
7312 if (i.prefix[ADDR_PREFIX] == 0)
7314 i.types[op].bitfield.disp32 = 0;
7315 i.types[op].bitfield.disp32s = 1;
7319 i.types[op].bitfield.disp32 = 1;
7320 i.types[op].bitfield.disp32s = 0;
7324 if (!i.tm.opcode_modifier.vecsib)
7325 i.rm.regmem = i.base_reg->reg_num;
7326 if ((i.base_reg->reg_flags & RegRex) != 0)
7328 i.sib.base = i.base_reg->reg_num;
7329 /* x86-64 ignores REX prefix bit here to avoid decoder
7331 if (!(i.base_reg->reg_flags & RegRex)
7332 && (i.base_reg->reg_num == EBP_REG_NUM
7333 || i.base_reg->reg_num == ESP_REG_NUM))
7335 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7337 fake_zero_displacement = 1;
7338 i.types[op].bitfield.disp8 = 1;
7340 i.sib.scale = i.log2_scale_factor;
7341 if (i.index_reg == 0)
7343 gas_assert (!i.tm.opcode_modifier.vecsib);
7344 /* <disp>(%esp) becomes two byte modrm with no index
7345 register. We've already stored the code for esp
7346 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7347 Any base register besides %esp will not use the
7348 extra modrm byte. */
7349 i.sib.index = NO_INDEX_REGISTER;
7351 else if (!i.tm.opcode_modifier.vecsib)
7353 if (i.index_reg->reg_num == RegIZ)
7354 i.sib.index = NO_INDEX_REGISTER;
7356 i.sib.index = i.index_reg->reg_num;
7357 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7358 if ((i.index_reg->reg_flags & RegRex) != 0)
7363 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7364 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7368 if (!fake_zero_displacement
7372 fake_zero_displacement = 1;
7373 if (i.disp_encoding == disp_encoding_8bit)
7374 i.types[op].bitfield.disp8 = 1;
7376 i.types[op].bitfield.disp32 = 1;
7378 i.rm.mode = mode_from_disp_size (i.types[op]);
7382 if (fake_zero_displacement)
7384 /* Fakes a zero displacement assuming that i.types[op]
7385 holds the correct displacement size. */
7388 gas_assert (i.op[op].disps == 0);
7389 exp = &disp_expressions[i.disp_operands++];
7390 i.op[op].disps = exp;
7391 exp->X_op = O_constant;
7392 exp->X_add_number = 0;
7393 exp->X_add_symbol = (symbolS *) 0;
7394 exp->X_op_symbol = (symbolS *) 0;
7402 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7404 if (operand_type_check (i.types[0], imm))
7405 i.vex.register_specifier = NULL;
7408 /* VEX.vvvv encodes one of the sources when the first
7409 operand is not an immediate. */
7410 if (i.tm.opcode_modifier.vexw == VEXW0)
7411 i.vex.register_specifier = i.op[0].regs;
7413 i.vex.register_specifier = i.op[1].regs;
7416 /* Destination is a XMM register encoded in the ModRM.reg
7418 i.rm.reg = i.op[2].regs->reg_num;
7419 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7422 /* ModRM.rm and VEX.B encodes the other source. */
7423 if (!i.mem_operands)
7427 if (i.tm.opcode_modifier.vexw == VEXW0)
7428 i.rm.regmem = i.op[1].regs->reg_num;
7430 i.rm.regmem = i.op[0].regs->reg_num;
7432 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7436 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7438 i.vex.register_specifier = i.op[2].regs;
7439 if (!i.mem_operands)
7442 i.rm.regmem = i.op[1].regs->reg_num;
7443 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7447 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7448 (if any) based on i.tm.extension_opcode. Again, we must be
7449 careful to make sure that segment/control/debug/test/MMX
7450 registers are coded into the i.rm.reg field. */
7451 else if (i.reg_operands)
7454 unsigned int vex_reg = ~0;
7456 for (op = 0; op < i.operands; op++)
7458 if (i.types[op].bitfield.reg
7459 || i.types[op].bitfield.regbnd
7460 || i.types[op].bitfield.regmask
7461 || i.types[op].bitfield.sreg2
7462 || i.types[op].bitfield.sreg3
7463 || i.types[op].bitfield.control
7464 || i.types[op].bitfield.debug
7465 || i.types[op].bitfield.test)
7467 if (i.types[op].bitfield.regsimd)
7469 if (i.types[op].bitfield.zmmword)
7470 i.has_regzmm = TRUE;
7471 else if (i.types[op].bitfield.ymmword)
7472 i.has_regymm = TRUE;
7474 i.has_regxmm = TRUE;
7477 if (i.types[op].bitfield.regmmx)
7479 i.has_regmmx = TRUE;
7486 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7488 /* For instructions with VexNDS, the register-only
7489 source operand is encoded in VEX prefix. */
7490 gas_assert (mem != (unsigned int) ~0);
7495 gas_assert (op < i.operands);
7499 /* Check register-only source operand when two source
7500 operands are swapped. */
7501 if (!i.tm.operand_types[op].bitfield.baseindex
7502 && i.tm.operand_types[op + 1].bitfield.baseindex)
7506 gas_assert (mem == (vex_reg + 1)
7507 && op < i.operands);
7512 gas_assert (vex_reg < i.operands);
7516 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7518 /* For instructions with VexNDD, the register destination
7519 is encoded in VEX prefix. */
7520 if (i.mem_operands == 0)
7522 /* There is no memory operand. */
7523 gas_assert ((op + 2) == i.operands);
7528 /* There are only 2 non-immediate operands. */
7529 gas_assert (op < i.imm_operands + 2
7530 && i.operands == i.imm_operands + 2);
7531 vex_reg = i.imm_operands + 1;
7535 gas_assert (op < i.operands);
7537 if (vex_reg != (unsigned int) ~0)
7539 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7541 if ((!type->bitfield.reg
7542 || (!type->bitfield.dword && !type->bitfield.qword))
7543 && !type->bitfield.regsimd
7544 && !operand_type_equal (type, ®mask))
7547 i.vex.register_specifier = i.op[vex_reg].regs;
7550 /* Don't set OP operand twice. */
7553 /* If there is an extension opcode to put here, the
7554 register number must be put into the regmem field. */
7555 if (i.tm.extension_opcode != None)
7557 i.rm.regmem = i.op[op].regs->reg_num;
7558 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7560 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7565 i.rm.reg = i.op[op].regs->reg_num;
7566 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7568 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7573 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7574 must set it to 3 to indicate this is a register operand
7575 in the regmem field. */
7576 if (!i.mem_operands)
7580 /* Fill in i.rm.reg field with extension opcode (if any). */
7581 if (i.tm.extension_opcode != None)
7582 i.rm.reg = i.tm.extension_opcode;
7588 output_branch (void)
7594 relax_substateT subtype;
7598 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7599 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7602 if (i.prefix[DATA_PREFIX] != 0)
7608 /* Pentium4 branch hints. */
7609 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7610 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7615 if (i.prefix[REX_PREFIX] != 0)
7621 /* BND prefixed jump. */
7622 if (i.prefix[BND_PREFIX] != 0)
7624 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7628 if (i.prefixes != 0 && !intel_syntax)
7629 as_warn (_("skipping prefixes on this instruction"));
7631 /* It's always a symbol; End frag & setup for relax.
7632 Make sure there is enough room in this frag for the largest
7633 instruction we may generate in md_convert_frag. This is 2
7634 bytes for the opcode and room for the prefix and largest
7636 frag_grow (prefix + 2 + 4);
7637 /* Prefix and 1 opcode byte go in fr_fix. */
7638 p = frag_more (prefix + 1);
7639 if (i.prefix[DATA_PREFIX] != 0)
7640 *p++ = DATA_PREFIX_OPCODE;
7641 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7642 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7643 *p++ = i.prefix[SEG_PREFIX];
7644 if (i.prefix[REX_PREFIX] != 0)
7645 *p++ = i.prefix[REX_PREFIX];
7646 *p = i.tm.base_opcode;
7648 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7649 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7650 else if (cpu_arch_flags.bitfield.cpui386)
7651 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7653 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7656 sym = i.op[0].disps->X_add_symbol;
7657 off = i.op[0].disps->X_add_number;
7659 if (i.op[0].disps->X_op != O_constant
7660 && i.op[0].disps->X_op != O_symbol)
7662 /* Handle complex expressions. */
7663 sym = make_expr_symbol (i.op[0].disps);
7667 /* 1 possible extra opcode + 4 byte displacement go in var part.
7668 Pass reloc in fr_var. */
7669 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7673 /* Return TRUE iff PLT32 relocation should be used for branching to
7677 need_plt32_p (symbolS *s)
7679 /* PLT32 relocation is ELF only. */
7683 /* Since there is no need to prepare for PLT branch on x86-64, we
7684 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7685 be used as a marker for 32-bit PC-relative branches. */
7689 /* Weak or undefined symbol need PLT32 relocation. */
7690 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7693 /* Non-global symbol doesn't need PLT32 relocation. */
7694 if (! S_IS_EXTERNAL (s))
7697 /* Other global symbols need PLT32 relocation. NB: Symbol with
7698 non-default visibilities are treated as normal global symbol
7699 so that PLT32 relocation can be used as a marker for 32-bit
7700 PC-relative branches. It is useful for linker relaxation. */
7711 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7713 if (i.tm.opcode_modifier.jumpbyte)
7715 /* This is a loop or jecxz type instruction. */
7717 if (i.prefix[ADDR_PREFIX] != 0)
7719 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7722 /* Pentium4 branch hints. */
7723 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7724 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7726 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7735 if (flag_code == CODE_16BIT)
7738 if (i.prefix[DATA_PREFIX] != 0)
7740 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7750 if (i.prefix[REX_PREFIX] != 0)
7752 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7756 /* BND prefixed jump. */
7757 if (i.prefix[BND_PREFIX] != 0)
7759 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7763 if (i.prefixes != 0 && !intel_syntax)
7764 as_warn (_("skipping prefixes on this instruction"));
7766 p = frag_more (i.tm.opcode_length + size);
7767 switch (i.tm.opcode_length)
7770 *p++ = i.tm.base_opcode >> 8;
7773 *p++ = i.tm.base_opcode;
7779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7781 && jump_reloc == NO_RELOC
7782 && need_plt32_p (i.op[0].disps->X_add_symbol))
7783 jump_reloc = BFD_RELOC_X86_64_PLT32;
7786 jump_reloc = reloc (size, 1, 1, jump_reloc);
7788 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7789 i.op[0].disps, 1, jump_reloc);
7791 /* All jumps handled here are signed, but don't use a signed limit
7792 check for 32 and 16 bit jumps as we want to allow wrap around at
7793 4G and 64k respectively. */
7795 fixP->fx_signed = 1;
7799 output_interseg_jump (void)
7807 if (flag_code == CODE_16BIT)
7811 if (i.prefix[DATA_PREFIX] != 0)
7817 if (i.prefix[REX_PREFIX] != 0)
7827 if (i.prefixes != 0 && !intel_syntax)
7828 as_warn (_("skipping prefixes on this instruction"));
7830 /* 1 opcode; 2 segment; offset */
7831 p = frag_more (prefix + 1 + 2 + size);
7833 if (i.prefix[DATA_PREFIX] != 0)
7834 *p++ = DATA_PREFIX_OPCODE;
7836 if (i.prefix[REX_PREFIX] != 0)
7837 *p++ = i.prefix[REX_PREFIX];
7839 *p++ = i.tm.base_opcode;
7840 if (i.op[1].imms->X_op == O_constant)
7842 offsetT n = i.op[1].imms->X_add_number;
7845 && !fits_in_unsigned_word (n)
7846 && !fits_in_signed_word (n))
7848 as_bad (_("16-bit jump out of range"));
7851 md_number_to_chars (p, n, size);
7854 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7855 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7856 if (i.op[0].imms->X_op != O_constant)
7857 as_bad (_("can't handle non absolute segment in `%s'"),
7859 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7862 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7867 asection *seg = now_seg;
7868 subsegT subseg = now_subseg;
7870 unsigned int alignment, align_size_1;
7871 unsigned int isa_1_descsz, feature_2_descsz, descsz;
7872 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
7873 unsigned int padding;
7875 if (!IS_ELF || !x86_used_note)
7878 x86_isa_1_used |= GNU_PROPERTY_X86_UINT32_VALID;
7879 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
7881 /* The .note.gnu.property section layout:
7883 Field Length Contents
7886 n_descsz 4 The note descriptor size
7887 n_type 4 NT_GNU_PROPERTY_TYPE_0
7889 n_desc n_descsz The program property array
7893 /* Create the .note.gnu.property section. */
7894 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
7895 bfd_set_section_flags (stdoutput, sec,
7902 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
7913 bfd_set_section_alignment (stdoutput, sec, alignment);
7914 elf_section_type (sec) = SHT_NOTE;
7916 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7918 isa_1_descsz_raw = 4 + 4 + 4;
7919 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7920 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
7922 feature_2_descsz_raw = isa_1_descsz;
7923 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7925 feature_2_descsz_raw += 4 + 4 + 4;
7926 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7927 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
7930 descsz = feature_2_descsz;
7931 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7932 p = frag_more (4 + 4 + 4 + 4 + descsz);
7934 /* Write n_namsz. */
7935 md_number_to_chars (p, (valueT) 4, 4);
7937 /* Write n_descsz. */
7938 md_number_to_chars (p + 4, (valueT) descsz, 4);
7941 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
7944 memcpy (p + 4 * 3, "GNU", 4);
7946 /* Write 4-byte type. */
7947 md_number_to_chars (p + 4 * 4,
7948 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
7950 /* Write 4-byte data size. */
7951 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
7953 /* Write 4-byte data. */
7954 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
7956 /* Zero out paddings. */
7957 padding = isa_1_descsz - isa_1_descsz_raw;
7959 memset (p + 4 * 7, 0, padding);
7961 /* Write 4-byte type. */
7962 md_number_to_chars (p + isa_1_descsz + 4 * 4,
7963 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
7965 /* Write 4-byte data size. */
7966 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
7968 /* Write 4-byte data. */
7969 md_number_to_chars (p + isa_1_descsz + 4 * 6,
7970 (valueT) x86_feature_2_used, 4);
7972 /* Zero out paddings. */
7973 padding = feature_2_descsz - feature_2_descsz_raw;
7975 memset (p + isa_1_descsz + 4 * 7, 0, padding);
7977 /* We probably can't restore the current segment, for there likely
7980 subseg_set (seg, subseg);
7987 fragS *insn_start_frag;
7988 offsetT insn_start_off;
7990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7991 if (IS_ELF && x86_used_note)
7993 if (i.tm.cpu_flags.bitfield.cpucmov)
7994 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
7995 if (i.tm.cpu_flags.bitfield.cpusse)
7996 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
7997 if (i.tm.cpu_flags.bitfield.cpusse2)
7998 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
7999 if (i.tm.cpu_flags.bitfield.cpusse3)
8000 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8001 if (i.tm.cpu_flags.bitfield.cpussse3)
8002 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8003 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8004 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8005 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8006 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8007 if (i.tm.cpu_flags.bitfield.cpuavx)
8008 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8009 if (i.tm.cpu_flags.bitfield.cpuavx2)
8010 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8011 if (i.tm.cpu_flags.bitfield.cpufma)
8012 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8013 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8014 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8015 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8016 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8017 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8018 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8019 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8020 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8021 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8022 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8023 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8024 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8025 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8026 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8027 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8028 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8029 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8030 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8031 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8032 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8033 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8034 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8035 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8036 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8037 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8038 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8039 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8040 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
8042 if (i.tm.cpu_flags.bitfield.cpu8087
8043 || i.tm.cpu_flags.bitfield.cpu287
8044 || i.tm.cpu_flags.bitfield.cpu387
8045 || i.tm.cpu_flags.bitfield.cpu687
8046 || i.tm.cpu_flags.bitfield.cpufisttp)
8047 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8048 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8049 Xfence instructions. */
8050 if (i.tm.base_opcode != 0xf18
8051 && i.tm.base_opcode != 0xf0d
8052 && i.tm.base_opcode != 0xfae
8054 || i.tm.cpu_flags.bitfield.cpummx
8055 || i.tm.cpu_flags.bitfield.cpua3dnow
8056 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8057 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8059 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8061 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8063 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8064 if (i.tm.cpu_flags.bitfield.cpufxsr)
8065 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8066 if (i.tm.cpu_flags.bitfield.cpuxsave)
8067 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8068 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8069 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8070 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8071 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8075 /* Tie dwarf2 debug info to the address at the start of the insn.
8076 We can't do this after the insn has been output as the current
8077 frag may have been closed off. eg. by frag_var. */
8078 dwarf2_emit_insn (0);
8080 insn_start_frag = frag_now;
8081 insn_start_off = frag_now_fix ();
8084 if (i.tm.opcode_modifier.jump)
8086 else if (i.tm.opcode_modifier.jumpbyte
8087 || i.tm.opcode_modifier.jumpdword)
8089 else if (i.tm.opcode_modifier.jumpintersegment)
8090 output_interseg_jump ();
8093 /* Output normal instructions here. */
8097 unsigned int prefix;
8100 && i.tm.base_opcode == 0xfae
8102 && i.imm_operands == 1
8103 && (i.op[0].imms->X_add_number == 0xe8
8104 || i.op[0].imms->X_add_number == 0xf0
8105 || i.op[0].imms->X_add_number == 0xf8))
8107 /* Encode lfence, mfence, and sfence as
8108 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8109 offsetT val = 0x240483f0ULL;
8111 md_number_to_chars (p, val, 5);
8115 /* Some processors fail on LOCK prefix. This options makes
8116 assembler ignore LOCK prefix and serves as a workaround. */
8117 if (omit_lock_prefix)
8119 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8121 i.prefix[LOCK_PREFIX] = 0;
8124 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8125 don't need the explicit prefix. */
8126 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
8128 switch (i.tm.opcode_length)
8131 if (i.tm.base_opcode & 0xff000000)
8133 prefix = (i.tm.base_opcode >> 24) & 0xff;
8134 add_prefix (prefix);
8138 if ((i.tm.base_opcode & 0xff0000) != 0)
8140 prefix = (i.tm.base_opcode >> 16) & 0xff;
8141 if (!i.tm.cpu_flags.bitfield.cpupadlock
8142 || prefix != REPE_PREFIX_OPCODE
8143 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
8144 add_prefix (prefix);
8150 /* Check for pseudo prefixes. */
8151 as_bad_where (insn_start_frag->fr_file,
8152 insn_start_frag->fr_line,
8153 _("pseudo prefix without instruction"));
8159 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8160 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8161 R_X86_64_GOTTPOFF relocation so that linker can safely
8162 perform IE->LE optimization. */
8163 if (x86_elf_abi == X86_64_X32_ABI
8165 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8166 && i.prefix[REX_PREFIX] == 0)
8167 add_prefix (REX_OPCODE);
8170 /* The prefix bytes. */
8171 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8173 FRAG_APPEND_1_CHAR (*q);
8177 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8182 /* REX byte is encoded in VEX prefix. */
8186 FRAG_APPEND_1_CHAR (*q);
8189 /* There should be no other prefixes for instructions
8194 /* For EVEX instructions i.vrex should become 0 after
8195 build_evex_prefix. For VEX instructions upper 16 registers
8196 aren't available, so VREX should be 0. */
8199 /* Now the VEX prefix. */
8200 p = frag_more (i.vex.length);
8201 for (j = 0; j < i.vex.length; j++)
8202 p[j] = i.vex.bytes[j];
8205 /* Now the opcode; be careful about word order here! */
8206 if (i.tm.opcode_length == 1)
8208 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8212 switch (i.tm.opcode_length)
8216 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8217 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8221 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8231 /* Put out high byte first: can't use md_number_to_chars! */
8232 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8233 *p = i.tm.base_opcode & 0xff;
8236 /* Now the modrm byte and sib byte (if present). */
8237 if (i.tm.opcode_modifier.modrm)
8239 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8242 /* If i.rm.regmem == ESP (4)
8243 && i.rm.mode != (Register mode)
8245 ==> need second modrm byte. */
8246 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8248 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
8249 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8251 | i.sib.scale << 6));
8254 if (i.disp_operands)
8255 output_disp (insn_start_frag, insn_start_off);
8258 output_imm (insn_start_frag, insn_start_off);
8264 pi ("" /*line*/, &i);
8266 #endif /* DEBUG386 */
8269 /* Return the size of the displacement operand N. */
8272 disp_size (unsigned int n)
8276 if (i.types[n].bitfield.disp64)
8278 else if (i.types[n].bitfield.disp8)
8280 else if (i.types[n].bitfield.disp16)
8285 /* Return the size of the immediate operand N. */
8288 imm_size (unsigned int n)
8291 if (i.types[n].bitfield.imm64)
8293 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8295 else if (i.types[n].bitfield.imm16)
8301 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
8306 for (n = 0; n < i.operands; n++)
8308 if (operand_type_check (i.types[n], disp))
8310 if (i.op[n].disps->X_op == O_constant)
8312 int size = disp_size (n);
8313 offsetT val = i.op[n].disps->X_add_number;
8315 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8317 p = frag_more (size);
8318 md_number_to_chars (p, val, size);
8322 enum bfd_reloc_code_real reloc_type;
8323 int size = disp_size (n);
8324 int sign = i.types[n].bitfield.disp32s;
8325 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8328 /* We can't have 8 bit displacement here. */
8329 gas_assert (!i.types[n].bitfield.disp8);
8331 /* The PC relative address is computed relative
8332 to the instruction boundary, so in case immediate
8333 fields follows, we need to adjust the value. */
8334 if (pcrel && i.imm_operands)
8339 for (n1 = 0; n1 < i.operands; n1++)
8340 if (operand_type_check (i.types[n1], imm))
8342 /* Only one immediate is allowed for PC
8343 relative address. */
8344 gas_assert (sz == 0);
8346 i.op[n].disps->X_add_number -= sz;
8348 /* We should find the immediate. */
8349 gas_assert (sz != 0);
8352 p = frag_more (size);
8353 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8355 && GOT_symbol == i.op[n].disps->X_add_symbol
8356 && (((reloc_type == BFD_RELOC_32
8357 || reloc_type == BFD_RELOC_X86_64_32S
8358 || (reloc_type == BFD_RELOC_64
8360 && (i.op[n].disps->X_op == O_symbol
8361 || (i.op[n].disps->X_op == O_add
8362 && ((symbol_get_value_expression
8363 (i.op[n].disps->X_op_symbol)->X_op)
8365 || reloc_type == BFD_RELOC_32_PCREL))
8369 if (insn_start_frag == frag_now)
8370 add = (p - frag_now->fr_literal) - insn_start_off;
8375 add = insn_start_frag->fr_fix - insn_start_off;
8376 for (fr = insn_start_frag->fr_next;
8377 fr && fr != frag_now; fr = fr->fr_next)
8379 add += p - frag_now->fr_literal;
8384 reloc_type = BFD_RELOC_386_GOTPC;
8385 i.op[n].imms->X_add_number += add;
8387 else if (reloc_type == BFD_RELOC_64)
8388 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8390 /* Don't do the adjustment for x86-64, as there
8391 the pcrel addressing is relative to the _next_
8392 insn, and that is taken care of in other code. */
8393 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8395 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8396 size, i.op[n].disps, pcrel,
8398 /* Check for "call/jmp *mem", "mov mem, %reg",
8399 "test %reg, mem" and "binop mem, %reg" where binop
8400 is one of adc, add, and, cmp, or, sbb, sub, xor
8401 instructions. Always generate R_386_GOT32X for
8402 "sym*GOT" operand in 32-bit mode. */
8403 if ((generate_relax_relocations
8406 && i.rm.regmem == 5))
8408 || (i.rm.mode == 0 && i.rm.regmem == 5))
8409 && ((i.operands == 1
8410 && i.tm.base_opcode == 0xff
8411 && (i.rm.reg == 2 || i.rm.reg == 4))
8413 && (i.tm.base_opcode == 0x8b
8414 || i.tm.base_opcode == 0x85
8415 || (i.tm.base_opcode & 0xc7) == 0x03))))
8419 fixP->fx_tcbit = i.rex != 0;
8421 && (i.base_reg->reg_num == RegIP))
8422 fixP->fx_tcbit2 = 1;
8425 fixP->fx_tcbit2 = 1;
8433 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8438 for (n = 0; n < i.operands; n++)
8440 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8441 if (i.rounding && (int) n == i.rounding->operand)
8444 if (operand_type_check (i.types[n], imm))
8446 if (i.op[n].imms->X_op == O_constant)
8448 int size = imm_size (n);
8451 val = offset_in_range (i.op[n].imms->X_add_number,
8453 p = frag_more (size);
8454 md_number_to_chars (p, val, size);
8458 /* Not absolute_section.
8459 Need a 32-bit fixup (don't support 8bit
8460 non-absolute imms). Try to support other
8462 enum bfd_reloc_code_real reloc_type;
8463 int size = imm_size (n);
8466 if (i.types[n].bitfield.imm32s
8467 && (i.suffix == QWORD_MNEM_SUFFIX
8468 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8473 p = frag_more (size);
8474 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8476 /* This is tough to explain. We end up with this one if we
8477 * have operands that look like
8478 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8479 * obtain the absolute address of the GOT, and it is strongly
8480 * preferable from a performance point of view to avoid using
8481 * a runtime relocation for this. The actual sequence of
8482 * instructions often look something like:
8487 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8489 * The call and pop essentially return the absolute address
8490 * of the label .L66 and store it in %ebx. The linker itself
8491 * will ultimately change the first operand of the addl so
8492 * that %ebx points to the GOT, but to keep things simple, the
8493 * .o file must have this operand set so that it generates not
8494 * the absolute address of .L66, but the absolute address of
8495 * itself. This allows the linker itself simply treat a GOTPC
8496 * relocation as asking for a pcrel offset to the GOT to be
8497 * added in, and the addend of the relocation is stored in the
8498 * operand field for the instruction itself.
8500 * Our job here is to fix the operand so that it would add
8501 * the correct offset so that %ebx would point to itself. The
8502 * thing that is tricky is that .-.L66 will point to the
8503 * beginning of the instruction, so we need to further modify
8504 * the operand so that it will point to itself. There are
8505 * other cases where you have something like:
8507 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8509 * and here no correction would be required. Internally in
8510 * the assembler we treat operands of this form as not being
8511 * pcrel since the '.' is explicitly mentioned, and I wonder
8512 * whether it would simplify matters to do it this way. Who
8513 * knows. In earlier versions of the PIC patches, the
8514 * pcrel_adjust field was used to store the correction, but
8515 * since the expression is not pcrel, I felt it would be
8516 * confusing to do it this way. */
8518 if ((reloc_type == BFD_RELOC_32
8519 || reloc_type == BFD_RELOC_X86_64_32S
8520 || reloc_type == BFD_RELOC_64)
8522 && GOT_symbol == i.op[n].imms->X_add_symbol
8523 && (i.op[n].imms->X_op == O_symbol
8524 || (i.op[n].imms->X_op == O_add
8525 && ((symbol_get_value_expression
8526 (i.op[n].imms->X_op_symbol)->X_op)
8531 if (insn_start_frag == frag_now)
8532 add = (p - frag_now->fr_literal) - insn_start_off;
8537 add = insn_start_frag->fr_fix - insn_start_off;
8538 for (fr = insn_start_frag->fr_next;
8539 fr && fr != frag_now; fr = fr->fr_next)
8541 add += p - frag_now->fr_literal;
8545 reloc_type = BFD_RELOC_386_GOTPC;
8547 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8549 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8550 i.op[n].imms->X_add_number += add;
8552 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8553 i.op[n].imms, 0, reloc_type);
8559 /* x86_cons_fix_new is called via the expression parsing code when a
8560 reloc is needed. We use this hook to get the correct .got reloc. */
8561 static int cons_sign = -1;
8564 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8565 expressionS *exp, bfd_reloc_code_real_type r)
8567 r = reloc (len, 0, cons_sign, r);
8570 if (exp->X_op == O_secrel)
8572 exp->X_op = O_symbol;
8573 r = BFD_RELOC_32_SECREL;
8577 fix_new_exp (frag, off, len, exp, 0, r);
8580 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8581 purpose of the `.dc.a' internal pseudo-op. */
8584 x86_address_bytes (void)
8586 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8588 return stdoutput->arch_info->bits_per_address / 8;
8591 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8593 # define lex_got(reloc, adjust, types) NULL
8595 /* Parse operands of the form
8596 <symbol>@GOTOFF+<nnn>
8597 and similar .plt or .got references.
8599 If we find one, set up the correct relocation in RELOC and copy the
8600 input string, minus the `@GOTOFF' into a malloc'd buffer for
8601 parsing by the calling routine. Return this buffer, and if ADJUST
8602 is non-null set it to the length of the string we removed from the
8603 input line. Otherwise return NULL. */
8605 lex_got (enum bfd_reloc_code_real *rel,
8607 i386_operand_type *types)
8609 /* Some of the relocations depend on the size of what field is to
8610 be relocated. But in our callers i386_immediate and i386_displacement
8611 we don't yet know the operand size (this will be set by insn
8612 matching). Hence we record the word32 relocation here,
8613 and adjust the reloc according to the real size in reloc(). */
8614 static const struct {
8617 const enum bfd_reloc_code_real rel[2];
8618 const i386_operand_type types64;
8620 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8621 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8623 OPERAND_TYPE_IMM32_64 },
8625 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8626 BFD_RELOC_X86_64_PLTOFF64 },
8627 OPERAND_TYPE_IMM64 },
8628 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8629 BFD_RELOC_X86_64_PLT32 },
8630 OPERAND_TYPE_IMM32_32S_DISP32 },
8631 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8632 BFD_RELOC_X86_64_GOTPLT64 },
8633 OPERAND_TYPE_IMM64_DISP64 },
8634 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8635 BFD_RELOC_X86_64_GOTOFF64 },
8636 OPERAND_TYPE_IMM64_DISP64 },
8637 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8638 BFD_RELOC_X86_64_GOTPCREL },
8639 OPERAND_TYPE_IMM32_32S_DISP32 },
8640 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8641 BFD_RELOC_X86_64_TLSGD },
8642 OPERAND_TYPE_IMM32_32S_DISP32 },
8643 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8644 _dummy_first_bfd_reloc_code_real },
8645 OPERAND_TYPE_NONE },
8646 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8647 BFD_RELOC_X86_64_TLSLD },
8648 OPERAND_TYPE_IMM32_32S_DISP32 },
8649 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8650 BFD_RELOC_X86_64_GOTTPOFF },
8651 OPERAND_TYPE_IMM32_32S_DISP32 },
8652 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8653 BFD_RELOC_X86_64_TPOFF32 },
8654 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8655 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8656 _dummy_first_bfd_reloc_code_real },
8657 OPERAND_TYPE_NONE },
8658 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8659 BFD_RELOC_X86_64_DTPOFF32 },
8660 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8661 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8662 _dummy_first_bfd_reloc_code_real },
8663 OPERAND_TYPE_NONE },
8664 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8665 _dummy_first_bfd_reloc_code_real },
8666 OPERAND_TYPE_NONE },
8667 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8668 BFD_RELOC_X86_64_GOT32 },
8669 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8670 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8671 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8672 OPERAND_TYPE_IMM32_32S_DISP32 },
8673 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8674 BFD_RELOC_X86_64_TLSDESC_CALL },
8675 OPERAND_TYPE_IMM32_32S_DISP32 },
8680 #if defined (OBJ_MAYBE_ELF)
8685 for (cp = input_line_pointer; *cp != '@'; cp++)
8686 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8689 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8691 int len = gotrel[j].len;
8692 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8694 if (gotrel[j].rel[object_64bit] != 0)
8697 char *tmpbuf, *past_reloc;
8699 *rel = gotrel[j].rel[object_64bit];
8703 if (flag_code != CODE_64BIT)
8705 types->bitfield.imm32 = 1;
8706 types->bitfield.disp32 = 1;
8709 *types = gotrel[j].types64;
8712 if (j != 0 && GOT_symbol == NULL)
8713 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8715 /* The length of the first part of our input line. */
8716 first = cp - input_line_pointer;
8718 /* The second part goes from after the reloc token until
8719 (and including) an end_of_line char or comma. */
8720 past_reloc = cp + 1 + len;
8722 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8724 second = cp + 1 - past_reloc;
8726 /* Allocate and copy string. The trailing NUL shouldn't
8727 be necessary, but be safe. */
8728 tmpbuf = XNEWVEC (char, first + second + 2);
8729 memcpy (tmpbuf, input_line_pointer, first);
8730 if (second != 0 && *past_reloc != ' ')
8731 /* Replace the relocation token with ' ', so that
8732 errors like foo@GOTOFF1 will be detected. */
8733 tmpbuf[first++] = ' ';
8735 /* Increment length by 1 if the relocation token is
8740 memcpy (tmpbuf + first, past_reloc, second);
8741 tmpbuf[first + second] = '\0';
8745 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8746 gotrel[j].str, 1 << (5 + object_64bit));
8751 /* Might be a symbol version string. Don't as_bad here. */
8760 /* Parse operands of the form
8761 <symbol>@SECREL32+<nnn>
8763 If we find one, set up the correct relocation in RELOC and copy the
8764 input string, minus the `@SECREL32' into a malloc'd buffer for
8765 parsing by the calling routine. Return this buffer, and if ADJUST
8766 is non-null set it to the length of the string we removed from the
8767 input line. Otherwise return NULL.
8769 This function is copied from the ELF version above adjusted for PE targets. */
8772 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8773 int *adjust ATTRIBUTE_UNUSED,
8774 i386_operand_type *types)
8780 const enum bfd_reloc_code_real rel[2];
8781 const i386_operand_type types64;
8785 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8786 BFD_RELOC_32_SECREL },
8787 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8793 for (cp = input_line_pointer; *cp != '@'; cp++)
8794 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8797 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8799 int len = gotrel[j].len;
8801 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8803 if (gotrel[j].rel[object_64bit] != 0)
8806 char *tmpbuf, *past_reloc;
8808 *rel = gotrel[j].rel[object_64bit];
8814 if (flag_code != CODE_64BIT)
8816 types->bitfield.imm32 = 1;
8817 types->bitfield.disp32 = 1;
8820 *types = gotrel[j].types64;
8823 /* The length of the first part of our input line. */
8824 first = cp - input_line_pointer;
8826 /* The second part goes from after the reloc token until
8827 (and including) an end_of_line char or comma. */
8828 past_reloc = cp + 1 + len;
8830 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8832 second = cp + 1 - past_reloc;
8834 /* Allocate and copy string. The trailing NUL shouldn't
8835 be necessary, but be safe. */
8836 tmpbuf = XNEWVEC (char, first + second + 2);
8837 memcpy (tmpbuf, input_line_pointer, first);
8838 if (second != 0 && *past_reloc != ' ')
8839 /* Replace the relocation token with ' ', so that
8840 errors like foo@SECLREL321 will be detected. */
8841 tmpbuf[first++] = ' ';
8842 memcpy (tmpbuf + first, past_reloc, second);
8843 tmpbuf[first + second] = '\0';
8847 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8848 gotrel[j].str, 1 << (5 + object_64bit));
8853 /* Might be a symbol version string. Don't as_bad here. */
8859 bfd_reloc_code_real_type
8860 x86_cons (expressionS *exp, int size)
8862 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8864 intel_syntax = -intel_syntax;
8867 if (size == 4 || (object_64bit && size == 8))
8869 /* Handle @GOTOFF and the like in an expression. */
8871 char *gotfree_input_line;
8874 save = input_line_pointer;
8875 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8876 if (gotfree_input_line)
8877 input_line_pointer = gotfree_input_line;
8881 if (gotfree_input_line)
8883 /* expression () has merrily parsed up to the end of line,
8884 or a comma - in the wrong buffer. Transfer how far
8885 input_line_pointer has moved to the right buffer. */
8886 input_line_pointer = (save
8887 + (input_line_pointer - gotfree_input_line)
8889 free (gotfree_input_line);
8890 if (exp->X_op == O_constant
8891 || exp->X_op == O_absent
8892 || exp->X_op == O_illegal
8893 || exp->X_op == O_register
8894 || exp->X_op == O_big)
8896 char c = *input_line_pointer;
8897 *input_line_pointer = 0;
8898 as_bad (_("missing or invalid expression `%s'"), save);
8899 *input_line_pointer = c;
8906 intel_syntax = -intel_syntax;
8909 i386_intel_simplify (exp);
8915 signed_cons (int size)
8917 if (flag_code == CODE_64BIT)
8925 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8932 if (exp.X_op == O_symbol)
8933 exp.X_op = O_secrel;
8935 emit_expr (&exp, 4);
8937 while (*input_line_pointer++ == ',');
8939 input_line_pointer--;
8940 demand_empty_rest_of_line ();
8944 /* Handle Vector operations. */
8947 check_VecOperations (char *op_string, char *op_end)
8949 const reg_entry *mask;
8954 && (op_end == NULL || op_string < op_end))
8957 if (*op_string == '{')
8961 /* Check broadcasts. */
8962 if (strncmp (op_string, "1to", 3) == 0)
8967 goto duplicated_vec_op;
8970 if (*op_string == '8')
8972 else if (*op_string == '4')
8974 else if (*op_string == '2')
8976 else if (*op_string == '1'
8977 && *(op_string+1) == '6')
8984 as_bad (_("Unsupported broadcast: `%s'"), saved);
8989 broadcast_op.type = bcst_type;
8990 broadcast_op.operand = this_operand;
8991 broadcast_op.bytes = 0;
8992 i.broadcast = &broadcast_op;
8994 /* Check masking operation. */
8995 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8997 /* k0 can't be used for write mask. */
8998 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
9000 as_bad (_("`%s%s' can't be used for write mask"),
9001 register_prefix, mask->reg_name);
9007 mask_op.mask = mask;
9008 mask_op.zeroing = 0;
9009 mask_op.operand = this_operand;
9015 goto duplicated_vec_op;
9017 i.mask->mask = mask;
9019 /* Only "{z}" is allowed here. No need to check
9020 zeroing mask explicitly. */
9021 if (i.mask->operand != this_operand)
9023 as_bad (_("invalid write mask `%s'"), saved);
9030 /* Check zeroing-flag for masking operation. */
9031 else if (*op_string == 'z')
9035 mask_op.mask = NULL;
9036 mask_op.zeroing = 1;
9037 mask_op.operand = this_operand;
9042 if (i.mask->zeroing)
9045 as_bad (_("duplicated `%s'"), saved);
9049 i.mask->zeroing = 1;
9051 /* Only "{%k}" is allowed here. No need to check mask
9052 register explicitly. */
9053 if (i.mask->operand != this_operand)
9055 as_bad (_("invalid zeroing-masking `%s'"),
9064 goto unknown_vec_op;
9066 if (*op_string != '}')
9068 as_bad (_("missing `}' in `%s'"), saved);
9073 /* Strip whitespace since the addition of pseudo prefixes
9074 changed how the scrubber treats '{'. */
9075 if (is_space_char (*op_string))
9081 /* We don't know this one. */
9082 as_bad (_("unknown vector operation: `%s'"), saved);
9086 if (i.mask && i.mask->zeroing && !i.mask->mask)
9088 as_bad (_("zeroing-masking only allowed with write mask"));
9096 i386_immediate (char *imm_start)
9098 char *save_input_line_pointer;
9099 char *gotfree_input_line;
9102 i386_operand_type types;
9104 operand_type_set (&types, ~0);
9106 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9108 as_bad (_("at most %d immediate operands are allowed"),
9109 MAX_IMMEDIATE_OPERANDS);
9113 exp = &im_expressions[i.imm_operands++];
9114 i.op[this_operand].imms = exp;
9116 if (is_space_char (*imm_start))
9119 save_input_line_pointer = input_line_pointer;
9120 input_line_pointer = imm_start;
9122 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9123 if (gotfree_input_line)
9124 input_line_pointer = gotfree_input_line;
9126 exp_seg = expression (exp);
9130 /* Handle vector operations. */
9131 if (*input_line_pointer == '{')
9133 input_line_pointer = check_VecOperations (input_line_pointer,
9135 if (input_line_pointer == NULL)
9139 if (*input_line_pointer)
9140 as_bad (_("junk `%s' after expression"), input_line_pointer);
9142 input_line_pointer = save_input_line_pointer;
9143 if (gotfree_input_line)
9145 free (gotfree_input_line);
9147 if (exp->X_op == O_constant || exp->X_op == O_register)
9148 exp->X_op = O_illegal;
9151 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9155 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9156 i386_operand_type types, const char *imm_start)
9158 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
9161 as_bad (_("missing or invalid immediate expression `%s'"),
9165 else if (exp->X_op == O_constant)
9167 /* Size it properly later. */
9168 i.types[this_operand].bitfield.imm64 = 1;
9169 /* If not 64bit, sign extend val. */
9170 if (flag_code != CODE_64BIT
9171 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9173 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
9175 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9176 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
9177 && exp_seg != absolute_section
9178 && exp_seg != text_section
9179 && exp_seg != data_section
9180 && exp_seg != bss_section
9181 && exp_seg != undefined_section
9182 && !bfd_is_com_section (exp_seg))
9184 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9188 else if (!intel_syntax && exp_seg == reg_section)
9191 as_bad (_("illegal immediate register operand %s"), imm_start);
9196 /* This is an address. The size of the address will be
9197 determined later, depending on destination register,
9198 suffix, or the default for the section. */
9199 i.types[this_operand].bitfield.imm8 = 1;
9200 i.types[this_operand].bitfield.imm16 = 1;
9201 i.types[this_operand].bitfield.imm32 = 1;
9202 i.types[this_operand].bitfield.imm32s = 1;
9203 i.types[this_operand].bitfield.imm64 = 1;
9204 i.types[this_operand] = operand_type_and (i.types[this_operand],
9212 i386_scale (char *scale)
9215 char *save = input_line_pointer;
9217 input_line_pointer = scale;
9218 val = get_absolute_expression ();
9223 i.log2_scale_factor = 0;
9226 i.log2_scale_factor = 1;
9229 i.log2_scale_factor = 2;
9232 i.log2_scale_factor = 3;
9236 char sep = *input_line_pointer;
9238 *input_line_pointer = '\0';
9239 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9241 *input_line_pointer = sep;
9242 input_line_pointer = save;
9246 if (i.log2_scale_factor != 0 && i.index_reg == 0)
9248 as_warn (_("scale factor of %d without an index register"),
9249 1 << i.log2_scale_factor);
9250 i.log2_scale_factor = 0;
9252 scale = input_line_pointer;
9253 input_line_pointer = save;
9258 i386_displacement (char *disp_start, char *disp_end)
9262 char *save_input_line_pointer;
9263 char *gotfree_input_line;
9265 i386_operand_type bigdisp, types = anydisp;
9268 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9270 as_bad (_("at most %d displacement operands are allowed"),
9271 MAX_MEMORY_OPERANDS);
9275 operand_type_set (&bigdisp, 0);
9276 if ((i.types[this_operand].bitfield.jumpabsolute)
9277 || (!current_templates->start->opcode_modifier.jump
9278 && !current_templates->start->opcode_modifier.jumpdword))
9280 bigdisp.bitfield.disp32 = 1;
9281 override = (i.prefix[ADDR_PREFIX] != 0);
9282 if (flag_code == CODE_64BIT)
9286 bigdisp.bitfield.disp32s = 1;
9287 bigdisp.bitfield.disp64 = 1;
9290 else if ((flag_code == CODE_16BIT) ^ override)
9292 bigdisp.bitfield.disp32 = 0;
9293 bigdisp.bitfield.disp16 = 1;
9298 /* For PC-relative branches, the width of the displacement
9299 is dependent upon data size, not address size. */
9300 override = (i.prefix[DATA_PREFIX] != 0);
9301 if (flag_code == CODE_64BIT)
9303 if (override || i.suffix == WORD_MNEM_SUFFIX)
9304 bigdisp.bitfield.disp16 = 1;
9307 bigdisp.bitfield.disp32 = 1;
9308 bigdisp.bitfield.disp32s = 1;
9314 override = (i.suffix == (flag_code != CODE_16BIT
9316 : LONG_MNEM_SUFFIX));
9317 bigdisp.bitfield.disp32 = 1;
9318 if ((flag_code == CODE_16BIT) ^ override)
9320 bigdisp.bitfield.disp32 = 0;
9321 bigdisp.bitfield.disp16 = 1;
9325 i.types[this_operand] = operand_type_or (i.types[this_operand],
9328 exp = &disp_expressions[i.disp_operands];
9329 i.op[this_operand].disps = exp;
9331 save_input_line_pointer = input_line_pointer;
9332 input_line_pointer = disp_start;
9333 END_STRING_AND_SAVE (disp_end);
9335 #ifndef GCC_ASM_O_HACK
9336 #define GCC_ASM_O_HACK 0
9339 END_STRING_AND_SAVE (disp_end + 1);
9340 if (i.types[this_operand].bitfield.baseIndex
9341 && displacement_string_end[-1] == '+')
9343 /* This hack is to avoid a warning when using the "o"
9344 constraint within gcc asm statements.
9347 #define _set_tssldt_desc(n,addr,limit,type) \
9348 __asm__ __volatile__ ( \
9350 "movw %w1,2+%0\n\t" \
9352 "movb %b1,4+%0\n\t" \
9353 "movb %4,5+%0\n\t" \
9354 "movb $0,6+%0\n\t" \
9355 "movb %h1,7+%0\n\t" \
9357 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9359 This works great except that the output assembler ends
9360 up looking a bit weird if it turns out that there is
9361 no offset. You end up producing code that looks like:
9374 So here we provide the missing zero. */
9376 *displacement_string_end = '0';
9379 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9380 if (gotfree_input_line)
9381 input_line_pointer = gotfree_input_line;
9383 exp_seg = expression (exp);
9386 if (*input_line_pointer)
9387 as_bad (_("junk `%s' after expression"), input_line_pointer);
9389 RESTORE_END_STRING (disp_end + 1);
9391 input_line_pointer = save_input_line_pointer;
9392 if (gotfree_input_line)
9394 free (gotfree_input_line);
9396 if (exp->X_op == O_constant || exp->X_op == O_register)
9397 exp->X_op = O_illegal;
9400 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9402 RESTORE_END_STRING (disp_end);
9408 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9409 i386_operand_type types, const char *disp_start)
9411 i386_operand_type bigdisp;
9414 /* We do this to make sure that the section symbol is in
9415 the symbol table. We will ultimately change the relocation
9416 to be relative to the beginning of the section. */
9417 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9418 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9419 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9421 if (exp->X_op != O_symbol)
9424 if (S_IS_LOCAL (exp->X_add_symbol)
9425 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9426 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9427 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9428 exp->X_op = O_subtract;
9429 exp->X_op_symbol = GOT_symbol;
9430 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9431 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9432 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9433 i.reloc[this_operand] = BFD_RELOC_64;
9435 i.reloc[this_operand] = BFD_RELOC_32;
9438 else if (exp->X_op == O_absent
9439 || exp->X_op == O_illegal
9440 || exp->X_op == O_big)
9443 as_bad (_("missing or invalid displacement expression `%s'"),
9448 else if (flag_code == CODE_64BIT
9449 && !i.prefix[ADDR_PREFIX]
9450 && exp->X_op == O_constant)
9452 /* Since displacement is signed extended to 64bit, don't allow
9453 disp32 and turn off disp32s if they are out of range. */
9454 i.types[this_operand].bitfield.disp32 = 0;
9455 if (!fits_in_signed_long (exp->X_add_number))
9457 i.types[this_operand].bitfield.disp32s = 0;
9458 if (i.types[this_operand].bitfield.baseindex)
9460 as_bad (_("0x%lx out range of signed 32bit displacement"),
9461 (long) exp->X_add_number);
9467 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9468 else if (exp->X_op != O_constant
9469 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9470 && exp_seg != absolute_section
9471 && exp_seg != text_section
9472 && exp_seg != data_section
9473 && exp_seg != bss_section
9474 && exp_seg != undefined_section
9475 && !bfd_is_com_section (exp_seg))
9477 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9482 /* Check if this is a displacement only operand. */
9483 bigdisp = i.types[this_operand];
9484 bigdisp.bitfield.disp8 = 0;
9485 bigdisp.bitfield.disp16 = 0;
9486 bigdisp.bitfield.disp32 = 0;
9487 bigdisp.bitfield.disp32s = 0;
9488 bigdisp.bitfield.disp64 = 0;
9489 if (operand_type_all_zero (&bigdisp))
9490 i.types[this_operand] = operand_type_and (i.types[this_operand],
9496 /* Return the active addressing mode, taking address override and
9497 registers forming the address into consideration. Update the
9498 address override prefix if necessary. */
9500 static enum flag_code
9501 i386_addressing_mode (void)
9503 enum flag_code addr_mode;
9505 if (i.prefix[ADDR_PREFIX])
9506 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9509 addr_mode = flag_code;
9511 #if INFER_ADDR_PREFIX
9512 if (i.mem_operands == 0)
9514 /* Infer address prefix from the first memory operand. */
9515 const reg_entry *addr_reg = i.base_reg;
9517 if (addr_reg == NULL)
9518 addr_reg = i.index_reg;
9522 if (addr_reg->reg_type.bitfield.dword)
9523 addr_mode = CODE_32BIT;
9524 else if (flag_code != CODE_64BIT
9525 && addr_reg->reg_type.bitfield.word)
9526 addr_mode = CODE_16BIT;
9528 if (addr_mode != flag_code)
9530 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9532 /* Change the size of any displacement too. At most one
9533 of Disp16 or Disp32 is set.
9534 FIXME. There doesn't seem to be any real need for
9535 separate Disp16 and Disp32 flags. The same goes for
9536 Imm16 and Imm32. Removing them would probably clean
9537 up the code quite a lot. */
9538 if (flag_code != CODE_64BIT
9539 && (i.types[this_operand].bitfield.disp16
9540 || i.types[this_operand].bitfield.disp32))
9541 i.types[this_operand]
9542 = operand_type_xor (i.types[this_operand], disp16_32);
9552 /* Make sure the memory operand we've been dealt is valid.
9553 Return 1 on success, 0 on a failure. */
9556 i386_index_check (const char *operand_string)
9558 const char *kind = "base/index";
9559 enum flag_code addr_mode = i386_addressing_mode ();
9561 if (current_templates->start->opcode_modifier.isstring
9562 && !current_templates->start->opcode_modifier.immext
9563 && (current_templates->end[-1].opcode_modifier.isstring
9566 /* Memory operands of string insns are special in that they only allow
9567 a single register (rDI, rSI, or rBX) as their memory address. */
9568 const reg_entry *expected_reg;
9569 static const char *di_si[][2] =
9575 static const char *bx[] = { "ebx", "bx", "rbx" };
9577 kind = "string address";
9579 if (current_templates->start->opcode_modifier.repprefixok)
9581 i386_operand_type type = current_templates->end[-1].operand_types[0];
9583 if (!type.bitfield.baseindex
9584 || ((!i.mem_operands != !intel_syntax)
9585 && current_templates->end[-1].operand_types[1]
9586 .bitfield.baseindex))
9587 type = current_templates->end[-1].operand_types[1];
9588 expected_reg = hash_find (reg_hash,
9589 di_si[addr_mode][type.bitfield.esseg]);
9593 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9595 if (i.base_reg != expected_reg
9597 || operand_type_check (i.types[this_operand], disp))
9599 /* The second memory operand must have the same size as
9603 && !((addr_mode == CODE_64BIT
9604 && i.base_reg->reg_type.bitfield.qword)
9605 || (addr_mode == CODE_32BIT
9606 ? i.base_reg->reg_type.bitfield.dword
9607 : i.base_reg->reg_type.bitfield.word)))
9610 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9612 intel_syntax ? '[' : '(',
9614 expected_reg->reg_name,
9615 intel_syntax ? ']' : ')');
9622 as_bad (_("`%s' is not a valid %s expression"),
9623 operand_string, kind);
9628 if (addr_mode != CODE_16BIT)
9630 /* 32-bit/64-bit checks. */
9632 && ((addr_mode == CODE_64BIT
9633 ? !i.base_reg->reg_type.bitfield.qword
9634 : !i.base_reg->reg_type.bitfield.dword)
9635 || (i.index_reg && i.base_reg->reg_num == RegIP)
9636 || i.base_reg->reg_num == RegIZ))
9638 && !i.index_reg->reg_type.bitfield.xmmword
9639 && !i.index_reg->reg_type.bitfield.ymmword
9640 && !i.index_reg->reg_type.bitfield.zmmword
9641 && ((addr_mode == CODE_64BIT
9642 ? !i.index_reg->reg_type.bitfield.qword
9643 : !i.index_reg->reg_type.bitfield.dword)
9644 || !i.index_reg->reg_type.bitfield.baseindex)))
9647 /* bndmk, bndldx, and bndstx have special restrictions. */
9648 if (current_templates->start->base_opcode == 0xf30f1b
9649 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9651 /* They cannot use RIP-relative addressing. */
9652 if (i.base_reg && i.base_reg->reg_num == RegIP)
9654 as_bad (_("`%s' cannot be used here"), operand_string);
9658 /* bndldx and bndstx ignore their scale factor. */
9659 if (current_templates->start->base_opcode != 0xf30f1b
9660 && i.log2_scale_factor)
9661 as_warn (_("register scaling is being ignored here"));
9666 /* 16-bit checks. */
9668 && (!i.base_reg->reg_type.bitfield.word
9669 || !i.base_reg->reg_type.bitfield.baseindex))
9671 && (!i.index_reg->reg_type.bitfield.word
9672 || !i.index_reg->reg_type.bitfield.baseindex
9674 && i.base_reg->reg_num < 6
9675 && i.index_reg->reg_num >= 6
9676 && i.log2_scale_factor == 0))))
9683 /* Handle vector immediates. */
9686 RC_SAE_immediate (const char *imm_start)
9688 unsigned int match_found, j;
9689 const char *pstr = imm_start;
9697 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9699 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9703 rc_op.type = RC_NamesTable[j].type;
9704 rc_op.operand = this_operand;
9705 i.rounding = &rc_op;
9709 as_bad (_("duplicated `%s'"), imm_start);
9712 pstr += RC_NamesTable[j].len;
9722 as_bad (_("Missing '}': '%s'"), imm_start);
9725 /* RC/SAE immediate string should contain nothing more. */;
9728 as_bad (_("Junk after '}': '%s'"), imm_start);
9732 exp = &im_expressions[i.imm_operands++];
9733 i.op[this_operand].imms = exp;
9735 exp->X_op = O_constant;
9736 exp->X_add_number = 0;
9737 exp->X_add_symbol = (symbolS *) 0;
9738 exp->X_op_symbol = (symbolS *) 0;
9740 i.types[this_operand].bitfield.imm8 = 1;
9744 /* Only string instructions can have a second memory operand, so
9745 reduce current_templates to just those if it contains any. */
9747 maybe_adjust_templates (void)
9749 const insn_template *t;
9751 gas_assert (i.mem_operands == 1);
9753 for (t = current_templates->start; t < current_templates->end; ++t)
9754 if (t->opcode_modifier.isstring)
9757 if (t < current_templates->end)
9759 static templates aux_templates;
9760 bfd_boolean recheck;
9762 aux_templates.start = t;
9763 for (; t < current_templates->end; ++t)
9764 if (!t->opcode_modifier.isstring)
9766 aux_templates.end = t;
9768 /* Determine whether to re-check the first memory operand. */
9769 recheck = (aux_templates.start != current_templates->start
9770 || t != current_templates->end);
9772 current_templates = &aux_templates;
9777 if (i.memop1_string != NULL
9778 && i386_index_check (i.memop1_string) == 0)
9787 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9791 i386_att_operand (char *operand_string)
9795 char *op_string = operand_string;
9797 if (is_space_char (*op_string))
9800 /* We check for an absolute prefix (differentiating,
9801 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9802 if (*op_string == ABSOLUTE_PREFIX)
9805 if (is_space_char (*op_string))
9807 i.types[this_operand].bitfield.jumpabsolute = 1;
9810 /* Check if operand is a register. */
9811 if ((r = parse_register (op_string, &end_op)) != NULL)
9813 i386_operand_type temp;
9815 /* Check for a segment override by searching for ':' after a
9816 segment register. */
9818 if (is_space_char (*op_string))
9820 if (*op_string == ':'
9821 && (r->reg_type.bitfield.sreg2
9822 || r->reg_type.bitfield.sreg3))
9827 i.seg[i.mem_operands] = &es;
9830 i.seg[i.mem_operands] = &cs;
9833 i.seg[i.mem_operands] = &ss;
9836 i.seg[i.mem_operands] = &ds;
9839 i.seg[i.mem_operands] = &fs;
9842 i.seg[i.mem_operands] = &gs;
9846 /* Skip the ':' and whitespace. */
9848 if (is_space_char (*op_string))
9851 if (!is_digit_char (*op_string)
9852 && !is_identifier_char (*op_string)
9853 && *op_string != '('
9854 && *op_string != ABSOLUTE_PREFIX)
9856 as_bad (_("bad memory operand `%s'"), op_string);
9859 /* Handle case of %es:*foo. */
9860 if (*op_string == ABSOLUTE_PREFIX)
9863 if (is_space_char (*op_string))
9865 i.types[this_operand].bitfield.jumpabsolute = 1;
9867 goto do_memory_reference;
9870 /* Handle vector operations. */
9871 if (*op_string == '{')
9873 op_string = check_VecOperations (op_string, NULL);
9874 if (op_string == NULL)
9880 as_bad (_("junk `%s' after register"), op_string);
9884 temp.bitfield.baseindex = 0;
9885 i.types[this_operand] = operand_type_or (i.types[this_operand],
9887 i.types[this_operand].bitfield.unspecified = 0;
9888 i.op[this_operand].regs = r;
9891 else if (*op_string == REGISTER_PREFIX)
9893 as_bad (_("bad register name `%s'"), op_string);
9896 else if (*op_string == IMMEDIATE_PREFIX)
9899 if (i.types[this_operand].bitfield.jumpabsolute)
9901 as_bad (_("immediate operand illegal with absolute jump"));
9904 if (!i386_immediate (op_string))
9907 else if (RC_SAE_immediate (operand_string))
9909 /* If it is a RC or SAE immediate, do nothing. */
9912 else if (is_digit_char (*op_string)
9913 || is_identifier_char (*op_string)
9914 || *op_string == '"'
9915 || *op_string == '(')
9917 /* This is a memory reference of some sort. */
9920 /* Start and end of displacement string expression (if found). */
9921 char *displacement_string_start;
9922 char *displacement_string_end;
9925 do_memory_reference:
9926 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9928 if ((i.mem_operands == 1
9929 && !current_templates->start->opcode_modifier.isstring)
9930 || i.mem_operands == 2)
9932 as_bad (_("too many memory references for `%s'"),
9933 current_templates->start->name);
9937 /* Check for base index form. We detect the base index form by
9938 looking for an ')' at the end of the operand, searching
9939 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9941 base_string = op_string + strlen (op_string);
9943 /* Handle vector operations. */
9944 vop_start = strchr (op_string, '{');
9945 if (vop_start && vop_start < base_string)
9947 if (check_VecOperations (vop_start, base_string) == NULL)
9949 base_string = vop_start;
9953 if (is_space_char (*base_string))
9956 /* If we only have a displacement, set-up for it to be parsed later. */
9957 displacement_string_start = op_string;
9958 displacement_string_end = base_string + 1;
9960 if (*base_string == ')')
9963 unsigned int parens_balanced = 1;
9964 /* We've already checked that the number of left & right ()'s are
9965 equal, so this loop will not be infinite. */
9969 if (*base_string == ')')
9971 if (*base_string == '(')
9974 while (parens_balanced);
9976 temp_string = base_string;
9978 /* Skip past '(' and whitespace. */
9980 if (is_space_char (*base_string))
9983 if (*base_string == ','
9984 || ((i.base_reg = parse_register (base_string, &end_op))
9987 displacement_string_end = temp_string;
9989 i.types[this_operand].bitfield.baseindex = 1;
9993 base_string = end_op;
9994 if (is_space_char (*base_string))
9998 /* There may be an index reg or scale factor here. */
9999 if (*base_string == ',')
10002 if (is_space_char (*base_string))
10005 if ((i.index_reg = parse_register (base_string, &end_op))
10008 base_string = end_op;
10009 if (is_space_char (*base_string))
10011 if (*base_string == ',')
10014 if (is_space_char (*base_string))
10017 else if (*base_string != ')')
10019 as_bad (_("expecting `,' or `)' "
10020 "after index register in `%s'"),
10025 else if (*base_string == REGISTER_PREFIX)
10027 end_op = strchr (base_string, ',');
10030 as_bad (_("bad register name `%s'"), base_string);
10034 /* Check for scale factor. */
10035 if (*base_string != ')')
10037 char *end_scale = i386_scale (base_string);
10042 base_string = end_scale;
10043 if (is_space_char (*base_string))
10045 if (*base_string != ')')
10047 as_bad (_("expecting `)' "
10048 "after scale factor in `%s'"),
10053 else if (!i.index_reg)
10055 as_bad (_("expecting index register or scale factor "
10056 "after `,'; got '%c'"),
10061 else if (*base_string != ')')
10063 as_bad (_("expecting `,' or `)' "
10064 "after base register in `%s'"),
10069 else if (*base_string == REGISTER_PREFIX)
10071 end_op = strchr (base_string, ',');
10074 as_bad (_("bad register name `%s'"), base_string);
10079 /* If there's an expression beginning the operand, parse it,
10080 assuming displacement_string_start and
10081 displacement_string_end are meaningful. */
10082 if (displacement_string_start != displacement_string_end)
10084 if (!i386_displacement (displacement_string_start,
10085 displacement_string_end))
10089 /* Special case for (%dx) while doing input/output op. */
10091 && i.base_reg->reg_type.bitfield.inoutportreg
10092 && i.index_reg == 0
10093 && i.log2_scale_factor == 0
10094 && i.seg[i.mem_operands] == 0
10095 && !operand_type_check (i.types[this_operand], disp))
10097 i.types[this_operand] = i.base_reg->reg_type;
10101 if (i386_index_check (operand_string) == 0)
10103 i.flags[this_operand] |= Operand_Mem;
10104 if (i.mem_operands == 0)
10105 i.memop1_string = xstrdup (operand_string);
10110 /* It's not a memory operand; argh! */
10111 as_bad (_("invalid char %s beginning operand %d `%s'"),
10112 output_invalid (*op_string),
10117 return 1; /* Normal return. */
10120 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10121 that an rs_machine_dependent frag may reach. */
10124 i386_frag_max_var (fragS *frag)
10126 /* The only relaxable frags are for jumps.
10127 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10128 gas_assert (frag->fr_type == rs_machine_dependent);
10129 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10134 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
10136 /* STT_GNU_IFUNC symbol must go through PLT. */
10137 if ((symbol_get_bfdsym (fr_symbol)->flags
10138 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10141 if (!S_IS_EXTERNAL (fr_symbol))
10142 /* Symbol may be weak or local. */
10143 return !S_IS_WEAK (fr_symbol);
10145 /* Global symbols with non-default visibility can't be preempted. */
10146 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10149 if (fr_var != NO_RELOC)
10150 switch ((enum bfd_reloc_code_real) fr_var)
10152 case BFD_RELOC_386_PLT32:
10153 case BFD_RELOC_X86_64_PLT32:
10154 /* Symbol with PLT relocation may be preempted. */
10160 /* Global symbols with default visibility in a shared library may be
10161 preempted by another definition. */
10166 /* md_estimate_size_before_relax()
10168 Called just before relax() for rs_machine_dependent frags. The x86
10169 assembler uses these frags to handle variable size jump
10172 Any symbol that is now undefined will not become defined.
10173 Return the correct fr_subtype in the frag.
10174 Return the initial "guess for variable size of frag" to caller.
10175 The guess is actually the growth beyond the fixed part. Whatever
10176 we do to grow the fixed or variable part contributes to our
10180 md_estimate_size_before_relax (fragS *fragP, segT segment)
10182 /* We've already got fragP->fr_subtype right; all we have to do is
10183 check for un-relaxable symbols. On an ELF system, we can't relax
10184 an externally visible symbol, because it may be overridden by a
10186 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
10187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10189 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10192 #if defined (OBJ_COFF) && defined (TE_PE)
10193 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
10194 && S_IS_WEAK (fragP->fr_symbol))
10198 /* Symbol is undefined in this segment, or we need to keep a
10199 reloc so that weak symbols can be overridden. */
10200 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
10201 enum bfd_reloc_code_real reloc_type;
10202 unsigned char *opcode;
10205 if (fragP->fr_var != NO_RELOC)
10206 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
10207 else if (size == 2)
10208 reloc_type = BFD_RELOC_16_PCREL;
10209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10210 else if (need_plt32_p (fragP->fr_symbol))
10211 reloc_type = BFD_RELOC_X86_64_PLT32;
10214 reloc_type = BFD_RELOC_32_PCREL;
10216 old_fr_fix = fragP->fr_fix;
10217 opcode = (unsigned char *) fragP->fr_opcode;
10219 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
10222 /* Make jmp (0xeb) a (d)word displacement jump. */
10224 fragP->fr_fix += size;
10225 fix_new (fragP, old_fr_fix, size,
10227 fragP->fr_offset, 1,
10233 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
10235 /* Negate the condition, and branch past an
10236 unconditional jump. */
10239 /* Insert an unconditional jump. */
10241 /* We added two extra opcode bytes, and have a two byte
10243 fragP->fr_fix += 2 + 2;
10244 fix_new (fragP, old_fr_fix + 2, 2,
10246 fragP->fr_offset, 1,
10250 /* Fall through. */
10253 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10257 fragP->fr_fix += 1;
10258 fixP = fix_new (fragP, old_fr_fix, 1,
10260 fragP->fr_offset, 1,
10261 BFD_RELOC_8_PCREL);
10262 fixP->fx_signed = 1;
10266 /* This changes the byte-displacement jump 0x7N
10267 to the (d)word-displacement jump 0x0f,0x8N. */
10268 opcode[1] = opcode[0] + 0x10;
10269 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10270 /* We've added an opcode byte. */
10271 fragP->fr_fix += 1 + size;
10272 fix_new (fragP, old_fr_fix + 1, size,
10274 fragP->fr_offset, 1,
10279 BAD_CASE (fragP->fr_subtype);
10283 return fragP->fr_fix - old_fr_fix;
10286 /* Guess size depending on current relax state. Initially the relax
10287 state will correspond to a short jump and we return 1, because
10288 the variable part of the frag (the branch offset) is one byte
10289 long. However, we can relax a section more than once and in that
10290 case we must either set fr_subtype back to the unrelaxed state,
10291 or return the value for the appropriate branch. */
10292 return md_relax_table[fragP->fr_subtype].rlx_length;
10295 /* Called after relax() is finished.
10297 In: Address of frag.
10298 fr_type == rs_machine_dependent.
10299 fr_subtype is what the address relaxed to.
10301 Out: Any fixSs and constants are set up.
10302 Caller will turn frag into a ".space 0". */
10305 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10308 unsigned char *opcode;
10309 unsigned char *where_to_put_displacement = NULL;
10310 offsetT target_address;
10311 offsetT opcode_address;
10312 unsigned int extension = 0;
10313 offsetT displacement_from_opcode_start;
10315 opcode = (unsigned char *) fragP->fr_opcode;
10317 /* Address we want to reach in file space. */
10318 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10320 /* Address opcode resides at in file space. */
10321 opcode_address = fragP->fr_address + fragP->fr_fix;
10323 /* Displacement from opcode start to fill into instruction. */
10324 displacement_from_opcode_start = target_address - opcode_address;
10326 if ((fragP->fr_subtype & BIG) == 0)
10328 /* Don't have to change opcode. */
10329 extension = 1; /* 1 opcode + 1 displacement */
10330 where_to_put_displacement = &opcode[1];
10334 if (no_cond_jump_promotion
10335 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10336 as_warn_where (fragP->fr_file, fragP->fr_line,
10337 _("long jump required"));
10339 switch (fragP->fr_subtype)
10341 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10342 extension = 4; /* 1 opcode + 4 displacement */
10344 where_to_put_displacement = &opcode[1];
10347 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10348 extension = 2; /* 1 opcode + 2 displacement */
10350 where_to_put_displacement = &opcode[1];
10353 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10354 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10355 extension = 5; /* 2 opcode + 4 displacement */
10356 opcode[1] = opcode[0] + 0x10;
10357 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10358 where_to_put_displacement = &opcode[2];
10361 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10362 extension = 3; /* 2 opcode + 2 displacement */
10363 opcode[1] = opcode[0] + 0x10;
10364 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10365 where_to_put_displacement = &opcode[2];
10368 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10373 where_to_put_displacement = &opcode[3];
10377 BAD_CASE (fragP->fr_subtype);
10382 /* If size if less then four we are sure that the operand fits,
10383 but if it's 4, then it could be that the displacement is larger
10385 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10387 && ((addressT) (displacement_from_opcode_start - extension
10388 + ((addressT) 1 << 31))
10389 > (((addressT) 2 << 31) - 1)))
10391 as_bad_where (fragP->fr_file, fragP->fr_line,
10392 _("jump target out of range"));
10393 /* Make us emit 0. */
10394 displacement_from_opcode_start = extension;
10396 /* Now put displacement after opcode. */
10397 md_number_to_chars ((char *) where_to_put_displacement,
10398 (valueT) (displacement_from_opcode_start - extension),
10399 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10400 fragP->fr_fix += extension;
10403 /* Apply a fixup (fixP) to segment data, once it has been determined
10404 by our caller that we have all the info we need to fix it up.
10406 Parameter valP is the pointer to the value of the bits.
10408 On the 386, immediates, displacements, and data pointers are all in
10409 the same (little-endian) format, so we don't need to care about which
10410 we are handling. */
10413 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10415 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10416 valueT value = *valP;
10418 #if !defined (TE_Mach)
10419 if (fixP->fx_pcrel)
10421 switch (fixP->fx_r_type)
10427 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10430 case BFD_RELOC_X86_64_32S:
10431 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10434 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10437 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10442 if (fixP->fx_addsy != NULL
10443 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10444 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10445 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10446 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10447 && !use_rela_relocations)
10449 /* This is a hack. There should be a better way to handle this.
10450 This covers for the fact that bfd_install_relocation will
10451 subtract the current location (for partial_inplace, PC relative
10452 relocations); see more below. */
10456 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10459 value += fixP->fx_where + fixP->fx_frag->fr_address;
10461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10464 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10466 if ((sym_seg == seg
10467 || (symbol_section_p (fixP->fx_addsy)
10468 && sym_seg != absolute_section))
10469 && !generic_force_reloc (fixP))
10471 /* Yes, we add the values in twice. This is because
10472 bfd_install_relocation subtracts them out again. I think
10473 bfd_install_relocation is broken, but I don't dare change
10475 value += fixP->fx_where + fixP->fx_frag->fr_address;
10479 #if defined (OBJ_COFF) && defined (TE_PE)
10480 /* For some reason, the PE format does not store a
10481 section address offset for a PC relative symbol. */
10482 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10483 || S_IS_WEAK (fixP->fx_addsy))
10484 value += md_pcrel_from (fixP);
10487 #if defined (OBJ_COFF) && defined (TE_PE)
10488 if (fixP->fx_addsy != NULL
10489 && S_IS_WEAK (fixP->fx_addsy)
10490 /* PR 16858: Do not modify weak function references. */
10491 && ! fixP->fx_pcrel)
10493 #if !defined (TE_PEP)
10494 /* For x86 PE weak function symbols are neither PC-relative
10495 nor do they set S_IS_FUNCTION. So the only reliable way
10496 to detect them is to check the flags of their containing
10498 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10499 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10503 value -= S_GET_VALUE (fixP->fx_addsy);
10507 /* Fix a few things - the dynamic linker expects certain values here,
10508 and we must not disappoint it. */
10509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10510 if (IS_ELF && fixP->fx_addsy)
10511 switch (fixP->fx_r_type)
10513 case BFD_RELOC_386_PLT32:
10514 case BFD_RELOC_X86_64_PLT32:
10515 /* Make the jump instruction point to the address of the operand. At
10516 runtime we merely add the offset to the actual PLT entry. */
10520 case BFD_RELOC_386_TLS_GD:
10521 case BFD_RELOC_386_TLS_LDM:
10522 case BFD_RELOC_386_TLS_IE_32:
10523 case BFD_RELOC_386_TLS_IE:
10524 case BFD_RELOC_386_TLS_GOTIE:
10525 case BFD_RELOC_386_TLS_GOTDESC:
10526 case BFD_RELOC_X86_64_TLSGD:
10527 case BFD_RELOC_X86_64_TLSLD:
10528 case BFD_RELOC_X86_64_GOTTPOFF:
10529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10530 value = 0; /* Fully resolved at runtime. No addend. */
10532 case BFD_RELOC_386_TLS_LE:
10533 case BFD_RELOC_386_TLS_LDO_32:
10534 case BFD_RELOC_386_TLS_LE_32:
10535 case BFD_RELOC_X86_64_DTPOFF32:
10536 case BFD_RELOC_X86_64_DTPOFF64:
10537 case BFD_RELOC_X86_64_TPOFF32:
10538 case BFD_RELOC_X86_64_TPOFF64:
10539 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10542 case BFD_RELOC_386_TLS_DESC_CALL:
10543 case BFD_RELOC_X86_64_TLSDESC_CALL:
10544 value = 0; /* Fully resolved at runtime. No addend. */
10545 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10549 case BFD_RELOC_VTABLE_INHERIT:
10550 case BFD_RELOC_VTABLE_ENTRY:
10557 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10559 #endif /* !defined (TE_Mach) */
10561 /* Are we finished with this relocation now? */
10562 if (fixP->fx_addsy == NULL)
10564 #if defined (OBJ_COFF) && defined (TE_PE)
10565 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10568 /* Remember value for tc_gen_reloc. */
10569 fixP->fx_addnumber = value;
10570 /* Clear out the frag for now. */
10574 else if (use_rela_relocations)
10576 fixP->fx_no_overflow = 1;
10577 /* Remember value for tc_gen_reloc. */
10578 fixP->fx_addnumber = value;
10582 md_number_to_chars (p, value, fixP->fx_size);
10586 md_atof (int type, char *litP, int *sizeP)
10588 /* This outputs the LITTLENUMs in REVERSE order;
10589 in accord with the bigendian 386. */
10590 return ieee_md_atof (type, litP, sizeP, FALSE);
10593 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10596 output_invalid (int c)
10599 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10602 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10603 "(0x%x)", (unsigned char) c);
10604 return output_invalid_buf;
10607 /* REG_STRING starts *before* REGISTER_PREFIX. */
10609 static const reg_entry *
10610 parse_real_register (char *reg_string, char **end_op)
10612 char *s = reg_string;
10614 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10615 const reg_entry *r;
10617 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10618 if (*s == REGISTER_PREFIX)
10621 if (is_space_char (*s))
10624 p = reg_name_given;
10625 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10627 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10628 return (const reg_entry *) NULL;
10632 /* For naked regs, make sure that we are not dealing with an identifier.
10633 This prevents confusing an identifier like `eax_var' with register
10635 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10636 return (const reg_entry *) NULL;
10640 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10642 /* Handle floating point regs, allowing spaces in the (i) part. */
10643 if (r == i386_regtab /* %st is first entry of table */)
10645 if (!cpu_arch_flags.bitfield.cpu8087
10646 && !cpu_arch_flags.bitfield.cpu287
10647 && !cpu_arch_flags.bitfield.cpu387)
10648 return (const reg_entry *) NULL;
10650 if (is_space_char (*s))
10655 if (is_space_char (*s))
10657 if (*s >= '0' && *s <= '7')
10659 int fpr = *s - '0';
10661 if (is_space_char (*s))
10666 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10671 /* We have "%st(" then garbage. */
10672 return (const reg_entry *) NULL;
10676 if (r == NULL || allow_pseudo_reg)
10679 if (operand_type_all_zero (&r->reg_type))
10680 return (const reg_entry *) NULL;
10682 if ((r->reg_type.bitfield.dword
10683 || r->reg_type.bitfield.sreg3
10684 || r->reg_type.bitfield.control
10685 || r->reg_type.bitfield.debug
10686 || r->reg_type.bitfield.test)
10687 && !cpu_arch_flags.bitfield.cpui386)
10688 return (const reg_entry *) NULL;
10690 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10691 return (const reg_entry *) NULL;
10693 if (!cpu_arch_flags.bitfield.cpuavx512f)
10695 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10696 return (const reg_entry *) NULL;
10698 if (!cpu_arch_flags.bitfield.cpuavx)
10700 if (r->reg_type.bitfield.ymmword)
10701 return (const reg_entry *) NULL;
10703 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10704 return (const reg_entry *) NULL;
10708 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10709 return (const reg_entry *) NULL;
10711 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10712 if (!allow_index_reg && r->reg_num == RegIZ)
10713 return (const reg_entry *) NULL;
10715 /* Upper 16 vector registers are only available with VREX in 64bit
10716 mode, and require EVEX encoding. */
10717 if (r->reg_flags & RegVRex)
10719 if (!cpu_arch_flags.bitfield.cpuavx512f
10720 || flag_code != CODE_64BIT)
10721 return (const reg_entry *) NULL;
10723 i.vec_encoding = vex_encoding_evex;
10726 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10727 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10728 && flag_code != CODE_64BIT)
10729 return (const reg_entry *) NULL;
10731 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10732 return (const reg_entry *) NULL;
10737 /* REG_STRING starts *before* REGISTER_PREFIX. */
10739 static const reg_entry *
10740 parse_register (char *reg_string, char **end_op)
10742 const reg_entry *r;
10744 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10745 r = parse_real_register (reg_string, end_op);
10750 char *save = input_line_pointer;
10754 input_line_pointer = reg_string;
10755 c = get_symbol_name (®_string);
10756 symbolP = symbol_find (reg_string);
10757 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10759 const expressionS *e = symbol_get_value_expression (symbolP);
10761 know (e->X_op == O_register);
10762 know (e->X_add_number >= 0
10763 && (valueT) e->X_add_number < i386_regtab_size);
10764 r = i386_regtab + e->X_add_number;
10765 if ((r->reg_flags & RegVRex))
10766 i.vec_encoding = vex_encoding_evex;
10767 *end_op = input_line_pointer;
10769 *input_line_pointer = c;
10770 input_line_pointer = save;
10776 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10778 const reg_entry *r;
10779 char *end = input_line_pointer;
10782 r = parse_register (name, &input_line_pointer);
10783 if (r && end <= input_line_pointer)
10785 *nextcharP = *input_line_pointer;
10786 *input_line_pointer = 0;
10787 e->X_op = O_register;
10788 e->X_add_number = r - i386_regtab;
10791 input_line_pointer = end;
10793 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10797 md_operand (expressionS *e)
10800 const reg_entry *r;
10802 switch (*input_line_pointer)
10804 case REGISTER_PREFIX:
10805 r = parse_real_register (input_line_pointer, &end);
10808 e->X_op = O_register;
10809 e->X_add_number = r - i386_regtab;
10810 input_line_pointer = end;
10815 gas_assert (intel_syntax);
10816 end = input_line_pointer++;
10818 if (*input_line_pointer == ']')
10820 ++input_line_pointer;
10821 e->X_op_symbol = make_expr_symbol (e);
10822 e->X_add_symbol = NULL;
10823 e->X_add_number = 0;
10828 e->X_op = O_absent;
10829 input_line_pointer = end;
10836 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10837 const char *md_shortopts = "kVQ:sqnO::";
10839 const char *md_shortopts = "qnO::";
10842 #define OPTION_32 (OPTION_MD_BASE + 0)
10843 #define OPTION_64 (OPTION_MD_BASE + 1)
10844 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10845 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10846 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10847 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10848 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10849 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10850 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10851 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10852 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10853 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10854 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10855 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10856 #define OPTION_X32 (OPTION_MD_BASE + 14)
10857 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10858 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10859 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10860 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10861 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10862 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10863 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10864 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10865 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10866 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10867 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10869 struct option md_longopts[] =
10871 {"32", no_argument, NULL, OPTION_32},
10872 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10873 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10874 {"64", no_argument, NULL, OPTION_64},
10876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10877 {"x32", no_argument, NULL, OPTION_X32},
10878 {"mshared", no_argument, NULL, OPTION_MSHARED},
10879 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
10881 {"divide", no_argument, NULL, OPTION_DIVIDE},
10882 {"march", required_argument, NULL, OPTION_MARCH},
10883 {"mtune", required_argument, NULL, OPTION_MTUNE},
10884 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10885 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10886 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10887 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10888 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10889 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10890 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10891 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10892 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10893 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10894 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10895 # if defined (TE_PE) || defined (TE_PEP)
10896 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10898 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10899 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10900 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10901 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10902 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10903 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10904 {NULL, no_argument, NULL, 0}
10906 size_t md_longopts_size = sizeof (md_longopts);
10909 md_parse_option (int c, const char *arg)
10912 char *arch, *next, *saved;
10917 optimize_align_code = 0;
10921 quiet_warnings = 1;
10924 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10925 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10926 should be emitted or not. FIXME: Not implemented. */
10930 /* -V: SVR4 argument to print version ID. */
10932 print_version_id ();
10935 /* -k: Ignore for FreeBSD compatibility. */
10940 /* -s: On i386 Solaris, this tells the native assembler to use
10941 .stab instead of .stab.excl. We always use .stab anyhow. */
10944 case OPTION_MSHARED:
10948 case OPTION_X86_USED_NOTE:
10949 if (strcasecmp (arg, "yes") == 0)
10951 else if (strcasecmp (arg, "no") == 0)
10954 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
10959 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10960 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10963 const char **list, **l;
10965 list = bfd_target_list ();
10966 for (l = list; *l != NULL; l++)
10967 if (CONST_STRNEQ (*l, "elf64-x86-64")
10968 || strcmp (*l, "coff-x86-64") == 0
10969 || strcmp (*l, "pe-x86-64") == 0
10970 || strcmp (*l, "pei-x86-64") == 0
10971 || strcmp (*l, "mach-o-x86-64") == 0)
10973 default_arch = "x86_64";
10977 as_fatal (_("no compiled in support for x86_64"));
10983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10987 const char **list, **l;
10989 list = bfd_target_list ();
10990 for (l = list; *l != NULL; l++)
10991 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10993 default_arch = "x86_64:32";
10997 as_fatal (_("no compiled in support for 32bit x86_64"));
11001 as_fatal (_("32bit x86_64 is only supported for ELF"));
11006 default_arch = "i386";
11009 case OPTION_DIVIDE:
11010 #ifdef SVR4_COMMENT_CHARS
11015 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
11017 for (s = i386_comment_chars; *s != '\0'; s++)
11021 i386_comment_chars = n;
11027 saved = xstrdup (arg);
11029 /* Allow -march=+nosse. */
11035 as_fatal (_("invalid -march= option: `%s'"), arg);
11036 next = strchr (arch, '+');
11039 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11041 if (strcmp (arch, cpu_arch [j].name) == 0)
11044 if (! cpu_arch[j].flags.bitfield.cpui386)
11047 cpu_arch_name = cpu_arch[j].name;
11048 cpu_sub_arch_name = NULL;
11049 cpu_arch_flags = cpu_arch[j].flags;
11050 cpu_arch_isa = cpu_arch[j].type;
11051 cpu_arch_isa_flags = cpu_arch[j].flags;
11052 if (!cpu_arch_tune_set)
11054 cpu_arch_tune = cpu_arch_isa;
11055 cpu_arch_tune_flags = cpu_arch_isa_flags;
11059 else if (*cpu_arch [j].name == '.'
11060 && strcmp (arch, cpu_arch [j].name + 1) == 0)
11062 /* ISA extension. */
11063 i386_cpu_flags flags;
11065 flags = cpu_flags_or (cpu_arch_flags,
11066 cpu_arch[j].flags);
11068 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11070 if (cpu_sub_arch_name)
11072 char *name = cpu_sub_arch_name;
11073 cpu_sub_arch_name = concat (name,
11075 (const char *) NULL);
11079 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
11080 cpu_arch_flags = flags;
11081 cpu_arch_isa_flags = flags;
11085 = cpu_flags_or (cpu_arch_isa_flags,
11086 cpu_arch[j].flags);
11091 if (j >= ARRAY_SIZE (cpu_arch))
11093 /* Disable an ISA extension. */
11094 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11095 if (strcmp (arch, cpu_noarch [j].name) == 0)
11097 i386_cpu_flags flags;
11099 flags = cpu_flags_and_not (cpu_arch_flags,
11100 cpu_noarch[j].flags);
11101 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11103 if (cpu_sub_arch_name)
11105 char *name = cpu_sub_arch_name;
11106 cpu_sub_arch_name = concat (arch,
11107 (const char *) NULL);
11111 cpu_sub_arch_name = xstrdup (arch);
11112 cpu_arch_flags = flags;
11113 cpu_arch_isa_flags = flags;
11118 if (j >= ARRAY_SIZE (cpu_noarch))
11119 j = ARRAY_SIZE (cpu_arch);
11122 if (j >= ARRAY_SIZE (cpu_arch))
11123 as_fatal (_("invalid -march= option: `%s'"), arg);
11127 while (next != NULL);
11133 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11134 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11136 if (strcmp (arg, cpu_arch [j].name) == 0)
11138 cpu_arch_tune_set = 1;
11139 cpu_arch_tune = cpu_arch [j].type;
11140 cpu_arch_tune_flags = cpu_arch[j].flags;
11144 if (j >= ARRAY_SIZE (cpu_arch))
11145 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11148 case OPTION_MMNEMONIC:
11149 if (strcasecmp (arg, "att") == 0)
11150 intel_mnemonic = 0;
11151 else if (strcasecmp (arg, "intel") == 0)
11152 intel_mnemonic = 1;
11154 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
11157 case OPTION_MSYNTAX:
11158 if (strcasecmp (arg, "att") == 0)
11160 else if (strcasecmp (arg, "intel") == 0)
11163 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
11166 case OPTION_MINDEX_REG:
11167 allow_index_reg = 1;
11170 case OPTION_MNAKED_REG:
11171 allow_naked_reg = 1;
11174 case OPTION_MSSE2AVX:
11178 case OPTION_MSSE_CHECK:
11179 if (strcasecmp (arg, "error") == 0)
11180 sse_check = check_error;
11181 else if (strcasecmp (arg, "warning") == 0)
11182 sse_check = check_warning;
11183 else if (strcasecmp (arg, "none") == 0)
11184 sse_check = check_none;
11186 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
11189 case OPTION_MOPERAND_CHECK:
11190 if (strcasecmp (arg, "error") == 0)
11191 operand_check = check_error;
11192 else if (strcasecmp (arg, "warning") == 0)
11193 operand_check = check_warning;
11194 else if (strcasecmp (arg, "none") == 0)
11195 operand_check = check_none;
11197 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11200 case OPTION_MAVXSCALAR:
11201 if (strcasecmp (arg, "128") == 0)
11202 avxscalar = vex128;
11203 else if (strcasecmp (arg, "256") == 0)
11204 avxscalar = vex256;
11206 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
11209 case OPTION_MADD_BND_PREFIX:
11210 add_bnd_prefix = 1;
11213 case OPTION_MEVEXLIG:
11214 if (strcmp (arg, "128") == 0)
11215 evexlig = evexl128;
11216 else if (strcmp (arg, "256") == 0)
11217 evexlig = evexl256;
11218 else if (strcmp (arg, "512") == 0)
11219 evexlig = evexl512;
11221 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11224 case OPTION_MEVEXRCIG:
11225 if (strcmp (arg, "rne") == 0)
11227 else if (strcmp (arg, "rd") == 0)
11229 else if (strcmp (arg, "ru") == 0)
11231 else if (strcmp (arg, "rz") == 0)
11234 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11237 case OPTION_MEVEXWIG:
11238 if (strcmp (arg, "0") == 0)
11240 else if (strcmp (arg, "1") == 0)
11243 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11246 # if defined (TE_PE) || defined (TE_PEP)
11247 case OPTION_MBIG_OBJ:
11252 case OPTION_MOMIT_LOCK_PREFIX:
11253 if (strcasecmp (arg, "yes") == 0)
11254 omit_lock_prefix = 1;
11255 else if (strcasecmp (arg, "no") == 0)
11256 omit_lock_prefix = 0;
11258 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11261 case OPTION_MFENCE_AS_LOCK_ADD:
11262 if (strcasecmp (arg, "yes") == 0)
11264 else if (strcasecmp (arg, "no") == 0)
11267 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11270 case OPTION_MRELAX_RELOCATIONS:
11271 if (strcasecmp (arg, "yes") == 0)
11272 generate_relax_relocations = 1;
11273 else if (strcasecmp (arg, "no") == 0)
11274 generate_relax_relocations = 0;
11276 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11279 case OPTION_MAMD64:
11283 case OPTION_MINTEL64:
11291 /* Turn off -Os. */
11292 optimize_for_space = 0;
11294 else if (*arg == 's')
11296 optimize_for_space = 1;
11297 /* Turn on all encoding optimizations. */
11302 optimize = atoi (arg);
11303 /* Turn off -Os. */
11304 optimize_for_space = 0;
11314 #define MESSAGE_TEMPLATE \
11318 output_message (FILE *stream, char *p, char *message, char *start,
11319 int *left_p, const char *name, int len)
11321 int size = sizeof (MESSAGE_TEMPLATE);
11322 int left = *left_p;
11324 /* Reserve 2 spaces for ", " or ",\0" */
11327 /* Check if there is any room. */
11335 p = mempcpy (p, name, len);
11339 /* Output the current message now and start a new one. */
11342 fprintf (stream, "%s\n", message);
11344 left = size - (start - message) - len - 2;
11346 gas_assert (left >= 0);
11348 p = mempcpy (p, name, len);
11356 show_arch (FILE *stream, int ext, int check)
11358 static char message[] = MESSAGE_TEMPLATE;
11359 char *start = message + 27;
11361 int size = sizeof (MESSAGE_TEMPLATE);
11368 left = size - (start - message);
11369 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11371 /* Should it be skipped? */
11372 if (cpu_arch [j].skip)
11375 name = cpu_arch [j].name;
11376 len = cpu_arch [j].len;
11379 /* It is an extension. Skip if we aren't asked to show it. */
11390 /* It is an processor. Skip if we show only extension. */
11393 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11395 /* It is an impossible processor - skip. */
11399 p = output_message (stream, p, message, start, &left, name, len);
11402 /* Display disabled extensions. */
11404 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11406 name = cpu_noarch [j].name;
11407 len = cpu_noarch [j].len;
11408 p = output_message (stream, p, message, start, &left, name,
11413 fprintf (stream, "%s\n", message);
11417 md_show_usage (FILE *stream)
11419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11420 fprintf (stream, _("\
11422 -V print assembler version number\n\
11425 fprintf (stream, _("\
11426 -n Do not optimize code alignment\n\
11427 -q quieten some warnings\n"));
11428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11429 fprintf (stream, _("\
11432 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11433 || defined (TE_PE) || defined (TE_PEP))
11434 fprintf (stream, _("\
11435 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11437 #ifdef SVR4_COMMENT_CHARS
11438 fprintf (stream, _("\
11439 --divide do not treat `/' as a comment character\n"));
11441 fprintf (stream, _("\
11442 --divide ignored\n"));
11444 fprintf (stream, _("\
11445 -march=CPU[,+EXTENSION...]\n\
11446 generate code for CPU and EXTENSION, CPU is one of:\n"));
11447 show_arch (stream, 0, 1);
11448 fprintf (stream, _("\
11449 EXTENSION is combination of:\n"));
11450 show_arch (stream, 1, 0);
11451 fprintf (stream, _("\
11452 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11453 show_arch (stream, 0, 0);
11454 fprintf (stream, _("\
11455 -msse2avx encode SSE instructions with VEX prefix\n"));
11456 fprintf (stream, _("\
11457 -msse-check=[none|error|warning] (default: warning)\n\
11458 check SSE instructions\n"));
11459 fprintf (stream, _("\
11460 -moperand-check=[none|error|warning] (default: warning)\n\
11461 check operand combinations for validity\n"));
11462 fprintf (stream, _("\
11463 -mavxscalar=[128|256] (default: 128)\n\
11464 encode scalar AVX instructions with specific vector\n\
11466 fprintf (stream, _("\
11467 -mevexlig=[128|256|512] (default: 128)\n\
11468 encode scalar EVEX instructions with specific vector\n\
11470 fprintf (stream, _("\
11471 -mevexwig=[0|1] (default: 0)\n\
11472 encode EVEX instructions with specific EVEX.W value\n\
11473 for EVEX.W bit ignored instructions\n"));
11474 fprintf (stream, _("\
11475 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11476 encode EVEX instructions with specific EVEX.RC value\n\
11477 for SAE-only ignored instructions\n"));
11478 fprintf (stream, _("\
11479 -mmnemonic=[att|intel] "));
11480 if (SYSV386_COMPAT)
11481 fprintf (stream, _("(default: att)\n"));
11483 fprintf (stream, _("(default: intel)\n"));
11484 fprintf (stream, _("\
11485 use AT&T/Intel mnemonic\n"));
11486 fprintf (stream, _("\
11487 -msyntax=[att|intel] (default: att)\n\
11488 use AT&T/Intel syntax\n"));
11489 fprintf (stream, _("\
11490 -mindex-reg support pseudo index registers\n"));
11491 fprintf (stream, _("\
11492 -mnaked-reg don't require `%%' prefix for registers\n"));
11493 fprintf (stream, _("\
11494 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11496 fprintf (stream, _("\
11497 -mshared disable branch optimization for shared code\n"));
11498 fprintf (stream, _("\
11499 -mx86-used-note=[no|yes] "));
11500 if (DEFAULT_X86_USED_NOTE)
11501 fprintf (stream, _("(default: yes)\n"));
11503 fprintf (stream, _("(default: no)\n"));
11504 fprintf (stream, _("\
11505 generate x86 used ISA and feature properties\n"));
11507 #if defined (TE_PE) || defined (TE_PEP)
11508 fprintf (stream, _("\
11509 -mbig-obj generate big object files\n"));
11511 fprintf (stream, _("\
11512 -momit-lock-prefix=[no|yes] (default: no)\n\
11513 strip all lock prefixes\n"));
11514 fprintf (stream, _("\
11515 -mfence-as-lock-add=[no|yes] (default: no)\n\
11516 encode lfence, mfence and sfence as\n\
11517 lock addl $0x0, (%%{re}sp)\n"));
11518 fprintf (stream, _("\
11519 -mrelax-relocations=[no|yes] "));
11520 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11521 fprintf (stream, _("(default: yes)\n"));
11523 fprintf (stream, _("(default: no)\n"));
11524 fprintf (stream, _("\
11525 generate relax relocations\n"));
11526 fprintf (stream, _("\
11527 -mamd64 accept only AMD64 ISA [default]\n"));
11528 fprintf (stream, _("\
11529 -mintel64 accept only Intel64 ISA\n"));
11532 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11533 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11534 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11536 /* Pick the target format to use. */
11539 i386_target_format (void)
11541 if (!strncmp (default_arch, "x86_64", 6))
11543 update_code_flag (CODE_64BIT, 1);
11544 if (default_arch[6] == '\0')
11545 x86_elf_abi = X86_64_ABI;
11547 x86_elf_abi = X86_64_X32_ABI;
11549 else if (!strcmp (default_arch, "i386"))
11550 update_code_flag (CODE_32BIT, 1);
11551 else if (!strcmp (default_arch, "iamcu"))
11553 update_code_flag (CODE_32BIT, 1);
11554 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11556 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11557 cpu_arch_name = "iamcu";
11558 cpu_sub_arch_name = NULL;
11559 cpu_arch_flags = iamcu_flags;
11560 cpu_arch_isa = PROCESSOR_IAMCU;
11561 cpu_arch_isa_flags = iamcu_flags;
11562 if (!cpu_arch_tune_set)
11564 cpu_arch_tune = cpu_arch_isa;
11565 cpu_arch_tune_flags = cpu_arch_isa_flags;
11568 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11569 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11573 as_fatal (_("unknown architecture"));
11575 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11576 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11577 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11578 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11580 switch (OUTPUT_FLAVOR)
11582 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11583 case bfd_target_aout_flavour:
11584 return AOUT_TARGET_FORMAT;
11586 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11587 # if defined (TE_PE) || defined (TE_PEP)
11588 case bfd_target_coff_flavour:
11589 if (flag_code == CODE_64BIT)
11590 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11593 # elif defined (TE_GO32)
11594 case bfd_target_coff_flavour:
11595 return "coff-go32";
11597 case bfd_target_coff_flavour:
11598 return "coff-i386";
11601 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11602 case bfd_target_elf_flavour:
11604 const char *format;
11606 switch (x86_elf_abi)
11609 format = ELF_TARGET_FORMAT;
11612 use_rela_relocations = 1;
11614 format = ELF_TARGET_FORMAT64;
11616 case X86_64_X32_ABI:
11617 use_rela_relocations = 1;
11619 disallow_64bit_reloc = 1;
11620 format = ELF_TARGET_FORMAT32;
11623 if (cpu_arch_isa == PROCESSOR_L1OM)
11625 if (x86_elf_abi != X86_64_ABI)
11626 as_fatal (_("Intel L1OM is 64bit only"));
11627 return ELF_TARGET_L1OM_FORMAT;
11629 else if (cpu_arch_isa == PROCESSOR_K1OM)
11631 if (x86_elf_abi != X86_64_ABI)
11632 as_fatal (_("Intel K1OM is 64bit only"));
11633 return ELF_TARGET_K1OM_FORMAT;
11635 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11637 if (x86_elf_abi != I386_ABI)
11638 as_fatal (_("Intel MCU is 32bit only"));
11639 return ELF_TARGET_IAMCU_FORMAT;
11645 #if defined (OBJ_MACH_O)
11646 case bfd_target_mach_o_flavour:
11647 if (flag_code == CODE_64BIT)
11649 use_rela_relocations = 1;
11651 return "mach-o-x86-64";
11654 return "mach-o-i386";
11662 #endif /* OBJ_MAYBE_ more than one */
11665 md_undefined_symbol (char *name)
11667 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11668 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11669 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11670 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11674 if (symbol_find (name))
11675 as_bad (_("GOT already in symbol table"));
11676 GOT_symbol = symbol_new (name, undefined_section,
11677 (valueT) 0, &zero_address_frag);
11684 /* Round up a section size to the appropriate boundary. */
11687 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11689 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11690 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11692 /* For a.out, force the section size to be aligned. If we don't do
11693 this, BFD will align it for us, but it will not write out the
11694 final bytes of the section. This may be a bug in BFD, but it is
11695 easier to fix it here since that is how the other a.out targets
11699 align = bfd_get_section_alignment (stdoutput, segment);
11700 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11707 /* On the i386, PC-relative offsets are relative to the start of the
11708 next instruction. That is, the address of the offset, plus its
11709 size, since the offset is always the last part of the insn. */
11712 md_pcrel_from (fixS *fixP)
11714 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11720 s_bss (int ignore ATTRIBUTE_UNUSED)
11724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11726 obj_elf_section_change_hook ();
11728 temp = get_absolute_expression ();
11729 subseg_set (bss_section, (subsegT) temp);
11730 demand_empty_rest_of_line ();
11736 i386_validate_fix (fixS *fixp)
11738 if (fixp->fx_subsy)
11740 if (fixp->fx_subsy == GOT_symbol)
11742 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11746 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11747 if (fixp->fx_tcbit2)
11748 fixp->fx_r_type = (fixp->fx_tcbit
11749 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11750 : BFD_RELOC_X86_64_GOTPCRELX);
11753 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11758 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11760 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11762 fixp->fx_subsy = 0;
11765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11766 else if (!object_64bit)
11768 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11769 && fixp->fx_tcbit2)
11770 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11776 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11779 bfd_reloc_code_real_type code;
11781 switch (fixp->fx_r_type)
11783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11784 case BFD_RELOC_SIZE32:
11785 case BFD_RELOC_SIZE64:
11786 if (S_IS_DEFINED (fixp->fx_addsy)
11787 && !S_IS_EXTERNAL (fixp->fx_addsy))
11789 /* Resolve size relocation against local symbol to size of
11790 the symbol plus addend. */
11791 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11792 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11793 && !fits_in_unsigned_long (value))
11794 as_bad_where (fixp->fx_file, fixp->fx_line,
11795 _("symbol size computation overflow"));
11796 fixp->fx_addsy = NULL;
11797 fixp->fx_subsy = NULL;
11798 md_apply_fix (fixp, (valueT *) &value, NULL);
11802 /* Fall through. */
11804 case BFD_RELOC_X86_64_PLT32:
11805 case BFD_RELOC_X86_64_GOT32:
11806 case BFD_RELOC_X86_64_GOTPCREL:
11807 case BFD_RELOC_X86_64_GOTPCRELX:
11808 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11809 case BFD_RELOC_386_PLT32:
11810 case BFD_RELOC_386_GOT32:
11811 case BFD_RELOC_386_GOT32X:
11812 case BFD_RELOC_386_GOTOFF:
11813 case BFD_RELOC_386_GOTPC:
11814 case BFD_RELOC_386_TLS_GD:
11815 case BFD_RELOC_386_TLS_LDM:
11816 case BFD_RELOC_386_TLS_LDO_32:
11817 case BFD_RELOC_386_TLS_IE_32:
11818 case BFD_RELOC_386_TLS_IE:
11819 case BFD_RELOC_386_TLS_GOTIE:
11820 case BFD_RELOC_386_TLS_LE_32:
11821 case BFD_RELOC_386_TLS_LE:
11822 case BFD_RELOC_386_TLS_GOTDESC:
11823 case BFD_RELOC_386_TLS_DESC_CALL:
11824 case BFD_RELOC_X86_64_TLSGD:
11825 case BFD_RELOC_X86_64_TLSLD:
11826 case BFD_RELOC_X86_64_DTPOFF32:
11827 case BFD_RELOC_X86_64_DTPOFF64:
11828 case BFD_RELOC_X86_64_GOTTPOFF:
11829 case BFD_RELOC_X86_64_TPOFF32:
11830 case BFD_RELOC_X86_64_TPOFF64:
11831 case BFD_RELOC_X86_64_GOTOFF64:
11832 case BFD_RELOC_X86_64_GOTPC32:
11833 case BFD_RELOC_X86_64_GOT64:
11834 case BFD_RELOC_X86_64_GOTPCREL64:
11835 case BFD_RELOC_X86_64_GOTPC64:
11836 case BFD_RELOC_X86_64_GOTPLT64:
11837 case BFD_RELOC_X86_64_PLTOFF64:
11838 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11839 case BFD_RELOC_X86_64_TLSDESC_CALL:
11840 case BFD_RELOC_RVA:
11841 case BFD_RELOC_VTABLE_ENTRY:
11842 case BFD_RELOC_VTABLE_INHERIT:
11844 case BFD_RELOC_32_SECREL:
11846 code = fixp->fx_r_type;
11848 case BFD_RELOC_X86_64_32S:
11849 if (!fixp->fx_pcrel)
11851 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11852 code = fixp->fx_r_type;
11855 /* Fall through. */
11857 if (fixp->fx_pcrel)
11859 switch (fixp->fx_size)
11862 as_bad_where (fixp->fx_file, fixp->fx_line,
11863 _("can not do %d byte pc-relative relocation"),
11865 code = BFD_RELOC_32_PCREL;
11867 case 1: code = BFD_RELOC_8_PCREL; break;
11868 case 2: code = BFD_RELOC_16_PCREL; break;
11869 case 4: code = BFD_RELOC_32_PCREL; break;
11871 case 8: code = BFD_RELOC_64_PCREL; break;
11877 switch (fixp->fx_size)
11880 as_bad_where (fixp->fx_file, fixp->fx_line,
11881 _("can not do %d byte relocation"),
11883 code = BFD_RELOC_32;
11885 case 1: code = BFD_RELOC_8; break;
11886 case 2: code = BFD_RELOC_16; break;
11887 case 4: code = BFD_RELOC_32; break;
11889 case 8: code = BFD_RELOC_64; break;
11896 if ((code == BFD_RELOC_32
11897 || code == BFD_RELOC_32_PCREL
11898 || code == BFD_RELOC_X86_64_32S)
11900 && fixp->fx_addsy == GOT_symbol)
11903 code = BFD_RELOC_386_GOTPC;
11905 code = BFD_RELOC_X86_64_GOTPC32;
11907 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11909 && fixp->fx_addsy == GOT_symbol)
11911 code = BFD_RELOC_X86_64_GOTPC64;
11914 rel = XNEW (arelent);
11915 rel->sym_ptr_ptr = XNEW (asymbol *);
11916 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11918 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11920 if (!use_rela_relocations)
11922 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11923 vtable entry to be used in the relocation's section offset. */
11924 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11925 rel->address = fixp->fx_offset;
11926 #if defined (OBJ_COFF) && defined (TE_PE)
11927 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11928 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11933 /* Use the rela in 64bit mode. */
11936 if (disallow_64bit_reloc)
11939 case BFD_RELOC_X86_64_DTPOFF64:
11940 case BFD_RELOC_X86_64_TPOFF64:
11941 case BFD_RELOC_64_PCREL:
11942 case BFD_RELOC_X86_64_GOTOFF64:
11943 case BFD_RELOC_X86_64_GOT64:
11944 case BFD_RELOC_X86_64_GOTPCREL64:
11945 case BFD_RELOC_X86_64_GOTPC64:
11946 case BFD_RELOC_X86_64_GOTPLT64:
11947 case BFD_RELOC_X86_64_PLTOFF64:
11948 as_bad_where (fixp->fx_file, fixp->fx_line,
11949 _("cannot represent relocation type %s in x32 mode"),
11950 bfd_get_reloc_code_name (code));
11956 if (!fixp->fx_pcrel)
11957 rel->addend = fixp->fx_offset;
11961 case BFD_RELOC_X86_64_PLT32:
11962 case BFD_RELOC_X86_64_GOT32:
11963 case BFD_RELOC_X86_64_GOTPCREL:
11964 case BFD_RELOC_X86_64_GOTPCRELX:
11965 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11966 case BFD_RELOC_X86_64_TLSGD:
11967 case BFD_RELOC_X86_64_TLSLD:
11968 case BFD_RELOC_X86_64_GOTTPOFF:
11969 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11970 case BFD_RELOC_X86_64_TLSDESC_CALL:
11971 rel->addend = fixp->fx_offset - fixp->fx_size;
11974 rel->addend = (section->vma
11976 + fixp->fx_addnumber
11977 + md_pcrel_from (fixp));
11982 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11983 if (rel->howto == NULL)
11985 as_bad_where (fixp->fx_file, fixp->fx_line,
11986 _("cannot represent relocation type %s"),
11987 bfd_get_reloc_code_name (code));
11988 /* Set howto to a garbage value so that we can keep going. */
11989 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11990 gas_assert (rel->howto != NULL);
11996 #include "tc-i386-intel.c"
11999 tc_x86_parse_to_dw2regnum (expressionS *exp)
12001 int saved_naked_reg;
12002 char saved_register_dot;
12004 saved_naked_reg = allow_naked_reg;
12005 allow_naked_reg = 1;
12006 saved_register_dot = register_chars['.'];
12007 register_chars['.'] = '.';
12008 allow_pseudo_reg = 1;
12009 expression_and_evaluate (exp);
12010 allow_pseudo_reg = 0;
12011 register_chars['.'] = saved_register_dot;
12012 allow_naked_reg = saved_naked_reg;
12014 if (exp->X_op == O_register && exp->X_add_number >= 0)
12016 if ((addressT) exp->X_add_number < i386_regtab_size)
12018 exp->X_op = O_constant;
12019 exp->X_add_number = i386_regtab[exp->X_add_number]
12020 .dw2_regnum[flag_code >> 1];
12023 exp->X_op = O_illegal;
12028 tc_x86_frame_initial_instructions (void)
12030 static unsigned int sp_regno[2];
12032 if (!sp_regno[flag_code >> 1])
12034 char *saved_input = input_line_pointer;
12035 char sp[][4] = {"esp", "rsp"};
12038 input_line_pointer = sp[flag_code >> 1];
12039 tc_x86_parse_to_dw2regnum (&exp);
12040 gas_assert (exp.X_op == O_constant);
12041 sp_regno[flag_code >> 1] = exp.X_add_number;
12042 input_line_pointer = saved_input;
12045 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12046 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
12050 x86_dwarf2_addr_size (void)
12052 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12053 if (x86_elf_abi == X86_64_X32_ABI)
12056 return bfd_arch_bits_per_address (stdoutput) / 8;
12060 i386_elf_section_type (const char *str, size_t len)
12062 if (flag_code == CODE_64BIT
12063 && len == sizeof ("unwind") - 1
12064 && strncmp (str, "unwind", 6) == 0)
12065 return SHT_X86_64_UNWIND;
12072 i386_solaris_fix_up_eh_frame (segT sec)
12074 if (flag_code == CODE_64BIT)
12075 elf_section_type (sec) = SHT_X86_64_UNWIND;
12081 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12085 exp.X_op = O_secrel;
12086 exp.X_add_symbol = symbol;
12087 exp.X_add_number = 0;
12088 emit_expr (&exp, size);
12092 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12093 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12096 x86_64_section_letter (int letter, const char **ptr_msg)
12098 if (flag_code == CODE_64BIT)
12101 return SHF_X86_64_LARGE;
12103 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12106 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
12111 x86_64_section_word (char *str, size_t len)
12113 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
12114 return SHF_X86_64_LARGE;
12120 handle_large_common (int small ATTRIBUTE_UNUSED)
12122 if (flag_code != CODE_64BIT)
12124 s_comm_internal (0, elf_common_parse);
12125 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12129 static segT lbss_section;
12130 asection *saved_com_section_ptr = elf_com_section_ptr;
12131 asection *saved_bss_section = bss_section;
12133 if (lbss_section == NULL)
12135 flagword applicable;
12136 segT seg = now_seg;
12137 subsegT subseg = now_subseg;
12139 /* The .lbss section is for local .largecomm symbols. */
12140 lbss_section = subseg_new (".lbss", 0);
12141 applicable = bfd_applicable_section_flags (stdoutput);
12142 bfd_set_section_flags (stdoutput, lbss_section,
12143 applicable & SEC_ALLOC);
12144 seg_info (lbss_section)->bss = 1;
12146 subseg_set (seg, subseg);
12149 elf_com_section_ptr = &_bfd_elf_large_com_section;
12150 bss_section = lbss_section;
12152 s_comm_internal (0, elf_common_parse);
12154 elf_com_section_ptr = saved_com_section_ptr;
12155 bss_section = saved_bss_section;
12158 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */