1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
849 CPU_BTVER1_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
851 CPU_BTVER2_FLAGS, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
869 CPU_SSSE3_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_1_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
881 CPU_AVX512F_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
883 CPU_AVX512CD_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
885 CPU_AVX512ER_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
887 CPU_AVX512PF_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
889 CPU_AVX512DQ_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
891 CPU_AVX512BW_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
893 CPU_AVX512VL_FLAGS, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
897 CPU_VMFUNC_FLAGS, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
901 CPU_XSAVE_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEOPT_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEC_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
907 CPU_XSAVES_FLAGS, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
915 CPU_FSGSBASE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
917 CPU_RDRND_FLAGS, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
931 CPU_MOVBE_FLAGS, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
937 CPU_LZCNT_FLAGS, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
943 CPU_INVPCID_FLAGS, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
945 CPU_CLFLUSH_FLAGS, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
949 CPU_SYSCALL_FLAGS, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
951 CPU_RDTSCP_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
953 CPU_3DNOW_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
955 CPU_3DNOWA_FLAGS, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
957 CPU_PADLOCK_FLAGS, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
963 CPU_SSE4A_FLAGS, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
973 CPU_RDSEED_FLAGS, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
975 CPU_PRFCHW_FLAGS, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
983 CPU_CLFLUSHOPT_FLAGS, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
985 CPU_PREFETCHWT1_FLAGS, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
991 CPU_AVX512IFMA_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
993 CPU_AVX512VBMI_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1007 CPU_CLZERO_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1009 CPU_MWAITX_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1011 CPU_OSPKE_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1013 CPU_RDPID_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
1040 static const noarch_entry cpu_noarch[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1089 && *input_line_pointer == ',')
1091 align = parse_align (needs_align - 1);
1093 if (align == (addressT) -1)
1108 bss_alloc (symbolP, size, align);
1113 pe_lcomm (int needs_align)
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1119 const pseudo_typeS md_pseudo_table[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1124 {"align", s_align_ptwo, 0},
1126 {"arch", set_cpu_arch, 0},
1130 {"lcomm", pe_lcomm, 1},
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1136 {"slong", signed_cons, 4},
1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
1143 {"code64", set_code_flag, CODE_64BIT},
1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
1156 {"file", dwarf2_directive_file, 0},
1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1161 {"secrel32", pe_directive_secrel, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control *op_hash;
1172 /* Hash table for register lookup. */
1173 static struct hash_control *reg_hash;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1[] =
1180 static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt[] = {
1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt[] = {
1206 f32_1, f32_2, f16_3, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1238 alt_9, alt_10, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
1261 last = count % max_single_nop_size;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1269 nops = patt[last - 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1280 memcpy (where + offset, nops, last);
1285 fits_in_imm7 (offsetT num)
1287 return (num & 0x7f) == num;
1291 fits_in_imm31 (offsetT num)
1293 return (num & 0x7fffffff) == num;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1302 const unsigned char *const *patt = NULL;
1303 int max_single_nop_size;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
1307 switch (fragP->fr_type)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code == CODE_16BIT)
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
1354 case PROCESSOR_CORE:
1355 case PROCESSOR_CORE2:
1356 case PROCESSOR_COREI7:
1357 case PROCESSOR_L1OM:
1358 case PROCESSOR_K1OM:
1359 case PROCESSOR_GENERIC64:
1361 case PROCESSOR_ATHLON:
1363 case PROCESSOR_AMDFAM10:
1365 case PROCESSOR_ZNVER:
1369 case PROCESSOR_I386:
1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
1372 case PROCESSOR_PENTIUMPRO:
1373 case PROCESSOR_IAMCU:
1374 case PROCESSOR_GENERIC32:
1381 switch (fragP->tc_frag_data.tune)
1383 case PROCESSOR_UNKNOWN:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386:
1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
1392 case PROCESSOR_IAMCU:
1394 case PROCESSOR_ATHLON:
1396 case PROCESSOR_AMDFAM10:
1398 case PROCESSOR_ZNVER:
1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
1412 case PROCESSOR_CORE2:
1413 case PROCESSOR_COREI7:
1414 case PROCESSOR_L1OM:
1415 case PROCESSOR_K1OM:
1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1421 case PROCESSOR_GENERIC64:
1427 if (patt == f32_patt)
1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1442 limit = max_single_nop_size;
1444 if (fragP->fr_type == rs_fill_nop)
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1457 fragP->fr_var = count;
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1465 /* Use "jmp disp8" if possible. */
1467 where[0] = jump_disp8[0];
1473 unsigned int size_of_jump;
1475 if (flag_code == CODE_16BIT)
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1483 where[0] = jump32_disp32[0];
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
1505 operand_type_all_zero (const union i386_operand_type *x)
1507 switch (ARRAY_SIZE(x->array))
1518 return !x->array[0];
1525 operand_type_set (union i386_operand_type *x, unsigned int v)
1527 switch (ARRAY_SIZE(x->array))
1545 operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
1548 switch (ARRAY_SIZE(x->array))
1551 if (x->array[2] != y->array[2])
1555 if (x->array[1] != y->array[1])
1559 return x->array[0] == y->array[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags *x)
1569 switch (ARRAY_SIZE(x->array))
1584 return !x->array[0];
1591 cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1594 switch (ARRAY_SIZE(x->array))
1597 if (x->array[3] != y->array[3])
1601 if (x->array[2] != y->array[2])
1605 if (x->array[1] != y->array[1])
1609 return x->array[0] == y->array[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f)
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1626 switch (ARRAY_SIZE (x.array))
1629 x.array [3] &= y.array [3];
1632 x.array [2] &= y.array [2];
1635 x.array [1] &= y.array [1];
1638 x.array [0] &= y.array [0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1649 switch (ARRAY_SIZE (x.array))
1652 x.array [3] |= y.array [3];
1655 x.array [2] |= y.array [2];
1658 x.array [1] |= y.array [1];
1661 x.array [0] |= y.array [0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1672 switch (ARRAY_SIZE (x.array))
1675 x.array [3] &= ~y.array [3];
1678 x.array [2] &= ~y.array [2];
1681 x.array [1] &= ~y.array [1];
1684 x.array [0] &= ~y.array [0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template *t)
1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1709 if (cpu_flags_all_zero (&x))
1711 /* This instruction is available on all archs. */
1712 match |= CPU_FLAGS_ARCH_MATCH;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu = cpu_arch_flags;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1722 x.bitfield.cpuavx512vl = 0;
1724 cpu = cpu_flags_and (x, cpu);
1725 if (!cpu_flags_all_zero (&cpu))
1727 if (x.bitfield.cpuavx)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1737 else if (x.bitfield.cpuavx512f)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1747 match |= CPU_FLAGS_ARCH_MATCH;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x, i386_operand_type y)
1756 switch (ARRAY_SIZE (x.array))
1759 x.array [2] &= y.array [2];
1762 x.array [1] &= y.array [1];
1765 x.array [0] &= y.array [0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1776 switch (ARRAY_SIZE (x.array))
1779 x.array [2] &= ~y.array [2];
1782 x.array [1] &= ~y.array [1];
1785 x.array [0] &= ~y.array [0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x, i386_operand_type y)
1796 switch (ARRAY_SIZE (x.array))
1799 x.array [2] |= y.array [2];
1802 x.array [1] |= y.array [1];
1805 x.array [0] |= y.array [0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x, i386_operand_type y)
1816 switch (ARRAY_SIZE (x.array))
1819 x.array [2] ^= y.array [2];
1822 x.array [1] ^= y.array [1];
1825 x.array [0] ^= y.array [0];
1833 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1835 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
1841 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1842 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1843 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1852 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1863 operand_type_check (i386_operand_type t, enum operand_type c)
1868 return t.bitfield.reg;
1871 return (t.bitfield.imm8
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1901 operand J for instruction template T. */
1904 match_reg_size (const insn_template *t, unsigned int wanted, unsigned int given)
1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
1918 /* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1922 match_simd_size (const insn_template *t, unsigned int wanted, unsigned int given)
1924 return !((i.types[given].bitfield.xmmword
1925 && !t->operand_types[wanted].bitfield.xmmword)
1926 || (i.types[given].bitfield.ymmword
1927 && !t->operand_types[wanted].bitfield.ymmword)
1928 || (i.types[given].bitfield.zmmword
1929 && !t->operand_types[wanted].bitfield.zmmword));
1932 /* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1936 match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given)
1938 return (match_reg_size (t, wanted, given)
1939 && !((i.types[given].bitfield.unspecified
1941 && !t->operand_types[wanted].bitfield.unspecified)
1942 || (i.types[given].bitfield.fword
1943 && !t->operand_types[wanted].bitfield.fword)
1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
1948 || ((t->operand_types[wanted].bitfield.regsimd
1949 && !t->opcode_modifier.broadcast
1950 && (t->operand_types[wanted].bitfield.byte
1951 || t->operand_types[wanted].bitfield.word
1952 || t->operand_types[wanted].bitfield.dword
1953 || t->operand_types[wanted].bitfield.qword))
1954 ? (i.types[given].bitfield.xmmword
1955 || i.types[given].bitfield.ymmword
1956 || i.types[given].bitfield.zmmword)
1957 : !match_simd_size(t, wanted, given))));
1960 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1961 operands for instruction template T, and it has MATCH_REVERSE set if there
1962 is no size conflict on any operands for the template with operands reversed
1963 (and the template allows for reversing in the first place). */
1965 #define MATCH_STRAIGHT 1
1966 #define MATCH_REVERSE 2
1968 static INLINE unsigned int
1969 operand_size_match (const insn_template *t)
1971 unsigned int j, match = MATCH_STRAIGHT;
1973 /* Don't check jump instructions. */
1974 if (t->opcode_modifier.jump
1975 || t->opcode_modifier.jumpbyte
1976 || t->opcode_modifier.jumpdword
1977 || t->opcode_modifier.jumpintersegment)
1980 /* Check memory and accumulator operand size. */
1981 for (j = 0; j < i.operands; j++)
1983 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1984 && t->operand_types[j].bitfield.anysize)
1987 if (t->operand_types[j].bitfield.reg
1988 && !match_reg_size (t, j, j))
1994 if (t->operand_types[j].bitfield.regsimd
1995 && !match_simd_size (t, j, j))
2001 if (t->operand_types[j].bitfield.acc
2002 && (!match_reg_size (t, j, j) || !match_simd_size (t, j, j)))
2008 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2015 if (!t->opcode_modifier.d)
2019 i.error = operand_size_mismatch;
2023 /* Check reverse. */
2024 gas_assert (i.operands == 2);
2026 for (j = 0; j < 2; j++)
2028 if ((t->operand_types[j].bitfield.reg
2029 || t->operand_types[j].bitfield.acc)
2030 && !match_reg_size (t, j, !j))
2033 if (i.types[!j].bitfield.mem
2034 && !match_mem_size (t, j, !j))
2038 return match | MATCH_REVERSE;
2042 operand_type_match (i386_operand_type overlap,
2043 i386_operand_type given)
2045 i386_operand_type temp = overlap;
2047 temp.bitfield.jumpabsolute = 0;
2048 temp.bitfield.unspecified = 0;
2049 temp.bitfield.byte = 0;
2050 temp.bitfield.word = 0;
2051 temp.bitfield.dword = 0;
2052 temp.bitfield.fword = 0;
2053 temp.bitfield.qword = 0;
2054 temp.bitfield.tbyte = 0;
2055 temp.bitfield.xmmword = 0;
2056 temp.bitfield.ymmword = 0;
2057 temp.bitfield.zmmword = 0;
2058 if (operand_type_all_zero (&temp))
2061 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2062 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2066 i.error = operand_type_mismatch;
2070 /* If given types g0 and g1 are registers they must be of the same type
2071 unless the expected operand type register overlap is null.
2072 Memory operand size of certain SIMD instructions is also being checked
2076 operand_type_register_match (i386_operand_type g0,
2077 i386_operand_type t0,
2078 i386_operand_type g1,
2079 i386_operand_type t1)
2081 if (!g0.bitfield.reg
2082 && !g0.bitfield.regsimd
2083 && (!operand_type_check (g0, anymem)
2084 || g0.bitfield.unspecified
2085 || !t0.bitfield.regsimd))
2088 if (!g1.bitfield.reg
2089 && !g1.bitfield.regsimd
2090 && (!operand_type_check (g1, anymem)
2091 || g1.bitfield.unspecified
2092 || !t1.bitfield.regsimd))
2095 if (g0.bitfield.byte == g1.bitfield.byte
2096 && g0.bitfield.word == g1.bitfield.word
2097 && g0.bitfield.dword == g1.bitfield.dword
2098 && g0.bitfield.qword == g1.bitfield.qword
2099 && g0.bitfield.xmmword == g1.bitfield.xmmword
2100 && g0.bitfield.ymmword == g1.bitfield.ymmword
2101 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2104 if (!(t0.bitfield.byte & t1.bitfield.byte)
2105 && !(t0.bitfield.word & t1.bitfield.word)
2106 && !(t0.bitfield.dword & t1.bitfield.dword)
2107 && !(t0.bitfield.qword & t1.bitfield.qword)
2108 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2109 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2110 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2113 i.error = register_type_mismatch;
2118 static INLINE unsigned int
2119 register_number (const reg_entry *r)
2121 unsigned int nr = r->reg_num;
2123 if (r->reg_flags & RegRex)
2126 if (r->reg_flags & RegVRex)
2132 static INLINE unsigned int
2133 mode_from_disp_size (i386_operand_type t)
2135 if (t.bitfield.disp8)
2137 else if (t.bitfield.disp16
2138 || t.bitfield.disp32
2139 || t.bitfield.disp32s)
2146 fits_in_signed_byte (addressT num)
2148 return num + 0x80 <= 0xff;
2152 fits_in_unsigned_byte (addressT num)
2158 fits_in_unsigned_word (addressT num)
2160 return num <= 0xffff;
2164 fits_in_signed_word (addressT num)
2166 return num + 0x8000 <= 0xffff;
2170 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2175 return num + 0x80000000 <= 0xffffffff;
2177 } /* fits_in_signed_long() */
2180 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2185 return num <= 0xffffffff;
2187 } /* fits_in_unsigned_long() */
2190 fits_in_disp8 (offsetT num)
2192 int shift = i.memshift;
2198 mask = (1 << shift) - 1;
2200 /* Return 0 if NUM isn't properly aligned. */
2204 /* Check if NUM will fit in 8bit after shift. */
2205 return fits_in_signed_byte (num >> shift);
2209 fits_in_imm4 (offsetT num)
2211 return (num & 0xf) == num;
2214 static i386_operand_type
2215 smallest_imm_type (offsetT num)
2217 i386_operand_type t;
2219 operand_type_set (&t, 0);
2220 t.bitfield.imm64 = 1;
2222 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2224 /* This code is disabled on the 486 because all the Imm1 forms
2225 in the opcode table are slower on the i486. They're the
2226 versions with the implicitly specified single-position
2227 displacement, which has another syntax if you really want to
2229 t.bitfield.imm1 = 1;
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2236 else if (fits_in_signed_byte (num))
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm8s = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2244 else if (fits_in_unsigned_byte (num))
2246 t.bitfield.imm8 = 1;
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2251 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2253 t.bitfield.imm16 = 1;
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2257 else if (fits_in_signed_long (num))
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2262 else if (fits_in_unsigned_long (num))
2263 t.bitfield.imm32 = 1;
2269 offset_in_range (offsetT val, int size)
2275 case 1: mask = ((addressT) 1 << 8) - 1; break;
2276 case 2: mask = ((addressT) 1 << 16) - 1; break;
2277 case 4: mask = ((addressT) 2 << 31) - 1; break;
2279 case 8: mask = ((addressT) 2 << 63) - 1; break;
2285 /* If BFD64, sign extend val for 32bit address mode. */
2286 if (flag_code != CODE_64BIT
2287 || i.prefix[ADDR_PREFIX])
2288 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2289 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2292 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2294 char buf1[40], buf2[40];
2296 sprint_value (buf1, val);
2297 sprint_value (buf2, val & mask);
2298 as_warn (_("%s shortened to %s"), buf1, buf2);
2313 a. PREFIX_EXIST if attempting to add a prefix where one from the
2314 same class already exists.
2315 b. PREFIX_LOCK if lock prefix is added.
2316 c. PREFIX_REP if rep/repne prefix is added.
2317 d. PREFIX_DS if ds prefix is added.
2318 e. PREFIX_OTHER if other prefix is added.
2321 static enum PREFIX_GROUP
2322 add_prefix (unsigned int prefix)
2324 enum PREFIX_GROUP ret = PREFIX_OTHER;
2327 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2328 && flag_code == CODE_64BIT)
2330 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2331 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2332 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2333 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2344 case DS_PREFIX_OPCODE:
2347 case CS_PREFIX_OPCODE:
2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
2361 case LOCK_PREFIX_OPCODE:
2370 case ADDR_PREFIX_OPCODE:
2374 case DATA_PREFIX_OPCODE:
2378 if (i.prefix[q] != 0)
2386 i.prefix[q] |= prefix;
2389 as_bad (_("same type of prefix used twice"));
2395 update_code_flag (int value, int check)
2397 PRINTF_LIKE ((*as_error));
2399 flag_code = (enum flag_code) value;
2400 if (flag_code == CODE_64BIT)
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2413 as_error = as_fatal;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2422 as_error = as_fatal;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
2428 stackop_size = '\0';
2432 set_code_flag (int value)
2434 update_code_flag (value, 0);
2438 set_16bit_gcc_code_flag (int new_code_flag)
2440 flag_code = (enum flag_code) new_code_flag;
2441 if (flag_code != CODE_16BIT)
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
2445 stackop_size = LONG_MNEM_SUFFIX;
2449 set_intel_syntax (int syntax_flag)
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2458 int e = get_symbol_name (&string);
2460 if (strcmp (string, "prefix") == 0)
2462 else if (strcmp (string, "noprefix") == 0)
2465 as_bad (_("bad argument to syntax directive."));
2466 (void) restore_line_pointer (e);
2468 demand_empty_rest_of_line ();
2470 intel_syntax = syntax_flag;
2472 if (ask_naked_reg == 0)
2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2476 allow_naked_reg = (ask_naked_reg < 0);
2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
2482 register_prefix = allow_naked_reg ? "" : "%";
2486 set_intel_mnemonic (int mnemonic_flag)
2488 intel_mnemonic = mnemonic_flag;
2492 set_allow_index_reg (int flag)
2494 allow_index_reg = flag;
2498 set_check (int what)
2500 enum check_kind *kind;
2505 kind = &operand_check;
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2519 int e = get_symbol_name (&string);
2521 if (strcmp (string, "none") == 0)
2523 else if (strcmp (string, "warning") == 0)
2524 *kind = check_warning;
2525 else if (strcmp (string, "error") == 0)
2526 *kind = check_error;
2528 as_bad (_("bad argument to %s_check directive."), str);
2529 (void) restore_line_pointer (e);
2532 as_bad (_("missing argument for %s_check directive"), str);
2534 demand_empty_rest_of_line ();
2538 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2544 /* Intel LIOM is only supported on ELF. */
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2554 arch = default_arch;
2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2562 /* If we are targeting Intel L1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2564 || new_flag.bitfield.cpul1om)
2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2577 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2584 int e = get_symbol_name (&string);
2586 i386_cpu_flags flags;
2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2590 if (strcmp (string, cpu_arch[j].name) == 0)
2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2596 cpu_arch_name = cpu_arch[j].name;
2597 cpu_sub_arch_name = NULL;
2598 cpu_arch_flags = cpu_arch[j].flags;
2599 if (flag_code == CODE_64BIT)
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
2611 if (!cpu_arch_tune_set)
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2619 flags = cpu_flags_or (cpu_arch_flags,
2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2624 if (cpu_sub_arch_name)
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
2629 (const char *) NULL);
2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2634 cpu_arch_flags = flags;
2635 cpu_arch_isa_flags = flags;
2639 = cpu_flags_or (cpu_arch_isa_flags,
2641 (void) restore_line_pointer (e);
2642 demand_empty_rest_of_line ();
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2649 /* Disable an ISA extension. */
2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2657 if (cpu_sub_arch_name)
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2674 j = ARRAY_SIZE (cpu_arch);
2677 if (j >= ARRAY_SIZE (cpu_arch))
2678 as_bad (_("no such architecture: `%s'"), string);
2680 *input_line_pointer = e;
2683 as_bad (_("missing cpu architecture"));
2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2702 (void) restore_line_pointer (e);
2705 demand_empty_rest_of_line ();
2708 enum bfd_architecture
2711 if (cpu_arch_isa == PROCESSOR_L1OM)
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2733 return bfd_arch_i386;
2739 if (!strncmp (default_arch, "x86_64", 6))
2741 if (cpu_arch_isa == PROCESSOR_L1OM)
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2755 else if (default_arch[6] == '\0')
2756 return bfd_mach_x86_64;
2758 return bfd_mach_x64_32;
2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2770 return bfd_mach_i386_i386;
2773 as_fatal (_("unknown architecture"));
2779 const char *hash_err;
2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2784 /* Initialize op_hash hash table. */
2785 op_hash = hash_new ();
2788 const insn_template *optab;
2789 templates *core_optab;
2791 /* Setup for loop. */
2793 core_optab = XNEW (templates);
2794 core_optab->start = optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2802 /* different name --> ship out current template list;
2803 add to hash table; & begin anew. */
2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2807 (void *) core_optab);
2810 as_fatal (_("can't hash %s: %s"),
2814 if (optab->name == NULL)
2816 core_optab = XNEW (templates);
2817 core_optab->start = optab;
2822 /* Initialize reg_hash hash table. */
2823 reg_hash = hash_new ();
2825 const reg_entry *regtab;
2826 unsigned int regtab_size = i386_regtab_size;
2828 for (regtab = i386_regtab; regtab_size--; regtab++)
2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2832 as_fatal (_("can't hash %s: %s"),
2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2843 for (c = 0; c < 256; c++)
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2852 else if (ISLOWER (c))
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2858 else if (ISUPPER (c))
2860 mnemonic_chars[c] = TOLOWER (c);
2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2864 else if (c == '{' || c == '}')
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2870 if (ISALPHA (c) || ISDIGIT (c))
2871 identifier_chars[c] = c;
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2880 identifier_chars['@'] = '@';
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
2886 digit_chars['-'] = '-';
2887 mnemonic_chars['_'] = '_';
2888 mnemonic_chars['-'] = '-';
2889 mnemonic_chars['.'] = '.';
2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2897 if (flag_code == CODE_64BIT)
2899 #if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2903 x86_dwarf2_return_column = 16;
2905 x86_cie_data_alignment = -8;
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2915 i386_print_statistics (FILE *file)
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2923 /* Debugging routines for md_assemble. */
2924 static void pte (insn_template *);
2925 static void pt (i386_operand_type);
2926 static void pe (expressionS *);
2927 static void ps (symbolS *);
2930 pi (char *line, i386_insn *x)
2934 fprintf (stdout, "%s: template ", line);
2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2941 x->rm.mode, x->rm.reg, x->rm.regmem);
2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
2949 for (j = 0; j < x->operands; j++)
2951 fprintf (stdout, " #%d: ", j + 1);
2953 fprintf (stdout, "\n");
2954 if (x->types[j].bitfield.reg
2955 || x->types[j].bitfield.regmmx
2956 || x->types[j].bitfield.regsimd
2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
2971 pte (insn_template *t)
2974 fprintf (stdout, " %d operands ", t->operands);
2975 fprintf (stdout, "opcode %x ", t->base_opcode);
2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
2978 if (t->opcode_modifier.d)
2979 fprintf (stdout, "D");
2980 if (t->opcode_modifier.w)
2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
2983 for (j = 0; j < t->operands; j++)
2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
2987 fprintf (stdout, "\n");
2994 fprintf (stdout, " operation %d\n", e->X_op);
2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
2997 if (e->X_add_symbol)
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3014 fprintf (stdout, "%s type %s%s",
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3020 static struct type_name
3022 i386_operand_type mask;
3025 const type_names[] =
3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
3057 { OPERAND_TYPE_REGYMM, "rYMM" },
3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
3060 { OPERAND_TYPE_ESSEG, "es" },
3064 pt (i386_operand_type t)
3067 i386_operand_type a;
3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3071 a = operand_type_and (t, type_names[j].mask);
3072 if (!operand_type_all_zero (&a))
3073 fprintf (stdout, "%s, ", type_names[j].name);
3078 #endif /* DEBUG386 */
3080 static bfd_reloc_code_real_type
3081 reloc (unsigned int size,
3084 bfd_reloc_code_real_type other)
3086 if (other != NO_RELOC)
3088 reloc_howto_type *rel;
3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3119 if (other == BFD_RELOC_SIZE32)
3122 other = BFD_RELOC_SIZE64;
3125 as_bad (_("there are no pc-relative size relocations"));
3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3137 as_bad (_("unknown relocation (%u)"), other);
3138 else if (size != bfd_get_reloc_size (rel))
3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3140 bfd_get_reloc_size (rel),
3142 else if (pcrel && !rel->pc_relative)
3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3146 || (rel->complain_on_overflow == complain_overflow_unsigned
3148 as_bad (_("relocated field and relocation type differ in signedness"));
3157 as_bad (_("there are no unsigned pc-relative relocations"));
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
3162 case 4: return BFD_RELOC_32_PCREL;
3163 case 8: return BFD_RELOC_64_PCREL;
3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3172 case 4: return BFD_RELOC_X86_64_32S;
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
3189 /* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3195 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3255 intel_float_operand (const char *mnemonic)
3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3264 switch (mnemonic[1])
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3270 return 2 /* integer op */;
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3288 switch (mnemonic[3])
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3307 /* Build the VEX prefix. */
3310 build_vex_prefix (const insn_template *t)
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3324 register_specifier = 0xf;
3326 /* Use 2-byte VEX prefix by swapping destination and source
3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
3330 && i.operands == i.reg_operands
3331 && i.tm.opcode_modifier.vexopcode == VEX0F
3332 && i.tm.opcode_modifier.load
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3346 gas_assert (i.rm.mode == 3);
3350 i.rm.regmem = i.rm.reg;
3353 /* Use the next insn. */
3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
3359 else if (i.tm.opcode_modifier.vex == VEX256)
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3381 case DATA_PREFIX_OPCODE:
3384 case REPE_PREFIX_OPCODE:
3387 case REPNE_PREFIX_OPCODE:
3394 /* Use 2-byte VEX prefix if possible. */
3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
3397 && i.tm.opcode_modifier.vexw != VEXW1
3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3400 /* 2-byte VEX prefix. */
3404 i.vex.bytes[0] = 0xc5;
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3415 /* 3-byte VEX prefix. */
3420 switch (i.tm.opcode_modifier.vexopcode)
3424 i.vex.bytes[0] = 0xc4;
3428 i.vex.bytes[0] = 0xc4;
3432 i.vex.bytes[0] = 0xc4;
3436 i.vex.bytes[0] = 0x8f;
3440 i.vex.bytes[0] = 0x8f;
3444 i.vex.bytes[0] = 0x8f;
3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3466 static INLINE bfd_boolean
3467 is_evex_encoding (const insn_template *t)
3469 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3474 /* Build the EVEX prefix. */
3477 build_evex_prefix (void)
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3482 rex_byte vrex_used = 0;
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3487 gas_assert ((i.vrex & REX_X) == 0);
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3500 register_specifier = 0xf;
3502 /* Encode upper 16 vector index register in the fourth byte of
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3515 case DATA_PREFIX_OPCODE:
3518 case REPE_PREFIX_OPCODE:
3521 case REPNE_PREFIX_OPCODE:
3528 /* 4 byte EVEX prefix. */
3530 i.vex.bytes[0] = 0x62;
3533 switch (i.tm.opcode_modifier.vexopcode)
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3569 i.vex.bytes[1] &= ~0x40;
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3584 /* If w is not set it means we are dealing with WIG instruction. */
3587 if (evexwig == evexw1)
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3602 /* Don't always set the broadcast bit if there is no RC. */
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
3625 else if (i.broadcast && (int) op == i.broadcast->operand)
3627 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3628 * i.broadcast->type)
3631 i.tm.opcode_modifier.evex = EVEX512;
3634 i.tm.opcode_modifier.evex = EVEX256;
3637 i.tm.opcode_modifier.evex = EVEX128;
3648 switch (i.tm.opcode_modifier.evex)
3650 case EVEXLIG: /* LL' is ignored */
3651 vec_length = evexlig << 5;
3654 vec_length = 0 << 5;
3657 vec_length = 1 << 5;
3660 vec_length = 2 << 5;
3666 i.vex.bytes[3] |= vec_length;
3667 /* Encode the broadcast bit. */
3669 i.vex.bytes[3] |= 0x10;
3673 if (i.rounding->type != saeonly)
3674 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3676 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3679 if (i.mask && i.mask->mask)
3680 i.vex.bytes[3] |= i.mask->mask->reg_num;
3684 process_immext (void)
3688 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3691 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3692 with an opcode suffix which is coded in the same place as an
3693 8-bit immediate field would be.
3694 Here we check those operands and remove them afterwards. */
3697 for (x = 0; x < i.operands; x++)
3698 if (register_number (i.op[x].regs) != x)
3699 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3700 register_prefix, i.op[x].regs->reg_name, x + 1,
3706 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3708 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3709 suffix which is coded in the same place as an 8-bit immediate
3711 Here we check those operands and remove them afterwards. */
3714 if (i.operands != 3)
3717 for (x = 0; x < 2; x++)
3718 if (register_number (i.op[x].regs) != x)
3719 goto bad_register_operand;
3721 /* Check for third operand for mwaitx/monitorx insn. */
3722 if (register_number (i.op[x].regs)
3723 != (x + (i.tm.extension_opcode == 0xfb)))
3725 bad_register_operand:
3726 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3727 register_prefix, i.op[x].regs->reg_name, x+1,
3734 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3735 which is coded in the same place as an 8-bit immediate field
3736 would be. Here we fake an 8-bit immediate operand from the
3737 opcode suffix stored in tm.extension_opcode.
3739 AVX instructions also use this encoding, for some of
3740 3 argument instructions. */
3742 gas_assert (i.imm_operands <= 1
3744 || ((i.tm.opcode_modifier.vex
3745 || i.tm.opcode_modifier.vexopcode
3746 || is_evex_encoding (&i.tm))
3747 && i.operands <= 4)));
3749 exp = &im_expressions[i.imm_operands++];
3750 i.op[i.operands].imms = exp;
3751 i.types[i.operands] = imm8;
3753 exp->X_op = O_constant;
3754 exp->X_add_number = i.tm.extension_opcode;
3755 i.tm.extension_opcode = None;
3762 switch (i.tm.opcode_modifier.hleprefixok)
3767 as_bad (_("invalid instruction `%s' after `%s'"),
3768 i.tm.name, i.hle_prefix);
3771 if (i.prefix[LOCK_PREFIX])
3773 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3777 case HLEPrefixRelease:
3778 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3780 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3784 if (i.mem_operands == 0
3785 || !operand_type_check (i.types[i.operands - 1], anymem))
3787 as_bad (_("memory destination needed for instruction `%s'"
3788 " after `xrelease'"), i.tm.name);
3795 /* Try the shortest encoding by shortening operand size. */
3798 optimize_encoding (void)
3802 if (optimize_for_space
3803 && i.reg_operands == 1
3804 && i.imm_operands == 1
3805 && !i.types[1].bitfield.byte
3806 && i.op[0].imms->X_op == O_constant
3807 && fits_in_imm7 (i.op[0].imms->X_add_number)
3808 && ((i.tm.base_opcode == 0xa8
3809 && i.tm.extension_opcode == None)
3810 || (i.tm.base_opcode == 0xf6
3811 && i.tm.extension_opcode == 0x0)))
3814 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3816 unsigned int base_regnum = i.op[1].regs->reg_num;
3817 if (flag_code == CODE_64BIT || base_regnum < 4)
3819 i.types[1].bitfield.byte = 1;
3820 /* Ignore the suffix. */
3822 if (base_regnum >= 4
3823 && !(i.op[1].regs->reg_flags & RegRex))
3825 /* Handle SP, BP, SI and DI registers. */
3826 if (i.types[1].bitfield.word)
3828 else if (i.types[1].bitfield.dword)
3836 else if (flag_code == CODE_64BIT
3837 && ((i.types[1].bitfield.qword
3838 && i.reg_operands == 1
3839 && i.imm_operands == 1
3840 && i.op[0].imms->X_op == O_constant
3841 && ((i.tm.base_opcode == 0xb0
3842 && i.tm.extension_opcode == None
3843 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3844 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3845 && (((i.tm.base_opcode == 0x24
3846 || i.tm.base_opcode == 0xa8)
3847 && i.tm.extension_opcode == None)
3848 || (i.tm.base_opcode == 0x80
3849 && i.tm.extension_opcode == 0x4)
3850 || ((i.tm.base_opcode == 0xf6
3851 || i.tm.base_opcode == 0xc6)
3852 && i.tm.extension_opcode == 0x0)))))
3853 || (i.types[0].bitfield.qword
3854 && ((i.reg_operands == 2
3855 && i.op[0].regs == i.op[1].regs
3856 && ((i.tm.base_opcode == 0x30
3857 || i.tm.base_opcode == 0x28)
3858 && i.tm.extension_opcode == None))
3859 || (i.reg_operands == 1
3861 && i.tm.base_opcode == 0x30
3862 && i.tm.extension_opcode == None)))))
3865 andq $imm31, %r64 -> andl $imm31, %r32
3866 testq $imm31, %r64 -> testl $imm31, %r32
3867 xorq %r64, %r64 -> xorl %r32, %r32
3868 subq %r64, %r64 -> subl %r32, %r32
3869 movq $imm31, %r64 -> movl $imm31, %r32
3870 movq $imm32, %r64 -> movl $imm32, %r32
3872 i.tm.opcode_modifier.norex64 = 1;
3873 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3876 movq $imm31, %r64 -> movl $imm31, %r32
3877 movq $imm32, %r64 -> movl $imm32, %r32
3879 i.tm.operand_types[0].bitfield.imm32 = 1;
3880 i.tm.operand_types[0].bitfield.imm32s = 0;
3881 i.tm.operand_types[0].bitfield.imm64 = 0;
3882 i.types[0].bitfield.imm32 = 1;
3883 i.types[0].bitfield.imm32s = 0;
3884 i.types[0].bitfield.imm64 = 0;
3885 i.types[1].bitfield.dword = 1;
3886 i.types[1].bitfield.qword = 0;
3887 if (i.tm.base_opcode == 0xc6)
3890 movq $imm31, %r64 -> movl $imm31, %r32
3892 i.tm.base_opcode = 0xb0;
3893 i.tm.extension_opcode = None;
3894 i.tm.opcode_modifier.shortform = 1;
3895 i.tm.opcode_modifier.modrm = 0;
3899 else if (optimize > 1
3900 && i.reg_operands == 3
3901 && i.op[0].regs == i.op[1].regs
3902 && !i.types[2].bitfield.xmmword
3903 && (i.tm.opcode_modifier.vex
3904 || ((!i.mask || i.mask->zeroing)
3906 && is_evex_encoding (&i.tm)
3907 && (i.vec_encoding != vex_encoding_evex
3908 || i.tm.cpu_flags.bitfield.cpuavx512vl
3909 || (i.tm.operand_types[2].bitfield.zmmword
3910 && i.types[2].bitfield.ymmword)
3911 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3912 && ((i.tm.base_opcode == 0x55
3913 || i.tm.base_opcode == 0x6655
3914 || i.tm.base_opcode == 0x66df
3915 || i.tm.base_opcode == 0x57
3916 || i.tm.base_opcode == 0x6657
3917 || i.tm.base_opcode == 0x66ef
3918 || i.tm.base_opcode == 0x66f8
3919 || i.tm.base_opcode == 0x66f9
3920 || i.tm.base_opcode == 0x66fa
3921 || i.tm.base_opcode == 0x66fb)
3922 && i.tm.extension_opcode == None))
3925 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3927 EVEX VOP %zmmM, %zmmM, %zmmN
3928 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3929 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3930 EVEX VOP %ymmM, %ymmM, %ymmN
3931 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3933 VEX VOP %ymmM, %ymmM, %ymmN
3934 -> VEX VOP %xmmM, %xmmM, %xmmN
3935 VOP, one of vpandn and vpxor:
3936 VEX VOP %ymmM, %ymmM, %ymmN
3937 -> VEX VOP %xmmM, %xmmM, %xmmN
3938 VOP, one of vpandnd and vpandnq:
3939 EVEX VOP %zmmM, %zmmM, %zmmN
3940 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3941 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3942 EVEX VOP %ymmM, %ymmM, %ymmN
3943 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3944 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3945 VOP, one of vpxord and vpxorq:
3946 EVEX VOP %zmmM, %zmmM, %zmmN
3947 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3948 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3949 EVEX VOP %ymmM, %ymmM, %ymmN
3950 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3951 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3953 if (is_evex_encoding (&i.tm))
3955 if (i.vec_encoding == vex_encoding_evex)
3956 i.tm.opcode_modifier.evex = EVEX128;
3959 i.tm.opcode_modifier.vex = VEX128;
3960 i.tm.opcode_modifier.vexw = VEXW0;
3961 i.tm.opcode_modifier.evex = 0;
3965 i.tm.opcode_modifier.vex = VEX128;
3967 if (i.tm.opcode_modifier.vex)
3968 for (j = 0; j < 3; j++)
3970 i.types[j].bitfield.xmmword = 1;
3971 i.types[j].bitfield.ymmword = 0;
3976 /* This is the guts of the machine-dependent assembler. LINE points to a
3977 machine dependent instruction. This function is supposed to emit
3978 the frags/bytes it assembles to. */
3981 md_assemble (char *line)
3984 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3985 const insn_template *t;
3987 /* Initialize globals. */
3988 memset (&i, '\0', sizeof (i));
3989 for (j = 0; j < MAX_OPERANDS; j++)
3990 i.reloc[j] = NO_RELOC;
3991 memset (disp_expressions, '\0', sizeof (disp_expressions));
3992 memset (im_expressions, '\0', sizeof (im_expressions));
3993 save_stack_p = save_stack;
3995 /* First parse an instruction mnemonic & call i386_operand for the operands.
3996 We assume that the scrubber has arranged it so that line[0] is the valid
3997 start of a (possibly prefixed) mnemonic. */
3999 line = parse_insn (line, mnemonic);
4002 mnem_suffix = i.suffix;
4004 line = parse_operands (line, mnemonic);
4006 xfree (i.memop1_string);
4007 i.memop1_string = NULL;
4011 /* Now we've parsed the mnemonic into a set of templates, and have the
4012 operands at hand. */
4014 /* All intel opcodes have reversed operands except for "bound" and
4015 "enter". We also don't reverse intersegment "jmp" and "call"
4016 instructions with 2 immediate operands so that the immediate segment
4017 precedes the offset, as it does when in AT&T mode. */
4020 && (strcmp (mnemonic, "bound") != 0)
4021 && (strcmp (mnemonic, "invlpga") != 0)
4022 && !(operand_type_check (i.types[0], imm)
4023 && operand_type_check (i.types[1], imm)))
4026 /* The order of the immediates should be reversed
4027 for 2 immediates extrq and insertq instructions */
4028 if (i.imm_operands == 2
4029 && (strcmp (mnemonic, "extrq") == 0
4030 || strcmp (mnemonic, "insertq") == 0))
4031 swap_2_operands (0, 1);
4036 /* Don't optimize displacement for movabs since it only takes 64bit
4039 && i.disp_encoding != disp_encoding_32bit
4040 && (flag_code != CODE_64BIT
4041 || strcmp (mnemonic, "movabs") != 0))
4044 /* Next, we find a template that matches the given insn,
4045 making sure the overlap of the given operands types is consistent
4046 with the template operand types. */
4048 if (!(t = match_template (mnem_suffix)))
4051 if (sse_check != check_none
4052 && !i.tm.opcode_modifier.noavx
4053 && !i.tm.cpu_flags.bitfield.cpuavx
4054 && (i.tm.cpu_flags.bitfield.cpusse
4055 || i.tm.cpu_flags.bitfield.cpusse2
4056 || i.tm.cpu_flags.bitfield.cpusse3
4057 || i.tm.cpu_flags.bitfield.cpussse3
4058 || i.tm.cpu_flags.bitfield.cpusse4_1
4059 || i.tm.cpu_flags.bitfield.cpusse4_2
4060 || i.tm.cpu_flags.bitfield.cpupclmul
4061 || i.tm.cpu_flags.bitfield.cpuaes
4062 || i.tm.cpu_flags.bitfield.cpugfni))
4064 (sse_check == check_warning
4066 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4069 /* Zap movzx and movsx suffix. The suffix has been set from
4070 "word ptr" or "byte ptr" on the source operand in Intel syntax
4071 or extracted from mnemonic in AT&T syntax. But we'll use
4072 the destination register to choose the suffix for encoding. */
4073 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4075 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4076 there is no suffix, the default will be byte extension. */
4077 if (i.reg_operands != 2
4080 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4085 if (i.tm.opcode_modifier.fwait)
4086 if (!add_prefix (FWAIT_OPCODE))
4089 /* Check if REP prefix is OK. */
4090 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4092 as_bad (_("invalid instruction `%s' after `%s'"),
4093 i.tm.name, i.rep_prefix);
4097 /* Check for lock without a lockable instruction. Destination operand
4098 must be memory unless it is xchg (0x86). */
4099 if (i.prefix[LOCK_PREFIX]
4100 && (!i.tm.opcode_modifier.islockable
4101 || i.mem_operands == 0
4102 || (i.tm.base_opcode != 0x86
4103 && !operand_type_check (i.types[i.operands - 1], anymem))))
4105 as_bad (_("expecting lockable instruction after `lock'"));
4109 /* Check if HLE prefix is OK. */
4110 if (i.hle_prefix && !check_hle ())
4113 /* Check BND prefix. */
4114 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4115 as_bad (_("expecting valid branch instruction after `bnd'"));
4117 /* Check NOTRACK prefix. */
4118 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4119 as_bad (_("expecting indirect branch instruction after `notrack'"));
4121 if (i.tm.cpu_flags.bitfield.cpumpx)
4123 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4124 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4125 else if (flag_code != CODE_16BIT
4126 ? i.prefix[ADDR_PREFIX]
4127 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4128 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4131 /* Insert BND prefix. */
4132 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4134 if (!i.prefix[BND_PREFIX])
4135 add_prefix (BND_PREFIX_OPCODE);
4136 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4138 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4139 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4143 /* Check string instruction segment overrides. */
4144 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4146 if (!check_string ())
4148 i.disp_operands = 0;
4151 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4152 optimize_encoding ();
4154 if (!process_suffix ())
4157 /* Update operand types. */
4158 for (j = 0; j < i.operands; j++)
4159 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4161 /* Make still unresolved immediate matches conform to size of immediate
4162 given in i.suffix. */
4163 if (!finalize_imm ())
4166 if (i.types[0].bitfield.imm1)
4167 i.imm_operands = 0; /* kludge for shift insns. */
4169 /* We only need to check those implicit registers for instructions
4170 with 3 operands or less. */
4171 if (i.operands <= 3)
4172 for (j = 0; j < i.operands; j++)
4173 if (i.types[j].bitfield.inoutportreg
4174 || i.types[j].bitfield.shiftcount
4175 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4178 /* ImmExt should be processed after SSE2AVX. */
4179 if (!i.tm.opcode_modifier.sse2avx
4180 && i.tm.opcode_modifier.immext)
4183 /* For insns with operands there are more diddles to do to the opcode. */
4186 if (!process_operands ())
4189 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4191 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4192 as_warn (_("translating to `%sp'"), i.tm.name);
4195 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4196 || is_evex_encoding (&i.tm))
4198 if (flag_code == CODE_16BIT)
4200 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4205 if (i.tm.opcode_modifier.vex)
4206 build_vex_prefix (t);
4208 build_evex_prefix ();
4211 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4212 instructions may define INT_OPCODE as well, so avoid this corner
4213 case for those instructions that use MODRM. */
4214 if (i.tm.base_opcode == INT_OPCODE
4215 && !i.tm.opcode_modifier.modrm
4216 && i.op[0].imms->X_add_number == 3)
4218 i.tm.base_opcode = INT3_OPCODE;
4222 if ((i.tm.opcode_modifier.jump
4223 || i.tm.opcode_modifier.jumpbyte
4224 || i.tm.opcode_modifier.jumpdword)
4225 && i.op[0].disps->X_op == O_constant)
4227 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4228 the absolute address given by the constant. Since ix86 jumps and
4229 calls are pc relative, we need to generate a reloc. */
4230 i.op[0].disps->X_add_symbol = &abs_symbol;
4231 i.op[0].disps->X_op = O_symbol;
4234 if (i.tm.opcode_modifier.rex64)
4237 /* For 8 bit registers we need an empty rex prefix. Also if the
4238 instruction already has a prefix, we need to convert old
4239 registers to new ones. */
4241 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4242 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4243 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4244 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4245 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4246 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4251 i.rex |= REX_OPCODE;
4252 for (x = 0; x < 2; x++)
4254 /* Look for 8 bit operand that uses old registers. */
4255 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4256 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4258 /* In case it is "hi" register, give up. */
4259 if (i.op[x].regs->reg_num > 3)
4260 as_bad (_("can't encode register '%s%s' in an "
4261 "instruction requiring REX prefix."),
4262 register_prefix, i.op[x].regs->reg_name);
4264 /* Otherwise it is equivalent to the extended register.
4265 Since the encoding doesn't change this is merely
4266 cosmetic cleanup for debug output. */
4268 i.op[x].regs = i.op[x].regs + 8;
4273 if (i.rex == 0 && i.rex_encoding)
4275 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4276 that uses legacy register. If it is "hi" register, don't add
4277 the REX_OPCODE byte. */
4279 for (x = 0; x < 2; x++)
4280 if (i.types[x].bitfield.reg
4281 && i.types[x].bitfield.byte
4282 && (i.op[x].regs->reg_flags & RegRex64) == 0
4283 && i.op[x].regs->reg_num > 3)
4285 i.rex_encoding = FALSE;
4294 add_prefix (REX_OPCODE | i.rex);
4296 /* We are ready to output the insn. */
4301 parse_insn (char *line, char *mnemonic)
4304 char *token_start = l;
4307 const insn_template *t;
4313 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4318 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4320 as_bad (_("no such instruction: `%s'"), token_start);
4325 if (!is_space_char (*l)
4326 && *l != END_OF_INSN
4328 || (*l != PREFIX_SEPARATOR
4331 as_bad (_("invalid character %s in mnemonic"),
4332 output_invalid (*l));
4335 if (token_start == l)
4337 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4338 as_bad (_("expecting prefix; got nothing"));
4340 as_bad (_("expecting mnemonic; got nothing"));
4344 /* Look up instruction (or prefix) via hash table. */
4345 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4347 if (*l != END_OF_INSN
4348 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4349 && current_templates
4350 && current_templates->start->opcode_modifier.isprefix)
4352 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4354 as_bad ((flag_code != CODE_64BIT
4355 ? _("`%s' is only supported in 64-bit mode")
4356 : _("`%s' is not supported in 64-bit mode")),
4357 current_templates->start->name);
4360 /* If we are in 16-bit mode, do not allow addr16 or data16.
4361 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4362 if ((current_templates->start->opcode_modifier.size16
4363 || current_templates->start->opcode_modifier.size32)
4364 && flag_code != CODE_64BIT
4365 && (current_templates->start->opcode_modifier.size32
4366 ^ (flag_code == CODE_16BIT)))
4368 as_bad (_("redundant %s prefix"),
4369 current_templates->start->name);
4372 if (current_templates->start->opcode_length == 0)
4374 /* Handle pseudo prefixes. */
4375 switch (current_templates->start->base_opcode)
4379 i.disp_encoding = disp_encoding_8bit;
4383 i.disp_encoding = disp_encoding_32bit;
4387 i.dir_encoding = dir_encoding_load;
4391 i.dir_encoding = dir_encoding_store;
4395 i.vec_encoding = vex_encoding_vex2;
4399 i.vec_encoding = vex_encoding_vex3;
4403 i.vec_encoding = vex_encoding_evex;
4407 i.rex_encoding = TRUE;
4411 i.no_optimize = TRUE;
4419 /* Add prefix, checking for repeated prefixes. */
4420 switch (add_prefix (current_templates->start->base_opcode))
4425 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4426 i.notrack_prefix = current_templates->start->name;
4429 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4430 i.hle_prefix = current_templates->start->name;
4431 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4432 i.bnd_prefix = current_templates->start->name;
4434 i.rep_prefix = current_templates->start->name;
4440 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4447 if (!current_templates)
4449 /* Check if we should swap operand or force 32bit displacement in
4451 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4452 i.dir_encoding = dir_encoding_store;
4453 else if (mnem_p - 3 == dot_p
4456 i.disp_encoding = disp_encoding_8bit;
4457 else if (mnem_p - 4 == dot_p
4461 i.disp_encoding = disp_encoding_32bit;
4466 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4469 if (!current_templates)
4472 /* See if we can get a match by trimming off a suffix. */
4475 case WORD_MNEM_SUFFIX:
4476 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4477 i.suffix = SHORT_MNEM_SUFFIX;
4480 case BYTE_MNEM_SUFFIX:
4481 case QWORD_MNEM_SUFFIX:
4482 i.suffix = mnem_p[-1];
4484 current_templates = (const templates *) hash_find (op_hash,
4487 case SHORT_MNEM_SUFFIX:
4488 case LONG_MNEM_SUFFIX:
4491 i.suffix = mnem_p[-1];
4493 current_templates = (const templates *) hash_find (op_hash,
4502 if (intel_float_operand (mnemonic) == 1)
4503 i.suffix = SHORT_MNEM_SUFFIX;
4505 i.suffix = LONG_MNEM_SUFFIX;
4507 current_templates = (const templates *) hash_find (op_hash,
4512 if (!current_templates)
4514 as_bad (_("no such instruction: `%s'"), token_start);
4519 if (current_templates->start->opcode_modifier.jump
4520 || current_templates->start->opcode_modifier.jumpbyte)
4522 /* Check for a branch hint. We allow ",pt" and ",pn" for
4523 predict taken and predict not taken respectively.
4524 I'm not sure that branch hints actually do anything on loop
4525 and jcxz insns (JumpByte) for current Pentium4 chips. They
4526 may work in the future and it doesn't hurt to accept them
4528 if (l[0] == ',' && l[1] == 'p')
4532 if (!add_prefix (DS_PREFIX_OPCODE))
4536 else if (l[2] == 'n')
4538 if (!add_prefix (CS_PREFIX_OPCODE))
4544 /* Any other comma loses. */
4547 as_bad (_("invalid character %s in mnemonic"),
4548 output_invalid (*l));
4552 /* Check if instruction is supported on specified architecture. */
4554 for (t = current_templates->start; t < current_templates->end; ++t)
4556 supported |= cpu_flags_match (t);
4557 if (supported == CPU_FLAGS_PERFECT_MATCH)
4559 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4560 as_warn (_("use .code16 to ensure correct addressing mode"));
4566 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4567 as_bad (flag_code == CODE_64BIT
4568 ? _("`%s' is not supported in 64-bit mode")
4569 : _("`%s' is only supported in 64-bit mode"),
4570 current_templates->start->name);
4572 as_bad (_("`%s' is not supported on `%s%s'"),
4573 current_templates->start->name,
4574 cpu_arch_name ? cpu_arch_name : default_arch,
4575 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4581 parse_operands (char *l, const char *mnemonic)
4585 /* 1 if operand is pending after ','. */
4586 unsigned int expecting_operand = 0;
4588 /* Non-zero if operand parens not balanced. */
4589 unsigned int paren_not_balanced;
4591 while (*l != END_OF_INSN)
4593 /* Skip optional white space before operand. */
4594 if (is_space_char (*l))
4596 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4598 as_bad (_("invalid character %s before operand %d"),
4599 output_invalid (*l),
4603 token_start = l; /* After white space. */
4604 paren_not_balanced = 0;
4605 while (paren_not_balanced || *l != ',')
4607 if (*l == END_OF_INSN)
4609 if (paren_not_balanced)
4612 as_bad (_("unbalanced parenthesis in operand %d."),
4615 as_bad (_("unbalanced brackets in operand %d."),
4620 break; /* we are done */
4622 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4624 as_bad (_("invalid character %s in operand %d"),
4625 output_invalid (*l),
4632 ++paren_not_balanced;
4634 --paren_not_balanced;
4639 ++paren_not_balanced;
4641 --paren_not_balanced;
4645 if (l != token_start)
4646 { /* Yes, we've read in another operand. */
4647 unsigned int operand_ok;
4648 this_operand = i.operands++;
4649 if (i.operands > MAX_OPERANDS)
4651 as_bad (_("spurious operands; (%d operands/instruction max)"),
4655 i.types[this_operand].bitfield.unspecified = 1;
4656 /* Now parse operand adding info to 'i' as we go along. */
4657 END_STRING_AND_SAVE (l);
4661 i386_intel_operand (token_start,
4662 intel_float_operand (mnemonic));
4664 operand_ok = i386_att_operand (token_start);
4666 RESTORE_END_STRING (l);
4672 if (expecting_operand)
4674 expecting_operand_after_comma:
4675 as_bad (_("expecting operand after ','; got nothing"));
4680 as_bad (_("expecting operand before ','; got nothing"));
4685 /* Now *l must be either ',' or END_OF_INSN. */
4688 if (*++l == END_OF_INSN)
4690 /* Just skip it, if it's \n complain. */
4691 goto expecting_operand_after_comma;
4693 expecting_operand = 1;
4700 swap_2_operands (int xchg1, int xchg2)
4702 union i386_op temp_op;
4703 i386_operand_type temp_type;
4704 enum bfd_reloc_code_real temp_reloc;
4706 temp_type = i.types[xchg2];
4707 i.types[xchg2] = i.types[xchg1];
4708 i.types[xchg1] = temp_type;
4709 temp_op = i.op[xchg2];
4710 i.op[xchg2] = i.op[xchg1];
4711 i.op[xchg1] = temp_op;
4712 temp_reloc = i.reloc[xchg2];
4713 i.reloc[xchg2] = i.reloc[xchg1];
4714 i.reloc[xchg1] = temp_reloc;
4718 if (i.mask->operand == xchg1)
4719 i.mask->operand = xchg2;
4720 else if (i.mask->operand == xchg2)
4721 i.mask->operand = xchg1;
4725 if (i.broadcast->operand == xchg1)
4726 i.broadcast->operand = xchg2;
4727 else if (i.broadcast->operand == xchg2)
4728 i.broadcast->operand = xchg1;
4732 if (i.rounding->operand == xchg1)
4733 i.rounding->operand = xchg2;
4734 else if (i.rounding->operand == xchg2)
4735 i.rounding->operand = xchg1;
4740 swap_operands (void)
4746 swap_2_operands (1, i.operands - 2);
4750 swap_2_operands (0, i.operands - 1);
4756 if (i.mem_operands == 2)
4758 const seg_entry *temp_seg;
4759 temp_seg = i.seg[0];
4760 i.seg[0] = i.seg[1];
4761 i.seg[1] = temp_seg;
4765 /* Try to ensure constant immediates are represented in the smallest
4770 char guess_suffix = 0;
4774 guess_suffix = i.suffix;
4775 else if (i.reg_operands)
4777 /* Figure out a suffix from the last register operand specified.
4778 We can't do this properly yet, ie. excluding InOutPortReg,
4779 but the following works for instructions with immediates.
4780 In any case, we can't set i.suffix yet. */
4781 for (op = i.operands; --op >= 0;)
4782 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4784 guess_suffix = BYTE_MNEM_SUFFIX;
4787 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4789 guess_suffix = WORD_MNEM_SUFFIX;
4792 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4794 guess_suffix = LONG_MNEM_SUFFIX;
4797 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4799 guess_suffix = QWORD_MNEM_SUFFIX;
4803 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4804 guess_suffix = WORD_MNEM_SUFFIX;
4806 for (op = i.operands; --op >= 0;)
4807 if (operand_type_check (i.types[op], imm))
4809 switch (i.op[op].imms->X_op)
4812 /* If a suffix is given, this operand may be shortened. */
4813 switch (guess_suffix)
4815 case LONG_MNEM_SUFFIX:
4816 i.types[op].bitfield.imm32 = 1;
4817 i.types[op].bitfield.imm64 = 1;
4819 case WORD_MNEM_SUFFIX:
4820 i.types[op].bitfield.imm16 = 1;
4821 i.types[op].bitfield.imm32 = 1;
4822 i.types[op].bitfield.imm32s = 1;
4823 i.types[op].bitfield.imm64 = 1;
4825 case BYTE_MNEM_SUFFIX:
4826 i.types[op].bitfield.imm8 = 1;
4827 i.types[op].bitfield.imm8s = 1;
4828 i.types[op].bitfield.imm16 = 1;
4829 i.types[op].bitfield.imm32 = 1;
4830 i.types[op].bitfield.imm32s = 1;
4831 i.types[op].bitfield.imm64 = 1;
4835 /* If this operand is at most 16 bits, convert it
4836 to a signed 16 bit number before trying to see
4837 whether it will fit in an even smaller size.
4838 This allows a 16-bit operand such as $0xffe0 to
4839 be recognised as within Imm8S range. */
4840 if ((i.types[op].bitfield.imm16)
4841 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4843 i.op[op].imms->X_add_number =
4844 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4847 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4848 if ((i.types[op].bitfield.imm32)
4849 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4852 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4853 ^ ((offsetT) 1 << 31))
4854 - ((offsetT) 1 << 31));
4858 = operand_type_or (i.types[op],
4859 smallest_imm_type (i.op[op].imms->X_add_number));
4861 /* We must avoid matching of Imm32 templates when 64bit
4862 only immediate is available. */
4863 if (guess_suffix == QWORD_MNEM_SUFFIX)
4864 i.types[op].bitfield.imm32 = 0;
4871 /* Symbols and expressions. */
4873 /* Convert symbolic operand to proper sizes for matching, but don't
4874 prevent matching a set of insns that only supports sizes other
4875 than those matching the insn suffix. */
4877 i386_operand_type mask, allowed;
4878 const insn_template *t;
4880 operand_type_set (&mask, 0);
4881 operand_type_set (&allowed, 0);
4883 for (t = current_templates->start;
4884 t < current_templates->end;
4886 allowed = operand_type_or (allowed,
4887 t->operand_types[op]);
4888 switch (guess_suffix)
4890 case QWORD_MNEM_SUFFIX:
4891 mask.bitfield.imm64 = 1;
4892 mask.bitfield.imm32s = 1;
4894 case LONG_MNEM_SUFFIX:
4895 mask.bitfield.imm32 = 1;
4897 case WORD_MNEM_SUFFIX:
4898 mask.bitfield.imm16 = 1;
4900 case BYTE_MNEM_SUFFIX:
4901 mask.bitfield.imm8 = 1;
4906 allowed = operand_type_and (mask, allowed);
4907 if (!operand_type_all_zero (&allowed))
4908 i.types[op] = operand_type_and (i.types[op], mask);
4915 /* Try to use the smallest displacement type too. */
4917 optimize_disp (void)
4921 for (op = i.operands; --op >= 0;)
4922 if (operand_type_check (i.types[op], disp))
4924 if (i.op[op].disps->X_op == O_constant)
4926 offsetT op_disp = i.op[op].disps->X_add_number;
4928 if (i.types[op].bitfield.disp16
4929 && (op_disp & ~(offsetT) 0xffff) == 0)
4931 /* If this operand is at most 16 bits, convert
4932 to a signed 16 bit number and don't use 64bit
4934 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4935 i.types[op].bitfield.disp64 = 0;
4938 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4939 if (i.types[op].bitfield.disp32
4940 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4942 /* If this operand is at most 32 bits, convert
4943 to a signed 32 bit number and don't use 64bit
4945 op_disp &= (((offsetT) 2 << 31) - 1);
4946 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4947 i.types[op].bitfield.disp64 = 0;
4950 if (!op_disp && i.types[op].bitfield.baseindex)
4952 i.types[op].bitfield.disp8 = 0;
4953 i.types[op].bitfield.disp16 = 0;
4954 i.types[op].bitfield.disp32 = 0;
4955 i.types[op].bitfield.disp32s = 0;
4956 i.types[op].bitfield.disp64 = 0;
4960 else if (flag_code == CODE_64BIT)
4962 if (fits_in_signed_long (op_disp))
4964 i.types[op].bitfield.disp64 = 0;
4965 i.types[op].bitfield.disp32s = 1;
4967 if (i.prefix[ADDR_PREFIX]
4968 && fits_in_unsigned_long (op_disp))
4969 i.types[op].bitfield.disp32 = 1;
4971 if ((i.types[op].bitfield.disp32
4972 || i.types[op].bitfield.disp32s
4973 || i.types[op].bitfield.disp16)
4974 && fits_in_disp8 (op_disp))
4975 i.types[op].bitfield.disp8 = 1;
4977 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4978 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4980 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4981 i.op[op].disps, 0, i.reloc[op]);
4982 i.types[op].bitfield.disp8 = 0;
4983 i.types[op].bitfield.disp16 = 0;
4984 i.types[op].bitfield.disp32 = 0;
4985 i.types[op].bitfield.disp32s = 0;
4986 i.types[op].bitfield.disp64 = 0;
4989 /* We only support 64bit displacement on constants. */
4990 i.types[op].bitfield.disp64 = 0;
4994 /* Check if operands are valid for the instruction. */
4997 check_VecOperands (const insn_template *t)
5001 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5003 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5004 any one operand are implicity requiring AVX512VL support if the actual
5005 operand size is YMMword or XMMword. Since this function runs after
5006 template matching, there's no need to check for YMMword/XMMword in
5008 cpu = cpu_flags_and (t->cpu_flags, avx512);
5009 if (!cpu_flags_all_zero (&cpu)
5010 && !t->cpu_flags.bitfield.cpuavx512vl
5011 && !cpu_arch_flags.bitfield.cpuavx512vl)
5013 for (op = 0; op < t->operands; ++op)
5015 if (t->operand_types[op].bitfield.zmmword
5016 && (i.types[op].bitfield.ymmword
5017 || i.types[op].bitfield.xmmword))
5019 i.error = unsupported;
5025 /* Without VSIB byte, we can't have a vector register for index. */
5026 if (!t->opcode_modifier.vecsib
5028 && (i.index_reg->reg_type.bitfield.xmmword
5029 || i.index_reg->reg_type.bitfield.ymmword
5030 || i.index_reg->reg_type.bitfield.zmmword))
5032 i.error = unsupported_vector_index_register;
5036 /* Check if default mask is allowed. */
5037 if (t->opcode_modifier.nodefmask
5038 && (!i.mask || i.mask->mask->reg_num == 0))
5040 i.error = no_default_mask;
5044 /* For VSIB byte, we need a vector register for index, and all vector
5045 registers must be distinct. */
5046 if (t->opcode_modifier.vecsib)
5049 || !((t->opcode_modifier.vecsib == VecSIB128
5050 && i.index_reg->reg_type.bitfield.xmmword)
5051 || (t->opcode_modifier.vecsib == VecSIB256
5052 && i.index_reg->reg_type.bitfield.ymmword)
5053 || (t->opcode_modifier.vecsib == VecSIB512
5054 && i.index_reg->reg_type.bitfield.zmmword)))
5056 i.error = invalid_vsib_address;
5060 gas_assert (i.reg_operands == 2 || i.mask);
5061 if (i.reg_operands == 2 && !i.mask)
5063 gas_assert (i.types[0].bitfield.regsimd);
5064 gas_assert (i.types[0].bitfield.xmmword
5065 || i.types[0].bitfield.ymmword);
5066 gas_assert (i.types[2].bitfield.regsimd);
5067 gas_assert (i.types[2].bitfield.xmmword
5068 || i.types[2].bitfield.ymmword);
5069 if (operand_check == check_none)
5071 if (register_number (i.op[0].regs)
5072 != register_number (i.index_reg)
5073 && register_number (i.op[2].regs)
5074 != register_number (i.index_reg)
5075 && register_number (i.op[0].regs)
5076 != register_number (i.op[2].regs))
5078 if (operand_check == check_error)
5080 i.error = invalid_vector_register_set;
5083 as_warn (_("mask, index, and destination registers should be distinct"));
5085 else if (i.reg_operands == 1 && i.mask)
5087 if (i.types[1].bitfield.regsimd
5088 && (i.types[1].bitfield.xmmword
5089 || i.types[1].bitfield.ymmword
5090 || i.types[1].bitfield.zmmword)
5091 && (register_number (i.op[1].regs)
5092 == register_number (i.index_reg)))
5094 if (operand_check == check_error)
5096 i.error = invalid_vector_register_set;
5099 if (operand_check != check_none)
5100 as_warn (_("index and destination registers should be distinct"));
5105 /* Check if broadcast is supported by the instruction and is applied
5106 to the memory operand. */
5109 i386_operand_type type, overlap;
5111 /* Check if specified broadcast is supported in this instruction,
5112 and it's applied to memory operand of DWORD or QWORD type. */
5113 op = i.broadcast->operand;
5114 if (!t->opcode_modifier.broadcast
5115 || !i.types[op].bitfield.mem
5116 || (!i.types[op].bitfield.unspecified
5117 && (t->operand_types[op].bitfield.dword
5118 ? !i.types[op].bitfield.dword
5119 : !i.types[op].bitfield.qword)))
5122 i.error = unsupported_broadcast;
5126 operand_type_set (&type, 0);
5127 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5130 type.bitfield.qword = 1;
5133 type.bitfield.xmmword = 1;
5136 type.bitfield.ymmword = 1;
5139 type.bitfield.zmmword = 1;
5145 overlap = operand_type_and (type, t->operand_types[op]);
5146 if (operand_type_all_zero (&overlap))
5149 if (t->opcode_modifier.checkregsize)
5153 type.bitfield.baseindex = 1;
5154 for (j = 0; j < i.operands; ++j)
5157 && !operand_type_register_match(i.types[j],
5158 t->operand_types[j],
5160 t->operand_types[op]))
5165 /* If broadcast is supported in this instruction, we need to check if
5166 operand of one-element size isn't specified without broadcast. */
5167 else if (t->opcode_modifier.broadcast && i.mem_operands)
5169 /* Find memory operand. */
5170 for (op = 0; op < i.operands; op++)
5171 if (operand_type_check (i.types[op], anymem))
5173 gas_assert (op < i.operands);
5174 /* Check size of the memory operand. */
5175 if (t->operand_types[op].bitfield.dword
5176 ? i.types[op].bitfield.dword
5177 : i.types[op].bitfield.qword)
5179 i.error = broadcast_needed;
5184 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5186 /* Check if requested masking is supported. */
5188 && (!t->opcode_modifier.masking
5190 && t->opcode_modifier.masking == MERGING_MASKING)))
5192 i.error = unsupported_masking;
5196 /* Check if masking is applied to dest operand. */
5197 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5199 i.error = mask_not_on_destination;
5206 if ((i.rounding->type != saeonly
5207 && !t->opcode_modifier.staticrounding)
5208 || (i.rounding->type == saeonly
5209 && (t->opcode_modifier.staticrounding
5210 || !t->opcode_modifier.sae)))
5212 i.error = unsupported_rc_sae;
5215 /* If the instruction has several immediate operands and one of
5216 them is rounding, the rounding operand should be the last
5217 immediate operand. */
5218 if (i.imm_operands > 1
5219 && i.rounding->operand != (int) (i.imm_operands - 1))
5221 i.error = rc_sae_operand_not_last_imm;
5226 /* Check vector Disp8 operand. */
5227 if (t->opcode_modifier.disp8memshift
5228 && i.disp_encoding != disp_encoding_32bit)
5231 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5232 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5233 i.memshift = t->opcode_modifier.disp8memshift;
5236 const i386_operand_type *type = NULL;
5239 for (op = 0; op < i.operands; op++)
5240 if (operand_type_check (i.types[op], anymem))
5242 if (t->operand_types[op].bitfield.xmmword
5243 + t->operand_types[op].bitfield.ymmword
5244 + t->operand_types[op].bitfield.zmmword <= 1)
5245 type = &t->operand_types[op];
5246 else if (!i.types[op].bitfield.unspecified)
5247 type = &i.types[op];
5249 else if (i.types[op].bitfield.regsimd)
5251 if (i.types[op].bitfield.zmmword)
5253 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5255 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5261 if (type->bitfield.zmmword)
5263 else if (type->bitfield.ymmword)
5265 else if (type->bitfield.xmmword)
5269 /* For the check in fits_in_disp8(). */
5270 if (i.memshift == 0)
5274 for (op = 0; op < i.operands; op++)
5275 if (operand_type_check (i.types[op], disp)
5276 && i.op[op].disps->X_op == O_constant)
5278 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5280 i.types[op].bitfield.disp8 = 1;
5283 i.types[op].bitfield.disp8 = 0;
5292 /* Check if operands are valid for the instruction. Update VEX
5296 VEX_check_operands (const insn_template *t)
5298 if (i.vec_encoding == vex_encoding_evex)
5300 /* This instruction must be encoded with EVEX prefix. */
5301 if (!is_evex_encoding (t))
5303 i.error = unsupported;
5309 if (!t->opcode_modifier.vex)
5311 /* This instruction template doesn't have VEX prefix. */
5312 if (i.vec_encoding != vex_encoding_default)
5314 i.error = unsupported;
5320 /* Only check VEX_Imm4, which must be the first operand. */
5321 if (t->operand_types[0].bitfield.vec_imm4)
5323 if (i.op[0].imms->X_op != O_constant
5324 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5330 /* Turn off Imm8 so that update_imm won't complain. */
5331 i.types[0] = vec_imm4;
5337 static const insn_template *
5338 match_template (char mnem_suffix)
5340 /* Points to template once we've found it. */
5341 const insn_template *t;
5342 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5343 i386_operand_type overlap4;
5344 unsigned int found_reverse_match;
5345 i386_opcode_modifier suffix_check, mnemsuf_check;
5346 i386_operand_type operand_types [MAX_OPERANDS];
5347 int addr_prefix_disp;
5349 unsigned int found_cpu_match, size_match;
5350 unsigned int check_register;
5351 enum i386_error specific_error = 0;
5353 #if MAX_OPERANDS != 5
5354 # error "MAX_OPERANDS must be 5."
5357 found_reverse_match = 0;
5358 addr_prefix_disp = -1;
5360 memset (&suffix_check, 0, sizeof (suffix_check));
5361 if (intel_syntax && i.broadcast)
5363 else if (i.suffix == BYTE_MNEM_SUFFIX)
5364 suffix_check.no_bsuf = 1;
5365 else if (i.suffix == WORD_MNEM_SUFFIX)
5366 suffix_check.no_wsuf = 1;
5367 else if (i.suffix == SHORT_MNEM_SUFFIX)
5368 suffix_check.no_ssuf = 1;
5369 else if (i.suffix == LONG_MNEM_SUFFIX)
5370 suffix_check.no_lsuf = 1;
5371 else if (i.suffix == QWORD_MNEM_SUFFIX)
5372 suffix_check.no_qsuf = 1;
5373 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5374 suffix_check.no_ldsuf = 1;
5376 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5379 switch (mnem_suffix)
5381 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5382 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5383 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5384 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5385 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5389 /* Must have right number of operands. */
5390 i.error = number_of_operands_mismatch;
5392 for (t = current_templates->start; t < current_templates->end; t++)
5394 addr_prefix_disp = -1;
5396 if (i.operands != t->operands)
5399 /* Check processor support. */
5400 i.error = unsupported;
5401 found_cpu_match = (cpu_flags_match (t)
5402 == CPU_FLAGS_PERFECT_MATCH);
5403 if (!found_cpu_match)
5406 /* Check AT&T mnemonic. */
5407 i.error = unsupported_with_intel_mnemonic;
5408 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5411 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5412 i.error = unsupported_syntax;
5413 if ((intel_syntax && t->opcode_modifier.attsyntax)
5414 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5415 || (intel64 && t->opcode_modifier.amd64)
5416 || (!intel64 && t->opcode_modifier.intel64))
5419 /* Check the suffix, except for some instructions in intel mode. */
5420 i.error = invalid_instruction_suffix;
5421 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5422 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5423 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5424 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5425 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5426 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5427 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5429 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5430 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5431 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5432 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5433 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5434 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5435 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5438 size_match = operand_size_match (t);
5442 for (j = 0; j < MAX_OPERANDS; j++)
5443 operand_types[j] = t->operand_types[j];
5445 /* In general, don't allow 64-bit operands in 32-bit mode. */
5446 if (i.suffix == QWORD_MNEM_SUFFIX
5447 && flag_code != CODE_64BIT
5449 ? (!t->opcode_modifier.ignoresize
5450 && !t->opcode_modifier.broadcast
5451 && !intel_float_operand (t->name))
5452 : intel_float_operand (t->name) != 2)
5453 && ((!operand_types[0].bitfield.regmmx
5454 && !operand_types[0].bitfield.regsimd)
5455 || (!operand_types[t->operands > 1].bitfield.regmmx
5456 && !operand_types[t->operands > 1].bitfield.regsimd))
5457 && (t->base_opcode != 0x0fc7
5458 || t->extension_opcode != 1 /* cmpxchg8b */))
5461 /* In general, don't allow 32-bit operands on pre-386. */
5462 else if (i.suffix == LONG_MNEM_SUFFIX
5463 && !cpu_arch_flags.bitfield.cpui386
5465 ? (!t->opcode_modifier.ignoresize
5466 && !intel_float_operand (t->name))
5467 : intel_float_operand (t->name) != 2)
5468 && ((!operand_types[0].bitfield.regmmx
5469 && !operand_types[0].bitfield.regsimd)
5470 || (!operand_types[t->operands > 1].bitfield.regmmx
5471 && !operand_types[t->operands > 1].bitfield.regsimd)))
5474 /* Do not verify operands when there are none. */
5478 /* We've found a match; break out of loop. */
5482 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5483 into Disp32/Disp16/Disp32 operand. */
5484 if (i.prefix[ADDR_PREFIX] != 0)
5486 /* There should be only one Disp operand. */
5490 for (j = 0; j < MAX_OPERANDS; j++)
5492 if (operand_types[j].bitfield.disp16)
5494 addr_prefix_disp = j;
5495 operand_types[j].bitfield.disp32 = 1;
5496 operand_types[j].bitfield.disp16 = 0;
5502 for (j = 0; j < MAX_OPERANDS; j++)
5504 if (operand_types[j].bitfield.disp32)
5506 addr_prefix_disp = j;
5507 operand_types[j].bitfield.disp32 = 0;
5508 operand_types[j].bitfield.disp16 = 1;
5514 for (j = 0; j < MAX_OPERANDS; j++)
5516 if (operand_types[j].bitfield.disp64)
5518 addr_prefix_disp = j;
5519 operand_types[j].bitfield.disp64 = 0;
5520 operand_types[j].bitfield.disp32 = 1;
5528 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5529 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5532 /* We check register size if needed. */
5533 if (t->opcode_modifier.checkregsize)
5535 check_register = (1 << t->operands) - 1;
5537 check_register &= ~(1 << i.broadcast->operand);
5542 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5543 switch (t->operands)
5546 if (!operand_type_match (overlap0, i.types[0]))
5550 /* xchg %eax, %eax is a special case. It is an alias for nop
5551 only in 32bit mode and we can use opcode 0x90. In 64bit
5552 mode, we can't use 0x90 for xchg %eax, %eax since it should
5553 zero-extend %eax to %rax. */
5554 if (flag_code == CODE_64BIT
5555 && t->base_opcode == 0x90
5556 && operand_type_equal (&i.types [0], &acc32)
5557 && operand_type_equal (&i.types [1], &acc32))
5559 /* xrelease mov %eax, <disp> is another special case. It must not
5560 match the accumulator-only encoding of mov. */
5561 if (flag_code != CODE_64BIT
5563 && t->base_opcode == 0xa0
5564 && i.types[0].bitfield.acc
5565 && operand_type_check (i.types[1], anymem))
5567 if (!(size_match & MATCH_STRAIGHT))
5569 /* If we want store form, we reverse direction of operands. */
5570 if (i.dir_encoding == dir_encoding_store
5571 && t->opcode_modifier.d)
5576 /* If we want store form, we skip the current load. */
5577 if (i.dir_encoding == dir_encoding_store
5578 && i.mem_operands == 0
5579 && t->opcode_modifier.load)
5584 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5585 if (!operand_type_match (overlap0, i.types[0])
5586 || !operand_type_match (overlap1, i.types[1])
5587 || ((check_register & 3) == 3
5588 && !operand_type_register_match (i.types[0],
5593 /* Check if other direction is valid ... */
5594 if (!t->opcode_modifier.d)
5598 if (!(size_match & MATCH_REVERSE))
5600 /* Try reversing direction of operands. */
5601 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5602 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5603 if (!operand_type_match (overlap0, i.types[0])
5604 || !operand_type_match (overlap1, i.types[1])
5606 && !operand_type_register_match (i.types[0],
5611 /* Does not match either direction. */
5614 /* found_reverse_match holds which of D or FloatR
5616 if (!t->opcode_modifier.d)
5617 found_reverse_match = 0;
5618 else if (operand_types[0].bitfield.tbyte)
5619 found_reverse_match = Opcode_FloatD;
5621 found_reverse_match = Opcode_D;
5622 if (t->opcode_modifier.floatr)
5623 found_reverse_match |= Opcode_FloatR;
5627 /* Found a forward 2 operand match here. */
5628 switch (t->operands)
5631 overlap4 = operand_type_and (i.types[4],
5635 overlap3 = operand_type_and (i.types[3],
5639 overlap2 = operand_type_and (i.types[2],
5644 switch (t->operands)
5647 if (!operand_type_match (overlap4, i.types[4])
5648 || !operand_type_register_match (i.types[3],
5655 if (!operand_type_match (overlap3, i.types[3])
5656 || ((check_register & 0xa) == 0xa
5657 && !operand_type_register_match (i.types[1],
5661 || ((check_register & 0xc) == 0xc
5662 && !operand_type_register_match (i.types[2],
5669 /* Here we make use of the fact that there are no
5670 reverse match 3 operand instructions. */
5671 if (!operand_type_match (overlap2, i.types[2])
5672 || ((check_register & 5) == 5
5673 && !operand_type_register_match (i.types[0],
5677 || ((check_register & 6) == 6
5678 && !operand_type_register_match (i.types[1],
5686 /* Found either forward/reverse 2, 3 or 4 operand match here:
5687 slip through to break. */
5689 if (!found_cpu_match)
5691 found_reverse_match = 0;
5695 /* Check if vector and VEX operands are valid. */
5696 if (check_VecOperands (t) || VEX_check_operands (t))
5698 specific_error = i.error;
5702 /* We've found a match; break out of loop. */
5706 if (t == current_templates->end)
5708 /* We found no match. */
5709 const char *err_msg;
5710 switch (specific_error ? specific_error : i.error)
5714 case operand_size_mismatch:
5715 err_msg = _("operand size mismatch");
5717 case operand_type_mismatch:
5718 err_msg = _("operand type mismatch");
5720 case register_type_mismatch:
5721 err_msg = _("register type mismatch");
5723 case number_of_operands_mismatch:
5724 err_msg = _("number of operands mismatch");
5726 case invalid_instruction_suffix:
5727 err_msg = _("invalid instruction suffix");
5730 err_msg = _("constant doesn't fit in 4 bits");
5732 case unsupported_with_intel_mnemonic:
5733 err_msg = _("unsupported with Intel mnemonic");
5735 case unsupported_syntax:
5736 err_msg = _("unsupported syntax");
5739 as_bad (_("unsupported instruction `%s'"),
5740 current_templates->start->name);
5742 case invalid_vsib_address:
5743 err_msg = _("invalid VSIB address");
5745 case invalid_vector_register_set:
5746 err_msg = _("mask, index, and destination registers must be distinct");
5748 case unsupported_vector_index_register:
5749 err_msg = _("unsupported vector index register");
5751 case unsupported_broadcast:
5752 err_msg = _("unsupported broadcast");
5754 case broadcast_not_on_src_operand:
5755 err_msg = _("broadcast not on source memory operand");
5757 case broadcast_needed:
5758 err_msg = _("broadcast is needed for operand of such type");
5760 case unsupported_masking:
5761 err_msg = _("unsupported masking");
5763 case mask_not_on_destination:
5764 err_msg = _("mask not on destination operand");
5766 case no_default_mask:
5767 err_msg = _("default mask isn't allowed");
5769 case unsupported_rc_sae:
5770 err_msg = _("unsupported static rounding/sae");
5772 case rc_sae_operand_not_last_imm:
5774 err_msg = _("RC/SAE operand must precede immediate operands");
5776 err_msg = _("RC/SAE operand must follow immediate operands");
5778 case invalid_register_operand:
5779 err_msg = _("invalid register operand");
5782 as_bad (_("%s for `%s'"), err_msg,
5783 current_templates->start->name);
5787 if (!quiet_warnings)
5790 && (i.types[0].bitfield.jumpabsolute
5791 != operand_types[0].bitfield.jumpabsolute))
5793 as_warn (_("indirect %s without `*'"), t->name);
5796 if (t->opcode_modifier.isprefix
5797 && t->opcode_modifier.ignoresize)
5799 /* Warn them that a data or address size prefix doesn't
5800 affect assembly of the next line of code. */
5801 as_warn (_("stand-alone `%s' prefix"), t->name);
5805 /* Copy the template we found. */
5808 if (addr_prefix_disp != -1)
5809 i.tm.operand_types[addr_prefix_disp]
5810 = operand_types[addr_prefix_disp];
5812 if (found_reverse_match)
5814 /* If we found a reverse match we must alter the opcode
5815 direction bit. found_reverse_match holds bits to change
5816 (different for int & float insns). */
5818 i.tm.base_opcode ^= found_reverse_match;
5820 i.tm.operand_types[0] = operand_types[1];
5821 i.tm.operand_types[1] = operand_types[0];
5830 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5831 if (i.tm.operand_types[mem_op].bitfield.esseg)
5833 if (i.seg[0] != NULL && i.seg[0] != &es)
5835 as_bad (_("`%s' operand %d must use `%ses' segment"),
5841 /* There's only ever one segment override allowed per instruction.
5842 This instruction possibly has a legal segment override on the
5843 second operand, so copy the segment to where non-string
5844 instructions store it, allowing common code. */
5845 i.seg[0] = i.seg[1];
5847 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5849 if (i.seg[1] != NULL && i.seg[1] != &es)
5851 as_bad (_("`%s' operand %d must use `%ses' segment"),
5862 process_suffix (void)
5864 /* If matched instruction specifies an explicit instruction mnemonic
5866 if (i.tm.opcode_modifier.size16)
5867 i.suffix = WORD_MNEM_SUFFIX;
5868 else if (i.tm.opcode_modifier.size32)
5869 i.suffix = LONG_MNEM_SUFFIX;
5870 else if (i.tm.opcode_modifier.size64)
5871 i.suffix = QWORD_MNEM_SUFFIX;
5872 else if (i.reg_operands)
5874 /* If there's no instruction mnemonic suffix we try to invent one
5875 based on register operands. */
5878 /* We take i.suffix from the last register operand specified,
5879 Destination register type is more significant than source
5880 register type. crc32 in SSE4.2 prefers source register
5882 if (i.tm.base_opcode == 0xf20f38f1)
5884 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5885 i.suffix = WORD_MNEM_SUFFIX;
5886 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5887 i.suffix = LONG_MNEM_SUFFIX;
5888 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5889 i.suffix = QWORD_MNEM_SUFFIX;
5891 else if (i.tm.base_opcode == 0xf20f38f0)
5893 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5894 i.suffix = BYTE_MNEM_SUFFIX;
5901 if (i.tm.base_opcode == 0xf20f38f1
5902 || i.tm.base_opcode == 0xf20f38f0)
5904 /* We have to know the operand size for crc32. */
5905 as_bad (_("ambiguous memory operand size for `%s`"),
5910 for (op = i.operands; --op >= 0;)
5911 if (!i.tm.operand_types[op].bitfield.inoutportreg
5912 && !i.tm.operand_types[op].bitfield.shiftcount)
5914 if (!i.types[op].bitfield.reg)
5916 if (i.types[op].bitfield.byte)
5917 i.suffix = BYTE_MNEM_SUFFIX;
5918 else if (i.types[op].bitfield.word)
5919 i.suffix = WORD_MNEM_SUFFIX;
5920 else if (i.types[op].bitfield.dword)
5921 i.suffix = LONG_MNEM_SUFFIX;
5922 else if (i.types[op].bitfield.qword)
5923 i.suffix = QWORD_MNEM_SUFFIX;
5930 else if (i.suffix == BYTE_MNEM_SUFFIX)
5933 && i.tm.opcode_modifier.ignoresize
5934 && i.tm.opcode_modifier.no_bsuf)
5936 else if (!check_byte_reg ())
5939 else if (i.suffix == LONG_MNEM_SUFFIX)
5942 && i.tm.opcode_modifier.ignoresize
5943 && i.tm.opcode_modifier.no_lsuf
5944 && !i.tm.opcode_modifier.todword
5945 && !i.tm.opcode_modifier.toqword)
5947 else if (!check_long_reg ())
5950 else if (i.suffix == QWORD_MNEM_SUFFIX)
5953 && i.tm.opcode_modifier.ignoresize
5954 && i.tm.opcode_modifier.no_qsuf
5955 && !i.tm.opcode_modifier.todword
5956 && !i.tm.opcode_modifier.toqword)
5958 else if (!check_qword_reg ())
5961 else if (i.suffix == WORD_MNEM_SUFFIX)
5964 && i.tm.opcode_modifier.ignoresize
5965 && i.tm.opcode_modifier.no_wsuf)
5967 else if (!check_word_reg ())
5970 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5971 /* Do nothing if the instruction is going to ignore the prefix. */
5976 else if (i.tm.opcode_modifier.defaultsize
5978 /* exclude fldenv/frstor/fsave/fstenv */
5979 && i.tm.opcode_modifier.no_ssuf)
5981 i.suffix = stackop_size;
5983 else if (intel_syntax
5985 && (i.tm.operand_types[0].bitfield.jumpabsolute
5986 || i.tm.opcode_modifier.jumpbyte
5987 || i.tm.opcode_modifier.jumpintersegment
5988 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5989 && i.tm.extension_opcode <= 3)))
5994 if (!i.tm.opcode_modifier.no_qsuf)
5996 i.suffix = QWORD_MNEM_SUFFIX;
6001 if (!i.tm.opcode_modifier.no_lsuf)
6002 i.suffix = LONG_MNEM_SUFFIX;
6005 if (!i.tm.opcode_modifier.no_wsuf)
6006 i.suffix = WORD_MNEM_SUFFIX;
6015 if (i.tm.opcode_modifier.w)
6017 as_bad (_("no instruction mnemonic suffix given and "
6018 "no register operands; can't size instruction"));
6024 unsigned int suffixes;
6026 suffixes = !i.tm.opcode_modifier.no_bsuf;
6027 if (!i.tm.opcode_modifier.no_wsuf)
6029 if (!i.tm.opcode_modifier.no_lsuf)
6031 if (!i.tm.opcode_modifier.no_ldsuf)
6033 if (!i.tm.opcode_modifier.no_ssuf)
6035 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6038 /* There are more than suffix matches. */
6039 if (i.tm.opcode_modifier.w
6040 || ((suffixes & (suffixes - 1))
6041 && !i.tm.opcode_modifier.defaultsize
6042 && !i.tm.opcode_modifier.ignoresize))
6044 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6050 /* Change the opcode based on the operand size given by i.suffix. */
6053 /* Size floating point instruction. */
6054 case LONG_MNEM_SUFFIX:
6055 if (i.tm.opcode_modifier.floatmf)
6057 i.tm.base_opcode ^= 4;
6061 case WORD_MNEM_SUFFIX:
6062 case QWORD_MNEM_SUFFIX:
6063 /* It's not a byte, select word/dword operation. */
6064 if (i.tm.opcode_modifier.w)
6066 if (i.tm.opcode_modifier.shortform)
6067 i.tm.base_opcode |= 8;
6069 i.tm.base_opcode |= 1;
6072 case SHORT_MNEM_SUFFIX:
6073 /* Now select between word & dword operations via the operand
6074 size prefix, except for instructions that will ignore this
6076 if (i.reg_operands > 0
6077 && i.types[0].bitfield.reg
6078 && i.tm.opcode_modifier.addrprefixopreg
6079 && (i.tm.opcode_modifier.immext
6080 || i.operands == 1))
6082 /* The address size override prefix changes the size of the
6084 if ((flag_code == CODE_32BIT
6085 && i.op[0].regs->reg_type.bitfield.word)
6086 || (flag_code != CODE_32BIT
6087 && i.op[0].regs->reg_type.bitfield.dword))
6088 if (!add_prefix (ADDR_PREFIX_OPCODE))
6091 else if (i.suffix != QWORD_MNEM_SUFFIX
6092 && !i.tm.opcode_modifier.ignoresize
6093 && !i.tm.opcode_modifier.floatmf
6094 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6095 || (flag_code == CODE_64BIT
6096 && i.tm.opcode_modifier.jumpbyte)))
6098 unsigned int prefix = DATA_PREFIX_OPCODE;
6100 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6101 prefix = ADDR_PREFIX_OPCODE;
6103 if (!add_prefix (prefix))
6107 /* Set mode64 for an operand. */
6108 if (i.suffix == QWORD_MNEM_SUFFIX
6109 && flag_code == CODE_64BIT
6110 && !i.tm.opcode_modifier.norex64
6111 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6113 && ! (i.operands == 2
6114 && i.tm.base_opcode == 0x90
6115 && i.tm.extension_opcode == None
6116 && operand_type_equal (&i.types [0], &acc64)
6117 && operand_type_equal (&i.types [1], &acc64)))
6123 if (i.reg_operands != 0
6125 && i.tm.opcode_modifier.addrprefixopreg
6126 && !i.tm.opcode_modifier.immext)
6128 /* Check invalid register operand when the address size override
6129 prefix changes the size of register operands. */
6131 enum { need_word, need_dword, need_qword } need;
6133 if (flag_code == CODE_32BIT)
6134 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6137 if (i.prefix[ADDR_PREFIX])
6140 need = flag_code == CODE_64BIT ? need_qword : need_word;
6143 for (op = 0; op < i.operands; op++)
6144 if (i.types[op].bitfield.reg
6145 && ((need == need_word
6146 && !i.op[op].regs->reg_type.bitfield.word)
6147 || (need == need_dword
6148 && !i.op[op].regs->reg_type.bitfield.dword)
6149 || (need == need_qword
6150 && !i.op[op].regs->reg_type.bitfield.qword)))
6152 as_bad (_("invalid register operand size for `%s'"),
6162 check_byte_reg (void)
6166 for (op = i.operands; --op >= 0;)
6168 /* Skip non-register operands. */
6169 if (!i.types[op].bitfield.reg)
6172 /* If this is an eight bit register, it's OK. If it's the 16 or
6173 32 bit version of an eight bit register, we will just use the
6174 low portion, and that's OK too. */
6175 if (i.types[op].bitfield.byte)
6178 /* I/O port address operands are OK too. */
6179 if (i.tm.operand_types[op].bitfield.inoutportreg)
6182 /* crc32 doesn't generate this warning. */
6183 if (i.tm.base_opcode == 0xf20f38f0)
6186 if ((i.types[op].bitfield.word
6187 || i.types[op].bitfield.dword
6188 || i.types[op].bitfield.qword)
6189 && i.op[op].regs->reg_num < 4
6190 /* Prohibit these changes in 64bit mode, since the lowering
6191 would be more complicated. */
6192 && flag_code != CODE_64BIT)
6194 #if REGISTER_WARNINGS
6195 if (!quiet_warnings)
6196 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6198 (i.op[op].regs + (i.types[op].bitfield.word
6199 ? REGNAM_AL - REGNAM_AX
6200 : REGNAM_AL - REGNAM_EAX))->reg_name,
6202 i.op[op].regs->reg_name,
6207 /* Any other register is bad. */
6208 if (i.types[op].bitfield.reg
6209 || i.types[op].bitfield.regmmx
6210 || i.types[op].bitfield.regsimd
6211 || i.types[op].bitfield.sreg2
6212 || i.types[op].bitfield.sreg3
6213 || i.types[op].bitfield.control
6214 || i.types[op].bitfield.debug
6215 || i.types[op].bitfield.test)
6217 as_bad (_("`%s%s' not allowed with `%s%c'"),
6219 i.op[op].regs->reg_name,
6229 check_long_reg (void)
6233 for (op = i.operands; --op >= 0;)
6234 /* Skip non-register operands. */
6235 if (!i.types[op].bitfield.reg)
6237 /* Reject eight bit registers, except where the template requires
6238 them. (eg. movzb) */
6239 else if (i.types[op].bitfield.byte
6240 && (i.tm.operand_types[op].bitfield.reg
6241 || i.tm.operand_types[op].bitfield.acc)
6242 && (i.tm.operand_types[op].bitfield.word
6243 || i.tm.operand_types[op].bitfield.dword))
6245 as_bad (_("`%s%s' not allowed with `%s%c'"),
6247 i.op[op].regs->reg_name,
6252 /* Warn if the e prefix on a general reg is missing. */
6253 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6254 && i.types[op].bitfield.word
6255 && (i.tm.operand_types[op].bitfield.reg
6256 || i.tm.operand_types[op].bitfield.acc)
6257 && i.tm.operand_types[op].bitfield.dword)
6259 /* Prohibit these changes in the 64bit mode, since the
6260 lowering is more complicated. */
6261 if (flag_code == CODE_64BIT)
6263 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6264 register_prefix, i.op[op].regs->reg_name,
6268 #if REGISTER_WARNINGS
6269 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6271 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6272 register_prefix, i.op[op].regs->reg_name, i.suffix);
6275 /* Warn if the r prefix on a general reg is present. */
6276 else if (i.types[op].bitfield.qword
6277 && (i.tm.operand_types[op].bitfield.reg
6278 || i.tm.operand_types[op].bitfield.acc)
6279 && i.tm.operand_types[op].bitfield.dword)
6282 && i.tm.opcode_modifier.toqword
6283 && !i.types[0].bitfield.regsimd)
6285 /* Convert to QWORD. We want REX byte. */
6286 i.suffix = QWORD_MNEM_SUFFIX;
6290 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6291 register_prefix, i.op[op].regs->reg_name,
6300 check_qword_reg (void)
6304 for (op = i.operands; --op >= 0; )
6305 /* Skip non-register operands. */
6306 if (!i.types[op].bitfield.reg)
6308 /* Reject eight bit registers, except where the template requires
6309 them. (eg. movzb) */
6310 else if (i.types[op].bitfield.byte
6311 && (i.tm.operand_types[op].bitfield.reg
6312 || i.tm.operand_types[op].bitfield.acc)
6313 && (i.tm.operand_types[op].bitfield.word
6314 || i.tm.operand_types[op].bitfield.dword))
6316 as_bad (_("`%s%s' not allowed with `%s%c'"),
6318 i.op[op].regs->reg_name,
6323 /* Warn if the r prefix on a general reg is missing. */
6324 else if ((i.types[op].bitfield.word
6325 || i.types[op].bitfield.dword)
6326 && (i.tm.operand_types[op].bitfield.reg
6327 || i.tm.operand_types[op].bitfield.acc)
6328 && i.tm.operand_types[op].bitfield.qword)
6330 /* Prohibit these changes in the 64bit mode, since the
6331 lowering is more complicated. */
6333 && i.tm.opcode_modifier.todword
6334 && !i.types[0].bitfield.regsimd)
6336 /* Convert to DWORD. We don't want REX byte. */
6337 i.suffix = LONG_MNEM_SUFFIX;
6341 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6342 register_prefix, i.op[op].regs->reg_name,
6351 check_word_reg (void)
6354 for (op = i.operands; --op >= 0;)
6355 /* Skip non-register operands. */
6356 if (!i.types[op].bitfield.reg)
6358 /* Reject eight bit registers, except where the template requires
6359 them. (eg. movzb) */
6360 else if (i.types[op].bitfield.byte
6361 && (i.tm.operand_types[op].bitfield.reg
6362 || i.tm.operand_types[op].bitfield.acc)
6363 && (i.tm.operand_types[op].bitfield.word
6364 || i.tm.operand_types[op].bitfield.dword))
6366 as_bad (_("`%s%s' not allowed with `%s%c'"),
6368 i.op[op].regs->reg_name,
6373 /* Warn if the e or r prefix on a general reg is present. */
6374 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6375 && (i.types[op].bitfield.dword
6376 || i.types[op].bitfield.qword)
6377 && (i.tm.operand_types[op].bitfield.reg
6378 || i.tm.operand_types[op].bitfield.acc)
6379 && i.tm.operand_types[op].bitfield.word)
6381 /* Prohibit these changes in the 64bit mode, since the
6382 lowering is more complicated. */
6383 if (flag_code == CODE_64BIT)
6385 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6386 register_prefix, i.op[op].regs->reg_name,
6390 #if REGISTER_WARNINGS
6391 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6393 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6394 register_prefix, i.op[op].regs->reg_name, i.suffix);
6401 update_imm (unsigned int j)
6403 i386_operand_type overlap = i.types[j];
6404 if ((overlap.bitfield.imm8
6405 || overlap.bitfield.imm8s
6406 || overlap.bitfield.imm16
6407 || overlap.bitfield.imm32
6408 || overlap.bitfield.imm32s
6409 || overlap.bitfield.imm64)
6410 && !operand_type_equal (&overlap, &imm8)
6411 && !operand_type_equal (&overlap, &imm8s)
6412 && !operand_type_equal (&overlap, &imm16)
6413 && !operand_type_equal (&overlap, &imm32)
6414 && !operand_type_equal (&overlap, &imm32s)
6415 && !operand_type_equal (&overlap, &imm64))
6419 i386_operand_type temp;
6421 operand_type_set (&temp, 0);
6422 if (i.suffix == BYTE_MNEM_SUFFIX)
6424 temp.bitfield.imm8 = overlap.bitfield.imm8;
6425 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6427 else if (i.suffix == WORD_MNEM_SUFFIX)
6428 temp.bitfield.imm16 = overlap.bitfield.imm16;
6429 else if (i.suffix == QWORD_MNEM_SUFFIX)
6431 temp.bitfield.imm64 = overlap.bitfield.imm64;
6432 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6435 temp.bitfield.imm32 = overlap.bitfield.imm32;
6438 else if (operand_type_equal (&overlap, &imm16_32_32s)
6439 || operand_type_equal (&overlap, &imm16_32)
6440 || operand_type_equal (&overlap, &imm16_32s))
6442 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6447 if (!operand_type_equal (&overlap, &imm8)
6448 && !operand_type_equal (&overlap, &imm8s)
6449 && !operand_type_equal (&overlap, &imm16)
6450 && !operand_type_equal (&overlap, &imm32)
6451 && !operand_type_equal (&overlap, &imm32s)
6452 && !operand_type_equal (&overlap, &imm64))
6454 as_bad (_("no instruction mnemonic suffix given; "
6455 "can't determine immediate size"));
6459 i.types[j] = overlap;
6469 /* Update the first 2 immediate operands. */
6470 n = i.operands > 2 ? 2 : i.operands;
6473 for (j = 0; j < n; j++)
6474 if (update_imm (j) == 0)
6477 /* The 3rd operand can't be immediate operand. */
6478 gas_assert (operand_type_check (i.types[2], imm) == 0);
6485 process_operands (void)
6487 /* Default segment register this instruction will use for memory
6488 accesses. 0 means unknown. This is only for optimizing out
6489 unnecessary segment overrides. */
6490 const seg_entry *default_seg = 0;
6492 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6494 unsigned int dupl = i.operands;
6495 unsigned int dest = dupl - 1;
6498 /* The destination must be an xmm register. */
6499 gas_assert (i.reg_operands
6500 && MAX_OPERANDS > dupl
6501 && operand_type_equal (&i.types[dest], ®xmm));
6503 if (i.tm.operand_types[0].bitfield.acc
6504 && i.tm.operand_types[0].bitfield.xmmword)
6506 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6508 /* Keep xmm0 for instructions with VEX prefix and 3
6510 i.tm.operand_types[0].bitfield.acc = 0;
6511 i.tm.operand_types[0].bitfield.regsimd = 1;
6516 /* We remove the first xmm0 and keep the number of
6517 operands unchanged, which in fact duplicates the
6519 for (j = 1; j < i.operands; j++)
6521 i.op[j - 1] = i.op[j];
6522 i.types[j - 1] = i.types[j];
6523 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6527 else if (i.tm.opcode_modifier.implicit1stxmm0)
6529 gas_assert ((MAX_OPERANDS - 1) > dupl
6530 && (i.tm.opcode_modifier.vexsources
6533 /* Add the implicit xmm0 for instructions with VEX prefix
6535 for (j = i.operands; j > 0; j--)
6537 i.op[j] = i.op[j - 1];
6538 i.types[j] = i.types[j - 1];
6539 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6542 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6543 i.types[0] = regxmm;
6544 i.tm.operand_types[0] = regxmm;
6547 i.reg_operands += 2;
6552 i.op[dupl] = i.op[dest];
6553 i.types[dupl] = i.types[dest];
6554 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6563 i.op[dupl] = i.op[dest];
6564 i.types[dupl] = i.types[dest];
6565 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6568 if (i.tm.opcode_modifier.immext)
6571 else if (i.tm.operand_types[0].bitfield.acc
6572 && i.tm.operand_types[0].bitfield.xmmword)
6576 for (j = 1; j < i.operands; j++)
6578 i.op[j - 1] = i.op[j];
6579 i.types[j - 1] = i.types[j];
6581 /* We need to adjust fields in i.tm since they are used by
6582 build_modrm_byte. */
6583 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6590 else if (i.tm.opcode_modifier.implicitquadgroup)
6592 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6594 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6595 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6596 regnum = register_number (i.op[1].regs);
6597 first_reg_in_group = regnum & ~3;
6598 last_reg_in_group = first_reg_in_group + 3;
6599 if (regnum != first_reg_in_group)
6600 as_warn (_("source register `%s%s' implicitly denotes"
6601 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6602 register_prefix, i.op[1].regs->reg_name,
6603 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6604 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6607 else if (i.tm.opcode_modifier.regkludge)
6609 /* The imul $imm, %reg instruction is converted into
6610 imul $imm, %reg, %reg, and the clr %reg instruction
6611 is converted into xor %reg, %reg. */
6613 unsigned int first_reg_op;
6615 if (operand_type_check (i.types[0], reg))
6619 /* Pretend we saw the extra register operand. */
6620 gas_assert (i.reg_operands == 1
6621 && i.op[first_reg_op + 1].regs == 0);
6622 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6623 i.types[first_reg_op + 1] = i.types[first_reg_op];
6628 if (i.tm.opcode_modifier.shortform)
6630 if (i.types[0].bitfield.sreg2
6631 || i.types[0].bitfield.sreg3)
6633 if (i.tm.base_opcode == POP_SEG_SHORT
6634 && i.op[0].regs->reg_num == 1)
6636 as_bad (_("you can't `pop %scs'"), register_prefix);
6639 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6640 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6645 /* The register or float register operand is in operand
6649 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6650 || operand_type_check (i.types[0], reg))
6654 /* Register goes in low 3 bits of opcode. */
6655 i.tm.base_opcode |= i.op[op].regs->reg_num;
6656 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6658 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6660 /* Warn about some common errors, but press on regardless.
6661 The first case can be generated by gcc (<= 2.8.1). */
6662 if (i.operands == 2)
6664 /* Reversed arguments on faddp, fsubp, etc. */
6665 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6666 register_prefix, i.op[!intel_syntax].regs->reg_name,
6667 register_prefix, i.op[intel_syntax].regs->reg_name);
6671 /* Extraneous `l' suffix on fp insn. */
6672 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6673 register_prefix, i.op[0].regs->reg_name);
6678 else if (i.tm.opcode_modifier.modrm)
6680 /* The opcode is completed (modulo i.tm.extension_opcode which
6681 must be put into the modrm byte). Now, we make the modrm and
6682 index base bytes based on all the info we've collected. */
6684 default_seg = build_modrm_byte ();
6686 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6690 else if (i.tm.opcode_modifier.isstring)
6692 /* For the string instructions that allow a segment override
6693 on one of their operands, the default segment is ds. */
6697 if (i.tm.base_opcode == 0x8d /* lea */
6700 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6702 /* If a segment was explicitly specified, and the specified segment
6703 is not the default, use an opcode prefix to select it. If we
6704 never figured out what the default segment is, then default_seg
6705 will be zero at this point, and the specified segment prefix will
6707 if ((i.seg[0]) && (i.seg[0] != default_seg))
6709 if (!add_prefix (i.seg[0]->seg_prefix))
6715 static const seg_entry *
6716 build_modrm_byte (void)
6718 const seg_entry *default_seg = 0;
6719 unsigned int source, dest;
6722 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6725 unsigned int nds, reg_slot;
6728 dest = i.operands - 1;
6731 /* There are 2 kinds of instructions:
6732 1. 5 operands: 4 register operands or 3 register operands
6733 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6734 VexW0 or VexW1. The destination must be either XMM, YMM or
6736 2. 4 operands: 4 register operands or 3 register operands
6737 plus 1 memory operand, with VexXDS. */
6738 gas_assert ((i.reg_operands == 4
6739 || (i.reg_operands == 3 && i.mem_operands == 1))
6740 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6741 && i.tm.opcode_modifier.vexw
6742 && i.tm.operand_types[dest].bitfield.regsimd);
6744 /* If VexW1 is set, the first non-immediate operand is the source and
6745 the second non-immediate one is encoded in the immediate operand. */
6746 if (i.tm.opcode_modifier.vexw == VEXW1)
6748 source = i.imm_operands;
6749 reg_slot = i.imm_operands + 1;
6753 source = i.imm_operands + 1;
6754 reg_slot = i.imm_operands;
6757 if (i.imm_operands == 0)
6759 /* When there is no immediate operand, generate an 8bit
6760 immediate operand to encode the first operand. */
6761 exp = &im_expressions[i.imm_operands++];
6762 i.op[i.operands].imms = exp;
6763 i.types[i.operands] = imm8;
6766 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6767 exp->X_op = O_constant;
6768 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6769 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6773 unsigned int imm_slot;
6775 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6777 if (i.tm.opcode_modifier.immext)
6779 /* When ImmExt is set, the immediate byte is the last
6781 imm_slot = i.operands - 1;
6789 /* Turn on Imm8 so that output_imm will generate it. */
6790 i.types[imm_slot].bitfield.imm8 = 1;
6793 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6794 i.op[imm_slot].imms->X_add_number
6795 |= register_number (i.op[reg_slot].regs) << 4;
6796 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6799 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6800 i.vex.register_specifier = i.op[nds].regs;
6805 /* i.reg_operands MUST be the number of real register operands;
6806 implicit registers do not count. If there are 3 register
6807 operands, it must be a instruction with VexNDS. For a
6808 instruction with VexNDD, the destination register is encoded
6809 in VEX prefix. If there are 4 register operands, it must be
6810 a instruction with VEX prefix and 3 sources. */
6811 if (i.mem_operands == 0
6812 && ((i.reg_operands == 2
6813 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6814 || (i.reg_operands == 3
6815 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6816 || (i.reg_operands == 4 && vex_3_sources)))
6824 /* When there are 3 operands, one of them may be immediate,
6825 which may be the first or the last operand. Otherwise,
6826 the first operand must be shift count register (cl) or it
6827 is an instruction with VexNDS. */
6828 gas_assert (i.imm_operands == 1
6829 || (i.imm_operands == 0
6830 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6831 || i.types[0].bitfield.shiftcount)));
6832 if (operand_type_check (i.types[0], imm)
6833 || i.types[0].bitfield.shiftcount)
6839 /* When there are 4 operands, the first two must be 8bit
6840 immediate operands. The source operand will be the 3rd
6843 For instructions with VexNDS, if the first operand
6844 an imm8, the source operand is the 2nd one. If the last
6845 operand is imm8, the source operand is the first one. */
6846 gas_assert ((i.imm_operands == 2
6847 && i.types[0].bitfield.imm8
6848 && i.types[1].bitfield.imm8)
6849 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6850 && i.imm_operands == 1
6851 && (i.types[0].bitfield.imm8
6852 || i.types[i.operands - 1].bitfield.imm8
6854 if (i.imm_operands == 2)
6858 if (i.types[0].bitfield.imm8)
6865 if (is_evex_encoding (&i.tm))
6867 /* For EVEX instructions, when there are 5 operands, the
6868 first one must be immediate operand. If the second one
6869 is immediate operand, the source operand is the 3th
6870 one. If the last one is immediate operand, the source
6871 operand is the 2nd one. */
6872 gas_assert (i.imm_operands == 2
6873 && i.tm.opcode_modifier.sae
6874 && operand_type_check (i.types[0], imm));
6875 if (operand_type_check (i.types[1], imm))
6877 else if (operand_type_check (i.types[4], imm))
6891 /* RC/SAE operand could be between DEST and SRC. That happens
6892 when one operand is GPR and the other one is XMM/YMM/ZMM
6894 if (i.rounding && i.rounding->operand == (int) dest)
6897 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6899 /* For instructions with VexNDS, the register-only source
6900 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6901 register. It is encoded in VEX prefix. We need to
6902 clear RegMem bit before calling operand_type_equal. */
6904 i386_operand_type op;
6907 /* Check register-only source operand when two source
6908 operands are swapped. */
6909 if (!i.tm.operand_types[source].bitfield.baseindex
6910 && i.tm.operand_types[dest].bitfield.baseindex)
6918 op = i.tm.operand_types[vvvv];
6919 op.bitfield.regmem = 0;
6920 if ((dest + 1) >= i.operands
6921 || ((!op.bitfield.reg
6922 || (!op.bitfield.dword && !op.bitfield.qword))
6923 && !op.bitfield.regsimd
6924 && !operand_type_equal (&op, ®mask)))
6926 i.vex.register_specifier = i.op[vvvv].regs;
6932 /* One of the register operands will be encoded in the i.tm.reg
6933 field, the other in the combined i.tm.mode and i.tm.regmem
6934 fields. If no form of this instruction supports a memory
6935 destination operand, then we assume the source operand may
6936 sometimes be a memory operand and so we need to store the
6937 destination in the i.rm.reg field. */
6938 if (!i.tm.operand_types[dest].bitfield.regmem
6939 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6941 i.rm.reg = i.op[dest].regs->reg_num;
6942 i.rm.regmem = i.op[source].regs->reg_num;
6943 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6945 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6947 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6949 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6954 i.rm.reg = i.op[source].regs->reg_num;
6955 i.rm.regmem = i.op[dest].regs->reg_num;
6956 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6958 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6960 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6962 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6965 if (flag_code != CODE_64BIT && (i.rex & REX_R))
6967 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
6970 add_prefix (LOCK_PREFIX_OPCODE);
6974 { /* If it's not 2 reg operands... */
6979 unsigned int fake_zero_displacement = 0;
6982 for (op = 0; op < i.operands; op++)
6983 if (operand_type_check (i.types[op], anymem))
6985 gas_assert (op < i.operands);
6987 if (i.tm.opcode_modifier.vecsib)
6989 if (i.index_reg->reg_num == RegEiz
6990 || i.index_reg->reg_num == RegRiz)
6993 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6996 i.sib.base = NO_BASE_REGISTER;
6997 i.sib.scale = i.log2_scale_factor;
6998 i.types[op].bitfield.disp8 = 0;
6999 i.types[op].bitfield.disp16 = 0;
7000 i.types[op].bitfield.disp64 = 0;
7001 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7003 /* Must be 32 bit */
7004 i.types[op].bitfield.disp32 = 1;
7005 i.types[op].bitfield.disp32s = 0;
7009 i.types[op].bitfield.disp32 = 0;
7010 i.types[op].bitfield.disp32s = 1;
7013 i.sib.index = i.index_reg->reg_num;
7014 if ((i.index_reg->reg_flags & RegRex) != 0)
7016 if ((i.index_reg->reg_flags & RegVRex) != 0)
7022 if (i.base_reg == 0)
7025 if (!i.disp_operands)
7026 fake_zero_displacement = 1;
7027 if (i.index_reg == 0)
7029 i386_operand_type newdisp;
7031 gas_assert (!i.tm.opcode_modifier.vecsib);
7032 /* Operand is just <disp> */
7033 if (flag_code == CODE_64BIT)
7035 /* 64bit mode overwrites the 32bit absolute
7036 addressing by RIP relative addressing and
7037 absolute addressing is encoded by one of the
7038 redundant SIB forms. */
7039 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7040 i.sib.base = NO_BASE_REGISTER;
7041 i.sib.index = NO_INDEX_REGISTER;
7042 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7044 else if ((flag_code == CODE_16BIT)
7045 ^ (i.prefix[ADDR_PREFIX] != 0))
7047 i.rm.regmem = NO_BASE_REGISTER_16;
7052 i.rm.regmem = NO_BASE_REGISTER;
7055 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7056 i.types[op] = operand_type_or (i.types[op], newdisp);
7058 else if (!i.tm.opcode_modifier.vecsib)
7060 /* !i.base_reg && i.index_reg */
7061 if (i.index_reg->reg_num == RegEiz
7062 || i.index_reg->reg_num == RegRiz)
7063 i.sib.index = NO_INDEX_REGISTER;
7065 i.sib.index = i.index_reg->reg_num;
7066 i.sib.base = NO_BASE_REGISTER;
7067 i.sib.scale = i.log2_scale_factor;
7068 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7069 i.types[op].bitfield.disp8 = 0;
7070 i.types[op].bitfield.disp16 = 0;
7071 i.types[op].bitfield.disp64 = 0;
7072 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7074 /* Must be 32 bit */
7075 i.types[op].bitfield.disp32 = 1;
7076 i.types[op].bitfield.disp32s = 0;
7080 i.types[op].bitfield.disp32 = 0;
7081 i.types[op].bitfield.disp32s = 1;
7083 if ((i.index_reg->reg_flags & RegRex) != 0)
7087 /* RIP addressing for 64bit mode. */
7088 else if (i.base_reg->reg_num == RegRip ||
7089 i.base_reg->reg_num == RegEip)
7091 gas_assert (!i.tm.opcode_modifier.vecsib);
7092 i.rm.regmem = NO_BASE_REGISTER;
7093 i.types[op].bitfield.disp8 = 0;
7094 i.types[op].bitfield.disp16 = 0;
7095 i.types[op].bitfield.disp32 = 0;
7096 i.types[op].bitfield.disp32s = 1;
7097 i.types[op].bitfield.disp64 = 0;
7098 i.flags[op] |= Operand_PCrel;
7099 if (! i.disp_operands)
7100 fake_zero_displacement = 1;
7102 else if (i.base_reg->reg_type.bitfield.word)
7104 gas_assert (!i.tm.opcode_modifier.vecsib);
7105 switch (i.base_reg->reg_num)
7108 if (i.index_reg == 0)
7110 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7111 i.rm.regmem = i.index_reg->reg_num - 6;
7115 if (i.index_reg == 0)
7118 if (operand_type_check (i.types[op], disp) == 0)
7120 /* fake (%bp) into 0(%bp) */
7121 i.types[op].bitfield.disp8 = 1;
7122 fake_zero_displacement = 1;
7125 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7126 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7128 default: /* (%si) -> 4 or (%di) -> 5 */
7129 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7131 i.rm.mode = mode_from_disp_size (i.types[op]);
7133 else /* i.base_reg and 32/64 bit mode */
7135 if (flag_code == CODE_64BIT
7136 && operand_type_check (i.types[op], disp))
7138 i.types[op].bitfield.disp16 = 0;
7139 i.types[op].bitfield.disp64 = 0;
7140 if (i.prefix[ADDR_PREFIX] == 0)
7142 i.types[op].bitfield.disp32 = 0;
7143 i.types[op].bitfield.disp32s = 1;
7147 i.types[op].bitfield.disp32 = 1;
7148 i.types[op].bitfield.disp32s = 0;
7152 if (!i.tm.opcode_modifier.vecsib)
7153 i.rm.regmem = i.base_reg->reg_num;
7154 if ((i.base_reg->reg_flags & RegRex) != 0)
7156 i.sib.base = i.base_reg->reg_num;
7157 /* x86-64 ignores REX prefix bit here to avoid decoder
7159 if (!(i.base_reg->reg_flags & RegRex)
7160 && (i.base_reg->reg_num == EBP_REG_NUM
7161 || i.base_reg->reg_num == ESP_REG_NUM))
7163 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7165 fake_zero_displacement = 1;
7166 i.types[op].bitfield.disp8 = 1;
7168 i.sib.scale = i.log2_scale_factor;
7169 if (i.index_reg == 0)
7171 gas_assert (!i.tm.opcode_modifier.vecsib);
7172 /* <disp>(%esp) becomes two byte modrm with no index
7173 register. We've already stored the code for esp
7174 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7175 Any base register besides %esp will not use the
7176 extra modrm byte. */
7177 i.sib.index = NO_INDEX_REGISTER;
7179 else if (!i.tm.opcode_modifier.vecsib)
7181 if (i.index_reg->reg_num == RegEiz
7182 || i.index_reg->reg_num == RegRiz)
7183 i.sib.index = NO_INDEX_REGISTER;
7185 i.sib.index = i.index_reg->reg_num;
7186 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7187 if ((i.index_reg->reg_flags & RegRex) != 0)
7192 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7193 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7197 if (!fake_zero_displacement
7201 fake_zero_displacement = 1;
7202 if (i.disp_encoding == disp_encoding_8bit)
7203 i.types[op].bitfield.disp8 = 1;
7205 i.types[op].bitfield.disp32 = 1;
7207 i.rm.mode = mode_from_disp_size (i.types[op]);
7211 if (fake_zero_displacement)
7213 /* Fakes a zero displacement assuming that i.types[op]
7214 holds the correct displacement size. */
7217 gas_assert (i.op[op].disps == 0);
7218 exp = &disp_expressions[i.disp_operands++];
7219 i.op[op].disps = exp;
7220 exp->X_op = O_constant;
7221 exp->X_add_number = 0;
7222 exp->X_add_symbol = (symbolS *) 0;
7223 exp->X_op_symbol = (symbolS *) 0;
7231 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7233 if (operand_type_check (i.types[0], imm))
7234 i.vex.register_specifier = NULL;
7237 /* VEX.vvvv encodes one of the sources when the first
7238 operand is not an immediate. */
7239 if (i.tm.opcode_modifier.vexw == VEXW0)
7240 i.vex.register_specifier = i.op[0].regs;
7242 i.vex.register_specifier = i.op[1].regs;
7245 /* Destination is a XMM register encoded in the ModRM.reg
7247 i.rm.reg = i.op[2].regs->reg_num;
7248 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7251 /* ModRM.rm and VEX.B encodes the other source. */
7252 if (!i.mem_operands)
7256 if (i.tm.opcode_modifier.vexw == VEXW0)
7257 i.rm.regmem = i.op[1].regs->reg_num;
7259 i.rm.regmem = i.op[0].regs->reg_num;
7261 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7265 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7267 i.vex.register_specifier = i.op[2].regs;
7268 if (!i.mem_operands)
7271 i.rm.regmem = i.op[1].regs->reg_num;
7272 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7276 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7277 (if any) based on i.tm.extension_opcode. Again, we must be
7278 careful to make sure that segment/control/debug/test/MMX
7279 registers are coded into the i.rm.reg field. */
7280 else if (i.reg_operands)
7283 unsigned int vex_reg = ~0;
7285 for (op = 0; op < i.operands; op++)
7286 if (i.types[op].bitfield.reg
7287 || i.types[op].bitfield.regmmx
7288 || i.types[op].bitfield.regsimd
7289 || i.types[op].bitfield.regbnd
7290 || i.types[op].bitfield.regmask
7291 || i.types[op].bitfield.sreg2
7292 || i.types[op].bitfield.sreg3
7293 || i.types[op].bitfield.control
7294 || i.types[op].bitfield.debug
7295 || i.types[op].bitfield.test)
7300 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7302 /* For instructions with VexNDS, the register-only
7303 source operand is encoded in VEX prefix. */
7304 gas_assert (mem != (unsigned int) ~0);
7309 gas_assert (op < i.operands);
7313 /* Check register-only source operand when two source
7314 operands are swapped. */
7315 if (!i.tm.operand_types[op].bitfield.baseindex
7316 && i.tm.operand_types[op + 1].bitfield.baseindex)
7320 gas_assert (mem == (vex_reg + 1)
7321 && op < i.operands);
7326 gas_assert (vex_reg < i.operands);
7330 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7332 /* For instructions with VexNDD, the register destination
7333 is encoded in VEX prefix. */
7334 if (i.mem_operands == 0)
7336 /* There is no memory operand. */
7337 gas_assert ((op + 2) == i.operands);
7342 /* There are only 2 non-immediate operands. */
7343 gas_assert (op < i.imm_operands + 2
7344 && i.operands == i.imm_operands + 2);
7345 vex_reg = i.imm_operands + 1;
7349 gas_assert (op < i.operands);
7351 if (vex_reg != (unsigned int) ~0)
7353 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7355 if ((!type->bitfield.reg
7356 || (!type->bitfield.dword && !type->bitfield.qword))
7357 && !type->bitfield.regsimd
7358 && !operand_type_equal (type, ®mask))
7361 i.vex.register_specifier = i.op[vex_reg].regs;
7364 /* Don't set OP operand twice. */
7367 /* If there is an extension opcode to put here, the
7368 register number must be put into the regmem field. */
7369 if (i.tm.extension_opcode != None)
7371 i.rm.regmem = i.op[op].regs->reg_num;
7372 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7374 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7379 i.rm.reg = i.op[op].regs->reg_num;
7380 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7382 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7387 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7388 must set it to 3 to indicate this is a register operand
7389 in the regmem field. */
7390 if (!i.mem_operands)
7394 /* Fill in i.rm.reg field with extension opcode (if any). */
7395 if (i.tm.extension_opcode != None)
7396 i.rm.reg = i.tm.extension_opcode;
7402 output_branch (void)
7408 relax_substateT subtype;
7412 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7413 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7416 if (i.prefix[DATA_PREFIX] != 0)
7422 /* Pentium4 branch hints. */
7423 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7424 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7429 if (i.prefix[REX_PREFIX] != 0)
7435 /* BND prefixed jump. */
7436 if (i.prefix[BND_PREFIX] != 0)
7438 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7442 if (i.prefixes != 0 && !intel_syntax)
7443 as_warn (_("skipping prefixes on this instruction"));
7445 /* It's always a symbol; End frag & setup for relax.
7446 Make sure there is enough room in this frag for the largest
7447 instruction we may generate in md_convert_frag. This is 2
7448 bytes for the opcode and room for the prefix and largest
7450 frag_grow (prefix + 2 + 4);
7451 /* Prefix and 1 opcode byte go in fr_fix. */
7452 p = frag_more (prefix + 1);
7453 if (i.prefix[DATA_PREFIX] != 0)
7454 *p++ = DATA_PREFIX_OPCODE;
7455 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7456 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7457 *p++ = i.prefix[SEG_PREFIX];
7458 if (i.prefix[REX_PREFIX] != 0)
7459 *p++ = i.prefix[REX_PREFIX];
7460 *p = i.tm.base_opcode;
7462 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7463 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7464 else if (cpu_arch_flags.bitfield.cpui386)
7465 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7467 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7470 sym = i.op[0].disps->X_add_symbol;
7471 off = i.op[0].disps->X_add_number;
7473 if (i.op[0].disps->X_op != O_constant
7474 && i.op[0].disps->X_op != O_symbol)
7476 /* Handle complex expressions. */
7477 sym = make_expr_symbol (i.op[0].disps);
7481 /* 1 possible extra opcode + 4 byte displacement go in var part.
7482 Pass reloc in fr_var. */
7483 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7486 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7487 /* Return TRUE iff PLT32 relocation should be used for branching to
7491 need_plt32_p (symbolS *s)
7493 /* PLT32 relocation is ELF only. */
7497 /* Since there is no need to prepare for PLT branch on x86-64, we
7498 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7499 be used as a marker for 32-bit PC-relative branches. */
7503 /* Weak or undefined symbol need PLT32 relocation. */
7504 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7507 /* Non-global symbol doesn't need PLT32 relocation. */
7508 if (! S_IS_EXTERNAL (s))
7511 /* Other global symbols need PLT32 relocation. NB: Symbol with
7512 non-default visibilities are treated as normal global symbol
7513 so that PLT32 relocation can be used as a marker for 32-bit
7514 PC-relative branches. It is useful for linker relaxation. */
7525 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7527 if (i.tm.opcode_modifier.jumpbyte)
7529 /* This is a loop or jecxz type instruction. */
7531 if (i.prefix[ADDR_PREFIX] != 0)
7533 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7536 /* Pentium4 branch hints. */
7537 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7538 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7540 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7549 if (flag_code == CODE_16BIT)
7552 if (i.prefix[DATA_PREFIX] != 0)
7554 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7564 if (i.prefix[REX_PREFIX] != 0)
7566 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7570 /* BND prefixed jump. */
7571 if (i.prefix[BND_PREFIX] != 0)
7573 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7577 if (i.prefixes != 0 && !intel_syntax)
7578 as_warn (_("skipping prefixes on this instruction"));
7580 p = frag_more (i.tm.opcode_length + size);
7581 switch (i.tm.opcode_length)
7584 *p++ = i.tm.base_opcode >> 8;
7587 *p++ = i.tm.base_opcode;
7593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7595 && jump_reloc == NO_RELOC
7596 && need_plt32_p (i.op[0].disps->X_add_symbol))
7597 jump_reloc = BFD_RELOC_X86_64_PLT32;
7600 jump_reloc = reloc (size, 1, 1, jump_reloc);
7602 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7603 i.op[0].disps, 1, jump_reloc);
7605 /* All jumps handled here are signed, but don't use a signed limit
7606 check for 32 and 16 bit jumps as we want to allow wrap around at
7607 4G and 64k respectively. */
7609 fixP->fx_signed = 1;
7613 output_interseg_jump (void)
7621 if (flag_code == CODE_16BIT)
7625 if (i.prefix[DATA_PREFIX] != 0)
7631 if (i.prefix[REX_PREFIX] != 0)
7641 if (i.prefixes != 0 && !intel_syntax)
7642 as_warn (_("skipping prefixes on this instruction"));
7644 /* 1 opcode; 2 segment; offset */
7645 p = frag_more (prefix + 1 + 2 + size);
7647 if (i.prefix[DATA_PREFIX] != 0)
7648 *p++ = DATA_PREFIX_OPCODE;
7650 if (i.prefix[REX_PREFIX] != 0)
7651 *p++ = i.prefix[REX_PREFIX];
7653 *p++ = i.tm.base_opcode;
7654 if (i.op[1].imms->X_op == O_constant)
7656 offsetT n = i.op[1].imms->X_add_number;
7659 && !fits_in_unsigned_word (n)
7660 && !fits_in_signed_word (n))
7662 as_bad (_("16-bit jump out of range"));
7665 md_number_to_chars (p, n, size);
7668 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7669 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7670 if (i.op[0].imms->X_op != O_constant)
7671 as_bad (_("can't handle non absolute segment in `%s'"),
7673 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7679 fragS *insn_start_frag;
7680 offsetT insn_start_off;
7682 /* Tie dwarf2 debug info to the address at the start of the insn.
7683 We can't do this after the insn has been output as the current
7684 frag may have been closed off. eg. by frag_var. */
7685 dwarf2_emit_insn (0);
7687 insn_start_frag = frag_now;
7688 insn_start_off = frag_now_fix ();
7691 if (i.tm.opcode_modifier.jump)
7693 else if (i.tm.opcode_modifier.jumpbyte
7694 || i.tm.opcode_modifier.jumpdword)
7696 else if (i.tm.opcode_modifier.jumpintersegment)
7697 output_interseg_jump ();
7700 /* Output normal instructions here. */
7704 unsigned int prefix;
7707 && i.tm.base_opcode == 0xfae
7709 && i.imm_operands == 1
7710 && (i.op[0].imms->X_add_number == 0xe8
7711 || i.op[0].imms->X_add_number == 0xf0
7712 || i.op[0].imms->X_add_number == 0xf8))
7714 /* Encode lfence, mfence, and sfence as
7715 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7716 offsetT val = 0x240483f0ULL;
7718 md_number_to_chars (p, val, 5);
7722 /* Some processors fail on LOCK prefix. This options makes
7723 assembler ignore LOCK prefix and serves as a workaround. */
7724 if (omit_lock_prefix)
7726 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7728 i.prefix[LOCK_PREFIX] = 0;
7731 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7732 don't need the explicit prefix. */
7733 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7735 switch (i.tm.opcode_length)
7738 if (i.tm.base_opcode & 0xff000000)
7740 prefix = (i.tm.base_opcode >> 24) & 0xff;
7741 add_prefix (prefix);
7745 if ((i.tm.base_opcode & 0xff0000) != 0)
7747 prefix = (i.tm.base_opcode >> 16) & 0xff;
7748 if (!i.tm.cpu_flags.bitfield.cpupadlock
7749 || prefix != REPE_PREFIX_OPCODE
7750 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7751 add_prefix (prefix);
7757 /* Check for pseudo prefixes. */
7758 as_bad_where (insn_start_frag->fr_file,
7759 insn_start_frag->fr_line,
7760 _("pseudo prefix without instruction"));
7766 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7767 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7768 R_X86_64_GOTTPOFF relocation so that linker can safely
7769 perform IE->LE optimization. */
7770 if (x86_elf_abi == X86_64_X32_ABI
7772 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7773 && i.prefix[REX_PREFIX] == 0)
7774 add_prefix (REX_OPCODE);
7777 /* The prefix bytes. */
7778 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7780 FRAG_APPEND_1_CHAR (*q);
7784 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7789 /* REX byte is encoded in VEX prefix. */
7793 FRAG_APPEND_1_CHAR (*q);
7796 /* There should be no other prefixes for instructions
7801 /* For EVEX instructions i.vrex should become 0 after
7802 build_evex_prefix. For VEX instructions upper 16 registers
7803 aren't available, so VREX should be 0. */
7806 /* Now the VEX prefix. */
7807 p = frag_more (i.vex.length);
7808 for (j = 0; j < i.vex.length; j++)
7809 p[j] = i.vex.bytes[j];
7812 /* Now the opcode; be careful about word order here! */
7813 if (i.tm.opcode_length == 1)
7815 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7819 switch (i.tm.opcode_length)
7823 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7824 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7828 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7838 /* Put out high byte first: can't use md_number_to_chars! */
7839 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7840 *p = i.tm.base_opcode & 0xff;
7843 /* Now the modrm byte and sib byte (if present). */
7844 if (i.tm.opcode_modifier.modrm)
7846 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7849 /* If i.rm.regmem == ESP (4)
7850 && i.rm.mode != (Register mode)
7852 ==> need second modrm byte. */
7853 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7855 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7856 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7858 | i.sib.scale << 6));
7861 if (i.disp_operands)
7862 output_disp (insn_start_frag, insn_start_off);
7865 output_imm (insn_start_frag, insn_start_off);
7871 pi ("" /*line*/, &i);
7873 #endif /* DEBUG386 */
7876 /* Return the size of the displacement operand N. */
7879 disp_size (unsigned int n)
7883 if (i.types[n].bitfield.disp64)
7885 else if (i.types[n].bitfield.disp8)
7887 else if (i.types[n].bitfield.disp16)
7892 /* Return the size of the immediate operand N. */
7895 imm_size (unsigned int n)
7898 if (i.types[n].bitfield.imm64)
7900 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7902 else if (i.types[n].bitfield.imm16)
7908 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7913 for (n = 0; n < i.operands; n++)
7915 if (operand_type_check (i.types[n], disp))
7917 if (i.op[n].disps->X_op == O_constant)
7919 int size = disp_size (n);
7920 offsetT val = i.op[n].disps->X_add_number;
7922 val = offset_in_range (val >> i.memshift, size);
7923 p = frag_more (size);
7924 md_number_to_chars (p, val, size);
7928 enum bfd_reloc_code_real reloc_type;
7929 int size = disp_size (n);
7930 int sign = i.types[n].bitfield.disp32s;
7931 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7934 /* We can't have 8 bit displacement here. */
7935 gas_assert (!i.types[n].bitfield.disp8);
7937 /* The PC relative address is computed relative
7938 to the instruction boundary, so in case immediate
7939 fields follows, we need to adjust the value. */
7940 if (pcrel && i.imm_operands)
7945 for (n1 = 0; n1 < i.operands; n1++)
7946 if (operand_type_check (i.types[n1], imm))
7948 /* Only one immediate is allowed for PC
7949 relative address. */
7950 gas_assert (sz == 0);
7952 i.op[n].disps->X_add_number -= sz;
7954 /* We should find the immediate. */
7955 gas_assert (sz != 0);
7958 p = frag_more (size);
7959 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7961 && GOT_symbol == i.op[n].disps->X_add_symbol
7962 && (((reloc_type == BFD_RELOC_32
7963 || reloc_type == BFD_RELOC_X86_64_32S
7964 || (reloc_type == BFD_RELOC_64
7966 && (i.op[n].disps->X_op == O_symbol
7967 || (i.op[n].disps->X_op == O_add
7968 && ((symbol_get_value_expression
7969 (i.op[n].disps->X_op_symbol)->X_op)
7971 || reloc_type == BFD_RELOC_32_PCREL))
7975 if (insn_start_frag == frag_now)
7976 add = (p - frag_now->fr_literal) - insn_start_off;
7981 add = insn_start_frag->fr_fix - insn_start_off;
7982 for (fr = insn_start_frag->fr_next;
7983 fr && fr != frag_now; fr = fr->fr_next)
7985 add += p - frag_now->fr_literal;
7990 reloc_type = BFD_RELOC_386_GOTPC;
7991 i.op[n].imms->X_add_number += add;
7993 else if (reloc_type == BFD_RELOC_64)
7994 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7996 /* Don't do the adjustment for x86-64, as there
7997 the pcrel addressing is relative to the _next_
7998 insn, and that is taken care of in other code. */
7999 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8001 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8002 size, i.op[n].disps, pcrel,
8004 /* Check for "call/jmp *mem", "mov mem, %reg",
8005 "test %reg, mem" and "binop mem, %reg" where binop
8006 is one of adc, add, and, cmp, or, sbb, sub, xor
8007 instructions. Always generate R_386_GOT32X for
8008 "sym*GOT" operand in 32-bit mode. */
8009 if ((generate_relax_relocations
8012 && i.rm.regmem == 5))
8014 || (i.rm.mode == 0 && i.rm.regmem == 5))
8015 && ((i.operands == 1
8016 && i.tm.base_opcode == 0xff
8017 && (i.rm.reg == 2 || i.rm.reg == 4))
8019 && (i.tm.base_opcode == 0x8b
8020 || i.tm.base_opcode == 0x85
8021 || (i.tm.base_opcode & 0xc7) == 0x03))))
8025 fixP->fx_tcbit = i.rex != 0;
8027 && (i.base_reg->reg_num == RegRip
8028 || i.base_reg->reg_num == RegEip))
8029 fixP->fx_tcbit2 = 1;
8032 fixP->fx_tcbit2 = 1;
8040 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8045 for (n = 0; n < i.operands; n++)
8047 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8048 if (i.rounding && (int) n == i.rounding->operand)
8051 if (operand_type_check (i.types[n], imm))
8053 if (i.op[n].imms->X_op == O_constant)
8055 int size = imm_size (n);
8058 val = offset_in_range (i.op[n].imms->X_add_number,
8060 p = frag_more (size);
8061 md_number_to_chars (p, val, size);
8065 /* Not absolute_section.
8066 Need a 32-bit fixup (don't support 8bit
8067 non-absolute imms). Try to support other
8069 enum bfd_reloc_code_real reloc_type;
8070 int size = imm_size (n);
8073 if (i.types[n].bitfield.imm32s
8074 && (i.suffix == QWORD_MNEM_SUFFIX
8075 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8080 p = frag_more (size);
8081 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8083 /* This is tough to explain. We end up with this one if we
8084 * have operands that look like
8085 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8086 * obtain the absolute address of the GOT, and it is strongly
8087 * preferable from a performance point of view to avoid using
8088 * a runtime relocation for this. The actual sequence of
8089 * instructions often look something like:
8094 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8096 * The call and pop essentially return the absolute address
8097 * of the label .L66 and store it in %ebx. The linker itself
8098 * will ultimately change the first operand of the addl so
8099 * that %ebx points to the GOT, but to keep things simple, the
8100 * .o file must have this operand set so that it generates not
8101 * the absolute address of .L66, but the absolute address of
8102 * itself. This allows the linker itself simply treat a GOTPC
8103 * relocation as asking for a pcrel offset to the GOT to be
8104 * added in, and the addend of the relocation is stored in the
8105 * operand field for the instruction itself.
8107 * Our job here is to fix the operand so that it would add
8108 * the correct offset so that %ebx would point to itself. The
8109 * thing that is tricky is that .-.L66 will point to the
8110 * beginning of the instruction, so we need to further modify
8111 * the operand so that it will point to itself. There are
8112 * other cases where you have something like:
8114 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8116 * and here no correction would be required. Internally in
8117 * the assembler we treat operands of this form as not being
8118 * pcrel since the '.' is explicitly mentioned, and I wonder
8119 * whether it would simplify matters to do it this way. Who
8120 * knows. In earlier versions of the PIC patches, the
8121 * pcrel_adjust field was used to store the correction, but
8122 * since the expression is not pcrel, I felt it would be
8123 * confusing to do it this way. */
8125 if ((reloc_type == BFD_RELOC_32
8126 || reloc_type == BFD_RELOC_X86_64_32S
8127 || reloc_type == BFD_RELOC_64)
8129 && GOT_symbol == i.op[n].imms->X_add_symbol
8130 && (i.op[n].imms->X_op == O_symbol
8131 || (i.op[n].imms->X_op == O_add
8132 && ((symbol_get_value_expression
8133 (i.op[n].imms->X_op_symbol)->X_op)
8138 if (insn_start_frag == frag_now)
8139 add = (p - frag_now->fr_literal) - insn_start_off;
8144 add = insn_start_frag->fr_fix - insn_start_off;
8145 for (fr = insn_start_frag->fr_next;
8146 fr && fr != frag_now; fr = fr->fr_next)
8148 add += p - frag_now->fr_literal;
8152 reloc_type = BFD_RELOC_386_GOTPC;
8154 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8156 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8157 i.op[n].imms->X_add_number += add;
8159 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8160 i.op[n].imms, 0, reloc_type);
8166 /* x86_cons_fix_new is called via the expression parsing code when a
8167 reloc is needed. We use this hook to get the correct .got reloc. */
8168 static int cons_sign = -1;
8171 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8172 expressionS *exp, bfd_reloc_code_real_type r)
8174 r = reloc (len, 0, cons_sign, r);
8177 if (exp->X_op == O_secrel)
8179 exp->X_op = O_symbol;
8180 r = BFD_RELOC_32_SECREL;
8184 fix_new_exp (frag, off, len, exp, 0, r);
8187 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8188 purpose of the `.dc.a' internal pseudo-op. */
8191 x86_address_bytes (void)
8193 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8195 return stdoutput->arch_info->bits_per_address / 8;
8198 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8200 # define lex_got(reloc, adjust, types) NULL
8202 /* Parse operands of the form
8203 <symbol>@GOTOFF+<nnn>
8204 and similar .plt or .got references.
8206 If we find one, set up the correct relocation in RELOC and copy the
8207 input string, minus the `@GOTOFF' into a malloc'd buffer for
8208 parsing by the calling routine. Return this buffer, and if ADJUST
8209 is non-null set it to the length of the string we removed from the
8210 input line. Otherwise return NULL. */
8212 lex_got (enum bfd_reloc_code_real *rel,
8214 i386_operand_type *types)
8216 /* Some of the relocations depend on the size of what field is to
8217 be relocated. But in our callers i386_immediate and i386_displacement
8218 we don't yet know the operand size (this will be set by insn
8219 matching). Hence we record the word32 relocation here,
8220 and adjust the reloc according to the real size in reloc(). */
8221 static const struct {
8224 const enum bfd_reloc_code_real rel[2];
8225 const i386_operand_type types64;
8227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8228 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8230 OPERAND_TYPE_IMM32_64 },
8232 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8233 BFD_RELOC_X86_64_PLTOFF64 },
8234 OPERAND_TYPE_IMM64 },
8235 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8236 BFD_RELOC_X86_64_PLT32 },
8237 OPERAND_TYPE_IMM32_32S_DISP32 },
8238 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8239 BFD_RELOC_X86_64_GOTPLT64 },
8240 OPERAND_TYPE_IMM64_DISP64 },
8241 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8242 BFD_RELOC_X86_64_GOTOFF64 },
8243 OPERAND_TYPE_IMM64_DISP64 },
8244 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8245 BFD_RELOC_X86_64_GOTPCREL },
8246 OPERAND_TYPE_IMM32_32S_DISP32 },
8247 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8248 BFD_RELOC_X86_64_TLSGD },
8249 OPERAND_TYPE_IMM32_32S_DISP32 },
8250 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8251 _dummy_first_bfd_reloc_code_real },
8252 OPERAND_TYPE_NONE },
8253 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8254 BFD_RELOC_X86_64_TLSLD },
8255 OPERAND_TYPE_IMM32_32S_DISP32 },
8256 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8257 BFD_RELOC_X86_64_GOTTPOFF },
8258 OPERAND_TYPE_IMM32_32S_DISP32 },
8259 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8260 BFD_RELOC_X86_64_TPOFF32 },
8261 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8262 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8263 _dummy_first_bfd_reloc_code_real },
8264 OPERAND_TYPE_NONE },
8265 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8266 BFD_RELOC_X86_64_DTPOFF32 },
8267 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8268 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8269 _dummy_first_bfd_reloc_code_real },
8270 OPERAND_TYPE_NONE },
8271 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8272 _dummy_first_bfd_reloc_code_real },
8273 OPERAND_TYPE_NONE },
8274 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8275 BFD_RELOC_X86_64_GOT32 },
8276 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8277 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8278 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8279 OPERAND_TYPE_IMM32_32S_DISP32 },
8280 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8281 BFD_RELOC_X86_64_TLSDESC_CALL },
8282 OPERAND_TYPE_IMM32_32S_DISP32 },
8287 #if defined (OBJ_MAYBE_ELF)
8292 for (cp = input_line_pointer; *cp != '@'; cp++)
8293 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8296 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8298 int len = gotrel[j].len;
8299 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8301 if (gotrel[j].rel[object_64bit] != 0)
8304 char *tmpbuf, *past_reloc;
8306 *rel = gotrel[j].rel[object_64bit];
8310 if (flag_code != CODE_64BIT)
8312 types->bitfield.imm32 = 1;
8313 types->bitfield.disp32 = 1;
8316 *types = gotrel[j].types64;
8319 if (j != 0 && GOT_symbol == NULL)
8320 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8322 /* The length of the first part of our input line. */
8323 first = cp - input_line_pointer;
8325 /* The second part goes from after the reloc token until
8326 (and including) an end_of_line char or comma. */
8327 past_reloc = cp + 1 + len;
8329 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8331 second = cp + 1 - past_reloc;
8333 /* Allocate and copy string. The trailing NUL shouldn't
8334 be necessary, but be safe. */
8335 tmpbuf = XNEWVEC (char, first + second + 2);
8336 memcpy (tmpbuf, input_line_pointer, first);
8337 if (second != 0 && *past_reloc != ' ')
8338 /* Replace the relocation token with ' ', so that
8339 errors like foo@GOTOFF1 will be detected. */
8340 tmpbuf[first++] = ' ';
8342 /* Increment length by 1 if the relocation token is
8347 memcpy (tmpbuf + first, past_reloc, second);
8348 tmpbuf[first + second] = '\0';
8352 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8353 gotrel[j].str, 1 << (5 + object_64bit));
8358 /* Might be a symbol version string. Don't as_bad here. */
8367 /* Parse operands of the form
8368 <symbol>@SECREL32+<nnn>
8370 If we find one, set up the correct relocation in RELOC and copy the
8371 input string, minus the `@SECREL32' into a malloc'd buffer for
8372 parsing by the calling routine. Return this buffer, and if ADJUST
8373 is non-null set it to the length of the string we removed from the
8374 input line. Otherwise return NULL.
8376 This function is copied from the ELF version above adjusted for PE targets. */
8379 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8380 int *adjust ATTRIBUTE_UNUSED,
8381 i386_operand_type *types)
8387 const enum bfd_reloc_code_real rel[2];
8388 const i386_operand_type types64;
8392 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8393 BFD_RELOC_32_SECREL },
8394 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8400 for (cp = input_line_pointer; *cp != '@'; cp++)
8401 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8404 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8406 int len = gotrel[j].len;
8408 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8410 if (gotrel[j].rel[object_64bit] != 0)
8413 char *tmpbuf, *past_reloc;
8415 *rel = gotrel[j].rel[object_64bit];
8421 if (flag_code != CODE_64BIT)
8423 types->bitfield.imm32 = 1;
8424 types->bitfield.disp32 = 1;
8427 *types = gotrel[j].types64;
8430 /* The length of the first part of our input line. */
8431 first = cp - input_line_pointer;
8433 /* The second part goes from after the reloc token until
8434 (and including) an end_of_line char or comma. */
8435 past_reloc = cp + 1 + len;
8437 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8439 second = cp + 1 - past_reloc;
8441 /* Allocate and copy string. The trailing NUL shouldn't
8442 be necessary, but be safe. */
8443 tmpbuf = XNEWVEC (char, first + second + 2);
8444 memcpy (tmpbuf, input_line_pointer, first);
8445 if (second != 0 && *past_reloc != ' ')
8446 /* Replace the relocation token with ' ', so that
8447 errors like foo@SECLREL321 will be detected. */
8448 tmpbuf[first++] = ' ';
8449 memcpy (tmpbuf + first, past_reloc, second);
8450 tmpbuf[first + second] = '\0';
8454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8455 gotrel[j].str, 1 << (5 + object_64bit));
8460 /* Might be a symbol version string. Don't as_bad here. */
8466 bfd_reloc_code_real_type
8467 x86_cons (expressionS *exp, int size)
8469 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8471 intel_syntax = -intel_syntax;
8474 if (size == 4 || (object_64bit && size == 8))
8476 /* Handle @GOTOFF and the like in an expression. */
8478 char *gotfree_input_line;
8481 save = input_line_pointer;
8482 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8483 if (gotfree_input_line)
8484 input_line_pointer = gotfree_input_line;
8488 if (gotfree_input_line)
8490 /* expression () has merrily parsed up to the end of line,
8491 or a comma - in the wrong buffer. Transfer how far
8492 input_line_pointer has moved to the right buffer. */
8493 input_line_pointer = (save
8494 + (input_line_pointer - gotfree_input_line)
8496 free (gotfree_input_line);
8497 if (exp->X_op == O_constant
8498 || exp->X_op == O_absent
8499 || exp->X_op == O_illegal
8500 || exp->X_op == O_register
8501 || exp->X_op == O_big)
8503 char c = *input_line_pointer;
8504 *input_line_pointer = 0;
8505 as_bad (_("missing or invalid expression `%s'"), save);
8506 *input_line_pointer = c;
8513 intel_syntax = -intel_syntax;
8516 i386_intel_simplify (exp);
8522 signed_cons (int size)
8524 if (flag_code == CODE_64BIT)
8532 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8539 if (exp.X_op == O_symbol)
8540 exp.X_op = O_secrel;
8542 emit_expr (&exp, 4);
8544 while (*input_line_pointer++ == ',');
8546 input_line_pointer--;
8547 demand_empty_rest_of_line ();
8551 /* Handle Vector operations. */
8554 check_VecOperations (char *op_string, char *op_end)
8556 const reg_entry *mask;
8561 && (op_end == NULL || op_string < op_end))
8564 if (*op_string == '{')
8568 /* Check broadcasts. */
8569 if (strncmp (op_string, "1to", 3) == 0)
8574 goto duplicated_vec_op;
8577 if (*op_string == '8')
8579 else if (*op_string == '4')
8581 else if (*op_string == '2')
8583 else if (*op_string == '1'
8584 && *(op_string+1) == '6')
8591 as_bad (_("Unsupported broadcast: `%s'"), saved);
8596 broadcast_op.type = bcst_type;
8597 broadcast_op.operand = this_operand;
8598 i.broadcast = &broadcast_op;
8600 /* Check masking operation. */
8601 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8603 /* k0 can't be used for write mask. */
8604 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8606 as_bad (_("`%s%s' can't be used for write mask"),
8607 register_prefix, mask->reg_name);
8613 mask_op.mask = mask;
8614 mask_op.zeroing = 0;
8615 mask_op.operand = this_operand;
8621 goto duplicated_vec_op;
8623 i.mask->mask = mask;
8625 /* Only "{z}" is allowed here. No need to check
8626 zeroing mask explicitly. */
8627 if (i.mask->operand != this_operand)
8629 as_bad (_("invalid write mask `%s'"), saved);
8636 /* Check zeroing-flag for masking operation. */
8637 else if (*op_string == 'z')
8641 mask_op.mask = NULL;
8642 mask_op.zeroing = 1;
8643 mask_op.operand = this_operand;
8648 if (i.mask->zeroing)
8651 as_bad (_("duplicated `%s'"), saved);
8655 i.mask->zeroing = 1;
8657 /* Only "{%k}" is allowed here. No need to check mask
8658 register explicitly. */
8659 if (i.mask->operand != this_operand)
8661 as_bad (_("invalid zeroing-masking `%s'"),
8670 goto unknown_vec_op;
8672 if (*op_string != '}')
8674 as_bad (_("missing `}' in `%s'"), saved);
8679 /* Strip whitespace since the addition of pseudo prefixes
8680 changed how the scrubber treats '{'. */
8681 if (is_space_char (*op_string))
8687 /* We don't know this one. */
8688 as_bad (_("unknown vector operation: `%s'"), saved);
8692 if (i.mask && i.mask->zeroing && !i.mask->mask)
8694 as_bad (_("zeroing-masking only allowed with write mask"));
8702 i386_immediate (char *imm_start)
8704 char *save_input_line_pointer;
8705 char *gotfree_input_line;
8708 i386_operand_type types;
8710 operand_type_set (&types, ~0);
8712 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8714 as_bad (_("at most %d immediate operands are allowed"),
8715 MAX_IMMEDIATE_OPERANDS);
8719 exp = &im_expressions[i.imm_operands++];
8720 i.op[this_operand].imms = exp;
8722 if (is_space_char (*imm_start))
8725 save_input_line_pointer = input_line_pointer;
8726 input_line_pointer = imm_start;
8728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8729 if (gotfree_input_line)
8730 input_line_pointer = gotfree_input_line;
8732 exp_seg = expression (exp);
8736 /* Handle vector operations. */
8737 if (*input_line_pointer == '{')
8739 input_line_pointer = check_VecOperations (input_line_pointer,
8741 if (input_line_pointer == NULL)
8745 if (*input_line_pointer)
8746 as_bad (_("junk `%s' after expression"), input_line_pointer);
8748 input_line_pointer = save_input_line_pointer;
8749 if (gotfree_input_line)
8751 free (gotfree_input_line);
8753 if (exp->X_op == O_constant || exp->X_op == O_register)
8754 exp->X_op = O_illegal;
8757 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8761 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8762 i386_operand_type types, const char *imm_start)
8764 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8767 as_bad (_("missing or invalid immediate expression `%s'"),
8771 else if (exp->X_op == O_constant)
8773 /* Size it properly later. */
8774 i.types[this_operand].bitfield.imm64 = 1;
8775 /* If not 64bit, sign extend val. */
8776 if (flag_code != CODE_64BIT
8777 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8779 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8781 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8782 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8783 && exp_seg != absolute_section
8784 && exp_seg != text_section
8785 && exp_seg != data_section
8786 && exp_seg != bss_section
8787 && exp_seg != undefined_section
8788 && !bfd_is_com_section (exp_seg))
8790 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8794 else if (!intel_syntax && exp_seg == reg_section)
8797 as_bad (_("illegal immediate register operand %s"), imm_start);
8802 /* This is an address. The size of the address will be
8803 determined later, depending on destination register,
8804 suffix, or the default for the section. */
8805 i.types[this_operand].bitfield.imm8 = 1;
8806 i.types[this_operand].bitfield.imm16 = 1;
8807 i.types[this_operand].bitfield.imm32 = 1;
8808 i.types[this_operand].bitfield.imm32s = 1;
8809 i.types[this_operand].bitfield.imm64 = 1;
8810 i.types[this_operand] = operand_type_and (i.types[this_operand],
8818 i386_scale (char *scale)
8821 char *save = input_line_pointer;
8823 input_line_pointer = scale;
8824 val = get_absolute_expression ();
8829 i.log2_scale_factor = 0;
8832 i.log2_scale_factor = 1;
8835 i.log2_scale_factor = 2;
8838 i.log2_scale_factor = 3;
8842 char sep = *input_line_pointer;
8844 *input_line_pointer = '\0';
8845 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8847 *input_line_pointer = sep;
8848 input_line_pointer = save;
8852 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8854 as_warn (_("scale factor of %d without an index register"),
8855 1 << i.log2_scale_factor);
8856 i.log2_scale_factor = 0;
8858 scale = input_line_pointer;
8859 input_line_pointer = save;
8864 i386_displacement (char *disp_start, char *disp_end)
8868 char *save_input_line_pointer;
8869 char *gotfree_input_line;
8871 i386_operand_type bigdisp, types = anydisp;
8874 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8876 as_bad (_("at most %d displacement operands are allowed"),
8877 MAX_MEMORY_OPERANDS);
8881 operand_type_set (&bigdisp, 0);
8882 if ((i.types[this_operand].bitfield.jumpabsolute)
8883 || (!current_templates->start->opcode_modifier.jump
8884 && !current_templates->start->opcode_modifier.jumpdword))
8886 bigdisp.bitfield.disp32 = 1;
8887 override = (i.prefix[ADDR_PREFIX] != 0);
8888 if (flag_code == CODE_64BIT)
8892 bigdisp.bitfield.disp32s = 1;
8893 bigdisp.bitfield.disp64 = 1;
8896 else if ((flag_code == CODE_16BIT) ^ override)
8898 bigdisp.bitfield.disp32 = 0;
8899 bigdisp.bitfield.disp16 = 1;
8904 /* For PC-relative branches, the width of the displacement
8905 is dependent upon data size, not address size. */
8906 override = (i.prefix[DATA_PREFIX] != 0);
8907 if (flag_code == CODE_64BIT)
8909 if (override || i.suffix == WORD_MNEM_SUFFIX)
8910 bigdisp.bitfield.disp16 = 1;
8913 bigdisp.bitfield.disp32 = 1;
8914 bigdisp.bitfield.disp32s = 1;
8920 override = (i.suffix == (flag_code != CODE_16BIT
8922 : LONG_MNEM_SUFFIX));
8923 bigdisp.bitfield.disp32 = 1;
8924 if ((flag_code == CODE_16BIT) ^ override)
8926 bigdisp.bitfield.disp32 = 0;
8927 bigdisp.bitfield.disp16 = 1;
8931 i.types[this_operand] = operand_type_or (i.types[this_operand],
8934 exp = &disp_expressions[i.disp_operands];
8935 i.op[this_operand].disps = exp;
8937 save_input_line_pointer = input_line_pointer;
8938 input_line_pointer = disp_start;
8939 END_STRING_AND_SAVE (disp_end);
8941 #ifndef GCC_ASM_O_HACK
8942 #define GCC_ASM_O_HACK 0
8945 END_STRING_AND_SAVE (disp_end + 1);
8946 if (i.types[this_operand].bitfield.baseIndex
8947 && displacement_string_end[-1] == '+')
8949 /* This hack is to avoid a warning when using the "o"
8950 constraint within gcc asm statements.
8953 #define _set_tssldt_desc(n,addr,limit,type) \
8954 __asm__ __volatile__ ( \
8956 "movw %w1,2+%0\n\t" \
8958 "movb %b1,4+%0\n\t" \
8959 "movb %4,5+%0\n\t" \
8960 "movb $0,6+%0\n\t" \
8961 "movb %h1,7+%0\n\t" \
8963 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8965 This works great except that the output assembler ends
8966 up looking a bit weird if it turns out that there is
8967 no offset. You end up producing code that looks like:
8980 So here we provide the missing zero. */
8982 *displacement_string_end = '0';
8985 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8986 if (gotfree_input_line)
8987 input_line_pointer = gotfree_input_line;
8989 exp_seg = expression (exp);
8992 if (*input_line_pointer)
8993 as_bad (_("junk `%s' after expression"), input_line_pointer);
8995 RESTORE_END_STRING (disp_end + 1);
8997 input_line_pointer = save_input_line_pointer;
8998 if (gotfree_input_line)
9000 free (gotfree_input_line);
9002 if (exp->X_op == O_constant || exp->X_op == O_register)
9003 exp->X_op = O_illegal;
9006 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9008 RESTORE_END_STRING (disp_end);
9014 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9015 i386_operand_type types, const char *disp_start)
9017 i386_operand_type bigdisp;
9020 /* We do this to make sure that the section symbol is in
9021 the symbol table. We will ultimately change the relocation
9022 to be relative to the beginning of the section. */
9023 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9024 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9025 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9027 if (exp->X_op != O_symbol)
9030 if (S_IS_LOCAL (exp->X_add_symbol)
9031 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9032 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9033 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9034 exp->X_op = O_subtract;
9035 exp->X_op_symbol = GOT_symbol;
9036 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9037 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9038 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9039 i.reloc[this_operand] = BFD_RELOC_64;
9041 i.reloc[this_operand] = BFD_RELOC_32;
9044 else if (exp->X_op == O_absent
9045 || exp->X_op == O_illegal
9046 || exp->X_op == O_big)
9049 as_bad (_("missing or invalid displacement expression `%s'"),
9054 else if (flag_code == CODE_64BIT
9055 && !i.prefix[ADDR_PREFIX]
9056 && exp->X_op == O_constant)
9058 /* Since displacement is signed extended to 64bit, don't allow
9059 disp32 and turn off disp32s if they are out of range. */
9060 i.types[this_operand].bitfield.disp32 = 0;
9061 if (!fits_in_signed_long (exp->X_add_number))
9063 i.types[this_operand].bitfield.disp32s = 0;
9064 if (i.types[this_operand].bitfield.baseindex)
9066 as_bad (_("0x%lx out range of signed 32bit displacement"),
9067 (long) exp->X_add_number);
9073 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9074 else if (exp->X_op != O_constant
9075 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9076 && exp_seg != absolute_section
9077 && exp_seg != text_section
9078 && exp_seg != data_section
9079 && exp_seg != bss_section
9080 && exp_seg != undefined_section
9081 && !bfd_is_com_section (exp_seg))
9083 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9088 /* Check if this is a displacement only operand. */
9089 bigdisp = i.types[this_operand];
9090 bigdisp.bitfield.disp8 = 0;
9091 bigdisp.bitfield.disp16 = 0;
9092 bigdisp.bitfield.disp32 = 0;
9093 bigdisp.bitfield.disp32s = 0;
9094 bigdisp.bitfield.disp64 = 0;
9095 if (operand_type_all_zero (&bigdisp))
9096 i.types[this_operand] = operand_type_and (i.types[this_operand],
9102 /* Return the active addressing mode, taking address override and
9103 registers forming the address into consideration. Update the
9104 address override prefix if necessary. */
9106 static enum flag_code
9107 i386_addressing_mode (void)
9109 enum flag_code addr_mode;
9111 if (i.prefix[ADDR_PREFIX])
9112 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9115 addr_mode = flag_code;
9117 #if INFER_ADDR_PREFIX
9118 if (i.mem_operands == 0)
9120 /* Infer address prefix from the first memory operand. */
9121 const reg_entry *addr_reg = i.base_reg;
9123 if (addr_reg == NULL)
9124 addr_reg = i.index_reg;
9128 if (addr_reg->reg_num == RegEip
9129 || addr_reg->reg_num == RegEiz
9130 || addr_reg->reg_type.bitfield.dword)
9131 addr_mode = CODE_32BIT;
9132 else if (flag_code != CODE_64BIT
9133 && addr_reg->reg_type.bitfield.word)
9134 addr_mode = CODE_16BIT;
9136 if (addr_mode != flag_code)
9138 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9140 /* Change the size of any displacement too. At most one
9141 of Disp16 or Disp32 is set.
9142 FIXME. There doesn't seem to be any real need for
9143 separate Disp16 and Disp32 flags. The same goes for
9144 Imm16 and Imm32. Removing them would probably clean
9145 up the code quite a lot. */
9146 if (flag_code != CODE_64BIT
9147 && (i.types[this_operand].bitfield.disp16
9148 || i.types[this_operand].bitfield.disp32))
9149 i.types[this_operand]
9150 = operand_type_xor (i.types[this_operand], disp16_32);
9160 /* Make sure the memory operand we've been dealt is valid.
9161 Return 1 on success, 0 on a failure. */
9164 i386_index_check (const char *operand_string)
9166 const char *kind = "base/index";
9167 enum flag_code addr_mode = i386_addressing_mode ();
9169 if (current_templates->start->opcode_modifier.isstring
9170 && !current_templates->start->opcode_modifier.immext
9171 && (current_templates->end[-1].opcode_modifier.isstring
9174 /* Memory operands of string insns are special in that they only allow
9175 a single register (rDI, rSI, or rBX) as their memory address. */
9176 const reg_entry *expected_reg;
9177 static const char *di_si[][2] =
9183 static const char *bx[] = { "ebx", "bx", "rbx" };
9185 kind = "string address";
9187 if (current_templates->start->opcode_modifier.repprefixok)
9189 i386_operand_type type = current_templates->end[-1].operand_types[0];
9191 if (!type.bitfield.baseindex
9192 || ((!i.mem_operands != !intel_syntax)
9193 && current_templates->end[-1].operand_types[1]
9194 .bitfield.baseindex))
9195 type = current_templates->end[-1].operand_types[1];
9196 expected_reg = hash_find (reg_hash,
9197 di_si[addr_mode][type.bitfield.esseg]);
9201 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9203 if (i.base_reg != expected_reg
9205 || operand_type_check (i.types[this_operand], disp))
9207 /* The second memory operand must have the same size as
9211 && !((addr_mode == CODE_64BIT
9212 && i.base_reg->reg_type.bitfield.qword)
9213 || (addr_mode == CODE_32BIT
9214 ? i.base_reg->reg_type.bitfield.dword
9215 : i.base_reg->reg_type.bitfield.word)))
9218 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9220 intel_syntax ? '[' : '(',
9222 expected_reg->reg_name,
9223 intel_syntax ? ']' : ')');
9230 as_bad (_("`%s' is not a valid %s expression"),
9231 operand_string, kind);
9236 if (addr_mode != CODE_16BIT)
9238 /* 32-bit/64-bit checks. */
9240 && (addr_mode == CODE_64BIT
9241 ? !i.base_reg->reg_type.bitfield.qword
9242 : !i.base_reg->reg_type.bitfield.dword)
9244 || (i.base_reg->reg_num
9245 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9247 && !i.index_reg->reg_type.bitfield.xmmword
9248 && !i.index_reg->reg_type.bitfield.ymmword
9249 && !i.index_reg->reg_type.bitfield.zmmword
9250 && ((addr_mode == CODE_64BIT
9251 ? !(i.index_reg->reg_type.bitfield.qword
9252 || i.index_reg->reg_num == RegRiz)
9253 : !(i.index_reg->reg_type.bitfield.dword
9254 || i.index_reg->reg_num == RegEiz))
9255 || !i.index_reg->reg_type.bitfield.baseindex)))
9258 /* bndmk, bndldx, and bndstx have special restrictions. */
9259 if (current_templates->start->base_opcode == 0xf30f1b
9260 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9262 /* They cannot use RIP-relative addressing. */
9263 if (i.base_reg && i.base_reg->reg_num == RegRip)
9265 as_bad (_("`%s' cannot be used here"), operand_string);
9269 /* bndldx and bndstx ignore their scale factor. */
9270 if (current_templates->start->base_opcode != 0xf30f1b
9271 && i.log2_scale_factor)
9272 as_warn (_("register scaling is being ignored here"));
9277 /* 16-bit checks. */
9279 && (!i.base_reg->reg_type.bitfield.word
9280 || !i.base_reg->reg_type.bitfield.baseindex))
9282 && (!i.index_reg->reg_type.bitfield.word
9283 || !i.index_reg->reg_type.bitfield.baseindex
9285 && i.base_reg->reg_num < 6
9286 && i.index_reg->reg_num >= 6
9287 && i.log2_scale_factor == 0))))
9294 /* Handle vector immediates. */
9297 RC_SAE_immediate (const char *imm_start)
9299 unsigned int match_found, j;
9300 const char *pstr = imm_start;
9308 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9310 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9314 rc_op.type = RC_NamesTable[j].type;
9315 rc_op.operand = this_operand;
9316 i.rounding = &rc_op;
9320 as_bad (_("duplicated `%s'"), imm_start);
9323 pstr += RC_NamesTable[j].len;
9333 as_bad (_("Missing '}': '%s'"), imm_start);
9336 /* RC/SAE immediate string should contain nothing more. */;
9339 as_bad (_("Junk after '}': '%s'"), imm_start);
9343 exp = &im_expressions[i.imm_operands++];
9344 i.op[this_operand].imms = exp;
9346 exp->X_op = O_constant;
9347 exp->X_add_number = 0;
9348 exp->X_add_symbol = (symbolS *) 0;
9349 exp->X_op_symbol = (symbolS *) 0;
9351 i.types[this_operand].bitfield.imm8 = 1;
9355 /* Only string instructions can have a second memory operand, so
9356 reduce current_templates to just those if it contains any. */
9358 maybe_adjust_templates (void)
9360 const insn_template *t;
9362 gas_assert (i.mem_operands == 1);
9364 for (t = current_templates->start; t < current_templates->end; ++t)
9365 if (t->opcode_modifier.isstring)
9368 if (t < current_templates->end)
9370 static templates aux_templates;
9371 bfd_boolean recheck;
9373 aux_templates.start = t;
9374 for (; t < current_templates->end; ++t)
9375 if (!t->opcode_modifier.isstring)
9377 aux_templates.end = t;
9379 /* Determine whether to re-check the first memory operand. */
9380 recheck = (aux_templates.start != current_templates->start
9381 || t != current_templates->end);
9383 current_templates = &aux_templates;
9388 if (i.memop1_string != NULL
9389 && i386_index_check (i.memop1_string) == 0)
9398 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9402 i386_att_operand (char *operand_string)
9406 char *op_string = operand_string;
9408 if (is_space_char (*op_string))
9411 /* We check for an absolute prefix (differentiating,
9412 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9413 if (*op_string == ABSOLUTE_PREFIX)
9416 if (is_space_char (*op_string))
9418 i.types[this_operand].bitfield.jumpabsolute = 1;
9421 /* Check if operand is a register. */
9422 if ((r = parse_register (op_string, &end_op)) != NULL)
9424 i386_operand_type temp;
9426 /* Check for a segment override by searching for ':' after a
9427 segment register. */
9429 if (is_space_char (*op_string))
9431 if (*op_string == ':'
9432 && (r->reg_type.bitfield.sreg2
9433 || r->reg_type.bitfield.sreg3))
9438 i.seg[i.mem_operands] = &es;
9441 i.seg[i.mem_operands] = &cs;
9444 i.seg[i.mem_operands] = &ss;
9447 i.seg[i.mem_operands] = &ds;
9450 i.seg[i.mem_operands] = &fs;
9453 i.seg[i.mem_operands] = &gs;
9457 /* Skip the ':' and whitespace. */
9459 if (is_space_char (*op_string))
9462 if (!is_digit_char (*op_string)
9463 && !is_identifier_char (*op_string)
9464 && *op_string != '('
9465 && *op_string != ABSOLUTE_PREFIX)
9467 as_bad (_("bad memory operand `%s'"), op_string);
9470 /* Handle case of %es:*foo. */
9471 if (*op_string == ABSOLUTE_PREFIX)
9474 if (is_space_char (*op_string))
9476 i.types[this_operand].bitfield.jumpabsolute = 1;
9478 goto do_memory_reference;
9481 /* Handle vector operations. */
9482 if (*op_string == '{')
9484 op_string = check_VecOperations (op_string, NULL);
9485 if (op_string == NULL)
9491 as_bad (_("junk `%s' after register"), op_string);
9495 temp.bitfield.baseindex = 0;
9496 i.types[this_operand] = operand_type_or (i.types[this_operand],
9498 i.types[this_operand].bitfield.unspecified = 0;
9499 i.op[this_operand].regs = r;
9502 else if (*op_string == REGISTER_PREFIX)
9504 as_bad (_("bad register name `%s'"), op_string);
9507 else if (*op_string == IMMEDIATE_PREFIX)
9510 if (i.types[this_operand].bitfield.jumpabsolute)
9512 as_bad (_("immediate operand illegal with absolute jump"));
9515 if (!i386_immediate (op_string))
9518 else if (RC_SAE_immediate (operand_string))
9520 /* If it is a RC or SAE immediate, do nothing. */
9523 else if (is_digit_char (*op_string)
9524 || is_identifier_char (*op_string)
9525 || *op_string == '"'
9526 || *op_string == '(')
9528 /* This is a memory reference of some sort. */
9531 /* Start and end of displacement string expression (if found). */
9532 char *displacement_string_start;
9533 char *displacement_string_end;
9536 do_memory_reference:
9537 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9539 if ((i.mem_operands == 1
9540 && !current_templates->start->opcode_modifier.isstring)
9541 || i.mem_operands == 2)
9543 as_bad (_("too many memory references for `%s'"),
9544 current_templates->start->name);
9548 /* Check for base index form. We detect the base index form by
9549 looking for an ')' at the end of the operand, searching
9550 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9552 base_string = op_string + strlen (op_string);
9554 /* Handle vector operations. */
9555 vop_start = strchr (op_string, '{');
9556 if (vop_start && vop_start < base_string)
9558 if (check_VecOperations (vop_start, base_string) == NULL)
9560 base_string = vop_start;
9564 if (is_space_char (*base_string))
9567 /* If we only have a displacement, set-up for it to be parsed later. */
9568 displacement_string_start = op_string;
9569 displacement_string_end = base_string + 1;
9571 if (*base_string == ')')
9574 unsigned int parens_balanced = 1;
9575 /* We've already checked that the number of left & right ()'s are
9576 equal, so this loop will not be infinite. */
9580 if (*base_string == ')')
9582 if (*base_string == '(')
9585 while (parens_balanced);
9587 temp_string = base_string;
9589 /* Skip past '(' and whitespace. */
9591 if (is_space_char (*base_string))
9594 if (*base_string == ','
9595 || ((i.base_reg = parse_register (base_string, &end_op))
9598 displacement_string_end = temp_string;
9600 i.types[this_operand].bitfield.baseindex = 1;
9604 base_string = end_op;
9605 if (is_space_char (*base_string))
9609 /* There may be an index reg or scale factor here. */
9610 if (*base_string == ',')
9613 if (is_space_char (*base_string))
9616 if ((i.index_reg = parse_register (base_string, &end_op))
9619 base_string = end_op;
9620 if (is_space_char (*base_string))
9622 if (*base_string == ',')
9625 if (is_space_char (*base_string))
9628 else if (*base_string != ')')
9630 as_bad (_("expecting `,' or `)' "
9631 "after index register in `%s'"),
9636 else if (*base_string == REGISTER_PREFIX)
9638 end_op = strchr (base_string, ',');
9641 as_bad (_("bad register name `%s'"), base_string);
9645 /* Check for scale factor. */
9646 if (*base_string != ')')
9648 char *end_scale = i386_scale (base_string);
9653 base_string = end_scale;
9654 if (is_space_char (*base_string))
9656 if (*base_string != ')')
9658 as_bad (_("expecting `)' "
9659 "after scale factor in `%s'"),
9664 else if (!i.index_reg)
9666 as_bad (_("expecting index register or scale factor "
9667 "after `,'; got '%c'"),
9672 else if (*base_string != ')')
9674 as_bad (_("expecting `,' or `)' "
9675 "after base register in `%s'"),
9680 else if (*base_string == REGISTER_PREFIX)
9682 end_op = strchr (base_string, ',');
9685 as_bad (_("bad register name `%s'"), base_string);
9690 /* If there's an expression beginning the operand, parse it,
9691 assuming displacement_string_start and
9692 displacement_string_end are meaningful. */
9693 if (displacement_string_start != displacement_string_end)
9695 if (!i386_displacement (displacement_string_start,
9696 displacement_string_end))
9700 /* Special case for (%dx) while doing input/output op. */
9702 && i.base_reg->reg_type.bitfield.inoutportreg
9704 && i.log2_scale_factor == 0
9705 && i.seg[i.mem_operands] == 0
9706 && !operand_type_check (i.types[this_operand], disp))
9708 i.types[this_operand] = i.base_reg->reg_type;
9712 if (i386_index_check (operand_string) == 0)
9714 i.types[this_operand].bitfield.mem = 1;
9715 if (i.mem_operands == 0)
9716 i.memop1_string = xstrdup (operand_string);
9721 /* It's not a memory operand; argh! */
9722 as_bad (_("invalid char %s beginning operand %d `%s'"),
9723 output_invalid (*op_string),
9728 return 1; /* Normal return. */
9731 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9732 that an rs_machine_dependent frag may reach. */
9735 i386_frag_max_var (fragS *frag)
9737 /* The only relaxable frags are for jumps.
9738 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9739 gas_assert (frag->fr_type == rs_machine_dependent);
9740 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9745 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9747 /* STT_GNU_IFUNC symbol must go through PLT. */
9748 if ((symbol_get_bfdsym (fr_symbol)->flags
9749 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9752 if (!S_IS_EXTERNAL (fr_symbol))
9753 /* Symbol may be weak or local. */
9754 return !S_IS_WEAK (fr_symbol);
9756 /* Global symbols with non-default visibility can't be preempted. */
9757 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9760 if (fr_var != NO_RELOC)
9761 switch ((enum bfd_reloc_code_real) fr_var)
9763 case BFD_RELOC_386_PLT32:
9764 case BFD_RELOC_X86_64_PLT32:
9765 /* Symbol with PLT relocation may be preempted. */
9771 /* Global symbols with default visibility in a shared library may be
9772 preempted by another definition. */
9777 /* md_estimate_size_before_relax()
9779 Called just before relax() for rs_machine_dependent frags. The x86
9780 assembler uses these frags to handle variable size jump
9783 Any symbol that is now undefined will not become defined.
9784 Return the correct fr_subtype in the frag.
9785 Return the initial "guess for variable size of frag" to caller.
9786 The guess is actually the growth beyond the fixed part. Whatever
9787 we do to grow the fixed or variable part contributes to our
9791 md_estimate_size_before_relax (fragS *fragP, segT segment)
9793 /* We've already got fragP->fr_subtype right; all we have to do is
9794 check for un-relaxable symbols. On an ELF system, we can't relax
9795 an externally visible symbol, because it may be overridden by a
9797 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9800 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9803 #if defined (OBJ_COFF) && defined (TE_PE)
9804 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9805 && S_IS_WEAK (fragP->fr_symbol))
9809 /* Symbol is undefined in this segment, or we need to keep a
9810 reloc so that weak symbols can be overridden. */
9811 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9812 enum bfd_reloc_code_real reloc_type;
9813 unsigned char *opcode;
9816 if (fragP->fr_var != NO_RELOC)
9817 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9819 reloc_type = BFD_RELOC_16_PCREL;
9820 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9821 else if (need_plt32_p (fragP->fr_symbol))
9822 reloc_type = BFD_RELOC_X86_64_PLT32;
9825 reloc_type = BFD_RELOC_32_PCREL;
9827 old_fr_fix = fragP->fr_fix;
9828 opcode = (unsigned char *) fragP->fr_opcode;
9830 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9833 /* Make jmp (0xeb) a (d)word displacement jump. */
9835 fragP->fr_fix += size;
9836 fix_new (fragP, old_fr_fix, size,
9838 fragP->fr_offset, 1,
9844 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9846 /* Negate the condition, and branch past an
9847 unconditional jump. */
9850 /* Insert an unconditional jump. */
9852 /* We added two extra opcode bytes, and have a two byte
9854 fragP->fr_fix += 2 + 2;
9855 fix_new (fragP, old_fr_fix + 2, 2,
9857 fragP->fr_offset, 1,
9864 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9869 fixP = fix_new (fragP, old_fr_fix, 1,
9871 fragP->fr_offset, 1,
9873 fixP->fx_signed = 1;
9877 /* This changes the byte-displacement jump 0x7N
9878 to the (d)word-displacement jump 0x0f,0x8N. */
9879 opcode[1] = opcode[0] + 0x10;
9880 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9881 /* We've added an opcode byte. */
9882 fragP->fr_fix += 1 + size;
9883 fix_new (fragP, old_fr_fix + 1, size,
9885 fragP->fr_offset, 1,
9890 BAD_CASE (fragP->fr_subtype);
9894 return fragP->fr_fix - old_fr_fix;
9897 /* Guess size depending on current relax state. Initially the relax
9898 state will correspond to a short jump and we return 1, because
9899 the variable part of the frag (the branch offset) is one byte
9900 long. However, we can relax a section more than once and in that
9901 case we must either set fr_subtype back to the unrelaxed state,
9902 or return the value for the appropriate branch. */
9903 return md_relax_table[fragP->fr_subtype].rlx_length;
9906 /* Called after relax() is finished.
9908 In: Address of frag.
9909 fr_type == rs_machine_dependent.
9910 fr_subtype is what the address relaxed to.
9912 Out: Any fixSs and constants are set up.
9913 Caller will turn frag into a ".space 0". */
9916 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9919 unsigned char *opcode;
9920 unsigned char *where_to_put_displacement = NULL;
9921 offsetT target_address;
9922 offsetT opcode_address;
9923 unsigned int extension = 0;
9924 offsetT displacement_from_opcode_start;
9926 opcode = (unsigned char *) fragP->fr_opcode;
9928 /* Address we want to reach in file space. */
9929 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9931 /* Address opcode resides at in file space. */
9932 opcode_address = fragP->fr_address + fragP->fr_fix;
9934 /* Displacement from opcode start to fill into instruction. */
9935 displacement_from_opcode_start = target_address - opcode_address;
9937 if ((fragP->fr_subtype & BIG) == 0)
9939 /* Don't have to change opcode. */
9940 extension = 1; /* 1 opcode + 1 displacement */
9941 where_to_put_displacement = &opcode[1];
9945 if (no_cond_jump_promotion
9946 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9947 as_warn_where (fragP->fr_file, fragP->fr_line,
9948 _("long jump required"));
9950 switch (fragP->fr_subtype)
9952 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9953 extension = 4; /* 1 opcode + 4 displacement */
9955 where_to_put_displacement = &opcode[1];
9958 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9959 extension = 2; /* 1 opcode + 2 displacement */
9961 where_to_put_displacement = &opcode[1];
9964 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9965 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9966 extension = 5; /* 2 opcode + 4 displacement */
9967 opcode[1] = opcode[0] + 0x10;
9968 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9969 where_to_put_displacement = &opcode[2];
9972 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9973 extension = 3; /* 2 opcode + 2 displacement */
9974 opcode[1] = opcode[0] + 0x10;
9975 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9976 where_to_put_displacement = &opcode[2];
9979 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9984 where_to_put_displacement = &opcode[3];
9988 BAD_CASE (fragP->fr_subtype);
9993 /* If size if less then four we are sure that the operand fits,
9994 but if it's 4, then it could be that the displacement is larger
9996 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9998 && ((addressT) (displacement_from_opcode_start - extension
9999 + ((addressT) 1 << 31))
10000 > (((addressT) 2 << 31) - 1)))
10002 as_bad_where (fragP->fr_file, fragP->fr_line,
10003 _("jump target out of range"));
10004 /* Make us emit 0. */
10005 displacement_from_opcode_start = extension;
10007 /* Now put displacement after opcode. */
10008 md_number_to_chars ((char *) where_to_put_displacement,
10009 (valueT) (displacement_from_opcode_start - extension),
10010 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10011 fragP->fr_fix += extension;
10014 /* Apply a fixup (fixP) to segment data, once it has been determined
10015 by our caller that we have all the info we need to fix it up.
10017 Parameter valP is the pointer to the value of the bits.
10019 On the 386, immediates, displacements, and data pointers are all in
10020 the same (little-endian) format, so we don't need to care about which
10021 we are handling. */
10024 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10026 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10027 valueT value = *valP;
10029 #if !defined (TE_Mach)
10030 if (fixP->fx_pcrel)
10032 switch (fixP->fx_r_type)
10038 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10041 case BFD_RELOC_X86_64_32S:
10042 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10045 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10048 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10053 if (fixP->fx_addsy != NULL
10054 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10055 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10056 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10057 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10058 && !use_rela_relocations)
10060 /* This is a hack. There should be a better way to handle this.
10061 This covers for the fact that bfd_install_relocation will
10062 subtract the current location (for partial_inplace, PC relative
10063 relocations); see more below. */
10067 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10070 value += fixP->fx_where + fixP->fx_frag->fr_address;
10072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10075 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10077 if ((sym_seg == seg
10078 || (symbol_section_p (fixP->fx_addsy)
10079 && sym_seg != absolute_section))
10080 && !generic_force_reloc (fixP))
10082 /* Yes, we add the values in twice. This is because
10083 bfd_install_relocation subtracts them out again. I think
10084 bfd_install_relocation is broken, but I don't dare change
10086 value += fixP->fx_where + fixP->fx_frag->fr_address;
10090 #if defined (OBJ_COFF) && defined (TE_PE)
10091 /* For some reason, the PE format does not store a
10092 section address offset for a PC relative symbol. */
10093 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10094 || S_IS_WEAK (fixP->fx_addsy))
10095 value += md_pcrel_from (fixP);
10098 #if defined (OBJ_COFF) && defined (TE_PE)
10099 if (fixP->fx_addsy != NULL
10100 && S_IS_WEAK (fixP->fx_addsy)
10101 /* PR 16858: Do not modify weak function references. */
10102 && ! fixP->fx_pcrel)
10104 #if !defined (TE_PEP)
10105 /* For x86 PE weak function symbols are neither PC-relative
10106 nor do they set S_IS_FUNCTION. So the only reliable way
10107 to detect them is to check the flags of their containing
10109 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10110 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10114 value -= S_GET_VALUE (fixP->fx_addsy);
10118 /* Fix a few things - the dynamic linker expects certain values here,
10119 and we must not disappoint it. */
10120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10121 if (IS_ELF && fixP->fx_addsy)
10122 switch (fixP->fx_r_type)
10124 case BFD_RELOC_386_PLT32:
10125 case BFD_RELOC_X86_64_PLT32:
10126 /* Make the jump instruction point to the address of the operand. At
10127 runtime we merely add the offset to the actual PLT entry. */
10131 case BFD_RELOC_386_TLS_GD:
10132 case BFD_RELOC_386_TLS_LDM:
10133 case BFD_RELOC_386_TLS_IE_32:
10134 case BFD_RELOC_386_TLS_IE:
10135 case BFD_RELOC_386_TLS_GOTIE:
10136 case BFD_RELOC_386_TLS_GOTDESC:
10137 case BFD_RELOC_X86_64_TLSGD:
10138 case BFD_RELOC_X86_64_TLSLD:
10139 case BFD_RELOC_X86_64_GOTTPOFF:
10140 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10141 value = 0; /* Fully resolved at runtime. No addend. */
10143 case BFD_RELOC_386_TLS_LE:
10144 case BFD_RELOC_386_TLS_LDO_32:
10145 case BFD_RELOC_386_TLS_LE_32:
10146 case BFD_RELOC_X86_64_DTPOFF32:
10147 case BFD_RELOC_X86_64_DTPOFF64:
10148 case BFD_RELOC_X86_64_TPOFF32:
10149 case BFD_RELOC_X86_64_TPOFF64:
10150 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10153 case BFD_RELOC_386_TLS_DESC_CALL:
10154 case BFD_RELOC_X86_64_TLSDESC_CALL:
10155 value = 0; /* Fully resolved at runtime. No addend. */
10156 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10160 case BFD_RELOC_VTABLE_INHERIT:
10161 case BFD_RELOC_VTABLE_ENTRY:
10168 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10170 #endif /* !defined (TE_Mach) */
10172 /* Are we finished with this relocation now? */
10173 if (fixP->fx_addsy == NULL)
10175 #if defined (OBJ_COFF) && defined (TE_PE)
10176 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10179 /* Remember value for tc_gen_reloc. */
10180 fixP->fx_addnumber = value;
10181 /* Clear out the frag for now. */
10185 else if (use_rela_relocations)
10187 fixP->fx_no_overflow = 1;
10188 /* Remember value for tc_gen_reloc. */
10189 fixP->fx_addnumber = value;
10193 md_number_to_chars (p, value, fixP->fx_size);
10197 md_atof (int type, char *litP, int *sizeP)
10199 /* This outputs the LITTLENUMs in REVERSE order;
10200 in accord with the bigendian 386. */
10201 return ieee_md_atof (type, litP, sizeP, FALSE);
10204 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10207 output_invalid (int c)
10210 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10213 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10214 "(0x%x)", (unsigned char) c);
10215 return output_invalid_buf;
10218 /* REG_STRING starts *before* REGISTER_PREFIX. */
10220 static const reg_entry *
10221 parse_real_register (char *reg_string, char **end_op)
10223 char *s = reg_string;
10225 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10226 const reg_entry *r;
10228 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10229 if (*s == REGISTER_PREFIX)
10232 if (is_space_char (*s))
10235 p = reg_name_given;
10236 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10238 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10239 return (const reg_entry *) NULL;
10243 /* For naked regs, make sure that we are not dealing with an identifier.
10244 This prevents confusing an identifier like `eax_var' with register
10246 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10247 return (const reg_entry *) NULL;
10251 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10253 /* Handle floating point regs, allowing spaces in the (i) part. */
10254 if (r == i386_regtab /* %st is first entry of table */)
10256 if (!cpu_arch_flags.bitfield.cpu8087
10257 && !cpu_arch_flags.bitfield.cpu287
10258 && !cpu_arch_flags.bitfield.cpu387)
10259 return (const reg_entry *) NULL;
10261 if (is_space_char (*s))
10266 if (is_space_char (*s))
10268 if (*s >= '0' && *s <= '7')
10270 int fpr = *s - '0';
10272 if (is_space_char (*s))
10277 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10282 /* We have "%st(" then garbage. */
10283 return (const reg_entry *) NULL;
10287 if (r == NULL || allow_pseudo_reg)
10290 if (operand_type_all_zero (&r->reg_type))
10291 return (const reg_entry *) NULL;
10293 if ((r->reg_type.bitfield.dword
10294 || r->reg_type.bitfield.sreg3
10295 || r->reg_type.bitfield.control
10296 || r->reg_type.bitfield.debug
10297 || r->reg_type.bitfield.test)
10298 && !cpu_arch_flags.bitfield.cpui386)
10299 return (const reg_entry *) NULL;
10301 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10302 return (const reg_entry *) NULL;
10304 if (!cpu_arch_flags.bitfield.cpuavx512f)
10306 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10307 return (const reg_entry *) NULL;
10309 if (!cpu_arch_flags.bitfield.cpuavx)
10311 if (r->reg_type.bitfield.ymmword)
10312 return (const reg_entry *) NULL;
10314 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10315 return (const reg_entry *) NULL;
10319 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10320 return (const reg_entry *) NULL;
10322 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10323 if (!allow_index_reg
10324 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10325 return (const reg_entry *) NULL;
10327 /* Upper 16 vector registers are only available with VREX in 64bit
10328 mode, and require EVEX encoding. */
10329 if (r->reg_flags & RegVRex)
10331 if (!cpu_arch_flags.bitfield.cpuvrex
10332 || flag_code != CODE_64BIT)
10333 return (const reg_entry *) NULL;
10335 i.vec_encoding = vex_encoding_evex;
10338 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10339 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10340 && flag_code != CODE_64BIT)
10341 return (const reg_entry *) NULL;
10343 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10344 return (const reg_entry *) NULL;
10349 /* REG_STRING starts *before* REGISTER_PREFIX. */
10351 static const reg_entry *
10352 parse_register (char *reg_string, char **end_op)
10354 const reg_entry *r;
10356 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10357 r = parse_real_register (reg_string, end_op);
10362 char *save = input_line_pointer;
10366 input_line_pointer = reg_string;
10367 c = get_symbol_name (®_string);
10368 symbolP = symbol_find (reg_string);
10369 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10371 const expressionS *e = symbol_get_value_expression (symbolP);
10373 know (e->X_op == O_register);
10374 know (e->X_add_number >= 0
10375 && (valueT) e->X_add_number < i386_regtab_size);
10376 r = i386_regtab + e->X_add_number;
10377 if ((r->reg_flags & RegVRex))
10378 i.vec_encoding = vex_encoding_evex;
10379 *end_op = input_line_pointer;
10381 *input_line_pointer = c;
10382 input_line_pointer = save;
10388 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10390 const reg_entry *r;
10391 char *end = input_line_pointer;
10394 r = parse_register (name, &input_line_pointer);
10395 if (r && end <= input_line_pointer)
10397 *nextcharP = *input_line_pointer;
10398 *input_line_pointer = 0;
10399 e->X_op = O_register;
10400 e->X_add_number = r - i386_regtab;
10403 input_line_pointer = end;
10405 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10409 md_operand (expressionS *e)
10412 const reg_entry *r;
10414 switch (*input_line_pointer)
10416 case REGISTER_PREFIX:
10417 r = parse_real_register (input_line_pointer, &end);
10420 e->X_op = O_register;
10421 e->X_add_number = r - i386_regtab;
10422 input_line_pointer = end;
10427 gas_assert (intel_syntax);
10428 end = input_line_pointer++;
10430 if (*input_line_pointer == ']')
10432 ++input_line_pointer;
10433 e->X_op_symbol = make_expr_symbol (e);
10434 e->X_add_symbol = NULL;
10435 e->X_add_number = 0;
10440 e->X_op = O_absent;
10441 input_line_pointer = end;
10448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10449 const char *md_shortopts = "kVQ:sqnO::";
10451 const char *md_shortopts = "qnO::";
10454 #define OPTION_32 (OPTION_MD_BASE + 0)
10455 #define OPTION_64 (OPTION_MD_BASE + 1)
10456 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10457 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10458 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10459 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10460 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10461 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10462 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10463 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10464 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10465 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10466 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10467 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10468 #define OPTION_X32 (OPTION_MD_BASE + 14)
10469 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10470 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10471 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10472 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10473 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10474 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10475 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10476 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10477 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10478 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10480 struct option md_longopts[] =
10482 {"32", no_argument, NULL, OPTION_32},
10483 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10484 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10485 {"64", no_argument, NULL, OPTION_64},
10487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10488 {"x32", no_argument, NULL, OPTION_X32},
10489 {"mshared", no_argument, NULL, OPTION_MSHARED},
10491 {"divide", no_argument, NULL, OPTION_DIVIDE},
10492 {"march", required_argument, NULL, OPTION_MARCH},
10493 {"mtune", required_argument, NULL, OPTION_MTUNE},
10494 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10495 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10496 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10497 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10498 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10499 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10500 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10501 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10502 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10503 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10504 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10505 # if defined (TE_PE) || defined (TE_PEP)
10506 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10508 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10509 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10510 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10511 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10512 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10513 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10514 {NULL, no_argument, NULL, 0}
10516 size_t md_longopts_size = sizeof (md_longopts);
10519 md_parse_option (int c, const char *arg)
10522 char *arch, *next, *saved;
10527 optimize_align_code = 0;
10531 quiet_warnings = 1;
10534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10535 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10536 should be emitted or not. FIXME: Not implemented. */
10540 /* -V: SVR4 argument to print version ID. */
10542 print_version_id ();
10545 /* -k: Ignore for FreeBSD compatibility. */
10550 /* -s: On i386 Solaris, this tells the native assembler to use
10551 .stab instead of .stab.excl. We always use .stab anyhow. */
10554 case OPTION_MSHARED:
10558 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10559 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10562 const char **list, **l;
10564 list = bfd_target_list ();
10565 for (l = list; *l != NULL; l++)
10566 if (CONST_STRNEQ (*l, "elf64-x86-64")
10567 || strcmp (*l, "coff-x86-64") == 0
10568 || strcmp (*l, "pe-x86-64") == 0
10569 || strcmp (*l, "pei-x86-64") == 0
10570 || strcmp (*l, "mach-o-x86-64") == 0)
10572 default_arch = "x86_64";
10576 as_fatal (_("no compiled in support for x86_64"));
10582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10586 const char **list, **l;
10588 list = bfd_target_list ();
10589 for (l = list; *l != NULL; l++)
10590 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10592 default_arch = "x86_64:32";
10596 as_fatal (_("no compiled in support for 32bit x86_64"));
10600 as_fatal (_("32bit x86_64 is only supported for ELF"));
10605 default_arch = "i386";
10608 case OPTION_DIVIDE:
10609 #ifdef SVR4_COMMENT_CHARS
10614 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10616 for (s = i386_comment_chars; *s != '\0'; s++)
10620 i386_comment_chars = n;
10626 saved = xstrdup (arg);
10628 /* Allow -march=+nosse. */
10634 as_fatal (_("invalid -march= option: `%s'"), arg);
10635 next = strchr (arch, '+');
10638 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10640 if (strcmp (arch, cpu_arch [j].name) == 0)
10643 if (! cpu_arch[j].flags.bitfield.cpui386)
10646 cpu_arch_name = cpu_arch[j].name;
10647 cpu_sub_arch_name = NULL;
10648 cpu_arch_flags = cpu_arch[j].flags;
10649 cpu_arch_isa = cpu_arch[j].type;
10650 cpu_arch_isa_flags = cpu_arch[j].flags;
10651 if (!cpu_arch_tune_set)
10653 cpu_arch_tune = cpu_arch_isa;
10654 cpu_arch_tune_flags = cpu_arch_isa_flags;
10658 else if (*cpu_arch [j].name == '.'
10659 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10661 /* ISA extension. */
10662 i386_cpu_flags flags;
10664 flags = cpu_flags_or (cpu_arch_flags,
10665 cpu_arch[j].flags);
10667 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10669 if (cpu_sub_arch_name)
10671 char *name = cpu_sub_arch_name;
10672 cpu_sub_arch_name = concat (name,
10674 (const char *) NULL);
10678 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10679 cpu_arch_flags = flags;
10680 cpu_arch_isa_flags = flags;
10684 = cpu_flags_or (cpu_arch_isa_flags,
10685 cpu_arch[j].flags);
10690 if (j >= ARRAY_SIZE (cpu_arch))
10692 /* Disable an ISA extension. */
10693 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10694 if (strcmp (arch, cpu_noarch [j].name) == 0)
10696 i386_cpu_flags flags;
10698 flags = cpu_flags_and_not (cpu_arch_flags,
10699 cpu_noarch[j].flags);
10700 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10702 if (cpu_sub_arch_name)
10704 char *name = cpu_sub_arch_name;
10705 cpu_sub_arch_name = concat (arch,
10706 (const char *) NULL);
10710 cpu_sub_arch_name = xstrdup (arch);
10711 cpu_arch_flags = flags;
10712 cpu_arch_isa_flags = flags;
10717 if (j >= ARRAY_SIZE (cpu_noarch))
10718 j = ARRAY_SIZE (cpu_arch);
10721 if (j >= ARRAY_SIZE (cpu_arch))
10722 as_fatal (_("invalid -march= option: `%s'"), arg);
10726 while (next != NULL);
10732 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10733 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10735 if (strcmp (arg, cpu_arch [j].name) == 0)
10737 cpu_arch_tune_set = 1;
10738 cpu_arch_tune = cpu_arch [j].type;
10739 cpu_arch_tune_flags = cpu_arch[j].flags;
10743 if (j >= ARRAY_SIZE (cpu_arch))
10744 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10747 case OPTION_MMNEMONIC:
10748 if (strcasecmp (arg, "att") == 0)
10749 intel_mnemonic = 0;
10750 else if (strcasecmp (arg, "intel") == 0)
10751 intel_mnemonic = 1;
10753 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10756 case OPTION_MSYNTAX:
10757 if (strcasecmp (arg, "att") == 0)
10759 else if (strcasecmp (arg, "intel") == 0)
10762 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10765 case OPTION_MINDEX_REG:
10766 allow_index_reg = 1;
10769 case OPTION_MNAKED_REG:
10770 allow_naked_reg = 1;
10773 case OPTION_MSSE2AVX:
10777 case OPTION_MSSE_CHECK:
10778 if (strcasecmp (arg, "error") == 0)
10779 sse_check = check_error;
10780 else if (strcasecmp (arg, "warning") == 0)
10781 sse_check = check_warning;
10782 else if (strcasecmp (arg, "none") == 0)
10783 sse_check = check_none;
10785 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10788 case OPTION_MOPERAND_CHECK:
10789 if (strcasecmp (arg, "error") == 0)
10790 operand_check = check_error;
10791 else if (strcasecmp (arg, "warning") == 0)
10792 operand_check = check_warning;
10793 else if (strcasecmp (arg, "none") == 0)
10794 operand_check = check_none;
10796 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10799 case OPTION_MAVXSCALAR:
10800 if (strcasecmp (arg, "128") == 0)
10801 avxscalar = vex128;
10802 else if (strcasecmp (arg, "256") == 0)
10803 avxscalar = vex256;
10805 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10808 case OPTION_MADD_BND_PREFIX:
10809 add_bnd_prefix = 1;
10812 case OPTION_MEVEXLIG:
10813 if (strcmp (arg, "128") == 0)
10814 evexlig = evexl128;
10815 else if (strcmp (arg, "256") == 0)
10816 evexlig = evexl256;
10817 else if (strcmp (arg, "512") == 0)
10818 evexlig = evexl512;
10820 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10823 case OPTION_MEVEXRCIG:
10824 if (strcmp (arg, "rne") == 0)
10826 else if (strcmp (arg, "rd") == 0)
10828 else if (strcmp (arg, "ru") == 0)
10830 else if (strcmp (arg, "rz") == 0)
10833 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10836 case OPTION_MEVEXWIG:
10837 if (strcmp (arg, "0") == 0)
10839 else if (strcmp (arg, "1") == 0)
10842 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10845 # if defined (TE_PE) || defined (TE_PEP)
10846 case OPTION_MBIG_OBJ:
10851 case OPTION_MOMIT_LOCK_PREFIX:
10852 if (strcasecmp (arg, "yes") == 0)
10853 omit_lock_prefix = 1;
10854 else if (strcasecmp (arg, "no") == 0)
10855 omit_lock_prefix = 0;
10857 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10860 case OPTION_MFENCE_AS_LOCK_ADD:
10861 if (strcasecmp (arg, "yes") == 0)
10863 else if (strcasecmp (arg, "no") == 0)
10866 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10869 case OPTION_MRELAX_RELOCATIONS:
10870 if (strcasecmp (arg, "yes") == 0)
10871 generate_relax_relocations = 1;
10872 else if (strcasecmp (arg, "no") == 0)
10873 generate_relax_relocations = 0;
10875 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10878 case OPTION_MAMD64:
10882 case OPTION_MINTEL64:
10890 /* Turn off -Os. */
10891 optimize_for_space = 0;
10893 else if (*arg == 's')
10895 optimize_for_space = 1;
10896 /* Turn on all encoding optimizations. */
10901 optimize = atoi (arg);
10902 /* Turn off -Os. */
10903 optimize_for_space = 0;
10913 #define MESSAGE_TEMPLATE \
10917 output_message (FILE *stream, char *p, char *message, char *start,
10918 int *left_p, const char *name, int len)
10920 int size = sizeof (MESSAGE_TEMPLATE);
10921 int left = *left_p;
10923 /* Reserve 2 spaces for ", " or ",\0" */
10926 /* Check if there is any room. */
10934 p = mempcpy (p, name, len);
10938 /* Output the current message now and start a new one. */
10941 fprintf (stream, "%s\n", message);
10943 left = size - (start - message) - len - 2;
10945 gas_assert (left >= 0);
10947 p = mempcpy (p, name, len);
10955 show_arch (FILE *stream, int ext, int check)
10957 static char message[] = MESSAGE_TEMPLATE;
10958 char *start = message + 27;
10960 int size = sizeof (MESSAGE_TEMPLATE);
10967 left = size - (start - message);
10968 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10970 /* Should it be skipped? */
10971 if (cpu_arch [j].skip)
10974 name = cpu_arch [j].name;
10975 len = cpu_arch [j].len;
10978 /* It is an extension. Skip if we aren't asked to show it. */
10989 /* It is an processor. Skip if we show only extension. */
10992 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10994 /* It is an impossible processor - skip. */
10998 p = output_message (stream, p, message, start, &left, name, len);
11001 /* Display disabled extensions. */
11003 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11005 name = cpu_noarch [j].name;
11006 len = cpu_noarch [j].len;
11007 p = output_message (stream, p, message, start, &left, name,
11012 fprintf (stream, "%s\n", message);
11016 md_show_usage (FILE *stream)
11018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11019 fprintf (stream, _("\
11021 -V print assembler version number\n\
11024 fprintf (stream, _("\
11025 -n Do not optimize code alignment\n\
11026 -q quieten some warnings\n"));
11027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11028 fprintf (stream, _("\
11031 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11032 || defined (TE_PE) || defined (TE_PEP))
11033 fprintf (stream, _("\
11034 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11036 #ifdef SVR4_COMMENT_CHARS
11037 fprintf (stream, _("\
11038 --divide do not treat `/' as a comment character\n"));
11040 fprintf (stream, _("\
11041 --divide ignored\n"));
11043 fprintf (stream, _("\
11044 -march=CPU[,+EXTENSION...]\n\
11045 generate code for CPU and EXTENSION, CPU is one of:\n"));
11046 show_arch (stream, 0, 1);
11047 fprintf (stream, _("\
11048 EXTENSION is combination of:\n"));
11049 show_arch (stream, 1, 0);
11050 fprintf (stream, _("\
11051 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11052 show_arch (stream, 0, 0);
11053 fprintf (stream, _("\
11054 -msse2avx encode SSE instructions with VEX prefix\n"));
11055 fprintf (stream, _("\
11056 -msse-check=[none|error|warning]\n\
11057 check SSE instructions\n"));
11058 fprintf (stream, _("\
11059 -moperand-check=[none|error|warning]\n\
11060 check operand combinations for validity\n"));
11061 fprintf (stream, _("\
11062 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11064 fprintf (stream, _("\
11065 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11067 fprintf (stream, _("\
11068 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11069 for EVEX.W bit ignored instructions\n"));
11070 fprintf (stream, _("\
11071 -mevexrcig=[rne|rd|ru|rz]\n\
11072 encode EVEX instructions with specific EVEX.RC value\n\
11073 for SAE-only ignored instructions\n"));
11074 fprintf (stream, _("\
11075 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11076 fprintf (stream, _("\
11077 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11078 fprintf (stream, _("\
11079 -mindex-reg support pseudo index registers\n"));
11080 fprintf (stream, _("\
11081 -mnaked-reg don't require `%%' prefix for registers\n"));
11082 fprintf (stream, _("\
11083 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11084 fprintf (stream, _("\
11085 -mshared disable branch optimization for shared code\n"));
11086 # if defined (TE_PE) || defined (TE_PEP)
11087 fprintf (stream, _("\
11088 -mbig-obj generate big object files\n"));
11090 fprintf (stream, _("\
11091 -momit-lock-prefix=[no|yes]\n\
11092 strip all lock prefixes\n"));
11093 fprintf (stream, _("\
11094 -mfence-as-lock-add=[no|yes]\n\
11095 encode lfence, mfence and sfence as\n\
11096 lock addl $0x0, (%%{re}sp)\n"));
11097 fprintf (stream, _("\
11098 -mrelax-relocations=[no|yes]\n\
11099 generate relax relocations\n"));
11100 fprintf (stream, _("\
11101 -mamd64 accept only AMD64 ISA\n"));
11102 fprintf (stream, _("\
11103 -mintel64 accept only Intel64 ISA\n"));
11106 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11107 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11108 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11110 /* Pick the target format to use. */
11113 i386_target_format (void)
11115 if (!strncmp (default_arch, "x86_64", 6))
11117 update_code_flag (CODE_64BIT, 1);
11118 if (default_arch[6] == '\0')
11119 x86_elf_abi = X86_64_ABI;
11121 x86_elf_abi = X86_64_X32_ABI;
11123 else if (!strcmp (default_arch, "i386"))
11124 update_code_flag (CODE_32BIT, 1);
11125 else if (!strcmp (default_arch, "iamcu"))
11127 update_code_flag (CODE_32BIT, 1);
11128 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11130 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11131 cpu_arch_name = "iamcu";
11132 cpu_sub_arch_name = NULL;
11133 cpu_arch_flags = iamcu_flags;
11134 cpu_arch_isa = PROCESSOR_IAMCU;
11135 cpu_arch_isa_flags = iamcu_flags;
11136 if (!cpu_arch_tune_set)
11138 cpu_arch_tune = cpu_arch_isa;
11139 cpu_arch_tune_flags = cpu_arch_isa_flags;
11142 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11143 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11147 as_fatal (_("unknown architecture"));
11149 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11150 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11151 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11152 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11154 switch (OUTPUT_FLAVOR)
11156 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11157 case bfd_target_aout_flavour:
11158 return AOUT_TARGET_FORMAT;
11160 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11161 # if defined (TE_PE) || defined (TE_PEP)
11162 case bfd_target_coff_flavour:
11163 if (flag_code == CODE_64BIT)
11164 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11167 # elif defined (TE_GO32)
11168 case bfd_target_coff_flavour:
11169 return "coff-go32";
11171 case bfd_target_coff_flavour:
11172 return "coff-i386";
11175 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11176 case bfd_target_elf_flavour:
11178 const char *format;
11180 switch (x86_elf_abi)
11183 format = ELF_TARGET_FORMAT;
11186 use_rela_relocations = 1;
11188 format = ELF_TARGET_FORMAT64;
11190 case X86_64_X32_ABI:
11191 use_rela_relocations = 1;
11193 disallow_64bit_reloc = 1;
11194 format = ELF_TARGET_FORMAT32;
11197 if (cpu_arch_isa == PROCESSOR_L1OM)
11199 if (x86_elf_abi != X86_64_ABI)
11200 as_fatal (_("Intel L1OM is 64bit only"));
11201 return ELF_TARGET_L1OM_FORMAT;
11203 else if (cpu_arch_isa == PROCESSOR_K1OM)
11205 if (x86_elf_abi != X86_64_ABI)
11206 as_fatal (_("Intel K1OM is 64bit only"));
11207 return ELF_TARGET_K1OM_FORMAT;
11209 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11211 if (x86_elf_abi != I386_ABI)
11212 as_fatal (_("Intel MCU is 32bit only"));
11213 return ELF_TARGET_IAMCU_FORMAT;
11219 #if defined (OBJ_MACH_O)
11220 case bfd_target_mach_o_flavour:
11221 if (flag_code == CODE_64BIT)
11223 use_rela_relocations = 1;
11225 return "mach-o-x86-64";
11228 return "mach-o-i386";
11236 #endif /* OBJ_MAYBE_ more than one */
11239 md_undefined_symbol (char *name)
11241 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11242 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11243 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11244 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11248 if (symbol_find (name))
11249 as_bad (_("GOT already in symbol table"));
11250 GOT_symbol = symbol_new (name, undefined_section,
11251 (valueT) 0, &zero_address_frag);
11258 /* Round up a section size to the appropriate boundary. */
11261 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11263 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11264 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11266 /* For a.out, force the section size to be aligned. If we don't do
11267 this, BFD will align it for us, but it will not write out the
11268 final bytes of the section. This may be a bug in BFD, but it is
11269 easier to fix it here since that is how the other a.out targets
11273 align = bfd_get_section_alignment (stdoutput, segment);
11274 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11281 /* On the i386, PC-relative offsets are relative to the start of the
11282 next instruction. That is, the address of the offset, plus its
11283 size, since the offset is always the last part of the insn. */
11286 md_pcrel_from (fixS *fixP)
11288 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11294 s_bss (int ignore ATTRIBUTE_UNUSED)
11298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11300 obj_elf_section_change_hook ();
11302 temp = get_absolute_expression ();
11303 subseg_set (bss_section, (subsegT) temp);
11304 demand_empty_rest_of_line ();
11310 i386_validate_fix (fixS *fixp)
11312 if (fixp->fx_subsy)
11314 if (fixp->fx_subsy == GOT_symbol)
11316 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11320 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11321 if (fixp->fx_tcbit2)
11322 fixp->fx_r_type = (fixp->fx_tcbit
11323 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11324 : BFD_RELOC_X86_64_GOTPCRELX);
11327 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11332 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11334 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11336 fixp->fx_subsy = 0;
11339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11340 else if (!object_64bit)
11342 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11343 && fixp->fx_tcbit2)
11344 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11350 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11353 bfd_reloc_code_real_type code;
11355 switch (fixp->fx_r_type)
11357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11358 case BFD_RELOC_SIZE32:
11359 case BFD_RELOC_SIZE64:
11360 if (S_IS_DEFINED (fixp->fx_addsy)
11361 && !S_IS_EXTERNAL (fixp->fx_addsy))
11363 /* Resolve size relocation against local symbol to size of
11364 the symbol plus addend. */
11365 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11366 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11367 && !fits_in_unsigned_long (value))
11368 as_bad_where (fixp->fx_file, fixp->fx_line,
11369 _("symbol size computation overflow"));
11370 fixp->fx_addsy = NULL;
11371 fixp->fx_subsy = NULL;
11372 md_apply_fix (fixp, (valueT *) &value, NULL);
11376 /* Fall through. */
11378 case BFD_RELOC_X86_64_PLT32:
11379 case BFD_RELOC_X86_64_GOT32:
11380 case BFD_RELOC_X86_64_GOTPCREL:
11381 case BFD_RELOC_X86_64_GOTPCRELX:
11382 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11383 case BFD_RELOC_386_PLT32:
11384 case BFD_RELOC_386_GOT32:
11385 case BFD_RELOC_386_GOT32X:
11386 case BFD_RELOC_386_GOTOFF:
11387 case BFD_RELOC_386_GOTPC:
11388 case BFD_RELOC_386_TLS_GD:
11389 case BFD_RELOC_386_TLS_LDM:
11390 case BFD_RELOC_386_TLS_LDO_32:
11391 case BFD_RELOC_386_TLS_IE_32:
11392 case BFD_RELOC_386_TLS_IE:
11393 case BFD_RELOC_386_TLS_GOTIE:
11394 case BFD_RELOC_386_TLS_LE_32:
11395 case BFD_RELOC_386_TLS_LE:
11396 case BFD_RELOC_386_TLS_GOTDESC:
11397 case BFD_RELOC_386_TLS_DESC_CALL:
11398 case BFD_RELOC_X86_64_TLSGD:
11399 case BFD_RELOC_X86_64_TLSLD:
11400 case BFD_RELOC_X86_64_DTPOFF32:
11401 case BFD_RELOC_X86_64_DTPOFF64:
11402 case BFD_RELOC_X86_64_GOTTPOFF:
11403 case BFD_RELOC_X86_64_TPOFF32:
11404 case BFD_RELOC_X86_64_TPOFF64:
11405 case BFD_RELOC_X86_64_GOTOFF64:
11406 case BFD_RELOC_X86_64_GOTPC32:
11407 case BFD_RELOC_X86_64_GOT64:
11408 case BFD_RELOC_X86_64_GOTPCREL64:
11409 case BFD_RELOC_X86_64_GOTPC64:
11410 case BFD_RELOC_X86_64_GOTPLT64:
11411 case BFD_RELOC_X86_64_PLTOFF64:
11412 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11413 case BFD_RELOC_X86_64_TLSDESC_CALL:
11414 case BFD_RELOC_RVA:
11415 case BFD_RELOC_VTABLE_ENTRY:
11416 case BFD_RELOC_VTABLE_INHERIT:
11418 case BFD_RELOC_32_SECREL:
11420 code = fixp->fx_r_type;
11422 case BFD_RELOC_X86_64_32S:
11423 if (!fixp->fx_pcrel)
11425 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11426 code = fixp->fx_r_type;
11429 /* Fall through. */
11431 if (fixp->fx_pcrel)
11433 switch (fixp->fx_size)
11436 as_bad_where (fixp->fx_file, fixp->fx_line,
11437 _("can not do %d byte pc-relative relocation"),
11439 code = BFD_RELOC_32_PCREL;
11441 case 1: code = BFD_RELOC_8_PCREL; break;
11442 case 2: code = BFD_RELOC_16_PCREL; break;
11443 case 4: code = BFD_RELOC_32_PCREL; break;
11445 case 8: code = BFD_RELOC_64_PCREL; break;
11451 switch (fixp->fx_size)
11454 as_bad_where (fixp->fx_file, fixp->fx_line,
11455 _("can not do %d byte relocation"),
11457 code = BFD_RELOC_32;
11459 case 1: code = BFD_RELOC_8; break;
11460 case 2: code = BFD_RELOC_16; break;
11461 case 4: code = BFD_RELOC_32; break;
11463 case 8: code = BFD_RELOC_64; break;
11470 if ((code == BFD_RELOC_32
11471 || code == BFD_RELOC_32_PCREL
11472 || code == BFD_RELOC_X86_64_32S)
11474 && fixp->fx_addsy == GOT_symbol)
11477 code = BFD_RELOC_386_GOTPC;
11479 code = BFD_RELOC_X86_64_GOTPC32;
11481 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11483 && fixp->fx_addsy == GOT_symbol)
11485 code = BFD_RELOC_X86_64_GOTPC64;
11488 rel = XNEW (arelent);
11489 rel->sym_ptr_ptr = XNEW (asymbol *);
11490 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11492 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11494 if (!use_rela_relocations)
11496 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11497 vtable entry to be used in the relocation's section offset. */
11498 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11499 rel->address = fixp->fx_offset;
11500 #if defined (OBJ_COFF) && defined (TE_PE)
11501 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11502 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11507 /* Use the rela in 64bit mode. */
11510 if (disallow_64bit_reloc)
11513 case BFD_RELOC_X86_64_DTPOFF64:
11514 case BFD_RELOC_X86_64_TPOFF64:
11515 case BFD_RELOC_64_PCREL:
11516 case BFD_RELOC_X86_64_GOTOFF64:
11517 case BFD_RELOC_X86_64_GOT64:
11518 case BFD_RELOC_X86_64_GOTPCREL64:
11519 case BFD_RELOC_X86_64_GOTPC64:
11520 case BFD_RELOC_X86_64_GOTPLT64:
11521 case BFD_RELOC_X86_64_PLTOFF64:
11522 as_bad_where (fixp->fx_file, fixp->fx_line,
11523 _("cannot represent relocation type %s in x32 mode"),
11524 bfd_get_reloc_code_name (code));
11530 if (!fixp->fx_pcrel)
11531 rel->addend = fixp->fx_offset;
11535 case BFD_RELOC_X86_64_PLT32:
11536 case BFD_RELOC_X86_64_GOT32:
11537 case BFD_RELOC_X86_64_GOTPCREL:
11538 case BFD_RELOC_X86_64_GOTPCRELX:
11539 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11540 case BFD_RELOC_X86_64_TLSGD:
11541 case BFD_RELOC_X86_64_TLSLD:
11542 case BFD_RELOC_X86_64_GOTTPOFF:
11543 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11544 case BFD_RELOC_X86_64_TLSDESC_CALL:
11545 rel->addend = fixp->fx_offset - fixp->fx_size;
11548 rel->addend = (section->vma
11550 + fixp->fx_addnumber
11551 + md_pcrel_from (fixp));
11556 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11557 if (rel->howto == NULL)
11559 as_bad_where (fixp->fx_file, fixp->fx_line,
11560 _("cannot represent relocation type %s"),
11561 bfd_get_reloc_code_name (code));
11562 /* Set howto to a garbage value so that we can keep going. */
11563 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11564 gas_assert (rel->howto != NULL);
11570 #include "tc-i386-intel.c"
11573 tc_x86_parse_to_dw2regnum (expressionS *exp)
11575 int saved_naked_reg;
11576 char saved_register_dot;
11578 saved_naked_reg = allow_naked_reg;
11579 allow_naked_reg = 1;
11580 saved_register_dot = register_chars['.'];
11581 register_chars['.'] = '.';
11582 allow_pseudo_reg = 1;
11583 expression_and_evaluate (exp);
11584 allow_pseudo_reg = 0;
11585 register_chars['.'] = saved_register_dot;
11586 allow_naked_reg = saved_naked_reg;
11588 if (exp->X_op == O_register && exp->X_add_number >= 0)
11590 if ((addressT) exp->X_add_number < i386_regtab_size)
11592 exp->X_op = O_constant;
11593 exp->X_add_number = i386_regtab[exp->X_add_number]
11594 .dw2_regnum[flag_code >> 1];
11597 exp->X_op = O_illegal;
11602 tc_x86_frame_initial_instructions (void)
11604 static unsigned int sp_regno[2];
11606 if (!sp_regno[flag_code >> 1])
11608 char *saved_input = input_line_pointer;
11609 char sp[][4] = {"esp", "rsp"};
11612 input_line_pointer = sp[flag_code >> 1];
11613 tc_x86_parse_to_dw2regnum (&exp);
11614 gas_assert (exp.X_op == O_constant);
11615 sp_regno[flag_code >> 1] = exp.X_add_number;
11616 input_line_pointer = saved_input;
11619 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11620 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11624 x86_dwarf2_addr_size (void)
11626 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11627 if (x86_elf_abi == X86_64_X32_ABI)
11630 return bfd_arch_bits_per_address (stdoutput) / 8;
11634 i386_elf_section_type (const char *str, size_t len)
11636 if (flag_code == CODE_64BIT
11637 && len == sizeof ("unwind") - 1
11638 && strncmp (str, "unwind", 6) == 0)
11639 return SHT_X86_64_UNWIND;
11646 i386_solaris_fix_up_eh_frame (segT sec)
11648 if (flag_code == CODE_64BIT)
11649 elf_section_type (sec) = SHT_X86_64_UNWIND;
11655 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11659 exp.X_op = O_secrel;
11660 exp.X_add_symbol = symbol;
11661 exp.X_add_number = 0;
11662 emit_expr (&exp, size);
11666 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11667 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11670 x86_64_section_letter (int letter, const char **ptr_msg)
11672 if (flag_code == CODE_64BIT)
11675 return SHF_X86_64_LARGE;
11677 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11680 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11685 x86_64_section_word (char *str, size_t len)
11687 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11688 return SHF_X86_64_LARGE;
11694 handle_large_common (int small ATTRIBUTE_UNUSED)
11696 if (flag_code != CODE_64BIT)
11698 s_comm_internal (0, elf_common_parse);
11699 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11703 static segT lbss_section;
11704 asection *saved_com_section_ptr = elf_com_section_ptr;
11705 asection *saved_bss_section = bss_section;
11707 if (lbss_section == NULL)
11709 flagword applicable;
11710 segT seg = now_seg;
11711 subsegT subseg = now_subseg;
11713 /* The .lbss section is for local .largecomm symbols. */
11714 lbss_section = subseg_new (".lbss", 0);
11715 applicable = bfd_applicable_section_flags (stdoutput);
11716 bfd_set_section_flags (stdoutput, lbss_section,
11717 applicable & SEC_ALLOC);
11718 seg_info (lbss_section)->bss = 1;
11720 subseg_set (seg, subseg);
11723 elf_com_section_ptr = &_bfd_elf_large_com_section;
11724 bss_section = lbss_section;
11726 s_comm_internal (0, elf_common_parse);
11728 elf_com_section_ptr = saved_com_section_ptr;
11729 bss_section = saved_bss_section;
11732 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */