1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
274 mask_not_on_destination,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
283 /* TM holds the template for the insn were currently assembling. */
286 /* SUFFIX holds the instruction size suffix for byte, word, dword
287 or qword, if given. */
290 /* OPERANDS gives the number of given operands. */
291 unsigned int operands;
293 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
294 of given register, displacement, memory operands and immediate
296 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298 /* TYPES [i] is the type (see above #defines) which tells us how to
299 use OP[i] for the corresponding operand. */
300 i386_operand_type types[MAX_OPERANDS];
302 /* Displacement expression, immediate expression, or register for each
304 union i386_op op[MAX_OPERANDS];
306 /* Flags for operands. */
307 unsigned int flags[MAX_OPERANDS];
308 #define Operand_PCrel 1
310 /* Relocation type for operand */
311 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
313 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
314 the base index byte below. */
315 const reg_entry *base_reg;
316 const reg_entry *index_reg;
317 unsigned int log2_scale_factor;
319 /* SEG gives the seg_entries of this insn. They are zero unless
320 explicit segment overrides are given. */
321 const seg_entry *seg[2];
323 /* Copied first memory operand string, for re-checking. */
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes;
329 unsigned char prefix[MAX_PREFIXES];
331 /* RM and SIB are the modrm byte and the sib byte where the
332 addressing modes of this insn are encoded. */
339 /* Masking attributes. */
340 struct Mask_Operation *mask;
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation *rounding;
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation *broadcast;
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift;
351 /* Prefer load or store in encoding. */
354 dir_encoding_default = 0,
359 /* Prefer 8bit or 32bit displacement in encoding. */
362 disp_encoding_default = 0,
367 /* Prefer the REX byte in encoding. */
368 bfd_boolean rex_encoding;
370 /* Disable instruction size optimization. */
371 bfd_boolean no_optimize;
373 /* How to encode vector instructions. */
376 vex_encoding_default = 0,
383 const char *rep_prefix;
386 const char *hle_prefix;
388 /* Have BND prefix. */
389 const char *bnd_prefix;
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
395 enum i386_error error;
398 typedef struct _i386_insn i386_insn;
400 /* Link RC type with corresponding string, that'll be looked for in
409 static const struct RC_name RC_NamesTable[] =
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars[] = "*%-([{}"
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars = "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
445 const char *i386_comment_chars = "#";
446 #define PREFIX_SEPARATOR '/'
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars[] = "#/";
459 const char line_separator_chars[] = ";";
461 /* Chars that can be used to separate mant from exp in floating point
463 const char EXP_CHARS[] = "eE";
465 /* Chars that mean this number is a floating point constant
468 const char FLT_CHARS[] = "fFdDxX";
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars[256];
472 static char register_chars[256];
473 static char operand_chars[256];
474 static char identifier_chars[256];
475 static char digit_chars[256];
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack[32];
493 static char *save_stack_p;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
499 /* The instruction we're assembling. */
502 /* Possible templates for current insn. */
503 static const templates *current_templates;
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509 /* Current operand we are working on. */
510 static int this_operand = -1;
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
520 static enum flag_code flag_code;
521 static unsigned int object_64bit;
522 static unsigned int disallow_64bit_reloc;
523 static int use_rela_relocations = 0;
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529 /* The ELF ABI to use. */
537 static enum x86_elf_abi x86_elf_abi = I386_ABI;
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj = 0;
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared = 0;
550 /* 1 for intel syntax,
552 static int intel_syntax = 0;
554 /* 1 for Intel64 ISA,
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic = !SYSV386_COMPAT;
562 /* 1 if pseudo registers are permitted. */
563 static int allow_pseudo_reg = 0;
565 /* 1 if register prefix % not required. */
566 static int allow_naked_reg = 0;
568 /* 1 if the assembler should add BND prefix for all control-transferring
569 instructions supporting it, even if this prefix wasn't specified
571 static int add_bnd_prefix = 0;
573 /* 1 if pseudo index register, eiz/riz, is allowed . */
574 static int allow_index_reg = 0;
576 /* 1 if the assembler should ignore LOCK prefix, even if it was
577 specified explicitly. */
578 static int omit_lock_prefix = 0;
580 /* 1 if the assembler should encode lfence, mfence, and sfence as
581 "lock addl $0, (%{re}sp)". */
582 static int avoid_fence = 0;
584 /* 1 if the assembler should generate relax relocations. */
586 static int generate_relax_relocations
587 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589 static enum check_kind
595 sse_check, operand_check = check_warning;
598 1. Clear the REX_W bit with register operand if possible.
599 2. Above plus use 128bit vector instruction to clear the full vector
602 static int optimize = 0;
605 1. Clear the REX_W bit with register operand if possible.
606 2. Above plus use 128bit vector instruction to clear the full vector
608 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 static int optimize_for_space = 0;
613 /* Register prefix used for error message. */
614 static const char *register_prefix = "%";
616 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
617 leave, push, and pop instructions so that gcc has the same stack
618 frame as in 32 bit mode. */
619 static char stackop_size = '\0';
621 /* Non-zero to optimize code alignment. */
622 int optimize_align_code = 1;
624 /* Non-zero to quieten some warnings. */
625 static int quiet_warnings = 0;
628 static const char *cpu_arch_name = NULL;
629 static char *cpu_sub_arch_name = NULL;
631 /* CPU feature flags. */
632 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634 /* If we have selected a cpu we are generating instructions for. */
635 static int cpu_arch_tune_set = 0;
637 /* Cpu we are generating instructions for. */
638 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
640 /* CPU feature flags of cpu we are generating instructions for. */
641 static i386_cpu_flags cpu_arch_tune_flags;
643 /* CPU instruction set architecture used. */
644 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
646 /* CPU feature flags of instruction set architecture used. */
647 i386_cpu_flags cpu_arch_isa_flags;
649 /* If set, conditional jumps are not automatically promoted to handle
650 larger than a byte offset. */
651 static unsigned int no_cond_jump_promotion = 0;
653 /* Encode SSE instructions with VEX prefix. */
654 static unsigned int sse2avx;
656 /* Encode scalar AVX instructions with specific vector length. */
663 /* Encode scalar EVEX LIG instructions with specific vector length. */
671 /* Encode EVEX WIG instructions with specific evex.w. */
678 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
679 static enum rc_type evexrcig = rne;
681 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
682 static symbolS *GOT_symbol;
684 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
685 unsigned int x86_dwarf2_return_column;
687 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
688 int x86_cie_data_alignment;
690 /* Interface to relax_segment.
691 There are 3 major relax states for 386 jump insns because the
692 different types of jumps add different sizes to frags when we're
693 figuring out what sort of jump to choose to reach a given label. */
696 #define UNCOND_JUMP 0
698 #define COND_JUMP86 2
703 #define SMALL16 (SMALL | CODE16)
705 #define BIG16 (BIG | CODE16)
709 #define INLINE __inline__
715 #define ENCODE_RELAX_STATE(type, size) \
716 ((relax_substateT) (((type) << 2) | (size)))
717 #define TYPE_FROM_RELAX_STATE(s) \
719 #define DISP_SIZE_FROM_RELAX_STATE(s) \
720 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
722 /* This table is used by relax_frag to promote short jumps to long
723 ones where necessary. SMALL (short) jumps may be promoted to BIG
724 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
725 don't allow a short jump in a 32 bit code segment to be promoted to
726 a 16 bit offset jump because it's slower (requires data size
727 prefix), and doesn't work, unless the destination is in the bottom
728 64k of the code segment (The top 16 bits of eip are zeroed). */
730 const relax_typeS md_relax_table[] =
733 1) most positive reach of this state,
734 2) most negative reach of this state,
735 3) how many bytes this mode will have in the variable part of the frag
736 4) which index into the table to try if we can't fit into this one. */
738 /* UNCOND_JUMP states. */
739 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
741 /* dword jmp adds 4 bytes to frag:
742 0 extra opcode bytes, 4 displacement bytes. */
744 /* word jmp adds 2 byte2 to frag:
745 0 extra opcode bytes, 2 displacement bytes. */
748 /* COND_JUMP states. */
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
751 /* dword conditionals adds 5 bytes to frag:
752 1 extra opcode byte, 4 displacement bytes. */
754 /* word conditionals add 3 bytes to frag:
755 1 extra opcode byte, 2 displacement bytes. */
758 /* COND_JUMP86 states. */
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
761 /* dword conditionals adds 5 bytes to frag:
762 1 extra opcode byte, 4 displacement bytes. */
764 /* word conditionals add 4 bytes to frag:
765 1 displacement byte and a 3 byte long branch insn. */
769 static const arch_entry cpu_arch[] =
771 /* Do not replace the first two entries - i386_target_format()
772 relies on them being there in this order. */
773 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
774 CPU_GENERIC32_FLAGS, 0 },
775 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
776 CPU_GENERIC64_FLAGS, 0 },
777 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
779 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
781 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
783 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
785 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
787 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
789 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
791 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
793 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
794 CPU_PENTIUMPRO_FLAGS, 0 },
795 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
797 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
799 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
801 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
803 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
804 CPU_NOCONA_FLAGS, 0 },
805 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
807 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
809 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
810 CPU_CORE2_FLAGS, 1 },
811 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 0 },
813 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
814 CPU_COREI7_FLAGS, 0 },
815 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
817 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
819 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
820 CPU_IAMCU_FLAGS, 0 },
821 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
823 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
825 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
826 CPU_ATHLON_FLAGS, 0 },
827 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
829 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
831 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
833 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
834 CPU_AMDFAM10_FLAGS, 0 },
835 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
836 CPU_BDVER1_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
838 CPU_BDVER2_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
840 CPU_BDVER3_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
842 CPU_BDVER4_FLAGS, 0 },
843 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
844 CPU_ZNVER1_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
846 CPU_ZNVER2_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1030 CPU_WAITPKG_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1032 CPU_CLDEMOTE_FLAGS, 0 },
1033 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1034 CPU_MOVDIRI_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1036 CPU_MOVDIR64B_FLAGS, 0 },
1039 static const noarch_entry cpu_noarch[] =
1041 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1042 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1043 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1044 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1045 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1046 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1047 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1048 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1053 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1054 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1070 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1071 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1072 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1077 /* Like s_lcomm_internal in gas/read.c but the alignment string
1078 is allowed to be optional. */
1081 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1088 && *input_line_pointer == ',')
1090 align = parse_align (needs_align - 1);
1092 if (align == (addressT) -1)
1107 bss_alloc (symbolP, size, align);
1112 pe_lcomm (int needs_align)
1114 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1118 const pseudo_typeS md_pseudo_table[] =
1120 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1121 {"align", s_align_bytes, 0},
1123 {"align", s_align_ptwo, 0},
1125 {"arch", set_cpu_arch, 0},
1129 {"lcomm", pe_lcomm, 1},
1131 {"ffloat", float_cons, 'f'},
1132 {"dfloat", float_cons, 'd'},
1133 {"tfloat", float_cons, 'x'},
1135 {"slong", signed_cons, 4},
1136 {"noopt", s_ignore, 0},
1137 {"optim", s_ignore, 0},
1138 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1139 {"code16", set_code_flag, CODE_16BIT},
1140 {"code32", set_code_flag, CODE_32BIT},
1142 {"code64", set_code_flag, CODE_64BIT},
1144 {"intel_syntax", set_intel_syntax, 1},
1145 {"att_syntax", set_intel_syntax, 0},
1146 {"intel_mnemonic", set_intel_mnemonic, 1},
1147 {"att_mnemonic", set_intel_mnemonic, 0},
1148 {"allow_index_reg", set_allow_index_reg, 1},
1149 {"disallow_index_reg", set_allow_index_reg, 0},
1150 {"sse_check", set_check, 0},
1151 {"operand_check", set_check, 1},
1152 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1153 {"largecomm", handle_large_common, 0},
1155 {"file", dwarf2_directive_file, 0},
1156 {"loc", dwarf2_directive_loc, 0},
1157 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1160 {"secrel32", pe_directive_secrel, 0},
1165 /* For interface with expression (). */
1166 extern char *input_line_pointer;
1168 /* Hash table for instruction mnemonic lookup. */
1169 static struct hash_control *op_hash;
1171 /* Hash table for register lookup. */
1172 static struct hash_control *reg_hash;
1174 /* Various efficient no-op patterns for aligning code labels.
1175 Note: Don't try to assemble the instructions in the comments.
1176 0L and 0w are not legal. */
1177 static const unsigned char f32_1[] =
1179 static const unsigned char f32_2[] =
1180 {0x66,0x90}; /* xchg %ax,%ax */
1181 static const unsigned char f32_3[] =
1182 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1183 static const unsigned char f32_4[] =
1184 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1185 static const unsigned char f32_6[] =
1186 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1187 static const unsigned char f32_7[] =
1188 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1189 static const unsigned char f16_3[] =
1190 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1191 static const unsigned char f16_4[] =
1192 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1193 static const unsigned char jump_disp8[] =
1194 {0xeb}; /* jmp disp8 */
1195 static const unsigned char jump32_disp32[] =
1196 {0xe9}; /* jmp disp32 */
1197 static const unsigned char jump16_disp32[] =
1198 {0x66,0xe9}; /* jmp disp32 */
1199 /* 32-bit NOPs patterns. */
1200 static const unsigned char *const f32_patt[] = {
1201 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1203 /* 16-bit NOPs patterns. */
1204 static const unsigned char *const f16_patt[] = {
1205 f32_1, f32_2, f16_3, f16_4
1207 /* nopl (%[re]ax) */
1208 static const unsigned char alt_3[] =
1210 /* nopl 0(%[re]ax) */
1211 static const unsigned char alt_4[] =
1212 {0x0f,0x1f,0x40,0x00};
1213 /* nopl 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_5[] =
1215 {0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopw 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_6[] =
1218 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopl 0L(%[re]ax) */
1220 static const unsigned char alt_7[] =
1221 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1222 /* nopl 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_8[] =
1224 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_9[] =
1227 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_10[] =
1230 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* data16 nopw %cs:0L(%eax,%eax,1) */
1232 static const unsigned char alt_11[] =
1233 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 /* 32-bit and 64-bit NOPs patterns. */
1235 static const unsigned char *const alt_patt[] = {
1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1237 alt_9, alt_10, alt_11
1240 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1241 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1244 i386_output_nops (char *where, const unsigned char *const *patt,
1245 int count, int max_single_nop_size)
1248 /* Place the longer NOP first. */
1251 const unsigned char *nops = patt[max_single_nop_size - 1];
1253 /* Use the smaller one if the requsted one isn't available. */
1256 max_single_nop_size--;
1257 nops = patt[max_single_nop_size - 1];
1260 last = count % max_single_nop_size;
1263 for (offset = 0; offset < count; offset += max_single_nop_size)
1264 memcpy (where + offset, nops, max_single_nop_size);
1268 nops = patt[last - 1];
1271 /* Use the smaller one plus one-byte NOP if the needed one
1274 nops = patt[last - 1];
1275 memcpy (where + offset, nops, last);
1276 where[offset + last] = *patt[0];
1279 memcpy (where + offset, nops, last);
1284 fits_in_imm7 (offsetT num)
1286 return (num & 0x7f) == num;
1290 fits_in_imm31 (offsetT num)
1292 return (num & 0x7fffffff) == num;
1295 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1296 single NOP instruction LIMIT. */
1299 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1301 const unsigned char *const *patt = NULL;
1302 int max_single_nop_size;
1303 /* Maximum number of NOPs before switching to jump over NOPs. */
1304 int max_number_of_nops;
1306 switch (fragP->fr_type)
1315 /* We need to decide which NOP sequence to use for 32bit and
1316 64bit. When -mtune= is used:
1318 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1319 PROCESSOR_GENERIC32, f32_patt will be used.
1320 2. For the rest, alt_patt will be used.
1322 When -mtune= isn't used, alt_patt will be used if
1323 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1326 When -march= or .arch is used, we can't use anything beyond
1327 cpu_arch_isa_flags. */
1329 if (flag_code == CODE_16BIT)
1332 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1333 /* Limit number of NOPs to 2 in 16-bit mode. */
1334 max_number_of_nops = 2;
1338 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1340 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1341 switch (cpu_arch_tune)
1343 case PROCESSOR_UNKNOWN:
1344 /* We use cpu_arch_isa_flags to check if we SHOULD
1345 optimize with nops. */
1346 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1351 case PROCESSOR_PENTIUM4:
1352 case PROCESSOR_NOCONA:
1353 case PROCESSOR_CORE:
1354 case PROCESSOR_CORE2:
1355 case PROCESSOR_COREI7:
1356 case PROCESSOR_L1OM:
1357 case PROCESSOR_K1OM:
1358 case PROCESSOR_GENERIC64:
1360 case PROCESSOR_ATHLON:
1362 case PROCESSOR_AMDFAM10:
1364 case PROCESSOR_ZNVER:
1368 case PROCESSOR_I386:
1369 case PROCESSOR_I486:
1370 case PROCESSOR_PENTIUM:
1371 case PROCESSOR_PENTIUMPRO:
1372 case PROCESSOR_IAMCU:
1373 case PROCESSOR_GENERIC32:
1380 switch (fragP->tc_frag_data.tune)
1382 case PROCESSOR_UNKNOWN:
1383 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1384 PROCESSOR_UNKNOWN. */
1388 case PROCESSOR_I386:
1389 case PROCESSOR_I486:
1390 case PROCESSOR_PENTIUM:
1391 case PROCESSOR_IAMCU:
1393 case PROCESSOR_ATHLON:
1395 case PROCESSOR_AMDFAM10:
1397 case PROCESSOR_ZNVER:
1399 case PROCESSOR_GENERIC32:
1400 /* We use cpu_arch_isa_flags to check if we CAN optimize
1402 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1407 case PROCESSOR_PENTIUMPRO:
1408 case PROCESSOR_PENTIUM4:
1409 case PROCESSOR_NOCONA:
1410 case PROCESSOR_CORE:
1411 case PROCESSOR_CORE2:
1412 case PROCESSOR_COREI7:
1413 case PROCESSOR_L1OM:
1414 case PROCESSOR_K1OM:
1415 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1420 case PROCESSOR_GENERIC64:
1426 if (patt == f32_patt)
1428 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1429 /* Limit number of NOPs to 2 for older processors. */
1430 max_number_of_nops = 2;
1434 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1435 /* Limit number of NOPs to 7 for newer processors. */
1436 max_number_of_nops = 7;
1441 limit = max_single_nop_size;
1443 if (fragP->fr_type == rs_fill_nop)
1445 /* Output NOPs for .nop directive. */
1446 if (limit > max_single_nop_size)
1448 as_bad_where (fragP->fr_file, fragP->fr_line,
1449 _("invalid single nop size: %d "
1450 "(expect within [0, %d])"),
1451 limit, max_single_nop_size);
1456 fragP->fr_var = count;
1458 if ((count / max_single_nop_size) > max_number_of_nops)
1460 /* Generate jump over NOPs. */
1461 offsetT disp = count - 2;
1462 if (fits_in_imm7 (disp))
1464 /* Use "jmp disp8" if possible. */
1466 where[0] = jump_disp8[0];
1472 unsigned int size_of_jump;
1474 if (flag_code == CODE_16BIT)
1476 where[0] = jump16_disp32[0];
1477 where[1] = jump16_disp32[1];
1482 where[0] = jump32_disp32[0];
1486 count -= size_of_jump + 4;
1487 if (!fits_in_imm31 (count))
1489 as_bad_where (fragP->fr_file, fragP->fr_line,
1490 _("jump over nop padding out of range"));
1494 md_number_to_chars (where + size_of_jump, count, 4);
1495 where += size_of_jump + 4;
1499 /* Generate multiple NOPs. */
1500 i386_output_nops (where, patt, count, limit);
1504 operand_type_all_zero (const union i386_operand_type *x)
1506 switch (ARRAY_SIZE(x->array))
1517 return !x->array[0];
1524 operand_type_set (union i386_operand_type *x, unsigned int v)
1526 switch (ARRAY_SIZE(x->array))
1544 operand_type_equal (const union i386_operand_type *x,
1545 const union i386_operand_type *y)
1547 switch (ARRAY_SIZE(x->array))
1550 if (x->array[2] != y->array[2])
1554 if (x->array[1] != y->array[1])
1558 return x->array[0] == y->array[0];
1566 cpu_flags_all_zero (const union i386_cpu_flags *x)
1568 switch (ARRAY_SIZE(x->array))
1583 return !x->array[0];
1590 cpu_flags_equal (const union i386_cpu_flags *x,
1591 const union i386_cpu_flags *y)
1593 switch (ARRAY_SIZE(x->array))
1596 if (x->array[3] != y->array[3])
1600 if (x->array[2] != y->array[2])
1604 if (x->array[1] != y->array[1])
1608 return x->array[0] == y->array[0];
1616 cpu_flags_check_cpu64 (i386_cpu_flags f)
1618 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1619 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1622 static INLINE i386_cpu_flags
1623 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1625 switch (ARRAY_SIZE (x.array))
1628 x.array [3] &= y.array [3];
1631 x.array [2] &= y.array [2];
1634 x.array [1] &= y.array [1];
1637 x.array [0] &= y.array [0];
1645 static INLINE i386_cpu_flags
1646 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1648 switch (ARRAY_SIZE (x.array))
1651 x.array [3] |= y.array [3];
1654 x.array [2] |= y.array [2];
1657 x.array [1] |= y.array [1];
1660 x.array [0] |= y.array [0];
1668 static INLINE i386_cpu_flags
1669 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1671 switch (ARRAY_SIZE (x.array))
1674 x.array [3] &= ~y.array [3];
1677 x.array [2] &= ~y.array [2];
1680 x.array [1] &= ~y.array [1];
1683 x.array [0] &= ~y.array [0];
1691 #define CPU_FLAGS_ARCH_MATCH 0x1
1692 #define CPU_FLAGS_64BIT_MATCH 0x2
1694 #define CPU_FLAGS_PERFECT_MATCH \
1695 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1697 /* Return CPU flags match bits. */
1700 cpu_flags_match (const insn_template *t)
1702 i386_cpu_flags x = t->cpu_flags;
1703 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1705 x.bitfield.cpu64 = 0;
1706 x.bitfield.cpuno64 = 0;
1708 if (cpu_flags_all_zero (&x))
1710 /* This instruction is available on all archs. */
1711 match |= CPU_FLAGS_ARCH_MATCH;
1715 /* This instruction is available only on some archs. */
1716 i386_cpu_flags cpu = cpu_arch_flags;
1718 /* AVX512VL is no standalone feature - match it and then strip it. */
1719 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1721 x.bitfield.cpuavx512vl = 0;
1723 cpu = cpu_flags_and (x, cpu);
1724 if (!cpu_flags_all_zero (&cpu))
1726 if (x.bitfield.cpuavx)
1728 /* We need to check a few extra flags with AVX. */
1729 if (cpu.bitfield.cpuavx
1730 && (!t->opcode_modifier.sse2avx || sse2avx)
1731 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1732 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1733 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1734 match |= CPU_FLAGS_ARCH_MATCH;
1736 else if (x.bitfield.cpuavx512f)
1738 /* We need to check a few extra flags with AVX512F. */
1739 if (cpu.bitfield.cpuavx512f
1740 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1741 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1742 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1743 match |= CPU_FLAGS_ARCH_MATCH;
1746 match |= CPU_FLAGS_ARCH_MATCH;
1752 static INLINE i386_operand_type
1753 operand_type_and (i386_operand_type x, i386_operand_type y)
1755 switch (ARRAY_SIZE (x.array))
1758 x.array [2] &= y.array [2];
1761 x.array [1] &= y.array [1];
1764 x.array [0] &= y.array [0];
1772 static INLINE i386_operand_type
1773 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1775 switch (ARRAY_SIZE (x.array))
1778 x.array [2] &= ~y.array [2];
1781 x.array [1] &= ~y.array [1];
1784 x.array [0] &= ~y.array [0];
1792 static INLINE i386_operand_type
1793 operand_type_or (i386_operand_type x, i386_operand_type y)
1795 switch (ARRAY_SIZE (x.array))
1798 x.array [2] |= y.array [2];
1801 x.array [1] |= y.array [1];
1804 x.array [0] |= y.array [0];
1812 static INLINE i386_operand_type
1813 operand_type_xor (i386_operand_type x, i386_operand_type y)
1815 switch (ARRAY_SIZE (x.array))
1818 x.array [2] ^= y.array [2];
1821 x.array [1] ^= y.array [1];
1824 x.array [0] ^= y.array [0];
1832 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1833 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1834 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1835 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1836 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1837 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1838 static const i386_operand_type anydisp
1839 = OPERAND_TYPE_ANYDISP;
1840 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1841 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1842 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1843 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1844 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1845 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1846 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1847 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1848 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1849 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1850 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1851 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1862 operand_type_check (i386_operand_type t, enum operand_type c)
1867 return t.bitfield.reg;
1870 return (t.bitfield.imm8
1874 || t.bitfield.imm32s
1875 || t.bitfield.imm64);
1878 return (t.bitfield.disp8
1879 || t.bitfield.disp16
1880 || t.bitfield.disp32
1881 || t.bitfield.disp32s
1882 || t.bitfield.disp64);
1885 return (t.bitfield.disp8
1886 || t.bitfield.disp16
1887 || t.bitfield.disp32
1888 || t.bitfield.disp32s
1889 || t.bitfield.disp64
1890 || t.bitfield.baseindex);
1899 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1900 between operand GIVEN and opeand WANTED for instruction template T. */
1903 match_operand_size (const insn_template *t, unsigned int wanted,
1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
1918 /* Return 1 if there is no conflict in SIMD register between operand
1919 GIVEN and opeand WANTED for instruction template T. */
1922 match_simd_size (const insn_template *t, unsigned int wanted,
1925 return !((i.types[given].bitfield.xmmword
1926 && !t->operand_types[wanted].bitfield.xmmword)
1927 || (i.types[given].bitfield.ymmword
1928 && !t->operand_types[wanted].bitfield.ymmword)
1929 || (i.types[given].bitfield.zmmword
1930 && !t->operand_types[wanted].bitfield.zmmword));
1933 /* Return 1 if there is no conflict in any size between operand GIVEN
1934 and opeand WANTED for instruction template T. */
1937 match_mem_size (const insn_template *t, unsigned int wanted,
1940 return (match_operand_size (t, wanted, given)
1941 && !((i.types[given].bitfield.unspecified
1943 && !t->operand_types[wanted].bitfield.unspecified)
1944 || (i.types[given].bitfield.fword
1945 && !t->operand_types[wanted].bitfield.fword)
1946 /* For scalar opcode templates to allow register and memory
1947 operands at the same time, some special casing is needed
1948 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1949 down-conversion vpmov*. */
1950 || ((t->operand_types[wanted].bitfield.regsimd
1951 && !t->opcode_modifier.broadcast
1952 && (t->operand_types[wanted].bitfield.byte
1953 || t->operand_types[wanted].bitfield.word
1954 || t->operand_types[wanted].bitfield.dword
1955 || t->operand_types[wanted].bitfield.qword))
1956 ? (i.types[given].bitfield.xmmword
1957 || i.types[given].bitfield.ymmword
1958 || i.types[given].bitfield.zmmword)
1959 : !match_simd_size(t, wanted, given))));
1962 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1963 operands for instruction template T, and it has MATCH_REVERSE set if there
1964 is no size conflict on any operands for the template with operands reversed
1965 (and the template allows for reversing in the first place). */
1967 #define MATCH_STRAIGHT 1
1968 #define MATCH_REVERSE 2
1970 static INLINE unsigned int
1971 operand_size_match (const insn_template *t)
1973 unsigned int j, match = MATCH_STRAIGHT;
1975 /* Don't check jump instructions. */
1976 if (t->opcode_modifier.jump
1977 || t->opcode_modifier.jumpbyte
1978 || t->opcode_modifier.jumpdword
1979 || t->opcode_modifier.jumpintersegment)
1982 /* Check memory and accumulator operand size. */
1983 for (j = 0; j < i.operands; j++)
1985 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1986 && t->operand_types[j].bitfield.anysize)
1989 if (t->operand_types[j].bitfield.reg
1990 && !match_operand_size (t, j, j))
1996 if (t->operand_types[j].bitfield.regsimd
1997 && !match_simd_size (t, j, j))
2003 if (t->operand_types[j].bitfield.acc
2004 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2010 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2017 if (!t->opcode_modifier.d)
2021 i.error = operand_size_mismatch;
2025 /* Check reverse. */
2026 gas_assert (i.operands == 2);
2028 for (j = 0; j < 2; j++)
2030 if ((t->operand_types[j].bitfield.reg
2031 || t->operand_types[j].bitfield.acc)
2032 && !match_operand_size (t, j, !j))
2035 if (i.types[!j].bitfield.mem
2036 && !match_mem_size (t, j, !j))
2040 return match | MATCH_REVERSE;
2044 operand_type_match (i386_operand_type overlap,
2045 i386_operand_type given)
2047 i386_operand_type temp = overlap;
2049 temp.bitfield.jumpabsolute = 0;
2050 temp.bitfield.unspecified = 0;
2051 temp.bitfield.byte = 0;
2052 temp.bitfield.word = 0;
2053 temp.bitfield.dword = 0;
2054 temp.bitfield.fword = 0;
2055 temp.bitfield.qword = 0;
2056 temp.bitfield.tbyte = 0;
2057 temp.bitfield.xmmword = 0;
2058 temp.bitfield.ymmword = 0;
2059 temp.bitfield.zmmword = 0;
2060 if (operand_type_all_zero (&temp))
2063 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2064 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2068 i.error = operand_type_mismatch;
2072 /* If given types g0 and g1 are registers they must be of the same type
2073 unless the expected operand type register overlap is null.
2074 Memory operand size of certain SIMD instructions is also being checked
2078 operand_type_register_match (i386_operand_type g0,
2079 i386_operand_type t0,
2080 i386_operand_type g1,
2081 i386_operand_type t1)
2083 if (!g0.bitfield.reg
2084 && !g0.bitfield.regsimd
2085 && (!operand_type_check (g0, anymem)
2086 || g0.bitfield.unspecified
2087 || !t0.bitfield.regsimd))
2090 if (!g1.bitfield.reg
2091 && !g1.bitfield.regsimd
2092 && (!operand_type_check (g1, anymem)
2093 || g1.bitfield.unspecified
2094 || !t1.bitfield.regsimd))
2097 if (g0.bitfield.byte == g1.bitfield.byte
2098 && g0.bitfield.word == g1.bitfield.word
2099 && g0.bitfield.dword == g1.bitfield.dword
2100 && g0.bitfield.qword == g1.bitfield.qword
2101 && g0.bitfield.xmmword == g1.bitfield.xmmword
2102 && g0.bitfield.ymmword == g1.bitfield.ymmword
2103 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2106 if (!(t0.bitfield.byte & t1.bitfield.byte)
2107 && !(t0.bitfield.word & t1.bitfield.word)
2108 && !(t0.bitfield.dword & t1.bitfield.dword)
2109 && !(t0.bitfield.qword & t1.bitfield.qword)
2110 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2111 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2112 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2115 i.error = register_type_mismatch;
2120 static INLINE unsigned int
2121 register_number (const reg_entry *r)
2123 unsigned int nr = r->reg_num;
2125 if (r->reg_flags & RegRex)
2128 if (r->reg_flags & RegVRex)
2134 static INLINE unsigned int
2135 mode_from_disp_size (i386_operand_type t)
2137 if (t.bitfield.disp8)
2139 else if (t.bitfield.disp16
2140 || t.bitfield.disp32
2141 || t.bitfield.disp32s)
2148 fits_in_signed_byte (addressT num)
2150 return num + 0x80 <= 0xff;
2154 fits_in_unsigned_byte (addressT num)
2160 fits_in_unsigned_word (addressT num)
2162 return num <= 0xffff;
2166 fits_in_signed_word (addressT num)
2168 return num + 0x8000 <= 0xffff;
2172 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2177 return num + 0x80000000 <= 0xffffffff;
2179 } /* fits_in_signed_long() */
2182 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2187 return num <= 0xffffffff;
2189 } /* fits_in_unsigned_long() */
2192 fits_in_disp8 (offsetT num)
2194 int shift = i.memshift;
2200 mask = (1 << shift) - 1;
2202 /* Return 0 if NUM isn't properly aligned. */
2206 /* Check if NUM will fit in 8bit after shift. */
2207 return fits_in_signed_byte (num >> shift);
2211 fits_in_imm4 (offsetT num)
2213 return (num & 0xf) == num;
2216 static i386_operand_type
2217 smallest_imm_type (offsetT num)
2219 i386_operand_type t;
2221 operand_type_set (&t, 0);
2222 t.bitfield.imm64 = 1;
2224 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2226 /* This code is disabled on the 486 because all the Imm1 forms
2227 in the opcode table are slower on the i486. They're the
2228 versions with the implicitly specified single-position
2229 displacement, which has another syntax if you really want to
2231 t.bitfield.imm1 = 1;
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm8s = 1;
2234 t.bitfield.imm16 = 1;
2235 t.bitfield.imm32 = 1;
2236 t.bitfield.imm32s = 1;
2238 else if (fits_in_signed_byte (num))
2240 t.bitfield.imm8 = 1;
2241 t.bitfield.imm8s = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2246 else if (fits_in_unsigned_byte (num))
2248 t.bitfield.imm8 = 1;
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2253 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2255 t.bitfield.imm16 = 1;
2256 t.bitfield.imm32 = 1;
2257 t.bitfield.imm32s = 1;
2259 else if (fits_in_signed_long (num))
2261 t.bitfield.imm32 = 1;
2262 t.bitfield.imm32s = 1;
2264 else if (fits_in_unsigned_long (num))
2265 t.bitfield.imm32 = 1;
2271 offset_in_range (offsetT val, int size)
2277 case 1: mask = ((addressT) 1 << 8) - 1; break;
2278 case 2: mask = ((addressT) 1 << 16) - 1; break;
2279 case 4: mask = ((addressT) 2 << 31) - 1; break;
2281 case 8: mask = ((addressT) 2 << 63) - 1; break;
2287 /* If BFD64, sign extend val for 32bit address mode. */
2288 if (flag_code != CODE_64BIT
2289 || i.prefix[ADDR_PREFIX])
2290 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2291 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2294 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2296 char buf1[40], buf2[40];
2298 sprint_value (buf1, val);
2299 sprint_value (buf2, val & mask);
2300 as_warn (_("%s shortened to %s"), buf1, buf2);
2315 a. PREFIX_EXIST if attempting to add a prefix where one from the
2316 same class already exists.
2317 b. PREFIX_LOCK if lock prefix is added.
2318 c. PREFIX_REP if rep/repne prefix is added.
2319 d. PREFIX_DS if ds prefix is added.
2320 e. PREFIX_OTHER if other prefix is added.
2323 static enum PREFIX_GROUP
2324 add_prefix (unsigned int prefix)
2326 enum PREFIX_GROUP ret = PREFIX_OTHER;
2329 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2330 && flag_code == CODE_64BIT)
2332 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2333 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2334 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2335 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2346 case DS_PREFIX_OPCODE:
2349 case CS_PREFIX_OPCODE:
2350 case ES_PREFIX_OPCODE:
2351 case FS_PREFIX_OPCODE:
2352 case GS_PREFIX_OPCODE:
2353 case SS_PREFIX_OPCODE:
2357 case REPNE_PREFIX_OPCODE:
2358 case REPE_PREFIX_OPCODE:
2363 case LOCK_PREFIX_OPCODE:
2372 case ADDR_PREFIX_OPCODE:
2376 case DATA_PREFIX_OPCODE:
2380 if (i.prefix[q] != 0)
2388 i.prefix[q] |= prefix;
2391 as_bad (_("same type of prefix used twice"));
2397 update_code_flag (int value, int check)
2399 PRINTF_LIKE ((*as_error));
2401 flag_code = (enum flag_code) value;
2402 if (flag_code == CODE_64BIT)
2404 cpu_arch_flags.bitfield.cpu64 = 1;
2405 cpu_arch_flags.bitfield.cpuno64 = 0;
2409 cpu_arch_flags.bitfield.cpu64 = 0;
2410 cpu_arch_flags.bitfield.cpuno64 = 1;
2412 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2415 as_error = as_fatal;
2418 (*as_error) (_("64bit mode not supported on `%s'."),
2419 cpu_arch_name ? cpu_arch_name : default_arch);
2421 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2424 as_error = as_fatal;
2427 (*as_error) (_("32bit mode not supported on `%s'."),
2428 cpu_arch_name ? cpu_arch_name : default_arch);
2430 stackop_size = '\0';
2434 set_code_flag (int value)
2436 update_code_flag (value, 0);
2440 set_16bit_gcc_code_flag (int new_code_flag)
2442 flag_code = (enum flag_code) new_code_flag;
2443 if (flag_code != CODE_16BIT)
2445 cpu_arch_flags.bitfield.cpu64 = 0;
2446 cpu_arch_flags.bitfield.cpuno64 = 1;
2447 stackop_size = LONG_MNEM_SUFFIX;
2451 set_intel_syntax (int syntax_flag)
2453 /* Find out if register prefixing is specified. */
2454 int ask_naked_reg = 0;
2457 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2460 int e = get_symbol_name (&string);
2462 if (strcmp (string, "prefix") == 0)
2464 else if (strcmp (string, "noprefix") == 0)
2467 as_bad (_("bad argument to syntax directive."));
2468 (void) restore_line_pointer (e);
2470 demand_empty_rest_of_line ();
2472 intel_syntax = syntax_flag;
2474 if (ask_naked_reg == 0)
2475 allow_naked_reg = (intel_syntax
2476 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2478 allow_naked_reg = (ask_naked_reg < 0);
2480 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2482 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2483 identifier_chars['$'] = intel_syntax ? '$' : 0;
2484 register_prefix = allow_naked_reg ? "" : "%";
2488 set_intel_mnemonic (int mnemonic_flag)
2490 intel_mnemonic = mnemonic_flag;
2494 set_allow_index_reg (int flag)
2496 allow_index_reg = flag;
2500 set_check (int what)
2502 enum check_kind *kind;
2507 kind = &operand_check;
2518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2521 int e = get_symbol_name (&string);
2523 if (strcmp (string, "none") == 0)
2525 else if (strcmp (string, "warning") == 0)
2526 *kind = check_warning;
2527 else if (strcmp (string, "error") == 0)
2528 *kind = check_error;
2530 as_bad (_("bad argument to %s_check directive."), str);
2531 (void) restore_line_pointer (e);
2534 as_bad (_("missing argument for %s_check directive"), str);
2536 demand_empty_rest_of_line ();
2540 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2541 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2544 static const char *arch;
2546 /* Intel LIOM is only supported on ELF. */
2552 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2553 use default_arch. */
2554 arch = cpu_arch_name;
2556 arch = default_arch;
2559 /* If we are targeting Intel MCU, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2561 || new_flag.bitfield.cpuiamcu)
2564 /* If we are targeting Intel L1OM, we must enable it. */
2565 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2566 || new_flag.bitfield.cpul1om)
2569 /* If we are targeting Intel K1OM, we must enable it. */
2570 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2571 || new_flag.bitfield.cpuk1om)
2574 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2579 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2583 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2586 int e = get_symbol_name (&string);
2588 i386_cpu_flags flags;
2590 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2592 if (strcmp (string, cpu_arch[j].name) == 0)
2594 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2598 cpu_arch_name = cpu_arch[j].name;
2599 cpu_sub_arch_name = NULL;
2600 cpu_arch_flags = cpu_arch[j].flags;
2601 if (flag_code == CODE_64BIT)
2603 cpu_arch_flags.bitfield.cpu64 = 1;
2604 cpu_arch_flags.bitfield.cpuno64 = 0;
2608 cpu_arch_flags.bitfield.cpu64 = 0;
2609 cpu_arch_flags.bitfield.cpuno64 = 1;
2611 cpu_arch_isa = cpu_arch[j].type;
2612 cpu_arch_isa_flags = cpu_arch[j].flags;
2613 if (!cpu_arch_tune_set)
2615 cpu_arch_tune = cpu_arch_isa;
2616 cpu_arch_tune_flags = cpu_arch_isa_flags;
2621 flags = cpu_flags_or (cpu_arch_flags,
2624 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2626 if (cpu_sub_arch_name)
2628 char *name = cpu_sub_arch_name;
2629 cpu_sub_arch_name = concat (name,
2631 (const char *) NULL);
2635 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2636 cpu_arch_flags = flags;
2637 cpu_arch_isa_flags = flags;
2641 = cpu_flags_or (cpu_arch_isa_flags,
2643 (void) restore_line_pointer (e);
2644 demand_empty_rest_of_line ();
2649 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2651 /* Disable an ISA extension. */
2652 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2653 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2655 flags = cpu_flags_and_not (cpu_arch_flags,
2656 cpu_noarch[j].flags);
2657 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2659 if (cpu_sub_arch_name)
2661 char *name = cpu_sub_arch_name;
2662 cpu_sub_arch_name = concat (name, string,
2663 (const char *) NULL);
2667 cpu_sub_arch_name = xstrdup (string);
2668 cpu_arch_flags = flags;
2669 cpu_arch_isa_flags = flags;
2671 (void) restore_line_pointer (e);
2672 demand_empty_rest_of_line ();
2676 j = ARRAY_SIZE (cpu_arch);
2679 if (j >= ARRAY_SIZE (cpu_arch))
2680 as_bad (_("no such architecture: `%s'"), string);
2682 *input_line_pointer = e;
2685 as_bad (_("missing cpu architecture"));
2687 no_cond_jump_promotion = 0;
2688 if (*input_line_pointer == ','
2689 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2694 ++input_line_pointer;
2695 e = get_symbol_name (&string);
2697 if (strcmp (string, "nojumps") == 0)
2698 no_cond_jump_promotion = 1;
2699 else if (strcmp (string, "jumps") == 0)
2702 as_bad (_("no such architecture modifier: `%s'"), string);
2704 (void) restore_line_pointer (e);
2707 demand_empty_rest_of_line ();
2710 enum bfd_architecture
2713 if (cpu_arch_isa == PROCESSOR_L1OM)
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code != CODE_64BIT)
2717 as_fatal (_("Intel L1OM is 64bit ELF only"));
2718 return bfd_arch_l1om;
2720 else if (cpu_arch_isa == PROCESSOR_K1OM)
2722 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2723 || flag_code != CODE_64BIT)
2724 as_fatal (_("Intel K1OM is 64bit ELF only"));
2725 return bfd_arch_k1om;
2727 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2729 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2730 || flag_code == CODE_64BIT)
2731 as_fatal (_("Intel MCU is 32bit ELF only"));
2732 return bfd_arch_iamcu;
2735 return bfd_arch_i386;
2741 if (!strncmp (default_arch, "x86_64", 6))
2743 if (cpu_arch_isa == PROCESSOR_L1OM)
2745 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2746 || default_arch[6] != '\0')
2747 as_fatal (_("Intel L1OM is 64bit ELF only"));
2748 return bfd_mach_l1om;
2750 else if (cpu_arch_isa == PROCESSOR_K1OM)
2752 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2753 || default_arch[6] != '\0')
2754 as_fatal (_("Intel K1OM is 64bit ELF only"));
2755 return bfd_mach_k1om;
2757 else if (default_arch[6] == '\0')
2758 return bfd_mach_x86_64;
2760 return bfd_mach_x64_32;
2762 else if (!strcmp (default_arch, "i386")
2763 || !strcmp (default_arch, "iamcu"))
2765 if (cpu_arch_isa == PROCESSOR_IAMCU)
2767 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2768 as_fatal (_("Intel MCU is 32bit ELF only"));
2769 return bfd_mach_i386_iamcu;
2772 return bfd_mach_i386_i386;
2775 as_fatal (_("unknown architecture"));
2781 const char *hash_err;
2783 /* Support pseudo prefixes like {disp32}. */
2784 lex_type ['{'] = LEX_BEGIN_NAME;
2786 /* Initialize op_hash hash table. */
2787 op_hash = hash_new ();
2790 const insn_template *optab;
2791 templates *core_optab;
2793 /* Setup for loop. */
2795 core_optab = XNEW (templates);
2796 core_optab->start = optab;
2801 if (optab->name == NULL
2802 || strcmp (optab->name, (optab - 1)->name) != 0)
2804 /* different name --> ship out current template list;
2805 add to hash table; & begin anew. */
2806 core_optab->end = optab;
2807 hash_err = hash_insert (op_hash,
2809 (void *) core_optab);
2812 as_fatal (_("can't hash %s: %s"),
2816 if (optab->name == NULL)
2818 core_optab = XNEW (templates);
2819 core_optab->start = optab;
2824 /* Initialize reg_hash hash table. */
2825 reg_hash = hash_new ();
2827 const reg_entry *regtab;
2828 unsigned int regtab_size = i386_regtab_size;
2830 for (regtab = i386_regtab; regtab_size--; regtab++)
2832 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2834 as_fatal (_("can't hash %s: %s"),
2840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2845 for (c = 0; c < 256; c++)
2850 mnemonic_chars[c] = c;
2851 register_chars[c] = c;
2852 operand_chars[c] = c;
2854 else if (ISLOWER (c))
2856 mnemonic_chars[c] = c;
2857 register_chars[c] = c;
2858 operand_chars[c] = c;
2860 else if (ISUPPER (c))
2862 mnemonic_chars[c] = TOLOWER (c);
2863 register_chars[c] = mnemonic_chars[c];
2864 operand_chars[c] = c;
2866 else if (c == '{' || c == '}')
2868 mnemonic_chars[c] = c;
2869 operand_chars[c] = c;
2872 if (ISALPHA (c) || ISDIGIT (c))
2873 identifier_chars[c] = c;
2876 identifier_chars[c] = c;
2877 operand_chars[c] = c;
2882 identifier_chars['@'] = '@';
2885 identifier_chars['?'] = '?';
2886 operand_chars['?'] = '?';
2888 digit_chars['-'] = '-';
2889 mnemonic_chars['_'] = '_';
2890 mnemonic_chars['-'] = '-';
2891 mnemonic_chars['.'] = '.';
2892 identifier_chars['_'] = '_';
2893 identifier_chars['.'] = '.';
2895 for (p = operand_special_chars; *p != '\0'; p++)
2896 operand_chars[(unsigned char) *p] = *p;
2899 if (flag_code == CODE_64BIT)
2901 #if defined (OBJ_COFF) && defined (TE_PE)
2902 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2905 x86_dwarf2_return_column = 16;
2907 x86_cie_data_alignment = -8;
2911 x86_dwarf2_return_column = 8;
2912 x86_cie_data_alignment = -4;
2917 i386_print_statistics (FILE *file)
2919 hash_print_statistics (file, "i386 opcode", op_hash);
2920 hash_print_statistics (file, "i386 register", reg_hash);
2925 /* Debugging routines for md_assemble. */
2926 static void pte (insn_template *);
2927 static void pt (i386_operand_type);
2928 static void pe (expressionS *);
2929 static void ps (symbolS *);
2932 pi (char *line, i386_insn *x)
2936 fprintf (stdout, "%s: template ", line);
2938 fprintf (stdout, " address: base %s index %s scale %x\n",
2939 x->base_reg ? x->base_reg->reg_name : "none",
2940 x->index_reg ? x->index_reg->reg_name : "none",
2941 x->log2_scale_factor);
2942 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2943 x->rm.mode, x->rm.reg, x->rm.regmem);
2944 fprintf (stdout, " sib: base %x index %x scale %x\n",
2945 x->sib.base, x->sib.index, x->sib.scale);
2946 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2947 (x->rex & REX_W) != 0,
2948 (x->rex & REX_R) != 0,
2949 (x->rex & REX_X) != 0,
2950 (x->rex & REX_B) != 0);
2951 for (j = 0; j < x->operands; j++)
2953 fprintf (stdout, " #%d: ", j + 1);
2955 fprintf (stdout, "\n");
2956 if (x->types[j].bitfield.reg
2957 || x->types[j].bitfield.regmmx
2958 || x->types[j].bitfield.regsimd
2959 || x->types[j].bitfield.sreg2
2960 || x->types[j].bitfield.sreg3
2961 || x->types[j].bitfield.control
2962 || x->types[j].bitfield.debug
2963 || x->types[j].bitfield.test)
2964 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2965 if (operand_type_check (x->types[j], imm))
2967 if (operand_type_check (x->types[j], disp))
2968 pe (x->op[j].disps);
2973 pte (insn_template *t)
2976 fprintf (stdout, " %d operands ", t->operands);
2977 fprintf (stdout, "opcode %x ", t->base_opcode);
2978 if (t->extension_opcode != None)
2979 fprintf (stdout, "ext %x ", t->extension_opcode);
2980 if (t->opcode_modifier.d)
2981 fprintf (stdout, "D");
2982 if (t->opcode_modifier.w)
2983 fprintf (stdout, "W");
2984 fprintf (stdout, "\n");
2985 for (j = 0; j < t->operands; j++)
2987 fprintf (stdout, " #%d type ", j + 1);
2988 pt (t->operand_types[j]);
2989 fprintf (stdout, "\n");
2996 fprintf (stdout, " operation %d\n", e->X_op);
2997 fprintf (stdout, " add_number %ld (%lx)\n",
2998 (long) e->X_add_number, (long) e->X_add_number);
2999 if (e->X_add_symbol)
3001 fprintf (stdout, " add_symbol ");
3002 ps (e->X_add_symbol);
3003 fprintf (stdout, "\n");
3007 fprintf (stdout, " op_symbol ");
3008 ps (e->X_op_symbol);
3009 fprintf (stdout, "\n");
3016 fprintf (stdout, "%s type %s%s",
3018 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3019 segment_name (S_GET_SEGMENT (s)));
3022 static struct type_name
3024 i386_operand_type mask;
3027 const type_names[] =
3029 { OPERAND_TYPE_REG8, "r8" },
3030 { OPERAND_TYPE_REG16, "r16" },
3031 { OPERAND_TYPE_REG32, "r32" },
3032 { OPERAND_TYPE_REG64, "r64" },
3033 { OPERAND_TYPE_IMM8, "i8" },
3034 { OPERAND_TYPE_IMM8, "i8s" },
3035 { OPERAND_TYPE_IMM16, "i16" },
3036 { OPERAND_TYPE_IMM32, "i32" },
3037 { OPERAND_TYPE_IMM32S, "i32s" },
3038 { OPERAND_TYPE_IMM64, "i64" },
3039 { OPERAND_TYPE_IMM1, "i1" },
3040 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3041 { OPERAND_TYPE_DISP8, "d8" },
3042 { OPERAND_TYPE_DISP16, "d16" },
3043 { OPERAND_TYPE_DISP32, "d32" },
3044 { OPERAND_TYPE_DISP32S, "d32s" },
3045 { OPERAND_TYPE_DISP64, "d64" },
3046 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3047 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3048 { OPERAND_TYPE_CONTROL, "control reg" },
3049 { OPERAND_TYPE_TEST, "test reg" },
3050 { OPERAND_TYPE_DEBUG, "debug reg" },
3051 { OPERAND_TYPE_FLOATREG, "FReg" },
3052 { OPERAND_TYPE_FLOATACC, "FAcc" },
3053 { OPERAND_TYPE_SREG2, "SReg2" },
3054 { OPERAND_TYPE_SREG3, "SReg3" },
3055 { OPERAND_TYPE_ACC, "Acc" },
3056 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3057 { OPERAND_TYPE_REGMMX, "rMMX" },
3058 { OPERAND_TYPE_REGXMM, "rXMM" },
3059 { OPERAND_TYPE_REGYMM, "rYMM" },
3060 { OPERAND_TYPE_REGZMM, "rZMM" },
3061 { OPERAND_TYPE_REGMASK, "Mask reg" },
3062 { OPERAND_TYPE_ESSEG, "es" },
3066 pt (i386_operand_type t)
3069 i386_operand_type a;
3071 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3073 a = operand_type_and (t, type_names[j].mask);
3074 if (!operand_type_all_zero (&a))
3075 fprintf (stdout, "%s, ", type_names[j].name);
3080 #endif /* DEBUG386 */
3082 static bfd_reloc_code_real_type
3083 reloc (unsigned int size,
3086 bfd_reloc_code_real_type other)
3088 if (other != NO_RELOC)
3090 reloc_howto_type *rel;
3095 case BFD_RELOC_X86_64_GOT32:
3096 return BFD_RELOC_X86_64_GOT64;
3098 case BFD_RELOC_X86_64_GOTPLT64:
3099 return BFD_RELOC_X86_64_GOTPLT64;
3101 case BFD_RELOC_X86_64_PLTOFF64:
3102 return BFD_RELOC_X86_64_PLTOFF64;
3104 case BFD_RELOC_X86_64_GOTPC32:
3105 other = BFD_RELOC_X86_64_GOTPC64;
3107 case BFD_RELOC_X86_64_GOTPCREL:
3108 other = BFD_RELOC_X86_64_GOTPCREL64;
3110 case BFD_RELOC_X86_64_TPOFF32:
3111 other = BFD_RELOC_X86_64_TPOFF64;
3113 case BFD_RELOC_X86_64_DTPOFF32:
3114 other = BFD_RELOC_X86_64_DTPOFF64;
3120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3121 if (other == BFD_RELOC_SIZE32)
3124 other = BFD_RELOC_SIZE64;
3127 as_bad (_("there are no pc-relative size relocations"));
3133 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3134 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3137 rel = bfd_reloc_type_lookup (stdoutput, other);
3139 as_bad (_("unknown relocation (%u)"), other);
3140 else if (size != bfd_get_reloc_size (rel))
3141 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3142 bfd_get_reloc_size (rel),
3144 else if (pcrel && !rel->pc_relative)
3145 as_bad (_("non-pc-relative relocation for pc-relative field"));
3146 else if ((rel->complain_on_overflow == complain_overflow_signed
3148 || (rel->complain_on_overflow == complain_overflow_unsigned
3150 as_bad (_("relocated field and relocation type differ in signedness"));
3159 as_bad (_("there are no unsigned pc-relative relocations"));
3162 case 1: return BFD_RELOC_8_PCREL;
3163 case 2: return BFD_RELOC_16_PCREL;
3164 case 4: return BFD_RELOC_32_PCREL;
3165 case 8: return BFD_RELOC_64_PCREL;
3167 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3174 case 4: return BFD_RELOC_X86_64_32S;
3179 case 1: return BFD_RELOC_8;
3180 case 2: return BFD_RELOC_16;
3181 case 4: return BFD_RELOC_32;
3182 case 8: return BFD_RELOC_64;
3184 as_bad (_("cannot do %s %u byte relocation"),
3185 sign > 0 ? "signed" : "unsigned", size);
3191 /* Here we decide which fixups can be adjusted to make them relative to
3192 the beginning of the section instead of the symbol. Basically we need
3193 to make sure that the dynamic relocations are done correctly, so in
3194 some cases we force the original symbol to be used. */
3197 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3203 /* Don't adjust pc-relative references to merge sections in 64-bit
3205 if (use_rela_relocations
3206 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3210 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3211 and changed later by validate_fix. */
3212 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3213 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3216 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3217 for size relocations. */
3218 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3219 || fixP->fx_r_type == BFD_RELOC_SIZE64
3220 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3221 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3222 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3223 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3249 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3250 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3257 intel_float_operand (const char *mnemonic)
3259 /* Note that the value returned is meaningful only for opcodes with (memory)
3260 operands, hence the code here is free to improperly handle opcodes that
3261 have no operands (for better performance and smaller code). */
3263 if (mnemonic[0] != 'f')
3264 return 0; /* non-math */
3266 switch (mnemonic[1])
3268 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3269 the fs segment override prefix not currently handled because no
3270 call path can make opcodes without operands get here */
3272 return 2 /* integer op */;
3274 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3275 return 3; /* fldcw/fldenv */
3278 if (mnemonic[2] != 'o' /* fnop */)
3279 return 3; /* non-waiting control op */
3282 if (mnemonic[2] == 's')
3283 return 3; /* frstor/frstpm */
3286 if (mnemonic[2] == 'a')
3287 return 3; /* fsave */
3288 if (mnemonic[2] == 't')
3290 switch (mnemonic[3])
3292 case 'c': /* fstcw */
3293 case 'd': /* fstdw */
3294 case 'e': /* fstenv */
3295 case 's': /* fsts[gw] */
3301 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3302 return 0; /* fxsave/fxrstor are not really math ops */
3309 /* Build the VEX prefix. */
3312 build_vex_prefix (const insn_template *t)
3314 unsigned int register_specifier;
3315 unsigned int implied_prefix;
3316 unsigned int vector_length;
3318 /* Check register specifier. */
3319 if (i.vex.register_specifier)
3321 register_specifier =
3322 ~register_number (i.vex.register_specifier) & 0xf;
3323 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3326 register_specifier = 0xf;
3328 /* Use 2-byte VEX prefix by swapping destination and source
3330 if (i.vec_encoding != vex_encoding_vex3
3331 && i.dir_encoding == dir_encoding_default
3332 && i.operands == i.reg_operands
3333 && i.tm.opcode_modifier.vexopcode == VEX0F
3334 && i.tm.opcode_modifier.load
3337 unsigned int xchg = i.operands - 1;
3338 union i386_op temp_op;
3339 i386_operand_type temp_type;
3341 temp_type = i.types[xchg];
3342 i.types[xchg] = i.types[0];
3343 i.types[0] = temp_type;
3344 temp_op = i.op[xchg];
3345 i.op[xchg] = i.op[0];
3348 gas_assert (i.rm.mode == 3);
3352 i.rm.regmem = i.rm.reg;
3355 /* Use the next insn. */
3359 if (i.tm.opcode_modifier.vex == VEXScalar)
3360 vector_length = avxscalar;
3361 else if (i.tm.opcode_modifier.vex == VEX256)
3367 /* Determine vector length from the last multi-length vector
3370 for (op = t->operands; op--;)
3371 if (t->operand_types[op].bitfield.xmmword
3372 && t->operand_types[op].bitfield.ymmword
3373 && i.types[op].bitfield.ymmword)
3380 switch ((i.tm.base_opcode >> 8) & 0xff)
3385 case DATA_PREFIX_OPCODE:
3388 case REPE_PREFIX_OPCODE:
3391 case REPNE_PREFIX_OPCODE:
3398 /* Use 2-byte VEX prefix if possible. */
3399 if (i.vec_encoding != vex_encoding_vex3
3400 && i.tm.opcode_modifier.vexopcode == VEX0F
3401 && i.tm.opcode_modifier.vexw != VEXW1
3402 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3404 /* 2-byte VEX prefix. */
3408 i.vex.bytes[0] = 0xc5;
3410 /* Check the REX.R bit. */
3411 r = (i.rex & REX_R) ? 0 : 1;
3412 i.vex.bytes[1] = (r << 7
3413 | register_specifier << 3
3414 | vector_length << 2
3419 /* 3-byte VEX prefix. */
3424 switch (i.tm.opcode_modifier.vexopcode)
3428 i.vex.bytes[0] = 0xc4;
3432 i.vex.bytes[0] = 0xc4;
3436 i.vex.bytes[0] = 0xc4;
3440 i.vex.bytes[0] = 0x8f;
3444 i.vex.bytes[0] = 0x8f;
3448 i.vex.bytes[0] = 0x8f;
3454 /* The high 3 bits of the second VEX byte are 1's compliment
3455 of RXB bits from REX. */
3456 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3458 /* Check the REX.W bit. */
3459 w = (i.rex & REX_W) ? 1 : 0;
3460 if (i.tm.opcode_modifier.vexw == VEXW1)
3463 i.vex.bytes[2] = (w << 7
3464 | register_specifier << 3
3465 | vector_length << 2
3470 static INLINE bfd_boolean
3471 is_evex_encoding (const insn_template *t)
3473 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3474 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3475 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3478 /* Build the EVEX prefix. */
3481 build_evex_prefix (void)
3483 unsigned int register_specifier;
3484 unsigned int implied_prefix;
3486 rex_byte vrex_used = 0;
3488 /* Check register specifier. */
3489 if (i.vex.register_specifier)
3491 gas_assert ((i.vrex & REX_X) == 0);
3493 register_specifier = i.vex.register_specifier->reg_num;
3494 if ((i.vex.register_specifier->reg_flags & RegRex))
3495 register_specifier += 8;
3496 /* The upper 16 registers are encoded in the fourth byte of the
3498 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3499 i.vex.bytes[3] = 0x8;
3500 register_specifier = ~register_specifier & 0xf;
3504 register_specifier = 0xf;
3506 /* Encode upper 16 vector index register in the fourth byte of
3508 if (!(i.vrex & REX_X))
3509 i.vex.bytes[3] = 0x8;
3514 switch ((i.tm.base_opcode >> 8) & 0xff)
3519 case DATA_PREFIX_OPCODE:
3522 case REPE_PREFIX_OPCODE:
3525 case REPNE_PREFIX_OPCODE:
3532 /* 4 byte EVEX prefix. */
3534 i.vex.bytes[0] = 0x62;
3537 switch (i.tm.opcode_modifier.vexopcode)
3553 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3555 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3557 /* The fifth bit of the second EVEX byte is 1's compliment of the
3558 REX_R bit in VREX. */
3559 if (!(i.vrex & REX_R))
3560 i.vex.bytes[1] |= 0x10;
3564 if ((i.reg_operands + i.imm_operands) == i.operands)
3566 /* When all operands are registers, the REX_X bit in REX is not
3567 used. We reuse it to encode the upper 16 registers, which is
3568 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3569 as 1's compliment. */
3570 if ((i.vrex & REX_B))
3573 i.vex.bytes[1] &= ~0x40;
3577 /* EVEX instructions shouldn't need the REX prefix. */
3578 i.vrex &= ~vrex_used;
3579 gas_assert (i.vrex == 0);
3581 /* Check the REX.W bit. */
3582 w = (i.rex & REX_W) ? 1 : 0;
3583 if (i.tm.opcode_modifier.vexw)
3585 if (i.tm.opcode_modifier.vexw == VEXW1)
3588 /* If w is not set it means we are dealing with WIG instruction. */
3591 if (evexwig == evexw1)
3595 /* Encode the U bit. */
3596 implied_prefix |= 0x4;
3598 /* The third byte of the EVEX prefix. */
3599 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3601 /* The fourth byte of the EVEX prefix. */
3602 /* The zeroing-masking bit. */
3603 if (i.mask && i.mask->zeroing)
3604 i.vex.bytes[3] |= 0x80;
3606 /* Don't always set the broadcast bit if there is no RC. */
3609 /* Encode the vector length. */
3610 unsigned int vec_length;
3612 if (!i.tm.opcode_modifier.evex
3613 || i.tm.opcode_modifier.evex == EVEXDYN)
3617 /* Determine vector length from the last multi-length vector
3620 for (op = i.operands; op--;)
3621 if (i.tm.operand_types[op].bitfield.xmmword
3622 + i.tm.operand_types[op].bitfield.ymmword
3623 + i.tm.operand_types[op].bitfield.zmmword > 1)
3625 if (i.types[op].bitfield.zmmword)
3627 i.tm.opcode_modifier.evex = EVEX512;
3630 else if (i.types[op].bitfield.ymmword)
3632 i.tm.opcode_modifier.evex = EVEX256;
3635 else if (i.types[op].bitfield.xmmword)
3637 i.tm.opcode_modifier.evex = EVEX128;
3640 else if (i.broadcast && (int) op == i.broadcast->operand)
3642 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3643 * i.broadcast->type)
3646 i.tm.opcode_modifier.evex = EVEX512;
3649 i.tm.opcode_modifier.evex = EVEX256;
3652 i.tm.opcode_modifier.evex = EVEX128;
3661 if (op >= MAX_OPERANDS)
3665 switch (i.tm.opcode_modifier.evex)
3667 case EVEXLIG: /* LL' is ignored */
3668 vec_length = evexlig << 5;
3671 vec_length = 0 << 5;
3674 vec_length = 1 << 5;
3677 vec_length = 2 << 5;
3683 i.vex.bytes[3] |= vec_length;
3684 /* Encode the broadcast bit. */
3686 i.vex.bytes[3] |= 0x10;
3690 if (i.rounding->type != saeonly)
3691 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3693 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3696 if (i.mask && i.mask->mask)
3697 i.vex.bytes[3] |= i.mask->mask->reg_num;
3701 process_immext (void)
3705 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3708 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3709 with an opcode suffix which is coded in the same place as an
3710 8-bit immediate field would be.
3711 Here we check those operands and remove them afterwards. */
3714 for (x = 0; x < i.operands; x++)
3715 if (register_number (i.op[x].regs) != x)
3716 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3717 register_prefix, i.op[x].regs->reg_name, x + 1,
3723 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3725 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3726 suffix which is coded in the same place as an 8-bit immediate
3728 Here we check those operands and remove them afterwards. */
3731 if (i.operands != 3)
3734 for (x = 0; x < 2; x++)
3735 if (register_number (i.op[x].regs) != x)
3736 goto bad_register_operand;
3738 /* Check for third operand for mwaitx/monitorx insn. */
3739 if (register_number (i.op[x].regs)
3740 != (x + (i.tm.extension_opcode == 0xfb)))
3742 bad_register_operand:
3743 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3744 register_prefix, i.op[x].regs->reg_name, x+1,
3751 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3752 which is coded in the same place as an 8-bit immediate field
3753 would be. Here we fake an 8-bit immediate operand from the
3754 opcode suffix stored in tm.extension_opcode.
3756 AVX instructions also use this encoding, for some of
3757 3 argument instructions. */
3759 gas_assert (i.imm_operands <= 1
3761 || ((i.tm.opcode_modifier.vex
3762 || i.tm.opcode_modifier.vexopcode
3763 || is_evex_encoding (&i.tm))
3764 && i.operands <= 4)));
3766 exp = &im_expressions[i.imm_operands++];
3767 i.op[i.operands].imms = exp;
3768 i.types[i.operands] = imm8;
3770 exp->X_op = O_constant;
3771 exp->X_add_number = i.tm.extension_opcode;
3772 i.tm.extension_opcode = None;
3779 switch (i.tm.opcode_modifier.hleprefixok)
3784 as_bad (_("invalid instruction `%s' after `%s'"),
3785 i.tm.name, i.hle_prefix);
3788 if (i.prefix[LOCK_PREFIX])
3790 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3794 case HLEPrefixRelease:
3795 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3797 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3801 if (i.mem_operands == 0
3802 || !operand_type_check (i.types[i.operands - 1], anymem))
3804 as_bad (_("memory destination needed for instruction `%s'"
3805 " after `xrelease'"), i.tm.name);
3812 /* Try the shortest encoding by shortening operand size. */
3815 optimize_encoding (void)
3819 if (optimize_for_space
3820 && i.reg_operands == 1
3821 && i.imm_operands == 1
3822 && !i.types[1].bitfield.byte
3823 && i.op[0].imms->X_op == O_constant
3824 && fits_in_imm7 (i.op[0].imms->X_add_number)
3825 && ((i.tm.base_opcode == 0xa8
3826 && i.tm.extension_opcode == None)
3827 || (i.tm.base_opcode == 0xf6
3828 && i.tm.extension_opcode == 0x0)))
3831 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3833 unsigned int base_regnum = i.op[1].regs->reg_num;
3834 if (flag_code == CODE_64BIT || base_regnum < 4)
3836 i.types[1].bitfield.byte = 1;
3837 /* Ignore the suffix. */
3839 if (base_regnum >= 4
3840 && !(i.op[1].regs->reg_flags & RegRex))
3842 /* Handle SP, BP, SI and DI registers. */
3843 if (i.types[1].bitfield.word)
3845 else if (i.types[1].bitfield.dword)
3853 else if (flag_code == CODE_64BIT
3854 && ((i.types[1].bitfield.qword
3855 && i.reg_operands == 1
3856 && i.imm_operands == 1
3857 && i.op[0].imms->X_op == O_constant
3858 && ((i.tm.base_opcode == 0xb0
3859 && i.tm.extension_opcode == None
3860 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3861 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3862 && (((i.tm.base_opcode == 0x24
3863 || i.tm.base_opcode == 0xa8)
3864 && i.tm.extension_opcode == None)
3865 || (i.tm.base_opcode == 0x80
3866 && i.tm.extension_opcode == 0x4)
3867 || ((i.tm.base_opcode == 0xf6
3868 || i.tm.base_opcode == 0xc6)
3869 && i.tm.extension_opcode == 0x0)))))
3870 || (i.types[0].bitfield.qword
3871 && ((i.reg_operands == 2
3872 && i.op[0].regs == i.op[1].regs
3873 && ((i.tm.base_opcode == 0x30
3874 || i.tm.base_opcode == 0x28)
3875 && i.tm.extension_opcode == None))
3876 || (i.reg_operands == 1
3878 && i.tm.base_opcode == 0x30
3879 && i.tm.extension_opcode == None)))))
3882 andq $imm31, %r64 -> andl $imm31, %r32
3883 testq $imm31, %r64 -> testl $imm31, %r32
3884 xorq %r64, %r64 -> xorl %r32, %r32
3885 subq %r64, %r64 -> subl %r32, %r32
3886 movq $imm31, %r64 -> movl $imm31, %r32
3887 movq $imm32, %r64 -> movl $imm32, %r32
3889 i.tm.opcode_modifier.norex64 = 1;
3890 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3896 i.tm.operand_types[0].bitfield.imm32 = 1;
3897 i.tm.operand_types[0].bitfield.imm32s = 0;
3898 i.tm.operand_types[0].bitfield.imm64 = 0;
3899 i.types[0].bitfield.imm32 = 1;
3900 i.types[0].bitfield.imm32s = 0;
3901 i.types[0].bitfield.imm64 = 0;
3902 i.types[1].bitfield.dword = 1;
3903 i.types[1].bitfield.qword = 0;
3904 if (i.tm.base_opcode == 0xc6)
3907 movq $imm31, %r64 -> movl $imm31, %r32
3909 i.tm.base_opcode = 0xb0;
3910 i.tm.extension_opcode = None;
3911 i.tm.opcode_modifier.shortform = 1;
3912 i.tm.opcode_modifier.modrm = 0;
3916 else if (optimize > 1
3917 && i.reg_operands == 3
3918 && i.op[0].regs == i.op[1].regs
3919 && !i.types[2].bitfield.xmmword
3920 && (i.tm.opcode_modifier.vex
3921 || ((!i.mask || i.mask->zeroing)
3923 && is_evex_encoding (&i.tm)
3924 && (i.vec_encoding != vex_encoding_evex
3925 || i.tm.cpu_flags.bitfield.cpuavx512vl
3926 || (i.tm.operand_types[2].bitfield.zmmword
3927 && i.types[2].bitfield.ymmword)
3928 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3929 && ((i.tm.base_opcode == 0x55
3930 || i.tm.base_opcode == 0x6655
3931 || i.tm.base_opcode == 0x66df
3932 || i.tm.base_opcode == 0x57
3933 || i.tm.base_opcode == 0x6657
3934 || i.tm.base_opcode == 0x66ef
3935 || i.tm.base_opcode == 0x66f8
3936 || i.tm.base_opcode == 0x66f9
3937 || i.tm.base_opcode == 0x66fa
3938 || i.tm.base_opcode == 0x66fb)
3939 && i.tm.extension_opcode == None))
3942 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3944 EVEX VOP %zmmM, %zmmM, %zmmN
3945 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3946 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3947 EVEX VOP %ymmM, %ymmM, %ymmN
3948 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3949 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3950 VEX VOP %ymmM, %ymmM, %ymmN
3951 -> VEX VOP %xmmM, %xmmM, %xmmN
3952 VOP, one of vpandn and vpxor:
3953 VEX VOP %ymmM, %ymmM, %ymmN
3954 -> VEX VOP %xmmM, %xmmM, %xmmN
3955 VOP, one of vpandnd and vpandnq:
3956 EVEX VOP %zmmM, %zmmM, %zmmN
3957 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3958 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3959 EVEX VOP %ymmM, %ymmM, %ymmN
3960 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3961 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3962 VOP, one of vpxord and vpxorq:
3963 EVEX VOP %zmmM, %zmmM, %zmmN
3964 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3965 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3966 EVEX VOP %ymmM, %ymmM, %ymmN
3967 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3968 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3970 if (is_evex_encoding (&i.tm))
3972 if (i.vec_encoding == vex_encoding_evex)
3973 i.tm.opcode_modifier.evex = EVEX128;
3976 i.tm.opcode_modifier.vex = VEX128;
3977 i.tm.opcode_modifier.vexw = VEXW0;
3978 i.tm.opcode_modifier.evex = 0;
3982 i.tm.opcode_modifier.vex = VEX128;
3984 if (i.tm.opcode_modifier.vex)
3985 for (j = 0; j < 3; j++)
3987 i.types[j].bitfield.xmmword = 1;
3988 i.types[j].bitfield.ymmword = 0;
3993 /* This is the guts of the machine-dependent assembler. LINE points to a
3994 machine dependent instruction. This function is supposed to emit
3995 the frags/bytes it assembles to. */
3998 md_assemble (char *line)
4001 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4002 const insn_template *t;
4004 /* Initialize globals. */
4005 memset (&i, '\0', sizeof (i));
4006 for (j = 0; j < MAX_OPERANDS; j++)
4007 i.reloc[j] = NO_RELOC;
4008 memset (disp_expressions, '\0', sizeof (disp_expressions));
4009 memset (im_expressions, '\0', sizeof (im_expressions));
4010 save_stack_p = save_stack;
4012 /* First parse an instruction mnemonic & call i386_operand for the operands.
4013 We assume that the scrubber has arranged it so that line[0] is the valid
4014 start of a (possibly prefixed) mnemonic. */
4016 line = parse_insn (line, mnemonic);
4019 mnem_suffix = i.suffix;
4021 line = parse_operands (line, mnemonic);
4023 xfree (i.memop1_string);
4024 i.memop1_string = NULL;
4028 /* Now we've parsed the mnemonic into a set of templates, and have the
4029 operands at hand. */
4031 /* All intel opcodes have reversed operands except for "bound" and
4032 "enter". We also don't reverse intersegment "jmp" and "call"
4033 instructions with 2 immediate operands so that the immediate segment
4034 precedes the offset, as it does when in AT&T mode. */
4037 && (strcmp (mnemonic, "bound") != 0)
4038 && (strcmp (mnemonic, "invlpga") != 0)
4039 && !(operand_type_check (i.types[0], imm)
4040 && operand_type_check (i.types[1], imm)))
4043 /* The order of the immediates should be reversed
4044 for 2 immediates extrq and insertq instructions */
4045 if (i.imm_operands == 2
4046 && (strcmp (mnemonic, "extrq") == 0
4047 || strcmp (mnemonic, "insertq") == 0))
4048 swap_2_operands (0, 1);
4053 /* Don't optimize displacement for movabs since it only takes 64bit
4056 && i.disp_encoding != disp_encoding_32bit
4057 && (flag_code != CODE_64BIT
4058 || strcmp (mnemonic, "movabs") != 0))
4061 /* Next, we find a template that matches the given insn,
4062 making sure the overlap of the given operands types is consistent
4063 with the template operand types. */
4065 if (!(t = match_template (mnem_suffix)))
4068 if (sse_check != check_none
4069 && !i.tm.opcode_modifier.noavx
4070 && !i.tm.cpu_flags.bitfield.cpuavx
4071 && (i.tm.cpu_flags.bitfield.cpusse
4072 || i.tm.cpu_flags.bitfield.cpusse2
4073 || i.tm.cpu_flags.bitfield.cpusse3
4074 || i.tm.cpu_flags.bitfield.cpussse3
4075 || i.tm.cpu_flags.bitfield.cpusse4_1
4076 || i.tm.cpu_flags.bitfield.cpusse4_2
4077 || i.tm.cpu_flags.bitfield.cpupclmul
4078 || i.tm.cpu_flags.bitfield.cpuaes
4079 || i.tm.cpu_flags.bitfield.cpugfni))
4081 (sse_check == check_warning
4083 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4086 /* Zap movzx and movsx suffix. The suffix has been set from
4087 "word ptr" or "byte ptr" on the source operand in Intel syntax
4088 or extracted from mnemonic in AT&T syntax. But we'll use
4089 the destination register to choose the suffix for encoding. */
4090 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4092 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4093 there is no suffix, the default will be byte extension. */
4094 if (i.reg_operands != 2
4097 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4102 if (i.tm.opcode_modifier.fwait)
4103 if (!add_prefix (FWAIT_OPCODE))
4106 /* Check if REP prefix is OK. */
4107 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4109 as_bad (_("invalid instruction `%s' after `%s'"),
4110 i.tm.name, i.rep_prefix);
4114 /* Check for lock without a lockable instruction. Destination operand
4115 must be memory unless it is xchg (0x86). */
4116 if (i.prefix[LOCK_PREFIX]
4117 && (!i.tm.opcode_modifier.islockable
4118 || i.mem_operands == 0
4119 || (i.tm.base_opcode != 0x86
4120 && !operand_type_check (i.types[i.operands - 1], anymem))))
4122 as_bad (_("expecting lockable instruction after `lock'"));
4126 /* Check if HLE prefix is OK. */
4127 if (i.hle_prefix && !check_hle ())
4130 /* Check BND prefix. */
4131 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4132 as_bad (_("expecting valid branch instruction after `bnd'"));
4134 /* Check NOTRACK prefix. */
4135 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4136 as_bad (_("expecting indirect branch instruction after `notrack'"));
4138 if (i.tm.cpu_flags.bitfield.cpumpx)
4140 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4141 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4142 else if (flag_code != CODE_16BIT
4143 ? i.prefix[ADDR_PREFIX]
4144 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4145 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4148 /* Insert BND prefix. */
4149 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4151 if (!i.prefix[BND_PREFIX])
4152 add_prefix (BND_PREFIX_OPCODE);
4153 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4155 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4156 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4160 /* Check string instruction segment overrides. */
4161 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4163 if (!check_string ())
4165 i.disp_operands = 0;
4168 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4169 optimize_encoding ();
4171 if (!process_suffix ())
4174 /* Update operand types. */
4175 for (j = 0; j < i.operands; j++)
4176 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4178 /* Make still unresolved immediate matches conform to size of immediate
4179 given in i.suffix. */
4180 if (!finalize_imm ())
4183 if (i.types[0].bitfield.imm1)
4184 i.imm_operands = 0; /* kludge for shift insns. */
4186 /* We only need to check those implicit registers for instructions
4187 with 3 operands or less. */
4188 if (i.operands <= 3)
4189 for (j = 0; j < i.operands; j++)
4190 if (i.types[j].bitfield.inoutportreg
4191 || i.types[j].bitfield.shiftcount
4192 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4195 /* ImmExt should be processed after SSE2AVX. */
4196 if (!i.tm.opcode_modifier.sse2avx
4197 && i.tm.opcode_modifier.immext)
4200 /* For insns with operands there are more diddles to do to the opcode. */
4203 if (!process_operands ())
4206 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4208 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4209 as_warn (_("translating to `%sp'"), i.tm.name);
4212 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4213 || is_evex_encoding (&i.tm))
4215 if (flag_code == CODE_16BIT)
4217 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4222 if (i.tm.opcode_modifier.vex)
4223 build_vex_prefix (t);
4225 build_evex_prefix ();
4228 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4229 instructions may define INT_OPCODE as well, so avoid this corner
4230 case for those instructions that use MODRM. */
4231 if (i.tm.base_opcode == INT_OPCODE
4232 && !i.tm.opcode_modifier.modrm
4233 && i.op[0].imms->X_add_number == 3)
4235 i.tm.base_opcode = INT3_OPCODE;
4239 if ((i.tm.opcode_modifier.jump
4240 || i.tm.opcode_modifier.jumpbyte
4241 || i.tm.opcode_modifier.jumpdword)
4242 && i.op[0].disps->X_op == O_constant)
4244 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4245 the absolute address given by the constant. Since ix86 jumps and
4246 calls are pc relative, we need to generate a reloc. */
4247 i.op[0].disps->X_add_symbol = &abs_symbol;
4248 i.op[0].disps->X_op = O_symbol;
4251 if (i.tm.opcode_modifier.rex64)
4254 /* For 8 bit registers we need an empty rex prefix. Also if the
4255 instruction already has a prefix, we need to convert old
4256 registers to new ones. */
4258 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4259 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4260 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4261 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4262 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4263 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4268 i.rex |= REX_OPCODE;
4269 for (x = 0; x < 2; x++)
4271 /* Look for 8 bit operand that uses old registers. */
4272 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4273 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4275 /* In case it is "hi" register, give up. */
4276 if (i.op[x].regs->reg_num > 3)
4277 as_bad (_("can't encode register '%s%s' in an "
4278 "instruction requiring REX prefix."),
4279 register_prefix, i.op[x].regs->reg_name);
4281 /* Otherwise it is equivalent to the extended register.
4282 Since the encoding doesn't change this is merely
4283 cosmetic cleanup for debug output. */
4285 i.op[x].regs = i.op[x].regs + 8;
4290 if (i.rex == 0 && i.rex_encoding)
4292 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4293 that uses legacy register. If it is "hi" register, don't add
4294 the REX_OPCODE byte. */
4296 for (x = 0; x < 2; x++)
4297 if (i.types[x].bitfield.reg
4298 && i.types[x].bitfield.byte
4299 && (i.op[x].regs->reg_flags & RegRex64) == 0
4300 && i.op[x].regs->reg_num > 3)
4302 i.rex_encoding = FALSE;
4311 add_prefix (REX_OPCODE | i.rex);
4313 /* We are ready to output the insn. */
4318 parse_insn (char *line, char *mnemonic)
4321 char *token_start = l;
4324 const insn_template *t;
4330 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4335 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4337 as_bad (_("no such instruction: `%s'"), token_start);
4342 if (!is_space_char (*l)
4343 && *l != END_OF_INSN
4345 || (*l != PREFIX_SEPARATOR
4348 as_bad (_("invalid character %s in mnemonic"),
4349 output_invalid (*l));
4352 if (token_start == l)
4354 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4355 as_bad (_("expecting prefix; got nothing"));
4357 as_bad (_("expecting mnemonic; got nothing"));
4361 /* Look up instruction (or prefix) via hash table. */
4362 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4364 if (*l != END_OF_INSN
4365 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4366 && current_templates
4367 && current_templates->start->opcode_modifier.isprefix)
4369 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4371 as_bad ((flag_code != CODE_64BIT
4372 ? _("`%s' is only supported in 64-bit mode")
4373 : _("`%s' is not supported in 64-bit mode")),
4374 current_templates->start->name);
4377 /* If we are in 16-bit mode, do not allow addr16 or data16.
4378 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4379 if ((current_templates->start->opcode_modifier.size16
4380 || current_templates->start->opcode_modifier.size32)
4381 && flag_code != CODE_64BIT
4382 && (current_templates->start->opcode_modifier.size32
4383 ^ (flag_code == CODE_16BIT)))
4385 as_bad (_("redundant %s prefix"),
4386 current_templates->start->name);
4389 if (current_templates->start->opcode_length == 0)
4391 /* Handle pseudo prefixes. */
4392 switch (current_templates->start->base_opcode)
4396 i.disp_encoding = disp_encoding_8bit;
4400 i.disp_encoding = disp_encoding_32bit;
4404 i.dir_encoding = dir_encoding_load;
4408 i.dir_encoding = dir_encoding_store;
4412 i.vec_encoding = vex_encoding_vex2;
4416 i.vec_encoding = vex_encoding_vex3;
4420 i.vec_encoding = vex_encoding_evex;
4424 i.rex_encoding = TRUE;
4428 i.no_optimize = TRUE;
4436 /* Add prefix, checking for repeated prefixes. */
4437 switch (add_prefix (current_templates->start->base_opcode))
4442 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4443 i.notrack_prefix = current_templates->start->name;
4446 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4447 i.hle_prefix = current_templates->start->name;
4448 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4449 i.bnd_prefix = current_templates->start->name;
4451 i.rep_prefix = current_templates->start->name;
4457 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4464 if (!current_templates)
4466 /* Check if we should swap operand or force 32bit displacement in
4468 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4469 i.dir_encoding = dir_encoding_store;
4470 else if (mnem_p - 3 == dot_p
4473 i.disp_encoding = disp_encoding_8bit;
4474 else if (mnem_p - 4 == dot_p
4478 i.disp_encoding = disp_encoding_32bit;
4483 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4486 if (!current_templates)
4489 /* See if we can get a match by trimming off a suffix. */
4492 case WORD_MNEM_SUFFIX:
4493 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4494 i.suffix = SHORT_MNEM_SUFFIX;
4497 case BYTE_MNEM_SUFFIX:
4498 case QWORD_MNEM_SUFFIX:
4499 i.suffix = mnem_p[-1];
4501 current_templates = (const templates *) hash_find (op_hash,
4504 case SHORT_MNEM_SUFFIX:
4505 case LONG_MNEM_SUFFIX:
4508 i.suffix = mnem_p[-1];
4510 current_templates = (const templates *) hash_find (op_hash,
4519 if (intel_float_operand (mnemonic) == 1)
4520 i.suffix = SHORT_MNEM_SUFFIX;
4522 i.suffix = LONG_MNEM_SUFFIX;
4524 current_templates = (const templates *) hash_find (op_hash,
4529 if (!current_templates)
4531 as_bad (_("no such instruction: `%s'"), token_start);
4536 if (current_templates->start->opcode_modifier.jump
4537 || current_templates->start->opcode_modifier.jumpbyte)
4539 /* Check for a branch hint. We allow ",pt" and ",pn" for
4540 predict taken and predict not taken respectively.
4541 I'm not sure that branch hints actually do anything on loop
4542 and jcxz insns (JumpByte) for current Pentium4 chips. They
4543 may work in the future and it doesn't hurt to accept them
4545 if (l[0] == ',' && l[1] == 'p')
4549 if (!add_prefix (DS_PREFIX_OPCODE))
4553 else if (l[2] == 'n')
4555 if (!add_prefix (CS_PREFIX_OPCODE))
4561 /* Any other comma loses. */
4564 as_bad (_("invalid character %s in mnemonic"),
4565 output_invalid (*l));
4569 /* Check if instruction is supported on specified architecture. */
4571 for (t = current_templates->start; t < current_templates->end; ++t)
4573 supported |= cpu_flags_match (t);
4574 if (supported == CPU_FLAGS_PERFECT_MATCH)
4576 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4577 as_warn (_("use .code16 to ensure correct addressing mode"));
4583 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4584 as_bad (flag_code == CODE_64BIT
4585 ? _("`%s' is not supported in 64-bit mode")
4586 : _("`%s' is only supported in 64-bit mode"),
4587 current_templates->start->name);
4589 as_bad (_("`%s' is not supported on `%s%s'"),
4590 current_templates->start->name,
4591 cpu_arch_name ? cpu_arch_name : default_arch,
4592 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4598 parse_operands (char *l, const char *mnemonic)
4602 /* 1 if operand is pending after ','. */
4603 unsigned int expecting_operand = 0;
4605 /* Non-zero if operand parens not balanced. */
4606 unsigned int paren_not_balanced;
4608 while (*l != END_OF_INSN)
4610 /* Skip optional white space before operand. */
4611 if (is_space_char (*l))
4613 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4615 as_bad (_("invalid character %s before operand %d"),
4616 output_invalid (*l),
4620 token_start = l; /* After white space. */
4621 paren_not_balanced = 0;
4622 while (paren_not_balanced || *l != ',')
4624 if (*l == END_OF_INSN)
4626 if (paren_not_balanced)
4629 as_bad (_("unbalanced parenthesis in operand %d."),
4632 as_bad (_("unbalanced brackets in operand %d."),
4637 break; /* we are done */
4639 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4641 as_bad (_("invalid character %s in operand %d"),
4642 output_invalid (*l),
4649 ++paren_not_balanced;
4651 --paren_not_balanced;
4656 ++paren_not_balanced;
4658 --paren_not_balanced;
4662 if (l != token_start)
4663 { /* Yes, we've read in another operand. */
4664 unsigned int operand_ok;
4665 this_operand = i.operands++;
4666 if (i.operands > MAX_OPERANDS)
4668 as_bad (_("spurious operands; (%d operands/instruction max)"),
4672 i.types[this_operand].bitfield.unspecified = 1;
4673 /* Now parse operand adding info to 'i' as we go along. */
4674 END_STRING_AND_SAVE (l);
4678 i386_intel_operand (token_start,
4679 intel_float_operand (mnemonic));
4681 operand_ok = i386_att_operand (token_start);
4683 RESTORE_END_STRING (l);
4689 if (expecting_operand)
4691 expecting_operand_after_comma:
4692 as_bad (_("expecting operand after ','; got nothing"));
4697 as_bad (_("expecting operand before ','; got nothing"));
4702 /* Now *l must be either ',' or END_OF_INSN. */
4705 if (*++l == END_OF_INSN)
4707 /* Just skip it, if it's \n complain. */
4708 goto expecting_operand_after_comma;
4710 expecting_operand = 1;
4717 swap_2_operands (int xchg1, int xchg2)
4719 union i386_op temp_op;
4720 i386_operand_type temp_type;
4721 enum bfd_reloc_code_real temp_reloc;
4723 temp_type = i.types[xchg2];
4724 i.types[xchg2] = i.types[xchg1];
4725 i.types[xchg1] = temp_type;
4726 temp_op = i.op[xchg2];
4727 i.op[xchg2] = i.op[xchg1];
4728 i.op[xchg1] = temp_op;
4729 temp_reloc = i.reloc[xchg2];
4730 i.reloc[xchg2] = i.reloc[xchg1];
4731 i.reloc[xchg1] = temp_reloc;
4735 if (i.mask->operand == xchg1)
4736 i.mask->operand = xchg2;
4737 else if (i.mask->operand == xchg2)
4738 i.mask->operand = xchg1;
4742 if (i.broadcast->operand == xchg1)
4743 i.broadcast->operand = xchg2;
4744 else if (i.broadcast->operand == xchg2)
4745 i.broadcast->operand = xchg1;
4749 if (i.rounding->operand == xchg1)
4750 i.rounding->operand = xchg2;
4751 else if (i.rounding->operand == xchg2)
4752 i.rounding->operand = xchg1;
4757 swap_operands (void)
4763 swap_2_operands (1, i.operands - 2);
4767 swap_2_operands (0, i.operands - 1);
4773 if (i.mem_operands == 2)
4775 const seg_entry *temp_seg;
4776 temp_seg = i.seg[0];
4777 i.seg[0] = i.seg[1];
4778 i.seg[1] = temp_seg;
4782 /* Try to ensure constant immediates are represented in the smallest
4787 char guess_suffix = 0;
4791 guess_suffix = i.suffix;
4792 else if (i.reg_operands)
4794 /* Figure out a suffix from the last register operand specified.
4795 We can't do this properly yet, ie. excluding InOutPortReg,
4796 but the following works for instructions with immediates.
4797 In any case, we can't set i.suffix yet. */
4798 for (op = i.operands; --op >= 0;)
4799 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4801 guess_suffix = BYTE_MNEM_SUFFIX;
4804 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4806 guess_suffix = WORD_MNEM_SUFFIX;
4809 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4811 guess_suffix = LONG_MNEM_SUFFIX;
4814 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4816 guess_suffix = QWORD_MNEM_SUFFIX;
4820 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4821 guess_suffix = WORD_MNEM_SUFFIX;
4823 for (op = i.operands; --op >= 0;)
4824 if (operand_type_check (i.types[op], imm))
4826 switch (i.op[op].imms->X_op)
4829 /* If a suffix is given, this operand may be shortened. */
4830 switch (guess_suffix)
4832 case LONG_MNEM_SUFFIX:
4833 i.types[op].bitfield.imm32 = 1;
4834 i.types[op].bitfield.imm64 = 1;
4836 case WORD_MNEM_SUFFIX:
4837 i.types[op].bitfield.imm16 = 1;
4838 i.types[op].bitfield.imm32 = 1;
4839 i.types[op].bitfield.imm32s = 1;
4840 i.types[op].bitfield.imm64 = 1;
4842 case BYTE_MNEM_SUFFIX:
4843 i.types[op].bitfield.imm8 = 1;
4844 i.types[op].bitfield.imm8s = 1;
4845 i.types[op].bitfield.imm16 = 1;
4846 i.types[op].bitfield.imm32 = 1;
4847 i.types[op].bitfield.imm32s = 1;
4848 i.types[op].bitfield.imm64 = 1;
4852 /* If this operand is at most 16 bits, convert it
4853 to a signed 16 bit number before trying to see
4854 whether it will fit in an even smaller size.
4855 This allows a 16-bit operand such as $0xffe0 to
4856 be recognised as within Imm8S range. */
4857 if ((i.types[op].bitfield.imm16)
4858 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4860 i.op[op].imms->X_add_number =
4861 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4864 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4865 if ((i.types[op].bitfield.imm32)
4866 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4869 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4870 ^ ((offsetT) 1 << 31))
4871 - ((offsetT) 1 << 31));
4875 = operand_type_or (i.types[op],
4876 smallest_imm_type (i.op[op].imms->X_add_number));
4878 /* We must avoid matching of Imm32 templates when 64bit
4879 only immediate is available. */
4880 if (guess_suffix == QWORD_MNEM_SUFFIX)
4881 i.types[op].bitfield.imm32 = 0;
4888 /* Symbols and expressions. */
4890 /* Convert symbolic operand to proper sizes for matching, but don't
4891 prevent matching a set of insns that only supports sizes other
4892 than those matching the insn suffix. */
4894 i386_operand_type mask, allowed;
4895 const insn_template *t;
4897 operand_type_set (&mask, 0);
4898 operand_type_set (&allowed, 0);
4900 for (t = current_templates->start;
4901 t < current_templates->end;
4903 allowed = operand_type_or (allowed,
4904 t->operand_types[op]);
4905 switch (guess_suffix)
4907 case QWORD_MNEM_SUFFIX:
4908 mask.bitfield.imm64 = 1;
4909 mask.bitfield.imm32s = 1;
4911 case LONG_MNEM_SUFFIX:
4912 mask.bitfield.imm32 = 1;
4914 case WORD_MNEM_SUFFIX:
4915 mask.bitfield.imm16 = 1;
4917 case BYTE_MNEM_SUFFIX:
4918 mask.bitfield.imm8 = 1;
4923 allowed = operand_type_and (mask, allowed);
4924 if (!operand_type_all_zero (&allowed))
4925 i.types[op] = operand_type_and (i.types[op], mask);
4932 /* Try to use the smallest displacement type too. */
4934 optimize_disp (void)
4938 for (op = i.operands; --op >= 0;)
4939 if (operand_type_check (i.types[op], disp))
4941 if (i.op[op].disps->X_op == O_constant)
4943 offsetT op_disp = i.op[op].disps->X_add_number;
4945 if (i.types[op].bitfield.disp16
4946 && (op_disp & ~(offsetT) 0xffff) == 0)
4948 /* If this operand is at most 16 bits, convert
4949 to a signed 16 bit number and don't use 64bit
4951 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4952 i.types[op].bitfield.disp64 = 0;
4955 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4956 if (i.types[op].bitfield.disp32
4957 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4959 /* If this operand is at most 32 bits, convert
4960 to a signed 32 bit number and don't use 64bit
4962 op_disp &= (((offsetT) 2 << 31) - 1);
4963 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4964 i.types[op].bitfield.disp64 = 0;
4967 if (!op_disp && i.types[op].bitfield.baseindex)
4969 i.types[op].bitfield.disp8 = 0;
4970 i.types[op].bitfield.disp16 = 0;
4971 i.types[op].bitfield.disp32 = 0;
4972 i.types[op].bitfield.disp32s = 0;
4973 i.types[op].bitfield.disp64 = 0;
4977 else if (flag_code == CODE_64BIT)
4979 if (fits_in_signed_long (op_disp))
4981 i.types[op].bitfield.disp64 = 0;
4982 i.types[op].bitfield.disp32s = 1;
4984 if (i.prefix[ADDR_PREFIX]
4985 && fits_in_unsigned_long (op_disp))
4986 i.types[op].bitfield.disp32 = 1;
4988 if ((i.types[op].bitfield.disp32
4989 || i.types[op].bitfield.disp32s
4990 || i.types[op].bitfield.disp16)
4991 && fits_in_disp8 (op_disp))
4992 i.types[op].bitfield.disp8 = 1;
4994 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4995 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4997 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4998 i.op[op].disps, 0, i.reloc[op]);
4999 i.types[op].bitfield.disp8 = 0;
5000 i.types[op].bitfield.disp16 = 0;
5001 i.types[op].bitfield.disp32 = 0;
5002 i.types[op].bitfield.disp32s = 0;
5003 i.types[op].bitfield.disp64 = 0;
5006 /* We only support 64bit displacement on constants. */
5007 i.types[op].bitfield.disp64 = 0;
5011 /* Check if operands are valid for the instruction. */
5014 check_VecOperands (const insn_template *t)
5018 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5020 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5021 any one operand are implicity requiring AVX512VL support if the actual
5022 operand size is YMMword or XMMword. Since this function runs after
5023 template matching, there's no need to check for YMMword/XMMword in
5025 cpu = cpu_flags_and (t->cpu_flags, avx512);
5026 if (!cpu_flags_all_zero (&cpu)
5027 && !t->cpu_flags.bitfield.cpuavx512vl
5028 && !cpu_arch_flags.bitfield.cpuavx512vl)
5030 for (op = 0; op < t->operands; ++op)
5032 if (t->operand_types[op].bitfield.zmmword
5033 && (i.types[op].bitfield.ymmword
5034 || i.types[op].bitfield.xmmword))
5036 i.error = unsupported;
5042 /* Without VSIB byte, we can't have a vector register for index. */
5043 if (!t->opcode_modifier.vecsib
5045 && (i.index_reg->reg_type.bitfield.xmmword
5046 || i.index_reg->reg_type.bitfield.ymmword
5047 || i.index_reg->reg_type.bitfield.zmmword))
5049 i.error = unsupported_vector_index_register;
5053 /* Check if default mask is allowed. */
5054 if (t->opcode_modifier.nodefmask
5055 && (!i.mask || i.mask->mask->reg_num == 0))
5057 i.error = no_default_mask;
5061 /* For VSIB byte, we need a vector register for index, and all vector
5062 registers must be distinct. */
5063 if (t->opcode_modifier.vecsib)
5066 || !((t->opcode_modifier.vecsib == VecSIB128
5067 && i.index_reg->reg_type.bitfield.xmmword)
5068 || (t->opcode_modifier.vecsib == VecSIB256
5069 && i.index_reg->reg_type.bitfield.ymmword)
5070 || (t->opcode_modifier.vecsib == VecSIB512
5071 && i.index_reg->reg_type.bitfield.zmmword)))
5073 i.error = invalid_vsib_address;
5077 gas_assert (i.reg_operands == 2 || i.mask);
5078 if (i.reg_operands == 2 && !i.mask)
5080 gas_assert (i.types[0].bitfield.regsimd);
5081 gas_assert (i.types[0].bitfield.xmmword
5082 || i.types[0].bitfield.ymmword);
5083 gas_assert (i.types[2].bitfield.regsimd);
5084 gas_assert (i.types[2].bitfield.xmmword
5085 || i.types[2].bitfield.ymmword);
5086 if (operand_check == check_none)
5088 if (register_number (i.op[0].regs)
5089 != register_number (i.index_reg)
5090 && register_number (i.op[2].regs)
5091 != register_number (i.index_reg)
5092 && register_number (i.op[0].regs)
5093 != register_number (i.op[2].regs))
5095 if (operand_check == check_error)
5097 i.error = invalid_vector_register_set;
5100 as_warn (_("mask, index, and destination registers should be distinct"));
5102 else if (i.reg_operands == 1 && i.mask)
5104 if (i.types[1].bitfield.regsimd
5105 && (i.types[1].bitfield.xmmword
5106 || i.types[1].bitfield.ymmword
5107 || i.types[1].bitfield.zmmword)
5108 && (register_number (i.op[1].regs)
5109 == register_number (i.index_reg)))
5111 if (operand_check == check_error)
5113 i.error = invalid_vector_register_set;
5116 if (operand_check != check_none)
5117 as_warn (_("index and destination registers should be distinct"));
5122 /* Check if broadcast is supported by the instruction and is applied
5123 to the memory operand. */
5126 i386_operand_type type, overlap;
5128 /* Check if specified broadcast is supported in this instruction,
5129 and it's applied to memory operand of DWORD or QWORD type. */
5130 op = i.broadcast->operand;
5131 if (!t->opcode_modifier.broadcast
5132 || !i.types[op].bitfield.mem
5133 || (!i.types[op].bitfield.unspecified
5134 && (t->operand_types[op].bitfield.dword
5135 ? !i.types[op].bitfield.dword
5136 : !i.types[op].bitfield.qword)))
5139 i.error = unsupported_broadcast;
5143 operand_type_set (&type, 0);
5144 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5147 type.bitfield.qword = 1;
5150 type.bitfield.xmmword = 1;
5153 type.bitfield.ymmword = 1;
5156 type.bitfield.zmmword = 1;
5162 overlap = operand_type_and (type, t->operand_types[op]);
5163 if (operand_type_all_zero (&overlap))
5166 if (t->opcode_modifier.checkregsize)
5170 type.bitfield.baseindex = 1;
5171 for (j = 0; j < i.operands; ++j)
5174 && !operand_type_register_match(i.types[j],
5175 t->operand_types[j],
5177 t->operand_types[op]))
5182 /* If broadcast is supported in this instruction, we need to check if
5183 operand of one-element size isn't specified without broadcast. */
5184 else if (t->opcode_modifier.broadcast && i.mem_operands)
5186 /* Find memory operand. */
5187 for (op = 0; op < i.operands; op++)
5188 if (operand_type_check (i.types[op], anymem))
5190 gas_assert (op < i.operands);
5191 /* Check size of the memory operand. */
5192 if (t->operand_types[op].bitfield.dword
5193 ? i.types[op].bitfield.dword
5194 : i.types[op].bitfield.qword)
5196 i.error = broadcast_needed;
5201 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5203 /* Check if requested masking is supported. */
5205 && (!t->opcode_modifier.masking
5207 && t->opcode_modifier.masking == MERGING_MASKING)))
5209 i.error = unsupported_masking;
5213 /* Check if masking is applied to dest operand. */
5214 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5216 i.error = mask_not_on_destination;
5223 if ((i.rounding->type != saeonly
5224 && !t->opcode_modifier.staticrounding)
5225 || (i.rounding->type == saeonly
5226 && (t->opcode_modifier.staticrounding
5227 || !t->opcode_modifier.sae)))
5229 i.error = unsupported_rc_sae;
5232 /* If the instruction has several immediate operands and one of
5233 them is rounding, the rounding operand should be the last
5234 immediate operand. */
5235 if (i.imm_operands > 1
5236 && i.rounding->operand != (int) (i.imm_operands - 1))
5238 i.error = rc_sae_operand_not_last_imm;
5243 /* Check vector Disp8 operand. */
5244 if (t->opcode_modifier.disp8memshift
5245 && i.disp_encoding != disp_encoding_32bit)
5248 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5249 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5250 i.memshift = t->opcode_modifier.disp8memshift;
5253 const i386_operand_type *type = NULL;
5256 for (op = 0; op < i.operands; op++)
5257 if (operand_type_check (i.types[op], anymem))
5259 if (t->opcode_modifier.evex == EVEXLIG)
5260 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5261 else if (t->operand_types[op].bitfield.xmmword
5262 + t->operand_types[op].bitfield.ymmword
5263 + t->operand_types[op].bitfield.zmmword <= 1)
5264 type = &t->operand_types[op];
5265 else if (!i.types[op].bitfield.unspecified)
5266 type = &i.types[op];
5268 else if (i.types[op].bitfield.regsimd
5269 && t->opcode_modifier.evex != EVEXLIG)
5271 if (i.types[op].bitfield.zmmword)
5273 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5275 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5281 if (type->bitfield.zmmword)
5283 else if (type->bitfield.ymmword)
5285 else if (type->bitfield.xmmword)
5289 /* For the check in fits_in_disp8(). */
5290 if (i.memshift == 0)
5294 for (op = 0; op < i.operands; op++)
5295 if (operand_type_check (i.types[op], disp)
5296 && i.op[op].disps->X_op == O_constant)
5298 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5300 i.types[op].bitfield.disp8 = 1;
5303 i.types[op].bitfield.disp8 = 0;
5312 /* Check if operands are valid for the instruction. Update VEX
5316 VEX_check_operands (const insn_template *t)
5318 if (i.vec_encoding == vex_encoding_evex)
5320 /* This instruction must be encoded with EVEX prefix. */
5321 if (!is_evex_encoding (t))
5323 i.error = unsupported;
5329 if (!t->opcode_modifier.vex)
5331 /* This instruction template doesn't have VEX prefix. */
5332 if (i.vec_encoding != vex_encoding_default)
5334 i.error = unsupported;
5340 /* Only check VEX_Imm4, which must be the first operand. */
5341 if (t->operand_types[0].bitfield.vec_imm4)
5343 if (i.op[0].imms->X_op != O_constant
5344 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5350 /* Turn off Imm8 so that update_imm won't complain. */
5351 i.types[0] = vec_imm4;
5357 static const insn_template *
5358 match_template (char mnem_suffix)
5360 /* Points to template once we've found it. */
5361 const insn_template *t;
5362 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5363 i386_operand_type overlap4;
5364 unsigned int found_reverse_match;
5365 i386_opcode_modifier suffix_check, mnemsuf_check;
5366 i386_operand_type operand_types [MAX_OPERANDS];
5367 int addr_prefix_disp;
5369 unsigned int found_cpu_match, size_match;
5370 unsigned int check_register;
5371 enum i386_error specific_error = 0;
5373 #if MAX_OPERANDS != 5
5374 # error "MAX_OPERANDS must be 5."
5377 found_reverse_match = 0;
5378 addr_prefix_disp = -1;
5380 memset (&suffix_check, 0, sizeof (suffix_check));
5381 if (intel_syntax && i.broadcast)
5383 else if (i.suffix == BYTE_MNEM_SUFFIX)
5384 suffix_check.no_bsuf = 1;
5385 else if (i.suffix == WORD_MNEM_SUFFIX)
5386 suffix_check.no_wsuf = 1;
5387 else if (i.suffix == SHORT_MNEM_SUFFIX)
5388 suffix_check.no_ssuf = 1;
5389 else if (i.suffix == LONG_MNEM_SUFFIX)
5390 suffix_check.no_lsuf = 1;
5391 else if (i.suffix == QWORD_MNEM_SUFFIX)
5392 suffix_check.no_qsuf = 1;
5393 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5394 suffix_check.no_ldsuf = 1;
5396 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5399 switch (mnem_suffix)
5401 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5402 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5403 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5404 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5405 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5409 /* Must have right number of operands. */
5410 i.error = number_of_operands_mismatch;
5412 for (t = current_templates->start; t < current_templates->end; t++)
5414 addr_prefix_disp = -1;
5416 if (i.operands != t->operands)
5419 /* Check processor support. */
5420 i.error = unsupported;
5421 found_cpu_match = (cpu_flags_match (t)
5422 == CPU_FLAGS_PERFECT_MATCH);
5423 if (!found_cpu_match)
5426 /* Check AT&T mnemonic. */
5427 i.error = unsupported_with_intel_mnemonic;
5428 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5431 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5432 i.error = unsupported_syntax;
5433 if ((intel_syntax && t->opcode_modifier.attsyntax)
5434 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5435 || (intel64 && t->opcode_modifier.amd64)
5436 || (!intel64 && t->opcode_modifier.intel64))
5439 /* Check the suffix, except for some instructions in intel mode. */
5440 i.error = invalid_instruction_suffix;
5441 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5442 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5443 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5444 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5445 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5446 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5447 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5449 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5450 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5451 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5452 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5453 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5454 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5455 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5458 size_match = operand_size_match (t);
5462 for (j = 0; j < MAX_OPERANDS; j++)
5463 operand_types[j] = t->operand_types[j];
5465 /* In general, don't allow 64-bit operands in 32-bit mode. */
5466 if (i.suffix == QWORD_MNEM_SUFFIX
5467 && flag_code != CODE_64BIT
5469 ? (!t->opcode_modifier.ignoresize
5470 && !t->opcode_modifier.broadcast
5471 && !intel_float_operand (t->name))
5472 : intel_float_operand (t->name) != 2)
5473 && ((!operand_types[0].bitfield.regmmx
5474 && !operand_types[0].bitfield.regsimd)
5475 || (!operand_types[t->operands > 1].bitfield.regmmx
5476 && !operand_types[t->operands > 1].bitfield.regsimd))
5477 && (t->base_opcode != 0x0fc7
5478 || t->extension_opcode != 1 /* cmpxchg8b */))
5481 /* In general, don't allow 32-bit operands on pre-386. */
5482 else if (i.suffix == LONG_MNEM_SUFFIX
5483 && !cpu_arch_flags.bitfield.cpui386
5485 ? (!t->opcode_modifier.ignoresize
5486 && !intel_float_operand (t->name))
5487 : intel_float_operand (t->name) != 2)
5488 && ((!operand_types[0].bitfield.regmmx
5489 && !operand_types[0].bitfield.regsimd)
5490 || (!operand_types[t->operands > 1].bitfield.regmmx
5491 && !operand_types[t->operands > 1].bitfield.regsimd)))
5494 /* Do not verify operands when there are none. */
5498 /* We've found a match; break out of loop. */
5502 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5503 into Disp32/Disp16/Disp32 operand. */
5504 if (i.prefix[ADDR_PREFIX] != 0)
5506 /* There should be only one Disp operand. */
5510 for (j = 0; j < MAX_OPERANDS; j++)
5512 if (operand_types[j].bitfield.disp16)
5514 addr_prefix_disp = j;
5515 operand_types[j].bitfield.disp32 = 1;
5516 operand_types[j].bitfield.disp16 = 0;
5522 for (j = 0; j < MAX_OPERANDS; j++)
5524 if (operand_types[j].bitfield.disp32)
5526 addr_prefix_disp = j;
5527 operand_types[j].bitfield.disp32 = 0;
5528 operand_types[j].bitfield.disp16 = 1;
5534 for (j = 0; j < MAX_OPERANDS; j++)
5536 if (operand_types[j].bitfield.disp64)
5538 addr_prefix_disp = j;
5539 operand_types[j].bitfield.disp64 = 0;
5540 operand_types[j].bitfield.disp32 = 1;
5548 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5549 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5552 /* We check register size if needed. */
5553 if (t->opcode_modifier.checkregsize)
5555 check_register = (1 << t->operands) - 1;
5557 check_register &= ~(1 << i.broadcast->operand);
5562 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5563 switch (t->operands)
5566 if (!operand_type_match (overlap0, i.types[0]))
5570 /* xchg %eax, %eax is a special case. It is an alias for nop
5571 only in 32bit mode and we can use opcode 0x90. In 64bit
5572 mode, we can't use 0x90 for xchg %eax, %eax since it should
5573 zero-extend %eax to %rax. */
5574 if (flag_code == CODE_64BIT
5575 && t->base_opcode == 0x90
5576 && operand_type_equal (&i.types [0], &acc32)
5577 && operand_type_equal (&i.types [1], &acc32))
5579 /* xrelease mov %eax, <disp> is another special case. It must not
5580 match the accumulator-only encoding of mov. */
5581 if (flag_code != CODE_64BIT
5583 && t->base_opcode == 0xa0
5584 && i.types[0].bitfield.acc
5585 && operand_type_check (i.types[1], anymem))
5587 if (!(size_match & MATCH_STRAIGHT))
5589 /* If we want store form, we reverse direction of operands. */
5590 if (i.dir_encoding == dir_encoding_store
5591 && t->opcode_modifier.d)
5596 /* If we want store form, we skip the current load. */
5597 if (i.dir_encoding == dir_encoding_store
5598 && i.mem_operands == 0
5599 && t->opcode_modifier.load)
5604 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5605 if (!operand_type_match (overlap0, i.types[0])
5606 || !operand_type_match (overlap1, i.types[1])
5607 || ((check_register & 3) == 3
5608 && !operand_type_register_match (i.types[0],
5613 /* Check if other direction is valid ... */
5614 if (!t->opcode_modifier.d)
5618 if (!(size_match & MATCH_REVERSE))
5620 /* Try reversing direction of operands. */
5621 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5622 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5623 if (!operand_type_match (overlap0, i.types[0])
5624 || !operand_type_match (overlap1, i.types[1])
5626 && !operand_type_register_match (i.types[0],
5631 /* Does not match either direction. */
5634 /* found_reverse_match holds which of D or FloatR
5636 if (!t->opcode_modifier.d)
5637 found_reverse_match = 0;
5638 else if (operand_types[0].bitfield.tbyte)
5639 found_reverse_match = Opcode_FloatD;
5641 found_reverse_match = Opcode_D;
5642 if (t->opcode_modifier.floatr)
5643 found_reverse_match |= Opcode_FloatR;
5647 /* Found a forward 2 operand match here. */
5648 switch (t->operands)
5651 overlap4 = operand_type_and (i.types[4],
5655 overlap3 = operand_type_and (i.types[3],
5659 overlap2 = operand_type_and (i.types[2],
5664 switch (t->operands)
5667 if (!operand_type_match (overlap4, i.types[4])
5668 || !operand_type_register_match (i.types[3],
5675 if (!operand_type_match (overlap3, i.types[3])
5676 || ((check_register & 0xa) == 0xa
5677 && !operand_type_register_match (i.types[1],
5681 || ((check_register & 0xc) == 0xc
5682 && !operand_type_register_match (i.types[2],
5689 /* Here we make use of the fact that there are no
5690 reverse match 3 operand instructions. */
5691 if (!operand_type_match (overlap2, i.types[2])
5692 || ((check_register & 5) == 5
5693 && !operand_type_register_match (i.types[0],
5697 || ((check_register & 6) == 6
5698 && !operand_type_register_match (i.types[1],
5706 /* Found either forward/reverse 2, 3 or 4 operand match here:
5707 slip through to break. */
5709 if (!found_cpu_match)
5711 found_reverse_match = 0;
5715 /* Check if vector and VEX operands are valid. */
5716 if (check_VecOperands (t) || VEX_check_operands (t))
5718 specific_error = i.error;
5722 /* We've found a match; break out of loop. */
5726 if (t == current_templates->end)
5728 /* We found no match. */
5729 const char *err_msg;
5730 switch (specific_error ? specific_error : i.error)
5734 case operand_size_mismatch:
5735 err_msg = _("operand size mismatch");
5737 case operand_type_mismatch:
5738 err_msg = _("operand type mismatch");
5740 case register_type_mismatch:
5741 err_msg = _("register type mismatch");
5743 case number_of_operands_mismatch:
5744 err_msg = _("number of operands mismatch");
5746 case invalid_instruction_suffix:
5747 err_msg = _("invalid instruction suffix");
5750 err_msg = _("constant doesn't fit in 4 bits");
5752 case unsupported_with_intel_mnemonic:
5753 err_msg = _("unsupported with Intel mnemonic");
5755 case unsupported_syntax:
5756 err_msg = _("unsupported syntax");
5759 as_bad (_("unsupported instruction `%s'"),
5760 current_templates->start->name);
5762 case invalid_vsib_address:
5763 err_msg = _("invalid VSIB address");
5765 case invalid_vector_register_set:
5766 err_msg = _("mask, index, and destination registers must be distinct");
5768 case unsupported_vector_index_register:
5769 err_msg = _("unsupported vector index register");
5771 case unsupported_broadcast:
5772 err_msg = _("unsupported broadcast");
5774 case broadcast_needed:
5775 err_msg = _("broadcast is needed for operand of such type");
5777 case unsupported_masking:
5778 err_msg = _("unsupported masking");
5780 case mask_not_on_destination:
5781 err_msg = _("mask not on destination operand");
5783 case no_default_mask:
5784 err_msg = _("default mask isn't allowed");
5786 case unsupported_rc_sae:
5787 err_msg = _("unsupported static rounding/sae");
5789 case rc_sae_operand_not_last_imm:
5791 err_msg = _("RC/SAE operand must precede immediate operands");
5793 err_msg = _("RC/SAE operand must follow immediate operands");
5795 case invalid_register_operand:
5796 err_msg = _("invalid register operand");
5799 as_bad (_("%s for `%s'"), err_msg,
5800 current_templates->start->name);
5804 if (!quiet_warnings)
5807 && (i.types[0].bitfield.jumpabsolute
5808 != operand_types[0].bitfield.jumpabsolute))
5810 as_warn (_("indirect %s without `*'"), t->name);
5813 if (t->opcode_modifier.isprefix
5814 && t->opcode_modifier.ignoresize)
5816 /* Warn them that a data or address size prefix doesn't
5817 affect assembly of the next line of code. */
5818 as_warn (_("stand-alone `%s' prefix"), t->name);
5822 /* Copy the template we found. */
5825 if (addr_prefix_disp != -1)
5826 i.tm.operand_types[addr_prefix_disp]
5827 = operand_types[addr_prefix_disp];
5829 if (found_reverse_match)
5831 /* If we found a reverse match we must alter the opcode
5832 direction bit. found_reverse_match holds bits to change
5833 (different for int & float insns). */
5835 i.tm.base_opcode ^= found_reverse_match;
5837 i.tm.operand_types[0] = operand_types[1];
5838 i.tm.operand_types[1] = operand_types[0];
5847 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5848 if (i.tm.operand_types[mem_op].bitfield.esseg)
5850 if (i.seg[0] != NULL && i.seg[0] != &es)
5852 as_bad (_("`%s' operand %d must use `%ses' segment"),
5858 /* There's only ever one segment override allowed per instruction.
5859 This instruction possibly has a legal segment override on the
5860 second operand, so copy the segment to where non-string
5861 instructions store it, allowing common code. */
5862 i.seg[0] = i.seg[1];
5864 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5866 if (i.seg[1] != NULL && i.seg[1] != &es)
5868 as_bad (_("`%s' operand %d must use `%ses' segment"),
5879 process_suffix (void)
5881 /* If matched instruction specifies an explicit instruction mnemonic
5883 if (i.tm.opcode_modifier.size16)
5884 i.suffix = WORD_MNEM_SUFFIX;
5885 else if (i.tm.opcode_modifier.size32)
5886 i.suffix = LONG_MNEM_SUFFIX;
5887 else if (i.tm.opcode_modifier.size64)
5888 i.suffix = QWORD_MNEM_SUFFIX;
5889 else if (i.reg_operands)
5891 /* If there's no instruction mnemonic suffix we try to invent one
5892 based on register operands. */
5895 /* We take i.suffix from the last register operand specified,
5896 Destination register type is more significant than source
5897 register type. crc32 in SSE4.2 prefers source register
5899 if (i.tm.base_opcode == 0xf20f38f1)
5901 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5902 i.suffix = WORD_MNEM_SUFFIX;
5903 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5904 i.suffix = LONG_MNEM_SUFFIX;
5905 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5906 i.suffix = QWORD_MNEM_SUFFIX;
5908 else if (i.tm.base_opcode == 0xf20f38f0)
5910 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5911 i.suffix = BYTE_MNEM_SUFFIX;
5918 if (i.tm.base_opcode == 0xf20f38f1
5919 || i.tm.base_opcode == 0xf20f38f0)
5921 /* We have to know the operand size for crc32. */
5922 as_bad (_("ambiguous memory operand size for `%s`"),
5927 for (op = i.operands; --op >= 0;)
5928 if (!i.tm.operand_types[op].bitfield.inoutportreg
5929 && !i.tm.operand_types[op].bitfield.shiftcount)
5931 if (!i.types[op].bitfield.reg)
5933 if (i.types[op].bitfield.byte)
5934 i.suffix = BYTE_MNEM_SUFFIX;
5935 else if (i.types[op].bitfield.word)
5936 i.suffix = WORD_MNEM_SUFFIX;
5937 else if (i.types[op].bitfield.dword)
5938 i.suffix = LONG_MNEM_SUFFIX;
5939 else if (i.types[op].bitfield.qword)
5940 i.suffix = QWORD_MNEM_SUFFIX;
5947 else if (i.suffix == BYTE_MNEM_SUFFIX)
5950 && i.tm.opcode_modifier.ignoresize
5951 && i.tm.opcode_modifier.no_bsuf)
5953 else if (!check_byte_reg ())
5956 else if (i.suffix == LONG_MNEM_SUFFIX)
5959 && i.tm.opcode_modifier.ignoresize
5960 && i.tm.opcode_modifier.no_lsuf
5961 && !i.tm.opcode_modifier.todword
5962 && !i.tm.opcode_modifier.toqword)
5964 else if (!check_long_reg ())
5967 else if (i.suffix == QWORD_MNEM_SUFFIX)
5970 && i.tm.opcode_modifier.ignoresize
5971 && i.tm.opcode_modifier.no_qsuf
5972 && !i.tm.opcode_modifier.todword
5973 && !i.tm.opcode_modifier.toqword)
5975 else if (!check_qword_reg ())
5978 else if (i.suffix == WORD_MNEM_SUFFIX)
5981 && i.tm.opcode_modifier.ignoresize
5982 && i.tm.opcode_modifier.no_wsuf)
5984 else if (!check_word_reg ())
5987 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5988 /* Do nothing if the instruction is going to ignore the prefix. */
5993 else if (i.tm.opcode_modifier.defaultsize
5995 /* exclude fldenv/frstor/fsave/fstenv */
5996 && i.tm.opcode_modifier.no_ssuf)
5998 i.suffix = stackop_size;
6000 else if (intel_syntax
6002 && (i.tm.operand_types[0].bitfield.jumpabsolute
6003 || i.tm.opcode_modifier.jumpbyte
6004 || i.tm.opcode_modifier.jumpintersegment
6005 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6006 && i.tm.extension_opcode <= 3)))
6011 if (!i.tm.opcode_modifier.no_qsuf)
6013 i.suffix = QWORD_MNEM_SUFFIX;
6018 if (!i.tm.opcode_modifier.no_lsuf)
6019 i.suffix = LONG_MNEM_SUFFIX;
6022 if (!i.tm.opcode_modifier.no_wsuf)
6023 i.suffix = WORD_MNEM_SUFFIX;
6032 if (i.tm.opcode_modifier.w)
6034 as_bad (_("no instruction mnemonic suffix given and "
6035 "no register operands; can't size instruction"));
6041 unsigned int suffixes;
6043 suffixes = !i.tm.opcode_modifier.no_bsuf;
6044 if (!i.tm.opcode_modifier.no_wsuf)
6046 if (!i.tm.opcode_modifier.no_lsuf)
6048 if (!i.tm.opcode_modifier.no_ldsuf)
6050 if (!i.tm.opcode_modifier.no_ssuf)
6052 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6055 /* There are more than suffix matches. */
6056 if (i.tm.opcode_modifier.w
6057 || ((suffixes & (suffixes - 1))
6058 && !i.tm.opcode_modifier.defaultsize
6059 && !i.tm.opcode_modifier.ignoresize))
6061 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6067 /* Change the opcode based on the operand size given by i.suffix. */
6070 /* Size floating point instruction. */
6071 case LONG_MNEM_SUFFIX:
6072 if (i.tm.opcode_modifier.floatmf)
6074 i.tm.base_opcode ^= 4;
6078 case WORD_MNEM_SUFFIX:
6079 case QWORD_MNEM_SUFFIX:
6080 /* It's not a byte, select word/dword operation. */
6081 if (i.tm.opcode_modifier.w)
6083 if (i.tm.opcode_modifier.shortform)
6084 i.tm.base_opcode |= 8;
6086 i.tm.base_opcode |= 1;
6089 case SHORT_MNEM_SUFFIX:
6090 /* Now select between word & dword operations via the operand
6091 size prefix, except for instructions that will ignore this
6093 if (i.reg_operands > 0
6094 && i.types[0].bitfield.reg
6095 && i.tm.opcode_modifier.addrprefixopreg
6096 && (i.tm.opcode_modifier.immext
6097 || i.operands == 1))
6099 /* The address size override prefix changes the size of the
6101 if ((flag_code == CODE_32BIT
6102 && i.op[0].regs->reg_type.bitfield.word)
6103 || (flag_code != CODE_32BIT
6104 && i.op[0].regs->reg_type.bitfield.dword))
6105 if (!add_prefix (ADDR_PREFIX_OPCODE))
6108 else if (i.suffix != QWORD_MNEM_SUFFIX
6109 && !i.tm.opcode_modifier.ignoresize
6110 && !i.tm.opcode_modifier.floatmf
6111 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6112 || (flag_code == CODE_64BIT
6113 && i.tm.opcode_modifier.jumpbyte)))
6115 unsigned int prefix = DATA_PREFIX_OPCODE;
6117 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6118 prefix = ADDR_PREFIX_OPCODE;
6120 if (!add_prefix (prefix))
6124 /* Set mode64 for an operand. */
6125 if (i.suffix == QWORD_MNEM_SUFFIX
6126 && flag_code == CODE_64BIT
6127 && !i.tm.opcode_modifier.norex64
6128 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6130 && ! (i.operands == 2
6131 && i.tm.base_opcode == 0x90
6132 && i.tm.extension_opcode == None
6133 && operand_type_equal (&i.types [0], &acc64)
6134 && operand_type_equal (&i.types [1], &acc64)))
6140 if (i.reg_operands != 0
6142 && i.tm.opcode_modifier.addrprefixopreg
6143 && !i.tm.opcode_modifier.immext)
6145 /* Check invalid register operand when the address size override
6146 prefix changes the size of register operands. */
6148 enum { need_word, need_dword, need_qword } need;
6150 if (flag_code == CODE_32BIT)
6151 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6154 if (i.prefix[ADDR_PREFIX])
6157 need = flag_code == CODE_64BIT ? need_qword : need_word;
6160 for (op = 0; op < i.operands; op++)
6161 if (i.types[op].bitfield.reg
6162 && ((need == need_word
6163 && !i.op[op].regs->reg_type.bitfield.word)
6164 || (need == need_dword
6165 && !i.op[op].regs->reg_type.bitfield.dword)
6166 || (need == need_qword
6167 && !i.op[op].regs->reg_type.bitfield.qword)))
6169 as_bad (_("invalid register operand size for `%s'"),
6179 check_byte_reg (void)
6183 for (op = i.operands; --op >= 0;)
6185 /* Skip non-register operands. */
6186 if (!i.types[op].bitfield.reg)
6189 /* If this is an eight bit register, it's OK. If it's the 16 or
6190 32 bit version of an eight bit register, we will just use the
6191 low portion, and that's OK too. */
6192 if (i.types[op].bitfield.byte)
6195 /* I/O port address operands are OK too. */
6196 if (i.tm.operand_types[op].bitfield.inoutportreg)
6199 /* crc32 doesn't generate this warning. */
6200 if (i.tm.base_opcode == 0xf20f38f0)
6203 if ((i.types[op].bitfield.word
6204 || i.types[op].bitfield.dword
6205 || i.types[op].bitfield.qword)
6206 && i.op[op].regs->reg_num < 4
6207 /* Prohibit these changes in 64bit mode, since the lowering
6208 would be more complicated. */
6209 && flag_code != CODE_64BIT)
6211 #if REGISTER_WARNINGS
6212 if (!quiet_warnings)
6213 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6215 (i.op[op].regs + (i.types[op].bitfield.word
6216 ? REGNAM_AL - REGNAM_AX
6217 : REGNAM_AL - REGNAM_EAX))->reg_name,
6219 i.op[op].regs->reg_name,
6224 /* Any other register is bad. */
6225 if (i.types[op].bitfield.reg
6226 || i.types[op].bitfield.regmmx
6227 || i.types[op].bitfield.regsimd
6228 || i.types[op].bitfield.sreg2
6229 || i.types[op].bitfield.sreg3
6230 || i.types[op].bitfield.control
6231 || i.types[op].bitfield.debug
6232 || i.types[op].bitfield.test)
6234 as_bad (_("`%s%s' not allowed with `%s%c'"),
6236 i.op[op].regs->reg_name,
6246 check_long_reg (void)
6250 for (op = i.operands; --op >= 0;)
6251 /* Skip non-register operands. */
6252 if (!i.types[op].bitfield.reg)
6254 /* Reject eight bit registers, except where the template requires
6255 them. (eg. movzb) */
6256 else if (i.types[op].bitfield.byte
6257 && (i.tm.operand_types[op].bitfield.reg
6258 || i.tm.operand_types[op].bitfield.acc)
6259 && (i.tm.operand_types[op].bitfield.word
6260 || i.tm.operand_types[op].bitfield.dword))
6262 as_bad (_("`%s%s' not allowed with `%s%c'"),
6264 i.op[op].regs->reg_name,
6269 /* Warn if the e prefix on a general reg is missing. */
6270 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6271 && i.types[op].bitfield.word
6272 && (i.tm.operand_types[op].bitfield.reg
6273 || i.tm.operand_types[op].bitfield.acc)
6274 && i.tm.operand_types[op].bitfield.dword)
6276 /* Prohibit these changes in the 64bit mode, since the
6277 lowering is more complicated. */
6278 if (flag_code == CODE_64BIT)
6280 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6281 register_prefix, i.op[op].regs->reg_name,
6285 #if REGISTER_WARNINGS
6286 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6288 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6289 register_prefix, i.op[op].regs->reg_name, i.suffix);
6292 /* Warn if the r prefix on a general reg is present. */
6293 else if (i.types[op].bitfield.qword
6294 && (i.tm.operand_types[op].bitfield.reg
6295 || i.tm.operand_types[op].bitfield.acc)
6296 && i.tm.operand_types[op].bitfield.dword)
6299 && i.tm.opcode_modifier.toqword
6300 && !i.types[0].bitfield.regsimd)
6302 /* Convert to QWORD. We want REX byte. */
6303 i.suffix = QWORD_MNEM_SUFFIX;
6307 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6308 register_prefix, i.op[op].regs->reg_name,
6317 check_qword_reg (void)
6321 for (op = i.operands; --op >= 0; )
6322 /* Skip non-register operands. */
6323 if (!i.types[op].bitfield.reg)
6325 /* Reject eight bit registers, except where the template requires
6326 them. (eg. movzb) */
6327 else if (i.types[op].bitfield.byte
6328 && (i.tm.operand_types[op].bitfield.reg
6329 || i.tm.operand_types[op].bitfield.acc)
6330 && (i.tm.operand_types[op].bitfield.word
6331 || i.tm.operand_types[op].bitfield.dword))
6333 as_bad (_("`%s%s' not allowed with `%s%c'"),
6335 i.op[op].regs->reg_name,
6340 /* Warn if the r prefix on a general reg is missing. */
6341 else if ((i.types[op].bitfield.word
6342 || i.types[op].bitfield.dword)
6343 && (i.tm.operand_types[op].bitfield.reg
6344 || i.tm.operand_types[op].bitfield.acc)
6345 && i.tm.operand_types[op].bitfield.qword)
6347 /* Prohibit these changes in the 64bit mode, since the
6348 lowering is more complicated. */
6350 && i.tm.opcode_modifier.todword
6351 && !i.types[0].bitfield.regsimd)
6353 /* Convert to DWORD. We don't want REX byte. */
6354 i.suffix = LONG_MNEM_SUFFIX;
6358 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6359 register_prefix, i.op[op].regs->reg_name,
6368 check_word_reg (void)
6371 for (op = i.operands; --op >= 0;)
6372 /* Skip non-register operands. */
6373 if (!i.types[op].bitfield.reg)
6375 /* Reject eight bit registers, except where the template requires
6376 them. (eg. movzb) */
6377 else if (i.types[op].bitfield.byte
6378 && (i.tm.operand_types[op].bitfield.reg
6379 || i.tm.operand_types[op].bitfield.acc)
6380 && (i.tm.operand_types[op].bitfield.word
6381 || i.tm.operand_types[op].bitfield.dword))
6383 as_bad (_("`%s%s' not allowed with `%s%c'"),
6385 i.op[op].regs->reg_name,
6390 /* Warn if the e or r prefix on a general reg is present. */
6391 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6392 && (i.types[op].bitfield.dword
6393 || i.types[op].bitfield.qword)
6394 && (i.tm.operand_types[op].bitfield.reg
6395 || i.tm.operand_types[op].bitfield.acc)
6396 && i.tm.operand_types[op].bitfield.word)
6398 /* Prohibit these changes in the 64bit mode, since the
6399 lowering is more complicated. */
6400 if (flag_code == CODE_64BIT)
6402 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6403 register_prefix, i.op[op].regs->reg_name,
6407 #if REGISTER_WARNINGS
6408 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6410 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6411 register_prefix, i.op[op].regs->reg_name, i.suffix);
6418 update_imm (unsigned int j)
6420 i386_operand_type overlap = i.types[j];
6421 if ((overlap.bitfield.imm8
6422 || overlap.bitfield.imm8s
6423 || overlap.bitfield.imm16
6424 || overlap.bitfield.imm32
6425 || overlap.bitfield.imm32s
6426 || overlap.bitfield.imm64)
6427 && !operand_type_equal (&overlap, &imm8)
6428 && !operand_type_equal (&overlap, &imm8s)
6429 && !operand_type_equal (&overlap, &imm16)
6430 && !operand_type_equal (&overlap, &imm32)
6431 && !operand_type_equal (&overlap, &imm32s)
6432 && !operand_type_equal (&overlap, &imm64))
6436 i386_operand_type temp;
6438 operand_type_set (&temp, 0);
6439 if (i.suffix == BYTE_MNEM_SUFFIX)
6441 temp.bitfield.imm8 = overlap.bitfield.imm8;
6442 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6444 else if (i.suffix == WORD_MNEM_SUFFIX)
6445 temp.bitfield.imm16 = overlap.bitfield.imm16;
6446 else if (i.suffix == QWORD_MNEM_SUFFIX)
6448 temp.bitfield.imm64 = overlap.bitfield.imm64;
6449 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6452 temp.bitfield.imm32 = overlap.bitfield.imm32;
6455 else if (operand_type_equal (&overlap, &imm16_32_32s)
6456 || operand_type_equal (&overlap, &imm16_32)
6457 || operand_type_equal (&overlap, &imm16_32s))
6459 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6464 if (!operand_type_equal (&overlap, &imm8)
6465 && !operand_type_equal (&overlap, &imm8s)
6466 && !operand_type_equal (&overlap, &imm16)
6467 && !operand_type_equal (&overlap, &imm32)
6468 && !operand_type_equal (&overlap, &imm32s)
6469 && !operand_type_equal (&overlap, &imm64))
6471 as_bad (_("no instruction mnemonic suffix given; "
6472 "can't determine immediate size"));
6476 i.types[j] = overlap;
6486 /* Update the first 2 immediate operands. */
6487 n = i.operands > 2 ? 2 : i.operands;
6490 for (j = 0; j < n; j++)
6491 if (update_imm (j) == 0)
6494 /* The 3rd operand can't be immediate operand. */
6495 gas_assert (operand_type_check (i.types[2], imm) == 0);
6502 process_operands (void)
6504 /* Default segment register this instruction will use for memory
6505 accesses. 0 means unknown. This is only for optimizing out
6506 unnecessary segment overrides. */
6507 const seg_entry *default_seg = 0;
6509 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6511 unsigned int dupl = i.operands;
6512 unsigned int dest = dupl - 1;
6515 /* The destination must be an xmm register. */
6516 gas_assert (i.reg_operands
6517 && MAX_OPERANDS > dupl
6518 && operand_type_equal (&i.types[dest], ®xmm));
6520 if (i.tm.operand_types[0].bitfield.acc
6521 && i.tm.operand_types[0].bitfield.xmmword)
6523 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6525 /* Keep xmm0 for instructions with VEX prefix and 3
6527 i.tm.operand_types[0].bitfield.acc = 0;
6528 i.tm.operand_types[0].bitfield.regsimd = 1;
6533 /* We remove the first xmm0 and keep the number of
6534 operands unchanged, which in fact duplicates the
6536 for (j = 1; j < i.operands; j++)
6538 i.op[j - 1] = i.op[j];
6539 i.types[j - 1] = i.types[j];
6540 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6544 else if (i.tm.opcode_modifier.implicit1stxmm0)
6546 gas_assert ((MAX_OPERANDS - 1) > dupl
6547 && (i.tm.opcode_modifier.vexsources
6550 /* Add the implicit xmm0 for instructions with VEX prefix
6552 for (j = i.operands; j > 0; j--)
6554 i.op[j] = i.op[j - 1];
6555 i.types[j] = i.types[j - 1];
6556 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6559 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6560 i.types[0] = regxmm;
6561 i.tm.operand_types[0] = regxmm;
6564 i.reg_operands += 2;
6569 i.op[dupl] = i.op[dest];
6570 i.types[dupl] = i.types[dest];
6571 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6580 i.op[dupl] = i.op[dest];
6581 i.types[dupl] = i.types[dest];
6582 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6585 if (i.tm.opcode_modifier.immext)
6588 else if (i.tm.operand_types[0].bitfield.acc
6589 && i.tm.operand_types[0].bitfield.xmmword)
6593 for (j = 1; j < i.operands; j++)
6595 i.op[j - 1] = i.op[j];
6596 i.types[j - 1] = i.types[j];
6598 /* We need to adjust fields in i.tm since they are used by
6599 build_modrm_byte. */
6600 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6607 else if (i.tm.opcode_modifier.implicitquadgroup)
6609 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6611 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6612 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6613 regnum = register_number (i.op[1].regs);
6614 first_reg_in_group = regnum & ~3;
6615 last_reg_in_group = first_reg_in_group + 3;
6616 if (regnum != first_reg_in_group)
6617 as_warn (_("source register `%s%s' implicitly denotes"
6618 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6619 register_prefix, i.op[1].regs->reg_name,
6620 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6621 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6624 else if (i.tm.opcode_modifier.regkludge)
6626 /* The imul $imm, %reg instruction is converted into
6627 imul $imm, %reg, %reg, and the clr %reg instruction
6628 is converted into xor %reg, %reg. */
6630 unsigned int first_reg_op;
6632 if (operand_type_check (i.types[0], reg))
6636 /* Pretend we saw the extra register operand. */
6637 gas_assert (i.reg_operands == 1
6638 && i.op[first_reg_op + 1].regs == 0);
6639 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6640 i.types[first_reg_op + 1] = i.types[first_reg_op];
6645 if (i.tm.opcode_modifier.shortform)
6647 if (i.types[0].bitfield.sreg2
6648 || i.types[0].bitfield.sreg3)
6650 if (i.tm.base_opcode == POP_SEG_SHORT
6651 && i.op[0].regs->reg_num == 1)
6653 as_bad (_("you can't `pop %scs'"), register_prefix);
6656 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6657 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6662 /* The register or float register operand is in operand
6666 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6667 || operand_type_check (i.types[0], reg))
6671 /* Register goes in low 3 bits of opcode. */
6672 i.tm.base_opcode |= i.op[op].regs->reg_num;
6673 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6675 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6677 /* Warn about some common errors, but press on regardless.
6678 The first case can be generated by gcc (<= 2.8.1). */
6679 if (i.operands == 2)
6681 /* Reversed arguments on faddp, fsubp, etc. */
6682 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6683 register_prefix, i.op[!intel_syntax].regs->reg_name,
6684 register_prefix, i.op[intel_syntax].regs->reg_name);
6688 /* Extraneous `l' suffix on fp insn. */
6689 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6690 register_prefix, i.op[0].regs->reg_name);
6695 else if (i.tm.opcode_modifier.modrm)
6697 /* The opcode is completed (modulo i.tm.extension_opcode which
6698 must be put into the modrm byte). Now, we make the modrm and
6699 index base bytes based on all the info we've collected. */
6701 default_seg = build_modrm_byte ();
6703 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6707 else if (i.tm.opcode_modifier.isstring)
6709 /* For the string instructions that allow a segment override
6710 on one of their operands, the default segment is ds. */
6714 if (i.tm.base_opcode == 0x8d /* lea */
6717 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6719 /* If a segment was explicitly specified, and the specified segment
6720 is not the default, use an opcode prefix to select it. If we
6721 never figured out what the default segment is, then default_seg
6722 will be zero at this point, and the specified segment prefix will
6724 if ((i.seg[0]) && (i.seg[0] != default_seg))
6726 if (!add_prefix (i.seg[0]->seg_prefix))
6732 static const seg_entry *
6733 build_modrm_byte (void)
6735 const seg_entry *default_seg = 0;
6736 unsigned int source, dest;
6739 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6742 unsigned int nds, reg_slot;
6745 dest = i.operands - 1;
6748 /* There are 2 kinds of instructions:
6749 1. 5 operands: 4 register operands or 3 register operands
6750 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6751 VexW0 or VexW1. The destination must be either XMM, YMM or
6753 2. 4 operands: 4 register operands or 3 register operands
6754 plus 1 memory operand, with VexXDS. */
6755 gas_assert ((i.reg_operands == 4
6756 || (i.reg_operands == 3 && i.mem_operands == 1))
6757 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6758 && i.tm.opcode_modifier.vexw
6759 && i.tm.operand_types[dest].bitfield.regsimd);
6761 /* If VexW1 is set, the first non-immediate operand is the source and
6762 the second non-immediate one is encoded in the immediate operand. */
6763 if (i.tm.opcode_modifier.vexw == VEXW1)
6765 source = i.imm_operands;
6766 reg_slot = i.imm_operands + 1;
6770 source = i.imm_operands + 1;
6771 reg_slot = i.imm_operands;
6774 if (i.imm_operands == 0)
6776 /* When there is no immediate operand, generate an 8bit
6777 immediate operand to encode the first operand. */
6778 exp = &im_expressions[i.imm_operands++];
6779 i.op[i.operands].imms = exp;
6780 i.types[i.operands] = imm8;
6783 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6784 exp->X_op = O_constant;
6785 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6786 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6790 unsigned int imm_slot;
6792 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6794 if (i.tm.opcode_modifier.immext)
6796 /* When ImmExt is set, the immediate byte is the last
6798 imm_slot = i.operands - 1;
6806 /* Turn on Imm8 so that output_imm will generate it. */
6807 i.types[imm_slot].bitfield.imm8 = 1;
6810 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6811 i.op[imm_slot].imms->X_add_number
6812 |= register_number (i.op[reg_slot].regs) << 4;
6813 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6816 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6817 i.vex.register_specifier = i.op[nds].regs;
6822 /* i.reg_operands MUST be the number of real register operands;
6823 implicit registers do not count. If there are 3 register
6824 operands, it must be a instruction with VexNDS. For a
6825 instruction with VexNDD, the destination register is encoded
6826 in VEX prefix. If there are 4 register operands, it must be
6827 a instruction with VEX prefix and 3 sources. */
6828 if (i.mem_operands == 0
6829 && ((i.reg_operands == 2
6830 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6831 || (i.reg_operands == 3
6832 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6833 || (i.reg_operands == 4 && vex_3_sources)))
6841 /* When there are 3 operands, one of them may be immediate,
6842 which may be the first or the last operand. Otherwise,
6843 the first operand must be shift count register (cl) or it
6844 is an instruction with VexNDS. */
6845 gas_assert (i.imm_operands == 1
6846 || (i.imm_operands == 0
6847 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6848 || i.types[0].bitfield.shiftcount)));
6849 if (operand_type_check (i.types[0], imm)
6850 || i.types[0].bitfield.shiftcount)
6856 /* When there are 4 operands, the first two must be 8bit
6857 immediate operands. The source operand will be the 3rd
6860 For instructions with VexNDS, if the first operand
6861 an imm8, the source operand is the 2nd one. If the last
6862 operand is imm8, the source operand is the first one. */
6863 gas_assert ((i.imm_operands == 2
6864 && i.types[0].bitfield.imm8
6865 && i.types[1].bitfield.imm8)
6866 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6867 && i.imm_operands == 1
6868 && (i.types[0].bitfield.imm8
6869 || i.types[i.operands - 1].bitfield.imm8
6871 if (i.imm_operands == 2)
6875 if (i.types[0].bitfield.imm8)
6882 if (is_evex_encoding (&i.tm))
6884 /* For EVEX instructions, when there are 5 operands, the
6885 first one must be immediate operand. If the second one
6886 is immediate operand, the source operand is the 3th
6887 one. If the last one is immediate operand, the source
6888 operand is the 2nd one. */
6889 gas_assert (i.imm_operands == 2
6890 && i.tm.opcode_modifier.sae
6891 && operand_type_check (i.types[0], imm));
6892 if (operand_type_check (i.types[1], imm))
6894 else if (operand_type_check (i.types[4], imm))
6908 /* RC/SAE operand could be between DEST and SRC. That happens
6909 when one operand is GPR and the other one is XMM/YMM/ZMM
6911 if (i.rounding && i.rounding->operand == (int) dest)
6914 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6916 /* For instructions with VexNDS, the register-only source
6917 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6918 register. It is encoded in VEX prefix. We need to
6919 clear RegMem bit before calling operand_type_equal. */
6921 i386_operand_type op;
6924 /* Check register-only source operand when two source
6925 operands are swapped. */
6926 if (!i.tm.operand_types[source].bitfield.baseindex
6927 && i.tm.operand_types[dest].bitfield.baseindex)
6935 op = i.tm.operand_types[vvvv];
6936 op.bitfield.regmem = 0;
6937 if ((dest + 1) >= i.operands
6938 || ((!op.bitfield.reg
6939 || (!op.bitfield.dword && !op.bitfield.qword))
6940 && !op.bitfield.regsimd
6941 && !operand_type_equal (&op, ®mask)))
6943 i.vex.register_specifier = i.op[vvvv].regs;
6949 /* One of the register operands will be encoded in the i.tm.reg
6950 field, the other in the combined i.tm.mode and i.tm.regmem
6951 fields. If no form of this instruction supports a memory
6952 destination operand, then we assume the source operand may
6953 sometimes be a memory operand and so we need to store the
6954 destination in the i.rm.reg field. */
6955 if (!i.tm.operand_types[dest].bitfield.regmem
6956 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6958 i.rm.reg = i.op[dest].regs->reg_num;
6959 i.rm.regmem = i.op[source].regs->reg_num;
6960 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6962 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6964 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6966 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6971 i.rm.reg = i.op[source].regs->reg_num;
6972 i.rm.regmem = i.op[dest].regs->reg_num;
6973 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6975 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6977 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6979 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6982 if (flag_code != CODE_64BIT && (i.rex & REX_R))
6984 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
6987 add_prefix (LOCK_PREFIX_OPCODE);
6991 { /* If it's not 2 reg operands... */
6996 unsigned int fake_zero_displacement = 0;
6999 for (op = 0; op < i.operands; op++)
7000 if (operand_type_check (i.types[op], anymem))
7002 gas_assert (op < i.operands);
7004 if (i.tm.opcode_modifier.vecsib)
7006 if (i.index_reg->reg_num == RegEiz
7007 || i.index_reg->reg_num == RegRiz)
7010 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7013 i.sib.base = NO_BASE_REGISTER;
7014 i.sib.scale = i.log2_scale_factor;
7015 i.types[op].bitfield.disp8 = 0;
7016 i.types[op].bitfield.disp16 = 0;
7017 i.types[op].bitfield.disp64 = 0;
7018 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7020 /* Must be 32 bit */
7021 i.types[op].bitfield.disp32 = 1;
7022 i.types[op].bitfield.disp32s = 0;
7026 i.types[op].bitfield.disp32 = 0;
7027 i.types[op].bitfield.disp32s = 1;
7030 i.sib.index = i.index_reg->reg_num;
7031 if ((i.index_reg->reg_flags & RegRex) != 0)
7033 if ((i.index_reg->reg_flags & RegVRex) != 0)
7039 if (i.base_reg == 0)
7042 if (!i.disp_operands)
7043 fake_zero_displacement = 1;
7044 if (i.index_reg == 0)
7046 i386_operand_type newdisp;
7048 gas_assert (!i.tm.opcode_modifier.vecsib);
7049 /* Operand is just <disp> */
7050 if (flag_code == CODE_64BIT)
7052 /* 64bit mode overwrites the 32bit absolute
7053 addressing by RIP relative addressing and
7054 absolute addressing is encoded by one of the
7055 redundant SIB forms. */
7056 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7057 i.sib.base = NO_BASE_REGISTER;
7058 i.sib.index = NO_INDEX_REGISTER;
7059 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7061 else if ((flag_code == CODE_16BIT)
7062 ^ (i.prefix[ADDR_PREFIX] != 0))
7064 i.rm.regmem = NO_BASE_REGISTER_16;
7069 i.rm.regmem = NO_BASE_REGISTER;
7072 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7073 i.types[op] = operand_type_or (i.types[op], newdisp);
7075 else if (!i.tm.opcode_modifier.vecsib)
7077 /* !i.base_reg && i.index_reg */
7078 if (i.index_reg->reg_num == RegEiz
7079 || i.index_reg->reg_num == RegRiz)
7080 i.sib.index = NO_INDEX_REGISTER;
7082 i.sib.index = i.index_reg->reg_num;
7083 i.sib.base = NO_BASE_REGISTER;
7084 i.sib.scale = i.log2_scale_factor;
7085 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7086 i.types[op].bitfield.disp8 = 0;
7087 i.types[op].bitfield.disp16 = 0;
7088 i.types[op].bitfield.disp64 = 0;
7089 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7091 /* Must be 32 bit */
7092 i.types[op].bitfield.disp32 = 1;
7093 i.types[op].bitfield.disp32s = 0;
7097 i.types[op].bitfield.disp32 = 0;
7098 i.types[op].bitfield.disp32s = 1;
7100 if ((i.index_reg->reg_flags & RegRex) != 0)
7104 /* RIP addressing for 64bit mode. */
7105 else if (i.base_reg->reg_num == RegRip ||
7106 i.base_reg->reg_num == RegEip)
7108 gas_assert (!i.tm.opcode_modifier.vecsib);
7109 i.rm.regmem = NO_BASE_REGISTER;
7110 i.types[op].bitfield.disp8 = 0;
7111 i.types[op].bitfield.disp16 = 0;
7112 i.types[op].bitfield.disp32 = 0;
7113 i.types[op].bitfield.disp32s = 1;
7114 i.types[op].bitfield.disp64 = 0;
7115 i.flags[op] |= Operand_PCrel;
7116 if (! i.disp_operands)
7117 fake_zero_displacement = 1;
7119 else if (i.base_reg->reg_type.bitfield.word)
7121 gas_assert (!i.tm.opcode_modifier.vecsib);
7122 switch (i.base_reg->reg_num)
7125 if (i.index_reg == 0)
7127 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7128 i.rm.regmem = i.index_reg->reg_num - 6;
7132 if (i.index_reg == 0)
7135 if (operand_type_check (i.types[op], disp) == 0)
7137 /* fake (%bp) into 0(%bp) */
7138 i.types[op].bitfield.disp8 = 1;
7139 fake_zero_displacement = 1;
7142 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7143 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7145 default: /* (%si) -> 4 or (%di) -> 5 */
7146 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7148 i.rm.mode = mode_from_disp_size (i.types[op]);
7150 else /* i.base_reg and 32/64 bit mode */
7152 if (flag_code == CODE_64BIT
7153 && operand_type_check (i.types[op], disp))
7155 i.types[op].bitfield.disp16 = 0;
7156 i.types[op].bitfield.disp64 = 0;
7157 if (i.prefix[ADDR_PREFIX] == 0)
7159 i.types[op].bitfield.disp32 = 0;
7160 i.types[op].bitfield.disp32s = 1;
7164 i.types[op].bitfield.disp32 = 1;
7165 i.types[op].bitfield.disp32s = 0;
7169 if (!i.tm.opcode_modifier.vecsib)
7170 i.rm.regmem = i.base_reg->reg_num;
7171 if ((i.base_reg->reg_flags & RegRex) != 0)
7173 i.sib.base = i.base_reg->reg_num;
7174 /* x86-64 ignores REX prefix bit here to avoid decoder
7176 if (!(i.base_reg->reg_flags & RegRex)
7177 && (i.base_reg->reg_num == EBP_REG_NUM
7178 || i.base_reg->reg_num == ESP_REG_NUM))
7180 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7182 fake_zero_displacement = 1;
7183 i.types[op].bitfield.disp8 = 1;
7185 i.sib.scale = i.log2_scale_factor;
7186 if (i.index_reg == 0)
7188 gas_assert (!i.tm.opcode_modifier.vecsib);
7189 /* <disp>(%esp) becomes two byte modrm with no index
7190 register. We've already stored the code for esp
7191 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7192 Any base register besides %esp will not use the
7193 extra modrm byte. */
7194 i.sib.index = NO_INDEX_REGISTER;
7196 else if (!i.tm.opcode_modifier.vecsib)
7198 if (i.index_reg->reg_num == RegEiz
7199 || i.index_reg->reg_num == RegRiz)
7200 i.sib.index = NO_INDEX_REGISTER;
7202 i.sib.index = i.index_reg->reg_num;
7203 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7204 if ((i.index_reg->reg_flags & RegRex) != 0)
7209 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7210 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7214 if (!fake_zero_displacement
7218 fake_zero_displacement = 1;
7219 if (i.disp_encoding == disp_encoding_8bit)
7220 i.types[op].bitfield.disp8 = 1;
7222 i.types[op].bitfield.disp32 = 1;
7224 i.rm.mode = mode_from_disp_size (i.types[op]);
7228 if (fake_zero_displacement)
7230 /* Fakes a zero displacement assuming that i.types[op]
7231 holds the correct displacement size. */
7234 gas_assert (i.op[op].disps == 0);
7235 exp = &disp_expressions[i.disp_operands++];
7236 i.op[op].disps = exp;
7237 exp->X_op = O_constant;
7238 exp->X_add_number = 0;
7239 exp->X_add_symbol = (symbolS *) 0;
7240 exp->X_op_symbol = (symbolS *) 0;
7248 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7250 if (operand_type_check (i.types[0], imm))
7251 i.vex.register_specifier = NULL;
7254 /* VEX.vvvv encodes one of the sources when the first
7255 operand is not an immediate. */
7256 if (i.tm.opcode_modifier.vexw == VEXW0)
7257 i.vex.register_specifier = i.op[0].regs;
7259 i.vex.register_specifier = i.op[1].regs;
7262 /* Destination is a XMM register encoded in the ModRM.reg
7264 i.rm.reg = i.op[2].regs->reg_num;
7265 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7268 /* ModRM.rm and VEX.B encodes the other source. */
7269 if (!i.mem_operands)
7273 if (i.tm.opcode_modifier.vexw == VEXW0)
7274 i.rm.regmem = i.op[1].regs->reg_num;
7276 i.rm.regmem = i.op[0].regs->reg_num;
7278 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7282 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7284 i.vex.register_specifier = i.op[2].regs;
7285 if (!i.mem_operands)
7288 i.rm.regmem = i.op[1].regs->reg_num;
7289 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7293 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7294 (if any) based on i.tm.extension_opcode. Again, we must be
7295 careful to make sure that segment/control/debug/test/MMX
7296 registers are coded into the i.rm.reg field. */
7297 else if (i.reg_operands)
7300 unsigned int vex_reg = ~0;
7302 for (op = 0; op < i.operands; op++)
7303 if (i.types[op].bitfield.reg
7304 || i.types[op].bitfield.regmmx
7305 || i.types[op].bitfield.regsimd
7306 || i.types[op].bitfield.regbnd
7307 || i.types[op].bitfield.regmask
7308 || i.types[op].bitfield.sreg2
7309 || i.types[op].bitfield.sreg3
7310 || i.types[op].bitfield.control
7311 || i.types[op].bitfield.debug
7312 || i.types[op].bitfield.test)
7317 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7319 /* For instructions with VexNDS, the register-only
7320 source operand is encoded in VEX prefix. */
7321 gas_assert (mem != (unsigned int) ~0);
7326 gas_assert (op < i.operands);
7330 /* Check register-only source operand when two source
7331 operands are swapped. */
7332 if (!i.tm.operand_types[op].bitfield.baseindex
7333 && i.tm.operand_types[op + 1].bitfield.baseindex)
7337 gas_assert (mem == (vex_reg + 1)
7338 && op < i.operands);
7343 gas_assert (vex_reg < i.operands);
7347 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7349 /* For instructions with VexNDD, the register destination
7350 is encoded in VEX prefix. */
7351 if (i.mem_operands == 0)
7353 /* There is no memory operand. */
7354 gas_assert ((op + 2) == i.operands);
7359 /* There are only 2 non-immediate operands. */
7360 gas_assert (op < i.imm_operands + 2
7361 && i.operands == i.imm_operands + 2);
7362 vex_reg = i.imm_operands + 1;
7366 gas_assert (op < i.operands);
7368 if (vex_reg != (unsigned int) ~0)
7370 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7372 if ((!type->bitfield.reg
7373 || (!type->bitfield.dword && !type->bitfield.qword))
7374 && !type->bitfield.regsimd
7375 && !operand_type_equal (type, ®mask))
7378 i.vex.register_specifier = i.op[vex_reg].regs;
7381 /* Don't set OP operand twice. */
7384 /* If there is an extension opcode to put here, the
7385 register number must be put into the regmem field. */
7386 if (i.tm.extension_opcode != None)
7388 i.rm.regmem = i.op[op].regs->reg_num;
7389 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7391 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7396 i.rm.reg = i.op[op].regs->reg_num;
7397 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7399 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7404 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7405 must set it to 3 to indicate this is a register operand
7406 in the regmem field. */
7407 if (!i.mem_operands)
7411 /* Fill in i.rm.reg field with extension opcode (if any). */
7412 if (i.tm.extension_opcode != None)
7413 i.rm.reg = i.tm.extension_opcode;
7419 output_branch (void)
7425 relax_substateT subtype;
7429 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7430 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7433 if (i.prefix[DATA_PREFIX] != 0)
7439 /* Pentium4 branch hints. */
7440 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7441 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7446 if (i.prefix[REX_PREFIX] != 0)
7452 /* BND prefixed jump. */
7453 if (i.prefix[BND_PREFIX] != 0)
7455 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7459 if (i.prefixes != 0 && !intel_syntax)
7460 as_warn (_("skipping prefixes on this instruction"));
7462 /* It's always a symbol; End frag & setup for relax.
7463 Make sure there is enough room in this frag for the largest
7464 instruction we may generate in md_convert_frag. This is 2
7465 bytes for the opcode and room for the prefix and largest
7467 frag_grow (prefix + 2 + 4);
7468 /* Prefix and 1 opcode byte go in fr_fix. */
7469 p = frag_more (prefix + 1);
7470 if (i.prefix[DATA_PREFIX] != 0)
7471 *p++ = DATA_PREFIX_OPCODE;
7472 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7473 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7474 *p++ = i.prefix[SEG_PREFIX];
7475 if (i.prefix[REX_PREFIX] != 0)
7476 *p++ = i.prefix[REX_PREFIX];
7477 *p = i.tm.base_opcode;
7479 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7480 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7481 else if (cpu_arch_flags.bitfield.cpui386)
7482 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7484 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7487 sym = i.op[0].disps->X_add_symbol;
7488 off = i.op[0].disps->X_add_number;
7490 if (i.op[0].disps->X_op != O_constant
7491 && i.op[0].disps->X_op != O_symbol)
7493 /* Handle complex expressions. */
7494 sym = make_expr_symbol (i.op[0].disps);
7498 /* 1 possible extra opcode + 4 byte displacement go in var part.
7499 Pass reloc in fr_var. */
7500 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7504 /* Return TRUE iff PLT32 relocation should be used for branching to
7508 need_plt32_p (symbolS *s)
7510 /* PLT32 relocation is ELF only. */
7514 /* Since there is no need to prepare for PLT branch on x86-64, we
7515 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7516 be used as a marker for 32-bit PC-relative branches. */
7520 /* Weak or undefined symbol need PLT32 relocation. */
7521 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7524 /* Non-global symbol doesn't need PLT32 relocation. */
7525 if (! S_IS_EXTERNAL (s))
7528 /* Other global symbols need PLT32 relocation. NB: Symbol with
7529 non-default visibilities are treated as normal global symbol
7530 so that PLT32 relocation can be used as a marker for 32-bit
7531 PC-relative branches. It is useful for linker relaxation. */
7542 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7544 if (i.tm.opcode_modifier.jumpbyte)
7546 /* This is a loop or jecxz type instruction. */
7548 if (i.prefix[ADDR_PREFIX] != 0)
7550 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7553 /* Pentium4 branch hints. */
7554 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7555 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7557 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7566 if (flag_code == CODE_16BIT)
7569 if (i.prefix[DATA_PREFIX] != 0)
7571 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7581 if (i.prefix[REX_PREFIX] != 0)
7583 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7587 /* BND prefixed jump. */
7588 if (i.prefix[BND_PREFIX] != 0)
7590 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7594 if (i.prefixes != 0 && !intel_syntax)
7595 as_warn (_("skipping prefixes on this instruction"));
7597 p = frag_more (i.tm.opcode_length + size);
7598 switch (i.tm.opcode_length)
7601 *p++ = i.tm.base_opcode >> 8;
7604 *p++ = i.tm.base_opcode;
7610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7612 && jump_reloc == NO_RELOC
7613 && need_plt32_p (i.op[0].disps->X_add_symbol))
7614 jump_reloc = BFD_RELOC_X86_64_PLT32;
7617 jump_reloc = reloc (size, 1, 1, jump_reloc);
7619 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7620 i.op[0].disps, 1, jump_reloc);
7622 /* All jumps handled here are signed, but don't use a signed limit
7623 check for 32 and 16 bit jumps as we want to allow wrap around at
7624 4G and 64k respectively. */
7626 fixP->fx_signed = 1;
7630 output_interseg_jump (void)
7638 if (flag_code == CODE_16BIT)
7642 if (i.prefix[DATA_PREFIX] != 0)
7648 if (i.prefix[REX_PREFIX] != 0)
7658 if (i.prefixes != 0 && !intel_syntax)
7659 as_warn (_("skipping prefixes on this instruction"));
7661 /* 1 opcode; 2 segment; offset */
7662 p = frag_more (prefix + 1 + 2 + size);
7664 if (i.prefix[DATA_PREFIX] != 0)
7665 *p++ = DATA_PREFIX_OPCODE;
7667 if (i.prefix[REX_PREFIX] != 0)
7668 *p++ = i.prefix[REX_PREFIX];
7670 *p++ = i.tm.base_opcode;
7671 if (i.op[1].imms->X_op == O_constant)
7673 offsetT n = i.op[1].imms->X_add_number;
7676 && !fits_in_unsigned_word (n)
7677 && !fits_in_signed_word (n))
7679 as_bad (_("16-bit jump out of range"));
7682 md_number_to_chars (p, n, size);
7685 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7686 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7687 if (i.op[0].imms->X_op != O_constant)
7688 as_bad (_("can't handle non absolute segment in `%s'"),
7690 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7696 fragS *insn_start_frag;
7697 offsetT insn_start_off;
7699 /* Tie dwarf2 debug info to the address at the start of the insn.
7700 We can't do this after the insn has been output as the current
7701 frag may have been closed off. eg. by frag_var. */
7702 dwarf2_emit_insn (0);
7704 insn_start_frag = frag_now;
7705 insn_start_off = frag_now_fix ();
7708 if (i.tm.opcode_modifier.jump)
7710 else if (i.tm.opcode_modifier.jumpbyte
7711 || i.tm.opcode_modifier.jumpdword)
7713 else if (i.tm.opcode_modifier.jumpintersegment)
7714 output_interseg_jump ();
7717 /* Output normal instructions here. */
7721 unsigned int prefix;
7724 && i.tm.base_opcode == 0xfae
7726 && i.imm_operands == 1
7727 && (i.op[0].imms->X_add_number == 0xe8
7728 || i.op[0].imms->X_add_number == 0xf0
7729 || i.op[0].imms->X_add_number == 0xf8))
7731 /* Encode lfence, mfence, and sfence as
7732 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7733 offsetT val = 0x240483f0ULL;
7735 md_number_to_chars (p, val, 5);
7739 /* Some processors fail on LOCK prefix. This options makes
7740 assembler ignore LOCK prefix and serves as a workaround. */
7741 if (omit_lock_prefix)
7743 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7745 i.prefix[LOCK_PREFIX] = 0;
7748 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7749 don't need the explicit prefix. */
7750 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7752 switch (i.tm.opcode_length)
7755 if (i.tm.base_opcode & 0xff000000)
7757 prefix = (i.tm.base_opcode >> 24) & 0xff;
7758 add_prefix (prefix);
7762 if ((i.tm.base_opcode & 0xff0000) != 0)
7764 prefix = (i.tm.base_opcode >> 16) & 0xff;
7765 if (!i.tm.cpu_flags.bitfield.cpupadlock
7766 || prefix != REPE_PREFIX_OPCODE
7767 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7768 add_prefix (prefix);
7774 /* Check for pseudo prefixes. */
7775 as_bad_where (insn_start_frag->fr_file,
7776 insn_start_frag->fr_line,
7777 _("pseudo prefix without instruction"));
7783 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7784 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7785 R_X86_64_GOTTPOFF relocation so that linker can safely
7786 perform IE->LE optimization. */
7787 if (x86_elf_abi == X86_64_X32_ABI
7789 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7790 && i.prefix[REX_PREFIX] == 0)
7791 add_prefix (REX_OPCODE);
7794 /* The prefix bytes. */
7795 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7797 FRAG_APPEND_1_CHAR (*q);
7801 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7806 /* REX byte is encoded in VEX prefix. */
7810 FRAG_APPEND_1_CHAR (*q);
7813 /* There should be no other prefixes for instructions
7818 /* For EVEX instructions i.vrex should become 0 after
7819 build_evex_prefix. For VEX instructions upper 16 registers
7820 aren't available, so VREX should be 0. */
7823 /* Now the VEX prefix. */
7824 p = frag_more (i.vex.length);
7825 for (j = 0; j < i.vex.length; j++)
7826 p[j] = i.vex.bytes[j];
7829 /* Now the opcode; be careful about word order here! */
7830 if (i.tm.opcode_length == 1)
7832 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7836 switch (i.tm.opcode_length)
7840 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7841 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7845 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7855 /* Put out high byte first: can't use md_number_to_chars! */
7856 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7857 *p = i.tm.base_opcode & 0xff;
7860 /* Now the modrm byte and sib byte (if present). */
7861 if (i.tm.opcode_modifier.modrm)
7863 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7866 /* If i.rm.regmem == ESP (4)
7867 && i.rm.mode != (Register mode)
7869 ==> need second modrm byte. */
7870 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7872 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7873 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7875 | i.sib.scale << 6));
7878 if (i.disp_operands)
7879 output_disp (insn_start_frag, insn_start_off);
7882 output_imm (insn_start_frag, insn_start_off);
7888 pi ("" /*line*/, &i);
7890 #endif /* DEBUG386 */
7893 /* Return the size of the displacement operand N. */
7896 disp_size (unsigned int n)
7900 if (i.types[n].bitfield.disp64)
7902 else if (i.types[n].bitfield.disp8)
7904 else if (i.types[n].bitfield.disp16)
7909 /* Return the size of the immediate operand N. */
7912 imm_size (unsigned int n)
7915 if (i.types[n].bitfield.imm64)
7917 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7919 else if (i.types[n].bitfield.imm16)
7925 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7930 for (n = 0; n < i.operands; n++)
7932 if (operand_type_check (i.types[n], disp))
7934 if (i.op[n].disps->X_op == O_constant)
7936 int size = disp_size (n);
7937 offsetT val = i.op[n].disps->X_add_number;
7939 val = offset_in_range (val >> i.memshift, size);
7940 p = frag_more (size);
7941 md_number_to_chars (p, val, size);
7945 enum bfd_reloc_code_real reloc_type;
7946 int size = disp_size (n);
7947 int sign = i.types[n].bitfield.disp32s;
7948 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7951 /* We can't have 8 bit displacement here. */
7952 gas_assert (!i.types[n].bitfield.disp8);
7954 /* The PC relative address is computed relative
7955 to the instruction boundary, so in case immediate
7956 fields follows, we need to adjust the value. */
7957 if (pcrel && i.imm_operands)
7962 for (n1 = 0; n1 < i.operands; n1++)
7963 if (operand_type_check (i.types[n1], imm))
7965 /* Only one immediate is allowed for PC
7966 relative address. */
7967 gas_assert (sz == 0);
7969 i.op[n].disps->X_add_number -= sz;
7971 /* We should find the immediate. */
7972 gas_assert (sz != 0);
7975 p = frag_more (size);
7976 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7978 && GOT_symbol == i.op[n].disps->X_add_symbol
7979 && (((reloc_type == BFD_RELOC_32
7980 || reloc_type == BFD_RELOC_X86_64_32S
7981 || (reloc_type == BFD_RELOC_64
7983 && (i.op[n].disps->X_op == O_symbol
7984 || (i.op[n].disps->X_op == O_add
7985 && ((symbol_get_value_expression
7986 (i.op[n].disps->X_op_symbol)->X_op)
7988 || reloc_type == BFD_RELOC_32_PCREL))
7992 if (insn_start_frag == frag_now)
7993 add = (p - frag_now->fr_literal) - insn_start_off;
7998 add = insn_start_frag->fr_fix - insn_start_off;
7999 for (fr = insn_start_frag->fr_next;
8000 fr && fr != frag_now; fr = fr->fr_next)
8002 add += p - frag_now->fr_literal;
8007 reloc_type = BFD_RELOC_386_GOTPC;
8008 i.op[n].imms->X_add_number += add;
8010 else if (reloc_type == BFD_RELOC_64)
8011 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8013 /* Don't do the adjustment for x86-64, as there
8014 the pcrel addressing is relative to the _next_
8015 insn, and that is taken care of in other code. */
8016 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8018 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8019 size, i.op[n].disps, pcrel,
8021 /* Check for "call/jmp *mem", "mov mem, %reg",
8022 "test %reg, mem" and "binop mem, %reg" where binop
8023 is one of adc, add, and, cmp, or, sbb, sub, xor
8024 instructions. Always generate R_386_GOT32X for
8025 "sym*GOT" operand in 32-bit mode. */
8026 if ((generate_relax_relocations
8029 && i.rm.regmem == 5))
8031 || (i.rm.mode == 0 && i.rm.regmem == 5))
8032 && ((i.operands == 1
8033 && i.tm.base_opcode == 0xff
8034 && (i.rm.reg == 2 || i.rm.reg == 4))
8036 && (i.tm.base_opcode == 0x8b
8037 || i.tm.base_opcode == 0x85
8038 || (i.tm.base_opcode & 0xc7) == 0x03))))
8042 fixP->fx_tcbit = i.rex != 0;
8044 && (i.base_reg->reg_num == RegRip
8045 || i.base_reg->reg_num == RegEip))
8046 fixP->fx_tcbit2 = 1;
8049 fixP->fx_tcbit2 = 1;
8057 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8062 for (n = 0; n < i.operands; n++)
8064 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8065 if (i.rounding && (int) n == i.rounding->operand)
8068 if (operand_type_check (i.types[n], imm))
8070 if (i.op[n].imms->X_op == O_constant)
8072 int size = imm_size (n);
8075 val = offset_in_range (i.op[n].imms->X_add_number,
8077 p = frag_more (size);
8078 md_number_to_chars (p, val, size);
8082 /* Not absolute_section.
8083 Need a 32-bit fixup (don't support 8bit
8084 non-absolute imms). Try to support other
8086 enum bfd_reloc_code_real reloc_type;
8087 int size = imm_size (n);
8090 if (i.types[n].bitfield.imm32s
8091 && (i.suffix == QWORD_MNEM_SUFFIX
8092 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8097 p = frag_more (size);
8098 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8100 /* This is tough to explain. We end up with this one if we
8101 * have operands that look like
8102 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8103 * obtain the absolute address of the GOT, and it is strongly
8104 * preferable from a performance point of view to avoid using
8105 * a runtime relocation for this. The actual sequence of
8106 * instructions often look something like:
8111 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8113 * The call and pop essentially return the absolute address
8114 * of the label .L66 and store it in %ebx. The linker itself
8115 * will ultimately change the first operand of the addl so
8116 * that %ebx points to the GOT, but to keep things simple, the
8117 * .o file must have this operand set so that it generates not
8118 * the absolute address of .L66, but the absolute address of
8119 * itself. This allows the linker itself simply treat a GOTPC
8120 * relocation as asking for a pcrel offset to the GOT to be
8121 * added in, and the addend of the relocation is stored in the
8122 * operand field for the instruction itself.
8124 * Our job here is to fix the operand so that it would add
8125 * the correct offset so that %ebx would point to itself. The
8126 * thing that is tricky is that .-.L66 will point to the
8127 * beginning of the instruction, so we need to further modify
8128 * the operand so that it will point to itself. There are
8129 * other cases where you have something like:
8131 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8133 * and here no correction would be required. Internally in
8134 * the assembler we treat operands of this form as not being
8135 * pcrel since the '.' is explicitly mentioned, and I wonder
8136 * whether it would simplify matters to do it this way. Who
8137 * knows. In earlier versions of the PIC patches, the
8138 * pcrel_adjust field was used to store the correction, but
8139 * since the expression is not pcrel, I felt it would be
8140 * confusing to do it this way. */
8142 if ((reloc_type == BFD_RELOC_32
8143 || reloc_type == BFD_RELOC_X86_64_32S
8144 || reloc_type == BFD_RELOC_64)
8146 && GOT_symbol == i.op[n].imms->X_add_symbol
8147 && (i.op[n].imms->X_op == O_symbol
8148 || (i.op[n].imms->X_op == O_add
8149 && ((symbol_get_value_expression
8150 (i.op[n].imms->X_op_symbol)->X_op)
8155 if (insn_start_frag == frag_now)
8156 add = (p - frag_now->fr_literal) - insn_start_off;
8161 add = insn_start_frag->fr_fix - insn_start_off;
8162 for (fr = insn_start_frag->fr_next;
8163 fr && fr != frag_now; fr = fr->fr_next)
8165 add += p - frag_now->fr_literal;
8169 reloc_type = BFD_RELOC_386_GOTPC;
8171 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8173 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8174 i.op[n].imms->X_add_number += add;
8176 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8177 i.op[n].imms, 0, reloc_type);
8183 /* x86_cons_fix_new is called via the expression parsing code when a
8184 reloc is needed. We use this hook to get the correct .got reloc. */
8185 static int cons_sign = -1;
8188 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8189 expressionS *exp, bfd_reloc_code_real_type r)
8191 r = reloc (len, 0, cons_sign, r);
8194 if (exp->X_op == O_secrel)
8196 exp->X_op = O_symbol;
8197 r = BFD_RELOC_32_SECREL;
8201 fix_new_exp (frag, off, len, exp, 0, r);
8204 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8205 purpose of the `.dc.a' internal pseudo-op. */
8208 x86_address_bytes (void)
8210 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8212 return stdoutput->arch_info->bits_per_address / 8;
8215 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8217 # define lex_got(reloc, adjust, types) NULL
8219 /* Parse operands of the form
8220 <symbol>@GOTOFF+<nnn>
8221 and similar .plt or .got references.
8223 If we find one, set up the correct relocation in RELOC and copy the
8224 input string, minus the `@GOTOFF' into a malloc'd buffer for
8225 parsing by the calling routine. Return this buffer, and if ADJUST
8226 is non-null set it to the length of the string we removed from the
8227 input line. Otherwise return NULL. */
8229 lex_got (enum bfd_reloc_code_real *rel,
8231 i386_operand_type *types)
8233 /* Some of the relocations depend on the size of what field is to
8234 be relocated. But in our callers i386_immediate and i386_displacement
8235 we don't yet know the operand size (this will be set by insn
8236 matching). Hence we record the word32 relocation here,
8237 and adjust the reloc according to the real size in reloc(). */
8238 static const struct {
8241 const enum bfd_reloc_code_real rel[2];
8242 const i386_operand_type types64;
8244 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8245 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8247 OPERAND_TYPE_IMM32_64 },
8249 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8250 BFD_RELOC_X86_64_PLTOFF64 },
8251 OPERAND_TYPE_IMM64 },
8252 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8253 BFD_RELOC_X86_64_PLT32 },
8254 OPERAND_TYPE_IMM32_32S_DISP32 },
8255 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8256 BFD_RELOC_X86_64_GOTPLT64 },
8257 OPERAND_TYPE_IMM64_DISP64 },
8258 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8259 BFD_RELOC_X86_64_GOTOFF64 },
8260 OPERAND_TYPE_IMM64_DISP64 },
8261 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8262 BFD_RELOC_X86_64_GOTPCREL },
8263 OPERAND_TYPE_IMM32_32S_DISP32 },
8264 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8265 BFD_RELOC_X86_64_TLSGD },
8266 OPERAND_TYPE_IMM32_32S_DISP32 },
8267 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8268 _dummy_first_bfd_reloc_code_real },
8269 OPERAND_TYPE_NONE },
8270 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8271 BFD_RELOC_X86_64_TLSLD },
8272 OPERAND_TYPE_IMM32_32S_DISP32 },
8273 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8274 BFD_RELOC_X86_64_GOTTPOFF },
8275 OPERAND_TYPE_IMM32_32S_DISP32 },
8276 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8277 BFD_RELOC_X86_64_TPOFF32 },
8278 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8279 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8280 _dummy_first_bfd_reloc_code_real },
8281 OPERAND_TYPE_NONE },
8282 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8283 BFD_RELOC_X86_64_DTPOFF32 },
8284 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8285 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8286 _dummy_first_bfd_reloc_code_real },
8287 OPERAND_TYPE_NONE },
8288 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8289 _dummy_first_bfd_reloc_code_real },
8290 OPERAND_TYPE_NONE },
8291 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8292 BFD_RELOC_X86_64_GOT32 },
8293 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8294 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8295 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8296 OPERAND_TYPE_IMM32_32S_DISP32 },
8297 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8298 BFD_RELOC_X86_64_TLSDESC_CALL },
8299 OPERAND_TYPE_IMM32_32S_DISP32 },
8304 #if defined (OBJ_MAYBE_ELF)
8309 for (cp = input_line_pointer; *cp != '@'; cp++)
8310 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8313 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8315 int len = gotrel[j].len;
8316 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8318 if (gotrel[j].rel[object_64bit] != 0)
8321 char *tmpbuf, *past_reloc;
8323 *rel = gotrel[j].rel[object_64bit];
8327 if (flag_code != CODE_64BIT)
8329 types->bitfield.imm32 = 1;
8330 types->bitfield.disp32 = 1;
8333 *types = gotrel[j].types64;
8336 if (j != 0 && GOT_symbol == NULL)
8337 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8339 /* The length of the first part of our input line. */
8340 first = cp - input_line_pointer;
8342 /* The second part goes from after the reloc token until
8343 (and including) an end_of_line char or comma. */
8344 past_reloc = cp + 1 + len;
8346 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8348 second = cp + 1 - past_reloc;
8350 /* Allocate and copy string. The trailing NUL shouldn't
8351 be necessary, but be safe. */
8352 tmpbuf = XNEWVEC (char, first + second + 2);
8353 memcpy (tmpbuf, input_line_pointer, first);
8354 if (second != 0 && *past_reloc != ' ')
8355 /* Replace the relocation token with ' ', so that
8356 errors like foo@GOTOFF1 will be detected. */
8357 tmpbuf[first++] = ' ';
8359 /* Increment length by 1 if the relocation token is
8364 memcpy (tmpbuf + first, past_reloc, second);
8365 tmpbuf[first + second] = '\0';
8369 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8370 gotrel[j].str, 1 << (5 + object_64bit));
8375 /* Might be a symbol version string. Don't as_bad here. */
8384 /* Parse operands of the form
8385 <symbol>@SECREL32+<nnn>
8387 If we find one, set up the correct relocation in RELOC and copy the
8388 input string, minus the `@SECREL32' into a malloc'd buffer for
8389 parsing by the calling routine. Return this buffer, and if ADJUST
8390 is non-null set it to the length of the string we removed from the
8391 input line. Otherwise return NULL.
8393 This function is copied from the ELF version above adjusted for PE targets. */
8396 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8397 int *adjust ATTRIBUTE_UNUSED,
8398 i386_operand_type *types)
8404 const enum bfd_reloc_code_real rel[2];
8405 const i386_operand_type types64;
8409 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8410 BFD_RELOC_32_SECREL },
8411 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8417 for (cp = input_line_pointer; *cp != '@'; cp++)
8418 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8421 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8423 int len = gotrel[j].len;
8425 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8427 if (gotrel[j].rel[object_64bit] != 0)
8430 char *tmpbuf, *past_reloc;
8432 *rel = gotrel[j].rel[object_64bit];
8438 if (flag_code != CODE_64BIT)
8440 types->bitfield.imm32 = 1;
8441 types->bitfield.disp32 = 1;
8444 *types = gotrel[j].types64;
8447 /* The length of the first part of our input line. */
8448 first = cp - input_line_pointer;
8450 /* The second part goes from after the reloc token until
8451 (and including) an end_of_line char or comma. */
8452 past_reloc = cp + 1 + len;
8454 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8456 second = cp + 1 - past_reloc;
8458 /* Allocate and copy string. The trailing NUL shouldn't
8459 be necessary, but be safe. */
8460 tmpbuf = XNEWVEC (char, first + second + 2);
8461 memcpy (tmpbuf, input_line_pointer, first);
8462 if (second != 0 && *past_reloc != ' ')
8463 /* Replace the relocation token with ' ', so that
8464 errors like foo@SECLREL321 will be detected. */
8465 tmpbuf[first++] = ' ';
8466 memcpy (tmpbuf + first, past_reloc, second);
8467 tmpbuf[first + second] = '\0';
8471 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8472 gotrel[j].str, 1 << (5 + object_64bit));
8477 /* Might be a symbol version string. Don't as_bad here. */
8483 bfd_reloc_code_real_type
8484 x86_cons (expressionS *exp, int size)
8486 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8488 intel_syntax = -intel_syntax;
8491 if (size == 4 || (object_64bit && size == 8))
8493 /* Handle @GOTOFF and the like in an expression. */
8495 char *gotfree_input_line;
8498 save = input_line_pointer;
8499 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8500 if (gotfree_input_line)
8501 input_line_pointer = gotfree_input_line;
8505 if (gotfree_input_line)
8507 /* expression () has merrily parsed up to the end of line,
8508 or a comma - in the wrong buffer. Transfer how far
8509 input_line_pointer has moved to the right buffer. */
8510 input_line_pointer = (save
8511 + (input_line_pointer - gotfree_input_line)
8513 free (gotfree_input_line);
8514 if (exp->X_op == O_constant
8515 || exp->X_op == O_absent
8516 || exp->X_op == O_illegal
8517 || exp->X_op == O_register
8518 || exp->X_op == O_big)
8520 char c = *input_line_pointer;
8521 *input_line_pointer = 0;
8522 as_bad (_("missing or invalid expression `%s'"), save);
8523 *input_line_pointer = c;
8530 intel_syntax = -intel_syntax;
8533 i386_intel_simplify (exp);
8539 signed_cons (int size)
8541 if (flag_code == CODE_64BIT)
8549 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8556 if (exp.X_op == O_symbol)
8557 exp.X_op = O_secrel;
8559 emit_expr (&exp, 4);
8561 while (*input_line_pointer++ == ',');
8563 input_line_pointer--;
8564 demand_empty_rest_of_line ();
8568 /* Handle Vector operations. */
8571 check_VecOperations (char *op_string, char *op_end)
8573 const reg_entry *mask;
8578 && (op_end == NULL || op_string < op_end))
8581 if (*op_string == '{')
8585 /* Check broadcasts. */
8586 if (strncmp (op_string, "1to", 3) == 0)
8591 goto duplicated_vec_op;
8594 if (*op_string == '8')
8596 else if (*op_string == '4')
8598 else if (*op_string == '2')
8600 else if (*op_string == '1'
8601 && *(op_string+1) == '6')
8608 as_bad (_("Unsupported broadcast: `%s'"), saved);
8613 broadcast_op.type = bcst_type;
8614 broadcast_op.operand = this_operand;
8615 i.broadcast = &broadcast_op;
8617 /* Check masking operation. */
8618 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8620 /* k0 can't be used for write mask. */
8621 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8623 as_bad (_("`%s%s' can't be used for write mask"),
8624 register_prefix, mask->reg_name);
8630 mask_op.mask = mask;
8631 mask_op.zeroing = 0;
8632 mask_op.operand = this_operand;
8638 goto duplicated_vec_op;
8640 i.mask->mask = mask;
8642 /* Only "{z}" is allowed here. No need to check
8643 zeroing mask explicitly. */
8644 if (i.mask->operand != this_operand)
8646 as_bad (_("invalid write mask `%s'"), saved);
8653 /* Check zeroing-flag for masking operation. */
8654 else if (*op_string == 'z')
8658 mask_op.mask = NULL;
8659 mask_op.zeroing = 1;
8660 mask_op.operand = this_operand;
8665 if (i.mask->zeroing)
8668 as_bad (_("duplicated `%s'"), saved);
8672 i.mask->zeroing = 1;
8674 /* Only "{%k}" is allowed here. No need to check mask
8675 register explicitly. */
8676 if (i.mask->operand != this_operand)
8678 as_bad (_("invalid zeroing-masking `%s'"),
8687 goto unknown_vec_op;
8689 if (*op_string != '}')
8691 as_bad (_("missing `}' in `%s'"), saved);
8696 /* Strip whitespace since the addition of pseudo prefixes
8697 changed how the scrubber treats '{'. */
8698 if (is_space_char (*op_string))
8704 /* We don't know this one. */
8705 as_bad (_("unknown vector operation: `%s'"), saved);
8709 if (i.mask && i.mask->zeroing && !i.mask->mask)
8711 as_bad (_("zeroing-masking only allowed with write mask"));
8719 i386_immediate (char *imm_start)
8721 char *save_input_line_pointer;
8722 char *gotfree_input_line;
8725 i386_operand_type types;
8727 operand_type_set (&types, ~0);
8729 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8731 as_bad (_("at most %d immediate operands are allowed"),
8732 MAX_IMMEDIATE_OPERANDS);
8736 exp = &im_expressions[i.imm_operands++];
8737 i.op[this_operand].imms = exp;
8739 if (is_space_char (*imm_start))
8742 save_input_line_pointer = input_line_pointer;
8743 input_line_pointer = imm_start;
8745 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8746 if (gotfree_input_line)
8747 input_line_pointer = gotfree_input_line;
8749 exp_seg = expression (exp);
8753 /* Handle vector operations. */
8754 if (*input_line_pointer == '{')
8756 input_line_pointer = check_VecOperations (input_line_pointer,
8758 if (input_line_pointer == NULL)
8762 if (*input_line_pointer)
8763 as_bad (_("junk `%s' after expression"), input_line_pointer);
8765 input_line_pointer = save_input_line_pointer;
8766 if (gotfree_input_line)
8768 free (gotfree_input_line);
8770 if (exp->X_op == O_constant || exp->X_op == O_register)
8771 exp->X_op = O_illegal;
8774 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8778 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8779 i386_operand_type types, const char *imm_start)
8781 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8784 as_bad (_("missing or invalid immediate expression `%s'"),
8788 else if (exp->X_op == O_constant)
8790 /* Size it properly later. */
8791 i.types[this_operand].bitfield.imm64 = 1;
8792 /* If not 64bit, sign extend val. */
8793 if (flag_code != CODE_64BIT
8794 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8796 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8798 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8799 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8800 && exp_seg != absolute_section
8801 && exp_seg != text_section
8802 && exp_seg != data_section
8803 && exp_seg != bss_section
8804 && exp_seg != undefined_section
8805 && !bfd_is_com_section (exp_seg))
8807 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8811 else if (!intel_syntax && exp_seg == reg_section)
8814 as_bad (_("illegal immediate register operand %s"), imm_start);
8819 /* This is an address. The size of the address will be
8820 determined later, depending on destination register,
8821 suffix, or the default for the section. */
8822 i.types[this_operand].bitfield.imm8 = 1;
8823 i.types[this_operand].bitfield.imm16 = 1;
8824 i.types[this_operand].bitfield.imm32 = 1;
8825 i.types[this_operand].bitfield.imm32s = 1;
8826 i.types[this_operand].bitfield.imm64 = 1;
8827 i.types[this_operand] = operand_type_and (i.types[this_operand],
8835 i386_scale (char *scale)
8838 char *save = input_line_pointer;
8840 input_line_pointer = scale;
8841 val = get_absolute_expression ();
8846 i.log2_scale_factor = 0;
8849 i.log2_scale_factor = 1;
8852 i.log2_scale_factor = 2;
8855 i.log2_scale_factor = 3;
8859 char sep = *input_line_pointer;
8861 *input_line_pointer = '\0';
8862 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8864 *input_line_pointer = sep;
8865 input_line_pointer = save;
8869 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8871 as_warn (_("scale factor of %d without an index register"),
8872 1 << i.log2_scale_factor);
8873 i.log2_scale_factor = 0;
8875 scale = input_line_pointer;
8876 input_line_pointer = save;
8881 i386_displacement (char *disp_start, char *disp_end)
8885 char *save_input_line_pointer;
8886 char *gotfree_input_line;
8888 i386_operand_type bigdisp, types = anydisp;
8891 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8893 as_bad (_("at most %d displacement operands are allowed"),
8894 MAX_MEMORY_OPERANDS);
8898 operand_type_set (&bigdisp, 0);
8899 if ((i.types[this_operand].bitfield.jumpabsolute)
8900 || (!current_templates->start->opcode_modifier.jump
8901 && !current_templates->start->opcode_modifier.jumpdword))
8903 bigdisp.bitfield.disp32 = 1;
8904 override = (i.prefix[ADDR_PREFIX] != 0);
8905 if (flag_code == CODE_64BIT)
8909 bigdisp.bitfield.disp32s = 1;
8910 bigdisp.bitfield.disp64 = 1;
8913 else if ((flag_code == CODE_16BIT) ^ override)
8915 bigdisp.bitfield.disp32 = 0;
8916 bigdisp.bitfield.disp16 = 1;
8921 /* For PC-relative branches, the width of the displacement
8922 is dependent upon data size, not address size. */
8923 override = (i.prefix[DATA_PREFIX] != 0);
8924 if (flag_code == CODE_64BIT)
8926 if (override || i.suffix == WORD_MNEM_SUFFIX)
8927 bigdisp.bitfield.disp16 = 1;
8930 bigdisp.bitfield.disp32 = 1;
8931 bigdisp.bitfield.disp32s = 1;
8937 override = (i.suffix == (flag_code != CODE_16BIT
8939 : LONG_MNEM_SUFFIX));
8940 bigdisp.bitfield.disp32 = 1;
8941 if ((flag_code == CODE_16BIT) ^ override)
8943 bigdisp.bitfield.disp32 = 0;
8944 bigdisp.bitfield.disp16 = 1;
8948 i.types[this_operand] = operand_type_or (i.types[this_operand],
8951 exp = &disp_expressions[i.disp_operands];
8952 i.op[this_operand].disps = exp;
8954 save_input_line_pointer = input_line_pointer;
8955 input_line_pointer = disp_start;
8956 END_STRING_AND_SAVE (disp_end);
8958 #ifndef GCC_ASM_O_HACK
8959 #define GCC_ASM_O_HACK 0
8962 END_STRING_AND_SAVE (disp_end + 1);
8963 if (i.types[this_operand].bitfield.baseIndex
8964 && displacement_string_end[-1] == '+')
8966 /* This hack is to avoid a warning when using the "o"
8967 constraint within gcc asm statements.
8970 #define _set_tssldt_desc(n,addr,limit,type) \
8971 __asm__ __volatile__ ( \
8973 "movw %w1,2+%0\n\t" \
8975 "movb %b1,4+%0\n\t" \
8976 "movb %4,5+%0\n\t" \
8977 "movb $0,6+%0\n\t" \
8978 "movb %h1,7+%0\n\t" \
8980 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8982 This works great except that the output assembler ends
8983 up looking a bit weird if it turns out that there is
8984 no offset. You end up producing code that looks like:
8997 So here we provide the missing zero. */
8999 *displacement_string_end = '0';
9002 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9003 if (gotfree_input_line)
9004 input_line_pointer = gotfree_input_line;
9006 exp_seg = expression (exp);
9009 if (*input_line_pointer)
9010 as_bad (_("junk `%s' after expression"), input_line_pointer);
9012 RESTORE_END_STRING (disp_end + 1);
9014 input_line_pointer = save_input_line_pointer;
9015 if (gotfree_input_line)
9017 free (gotfree_input_line);
9019 if (exp->X_op == O_constant || exp->X_op == O_register)
9020 exp->X_op = O_illegal;
9023 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9025 RESTORE_END_STRING (disp_end);
9031 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9032 i386_operand_type types, const char *disp_start)
9034 i386_operand_type bigdisp;
9037 /* We do this to make sure that the section symbol is in
9038 the symbol table. We will ultimately change the relocation
9039 to be relative to the beginning of the section. */
9040 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9041 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9042 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9044 if (exp->X_op != O_symbol)
9047 if (S_IS_LOCAL (exp->X_add_symbol)
9048 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9049 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9050 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9051 exp->X_op = O_subtract;
9052 exp->X_op_symbol = GOT_symbol;
9053 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9054 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9055 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9056 i.reloc[this_operand] = BFD_RELOC_64;
9058 i.reloc[this_operand] = BFD_RELOC_32;
9061 else if (exp->X_op == O_absent
9062 || exp->X_op == O_illegal
9063 || exp->X_op == O_big)
9066 as_bad (_("missing or invalid displacement expression `%s'"),
9071 else if (flag_code == CODE_64BIT
9072 && !i.prefix[ADDR_PREFIX]
9073 && exp->X_op == O_constant)
9075 /* Since displacement is signed extended to 64bit, don't allow
9076 disp32 and turn off disp32s if they are out of range. */
9077 i.types[this_operand].bitfield.disp32 = 0;
9078 if (!fits_in_signed_long (exp->X_add_number))
9080 i.types[this_operand].bitfield.disp32s = 0;
9081 if (i.types[this_operand].bitfield.baseindex)
9083 as_bad (_("0x%lx out range of signed 32bit displacement"),
9084 (long) exp->X_add_number);
9090 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9091 else if (exp->X_op != O_constant
9092 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9093 && exp_seg != absolute_section
9094 && exp_seg != text_section
9095 && exp_seg != data_section
9096 && exp_seg != bss_section
9097 && exp_seg != undefined_section
9098 && !bfd_is_com_section (exp_seg))
9100 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9105 /* Check if this is a displacement only operand. */
9106 bigdisp = i.types[this_operand];
9107 bigdisp.bitfield.disp8 = 0;
9108 bigdisp.bitfield.disp16 = 0;
9109 bigdisp.bitfield.disp32 = 0;
9110 bigdisp.bitfield.disp32s = 0;
9111 bigdisp.bitfield.disp64 = 0;
9112 if (operand_type_all_zero (&bigdisp))
9113 i.types[this_operand] = operand_type_and (i.types[this_operand],
9119 /* Return the active addressing mode, taking address override and
9120 registers forming the address into consideration. Update the
9121 address override prefix if necessary. */
9123 static enum flag_code
9124 i386_addressing_mode (void)
9126 enum flag_code addr_mode;
9128 if (i.prefix[ADDR_PREFIX])
9129 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9132 addr_mode = flag_code;
9134 #if INFER_ADDR_PREFIX
9135 if (i.mem_operands == 0)
9137 /* Infer address prefix from the first memory operand. */
9138 const reg_entry *addr_reg = i.base_reg;
9140 if (addr_reg == NULL)
9141 addr_reg = i.index_reg;
9145 if (addr_reg->reg_num == RegEip
9146 || addr_reg->reg_num == RegEiz
9147 || addr_reg->reg_type.bitfield.dword)
9148 addr_mode = CODE_32BIT;
9149 else if (flag_code != CODE_64BIT
9150 && addr_reg->reg_type.bitfield.word)
9151 addr_mode = CODE_16BIT;
9153 if (addr_mode != flag_code)
9155 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9157 /* Change the size of any displacement too. At most one
9158 of Disp16 or Disp32 is set.
9159 FIXME. There doesn't seem to be any real need for
9160 separate Disp16 and Disp32 flags. The same goes for
9161 Imm16 and Imm32. Removing them would probably clean
9162 up the code quite a lot. */
9163 if (flag_code != CODE_64BIT
9164 && (i.types[this_operand].bitfield.disp16
9165 || i.types[this_operand].bitfield.disp32))
9166 i.types[this_operand]
9167 = operand_type_xor (i.types[this_operand], disp16_32);
9177 /* Make sure the memory operand we've been dealt is valid.
9178 Return 1 on success, 0 on a failure. */
9181 i386_index_check (const char *operand_string)
9183 const char *kind = "base/index";
9184 enum flag_code addr_mode = i386_addressing_mode ();
9186 if (current_templates->start->opcode_modifier.isstring
9187 && !current_templates->start->opcode_modifier.immext
9188 && (current_templates->end[-1].opcode_modifier.isstring
9191 /* Memory operands of string insns are special in that they only allow
9192 a single register (rDI, rSI, or rBX) as their memory address. */
9193 const reg_entry *expected_reg;
9194 static const char *di_si[][2] =
9200 static const char *bx[] = { "ebx", "bx", "rbx" };
9202 kind = "string address";
9204 if (current_templates->start->opcode_modifier.repprefixok)
9206 i386_operand_type type = current_templates->end[-1].operand_types[0];
9208 if (!type.bitfield.baseindex
9209 || ((!i.mem_operands != !intel_syntax)
9210 && current_templates->end[-1].operand_types[1]
9211 .bitfield.baseindex))
9212 type = current_templates->end[-1].operand_types[1];
9213 expected_reg = hash_find (reg_hash,
9214 di_si[addr_mode][type.bitfield.esseg]);
9218 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9220 if (i.base_reg != expected_reg
9222 || operand_type_check (i.types[this_operand], disp))
9224 /* The second memory operand must have the same size as
9228 && !((addr_mode == CODE_64BIT
9229 && i.base_reg->reg_type.bitfield.qword)
9230 || (addr_mode == CODE_32BIT
9231 ? i.base_reg->reg_type.bitfield.dword
9232 : i.base_reg->reg_type.bitfield.word)))
9235 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9237 intel_syntax ? '[' : '(',
9239 expected_reg->reg_name,
9240 intel_syntax ? ']' : ')');
9247 as_bad (_("`%s' is not a valid %s expression"),
9248 operand_string, kind);
9253 if (addr_mode != CODE_16BIT)
9255 /* 32-bit/64-bit checks. */
9257 && (addr_mode == CODE_64BIT
9258 ? !i.base_reg->reg_type.bitfield.qword
9259 : !i.base_reg->reg_type.bitfield.dword)
9261 || (i.base_reg->reg_num
9262 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9264 && !i.index_reg->reg_type.bitfield.xmmword
9265 && !i.index_reg->reg_type.bitfield.ymmword
9266 && !i.index_reg->reg_type.bitfield.zmmword
9267 && ((addr_mode == CODE_64BIT
9268 ? !(i.index_reg->reg_type.bitfield.qword
9269 || i.index_reg->reg_num == RegRiz)
9270 : !(i.index_reg->reg_type.bitfield.dword
9271 || i.index_reg->reg_num == RegEiz))
9272 || !i.index_reg->reg_type.bitfield.baseindex)))
9275 /* bndmk, bndldx, and bndstx have special restrictions. */
9276 if (current_templates->start->base_opcode == 0xf30f1b
9277 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9279 /* They cannot use RIP-relative addressing. */
9280 if (i.base_reg && i.base_reg->reg_num == RegRip)
9282 as_bad (_("`%s' cannot be used here"), operand_string);
9286 /* bndldx and bndstx ignore their scale factor. */
9287 if (current_templates->start->base_opcode != 0xf30f1b
9288 && i.log2_scale_factor)
9289 as_warn (_("register scaling is being ignored here"));
9294 /* 16-bit checks. */
9296 && (!i.base_reg->reg_type.bitfield.word
9297 || !i.base_reg->reg_type.bitfield.baseindex))
9299 && (!i.index_reg->reg_type.bitfield.word
9300 || !i.index_reg->reg_type.bitfield.baseindex
9302 && i.base_reg->reg_num < 6
9303 && i.index_reg->reg_num >= 6
9304 && i.log2_scale_factor == 0))))
9311 /* Handle vector immediates. */
9314 RC_SAE_immediate (const char *imm_start)
9316 unsigned int match_found, j;
9317 const char *pstr = imm_start;
9325 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9327 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9331 rc_op.type = RC_NamesTable[j].type;
9332 rc_op.operand = this_operand;
9333 i.rounding = &rc_op;
9337 as_bad (_("duplicated `%s'"), imm_start);
9340 pstr += RC_NamesTable[j].len;
9350 as_bad (_("Missing '}': '%s'"), imm_start);
9353 /* RC/SAE immediate string should contain nothing more. */;
9356 as_bad (_("Junk after '}': '%s'"), imm_start);
9360 exp = &im_expressions[i.imm_operands++];
9361 i.op[this_operand].imms = exp;
9363 exp->X_op = O_constant;
9364 exp->X_add_number = 0;
9365 exp->X_add_symbol = (symbolS *) 0;
9366 exp->X_op_symbol = (symbolS *) 0;
9368 i.types[this_operand].bitfield.imm8 = 1;
9372 /* Only string instructions can have a second memory operand, so
9373 reduce current_templates to just those if it contains any. */
9375 maybe_adjust_templates (void)
9377 const insn_template *t;
9379 gas_assert (i.mem_operands == 1);
9381 for (t = current_templates->start; t < current_templates->end; ++t)
9382 if (t->opcode_modifier.isstring)
9385 if (t < current_templates->end)
9387 static templates aux_templates;
9388 bfd_boolean recheck;
9390 aux_templates.start = t;
9391 for (; t < current_templates->end; ++t)
9392 if (!t->opcode_modifier.isstring)
9394 aux_templates.end = t;
9396 /* Determine whether to re-check the first memory operand. */
9397 recheck = (aux_templates.start != current_templates->start
9398 || t != current_templates->end);
9400 current_templates = &aux_templates;
9405 if (i.memop1_string != NULL
9406 && i386_index_check (i.memop1_string) == 0)
9415 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9419 i386_att_operand (char *operand_string)
9423 char *op_string = operand_string;
9425 if (is_space_char (*op_string))
9428 /* We check for an absolute prefix (differentiating,
9429 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9430 if (*op_string == ABSOLUTE_PREFIX)
9433 if (is_space_char (*op_string))
9435 i.types[this_operand].bitfield.jumpabsolute = 1;
9438 /* Check if operand is a register. */
9439 if ((r = parse_register (op_string, &end_op)) != NULL)
9441 i386_operand_type temp;
9443 /* Check for a segment override by searching for ':' after a
9444 segment register. */
9446 if (is_space_char (*op_string))
9448 if (*op_string == ':'
9449 && (r->reg_type.bitfield.sreg2
9450 || r->reg_type.bitfield.sreg3))
9455 i.seg[i.mem_operands] = &es;
9458 i.seg[i.mem_operands] = &cs;
9461 i.seg[i.mem_operands] = &ss;
9464 i.seg[i.mem_operands] = &ds;
9467 i.seg[i.mem_operands] = &fs;
9470 i.seg[i.mem_operands] = &gs;
9474 /* Skip the ':' and whitespace. */
9476 if (is_space_char (*op_string))
9479 if (!is_digit_char (*op_string)
9480 && !is_identifier_char (*op_string)
9481 && *op_string != '('
9482 && *op_string != ABSOLUTE_PREFIX)
9484 as_bad (_("bad memory operand `%s'"), op_string);
9487 /* Handle case of %es:*foo. */
9488 if (*op_string == ABSOLUTE_PREFIX)
9491 if (is_space_char (*op_string))
9493 i.types[this_operand].bitfield.jumpabsolute = 1;
9495 goto do_memory_reference;
9498 /* Handle vector operations. */
9499 if (*op_string == '{')
9501 op_string = check_VecOperations (op_string, NULL);
9502 if (op_string == NULL)
9508 as_bad (_("junk `%s' after register"), op_string);
9512 temp.bitfield.baseindex = 0;
9513 i.types[this_operand] = operand_type_or (i.types[this_operand],
9515 i.types[this_operand].bitfield.unspecified = 0;
9516 i.op[this_operand].regs = r;
9519 else if (*op_string == REGISTER_PREFIX)
9521 as_bad (_("bad register name `%s'"), op_string);
9524 else if (*op_string == IMMEDIATE_PREFIX)
9527 if (i.types[this_operand].bitfield.jumpabsolute)
9529 as_bad (_("immediate operand illegal with absolute jump"));
9532 if (!i386_immediate (op_string))
9535 else if (RC_SAE_immediate (operand_string))
9537 /* If it is a RC or SAE immediate, do nothing. */
9540 else if (is_digit_char (*op_string)
9541 || is_identifier_char (*op_string)
9542 || *op_string == '"'
9543 || *op_string == '(')
9545 /* This is a memory reference of some sort. */
9548 /* Start and end of displacement string expression (if found). */
9549 char *displacement_string_start;
9550 char *displacement_string_end;
9553 do_memory_reference:
9554 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9556 if ((i.mem_operands == 1
9557 && !current_templates->start->opcode_modifier.isstring)
9558 || i.mem_operands == 2)
9560 as_bad (_("too many memory references for `%s'"),
9561 current_templates->start->name);
9565 /* Check for base index form. We detect the base index form by
9566 looking for an ')' at the end of the operand, searching
9567 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9569 base_string = op_string + strlen (op_string);
9571 /* Handle vector operations. */
9572 vop_start = strchr (op_string, '{');
9573 if (vop_start && vop_start < base_string)
9575 if (check_VecOperations (vop_start, base_string) == NULL)
9577 base_string = vop_start;
9581 if (is_space_char (*base_string))
9584 /* If we only have a displacement, set-up for it to be parsed later. */
9585 displacement_string_start = op_string;
9586 displacement_string_end = base_string + 1;
9588 if (*base_string == ')')
9591 unsigned int parens_balanced = 1;
9592 /* We've already checked that the number of left & right ()'s are
9593 equal, so this loop will not be infinite. */
9597 if (*base_string == ')')
9599 if (*base_string == '(')
9602 while (parens_balanced);
9604 temp_string = base_string;
9606 /* Skip past '(' and whitespace. */
9608 if (is_space_char (*base_string))
9611 if (*base_string == ','
9612 || ((i.base_reg = parse_register (base_string, &end_op))
9615 displacement_string_end = temp_string;
9617 i.types[this_operand].bitfield.baseindex = 1;
9621 base_string = end_op;
9622 if (is_space_char (*base_string))
9626 /* There may be an index reg or scale factor here. */
9627 if (*base_string == ',')
9630 if (is_space_char (*base_string))
9633 if ((i.index_reg = parse_register (base_string, &end_op))
9636 base_string = end_op;
9637 if (is_space_char (*base_string))
9639 if (*base_string == ',')
9642 if (is_space_char (*base_string))
9645 else if (*base_string != ')')
9647 as_bad (_("expecting `,' or `)' "
9648 "after index register in `%s'"),
9653 else if (*base_string == REGISTER_PREFIX)
9655 end_op = strchr (base_string, ',');
9658 as_bad (_("bad register name `%s'"), base_string);
9662 /* Check for scale factor. */
9663 if (*base_string != ')')
9665 char *end_scale = i386_scale (base_string);
9670 base_string = end_scale;
9671 if (is_space_char (*base_string))
9673 if (*base_string != ')')
9675 as_bad (_("expecting `)' "
9676 "after scale factor in `%s'"),
9681 else if (!i.index_reg)
9683 as_bad (_("expecting index register or scale factor "
9684 "after `,'; got '%c'"),
9689 else if (*base_string != ')')
9691 as_bad (_("expecting `,' or `)' "
9692 "after base register in `%s'"),
9697 else if (*base_string == REGISTER_PREFIX)
9699 end_op = strchr (base_string, ',');
9702 as_bad (_("bad register name `%s'"), base_string);
9707 /* If there's an expression beginning the operand, parse it,
9708 assuming displacement_string_start and
9709 displacement_string_end are meaningful. */
9710 if (displacement_string_start != displacement_string_end)
9712 if (!i386_displacement (displacement_string_start,
9713 displacement_string_end))
9717 /* Special case for (%dx) while doing input/output op. */
9719 && i.base_reg->reg_type.bitfield.inoutportreg
9721 && i.log2_scale_factor == 0
9722 && i.seg[i.mem_operands] == 0
9723 && !operand_type_check (i.types[this_operand], disp))
9725 i.types[this_operand] = i.base_reg->reg_type;
9729 if (i386_index_check (operand_string) == 0)
9731 i.types[this_operand].bitfield.mem = 1;
9732 if (i.mem_operands == 0)
9733 i.memop1_string = xstrdup (operand_string);
9738 /* It's not a memory operand; argh! */
9739 as_bad (_("invalid char %s beginning operand %d `%s'"),
9740 output_invalid (*op_string),
9745 return 1; /* Normal return. */
9748 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9749 that an rs_machine_dependent frag may reach. */
9752 i386_frag_max_var (fragS *frag)
9754 /* The only relaxable frags are for jumps.
9755 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9756 gas_assert (frag->fr_type == rs_machine_dependent);
9757 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9760 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9762 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9764 /* STT_GNU_IFUNC symbol must go through PLT. */
9765 if ((symbol_get_bfdsym (fr_symbol)->flags
9766 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9769 if (!S_IS_EXTERNAL (fr_symbol))
9770 /* Symbol may be weak or local. */
9771 return !S_IS_WEAK (fr_symbol);
9773 /* Global symbols with non-default visibility can't be preempted. */
9774 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9777 if (fr_var != NO_RELOC)
9778 switch ((enum bfd_reloc_code_real) fr_var)
9780 case BFD_RELOC_386_PLT32:
9781 case BFD_RELOC_X86_64_PLT32:
9782 /* Symbol with PLT relocation may be preempted. */
9788 /* Global symbols with default visibility in a shared library may be
9789 preempted by another definition. */
9794 /* md_estimate_size_before_relax()
9796 Called just before relax() for rs_machine_dependent frags. The x86
9797 assembler uses these frags to handle variable size jump
9800 Any symbol that is now undefined will not become defined.
9801 Return the correct fr_subtype in the frag.
9802 Return the initial "guess for variable size of frag" to caller.
9803 The guess is actually the growth beyond the fixed part. Whatever
9804 we do to grow the fixed or variable part contributes to our
9808 md_estimate_size_before_relax (fragS *fragP, segT segment)
9810 /* We've already got fragP->fr_subtype right; all we have to do is
9811 check for un-relaxable symbols. On an ELF system, we can't relax
9812 an externally visible symbol, because it may be overridden by a
9814 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9815 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9817 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9820 #if defined (OBJ_COFF) && defined (TE_PE)
9821 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9822 && S_IS_WEAK (fragP->fr_symbol))
9826 /* Symbol is undefined in this segment, or we need to keep a
9827 reloc so that weak symbols can be overridden. */
9828 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9829 enum bfd_reloc_code_real reloc_type;
9830 unsigned char *opcode;
9833 if (fragP->fr_var != NO_RELOC)
9834 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9836 reloc_type = BFD_RELOC_16_PCREL;
9837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9838 else if (need_plt32_p (fragP->fr_symbol))
9839 reloc_type = BFD_RELOC_X86_64_PLT32;
9842 reloc_type = BFD_RELOC_32_PCREL;
9844 old_fr_fix = fragP->fr_fix;
9845 opcode = (unsigned char *) fragP->fr_opcode;
9847 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9850 /* Make jmp (0xeb) a (d)word displacement jump. */
9852 fragP->fr_fix += size;
9853 fix_new (fragP, old_fr_fix, size,
9855 fragP->fr_offset, 1,
9861 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9863 /* Negate the condition, and branch past an
9864 unconditional jump. */
9867 /* Insert an unconditional jump. */
9869 /* We added two extra opcode bytes, and have a two byte
9871 fragP->fr_fix += 2 + 2;
9872 fix_new (fragP, old_fr_fix + 2, 2,
9874 fragP->fr_offset, 1,
9881 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9886 fixP = fix_new (fragP, old_fr_fix, 1,
9888 fragP->fr_offset, 1,
9890 fixP->fx_signed = 1;
9894 /* This changes the byte-displacement jump 0x7N
9895 to the (d)word-displacement jump 0x0f,0x8N. */
9896 opcode[1] = opcode[0] + 0x10;
9897 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9898 /* We've added an opcode byte. */
9899 fragP->fr_fix += 1 + size;
9900 fix_new (fragP, old_fr_fix + 1, size,
9902 fragP->fr_offset, 1,
9907 BAD_CASE (fragP->fr_subtype);
9911 return fragP->fr_fix - old_fr_fix;
9914 /* Guess size depending on current relax state. Initially the relax
9915 state will correspond to a short jump and we return 1, because
9916 the variable part of the frag (the branch offset) is one byte
9917 long. However, we can relax a section more than once and in that
9918 case we must either set fr_subtype back to the unrelaxed state,
9919 or return the value for the appropriate branch. */
9920 return md_relax_table[fragP->fr_subtype].rlx_length;
9923 /* Called after relax() is finished.
9925 In: Address of frag.
9926 fr_type == rs_machine_dependent.
9927 fr_subtype is what the address relaxed to.
9929 Out: Any fixSs and constants are set up.
9930 Caller will turn frag into a ".space 0". */
9933 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9936 unsigned char *opcode;
9937 unsigned char *where_to_put_displacement = NULL;
9938 offsetT target_address;
9939 offsetT opcode_address;
9940 unsigned int extension = 0;
9941 offsetT displacement_from_opcode_start;
9943 opcode = (unsigned char *) fragP->fr_opcode;
9945 /* Address we want to reach in file space. */
9946 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9948 /* Address opcode resides at in file space. */
9949 opcode_address = fragP->fr_address + fragP->fr_fix;
9951 /* Displacement from opcode start to fill into instruction. */
9952 displacement_from_opcode_start = target_address - opcode_address;
9954 if ((fragP->fr_subtype & BIG) == 0)
9956 /* Don't have to change opcode. */
9957 extension = 1; /* 1 opcode + 1 displacement */
9958 where_to_put_displacement = &opcode[1];
9962 if (no_cond_jump_promotion
9963 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9964 as_warn_where (fragP->fr_file, fragP->fr_line,
9965 _("long jump required"));
9967 switch (fragP->fr_subtype)
9969 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9970 extension = 4; /* 1 opcode + 4 displacement */
9972 where_to_put_displacement = &opcode[1];
9975 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9976 extension = 2; /* 1 opcode + 2 displacement */
9978 where_to_put_displacement = &opcode[1];
9981 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9982 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9983 extension = 5; /* 2 opcode + 4 displacement */
9984 opcode[1] = opcode[0] + 0x10;
9985 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9986 where_to_put_displacement = &opcode[2];
9989 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9990 extension = 3; /* 2 opcode + 2 displacement */
9991 opcode[1] = opcode[0] + 0x10;
9992 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9993 where_to_put_displacement = &opcode[2];
9996 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10001 where_to_put_displacement = &opcode[3];
10005 BAD_CASE (fragP->fr_subtype);
10010 /* If size if less then four we are sure that the operand fits,
10011 but if it's 4, then it could be that the displacement is larger
10013 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10015 && ((addressT) (displacement_from_opcode_start - extension
10016 + ((addressT) 1 << 31))
10017 > (((addressT) 2 << 31) - 1)))
10019 as_bad_where (fragP->fr_file, fragP->fr_line,
10020 _("jump target out of range"));
10021 /* Make us emit 0. */
10022 displacement_from_opcode_start = extension;
10024 /* Now put displacement after opcode. */
10025 md_number_to_chars ((char *) where_to_put_displacement,
10026 (valueT) (displacement_from_opcode_start - extension),
10027 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10028 fragP->fr_fix += extension;
10031 /* Apply a fixup (fixP) to segment data, once it has been determined
10032 by our caller that we have all the info we need to fix it up.
10034 Parameter valP is the pointer to the value of the bits.
10036 On the 386, immediates, displacements, and data pointers are all in
10037 the same (little-endian) format, so we don't need to care about which
10038 we are handling. */
10041 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10043 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10044 valueT value = *valP;
10046 #if !defined (TE_Mach)
10047 if (fixP->fx_pcrel)
10049 switch (fixP->fx_r_type)
10055 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10058 case BFD_RELOC_X86_64_32S:
10059 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10062 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10065 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10070 if (fixP->fx_addsy != NULL
10071 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10072 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10073 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10074 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10075 && !use_rela_relocations)
10077 /* This is a hack. There should be a better way to handle this.
10078 This covers for the fact that bfd_install_relocation will
10079 subtract the current location (for partial_inplace, PC relative
10080 relocations); see more below. */
10084 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10087 value += fixP->fx_where + fixP->fx_frag->fr_address;
10089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10092 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10094 if ((sym_seg == seg
10095 || (symbol_section_p (fixP->fx_addsy)
10096 && sym_seg != absolute_section))
10097 && !generic_force_reloc (fixP))
10099 /* Yes, we add the values in twice. This is because
10100 bfd_install_relocation subtracts them out again. I think
10101 bfd_install_relocation is broken, but I don't dare change
10103 value += fixP->fx_where + fixP->fx_frag->fr_address;
10107 #if defined (OBJ_COFF) && defined (TE_PE)
10108 /* For some reason, the PE format does not store a
10109 section address offset for a PC relative symbol. */
10110 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10111 || S_IS_WEAK (fixP->fx_addsy))
10112 value += md_pcrel_from (fixP);
10115 #if defined (OBJ_COFF) && defined (TE_PE)
10116 if (fixP->fx_addsy != NULL
10117 && S_IS_WEAK (fixP->fx_addsy)
10118 /* PR 16858: Do not modify weak function references. */
10119 && ! fixP->fx_pcrel)
10121 #if !defined (TE_PEP)
10122 /* For x86 PE weak function symbols are neither PC-relative
10123 nor do they set S_IS_FUNCTION. So the only reliable way
10124 to detect them is to check the flags of their containing
10126 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10127 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10131 value -= S_GET_VALUE (fixP->fx_addsy);
10135 /* Fix a few things - the dynamic linker expects certain values here,
10136 and we must not disappoint it. */
10137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10138 if (IS_ELF && fixP->fx_addsy)
10139 switch (fixP->fx_r_type)
10141 case BFD_RELOC_386_PLT32:
10142 case BFD_RELOC_X86_64_PLT32:
10143 /* Make the jump instruction point to the address of the operand. At
10144 runtime we merely add the offset to the actual PLT entry. */
10148 case BFD_RELOC_386_TLS_GD:
10149 case BFD_RELOC_386_TLS_LDM:
10150 case BFD_RELOC_386_TLS_IE_32:
10151 case BFD_RELOC_386_TLS_IE:
10152 case BFD_RELOC_386_TLS_GOTIE:
10153 case BFD_RELOC_386_TLS_GOTDESC:
10154 case BFD_RELOC_X86_64_TLSGD:
10155 case BFD_RELOC_X86_64_TLSLD:
10156 case BFD_RELOC_X86_64_GOTTPOFF:
10157 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10158 value = 0; /* Fully resolved at runtime. No addend. */
10160 case BFD_RELOC_386_TLS_LE:
10161 case BFD_RELOC_386_TLS_LDO_32:
10162 case BFD_RELOC_386_TLS_LE_32:
10163 case BFD_RELOC_X86_64_DTPOFF32:
10164 case BFD_RELOC_X86_64_DTPOFF64:
10165 case BFD_RELOC_X86_64_TPOFF32:
10166 case BFD_RELOC_X86_64_TPOFF64:
10167 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10170 case BFD_RELOC_386_TLS_DESC_CALL:
10171 case BFD_RELOC_X86_64_TLSDESC_CALL:
10172 value = 0; /* Fully resolved at runtime. No addend. */
10173 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10177 case BFD_RELOC_VTABLE_INHERIT:
10178 case BFD_RELOC_VTABLE_ENTRY:
10185 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10187 #endif /* !defined (TE_Mach) */
10189 /* Are we finished with this relocation now? */
10190 if (fixP->fx_addsy == NULL)
10192 #if defined (OBJ_COFF) && defined (TE_PE)
10193 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10196 /* Remember value for tc_gen_reloc. */
10197 fixP->fx_addnumber = value;
10198 /* Clear out the frag for now. */
10202 else if (use_rela_relocations)
10204 fixP->fx_no_overflow = 1;
10205 /* Remember value for tc_gen_reloc. */
10206 fixP->fx_addnumber = value;
10210 md_number_to_chars (p, value, fixP->fx_size);
10214 md_atof (int type, char *litP, int *sizeP)
10216 /* This outputs the LITTLENUMs in REVERSE order;
10217 in accord with the bigendian 386. */
10218 return ieee_md_atof (type, litP, sizeP, FALSE);
10221 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10224 output_invalid (int c)
10227 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10230 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10231 "(0x%x)", (unsigned char) c);
10232 return output_invalid_buf;
10235 /* REG_STRING starts *before* REGISTER_PREFIX. */
10237 static const reg_entry *
10238 parse_real_register (char *reg_string, char **end_op)
10240 char *s = reg_string;
10242 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10243 const reg_entry *r;
10245 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10246 if (*s == REGISTER_PREFIX)
10249 if (is_space_char (*s))
10252 p = reg_name_given;
10253 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10255 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10256 return (const reg_entry *) NULL;
10260 /* For naked regs, make sure that we are not dealing with an identifier.
10261 This prevents confusing an identifier like `eax_var' with register
10263 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10264 return (const reg_entry *) NULL;
10268 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10270 /* Handle floating point regs, allowing spaces in the (i) part. */
10271 if (r == i386_regtab /* %st is first entry of table */)
10273 if (!cpu_arch_flags.bitfield.cpu8087
10274 && !cpu_arch_flags.bitfield.cpu287
10275 && !cpu_arch_flags.bitfield.cpu387)
10276 return (const reg_entry *) NULL;
10278 if (is_space_char (*s))
10283 if (is_space_char (*s))
10285 if (*s >= '0' && *s <= '7')
10287 int fpr = *s - '0';
10289 if (is_space_char (*s))
10294 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10299 /* We have "%st(" then garbage. */
10300 return (const reg_entry *) NULL;
10304 if (r == NULL || allow_pseudo_reg)
10307 if (operand_type_all_zero (&r->reg_type))
10308 return (const reg_entry *) NULL;
10310 if ((r->reg_type.bitfield.dword
10311 || r->reg_type.bitfield.sreg3
10312 || r->reg_type.bitfield.control
10313 || r->reg_type.bitfield.debug
10314 || r->reg_type.bitfield.test)
10315 && !cpu_arch_flags.bitfield.cpui386)
10316 return (const reg_entry *) NULL;
10318 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10319 return (const reg_entry *) NULL;
10321 if (!cpu_arch_flags.bitfield.cpuavx512f)
10323 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10324 return (const reg_entry *) NULL;
10326 if (!cpu_arch_flags.bitfield.cpuavx)
10328 if (r->reg_type.bitfield.ymmword)
10329 return (const reg_entry *) NULL;
10331 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10332 return (const reg_entry *) NULL;
10336 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10337 return (const reg_entry *) NULL;
10339 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10340 if (!allow_index_reg
10341 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10342 return (const reg_entry *) NULL;
10344 /* Upper 16 vector registers are only available with VREX in 64bit
10345 mode, and require EVEX encoding. */
10346 if (r->reg_flags & RegVRex)
10348 if (!cpu_arch_flags.bitfield.cpuvrex
10349 || flag_code != CODE_64BIT)
10350 return (const reg_entry *) NULL;
10352 i.vec_encoding = vex_encoding_evex;
10355 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10356 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10357 && flag_code != CODE_64BIT)
10358 return (const reg_entry *) NULL;
10360 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10361 return (const reg_entry *) NULL;
10366 /* REG_STRING starts *before* REGISTER_PREFIX. */
10368 static const reg_entry *
10369 parse_register (char *reg_string, char **end_op)
10371 const reg_entry *r;
10373 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10374 r = parse_real_register (reg_string, end_op);
10379 char *save = input_line_pointer;
10383 input_line_pointer = reg_string;
10384 c = get_symbol_name (®_string);
10385 symbolP = symbol_find (reg_string);
10386 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10388 const expressionS *e = symbol_get_value_expression (symbolP);
10390 know (e->X_op == O_register);
10391 know (e->X_add_number >= 0
10392 && (valueT) e->X_add_number < i386_regtab_size);
10393 r = i386_regtab + e->X_add_number;
10394 if ((r->reg_flags & RegVRex))
10395 i.vec_encoding = vex_encoding_evex;
10396 *end_op = input_line_pointer;
10398 *input_line_pointer = c;
10399 input_line_pointer = save;
10405 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10407 const reg_entry *r;
10408 char *end = input_line_pointer;
10411 r = parse_register (name, &input_line_pointer);
10412 if (r && end <= input_line_pointer)
10414 *nextcharP = *input_line_pointer;
10415 *input_line_pointer = 0;
10416 e->X_op = O_register;
10417 e->X_add_number = r - i386_regtab;
10420 input_line_pointer = end;
10422 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10426 md_operand (expressionS *e)
10429 const reg_entry *r;
10431 switch (*input_line_pointer)
10433 case REGISTER_PREFIX:
10434 r = parse_real_register (input_line_pointer, &end);
10437 e->X_op = O_register;
10438 e->X_add_number = r - i386_regtab;
10439 input_line_pointer = end;
10444 gas_assert (intel_syntax);
10445 end = input_line_pointer++;
10447 if (*input_line_pointer == ']')
10449 ++input_line_pointer;
10450 e->X_op_symbol = make_expr_symbol (e);
10451 e->X_add_symbol = NULL;
10452 e->X_add_number = 0;
10457 e->X_op = O_absent;
10458 input_line_pointer = end;
10465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10466 const char *md_shortopts = "kVQ:sqnO::";
10468 const char *md_shortopts = "qnO::";
10471 #define OPTION_32 (OPTION_MD_BASE + 0)
10472 #define OPTION_64 (OPTION_MD_BASE + 1)
10473 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10474 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10475 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10476 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10477 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10478 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10479 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10480 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10481 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10482 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10483 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10484 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10485 #define OPTION_X32 (OPTION_MD_BASE + 14)
10486 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10487 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10488 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10489 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10490 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10491 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10492 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10493 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10494 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10495 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10497 struct option md_longopts[] =
10499 {"32", no_argument, NULL, OPTION_32},
10500 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10501 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10502 {"64", no_argument, NULL, OPTION_64},
10504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10505 {"x32", no_argument, NULL, OPTION_X32},
10506 {"mshared", no_argument, NULL, OPTION_MSHARED},
10508 {"divide", no_argument, NULL, OPTION_DIVIDE},
10509 {"march", required_argument, NULL, OPTION_MARCH},
10510 {"mtune", required_argument, NULL, OPTION_MTUNE},
10511 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10512 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10513 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10514 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10515 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10516 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10517 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10518 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10519 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10520 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10521 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10522 # if defined (TE_PE) || defined (TE_PEP)
10523 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10525 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10526 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10527 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10528 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10529 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10530 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10531 {NULL, no_argument, NULL, 0}
10533 size_t md_longopts_size = sizeof (md_longopts);
10536 md_parse_option (int c, const char *arg)
10539 char *arch, *next, *saved;
10544 optimize_align_code = 0;
10548 quiet_warnings = 1;
10551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10552 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10553 should be emitted or not. FIXME: Not implemented. */
10557 /* -V: SVR4 argument to print version ID. */
10559 print_version_id ();
10562 /* -k: Ignore for FreeBSD compatibility. */
10567 /* -s: On i386 Solaris, this tells the native assembler to use
10568 .stab instead of .stab.excl. We always use .stab anyhow. */
10571 case OPTION_MSHARED:
10575 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10576 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10579 const char **list, **l;
10581 list = bfd_target_list ();
10582 for (l = list; *l != NULL; l++)
10583 if (CONST_STRNEQ (*l, "elf64-x86-64")
10584 || strcmp (*l, "coff-x86-64") == 0
10585 || strcmp (*l, "pe-x86-64") == 0
10586 || strcmp (*l, "pei-x86-64") == 0
10587 || strcmp (*l, "mach-o-x86-64") == 0)
10589 default_arch = "x86_64";
10593 as_fatal (_("no compiled in support for x86_64"));
10599 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10603 const char **list, **l;
10605 list = bfd_target_list ();
10606 for (l = list; *l != NULL; l++)
10607 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10609 default_arch = "x86_64:32";
10613 as_fatal (_("no compiled in support for 32bit x86_64"));
10617 as_fatal (_("32bit x86_64 is only supported for ELF"));
10622 default_arch = "i386";
10625 case OPTION_DIVIDE:
10626 #ifdef SVR4_COMMENT_CHARS
10631 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10633 for (s = i386_comment_chars; *s != '\0'; s++)
10637 i386_comment_chars = n;
10643 saved = xstrdup (arg);
10645 /* Allow -march=+nosse. */
10651 as_fatal (_("invalid -march= option: `%s'"), arg);
10652 next = strchr (arch, '+');
10655 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10657 if (strcmp (arch, cpu_arch [j].name) == 0)
10660 if (! cpu_arch[j].flags.bitfield.cpui386)
10663 cpu_arch_name = cpu_arch[j].name;
10664 cpu_sub_arch_name = NULL;
10665 cpu_arch_flags = cpu_arch[j].flags;
10666 cpu_arch_isa = cpu_arch[j].type;
10667 cpu_arch_isa_flags = cpu_arch[j].flags;
10668 if (!cpu_arch_tune_set)
10670 cpu_arch_tune = cpu_arch_isa;
10671 cpu_arch_tune_flags = cpu_arch_isa_flags;
10675 else if (*cpu_arch [j].name == '.'
10676 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10678 /* ISA extension. */
10679 i386_cpu_flags flags;
10681 flags = cpu_flags_or (cpu_arch_flags,
10682 cpu_arch[j].flags);
10684 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10686 if (cpu_sub_arch_name)
10688 char *name = cpu_sub_arch_name;
10689 cpu_sub_arch_name = concat (name,
10691 (const char *) NULL);
10695 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10696 cpu_arch_flags = flags;
10697 cpu_arch_isa_flags = flags;
10701 = cpu_flags_or (cpu_arch_isa_flags,
10702 cpu_arch[j].flags);
10707 if (j >= ARRAY_SIZE (cpu_arch))
10709 /* Disable an ISA extension. */
10710 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10711 if (strcmp (arch, cpu_noarch [j].name) == 0)
10713 i386_cpu_flags flags;
10715 flags = cpu_flags_and_not (cpu_arch_flags,
10716 cpu_noarch[j].flags);
10717 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10719 if (cpu_sub_arch_name)
10721 char *name = cpu_sub_arch_name;
10722 cpu_sub_arch_name = concat (arch,
10723 (const char *) NULL);
10727 cpu_sub_arch_name = xstrdup (arch);
10728 cpu_arch_flags = flags;
10729 cpu_arch_isa_flags = flags;
10734 if (j >= ARRAY_SIZE (cpu_noarch))
10735 j = ARRAY_SIZE (cpu_arch);
10738 if (j >= ARRAY_SIZE (cpu_arch))
10739 as_fatal (_("invalid -march= option: `%s'"), arg);
10743 while (next != NULL);
10749 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10750 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10752 if (strcmp (arg, cpu_arch [j].name) == 0)
10754 cpu_arch_tune_set = 1;
10755 cpu_arch_tune = cpu_arch [j].type;
10756 cpu_arch_tune_flags = cpu_arch[j].flags;
10760 if (j >= ARRAY_SIZE (cpu_arch))
10761 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10764 case OPTION_MMNEMONIC:
10765 if (strcasecmp (arg, "att") == 0)
10766 intel_mnemonic = 0;
10767 else if (strcasecmp (arg, "intel") == 0)
10768 intel_mnemonic = 1;
10770 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10773 case OPTION_MSYNTAX:
10774 if (strcasecmp (arg, "att") == 0)
10776 else if (strcasecmp (arg, "intel") == 0)
10779 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10782 case OPTION_MINDEX_REG:
10783 allow_index_reg = 1;
10786 case OPTION_MNAKED_REG:
10787 allow_naked_reg = 1;
10790 case OPTION_MSSE2AVX:
10794 case OPTION_MSSE_CHECK:
10795 if (strcasecmp (arg, "error") == 0)
10796 sse_check = check_error;
10797 else if (strcasecmp (arg, "warning") == 0)
10798 sse_check = check_warning;
10799 else if (strcasecmp (arg, "none") == 0)
10800 sse_check = check_none;
10802 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10805 case OPTION_MOPERAND_CHECK:
10806 if (strcasecmp (arg, "error") == 0)
10807 operand_check = check_error;
10808 else if (strcasecmp (arg, "warning") == 0)
10809 operand_check = check_warning;
10810 else if (strcasecmp (arg, "none") == 0)
10811 operand_check = check_none;
10813 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10816 case OPTION_MAVXSCALAR:
10817 if (strcasecmp (arg, "128") == 0)
10818 avxscalar = vex128;
10819 else if (strcasecmp (arg, "256") == 0)
10820 avxscalar = vex256;
10822 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10825 case OPTION_MADD_BND_PREFIX:
10826 add_bnd_prefix = 1;
10829 case OPTION_MEVEXLIG:
10830 if (strcmp (arg, "128") == 0)
10831 evexlig = evexl128;
10832 else if (strcmp (arg, "256") == 0)
10833 evexlig = evexl256;
10834 else if (strcmp (arg, "512") == 0)
10835 evexlig = evexl512;
10837 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10840 case OPTION_MEVEXRCIG:
10841 if (strcmp (arg, "rne") == 0)
10843 else if (strcmp (arg, "rd") == 0)
10845 else if (strcmp (arg, "ru") == 0)
10847 else if (strcmp (arg, "rz") == 0)
10850 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10853 case OPTION_MEVEXWIG:
10854 if (strcmp (arg, "0") == 0)
10856 else if (strcmp (arg, "1") == 0)
10859 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10862 # if defined (TE_PE) || defined (TE_PEP)
10863 case OPTION_MBIG_OBJ:
10868 case OPTION_MOMIT_LOCK_PREFIX:
10869 if (strcasecmp (arg, "yes") == 0)
10870 omit_lock_prefix = 1;
10871 else if (strcasecmp (arg, "no") == 0)
10872 omit_lock_prefix = 0;
10874 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10877 case OPTION_MFENCE_AS_LOCK_ADD:
10878 if (strcasecmp (arg, "yes") == 0)
10880 else if (strcasecmp (arg, "no") == 0)
10883 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10886 case OPTION_MRELAX_RELOCATIONS:
10887 if (strcasecmp (arg, "yes") == 0)
10888 generate_relax_relocations = 1;
10889 else if (strcasecmp (arg, "no") == 0)
10890 generate_relax_relocations = 0;
10892 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10895 case OPTION_MAMD64:
10899 case OPTION_MINTEL64:
10907 /* Turn off -Os. */
10908 optimize_for_space = 0;
10910 else if (*arg == 's')
10912 optimize_for_space = 1;
10913 /* Turn on all encoding optimizations. */
10918 optimize = atoi (arg);
10919 /* Turn off -Os. */
10920 optimize_for_space = 0;
10930 #define MESSAGE_TEMPLATE \
10934 output_message (FILE *stream, char *p, char *message, char *start,
10935 int *left_p, const char *name, int len)
10937 int size = sizeof (MESSAGE_TEMPLATE);
10938 int left = *left_p;
10940 /* Reserve 2 spaces for ", " or ",\0" */
10943 /* Check if there is any room. */
10951 p = mempcpy (p, name, len);
10955 /* Output the current message now and start a new one. */
10958 fprintf (stream, "%s\n", message);
10960 left = size - (start - message) - len - 2;
10962 gas_assert (left >= 0);
10964 p = mempcpy (p, name, len);
10972 show_arch (FILE *stream, int ext, int check)
10974 static char message[] = MESSAGE_TEMPLATE;
10975 char *start = message + 27;
10977 int size = sizeof (MESSAGE_TEMPLATE);
10984 left = size - (start - message);
10985 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10987 /* Should it be skipped? */
10988 if (cpu_arch [j].skip)
10991 name = cpu_arch [j].name;
10992 len = cpu_arch [j].len;
10995 /* It is an extension. Skip if we aren't asked to show it. */
11006 /* It is an processor. Skip if we show only extension. */
11009 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11011 /* It is an impossible processor - skip. */
11015 p = output_message (stream, p, message, start, &left, name, len);
11018 /* Display disabled extensions. */
11020 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11022 name = cpu_noarch [j].name;
11023 len = cpu_noarch [j].len;
11024 p = output_message (stream, p, message, start, &left, name,
11029 fprintf (stream, "%s\n", message);
11033 md_show_usage (FILE *stream)
11035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11036 fprintf (stream, _("\
11038 -V print assembler version number\n\
11041 fprintf (stream, _("\
11042 -n Do not optimize code alignment\n\
11043 -q quieten some warnings\n"));
11044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11045 fprintf (stream, _("\
11048 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11049 || defined (TE_PE) || defined (TE_PEP))
11050 fprintf (stream, _("\
11051 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11053 #ifdef SVR4_COMMENT_CHARS
11054 fprintf (stream, _("\
11055 --divide do not treat `/' as a comment character\n"));
11057 fprintf (stream, _("\
11058 --divide ignored\n"));
11060 fprintf (stream, _("\
11061 -march=CPU[,+EXTENSION...]\n\
11062 generate code for CPU and EXTENSION, CPU is one of:\n"));
11063 show_arch (stream, 0, 1);
11064 fprintf (stream, _("\
11065 EXTENSION is combination of:\n"));
11066 show_arch (stream, 1, 0);
11067 fprintf (stream, _("\
11068 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11069 show_arch (stream, 0, 0);
11070 fprintf (stream, _("\
11071 -msse2avx encode SSE instructions with VEX prefix\n"));
11072 fprintf (stream, _("\
11073 -msse-check=[none|error|warning]\n\
11074 check SSE instructions\n"));
11075 fprintf (stream, _("\
11076 -moperand-check=[none|error|warning]\n\
11077 check operand combinations for validity\n"));
11078 fprintf (stream, _("\
11079 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11081 fprintf (stream, _("\
11082 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11084 fprintf (stream, _("\
11085 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11086 for EVEX.W bit ignored instructions\n"));
11087 fprintf (stream, _("\
11088 -mevexrcig=[rne|rd|ru|rz]\n\
11089 encode EVEX instructions with specific EVEX.RC value\n\
11090 for SAE-only ignored instructions\n"));
11091 fprintf (stream, _("\
11092 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11093 fprintf (stream, _("\
11094 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11095 fprintf (stream, _("\
11096 -mindex-reg support pseudo index registers\n"));
11097 fprintf (stream, _("\
11098 -mnaked-reg don't require `%%' prefix for registers\n"));
11099 fprintf (stream, _("\
11100 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11101 fprintf (stream, _("\
11102 -mshared disable branch optimization for shared code\n"));
11103 # if defined (TE_PE) || defined (TE_PEP)
11104 fprintf (stream, _("\
11105 -mbig-obj generate big object files\n"));
11107 fprintf (stream, _("\
11108 -momit-lock-prefix=[no|yes]\n\
11109 strip all lock prefixes\n"));
11110 fprintf (stream, _("\
11111 -mfence-as-lock-add=[no|yes]\n\
11112 encode lfence, mfence and sfence as\n\
11113 lock addl $0x0, (%%{re}sp)\n"));
11114 fprintf (stream, _("\
11115 -mrelax-relocations=[no|yes]\n\
11116 generate relax relocations\n"));
11117 fprintf (stream, _("\
11118 -mamd64 accept only AMD64 ISA\n"));
11119 fprintf (stream, _("\
11120 -mintel64 accept only Intel64 ISA\n"));
11123 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11124 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11125 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11127 /* Pick the target format to use. */
11130 i386_target_format (void)
11132 if (!strncmp (default_arch, "x86_64", 6))
11134 update_code_flag (CODE_64BIT, 1);
11135 if (default_arch[6] == '\0')
11136 x86_elf_abi = X86_64_ABI;
11138 x86_elf_abi = X86_64_X32_ABI;
11140 else if (!strcmp (default_arch, "i386"))
11141 update_code_flag (CODE_32BIT, 1);
11142 else if (!strcmp (default_arch, "iamcu"))
11144 update_code_flag (CODE_32BIT, 1);
11145 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11147 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11148 cpu_arch_name = "iamcu";
11149 cpu_sub_arch_name = NULL;
11150 cpu_arch_flags = iamcu_flags;
11151 cpu_arch_isa = PROCESSOR_IAMCU;
11152 cpu_arch_isa_flags = iamcu_flags;
11153 if (!cpu_arch_tune_set)
11155 cpu_arch_tune = cpu_arch_isa;
11156 cpu_arch_tune_flags = cpu_arch_isa_flags;
11159 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11160 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11164 as_fatal (_("unknown architecture"));
11166 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11167 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11168 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11169 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11171 switch (OUTPUT_FLAVOR)
11173 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11174 case bfd_target_aout_flavour:
11175 return AOUT_TARGET_FORMAT;
11177 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11178 # if defined (TE_PE) || defined (TE_PEP)
11179 case bfd_target_coff_flavour:
11180 if (flag_code == CODE_64BIT)
11181 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11184 # elif defined (TE_GO32)
11185 case bfd_target_coff_flavour:
11186 return "coff-go32";
11188 case bfd_target_coff_flavour:
11189 return "coff-i386";
11192 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11193 case bfd_target_elf_flavour:
11195 const char *format;
11197 switch (x86_elf_abi)
11200 format = ELF_TARGET_FORMAT;
11203 use_rela_relocations = 1;
11205 format = ELF_TARGET_FORMAT64;
11207 case X86_64_X32_ABI:
11208 use_rela_relocations = 1;
11210 disallow_64bit_reloc = 1;
11211 format = ELF_TARGET_FORMAT32;
11214 if (cpu_arch_isa == PROCESSOR_L1OM)
11216 if (x86_elf_abi != X86_64_ABI)
11217 as_fatal (_("Intel L1OM is 64bit only"));
11218 return ELF_TARGET_L1OM_FORMAT;
11220 else if (cpu_arch_isa == PROCESSOR_K1OM)
11222 if (x86_elf_abi != X86_64_ABI)
11223 as_fatal (_("Intel K1OM is 64bit only"));
11224 return ELF_TARGET_K1OM_FORMAT;
11226 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11228 if (x86_elf_abi != I386_ABI)
11229 as_fatal (_("Intel MCU is 32bit only"));
11230 return ELF_TARGET_IAMCU_FORMAT;
11236 #if defined (OBJ_MACH_O)
11237 case bfd_target_mach_o_flavour:
11238 if (flag_code == CODE_64BIT)
11240 use_rela_relocations = 1;
11242 return "mach-o-x86-64";
11245 return "mach-o-i386";
11253 #endif /* OBJ_MAYBE_ more than one */
11256 md_undefined_symbol (char *name)
11258 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11259 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11260 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11261 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11265 if (symbol_find (name))
11266 as_bad (_("GOT already in symbol table"));
11267 GOT_symbol = symbol_new (name, undefined_section,
11268 (valueT) 0, &zero_address_frag);
11275 /* Round up a section size to the appropriate boundary. */
11278 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11280 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11281 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11283 /* For a.out, force the section size to be aligned. If we don't do
11284 this, BFD will align it for us, but it will not write out the
11285 final bytes of the section. This may be a bug in BFD, but it is
11286 easier to fix it here since that is how the other a.out targets
11290 align = bfd_get_section_alignment (stdoutput, segment);
11291 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11298 /* On the i386, PC-relative offsets are relative to the start of the
11299 next instruction. That is, the address of the offset, plus its
11300 size, since the offset is always the last part of the insn. */
11303 md_pcrel_from (fixS *fixP)
11305 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11311 s_bss (int ignore ATTRIBUTE_UNUSED)
11315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11317 obj_elf_section_change_hook ();
11319 temp = get_absolute_expression ();
11320 subseg_set (bss_section, (subsegT) temp);
11321 demand_empty_rest_of_line ();
11327 i386_validate_fix (fixS *fixp)
11329 if (fixp->fx_subsy)
11331 if (fixp->fx_subsy == GOT_symbol)
11333 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11338 if (fixp->fx_tcbit2)
11339 fixp->fx_r_type = (fixp->fx_tcbit
11340 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11341 : BFD_RELOC_X86_64_GOTPCRELX);
11344 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11349 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11351 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11353 fixp->fx_subsy = 0;
11356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11357 else if (!object_64bit)
11359 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11360 && fixp->fx_tcbit2)
11361 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11367 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11370 bfd_reloc_code_real_type code;
11372 switch (fixp->fx_r_type)
11374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11375 case BFD_RELOC_SIZE32:
11376 case BFD_RELOC_SIZE64:
11377 if (S_IS_DEFINED (fixp->fx_addsy)
11378 && !S_IS_EXTERNAL (fixp->fx_addsy))
11380 /* Resolve size relocation against local symbol to size of
11381 the symbol plus addend. */
11382 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11383 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11384 && !fits_in_unsigned_long (value))
11385 as_bad_where (fixp->fx_file, fixp->fx_line,
11386 _("symbol size computation overflow"));
11387 fixp->fx_addsy = NULL;
11388 fixp->fx_subsy = NULL;
11389 md_apply_fix (fixp, (valueT *) &value, NULL);
11393 /* Fall through. */
11395 case BFD_RELOC_X86_64_PLT32:
11396 case BFD_RELOC_X86_64_GOT32:
11397 case BFD_RELOC_X86_64_GOTPCREL:
11398 case BFD_RELOC_X86_64_GOTPCRELX:
11399 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11400 case BFD_RELOC_386_PLT32:
11401 case BFD_RELOC_386_GOT32:
11402 case BFD_RELOC_386_GOT32X:
11403 case BFD_RELOC_386_GOTOFF:
11404 case BFD_RELOC_386_GOTPC:
11405 case BFD_RELOC_386_TLS_GD:
11406 case BFD_RELOC_386_TLS_LDM:
11407 case BFD_RELOC_386_TLS_LDO_32:
11408 case BFD_RELOC_386_TLS_IE_32:
11409 case BFD_RELOC_386_TLS_IE:
11410 case BFD_RELOC_386_TLS_GOTIE:
11411 case BFD_RELOC_386_TLS_LE_32:
11412 case BFD_RELOC_386_TLS_LE:
11413 case BFD_RELOC_386_TLS_GOTDESC:
11414 case BFD_RELOC_386_TLS_DESC_CALL:
11415 case BFD_RELOC_X86_64_TLSGD:
11416 case BFD_RELOC_X86_64_TLSLD:
11417 case BFD_RELOC_X86_64_DTPOFF32:
11418 case BFD_RELOC_X86_64_DTPOFF64:
11419 case BFD_RELOC_X86_64_GOTTPOFF:
11420 case BFD_RELOC_X86_64_TPOFF32:
11421 case BFD_RELOC_X86_64_TPOFF64:
11422 case BFD_RELOC_X86_64_GOTOFF64:
11423 case BFD_RELOC_X86_64_GOTPC32:
11424 case BFD_RELOC_X86_64_GOT64:
11425 case BFD_RELOC_X86_64_GOTPCREL64:
11426 case BFD_RELOC_X86_64_GOTPC64:
11427 case BFD_RELOC_X86_64_GOTPLT64:
11428 case BFD_RELOC_X86_64_PLTOFF64:
11429 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11430 case BFD_RELOC_X86_64_TLSDESC_CALL:
11431 case BFD_RELOC_RVA:
11432 case BFD_RELOC_VTABLE_ENTRY:
11433 case BFD_RELOC_VTABLE_INHERIT:
11435 case BFD_RELOC_32_SECREL:
11437 code = fixp->fx_r_type;
11439 case BFD_RELOC_X86_64_32S:
11440 if (!fixp->fx_pcrel)
11442 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11443 code = fixp->fx_r_type;
11446 /* Fall through. */
11448 if (fixp->fx_pcrel)
11450 switch (fixp->fx_size)
11453 as_bad_where (fixp->fx_file, fixp->fx_line,
11454 _("can not do %d byte pc-relative relocation"),
11456 code = BFD_RELOC_32_PCREL;
11458 case 1: code = BFD_RELOC_8_PCREL; break;
11459 case 2: code = BFD_RELOC_16_PCREL; break;
11460 case 4: code = BFD_RELOC_32_PCREL; break;
11462 case 8: code = BFD_RELOC_64_PCREL; break;
11468 switch (fixp->fx_size)
11471 as_bad_where (fixp->fx_file, fixp->fx_line,
11472 _("can not do %d byte relocation"),
11474 code = BFD_RELOC_32;
11476 case 1: code = BFD_RELOC_8; break;
11477 case 2: code = BFD_RELOC_16; break;
11478 case 4: code = BFD_RELOC_32; break;
11480 case 8: code = BFD_RELOC_64; break;
11487 if ((code == BFD_RELOC_32
11488 || code == BFD_RELOC_32_PCREL
11489 || code == BFD_RELOC_X86_64_32S)
11491 && fixp->fx_addsy == GOT_symbol)
11494 code = BFD_RELOC_386_GOTPC;
11496 code = BFD_RELOC_X86_64_GOTPC32;
11498 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11500 && fixp->fx_addsy == GOT_symbol)
11502 code = BFD_RELOC_X86_64_GOTPC64;
11505 rel = XNEW (arelent);
11506 rel->sym_ptr_ptr = XNEW (asymbol *);
11507 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11509 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11511 if (!use_rela_relocations)
11513 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11514 vtable entry to be used in the relocation's section offset. */
11515 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11516 rel->address = fixp->fx_offset;
11517 #if defined (OBJ_COFF) && defined (TE_PE)
11518 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11519 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11524 /* Use the rela in 64bit mode. */
11527 if (disallow_64bit_reloc)
11530 case BFD_RELOC_X86_64_DTPOFF64:
11531 case BFD_RELOC_X86_64_TPOFF64:
11532 case BFD_RELOC_64_PCREL:
11533 case BFD_RELOC_X86_64_GOTOFF64:
11534 case BFD_RELOC_X86_64_GOT64:
11535 case BFD_RELOC_X86_64_GOTPCREL64:
11536 case BFD_RELOC_X86_64_GOTPC64:
11537 case BFD_RELOC_X86_64_GOTPLT64:
11538 case BFD_RELOC_X86_64_PLTOFF64:
11539 as_bad_where (fixp->fx_file, fixp->fx_line,
11540 _("cannot represent relocation type %s in x32 mode"),
11541 bfd_get_reloc_code_name (code));
11547 if (!fixp->fx_pcrel)
11548 rel->addend = fixp->fx_offset;
11552 case BFD_RELOC_X86_64_PLT32:
11553 case BFD_RELOC_X86_64_GOT32:
11554 case BFD_RELOC_X86_64_GOTPCREL:
11555 case BFD_RELOC_X86_64_GOTPCRELX:
11556 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11557 case BFD_RELOC_X86_64_TLSGD:
11558 case BFD_RELOC_X86_64_TLSLD:
11559 case BFD_RELOC_X86_64_GOTTPOFF:
11560 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11561 case BFD_RELOC_X86_64_TLSDESC_CALL:
11562 rel->addend = fixp->fx_offset - fixp->fx_size;
11565 rel->addend = (section->vma
11567 + fixp->fx_addnumber
11568 + md_pcrel_from (fixp));
11573 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11574 if (rel->howto == NULL)
11576 as_bad_where (fixp->fx_file, fixp->fx_line,
11577 _("cannot represent relocation type %s"),
11578 bfd_get_reloc_code_name (code));
11579 /* Set howto to a garbage value so that we can keep going. */
11580 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11581 gas_assert (rel->howto != NULL);
11587 #include "tc-i386-intel.c"
11590 tc_x86_parse_to_dw2regnum (expressionS *exp)
11592 int saved_naked_reg;
11593 char saved_register_dot;
11595 saved_naked_reg = allow_naked_reg;
11596 allow_naked_reg = 1;
11597 saved_register_dot = register_chars['.'];
11598 register_chars['.'] = '.';
11599 allow_pseudo_reg = 1;
11600 expression_and_evaluate (exp);
11601 allow_pseudo_reg = 0;
11602 register_chars['.'] = saved_register_dot;
11603 allow_naked_reg = saved_naked_reg;
11605 if (exp->X_op == O_register && exp->X_add_number >= 0)
11607 if ((addressT) exp->X_add_number < i386_regtab_size)
11609 exp->X_op = O_constant;
11610 exp->X_add_number = i386_regtab[exp->X_add_number]
11611 .dw2_regnum[flag_code >> 1];
11614 exp->X_op = O_illegal;
11619 tc_x86_frame_initial_instructions (void)
11621 static unsigned int sp_regno[2];
11623 if (!sp_regno[flag_code >> 1])
11625 char *saved_input = input_line_pointer;
11626 char sp[][4] = {"esp", "rsp"};
11629 input_line_pointer = sp[flag_code >> 1];
11630 tc_x86_parse_to_dw2regnum (&exp);
11631 gas_assert (exp.X_op == O_constant);
11632 sp_regno[flag_code >> 1] = exp.X_add_number;
11633 input_line_pointer = saved_input;
11636 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11637 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11641 x86_dwarf2_addr_size (void)
11643 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11644 if (x86_elf_abi == X86_64_X32_ABI)
11647 return bfd_arch_bits_per_address (stdoutput) / 8;
11651 i386_elf_section_type (const char *str, size_t len)
11653 if (flag_code == CODE_64BIT
11654 && len == sizeof ("unwind") - 1
11655 && strncmp (str, "unwind", 6) == 0)
11656 return SHT_X86_64_UNWIND;
11663 i386_solaris_fix_up_eh_frame (segT sec)
11665 if (flag_code == CODE_64BIT)
11666 elf_section_type (sec) = SHT_X86_64_UNWIND;
11672 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11676 exp.X_op = O_secrel;
11677 exp.X_add_symbol = symbol;
11678 exp.X_add_number = 0;
11679 emit_expr (&exp, size);
11683 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11684 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11687 x86_64_section_letter (int letter, const char **ptr_msg)
11689 if (flag_code == CODE_64BIT)
11692 return SHF_X86_64_LARGE;
11694 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11697 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11702 x86_64_section_word (char *str, size_t len)
11704 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11705 return SHF_X86_64_LARGE;
11711 handle_large_common (int small ATTRIBUTE_UNUSED)
11713 if (flag_code != CODE_64BIT)
11715 s_comm_internal (0, elf_common_parse);
11716 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11720 static segT lbss_section;
11721 asection *saved_com_section_ptr = elf_com_section_ptr;
11722 asection *saved_bss_section = bss_section;
11724 if (lbss_section == NULL)
11726 flagword applicable;
11727 segT seg = now_seg;
11728 subsegT subseg = now_subseg;
11730 /* The .lbss section is for local .largecomm symbols. */
11731 lbss_section = subseg_new (".lbss", 0);
11732 applicable = bfd_applicable_section_flags (stdoutput);
11733 bfd_set_section_flags (stdoutput, lbss_section,
11734 applicable & SEC_ALLOC);
11735 seg_info (lbss_section)->bss = 1;
11737 subseg_set (seg, subseg);
11740 elf_com_section_ptr = &_bfd_elf_large_com_section;
11741 bss_section = lbss_section;
11743 s_comm_internal (0, elf_common_parse);
11745 elf_com_section_ptr = saved_com_section_ptr;
11746 bss_section = saved_bss_section;
11749 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */