1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void swap_imm_operands PARAMS ((void));
93 static void optimize_imm PARAMS ((void));
94 static void optimize_disp PARAMS ((void));
95 static int match_template PARAMS ((void));
96 static int check_string PARAMS ((void));
97 static int process_suffix PARAMS ((void));
98 static int check_byte_reg PARAMS ((void));
99 static int check_long_reg PARAMS ((void));
100 static int check_qword_reg PARAMS ((void));
101 static int check_word_reg PARAMS ((void));
102 static int finalize_imm PARAMS ((void));
103 static int process_operands PARAMS ((void));
104 static const seg_entry *build_modrm_byte PARAMS ((void));
105 static void output_insn PARAMS ((void));
106 static void output_branch PARAMS ((void));
107 static void output_jump PARAMS ((void));
108 static void output_interseg_jump PARAMS ((void));
109 static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111 static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
114 static void s_bss PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED);
120 static const char *default_arch = DEFAULT_ARCH;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry *regs;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types[MAX_OPERANDS];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op[MAX_OPERANDS];
157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry *seg[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars = "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars = "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars[] = "#/";
229 const char line_separator_chars[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars[256];
242 static char register_chars[256];
243 static char operand_chars[256];
244 static char identifier_chars[256];
245 static char digit_chars[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack[32];
263 static char *save_stack_p;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates *current_templates;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions[2], im_expressions[2];
278 /* Current operand we are working on. */
279 static int this_operand;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code;
291 static unsigned int object_64bit;
292 static int use_rela_relocations = 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names[] =
302 /* 1 for intel syntax,
304 static int intel_syntax = 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg = 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size = '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code = 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings = 0;
321 static const char *cpu_arch_name = NULL;
322 static const char *cpu_sub_arch_name = NULL;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set = 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags = 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags = 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion = 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS *GOT_symbol;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch[] =
436 {"generic32", PROCESSOR_GENERIC32,
437 Cpu186|Cpu286|Cpu386},
438 {"generic64", PROCESSOR_GENERIC64,
439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
443 {"i186", PROCESSOR_UNKNOWN,
445 {"i286", PROCESSOR_UNKNOWN,
447 {"i386", PROCESSOR_GENERIC32,
448 Cpu186|Cpu286|Cpu386},
449 {"i486", PROCESSOR_I486,
450 Cpu186|Cpu286|Cpu386|Cpu486},
451 {"i586", PROCESSOR_PENTIUM,
452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
453 {"i686", PROCESSOR_PENTIUMPRO,
454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
455 {"pentium", PROCESSOR_PENTIUM,
456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
459 {"pentiumii", PROCESSOR_PENTIUMPRO,
460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
463 {"pentium4", PROCESSOR_PENTIUM4,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
472 {"yonah", PROCESSOR_YONAH,
473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
475 {"merom", PROCESSOR_MEROM,
476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
480 {"k6_2", PROCESSOR_K6,
481 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
482 {"athlon", PROCESSOR_ATHLON,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
484 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
485 {"sledgehammer", PROCESSOR_K8,
486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"opteron", PROCESSOR_K8,
489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
490 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"amdfam10", PROCESSOR_AMDFAM10,
495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
496 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
498 {".mmx", PROCESSOR_UNKNOWN,
500 {".sse", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE},
502 {".sse2", PROCESSOR_UNKNOWN,
503 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
504 {".sse3", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
506 {".3dnow", PROCESSOR_UNKNOWN,
508 {".3dnowa", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
510 {".padlock", PROCESSOR_UNKNOWN,
512 {".pacifica", PROCESSOR_UNKNOWN,
514 {".svme", PROCESSOR_UNKNOWN,
516 {".sse4a", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
518 {".abm", PROCESSOR_UNKNOWN,
522 const pseudo_typeS md_pseudo_table[] =
524 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes, 0},
527 {"align", s_align_ptwo, 0},
529 {"arch", set_cpu_arch, 0},
533 {"ffloat", float_cons, 'f'},
534 {"dfloat", float_cons, 'd'},
535 {"tfloat", float_cons, 'x'},
537 {"slong", signed_cons, 4},
538 {"noopt", s_ignore, 0},
539 {"optim", s_ignore, 0},
540 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
541 {"code16", set_code_flag, CODE_16BIT},
542 {"code32", set_code_flag, CODE_32BIT},
543 {"code64", set_code_flag, CODE_64BIT},
544 {"intel_syntax", set_intel_syntax, 1},
545 {"att_syntax", set_intel_syntax, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragP, count)
573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
576 static const char f32_1[] =
578 static const char f32_2[] =
579 {0x66,0x90}; /* xchg %ax,%ax */
580 static const char f32_3[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5[] =
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8[] =
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
615 static const char f16_3[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
617 static const char f16_4[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5[] =
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
637 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
640 static const char alt_3[] =
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
744 if (count <= 0 || count > 15)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
764 if (flag_code == CODE_16BIT)
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
782 for (i = 0; i < remains; i++)
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
788 for (; i < nnops; i++)
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
797 const char *const *patt = NULL;
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
812 case PROCESSOR_MEROM:
813 patt = alt_long_patt;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
818 case PROCESSOR_YONAH:
820 case PROCESSOR_ATHLON:
822 case PROCESSOR_GENERIC64:
823 case PROCESSOR_AMDFAM10:
824 patt = alt_short_patt;
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
835 switch (cpu_arch_tune)
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_YONAH:
850 case PROCESSOR_ATHLON:
852 case PROCESSOR_AMDFAM10:
853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
861 case PROCESSOR_MEROM:
862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
873 memcpy (fragP->fr_literal + fragP->fr_fix,
874 patt[count - 1], count);
876 fragP->fr_var = count;
879 static INLINE unsigned int
880 mode_from_disp_size (t)
883 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
887 fits_in_signed_byte (num)
890 return (num >= -128) && (num <= 127);
894 fits_in_unsigned_byte (num)
897 return (num & 0xff) == num;
901 fits_in_unsigned_word (num)
904 return (num & 0xffff) == num;
908 fits_in_signed_word (num)
911 return (-32768 <= num) && (num <= 32767);
914 fits_in_signed_long (num)
915 offsetT num ATTRIBUTE_UNUSED;
920 return (!(((offsetT) -1 << 31) & num)
921 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
923 } /* fits_in_signed_long() */
925 fits_in_unsigned_long (num)
926 offsetT num ATTRIBUTE_UNUSED;
931 return (num & (((offsetT) 2 << 31) - 1)) == num;
933 } /* fits_in_unsigned_long() */
936 smallest_imm_type (num)
939 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
947 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
949 return (fits_in_signed_byte (num)
950 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_byte (num)
952 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
953 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
954 ? (Imm16 | Imm32 | Imm32S | Imm64)
955 : fits_in_signed_long (num)
956 ? (Imm32 | Imm32S | Imm64)
957 : fits_in_unsigned_long (num)
963 offset_in_range (val, size)
971 case 1: mask = ((addressT) 1 << 8) - 1; break;
972 case 2: mask = ((addressT) 1 << 16) - 1; break;
973 case 4: mask = ((addressT) 2 << 31) - 1; break;
975 case 8: mask = ((addressT) 2 << 63) - 1; break;
980 /* If BFD64, sign extend val. */
981 if (!use_rela_relocations)
982 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
983 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
985 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
987 char buf1[40], buf2[40];
989 sprint_value (buf1, val);
990 sprint_value (buf2, val & mask);
991 as_warn (_("%s shortened to %s"), buf1, buf2);
996 /* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
1001 unsigned int prefix;
1006 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1007 && flag_code == CODE_64BIT)
1009 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1010 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1011 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1022 case CS_PREFIX_OPCODE:
1023 case DS_PREFIX_OPCODE:
1024 case ES_PREFIX_OPCODE:
1025 case FS_PREFIX_OPCODE:
1026 case GS_PREFIX_OPCODE:
1027 case SS_PREFIX_OPCODE:
1031 case REPNE_PREFIX_OPCODE:
1032 case REPE_PREFIX_OPCODE:
1035 case LOCK_PREFIX_OPCODE:
1043 case ADDR_PREFIX_OPCODE:
1047 case DATA_PREFIX_OPCODE:
1051 if (i.prefix[q] != 0)
1059 i.prefix[q] |= prefix;
1062 as_bad (_("same type of prefix used twice"));
1068 set_code_flag (value)
1072 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1073 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1074 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1076 as_bad (_("64bit mode not supported on this CPU."));
1078 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1080 as_bad (_("32bit mode not supported on this CPU."));
1082 stackop_size = '\0';
1086 set_16bit_gcc_code_flag (new_code_flag)
1089 flag_code = new_code_flag;
1090 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1091 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1092 stackop_size = LONG_MNEM_SUFFIX;
1096 set_intel_syntax (syntax_flag)
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg = 0;
1103 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1105 char *string = input_line_pointer;
1106 int e = get_symbol_end ();
1108 if (strcmp (string, "prefix") == 0)
1110 else if (strcmp (string, "noprefix") == 0)
1113 as_bad (_("bad argument to syntax directive."));
1114 *input_line_pointer = e;
1116 demand_empty_rest_of_line ();
1118 intel_syntax = syntax_flag;
1120 if (ask_naked_reg == 0)
1121 allow_naked_reg = (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1124 allow_naked_reg = (ask_naked_reg < 0);
1126 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1127 identifier_chars['$'] = intel_syntax ? '$' : 0;
1131 set_cpu_arch (dummy)
1132 int dummy ATTRIBUTE_UNUSED;
1136 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1138 char *string = input_line_pointer;
1139 int e = get_symbol_end ();
1142 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1144 if (strcmp (string, cpu_arch[i].name) == 0)
1148 cpu_arch_name = cpu_arch[i].name;
1149 cpu_sub_arch_name = NULL;
1150 cpu_arch_flags = (cpu_arch[i].flags
1151 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1152 cpu_arch_isa = cpu_arch[i].type;
1153 cpu_arch_isa_flags = cpu_arch[i].flags;
1154 if (!cpu_arch_tune_set)
1156 cpu_arch_tune = cpu_arch_isa;
1157 cpu_arch_tune_flags = cpu_arch_isa_flags;
1161 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1163 cpu_sub_arch_name = cpu_arch[i].name;
1164 cpu_arch_flags |= cpu_arch[i].flags;
1166 *input_line_pointer = e;
1167 demand_empty_rest_of_line ();
1171 if (i >= ARRAY_SIZE (cpu_arch))
1172 as_bad (_("no such architecture: `%s'"), string);
1174 *input_line_pointer = e;
1177 as_bad (_("missing cpu architecture"));
1179 no_cond_jump_promotion = 0;
1180 if (*input_line_pointer == ','
1181 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1183 char *string = ++input_line_pointer;
1184 int e = get_symbol_end ();
1186 if (strcmp (string, "nojumps") == 0)
1187 no_cond_jump_promotion = 1;
1188 else if (strcmp (string, "jumps") == 0)
1191 as_bad (_("no such architecture modifier: `%s'"), string);
1193 *input_line_pointer = e;
1196 demand_empty_rest_of_line ();
1202 if (!strcmp (default_arch, "x86_64"))
1203 return bfd_mach_x86_64;
1204 else if (!strcmp (default_arch, "i386"))
1205 return bfd_mach_i386_i386;
1207 as_fatal (_("Unknown architecture"));
1213 const char *hash_err;
1215 /* Initialize op_hash hash table. */
1216 op_hash = hash_new ();
1219 const template *optab;
1220 templates *core_optab;
1222 /* Setup for loop. */
1224 core_optab = (templates *) xmalloc (sizeof (templates));
1225 core_optab->start = optab;
1230 if (optab->name == NULL
1231 || strcmp (optab->name, (optab - 1)->name) != 0)
1233 /* different name --> ship out current template list;
1234 add to hash table; & begin anew. */
1235 core_optab->end = optab;
1236 hash_err = hash_insert (op_hash,
1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1245 if (optab->name == NULL)
1247 core_optab = (templates *) xmalloc (sizeof (templates));
1248 core_optab->start = optab;
1253 /* Initialize reg_hash hash table. */
1254 reg_hash = hash_new ();
1256 const reg_entry *regtab;
1258 for (regtab = i386_regtab;
1259 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1262 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1275 for (c = 0; c < 256; c++)
1280 mnemonic_chars[c] = c;
1281 register_chars[c] = c;
1282 operand_chars[c] = c;
1284 else if (ISLOWER (c))
1286 mnemonic_chars[c] = c;
1287 register_chars[c] = c;
1288 operand_chars[c] = c;
1290 else if (ISUPPER (c))
1292 mnemonic_chars[c] = TOLOWER (c);
1293 register_chars[c] = mnemonic_chars[c];
1294 operand_chars[c] = c;
1297 if (ISALPHA (c) || ISDIGIT (c))
1298 identifier_chars[c] = c;
1301 identifier_chars[c] = c;
1302 operand_chars[c] = c;
1307 identifier_chars['@'] = '@';
1310 identifier_chars['?'] = '?';
1311 operand_chars['?'] = '?';
1313 digit_chars['-'] = '-';
1314 mnemonic_chars['-'] = '-';
1315 identifier_chars['_'] = '_';
1316 identifier_chars['.'] = '.';
1318 for (p = operand_special_chars; *p != '\0'; p++)
1319 operand_chars[(unsigned char) *p] = *p;
1322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1325 record_alignment (text_section, 2);
1326 record_alignment (data_section, 2);
1327 record_alignment (bss_section, 2);
1331 if (flag_code == CODE_64BIT)
1333 x86_dwarf2_return_column = 16;
1334 x86_cie_data_alignment = -8;
1338 x86_dwarf2_return_column = 8;
1339 x86_cie_data_alignment = -4;
1344 i386_print_statistics (file)
1347 hash_print_statistics (file, "i386 opcode", op_hash);
1348 hash_print_statistics (file, "i386 register", reg_hash);
1353 /* Debugging routines for md_assemble. */
1354 static void pi PARAMS ((char *, i386_insn *));
1355 static void pte PARAMS ((template *));
1356 static void pt PARAMS ((unsigned int));
1357 static void pe PARAMS ((expressionS *));
1358 static void ps PARAMS ((symbolS *));
1367 fprintf (stdout, "%s: template ", line);
1369 fprintf (stdout, " address: base %s index %s scale %x\n",
1370 x->base_reg ? x->base_reg->reg_name : "none",
1371 x->index_reg ? x->index_reg->reg_name : "none",
1372 x->log2_scale_factor);
1373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1374 x->rm.mode, x->rm.reg, x->rm.regmem);
1375 fprintf (stdout, " sib: base %x index %x scale %x\n",
1376 x->sib.base, x->sib.index, x->sib.scale);
1377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1378 (x->rex & REX_MODE64) != 0,
1379 (x->rex & REX_EXTX) != 0,
1380 (x->rex & REX_EXTY) != 0,
1381 (x->rex & REX_EXTZ) != 0);
1382 for (i = 0; i < x->operands; i++)
1384 fprintf (stdout, " #%d: ", i + 1);
1386 fprintf (stdout, "\n");
1388 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1389 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1390 if (x->types[i] & Imm)
1392 if (x->types[i] & Disp)
1393 pe (x->op[i].disps);
1402 fprintf (stdout, " %d operands ", t->operands);
1403 fprintf (stdout, "opcode %x ", t->base_opcode);
1404 if (t->extension_opcode != None)
1405 fprintf (stdout, "ext %x ", t->extension_opcode);
1406 if (t->opcode_modifier & D)
1407 fprintf (stdout, "D");
1408 if (t->opcode_modifier & W)
1409 fprintf (stdout, "W");
1410 fprintf (stdout, "\n");
1411 for (i = 0; i < t->operands; i++)
1413 fprintf (stdout, " #%d type ", i + 1);
1414 pt (t->operand_types[i]);
1415 fprintf (stdout, "\n");
1423 fprintf (stdout, " operation %d\n", e->X_op);
1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
1426 if (e->X_add_symbol)
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1444 fprintf (stdout, "%s type %s%s",
1446 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s)));
1450 static struct type_name
1455 const type_names[] =
1468 { BaseIndex, "BaseIndex" },
1472 { Disp32S, "d32s" },
1474 { InOutPortReg, "InOutPortReg" },
1475 { ShiftCount, "ShiftCount" },
1476 { Control, "control reg" },
1477 { Test, "test reg" },
1478 { Debug, "debug reg" },
1479 { FloatReg, "FReg" },
1480 { FloatAcc, "FAcc" },
1484 { JumpAbsolute, "Jump Absolute" },
1495 const struct type_name *ty;
1497 for (ty = type_names; ty->mask; ty++)
1499 fprintf (stdout, "%s, ", ty->tname);
1503 #endif /* DEBUG386 */
1505 static bfd_reloc_code_real_type
1506 reloc (unsigned int size,
1509 bfd_reloc_code_real_type other)
1511 if (other != NO_RELOC)
1513 reloc_howto_type *reloc;
1518 case BFD_RELOC_X86_64_GOT32:
1519 return BFD_RELOC_X86_64_GOT64;
1521 case BFD_RELOC_X86_64_PLTOFF64:
1522 return BFD_RELOC_X86_64_PLTOFF64;
1524 case BFD_RELOC_X86_64_GOTPC32:
1525 other = BFD_RELOC_X86_64_GOTPC64;
1527 case BFD_RELOC_X86_64_GOTPCREL:
1528 other = BFD_RELOC_X86_64_GOTPCREL64;
1530 case BFD_RELOC_X86_64_TPOFF32:
1531 other = BFD_RELOC_X86_64_TPOFF64;
1533 case BFD_RELOC_X86_64_DTPOFF32:
1534 other = BFD_RELOC_X86_64_DTPOFF64;
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size == 4 && flag_code != CODE_64BIT)
1544 reloc = bfd_reloc_type_lookup (stdoutput, other);
1546 as_bad (_("unknown relocation (%u)"), other);
1547 else if (size != bfd_get_reloc_size (reloc))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc),
1551 else if (pcrel && !reloc->pc_relative)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc->complain_on_overflow == complain_overflow_signed
1555 || (reloc->complain_on_overflow == complain_overflow_unsigned
1557 as_bad (_("relocated field and relocation type differ in signedness"));
1566 as_bad (_("there are no unsigned pc-relative relocations"));
1569 case 1: return BFD_RELOC_8_PCREL;
1570 case 2: return BFD_RELOC_16_PCREL;
1571 case 4: return BFD_RELOC_32_PCREL;
1572 case 8: return BFD_RELOC_64_PCREL;
1574 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1581 case 4: return BFD_RELOC_X86_64_32S;
1586 case 1: return BFD_RELOC_8;
1587 case 2: return BFD_RELOC_16;
1588 case 4: return BFD_RELOC_32;
1589 case 8: return BFD_RELOC_64;
1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign > 0 ? "signed" : "unsigned", size);
1596 return BFD_RELOC_NONE;
1599 /* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1605 tc_i386_fix_adjustable (fixP)
1606 fixS *fixP ATTRIBUTE_UNUSED;
1608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1622 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1625 /* adjust_reloc_syms doesn't know about the GOT. */
1626 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1627 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1628 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1639 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1642 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1643 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1644 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1645 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1648 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1652 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1653 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1659 static int intel_float_operand PARAMS ((const char *mnemonic));
1662 intel_float_operand (mnemonic)
1663 const char *mnemonic;
1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1669 if (mnemonic[0] != 'f')
1670 return 0; /* non-math */
1672 switch (mnemonic[1])
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1678 return 2 /* integer op */;
1680 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1684 if (mnemonic[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1688 if (mnemonic[2] == 's')
1689 return 3; /* frstor/frstpm */
1692 if (mnemonic[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic[2] == 't')
1696 switch (mnemonic[3])
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1707 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1715 /* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1724 char mnemonic[MAX_MNEM_SIZE];
1726 /* Initialize globals. */
1727 memset (&i, '\0', sizeof (i));
1728 for (j = 0; j < MAX_OPERANDS; j++)
1729 i.reloc[j] = NO_RELOC;
1730 memset (disp_expressions, '\0', sizeof (disp_expressions));
1731 memset (im_expressions, '\0', sizeof (im_expressions));
1732 save_stack_p = save_stack;
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
1736 start of a (possibly prefixed) mnemonic. */
1738 line = parse_insn (line, mnemonic);
1742 line = parse_operands (line, mnemonic);
1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i.imm_operands == 2) &&
1749 ((strcmp (mnemonic, "extrq") == 0)
1750 || (strcmp (mnemonic, "insertq") == 0)))
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
1766 precedes the offset, as it does when in AT&T mode. */
1767 if (intel_syntax && i.operands > 1
1768 && (strcmp (mnemonic, "bound") != 0)
1769 && (strcmp (mnemonic, "invlpga") != 0)
1770 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1776 /* Don't optimize displacement for movabs since it only takes 64bit
1779 && (flag_code != CODE_64BIT
1780 || strcmp (mnemonic, "movabs") != 0))
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
1787 if (!match_template ())
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1794 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1795 i.tm.base_opcode ^= FloatR;
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1802 if (i.reg_operands < 2
1804 && (~i.tm.opcode_modifier
1811 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1817 if (i.tm.opcode_modifier & FWait)
1818 if (!add_prefix (FWAIT_OPCODE))
1821 /* Check string instruction segment overrides. */
1822 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1824 if (!check_string ())
1828 if (!process_suffix ())
1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1836 if (i.types[0] & Imm1)
1837 i.imm_operands = 0; /* kludge for shift insns. */
1838 if (i.types[0] & ImplicitRegister)
1840 if (i.types[1] & ImplicitRegister)
1842 if (i.types[2] & ImplicitRegister)
1845 if (i.tm.opcode_modifier & ImmExt)
1849 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1851 /* These Intel Prescott New Instructions have the fixed
1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1857 for (x = 0; x < i.operands; x++)
1858 if (i.op[x].regs->reg_num != x)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1860 i.op[x].regs->reg_name, x + 1, i.tm.name);
1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
1869 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1871 exp = &im_expressions[i.imm_operands++];
1872 i.op[i.operands].imms = exp;
1873 i.types[i.operands++] = Imm8;
1874 exp->X_op = O_constant;
1875 exp->X_add_number = i.tm.extension_opcode;
1876 i.tm.extension_opcode = None;
1879 /* For insns with operands there are more diddles to do to the opcode. */
1882 if (!process_operands ())
1885 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i.tm.name);
1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1894 i.tm.base_opcode = INT3_OPCODE;
1898 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1899 && i.op[0].disps->X_op == O_constant)
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i.op[0].disps->X_add_symbol = &abs_symbol;
1905 i.op[0].disps->X_op = O_symbol;
1908 if ((i.tm.opcode_modifier & Rex64) != 0)
1909 i.rex |= REX_MODE64;
1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
1915 if (((i.types[0] & Reg8) != 0
1916 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1917 || ((i.types[1] & Reg8) != 0
1918 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1919 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1924 i.rex |= REX_OPCODE;
1925 for (x = 0; x < 2; x++)
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i.types[x] & Reg8) != 0
1929 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1931 /* In case it is "hi" register, give up. */
1932 if (i.op[x].regs->reg_num > 3)
1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1934 i.op[x].regs->reg_name);
1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1940 i.op[x].regs = i.op[x].regs + 8;
1946 add_prefix (REX_OPCODE | i.rex);
1948 /* We are ready to output the insn. */
1953 parse_insn (line, mnemonic)
1958 char *token_start = l;
1963 /* Non-zero if we found a prefix only acceptable with string insns. */
1964 const char *expecting_string_instruction = NULL;
1969 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1972 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1974 as_bad (_("no such instruction: `%s'"), token_start);
1979 if (!is_space_char (*l)
1980 && *l != END_OF_INSN
1982 || (*l != PREFIX_SEPARATOR
1985 as_bad (_("invalid character %s in mnemonic"),
1986 output_invalid (*l));
1989 if (token_start == l)
1991 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1992 as_bad (_("expecting prefix; got nothing"));
1994 as_bad (_("expecting mnemonic; got nothing"));
1998 /* Look up instruction (or prefix) via hash table. */
1999 current_templates = hash_find (op_hash, mnemonic);
2001 if (*l != END_OF_INSN
2002 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2003 && current_templates
2004 && (current_templates->start->opcode_modifier & IsPrefix))
2006 if (current_templates->start->cpu_flags
2007 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2009 as_bad ((flag_code != CODE_64BIT
2010 ? _("`%s' is only supported in 64-bit mode")
2011 : _("`%s' is not supported in 64-bit mode")),
2012 current_templates->start->name);
2015 /* If we are in 16-bit mode, do not allow addr16 or data16.
2016 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2017 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2018 && flag_code != CODE_64BIT
2019 && (((current_templates->start->opcode_modifier & Size32) != 0)
2020 ^ (flag_code == CODE_16BIT)))
2022 as_bad (_("redundant %s prefix"),
2023 current_templates->start->name);
2026 /* Add prefix, checking for repeated prefixes. */
2027 switch (add_prefix (current_templates->start->base_opcode))
2032 expecting_string_instruction = current_templates->start->name;
2035 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2042 if (!current_templates)
2044 /* See if we can get a match by trimming off a suffix. */
2047 case WORD_MNEM_SUFFIX:
2048 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2049 i.suffix = SHORT_MNEM_SUFFIX;
2051 case BYTE_MNEM_SUFFIX:
2052 case QWORD_MNEM_SUFFIX:
2053 i.suffix = mnem_p[-1];
2055 current_templates = hash_find (op_hash, mnemonic);
2057 case SHORT_MNEM_SUFFIX:
2058 case LONG_MNEM_SUFFIX:
2061 i.suffix = mnem_p[-1];
2063 current_templates = hash_find (op_hash, mnemonic);
2071 if (intel_float_operand (mnemonic) == 1)
2072 i.suffix = SHORT_MNEM_SUFFIX;
2074 i.suffix = LONG_MNEM_SUFFIX;
2076 current_templates = hash_find (op_hash, mnemonic);
2080 if (!current_templates)
2082 as_bad (_("no such instruction: `%s'"), token_start);
2087 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2089 /* Check for a branch hint. We allow ",pt" and ",pn" for
2090 predict taken and predict not taken respectively.
2091 I'm not sure that branch hints actually do anything on loop
2092 and jcxz insns (JumpByte) for current Pentium4 chips. They
2093 may work in the future and it doesn't hurt to accept them
2095 if (l[0] == ',' && l[1] == 'p')
2099 if (!add_prefix (DS_PREFIX_OPCODE))
2103 else if (l[2] == 'n')
2105 if (!add_prefix (CS_PREFIX_OPCODE))
2111 /* Any other comma loses. */
2114 as_bad (_("invalid character %s in mnemonic"),
2115 output_invalid (*l));
2119 /* Check if instruction is supported on specified architecture. */
2121 for (t = current_templates->start; t < current_templates->end; ++t)
2123 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2124 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2126 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2129 if (!(supported & 2))
2131 as_bad (flag_code == CODE_64BIT
2132 ? _("`%s' is not supported in 64-bit mode")
2133 : _("`%s' is only supported in 64-bit mode"),
2134 current_templates->start->name);
2137 if (!(supported & 1))
2139 as_warn (_("`%s' is not supported on `%s%s'"),
2140 current_templates->start->name,
2142 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2144 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2146 as_warn (_("use .code16 to ensure correct addressing mode"));
2149 /* Check for rep/repne without a string instruction. */
2150 if (expecting_string_instruction)
2152 static templates override;
2154 for (t = current_templates->start; t < current_templates->end; ++t)
2155 if (t->opcode_modifier & IsString)
2157 if (t >= current_templates->end)
2159 as_bad (_("expecting string instruction after `%s'"),
2160 expecting_string_instruction);
2163 for (override.start = t; t < current_templates->end; ++t)
2164 if (!(t->opcode_modifier & IsString))
2167 current_templates = &override;
2174 parse_operands (l, mnemonic)
2176 const char *mnemonic;
2180 /* 1 if operand is pending after ','. */
2181 unsigned int expecting_operand = 0;
2183 /* Non-zero if operand parens not balanced. */
2184 unsigned int paren_not_balanced;
2186 while (*l != END_OF_INSN)
2188 /* Skip optional white space before operand. */
2189 if (is_space_char (*l))
2191 if (!is_operand_char (*l) && *l != END_OF_INSN)
2193 as_bad (_("invalid character %s before operand %d"),
2194 output_invalid (*l),
2198 token_start = l; /* after white space */
2199 paren_not_balanced = 0;
2200 while (paren_not_balanced || *l != ',')
2202 if (*l == END_OF_INSN)
2204 if (paren_not_balanced)
2207 as_bad (_("unbalanced parenthesis in operand %d."),
2210 as_bad (_("unbalanced brackets in operand %d."),
2215 break; /* we are done */
2217 else if (!is_operand_char (*l) && !is_space_char (*l))
2219 as_bad (_("invalid character %s in operand %d"),
2220 output_invalid (*l),
2227 ++paren_not_balanced;
2229 --paren_not_balanced;
2234 ++paren_not_balanced;
2236 --paren_not_balanced;
2240 if (l != token_start)
2241 { /* Yes, we've read in another operand. */
2242 unsigned int operand_ok;
2243 this_operand = i.operands++;
2244 if (i.operands > MAX_OPERANDS)
2246 as_bad (_("spurious operands; (%d operands/instruction max)"),
2250 /* Now parse operand adding info to 'i' as we go along. */
2251 END_STRING_AND_SAVE (l);
2255 i386_intel_operand (token_start,
2256 intel_float_operand (mnemonic));
2258 operand_ok = i386_operand (token_start);
2260 RESTORE_END_STRING (l);
2266 if (expecting_operand)
2268 expecting_operand_after_comma:
2269 as_bad (_("expecting operand after ','; got nothing"));
2274 as_bad (_("expecting operand before ','; got nothing"));
2279 /* Now *l must be either ',' or END_OF_INSN. */
2282 if (*++l == END_OF_INSN)
2284 /* Just skip it, if it's \n complain. */
2285 goto expecting_operand_after_comma;
2287 expecting_operand = 1;
2294 swap_imm_operands ()
2296 union i386_op temp_op;
2297 unsigned int temp_type;
2298 enum bfd_reloc_code_real temp_reloc;
2302 temp_type = i.types[xchg2];
2303 i.types[xchg2] = i.types[xchg1];
2304 i.types[xchg1] = temp_type;
2305 temp_op = i.op[xchg2];
2306 i.op[xchg2] = i.op[xchg1];
2307 i.op[xchg1] = temp_op;
2308 temp_reloc = i.reloc[xchg2];
2309 i.reloc[xchg2] = i.reloc[xchg1];
2310 i.reloc[xchg1] = temp_reloc;
2317 union i386_op temp_op;
2318 unsigned int temp_type;
2319 enum bfd_reloc_code_real temp_reloc;
2323 if (i.operands == 4)
2324 /* There will be two exchanges in a 4 operand instruction.
2325 First exchange is the done inside this block.(1st and 4rth operand)
2326 The next exchange is done outside this block.(2nd and 3rd operand) */
2330 temp_type = i.types[xchg2];
2331 i.types[xchg2] = i.types[xchg1];
2332 i.types[xchg1] = temp_type;
2333 temp_op = i.op[xchg2];
2334 i.op[xchg2] = i.op[xchg1];
2335 i.op[xchg1] = temp_op;
2336 temp_reloc = i.reloc[xchg2];
2337 i.reloc[xchg2] = i.reloc[xchg1];
2338 i.reloc[xchg1] = temp_reloc;
2343 if (i.operands == 2)
2348 else if (i.operands == 3)
2353 temp_type = i.types[xchg2];
2354 i.types[xchg2] = i.types[xchg1];
2355 i.types[xchg1] = temp_type;
2356 temp_op = i.op[xchg2];
2357 i.op[xchg2] = i.op[xchg1];
2358 i.op[xchg1] = temp_op;
2359 temp_reloc = i.reloc[xchg2];
2360 i.reloc[xchg2] = i.reloc[xchg1];
2361 i.reloc[xchg1] = temp_reloc;
2363 if (i.mem_operands == 2)
2365 const seg_entry *temp_seg;
2366 temp_seg = i.seg[0];
2367 i.seg[0] = i.seg[1];
2368 i.seg[1] = temp_seg;
2372 /* Try to ensure constant immediates are represented in the smallest
2377 char guess_suffix = 0;
2381 guess_suffix = i.suffix;
2382 else if (i.reg_operands)
2384 /* Figure out a suffix from the last register operand specified.
2385 We can't do this properly yet, ie. excluding InOutPortReg,
2386 but the following works for instructions with immediates.
2387 In any case, we can't set i.suffix yet. */
2388 for (op = i.operands; --op >= 0;)
2389 if (i.types[op] & Reg)
2391 if (i.types[op] & Reg8)
2392 guess_suffix = BYTE_MNEM_SUFFIX;
2393 else if (i.types[op] & Reg16)
2394 guess_suffix = WORD_MNEM_SUFFIX;
2395 else if (i.types[op] & Reg32)
2396 guess_suffix = LONG_MNEM_SUFFIX;
2397 else if (i.types[op] & Reg64)
2398 guess_suffix = QWORD_MNEM_SUFFIX;
2402 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2403 guess_suffix = WORD_MNEM_SUFFIX;
2405 for (op = i.operands; --op >= 0;)
2406 if (i.types[op] & Imm)
2408 switch (i.op[op].imms->X_op)
2411 /* If a suffix is given, this operand may be shortened. */
2412 switch (guess_suffix)
2414 case LONG_MNEM_SUFFIX:
2415 i.types[op] |= Imm32 | Imm64;
2417 case WORD_MNEM_SUFFIX:
2418 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2420 case BYTE_MNEM_SUFFIX:
2421 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2425 /* If this operand is at most 16 bits, convert it
2426 to a signed 16 bit number before trying to see
2427 whether it will fit in an even smaller size.
2428 This allows a 16-bit operand such as $0xffe0 to
2429 be recognised as within Imm8S range. */
2430 if ((i.types[op] & Imm16)
2431 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2433 i.op[op].imms->X_add_number =
2434 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2436 if ((i.types[op] & Imm32)
2437 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2440 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2441 ^ ((offsetT) 1 << 31))
2442 - ((offsetT) 1 << 31));
2444 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2446 /* We must avoid matching of Imm32 templates when 64bit
2447 only immediate is available. */
2448 if (guess_suffix == QWORD_MNEM_SUFFIX)
2449 i.types[op] &= ~Imm32;
2456 /* Symbols and expressions. */
2458 /* Convert symbolic operand to proper sizes for matching, but don't
2459 prevent matching a set of insns that only supports sizes other
2460 than those matching the insn suffix. */
2462 unsigned int mask, allowed = 0;
2465 for (t = current_templates->start; t < current_templates->end; ++t)
2466 allowed |= t->operand_types[op];
2467 switch (guess_suffix)
2469 case QWORD_MNEM_SUFFIX:
2470 mask = Imm64 | Imm32S;
2472 case LONG_MNEM_SUFFIX:
2475 case WORD_MNEM_SUFFIX:
2478 case BYTE_MNEM_SUFFIX:
2486 i.types[op] &= mask;
2493 /* Try to use the smallest displacement type too. */
2499 for (op = i.operands; --op >= 0;)
2500 if (i.types[op] & Disp)
2502 if (i.op[op].disps->X_op == O_constant)
2504 offsetT disp = i.op[op].disps->X_add_number;
2506 if ((i.types[op] & Disp16)
2507 && (disp & ~(offsetT) 0xffff) == 0)
2509 /* If this operand is at most 16 bits, convert
2510 to a signed 16 bit number and don't use 64bit
2512 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2513 i.types[op] &= ~Disp64;
2515 if ((i.types[op] & Disp32)
2516 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2518 /* If this operand is at most 32 bits, convert
2519 to a signed 32 bit number and don't use 64bit
2521 disp &= (((offsetT) 2 << 31) - 1);
2522 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2523 i.types[op] &= ~Disp64;
2525 if (!disp && (i.types[op] & BaseIndex))
2527 i.types[op] &= ~Disp;
2531 else if (flag_code == CODE_64BIT)
2533 if (fits_in_signed_long (disp))
2535 i.types[op] &= ~Disp64;
2536 i.types[op] |= Disp32S;
2538 if (fits_in_unsigned_long (disp))
2539 i.types[op] |= Disp32;
2541 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2542 && fits_in_signed_byte (disp))
2543 i.types[op] |= Disp8;
2545 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2546 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2548 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2549 i.op[op].disps, 0, i.reloc[op]);
2550 i.types[op] &= ~Disp;
2553 /* We only support 64bit displacement on constants. */
2554 i.types[op] &= ~Disp64;
2561 /* Points to template once we've found it. */
2563 unsigned int overlap0, overlap1, overlap2;
2564 unsigned int found_reverse_match;
2566 unsigned int operand_types [3];
2567 int addr_prefix_disp;
2569 #define MATCH(overlap, given, template) \
2570 ((overlap & ~JumpAbsolute) \
2571 && (((given) & (BaseIndex | JumpAbsolute)) \
2572 == ((overlap) & (BaseIndex | JumpAbsolute))))
2574 /* If given types r0 and r1 are registers they must be of the same type
2575 unless the expected operand type register overlap is null.
2576 Note that Acc in a template matches every size of reg. */
2577 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2578 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2579 || ((g0) & Reg) == ((g1) & Reg) \
2580 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2585 found_reverse_match = 0;
2586 operand_types [0] = 0;
2587 operand_types [1] = 0;
2588 operand_types [2] = 0;
2589 addr_prefix_disp = -1;
2590 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2592 : (i.suffix == WORD_MNEM_SUFFIX
2594 : (i.suffix == SHORT_MNEM_SUFFIX
2596 : (i.suffix == LONG_MNEM_SUFFIX
2598 : (i.suffix == QWORD_MNEM_SUFFIX
2600 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2601 ? No_xSuf : 0))))));
2603 for (t = current_templates->start; t < current_templates->end; t++)
2605 addr_prefix_disp = -1;
2607 /* Must have right number of operands. */
2608 if (i.operands != t->operands)
2611 /* Check the suffix, except for some instructions in intel mode. */
2612 if ((t->opcode_modifier & suffix_check)
2614 && (t->opcode_modifier & IgnoreSize)))
2617 operand_types [0] = t->operand_types [0];
2618 operand_types [1] = t->operand_types [1];
2619 operand_types [2] = t->operand_types [2];
2621 /* In general, don't allow 64-bit operands in 32-bit mode. */
2622 if (i.suffix == QWORD_MNEM_SUFFIX
2623 && flag_code != CODE_64BIT
2625 ? (!(t->opcode_modifier & IgnoreSize)
2626 && !intel_float_operand (t->name))
2627 : intel_float_operand (t->name) != 2)
2628 && (!(operand_types[0] & (RegMMX | RegXMM))
2629 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2630 && (t->base_opcode != 0x0fc7
2631 || t->extension_opcode != 1 /* cmpxchg8b */))
2634 /* Do not verify operands when there are none. */
2635 else if (!t->operands)
2637 if (t->cpu_flags & ~cpu_arch_flags)
2639 /* We've found a match; break out of loop. */
2643 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2644 into Disp32/Disp16/Disp32 operand. */
2645 if (i.prefix[ADDR_PREFIX] != 0)
2647 unsigned int j, DispOn = 0, DispOff = 0;
2665 for (j = 0; j < 3; j++)
2667 /* There should be only one Disp operand. */
2668 if ((operand_types[j] & DispOff))
2670 addr_prefix_disp = j;
2671 operand_types[j] |= DispOn;
2672 operand_types[j] &= ~DispOff;
2678 overlap0 = i.types[0] & operand_types[0];
2679 switch (t->operands)
2682 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2687 overlap1 = i.types[1] & operand_types[1];
2688 if (!MATCH (overlap0, i.types[0], operand_types[0])
2689 || !MATCH (overlap1, i.types[1], operand_types[1])
2690 /* monitor in SSE3 is a very special case. The first
2691 register and the second register may have different
2693 || !((t->base_opcode == 0x0f01
2694 && t->extension_opcode == 0xc8)
2695 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2697 overlap1, i.types[1],
2700 /* Check if other direction is valid ... */
2701 if ((t->opcode_modifier & (D | FloatD)) == 0)
2704 /* Try reversing direction of operands. */
2705 overlap0 = i.types[0] & operand_types[1];
2706 overlap1 = i.types[1] & operand_types[0];
2707 if (!MATCH (overlap0, i.types[0], operand_types[1])
2708 || !MATCH (overlap1, i.types[1], operand_types[0])
2709 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2711 overlap1, i.types[1],
2714 /* Does not match either direction. */
2717 /* found_reverse_match holds which of D or FloatDR
2719 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2721 /* Found a forward 2 operand match here. */
2722 else if (t->operands == 3)
2724 /* Here we make use of the fact that there are no
2725 reverse match 3 operand instructions, and all 3
2726 operand instructions only need to be checked for
2727 register consistency between operands 2 and 3. */
2728 overlap2 = i.types[2] & operand_types[2];
2729 if (!MATCH (overlap2, i.types[2], operand_types[2])
2730 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2732 overlap2, i.types[2],
2737 /* Found either forward/reverse 2 or 3 operand match here:
2738 slip through to break. */
2740 if (t->cpu_flags & ~cpu_arch_flags)
2742 found_reverse_match = 0;
2745 /* We've found a match; break out of loop. */
2749 if (t == current_templates->end)
2751 /* We found no match. */
2752 as_bad (_("suffix or operands invalid for `%s'"),
2753 current_templates->start->name);
2757 if (!quiet_warnings)
2760 && ((i.types[0] & JumpAbsolute)
2761 != (operand_types[0] & JumpAbsolute)))
2763 as_warn (_("indirect %s without `*'"), t->name);
2766 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2767 == (IsPrefix | IgnoreSize))
2769 /* Warn them that a data or address size prefix doesn't
2770 affect assembly of the next line of code. */
2771 as_warn (_("stand-alone `%s' prefix"), t->name);
2775 /* Copy the template we found. */
2778 if (addr_prefix_disp != -1)
2779 i.tm.operand_types[addr_prefix_disp]
2780 = operand_types[addr_prefix_disp];
2782 if (found_reverse_match)
2784 /* If we found a reverse match we must alter the opcode
2785 direction bit. found_reverse_match holds bits to change
2786 (different for int & float insns). */
2788 i.tm.base_opcode ^= found_reverse_match;
2790 i.tm.operand_types[0] = operand_types[1];
2791 i.tm.operand_types[1] = operand_types[0];
2800 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2801 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2803 if (i.seg[0] != NULL && i.seg[0] != &es)
2805 as_bad (_("`%s' operand %d must use `%%es' segment"),
2810 /* There's only ever one segment override allowed per instruction.
2811 This instruction possibly has a legal segment override on the
2812 second operand, so copy the segment to where non-string
2813 instructions store it, allowing common code. */
2814 i.seg[0] = i.seg[1];
2816 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2818 if (i.seg[1] != NULL && i.seg[1] != &es)
2820 as_bad (_("`%s' operand %d must use `%%es' segment"),
2830 process_suffix (void)
2832 /* If matched instruction specifies an explicit instruction mnemonic
2834 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2836 if (i.tm.opcode_modifier & Size16)
2837 i.suffix = WORD_MNEM_SUFFIX;
2838 else if (i.tm.opcode_modifier & Size64)
2839 i.suffix = QWORD_MNEM_SUFFIX;
2841 i.suffix = LONG_MNEM_SUFFIX;
2843 else if (i.reg_operands)
2845 /* If there's no instruction mnemonic suffix we try to invent one
2846 based on register operands. */
2849 /* We take i.suffix from the last register operand specified,
2850 Destination register type is more significant than source
2854 for (op = i.operands; --op >= 0;)
2855 if ((i.types[op] & Reg)
2856 && !(i.tm.operand_types[op] & InOutPortReg))
2858 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2859 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2860 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2865 else if (i.suffix == BYTE_MNEM_SUFFIX)
2867 if (!check_byte_reg ())
2870 else if (i.suffix == LONG_MNEM_SUFFIX)
2872 if (!check_long_reg ())
2875 else if (i.suffix == QWORD_MNEM_SUFFIX)
2877 if (!check_qword_reg ())
2880 else if (i.suffix == WORD_MNEM_SUFFIX)
2882 if (!check_word_reg ())
2885 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2886 /* Do nothing if the instruction is going to ignore the prefix. */
2891 else if ((i.tm.opcode_modifier & DefaultSize)
2893 /* exclude fldenv/frstor/fsave/fstenv */
2894 && (i.tm.opcode_modifier & No_sSuf))
2896 i.suffix = stackop_size;
2898 else if (intel_syntax
2900 && ((i.tm.operand_types[0] & JumpAbsolute)
2901 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2902 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2903 && i.tm.extension_opcode <= 3)))
2908 if (!(i.tm.opcode_modifier & No_qSuf))
2910 i.suffix = QWORD_MNEM_SUFFIX;
2914 if (!(i.tm.opcode_modifier & No_lSuf))
2915 i.suffix = LONG_MNEM_SUFFIX;
2918 if (!(i.tm.opcode_modifier & No_wSuf))
2919 i.suffix = WORD_MNEM_SUFFIX;
2928 if (i.tm.opcode_modifier & W)
2930 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2936 unsigned int suffixes = (~i.tm.opcode_modifier
2944 if ((i.tm.opcode_modifier & W)
2945 || ((suffixes & (suffixes - 1))
2946 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2948 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2954 /* Change the opcode based on the operand size given by i.suffix;
2955 We don't need to change things for byte insns. */
2957 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2959 /* It's not a byte, select word/dword operation. */
2960 if (i.tm.opcode_modifier & W)
2962 if (i.tm.opcode_modifier & ShortForm)
2963 i.tm.base_opcode |= 8;
2965 i.tm.base_opcode |= 1;
2968 /* Now select between word & dword operations via the operand
2969 size prefix, except for instructions that will ignore this
2971 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2973 /* monitor in SSE3 is a very special case. The default size
2974 of AX is the size of mode. The address size override
2975 prefix will change the size of AX. */
2976 if (i.op->regs[0].reg_type &
2977 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2978 if (!add_prefix (ADDR_PREFIX_OPCODE))
2981 else if (i.suffix != QWORD_MNEM_SUFFIX
2982 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2983 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2984 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2985 || (flag_code == CODE_64BIT
2986 && (i.tm.opcode_modifier & JumpByte))))
2988 unsigned int prefix = DATA_PREFIX_OPCODE;
2990 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2991 prefix = ADDR_PREFIX_OPCODE;
2993 if (!add_prefix (prefix))
2997 /* Set mode64 for an operand. */
2998 if (i.suffix == QWORD_MNEM_SUFFIX
2999 && flag_code == CODE_64BIT
3000 && (i.tm.opcode_modifier & NoRex64) == 0)
3002 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3005 || i.types [0] != (Acc | Reg64)
3006 || i.types [1] != (Acc | Reg64)
3007 || strcmp (i.tm.name, "xchg") != 0)
3008 i.rex |= REX_MODE64;
3011 /* Size floating point instruction. */
3012 if (i.suffix == LONG_MNEM_SUFFIX)
3013 if (i.tm.opcode_modifier & FloatMF)
3014 i.tm.base_opcode ^= 4;
3021 check_byte_reg (void)
3025 for (op = i.operands; --op >= 0;)
3027 /* If this is an eight bit register, it's OK. If it's the 16 or
3028 32 bit version of an eight bit register, we will just use the
3029 low portion, and that's OK too. */
3030 if (i.types[op] & Reg8)
3033 /* movzx and movsx should not generate this warning. */
3035 && (i.tm.base_opcode == 0xfb7
3036 || i.tm.base_opcode == 0xfb6
3037 || i.tm.base_opcode == 0x63
3038 || i.tm.base_opcode == 0xfbe
3039 || i.tm.base_opcode == 0xfbf))
3042 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3044 /* Prohibit these changes in the 64bit mode, since the
3045 lowering is more complicated. */
3046 if (flag_code == CODE_64BIT
3047 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3049 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3050 i.op[op].regs->reg_name,
3054 #if REGISTER_WARNINGS
3056 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3057 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3058 (i.op[op].regs + (i.types[op] & Reg16
3059 ? REGNAM_AL - REGNAM_AX
3060 : REGNAM_AL - REGNAM_EAX))->reg_name,
3061 i.op[op].regs->reg_name,
3066 /* Any other register is bad. */
3067 if (i.types[op] & (Reg | RegMMX | RegXMM
3069 | Control | Debug | Test
3070 | FloatReg | FloatAcc))
3072 as_bad (_("`%%%s' not allowed with `%s%c'"),
3073 i.op[op].regs->reg_name,
3087 for (op = i.operands; --op >= 0;)
3088 /* Reject eight bit registers, except where the template requires
3089 them. (eg. movzb) */
3090 if ((i.types[op] & Reg8) != 0
3091 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3093 as_bad (_("`%%%s' not allowed with `%s%c'"),
3094 i.op[op].regs->reg_name,
3099 /* Warn if the e prefix on a general reg is missing. */
3100 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3101 && (i.types[op] & Reg16) != 0
3102 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3104 /* Prohibit these changes in the 64bit mode, since the
3105 lowering is more complicated. */
3106 if (flag_code == CODE_64BIT)
3108 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3109 i.op[op].regs->reg_name,
3113 #if REGISTER_WARNINGS
3115 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3116 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3117 i.op[op].regs->reg_name,
3121 /* Warn if the r prefix on a general reg is missing. */
3122 else if ((i.types[op] & Reg64) != 0
3123 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3125 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3126 i.op[op].regs->reg_name,
3138 for (op = i.operands; --op >= 0; )
3139 /* Reject eight bit registers, except where the template requires
3140 them. (eg. movzb) */
3141 if ((i.types[op] & Reg8) != 0
3142 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3144 as_bad (_("`%%%s' not allowed with `%s%c'"),
3145 i.op[op].regs->reg_name,
3150 /* Warn if the e prefix on a general reg is missing. */
3151 else if (((i.types[op] & Reg16) != 0
3152 || (i.types[op] & Reg32) != 0)
3153 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3155 /* Prohibit these changes in the 64bit mode, since the
3156 lowering is more complicated. */
3157 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3158 i.op[op].regs->reg_name,
3169 for (op = i.operands; --op >= 0;)
3170 /* Reject eight bit registers, except where the template requires
3171 them. (eg. movzb) */
3172 if ((i.types[op] & Reg8) != 0
3173 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3175 as_bad (_("`%%%s' not allowed with `%s%c'"),
3176 i.op[op].regs->reg_name,
3181 /* Warn if the e prefix on a general reg is present. */
3182 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3183 && (i.types[op] & Reg32) != 0
3184 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3186 /* Prohibit these changes in the 64bit mode, since the
3187 lowering is more complicated. */
3188 if (flag_code == CODE_64BIT)
3190 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3191 i.op[op].regs->reg_name,
3196 #if REGISTER_WARNINGS
3197 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3198 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3199 i.op[op].regs->reg_name,
3209 unsigned int overlap0, overlap1, overlap2;
3211 overlap0 = i.types[0] & i.tm.operand_types[0];
3212 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3213 && overlap0 != Imm8 && overlap0 != Imm8S
3214 && overlap0 != Imm16 && overlap0 != Imm32S
3215 && overlap0 != Imm32 && overlap0 != Imm64)
3219 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3221 : (i.suffix == WORD_MNEM_SUFFIX
3223 : (i.suffix == QWORD_MNEM_SUFFIX
3227 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3228 || overlap0 == (Imm16 | Imm32)
3229 || overlap0 == (Imm16 | Imm32S))
3231 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3234 if (overlap0 != Imm8 && overlap0 != Imm8S
3235 && overlap0 != Imm16 && overlap0 != Imm32S
3236 && overlap0 != Imm32 && overlap0 != Imm64)
3238 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3242 i.types[0] = overlap0;
3244 overlap1 = i.types[1] & i.tm.operand_types[1];
3245 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3246 && overlap1 != Imm8 && overlap1 != Imm8S
3247 && overlap1 != Imm16 && overlap1 != Imm32S
3248 && overlap1 != Imm32 && overlap1 != Imm64)
3252 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3254 : (i.suffix == WORD_MNEM_SUFFIX
3256 : (i.suffix == QWORD_MNEM_SUFFIX
3260 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3261 || overlap1 == (Imm16 | Imm32)
3262 || overlap1 == (Imm16 | Imm32S))
3264 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3267 if (overlap1 != Imm8 && overlap1 != Imm8S
3268 && overlap1 != Imm16 && overlap1 != Imm32S
3269 && overlap1 != Imm32 && overlap1 != Imm64)
3271 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3275 i.types[1] = overlap1;
3277 overlap2 = i.types[2] & i.tm.operand_types[2];
3278 assert ((overlap2 & Imm) == 0);
3279 i.types[2] = overlap2;
3287 /* Default segment register this instruction will use for memory
3288 accesses. 0 means unknown. This is only for optimizing out
3289 unnecessary segment overrides. */
3290 const seg_entry *default_seg = 0;
3292 /* The imul $imm, %reg instruction is converted into
3293 imul $imm, %reg, %reg, and the clr %reg instruction
3294 is converted into xor %reg, %reg. */
3295 if (i.tm.opcode_modifier & regKludge)
3297 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3298 /* Pretend we saw the extra register operand. */
3299 assert (i.op[first_reg_op + 1].regs == 0);
3300 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3301 i.types[first_reg_op + 1] = i.types[first_reg_op];
3305 if (i.tm.opcode_modifier & ShortForm)
3307 /* The register or float register operand is in operand 0 or 1. */
3308 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3309 /* Register goes in low 3 bits of opcode. */
3310 i.tm.base_opcode |= i.op[op].regs->reg_num;
3311 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3313 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3315 /* Warn about some common errors, but press on regardless.
3316 The first case can be generated by gcc (<= 2.8.1). */
3317 if (i.operands == 2)
3319 /* Reversed arguments on faddp, fsubp, etc. */
3320 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3321 i.op[1].regs->reg_name,
3322 i.op[0].regs->reg_name);
3326 /* Extraneous `l' suffix on fp insn. */
3327 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3328 i.op[0].regs->reg_name);
3332 else if (i.tm.opcode_modifier & Modrm)
3334 /* The opcode is completed (modulo i.tm.extension_opcode which
3335 must be put into the modrm byte). Now, we make the modrm and
3336 index base bytes based on all the info we've collected. */
3338 default_seg = build_modrm_byte ();
3340 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3342 if (i.tm.base_opcode == POP_SEG_SHORT
3343 && i.op[0].regs->reg_num == 1)
3345 as_bad (_("you can't `pop %%cs'"));
3348 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3349 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3352 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3356 else if ((i.tm.opcode_modifier & IsString) != 0)
3358 /* For the string instructions that allow a segment override
3359 on one of their operands, the default segment is ds. */
3363 if ((i.tm.base_opcode == 0x8d /* lea */
3364 || (i.tm.cpu_flags & CpuSVME))
3365 && i.seg[0] && !quiet_warnings)
3366 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3368 /* If a segment was explicitly specified, and the specified segment
3369 is not the default, use an opcode prefix to select it. If we
3370 never figured out what the default segment is, then default_seg
3371 will be zero at this point, and the specified segment prefix will
3373 if ((i.seg[0]) && (i.seg[0] != default_seg))
3375 if (!add_prefix (i.seg[0]->seg_prefix))
3381 static const seg_entry *
3384 const seg_entry *default_seg = 0;
3386 /* i.reg_operands MUST be the number of real register operands;
3387 implicit registers do not count. */
3388 if (i.reg_operands == 2)
3390 unsigned int source, dest;
3391 source = ((i.types[0]
3392 & (Reg | RegMMX | RegXMM
3394 | Control | Debug | Test))
3397 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3398 bytes and hence source operand will be in the next byte after the immediates */
3399 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
3403 /* One of the register operands will be encoded in the i.tm.reg
3404 field, the other in the combined i.tm.mode and i.tm.regmem
3405 fields. If no form of this instruction supports a memory
3406 destination operand, then we assume the source operand may
3407 sometimes be a memory operand and so we need to store the
3408 destination in the i.rm.reg field. */
3409 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3411 i.rm.reg = i.op[dest].regs->reg_num;
3412 i.rm.regmem = i.op[source].regs->reg_num;
3413 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3415 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3420 i.rm.reg = i.op[source].regs->reg_num;
3421 i.rm.regmem = i.op[dest].regs->reg_num;
3422 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3424 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3427 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3429 if (!((i.types[0] | i.types[1]) & Control))
3431 i.rex &= ~(REX_EXTX | REX_EXTZ);
3432 add_prefix (LOCK_PREFIX_OPCODE);
3436 { /* If it's not 2 reg operands... */
3439 unsigned int fake_zero_displacement = 0;
3440 unsigned int op = ((i.types[0] & AnyMem)
3442 : (i.types[1] & AnyMem) ? 1 : 2);
3446 if (i.base_reg == 0)
3449 if (!i.disp_operands)
3450 fake_zero_displacement = 1;
3451 if (i.index_reg == 0)
3453 /* Operand is just <disp> */
3454 if (flag_code == CODE_64BIT)
3456 /* 64bit mode overwrites the 32bit absolute
3457 addressing by RIP relative addressing and
3458 absolute addressing is encoded by one of the
3459 redundant SIB forms. */
3460 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3461 i.sib.base = NO_BASE_REGISTER;
3462 i.sib.index = NO_INDEX_REGISTER;
3463 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3465 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3467 i.rm.regmem = NO_BASE_REGISTER_16;
3468 i.types[op] = Disp16;
3472 i.rm.regmem = NO_BASE_REGISTER;
3473 i.types[op] = Disp32;
3476 else /* !i.base_reg && i.index_reg */
3478 i.sib.index = i.index_reg->reg_num;
3479 i.sib.base = NO_BASE_REGISTER;
3480 i.sib.scale = i.log2_scale_factor;
3481 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3482 i.types[op] &= ~Disp;
3483 if (flag_code != CODE_64BIT)
3484 i.types[op] |= Disp32; /* Must be 32 bit */
3486 i.types[op] |= Disp32S;
3487 if ((i.index_reg->reg_flags & RegRex) != 0)
3491 /* RIP addressing for 64bit mode. */
3492 else if (i.base_reg->reg_type == BaseIndex)
3494 i.rm.regmem = NO_BASE_REGISTER;
3495 i.types[op] &= ~ Disp;
3496 i.types[op] |= Disp32S;
3497 i.flags[op] = Operand_PCrel;
3498 if (! i.disp_operands)
3499 fake_zero_displacement = 1;
3501 else if (i.base_reg->reg_type & Reg16)
3503 switch (i.base_reg->reg_num)
3506 if (i.index_reg == 0)
3508 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3509 i.rm.regmem = i.index_reg->reg_num - 6;
3513 if (i.index_reg == 0)
3516 if ((i.types[op] & Disp) == 0)
3518 /* fake (%bp) into 0(%bp) */
3519 i.types[op] |= Disp8;
3520 fake_zero_displacement = 1;
3523 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3524 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3526 default: /* (%si) -> 4 or (%di) -> 5 */
3527 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3529 i.rm.mode = mode_from_disp_size (i.types[op]);
3531 else /* i.base_reg and 32/64 bit mode */
3533 if (flag_code == CODE_64BIT
3534 && (i.types[op] & Disp))
3535 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3537 i.rm.regmem = i.base_reg->reg_num;
3538 if ((i.base_reg->reg_flags & RegRex) != 0)
3540 i.sib.base = i.base_reg->reg_num;
3541 /* x86-64 ignores REX prefix bit here to avoid decoder
3543 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3546 if (i.disp_operands == 0)
3548 fake_zero_displacement = 1;
3549 i.types[op] |= Disp8;
3552 else if (i.base_reg->reg_num == ESP_REG_NUM)
3556 i.sib.scale = i.log2_scale_factor;
3557 if (i.index_reg == 0)
3559 /* <disp>(%esp) becomes two byte modrm with no index
3560 register. We've already stored the code for esp
3561 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3562 Any base register besides %esp will not use the
3563 extra modrm byte. */
3564 i.sib.index = NO_INDEX_REGISTER;
3565 #if !SCALE1_WHEN_NO_INDEX
3566 /* Another case where we force the second modrm byte. */
3567 if (i.log2_scale_factor)
3568 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3573 i.sib.index = i.index_reg->reg_num;
3574 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3575 if ((i.index_reg->reg_flags & RegRex) != 0)
3580 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3581 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3584 i.rm.mode = mode_from_disp_size (i.types[op]);
3587 if (fake_zero_displacement)
3589 /* Fakes a zero displacement assuming that i.types[op]
3590 holds the correct displacement size. */
3593 assert (i.op[op].disps == 0);
3594 exp = &disp_expressions[i.disp_operands++];
3595 i.op[op].disps = exp;
3596 exp->X_op = O_constant;
3597 exp->X_add_number = 0;
3598 exp->X_add_symbol = (symbolS *) 0;
3599 exp->X_op_symbol = (symbolS *) 0;
3603 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3604 (if any) based on i.tm.extension_opcode. Again, we must be
3605 careful to make sure that segment/control/debug/test/MMX
3606 registers are coded into the i.rm.reg field. */
3611 & (Reg | RegMMX | RegXMM
3613 | Control | Debug | Test))
3616 & (Reg | RegMMX | RegXMM
3618 | Control | Debug | Test))
3621 /* If there is an extension opcode to put here, the register
3622 number must be put into the regmem field. */
3623 if (i.tm.extension_opcode != None)
3625 i.rm.regmem = i.op[op].regs->reg_num;
3626 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3631 i.rm.reg = i.op[op].regs->reg_num;
3632 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3636 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3637 must set it to 3 to indicate this is a register operand
3638 in the regmem field. */
3639 if (!i.mem_operands)
3643 /* Fill in i.rm.reg field with extension opcode (if any). */
3644 if (i.tm.extension_opcode != None)
3645 i.rm.reg = i.tm.extension_opcode;
3656 relax_substateT subtype;
3661 if (flag_code == CODE_16BIT)
3665 if (i.prefix[DATA_PREFIX] != 0)
3671 /* Pentium4 branch hints. */
3672 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3673 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3678 if (i.prefix[REX_PREFIX] != 0)
3684 if (i.prefixes != 0 && !intel_syntax)
3685 as_warn (_("skipping prefixes on this instruction"));
3687 /* It's always a symbol; End frag & setup for relax.
3688 Make sure there is enough room in this frag for the largest
3689 instruction we may generate in md_convert_frag. This is 2
3690 bytes for the opcode and room for the prefix and largest
3692 frag_grow (prefix + 2 + 4);
3693 /* Prefix and 1 opcode byte go in fr_fix. */
3694 p = frag_more (prefix + 1);
3695 if (i.prefix[DATA_PREFIX] != 0)
3696 *p++ = DATA_PREFIX_OPCODE;
3697 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3698 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3699 *p++ = i.prefix[SEG_PREFIX];
3700 if (i.prefix[REX_PREFIX] != 0)
3701 *p++ = i.prefix[REX_PREFIX];
3702 *p = i.tm.base_opcode;
3704 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3705 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3706 else if ((cpu_arch_flags & Cpu386) != 0)
3707 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3709 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3712 sym = i.op[0].disps->X_add_symbol;
3713 off = i.op[0].disps->X_add_number;
3715 if (i.op[0].disps->X_op != O_constant
3716 && i.op[0].disps->X_op != O_symbol)
3718 /* Handle complex expressions. */
3719 sym = make_expr_symbol (i.op[0].disps);
3723 /* 1 possible extra opcode + 4 byte displacement go in var part.
3724 Pass reloc in fr_var. */
3725 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3735 if (i.tm.opcode_modifier & JumpByte)
3737 /* This is a loop or jecxz type instruction. */
3739 if (i.prefix[ADDR_PREFIX] != 0)
3741 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3744 /* Pentium4 branch hints. */
3745 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3746 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3748 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3757 if (flag_code == CODE_16BIT)
3760 if (i.prefix[DATA_PREFIX] != 0)
3762 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3772 if (i.prefix[REX_PREFIX] != 0)
3774 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3778 if (i.prefixes != 0 && !intel_syntax)
3779 as_warn (_("skipping prefixes on this instruction"));
3781 p = frag_more (1 + size);
3782 *p++ = i.tm.base_opcode;
3784 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3785 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3787 /* All jumps handled here are signed, but don't use a signed limit
3788 check for 32 and 16 bit jumps as we want to allow wrap around at
3789 4G and 64k respectively. */
3791 fixP->fx_signed = 1;
3795 output_interseg_jump ()
3803 if (flag_code == CODE_16BIT)
3807 if (i.prefix[DATA_PREFIX] != 0)
3813 if (i.prefix[REX_PREFIX] != 0)
3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
3826 /* 1 opcode; 2 segment; offset */
3827 p = frag_more (prefix + 1 + 2 + size);
3829 if (i.prefix[DATA_PREFIX] != 0)
3830 *p++ = DATA_PREFIX_OPCODE;
3832 if (i.prefix[REX_PREFIX] != 0)
3833 *p++ = i.prefix[REX_PREFIX];
3835 *p++ = i.tm.base_opcode;
3836 if (i.op[1].imms->X_op == O_constant)
3838 offsetT n = i.op[1].imms->X_add_number;
3841 && !fits_in_unsigned_word (n)
3842 && !fits_in_signed_word (n))
3844 as_bad (_("16-bit jump out of range"));
3847 md_number_to_chars (p, n, size);
3850 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3851 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3852 if (i.op[0].imms->X_op != O_constant)
3853 as_bad (_("can't handle non absolute segment in `%s'"),
3855 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3861 fragS *insn_start_frag;
3862 offsetT insn_start_off;
3864 /* Tie dwarf2 debug info to the address at the start of the insn.
3865 We can't do this after the insn has been output as the current
3866 frag may have been closed off. eg. by frag_var. */
3867 dwarf2_emit_insn (0);
3869 insn_start_frag = frag_now;
3870 insn_start_off = frag_now_fix ();
3873 if (i.tm.opcode_modifier & Jump)
3875 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3877 else if (i.tm.opcode_modifier & JumpInterSegment)
3878 output_interseg_jump ();
3881 /* Output normal instructions here. */
3884 unsigned int prefix;
3886 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3887 Instructions have 3 bytes. We may use one more higher byte
3888 to specify a prefix the instruction requires. */
3889 if ((i.tm.cpu_flags & CpuMNI) != 0)
3891 if (i.tm.base_opcode & 0xff000000)
3893 prefix = (i.tm.base_opcode >> 24) & 0xff;
3897 else if ((i.tm.base_opcode & 0xff0000) != 0)
3899 prefix = (i.tm.base_opcode >> 16) & 0xff;
3900 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3903 if (prefix != REPE_PREFIX_OPCODE
3904 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3905 add_prefix (prefix);
3908 add_prefix (prefix);
3911 /* The prefix bytes. */
3913 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3919 md_number_to_chars (p, (valueT) *q, 1);
3923 /* Now the opcode; be careful about word order here! */
3924 if (fits_in_unsigned_byte (i.tm.base_opcode))
3926 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3930 if ((i.tm.cpu_flags & CpuMNI) != 0)
3933 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3938 /* Put out high byte first: can't use md_number_to_chars! */
3939 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3940 *p = i.tm.base_opcode & 0xff;
3943 /* Now the modrm byte and sib byte (if present). */
3944 if (i.tm.opcode_modifier & Modrm)
3947 md_number_to_chars (p,
3948 (valueT) (i.rm.regmem << 0
3952 /* If i.rm.regmem == ESP (4)
3953 && i.rm.mode != (Register mode)
3955 ==> need second modrm byte. */
3956 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3958 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3961 md_number_to_chars (p,
3962 (valueT) (i.sib.base << 0
3964 | i.sib.scale << 6),
3969 if (i.disp_operands)
3970 output_disp (insn_start_frag, insn_start_off);
3973 output_imm (insn_start_frag, insn_start_off);
3979 pi ("" /*line*/, &i);
3981 #endif /* DEBUG386 */
3985 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
3990 for (n = 0; n < i.operands; n++)
3992 if (i.types[n] & Disp)
3994 if (i.op[n].disps->X_op == O_constant)
4000 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4003 if (i.types[n] & Disp8)
4005 if (i.types[n] & Disp64)
4008 val = offset_in_range (i.op[n].disps->X_add_number,
4010 p = frag_more (size);
4011 md_number_to_chars (p, val, size);
4015 enum bfd_reloc_code_real reloc_type;
4018 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4020 /* The PC relative address is computed relative
4021 to the instruction boundary, so in case immediate
4022 fields follows, we need to adjust the value. */
4023 if (pcrel && i.imm_operands)
4028 for (n1 = 0; n1 < i.operands; n1++)
4029 if (i.types[n1] & Imm)
4031 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4034 if (i.types[n1] & (Imm8 | Imm8S))
4036 if (i.types[n1] & Imm64)
4041 /* We should find the immediate. */
4042 if (n1 == i.operands)
4044 i.op[n].disps->X_add_number -= imm_size;
4047 if (i.types[n] & Disp32S)
4050 if (i.types[n] & (Disp16 | Disp64))
4053 if (i.types[n] & Disp64)
4057 p = frag_more (size);
4058 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4060 && GOT_symbol == i.op[n].disps->X_add_symbol
4061 && (((reloc_type == BFD_RELOC_32
4062 || reloc_type == BFD_RELOC_X86_64_32S
4063 || (reloc_type == BFD_RELOC_64
4065 && (i.op[n].disps->X_op == O_symbol
4066 || (i.op[n].disps->X_op == O_add
4067 && ((symbol_get_value_expression
4068 (i.op[n].disps->X_op_symbol)->X_op)
4070 || reloc_type == BFD_RELOC_32_PCREL))
4074 if (insn_start_frag == frag_now)
4075 add = (p - frag_now->fr_literal) - insn_start_off;
4080 add = insn_start_frag->fr_fix - insn_start_off;
4081 for (fr = insn_start_frag->fr_next;
4082 fr && fr != frag_now; fr = fr->fr_next)
4084 add += p - frag_now->fr_literal;
4089 reloc_type = BFD_RELOC_386_GOTPC;
4090 i.op[n].imms->X_add_number += add;
4092 else if (reloc_type == BFD_RELOC_64)
4093 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4095 /* Don't do the adjustment for x86-64, as there
4096 the pcrel addressing is relative to the _next_
4097 insn, and that is taken care of in other code. */
4098 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4100 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4101 i.op[n].disps, pcrel, reloc_type);
4108 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4113 for (n = 0; n < i.operands; n++)
4115 if (i.types[n] & Imm)
4117 if (i.op[n].imms->X_op == O_constant)
4123 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4126 if (i.types[n] & (Imm8 | Imm8S))
4128 else if (i.types[n] & Imm64)
4131 val = offset_in_range (i.op[n].imms->X_add_number,
4133 p = frag_more (size);
4134 md_number_to_chars (p, val, size);
4138 /* Not absolute_section.
4139 Need a 32-bit fixup (don't support 8bit
4140 non-absolute imms). Try to support other
4142 enum bfd_reloc_code_real reloc_type;
4146 if ((i.types[n] & (Imm32S))
4147 && (i.suffix == QWORD_MNEM_SUFFIX
4148 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4150 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4153 if (i.types[n] & (Imm8 | Imm8S))
4155 if (i.types[n] & Imm64)
4159 p = frag_more (size);
4160 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4162 /* This is tough to explain. We end up with this one if we
4163 * have operands that look like
4164 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4165 * obtain the absolute address of the GOT, and it is strongly
4166 * preferable from a performance point of view to avoid using
4167 * a runtime relocation for this. The actual sequence of
4168 * instructions often look something like:
4173 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4175 * The call and pop essentially return the absolute address
4176 * of the label .L66 and store it in %ebx. The linker itself
4177 * will ultimately change the first operand of the addl so
4178 * that %ebx points to the GOT, but to keep things simple, the
4179 * .o file must have this operand set so that it generates not
4180 * the absolute address of .L66, but the absolute address of
4181 * itself. This allows the linker itself simply treat a GOTPC
4182 * relocation as asking for a pcrel offset to the GOT to be
4183 * added in, and the addend of the relocation is stored in the
4184 * operand field for the instruction itself.
4186 * Our job here is to fix the operand so that it would add
4187 * the correct offset so that %ebx would point to itself. The
4188 * thing that is tricky is that .-.L66 will point to the
4189 * beginning of the instruction, so we need to further modify
4190 * the operand so that it will point to itself. There are
4191 * other cases where you have something like:
4193 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4195 * and here no correction would be required. Internally in
4196 * the assembler we treat operands of this form as not being
4197 * pcrel since the '.' is explicitly mentioned, and I wonder
4198 * whether it would simplify matters to do it this way. Who
4199 * knows. In earlier versions of the PIC patches, the
4200 * pcrel_adjust field was used to store the correction, but
4201 * since the expression is not pcrel, I felt it would be
4202 * confusing to do it this way. */
4204 if ((reloc_type == BFD_RELOC_32
4205 || reloc_type == BFD_RELOC_X86_64_32S
4206 || reloc_type == BFD_RELOC_64)
4208 && GOT_symbol == i.op[n].imms->X_add_symbol
4209 && (i.op[n].imms->X_op == O_symbol
4210 || (i.op[n].imms->X_op == O_add
4211 && ((symbol_get_value_expression
4212 (i.op[n].imms->X_op_symbol)->X_op)
4217 if (insn_start_frag == frag_now)
4218 add = (p - frag_now->fr_literal) - insn_start_off;
4223 add = insn_start_frag->fr_fix - insn_start_off;
4224 for (fr = insn_start_frag->fr_next;
4225 fr && fr != frag_now; fr = fr->fr_next)
4227 add += p - frag_now->fr_literal;
4231 reloc_type = BFD_RELOC_386_GOTPC;
4233 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4235 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4236 i.op[n].imms->X_add_number += add;
4238 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4239 i.op[n].imms, 0, reloc_type);
4245 /* x86_cons_fix_new is called via the expression parsing code when a
4246 reloc is needed. We use this hook to get the correct .got reloc. */
4247 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4248 static int cons_sign = -1;
4251 x86_cons_fix_new (fragS *frag,
4256 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4258 got_reloc = NO_RELOC;
4261 if (exp->X_op == O_secrel)
4263 exp->X_op = O_symbol;
4264 r = BFD_RELOC_32_SECREL;
4268 fix_new_exp (frag, off, len, exp, 0, r);
4271 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4272 # define lex_got(reloc, adjust, types) NULL
4274 /* Parse operands of the form
4275 <symbol>@GOTOFF+<nnn>
4276 and similar .plt or .got references.
4278 If we find one, set up the correct relocation in RELOC and copy the
4279 input string, minus the `@GOTOFF' into a malloc'd buffer for
4280 parsing by the calling routine. Return this buffer, and if ADJUST
4281 is non-null set it to the length of the string we removed from the
4282 input line. Otherwise return NULL. */
4284 lex_got (enum bfd_reloc_code_real *reloc,
4286 unsigned int *types)
4288 /* Some of the relocations depend on the size of what field is to
4289 be relocated. But in our callers i386_immediate and i386_displacement
4290 we don't yet know the operand size (this will be set by insn
4291 matching). Hence we record the word32 relocation here,
4292 and adjust the reloc according to the real size in reloc(). */
4293 static const struct {
4295 const enum bfd_reloc_code_real rel[2];
4296 const unsigned int types64;
4298 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4299 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4300 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4301 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4302 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4303 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4304 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4305 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4306 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4307 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4308 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4309 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4310 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4311 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4312 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4313 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4314 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4322 for (cp = input_line_pointer; *cp != '@'; cp++)
4323 if (is_end_of_line[(unsigned char) *cp])
4326 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4330 len = strlen (gotrel[j].str);
4331 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4333 if (gotrel[j].rel[object_64bit] != 0)
4336 char *tmpbuf, *past_reloc;
4338 *reloc = gotrel[j].rel[object_64bit];
4344 if (flag_code != CODE_64BIT)
4345 *types = Imm32|Disp32;
4347 *types = gotrel[j].types64;
4350 if (GOT_symbol == NULL)
4351 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4353 /* Replace the relocation token with ' ', so that
4354 errors like foo@GOTOFF1 will be detected. */
4356 /* The length of the first part of our input line. */
4357 first = cp - input_line_pointer;
4359 /* The second part goes from after the reloc token until
4360 (and including) an end_of_line char. Don't use strlen
4361 here as the end_of_line char may not be a NUL. */
4362 past_reloc = cp + 1 + len;
4363 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4365 second = cp - past_reloc;
4367 /* Allocate and copy string. The trailing NUL shouldn't
4368 be necessary, but be safe. */
4369 tmpbuf = xmalloc (first + second + 2);
4370 memcpy (tmpbuf, input_line_pointer, first);
4371 tmpbuf[first] = ' ';
4372 memcpy (tmpbuf + first + 1, past_reloc, second);
4373 tmpbuf[first + second + 1] = '\0';
4377 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4378 gotrel[j].str, 1 << (5 + object_64bit));
4383 /* Might be a symbol version string. Don't as_bad here. */
4388 x86_cons (exp, size)
4392 if (size == 4 || (object_64bit && size == 8))
4394 /* Handle @GOTOFF and the like in an expression. */
4396 char *gotfree_input_line;
4399 save = input_line_pointer;
4400 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4401 if (gotfree_input_line)
4402 input_line_pointer = gotfree_input_line;
4406 if (gotfree_input_line)
4408 /* expression () has merrily parsed up to the end of line,
4409 or a comma - in the wrong buffer. Transfer how far
4410 input_line_pointer has moved to the right buffer. */
4411 input_line_pointer = (save
4412 + (input_line_pointer - gotfree_input_line)
4414 free (gotfree_input_line);
4422 static void signed_cons (int size)
4424 if (flag_code == CODE_64BIT)
4432 pe_directive_secrel (dummy)
4433 int dummy ATTRIBUTE_UNUSED;
4440 if (exp.X_op == O_symbol)
4441 exp.X_op = O_secrel;
4443 emit_expr (&exp, 4);
4445 while (*input_line_pointer++ == ',');
4447 input_line_pointer--;
4448 demand_empty_rest_of_line ();
4452 static int i386_immediate PARAMS ((char *));
4455 i386_immediate (imm_start)
4458 char *save_input_line_pointer;
4459 char *gotfree_input_line;
4462 unsigned int types = ~0U;
4464 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4466 as_bad (_("only 1 or 2 immediate operands are allowed"));
4470 exp = &im_expressions[i.imm_operands++];
4471 i.op[this_operand].imms = exp;
4473 if (is_space_char (*imm_start))
4476 save_input_line_pointer = input_line_pointer;
4477 input_line_pointer = imm_start;
4479 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4480 if (gotfree_input_line)
4481 input_line_pointer = gotfree_input_line;
4483 exp_seg = expression (exp);
4486 if (*input_line_pointer)
4487 as_bad (_("junk `%s' after expression"), input_line_pointer);
4489 input_line_pointer = save_input_line_pointer;
4490 if (gotfree_input_line)
4491 free (gotfree_input_line);
4493 if (exp->X_op == O_absent || exp->X_op == O_big)
4495 /* Missing or bad expr becomes absolute 0. */
4496 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4498 exp->X_op = O_constant;
4499 exp->X_add_number = 0;
4500 exp->X_add_symbol = (symbolS *) 0;
4501 exp->X_op_symbol = (symbolS *) 0;
4503 else if (exp->X_op == O_constant)
4505 /* Size it properly later. */
4506 i.types[this_operand] |= Imm64;
4507 /* If BFD64, sign extend val. */
4508 if (!use_rela_relocations)
4509 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4510 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4512 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4513 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4514 && exp_seg != absolute_section
4515 && exp_seg != text_section
4516 && exp_seg != data_section
4517 && exp_seg != bss_section
4518 && exp_seg != undefined_section
4519 && !bfd_is_com_section (exp_seg))
4521 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4525 else if (!intel_syntax && exp->X_op == O_register)
4527 as_bad (_("illegal immediate register operand %s"), imm_start);
4532 /* This is an address. The size of the address will be
4533 determined later, depending on destination register,
4534 suffix, or the default for the section. */
4535 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4536 i.types[this_operand] &= types;
4542 static char *i386_scale PARAMS ((char *));
4549 char *save = input_line_pointer;
4551 input_line_pointer = scale;
4552 val = get_absolute_expression ();
4557 i.log2_scale_factor = 0;
4560 i.log2_scale_factor = 1;
4563 i.log2_scale_factor = 2;
4566 i.log2_scale_factor = 3;
4570 char sep = *input_line_pointer;
4572 *input_line_pointer = '\0';
4573 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4575 *input_line_pointer = sep;
4576 input_line_pointer = save;
4580 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4582 as_warn (_("scale factor of %d without an index register"),
4583 1 << i.log2_scale_factor);
4584 #if SCALE1_WHEN_NO_INDEX
4585 i.log2_scale_factor = 0;
4588 scale = input_line_pointer;
4589 input_line_pointer = save;
4593 static int i386_displacement PARAMS ((char *, char *));
4596 i386_displacement (disp_start, disp_end)
4602 char *save_input_line_pointer;
4603 char *gotfree_input_line;
4604 int bigdisp, override;
4605 unsigned int types = Disp;
4607 if ((i.types[this_operand] & JumpAbsolute)
4608 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4611 override = (i.prefix[ADDR_PREFIX] != 0);
4615 /* For PC-relative branches, the width of the displacement
4616 is dependent upon data size, not address size. */
4618 override = (i.prefix[DATA_PREFIX] != 0);
4620 if (flag_code == CODE_64BIT)
4623 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4625 : Disp32S | Disp32);
4627 bigdisp = Disp64 | Disp32S | Disp32;
4634 override = (i.suffix == (flag_code != CODE_16BIT
4636 : LONG_MNEM_SUFFIX));
4639 if ((flag_code == CODE_16BIT) ^ override)
4642 i.types[this_operand] |= bigdisp;
4644 exp = &disp_expressions[i.disp_operands];
4645 i.op[this_operand].disps = exp;
4647 save_input_line_pointer = input_line_pointer;
4648 input_line_pointer = disp_start;
4649 END_STRING_AND_SAVE (disp_end);
4651 #ifndef GCC_ASM_O_HACK
4652 #define GCC_ASM_O_HACK 0
4655 END_STRING_AND_SAVE (disp_end + 1);
4656 if ((i.types[this_operand] & BaseIndex) != 0
4657 && displacement_string_end[-1] == '+')
4659 /* This hack is to avoid a warning when using the "o"
4660 constraint within gcc asm statements.
4663 #define _set_tssldt_desc(n,addr,limit,type) \
4664 __asm__ __volatile__ ( \
4666 "movw %w1,2+%0\n\t" \
4668 "movb %b1,4+%0\n\t" \
4669 "movb %4,5+%0\n\t" \
4670 "movb $0,6+%0\n\t" \
4671 "movb %h1,7+%0\n\t" \
4673 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4675 This works great except that the output assembler ends
4676 up looking a bit weird if it turns out that there is
4677 no offset. You end up producing code that looks like:
4690 So here we provide the missing zero. */
4692 *displacement_string_end = '0';
4695 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4696 if (gotfree_input_line)
4697 input_line_pointer = gotfree_input_line;
4699 exp_seg = expression (exp);
4702 if (*input_line_pointer)
4703 as_bad (_("junk `%s' after expression"), input_line_pointer);
4705 RESTORE_END_STRING (disp_end + 1);
4707 RESTORE_END_STRING (disp_end);
4708 input_line_pointer = save_input_line_pointer;
4709 if (gotfree_input_line)
4710 free (gotfree_input_line);
4712 /* We do this to make sure that the section symbol is in
4713 the symbol table. We will ultimately change the relocation
4714 to be relative to the beginning of the section. */
4715 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4716 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4717 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4719 if (exp->X_op != O_symbol)
4721 as_bad (_("bad expression used with @%s"),
4722 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4728 if (S_IS_LOCAL (exp->X_add_symbol)
4729 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4730 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4731 exp->X_op = O_subtract;
4732 exp->X_op_symbol = GOT_symbol;
4733 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4734 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4735 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4736 i.reloc[this_operand] = BFD_RELOC_64;
4738 i.reloc[this_operand] = BFD_RELOC_32;
4741 if (exp->X_op == O_absent || exp->X_op == O_big)
4743 /* Missing or bad expr becomes absolute 0. */
4744 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4746 exp->X_op = O_constant;
4747 exp->X_add_number = 0;
4748 exp->X_add_symbol = (symbolS *) 0;
4749 exp->X_op_symbol = (symbolS *) 0;
4752 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4753 if (exp->X_op != O_constant
4754 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4755 && exp_seg != absolute_section
4756 && exp_seg != text_section
4757 && exp_seg != data_section
4758 && exp_seg != bss_section
4759 && exp_seg != undefined_section
4760 && !bfd_is_com_section (exp_seg))
4762 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4767 if (!(i.types[this_operand] & ~Disp))
4768 i.types[this_operand] &= types;
4773 static int i386_index_check PARAMS ((const char *));
4775 /* Make sure the memory operand we've been dealt is valid.
4776 Return 1 on success, 0 on a failure. */
4779 i386_index_check (operand_string)
4780 const char *operand_string;
4783 #if INFER_ADDR_PREFIX
4789 if ((current_templates->start->cpu_flags & CpuSVME)
4790 && current_templates->end[-1].operand_types[0] == AnyMem)
4792 /* Memory operands of SVME insns are special in that they only allow
4793 rAX as their memory address and ignore any segment override. */
4796 /* SKINIT is even more restrictive: it always requires EAX. */
4797 if (strcmp (current_templates->start->name, "skinit") == 0)
4799 else if (flag_code == CODE_64BIT)
4800 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4802 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4806 || !(i.base_reg->reg_type & Acc)
4807 || !(i.base_reg->reg_type & RegXX)
4809 || (i.types[0] & Disp))
4812 else if (flag_code == CODE_64BIT)
4814 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4817 && ((i.base_reg->reg_type & RegXX) == 0)
4818 && (i.base_reg->reg_type != BaseIndex
4821 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4822 != (RegXX | BaseIndex))))
4827 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4831 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4832 != (Reg16 | BaseIndex)))
4834 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4835 != (Reg16 | BaseIndex))
4837 && i.base_reg->reg_num < 6
4838 && i.index_reg->reg_num >= 6
4839 && i.log2_scale_factor == 0))))
4846 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4848 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4849 != (Reg32 | BaseIndex))))
4855 #if INFER_ADDR_PREFIX
4856 if (i.prefix[ADDR_PREFIX] == 0)
4858 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4860 /* Change the size of any displacement too. At most one of
4861 Disp16 or Disp32 is set.
4862 FIXME. There doesn't seem to be any real need for separate
4863 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4864 Removing them would probably clean up the code quite a lot. */
4865 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4866 i.types[this_operand] ^= (Disp16 | Disp32);
4871 as_bad (_("`%s' is not a valid base/index expression"),
4875 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4877 flag_code_names[flag_code]);
4882 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4886 i386_operand (operand_string)
4887 char *operand_string;
4891 char *op_string = operand_string;
4893 if (is_space_char (*op_string))
4896 /* We check for an absolute prefix (differentiating,
4897 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4898 if (*op_string == ABSOLUTE_PREFIX)
4901 if (is_space_char (*op_string))
4903 i.types[this_operand] |= JumpAbsolute;
4906 /* Check if operand is a register. */
4907 if ((r = parse_register (op_string, &end_op)) != NULL)
4909 /* Check for a segment override by searching for ':' after a
4910 segment register. */
4912 if (is_space_char (*op_string))
4914 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4919 i.seg[i.mem_operands] = &es;
4922 i.seg[i.mem_operands] = &cs;
4925 i.seg[i.mem_operands] = &ss;
4928 i.seg[i.mem_operands] = &ds;
4931 i.seg[i.mem_operands] = &fs;
4934 i.seg[i.mem_operands] = &gs;
4938 /* Skip the ':' and whitespace. */
4940 if (is_space_char (*op_string))
4943 if (!is_digit_char (*op_string)
4944 && !is_identifier_char (*op_string)
4945 && *op_string != '('
4946 && *op_string != ABSOLUTE_PREFIX)
4948 as_bad (_("bad memory operand `%s'"), op_string);
4951 /* Handle case of %es:*foo. */
4952 if (*op_string == ABSOLUTE_PREFIX)
4955 if (is_space_char (*op_string))
4957 i.types[this_operand] |= JumpAbsolute;
4959 goto do_memory_reference;
4963 as_bad (_("junk `%s' after register"), op_string);
4966 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4967 i.op[this_operand].regs = r;
4970 else if (*op_string == REGISTER_PREFIX)
4972 as_bad (_("bad register name `%s'"), op_string);
4975 else if (*op_string == IMMEDIATE_PREFIX)
4978 if (i.types[this_operand] & JumpAbsolute)
4980 as_bad (_("immediate operand illegal with absolute jump"));
4983 if (!i386_immediate (op_string))
4986 else if (is_digit_char (*op_string)
4987 || is_identifier_char (*op_string)
4988 || *op_string == '(')
4990 /* This is a memory reference of some sort. */
4993 /* Start and end of displacement string expression (if found). */
4994 char *displacement_string_start;
4995 char *displacement_string_end;
4997 do_memory_reference:
4998 if ((i.mem_operands == 1
4999 && (current_templates->start->opcode_modifier & IsString) == 0)
5000 || i.mem_operands == 2)
5002 as_bad (_("too many memory references for `%s'"),
5003 current_templates->start->name);
5007 /* Check for base index form. We detect the base index form by
5008 looking for an ')' at the end of the operand, searching
5009 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5011 base_string = op_string + strlen (op_string);
5014 if (is_space_char (*base_string))
5017 /* If we only have a displacement, set-up for it to be parsed later. */
5018 displacement_string_start = op_string;
5019 displacement_string_end = base_string + 1;
5021 if (*base_string == ')')
5024 unsigned int parens_balanced = 1;
5025 /* We've already checked that the number of left & right ()'s are
5026 equal, so this loop will not be infinite. */
5030 if (*base_string == ')')
5032 if (*base_string == '(')
5035 while (parens_balanced);
5037 temp_string = base_string;
5039 /* Skip past '(' and whitespace. */
5041 if (is_space_char (*base_string))
5044 if (*base_string == ','
5045 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
5047 displacement_string_end = temp_string;
5049 i.types[this_operand] |= BaseIndex;
5053 base_string = end_op;
5054 if (is_space_char (*base_string))
5058 /* There may be an index reg or scale factor here. */
5059 if (*base_string == ',')
5062 if (is_space_char (*base_string))
5065 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5067 base_string = end_op;
5068 if (is_space_char (*base_string))
5070 if (*base_string == ',')
5073 if (is_space_char (*base_string))
5076 else if (*base_string != ')')
5078 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5083 else if (*base_string == REGISTER_PREFIX)
5085 as_bad (_("bad register name `%s'"), base_string);
5089 /* Check for scale factor. */
5090 if (*base_string != ')')
5092 char *end_scale = i386_scale (base_string);
5097 base_string = end_scale;
5098 if (is_space_char (*base_string))
5100 if (*base_string != ')')
5102 as_bad (_("expecting `)' after scale factor in `%s'"),
5107 else if (!i.index_reg)
5109 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5114 else if (*base_string != ')')
5116 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5121 else if (*base_string == REGISTER_PREFIX)
5123 as_bad (_("bad register name `%s'"), base_string);
5128 /* If there's an expression beginning the operand, parse it,
5129 assuming displacement_string_start and
5130 displacement_string_end are meaningful. */
5131 if (displacement_string_start != displacement_string_end)
5133 if (!i386_displacement (displacement_string_start,
5134 displacement_string_end))
5138 /* Special case for (%dx) while doing input/output op. */
5140 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5142 && i.log2_scale_factor == 0
5143 && i.seg[i.mem_operands] == 0
5144 && (i.types[this_operand] & Disp) == 0)
5146 i.types[this_operand] = InOutPortReg;
5150 if (i386_index_check (operand_string) == 0)
5156 /* It's not a memory operand; argh! */
5157 as_bad (_("invalid char %s beginning operand %d `%s'"),
5158 output_invalid (*op_string),
5163 return 1; /* Normal return. */
5166 /* md_estimate_size_before_relax()
5168 Called just before relax() for rs_machine_dependent frags. The x86
5169 assembler uses these frags to handle variable size jump
5172 Any symbol that is now undefined will not become defined.
5173 Return the correct fr_subtype in the frag.
5174 Return the initial "guess for variable size of frag" to caller.
5175 The guess is actually the growth beyond the fixed part. Whatever
5176 we do to grow the fixed or variable part contributes to our
5180 md_estimate_size_before_relax (fragP, segment)
5184 /* We've already got fragP->fr_subtype right; all we have to do is
5185 check for un-relaxable symbols. On an ELF system, we can't relax
5186 an externally visible symbol, because it may be overridden by a
5188 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5191 && (S_IS_EXTERNAL (fragP->fr_symbol)
5192 || S_IS_WEAK (fragP->fr_symbol)))
5196 /* Symbol is undefined in this segment, or we need to keep a
5197 reloc so that weak symbols can be overridden. */
5198 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5199 enum bfd_reloc_code_real reloc_type;
5200 unsigned char *opcode;
5203 if (fragP->fr_var != NO_RELOC)
5204 reloc_type = fragP->fr_var;
5206 reloc_type = BFD_RELOC_16_PCREL;
5208 reloc_type = BFD_RELOC_32_PCREL;
5210 old_fr_fix = fragP->fr_fix;
5211 opcode = (unsigned char *) fragP->fr_opcode;
5213 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5216 /* Make jmp (0xeb) a (d)word displacement jump. */
5218 fragP->fr_fix += size;
5219 fix_new (fragP, old_fr_fix, size,
5221 fragP->fr_offset, 1,
5227 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5229 /* Negate the condition, and branch past an
5230 unconditional jump. */
5233 /* Insert an unconditional jump. */
5235 /* We added two extra opcode bytes, and have a two byte
5237 fragP->fr_fix += 2 + 2;
5238 fix_new (fragP, old_fr_fix + 2, 2,
5240 fragP->fr_offset, 1,
5247 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5252 fixP = fix_new (fragP, old_fr_fix, 1,
5254 fragP->fr_offset, 1,
5256 fixP->fx_signed = 1;
5260 /* This changes the byte-displacement jump 0x7N
5261 to the (d)word-displacement jump 0x0f,0x8N. */
5262 opcode[1] = opcode[0] + 0x10;
5263 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5264 /* We've added an opcode byte. */
5265 fragP->fr_fix += 1 + size;
5266 fix_new (fragP, old_fr_fix + 1, size,
5268 fragP->fr_offset, 1,
5273 BAD_CASE (fragP->fr_subtype);
5277 return fragP->fr_fix - old_fr_fix;
5280 /* Guess size depending on current relax state. Initially the relax
5281 state will correspond to a short jump and we return 1, because
5282 the variable part of the frag (the branch offset) is one byte
5283 long. However, we can relax a section more than once and in that
5284 case we must either set fr_subtype back to the unrelaxed state,
5285 or return the value for the appropriate branch. */
5286 return md_relax_table[fragP->fr_subtype].rlx_length;
5289 /* Called after relax() is finished.
5291 In: Address of frag.
5292 fr_type == rs_machine_dependent.
5293 fr_subtype is what the address relaxed to.
5295 Out: Any fixSs and constants are set up.
5296 Caller will turn frag into a ".space 0". */
5299 md_convert_frag (abfd, sec, fragP)
5300 bfd *abfd ATTRIBUTE_UNUSED;
5301 segT sec ATTRIBUTE_UNUSED;
5304 unsigned char *opcode;
5305 unsigned char *where_to_put_displacement = NULL;
5306 offsetT target_address;
5307 offsetT opcode_address;
5308 unsigned int extension = 0;
5309 offsetT displacement_from_opcode_start;
5311 opcode = (unsigned char *) fragP->fr_opcode;
5313 /* Address we want to reach in file space. */
5314 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5316 /* Address opcode resides at in file space. */
5317 opcode_address = fragP->fr_address + fragP->fr_fix;
5319 /* Displacement from opcode start to fill into instruction. */
5320 displacement_from_opcode_start = target_address - opcode_address;
5322 if ((fragP->fr_subtype & BIG) == 0)
5324 /* Don't have to change opcode. */
5325 extension = 1; /* 1 opcode + 1 displacement */
5326 where_to_put_displacement = &opcode[1];
5330 if (no_cond_jump_promotion
5331 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5332 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5334 switch (fragP->fr_subtype)
5336 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5337 extension = 4; /* 1 opcode + 4 displacement */
5339 where_to_put_displacement = &opcode[1];
5342 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5343 extension = 2; /* 1 opcode + 2 displacement */
5345 where_to_put_displacement = &opcode[1];
5348 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5349 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5350 extension = 5; /* 2 opcode + 4 displacement */
5351 opcode[1] = opcode[0] + 0x10;
5352 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5353 where_to_put_displacement = &opcode[2];
5356 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5357 extension = 3; /* 2 opcode + 2 displacement */
5358 opcode[1] = opcode[0] + 0x10;
5359 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5360 where_to_put_displacement = &opcode[2];
5363 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5368 where_to_put_displacement = &opcode[3];
5372 BAD_CASE (fragP->fr_subtype);
5377 /* If size if less then four we are sure that the operand fits,
5378 but if it's 4, then it could be that the displacement is larger
5380 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5382 && ((addressT) (displacement_from_opcode_start - extension
5383 + ((addressT) 1 << 31))
5384 > (((addressT) 2 << 31) - 1)))
5386 as_bad_where (fragP->fr_file, fragP->fr_line,
5387 _("jump target out of range"));
5388 /* Make us emit 0. */
5389 displacement_from_opcode_start = extension;
5391 /* Now put displacement after opcode. */
5392 md_number_to_chars ((char *) where_to_put_displacement,
5393 (valueT) (displacement_from_opcode_start - extension),
5394 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5395 fragP->fr_fix += extension;
5398 /* Size of byte displacement jmp. */
5399 int md_short_jump_size = 2;
5401 /* Size of dword displacement jmp. */
5402 int md_long_jump_size = 5;
5405 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5407 addressT from_addr, to_addr;
5408 fragS *frag ATTRIBUTE_UNUSED;
5409 symbolS *to_symbol ATTRIBUTE_UNUSED;
5413 offset = to_addr - (from_addr + 2);
5414 /* Opcode for byte-disp jump. */
5415 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5416 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5420 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5422 addressT from_addr, to_addr;
5423 fragS *frag ATTRIBUTE_UNUSED;
5424 symbolS *to_symbol ATTRIBUTE_UNUSED;
5428 offset = to_addr - (from_addr + 5);
5429 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5430 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5433 /* Apply a fixup (fixS) to segment data, once it has been determined
5434 by our caller that we have all the info we need to fix it up.
5436 On the 386, immediates, displacements, and data pointers are all in
5437 the same (little-endian) format, so we don't need to care about which
5441 md_apply_fix (fixP, valP, seg)
5442 /* The fix we're to put in. */
5444 /* Pointer to the value of the bits. */
5446 /* Segment fix is from. */
5447 segT seg ATTRIBUTE_UNUSED;
5449 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5450 valueT value = *valP;
5452 #if !defined (TE_Mach)
5455 switch (fixP->fx_r_type)
5461 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5464 case BFD_RELOC_X86_64_32S:
5465 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5468 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5471 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5476 if (fixP->fx_addsy != NULL
5477 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5478 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5479 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5480 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5481 && !use_rela_relocations)
5483 /* This is a hack. There should be a better way to handle this.
5484 This covers for the fact that bfd_install_relocation will
5485 subtract the current location (for partial_inplace, PC relative
5486 relocations); see more below. */
5490 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5493 value += fixP->fx_where + fixP->fx_frag->fr_address;
5495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5498 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5501 || (symbol_section_p (fixP->fx_addsy)
5502 && sym_seg != absolute_section))
5503 && !generic_force_reloc (fixP))
5505 /* Yes, we add the values in twice. This is because
5506 bfd_install_relocation subtracts them out again. I think
5507 bfd_install_relocation is broken, but I don't dare change
5509 value += fixP->fx_where + fixP->fx_frag->fr_address;
5513 #if defined (OBJ_COFF) && defined (TE_PE)
5514 /* For some reason, the PE format does not store a
5515 section address offset for a PC relative symbol. */
5516 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5517 || S_IS_WEAK (fixP->fx_addsy))
5518 value += md_pcrel_from (fixP);
5522 /* Fix a few things - the dynamic linker expects certain values here,
5523 and we must not disappoint it. */
5524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5525 if (IS_ELF && fixP->fx_addsy)
5526 switch (fixP->fx_r_type)
5528 case BFD_RELOC_386_PLT32:
5529 case BFD_RELOC_X86_64_PLT32:
5530 /* Make the jump instruction point to the address of the operand. At
5531 runtime we merely add the offset to the actual PLT entry. */
5535 case BFD_RELOC_386_TLS_GD:
5536 case BFD_RELOC_386_TLS_LDM:
5537 case BFD_RELOC_386_TLS_IE_32:
5538 case BFD_RELOC_386_TLS_IE:
5539 case BFD_RELOC_386_TLS_GOTIE:
5540 case BFD_RELOC_386_TLS_GOTDESC:
5541 case BFD_RELOC_X86_64_TLSGD:
5542 case BFD_RELOC_X86_64_TLSLD:
5543 case BFD_RELOC_X86_64_GOTTPOFF:
5544 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5545 value = 0; /* Fully resolved at runtime. No addend. */
5547 case BFD_RELOC_386_TLS_LE:
5548 case BFD_RELOC_386_TLS_LDO_32:
5549 case BFD_RELOC_386_TLS_LE_32:
5550 case BFD_RELOC_X86_64_DTPOFF32:
5551 case BFD_RELOC_X86_64_DTPOFF64:
5552 case BFD_RELOC_X86_64_TPOFF32:
5553 case BFD_RELOC_X86_64_TPOFF64:
5554 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5557 case BFD_RELOC_386_TLS_DESC_CALL:
5558 case BFD_RELOC_X86_64_TLSDESC_CALL:
5559 value = 0; /* Fully resolved at runtime. No addend. */
5560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5564 case BFD_RELOC_386_GOT32:
5565 case BFD_RELOC_X86_64_GOT32:
5566 value = 0; /* Fully resolved at runtime. No addend. */
5569 case BFD_RELOC_VTABLE_INHERIT:
5570 case BFD_RELOC_VTABLE_ENTRY:
5577 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5579 #endif /* !defined (TE_Mach) */
5581 /* Are we finished with this relocation now? */
5582 if (fixP->fx_addsy == NULL)
5584 else if (use_rela_relocations)
5586 fixP->fx_no_overflow = 1;
5587 /* Remember value for tc_gen_reloc. */
5588 fixP->fx_addnumber = value;
5592 md_number_to_chars (p, value, fixP->fx_size);
5595 #define MAX_LITTLENUMS 6
5597 /* Turn the string pointed to by litP into a floating point constant
5598 of type TYPE, and emit the appropriate bytes. The number of
5599 LITTLENUMS emitted is stored in *SIZEP. An error message is
5600 returned, or NULL on OK. */
5603 md_atof (type, litP, sizeP)
5609 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5610 LITTLENUM_TYPE *wordP;
5632 return _("Bad call to md_atof ()");
5634 t = atof_ieee (input_line_pointer, type, words);
5636 input_line_pointer = t;
5638 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5639 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5640 the bigendian 386. */
5641 for (wordP = words + prec - 1; prec--;)
5643 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5644 litP += sizeof (LITTLENUM_TYPE);
5649 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5656 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5659 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5660 "(0x%x)", (unsigned char) c);
5661 return output_invalid_buf;
5664 /* REG_STRING starts *before* REGISTER_PREFIX. */
5666 static const reg_entry *
5667 parse_real_register (char *reg_string, char **end_op)
5669 char *s = reg_string;
5671 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5674 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5675 if (*s == REGISTER_PREFIX)
5678 if (is_space_char (*s))
5682 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5684 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5685 return (const reg_entry *) NULL;
5689 /* For naked regs, make sure that we are not dealing with an identifier.
5690 This prevents confusing an identifier like `eax_var' with register
5692 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5693 return (const reg_entry *) NULL;
5697 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5699 /* Handle floating point regs, allowing spaces in the (i) part. */
5700 if (r == i386_regtab /* %st is first entry of table */)
5702 if (is_space_char (*s))
5707 if (is_space_char (*s))
5709 if (*s >= '0' && *s <= '7')
5711 r = &i386_float_regtab[*s - '0'];
5713 if (is_space_char (*s))
5721 /* We have "%st(" then garbage. */
5722 return (const reg_entry *) NULL;
5727 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5728 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5729 && flag_code != CODE_64BIT)
5730 return (const reg_entry *) NULL;
5735 /* REG_STRING starts *before* REGISTER_PREFIX. */
5737 static const reg_entry *
5738 parse_register (char *reg_string, char **end_op)
5742 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5743 r = parse_real_register (reg_string, end_op);
5748 char *save = input_line_pointer;
5752 input_line_pointer = reg_string;
5753 c = get_symbol_end ();
5754 symbolP = symbol_find (reg_string);
5755 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5757 const expressionS *e = symbol_get_value_expression (symbolP);
5759 know (e->X_op == O_register);
5760 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5761 r = i386_regtab + e->X_add_number;
5762 *end_op = input_line_pointer;
5764 *input_line_pointer = c;
5765 input_line_pointer = save;
5771 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5774 char *end = input_line_pointer;
5777 r = parse_register (name, &input_line_pointer);
5778 if (r && end <= input_line_pointer)
5780 *nextcharP = *input_line_pointer;
5781 *input_line_pointer = 0;
5782 e->X_op = O_register;
5783 e->X_add_number = r - i386_regtab;
5786 input_line_pointer = end;
5792 md_operand (expressionS *e)
5794 if (*input_line_pointer == REGISTER_PREFIX)
5797 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5801 e->X_op = O_register;
5802 e->X_add_number = r - i386_regtab;
5803 input_line_pointer = end;
5809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5810 const char *md_shortopts = "kVQ:sqn";
5812 const char *md_shortopts = "qn";
5815 #define OPTION_32 (OPTION_MD_BASE + 0)
5816 #define OPTION_64 (OPTION_MD_BASE + 1)
5817 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5818 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5819 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5821 struct option md_longopts[] =
5823 {"32", no_argument, NULL, OPTION_32},
5824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5825 {"64", no_argument, NULL, OPTION_64},
5827 {"divide", no_argument, NULL, OPTION_DIVIDE},
5828 {"march", required_argument, NULL, OPTION_MARCH},
5829 {"mtune", required_argument, NULL, OPTION_MTUNE},
5830 {NULL, no_argument, NULL, 0}
5832 size_t md_longopts_size = sizeof (md_longopts);
5835 md_parse_option (int c, char *arg)
5842 optimize_align_code = 0;
5849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5850 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5851 should be emitted or not. FIXME: Not implemented. */
5855 /* -V: SVR4 argument to print version ID. */
5857 print_version_id ();
5860 /* -k: Ignore for FreeBSD compatibility. */
5865 /* -s: On i386 Solaris, this tells the native assembler to use
5866 .stab instead of .stab.excl. We always use .stab anyhow. */
5869 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5872 const char **list, **l;
5874 list = bfd_target_list ();
5875 for (l = list; *l != NULL; l++)
5876 if ( strncmp (*l, "elf64-x86-64", 12) == 0
5877 || strcmp (*l, "coff-x86-64") == 0
5878 || strcmp (*l, "pe-x86-64") == 0
5879 || strcmp (*l, "pei-x86-64") == 0)
5881 default_arch = "x86_64";
5885 as_fatal (_("No compiled in support for x86_64"));
5892 default_arch = "i386";
5896 #ifdef SVR4_COMMENT_CHARS
5901 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5903 for (s = i386_comment_chars; *s != '\0'; s++)
5907 i386_comment_chars = n;
5914 as_fatal (_("Invalid -march= option: `%s'"), arg);
5915 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5917 if (strcmp (arg, cpu_arch [i].name) == 0)
5919 cpu_arch_isa = cpu_arch[i].type;
5920 cpu_arch_isa_flags = cpu_arch[i].flags;
5921 if (!cpu_arch_tune_set)
5923 cpu_arch_tune = cpu_arch_isa;
5924 cpu_arch_tune_flags = cpu_arch_isa_flags;
5929 if (i >= ARRAY_SIZE (cpu_arch))
5930 as_fatal (_("Invalid -march= option: `%s'"), arg);
5935 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5936 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5938 if (strcmp (arg, cpu_arch [i].name) == 0)
5940 cpu_arch_tune_set = 1;
5941 cpu_arch_tune = cpu_arch [i].type;
5942 cpu_arch_tune_flags = cpu_arch[i].flags;
5946 if (i >= ARRAY_SIZE (cpu_arch))
5947 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5957 md_show_usage (stream)
5960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5961 fprintf (stream, _("\
5963 -V print assembler version number\n\
5966 fprintf (stream, _("\
5967 -n Do not optimize code alignment\n\
5968 -q quieten some warnings\n"));
5969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5970 fprintf (stream, _("\
5973 #ifdef SVR4_COMMENT_CHARS
5974 fprintf (stream, _("\
5975 --divide do not treat `/' as a comment character\n"));
5977 fprintf (stream, _("\
5978 --divide ignored\n"));
5980 fprintf (stream, _("\
5981 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5982 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5983 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5989 x86_64_target_format (void)
5991 if (strcmp (default_arch, "x86_64") == 0)
5993 set_code_flag (CODE_64BIT);
5994 return COFF_TARGET_FORMAT;
5996 else if (strcmp (default_arch, "i386") == 0)
5998 set_code_flag (CODE_32BIT);
6002 as_fatal (_("Unknown architecture"));
6007 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6010 /* Pick the target format to use. */
6013 i386_target_format ()
6015 if (!strcmp (default_arch, "x86_64"))
6017 set_code_flag (CODE_64BIT);
6018 if (cpu_arch_isa_flags == 0)
6019 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6020 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6022 if (cpu_arch_tune_flags == 0)
6023 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6024 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6027 else if (!strcmp (default_arch, "i386"))
6029 set_code_flag (CODE_32BIT);
6030 if (cpu_arch_isa_flags == 0)
6031 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6032 if (cpu_arch_tune_flags == 0)
6033 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6036 as_fatal (_("Unknown architecture"));
6037 switch (OUTPUT_FLAVOR)
6039 #ifdef OBJ_MAYBE_AOUT
6040 case bfd_target_aout_flavour:
6041 return AOUT_TARGET_FORMAT;
6043 #ifdef OBJ_MAYBE_COFF
6044 case bfd_target_coff_flavour:
6047 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6048 case bfd_target_elf_flavour:
6050 if (flag_code == CODE_64BIT)
6053 use_rela_relocations = 1;
6055 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6064 #endif /* OBJ_MAYBE_ more than one */
6066 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6067 void i386_elf_emit_arch_note ()
6069 if (IS_ELF && cpu_arch_name != NULL)
6072 asection *seg = now_seg;
6073 subsegT subseg = now_subseg;
6074 Elf_Internal_Note i_note;
6075 Elf_External_Note e_note;
6076 asection *note_secp;
6079 /* Create the .note section. */
6080 note_secp = subseg_new (".note", 0);
6081 bfd_set_section_flags (stdoutput,
6083 SEC_HAS_CONTENTS | SEC_READONLY);
6085 /* Process the arch string. */
6086 len = strlen (cpu_arch_name);
6088 i_note.namesz = len + 1;
6090 i_note.type = NT_ARCH;
6091 p = frag_more (sizeof (e_note.namesz));
6092 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6093 p = frag_more (sizeof (e_note.descsz));
6094 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6095 p = frag_more (sizeof (e_note.type));
6096 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6097 p = frag_more (len + 1);
6098 strcpy (p, cpu_arch_name);
6100 frag_align (2, 0, 0);
6102 subseg_set (seg, subseg);
6108 md_undefined_symbol (name)
6111 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6112 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6113 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6114 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6118 if (symbol_find (name))
6119 as_bad (_("GOT already in symbol table"));
6120 GOT_symbol = symbol_new (name, undefined_section,
6121 (valueT) 0, &zero_address_frag);
6128 /* Round up a section size to the appropriate boundary. */
6131 md_section_align (segment, size)
6132 segT segment ATTRIBUTE_UNUSED;
6135 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6136 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6138 /* For a.out, force the section size to be aligned. If we don't do
6139 this, BFD will align it for us, but it will not write out the
6140 final bytes of the section. This may be a bug in BFD, but it is
6141 easier to fix it here since that is how the other a.out targets
6145 align = bfd_get_section_alignment (stdoutput, segment);
6146 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6153 /* On the i386, PC-relative offsets are relative to the start of the
6154 next instruction. That is, the address of the offset, plus its
6155 size, since the offset is always the last part of the insn. */
6158 md_pcrel_from (fixP)
6161 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6168 int ignore ATTRIBUTE_UNUSED;
6172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6174 obj_elf_section_change_hook ();
6176 temp = get_absolute_expression ();
6177 subseg_set (bss_section, (subsegT) temp);
6178 demand_empty_rest_of_line ();
6184 i386_validate_fix (fixp)
6187 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6189 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6193 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6198 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6200 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6207 tc_gen_reloc (section, fixp)
6208 asection *section ATTRIBUTE_UNUSED;
6212 bfd_reloc_code_real_type code;
6214 switch (fixp->fx_r_type)
6216 case BFD_RELOC_X86_64_PLT32:
6217 case BFD_RELOC_X86_64_GOT32:
6218 case BFD_RELOC_X86_64_GOTPCREL:
6219 case BFD_RELOC_386_PLT32:
6220 case BFD_RELOC_386_GOT32:
6221 case BFD_RELOC_386_GOTOFF:
6222 case BFD_RELOC_386_GOTPC:
6223 case BFD_RELOC_386_TLS_GD:
6224 case BFD_RELOC_386_TLS_LDM:
6225 case BFD_RELOC_386_TLS_LDO_32:
6226 case BFD_RELOC_386_TLS_IE_32:
6227 case BFD_RELOC_386_TLS_IE:
6228 case BFD_RELOC_386_TLS_GOTIE:
6229 case BFD_RELOC_386_TLS_LE_32:
6230 case BFD_RELOC_386_TLS_LE:
6231 case BFD_RELOC_386_TLS_GOTDESC:
6232 case BFD_RELOC_386_TLS_DESC_CALL:
6233 case BFD_RELOC_X86_64_TLSGD:
6234 case BFD_RELOC_X86_64_TLSLD:
6235 case BFD_RELOC_X86_64_DTPOFF32:
6236 case BFD_RELOC_X86_64_DTPOFF64:
6237 case BFD_RELOC_X86_64_GOTTPOFF:
6238 case BFD_RELOC_X86_64_TPOFF32:
6239 case BFD_RELOC_X86_64_TPOFF64:
6240 case BFD_RELOC_X86_64_GOTOFF64:
6241 case BFD_RELOC_X86_64_GOTPC32:
6242 case BFD_RELOC_X86_64_GOT64:
6243 case BFD_RELOC_X86_64_GOTPCREL64:
6244 case BFD_RELOC_X86_64_GOTPC64:
6245 case BFD_RELOC_X86_64_GOTPLT64:
6246 case BFD_RELOC_X86_64_PLTOFF64:
6247 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6248 case BFD_RELOC_X86_64_TLSDESC_CALL:
6250 case BFD_RELOC_VTABLE_ENTRY:
6251 case BFD_RELOC_VTABLE_INHERIT:
6253 case BFD_RELOC_32_SECREL:
6255 code = fixp->fx_r_type;
6257 case BFD_RELOC_X86_64_32S:
6258 if (!fixp->fx_pcrel)
6260 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6261 code = fixp->fx_r_type;
6267 switch (fixp->fx_size)
6270 as_bad_where (fixp->fx_file, fixp->fx_line,
6271 _("can not do %d byte pc-relative relocation"),
6273 code = BFD_RELOC_32_PCREL;
6275 case 1: code = BFD_RELOC_8_PCREL; break;
6276 case 2: code = BFD_RELOC_16_PCREL; break;
6277 case 4: code = BFD_RELOC_32_PCREL; break;
6279 case 8: code = BFD_RELOC_64_PCREL; break;
6285 switch (fixp->fx_size)
6288 as_bad_where (fixp->fx_file, fixp->fx_line,
6289 _("can not do %d byte relocation"),
6291 code = BFD_RELOC_32;
6293 case 1: code = BFD_RELOC_8; break;
6294 case 2: code = BFD_RELOC_16; break;
6295 case 4: code = BFD_RELOC_32; break;
6297 case 8: code = BFD_RELOC_64; break;
6304 if ((code == BFD_RELOC_32
6305 || code == BFD_RELOC_32_PCREL
6306 || code == BFD_RELOC_X86_64_32S)
6308 && fixp->fx_addsy == GOT_symbol)
6311 code = BFD_RELOC_386_GOTPC;
6313 code = BFD_RELOC_X86_64_GOTPC32;
6315 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6317 && fixp->fx_addsy == GOT_symbol)
6319 code = BFD_RELOC_X86_64_GOTPC64;
6322 rel = (arelent *) xmalloc (sizeof (arelent));
6323 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6324 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6326 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6328 if (!use_rela_relocations)
6330 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6331 vtable entry to be used in the relocation's section offset. */
6332 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6333 rel->address = fixp->fx_offset;
6337 /* Use the rela in 64bit mode. */
6340 if (!fixp->fx_pcrel)
6341 rel->addend = fixp->fx_offset;
6345 case BFD_RELOC_X86_64_PLT32:
6346 case BFD_RELOC_X86_64_GOT32:
6347 case BFD_RELOC_X86_64_GOTPCREL:
6348 case BFD_RELOC_X86_64_TLSGD:
6349 case BFD_RELOC_X86_64_TLSLD:
6350 case BFD_RELOC_X86_64_GOTTPOFF:
6351 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6352 case BFD_RELOC_X86_64_TLSDESC_CALL:
6353 rel->addend = fixp->fx_offset - fixp->fx_size;
6356 rel->addend = (section->vma
6358 + fixp->fx_addnumber
6359 + md_pcrel_from (fixp));
6364 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6365 if (rel->howto == NULL)
6367 as_bad_where (fixp->fx_file, fixp->fx_line,
6368 _("cannot represent relocation type %s"),
6369 bfd_get_reloc_code_name (code));
6370 /* Set howto to a garbage value so that we can keep going. */
6371 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6372 assert (rel->howto != NULL);
6379 /* Parse operands using Intel syntax. This implements a recursive descent
6380 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6383 FIXME: We do not recognize the full operand grammar defined in the MASM
6384 documentation. In particular, all the structure/union and
6385 high-level macro operands are missing.
6387 Uppercase words are terminals, lower case words are non-terminals.
6388 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6389 bars '|' denote choices. Most grammar productions are implemented in
6390 functions called 'intel_<production>'.
6392 Initial production is 'expr'.
6398 binOp & | AND | \| | OR | ^ | XOR
6400 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6402 constant digits [[ radixOverride ]]
6404 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6442 => expr expr cmpOp e04
6445 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6446 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6448 hexdigit a | b | c | d | e | f
6449 | A | B | C | D | E | F
6455 mulOp * | / | % | MOD | << | SHL | >> | SHR
6459 register specialRegister
6463 segmentRegister CS | DS | ES | FS | GS | SS
6465 specialRegister CR0 | CR2 | CR3 | CR4
6466 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6467 | TR3 | TR4 | TR5 | TR6 | TR7
6469 We simplify the grammar in obvious places (e.g., register parsing is
6470 done by calling parse_register) and eliminate immediate left recursion
6471 to implement a recursive-descent parser.
6475 expr' cmpOp e04 expr'
6526 /* Parsing structure for the intel syntax parser. Used to implement the
6527 semantic actions for the operand grammar. */
6528 struct intel_parser_s
6530 char *op_string; /* The string being parsed. */
6531 int got_a_float; /* Whether the operand is a float. */
6532 int op_modifier; /* Operand modifier. */
6533 int is_mem; /* 1 if operand is memory reference. */
6534 int in_offset; /* >=1 if parsing operand of offset. */
6535 int in_bracket; /* >=1 if parsing operand in brackets. */
6536 const reg_entry *reg; /* Last register reference found. */
6537 char *disp; /* Displacement string being built. */
6538 char *next_operand; /* Resume point when splitting operands. */
6541 static struct intel_parser_s intel_parser;
6543 /* Token structure for parsing intel syntax. */
6546 int code; /* Token code. */
6547 const reg_entry *reg; /* Register entry for register tokens. */
6548 char *str; /* String representation. */
6551 static struct intel_token cur_token, prev_token;
6553 /* Token codes for the intel parser. Since T_SHORT is already used
6554 by COFF, undefine it first to prevent a warning. */
6573 /* Prototypes for intel parser functions. */
6574 static int intel_match_token PARAMS ((int code));
6575 static void intel_get_token PARAMS ((void));
6576 static void intel_putback_token PARAMS ((void));
6577 static int intel_expr PARAMS ((void));
6578 static int intel_e04 PARAMS ((void));
6579 static int intel_e05 PARAMS ((void));
6580 static int intel_e06 PARAMS ((void));
6581 static int intel_e09 PARAMS ((void));
6582 static int intel_bracket_expr PARAMS ((void));
6583 static int intel_e10 PARAMS ((void));
6584 static int intel_e11 PARAMS ((void));
6587 i386_intel_operand (operand_string, got_a_float)
6588 char *operand_string;
6594 p = intel_parser.op_string = xstrdup (operand_string);
6595 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6599 /* Initialize token holders. */
6600 cur_token.code = prev_token.code = T_NIL;
6601 cur_token.reg = prev_token.reg = NULL;
6602 cur_token.str = prev_token.str = NULL;
6604 /* Initialize parser structure. */
6605 intel_parser.got_a_float = got_a_float;
6606 intel_parser.op_modifier = 0;
6607 intel_parser.is_mem = 0;
6608 intel_parser.in_offset = 0;
6609 intel_parser.in_bracket = 0;
6610 intel_parser.reg = NULL;
6611 intel_parser.disp[0] = '\0';
6612 intel_parser.next_operand = NULL;
6614 /* Read the first token and start the parser. */
6616 ret = intel_expr ();
6621 if (cur_token.code != T_NIL)
6623 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6624 current_templates->start->name, cur_token.str);
6627 /* If we found a memory reference, hand it over to i386_displacement
6628 to fill in the rest of the operand fields. */
6629 else if (intel_parser.is_mem)
6631 if ((i.mem_operands == 1
6632 && (current_templates->start->opcode_modifier & IsString) == 0)
6633 || i.mem_operands == 2)
6635 as_bad (_("too many memory references for '%s'"),
6636 current_templates->start->name);
6641 char *s = intel_parser.disp;
6644 if (!quiet_warnings && intel_parser.is_mem < 0)
6645 /* See the comments in intel_bracket_expr. */
6646 as_warn (_("Treating `%s' as memory reference"), operand_string);
6648 /* Add the displacement expression. */
6650 ret = i386_displacement (s, s + strlen (s));
6653 /* Swap base and index in 16-bit memory operands like
6654 [si+bx]. Since i386_index_check is also used in AT&T
6655 mode we have to do that here. */
6658 && (i.base_reg->reg_type & Reg16)
6659 && (i.index_reg->reg_type & Reg16)
6660 && i.base_reg->reg_num >= 6
6661 && i.index_reg->reg_num < 6)
6663 const reg_entry *base = i.index_reg;
6665 i.index_reg = i.base_reg;
6668 ret = i386_index_check (operand_string);
6673 /* Constant and OFFSET expressions are handled by i386_immediate. */
6674 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6675 || intel_parser.reg == NULL)
6676 ret = i386_immediate (intel_parser.disp);
6678 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6680 if (!ret || !intel_parser.next_operand)
6682 intel_parser.op_string = intel_parser.next_operand;
6683 this_operand = i.operands++;
6687 free (intel_parser.disp);
6692 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6696 expr' cmpOp e04 expr'
6701 /* XXX Implement the comparison operators. */
6702 return intel_e04 ();
6719 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6720 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6722 if (cur_token.code == '+')
6724 else if (cur_token.code == '-')
6725 nregs = NUM_ADDRESS_REGS;
6729 strcat (intel_parser.disp, cur_token.str);
6730 intel_match_token (cur_token.code);
6741 int nregs = ~NUM_ADDRESS_REGS;
6748 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6752 str[0] = cur_token.code;
6754 strcat (intel_parser.disp, str);
6759 intel_match_token (cur_token.code);
6764 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6765 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6776 int nregs = ~NUM_ADDRESS_REGS;
6783 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6787 str[0] = cur_token.code;
6789 strcat (intel_parser.disp, str);
6791 else if (cur_token.code == T_SHL)
6792 strcat (intel_parser.disp, "<<");
6793 else if (cur_token.code == T_SHR)
6794 strcat (intel_parser.disp, ">>");
6798 intel_match_token (cur_token.code);
6803 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6804 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6822 int nregs = ~NUM_ADDRESS_REGS;
6827 /* Don't consume constants here. */
6828 if (cur_token.code == '+' || cur_token.code == '-')
6830 /* Need to look one token ahead - if the next token
6831 is a constant, the current token is its sign. */
6834 intel_match_token (cur_token.code);
6835 next_code = cur_token.code;
6836 intel_putback_token ();
6837 if (next_code == T_CONST)
6841 /* e09 OFFSET e09 */
6842 if (cur_token.code == T_OFFSET)
6845 ++intel_parser.in_offset;
6849 else if (cur_token.code == T_SHORT)
6850 intel_parser.op_modifier |= 1 << T_SHORT;
6853 else if (cur_token.code == '+')
6854 strcat (intel_parser.disp, "+");
6859 else if (cur_token.code == '-' || cur_token.code == '~')
6865 str[0] = cur_token.code;
6867 strcat (intel_parser.disp, str);
6874 intel_match_token (cur_token.code);
6882 /* e09' PTR e10 e09' */
6883 if (cur_token.code == T_PTR)
6887 if (prev_token.code == T_BYTE)
6888 suffix = BYTE_MNEM_SUFFIX;
6890 else if (prev_token.code == T_WORD)
6892 if (current_templates->start->name[0] == 'l'
6893 && current_templates->start->name[2] == 's'
6894 && current_templates->start->name[3] == 0)
6895 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6896 else if (intel_parser.got_a_float == 2) /* "fi..." */
6897 suffix = SHORT_MNEM_SUFFIX;
6899 suffix = WORD_MNEM_SUFFIX;
6902 else if (prev_token.code == T_DWORD)
6904 if (current_templates->start->name[0] == 'l'
6905 && current_templates->start->name[2] == 's'
6906 && current_templates->start->name[3] == 0)
6907 suffix = WORD_MNEM_SUFFIX;
6908 else if (flag_code == CODE_16BIT
6909 && (current_templates->start->opcode_modifier
6910 & (Jump | JumpDword)))
6911 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6912 else if (intel_parser.got_a_float == 1) /* "f..." */
6913 suffix = SHORT_MNEM_SUFFIX;
6915 suffix = LONG_MNEM_SUFFIX;
6918 else if (prev_token.code == T_FWORD)
6920 if (current_templates->start->name[0] == 'l'
6921 && current_templates->start->name[2] == 's'
6922 && current_templates->start->name[3] == 0)
6923 suffix = LONG_MNEM_SUFFIX;
6924 else if (!intel_parser.got_a_float)
6926 if (flag_code == CODE_16BIT)
6927 add_prefix (DATA_PREFIX_OPCODE);
6928 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6931 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6934 else if (prev_token.code == T_QWORD)
6936 if (intel_parser.got_a_float == 1) /* "f..." */
6937 suffix = LONG_MNEM_SUFFIX;
6939 suffix = QWORD_MNEM_SUFFIX;
6942 else if (prev_token.code == T_TBYTE)
6944 if (intel_parser.got_a_float == 1)
6945 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6947 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6950 else if (prev_token.code == T_XMMWORD)
6952 /* XXX ignored for now, but accepted since gcc uses it */
6958 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6962 /* Operands for jump/call using 'ptr' notation denote absolute
6964 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6965 i.types[this_operand] |= JumpAbsolute;
6967 if (current_templates->start->base_opcode == 0x8d /* lea */)
6971 else if (i.suffix != suffix)
6973 as_bad (_("Conflicting operand modifiers"));
6979 /* e09' : e10 e09' */
6980 else if (cur_token.code == ':')
6982 if (prev_token.code != T_REG)
6984 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6985 segment/group identifier (which we don't have), using comma
6986 as the operand separator there is even less consistent, since
6987 there all branches only have a single operand. */
6988 if (this_operand != 0
6989 || intel_parser.in_offset
6990 || intel_parser.in_bracket
6991 || (!(current_templates->start->opcode_modifier
6992 & (Jump|JumpDword|JumpInterSegment))
6993 && !(current_templates->start->operand_types[0]
6995 return intel_match_token (T_NIL);
6996 /* Remember the start of the 2nd operand and terminate 1st
6998 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6999 another expression), but it gets at least the simplest case
7000 (a plain number or symbol on the left side) right. */
7001 intel_parser.next_operand = intel_parser.op_string;
7002 *--intel_parser.op_string = '\0';
7003 return intel_match_token (':');
7011 intel_match_token (cur_token.code);
7017 --intel_parser.in_offset;
7020 if (NUM_ADDRESS_REGS > nregs)
7022 as_bad (_("Invalid operand to `OFFSET'"));
7025 intel_parser.op_modifier |= 1 << T_OFFSET;
7028 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7029 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7034 intel_bracket_expr ()
7036 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7037 const char *start = intel_parser.op_string;
7040 if (i.op[this_operand].regs)
7041 return intel_match_token (T_NIL);
7043 intel_match_token ('[');
7045 /* Mark as a memory operand only if it's not already known to be an
7046 offset expression. If it's an offset expression, we need to keep
7048 if (!intel_parser.in_offset)
7050 ++intel_parser.in_bracket;
7052 /* Operands for jump/call inside brackets denote absolute addresses. */
7053 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7054 i.types[this_operand] |= JumpAbsolute;
7056 /* Unfortunately gas always diverged from MASM in a respect that can't
7057 be easily fixed without risking to break code sequences likely to be
7058 encountered (the testsuite even check for this): MASM doesn't consider
7059 an expression inside brackets unconditionally as a memory reference.
7060 When that is e.g. a constant, an offset expression, or the sum of the
7061 two, this is still taken as a constant load. gas, however, always
7062 treated these as memory references. As a compromise, we'll try to make
7063 offset expressions inside brackets work the MASM way (since that's
7064 less likely to be found in real world code), but make constants alone
7065 continue to work the traditional gas way. In either case, issue a
7067 intel_parser.op_modifier &= ~was_offset;
7070 strcat (intel_parser.disp, "[");
7072 /* Add a '+' to the displacement string if necessary. */
7073 if (*intel_parser.disp != '\0'
7074 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7075 strcat (intel_parser.disp, "+");
7078 && (len = intel_parser.op_string - start - 1,
7079 intel_match_token (']')))
7081 /* Preserve brackets when the operand is an offset expression. */
7082 if (intel_parser.in_offset)
7083 strcat (intel_parser.disp, "]");
7086 --intel_parser.in_bracket;
7087 if (i.base_reg || i.index_reg)
7088 intel_parser.is_mem = 1;
7089 if (!intel_parser.is_mem)
7091 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7092 /* Defer the warning until all of the operand was parsed. */
7093 intel_parser.is_mem = -1;
7094 else if (!quiet_warnings)
7095 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7098 intel_parser.op_modifier |= was_offset;
7115 while (cur_token.code == '[')
7117 if (!intel_bracket_expr ())
7142 switch (cur_token.code)
7146 intel_match_token ('(');
7147 strcat (intel_parser.disp, "(");
7149 if (intel_expr () && intel_match_token (')'))
7151 strcat (intel_parser.disp, ")");
7158 return intel_bracket_expr ();
7163 strcat (intel_parser.disp, cur_token.str);
7164 intel_match_token (cur_token.code);
7166 /* Mark as a memory operand only if it's not already known to be an
7167 offset expression. */
7168 if (!intel_parser.in_offset)
7169 intel_parser.is_mem = 1;
7176 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7178 intel_match_token (T_REG);
7180 /* Check for segment change. */
7181 if (cur_token.code == ':')
7183 if (!(reg->reg_type & (SReg2 | SReg3)))
7185 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7188 else if (i.seg[i.mem_operands])
7189 as_warn (_("Extra segment override ignored"));
7192 if (!intel_parser.in_offset)
7193 intel_parser.is_mem = 1;
7194 switch (reg->reg_num)
7197 i.seg[i.mem_operands] = &es;
7200 i.seg[i.mem_operands] = &cs;
7203 i.seg[i.mem_operands] = &ss;
7206 i.seg[i.mem_operands] = &ds;
7209 i.seg[i.mem_operands] = &fs;
7212 i.seg[i.mem_operands] = &gs;
7218 /* Not a segment register. Check for register scaling. */
7219 else if (cur_token.code == '*')
7221 if (!intel_parser.in_bracket)
7223 as_bad (_("Register scaling only allowed in memory operands"));
7227 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7228 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7229 else if (i.index_reg)
7230 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7232 /* What follows must be a valid scale. */
7233 intel_match_token ('*');
7235 i.types[this_operand] |= BaseIndex;
7237 /* Set the scale after setting the register (otherwise,
7238 i386_scale will complain) */
7239 if (cur_token.code == '+' || cur_token.code == '-')
7241 char *str, sign = cur_token.code;
7242 intel_match_token (cur_token.code);
7243 if (cur_token.code != T_CONST)
7245 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7249 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7250 strcpy (str + 1, cur_token.str);
7252 if (!i386_scale (str))
7256 else if (!i386_scale (cur_token.str))
7258 intel_match_token (cur_token.code);
7261 /* No scaling. If this is a memory operand, the register is either a
7262 base register (first occurrence) or an index register (second
7264 else if (intel_parser.in_bracket)
7269 else if (!i.index_reg)
7273 as_bad (_("Too many register references in memory operand"));
7277 i.types[this_operand] |= BaseIndex;
7280 /* It's neither base nor index. */
7281 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7283 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7284 i.op[this_operand].regs = reg;
7289 as_bad (_("Invalid use of register"));
7293 /* Since registers are not part of the displacement string (except
7294 when we're parsing offset operands), we may need to remove any
7295 preceding '+' from the displacement string. */
7296 if (*intel_parser.disp != '\0'
7297 && !intel_parser.in_offset)
7299 char *s = intel_parser.disp;
7300 s += strlen (s) - 1;
7323 intel_match_token (cur_token.code);
7325 if (cur_token.code == T_PTR)
7328 /* It must have been an identifier. */
7329 intel_putback_token ();
7330 cur_token.code = T_ID;
7336 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7340 /* The identifier represents a memory reference only if it's not
7341 preceded by an offset modifier and if it's not an equate. */
7342 symbolP = symbol_find(cur_token.str);
7343 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7344 intel_parser.is_mem = 1;
7352 char *save_str, sign = 0;
7354 /* Allow constants that start with `+' or `-'. */
7355 if (cur_token.code == '-' || cur_token.code == '+')
7357 sign = cur_token.code;
7358 intel_match_token (cur_token.code);
7359 if (cur_token.code != T_CONST)
7361 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7367 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7368 strcpy (save_str + !!sign, cur_token.str);
7372 /* Get the next token to check for register scaling. */
7373 intel_match_token (cur_token.code);
7375 /* Check if this constant is a scaling factor for an index register. */
7376 if (cur_token.code == '*')
7378 if (intel_match_token ('*') && cur_token.code == T_REG)
7380 const reg_entry *reg = cur_token.reg;
7382 if (!intel_parser.in_bracket)
7384 as_bad (_("Register scaling only allowed in memory operands"));
7388 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7389 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7390 else if (i.index_reg)
7391 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7393 /* The constant is followed by `* reg', so it must be
7396 i.types[this_operand] |= BaseIndex;
7398 /* Set the scale after setting the register (otherwise,
7399 i386_scale will complain) */
7400 if (!i386_scale (save_str))
7402 intel_match_token (T_REG);
7404 /* Since registers are not part of the displacement
7405 string, we may need to remove any preceding '+' from
7406 the displacement string. */
7407 if (*intel_parser.disp != '\0')
7409 char *s = intel_parser.disp;
7410 s += strlen (s) - 1;
7420 /* The constant was not used for register scaling. Since we have
7421 already consumed the token following `*' we now need to put it
7422 back in the stream. */
7423 intel_putback_token ();
7426 /* Add the constant to the displacement string. */
7427 strcat (intel_parser.disp, save_str);
7434 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7438 /* Match the given token against cur_token. If they match, read the next
7439 token from the operand string. */
7441 intel_match_token (code)
7444 if (cur_token.code == code)
7451 as_bad (_("Unexpected token `%s'"), cur_token.str);
7456 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7461 const reg_entry *reg;
7462 struct intel_token new_token;
7464 new_token.code = T_NIL;
7465 new_token.reg = NULL;
7466 new_token.str = NULL;
7468 /* Free the memory allocated to the previous token and move
7469 cur_token to prev_token. */
7471 free (prev_token.str);
7473 prev_token = cur_token;
7475 /* Skip whitespace. */
7476 while (is_space_char (*intel_parser.op_string))
7477 intel_parser.op_string++;
7479 /* Return an empty token if we find nothing else on the line. */
7480 if (*intel_parser.op_string == '\0')
7482 cur_token = new_token;
7486 /* The new token cannot be larger than the remainder of the operand
7488 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7489 new_token.str[0] = '\0';
7491 if (strchr ("0123456789", *intel_parser.op_string))
7493 char *p = new_token.str;
7494 char *q = intel_parser.op_string;
7495 new_token.code = T_CONST;
7497 /* Allow any kind of identifier char to encompass floating point and
7498 hexadecimal numbers. */
7499 while (is_identifier_char (*q))
7503 /* Recognize special symbol names [0-9][bf]. */
7504 if (strlen (intel_parser.op_string) == 2
7505 && (intel_parser.op_string[1] == 'b'
7506 || intel_parser.op_string[1] == 'f'))
7507 new_token.code = T_ID;
7510 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7512 size_t len = end_op - intel_parser.op_string;
7514 new_token.code = T_REG;
7515 new_token.reg = reg;
7517 memcpy (new_token.str, intel_parser.op_string, len);
7518 new_token.str[len] = '\0';
7521 else if (is_identifier_char (*intel_parser.op_string))
7523 char *p = new_token.str;
7524 char *q = intel_parser.op_string;
7526 /* A '.' or '$' followed by an identifier char is an identifier.
7527 Otherwise, it's operator '.' followed by an expression. */
7528 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7530 new_token.code = '.';
7531 new_token.str[0] = '.';
7532 new_token.str[1] = '\0';
7536 while (is_identifier_char (*q) || *q == '@')
7540 if (strcasecmp (new_token.str, "NOT") == 0)
7541 new_token.code = '~';
7543 else if (strcasecmp (new_token.str, "MOD") == 0)
7544 new_token.code = '%';
7546 else if (strcasecmp (new_token.str, "AND") == 0)
7547 new_token.code = '&';
7549 else if (strcasecmp (new_token.str, "OR") == 0)
7550 new_token.code = '|';
7552 else if (strcasecmp (new_token.str, "XOR") == 0)
7553 new_token.code = '^';
7555 else if (strcasecmp (new_token.str, "SHL") == 0)
7556 new_token.code = T_SHL;
7558 else if (strcasecmp (new_token.str, "SHR") == 0)
7559 new_token.code = T_SHR;
7561 else if (strcasecmp (new_token.str, "BYTE") == 0)
7562 new_token.code = T_BYTE;
7564 else if (strcasecmp (new_token.str, "WORD") == 0)
7565 new_token.code = T_WORD;
7567 else if (strcasecmp (new_token.str, "DWORD") == 0)
7568 new_token.code = T_DWORD;
7570 else if (strcasecmp (new_token.str, "FWORD") == 0)
7571 new_token.code = T_FWORD;
7573 else if (strcasecmp (new_token.str, "QWORD") == 0)
7574 new_token.code = T_QWORD;
7576 else if (strcasecmp (new_token.str, "TBYTE") == 0
7577 /* XXX remove (gcc still uses it) */
7578 || strcasecmp (new_token.str, "XWORD") == 0)
7579 new_token.code = T_TBYTE;
7581 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7582 || strcasecmp (new_token.str, "OWORD") == 0)
7583 new_token.code = T_XMMWORD;
7585 else if (strcasecmp (new_token.str, "PTR") == 0)
7586 new_token.code = T_PTR;
7588 else if (strcasecmp (new_token.str, "SHORT") == 0)
7589 new_token.code = T_SHORT;
7591 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7593 new_token.code = T_OFFSET;
7595 /* ??? This is not mentioned in the MASM grammar but gcc
7596 makes use of it with -mintel-syntax. OFFSET may be
7597 followed by FLAT: */
7598 if (strncasecmp (q, " FLAT:", 6) == 0)
7599 strcat (new_token.str, " FLAT:");
7602 /* ??? This is not mentioned in the MASM grammar. */
7603 else if (strcasecmp (new_token.str, "FLAT") == 0)
7605 new_token.code = T_OFFSET;
7607 strcat (new_token.str, ":");
7609 as_bad (_("`:' expected"));
7613 new_token.code = T_ID;
7617 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7619 new_token.code = *intel_parser.op_string;
7620 new_token.str[0] = *intel_parser.op_string;
7621 new_token.str[1] = '\0';
7624 else if (strchr ("<>", *intel_parser.op_string)
7625 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7627 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7628 new_token.str[0] = *intel_parser.op_string;
7629 new_token.str[1] = *intel_parser.op_string;
7630 new_token.str[2] = '\0';
7634 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7636 intel_parser.op_string += strlen (new_token.str);
7637 cur_token = new_token;
7640 /* Put cur_token back into the token stream and make cur_token point to
7643 intel_putback_token ()
7645 if (cur_token.code != T_NIL)
7647 intel_parser.op_string -= strlen (cur_token.str);
7648 free (cur_token.str);
7650 cur_token = prev_token;
7652 /* Forget prev_token. */
7653 prev_token.code = T_NIL;
7654 prev_token.reg = NULL;
7655 prev_token.str = NULL;
7659 tc_x86_regname_to_dw2regnum (char *regname)
7661 unsigned int regnum;
7662 unsigned int regnames_count;
7663 static const char *const regnames_32[] =
7665 "eax", "ecx", "edx", "ebx",
7666 "esp", "ebp", "esi", "edi",
7667 "eip", "eflags", NULL,
7668 "st0", "st1", "st2", "st3",
7669 "st4", "st5", "st6", "st7",
7671 "xmm0", "xmm1", "xmm2", "xmm3",
7672 "xmm4", "xmm5", "xmm6", "xmm7",
7673 "mm0", "mm1", "mm2", "mm3",
7674 "mm4", "mm5", "mm6", "mm7",
7675 "fcw", "fsw", "mxcsr",
7676 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7679 static const char *const regnames_64[] =
7681 "rax", "rdx", "rcx", "rbx",
7682 "rsi", "rdi", "rbp", "rsp",
7683 "r8", "r9", "r10", "r11",
7684 "r12", "r13", "r14", "r15",
7686 "xmm0", "xmm1", "xmm2", "xmm3",
7687 "xmm4", "xmm5", "xmm6", "xmm7",
7688 "xmm8", "xmm9", "xmm10", "xmm11",
7689 "xmm12", "xmm13", "xmm14", "xmm15",
7690 "st0", "st1", "st2", "st3",
7691 "st4", "st5", "st6", "st7",
7692 "mm0", "mm1", "mm2", "mm3",
7693 "mm4", "mm5", "mm6", "mm7",
7695 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7696 "fs.base", "gs.base", NULL, NULL,
7698 "mxcsr", "fcw", "fsw"
7700 const char *const *regnames;
7702 if (flag_code == CODE_64BIT)
7704 regnames = regnames_64;
7705 regnames_count = ARRAY_SIZE (regnames_64);
7709 regnames = regnames_32;
7710 regnames_count = ARRAY_SIZE (regnames_32);
7713 for (regnum = 0; regnum < regnames_count; regnum++)
7714 if (regnames[regnum] != NULL
7715 && strcmp (regname, regnames[regnum]) == 0)
7722 tc_x86_frame_initial_instructions (void)
7724 static unsigned int sp_regno;
7727 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7730 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7731 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7735 i386_elf_section_type (const char *str, size_t len)
7737 if (flag_code == CODE_64BIT
7738 && len == sizeof ("unwind") - 1
7739 && strncmp (str, "unwind", 6) == 0)
7740 return SHT_X86_64_UNWIND;
7747 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7751 expr.X_op = O_secrel;
7752 expr.X_add_symbol = symbol;
7753 expr.X_add_number = 0;
7754 emit_expr (&expr, size);
7758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7759 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7762 x86_64_section_letter (int letter, char **ptr_msg)
7764 if (flag_code == CODE_64BIT)
7767 return SHF_X86_64_LARGE;
7769 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7772 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7777 x86_64_section_word (char *str, size_t len)
7779 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7780 return SHF_X86_64_LARGE;
7786 handle_large_common (int small ATTRIBUTE_UNUSED)
7788 if (flag_code != CODE_64BIT)
7790 s_comm_internal (0, elf_common_parse);
7791 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7795 static segT lbss_section;
7796 asection *saved_com_section_ptr = elf_com_section_ptr;
7797 asection *saved_bss_section = bss_section;
7799 if (lbss_section == NULL)
7801 flagword applicable;
7803 subsegT subseg = now_subseg;
7805 /* The .lbss section is for local .largecomm symbols. */
7806 lbss_section = subseg_new (".lbss", 0);
7807 applicable = bfd_applicable_section_flags (stdoutput);
7808 bfd_set_section_flags (stdoutput, lbss_section,
7809 applicable & SEC_ALLOC);
7810 seg_info (lbss_section)->bss = 1;
7812 subseg_set (seg, subseg);
7815 elf_com_section_ptr = &_bfd_elf_large_com_section;
7816 bss_section = lbss_section;
7818 s_comm_internal (0, elf_common_parse);
7820 elf_com_section_ptr = saved_com_section_ptr;
7821 bss_section = saved_bss_section;
7824 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */