1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c);
69 static int i386_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry *parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry *build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS *, offsetT);
91 static void output_disp (fragS *, offsetT);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED);
99 static const char *default_arch = DEFAULT_ARCH;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry *regs;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types[MAX_OPERANDS];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op[MAX_OPERANDS];
136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry *seg[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars = "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars = "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "#/";
210 const char line_separator_chars[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars[256];
223 static char register_chars[256];
224 static char operand_chars[256];
225 static char identifier_chars[256];
226 static char digit_chars[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack[32];
244 static char *save_stack_p;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates *current_templates;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
260 /* Current operand we are working on. */
261 static int this_operand;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code;
272 static unsigned int object_64bit;
273 static int use_rela_relocations = 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names[] =
283 /* 1 for intel syntax,
285 static int intel_syntax = 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic = !SYSV386_COMPAT;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc = OLDGCC_COMPAT;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* 1 if fake index register, eiz/riz, is allowed . */
298 static int allow_index_reg = 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix = "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code = 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings = 0;
315 static const char *cpu_arch_name = NULL;
316 static const char *cpu_sub_arch_name = NULL;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
321 /* Bitwise NOT of cpu_arch_flags. */
322 static i386_cpu_flags cpu_arch_flags_not;
324 /* If we have selected a cpu we are generating instructions for. */
325 static int cpu_arch_tune_set = 0;
327 /* Cpu we are generating instructions for. */
328 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
330 /* CPU feature flags of cpu we are generating instructions for. */
331 static i386_cpu_flags cpu_arch_tune_flags;
333 /* CPU instruction set architecture used. */
334 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
336 /* CPU feature flags of instruction set architecture used. */
337 static i386_cpu_flags cpu_arch_isa_flags;
339 /* If set, conditional jumps are not automatically promoted to handle
340 larger than a byte offset. */
341 static unsigned int no_cond_jump_promotion = 0;
343 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
344 static symbolS *GOT_symbol;
346 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
347 unsigned int x86_dwarf2_return_column;
349 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
350 int x86_cie_data_alignment;
352 /* Interface to relax_segment.
353 There are 3 major relax states for 386 jump insns because the
354 different types of jumps add different sizes to frags when we're
355 figuring out what sort of jump to choose to reach a given label. */
358 #define UNCOND_JUMP 0
360 #define COND_JUMP86 2
365 #define SMALL16 (SMALL | CODE16)
367 #define BIG16 (BIG | CODE16)
371 #define INLINE __inline__
377 #define ENCODE_RELAX_STATE(type, size) \
378 ((relax_substateT) (((type) << 2) | (size)))
379 #define TYPE_FROM_RELAX_STATE(s) \
381 #define DISP_SIZE_FROM_RELAX_STATE(s) \
382 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
384 /* This table is used by relax_frag to promote short jumps to long
385 ones where necessary. SMALL (short) jumps may be promoted to BIG
386 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
387 don't allow a short jump in a 32 bit code segment to be promoted to
388 a 16 bit offset jump because it's slower (requires data size
389 prefix), and doesn't work, unless the destination is in the bottom
390 64k of the code segment (The top 16 bits of eip are zeroed). */
392 const relax_typeS md_relax_table[] =
395 1) most positive reach of this state,
396 2) most negative reach of this state,
397 3) how many bytes this mode will have in the variable part of the frag
398 4) which index into the table to try if we can't fit into this one. */
400 /* UNCOND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
403 /* dword jmp adds 4 bytes to frag:
404 0 extra opcode bytes, 4 displacement bytes. */
406 /* word jmp adds 2 byte2 to frag:
407 0 extra opcode bytes, 2 displacement bytes. */
410 /* COND_JUMP states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 3 bytes to frag:
417 1 extra opcode byte, 2 displacement bytes. */
420 /* COND_JUMP86 states. */
421 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
422 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
423 /* dword conditionals adds 5 bytes to frag:
424 1 extra opcode byte, 4 displacement bytes. */
426 /* word conditionals add 4 bytes to frag:
427 1 displacement byte and a 3 byte long branch insn. */
431 static const arch_entry cpu_arch[] =
433 {"generic32", PROCESSOR_GENERIC32,
434 CPU_GENERIC32_FLAGS },
435 {"generic64", PROCESSOR_GENERIC64,
436 CPU_GENERIC64_FLAGS },
437 {"i8086", PROCESSOR_UNKNOWN,
439 {"i186", PROCESSOR_UNKNOWN,
441 {"i286", PROCESSOR_UNKNOWN,
443 {"i386", PROCESSOR_I386,
445 {"i486", PROCESSOR_I486,
447 {"i586", PROCESSOR_PENTIUM,
449 {"i686", PROCESSOR_PENTIUMPRO,
451 {"pentium", PROCESSOR_PENTIUM,
453 {"pentiumpro",PROCESSOR_PENTIUMPRO,
455 {"pentiumii", PROCESSOR_PENTIUMPRO,
457 {"pentiumiii",PROCESSOR_PENTIUMPRO,
459 {"pentium4", PROCESSOR_PENTIUM4,
461 {"prescott", PROCESSOR_NOCONA,
463 {"nocona", PROCESSOR_NOCONA,
465 {"yonah", PROCESSOR_CORE,
467 {"core", PROCESSOR_CORE,
469 {"merom", PROCESSOR_CORE2,
471 {"core2", PROCESSOR_CORE2,
475 {"k6_2", PROCESSOR_K6,
477 {"athlon", PROCESSOR_ATHLON,
479 {"sledgehammer", PROCESSOR_K8,
481 {"opteron", PROCESSOR_K8,
485 {"amdfam10", PROCESSOR_AMDFAM10,
486 CPU_AMDFAM10_FLAGS },
487 {".mmx", PROCESSOR_UNKNOWN,
489 {".sse", PROCESSOR_UNKNOWN,
491 {".sse2", PROCESSOR_UNKNOWN,
493 {".sse3", PROCESSOR_UNKNOWN,
495 {".ssse3", PROCESSOR_UNKNOWN,
497 {".sse4.1", PROCESSOR_UNKNOWN,
499 {".sse4.2", PROCESSOR_UNKNOWN,
501 {".sse4", PROCESSOR_UNKNOWN,
503 {".3dnow", PROCESSOR_UNKNOWN,
505 {".3dnowa", PROCESSOR_UNKNOWN,
507 {".padlock", PROCESSOR_UNKNOWN,
509 {".pacifica", PROCESSOR_UNKNOWN,
511 {".svme", PROCESSOR_UNKNOWN,
513 {".sse4a", PROCESSOR_UNKNOWN,
515 {".abm", PROCESSOR_UNKNOWN,
517 {".sse5", PROCESSOR_UNKNOWN,
521 const pseudo_typeS md_pseudo_table[] =
523 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
524 {"align", s_align_bytes, 0},
526 {"align", s_align_ptwo, 0},
528 {"arch", set_cpu_arch, 0},
532 {"ffloat", float_cons, 'f'},
533 {"dfloat", float_cons, 'd'},
534 {"tfloat", float_cons, 'x'},
536 {"slong", signed_cons, 4},
537 {"noopt", s_ignore, 0},
538 {"optim", s_ignore, 0},
539 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
540 {"code16", set_code_flag, CODE_16BIT},
541 {"code32", set_code_flag, CODE_32BIT},
542 {"code64", set_code_flag, CODE_64BIT},
543 {"intel_syntax", set_intel_syntax, 1},
544 {"att_syntax", set_intel_syntax, 0},
545 {"intel_mnemonic", set_intel_mnemonic, 1},
546 {"att_mnemonic", set_intel_mnemonic, 0},
547 {"allow_index_reg", set_allow_index_reg, 1},
548 {"disallow_index_reg", set_allow_index_reg, 0},
549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 {"largecomm", handle_large_common, 0},
552 {"file", (void (*) (int)) dwarf2_directive_file, 0},
553 {"loc", dwarf2_directive_loc, 0},
554 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
557 {"secrel32", pe_directive_secrel, 0},
562 /* For interface with expression (). */
563 extern char *input_line_pointer;
565 /* Hash table for instruction mnemonic lookup. */
566 static struct hash_control *op_hash;
568 /* Hash table for register lookup. */
569 static struct hash_control *reg_hash;
572 i386_align_code (fragS *fragP, int count)
574 /* Various efficient no-op patterns for aligning code labels.
575 Note: Don't try to assemble the instructions in the comments.
576 0L and 0w are not legal. */
577 static const char f32_1[] =
579 static const char f32_2[] =
580 {0x66,0x90}; /* xchg %ax,%ax */
581 static const char f32_3[] =
582 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
583 static const char f32_4[] =
584 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_5[] =
587 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
588 static const char f32_6[] =
589 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
590 static const char f32_7[] =
591 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_8[] =
594 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
595 static const char f32_9[] =
596 {0x89,0xf6, /* movl %esi,%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_10[] =
599 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_11[] =
602 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f32_12[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
607 static const char f32_13[] =
608 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f32_14[] =
611 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
612 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
613 static const char f16_3[] =
614 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
615 static const char f16_4[] =
616 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_5[] =
619 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
620 static const char f16_6[] =
621 {0x89,0xf6, /* mov %si,%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_7[] =
624 {0x8d,0x74,0x00, /* lea 0(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char f16_8[] =
627 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
628 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
629 static const char jump_31[] =
630 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
632 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
633 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
634 static const char *const f32_patt[] = {
635 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
636 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
638 static const char *const f16_patt[] = {
639 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
642 static const char alt_3[] =
644 /* nopl 0(%[re]ax) */
645 static const char alt_4[] =
646 {0x0f,0x1f,0x40,0x00};
647 /* nopl 0(%[re]ax,%[re]ax,1) */
648 static const char alt_5[] =
649 {0x0f,0x1f,0x44,0x00,0x00};
650 /* nopw 0(%[re]ax,%[re]ax,1) */
651 static const char alt_6[] =
652 {0x66,0x0f,0x1f,0x44,0x00,0x00};
653 /* nopl 0L(%[re]ax) */
654 static const char alt_7[] =
655 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
656 /* nopl 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_8[] =
658 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw 0L(%[re]ax,%[re]ax,1) */
660 static const char alt_9[] =
661 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_10[] =
664 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
666 nopw %cs:0L(%[re]ax,%[re]ax,1) */
667 static const char alt_long_11[] =
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_12[] =
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_13[] =
685 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_14[] =
696 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 nopw %cs:0L(%[re]ax,%[re]ax,1) */
703 static const char alt_long_15[] =
709 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
710 /* nopl 0(%[re]ax,%[re]ax,1)
711 nopw 0(%[re]ax,%[re]ax,1) */
712 static const char alt_short_11[] =
713 {0x0f,0x1f,0x44,0x00,0x00,
714 0x66,0x0f,0x1f,0x44,0x00,0x00};
715 /* nopw 0(%[re]ax,%[re]ax,1)
716 nopw 0(%[re]ax,%[re]ax,1) */
717 static const char alt_short_12[] =
718 {0x66,0x0f,0x1f,0x44,0x00,0x00,
719 0x66,0x0f,0x1f,0x44,0x00,0x00};
720 /* nopw 0(%[re]ax,%[re]ax,1)
722 static const char alt_short_13[] =
723 {0x66,0x0f,0x1f,0x44,0x00,0x00,
724 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 static const char alt_short_14[] =
728 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
729 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
731 nopl 0L(%[re]ax,%[re]ax,1) */
732 static const char alt_short_15[] =
733 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
734 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
735 static const char *const alt_short_patt[] = {
736 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
737 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
738 alt_short_14, alt_short_15
740 static const char *const alt_long_patt[] = {
741 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
742 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
743 alt_long_14, alt_long_15
746 /* Only align for at least a positive non-zero boundary. */
747 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
750 /* We need to decide which NOP sequence to use for 32bit and
751 64bit. When -mtune= is used:
753 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
754 PROCESSOR_GENERIC32, f32_patt will be used.
755 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
756 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
757 alt_long_patt will be used.
758 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
759 PROCESSOR_AMDFAM10, alt_short_patt will be used.
761 When -mtune= isn't used, alt_long_patt will be used if
762 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
765 When -march= or .arch is used, we can't use anything beyond
766 cpu_arch_isa_flags. */
768 if (flag_code == CODE_16BIT)
772 memcpy (fragP->fr_literal + fragP->fr_fix,
774 /* Adjust jump offset. */
775 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
778 memcpy (fragP->fr_literal + fragP->fr_fix,
779 f16_patt[count - 1], count);
783 const char *const *patt = NULL;
785 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
787 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
788 switch (cpu_arch_tune)
790 case PROCESSOR_UNKNOWN:
791 /* We use cpu_arch_isa_flags to check if we SHOULD
792 optimize for Cpu686. */
793 if (cpu_arch_isa_flags.bitfield.cpui686)
794 patt = alt_long_patt;
798 case PROCESSOR_PENTIUMPRO:
799 case PROCESSOR_PENTIUM4:
800 case PROCESSOR_NOCONA:
802 case PROCESSOR_CORE2:
803 case PROCESSOR_GENERIC64:
804 patt = alt_long_patt;
807 case PROCESSOR_ATHLON:
809 case PROCESSOR_AMDFAM10:
810 patt = alt_short_patt;
814 case PROCESSOR_PENTIUM:
815 case PROCESSOR_GENERIC32:
822 switch (cpu_arch_tune)
824 case PROCESSOR_UNKNOWN:
825 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
826 PROCESSOR_UNKNOWN. */
832 case PROCESSOR_PENTIUM:
834 case PROCESSOR_ATHLON:
836 case PROCESSOR_AMDFAM10:
837 case PROCESSOR_GENERIC32:
838 /* We use cpu_arch_isa_flags to check if we CAN optimize
840 if (cpu_arch_isa_flags.bitfield.cpui686)
841 patt = alt_short_patt;
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
849 case PROCESSOR_CORE2:
850 if (cpu_arch_isa_flags.bitfield.cpui686)
851 patt = alt_long_patt;
855 case PROCESSOR_GENERIC64:
856 patt = alt_long_patt;
861 if (patt == f32_patt)
863 /* If the padding is less than 15 bytes, we use the normal
864 ones. Otherwise, we use a jump instruction and adjust
867 memcpy (fragP->fr_literal + fragP->fr_fix,
868 patt[count - 1], count);
871 memcpy (fragP->fr_literal + fragP->fr_fix,
873 /* Adjust jump offset. */
874 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
879 /* Maximum length of an instruction is 15 byte. If the
880 padding is greater than 15 bytes and we don't use jump,
881 we have to break it into smaller pieces. */
886 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
891 memcpy (fragP->fr_literal + fragP->fr_fix,
892 patt [padding - 1], padding);
895 fragP->fr_var = count;
899 uints_all_zero (const unsigned int *x, unsigned int size)
917 uints_set (unsigned int *x, unsigned int v, unsigned int size)
934 uints_equal (const unsigned int *x, const unsigned int *y,
946 return x[0] == y [0];
953 #define UINTS_ALL_ZERO(x) \
954 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
955 #define UINTS_SET(x, v) \
956 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
957 #define UINTS_CLEAR(x) \
958 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
959 #define UINTS_EQUAL(x, y) \
960 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
963 cpu_flags_check_cpu64 (i386_cpu_flags f)
965 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
966 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
969 static INLINE i386_cpu_flags
970 cpu_flags_not (i386_cpu_flags x)
972 switch (ARRAY_SIZE (x.array))
975 x.array [2] = ~x.array [2];
977 x.array [1] = ~x.array [1];
979 x.array [0] = ~x.array [0];
986 x.bitfield.unused = 0;
992 static INLINE i386_cpu_flags
993 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
995 switch (ARRAY_SIZE (x.array))
998 x.array [2] &= y.array [2];
1000 x.array [1] &= y.array [1];
1002 x.array [0] &= y.array [0];
1010 static INLINE i386_cpu_flags
1011 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1013 switch (ARRAY_SIZE (x.array))
1016 x.array [2] |= y.array [2];
1018 x.array [1] |= y.array [1];
1020 x.array [0] |= y.array [0];
1029 cpu_flags_match (i386_cpu_flags x)
1031 i386_cpu_flags not = cpu_arch_flags_not;
1033 not.bitfield.cpu64 = 1;
1034 not.bitfield.cpuno64 = 1;
1036 x.bitfield.cpu64 = 0;
1037 x.bitfield.cpuno64 = 0;
1039 not = cpu_flags_and (x, not);
1040 return UINTS_ALL_ZERO (not);
1043 static INLINE i386_operand_type
1044 operand_type_and (i386_operand_type x, i386_operand_type y)
1046 switch (ARRAY_SIZE (x.array))
1049 x.array [2] &= y.array [2];
1051 x.array [1] &= y.array [1];
1053 x.array [0] &= y.array [0];
1061 static INLINE i386_operand_type
1062 operand_type_or (i386_operand_type x, i386_operand_type y)
1064 switch (ARRAY_SIZE (x.array))
1067 x.array [2] |= y.array [2];
1069 x.array [1] |= y.array [1];
1071 x.array [0] |= y.array [0];
1079 static INLINE i386_operand_type
1080 operand_type_xor (i386_operand_type x, i386_operand_type y)
1082 switch (ARRAY_SIZE (x.array))
1085 x.array [2] ^= y.array [2];
1087 x.array [1] ^= y.array [1];
1089 x.array [0] ^= y.array [0];
1097 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1098 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1099 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1100 static const i386_operand_type reg16_inoutportreg
1101 = OPERAND_TYPE_REG16_INOUTPORTREG;
1102 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1103 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1104 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1105 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1106 static const i386_operand_type anydisp
1107 = OPERAND_TYPE_ANYDISP;
1108 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1109 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1110 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1111 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1112 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1113 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1114 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1115 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1116 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1117 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1128 operand_type_check (i386_operand_type t, enum operand_type c)
1133 return (t.bitfield.reg8
1136 || t.bitfield.reg64);
1139 return (t.bitfield.imm8
1143 || t.bitfield.imm32s
1144 || t.bitfield.imm64);
1147 return (t.bitfield.disp8
1148 || t.bitfield.disp16
1149 || t.bitfield.disp32
1150 || t.bitfield.disp32s
1151 || t.bitfield.disp64);
1154 return (t.bitfield.disp8
1155 || t.bitfield.disp16
1156 || t.bitfield.disp32
1157 || t.bitfield.disp32s
1158 || t.bitfield.disp64
1159 || t.bitfield.baseindex);
1167 operand_type_match (i386_operand_type overlap,
1168 i386_operand_type given)
1170 i386_operand_type temp = overlap;
1172 temp.bitfield.jumpabsolute = 0;
1173 if (UINTS_ALL_ZERO (temp))
1176 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1177 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1180 /* If given types r0 and r1 are registers they must be of the same type
1181 unless the expected operand type register overlap is null.
1182 Note that Acc in a template matches every size of reg. */
1185 operand_type_register_match (i386_operand_type m0,
1186 i386_operand_type g0,
1187 i386_operand_type t0,
1188 i386_operand_type m1,
1189 i386_operand_type g1,
1190 i386_operand_type t1)
1192 if (!operand_type_check (g0, reg))
1195 if (!operand_type_check (g1, reg))
1198 if (g0.bitfield.reg8 == g1.bitfield.reg8
1199 && g0.bitfield.reg16 == g1.bitfield.reg16
1200 && g0.bitfield.reg32 == g1.bitfield.reg32
1201 && g0.bitfield.reg64 == g1.bitfield.reg64)
1204 if (m0.bitfield.acc)
1206 t0.bitfield.reg8 = 1;
1207 t0.bitfield.reg16 = 1;
1208 t0.bitfield.reg32 = 1;
1209 t0.bitfield.reg64 = 1;
1212 if (m1.bitfield.acc)
1214 t1.bitfield.reg8 = 1;
1215 t1.bitfield.reg16 = 1;
1216 t1.bitfield.reg32 = 1;
1217 t1.bitfield.reg64 = 1;
1220 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1221 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1222 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1223 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1226 static INLINE unsigned int
1227 mode_from_disp_size (i386_operand_type t)
1229 if (t.bitfield.disp8)
1231 else if (t.bitfield.disp16
1232 || t.bitfield.disp32
1233 || t.bitfield.disp32s)
1240 fits_in_signed_byte (offsetT num)
1242 return (num >= -128) && (num <= 127);
1246 fits_in_unsigned_byte (offsetT num)
1248 return (num & 0xff) == num;
1252 fits_in_unsigned_word (offsetT num)
1254 return (num & 0xffff) == num;
1258 fits_in_signed_word (offsetT num)
1260 return (-32768 <= num) && (num <= 32767);
1264 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1269 return (!(((offsetT) -1 << 31) & num)
1270 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1272 } /* fits_in_signed_long() */
1275 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1280 return (num & (((offsetT) 2 << 31) - 1)) == num;
1282 } /* fits_in_unsigned_long() */
1284 static i386_operand_type
1285 smallest_imm_type (offsetT num)
1287 i386_operand_type t;
1290 t.bitfield.imm64 = 1;
1292 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1294 /* This code is disabled on the 486 because all the Imm1 forms
1295 in the opcode table are slower on the i486. They're the
1296 versions with the implicitly specified single-position
1297 displacement, which has another syntax if you really want to
1299 t.bitfield.imm1 = 1;
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm8s = 1;
1302 t.bitfield.imm16 = 1;
1303 t.bitfield.imm32 = 1;
1304 t.bitfield.imm32s = 1;
1306 else if (fits_in_signed_byte (num))
1308 t.bitfield.imm8 = 1;
1309 t.bitfield.imm8s = 1;
1310 t.bitfield.imm16 = 1;
1311 t.bitfield.imm32 = 1;
1312 t.bitfield.imm32s = 1;
1314 else if (fits_in_unsigned_byte (num))
1316 t.bitfield.imm8 = 1;
1317 t.bitfield.imm16 = 1;
1318 t.bitfield.imm32 = 1;
1319 t.bitfield.imm32s = 1;
1321 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1323 t.bitfield.imm16 = 1;
1324 t.bitfield.imm32 = 1;
1325 t.bitfield.imm32s = 1;
1327 else if (fits_in_signed_long (num))
1329 t.bitfield.imm32 = 1;
1330 t.bitfield.imm32s = 1;
1332 else if (fits_in_unsigned_long (num))
1333 t.bitfield.imm32 = 1;
1339 offset_in_range (offsetT val, int size)
1345 case 1: mask = ((addressT) 1 << 8) - 1; break;
1346 case 2: mask = ((addressT) 1 << 16) - 1; break;
1347 case 4: mask = ((addressT) 2 << 31) - 1; break;
1349 case 8: mask = ((addressT) 2 << 63) - 1; break;
1354 /* If BFD64, sign extend val. */
1355 if (!use_rela_relocations)
1356 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1357 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1359 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1361 char buf1[40], buf2[40];
1363 sprint_value (buf1, val);
1364 sprint_value (buf2, val & mask);
1365 as_warn (_("%s shortened to %s"), buf1, buf2);
1370 /* Returns 0 if attempting to add a prefix where one from the same
1371 class already exists, 1 if non rep/repne added, 2 if rep/repne
1374 add_prefix (unsigned int prefix)
1379 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1380 && flag_code == CODE_64BIT)
1382 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1383 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1384 && (prefix & (REX_R | REX_X | REX_B))))
1395 case CS_PREFIX_OPCODE:
1396 case DS_PREFIX_OPCODE:
1397 case ES_PREFIX_OPCODE:
1398 case FS_PREFIX_OPCODE:
1399 case GS_PREFIX_OPCODE:
1400 case SS_PREFIX_OPCODE:
1404 case REPNE_PREFIX_OPCODE:
1405 case REPE_PREFIX_OPCODE:
1408 case LOCK_PREFIX_OPCODE:
1416 case ADDR_PREFIX_OPCODE:
1420 case DATA_PREFIX_OPCODE:
1424 if (i.prefix[q] != 0)
1432 i.prefix[q] |= prefix;
1435 as_bad (_("same type of prefix used twice"));
1441 set_code_flag (int value)
1444 if (flag_code == CODE_64BIT)
1446 cpu_arch_flags.bitfield.cpu64 = 1;
1447 cpu_arch_flags.bitfield.cpuno64 = 0;
1448 cpu_arch_flags_not.bitfield.cpu64 = 0;
1449 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1453 cpu_arch_flags.bitfield.cpu64 = 0;
1454 cpu_arch_flags.bitfield.cpuno64 = 1;
1455 cpu_arch_flags_not.bitfield.cpu64 = 1;
1456 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1458 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1460 as_bad (_("64bit mode not supported on this CPU."));
1462 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1464 as_bad (_("32bit mode not supported on this CPU."));
1466 stackop_size = '\0';
1470 set_16bit_gcc_code_flag (int new_code_flag)
1472 flag_code = new_code_flag;
1473 if (flag_code != CODE_16BIT)
1475 cpu_arch_flags.bitfield.cpu64 = 0;
1476 cpu_arch_flags.bitfield.cpuno64 = 1;
1477 cpu_arch_flags_not.bitfield.cpu64 = 1;
1478 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1479 stackop_size = LONG_MNEM_SUFFIX;
1483 set_intel_syntax (int syntax_flag)
1485 /* Find out if register prefixing is specified. */
1486 int ask_naked_reg = 0;
1489 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1491 char *string = input_line_pointer;
1492 int e = get_symbol_end ();
1494 if (strcmp (string, "prefix") == 0)
1496 else if (strcmp (string, "noprefix") == 0)
1499 as_bad (_("bad argument to syntax directive."));
1500 *input_line_pointer = e;
1502 demand_empty_rest_of_line ();
1504 intel_syntax = syntax_flag;
1506 if (ask_naked_reg == 0)
1507 allow_naked_reg = (intel_syntax
1508 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1510 allow_naked_reg = (ask_naked_reg < 0);
1512 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1513 identifier_chars['$'] = intel_syntax ? '$' : 0;
1514 register_prefix = allow_naked_reg ? "" : "%";
1518 set_intel_mnemonic (int mnemonic_flag)
1520 /* Find out if register prefixing is specified. */
1521 int ask_naked_reg = 0;
1524 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1526 char *string = input_line_pointer;
1527 int e = get_symbol_end ();
1529 if (strcmp (string, "prefix") == 0)
1531 else if (strcmp (string, "noprefix") == 0)
1534 as_bad (_("bad argument to syntax directive."));
1535 *input_line_pointer = e;
1537 demand_empty_rest_of_line ();
1539 /* intel_mnemonic implies intel_syntax. */
1540 intel_mnemonic = intel_syntax = mnemonic_flag;
1542 if (ask_naked_reg == 0)
1543 allow_naked_reg = (intel_mnemonic
1544 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1546 allow_naked_reg = (ask_naked_reg < 0);
1548 identifier_chars['%'] = intel_mnemonic && allow_naked_reg ? '%' : 0;
1549 identifier_chars['$'] = intel_mnemonic ? '$' : 0;
1550 register_prefix = allow_naked_reg ? "" : "%";
1554 set_allow_index_reg (int flag)
1556 allow_index_reg = flag;
1560 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1564 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1566 char *string = input_line_pointer;
1567 int e = get_symbol_end ();
1569 i386_cpu_flags flags;
1571 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1573 if (strcmp (string, cpu_arch[i].name) == 0)
1577 cpu_arch_name = cpu_arch[i].name;
1578 cpu_sub_arch_name = NULL;
1579 cpu_arch_flags = cpu_arch[i].flags;
1580 if (flag_code == CODE_64BIT)
1582 cpu_arch_flags.bitfield.cpu64 = 1;
1583 cpu_arch_flags.bitfield.cpuno64 = 0;
1587 cpu_arch_flags.bitfield.cpu64 = 0;
1588 cpu_arch_flags.bitfield.cpuno64 = 1;
1590 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1591 cpu_arch_isa = cpu_arch[i].type;
1592 cpu_arch_isa_flags = cpu_arch[i].flags;
1593 if (!cpu_arch_tune_set)
1595 cpu_arch_tune = cpu_arch_isa;
1596 cpu_arch_tune_flags = cpu_arch_isa_flags;
1601 flags = cpu_flags_or (cpu_arch_flags,
1603 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1605 cpu_sub_arch_name = cpu_arch[i].name;
1606 cpu_arch_flags = flags;
1607 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1609 *input_line_pointer = e;
1610 demand_empty_rest_of_line ();
1614 if (i >= ARRAY_SIZE (cpu_arch))
1615 as_bad (_("no such architecture: `%s'"), string);
1617 *input_line_pointer = e;
1620 as_bad (_("missing cpu architecture"));
1622 no_cond_jump_promotion = 0;
1623 if (*input_line_pointer == ','
1624 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1626 char *string = ++input_line_pointer;
1627 int e = get_symbol_end ();
1629 if (strcmp (string, "nojumps") == 0)
1630 no_cond_jump_promotion = 1;
1631 else if (strcmp (string, "jumps") == 0)
1634 as_bad (_("no such architecture modifier: `%s'"), string);
1636 *input_line_pointer = e;
1639 demand_empty_rest_of_line ();
1645 if (!strcmp (default_arch, "x86_64"))
1646 return bfd_mach_x86_64;
1647 else if (!strcmp (default_arch, "i386"))
1648 return bfd_mach_i386_i386;
1650 as_fatal (_("Unknown architecture"));
1656 const char *hash_err;
1658 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1660 /* Initialize op_hash hash table. */
1661 op_hash = hash_new ();
1664 const template *optab;
1665 templates *core_optab;
1667 /* Setup for loop. */
1669 core_optab = (templates *) xmalloc (sizeof (templates));
1670 core_optab->start = optab;
1675 if (optab->name == NULL
1676 || strcmp (optab->name, (optab - 1)->name) != 0)
1678 /* different name --> ship out current template list;
1679 add to hash table; & begin anew. */
1680 core_optab->end = optab;
1681 hash_err = hash_insert (op_hash,
1686 as_fatal (_("Internal Error: Can't hash %s: %s"),
1690 if (optab->name == NULL)
1692 core_optab = (templates *) xmalloc (sizeof (templates));
1693 core_optab->start = optab;
1698 /* Initialize reg_hash hash table. */
1699 reg_hash = hash_new ();
1701 const reg_entry *regtab;
1702 unsigned int regtab_size = i386_regtab_size;
1704 for (regtab = i386_regtab; regtab_size--; regtab++)
1706 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1708 as_fatal (_("Internal Error: Can't hash %s: %s"),
1714 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1719 for (c = 0; c < 256; c++)
1724 mnemonic_chars[c] = c;
1725 register_chars[c] = c;
1726 operand_chars[c] = c;
1728 else if (ISLOWER (c))
1730 mnemonic_chars[c] = c;
1731 register_chars[c] = c;
1732 operand_chars[c] = c;
1734 else if (ISUPPER (c))
1736 mnemonic_chars[c] = TOLOWER (c);
1737 register_chars[c] = mnemonic_chars[c];
1738 operand_chars[c] = c;
1741 if (ISALPHA (c) || ISDIGIT (c))
1742 identifier_chars[c] = c;
1745 identifier_chars[c] = c;
1746 operand_chars[c] = c;
1751 identifier_chars['@'] = '@';
1754 identifier_chars['?'] = '?';
1755 operand_chars['?'] = '?';
1757 digit_chars['-'] = '-';
1758 mnemonic_chars['-'] = '-';
1759 mnemonic_chars['.'] = '.';
1760 identifier_chars['_'] = '_';
1761 identifier_chars['.'] = '.';
1763 for (p = operand_special_chars; *p != '\0'; p++)
1764 operand_chars[(unsigned char) *p] = *p;
1767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1770 record_alignment (text_section, 2);
1771 record_alignment (data_section, 2);
1772 record_alignment (bss_section, 2);
1776 if (flag_code == CODE_64BIT)
1778 x86_dwarf2_return_column = 16;
1779 x86_cie_data_alignment = -8;
1783 x86_dwarf2_return_column = 8;
1784 x86_cie_data_alignment = -4;
1789 i386_print_statistics (FILE *file)
1791 hash_print_statistics (file, "i386 opcode", op_hash);
1792 hash_print_statistics (file, "i386 register", reg_hash);
1797 /* Debugging routines for md_assemble. */
1798 static void pte (template *);
1799 static void pt (i386_operand_type);
1800 static void pe (expressionS *);
1801 static void ps (symbolS *);
1804 pi (char *line, i386_insn *x)
1808 fprintf (stdout, "%s: template ", line);
1810 fprintf (stdout, " address: base %s index %s scale %x\n",
1811 x->base_reg ? x->base_reg->reg_name : "none",
1812 x->index_reg ? x->index_reg->reg_name : "none",
1813 x->log2_scale_factor);
1814 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1815 x->rm.mode, x->rm.reg, x->rm.regmem);
1816 fprintf (stdout, " sib: base %x index %x scale %x\n",
1817 x->sib.base, x->sib.index, x->sib.scale);
1818 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1819 (x->rex & REX_W) != 0,
1820 (x->rex & REX_R) != 0,
1821 (x->rex & REX_X) != 0,
1822 (x->rex & REX_B) != 0);
1823 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1824 x->drex.reg, x->drex.rex);
1825 for (i = 0; i < x->operands; i++)
1827 fprintf (stdout, " #%d: ", i + 1);
1829 fprintf (stdout, "\n");
1830 if (x->types[i].bitfield.reg8
1831 || x->types[i].bitfield.reg16
1832 || x->types[i].bitfield.reg32
1833 || x->types[i].bitfield.reg64
1834 || x->types[i].bitfield.regmmx
1835 || x->types[i].bitfield.regxmm
1836 || x->types[i].bitfield.sreg2
1837 || x->types[i].bitfield.sreg3
1838 || x->types[i].bitfield.control
1839 || x->types[i].bitfield.debug
1840 || x->types[i].bitfield.test)
1841 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1842 if (operand_type_check (x->types[i], imm))
1844 if (operand_type_check (x->types[i], disp))
1845 pe (x->op[i].disps);
1853 fprintf (stdout, " %d operands ", t->operands);
1854 fprintf (stdout, "opcode %x ", t->base_opcode);
1855 if (t->extension_opcode != None)
1856 fprintf (stdout, "ext %x ", t->extension_opcode);
1857 if (t->opcode_modifier.d)
1858 fprintf (stdout, "D");
1859 if (t->opcode_modifier.w)
1860 fprintf (stdout, "W");
1861 fprintf (stdout, "\n");
1862 for (i = 0; i < t->operands; i++)
1864 fprintf (stdout, " #%d type ", i + 1);
1865 pt (t->operand_types[i]);
1866 fprintf (stdout, "\n");
1873 fprintf (stdout, " operation %d\n", e->X_op);
1874 fprintf (stdout, " add_number %ld (%lx)\n",
1875 (long) e->X_add_number, (long) e->X_add_number);
1876 if (e->X_add_symbol)
1878 fprintf (stdout, " add_symbol ");
1879 ps (e->X_add_symbol);
1880 fprintf (stdout, "\n");
1884 fprintf (stdout, " op_symbol ");
1885 ps (e->X_op_symbol);
1886 fprintf (stdout, "\n");
1893 fprintf (stdout, "%s type %s%s",
1895 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1896 segment_name (S_GET_SEGMENT (s)));
1899 static struct type_name
1901 i386_operand_type mask;
1904 const type_names[] =
1906 { OPERAND_TYPE_REG8, "r8" },
1907 { OPERAND_TYPE_REG16, "r16" },
1908 { OPERAND_TYPE_REG32, "r32" },
1909 { OPERAND_TYPE_REG64, "r64" },
1910 { OPERAND_TYPE_IMM8, "i8" },
1911 { OPERAND_TYPE_IMM8, "i8s" },
1912 { OPERAND_TYPE_IMM16, "i16" },
1913 { OPERAND_TYPE_IMM32, "i32" },
1914 { OPERAND_TYPE_IMM32S, "i32s" },
1915 { OPERAND_TYPE_IMM64, "i64" },
1916 { OPERAND_TYPE_IMM1, "i1" },
1917 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1918 { OPERAND_TYPE_DISP8, "d8" },
1919 { OPERAND_TYPE_DISP16, "d16" },
1920 { OPERAND_TYPE_DISP32, "d32" },
1921 { OPERAND_TYPE_DISP32S, "d32s" },
1922 { OPERAND_TYPE_DISP64, "d64" },
1923 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1924 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1925 { OPERAND_TYPE_CONTROL, "control reg" },
1926 { OPERAND_TYPE_TEST, "test reg" },
1927 { OPERAND_TYPE_DEBUG, "debug reg" },
1928 { OPERAND_TYPE_FLOATREG, "FReg" },
1929 { OPERAND_TYPE_FLOATACC, "FAcc" },
1930 { OPERAND_TYPE_SREG2, "SReg2" },
1931 { OPERAND_TYPE_SREG3, "SReg3" },
1932 { OPERAND_TYPE_ACC, "Acc" },
1933 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1934 { OPERAND_TYPE_REGMMX, "rMMX" },
1935 { OPERAND_TYPE_REGXMM, "rXMM" },
1936 { OPERAND_TYPE_ESSEG, "es" },
1940 pt (i386_operand_type t)
1943 i386_operand_type a;
1945 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1947 a = operand_type_and (t, type_names[j].mask);
1948 if (!UINTS_ALL_ZERO (a))
1949 fprintf (stdout, "%s, ", type_names[j].name);
1954 #endif /* DEBUG386 */
1956 static bfd_reloc_code_real_type
1957 reloc (unsigned int size,
1960 bfd_reloc_code_real_type other)
1962 if (other != NO_RELOC)
1964 reloc_howto_type *reloc;
1969 case BFD_RELOC_X86_64_GOT32:
1970 return BFD_RELOC_X86_64_GOT64;
1972 case BFD_RELOC_X86_64_PLTOFF64:
1973 return BFD_RELOC_X86_64_PLTOFF64;
1975 case BFD_RELOC_X86_64_GOTPC32:
1976 other = BFD_RELOC_X86_64_GOTPC64;
1978 case BFD_RELOC_X86_64_GOTPCREL:
1979 other = BFD_RELOC_X86_64_GOTPCREL64;
1981 case BFD_RELOC_X86_64_TPOFF32:
1982 other = BFD_RELOC_X86_64_TPOFF64;
1984 case BFD_RELOC_X86_64_DTPOFF32:
1985 other = BFD_RELOC_X86_64_DTPOFF64;
1991 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1992 if (size == 4 && flag_code != CODE_64BIT)
1995 reloc = bfd_reloc_type_lookup (stdoutput, other);
1997 as_bad (_("unknown relocation (%u)"), other);
1998 else if (size != bfd_get_reloc_size (reloc))
1999 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2000 bfd_get_reloc_size (reloc),
2002 else if (pcrel && !reloc->pc_relative)
2003 as_bad (_("non-pc-relative relocation for pc-relative field"));
2004 else if ((reloc->complain_on_overflow == complain_overflow_signed
2006 || (reloc->complain_on_overflow == complain_overflow_unsigned
2008 as_bad (_("relocated field and relocation type differ in signedness"));
2017 as_bad (_("there are no unsigned pc-relative relocations"));
2020 case 1: return BFD_RELOC_8_PCREL;
2021 case 2: return BFD_RELOC_16_PCREL;
2022 case 4: return BFD_RELOC_32_PCREL;
2023 case 8: return BFD_RELOC_64_PCREL;
2025 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2032 case 4: return BFD_RELOC_X86_64_32S;
2037 case 1: return BFD_RELOC_8;
2038 case 2: return BFD_RELOC_16;
2039 case 4: return BFD_RELOC_32;
2040 case 8: return BFD_RELOC_64;
2042 as_bad (_("cannot do %s %u byte relocation"),
2043 sign > 0 ? "signed" : "unsigned", size);
2047 return BFD_RELOC_NONE;
2050 /* Here we decide which fixups can be adjusted to make them relative to
2051 the beginning of the section instead of the symbol. Basically we need
2052 to make sure that the dynamic relocations are done correctly, so in
2053 some cases we force the original symbol to be used. */
2056 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2062 /* Don't adjust pc-relative references to merge sections in 64-bit
2064 if (use_rela_relocations
2065 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2069 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2070 and changed later by validate_fix. */
2071 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2072 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2075 /* adjust_reloc_syms doesn't know about the GOT. */
2076 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2077 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2078 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2079 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2080 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2081 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2082 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2083 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2084 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2085 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2086 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2087 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2088 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2089 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2090 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2091 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2092 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2093 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2094 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2095 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2096 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2097 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2098 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2099 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2100 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2101 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2102 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2103 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2110 intel_float_operand (const char *mnemonic)
2112 /* Note that the value returned is meaningful only for opcodes with (memory)
2113 operands, hence the code here is free to improperly handle opcodes that
2114 have no operands (for better performance and smaller code). */
2116 if (mnemonic[0] != 'f')
2117 return 0; /* non-math */
2119 switch (mnemonic[1])
2121 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2122 the fs segment override prefix not currently handled because no
2123 call path can make opcodes without operands get here */
2125 return 2 /* integer op */;
2127 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2128 return 3; /* fldcw/fldenv */
2131 if (mnemonic[2] != 'o' /* fnop */)
2132 return 3; /* non-waiting control op */
2135 if (mnemonic[2] == 's')
2136 return 3; /* frstor/frstpm */
2139 if (mnemonic[2] == 'a')
2140 return 3; /* fsave */
2141 if (mnemonic[2] == 't')
2143 switch (mnemonic[3])
2145 case 'c': /* fstcw */
2146 case 'd': /* fstdw */
2147 case 'e': /* fstenv */
2148 case 's': /* fsts[gw] */
2154 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2155 return 0; /* fxsave/fxrstor are not really math ops */
2162 /* This is the guts of the machine-dependent assembler. LINE points to a
2163 machine dependent instruction. This function is supposed to emit
2164 the frags/bytes it assembles to. */
2171 char mnemonic[MAX_MNEM_SIZE];
2173 /* Initialize globals. */
2174 memset (&i, '\0', sizeof (i));
2175 for (j = 0; j < MAX_OPERANDS; j++)
2176 i.reloc[j] = NO_RELOC;
2177 memset (disp_expressions, '\0', sizeof (disp_expressions));
2178 memset (im_expressions, '\0', sizeof (im_expressions));
2179 save_stack_p = save_stack;
2181 /* First parse an instruction mnemonic & call i386_operand for the operands.
2182 We assume that the scrubber has arranged it so that line[0] is the valid
2183 start of a (possibly prefixed) mnemonic. */
2185 line = parse_insn (line, mnemonic);
2189 line = parse_operands (line, mnemonic);
2193 /* Now we've parsed the mnemonic into a set of templates, and have the
2194 operands at hand. */
2196 /* All intel opcodes have reversed operands except for "bound" and
2197 "enter". We also don't reverse intersegment "jmp" and "call"
2198 instructions with 2 immediate operands so that the immediate segment
2199 precedes the offset, as it does when in AT&T mode. */
2202 && (strcmp (mnemonic, "bound") != 0)
2203 && (strcmp (mnemonic, "invlpga") != 0)
2204 && !(operand_type_check (i.types[0], imm)
2205 && operand_type_check (i.types[1], imm)))
2208 /* The order of the immediates should be reversed
2209 for 2 immediates extrq and insertq instructions */
2210 if (i.imm_operands == 2
2211 && (strcmp (mnemonic, "extrq") == 0
2212 || strcmp (mnemonic, "insertq") == 0))
2213 swap_2_operands (0, 1);
2218 /* Don't optimize displacement for movabs since it only takes 64bit
2221 && (flag_code != CODE_64BIT
2222 || strcmp (mnemonic, "movabs") != 0))
2225 /* Next, we find a template that matches the given insn,
2226 making sure the overlap of the given operands types is consistent
2227 with the template operand types. */
2229 if (!match_template ())
2234 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2236 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
2237 i.tm.base_opcode ^= Opcode_FloatR;
2239 /* Zap movzx and movsx suffix. The suffix may have been set from
2240 "word ptr" or "byte ptr" on the source operand, but we'll use
2241 the suffix later to choose the destination register. */
2242 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2244 if (i.reg_operands < 2
2246 && (!i.tm.opcode_modifier.no_bsuf
2247 || !i.tm.opcode_modifier.no_wsuf
2248 || !i.tm.opcode_modifier.no_lsuf
2249 || !i.tm.opcode_modifier.no_ssuf
2250 || !i.tm.opcode_modifier.no_ldsuf
2251 || !i.tm.opcode_modifier.no_qsuf))
2252 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2258 if (i.tm.opcode_modifier.fwait)
2259 if (!add_prefix (FWAIT_OPCODE))
2262 /* Check string instruction segment overrides. */
2263 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2265 if (!check_string ())
2269 if (!process_suffix ())
2272 /* Make still unresolved immediate matches conform to size of immediate
2273 given in i.suffix. */
2274 if (!finalize_imm ())
2277 if (i.types[0].bitfield.imm1)
2278 i.imm_operands = 0; /* kludge for shift insns. */
2280 for (j = 0; j < 3; j++)
2281 if (i.types[j].bitfield.inoutportreg
2282 || i.types[j].bitfield.shiftcount
2283 || i.types[j].bitfield.acc
2284 || i.types[j].bitfield.floatacc)
2287 if (i.tm.opcode_modifier.immext)
2291 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2293 /* Streaming SIMD extensions 3 Instructions have the fixed
2294 operands with an opcode suffix which is coded in the same
2295 place as an 8-bit immediate field would be. Here we check
2296 those operands and remove them afterwards. */
2299 for (x = 0; x < i.operands; x++)
2300 if (i.op[x].regs->reg_num != x)
2301 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2303 i.op[x].regs->reg_name,
2309 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2310 opcode suffix which is coded in the same place as an 8-bit
2311 immediate field would be. Here we fake an 8-bit immediate
2312 operand from the opcode suffix stored in tm.extension_opcode.
2313 SSE5 also uses this encoding, for some of its 3 argument
2316 assert (i.imm_operands == 0
2318 || (i.tm.cpu_flags.bitfield.cpusse5
2319 && i.operands <= 3)));
2321 exp = &im_expressions[i.imm_operands++];
2322 i.op[i.operands].imms = exp;
2323 UINTS_CLEAR (i.types[i.operands]);
2324 i.types[i.operands].bitfield.imm8 = 1;
2326 exp->X_op = O_constant;
2327 exp->X_add_number = i.tm.extension_opcode;
2328 i.tm.extension_opcode = None;
2331 /* For insns with operands there are more diddles to do to the opcode. */
2334 if (!process_operands ())
2337 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2339 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2340 as_warn (_("translating to `%sp'"), i.tm.name);
2343 /* Handle conversion of 'int $3' --> special int3 insn. */
2344 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2346 i.tm.base_opcode = INT3_OPCODE;
2350 if ((i.tm.opcode_modifier.jump
2351 || i.tm.opcode_modifier.jumpbyte
2352 || i.tm.opcode_modifier.jumpdword)
2353 && i.op[0].disps->X_op == O_constant)
2355 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2356 the absolute address given by the constant. Since ix86 jumps and
2357 calls are pc relative, we need to generate a reloc. */
2358 i.op[0].disps->X_add_symbol = &abs_symbol;
2359 i.op[0].disps->X_op = O_symbol;
2362 if (i.tm.opcode_modifier.rex64)
2365 /* For 8 bit registers we need an empty rex prefix. Also if the
2366 instruction already has a prefix, we need to convert old
2367 registers to new ones. */
2369 if ((i.types[0].bitfield.reg8
2370 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2371 || (i.types[1].bitfield.reg8
2372 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2373 || ((i.types[0].bitfield.reg8
2374 || i.types[1].bitfield.reg8)
2379 i.rex |= REX_OPCODE;
2380 for (x = 0; x < 2; x++)
2382 /* Look for 8 bit operand that uses old registers. */
2383 if (i.types[x].bitfield.reg8
2384 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2386 /* In case it is "hi" register, give up. */
2387 if (i.op[x].regs->reg_num > 3)
2388 as_bad (_("can't encode register '%s%s' in an "
2389 "instruction requiring REX prefix."),
2390 register_prefix, i.op[x].regs->reg_name);
2392 /* Otherwise it is equivalent to the extended register.
2393 Since the encoding doesn't change this is merely
2394 cosmetic cleanup for debug output. */
2396 i.op[x].regs = i.op[x].regs + 8;
2401 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2403 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2408 else if (i.rex != 0)
2409 add_prefix (REX_OPCODE | i.rex);
2411 /* We are ready to output the insn. */
2416 parse_insn (char *line, char *mnemonic)
2419 char *token_start = l;
2424 /* Non-zero if we found a prefix only acceptable with string insns. */
2425 const char *expecting_string_instruction = NULL;
2430 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2433 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2435 as_bad (_("no such instruction: `%s'"), token_start);
2440 if (!is_space_char (*l)
2441 && *l != END_OF_INSN
2443 || (*l != PREFIX_SEPARATOR
2446 as_bad (_("invalid character %s in mnemonic"),
2447 output_invalid (*l));
2450 if (token_start == l)
2452 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2453 as_bad (_("expecting prefix; got nothing"));
2455 as_bad (_("expecting mnemonic; got nothing"));
2459 /* Look up instruction (or prefix) via hash table. */
2460 current_templates = hash_find (op_hash, mnemonic);
2462 if (*l != END_OF_INSN
2463 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2464 && current_templates
2465 && current_templates->start->opcode_modifier.isprefix)
2467 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2469 as_bad ((flag_code != CODE_64BIT
2470 ? _("`%s' is only supported in 64-bit mode")
2471 : _("`%s' is not supported in 64-bit mode")),
2472 current_templates->start->name);
2475 /* If we are in 16-bit mode, do not allow addr16 or data16.
2476 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2477 if ((current_templates->start->opcode_modifier.size16
2478 || current_templates->start->opcode_modifier.size32)
2479 && flag_code != CODE_64BIT
2480 && (current_templates->start->opcode_modifier.size32
2481 ^ (flag_code == CODE_16BIT)))
2483 as_bad (_("redundant %s prefix"),
2484 current_templates->start->name);
2487 /* Add prefix, checking for repeated prefixes. */
2488 switch (add_prefix (current_templates->start->base_opcode))
2493 expecting_string_instruction = current_templates->start->name;
2496 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2503 if (!current_templates)
2505 /* See if we can get a match by trimming off a suffix. */
2508 case WORD_MNEM_SUFFIX:
2509 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2510 i.suffix = SHORT_MNEM_SUFFIX;
2512 case BYTE_MNEM_SUFFIX:
2513 case QWORD_MNEM_SUFFIX:
2514 i.suffix = mnem_p[-1];
2516 current_templates = hash_find (op_hash, mnemonic);
2518 case SHORT_MNEM_SUFFIX:
2519 case LONG_MNEM_SUFFIX:
2522 i.suffix = mnem_p[-1];
2524 current_templates = hash_find (op_hash, mnemonic);
2532 if (intel_float_operand (mnemonic) == 1)
2533 i.suffix = SHORT_MNEM_SUFFIX;
2535 i.suffix = LONG_MNEM_SUFFIX;
2537 current_templates = hash_find (op_hash, mnemonic);
2541 if (!current_templates)
2543 as_bad (_("no such instruction: `%s'"), token_start);
2548 if (current_templates->start->opcode_modifier.jump
2549 || current_templates->start->opcode_modifier.jumpbyte)
2551 /* Check for a branch hint. We allow ",pt" and ",pn" for
2552 predict taken and predict not taken respectively.
2553 I'm not sure that branch hints actually do anything on loop
2554 and jcxz insns (JumpByte) for current Pentium4 chips. They
2555 may work in the future and it doesn't hurt to accept them
2557 if (l[0] == ',' && l[1] == 'p')
2561 if (!add_prefix (DS_PREFIX_OPCODE))
2565 else if (l[2] == 'n')
2567 if (!add_prefix (CS_PREFIX_OPCODE))
2573 /* Any other comma loses. */
2576 as_bad (_("invalid character %s in mnemonic"),
2577 output_invalid (*l));
2581 /* Check if instruction is supported on specified architecture. */
2583 for (t = current_templates->start; t < current_templates->end; ++t)
2585 if (cpu_flags_match (t->cpu_flags))
2587 if (cpu_flags_check_cpu64 (t->cpu_flags))
2590 if (!(supported & 2))
2592 as_bad (flag_code == CODE_64BIT
2593 ? _("`%s' is not supported in 64-bit mode")
2594 : _("`%s' is only supported in 64-bit mode"),
2595 current_templates->start->name);
2598 if (!(supported & 1))
2600 as_warn (_("`%s' is not supported on `%s%s'"),
2601 current_templates->start->name,
2603 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2605 else if (!cpu_arch_flags.bitfield.cpui386
2606 && (flag_code != CODE_16BIT))
2608 as_warn (_("use .code16 to ensure correct addressing mode"));
2611 /* Check for rep/repne without a string instruction. */
2612 if (expecting_string_instruction)
2614 static templates override;
2616 for (t = current_templates->start; t < current_templates->end; ++t)
2617 if (t->opcode_modifier.isstring)
2619 if (t >= current_templates->end)
2621 as_bad (_("expecting string instruction after `%s'"),
2622 expecting_string_instruction);
2625 for (override.start = t; t < current_templates->end; ++t)
2626 if (!t->opcode_modifier.isstring)
2629 current_templates = &override;
2636 parse_operands (char *l, const char *mnemonic)
2640 /* 1 if operand is pending after ','. */
2641 unsigned int expecting_operand = 0;
2643 /* Non-zero if operand parens not balanced. */
2644 unsigned int paren_not_balanced;
2646 while (*l != END_OF_INSN)
2648 /* Skip optional white space before operand. */
2649 if (is_space_char (*l))
2651 if (!is_operand_char (*l) && *l != END_OF_INSN)
2653 as_bad (_("invalid character %s before operand %d"),
2654 output_invalid (*l),
2658 token_start = l; /* after white space */
2659 paren_not_balanced = 0;
2660 while (paren_not_balanced || *l != ',')
2662 if (*l == END_OF_INSN)
2664 if (paren_not_balanced)
2667 as_bad (_("unbalanced parenthesis in operand %d."),
2670 as_bad (_("unbalanced brackets in operand %d."),
2675 break; /* we are done */
2677 else if (!is_operand_char (*l) && !is_space_char (*l))
2679 as_bad (_("invalid character %s in operand %d"),
2680 output_invalid (*l),
2687 ++paren_not_balanced;
2689 --paren_not_balanced;
2694 ++paren_not_balanced;
2696 --paren_not_balanced;
2700 if (l != token_start)
2701 { /* Yes, we've read in another operand. */
2702 unsigned int operand_ok;
2703 this_operand = i.operands++;
2704 if (i.operands > MAX_OPERANDS)
2706 as_bad (_("spurious operands; (%d operands/instruction max)"),
2710 /* Now parse operand adding info to 'i' as we go along. */
2711 END_STRING_AND_SAVE (l);
2715 i386_intel_operand (token_start,
2716 intel_float_operand (mnemonic));
2718 operand_ok = i386_operand (token_start);
2720 RESTORE_END_STRING (l);
2726 if (expecting_operand)
2728 expecting_operand_after_comma:
2729 as_bad (_("expecting operand after ','; got nothing"));
2734 as_bad (_("expecting operand before ','; got nothing"));
2739 /* Now *l must be either ',' or END_OF_INSN. */
2742 if (*++l == END_OF_INSN)
2744 /* Just skip it, if it's \n complain. */
2745 goto expecting_operand_after_comma;
2747 expecting_operand = 1;
2754 swap_2_operands (int xchg1, int xchg2)
2756 union i386_op temp_op;
2757 i386_operand_type temp_type;
2758 enum bfd_reloc_code_real temp_reloc;
2760 temp_type = i.types[xchg2];
2761 i.types[xchg2] = i.types[xchg1];
2762 i.types[xchg1] = temp_type;
2763 temp_op = i.op[xchg2];
2764 i.op[xchg2] = i.op[xchg1];
2765 i.op[xchg1] = temp_op;
2766 temp_reloc = i.reloc[xchg2];
2767 i.reloc[xchg2] = i.reloc[xchg1];
2768 i.reloc[xchg1] = temp_reloc;
2772 swap_operands (void)
2777 swap_2_operands (1, i.operands - 2);
2780 swap_2_operands (0, i.operands - 1);
2786 if (i.mem_operands == 2)
2788 const seg_entry *temp_seg;
2789 temp_seg = i.seg[0];
2790 i.seg[0] = i.seg[1];
2791 i.seg[1] = temp_seg;
2795 /* Try to ensure constant immediates are represented in the smallest
2800 char guess_suffix = 0;
2804 guess_suffix = i.suffix;
2805 else if (i.reg_operands)
2807 /* Figure out a suffix from the last register operand specified.
2808 We can't do this properly yet, ie. excluding InOutPortReg,
2809 but the following works for instructions with immediates.
2810 In any case, we can't set i.suffix yet. */
2811 for (op = i.operands; --op >= 0;)
2812 if (i.types[op].bitfield.reg8)
2814 guess_suffix = BYTE_MNEM_SUFFIX;
2817 else if (i.types[op].bitfield.reg16)
2819 guess_suffix = WORD_MNEM_SUFFIX;
2822 else if (i.types[op].bitfield.reg32)
2824 guess_suffix = LONG_MNEM_SUFFIX;
2827 else if (i.types[op].bitfield.reg64)
2829 guess_suffix = QWORD_MNEM_SUFFIX;
2833 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2834 guess_suffix = WORD_MNEM_SUFFIX;
2836 for (op = i.operands; --op >= 0;)
2837 if (operand_type_check (i.types[op], imm))
2839 switch (i.op[op].imms->X_op)
2842 /* If a suffix is given, this operand may be shortened. */
2843 switch (guess_suffix)
2845 case LONG_MNEM_SUFFIX:
2846 i.types[op].bitfield.imm32 = 1;
2847 i.types[op].bitfield.imm64 = 1;
2849 case WORD_MNEM_SUFFIX:
2850 i.types[op].bitfield.imm16 = 1;
2851 i.types[op].bitfield.imm32 = 1;
2852 i.types[op].bitfield.imm32s = 1;
2853 i.types[op].bitfield.imm64 = 1;
2855 case BYTE_MNEM_SUFFIX:
2856 i.types[op].bitfield.imm8 = 1;
2857 i.types[op].bitfield.imm8s = 1;
2858 i.types[op].bitfield.imm16 = 1;
2859 i.types[op].bitfield.imm32 = 1;
2860 i.types[op].bitfield.imm32s = 1;
2861 i.types[op].bitfield.imm64 = 1;
2865 /* If this operand is at most 16 bits, convert it
2866 to a signed 16 bit number before trying to see
2867 whether it will fit in an even smaller size.
2868 This allows a 16-bit operand such as $0xffe0 to
2869 be recognised as within Imm8S range. */
2870 if ((i.types[op].bitfield.imm16)
2871 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2873 i.op[op].imms->X_add_number =
2874 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2876 if ((i.types[op].bitfield.imm32)
2877 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2880 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2881 ^ ((offsetT) 1 << 31))
2882 - ((offsetT) 1 << 31));
2885 = operand_type_or (i.types[op],
2886 smallest_imm_type (i.op[op].imms->X_add_number));
2888 /* We must avoid matching of Imm32 templates when 64bit
2889 only immediate is available. */
2890 if (guess_suffix == QWORD_MNEM_SUFFIX)
2891 i.types[op].bitfield.imm32 = 0;
2898 /* Symbols and expressions. */
2900 /* Convert symbolic operand to proper sizes for matching, but don't
2901 prevent matching a set of insns that only supports sizes other
2902 than those matching the insn suffix. */
2904 i386_operand_type mask, allowed;
2908 UINTS_CLEAR (allowed);
2910 for (t = current_templates->start;
2911 t < current_templates->end;
2913 allowed = operand_type_or (allowed,
2914 t->operand_types[op]);
2915 switch (guess_suffix)
2917 case QWORD_MNEM_SUFFIX:
2918 mask.bitfield.imm64 = 1;
2919 mask.bitfield.imm32s = 1;
2921 case LONG_MNEM_SUFFIX:
2922 mask.bitfield.imm32 = 1;
2924 case WORD_MNEM_SUFFIX:
2925 mask.bitfield.imm16 = 1;
2927 case BYTE_MNEM_SUFFIX:
2928 mask.bitfield.imm8 = 1;
2933 allowed = operand_type_and (mask, allowed);
2934 if (!UINTS_ALL_ZERO (allowed))
2935 i.types[op] = operand_type_and (i.types[op], mask);
2942 /* Try to use the smallest displacement type too. */
2944 optimize_disp (void)
2948 for (op = i.operands; --op >= 0;)
2949 if (operand_type_check (i.types[op], disp))
2951 if (i.op[op].disps->X_op == O_constant)
2953 offsetT disp = i.op[op].disps->X_add_number;
2955 if (i.types[op].bitfield.disp16
2956 && (disp & ~(offsetT) 0xffff) == 0)
2958 /* If this operand is at most 16 bits, convert
2959 to a signed 16 bit number and don't use 64bit
2961 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2962 i.types[op].bitfield.disp64 = 0;
2964 if (i.types[op].bitfield.disp32
2965 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2967 /* If this operand is at most 32 bits, convert
2968 to a signed 32 bit number and don't use 64bit
2970 disp &= (((offsetT) 2 << 31) - 1);
2971 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2972 i.types[op].bitfield.disp64 = 0;
2974 if (!disp && i.types[op].bitfield.baseindex)
2976 i.types[op].bitfield.disp8 = 0;
2977 i.types[op].bitfield.disp16 = 0;
2978 i.types[op].bitfield.disp32 = 0;
2979 i.types[op].bitfield.disp32s = 0;
2980 i.types[op].bitfield.disp64 = 0;
2984 else if (flag_code == CODE_64BIT)
2986 if (fits_in_signed_long (disp))
2988 i.types[op].bitfield.disp64 = 0;
2989 i.types[op].bitfield.disp32s = 1;
2991 if (fits_in_unsigned_long (disp))
2992 i.types[op].bitfield.disp32 = 1;
2994 if ((i.types[op].bitfield.disp32
2995 || i.types[op].bitfield.disp32s
2996 || i.types[op].bitfield.disp16)
2997 && fits_in_signed_byte (disp))
2998 i.types[op].bitfield.disp8 = 1;
3000 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3001 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3003 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3004 i.op[op].disps, 0, i.reloc[op]);
3005 i.types[op].bitfield.disp8 = 0;
3006 i.types[op].bitfield.disp16 = 0;
3007 i.types[op].bitfield.disp32 = 0;
3008 i.types[op].bitfield.disp32s = 0;
3009 i.types[op].bitfield.disp64 = 0;
3012 /* We only support 64bit displacement on constants. */
3013 i.types[op].bitfield.disp64 = 0;
3018 match_template (void)
3020 /* Points to template once we've found it. */
3022 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3023 unsigned int found_reverse_match;
3024 i386_opcode_modifier suffix_check;
3025 i386_operand_type operand_types [MAX_OPERANDS];
3026 int addr_prefix_disp;
3028 i386_cpu_flags overlap;
3030 #if MAX_OPERANDS != 4
3031 # error "MAX_OPERANDS must be 4."
3034 found_reverse_match = 0;
3035 addr_prefix_disp = -1;
3037 memset (&suffix_check, 0, sizeof (suffix_check));
3038 if (i.suffix == BYTE_MNEM_SUFFIX)
3039 suffix_check.no_bsuf = 1;
3040 else if (i.suffix == WORD_MNEM_SUFFIX)
3041 suffix_check.no_wsuf = 1;
3042 else if (i.suffix == SHORT_MNEM_SUFFIX)
3043 suffix_check.no_ssuf = 1;
3044 else if (i.suffix == LONG_MNEM_SUFFIX)
3045 suffix_check.no_lsuf = 1;
3046 else if (i.suffix == QWORD_MNEM_SUFFIX)
3047 suffix_check.no_qsuf = 1;
3048 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3049 suffix_check.no_ldsuf = 1;
3051 for (t = current_templates->start; t < current_templates->end; t++)
3053 addr_prefix_disp = -1;
3055 /* Must have right number of operands. */
3056 if (i.operands != t->operands)
3059 /* Check AT&T mnemonic and old gcc support. */
3060 if (t->opcode_modifier.attmnemonic
3063 && t->opcode_modifier.oldgcc)))
3066 /* Check Intel mnemonic. */
3067 if (!intel_mnemonic && t->opcode_modifier.intelmnemonic)
3070 /* Check the suffix, except for some instructions in intel mode. */
3071 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3072 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3073 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3074 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3075 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3076 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3077 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3080 for (j = 0; j < MAX_OPERANDS; j++)
3081 operand_types [j] = t->operand_types [j];
3083 /* In general, don't allow 64-bit operands in 32-bit mode. */
3084 if (i.suffix == QWORD_MNEM_SUFFIX
3085 && flag_code != CODE_64BIT
3087 ? (!t->opcode_modifier.ignoresize
3088 && !intel_float_operand (t->name))
3089 : intel_float_operand (t->name) != 2)
3090 && ((!operand_types[0].bitfield.regmmx
3091 && !operand_types[0].bitfield.regxmm)
3092 || (!operand_types[t->operands > 1].bitfield.regmmx
3093 && !!operand_types[t->operands > 1].bitfield.regxmm))
3094 && (t->base_opcode != 0x0fc7
3095 || t->extension_opcode != 1 /* cmpxchg8b */))
3098 /* Do not verify operands when there are none. */
3101 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3104 if (!UINTS_ALL_ZERO (overlap))
3106 /* We've found a match; break out of loop. */
3111 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3112 into Disp32/Disp16/Disp32 operand. */
3113 if (i.prefix[ADDR_PREFIX] != 0)
3115 /* There should be only one Disp operand. */
3119 for (j = 0; j < MAX_OPERANDS; j++)
3121 if (operand_types[j].bitfield.disp16)
3123 addr_prefix_disp = j;
3124 operand_types[j].bitfield.disp32 = 1;
3125 operand_types[j].bitfield.disp16 = 0;
3131 for (j = 0; j < MAX_OPERANDS; j++)
3133 if (operand_types[j].bitfield.disp32)
3135 addr_prefix_disp = j;
3136 operand_types[j].bitfield.disp32 = 0;
3137 operand_types[j].bitfield.disp16 = 1;
3143 for (j = 0; j < MAX_OPERANDS; j++)
3145 if (operand_types[j].bitfield.disp64)
3147 addr_prefix_disp = j;
3148 operand_types[j].bitfield.disp64 = 0;
3149 operand_types[j].bitfield.disp32 = 1;
3157 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3158 switch (t->operands)
3161 if (!operand_type_match (overlap0, i.types[0]))
3165 /* xchg %eax, %eax is a special case. It is an aliase for nop
3166 only in 32bit mode and we can use opcode 0x90. In 64bit
3167 mode, we can't use 0x90 for xchg %eax, %eax since it should
3168 zero-extend %eax to %rax. */
3169 if (flag_code == CODE_64BIT
3170 && t->base_opcode == 0x90
3171 && UINTS_EQUAL (i.types [0], acc32)
3172 && UINTS_EQUAL (i.types [1], acc32))
3176 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3177 if (!operand_type_match (overlap0, i.types[0])
3178 || !operand_type_match (overlap1, i.types[1])
3179 /* monitor in SSE3 is a very special case. The first
3180 register and the second register may have different
3181 sizes. The same applies to crc32 in SSE4.2. It is
3182 also true for invlpga, vmload, vmrun and vmsave in
3184 || !((t->base_opcode == 0x0f01
3185 && (t->extension_opcode == 0xc8
3186 || t->extension_opcode == 0xd8
3187 || t->extension_opcode == 0xda
3188 || t->extension_opcode == 0xdb
3189 || t->extension_opcode == 0xdf))
3190 || t->base_opcode == 0xf20f38f1
3191 || operand_type_register_match (overlap0, i.types[0],
3193 overlap1, i.types[1],
3196 /* Check if other direction is valid ... */
3197 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3200 /* Try reversing direction of operands. */
3201 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3202 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3203 if (!operand_type_match (overlap0, i.types[0])
3204 || !operand_type_match (overlap1, i.types[1])
3205 || !operand_type_register_match (overlap0, i.types[0],
3207 overlap1, i.types[1],
3210 /* Does not match either direction. */
3213 /* found_reverse_match holds which of D or FloatDR
3215 if (t->opcode_modifier.d)
3216 found_reverse_match = Opcode_D;
3217 else if (t->opcode_modifier.floatd)
3218 found_reverse_match = Opcode_FloatD;
3220 found_reverse_match = 0;
3221 if (t->opcode_modifier.floatr)
3222 found_reverse_match |= Opcode_FloatR;
3226 /* Found a forward 2 operand match here. */
3227 switch (t->operands)
3230 overlap3 = operand_type_and (i.types[3],
3233 overlap2 = operand_type_and (i.types[2],
3238 switch (t->operands)
3241 if (!operand_type_match (overlap3, i.types[3])
3242 || !operand_type_register_match (overlap2,
3250 /* Here we make use of the fact that there are no
3251 reverse match 3 operand instructions, and all 3
3252 operand instructions only need to be checked for
3253 register consistency between operands 2 and 3. */
3254 if (!operand_type_match (overlap2, i.types[2])
3255 || !operand_type_register_match (overlap1,
3265 /* Found either forward/reverse 2, 3 or 4 operand match here:
3266 slip through to break. */
3268 if (!UINTS_ALL_ZERO (overlap))
3270 found_reverse_match = 0;
3273 /* We've found a match; break out of loop. */
3277 if (t == current_templates->end)
3279 /* We found no match. */
3280 as_bad (_("suffix or operands invalid for `%s'"),
3281 current_templates->start->name);
3285 if (!quiet_warnings)
3288 && (i.types[0].bitfield.jumpabsolute
3289 != operand_types[0].bitfield.jumpabsolute))
3291 as_warn (_("indirect %s without `*'"), t->name);
3294 if (t->opcode_modifier.isprefix
3295 && t->opcode_modifier.ignoresize)
3297 /* Warn them that a data or address size prefix doesn't
3298 affect assembly of the next line of code. */
3299 as_warn (_("stand-alone `%s' prefix"), t->name);
3303 /* Copy the template we found. */
3306 if (addr_prefix_disp != -1)
3307 i.tm.operand_types[addr_prefix_disp]
3308 = operand_types[addr_prefix_disp];
3310 if (found_reverse_match)
3312 /* If we found a reverse match we must alter the opcode
3313 direction bit. found_reverse_match holds bits to change
3314 (different for int & float insns). */
3316 i.tm.base_opcode ^= found_reverse_match;
3318 i.tm.operand_types[0] = operand_types[1];
3319 i.tm.operand_types[1] = operand_types[0];
3328 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3329 if (i.tm.operand_types[mem_op].bitfield.esseg)
3331 if (i.seg[0] != NULL && i.seg[0] != &es)
3333 as_bad (_("`%s' operand %d must use `%%es' segment"),
3338 /* There's only ever one segment override allowed per instruction.
3339 This instruction possibly has a legal segment override on the
3340 second operand, so copy the segment to where non-string
3341 instructions store it, allowing common code. */
3342 i.seg[0] = i.seg[1];
3344 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3346 if (i.seg[1] != NULL && i.seg[1] != &es)
3348 as_bad (_("`%s' operand %d must use `%%es' segment"),
3358 process_suffix (void)
3360 /* If matched instruction specifies an explicit instruction mnemonic
3362 if (i.tm.opcode_modifier.size16)
3363 i.suffix = WORD_MNEM_SUFFIX;
3364 else if (i.tm.opcode_modifier.size32)
3365 i.suffix = LONG_MNEM_SUFFIX;
3366 else if (i.tm.opcode_modifier.size64)
3367 i.suffix = QWORD_MNEM_SUFFIX;
3368 else if (i.reg_operands)
3370 /* If there's no instruction mnemonic suffix we try to invent one
3371 based on register operands. */
3374 /* We take i.suffix from the last register operand specified,
3375 Destination register type is more significant than source
3376 register type. crc32 in SSE4.2 prefers source register
3378 if (i.tm.base_opcode == 0xf20f38f1)
3380 if (i.types[0].bitfield.reg16)
3381 i.suffix = WORD_MNEM_SUFFIX;
3382 else if (i.types[0].bitfield.reg32)
3383 i.suffix = LONG_MNEM_SUFFIX;
3384 else if (i.types[0].bitfield.reg64)
3385 i.suffix = QWORD_MNEM_SUFFIX;
3387 else if (i.tm.base_opcode == 0xf20f38f0)
3389 if (i.types[0].bitfield.reg8)
3390 i.suffix = BYTE_MNEM_SUFFIX;
3397 if (i.tm.base_opcode == 0xf20f38f1
3398 || i.tm.base_opcode == 0xf20f38f0)
3400 /* We have to know the operand size for crc32. */
3401 as_bad (_("ambiguous memory operand size for `%s`"),
3406 for (op = i.operands; --op >= 0;)
3407 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3409 if (i.types[op].bitfield.reg8)
3411 i.suffix = BYTE_MNEM_SUFFIX;
3414 else if (i.types[op].bitfield.reg16)
3416 i.suffix = WORD_MNEM_SUFFIX;
3419 else if (i.types[op].bitfield.reg32)
3421 i.suffix = LONG_MNEM_SUFFIX;
3424 else if (i.types[op].bitfield.reg64)
3426 i.suffix = QWORD_MNEM_SUFFIX;
3432 else if (i.suffix == BYTE_MNEM_SUFFIX)
3434 if (!check_byte_reg ())
3437 else if (i.suffix == LONG_MNEM_SUFFIX)
3439 if (!check_long_reg ())
3442 else if (i.suffix == QWORD_MNEM_SUFFIX)
3445 && i.tm.opcode_modifier.ignoresize
3446 && i.tm.opcode_modifier.no_qsuf)
3448 else if (!check_qword_reg ())
3451 else if (i.suffix == WORD_MNEM_SUFFIX)
3453 if (!check_word_reg ())
3456 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3457 /* Do nothing if the instruction is going to ignore the prefix. */
3462 else if (i.tm.opcode_modifier.defaultsize
3464 /* exclude fldenv/frstor/fsave/fstenv */
3465 && i.tm.opcode_modifier.no_ssuf)
3467 i.suffix = stackop_size;
3469 else if (intel_syntax
3471 && (i.tm.operand_types[0].bitfield.jumpabsolute
3472 || i.tm.opcode_modifier.jumpbyte
3473 || i.tm.opcode_modifier.jumpintersegment
3474 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3475 && i.tm.extension_opcode <= 3)))
3480 if (!i.tm.opcode_modifier.no_qsuf)
3482 i.suffix = QWORD_MNEM_SUFFIX;
3486 if (!i.tm.opcode_modifier.no_lsuf)
3487 i.suffix = LONG_MNEM_SUFFIX;
3490 if (!i.tm.opcode_modifier.no_wsuf)
3491 i.suffix = WORD_MNEM_SUFFIX;
3500 if (i.tm.opcode_modifier.w)
3502 as_bad (_("no instruction mnemonic suffix given and "
3503 "no register operands; can't size instruction"));
3509 unsigned int suffixes;
3511 suffixes = !i.tm.opcode_modifier.no_bsuf;
3512 if (!i.tm.opcode_modifier.no_wsuf)
3514 if (!i.tm.opcode_modifier.no_lsuf)
3516 if (!i.tm.opcode_modifier.no_lsuf)
3518 if (!i.tm.opcode_modifier.no_ssuf)
3520 if (!i.tm.opcode_modifier.no_qsuf)
3523 /* There are more than suffix matches. */
3524 if (i.tm.opcode_modifier.w
3525 || ((suffixes & (suffixes - 1))
3526 && !i.tm.opcode_modifier.defaultsize
3527 && !i.tm.opcode_modifier.ignoresize))
3529 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3535 /* Change the opcode based on the operand size given by i.suffix;
3536 We don't need to change things for byte insns. */
3538 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3540 /* It's not a byte, select word/dword operation. */
3541 if (i.tm.opcode_modifier.w)
3543 if (i.tm.opcode_modifier.shortform)
3544 i.tm.base_opcode |= 8;
3546 i.tm.base_opcode |= 1;
3549 /* Now select between word & dword operations via the operand
3550 size prefix, except for instructions that will ignore this
3552 if (i.tm.opcode_modifier.addrprefixop0)
3554 /* The address size override prefix changes the size of the
3556 if ((flag_code == CODE_32BIT
3557 && i.op->regs[0].reg_type.bitfield.reg16)
3558 || (flag_code != CODE_32BIT
3559 && i.op->regs[0].reg_type.bitfield.reg32))
3560 if (!add_prefix (ADDR_PREFIX_OPCODE))
3563 else if (i.suffix != QWORD_MNEM_SUFFIX
3564 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3565 && !i.tm.opcode_modifier.ignoresize
3566 && !i.tm.opcode_modifier.floatmf
3567 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3568 || (flag_code == CODE_64BIT
3569 && i.tm.opcode_modifier.jumpbyte)))
3571 unsigned int prefix = DATA_PREFIX_OPCODE;
3573 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3574 prefix = ADDR_PREFIX_OPCODE;
3576 if (!add_prefix (prefix))
3580 /* Set mode64 for an operand. */
3581 if (i.suffix == QWORD_MNEM_SUFFIX
3582 && flag_code == CODE_64BIT
3583 && !i.tm.opcode_modifier.norex64)
3585 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3586 need rex64. cmpxchg8b is also a special case. */
3587 if (! (i.operands == 2
3588 && i.tm.base_opcode == 0x90
3589 && i.tm.extension_opcode == None
3590 && UINTS_EQUAL (i.types [0], acc64)
3591 && UINTS_EQUAL (i.types [1], acc64))
3592 && ! (i.operands == 1
3593 && i.tm.base_opcode == 0xfc7
3594 && i.tm.extension_opcode == 1
3595 && !operand_type_check (i.types [0], reg)
3596 && operand_type_check (i.types [0], anymem)))
3600 /* Size floating point instruction. */
3601 if (i.suffix == LONG_MNEM_SUFFIX)
3602 if (i.tm.opcode_modifier.floatmf)
3603 i.tm.base_opcode ^= 4;
3610 check_byte_reg (void)
3614 for (op = i.operands; --op >= 0;)
3616 /* If this is an eight bit register, it's OK. If it's the 16 or
3617 32 bit version of an eight bit register, we will just use the
3618 low portion, and that's OK too. */
3619 if (i.types[op].bitfield.reg8)
3622 /* Don't generate this warning if not needed. */
3623 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3626 /* crc32 doesn't generate this warning. */
3627 if (i.tm.base_opcode == 0xf20f38f0)
3630 if ((i.types[op].bitfield.reg16
3631 || i.types[op].bitfield.reg32
3632 || i.types[op].bitfield.reg64)
3633 && i.op[op].regs->reg_num < 4)
3635 /* Prohibit these changes in the 64bit mode, since the
3636 lowering is more complicated. */
3637 if (flag_code == CODE_64BIT
3638 && !i.tm.operand_types[op].bitfield.inoutportreg)
3640 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3641 register_prefix, i.op[op].regs->reg_name,
3645 #if REGISTER_WARNINGS
3647 && !i.tm.operand_types[op].bitfield.inoutportreg)
3648 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3650 (i.op[op].regs + (i.types[op].bitfield.reg16
3651 ? REGNAM_AL - REGNAM_AX
3652 : REGNAM_AL - REGNAM_EAX))->reg_name,
3654 i.op[op].regs->reg_name,
3659 /* Any other register is bad. */
3660 if (i.types[op].bitfield.reg16
3661 || i.types[op].bitfield.reg32
3662 || i.types[op].bitfield.reg64
3663 || i.types[op].bitfield.regmmx
3664 || i.types[op].bitfield.regxmm
3665 || i.types[op].bitfield.sreg2
3666 || i.types[op].bitfield.sreg3
3667 || i.types[op].bitfield.control
3668 || i.types[op].bitfield.debug
3669 || i.types[op].bitfield.test
3670 || i.types[op].bitfield.floatreg
3671 || i.types[op].bitfield.floatacc)
3673 as_bad (_("`%s%s' not allowed with `%s%c'"),
3675 i.op[op].regs->reg_name,
3685 check_long_reg (void)
3689 for (op = i.operands; --op >= 0;)
3690 /* Reject eight bit registers, except where the template requires
3691 them. (eg. movzb) */
3692 if (i.types[op].bitfield.reg8
3693 && (i.tm.operand_types[op].bitfield.reg16
3694 || i.tm.operand_types[op].bitfield.reg32
3695 || i.tm.operand_types[op].bitfield.acc))
3697 as_bad (_("`%s%s' not allowed with `%s%c'"),
3699 i.op[op].regs->reg_name,
3704 /* Warn if the e prefix on a general reg is missing. */
3705 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3706 && i.types[op].bitfield.reg16
3707 && (i.tm.operand_types[op].bitfield.reg32
3708 || i.tm.operand_types[op].bitfield.acc))
3710 /* Prohibit these changes in the 64bit mode, since the
3711 lowering is more complicated. */
3712 if (flag_code == CODE_64BIT)
3714 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3715 register_prefix, i.op[op].regs->reg_name,
3719 #if REGISTER_WARNINGS
3721 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3723 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3725 i.op[op].regs->reg_name,
3729 /* Warn if the r prefix on a general reg is missing. */
3730 else if (i.types[op].bitfield.reg64
3731 && (i.tm.operand_types[op].bitfield.reg32
3732 || i.tm.operand_types[op].bitfield.acc))
3735 && i.tm.opcode_modifier.toqword
3736 && !i.types[0].bitfield.regxmm)
3738 /* Convert to QWORD. We want REX byte. */
3739 i.suffix = QWORD_MNEM_SUFFIX;
3743 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3744 register_prefix, i.op[op].regs->reg_name,
3753 check_qword_reg (void)
3757 for (op = i.operands; --op >= 0; )
3758 /* Reject eight bit registers, except where the template requires
3759 them. (eg. movzb) */
3760 if (i.types[op].bitfield.reg8
3761 && (i.tm.operand_types[op].bitfield.reg16
3762 || i.tm.operand_types[op].bitfield.reg32
3763 || i.tm.operand_types[op].bitfield.acc))
3765 as_bad (_("`%s%s' not allowed with `%s%c'"),
3767 i.op[op].regs->reg_name,
3772 /* Warn if the e prefix on a general reg is missing. */
3773 else if ((i.types[op].bitfield.reg16
3774 || i.types[op].bitfield.reg32)
3775 && (i.tm.operand_types[op].bitfield.reg32
3776 || i.tm.operand_types[op].bitfield.acc))
3778 /* Prohibit these changes in the 64bit mode, since the
3779 lowering is more complicated. */
3781 && i.tm.opcode_modifier.todword
3782 && !i.types[0].bitfield.regxmm)
3784 /* Convert to DWORD. We don't want REX byte. */
3785 i.suffix = LONG_MNEM_SUFFIX;
3789 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3790 register_prefix, i.op[op].regs->reg_name,
3799 check_word_reg (void)
3802 for (op = i.operands; --op >= 0;)
3803 /* Reject eight bit registers, except where the template requires
3804 them. (eg. movzb) */
3805 if (i.types[op].bitfield.reg8
3806 && (i.tm.operand_types[op].bitfield.reg16
3807 || i.tm.operand_types[op].bitfield.reg32
3808 || i.tm.operand_types[op].bitfield.acc))
3810 as_bad (_("`%s%s' not allowed with `%s%c'"),
3812 i.op[op].regs->reg_name,
3817 /* Warn if the e prefix on a general reg is present. */
3818 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3819 && i.types[op].bitfield.reg32
3820 && (i.tm.operand_types[op].bitfield.reg16
3821 || i.tm.operand_types[op].bitfield.acc))
3823 /* Prohibit these changes in the 64bit mode, since the
3824 lowering is more complicated. */
3825 if (flag_code == CODE_64BIT)
3827 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3828 register_prefix, i.op[op].regs->reg_name,
3833 #if REGISTER_WARNINGS
3834 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3836 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3838 i.op[op].regs->reg_name,
3846 update_imm (unsigned int j)
3848 i386_operand_type overlap;
3850 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3851 if ((overlap.bitfield.imm8
3852 || overlap.bitfield.imm8s
3853 || overlap.bitfield.imm16
3854 || overlap.bitfield.imm32
3855 || overlap.bitfield.imm32s
3856 || overlap.bitfield.imm64)
3857 && !UINTS_EQUAL (overlap, imm8)
3858 && !UINTS_EQUAL (overlap, imm8s)
3859 && !UINTS_EQUAL (overlap, imm16)
3860 && !UINTS_EQUAL (overlap, imm32)
3861 && !UINTS_EQUAL (overlap, imm32s)
3862 && !UINTS_EQUAL (overlap, imm64))
3866 i386_operand_type temp;
3869 if (i.suffix == BYTE_MNEM_SUFFIX)
3871 temp.bitfield.imm8 = overlap.bitfield.imm8;
3872 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3874 else if (i.suffix == WORD_MNEM_SUFFIX)
3875 temp.bitfield.imm16 = overlap.bitfield.imm16;
3876 else if (i.suffix == QWORD_MNEM_SUFFIX)
3878 temp.bitfield.imm64 = overlap.bitfield.imm64;
3879 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3882 temp.bitfield.imm32 = overlap.bitfield.imm32;
3885 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3886 || UINTS_EQUAL (overlap, imm16_32)
3887 || UINTS_EQUAL (overlap, imm16_32s))
3889 UINTS_CLEAR (overlap);
3890 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3891 overlap.bitfield.imm16 = 1;
3893 overlap.bitfield.imm32s = 1;
3895 if (!UINTS_EQUAL (overlap, imm8)
3896 && !UINTS_EQUAL (overlap, imm8s)
3897 && !UINTS_EQUAL (overlap, imm16)
3898 && !UINTS_EQUAL (overlap, imm32)
3899 && !UINTS_EQUAL (overlap, imm32s)
3900 && !UINTS_EQUAL (overlap, imm64))
3902 as_bad (_("no instruction mnemonic suffix given; "
3903 "can't determine immediate size"));
3907 i.types[j] = overlap;
3917 for (j = 0; j < 2; j++)
3918 if (update_imm (j) == 0)
3921 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3922 assert (operand_type_check (i.types[2], imm) == 0);
3930 i.drex.modrm_reg = None;
3931 i.drex.modrm_regmem = None;
3933 /* SSE5 4 operand instructions must have the destination the same as
3934 one of the inputs. Figure out the destination register and cache
3935 it away in the drex field, and remember which fields to use for
3937 if (i.tm.opcode_modifier.drex
3938 && i.tm.opcode_modifier.drexv
3941 i.tm.extension_opcode = None;
3943 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3944 if (i.types[0].bitfield.regxmm != 0
3945 && i.types[1].bitfield.regxmm != 0
3946 && i.types[2].bitfield.regxmm != 0
3947 && i.types[3].bitfield.regxmm != 0
3948 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3949 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3951 /* Clear the arguments that are stored in drex. */
3952 UINTS_CLEAR (i.types[0]);
3953 UINTS_CLEAR (i.types[3]);
3954 i.reg_operands -= 2;
3956 /* There are two different ways to encode a 4 operand
3957 instruction with all registers that uses OC1 set to
3958 0 or 1. Favor setting OC1 to 0 since this mimics the
3959 actions of other SSE5 assemblers. Use modrm encoding 2
3960 for register/register. Include the high order bit that
3961 is normally stored in the REX byte in the register
3963 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3964 i.drex.modrm_reg = 2;
3965 i.drex.modrm_regmem = 1;
3966 i.drex.reg = (i.op[3].regs->reg_num
3967 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3970 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3971 else if (i.types[0].bitfield.regxmm != 0
3972 && i.types[1].bitfield.regxmm != 0
3973 && (i.types[2].bitfield.regxmm
3974 || operand_type_check (i.types[2], anymem))
3975 && i.types[3].bitfield.regxmm != 0
3976 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3977 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3979 /* clear the arguments that are stored in drex */
3980 UINTS_CLEAR (i.types[0]);
3981 UINTS_CLEAR (i.types[3]);
3982 i.reg_operands -= 2;
3984 /* Specify the modrm encoding for memory addressing. Include
3985 the high order bit that is normally stored in the REX byte
3986 in the register field. */
3987 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3988 i.drex.modrm_reg = 1;
3989 i.drex.modrm_regmem = 2;
3990 i.drex.reg = (i.op[3].regs->reg_num
3991 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3994 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3995 else if (i.types[0].bitfield.regxmm != 0
3996 && operand_type_check (i.types[1], anymem) != 0
3997 && i.types[2].bitfield.regxmm != 0
3998 && i.types[3].bitfield.regxmm != 0
3999 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4000 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4002 /* Clear the arguments that are stored in drex. */
4003 UINTS_CLEAR (i.types[0]);
4004 UINTS_CLEAR (i.types[3]);
4005 i.reg_operands -= 2;
4007 /* Specify the modrm encoding for memory addressing. Include
4008 the high order bit that is normally stored in the REX byte
4009 in the register field. */
4010 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4011 i.drex.modrm_reg = 2;
4012 i.drex.modrm_regmem = 1;
4013 i.drex.reg = (i.op[3].regs->reg_num
4014 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4017 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4018 else if (i.types[0].bitfield.regxmm != 0
4019 && i.types[1].bitfield.regxmm != 0
4020 && i.types[2].bitfield.regxmm != 0
4021 && i.types[3].bitfield.regxmm != 0
4022 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4023 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4025 /* clear the arguments that are stored in drex */
4026 UINTS_CLEAR (i.types[2]);
4027 UINTS_CLEAR (i.types[3]);
4028 i.reg_operands -= 2;
4030 /* There are two different ways to encode a 4 operand
4031 instruction with all registers that uses OC1 set to
4032 0 or 1. Favor setting OC1 to 0 since this mimics the
4033 actions of other SSE5 assemblers. Use modrm encoding
4034 2 for register/register. Include the high order bit that
4035 is normally stored in the REX byte in the register
4037 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4038 i.drex.modrm_reg = 1;
4039 i.drex.modrm_regmem = 0;
4041 /* Remember the register, including the upper bits */
4042 i.drex.reg = (i.op[3].regs->reg_num
4043 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4046 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4047 else if (i.types[0].bitfield.regxmm != 0
4048 && (i.types[1].bitfield.regxmm
4049 || operand_type_check (i.types[1], anymem))
4050 && i.types[2].bitfield.regxmm != 0
4051 && i.types[3].bitfield.regxmm != 0
4052 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4053 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4055 /* Clear the arguments that are stored in drex. */
4056 UINTS_CLEAR (i.types[2]);
4057 UINTS_CLEAR (i.types[3]);
4058 i.reg_operands -= 2;
4060 /* Specify the modrm encoding and remember the register
4061 including the bits normally stored in the REX byte. */
4062 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4063 i.drex.modrm_reg = 0;
4064 i.drex.modrm_regmem = 1;
4065 i.drex.reg = (i.op[3].regs->reg_num
4066 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4069 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4070 else if (operand_type_check (i.types[0], anymem) != 0
4071 && i.types[1].bitfield.regxmm != 0
4072 && i.types[2].bitfield.regxmm != 0
4073 && i.types[3].bitfield.regxmm != 0
4074 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4075 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4077 /* clear the arguments that are stored in drex */
4078 UINTS_CLEAR (i.types[2]);
4079 UINTS_CLEAR (i.types[3]);
4080 i.reg_operands -= 2;
4082 /* Specify the modrm encoding and remember the register
4083 including the bits normally stored in the REX byte. */
4084 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4085 i.drex.modrm_reg = 1;
4086 i.drex.modrm_regmem = 0;
4087 i.drex.reg = (i.op[3].regs->reg_num
4088 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4092 as_bad (_("Incorrect operands for the '%s' instruction"),
4096 /* SSE5 instructions with the DREX byte where the only memory operand
4097 is in the 2nd argument, and the first and last xmm register must
4098 match, and is encoded in the DREX byte. */
4099 else if (i.tm.opcode_modifier.drex
4100 && !i.tm.opcode_modifier.drexv
4103 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4104 if (i.types[0].bitfield.regxmm != 0
4105 && (i.types[1].bitfield.regxmm
4106 || operand_type_check(i.types[1], anymem))
4107 && i.types[2].bitfield.regxmm != 0
4108 && i.types[3].bitfield.regxmm != 0
4109 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4110 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4112 /* clear the arguments that are stored in drex */
4113 UINTS_CLEAR (i.types[0]);
4114 UINTS_CLEAR (i.types[3]);
4115 i.reg_operands -= 2;
4117 /* Specify the modrm encoding and remember the register
4118 including the high bit normally stored in the REX
4120 i.drex.modrm_reg = 2;
4121 i.drex.modrm_regmem = 1;
4122 i.drex.reg = (i.op[3].regs->reg_num
4123 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4127 as_bad (_("Incorrect operands for the '%s' instruction"),
4131 /* SSE5 3 operand instructions that the result is a register, being
4132 either operand can be a memory operand, using OC0 to note which
4133 one is the memory. */
4134 else if (i.tm.opcode_modifier.drex
4135 && i.tm.opcode_modifier.drexv
4138 i.tm.extension_opcode = None;
4140 /* Case 1: 3 operand insn, src1 = register. */
4141 if (i.types[0].bitfield.regxmm != 0
4142 && i.types[1].bitfield.regxmm != 0
4143 && i.types[2].bitfield.regxmm != 0)
4145 /* Clear the arguments that are stored in drex. */
4146 UINTS_CLEAR (i.types[2]);
4149 /* Specify the modrm encoding and remember the register
4150 including the high bit normally stored in the REX byte. */
4151 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4152 i.drex.modrm_reg = 1;
4153 i.drex.modrm_regmem = 0;
4154 i.drex.reg = (i.op[2].regs->reg_num
4155 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4158 /* Case 2: 3 operand insn, src1 = memory. */
4159 else if (operand_type_check (i.types[0], anymem) != 0
4160 && i.types[1].bitfield.regxmm != 0
4161 && i.types[2].bitfield.regxmm != 0)
4163 /* Clear the arguments that are stored in drex. */
4164 UINTS_CLEAR (i.types[2]);
4167 /* Specify the modrm encoding and remember the register
4168 including the high bit normally stored in the REX
4170 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4171 i.drex.modrm_reg = 1;
4172 i.drex.modrm_regmem = 0;
4173 i.drex.reg = (i.op[2].regs->reg_num
4174 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4177 /* Case 3: 3 operand insn, src2 = memory. */
4178 else if (i.types[0].bitfield.regxmm != 0
4179 && operand_type_check (i.types[1], anymem) != 0
4180 && i.types[2].bitfield.regxmm != 0)
4182 /* Clear the arguments that are stored in drex. */
4183 UINTS_CLEAR (i.types[2]);
4186 /* Specify the modrm encoding and remember the register
4187 including the high bit normally stored in the REX byte. */
4188 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4189 i.drex.modrm_reg = 0;
4190 i.drex.modrm_regmem = 1;
4191 i.drex.reg = (i.op[2].regs->reg_num
4192 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4196 as_bad (_("Incorrect operands for the '%s' instruction"),
4200 /* SSE5 4 operand instructions that are the comparison instructions
4201 where the first operand is the immediate value of the comparison
4203 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4205 /* Case 1: 4 operand insn, src1 = reg/memory. */
4206 if (operand_type_check (i.types[0], imm) != 0
4207 && (i.types[1].bitfield.regxmm
4208 || operand_type_check (i.types[1], anymem))
4209 && i.types[2].bitfield.regxmm != 0
4210 && i.types[3].bitfield.regxmm != 0)
4212 /* clear the arguments that are stored in drex */
4213 UINTS_CLEAR (i.types[3]);
4216 /* Specify the modrm encoding and remember the register
4217 including the high bit normally stored in the REX byte. */
4218 i.drex.modrm_reg = 2;
4219 i.drex.modrm_regmem = 1;
4220 i.drex.reg = (i.op[3].regs->reg_num
4221 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4224 /* Case 2: 3 operand insn with ImmExt that places the
4225 opcode_extension as an immediate argument. This is used for
4226 all of the varients of comparison that supplies the appropriate
4227 value as part of the instruction. */
4228 else if ((i.types[0].bitfield.regxmm
4229 || operand_type_check (i.types[0], anymem))
4230 && i.types[1].bitfield.regxmm != 0
4231 && i.types[2].bitfield.regxmm != 0
4232 && operand_type_check (i.types[3], imm) != 0)
4234 /* clear the arguments that are stored in drex */
4235 UINTS_CLEAR (i.types[2]);
4238 /* Specify the modrm encoding and remember the register
4239 including the high bit normally stored in the REX byte. */
4240 i.drex.modrm_reg = 1;
4241 i.drex.modrm_regmem = 0;
4242 i.drex.reg = (i.op[2].regs->reg_num
4243 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4247 as_bad (_("Incorrect operands for the '%s' instruction"),
4251 else if (i.tm.opcode_modifier.drex
4252 || i.tm.opcode_modifier.drexv
4253 || i.tm.opcode_modifier.drexc)
4254 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4258 process_operands (void)
4260 /* Default segment register this instruction will use for memory
4261 accesses. 0 means unknown. This is only for optimizing out
4262 unnecessary segment overrides. */
4263 const seg_entry *default_seg = 0;
4265 /* Handle all of the DREX munging that SSE5 needs. */
4266 if (i.tm.opcode_modifier.drex
4267 || i.tm.opcode_modifier.drexv
4268 || i.tm.opcode_modifier.drexc)
4271 if (i.tm.opcode_modifier.firstxmm0)
4275 /* The first operand is implicit and must be xmm0. */
4276 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4277 if (i.op[0].regs->reg_num != 0)
4280 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4281 i.tm.name, register_prefix);
4283 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4284 i.tm.name, register_prefix);
4288 for (j = 1; j < i.operands; j++)
4290 i.op[j - 1] = i.op[j];
4291 i.types[j - 1] = i.types[j];
4293 /* We need to adjust fields in i.tm since they are used by
4294 build_modrm_byte. */
4295 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4302 else if (i.tm.opcode_modifier.regkludge)
4304 /* The imul $imm, %reg instruction is converted into
4305 imul $imm, %reg, %reg, and the clr %reg instruction
4306 is converted into xor %reg, %reg. */
4308 unsigned int first_reg_op;
4310 if (operand_type_check (i.types[0], reg))
4314 /* Pretend we saw the extra register operand. */
4315 assert (i.reg_operands == 1
4316 && i.op[first_reg_op + 1].regs == 0);
4317 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4318 i.types[first_reg_op + 1] = i.types[first_reg_op];
4323 if (i.tm.opcode_modifier.shortform)
4325 if (i.types[0].bitfield.sreg2
4326 || i.types[0].bitfield.sreg3)
4328 if (i.tm.base_opcode == POP_SEG_SHORT
4329 && i.op[0].regs->reg_num == 1)
4331 as_bad (_("you can't `pop %%cs'"));
4334 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4335 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4340 /* The register or float register operand is in operand
4344 if (i.types[0].bitfield.floatreg
4345 || operand_type_check (i.types[0], reg))
4349 /* Register goes in low 3 bits of opcode. */
4350 i.tm.base_opcode |= i.op[op].regs->reg_num;
4351 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4353 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4355 /* Warn about some common errors, but press on regardless.
4356 The first case can be generated by gcc (<= 2.8.1). */
4357 if (i.operands == 2)
4359 /* Reversed arguments on faddp, fsubp, etc. */
4360 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4361 register_prefix, i.op[1].regs->reg_name,
4362 register_prefix, i.op[0].regs->reg_name);
4366 /* Extraneous `l' suffix on fp insn. */
4367 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4368 register_prefix, i.op[0].regs->reg_name);
4373 else if (i.tm.opcode_modifier.modrm)
4375 /* The opcode is completed (modulo i.tm.extension_opcode which
4376 must be put into the modrm byte). Now, we make the modrm and
4377 index base bytes based on all the info we've collected. */
4379 default_seg = build_modrm_byte ();
4381 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4385 else if (i.tm.opcode_modifier.isstring)
4387 /* For the string instructions that allow a segment override
4388 on one of their operands, the default segment is ds. */
4392 if (i.tm.base_opcode == 0x8d /* lea */
4395 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4397 /* If a segment was explicitly specified, and the specified segment
4398 is not the default, use an opcode prefix to select it. If we
4399 never figured out what the default segment is, then default_seg
4400 will be zero at this point, and the specified segment prefix will
4402 if ((i.seg[0]) && (i.seg[0] != default_seg))
4404 if (!add_prefix (i.seg[0]->seg_prefix))
4410 static const seg_entry *
4411 build_modrm_byte (void)
4413 const seg_entry *default_seg = 0;
4415 /* SSE5 4 operand instructions are encoded in such a way that one of
4416 the inputs must match the destination register. Process_drex hides
4417 the 3rd argument in the drex field, so that by the time we get
4418 here, it looks to GAS as if this is a 2 operand instruction. */
4419 if ((i.tm.opcode_modifier.drex
4420 || i.tm.opcode_modifier.drexv
4421 || i.tm.opcode_modifier.drexc)
4422 && i.reg_operands == 2)
4424 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4425 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4427 i.rm.reg = reg->reg_num;
4428 i.rm.regmem = regmem->reg_num;
4430 if ((reg->reg_flags & RegRex) != 0)
4432 if ((regmem->reg_flags & RegRex) != 0)
4436 /* i.reg_operands MUST be the number of real register operands;
4437 implicit registers do not count. */
4438 else if (i.reg_operands == 2)
4440 unsigned int source, dest;
4448 /* When there are 3 operands, one of them may be immediate,
4449 which may be the first or the last operand. Otherwise,
4450 the first operand must be shift count register (cl). */
4451 assert (i.imm_operands == 1
4452 || (i.imm_operands == 0
4453 && i.types[0].bitfield.shiftcount));
4454 if (operand_type_check (i.types[0], imm)
4455 || i.types[0].bitfield.shiftcount)
4461 /* When there are 4 operands, the first two must be 8bit
4462 immediate operands. The source operand will be the 3rd
4464 assert (i.imm_operands == 2
4465 && i.types[0].bitfield.imm8
4466 && i.types[1].bitfield.imm8);
4476 /* One of the register operands will be encoded in the i.tm.reg
4477 field, the other in the combined i.tm.mode and i.tm.regmem
4478 fields. If no form of this instruction supports a memory
4479 destination operand, then we assume the source operand may
4480 sometimes be a memory operand and so we need to store the
4481 destination in the i.rm.reg field. */
4482 if (!i.tm.operand_types[dest].bitfield.regmem
4483 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4485 i.rm.reg = i.op[dest].regs->reg_num;
4486 i.rm.regmem = i.op[source].regs->reg_num;
4487 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4489 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4494 i.rm.reg = i.op[source].regs->reg_num;
4495 i.rm.regmem = i.op[dest].regs->reg_num;
4496 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4498 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4501 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4503 if (!i.types[0].bitfield.control
4504 && !i.types[1].bitfield.control)
4506 i.rex &= ~(REX_R | REX_B);
4507 add_prefix (LOCK_PREFIX_OPCODE);
4511 { /* If it's not 2 reg operands... */
4514 unsigned int fake_zero_displacement = 0;
4517 /* This has been precalculated for SSE5 instructions
4518 that have a DREX field earlier in process_drex. */
4519 if (i.tm.opcode_modifier.drex
4520 || i.tm.opcode_modifier.drexv
4521 || i.tm.opcode_modifier.drexc)
4522 op = i.drex.modrm_regmem;
4525 for (op = 0; op < i.operands; op++)
4526 if (operand_type_check (i.types[op], anymem))
4528 assert (op < i.operands);
4533 if (i.base_reg == 0)
4536 if (!i.disp_operands)
4537 fake_zero_displacement = 1;
4538 if (i.index_reg == 0)
4540 /* Operand is just <disp> */
4541 if (flag_code == CODE_64BIT)
4543 /* 64bit mode overwrites the 32bit absolute
4544 addressing by RIP relative addressing and
4545 absolute addressing is encoded by one of the
4546 redundant SIB forms. */
4547 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4548 i.sib.base = NO_BASE_REGISTER;
4549 i.sib.index = NO_INDEX_REGISTER;
4550 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4551 ? disp32s : disp32);
4553 else if ((flag_code == CODE_16BIT)
4554 ^ (i.prefix[ADDR_PREFIX] != 0))
4556 i.rm.regmem = NO_BASE_REGISTER_16;
4557 i.types[op] = disp16;
4561 i.rm.regmem = NO_BASE_REGISTER;
4562 i.types[op] = disp32;
4565 else /* !i.base_reg && i.index_reg */
4567 if (i.index_reg->reg_num == RegEiz
4568 || i.index_reg->reg_num == RegRiz)
4569 i.sib.index = NO_INDEX_REGISTER;
4571 i.sib.index = i.index_reg->reg_num;
4572 i.sib.base = NO_BASE_REGISTER;
4573 i.sib.scale = i.log2_scale_factor;
4574 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4575 i.types[op].bitfield.disp8 = 0;
4576 i.types[op].bitfield.disp16 = 0;
4577 i.types[op].bitfield.disp64 = 0;
4578 if (flag_code != CODE_64BIT)
4580 /* Must be 32 bit */
4581 i.types[op].bitfield.disp32 = 1;
4582 i.types[op].bitfield.disp32s = 0;
4586 i.types[op].bitfield.disp32 = 0;
4587 i.types[op].bitfield.disp32s = 1;
4589 if ((i.index_reg->reg_flags & RegRex) != 0)
4593 /* RIP addressing for 64bit mode. */
4594 else if (i.base_reg->reg_num == RegRip ||
4595 i.base_reg->reg_num == RegEip)
4597 i.rm.regmem = NO_BASE_REGISTER;
4598 i.types[op].bitfield.disp8 = 0;
4599 i.types[op].bitfield.disp16 = 0;
4600 i.types[op].bitfield.disp32 = 0;
4601 i.types[op].bitfield.disp32s = 1;
4602 i.types[op].bitfield.disp64 = 0;
4603 i.flags[op] |= Operand_PCrel;
4604 if (! i.disp_operands)
4605 fake_zero_displacement = 1;
4607 else if (i.base_reg->reg_type.bitfield.reg16)
4609 switch (i.base_reg->reg_num)
4612 if (i.index_reg == 0)
4614 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4615 i.rm.regmem = i.index_reg->reg_num - 6;
4619 if (i.index_reg == 0)
4622 if (operand_type_check (i.types[op], disp) == 0)
4624 /* fake (%bp) into 0(%bp) */
4625 i.types[op].bitfield.disp8 = 1;
4626 fake_zero_displacement = 1;
4629 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4630 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4632 default: /* (%si) -> 4 or (%di) -> 5 */
4633 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4635 i.rm.mode = mode_from_disp_size (i.types[op]);
4637 else /* i.base_reg and 32/64 bit mode */
4639 if (flag_code == CODE_64BIT
4640 && operand_type_check (i.types[op], disp))
4642 i386_operand_type temp;
4644 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4646 if (i.prefix[ADDR_PREFIX] == 0)
4647 i.types[op].bitfield.disp32s = 1;
4649 i.types[op].bitfield.disp32 = 1;
4652 i.rm.regmem = i.base_reg->reg_num;
4653 if ((i.base_reg->reg_flags & RegRex) != 0)
4655 i.sib.base = i.base_reg->reg_num;
4656 /* x86-64 ignores REX prefix bit here to avoid decoder
4658 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4661 if (i.disp_operands == 0)
4663 fake_zero_displacement = 1;
4664 i.types[op].bitfield.disp8 = 1;
4667 else if (i.base_reg->reg_num == ESP_REG_NUM)
4671 i.sib.scale = i.log2_scale_factor;
4672 if (i.index_reg == 0)
4674 /* <disp>(%esp) becomes two byte modrm with no index
4675 register. We've already stored the code for esp
4676 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4677 Any base register besides %esp will not use the
4678 extra modrm byte. */
4679 i.sib.index = NO_INDEX_REGISTER;
4683 if (i.index_reg->reg_num == RegEiz
4684 || i.index_reg->reg_num == RegRiz)
4685 i.sib.index = NO_INDEX_REGISTER;
4687 i.sib.index = i.index_reg->reg_num;
4688 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4689 if ((i.index_reg->reg_flags & RegRex) != 0)
4694 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4695 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4698 i.rm.mode = mode_from_disp_size (i.types[op]);
4701 if (fake_zero_displacement)
4703 /* Fakes a zero displacement assuming that i.types[op]
4704 holds the correct displacement size. */
4707 assert (i.op[op].disps == 0);
4708 exp = &disp_expressions[i.disp_operands++];
4709 i.op[op].disps = exp;
4710 exp->X_op = O_constant;
4711 exp->X_add_number = 0;
4712 exp->X_add_symbol = (symbolS *) 0;
4713 exp->X_op_symbol = (symbolS *) 0;
4717 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4718 (if any) based on i.tm.extension_opcode. Again, we must be
4719 careful to make sure that segment/control/debug/test/MMX
4720 registers are coded into the i.rm.reg field. */
4725 /* This has been precalculated for SSE5 instructions
4726 that have a DREX field earlier in process_drex. */
4727 if (i.tm.opcode_modifier.drex
4728 || i.tm.opcode_modifier.drexv
4729 || i.tm.opcode_modifier.drexc)
4731 op = i.drex.modrm_reg;
4732 i.rm.reg = i.op[op].regs->reg_num;
4733 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4738 for (op = 0; op < i.operands; op++)
4739 if (i.types[op].bitfield.reg8
4740 || i.types[op].bitfield.reg16
4741 || i.types[op].bitfield.reg32
4742 || i.types[op].bitfield.reg64
4743 || i.types[op].bitfield.regmmx
4744 || i.types[op].bitfield.regxmm
4745 || i.types[op].bitfield.sreg2
4746 || i.types[op].bitfield.sreg3
4747 || i.types[op].bitfield.control
4748 || i.types[op].bitfield.debug
4749 || i.types[op].bitfield.test)
4752 assert (op < i.operands);
4754 /* If there is an extension opcode to put here, the
4755 register number must be put into the regmem field. */
4756 if (i.tm.extension_opcode != None)
4758 i.rm.regmem = i.op[op].regs->reg_num;
4759 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4764 i.rm.reg = i.op[op].regs->reg_num;
4765 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4770 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4771 must set it to 3 to indicate this is a register operand
4772 in the regmem field. */
4773 if (!i.mem_operands)
4777 /* Fill in i.rm.reg field with extension opcode (if any). */
4778 if (i.tm.extension_opcode != None
4779 && !(i.tm.opcode_modifier.drex
4780 || i.tm.opcode_modifier.drexv
4781 || i.tm.opcode_modifier.drexc))
4782 i.rm.reg = i.tm.extension_opcode;
4788 output_branch (void)
4793 relax_substateT subtype;
4798 if (flag_code == CODE_16BIT)
4802 if (i.prefix[DATA_PREFIX] != 0)
4808 /* Pentium4 branch hints. */
4809 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4810 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4815 if (i.prefix[REX_PREFIX] != 0)
4821 if (i.prefixes != 0 && !intel_syntax)
4822 as_warn (_("skipping prefixes on this instruction"));
4824 /* It's always a symbol; End frag & setup for relax.
4825 Make sure there is enough room in this frag for the largest
4826 instruction we may generate in md_convert_frag. This is 2
4827 bytes for the opcode and room for the prefix and largest
4829 frag_grow (prefix + 2 + 4);
4830 /* Prefix and 1 opcode byte go in fr_fix. */
4831 p = frag_more (prefix + 1);
4832 if (i.prefix[DATA_PREFIX] != 0)
4833 *p++ = DATA_PREFIX_OPCODE;
4834 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4835 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4836 *p++ = i.prefix[SEG_PREFIX];
4837 if (i.prefix[REX_PREFIX] != 0)
4838 *p++ = i.prefix[REX_PREFIX];
4839 *p = i.tm.base_opcode;
4841 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4842 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4843 else if (cpu_arch_flags.bitfield.cpui386)
4844 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4846 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4849 sym = i.op[0].disps->X_add_symbol;
4850 off = i.op[0].disps->X_add_number;
4852 if (i.op[0].disps->X_op != O_constant
4853 && i.op[0].disps->X_op != O_symbol)
4855 /* Handle complex expressions. */
4856 sym = make_expr_symbol (i.op[0].disps);
4860 /* 1 possible extra opcode + 4 byte displacement go in var part.
4861 Pass reloc in fr_var. */
4862 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4872 if (i.tm.opcode_modifier.jumpbyte)
4874 /* This is a loop or jecxz type instruction. */
4876 if (i.prefix[ADDR_PREFIX] != 0)
4878 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4881 /* Pentium4 branch hints. */
4882 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4883 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4885 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4894 if (flag_code == CODE_16BIT)
4897 if (i.prefix[DATA_PREFIX] != 0)
4899 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4909 if (i.prefix[REX_PREFIX] != 0)
4911 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4915 if (i.prefixes != 0 && !intel_syntax)
4916 as_warn (_("skipping prefixes on this instruction"));
4918 p = frag_more (1 + size);
4919 *p++ = i.tm.base_opcode;
4921 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4922 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4924 /* All jumps handled here are signed, but don't use a signed limit
4925 check for 32 and 16 bit jumps as we want to allow wrap around at
4926 4G and 64k respectively. */
4928 fixP->fx_signed = 1;
4932 output_interseg_jump (void)
4940 if (flag_code == CODE_16BIT)
4944 if (i.prefix[DATA_PREFIX] != 0)
4950 if (i.prefix[REX_PREFIX] != 0)
4960 if (i.prefixes != 0 && !intel_syntax)
4961 as_warn (_("skipping prefixes on this instruction"));
4963 /* 1 opcode; 2 segment; offset */
4964 p = frag_more (prefix + 1 + 2 + size);
4966 if (i.prefix[DATA_PREFIX] != 0)
4967 *p++ = DATA_PREFIX_OPCODE;
4969 if (i.prefix[REX_PREFIX] != 0)
4970 *p++ = i.prefix[REX_PREFIX];
4972 *p++ = i.tm.base_opcode;
4973 if (i.op[1].imms->X_op == O_constant)
4975 offsetT n = i.op[1].imms->X_add_number;
4978 && !fits_in_unsigned_word (n)
4979 && !fits_in_signed_word (n))
4981 as_bad (_("16-bit jump out of range"));
4984 md_number_to_chars (p, n, size);
4987 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4988 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4989 if (i.op[0].imms->X_op != O_constant)
4990 as_bad (_("can't handle non absolute segment in `%s'"),
4992 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4998 fragS *insn_start_frag;
4999 offsetT insn_start_off;
5001 /* Tie dwarf2 debug info to the address at the start of the insn.
5002 We can't do this after the insn has been output as the current
5003 frag may have been closed off. eg. by frag_var. */
5004 dwarf2_emit_insn (0);
5006 insn_start_frag = frag_now;
5007 insn_start_off = frag_now_fix ();
5010 if (i.tm.opcode_modifier.jump)
5012 else if (i.tm.opcode_modifier.jumpbyte
5013 || i.tm.opcode_modifier.jumpdword)
5015 else if (i.tm.opcode_modifier.jumpintersegment)
5016 output_interseg_jump ();
5019 /* Output normal instructions here. */
5023 unsigned int prefix;
5025 switch (i.tm.opcode_length)
5028 if (i.tm.base_opcode & 0xff000000)
5030 prefix = (i.tm.base_opcode >> 24) & 0xff;
5035 if ((i.tm.base_opcode & 0xff0000) != 0)
5037 prefix = (i.tm.base_opcode >> 16) & 0xff;
5038 if (i.tm.cpu_flags.bitfield.cpupadlock)
5041 if (prefix != REPE_PREFIX_OPCODE
5042 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5043 add_prefix (prefix);
5046 add_prefix (prefix);
5055 /* The prefix bytes. */
5056 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5058 FRAG_APPEND_1_CHAR (*q);
5060 /* Now the opcode; be careful about word order here! */
5061 if (i.tm.opcode_length == 1)
5063 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5067 switch (i.tm.opcode_length)
5071 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5081 /* Put out high byte first: can't use md_number_to_chars! */
5082 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5083 *p = i.tm.base_opcode & 0xff;
5085 /* On SSE5, encode the OC1 bit in the DREX field if this
5086 encoding has multiple formats. */
5087 if (i.tm.opcode_modifier.drex
5088 && i.tm.opcode_modifier.drexv
5089 && DREX_OC1 (i.tm.extension_opcode))
5090 *p |= DREX_OC1_MASK;
5093 /* Now the modrm byte and sib byte (if present). */
5094 if (i.tm.opcode_modifier.modrm)
5096 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5099 /* If i.rm.regmem == ESP (4)
5100 && i.rm.mode != (Register mode)
5102 ==> need second modrm byte. */
5103 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5105 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5106 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5108 | i.sib.scale << 6));
5111 /* Write the DREX byte if needed. */
5112 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5115 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5117 /* Encode the OC0 bit if this encoding has multiple
5119 if ((i.tm.opcode_modifier.drex
5120 || i.tm.opcode_modifier.drexv)
5121 && DREX_OC0 (i.tm.extension_opcode))
5122 *p |= DREX_OC0_MASK;
5125 if (i.disp_operands)
5126 output_disp (insn_start_frag, insn_start_off);
5129 output_imm (insn_start_frag, insn_start_off);
5135 pi ("" /*line*/, &i);
5137 #endif /* DEBUG386 */
5140 /* Return the size of the displacement operand N. */
5143 disp_size (unsigned int n)
5146 if (i.types[n].bitfield.disp64)
5148 else if (i.types[n].bitfield.disp8)
5150 else if (i.types[n].bitfield.disp16)
5155 /* Return the size of the immediate operand N. */
5158 imm_size (unsigned int n)
5161 if (i.types[n].bitfield.imm64)
5163 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5165 else if (i.types[n].bitfield.imm16)
5171 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5176 for (n = 0; n < i.operands; n++)
5178 if (operand_type_check (i.types[n], disp))
5180 if (i.op[n].disps->X_op == O_constant)
5182 int size = disp_size (n);
5185 val = offset_in_range (i.op[n].disps->X_add_number,
5187 p = frag_more (size);
5188 md_number_to_chars (p, val, size);
5192 enum bfd_reloc_code_real reloc_type;
5193 int size = disp_size (n);
5194 int sign = i.types[n].bitfield.disp32s;
5195 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5197 /* We can't have 8 bit displacement here. */
5198 assert (!i.types[n].bitfield.disp8);
5200 /* The PC relative address is computed relative
5201 to the instruction boundary, so in case immediate
5202 fields follows, we need to adjust the value. */
5203 if (pcrel && i.imm_operands)
5208 for (n1 = 0; n1 < i.operands; n1++)
5209 if (operand_type_check (i.types[n1], imm))
5211 /* Only one immediate is allowed for PC
5212 relative address. */
5215 i.op[n].disps->X_add_number -= sz;
5217 /* We should find the immediate. */
5221 p = frag_more (size);
5222 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5224 && GOT_symbol == i.op[n].disps->X_add_symbol
5225 && (((reloc_type == BFD_RELOC_32
5226 || reloc_type == BFD_RELOC_X86_64_32S
5227 || (reloc_type == BFD_RELOC_64
5229 && (i.op[n].disps->X_op == O_symbol
5230 || (i.op[n].disps->X_op == O_add
5231 && ((symbol_get_value_expression
5232 (i.op[n].disps->X_op_symbol)->X_op)
5234 || reloc_type == BFD_RELOC_32_PCREL))
5238 if (insn_start_frag == frag_now)
5239 add = (p - frag_now->fr_literal) - insn_start_off;
5244 add = insn_start_frag->fr_fix - insn_start_off;
5245 for (fr = insn_start_frag->fr_next;
5246 fr && fr != frag_now; fr = fr->fr_next)
5248 add += p - frag_now->fr_literal;
5253 reloc_type = BFD_RELOC_386_GOTPC;
5254 i.op[n].imms->X_add_number += add;
5256 else if (reloc_type == BFD_RELOC_64)
5257 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5259 /* Don't do the adjustment for x86-64, as there
5260 the pcrel addressing is relative to the _next_
5261 insn, and that is taken care of in other code. */
5262 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5264 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5265 i.op[n].disps, pcrel, reloc_type);
5272 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5277 for (n = 0; n < i.operands; n++)
5279 if (operand_type_check (i.types[n], imm))
5281 if (i.op[n].imms->X_op == O_constant)
5283 int size = imm_size (n);
5286 val = offset_in_range (i.op[n].imms->X_add_number,
5288 p = frag_more (size);
5289 md_number_to_chars (p, val, size);
5293 /* Not absolute_section.
5294 Need a 32-bit fixup (don't support 8bit
5295 non-absolute imms). Try to support other
5297 enum bfd_reloc_code_real reloc_type;
5298 int size = imm_size (n);
5301 if (i.types[n].bitfield.imm32s
5302 && (i.suffix == QWORD_MNEM_SUFFIX
5303 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5308 p = frag_more (size);
5309 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5311 /* This is tough to explain. We end up with this one if we
5312 * have operands that look like
5313 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5314 * obtain the absolute address of the GOT, and it is strongly
5315 * preferable from a performance point of view to avoid using
5316 * a runtime relocation for this. The actual sequence of
5317 * instructions often look something like:
5322 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5324 * The call and pop essentially return the absolute address
5325 * of the label .L66 and store it in %ebx. The linker itself
5326 * will ultimately change the first operand of the addl so
5327 * that %ebx points to the GOT, but to keep things simple, the
5328 * .o file must have this operand set so that it generates not
5329 * the absolute address of .L66, but the absolute address of
5330 * itself. This allows the linker itself simply treat a GOTPC
5331 * relocation as asking for a pcrel offset to the GOT to be
5332 * added in, and the addend of the relocation is stored in the
5333 * operand field for the instruction itself.
5335 * Our job here is to fix the operand so that it would add
5336 * the correct offset so that %ebx would point to itself. The
5337 * thing that is tricky is that .-.L66 will point to the
5338 * beginning of the instruction, so we need to further modify
5339 * the operand so that it will point to itself. There are
5340 * other cases where you have something like:
5342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5344 * and here no correction would be required. Internally in
5345 * the assembler we treat operands of this form as not being
5346 * pcrel since the '.' is explicitly mentioned, and I wonder
5347 * whether it would simplify matters to do it this way. Who
5348 * knows. In earlier versions of the PIC patches, the
5349 * pcrel_adjust field was used to store the correction, but
5350 * since the expression is not pcrel, I felt it would be
5351 * confusing to do it this way. */
5353 if ((reloc_type == BFD_RELOC_32
5354 || reloc_type == BFD_RELOC_X86_64_32S
5355 || reloc_type == BFD_RELOC_64)
5357 && GOT_symbol == i.op[n].imms->X_add_symbol
5358 && (i.op[n].imms->X_op == O_symbol
5359 || (i.op[n].imms->X_op == O_add
5360 && ((symbol_get_value_expression
5361 (i.op[n].imms->X_op_symbol)->X_op)
5366 if (insn_start_frag == frag_now)
5367 add = (p - frag_now->fr_literal) - insn_start_off;
5372 add = insn_start_frag->fr_fix - insn_start_off;
5373 for (fr = insn_start_frag->fr_next;
5374 fr && fr != frag_now; fr = fr->fr_next)
5376 add += p - frag_now->fr_literal;
5380 reloc_type = BFD_RELOC_386_GOTPC;
5382 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5384 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5385 i.op[n].imms->X_add_number += add;
5387 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5388 i.op[n].imms, 0, reloc_type);
5394 /* x86_cons_fix_new is called via the expression parsing code when a
5395 reloc is needed. We use this hook to get the correct .got reloc. */
5396 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5397 static int cons_sign = -1;
5400 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5403 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5405 got_reloc = NO_RELOC;
5408 if (exp->X_op == O_secrel)
5410 exp->X_op = O_symbol;
5411 r = BFD_RELOC_32_SECREL;
5415 fix_new_exp (frag, off, len, exp, 0, r);
5418 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5419 # define lex_got(reloc, adjust, types) NULL
5421 /* Parse operands of the form
5422 <symbol>@GOTOFF+<nnn>
5423 and similar .plt or .got references.
5425 If we find one, set up the correct relocation in RELOC and copy the
5426 input string, minus the `@GOTOFF' into a malloc'd buffer for
5427 parsing by the calling routine. Return this buffer, and if ADJUST
5428 is non-null set it to the length of the string we removed from the
5429 input line. Otherwise return NULL. */
5431 lex_got (enum bfd_reloc_code_real *reloc,
5433 i386_operand_type *types)
5435 /* Some of the relocations depend on the size of what field is to
5436 be relocated. But in our callers i386_immediate and i386_displacement
5437 we don't yet know the operand size (this will be set by insn
5438 matching). Hence we record the word32 relocation here,
5439 and adjust the reloc according to the real size in reloc(). */
5440 static const struct {
5442 const enum bfd_reloc_code_real rel[2];
5443 const i386_operand_type types64;
5446 BFD_RELOC_X86_64_PLTOFF64 },
5447 OPERAND_TYPE_IMM64 },
5448 { "PLT", { BFD_RELOC_386_PLT32,
5449 BFD_RELOC_X86_64_PLT32 },
5450 OPERAND_TYPE_IMM32_32S_DISP32 },
5452 BFD_RELOC_X86_64_GOTPLT64 },
5453 OPERAND_TYPE_IMM64_DISP64 },
5454 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5455 BFD_RELOC_X86_64_GOTOFF64 },
5456 OPERAND_TYPE_IMM64_DISP64 },
5458 BFD_RELOC_X86_64_GOTPCREL },
5459 OPERAND_TYPE_IMM32_32S_DISP32 },
5460 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5461 BFD_RELOC_X86_64_TLSGD },
5462 OPERAND_TYPE_IMM32_32S_DISP32 },
5463 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5465 OPERAND_TYPE_NONE },
5467 BFD_RELOC_X86_64_TLSLD },
5468 OPERAND_TYPE_IMM32_32S_DISP32 },
5469 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5470 BFD_RELOC_X86_64_GOTTPOFF },
5471 OPERAND_TYPE_IMM32_32S_DISP32 },
5472 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5473 BFD_RELOC_X86_64_TPOFF32 },
5474 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5475 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5477 OPERAND_TYPE_NONE },
5478 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5479 BFD_RELOC_X86_64_DTPOFF32 },
5481 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5482 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5484 OPERAND_TYPE_NONE },
5485 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5487 OPERAND_TYPE_NONE },
5488 { "GOT", { BFD_RELOC_386_GOT32,
5489 BFD_RELOC_X86_64_GOT32 },
5490 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5491 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5492 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5493 OPERAND_TYPE_IMM32_32S_DISP32 },
5494 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5495 BFD_RELOC_X86_64_TLSDESC_CALL },
5496 OPERAND_TYPE_IMM32_32S_DISP32 },
5504 for (cp = input_line_pointer; *cp != '@'; cp++)
5505 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5508 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5512 len = strlen (gotrel[j].str);
5513 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5515 if (gotrel[j].rel[object_64bit] != 0)
5518 char *tmpbuf, *past_reloc;
5520 *reloc = gotrel[j].rel[object_64bit];
5526 if (flag_code != CODE_64BIT)
5528 types->bitfield.imm32 = 1;
5529 types->bitfield.disp32 = 1;
5532 *types = gotrel[j].types64;
5535 if (GOT_symbol == NULL)
5536 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5538 /* The length of the first part of our input line. */
5539 first = cp - input_line_pointer;
5541 /* The second part goes from after the reloc token until
5542 (and including) an end_of_line char or comma. */
5543 past_reloc = cp + 1 + len;
5545 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5547 second = cp + 1 - past_reloc;
5549 /* Allocate and copy string. The trailing NUL shouldn't
5550 be necessary, but be safe. */
5551 tmpbuf = xmalloc (first + second + 2);
5552 memcpy (tmpbuf, input_line_pointer, first);
5553 if (second != 0 && *past_reloc != ' ')
5554 /* Replace the relocation token with ' ', so that
5555 errors like foo@GOTOFF1 will be detected. */
5556 tmpbuf[first++] = ' ';
5557 memcpy (tmpbuf + first, past_reloc, second);
5558 tmpbuf[first + second] = '\0';
5562 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5563 gotrel[j].str, 1 << (5 + object_64bit));
5568 /* Might be a symbol version string. Don't as_bad here. */
5573 x86_cons (expressionS *exp, int size)
5575 if (size == 4 || (object_64bit && size == 8))
5577 /* Handle @GOTOFF and the like in an expression. */
5579 char *gotfree_input_line;
5582 save = input_line_pointer;
5583 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5584 if (gotfree_input_line)
5585 input_line_pointer = gotfree_input_line;
5589 if (gotfree_input_line)
5591 /* expression () has merrily parsed up to the end of line,
5592 or a comma - in the wrong buffer. Transfer how far
5593 input_line_pointer has moved to the right buffer. */
5594 input_line_pointer = (save
5595 + (input_line_pointer - gotfree_input_line)
5597 free (gotfree_input_line);
5598 if (exp->X_op == O_constant
5599 || exp->X_op == O_absent
5600 || exp->X_op == O_illegal
5601 || exp->X_op == O_register
5602 || exp->X_op == O_big)
5604 char c = *input_line_pointer;
5605 *input_line_pointer = 0;
5606 as_bad (_("missing or invalid expression `%s'"), save);
5607 *input_line_pointer = c;
5616 static void signed_cons (int size)
5618 if (flag_code == CODE_64BIT)
5626 pe_directive_secrel (dummy)
5627 int dummy ATTRIBUTE_UNUSED;
5634 if (exp.X_op == O_symbol)
5635 exp.X_op = O_secrel;
5637 emit_expr (&exp, 4);
5639 while (*input_line_pointer++ == ',');
5641 input_line_pointer--;
5642 demand_empty_rest_of_line ();
5647 i386_immediate (char *imm_start)
5649 char *save_input_line_pointer;
5650 char *gotfree_input_line;
5653 i386_operand_type types;
5655 UINTS_SET (types, ~0);
5657 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5659 as_bad (_("at most %d immediate operands are allowed"),
5660 MAX_IMMEDIATE_OPERANDS);
5664 exp = &im_expressions[i.imm_operands++];
5665 i.op[this_operand].imms = exp;
5667 if (is_space_char (*imm_start))
5670 save_input_line_pointer = input_line_pointer;
5671 input_line_pointer = imm_start;
5673 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5674 if (gotfree_input_line)
5675 input_line_pointer = gotfree_input_line;
5677 exp_seg = expression (exp);
5680 if (*input_line_pointer)
5681 as_bad (_("junk `%s' after expression"), input_line_pointer);
5683 input_line_pointer = save_input_line_pointer;
5684 if (gotfree_input_line)
5685 free (gotfree_input_line);
5687 if (exp->X_op == O_absent
5688 || exp->X_op == O_illegal
5689 || exp->X_op == O_big
5690 || (gotfree_input_line
5691 && (exp->X_op == O_constant
5692 || exp->X_op == O_register)))
5694 as_bad (_("missing or invalid immediate expression `%s'"),
5698 else if (exp->X_op == O_constant)
5700 /* Size it properly later. */
5701 i.types[this_operand].bitfield.imm64 = 1;
5702 /* If BFD64, sign extend val. */
5703 if (!use_rela_relocations
5704 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5706 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5708 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5709 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5710 && exp_seg != absolute_section
5711 && exp_seg != text_section
5712 && exp_seg != data_section
5713 && exp_seg != bss_section
5714 && exp_seg != undefined_section
5715 && !bfd_is_com_section (exp_seg))
5717 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5721 else if (!intel_syntax && exp->X_op == O_register)
5723 as_bad (_("illegal immediate register operand %s"), imm_start);
5728 /* This is an address. The size of the address will be
5729 determined later, depending on destination register,
5730 suffix, or the default for the section. */
5731 i.types[this_operand].bitfield.imm8 = 1;
5732 i.types[this_operand].bitfield.imm16 = 1;
5733 i.types[this_operand].bitfield.imm32 = 1;
5734 i.types[this_operand].bitfield.imm32s = 1;
5735 i.types[this_operand].bitfield.imm64 = 1;
5736 i.types[this_operand] = operand_type_and (i.types[this_operand],
5744 i386_scale (char *scale)
5747 char *save = input_line_pointer;
5749 input_line_pointer = scale;
5750 val = get_absolute_expression ();
5755 i.log2_scale_factor = 0;
5758 i.log2_scale_factor = 1;
5761 i.log2_scale_factor = 2;
5764 i.log2_scale_factor = 3;
5768 char sep = *input_line_pointer;
5770 *input_line_pointer = '\0';
5771 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5773 *input_line_pointer = sep;
5774 input_line_pointer = save;
5778 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5780 as_warn (_("scale factor of %d without an index register"),
5781 1 << i.log2_scale_factor);
5782 i.log2_scale_factor = 0;
5784 scale = input_line_pointer;
5785 input_line_pointer = save;
5790 i386_displacement (char *disp_start, char *disp_end)
5794 char *save_input_line_pointer;
5795 char *gotfree_input_line;
5797 i386_operand_type bigdisp, types = anydisp;
5800 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5802 as_bad (_("at most %d displacement operands are allowed"),
5803 MAX_MEMORY_OPERANDS);
5807 UINTS_CLEAR (bigdisp);
5808 if ((i.types[this_operand].bitfield.jumpabsolute)
5809 || (!current_templates->start->opcode_modifier.jump
5810 && !current_templates->start->opcode_modifier.jumpdword))
5812 bigdisp.bitfield.disp32 = 1;
5813 override = (i.prefix[ADDR_PREFIX] != 0);
5814 if (flag_code == CODE_64BIT)
5818 bigdisp.bitfield.disp32s = 1;
5819 bigdisp.bitfield.disp64 = 1;
5822 else if ((flag_code == CODE_16BIT) ^ override)
5824 bigdisp.bitfield.disp32 = 0;
5825 bigdisp.bitfield.disp16 = 1;
5830 /* For PC-relative branches, the width of the displacement
5831 is dependent upon data size, not address size. */
5832 override = (i.prefix[DATA_PREFIX] != 0);
5833 if (flag_code == CODE_64BIT)
5835 if (override || i.suffix == WORD_MNEM_SUFFIX)
5836 bigdisp.bitfield.disp16 = 1;
5839 bigdisp.bitfield.disp32 = 1;
5840 bigdisp.bitfield.disp32s = 1;
5846 override = (i.suffix == (flag_code != CODE_16BIT
5848 : LONG_MNEM_SUFFIX));
5849 bigdisp.bitfield.disp32 = 1;
5850 if ((flag_code == CODE_16BIT) ^ override)
5852 bigdisp.bitfield.disp32 = 0;
5853 bigdisp.bitfield.disp16 = 1;
5857 i.types[this_operand] = operand_type_or (i.types[this_operand],
5860 exp = &disp_expressions[i.disp_operands];
5861 i.op[this_operand].disps = exp;
5863 save_input_line_pointer = input_line_pointer;
5864 input_line_pointer = disp_start;
5865 END_STRING_AND_SAVE (disp_end);
5867 #ifndef GCC_ASM_O_HACK
5868 #define GCC_ASM_O_HACK 0
5871 END_STRING_AND_SAVE (disp_end + 1);
5872 if (i.types[this_operand].bitfield.baseIndex
5873 && displacement_string_end[-1] == '+')
5875 /* This hack is to avoid a warning when using the "o"
5876 constraint within gcc asm statements.
5879 #define _set_tssldt_desc(n,addr,limit,type) \
5880 __asm__ __volatile__ ( \
5882 "movw %w1,2+%0\n\t" \
5884 "movb %b1,4+%0\n\t" \
5885 "movb %4,5+%0\n\t" \
5886 "movb $0,6+%0\n\t" \
5887 "movb %h1,7+%0\n\t" \
5889 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5891 This works great except that the output assembler ends
5892 up looking a bit weird if it turns out that there is
5893 no offset. You end up producing code that looks like:
5906 So here we provide the missing zero. */
5908 *displacement_string_end = '0';
5911 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5912 if (gotfree_input_line)
5913 input_line_pointer = gotfree_input_line;
5915 exp_seg = expression (exp);
5918 if (*input_line_pointer)
5919 as_bad (_("junk `%s' after expression"), input_line_pointer);
5921 RESTORE_END_STRING (disp_end + 1);
5923 input_line_pointer = save_input_line_pointer;
5924 if (gotfree_input_line)
5925 free (gotfree_input_line);
5928 /* We do this to make sure that the section symbol is in
5929 the symbol table. We will ultimately change the relocation
5930 to be relative to the beginning of the section. */
5931 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5932 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5933 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5935 if (exp->X_op != O_symbol)
5938 if (S_IS_LOCAL (exp->X_add_symbol)
5939 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5940 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5941 exp->X_op = O_subtract;
5942 exp->X_op_symbol = GOT_symbol;
5943 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5944 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5945 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5946 i.reloc[this_operand] = BFD_RELOC_64;
5948 i.reloc[this_operand] = BFD_RELOC_32;
5951 else if (exp->X_op == O_absent
5952 || exp->X_op == O_illegal
5953 || exp->X_op == O_big
5954 || (gotfree_input_line
5955 && (exp->X_op == O_constant
5956 || exp->X_op == O_register)))
5959 as_bad (_("missing or invalid displacement expression `%s'"),
5964 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5965 else if (exp->X_op != O_constant
5966 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5967 && exp_seg != absolute_section
5968 && exp_seg != text_section
5969 && exp_seg != data_section
5970 && exp_seg != bss_section
5971 && exp_seg != undefined_section
5972 && !bfd_is_com_section (exp_seg))
5974 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5979 RESTORE_END_STRING (disp_end);
5981 /* Check if this is a displacement only operand. */
5982 bigdisp = i.types[this_operand];
5983 bigdisp.bitfield.disp8 = 0;
5984 bigdisp.bitfield.disp16 = 0;
5985 bigdisp.bitfield.disp32 = 0;
5986 bigdisp.bitfield.disp32s = 0;
5987 bigdisp.bitfield.disp64 = 0;
5988 if (UINTS_ALL_ZERO (bigdisp))
5989 i.types[this_operand] = operand_type_and (i.types[this_operand],
5995 /* Make sure the memory operand we've been dealt is valid.
5996 Return 1 on success, 0 on a failure. */
5999 i386_index_check (const char *operand_string)
6002 #if INFER_ADDR_PREFIX
6008 if (flag_code == CODE_64BIT)
6011 && ((i.prefix[ADDR_PREFIX] == 0
6012 && !i.base_reg->reg_type.bitfield.reg64)
6013 || (i.prefix[ADDR_PREFIX]
6014 && !i.base_reg->reg_type.bitfield.reg32))
6016 || i.base_reg->reg_num !=
6017 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6019 && (!i.index_reg->reg_type.bitfield.baseindex
6020 || (i.prefix[ADDR_PREFIX] == 0
6021 && i.index_reg->reg_num != RegRiz
6022 && !i.index_reg->reg_type.bitfield.reg64
6024 || (i.prefix[ADDR_PREFIX]
6025 && i.index_reg->reg_num != RegEiz
6026 && !i.index_reg->reg_type.bitfield.reg32))))
6031 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6035 && (!i.base_reg->reg_type.bitfield.reg16
6036 || !i.base_reg->reg_type.bitfield.baseindex))
6038 && (!i.index_reg->reg_type.bitfield.reg16
6039 || !i.index_reg->reg_type.bitfield.baseindex
6041 && i.base_reg->reg_num < 6
6042 && i.index_reg->reg_num >= 6
6043 && i.log2_scale_factor == 0))))
6050 && !i.base_reg->reg_type.bitfield.reg32)
6052 && ((!i.index_reg->reg_type.bitfield.reg32
6053 && i.index_reg->reg_num != RegEiz)
6054 || !i.index_reg->reg_type.bitfield.baseindex)))
6060 #if INFER_ADDR_PREFIX
6061 if (i.prefix[ADDR_PREFIX] == 0)
6063 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6065 /* Change the size of any displacement too. At most one of
6066 Disp16 or Disp32 is set.
6067 FIXME. There doesn't seem to be any real need for separate
6068 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6069 Removing them would probably clean up the code quite a lot. */
6070 if (flag_code != CODE_64BIT
6071 && (i.types[this_operand].bitfield.disp16
6072 || i.types[this_operand].bitfield.disp32))
6073 i.types[this_operand]
6074 = operand_type_xor (i.types[this_operand], disp16_32);
6079 as_bad (_("`%s' is not a valid base/index expression"),
6083 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6085 flag_code_names[flag_code]);
6090 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6094 i386_operand (char *operand_string)
6098 char *op_string = operand_string;
6100 if (is_space_char (*op_string))
6103 /* We check for an absolute prefix (differentiating,
6104 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6105 if (*op_string == ABSOLUTE_PREFIX)
6108 if (is_space_char (*op_string))
6110 i.types[this_operand].bitfield.jumpabsolute = 1;
6113 /* Check if operand is a register. */
6114 if ((r = parse_register (op_string, &end_op)) != NULL)
6116 i386_operand_type temp;
6118 /* Check for a segment override by searching for ':' after a
6119 segment register. */
6121 if (is_space_char (*op_string))
6123 if (*op_string == ':'
6124 && (r->reg_type.bitfield.sreg2
6125 || r->reg_type.bitfield.sreg3))
6130 i.seg[i.mem_operands] = &es;
6133 i.seg[i.mem_operands] = &cs;
6136 i.seg[i.mem_operands] = &ss;
6139 i.seg[i.mem_operands] = &ds;
6142 i.seg[i.mem_operands] = &fs;
6145 i.seg[i.mem_operands] = &gs;
6149 /* Skip the ':' and whitespace. */
6151 if (is_space_char (*op_string))
6154 if (!is_digit_char (*op_string)
6155 && !is_identifier_char (*op_string)
6156 && *op_string != '('
6157 && *op_string != ABSOLUTE_PREFIX)
6159 as_bad (_("bad memory operand `%s'"), op_string);
6162 /* Handle case of %es:*foo. */
6163 if (*op_string == ABSOLUTE_PREFIX)
6166 if (is_space_char (*op_string))
6168 i.types[this_operand].bitfield.jumpabsolute = 1;
6170 goto do_memory_reference;
6174 as_bad (_("junk `%s' after register"), op_string);
6178 temp.bitfield.baseindex = 0;
6179 i.types[this_operand] = operand_type_or (i.types[this_operand],
6181 i.op[this_operand].regs = r;
6184 else if (*op_string == REGISTER_PREFIX)
6186 as_bad (_("bad register name `%s'"), op_string);
6189 else if (*op_string == IMMEDIATE_PREFIX)
6192 if (i.types[this_operand].bitfield.jumpabsolute)
6194 as_bad (_("immediate operand illegal with absolute jump"));
6197 if (!i386_immediate (op_string))
6200 else if (is_digit_char (*op_string)
6201 || is_identifier_char (*op_string)
6202 || *op_string == '(')
6204 /* This is a memory reference of some sort. */
6207 /* Start and end of displacement string expression (if found). */
6208 char *displacement_string_start;
6209 char *displacement_string_end;
6211 do_memory_reference:
6212 if ((i.mem_operands == 1
6213 && !current_templates->start->opcode_modifier.isstring)
6214 || i.mem_operands == 2)
6216 as_bad (_("too many memory references for `%s'"),
6217 current_templates->start->name);
6221 /* Check for base index form. We detect the base index form by
6222 looking for an ')' at the end of the operand, searching
6223 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6225 base_string = op_string + strlen (op_string);
6228 if (is_space_char (*base_string))
6231 /* If we only have a displacement, set-up for it to be parsed later. */
6232 displacement_string_start = op_string;
6233 displacement_string_end = base_string + 1;
6235 if (*base_string == ')')
6238 unsigned int parens_balanced = 1;
6239 /* We've already checked that the number of left & right ()'s are
6240 equal, so this loop will not be infinite. */
6244 if (*base_string == ')')
6246 if (*base_string == '(')
6249 while (parens_balanced);
6251 temp_string = base_string;
6253 /* Skip past '(' and whitespace. */
6255 if (is_space_char (*base_string))
6258 if (*base_string == ','
6259 || ((i.base_reg = parse_register (base_string, &end_op))
6262 displacement_string_end = temp_string;
6264 i.types[this_operand].bitfield.baseindex = 1;
6268 base_string = end_op;
6269 if (is_space_char (*base_string))
6273 /* There may be an index reg or scale factor here. */
6274 if (*base_string == ',')
6277 if (is_space_char (*base_string))
6280 if ((i.index_reg = parse_register (base_string, &end_op))
6283 base_string = end_op;
6284 if (is_space_char (*base_string))
6286 if (*base_string == ',')
6289 if (is_space_char (*base_string))
6292 else if (*base_string != ')')
6294 as_bad (_("expecting `,' or `)' "
6295 "after index register in `%s'"),
6300 else if (*base_string == REGISTER_PREFIX)
6302 as_bad (_("bad register name `%s'"), base_string);
6306 /* Check for scale factor. */
6307 if (*base_string != ')')
6309 char *end_scale = i386_scale (base_string);
6314 base_string = end_scale;
6315 if (is_space_char (*base_string))
6317 if (*base_string != ')')
6319 as_bad (_("expecting `)' "
6320 "after scale factor in `%s'"),
6325 else if (!i.index_reg)
6327 as_bad (_("expecting index register or scale factor "
6328 "after `,'; got '%c'"),
6333 else if (*base_string != ')')
6335 as_bad (_("expecting `,' or `)' "
6336 "after base register in `%s'"),
6341 else if (*base_string == REGISTER_PREFIX)
6343 as_bad (_("bad register name `%s'"), base_string);
6348 /* If there's an expression beginning the operand, parse it,
6349 assuming displacement_string_start and
6350 displacement_string_end are meaningful. */
6351 if (displacement_string_start != displacement_string_end)
6353 if (!i386_displacement (displacement_string_start,
6354 displacement_string_end))
6358 /* Special case for (%dx) while doing input/output op. */
6360 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6362 && i.log2_scale_factor == 0
6363 && i.seg[i.mem_operands] == 0
6364 && !operand_type_check (i.types[this_operand], disp))
6366 UINTS_CLEAR (i.types[this_operand]);
6367 i.types[this_operand].bitfield.inoutportreg = 1;
6371 if (i386_index_check (operand_string) == 0)
6377 /* It's not a memory operand; argh! */
6378 as_bad (_("invalid char %s beginning operand %d `%s'"),
6379 output_invalid (*op_string),
6384 return 1; /* Normal return. */
6387 /* md_estimate_size_before_relax()
6389 Called just before relax() for rs_machine_dependent frags. The x86
6390 assembler uses these frags to handle variable size jump
6393 Any symbol that is now undefined will not become defined.
6394 Return the correct fr_subtype in the frag.
6395 Return the initial "guess for variable size of frag" to caller.
6396 The guess is actually the growth beyond the fixed part. Whatever
6397 we do to grow the fixed or variable part contributes to our
6401 md_estimate_size_before_relax (fragP, segment)
6405 /* We've already got fragP->fr_subtype right; all we have to do is
6406 check for un-relaxable symbols. On an ELF system, we can't relax
6407 an externally visible symbol, because it may be overridden by a
6409 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6412 && (S_IS_EXTERNAL (fragP->fr_symbol)
6413 || S_IS_WEAK (fragP->fr_symbol)))
6417 /* Symbol is undefined in this segment, or we need to keep a
6418 reloc so that weak symbols can be overridden. */
6419 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6420 enum bfd_reloc_code_real reloc_type;
6421 unsigned char *opcode;
6424 if (fragP->fr_var != NO_RELOC)
6425 reloc_type = fragP->fr_var;
6427 reloc_type = BFD_RELOC_16_PCREL;
6429 reloc_type = BFD_RELOC_32_PCREL;
6431 old_fr_fix = fragP->fr_fix;
6432 opcode = (unsigned char *) fragP->fr_opcode;
6434 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6437 /* Make jmp (0xeb) a (d)word displacement jump. */
6439 fragP->fr_fix += size;
6440 fix_new (fragP, old_fr_fix, size,
6442 fragP->fr_offset, 1,
6448 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6450 /* Negate the condition, and branch past an
6451 unconditional jump. */
6454 /* Insert an unconditional jump. */
6456 /* We added two extra opcode bytes, and have a two byte
6458 fragP->fr_fix += 2 + 2;
6459 fix_new (fragP, old_fr_fix + 2, 2,
6461 fragP->fr_offset, 1,
6468 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6473 fixP = fix_new (fragP, old_fr_fix, 1,
6475 fragP->fr_offset, 1,
6477 fixP->fx_signed = 1;
6481 /* This changes the byte-displacement jump 0x7N
6482 to the (d)word-displacement jump 0x0f,0x8N. */
6483 opcode[1] = opcode[0] + 0x10;
6484 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6485 /* We've added an opcode byte. */
6486 fragP->fr_fix += 1 + size;
6487 fix_new (fragP, old_fr_fix + 1, size,
6489 fragP->fr_offset, 1,
6494 BAD_CASE (fragP->fr_subtype);
6498 return fragP->fr_fix - old_fr_fix;
6501 /* Guess size depending on current relax state. Initially the relax
6502 state will correspond to a short jump and we return 1, because
6503 the variable part of the frag (the branch offset) is one byte
6504 long. However, we can relax a section more than once and in that
6505 case we must either set fr_subtype back to the unrelaxed state,
6506 or return the value for the appropriate branch. */
6507 return md_relax_table[fragP->fr_subtype].rlx_length;
6510 /* Called after relax() is finished.
6512 In: Address of frag.
6513 fr_type == rs_machine_dependent.
6514 fr_subtype is what the address relaxed to.
6516 Out: Any fixSs and constants are set up.
6517 Caller will turn frag into a ".space 0". */
6520 md_convert_frag (abfd, sec, fragP)
6521 bfd *abfd ATTRIBUTE_UNUSED;
6522 segT sec ATTRIBUTE_UNUSED;
6525 unsigned char *opcode;
6526 unsigned char *where_to_put_displacement = NULL;
6527 offsetT target_address;
6528 offsetT opcode_address;
6529 unsigned int extension = 0;
6530 offsetT displacement_from_opcode_start;
6532 opcode = (unsigned char *) fragP->fr_opcode;
6534 /* Address we want to reach in file space. */
6535 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6537 /* Address opcode resides at in file space. */
6538 opcode_address = fragP->fr_address + fragP->fr_fix;
6540 /* Displacement from opcode start to fill into instruction. */
6541 displacement_from_opcode_start = target_address - opcode_address;
6543 if ((fragP->fr_subtype & BIG) == 0)
6545 /* Don't have to change opcode. */
6546 extension = 1; /* 1 opcode + 1 displacement */
6547 where_to_put_displacement = &opcode[1];
6551 if (no_cond_jump_promotion
6552 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6553 as_warn_where (fragP->fr_file, fragP->fr_line,
6554 _("long jump required"));
6556 switch (fragP->fr_subtype)
6558 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6559 extension = 4; /* 1 opcode + 4 displacement */
6561 where_to_put_displacement = &opcode[1];
6564 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6565 extension = 2; /* 1 opcode + 2 displacement */
6567 where_to_put_displacement = &opcode[1];
6570 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6571 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6572 extension = 5; /* 2 opcode + 4 displacement */
6573 opcode[1] = opcode[0] + 0x10;
6574 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6575 where_to_put_displacement = &opcode[2];
6578 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6579 extension = 3; /* 2 opcode + 2 displacement */
6580 opcode[1] = opcode[0] + 0x10;
6581 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6582 where_to_put_displacement = &opcode[2];
6585 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6590 where_to_put_displacement = &opcode[3];
6594 BAD_CASE (fragP->fr_subtype);
6599 /* If size if less then four we are sure that the operand fits,
6600 but if it's 4, then it could be that the displacement is larger
6602 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6604 && ((addressT) (displacement_from_opcode_start - extension
6605 + ((addressT) 1 << 31))
6606 > (((addressT) 2 << 31) - 1)))
6608 as_bad_where (fragP->fr_file, fragP->fr_line,
6609 _("jump target out of range"));
6610 /* Make us emit 0. */
6611 displacement_from_opcode_start = extension;
6613 /* Now put displacement after opcode. */
6614 md_number_to_chars ((char *) where_to_put_displacement,
6615 (valueT) (displacement_from_opcode_start - extension),
6616 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6617 fragP->fr_fix += extension;
6620 /* Apply a fixup (fixS) to segment data, once it has been determined
6621 by our caller that we have all the info we need to fix it up.
6623 On the 386, immediates, displacements, and data pointers are all in
6624 the same (little-endian) format, so we don't need to care about which
6628 md_apply_fix (fixP, valP, seg)
6629 /* The fix we're to put in. */
6631 /* Pointer to the value of the bits. */
6633 /* Segment fix is from. */
6634 segT seg ATTRIBUTE_UNUSED;
6636 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6637 valueT value = *valP;
6639 #if !defined (TE_Mach)
6642 switch (fixP->fx_r_type)
6648 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6651 case BFD_RELOC_X86_64_32S:
6652 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6655 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6658 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6663 if (fixP->fx_addsy != NULL
6664 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6665 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6666 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6667 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6668 && !use_rela_relocations)
6670 /* This is a hack. There should be a better way to handle this.
6671 This covers for the fact that bfd_install_relocation will
6672 subtract the current location (for partial_inplace, PC relative
6673 relocations); see more below. */
6677 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6680 value += fixP->fx_where + fixP->fx_frag->fr_address;
6682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6685 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6688 || (symbol_section_p (fixP->fx_addsy)
6689 && sym_seg != absolute_section))
6690 && !generic_force_reloc (fixP))
6692 /* Yes, we add the values in twice. This is because
6693 bfd_install_relocation subtracts them out again. I think
6694 bfd_install_relocation is broken, but I don't dare change
6696 value += fixP->fx_where + fixP->fx_frag->fr_address;
6700 #if defined (OBJ_COFF) && defined (TE_PE)
6701 /* For some reason, the PE format does not store a
6702 section address offset for a PC relative symbol. */
6703 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6704 || S_IS_WEAK (fixP->fx_addsy))
6705 value += md_pcrel_from (fixP);
6709 /* Fix a few things - the dynamic linker expects certain values here,
6710 and we must not disappoint it. */
6711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6712 if (IS_ELF && fixP->fx_addsy)
6713 switch (fixP->fx_r_type)
6715 case BFD_RELOC_386_PLT32:
6716 case BFD_RELOC_X86_64_PLT32:
6717 /* Make the jump instruction point to the address of the operand. At
6718 runtime we merely add the offset to the actual PLT entry. */
6722 case BFD_RELOC_386_TLS_GD:
6723 case BFD_RELOC_386_TLS_LDM:
6724 case BFD_RELOC_386_TLS_IE_32:
6725 case BFD_RELOC_386_TLS_IE:
6726 case BFD_RELOC_386_TLS_GOTIE:
6727 case BFD_RELOC_386_TLS_GOTDESC:
6728 case BFD_RELOC_X86_64_TLSGD:
6729 case BFD_RELOC_X86_64_TLSLD:
6730 case BFD_RELOC_X86_64_GOTTPOFF:
6731 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6732 value = 0; /* Fully resolved at runtime. No addend. */
6734 case BFD_RELOC_386_TLS_LE:
6735 case BFD_RELOC_386_TLS_LDO_32:
6736 case BFD_RELOC_386_TLS_LE_32:
6737 case BFD_RELOC_X86_64_DTPOFF32:
6738 case BFD_RELOC_X86_64_DTPOFF64:
6739 case BFD_RELOC_X86_64_TPOFF32:
6740 case BFD_RELOC_X86_64_TPOFF64:
6741 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6744 case BFD_RELOC_386_TLS_DESC_CALL:
6745 case BFD_RELOC_X86_64_TLSDESC_CALL:
6746 value = 0; /* Fully resolved at runtime. No addend. */
6747 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6751 case BFD_RELOC_386_GOT32:
6752 case BFD_RELOC_X86_64_GOT32:
6753 value = 0; /* Fully resolved at runtime. No addend. */
6756 case BFD_RELOC_VTABLE_INHERIT:
6757 case BFD_RELOC_VTABLE_ENTRY:
6764 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6766 #endif /* !defined (TE_Mach) */
6768 /* Are we finished with this relocation now? */
6769 if (fixP->fx_addsy == NULL)
6771 else if (use_rela_relocations)
6773 fixP->fx_no_overflow = 1;
6774 /* Remember value for tc_gen_reloc. */
6775 fixP->fx_addnumber = value;
6779 md_number_to_chars (p, value, fixP->fx_size);
6783 md_atof (int type, char *litP, int *sizeP)
6785 /* This outputs the LITTLENUMs in REVERSE order;
6786 in accord with the bigendian 386. */
6787 return ieee_md_atof (type, litP, sizeP, FALSE);
6790 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6793 output_invalid (int c)
6796 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6799 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6800 "(0x%x)", (unsigned char) c);
6801 return output_invalid_buf;
6804 /* REG_STRING starts *before* REGISTER_PREFIX. */
6806 static const reg_entry *
6807 parse_real_register (char *reg_string, char **end_op)
6809 char *s = reg_string;
6811 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6814 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6815 if (*s == REGISTER_PREFIX)
6818 if (is_space_char (*s))
6822 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6824 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6825 return (const reg_entry *) NULL;
6829 /* For naked regs, make sure that we are not dealing with an identifier.
6830 This prevents confusing an identifier like `eax_var' with register
6832 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6833 return (const reg_entry *) NULL;
6837 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6839 /* Handle floating point regs, allowing spaces in the (i) part. */
6840 if (r == i386_regtab /* %st is first entry of table */)
6842 if (is_space_char (*s))
6847 if (is_space_char (*s))
6849 if (*s >= '0' && *s <= '7')
6853 if (is_space_char (*s))
6858 r = hash_find (reg_hash, "st(0)");
6863 /* We have "%st(" then garbage. */
6864 return (const reg_entry *) NULL;
6868 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6871 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6872 return (const reg_entry *) NULL;
6875 && ((r->reg_flags & (RegRex64 | RegRex))
6876 || r->reg_type.bitfield.reg64)
6877 && (!cpu_arch_flags.bitfield.cpulm
6878 || !UINTS_EQUAL (r->reg_type, control))
6879 && flag_code != CODE_64BIT)
6880 return (const reg_entry *) NULL;
6885 /* REG_STRING starts *before* REGISTER_PREFIX. */
6887 static const reg_entry *
6888 parse_register (char *reg_string, char **end_op)
6892 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6893 r = parse_real_register (reg_string, end_op);
6898 char *save = input_line_pointer;
6902 input_line_pointer = reg_string;
6903 c = get_symbol_end ();
6904 symbolP = symbol_find (reg_string);
6905 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6907 const expressionS *e = symbol_get_value_expression (symbolP);
6909 know (e->X_op == O_register);
6910 know (e->X_add_number >= 0
6911 && (valueT) e->X_add_number < i386_regtab_size);
6912 r = i386_regtab + e->X_add_number;
6913 *end_op = input_line_pointer;
6915 *input_line_pointer = c;
6916 input_line_pointer = save;
6922 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6925 char *end = input_line_pointer;
6928 r = parse_register (name, &input_line_pointer);
6929 if (r && end <= input_line_pointer)
6931 *nextcharP = *input_line_pointer;
6932 *input_line_pointer = 0;
6933 e->X_op = O_register;
6934 e->X_add_number = r - i386_regtab;
6937 input_line_pointer = end;
6943 md_operand (expressionS *e)
6945 if (*input_line_pointer == REGISTER_PREFIX)
6948 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6952 e->X_op = O_register;
6953 e->X_add_number = r - i386_regtab;
6954 input_line_pointer = end;
6960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6961 const char *md_shortopts = "kVQ:sqn";
6963 const char *md_shortopts = "qn";
6966 #define OPTION_32 (OPTION_MD_BASE + 0)
6967 #define OPTION_64 (OPTION_MD_BASE + 1)
6968 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6969 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6970 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6971 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6972 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6973 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6974 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6975 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6977 struct option md_longopts[] =
6979 {"32", no_argument, NULL, OPTION_32},
6980 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6981 {"64", no_argument, NULL, OPTION_64},
6983 {"divide", no_argument, NULL, OPTION_DIVIDE},
6984 {"march", required_argument, NULL, OPTION_MARCH},
6985 {"mtune", required_argument, NULL, OPTION_MTUNE},
6986 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6987 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6988 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6989 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6990 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
6991 {NULL, no_argument, NULL, 0}
6993 size_t md_longopts_size = sizeof (md_longopts);
6996 md_parse_option (int c, char *arg)
7003 optimize_align_code = 0;
7010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7011 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7012 should be emitted or not. FIXME: Not implemented. */
7016 /* -V: SVR4 argument to print version ID. */
7018 print_version_id ();
7021 /* -k: Ignore for FreeBSD compatibility. */
7026 /* -s: On i386 Solaris, this tells the native assembler to use
7027 .stab instead of .stab.excl. We always use .stab anyhow. */
7030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7033 const char **list, **l;
7035 list = bfd_target_list ();
7036 for (l = list; *l != NULL; l++)
7037 if (CONST_STRNEQ (*l, "elf64-x86-64")
7038 || strcmp (*l, "coff-x86-64") == 0
7039 || strcmp (*l, "pe-x86-64") == 0
7040 || strcmp (*l, "pei-x86-64") == 0)
7042 default_arch = "x86_64";
7046 as_fatal (_("No compiled in support for x86_64"));
7053 default_arch = "i386";
7057 #ifdef SVR4_COMMENT_CHARS
7062 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7064 for (s = i386_comment_chars; *s != '\0'; s++)
7068 i386_comment_chars = n;
7075 as_fatal (_("Invalid -march= option: `%s'"), arg);
7076 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7078 if (strcmp (arg, cpu_arch [i].name) == 0)
7080 cpu_arch_isa = cpu_arch[i].type;
7081 cpu_arch_isa_flags = cpu_arch[i].flags;
7082 if (!cpu_arch_tune_set)
7084 cpu_arch_tune = cpu_arch_isa;
7085 cpu_arch_tune_flags = cpu_arch_isa_flags;
7090 if (i >= ARRAY_SIZE (cpu_arch))
7091 as_fatal (_("Invalid -march= option: `%s'"), arg);
7096 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7097 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7099 if (strcmp (arg, cpu_arch [i].name) == 0)
7101 cpu_arch_tune_set = 1;
7102 cpu_arch_tune = cpu_arch [i].type;
7103 cpu_arch_tune_flags = cpu_arch[i].flags;
7107 if (i >= ARRAY_SIZE (cpu_arch))
7108 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7111 case OPTION_MMNEMONIC:
7112 if (strcasecmp (arg, "att") == 0)
7114 else if (strcasecmp (arg, "intel") == 0)
7117 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7120 case OPTION_MSYNTAX:
7121 if (strcasecmp (arg, "att") == 0)
7123 else if (strcasecmp (arg, "intel") == 0)
7126 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7129 case OPTION_MINDEX_REG:
7130 allow_index_reg = 1;
7133 case OPTION_MNAKED_REG:
7134 allow_naked_reg = 1;
7137 case OPTION_MOLD_GCC:
7149 md_show_usage (stream)
7152 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7153 fprintf (stream, _("\
7155 -V print assembler version number\n\
7158 fprintf (stream, _("\
7159 -n Do not optimize code alignment\n\
7160 -q quieten some warnings\n"));
7161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7162 fprintf (stream, _("\
7165 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7166 fprintf (stream, _("\
7167 --32/--64 generate 32bit/64bit code\n"));
7169 #ifdef SVR4_COMMENT_CHARS
7170 fprintf (stream, _("\
7171 --divide do not treat `/' as a comment character\n"));
7173 fprintf (stream, _("\
7174 --divide ignored\n"));
7176 fprintf (stream, _("\
7177 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7178 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7179 core, core2, k6, athlon, k8, generic32, generic64\n"));
7183 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7184 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7186 /* Pick the target format to use. */
7189 i386_target_format (void)
7191 if (!strcmp (default_arch, "x86_64"))
7193 set_code_flag (CODE_64BIT);
7194 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7196 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7197 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7198 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7199 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7201 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7202 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7203 cpu_arch_isa_flags.bitfield.cpummx= 1;
7204 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7205 cpu_arch_isa_flags.bitfield.cpusse = 1;
7206 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7208 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7210 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7211 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7212 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7213 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7214 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7215 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7216 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7217 cpu_arch_tune_flags.bitfield.cpummx= 1;
7218 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7219 cpu_arch_tune_flags.bitfield.cpusse = 1;
7220 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7223 else if (!strcmp (default_arch, "i386"))
7225 set_code_flag (CODE_32BIT);
7226 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7228 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7229 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7230 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7232 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7234 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7235 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7236 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7240 as_fatal (_("Unknown architecture"));
7241 switch (OUTPUT_FLAVOR)
7244 case bfd_target_coff_flavour:
7245 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7248 #ifdef OBJ_MAYBE_AOUT
7249 case bfd_target_aout_flavour:
7250 return AOUT_TARGET_FORMAT;
7252 #ifdef OBJ_MAYBE_COFF
7253 case bfd_target_coff_flavour:
7256 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7257 case bfd_target_elf_flavour:
7259 if (flag_code == CODE_64BIT)
7262 use_rela_relocations = 1;
7264 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7273 #endif /* OBJ_MAYBE_ more than one */
7275 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7277 i386_elf_emit_arch_note (void)
7279 if (IS_ELF && cpu_arch_name != NULL)
7282 asection *seg = now_seg;
7283 subsegT subseg = now_subseg;
7284 Elf_Internal_Note i_note;
7285 Elf_External_Note e_note;
7286 asection *note_secp;
7289 /* Create the .note section. */
7290 note_secp = subseg_new (".note", 0);
7291 bfd_set_section_flags (stdoutput,
7293 SEC_HAS_CONTENTS | SEC_READONLY);
7295 /* Process the arch string. */
7296 len = strlen (cpu_arch_name);
7298 i_note.namesz = len + 1;
7300 i_note.type = NT_ARCH;
7301 p = frag_more (sizeof (e_note.namesz));
7302 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7303 p = frag_more (sizeof (e_note.descsz));
7304 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7305 p = frag_more (sizeof (e_note.type));
7306 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7307 p = frag_more (len + 1);
7308 strcpy (p, cpu_arch_name);
7310 frag_align (2, 0, 0);
7312 subseg_set (seg, subseg);
7318 md_undefined_symbol (name)
7321 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7322 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7323 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7324 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7328 if (symbol_find (name))
7329 as_bad (_("GOT already in symbol table"));
7330 GOT_symbol = symbol_new (name, undefined_section,
7331 (valueT) 0, &zero_address_frag);
7338 /* Round up a section size to the appropriate boundary. */
7341 md_section_align (segment, size)
7342 segT segment ATTRIBUTE_UNUSED;
7345 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7346 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7348 /* For a.out, force the section size to be aligned. If we don't do
7349 this, BFD will align it for us, but it will not write out the
7350 final bytes of the section. This may be a bug in BFD, but it is
7351 easier to fix it here since that is how the other a.out targets
7355 align = bfd_get_section_alignment (stdoutput, segment);
7356 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7363 /* On the i386, PC-relative offsets are relative to the start of the
7364 next instruction. That is, the address of the offset, plus its
7365 size, since the offset is always the last part of the insn. */
7368 md_pcrel_from (fixS *fixP)
7370 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7376 s_bss (int ignore ATTRIBUTE_UNUSED)
7380 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7382 obj_elf_section_change_hook ();
7384 temp = get_absolute_expression ();
7385 subseg_set (bss_section, (subsegT) temp);
7386 demand_empty_rest_of_line ();
7392 i386_validate_fix (fixS *fixp)
7394 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7396 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7400 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7405 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7407 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7414 tc_gen_reloc (section, fixp)
7415 asection *section ATTRIBUTE_UNUSED;
7419 bfd_reloc_code_real_type code;
7421 switch (fixp->fx_r_type)
7423 case BFD_RELOC_X86_64_PLT32:
7424 case BFD_RELOC_X86_64_GOT32:
7425 case BFD_RELOC_X86_64_GOTPCREL:
7426 case BFD_RELOC_386_PLT32:
7427 case BFD_RELOC_386_GOT32:
7428 case BFD_RELOC_386_GOTOFF:
7429 case BFD_RELOC_386_GOTPC:
7430 case BFD_RELOC_386_TLS_GD:
7431 case BFD_RELOC_386_TLS_LDM:
7432 case BFD_RELOC_386_TLS_LDO_32:
7433 case BFD_RELOC_386_TLS_IE_32:
7434 case BFD_RELOC_386_TLS_IE:
7435 case BFD_RELOC_386_TLS_GOTIE:
7436 case BFD_RELOC_386_TLS_LE_32:
7437 case BFD_RELOC_386_TLS_LE:
7438 case BFD_RELOC_386_TLS_GOTDESC:
7439 case BFD_RELOC_386_TLS_DESC_CALL:
7440 case BFD_RELOC_X86_64_TLSGD:
7441 case BFD_RELOC_X86_64_TLSLD:
7442 case BFD_RELOC_X86_64_DTPOFF32:
7443 case BFD_RELOC_X86_64_DTPOFF64:
7444 case BFD_RELOC_X86_64_GOTTPOFF:
7445 case BFD_RELOC_X86_64_TPOFF32:
7446 case BFD_RELOC_X86_64_TPOFF64:
7447 case BFD_RELOC_X86_64_GOTOFF64:
7448 case BFD_RELOC_X86_64_GOTPC32:
7449 case BFD_RELOC_X86_64_GOT64:
7450 case BFD_RELOC_X86_64_GOTPCREL64:
7451 case BFD_RELOC_X86_64_GOTPC64:
7452 case BFD_RELOC_X86_64_GOTPLT64:
7453 case BFD_RELOC_X86_64_PLTOFF64:
7454 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7455 case BFD_RELOC_X86_64_TLSDESC_CALL:
7457 case BFD_RELOC_VTABLE_ENTRY:
7458 case BFD_RELOC_VTABLE_INHERIT:
7460 case BFD_RELOC_32_SECREL:
7462 code = fixp->fx_r_type;
7464 case BFD_RELOC_X86_64_32S:
7465 if (!fixp->fx_pcrel)
7467 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7468 code = fixp->fx_r_type;
7474 switch (fixp->fx_size)
7477 as_bad_where (fixp->fx_file, fixp->fx_line,
7478 _("can not do %d byte pc-relative relocation"),
7480 code = BFD_RELOC_32_PCREL;
7482 case 1: code = BFD_RELOC_8_PCREL; break;
7483 case 2: code = BFD_RELOC_16_PCREL; break;
7484 case 4: code = BFD_RELOC_32_PCREL; break;
7486 case 8: code = BFD_RELOC_64_PCREL; break;
7492 switch (fixp->fx_size)
7495 as_bad_where (fixp->fx_file, fixp->fx_line,
7496 _("can not do %d byte relocation"),
7498 code = BFD_RELOC_32;
7500 case 1: code = BFD_RELOC_8; break;
7501 case 2: code = BFD_RELOC_16; break;
7502 case 4: code = BFD_RELOC_32; break;
7504 case 8: code = BFD_RELOC_64; break;
7511 if ((code == BFD_RELOC_32
7512 || code == BFD_RELOC_32_PCREL
7513 || code == BFD_RELOC_X86_64_32S)
7515 && fixp->fx_addsy == GOT_symbol)
7518 code = BFD_RELOC_386_GOTPC;
7520 code = BFD_RELOC_X86_64_GOTPC32;
7522 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7524 && fixp->fx_addsy == GOT_symbol)
7526 code = BFD_RELOC_X86_64_GOTPC64;
7529 rel = (arelent *) xmalloc (sizeof (arelent));
7530 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7531 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7533 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7535 if (!use_rela_relocations)
7537 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7538 vtable entry to be used in the relocation's section offset. */
7539 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7540 rel->address = fixp->fx_offset;
7544 /* Use the rela in 64bit mode. */
7547 if (!fixp->fx_pcrel)
7548 rel->addend = fixp->fx_offset;
7552 case BFD_RELOC_X86_64_PLT32:
7553 case BFD_RELOC_X86_64_GOT32:
7554 case BFD_RELOC_X86_64_GOTPCREL:
7555 case BFD_RELOC_X86_64_TLSGD:
7556 case BFD_RELOC_X86_64_TLSLD:
7557 case BFD_RELOC_X86_64_GOTTPOFF:
7558 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7559 case BFD_RELOC_X86_64_TLSDESC_CALL:
7560 rel->addend = fixp->fx_offset - fixp->fx_size;
7563 rel->addend = (section->vma
7565 + fixp->fx_addnumber
7566 + md_pcrel_from (fixp));
7571 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7572 if (rel->howto == NULL)
7574 as_bad_where (fixp->fx_file, fixp->fx_line,
7575 _("cannot represent relocation type %s"),
7576 bfd_get_reloc_code_name (code));
7577 /* Set howto to a garbage value so that we can keep going. */
7578 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7579 assert (rel->howto != NULL);
7586 /* Parse operands using Intel syntax. This implements a recursive descent
7587 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7590 FIXME: We do not recognize the full operand grammar defined in the MASM
7591 documentation. In particular, all the structure/union and
7592 high-level macro operands are missing.
7594 Uppercase words are terminals, lower case words are non-terminals.
7595 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7596 bars '|' denote choices. Most grammar productions are implemented in
7597 functions called 'intel_<production>'.
7599 Initial production is 'expr'.
7605 binOp & | AND | \| | OR | ^ | XOR
7607 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7609 constant digits [[ radixOverride ]]
7611 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7649 => expr expr cmpOp e04
7652 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7653 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7655 hexdigit a | b | c | d | e | f
7656 | A | B | C | D | E | F
7662 mulOp * | / | % | MOD | << | SHL | >> | SHR
7666 register specialRegister
7670 segmentRegister CS | DS | ES | FS | GS | SS
7672 specialRegister CR0 | CR2 | CR3 | CR4
7673 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7674 | TR3 | TR4 | TR5 | TR6 | TR7
7676 We simplify the grammar in obvious places (e.g., register parsing is
7677 done by calling parse_register) and eliminate immediate left recursion
7678 to implement a recursive-descent parser.
7682 expr' cmpOp e04 expr'
7733 /* Parsing structure for the intel syntax parser. Used to implement the
7734 semantic actions for the operand grammar. */
7735 struct intel_parser_s
7737 char *op_string; /* The string being parsed. */
7738 int got_a_float; /* Whether the operand is a float. */
7739 int op_modifier; /* Operand modifier. */
7740 int is_mem; /* 1 if operand is memory reference. */
7741 int in_offset; /* >=1 if parsing operand of offset. */
7742 int in_bracket; /* >=1 if parsing operand in brackets. */
7743 const reg_entry *reg; /* Last register reference found. */
7744 char *disp; /* Displacement string being built. */
7745 char *next_operand; /* Resume point when splitting operands. */
7748 static struct intel_parser_s intel_parser;
7750 /* Token structure for parsing intel syntax. */
7753 int code; /* Token code. */
7754 const reg_entry *reg; /* Register entry for register tokens. */
7755 char *str; /* String representation. */
7758 static struct intel_token cur_token, prev_token;
7760 /* Token codes for the intel parser. Since T_SHORT is already used
7761 by COFF, undefine it first to prevent a warning. */
7780 /* Prototypes for intel parser functions. */
7781 static int intel_match_token (int);
7782 static void intel_putback_token (void);
7783 static void intel_get_token (void);
7784 static int intel_expr (void);
7785 static int intel_e04 (void);
7786 static int intel_e05 (void);
7787 static int intel_e06 (void);
7788 static int intel_e09 (void);
7789 static int intel_e10 (void);
7790 static int intel_e11 (void);
7793 i386_intel_operand (char *operand_string, int got_a_float)
7798 p = intel_parser.op_string = xstrdup (operand_string);
7799 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7803 /* Initialize token holders. */
7804 cur_token.code = prev_token.code = T_NIL;
7805 cur_token.reg = prev_token.reg = NULL;
7806 cur_token.str = prev_token.str = NULL;
7808 /* Initialize parser structure. */
7809 intel_parser.got_a_float = got_a_float;
7810 intel_parser.op_modifier = 0;
7811 intel_parser.is_mem = 0;
7812 intel_parser.in_offset = 0;
7813 intel_parser.in_bracket = 0;
7814 intel_parser.reg = NULL;
7815 intel_parser.disp[0] = '\0';
7816 intel_parser.next_operand = NULL;
7818 /* Read the first token and start the parser. */
7820 ret = intel_expr ();
7825 if (cur_token.code != T_NIL)
7827 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7828 current_templates->start->name, cur_token.str);
7831 /* If we found a memory reference, hand it over to i386_displacement
7832 to fill in the rest of the operand fields. */
7833 else if (intel_parser.is_mem)
7835 if ((i.mem_operands == 1
7836 && !current_templates->start->opcode_modifier.isstring)
7837 || i.mem_operands == 2)
7839 as_bad (_("too many memory references for '%s'"),
7840 current_templates->start->name);
7845 char *s = intel_parser.disp;
7848 if (!quiet_warnings && intel_parser.is_mem < 0)
7849 /* See the comments in intel_bracket_expr. */
7850 as_warn (_("Treating `%s' as memory reference"), operand_string);
7852 /* Add the displacement expression. */
7854 ret = i386_displacement (s, s + strlen (s));
7857 /* Swap base and index in 16-bit memory operands like
7858 [si+bx]. Since i386_index_check is also used in AT&T
7859 mode we have to do that here. */
7862 && i.base_reg->reg_type.bitfield.reg16
7863 && i.index_reg->reg_type.bitfield.reg16
7864 && i.base_reg->reg_num >= 6
7865 && i.index_reg->reg_num < 6)
7867 const reg_entry *base = i.index_reg;
7869 i.index_reg = i.base_reg;
7872 ret = i386_index_check (operand_string);
7877 /* Constant and OFFSET expressions are handled by i386_immediate. */
7878 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7879 || intel_parser.reg == NULL)
7880 ret = i386_immediate (intel_parser.disp);
7882 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7884 if (!ret || !intel_parser.next_operand)
7886 intel_parser.op_string = intel_parser.next_operand;
7887 this_operand = i.operands++;
7891 free (intel_parser.disp);
7896 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7900 expr' cmpOp e04 expr'
7905 /* XXX Implement the comparison operators. */
7906 return intel_e04 ();
7923 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7924 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7926 if (cur_token.code == '+')
7928 else if (cur_token.code == '-')
7929 nregs = NUM_ADDRESS_REGS;
7933 strcat (intel_parser.disp, cur_token.str);
7934 intel_match_token (cur_token.code);
7945 int nregs = ~NUM_ADDRESS_REGS;
7952 if (cur_token.code == '&'
7953 || cur_token.code == '|'
7954 || cur_token.code == '^')
7958 str[0] = cur_token.code;
7960 strcat (intel_parser.disp, str);
7965 intel_match_token (cur_token.code);
7970 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7971 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7982 int nregs = ~NUM_ADDRESS_REGS;
7989 if (cur_token.code == '*'
7990 || cur_token.code == '/'
7991 || cur_token.code == '%')
7995 str[0] = cur_token.code;
7997 strcat (intel_parser.disp, str);
7999 else if (cur_token.code == T_SHL)
8000 strcat (intel_parser.disp, "<<");
8001 else if (cur_token.code == T_SHR)
8002 strcat (intel_parser.disp, ">>");
8006 intel_match_token (cur_token.code);
8011 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8012 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8030 int nregs = ~NUM_ADDRESS_REGS;
8035 /* Don't consume constants here. */
8036 if (cur_token.code == '+' || cur_token.code == '-')
8038 /* Need to look one token ahead - if the next token
8039 is a constant, the current token is its sign. */
8042 intel_match_token (cur_token.code);
8043 next_code = cur_token.code;
8044 intel_putback_token ();
8045 if (next_code == T_CONST)
8049 /* e09 OFFSET e09 */
8050 if (cur_token.code == T_OFFSET)
8053 ++intel_parser.in_offset;
8057 else if (cur_token.code == T_SHORT)
8058 intel_parser.op_modifier |= 1 << T_SHORT;
8061 else if (cur_token.code == '+')
8062 strcat (intel_parser.disp, "+");
8067 else if (cur_token.code == '-' || cur_token.code == '~')
8073 str[0] = cur_token.code;
8075 strcat (intel_parser.disp, str);
8082 intel_match_token (cur_token.code);
8090 /* e09' PTR e10 e09' */
8091 if (cur_token.code == T_PTR)
8095 if (prev_token.code == T_BYTE)
8096 suffix = BYTE_MNEM_SUFFIX;
8098 else if (prev_token.code == T_WORD)
8100 if (current_templates->start->name[0] == 'l'
8101 && current_templates->start->name[2] == 's'
8102 && current_templates->start->name[3] == 0)
8103 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8104 else if (intel_parser.got_a_float == 2) /* "fi..." */
8105 suffix = SHORT_MNEM_SUFFIX;
8107 suffix = WORD_MNEM_SUFFIX;
8110 else if (prev_token.code == T_DWORD)
8112 if (current_templates->start->name[0] == 'l'
8113 && current_templates->start->name[2] == 's'
8114 && current_templates->start->name[3] == 0)
8115 suffix = WORD_MNEM_SUFFIX;
8116 else if (flag_code == CODE_16BIT
8117 && (current_templates->start->opcode_modifier.jump
8118 || current_templates->start->opcode_modifier.jumpdword))
8119 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8120 else if (intel_parser.got_a_float == 1) /* "f..." */
8121 suffix = SHORT_MNEM_SUFFIX;
8123 suffix = LONG_MNEM_SUFFIX;
8126 else if (prev_token.code == T_FWORD)
8128 if (current_templates->start->name[0] == 'l'
8129 && current_templates->start->name[2] == 's'
8130 && current_templates->start->name[3] == 0)
8131 suffix = LONG_MNEM_SUFFIX;
8132 else if (!intel_parser.got_a_float)
8134 if (flag_code == CODE_16BIT)
8135 add_prefix (DATA_PREFIX_OPCODE);
8136 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8139 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8142 else if (prev_token.code == T_QWORD)
8144 if (intel_parser.got_a_float == 1) /* "f..." */
8145 suffix = LONG_MNEM_SUFFIX;
8147 suffix = QWORD_MNEM_SUFFIX;
8150 else if (prev_token.code == T_TBYTE)
8152 if (intel_parser.got_a_float == 1)
8153 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8155 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8158 else if (prev_token.code == T_XMMWORD)
8160 /* XXX ignored for now, but accepted since gcc uses it */
8166 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8170 /* Operands for jump/call using 'ptr' notation denote absolute
8172 if (current_templates->start->opcode_modifier.jump
8173 || current_templates->start->opcode_modifier.jumpdword)
8174 i.types[this_operand].bitfield.jumpabsolute = 1;
8176 if (current_templates->start->base_opcode == 0x8d /* lea */)
8180 else if (i.suffix != suffix)
8182 as_bad (_("Conflicting operand modifiers"));
8188 /* e09' : e10 e09' */
8189 else if (cur_token.code == ':')
8191 if (prev_token.code != T_REG)
8193 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8194 segment/group identifier (which we don't have), using comma
8195 as the operand separator there is even less consistent, since
8196 there all branches only have a single operand. */
8197 if (this_operand != 0
8198 || intel_parser.in_offset
8199 || intel_parser.in_bracket
8200 || (!current_templates->start->opcode_modifier.jump
8201 && !current_templates->start->opcode_modifier.jumpdword
8202 && !current_templates->start->opcode_modifier.jumpintersegment
8203 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8204 return intel_match_token (T_NIL);
8205 /* Remember the start of the 2nd operand and terminate 1st
8207 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8208 another expression), but it gets at least the simplest case
8209 (a plain number or symbol on the left side) right. */
8210 intel_parser.next_operand = intel_parser.op_string;
8211 *--intel_parser.op_string = '\0';
8212 return intel_match_token (':');
8220 intel_match_token (cur_token.code);
8226 --intel_parser.in_offset;
8229 if (NUM_ADDRESS_REGS > nregs)
8231 as_bad (_("Invalid operand to `OFFSET'"));
8234 intel_parser.op_modifier |= 1 << T_OFFSET;
8237 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8238 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8243 intel_bracket_expr (void)
8245 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8246 const char *start = intel_parser.op_string;
8249 if (i.op[this_operand].regs)
8250 return intel_match_token (T_NIL);
8252 intel_match_token ('[');
8254 /* Mark as a memory operand only if it's not already known to be an
8255 offset expression. If it's an offset expression, we need to keep
8257 if (!intel_parser.in_offset)
8259 ++intel_parser.in_bracket;
8261 /* Operands for jump/call inside brackets denote absolute addresses. */
8262 if (current_templates->start->opcode_modifier.jump
8263 || current_templates->start->opcode_modifier.jumpdword)
8264 i.types[this_operand].bitfield.jumpabsolute = 1;
8266 /* Unfortunately gas always diverged from MASM in a respect that can't
8267 be easily fixed without risking to break code sequences likely to be
8268 encountered (the testsuite even check for this): MASM doesn't consider
8269 an expression inside brackets unconditionally as a memory reference.
8270 When that is e.g. a constant, an offset expression, or the sum of the
8271 two, this is still taken as a constant load. gas, however, always
8272 treated these as memory references. As a compromise, we'll try to make
8273 offset expressions inside brackets work the MASM way (since that's
8274 less likely to be found in real world code), but make constants alone
8275 continue to work the traditional gas way. In either case, issue a
8277 intel_parser.op_modifier &= ~was_offset;
8280 strcat (intel_parser.disp, "[");
8282 /* Add a '+' to the displacement string if necessary. */
8283 if (*intel_parser.disp != '\0'
8284 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8285 strcat (intel_parser.disp, "+");
8288 && (len = intel_parser.op_string - start - 1,
8289 intel_match_token (']')))
8291 /* Preserve brackets when the operand is an offset expression. */
8292 if (intel_parser.in_offset)
8293 strcat (intel_parser.disp, "]");
8296 --intel_parser.in_bracket;
8297 if (i.base_reg || i.index_reg)
8298 intel_parser.is_mem = 1;
8299 if (!intel_parser.is_mem)
8301 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8302 /* Defer the warning until all of the operand was parsed. */
8303 intel_parser.is_mem = -1;
8304 else if (!quiet_warnings)
8305 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8306 len, start, len, start);
8309 intel_parser.op_modifier |= was_offset;
8326 while (cur_token.code == '[')
8328 if (!intel_bracket_expr ())
8353 switch (cur_token.code)
8357 intel_match_token ('(');
8358 strcat (intel_parser.disp, "(");
8360 if (intel_expr () && intel_match_token (')'))
8362 strcat (intel_parser.disp, ")");
8369 return intel_bracket_expr ();
8374 strcat (intel_parser.disp, cur_token.str);
8375 intel_match_token (cur_token.code);
8377 /* Mark as a memory operand only if it's not already known to be an
8378 offset expression. */
8379 if (!intel_parser.in_offset)
8380 intel_parser.is_mem = 1;
8387 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8389 intel_match_token (T_REG);
8391 /* Check for segment change. */
8392 if (cur_token.code == ':')
8394 if (!reg->reg_type.bitfield.sreg2
8395 && !reg->reg_type.bitfield.sreg3)
8397 as_bad (_("`%s' is not a valid segment register"),
8401 else if (i.seg[i.mem_operands])
8402 as_warn (_("Extra segment override ignored"));
8405 if (!intel_parser.in_offset)
8406 intel_parser.is_mem = 1;
8407 switch (reg->reg_num)
8410 i.seg[i.mem_operands] = &es;
8413 i.seg[i.mem_operands] = &cs;
8416 i.seg[i.mem_operands] = &ss;
8419 i.seg[i.mem_operands] = &ds;
8422 i.seg[i.mem_operands] = &fs;
8425 i.seg[i.mem_operands] = &gs;
8431 /* Not a segment register. Check for register scaling. */
8432 else if (cur_token.code == '*')
8434 if (!intel_parser.in_bracket)
8436 as_bad (_("Register scaling only allowed in memory operands"));
8440 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8441 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8442 else if (i.index_reg)
8443 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8445 /* What follows must be a valid scale. */
8446 intel_match_token ('*');
8448 i.types[this_operand].bitfield.baseindex = 1;
8450 /* Set the scale after setting the register (otherwise,
8451 i386_scale will complain) */
8452 if (cur_token.code == '+' || cur_token.code == '-')
8454 char *str, sign = cur_token.code;
8455 intel_match_token (cur_token.code);
8456 if (cur_token.code != T_CONST)
8458 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8462 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8463 strcpy (str + 1, cur_token.str);
8465 if (!i386_scale (str))
8469 else if (!i386_scale (cur_token.str))
8471 intel_match_token (cur_token.code);
8474 /* No scaling. If this is a memory operand, the register is either a
8475 base register (first occurrence) or an index register (second
8477 else if (intel_parser.in_bracket)
8482 else if (!i.index_reg)
8486 as_bad (_("Too many register references in memory operand"));
8490 i.types[this_operand].bitfield.baseindex = 1;
8493 /* It's neither base nor index. */
8494 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8496 i386_operand_type temp = reg->reg_type;
8497 temp.bitfield.baseindex = 0;
8498 i.types[this_operand] = operand_type_or (i.types[this_operand],
8500 i.op[this_operand].regs = reg;
8505 as_bad (_("Invalid use of register"));
8509 /* Since registers are not part of the displacement string (except
8510 when we're parsing offset operands), we may need to remove any
8511 preceding '+' from the displacement string. */
8512 if (*intel_parser.disp != '\0'
8513 && !intel_parser.in_offset)
8515 char *s = intel_parser.disp;
8516 s += strlen (s) - 1;
8539 intel_match_token (cur_token.code);
8541 if (cur_token.code == T_PTR)
8544 /* It must have been an identifier. */
8545 intel_putback_token ();
8546 cur_token.code = T_ID;
8552 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8556 /* The identifier represents a memory reference only if it's not
8557 preceded by an offset modifier and if it's not an equate. */
8558 symbolP = symbol_find(cur_token.str);
8559 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8560 intel_parser.is_mem = 1;
8568 char *save_str, sign = 0;
8570 /* Allow constants that start with `+' or `-'. */
8571 if (cur_token.code == '-' || cur_token.code == '+')
8573 sign = cur_token.code;
8574 intel_match_token (cur_token.code);
8575 if (cur_token.code != T_CONST)
8577 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8583 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8584 strcpy (save_str + !!sign, cur_token.str);
8588 /* Get the next token to check for register scaling. */
8589 intel_match_token (cur_token.code);
8591 /* Check if this constant is a scaling factor for an
8593 if (cur_token.code == '*')
8595 if (intel_match_token ('*') && cur_token.code == T_REG)
8597 const reg_entry *reg = cur_token.reg;
8599 if (!intel_parser.in_bracket)
8601 as_bad (_("Register scaling only allowed "
8602 "in memory operands"));
8606 /* Disallow things like [1*si].
8607 sp and esp are invalid as index. */
8608 if (reg->reg_type.bitfield.reg16)
8609 reg = i386_regtab + REGNAM_AX + 4;
8610 else if (i.index_reg)
8611 reg = i386_regtab + REGNAM_EAX + 4;
8613 /* The constant is followed by `* reg', so it must be
8616 i.types[this_operand].bitfield.baseindex = 1;
8618 /* Set the scale after setting the register (otherwise,
8619 i386_scale will complain) */
8620 if (!i386_scale (save_str))
8622 intel_match_token (T_REG);
8624 /* Since registers are not part of the displacement
8625 string, we may need to remove any preceding '+' from
8626 the displacement string. */
8627 if (*intel_parser.disp != '\0')
8629 char *s = intel_parser.disp;
8630 s += strlen (s) - 1;
8640 /* The constant was not used for register scaling. Since we have
8641 already consumed the token following `*' we now need to put it
8642 back in the stream. */
8643 intel_putback_token ();
8646 /* Add the constant to the displacement string. */
8647 strcat (intel_parser.disp, save_str);
8654 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8658 /* Match the given token against cur_token. If they match, read the next
8659 token from the operand string. */
8661 intel_match_token (int code)
8663 if (cur_token.code == code)
8670 as_bad (_("Unexpected token `%s'"), cur_token.str);
8675 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8677 intel_get_token (void)
8680 const reg_entry *reg;
8681 struct intel_token new_token;
8683 new_token.code = T_NIL;
8684 new_token.reg = NULL;
8685 new_token.str = NULL;
8687 /* Free the memory allocated to the previous token and move
8688 cur_token to prev_token. */
8690 free (prev_token.str);
8692 prev_token = cur_token;
8694 /* Skip whitespace. */
8695 while (is_space_char (*intel_parser.op_string))
8696 intel_parser.op_string++;
8698 /* Return an empty token if we find nothing else on the line. */
8699 if (*intel_parser.op_string == '\0')
8701 cur_token = new_token;
8705 /* The new token cannot be larger than the remainder of the operand
8707 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8708 new_token.str[0] = '\0';
8710 if (strchr ("0123456789", *intel_parser.op_string))
8712 char *p = new_token.str;
8713 char *q = intel_parser.op_string;
8714 new_token.code = T_CONST;
8716 /* Allow any kind of identifier char to encompass floating point and
8717 hexadecimal numbers. */
8718 while (is_identifier_char (*q))
8722 /* Recognize special symbol names [0-9][bf]. */
8723 if (strlen (intel_parser.op_string) == 2
8724 && (intel_parser.op_string[1] == 'b'
8725 || intel_parser.op_string[1] == 'f'))
8726 new_token.code = T_ID;
8729 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8731 size_t len = end_op - intel_parser.op_string;
8733 new_token.code = T_REG;
8734 new_token.reg = reg;
8736 memcpy (new_token.str, intel_parser.op_string, len);
8737 new_token.str[len] = '\0';
8740 else if (is_identifier_char (*intel_parser.op_string))
8742 char *p = new_token.str;
8743 char *q = intel_parser.op_string;
8745 /* A '.' or '$' followed by an identifier char is an identifier.
8746 Otherwise, it's operator '.' followed by an expression. */
8747 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8749 new_token.code = '.';
8750 new_token.str[0] = '.';
8751 new_token.str[1] = '\0';
8755 while (is_identifier_char (*q) || *q == '@')
8759 if (strcasecmp (new_token.str, "NOT") == 0)
8760 new_token.code = '~';
8762 else if (strcasecmp (new_token.str, "MOD") == 0)
8763 new_token.code = '%';
8765 else if (strcasecmp (new_token.str, "AND") == 0)
8766 new_token.code = '&';
8768 else if (strcasecmp (new_token.str, "OR") == 0)
8769 new_token.code = '|';
8771 else if (strcasecmp (new_token.str, "XOR") == 0)
8772 new_token.code = '^';
8774 else if (strcasecmp (new_token.str, "SHL") == 0)
8775 new_token.code = T_SHL;
8777 else if (strcasecmp (new_token.str, "SHR") == 0)
8778 new_token.code = T_SHR;
8780 else if (strcasecmp (new_token.str, "BYTE") == 0)
8781 new_token.code = T_BYTE;
8783 else if (strcasecmp (new_token.str, "WORD") == 0)
8784 new_token.code = T_WORD;
8786 else if (strcasecmp (new_token.str, "DWORD") == 0)
8787 new_token.code = T_DWORD;
8789 else if (strcasecmp (new_token.str, "FWORD") == 0)
8790 new_token.code = T_FWORD;
8792 else if (strcasecmp (new_token.str, "QWORD") == 0)
8793 new_token.code = T_QWORD;
8795 else if (strcasecmp (new_token.str, "TBYTE") == 0
8796 /* XXX remove (gcc still uses it) */
8797 || strcasecmp (new_token.str, "XWORD") == 0)
8798 new_token.code = T_TBYTE;
8800 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8801 || strcasecmp (new_token.str, "OWORD") == 0)
8802 new_token.code = T_XMMWORD;
8804 else if (strcasecmp (new_token.str, "PTR") == 0)
8805 new_token.code = T_PTR;
8807 else if (strcasecmp (new_token.str, "SHORT") == 0)
8808 new_token.code = T_SHORT;
8810 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8812 new_token.code = T_OFFSET;
8814 /* ??? This is not mentioned in the MASM grammar but gcc
8815 makes use of it with -mintel-syntax. OFFSET may be
8816 followed by FLAT: */
8817 if (strncasecmp (q, " FLAT:", 6) == 0)
8818 strcat (new_token.str, " FLAT:");
8821 /* ??? This is not mentioned in the MASM grammar. */
8822 else if (strcasecmp (new_token.str, "FLAT") == 0)
8824 new_token.code = T_OFFSET;
8826 strcat (new_token.str, ":");
8828 as_bad (_("`:' expected"));
8832 new_token.code = T_ID;
8836 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8838 new_token.code = *intel_parser.op_string;
8839 new_token.str[0] = *intel_parser.op_string;
8840 new_token.str[1] = '\0';
8843 else if (strchr ("<>", *intel_parser.op_string)
8844 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8846 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8847 new_token.str[0] = *intel_parser.op_string;
8848 new_token.str[1] = *intel_parser.op_string;
8849 new_token.str[2] = '\0';
8853 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8855 intel_parser.op_string += strlen (new_token.str);
8856 cur_token = new_token;
8859 /* Put cur_token back into the token stream and make cur_token point to
8862 intel_putback_token (void)
8864 if (cur_token.code != T_NIL)
8866 intel_parser.op_string -= strlen (cur_token.str);
8867 free (cur_token.str);
8869 cur_token = prev_token;
8871 /* Forget prev_token. */
8872 prev_token.code = T_NIL;
8873 prev_token.reg = NULL;
8874 prev_token.str = NULL;
8878 tc_x86_regname_to_dw2regnum (char *regname)
8880 unsigned int regnum;
8881 unsigned int regnames_count;
8882 static const char *const regnames_32[] =
8884 "eax", "ecx", "edx", "ebx",
8885 "esp", "ebp", "esi", "edi",
8886 "eip", "eflags", NULL,
8887 "st0", "st1", "st2", "st3",
8888 "st4", "st5", "st6", "st7",
8890 "xmm0", "xmm1", "xmm2", "xmm3",
8891 "xmm4", "xmm5", "xmm6", "xmm7",
8892 "mm0", "mm1", "mm2", "mm3",
8893 "mm4", "mm5", "mm6", "mm7",
8894 "fcw", "fsw", "mxcsr",
8895 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8898 static const char *const regnames_64[] =
8900 "rax", "rdx", "rcx", "rbx",
8901 "rsi", "rdi", "rbp", "rsp",
8902 "r8", "r9", "r10", "r11",
8903 "r12", "r13", "r14", "r15",
8905 "xmm0", "xmm1", "xmm2", "xmm3",
8906 "xmm4", "xmm5", "xmm6", "xmm7",
8907 "xmm8", "xmm9", "xmm10", "xmm11",
8908 "xmm12", "xmm13", "xmm14", "xmm15",
8909 "st0", "st1", "st2", "st3",
8910 "st4", "st5", "st6", "st7",
8911 "mm0", "mm1", "mm2", "mm3",
8912 "mm4", "mm5", "mm6", "mm7",
8914 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8915 "fs.base", "gs.base", NULL, NULL,
8917 "mxcsr", "fcw", "fsw"
8919 const char *const *regnames;
8921 if (flag_code == CODE_64BIT)
8923 regnames = regnames_64;
8924 regnames_count = ARRAY_SIZE (regnames_64);
8928 regnames = regnames_32;
8929 regnames_count = ARRAY_SIZE (regnames_32);
8932 for (regnum = 0; regnum < regnames_count; regnum++)
8933 if (regnames[regnum] != NULL
8934 && strcmp (regname, regnames[regnum]) == 0)
8941 tc_x86_frame_initial_instructions (void)
8943 static unsigned int sp_regno;
8946 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8949 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8950 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8954 i386_elf_section_type (const char *str, size_t len)
8956 if (flag_code == CODE_64BIT
8957 && len == sizeof ("unwind") - 1
8958 && strncmp (str, "unwind", 6) == 0)
8959 return SHT_X86_64_UNWIND;
8966 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8970 expr.X_op = O_secrel;
8971 expr.X_add_symbol = symbol;
8972 expr.X_add_number = 0;
8973 emit_expr (&expr, size);
8977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8978 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8981 x86_64_section_letter (int letter, char **ptr_msg)
8983 if (flag_code == CODE_64BIT)
8986 return SHF_X86_64_LARGE;
8988 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8991 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8996 x86_64_section_word (char *str, size_t len)
8998 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8999 return SHF_X86_64_LARGE;
9005 handle_large_common (int small ATTRIBUTE_UNUSED)
9007 if (flag_code != CODE_64BIT)
9009 s_comm_internal (0, elf_common_parse);
9010 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9014 static segT lbss_section;
9015 asection *saved_com_section_ptr = elf_com_section_ptr;
9016 asection *saved_bss_section = bss_section;
9018 if (lbss_section == NULL)
9020 flagword applicable;
9022 subsegT subseg = now_subseg;
9024 /* The .lbss section is for local .largecomm symbols. */
9025 lbss_section = subseg_new (".lbss", 0);
9026 applicable = bfd_applicable_section_flags (stdoutput);
9027 bfd_set_section_flags (stdoutput, lbss_section,
9028 applicable & SEC_ALLOC);
9029 seg_info (lbss_section)->bss = 1;
9031 subseg_set (seg, subseg);
9034 elf_com_section_ptr = &_bfd_elf_large_com_section;
9035 bss_section = lbss_section;
9037 s_comm_internal (0, elf_common_parse);
9039 elf_com_section_ptr = saved_com_section_ptr;
9040 bss_section = saved_bss_section;
9043 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */