1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c);
69 static int i386_att_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry *parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry *build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS *, offsetT);
91 static void output_disp (fragS *, offsetT);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED);
99 static const char *default_arch = DEFAULT_ARCH;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry *regs;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types[MAX_OPERANDS];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op[MAX_OPERANDS];
136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry *seg[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars = "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars = "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "#/";
210 const char line_separator_chars[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars[256];
223 static char register_chars[256];
224 static char operand_chars[256];
225 static char identifier_chars[256];
226 static char digit_chars[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack[32];
244 static char *save_stack_p;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates *current_templates;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
260 /* Current operand we are working on. */
261 static int this_operand;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code;
272 static unsigned int object_64bit;
273 static int use_rela_relocations = 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names[] =
283 /* 1 for intel syntax,
285 static int intel_syntax = 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic = !SYSV386_COMPAT;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc = OLDGCC_COMPAT;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg = 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix = "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code = 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings = 0;
315 static const char *cpu_arch_name = NULL;
316 static const char *cpu_sub_arch_name = NULL;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragS *fragP, int count)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1[] =
576 static const char f32_2[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
639 static const char alt_3[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code == CODE_16BIT)
769 memcpy (fragP->fr_literal + fragP->fr_fix,
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
780 const char *const *patt = NULL;
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags.bitfield.cpui686)
791 patt = alt_long_patt;
795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
804 case PROCESSOR_ATHLON:
806 case PROCESSOR_AMDFAM10:
807 patt = alt_short_patt;
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
819 switch (cpu_arch_tune)
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM:
831 case PROCESSOR_ATHLON:
833 case PROCESSOR_AMDFAM10:
834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags.bitfield.cpui686)
838 patt = alt_short_patt;
842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE2:
847 if (cpu_arch_isa_flags.bitfield.cpui686)
848 patt = alt_long_patt;
852 case PROCESSOR_GENERIC64:
853 patt = alt_long_patt;
858 if (patt == f32_patt)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
868 memcpy (fragP->fr_literal + fragP->fr_fix,
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
892 fragP->fr_var = count;
896 uints_all_zero (const unsigned int *x, unsigned int size)
914 uints_set (unsigned int *x, unsigned int v, unsigned int size)
931 uints_equal (const unsigned int *x, const unsigned int *y,
943 return x[0] == y [0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f)
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
969 switch (ARRAY_SIZE (x.array))
972 x.array [2] &= y.array [2];
974 x.array [1] &= y.array [1];
976 x.array [0] &= y.array [0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
987 switch (ARRAY_SIZE (x.array))
990 x.array [2] |= y.array [2];
992 x.array [1] |= y.array [1];
994 x.array [0] |= y.array [0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x)
1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1013 if (UINTS_ALL_ZERO (x))
1017 i386_cpu_flags cpu = cpu_arch_flags;
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x, i386_operand_type y)
1030 switch (ARRAY_SIZE (x.array))
1033 x.array [2] &= y.array [2];
1035 x.array [1] &= y.array [1];
1037 x.array [0] &= y.array [0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x, i386_operand_type y)
1048 switch (ARRAY_SIZE (x.array))
1051 x.array [2] |= y.array [2];
1053 x.array [1] |= y.array [1];
1055 x.array [0] |= y.array [0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x, i386_operand_type y)
1066 switch (ARRAY_SIZE (x.array))
1069 x.array [2] ^= y.array [2];
1071 x.array [1] ^= y.array [1];
1073 x.array [0] ^= y.array [0];
1081 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
1092 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1112 operand_type_check (i386_operand_type t, enum operand_type c)
1117 return (t.bitfield.reg8
1120 || t.bitfield.reg64);
1123 return (t.bitfield.imm8
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1151 operand_type_match (i386_operand_type overlap,
1152 i386_operand_type given)
1154 i386_operand_type temp = overlap;
1156 temp.bitfield.jumpabsolute = 0;
1157 if (UINTS_ALL_ZERO (temp))
1160 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1161 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1164 /* If given types r0 and r1 are registers they must be of the same type
1165 unless the expected operand type register overlap is null.
1166 Note that Acc in a template matches every size of reg. */
1169 operand_type_register_match (i386_operand_type m0,
1170 i386_operand_type g0,
1171 i386_operand_type t0,
1172 i386_operand_type m1,
1173 i386_operand_type g1,
1174 i386_operand_type t1)
1176 if (!operand_type_check (g0, reg))
1179 if (!operand_type_check (g1, reg))
1182 if (g0.bitfield.reg8 == g1.bitfield.reg8
1183 && g0.bitfield.reg16 == g1.bitfield.reg16
1184 && g0.bitfield.reg32 == g1.bitfield.reg32
1185 && g0.bitfield.reg64 == g1.bitfield.reg64)
1188 if (m0.bitfield.acc)
1190 t0.bitfield.reg8 = 1;
1191 t0.bitfield.reg16 = 1;
1192 t0.bitfield.reg32 = 1;
1193 t0.bitfield.reg64 = 1;
1196 if (m1.bitfield.acc)
1198 t1.bitfield.reg8 = 1;
1199 t1.bitfield.reg16 = 1;
1200 t1.bitfield.reg32 = 1;
1201 t1.bitfield.reg64 = 1;
1204 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1205 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1206 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1207 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1210 static INLINE unsigned int
1211 mode_from_disp_size (i386_operand_type t)
1213 if (t.bitfield.disp8)
1215 else if (t.bitfield.disp16
1216 || t.bitfield.disp32
1217 || t.bitfield.disp32s)
1224 fits_in_signed_byte (offsetT num)
1226 return (num >= -128) && (num <= 127);
1230 fits_in_unsigned_byte (offsetT num)
1232 return (num & 0xff) == num;
1236 fits_in_unsigned_word (offsetT num)
1238 return (num & 0xffff) == num;
1242 fits_in_signed_word (offsetT num)
1244 return (-32768 <= num) && (num <= 32767);
1248 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1253 return (!(((offsetT) -1 << 31) & num)
1254 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1256 } /* fits_in_signed_long() */
1259 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1264 return (num & (((offsetT) 2 << 31) - 1)) == num;
1266 } /* fits_in_unsigned_long() */
1268 static i386_operand_type
1269 smallest_imm_type (offsetT num)
1271 i386_operand_type t;
1274 t.bitfield.imm64 = 1;
1276 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1278 /* This code is disabled on the 486 because all the Imm1 forms
1279 in the opcode table are slower on the i486. They're the
1280 versions with the implicitly specified single-position
1281 displacement, which has another syntax if you really want to
1283 t.bitfield.imm1 = 1;
1284 t.bitfield.imm8 = 1;
1285 t.bitfield.imm8s = 1;
1286 t.bitfield.imm16 = 1;
1287 t.bitfield.imm32 = 1;
1288 t.bitfield.imm32s = 1;
1290 else if (fits_in_signed_byte (num))
1292 t.bitfield.imm8 = 1;
1293 t.bitfield.imm8s = 1;
1294 t.bitfield.imm16 = 1;
1295 t.bitfield.imm32 = 1;
1296 t.bitfield.imm32s = 1;
1298 else if (fits_in_unsigned_byte (num))
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1305 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1311 else if (fits_in_signed_long (num))
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1316 else if (fits_in_unsigned_long (num))
1317 t.bitfield.imm32 = 1;
1323 offset_in_range (offsetT val, int size)
1329 case 1: mask = ((addressT) 1 << 8) - 1; break;
1330 case 2: mask = ((addressT) 1 << 16) - 1; break;
1331 case 4: mask = ((addressT) 2 << 31) - 1; break;
1333 case 8: mask = ((addressT) 2 << 63) - 1; break;
1338 /* If BFD64, sign extend val. */
1339 if (!use_rela_relocations)
1340 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1341 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1343 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1345 char buf1[40], buf2[40];
1347 sprint_value (buf1, val);
1348 sprint_value (buf2, val & mask);
1349 as_warn (_("%s shortened to %s"), buf1, buf2);
1354 /* Returns 0 if attempting to add a prefix where one from the same
1355 class already exists, 1 if non rep/repne added, 2 if rep/repne
1358 add_prefix (unsigned int prefix)
1363 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1364 && flag_code == CODE_64BIT)
1366 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1367 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1368 && (prefix & (REX_R | REX_X | REX_B))))
1379 case CS_PREFIX_OPCODE:
1380 case DS_PREFIX_OPCODE:
1381 case ES_PREFIX_OPCODE:
1382 case FS_PREFIX_OPCODE:
1383 case GS_PREFIX_OPCODE:
1384 case SS_PREFIX_OPCODE:
1388 case REPNE_PREFIX_OPCODE:
1389 case REPE_PREFIX_OPCODE:
1392 case LOCK_PREFIX_OPCODE:
1400 case ADDR_PREFIX_OPCODE:
1404 case DATA_PREFIX_OPCODE:
1408 if (i.prefix[q] != 0)
1416 i.prefix[q] |= prefix;
1419 as_bad (_("same type of prefix used twice"));
1425 set_code_flag (int value)
1428 if (flag_code == CODE_64BIT)
1430 cpu_arch_flags.bitfield.cpu64 = 1;
1431 cpu_arch_flags.bitfield.cpuno64 = 0;
1435 cpu_arch_flags.bitfield.cpu64 = 0;
1436 cpu_arch_flags.bitfield.cpuno64 = 1;
1438 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1440 as_bad (_("64bit mode not supported on this CPU."));
1442 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1444 as_bad (_("32bit mode not supported on this CPU."));
1446 stackop_size = '\0';
1450 set_16bit_gcc_code_flag (int new_code_flag)
1452 flag_code = new_code_flag;
1453 if (flag_code != CODE_16BIT)
1455 cpu_arch_flags.bitfield.cpu64 = 0;
1456 cpu_arch_flags.bitfield.cpuno64 = 1;
1457 stackop_size = LONG_MNEM_SUFFIX;
1461 set_intel_syntax (int syntax_flag)
1463 /* Find out if register prefixing is specified. */
1464 int ask_naked_reg = 0;
1467 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1469 char *string = input_line_pointer;
1470 int e = get_symbol_end ();
1472 if (strcmp (string, "prefix") == 0)
1474 else if (strcmp (string, "noprefix") == 0)
1477 as_bad (_("bad argument to syntax directive."));
1478 *input_line_pointer = e;
1480 demand_empty_rest_of_line ();
1482 intel_syntax = syntax_flag;
1484 if (ask_naked_reg == 0)
1485 allow_naked_reg = (intel_syntax
1486 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1488 allow_naked_reg = (ask_naked_reg < 0);
1490 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1491 identifier_chars['$'] = intel_syntax ? '$' : 0;
1492 register_prefix = allow_naked_reg ? "" : "%";
1496 set_intel_mnemonic (int mnemonic_flag)
1498 intel_mnemonic = mnemonic_flag;
1502 set_allow_index_reg (int flag)
1504 allow_index_reg = flag;
1508 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1512 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1514 char *string = input_line_pointer;
1515 int e = get_symbol_end ();
1517 i386_cpu_flags flags;
1519 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1521 if (strcmp (string, cpu_arch[i].name) == 0)
1525 cpu_arch_name = cpu_arch[i].name;
1526 cpu_sub_arch_name = NULL;
1527 cpu_arch_flags = cpu_arch[i].flags;
1528 if (flag_code == CODE_64BIT)
1530 cpu_arch_flags.bitfield.cpu64 = 1;
1531 cpu_arch_flags.bitfield.cpuno64 = 0;
1535 cpu_arch_flags.bitfield.cpu64 = 0;
1536 cpu_arch_flags.bitfield.cpuno64 = 1;
1538 cpu_arch_isa = cpu_arch[i].type;
1539 cpu_arch_isa_flags = cpu_arch[i].flags;
1540 if (!cpu_arch_tune_set)
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1548 flags = cpu_flags_or (cpu_arch_flags,
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1552 cpu_sub_arch_name = cpu_arch[i].name;
1553 cpu_arch_flags = flags;
1555 *input_line_pointer = e;
1556 demand_empty_rest_of_line ();
1560 if (i >= ARRAY_SIZE (cpu_arch))
1561 as_bad (_("no such architecture: `%s'"), string);
1563 *input_line_pointer = e;
1566 as_bad (_("missing cpu architecture"));
1568 no_cond_jump_promotion = 0;
1569 if (*input_line_pointer == ','
1570 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1572 char *string = ++input_line_pointer;
1573 int e = get_symbol_end ();
1575 if (strcmp (string, "nojumps") == 0)
1576 no_cond_jump_promotion = 1;
1577 else if (strcmp (string, "jumps") == 0)
1580 as_bad (_("no such architecture modifier: `%s'"), string);
1582 *input_line_pointer = e;
1585 demand_empty_rest_of_line ();
1591 if (!strcmp (default_arch, "x86_64"))
1592 return bfd_mach_x86_64;
1593 else if (!strcmp (default_arch, "i386"))
1594 return bfd_mach_i386_i386;
1596 as_fatal (_("Unknown architecture"));
1602 const char *hash_err;
1604 /* Initialize op_hash hash table. */
1605 op_hash = hash_new ();
1608 const template *optab;
1609 templates *core_optab;
1611 /* Setup for loop. */
1613 core_optab = (templates *) xmalloc (sizeof (templates));
1614 core_optab->start = optab;
1619 if (optab->name == NULL
1620 || strcmp (optab->name, (optab - 1)->name) != 0)
1622 /* different name --> ship out current template list;
1623 add to hash table; & begin anew. */
1624 core_optab->end = optab;
1625 hash_err = hash_insert (op_hash,
1630 as_fatal (_("Internal Error: Can't hash %s: %s"),
1634 if (optab->name == NULL)
1636 core_optab = (templates *) xmalloc (sizeof (templates));
1637 core_optab->start = optab;
1642 /* Initialize reg_hash hash table. */
1643 reg_hash = hash_new ();
1645 const reg_entry *regtab;
1646 unsigned int regtab_size = i386_regtab_size;
1648 for (regtab = i386_regtab; regtab_size--; regtab++)
1650 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1652 as_fatal (_("Internal Error: Can't hash %s: %s"),
1658 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1663 for (c = 0; c < 256; c++)
1668 mnemonic_chars[c] = c;
1669 register_chars[c] = c;
1670 operand_chars[c] = c;
1672 else if (ISLOWER (c))
1674 mnemonic_chars[c] = c;
1675 register_chars[c] = c;
1676 operand_chars[c] = c;
1678 else if (ISUPPER (c))
1680 mnemonic_chars[c] = TOLOWER (c);
1681 register_chars[c] = mnemonic_chars[c];
1682 operand_chars[c] = c;
1685 if (ISALPHA (c) || ISDIGIT (c))
1686 identifier_chars[c] = c;
1689 identifier_chars[c] = c;
1690 operand_chars[c] = c;
1695 identifier_chars['@'] = '@';
1698 identifier_chars['?'] = '?';
1699 operand_chars['?'] = '?';
1701 digit_chars['-'] = '-';
1702 mnemonic_chars['-'] = '-';
1703 mnemonic_chars['.'] = '.';
1704 identifier_chars['_'] = '_';
1705 identifier_chars['.'] = '.';
1707 for (p = operand_special_chars; *p != '\0'; p++)
1708 operand_chars[(unsigned char) *p] = *p;
1711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1714 record_alignment (text_section, 2);
1715 record_alignment (data_section, 2);
1716 record_alignment (bss_section, 2);
1720 if (flag_code == CODE_64BIT)
1722 x86_dwarf2_return_column = 16;
1723 x86_cie_data_alignment = -8;
1727 x86_dwarf2_return_column = 8;
1728 x86_cie_data_alignment = -4;
1733 i386_print_statistics (FILE *file)
1735 hash_print_statistics (file, "i386 opcode", op_hash);
1736 hash_print_statistics (file, "i386 register", reg_hash);
1741 /* Debugging routines for md_assemble. */
1742 static void pte (template *);
1743 static void pt (i386_operand_type);
1744 static void pe (expressionS *);
1745 static void ps (symbolS *);
1748 pi (char *line, i386_insn *x)
1752 fprintf (stdout, "%s: template ", line);
1754 fprintf (stdout, " address: base %s index %s scale %x\n",
1755 x->base_reg ? x->base_reg->reg_name : "none",
1756 x->index_reg ? x->index_reg->reg_name : "none",
1757 x->log2_scale_factor);
1758 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1759 x->rm.mode, x->rm.reg, x->rm.regmem);
1760 fprintf (stdout, " sib: base %x index %x scale %x\n",
1761 x->sib.base, x->sib.index, x->sib.scale);
1762 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1763 (x->rex & REX_W) != 0,
1764 (x->rex & REX_R) != 0,
1765 (x->rex & REX_X) != 0,
1766 (x->rex & REX_B) != 0);
1767 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1768 x->drex.reg, x->drex.rex);
1769 for (i = 0; i < x->operands; i++)
1771 fprintf (stdout, " #%d: ", i + 1);
1773 fprintf (stdout, "\n");
1774 if (x->types[i].bitfield.reg8
1775 || x->types[i].bitfield.reg16
1776 || x->types[i].bitfield.reg32
1777 || x->types[i].bitfield.reg64
1778 || x->types[i].bitfield.regmmx
1779 || x->types[i].bitfield.regxmm
1780 || x->types[i].bitfield.sreg2
1781 || x->types[i].bitfield.sreg3
1782 || x->types[i].bitfield.control
1783 || x->types[i].bitfield.debug
1784 || x->types[i].bitfield.test)
1785 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1786 if (operand_type_check (x->types[i], imm))
1788 if (operand_type_check (x->types[i], disp))
1789 pe (x->op[i].disps);
1797 fprintf (stdout, " %d operands ", t->operands);
1798 fprintf (stdout, "opcode %x ", t->base_opcode);
1799 if (t->extension_opcode != None)
1800 fprintf (stdout, "ext %x ", t->extension_opcode);
1801 if (t->opcode_modifier.d)
1802 fprintf (stdout, "D");
1803 if (t->opcode_modifier.w)
1804 fprintf (stdout, "W");
1805 fprintf (stdout, "\n");
1806 for (i = 0; i < t->operands; i++)
1808 fprintf (stdout, " #%d type ", i + 1);
1809 pt (t->operand_types[i]);
1810 fprintf (stdout, "\n");
1817 fprintf (stdout, " operation %d\n", e->X_op);
1818 fprintf (stdout, " add_number %ld (%lx)\n",
1819 (long) e->X_add_number, (long) e->X_add_number);
1820 if (e->X_add_symbol)
1822 fprintf (stdout, " add_symbol ");
1823 ps (e->X_add_symbol);
1824 fprintf (stdout, "\n");
1828 fprintf (stdout, " op_symbol ");
1829 ps (e->X_op_symbol);
1830 fprintf (stdout, "\n");
1837 fprintf (stdout, "%s type %s%s",
1839 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1840 segment_name (S_GET_SEGMENT (s)));
1843 static struct type_name
1845 i386_operand_type mask;
1848 const type_names[] =
1850 { OPERAND_TYPE_REG8, "r8" },
1851 { OPERAND_TYPE_REG16, "r16" },
1852 { OPERAND_TYPE_REG32, "r32" },
1853 { OPERAND_TYPE_REG64, "r64" },
1854 { OPERAND_TYPE_IMM8, "i8" },
1855 { OPERAND_TYPE_IMM8, "i8s" },
1856 { OPERAND_TYPE_IMM16, "i16" },
1857 { OPERAND_TYPE_IMM32, "i32" },
1858 { OPERAND_TYPE_IMM32S, "i32s" },
1859 { OPERAND_TYPE_IMM64, "i64" },
1860 { OPERAND_TYPE_IMM1, "i1" },
1861 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1862 { OPERAND_TYPE_DISP8, "d8" },
1863 { OPERAND_TYPE_DISP16, "d16" },
1864 { OPERAND_TYPE_DISP32, "d32" },
1865 { OPERAND_TYPE_DISP32S, "d32s" },
1866 { OPERAND_TYPE_DISP64, "d64" },
1867 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1868 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1869 { OPERAND_TYPE_CONTROL, "control reg" },
1870 { OPERAND_TYPE_TEST, "test reg" },
1871 { OPERAND_TYPE_DEBUG, "debug reg" },
1872 { OPERAND_TYPE_FLOATREG, "FReg" },
1873 { OPERAND_TYPE_FLOATACC, "FAcc" },
1874 { OPERAND_TYPE_SREG2, "SReg2" },
1875 { OPERAND_TYPE_SREG3, "SReg3" },
1876 { OPERAND_TYPE_ACC, "Acc" },
1877 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1878 { OPERAND_TYPE_REGMMX, "rMMX" },
1879 { OPERAND_TYPE_REGXMM, "rXMM" },
1880 { OPERAND_TYPE_ESSEG, "es" },
1884 pt (i386_operand_type t)
1887 i386_operand_type a;
1889 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1891 a = operand_type_and (t, type_names[j].mask);
1892 if (!UINTS_ALL_ZERO (a))
1893 fprintf (stdout, "%s, ", type_names[j].name);
1898 #endif /* DEBUG386 */
1900 static bfd_reloc_code_real_type
1901 reloc (unsigned int size,
1904 bfd_reloc_code_real_type other)
1906 if (other != NO_RELOC)
1908 reloc_howto_type *reloc;
1913 case BFD_RELOC_X86_64_GOT32:
1914 return BFD_RELOC_X86_64_GOT64;
1916 case BFD_RELOC_X86_64_PLTOFF64:
1917 return BFD_RELOC_X86_64_PLTOFF64;
1919 case BFD_RELOC_X86_64_GOTPC32:
1920 other = BFD_RELOC_X86_64_GOTPC64;
1922 case BFD_RELOC_X86_64_GOTPCREL:
1923 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 case BFD_RELOC_X86_64_TPOFF32:
1926 other = BFD_RELOC_X86_64_TPOFF64;
1928 case BFD_RELOC_X86_64_DTPOFF32:
1929 other = BFD_RELOC_X86_64_DTPOFF64;
1935 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1936 if (size == 4 && flag_code != CODE_64BIT)
1939 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 as_bad (_("unknown relocation (%u)"), other);
1942 else if (size != bfd_get_reloc_size (reloc))
1943 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1944 bfd_get_reloc_size (reloc),
1946 else if (pcrel && !reloc->pc_relative)
1947 as_bad (_("non-pc-relative relocation for pc-relative field"));
1948 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 || (reloc->complain_on_overflow == complain_overflow_unsigned
1952 as_bad (_("relocated field and relocation type differ in signedness"));
1961 as_bad (_("there are no unsigned pc-relative relocations"));
1964 case 1: return BFD_RELOC_8_PCREL;
1965 case 2: return BFD_RELOC_16_PCREL;
1966 case 4: return BFD_RELOC_32_PCREL;
1967 case 8: return BFD_RELOC_64_PCREL;
1969 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1976 case 4: return BFD_RELOC_X86_64_32S;
1981 case 1: return BFD_RELOC_8;
1982 case 2: return BFD_RELOC_16;
1983 case 4: return BFD_RELOC_32;
1984 case 8: return BFD_RELOC_64;
1986 as_bad (_("cannot do %s %u byte relocation"),
1987 sign > 0 ? "signed" : "unsigned", size);
1991 return BFD_RELOC_NONE;
1994 /* Here we decide which fixups can be adjusted to make them relative to
1995 the beginning of the section instead of the symbol. Basically we need
1996 to make sure that the dynamic relocations are done correctly, so in
1997 some cases we force the original symbol to be used. */
2000 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2006 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 if (use_rela_relocations
2009 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2013 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2014 and changed later by validate_fix. */
2015 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2016 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2019 /* adjust_reloc_syms doesn't know about the GOT. */
2020 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2021 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2022 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2023 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2033 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2040 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2046 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2054 intel_float_operand (const char *mnemonic)
2056 /* Note that the value returned is meaningful only for opcodes with (memory)
2057 operands, hence the code here is free to improperly handle opcodes that
2058 have no operands (for better performance and smaller code). */
2060 if (mnemonic[0] != 'f')
2061 return 0; /* non-math */
2063 switch (mnemonic[1])
2065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2066 the fs segment override prefix not currently handled because no
2067 call path can make opcodes without operands get here */
2069 return 2 /* integer op */;
2071 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2072 return 3; /* fldcw/fldenv */
2075 if (mnemonic[2] != 'o' /* fnop */)
2076 return 3; /* non-waiting control op */
2079 if (mnemonic[2] == 's')
2080 return 3; /* frstor/frstpm */
2083 if (mnemonic[2] == 'a')
2084 return 3; /* fsave */
2085 if (mnemonic[2] == 't')
2087 switch (mnemonic[3])
2089 case 'c': /* fstcw */
2090 case 'd': /* fstdw */
2091 case 'e': /* fstenv */
2092 case 's': /* fsts[gw] */
2098 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2099 return 0; /* fxsave/fxrstor are not really math ops */
2106 /* This is the guts of the machine-dependent assembler. LINE points to a
2107 machine dependent instruction. This function is supposed to emit
2108 the frags/bytes it assembles to. */
2115 char mnemonic[MAX_MNEM_SIZE];
2117 /* Initialize globals. */
2118 memset (&i, '\0', sizeof (i));
2119 for (j = 0; j < MAX_OPERANDS; j++)
2120 i.reloc[j] = NO_RELOC;
2121 memset (disp_expressions, '\0', sizeof (disp_expressions));
2122 memset (im_expressions, '\0', sizeof (im_expressions));
2123 save_stack_p = save_stack;
2125 /* First parse an instruction mnemonic & call i386_operand for the operands.
2126 We assume that the scrubber has arranged it so that line[0] is the valid
2127 start of a (possibly prefixed) mnemonic. */
2129 line = parse_insn (line, mnemonic);
2133 line = parse_operands (line, mnemonic);
2137 /* Now we've parsed the mnemonic into a set of templates, and have the
2138 operands at hand. */
2140 /* All intel opcodes have reversed operands except for "bound" and
2141 "enter". We also don't reverse intersegment "jmp" and "call"
2142 instructions with 2 immediate operands so that the immediate segment
2143 precedes the offset, as it does when in AT&T mode. */
2146 && (strcmp (mnemonic, "bound") != 0)
2147 && (strcmp (mnemonic, "invlpga") != 0)
2148 && !(operand_type_check (i.types[0], imm)
2149 && operand_type_check (i.types[1], imm)))
2152 /* The order of the immediates should be reversed
2153 for 2 immediates extrq and insertq instructions */
2154 if (i.imm_operands == 2
2155 && (strcmp (mnemonic, "extrq") == 0
2156 || strcmp (mnemonic, "insertq") == 0))
2157 swap_2_operands (0, 1);
2162 /* Don't optimize displacement for movabs since it only takes 64bit
2165 && (flag_code != CODE_64BIT
2166 || strcmp (mnemonic, "movabs") != 0))
2169 /* Next, we find a template that matches the given insn,
2170 making sure the overlap of the given operands types is consistent
2171 with the template operand types. */
2173 if (!match_template ())
2178 /* Zap movzx and movsx suffix. The suffix may have been set from
2179 "word ptr" or "byte ptr" on the source operand, but we'll use
2180 the suffix later to choose the destination register. */
2181 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2183 if (i.reg_operands < 2
2185 && (!i.tm.opcode_modifier.no_bsuf
2186 || !i.tm.opcode_modifier.no_wsuf
2187 || !i.tm.opcode_modifier.no_lsuf
2188 || !i.tm.opcode_modifier.no_ssuf
2189 || !i.tm.opcode_modifier.no_ldsuf
2190 || !i.tm.opcode_modifier.no_qsuf))
2191 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2197 if (i.tm.opcode_modifier.fwait)
2198 if (!add_prefix (FWAIT_OPCODE))
2201 /* Check string instruction segment overrides. */
2202 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2204 if (!check_string ())
2208 if (!process_suffix ())
2211 /* Make still unresolved immediate matches conform to size of immediate
2212 given in i.suffix. */
2213 if (!finalize_imm ())
2216 if (i.types[0].bitfield.imm1)
2217 i.imm_operands = 0; /* kludge for shift insns. */
2219 for (j = 0; j < 3; j++)
2220 if (i.types[j].bitfield.inoutportreg
2221 || i.types[j].bitfield.shiftcount
2222 || i.types[j].bitfield.acc
2223 || i.types[j].bitfield.floatacc)
2226 if (i.tm.opcode_modifier.immext)
2230 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2232 /* Streaming SIMD extensions 3 Instructions have the fixed
2233 operands with an opcode suffix which is coded in the same
2234 place as an 8-bit immediate field would be. Here we check
2235 those operands and remove them afterwards. */
2238 for (x = 0; x < i.operands; x++)
2239 if (i.op[x].regs->reg_num != x)
2240 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2242 i.op[x].regs->reg_name,
2248 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2249 opcode suffix which is coded in the same place as an 8-bit
2250 immediate field would be. Here we fake an 8-bit immediate
2251 operand from the opcode suffix stored in tm.extension_opcode.
2252 SSE5 also uses this encoding, for some of its 3 argument
2255 assert (i.imm_operands == 0
2257 || (i.tm.cpu_flags.bitfield.cpusse5
2258 && i.operands <= 3)));
2260 exp = &im_expressions[i.imm_operands++];
2261 i.op[i.operands].imms = exp;
2262 UINTS_CLEAR (i.types[i.operands]);
2263 i.types[i.operands].bitfield.imm8 = 1;
2265 exp->X_op = O_constant;
2266 exp->X_add_number = i.tm.extension_opcode;
2267 i.tm.extension_opcode = None;
2270 /* For insns with operands there are more diddles to do to the opcode. */
2273 if (!process_operands ())
2276 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2278 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2279 as_warn (_("translating to `%sp'"), i.tm.name);
2282 /* Handle conversion of 'int $3' --> special int3 insn. */
2283 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2285 i.tm.base_opcode = INT3_OPCODE;
2289 if ((i.tm.opcode_modifier.jump
2290 || i.tm.opcode_modifier.jumpbyte
2291 || i.tm.opcode_modifier.jumpdword)
2292 && i.op[0].disps->X_op == O_constant)
2294 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2295 the absolute address given by the constant. Since ix86 jumps and
2296 calls are pc relative, we need to generate a reloc. */
2297 i.op[0].disps->X_add_symbol = &abs_symbol;
2298 i.op[0].disps->X_op = O_symbol;
2301 if (i.tm.opcode_modifier.rex64)
2304 /* For 8 bit registers we need an empty rex prefix. Also if the
2305 instruction already has a prefix, we need to convert old
2306 registers to new ones. */
2308 if ((i.types[0].bitfield.reg8
2309 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2310 || (i.types[1].bitfield.reg8
2311 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2312 || ((i.types[0].bitfield.reg8
2313 || i.types[1].bitfield.reg8)
2318 i.rex |= REX_OPCODE;
2319 for (x = 0; x < 2; x++)
2321 /* Look for 8 bit operand that uses old registers. */
2322 if (i.types[x].bitfield.reg8
2323 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2325 /* In case it is "hi" register, give up. */
2326 if (i.op[x].regs->reg_num > 3)
2327 as_bad (_("can't encode register '%s%s' in an "
2328 "instruction requiring REX prefix."),
2329 register_prefix, i.op[x].regs->reg_name);
2331 /* Otherwise it is equivalent to the extended register.
2332 Since the encoding doesn't change this is merely
2333 cosmetic cleanup for debug output. */
2335 i.op[x].regs = i.op[x].regs + 8;
2340 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2342 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2347 else if (i.rex != 0)
2348 add_prefix (REX_OPCODE | i.rex);
2350 /* We are ready to output the insn. */
2355 parse_insn (char *line, char *mnemonic)
2358 char *token_start = l;
2363 /* Non-zero if we found a prefix only acceptable with string insns. */
2364 const char *expecting_string_instruction = NULL;
2369 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2372 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2374 as_bad (_("no such instruction: `%s'"), token_start);
2379 if (!is_space_char (*l)
2380 && *l != END_OF_INSN
2382 || (*l != PREFIX_SEPARATOR
2385 as_bad (_("invalid character %s in mnemonic"),
2386 output_invalid (*l));
2389 if (token_start == l)
2391 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2392 as_bad (_("expecting prefix; got nothing"));
2394 as_bad (_("expecting mnemonic; got nothing"));
2398 /* Look up instruction (or prefix) via hash table. */
2399 current_templates = hash_find (op_hash, mnemonic);
2401 if (*l != END_OF_INSN
2402 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2403 && current_templates
2404 && current_templates->start->opcode_modifier.isprefix)
2406 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2408 as_bad ((flag_code != CODE_64BIT
2409 ? _("`%s' is only supported in 64-bit mode")
2410 : _("`%s' is not supported in 64-bit mode")),
2411 current_templates->start->name);
2414 /* If we are in 16-bit mode, do not allow addr16 or data16.
2415 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2416 if ((current_templates->start->opcode_modifier.size16
2417 || current_templates->start->opcode_modifier.size32)
2418 && flag_code != CODE_64BIT
2419 && (current_templates->start->opcode_modifier.size32
2420 ^ (flag_code == CODE_16BIT)))
2422 as_bad (_("redundant %s prefix"),
2423 current_templates->start->name);
2426 /* Add prefix, checking for repeated prefixes. */
2427 switch (add_prefix (current_templates->start->base_opcode))
2432 expecting_string_instruction = current_templates->start->name;
2435 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2442 if (!current_templates)
2444 /* See if we can get a match by trimming off a suffix. */
2447 case WORD_MNEM_SUFFIX:
2448 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2449 i.suffix = SHORT_MNEM_SUFFIX;
2451 case BYTE_MNEM_SUFFIX:
2452 case QWORD_MNEM_SUFFIX:
2453 i.suffix = mnem_p[-1];
2455 current_templates = hash_find (op_hash, mnemonic);
2457 case SHORT_MNEM_SUFFIX:
2458 case LONG_MNEM_SUFFIX:
2461 i.suffix = mnem_p[-1];
2463 current_templates = hash_find (op_hash, mnemonic);
2471 if (intel_float_operand (mnemonic) == 1)
2472 i.suffix = SHORT_MNEM_SUFFIX;
2474 i.suffix = LONG_MNEM_SUFFIX;
2476 current_templates = hash_find (op_hash, mnemonic);
2480 if (!current_templates)
2482 as_bad (_("no such instruction: `%s'"), token_start);
2487 if (current_templates->start->opcode_modifier.jump
2488 || current_templates->start->opcode_modifier.jumpbyte)
2490 /* Check for a branch hint. We allow ",pt" and ",pn" for
2491 predict taken and predict not taken respectively.
2492 I'm not sure that branch hints actually do anything on loop
2493 and jcxz insns (JumpByte) for current Pentium4 chips. They
2494 may work in the future and it doesn't hurt to accept them
2496 if (l[0] == ',' && l[1] == 'p')
2500 if (!add_prefix (DS_PREFIX_OPCODE))
2504 else if (l[2] == 'n')
2506 if (!add_prefix (CS_PREFIX_OPCODE))
2512 /* Any other comma loses. */
2515 as_bad (_("invalid character %s in mnemonic"),
2516 output_invalid (*l));
2520 /* Check if instruction is supported on specified architecture. */
2522 for (t = current_templates->start; t < current_templates->end; ++t)
2524 supported |= cpu_flags_match (t->cpu_flags);
2529 if (!(supported & 2))
2531 as_bad (flag_code == CODE_64BIT
2532 ? _("`%s' is not supported in 64-bit mode")
2533 : _("`%s' is only supported in 64-bit mode"),
2534 current_templates->start->name);
2537 if (!(supported & 1))
2539 as_bad (_("`%s' is not supported on `%s%s'"),
2540 current_templates->start->name, cpu_arch_name,
2541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2546 if (!cpu_arch_flags.bitfield.cpui386
2547 && (flag_code != CODE_16BIT))
2549 as_warn (_("use .code16 to ensure correct addressing mode"));
2552 /* Check for rep/repne without a string instruction. */
2553 if (expecting_string_instruction)
2555 static templates override;
2557 for (t = current_templates->start; t < current_templates->end; ++t)
2558 if (t->opcode_modifier.isstring)
2560 if (t >= current_templates->end)
2562 as_bad (_("expecting string instruction after `%s'"),
2563 expecting_string_instruction);
2566 for (override.start = t; t < current_templates->end; ++t)
2567 if (!t->opcode_modifier.isstring)
2570 current_templates = &override;
2577 parse_operands (char *l, const char *mnemonic)
2581 /* 1 if operand is pending after ','. */
2582 unsigned int expecting_operand = 0;
2584 /* Non-zero if operand parens not balanced. */
2585 unsigned int paren_not_balanced;
2587 while (*l != END_OF_INSN)
2589 /* Skip optional white space before operand. */
2590 if (is_space_char (*l))
2592 if (!is_operand_char (*l) && *l != END_OF_INSN)
2594 as_bad (_("invalid character %s before operand %d"),
2595 output_invalid (*l),
2599 token_start = l; /* after white space */
2600 paren_not_balanced = 0;
2601 while (paren_not_balanced || *l != ',')
2603 if (*l == END_OF_INSN)
2605 if (paren_not_balanced)
2608 as_bad (_("unbalanced parenthesis in operand %d."),
2611 as_bad (_("unbalanced brackets in operand %d."),
2616 break; /* we are done */
2618 else if (!is_operand_char (*l) && !is_space_char (*l))
2620 as_bad (_("invalid character %s in operand %d"),
2621 output_invalid (*l),
2628 ++paren_not_balanced;
2630 --paren_not_balanced;
2635 ++paren_not_balanced;
2637 --paren_not_balanced;
2641 if (l != token_start)
2642 { /* Yes, we've read in another operand. */
2643 unsigned int operand_ok;
2644 this_operand = i.operands++;
2645 if (i.operands > MAX_OPERANDS)
2647 as_bad (_("spurious operands; (%d operands/instruction max)"),
2651 /* Now parse operand adding info to 'i' as we go along. */
2652 END_STRING_AND_SAVE (l);
2656 i386_intel_operand (token_start,
2657 intel_float_operand (mnemonic));
2659 operand_ok = i386_att_operand (token_start);
2661 RESTORE_END_STRING (l);
2667 if (expecting_operand)
2669 expecting_operand_after_comma:
2670 as_bad (_("expecting operand after ','; got nothing"));
2675 as_bad (_("expecting operand before ','; got nothing"));
2680 /* Now *l must be either ',' or END_OF_INSN. */
2683 if (*++l == END_OF_INSN)
2685 /* Just skip it, if it's \n complain. */
2686 goto expecting_operand_after_comma;
2688 expecting_operand = 1;
2695 swap_2_operands (int xchg1, int xchg2)
2697 union i386_op temp_op;
2698 i386_operand_type temp_type;
2699 enum bfd_reloc_code_real temp_reloc;
2701 temp_type = i.types[xchg2];
2702 i.types[xchg2] = i.types[xchg1];
2703 i.types[xchg1] = temp_type;
2704 temp_op = i.op[xchg2];
2705 i.op[xchg2] = i.op[xchg1];
2706 i.op[xchg1] = temp_op;
2707 temp_reloc = i.reloc[xchg2];
2708 i.reloc[xchg2] = i.reloc[xchg1];
2709 i.reloc[xchg1] = temp_reloc;
2713 swap_operands (void)
2718 swap_2_operands (1, i.operands - 2);
2721 swap_2_operands (0, i.operands - 1);
2727 if (i.mem_operands == 2)
2729 const seg_entry *temp_seg;
2730 temp_seg = i.seg[0];
2731 i.seg[0] = i.seg[1];
2732 i.seg[1] = temp_seg;
2736 /* Try to ensure constant immediates are represented in the smallest
2741 char guess_suffix = 0;
2745 guess_suffix = i.suffix;
2746 else if (i.reg_operands)
2748 /* Figure out a suffix from the last register operand specified.
2749 We can't do this properly yet, ie. excluding InOutPortReg,
2750 but the following works for instructions with immediates.
2751 In any case, we can't set i.suffix yet. */
2752 for (op = i.operands; --op >= 0;)
2753 if (i.types[op].bitfield.reg8)
2755 guess_suffix = BYTE_MNEM_SUFFIX;
2758 else if (i.types[op].bitfield.reg16)
2760 guess_suffix = WORD_MNEM_SUFFIX;
2763 else if (i.types[op].bitfield.reg32)
2765 guess_suffix = LONG_MNEM_SUFFIX;
2768 else if (i.types[op].bitfield.reg64)
2770 guess_suffix = QWORD_MNEM_SUFFIX;
2774 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2775 guess_suffix = WORD_MNEM_SUFFIX;
2777 for (op = i.operands; --op >= 0;)
2778 if (operand_type_check (i.types[op], imm))
2780 switch (i.op[op].imms->X_op)
2783 /* If a suffix is given, this operand may be shortened. */
2784 switch (guess_suffix)
2786 case LONG_MNEM_SUFFIX:
2787 i.types[op].bitfield.imm32 = 1;
2788 i.types[op].bitfield.imm64 = 1;
2790 case WORD_MNEM_SUFFIX:
2791 i.types[op].bitfield.imm16 = 1;
2792 i.types[op].bitfield.imm32 = 1;
2793 i.types[op].bitfield.imm32s = 1;
2794 i.types[op].bitfield.imm64 = 1;
2796 case BYTE_MNEM_SUFFIX:
2797 i.types[op].bitfield.imm8 = 1;
2798 i.types[op].bitfield.imm8s = 1;
2799 i.types[op].bitfield.imm16 = 1;
2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm32s = 1;
2802 i.types[op].bitfield.imm64 = 1;
2806 /* If this operand is at most 16 bits, convert it
2807 to a signed 16 bit number before trying to see
2808 whether it will fit in an even smaller size.
2809 This allows a 16-bit operand such as $0xffe0 to
2810 be recognised as within Imm8S range. */
2811 if ((i.types[op].bitfield.imm16)
2812 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2814 i.op[op].imms->X_add_number =
2815 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2817 if ((i.types[op].bitfield.imm32)
2818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2822 ^ ((offsetT) 1 << 31))
2823 - ((offsetT) 1 << 31));
2826 = operand_type_or (i.types[op],
2827 smallest_imm_type (i.op[op].imms->X_add_number));
2829 /* We must avoid matching of Imm32 templates when 64bit
2830 only immediate is available. */
2831 if (guess_suffix == QWORD_MNEM_SUFFIX)
2832 i.types[op].bitfield.imm32 = 0;
2839 /* Symbols and expressions. */
2841 /* Convert symbolic operand to proper sizes for matching, but don't
2842 prevent matching a set of insns that only supports sizes other
2843 than those matching the insn suffix. */
2845 i386_operand_type mask, allowed;
2849 UINTS_CLEAR (allowed);
2851 for (t = current_templates->start;
2852 t < current_templates->end;
2854 allowed = operand_type_or (allowed,
2855 t->operand_types[op]);
2856 switch (guess_suffix)
2858 case QWORD_MNEM_SUFFIX:
2859 mask.bitfield.imm64 = 1;
2860 mask.bitfield.imm32s = 1;
2862 case LONG_MNEM_SUFFIX:
2863 mask.bitfield.imm32 = 1;
2865 case WORD_MNEM_SUFFIX:
2866 mask.bitfield.imm16 = 1;
2868 case BYTE_MNEM_SUFFIX:
2869 mask.bitfield.imm8 = 1;
2874 allowed = operand_type_and (mask, allowed);
2875 if (!UINTS_ALL_ZERO (allowed))
2876 i.types[op] = operand_type_and (i.types[op], mask);
2883 /* Try to use the smallest displacement type too. */
2885 optimize_disp (void)
2889 for (op = i.operands; --op >= 0;)
2890 if (operand_type_check (i.types[op], disp))
2892 if (i.op[op].disps->X_op == O_constant)
2894 offsetT disp = i.op[op].disps->X_add_number;
2896 if (i.types[op].bitfield.disp16
2897 && (disp & ~(offsetT) 0xffff) == 0)
2899 /* If this operand is at most 16 bits, convert
2900 to a signed 16 bit number and don't use 64bit
2902 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2903 i.types[op].bitfield.disp64 = 0;
2905 if (i.types[op].bitfield.disp32
2906 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2908 /* If this operand is at most 32 bits, convert
2909 to a signed 32 bit number and don't use 64bit
2911 disp &= (((offsetT) 2 << 31) - 1);
2912 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2913 i.types[op].bitfield.disp64 = 0;
2915 if (!disp && i.types[op].bitfield.baseindex)
2917 i.types[op].bitfield.disp8 = 0;
2918 i.types[op].bitfield.disp16 = 0;
2919 i.types[op].bitfield.disp32 = 0;
2920 i.types[op].bitfield.disp32s = 0;
2921 i.types[op].bitfield.disp64 = 0;
2925 else if (flag_code == CODE_64BIT)
2927 if (fits_in_signed_long (disp))
2929 i.types[op].bitfield.disp64 = 0;
2930 i.types[op].bitfield.disp32s = 1;
2932 if (fits_in_unsigned_long (disp))
2933 i.types[op].bitfield.disp32 = 1;
2935 if ((i.types[op].bitfield.disp32
2936 || i.types[op].bitfield.disp32s
2937 || i.types[op].bitfield.disp16)
2938 && fits_in_signed_byte (disp))
2939 i.types[op].bitfield.disp8 = 1;
2941 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2942 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2944 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2945 i.op[op].disps, 0, i.reloc[op]);
2946 i.types[op].bitfield.disp8 = 0;
2947 i.types[op].bitfield.disp16 = 0;
2948 i.types[op].bitfield.disp32 = 0;
2949 i.types[op].bitfield.disp32s = 0;
2950 i.types[op].bitfield.disp64 = 0;
2953 /* We only support 64bit displacement on constants. */
2954 i.types[op].bitfield.disp64 = 0;
2959 match_template (void)
2961 /* Points to template once we've found it. */
2963 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2964 unsigned int found_reverse_match;
2965 i386_opcode_modifier suffix_check;
2966 i386_operand_type operand_types [MAX_OPERANDS];
2967 int addr_prefix_disp;
2969 unsigned int found_cpu_match;
2970 unsigned int check_register;
2972 #if MAX_OPERANDS != 4
2973 # error "MAX_OPERANDS must be 4."
2976 found_reverse_match = 0;
2977 addr_prefix_disp = -1;
2979 memset (&suffix_check, 0, sizeof (suffix_check));
2980 if (i.suffix == BYTE_MNEM_SUFFIX)
2981 suffix_check.no_bsuf = 1;
2982 else if (i.suffix == WORD_MNEM_SUFFIX)
2983 suffix_check.no_wsuf = 1;
2984 else if (i.suffix == SHORT_MNEM_SUFFIX)
2985 suffix_check.no_ssuf = 1;
2986 else if (i.suffix == LONG_MNEM_SUFFIX)
2987 suffix_check.no_lsuf = 1;
2988 else if (i.suffix == QWORD_MNEM_SUFFIX)
2989 suffix_check.no_qsuf = 1;
2990 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2991 suffix_check.no_ldsuf = 1;
2992 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
2993 suffix_check.xmmword = 1;
2995 for (t = current_templates->start; t < current_templates->end; t++)
2997 addr_prefix_disp = -1;
2999 /* Must have right number of operands. */
3000 if (i.operands != t->operands)
3003 /* Check processor support. */
3004 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3005 if (!found_cpu_match)
3008 /* Check old gcc support. */
3009 if (!old_gcc && t->opcode_modifier.oldgcc)
3012 /* Check AT&T mnemonic. */
3013 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3016 /* Check Intel syntax. */
3017 if (intel_syntax && t->opcode_modifier.attsyntax)
3020 /* Check the suffix, except for some instructions in intel mode. */
3021 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3022 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3023 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3024 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3025 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3026 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3027 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3030 /* Check the memory size in Intel mode when it is provided if
3034 && t->opcode_modifier.checksize
3035 && (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
3036 && (!t->opcode_modifier.word || !suffix_check.no_wsuf)
3037 && (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
3038 && (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
3039 && (!t->opcode_modifier.xmmword || !suffix_check.xmmword))
3042 for (j = 0; j < MAX_OPERANDS; j++)
3043 operand_types [j] = t->operand_types [j];
3045 /* In general, don't allow 64-bit operands in 32-bit mode. */
3046 if (i.suffix == QWORD_MNEM_SUFFIX
3047 && flag_code != CODE_64BIT
3049 ? (!t->opcode_modifier.ignoresize
3050 && !intel_float_operand (t->name))
3051 : intel_float_operand (t->name) != 2)
3052 && ((!operand_types[0].bitfield.regmmx
3053 && !operand_types[0].bitfield.regxmm)
3054 || (!operand_types[t->operands > 1].bitfield.regmmx
3055 && !!operand_types[t->operands > 1].bitfield.regxmm))
3056 && (t->base_opcode != 0x0fc7
3057 || t->extension_opcode != 1 /* cmpxchg8b */))
3060 /* Do not verify operands when there are none. */
3064 /* We've found a match; break out of loop. */
3068 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3069 into Disp32/Disp16/Disp32 operand. */
3070 if (i.prefix[ADDR_PREFIX] != 0)
3072 /* There should be only one Disp operand. */
3076 for (j = 0; j < MAX_OPERANDS; j++)
3078 if (operand_types[j].bitfield.disp16)
3080 addr_prefix_disp = j;
3081 operand_types[j].bitfield.disp32 = 1;
3082 operand_types[j].bitfield.disp16 = 0;
3088 for (j = 0; j < MAX_OPERANDS; j++)
3090 if (operand_types[j].bitfield.disp32)
3092 addr_prefix_disp = j;
3093 operand_types[j].bitfield.disp32 = 0;
3094 operand_types[j].bitfield.disp16 = 1;
3100 for (j = 0; j < MAX_OPERANDS; j++)
3102 if (operand_types[j].bitfield.disp64)
3104 addr_prefix_disp = j;
3105 operand_types[j].bitfield.disp64 = 0;
3106 operand_types[j].bitfield.disp32 = 1;
3114 /* We check register size only if size of operands can be
3115 encoded the canonical way. */
3116 check_register = t->opcode_modifier.w;
3117 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3118 switch (t->operands)
3121 if (!operand_type_match (overlap0, i.types[0]))
3125 /* xchg %eax, %eax is a special case. It is an aliase for nop
3126 only in 32bit mode and we can use opcode 0x90. In 64bit
3127 mode, we can't use 0x90 for xchg %eax, %eax since it should
3128 zero-extend %eax to %rax. */
3129 if (flag_code == CODE_64BIT
3130 && t->base_opcode == 0x90
3131 && UINTS_EQUAL (i.types [0], acc32)
3132 && UINTS_EQUAL (i.types [1], acc32))
3136 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3137 if (!operand_type_match (overlap0, i.types[0])
3138 || !operand_type_match (overlap1, i.types[1])
3140 && !operand_type_register_match (overlap0, i.types[0],
3142 overlap1, i.types[1],
3145 /* Check if other direction is valid ... */
3146 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3149 /* Try reversing direction of operands. */
3150 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3151 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3152 if (!operand_type_match (overlap0, i.types[0])
3153 || !operand_type_match (overlap1, i.types[1])
3155 && !operand_type_register_match (overlap0,
3162 /* Does not match either direction. */
3165 /* found_reverse_match holds which of D or FloatDR
3167 if (t->opcode_modifier.d)
3168 found_reverse_match = Opcode_D;
3169 else if (t->opcode_modifier.floatd)
3170 found_reverse_match = Opcode_FloatD;
3172 found_reverse_match = 0;
3173 if (t->opcode_modifier.floatr)
3174 found_reverse_match |= Opcode_FloatR;
3178 /* Found a forward 2 operand match here. */
3179 switch (t->operands)
3182 overlap3 = operand_type_and (i.types[3],
3185 overlap2 = operand_type_and (i.types[2],
3190 switch (t->operands)
3193 if (!operand_type_match (overlap3, i.types[3])
3195 && !operand_type_register_match (overlap2,
3203 /* Here we make use of the fact that there are no
3204 reverse match 3 operand instructions, and all 3
3205 operand instructions only need to be checked for
3206 register consistency between operands 2 and 3. */
3207 if (!operand_type_match (overlap2, i.types[2])
3209 && !operand_type_register_match (overlap1,
3219 /* Found either forward/reverse 2, 3 or 4 operand match here:
3220 slip through to break. */
3222 if (!found_cpu_match)
3224 found_reverse_match = 0;
3227 /* We've found a match; break out of loop. */
3231 if (t == current_templates->end)
3233 /* We found no match. */
3234 as_bad (_("suffix or operands invalid for `%s'"),
3235 current_templates->start->name);
3239 if (!quiet_warnings)
3242 && (i.types[0].bitfield.jumpabsolute
3243 != operand_types[0].bitfield.jumpabsolute))
3245 as_warn (_("indirect %s without `*'"), t->name);
3248 if (t->opcode_modifier.isprefix
3249 && t->opcode_modifier.ignoresize)
3251 /* Warn them that a data or address size prefix doesn't
3252 affect assembly of the next line of code. */
3253 as_warn (_("stand-alone `%s' prefix"), t->name);
3257 /* Copy the template we found. */
3260 if (addr_prefix_disp != -1)
3261 i.tm.operand_types[addr_prefix_disp]
3262 = operand_types[addr_prefix_disp];
3264 if (found_reverse_match)
3266 /* If we found a reverse match we must alter the opcode
3267 direction bit. found_reverse_match holds bits to change
3268 (different for int & float insns). */
3270 i.tm.base_opcode ^= found_reverse_match;
3272 i.tm.operand_types[0] = operand_types[1];
3273 i.tm.operand_types[1] = operand_types[0];
3282 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3283 if (i.tm.operand_types[mem_op].bitfield.esseg)
3285 if (i.seg[0] != NULL && i.seg[0] != &es)
3287 as_bad (_("`%s' operand %d must use `%%es' segment"),
3292 /* There's only ever one segment override allowed per instruction.
3293 This instruction possibly has a legal segment override on the
3294 second operand, so copy the segment to where non-string
3295 instructions store it, allowing common code. */
3296 i.seg[0] = i.seg[1];
3298 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3300 if (i.seg[1] != NULL && i.seg[1] != &es)
3302 as_bad (_("`%s' operand %d must use `%%es' segment"),
3312 process_suffix (void)
3314 /* If matched instruction specifies an explicit instruction mnemonic
3316 if (i.tm.opcode_modifier.size16)
3317 i.suffix = WORD_MNEM_SUFFIX;
3318 else if (i.tm.opcode_modifier.size32)
3319 i.suffix = LONG_MNEM_SUFFIX;
3320 else if (i.tm.opcode_modifier.size64)
3321 i.suffix = QWORD_MNEM_SUFFIX;
3322 else if (i.reg_operands)
3324 /* If there's no instruction mnemonic suffix we try to invent one
3325 based on register operands. */
3328 /* We take i.suffix from the last register operand specified,
3329 Destination register type is more significant than source
3330 register type. crc32 in SSE4.2 prefers source register
3332 if (i.tm.base_opcode == 0xf20f38f1)
3334 if (i.types[0].bitfield.reg16)
3335 i.suffix = WORD_MNEM_SUFFIX;
3336 else if (i.types[0].bitfield.reg32)
3337 i.suffix = LONG_MNEM_SUFFIX;
3338 else if (i.types[0].bitfield.reg64)
3339 i.suffix = QWORD_MNEM_SUFFIX;
3341 else if (i.tm.base_opcode == 0xf20f38f0)
3343 if (i.types[0].bitfield.reg8)
3344 i.suffix = BYTE_MNEM_SUFFIX;
3351 if (i.tm.base_opcode == 0xf20f38f1
3352 || i.tm.base_opcode == 0xf20f38f0)
3354 /* We have to know the operand size for crc32. */
3355 as_bad (_("ambiguous memory operand size for `%s`"),
3360 for (op = i.operands; --op >= 0;)
3361 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3363 if (i.types[op].bitfield.reg8)
3365 i.suffix = BYTE_MNEM_SUFFIX;
3368 else if (i.types[op].bitfield.reg16)
3370 i.suffix = WORD_MNEM_SUFFIX;
3373 else if (i.types[op].bitfield.reg32)
3375 i.suffix = LONG_MNEM_SUFFIX;
3378 else if (i.types[op].bitfield.reg64)
3380 i.suffix = QWORD_MNEM_SUFFIX;
3386 else if (i.suffix == BYTE_MNEM_SUFFIX)
3388 if (!check_byte_reg ())
3391 else if (i.suffix == LONG_MNEM_SUFFIX)
3393 if (!check_long_reg ())
3396 else if (i.suffix == QWORD_MNEM_SUFFIX)
3399 && i.tm.opcode_modifier.ignoresize
3400 && i.tm.opcode_modifier.no_qsuf)
3402 else if (!check_qword_reg ())
3405 else if (i.suffix == WORD_MNEM_SUFFIX)
3407 if (!check_word_reg ())
3410 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3412 /* Skip if the instruction has x suffix. match_template
3413 should check if it is a valid suffix. */
3415 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3416 /* Do nothing if the instruction is going to ignore the prefix. */
3421 else if (i.tm.opcode_modifier.defaultsize
3423 /* exclude fldenv/frstor/fsave/fstenv */
3424 && i.tm.opcode_modifier.no_ssuf)
3426 i.suffix = stackop_size;
3428 else if (intel_syntax
3430 && (i.tm.operand_types[0].bitfield.jumpabsolute
3431 || i.tm.opcode_modifier.jumpbyte
3432 || i.tm.opcode_modifier.jumpintersegment
3433 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3434 && i.tm.extension_opcode <= 3)))
3439 if (!i.tm.opcode_modifier.no_qsuf)
3441 i.suffix = QWORD_MNEM_SUFFIX;
3445 if (!i.tm.opcode_modifier.no_lsuf)
3446 i.suffix = LONG_MNEM_SUFFIX;
3449 if (!i.tm.opcode_modifier.no_wsuf)
3450 i.suffix = WORD_MNEM_SUFFIX;
3459 if (i.tm.opcode_modifier.w)
3461 as_bad (_("no instruction mnemonic suffix given and "
3462 "no register operands; can't size instruction"));
3468 unsigned int suffixes;
3470 suffixes = !i.tm.opcode_modifier.no_bsuf;
3471 if (!i.tm.opcode_modifier.no_wsuf)
3473 if (!i.tm.opcode_modifier.no_lsuf)
3475 if (!i.tm.opcode_modifier.no_ldsuf)
3477 if (!i.tm.opcode_modifier.no_ssuf)
3479 if (!i.tm.opcode_modifier.no_qsuf)
3482 /* There are more than suffix matches. */
3483 if (i.tm.opcode_modifier.w
3484 || ((suffixes & (suffixes - 1))
3485 && !i.tm.opcode_modifier.defaultsize
3486 && !i.tm.opcode_modifier.ignoresize))
3488 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3494 /* Change the opcode based on the operand size given by i.suffix;
3495 We don't need to change things for byte insns. */
3498 && i.suffix != BYTE_MNEM_SUFFIX
3499 && i.suffix != XMMWORD_MNEM_SUFFIX)
3501 /* It's not a byte, select word/dword operation. */
3502 if (i.tm.opcode_modifier.w)
3504 if (i.tm.opcode_modifier.shortform)
3505 i.tm.base_opcode |= 8;
3507 i.tm.base_opcode |= 1;
3510 /* Now select between word & dword operations via the operand
3511 size prefix, except for instructions that will ignore this
3513 if (i.tm.opcode_modifier.addrprefixop0)
3515 /* The address size override prefix changes the size of the
3517 if ((flag_code == CODE_32BIT
3518 && i.op->regs[0].reg_type.bitfield.reg16)
3519 || (flag_code != CODE_32BIT
3520 && i.op->regs[0].reg_type.bitfield.reg32))
3521 if (!add_prefix (ADDR_PREFIX_OPCODE))
3524 else if (i.suffix != QWORD_MNEM_SUFFIX
3525 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3526 && !i.tm.opcode_modifier.ignoresize
3527 && !i.tm.opcode_modifier.floatmf
3528 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3529 || (flag_code == CODE_64BIT
3530 && i.tm.opcode_modifier.jumpbyte)))
3532 unsigned int prefix = DATA_PREFIX_OPCODE;
3534 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3535 prefix = ADDR_PREFIX_OPCODE;
3537 if (!add_prefix (prefix))
3541 /* Set mode64 for an operand. */
3542 if (i.suffix == QWORD_MNEM_SUFFIX
3543 && flag_code == CODE_64BIT
3544 && !i.tm.opcode_modifier.norex64)
3546 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3547 need rex64. cmpxchg8b is also a special case. */
3548 if (! (i.operands == 2
3549 && i.tm.base_opcode == 0x90
3550 && i.tm.extension_opcode == None
3551 && UINTS_EQUAL (i.types [0], acc64)
3552 && UINTS_EQUAL (i.types [1], acc64))
3553 && ! (i.operands == 1
3554 && i.tm.base_opcode == 0xfc7
3555 && i.tm.extension_opcode == 1
3556 && !operand_type_check (i.types [0], reg)
3557 && operand_type_check (i.types [0], anymem)))
3561 /* Size floating point instruction. */
3562 if (i.suffix == LONG_MNEM_SUFFIX)
3563 if (i.tm.opcode_modifier.floatmf)
3564 i.tm.base_opcode ^= 4;
3571 check_byte_reg (void)
3575 for (op = i.operands; --op >= 0;)
3577 /* If this is an eight bit register, it's OK. If it's the 16 or
3578 32 bit version of an eight bit register, we will just use the
3579 low portion, and that's OK too. */
3580 if (i.types[op].bitfield.reg8)
3583 /* Don't generate this warning if not needed. */
3584 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3587 /* crc32 doesn't generate this warning. */
3588 if (i.tm.base_opcode == 0xf20f38f0)
3591 if ((i.types[op].bitfield.reg16
3592 || i.types[op].bitfield.reg32
3593 || i.types[op].bitfield.reg64)
3594 && i.op[op].regs->reg_num < 4)
3596 /* Prohibit these changes in the 64bit mode, since the
3597 lowering is more complicated. */
3598 if (flag_code == CODE_64BIT
3599 && !i.tm.operand_types[op].bitfield.inoutportreg)
3601 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3602 register_prefix, i.op[op].regs->reg_name,
3606 #if REGISTER_WARNINGS
3608 && !i.tm.operand_types[op].bitfield.inoutportreg)
3609 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3611 (i.op[op].regs + (i.types[op].bitfield.reg16
3612 ? REGNAM_AL - REGNAM_AX
3613 : REGNAM_AL - REGNAM_EAX))->reg_name,
3615 i.op[op].regs->reg_name,
3620 /* Any other register is bad. */
3621 if (i.types[op].bitfield.reg16
3622 || i.types[op].bitfield.reg32
3623 || i.types[op].bitfield.reg64
3624 || i.types[op].bitfield.regmmx
3625 || i.types[op].bitfield.regxmm
3626 || i.types[op].bitfield.sreg2
3627 || i.types[op].bitfield.sreg3
3628 || i.types[op].bitfield.control
3629 || i.types[op].bitfield.debug
3630 || i.types[op].bitfield.test
3631 || i.types[op].bitfield.floatreg
3632 || i.types[op].bitfield.floatacc)
3634 as_bad (_("`%s%s' not allowed with `%s%c'"),
3636 i.op[op].regs->reg_name,
3646 check_long_reg (void)
3650 for (op = i.operands; --op >= 0;)
3651 /* Reject eight bit registers, except where the template requires
3652 them. (eg. movzb) */
3653 if (i.types[op].bitfield.reg8
3654 && (i.tm.operand_types[op].bitfield.reg16
3655 || i.tm.operand_types[op].bitfield.reg32
3656 || i.tm.operand_types[op].bitfield.acc))
3658 as_bad (_("`%s%s' not allowed with `%s%c'"),
3660 i.op[op].regs->reg_name,
3665 /* Warn if the e prefix on a general reg is missing. */
3666 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3667 && i.types[op].bitfield.reg16
3668 && (i.tm.operand_types[op].bitfield.reg32
3669 || i.tm.operand_types[op].bitfield.acc))
3671 /* Prohibit these changes in the 64bit mode, since the
3672 lowering is more complicated. */
3673 if (flag_code == CODE_64BIT)
3675 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3676 register_prefix, i.op[op].regs->reg_name,
3680 #if REGISTER_WARNINGS
3682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3684 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3686 i.op[op].regs->reg_name,
3690 /* Warn if the r prefix on a general reg is missing. */
3691 else if (i.types[op].bitfield.reg64
3692 && (i.tm.operand_types[op].bitfield.reg32
3693 || i.tm.operand_types[op].bitfield.acc))
3696 && i.tm.opcode_modifier.toqword
3697 && !i.types[0].bitfield.regxmm)
3699 /* Convert to QWORD. We want REX byte. */
3700 i.suffix = QWORD_MNEM_SUFFIX;
3704 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3705 register_prefix, i.op[op].regs->reg_name,
3714 check_qword_reg (void)
3718 for (op = i.operands; --op >= 0; )
3719 /* Reject eight bit registers, except where the template requires
3720 them. (eg. movzb) */
3721 if (i.types[op].bitfield.reg8
3722 && (i.tm.operand_types[op].bitfield.reg16
3723 || i.tm.operand_types[op].bitfield.reg32
3724 || i.tm.operand_types[op].bitfield.acc))
3726 as_bad (_("`%s%s' not allowed with `%s%c'"),
3728 i.op[op].regs->reg_name,
3733 /* Warn if the e prefix on a general reg is missing. */
3734 else if ((i.types[op].bitfield.reg16
3735 || i.types[op].bitfield.reg32)
3736 && (i.tm.operand_types[op].bitfield.reg32
3737 || i.tm.operand_types[op].bitfield.acc))
3739 /* Prohibit these changes in the 64bit mode, since the
3740 lowering is more complicated. */
3742 && i.tm.opcode_modifier.todword
3743 && !i.types[0].bitfield.regxmm)
3745 /* Convert to DWORD. We don't want REX byte. */
3746 i.suffix = LONG_MNEM_SUFFIX;
3750 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3751 register_prefix, i.op[op].regs->reg_name,
3760 check_word_reg (void)
3763 for (op = i.operands; --op >= 0;)
3764 /* Reject eight bit registers, except where the template requires
3765 them. (eg. movzb) */
3766 if (i.types[op].bitfield.reg8
3767 && (i.tm.operand_types[op].bitfield.reg16
3768 || i.tm.operand_types[op].bitfield.reg32
3769 || i.tm.operand_types[op].bitfield.acc))
3771 as_bad (_("`%s%s' not allowed with `%s%c'"),
3773 i.op[op].regs->reg_name,
3778 /* Warn if the e prefix on a general reg is present. */
3779 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3780 && i.types[op].bitfield.reg32
3781 && (i.tm.operand_types[op].bitfield.reg16
3782 || i.tm.operand_types[op].bitfield.acc))
3784 /* Prohibit these changes in the 64bit mode, since the
3785 lowering is more complicated. */
3786 if (flag_code == CODE_64BIT)
3788 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3789 register_prefix, i.op[op].regs->reg_name,
3794 #if REGISTER_WARNINGS
3795 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3797 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3799 i.op[op].regs->reg_name,
3807 update_imm (unsigned int j)
3809 i386_operand_type overlap;
3811 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3812 if ((overlap.bitfield.imm8
3813 || overlap.bitfield.imm8s
3814 || overlap.bitfield.imm16
3815 || overlap.bitfield.imm32
3816 || overlap.bitfield.imm32s
3817 || overlap.bitfield.imm64)
3818 && !UINTS_EQUAL (overlap, imm8)
3819 && !UINTS_EQUAL (overlap, imm8s)
3820 && !UINTS_EQUAL (overlap, imm16)
3821 && !UINTS_EQUAL (overlap, imm32)
3822 && !UINTS_EQUAL (overlap, imm32s)
3823 && !UINTS_EQUAL (overlap, imm64))
3827 i386_operand_type temp;
3830 if (i.suffix == BYTE_MNEM_SUFFIX)
3832 temp.bitfield.imm8 = overlap.bitfield.imm8;
3833 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3835 else if (i.suffix == WORD_MNEM_SUFFIX)
3836 temp.bitfield.imm16 = overlap.bitfield.imm16;
3837 else if (i.suffix == QWORD_MNEM_SUFFIX)
3839 temp.bitfield.imm64 = overlap.bitfield.imm64;
3840 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3843 temp.bitfield.imm32 = overlap.bitfield.imm32;
3846 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3847 || UINTS_EQUAL (overlap, imm16_32)
3848 || UINTS_EQUAL (overlap, imm16_32s))
3850 UINTS_CLEAR (overlap);
3851 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3852 overlap.bitfield.imm16 = 1;
3854 overlap.bitfield.imm32s = 1;
3856 if (!UINTS_EQUAL (overlap, imm8)
3857 && !UINTS_EQUAL (overlap, imm8s)
3858 && !UINTS_EQUAL (overlap, imm16)
3859 && !UINTS_EQUAL (overlap, imm32)
3860 && !UINTS_EQUAL (overlap, imm32s)
3861 && !UINTS_EQUAL (overlap, imm64))
3863 as_bad (_("no instruction mnemonic suffix given; "
3864 "can't determine immediate size"));
3868 i.types[j] = overlap;
3878 for (j = 0; j < 2; j++)
3879 if (update_imm (j) == 0)
3882 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3883 assert (operand_type_check (i.types[2], imm) == 0);
3891 i.drex.modrm_reg = 0;
3892 i.drex.modrm_regmem = 0;
3894 /* SSE5 4 operand instructions must have the destination the same as
3895 one of the inputs. Figure out the destination register and cache
3896 it away in the drex field, and remember which fields to use for
3898 if (i.tm.opcode_modifier.drex
3899 && i.tm.opcode_modifier.drexv
3902 i.tm.extension_opcode = None;
3904 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3905 if (i.types[0].bitfield.regxmm != 0
3906 && i.types[1].bitfield.regxmm != 0
3907 && i.types[2].bitfield.regxmm != 0
3908 && i.types[3].bitfield.regxmm != 0
3909 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3910 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3912 /* Clear the arguments that are stored in drex. */
3913 UINTS_CLEAR (i.types[0]);
3914 UINTS_CLEAR (i.types[3]);
3915 i.reg_operands -= 2;
3917 /* There are two different ways to encode a 4 operand
3918 instruction with all registers that uses OC1 set to
3919 0 or 1. Favor setting OC1 to 0 since this mimics the
3920 actions of other SSE5 assemblers. Use modrm encoding 2
3921 for register/register. Include the high order bit that
3922 is normally stored in the REX byte in the register
3924 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3925 i.drex.modrm_reg = 2;
3926 i.drex.modrm_regmem = 1;
3927 i.drex.reg = (i.op[3].regs->reg_num
3928 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3931 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3932 else if (i.types[0].bitfield.regxmm != 0
3933 && i.types[1].bitfield.regxmm != 0
3934 && (i.types[2].bitfield.regxmm
3935 || operand_type_check (i.types[2], anymem))
3936 && i.types[3].bitfield.regxmm != 0
3937 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3938 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3940 /* clear the arguments that are stored in drex */
3941 UINTS_CLEAR (i.types[0]);
3942 UINTS_CLEAR (i.types[3]);
3943 i.reg_operands -= 2;
3945 /* Specify the modrm encoding for memory addressing. Include
3946 the high order bit that is normally stored in the REX byte
3947 in the register field. */
3948 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3949 i.drex.modrm_reg = 1;
3950 i.drex.modrm_regmem = 2;
3951 i.drex.reg = (i.op[3].regs->reg_num
3952 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3955 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3956 else if (i.types[0].bitfield.regxmm != 0
3957 && operand_type_check (i.types[1], anymem) != 0
3958 && i.types[2].bitfield.regxmm != 0
3959 && i.types[3].bitfield.regxmm != 0
3960 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3961 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3963 /* Clear the arguments that are stored in drex. */
3964 UINTS_CLEAR (i.types[0]);
3965 UINTS_CLEAR (i.types[3]);
3966 i.reg_operands -= 2;
3968 /* Specify the modrm encoding for memory addressing. Include
3969 the high order bit that is normally stored in the REX byte
3970 in the register field. */
3971 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3972 i.drex.modrm_reg = 2;
3973 i.drex.modrm_regmem = 1;
3974 i.drex.reg = (i.op[3].regs->reg_num
3975 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3978 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3979 else if (i.types[0].bitfield.regxmm != 0
3980 && i.types[1].bitfield.regxmm != 0
3981 && i.types[2].bitfield.regxmm != 0
3982 && i.types[3].bitfield.regxmm != 0
3983 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3984 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3986 /* clear the arguments that are stored in drex */
3987 UINTS_CLEAR (i.types[2]);
3988 UINTS_CLEAR (i.types[3]);
3989 i.reg_operands -= 2;
3991 /* There are two different ways to encode a 4 operand
3992 instruction with all registers that uses OC1 set to
3993 0 or 1. Favor setting OC1 to 0 since this mimics the
3994 actions of other SSE5 assemblers. Use modrm encoding
3995 2 for register/register. Include the high order bit that
3996 is normally stored in the REX byte in the register
3998 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3999 i.drex.modrm_reg = 1;
4000 i.drex.modrm_regmem = 0;
4002 /* Remember the register, including the upper bits */
4003 i.drex.reg = (i.op[3].regs->reg_num
4004 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4007 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4008 else if (i.types[0].bitfield.regxmm != 0
4009 && (i.types[1].bitfield.regxmm
4010 || operand_type_check (i.types[1], anymem))
4011 && i.types[2].bitfield.regxmm != 0
4012 && i.types[3].bitfield.regxmm != 0
4013 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4014 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4016 /* Clear the arguments that are stored in drex. */
4017 UINTS_CLEAR (i.types[2]);
4018 UINTS_CLEAR (i.types[3]);
4019 i.reg_operands -= 2;
4021 /* Specify the modrm encoding and remember the register
4022 including the bits normally stored in the REX byte. */
4023 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4024 i.drex.modrm_reg = 0;
4025 i.drex.modrm_regmem = 1;
4026 i.drex.reg = (i.op[3].regs->reg_num
4027 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4030 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4031 else if (operand_type_check (i.types[0], anymem) != 0
4032 && i.types[1].bitfield.regxmm != 0
4033 && i.types[2].bitfield.regxmm != 0
4034 && i.types[3].bitfield.regxmm != 0
4035 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4036 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4038 /* clear the arguments that are stored in drex */
4039 UINTS_CLEAR (i.types[2]);
4040 UINTS_CLEAR (i.types[3]);
4041 i.reg_operands -= 2;
4043 /* Specify the modrm encoding and remember the register
4044 including the bits normally stored in the REX byte. */
4045 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4046 i.drex.modrm_reg = 1;
4047 i.drex.modrm_regmem = 0;
4048 i.drex.reg = (i.op[3].regs->reg_num
4049 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4053 as_bad (_("Incorrect operands for the '%s' instruction"),
4057 /* SSE5 instructions with the DREX byte where the only memory operand
4058 is in the 2nd argument, and the first and last xmm register must
4059 match, and is encoded in the DREX byte. */
4060 else if (i.tm.opcode_modifier.drex
4061 && !i.tm.opcode_modifier.drexv
4064 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4065 if (i.types[0].bitfield.regxmm != 0
4066 && (i.types[1].bitfield.regxmm
4067 || operand_type_check(i.types[1], anymem))
4068 && i.types[2].bitfield.regxmm != 0
4069 && i.types[3].bitfield.regxmm != 0
4070 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4071 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4073 /* clear the arguments that are stored in drex */
4074 UINTS_CLEAR (i.types[0]);
4075 UINTS_CLEAR (i.types[3]);
4076 i.reg_operands -= 2;
4078 /* Specify the modrm encoding and remember the register
4079 including the high bit normally stored in the REX
4081 i.drex.modrm_reg = 2;
4082 i.drex.modrm_regmem = 1;
4083 i.drex.reg = (i.op[3].regs->reg_num
4084 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4088 as_bad (_("Incorrect operands for the '%s' instruction"),
4092 /* SSE5 3 operand instructions that the result is a register, being
4093 either operand can be a memory operand, using OC0 to note which
4094 one is the memory. */
4095 else if (i.tm.opcode_modifier.drex
4096 && i.tm.opcode_modifier.drexv
4099 i.tm.extension_opcode = None;
4101 /* Case 1: 3 operand insn, src1 = register. */
4102 if (i.types[0].bitfield.regxmm != 0
4103 && i.types[1].bitfield.regxmm != 0
4104 && i.types[2].bitfield.regxmm != 0)
4106 /* Clear the arguments that are stored in drex. */
4107 UINTS_CLEAR (i.types[2]);
4110 /* Specify the modrm encoding and remember the register
4111 including the high bit normally stored in the REX byte. */
4112 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4113 i.drex.modrm_reg = 1;
4114 i.drex.modrm_regmem = 0;
4115 i.drex.reg = (i.op[2].regs->reg_num
4116 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4119 /* Case 2: 3 operand insn, src1 = memory. */
4120 else if (operand_type_check (i.types[0], anymem) != 0
4121 && i.types[1].bitfield.regxmm != 0
4122 && i.types[2].bitfield.regxmm != 0)
4124 /* Clear the arguments that are stored in drex. */
4125 UINTS_CLEAR (i.types[2]);
4128 /* Specify the modrm encoding and remember the register
4129 including the high bit normally stored in the REX
4131 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4132 i.drex.modrm_reg = 1;
4133 i.drex.modrm_regmem = 0;
4134 i.drex.reg = (i.op[2].regs->reg_num
4135 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4138 /* Case 3: 3 operand insn, src2 = memory. */
4139 else if (i.types[0].bitfield.regxmm != 0
4140 && operand_type_check (i.types[1], anymem) != 0
4141 && i.types[2].bitfield.regxmm != 0)
4143 /* Clear the arguments that are stored in drex. */
4144 UINTS_CLEAR (i.types[2]);
4147 /* Specify the modrm encoding and remember the register
4148 including the high bit normally stored in the REX byte. */
4149 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4150 i.drex.modrm_reg = 0;
4151 i.drex.modrm_regmem = 1;
4152 i.drex.reg = (i.op[2].regs->reg_num
4153 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4157 as_bad (_("Incorrect operands for the '%s' instruction"),
4161 /* SSE5 4 operand instructions that are the comparison instructions
4162 where the first operand is the immediate value of the comparison
4164 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4166 /* Case 1: 4 operand insn, src1 = reg/memory. */
4167 if (operand_type_check (i.types[0], imm) != 0
4168 && (i.types[1].bitfield.regxmm
4169 || operand_type_check (i.types[1], anymem))
4170 && i.types[2].bitfield.regxmm != 0
4171 && i.types[3].bitfield.regxmm != 0)
4173 /* clear the arguments that are stored in drex */
4174 UINTS_CLEAR (i.types[3]);
4177 /* Specify the modrm encoding and remember the register
4178 including the high bit normally stored in the REX byte. */
4179 i.drex.modrm_reg = 2;
4180 i.drex.modrm_regmem = 1;
4181 i.drex.reg = (i.op[3].regs->reg_num
4182 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4185 /* Case 2: 3 operand insn with ImmExt that places the
4186 opcode_extension as an immediate argument. This is used for
4187 all of the varients of comparison that supplies the appropriate
4188 value as part of the instruction. */
4189 else if ((i.types[0].bitfield.regxmm
4190 || operand_type_check (i.types[0], anymem))
4191 && i.types[1].bitfield.regxmm != 0
4192 && i.types[2].bitfield.regxmm != 0
4193 && operand_type_check (i.types[3], imm) != 0)
4195 /* clear the arguments that are stored in drex */
4196 UINTS_CLEAR (i.types[2]);
4199 /* Specify the modrm encoding and remember the register
4200 including the high bit normally stored in the REX byte. */
4201 i.drex.modrm_reg = 1;
4202 i.drex.modrm_regmem = 0;
4203 i.drex.reg = (i.op[2].regs->reg_num
4204 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4208 as_bad (_("Incorrect operands for the '%s' instruction"),
4212 else if (i.tm.opcode_modifier.drex
4213 || i.tm.opcode_modifier.drexv
4214 || i.tm.opcode_modifier.drexc)
4215 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4219 process_operands (void)
4221 /* Default segment register this instruction will use for memory
4222 accesses. 0 means unknown. This is only for optimizing out
4223 unnecessary segment overrides. */
4224 const seg_entry *default_seg = 0;
4226 /* Handle all of the DREX munging that SSE5 needs. */
4227 if (i.tm.opcode_modifier.drex
4228 || i.tm.opcode_modifier.drexv
4229 || i.tm.opcode_modifier.drexc)
4232 if (i.tm.opcode_modifier.firstxmm0)
4236 /* The first operand is implicit and must be xmm0. */
4237 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4238 if (i.op[0].regs->reg_num != 0)
4241 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4242 i.tm.name, register_prefix);
4244 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4245 i.tm.name, register_prefix);
4249 for (j = 1; j < i.operands; j++)
4251 i.op[j - 1] = i.op[j];
4252 i.types[j - 1] = i.types[j];
4254 /* We need to adjust fields in i.tm since they are used by
4255 build_modrm_byte. */
4256 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4263 else if (i.tm.opcode_modifier.regkludge)
4265 /* The imul $imm, %reg instruction is converted into
4266 imul $imm, %reg, %reg, and the clr %reg instruction
4267 is converted into xor %reg, %reg. */
4269 unsigned int first_reg_op;
4271 if (operand_type_check (i.types[0], reg))
4275 /* Pretend we saw the extra register operand. */
4276 assert (i.reg_operands == 1
4277 && i.op[first_reg_op + 1].regs == 0);
4278 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4279 i.types[first_reg_op + 1] = i.types[first_reg_op];
4284 if (i.tm.opcode_modifier.shortform)
4286 if (i.types[0].bitfield.sreg2
4287 || i.types[0].bitfield.sreg3)
4289 if (i.tm.base_opcode == POP_SEG_SHORT
4290 && i.op[0].regs->reg_num == 1)
4292 as_bad (_("you can't `pop %%cs'"));
4295 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4296 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4301 /* The register or float register operand is in operand
4305 if (i.types[0].bitfield.floatreg
4306 || operand_type_check (i.types[0], reg))
4310 /* Register goes in low 3 bits of opcode. */
4311 i.tm.base_opcode |= i.op[op].regs->reg_num;
4312 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4314 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4316 /* Warn about some common errors, but press on regardless.
4317 The first case can be generated by gcc (<= 2.8.1). */
4318 if (i.operands == 2)
4320 /* Reversed arguments on faddp, fsubp, etc. */
4321 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4322 register_prefix, i.op[1].regs->reg_name,
4323 register_prefix, i.op[0].regs->reg_name);
4327 /* Extraneous `l' suffix on fp insn. */
4328 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4329 register_prefix, i.op[0].regs->reg_name);
4334 else if (i.tm.opcode_modifier.modrm)
4336 /* The opcode is completed (modulo i.tm.extension_opcode which
4337 must be put into the modrm byte). Now, we make the modrm and
4338 index base bytes based on all the info we've collected. */
4340 default_seg = build_modrm_byte ();
4342 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4346 else if (i.tm.opcode_modifier.isstring)
4348 /* For the string instructions that allow a segment override
4349 on one of their operands, the default segment is ds. */
4353 if (i.tm.base_opcode == 0x8d /* lea */
4356 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4358 /* If a segment was explicitly specified, and the specified segment
4359 is not the default, use an opcode prefix to select it. If we
4360 never figured out what the default segment is, then default_seg
4361 will be zero at this point, and the specified segment prefix will
4363 if ((i.seg[0]) && (i.seg[0] != default_seg))
4365 if (!add_prefix (i.seg[0]->seg_prefix))
4371 static const seg_entry *
4372 build_modrm_byte (void)
4374 const seg_entry *default_seg = 0;
4376 /* SSE5 4 operand instructions are encoded in such a way that one of
4377 the inputs must match the destination register. Process_drex hides
4378 the 3rd argument in the drex field, so that by the time we get
4379 here, it looks to GAS as if this is a 2 operand instruction. */
4380 if ((i.tm.opcode_modifier.drex
4381 || i.tm.opcode_modifier.drexv
4382 || i.tm.opcode_modifier.drexc)
4383 && i.reg_operands == 2)
4385 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4386 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4388 i.rm.reg = reg->reg_num;
4389 i.rm.regmem = regmem->reg_num;
4391 if ((reg->reg_flags & RegRex) != 0)
4393 if ((regmem->reg_flags & RegRex) != 0)
4397 /* i.reg_operands MUST be the number of real register operands;
4398 implicit registers do not count. */
4399 else if (i.reg_operands == 2)
4401 unsigned int source, dest;
4409 /* When there are 3 operands, one of them may be immediate,
4410 which may be the first or the last operand. Otherwise,
4411 the first operand must be shift count register (cl). */
4412 assert (i.imm_operands == 1
4413 || (i.imm_operands == 0
4414 && i.types[0].bitfield.shiftcount));
4415 if (operand_type_check (i.types[0], imm)
4416 || i.types[0].bitfield.shiftcount)
4422 /* When there are 4 operands, the first two must be 8bit
4423 immediate operands. The source operand will be the 3rd
4425 assert (i.imm_operands == 2
4426 && i.types[0].bitfield.imm8
4427 && i.types[1].bitfield.imm8);
4437 /* One of the register operands will be encoded in the i.tm.reg
4438 field, the other in the combined i.tm.mode and i.tm.regmem
4439 fields. If no form of this instruction supports a memory
4440 destination operand, then we assume the source operand may
4441 sometimes be a memory operand and so we need to store the
4442 destination in the i.rm.reg field. */
4443 if (!i.tm.operand_types[dest].bitfield.regmem
4444 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4446 i.rm.reg = i.op[dest].regs->reg_num;
4447 i.rm.regmem = i.op[source].regs->reg_num;
4448 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4450 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4455 i.rm.reg = i.op[source].regs->reg_num;
4456 i.rm.regmem = i.op[dest].regs->reg_num;
4457 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4459 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4462 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4464 if (!i.types[0].bitfield.control
4465 && !i.types[1].bitfield.control)
4467 i.rex &= ~(REX_R | REX_B);
4468 add_prefix (LOCK_PREFIX_OPCODE);
4472 { /* If it's not 2 reg operands... */
4475 unsigned int fake_zero_displacement = 0;
4478 /* This has been precalculated for SSE5 instructions
4479 that have a DREX field earlier in process_drex. */
4480 if (i.tm.opcode_modifier.drex
4481 || i.tm.opcode_modifier.drexv
4482 || i.tm.opcode_modifier.drexc)
4483 op = i.drex.modrm_regmem;
4486 for (op = 0; op < i.operands; op++)
4487 if (operand_type_check (i.types[op], anymem))
4489 assert (op < i.operands);
4494 if (i.base_reg == 0)
4497 if (!i.disp_operands)
4498 fake_zero_displacement = 1;
4499 if (i.index_reg == 0)
4501 /* Operand is just <disp> */
4502 if (flag_code == CODE_64BIT)
4504 /* 64bit mode overwrites the 32bit absolute
4505 addressing by RIP relative addressing and
4506 absolute addressing is encoded by one of the
4507 redundant SIB forms. */
4508 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4509 i.sib.base = NO_BASE_REGISTER;
4510 i.sib.index = NO_INDEX_REGISTER;
4511 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4512 ? disp32s : disp32);
4514 else if ((flag_code == CODE_16BIT)
4515 ^ (i.prefix[ADDR_PREFIX] != 0))
4517 i.rm.regmem = NO_BASE_REGISTER_16;
4518 i.types[op] = disp16;
4522 i.rm.regmem = NO_BASE_REGISTER;
4523 i.types[op] = disp32;
4526 else /* !i.base_reg && i.index_reg */
4528 if (i.index_reg->reg_num == RegEiz
4529 || i.index_reg->reg_num == RegRiz)
4530 i.sib.index = NO_INDEX_REGISTER;
4532 i.sib.index = i.index_reg->reg_num;
4533 i.sib.base = NO_BASE_REGISTER;
4534 i.sib.scale = i.log2_scale_factor;
4535 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4536 i.types[op].bitfield.disp8 = 0;
4537 i.types[op].bitfield.disp16 = 0;
4538 i.types[op].bitfield.disp64 = 0;
4539 if (flag_code != CODE_64BIT)
4541 /* Must be 32 bit */
4542 i.types[op].bitfield.disp32 = 1;
4543 i.types[op].bitfield.disp32s = 0;
4547 i.types[op].bitfield.disp32 = 0;
4548 i.types[op].bitfield.disp32s = 1;
4550 if ((i.index_reg->reg_flags & RegRex) != 0)
4554 /* RIP addressing for 64bit mode. */
4555 else if (i.base_reg->reg_num == RegRip ||
4556 i.base_reg->reg_num == RegEip)
4558 i.rm.regmem = NO_BASE_REGISTER;
4559 i.types[op].bitfield.disp8 = 0;
4560 i.types[op].bitfield.disp16 = 0;
4561 i.types[op].bitfield.disp32 = 0;
4562 i.types[op].bitfield.disp32s = 1;
4563 i.types[op].bitfield.disp64 = 0;
4564 i.flags[op] |= Operand_PCrel;
4565 if (! i.disp_operands)
4566 fake_zero_displacement = 1;
4568 else if (i.base_reg->reg_type.bitfield.reg16)
4570 switch (i.base_reg->reg_num)
4573 if (i.index_reg == 0)
4575 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4576 i.rm.regmem = i.index_reg->reg_num - 6;
4580 if (i.index_reg == 0)
4583 if (operand_type_check (i.types[op], disp) == 0)
4585 /* fake (%bp) into 0(%bp) */
4586 i.types[op].bitfield.disp8 = 1;
4587 fake_zero_displacement = 1;
4590 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4591 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4593 default: /* (%si) -> 4 or (%di) -> 5 */
4594 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4596 i.rm.mode = mode_from_disp_size (i.types[op]);
4598 else /* i.base_reg and 32/64 bit mode */
4600 if (flag_code == CODE_64BIT
4601 && operand_type_check (i.types[op], disp))
4603 i386_operand_type temp;
4605 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4607 if (i.prefix[ADDR_PREFIX] == 0)
4608 i.types[op].bitfield.disp32s = 1;
4610 i.types[op].bitfield.disp32 = 1;
4613 i.rm.regmem = i.base_reg->reg_num;
4614 if ((i.base_reg->reg_flags & RegRex) != 0)
4616 i.sib.base = i.base_reg->reg_num;
4617 /* x86-64 ignores REX prefix bit here to avoid decoder
4619 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4622 if (i.disp_operands == 0)
4624 fake_zero_displacement = 1;
4625 i.types[op].bitfield.disp8 = 1;
4628 else if (i.base_reg->reg_num == ESP_REG_NUM)
4632 i.sib.scale = i.log2_scale_factor;
4633 if (i.index_reg == 0)
4635 /* <disp>(%esp) becomes two byte modrm with no index
4636 register. We've already stored the code for esp
4637 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4638 Any base register besides %esp will not use the
4639 extra modrm byte. */
4640 i.sib.index = NO_INDEX_REGISTER;
4644 if (i.index_reg->reg_num == RegEiz
4645 || i.index_reg->reg_num == RegRiz)
4646 i.sib.index = NO_INDEX_REGISTER;
4648 i.sib.index = i.index_reg->reg_num;
4649 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4650 if ((i.index_reg->reg_flags & RegRex) != 0)
4655 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4656 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4659 i.rm.mode = mode_from_disp_size (i.types[op]);
4662 if (fake_zero_displacement)
4664 /* Fakes a zero displacement assuming that i.types[op]
4665 holds the correct displacement size. */
4668 assert (i.op[op].disps == 0);
4669 exp = &disp_expressions[i.disp_operands++];
4670 i.op[op].disps = exp;
4671 exp->X_op = O_constant;
4672 exp->X_add_number = 0;
4673 exp->X_add_symbol = (symbolS *) 0;
4674 exp->X_op_symbol = (symbolS *) 0;
4678 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4679 (if any) based on i.tm.extension_opcode. Again, we must be
4680 careful to make sure that segment/control/debug/test/MMX
4681 registers are coded into the i.rm.reg field. */
4686 /* This has been precalculated for SSE5 instructions
4687 that have a DREX field earlier in process_drex. */
4688 if (i.tm.opcode_modifier.drex
4689 || i.tm.opcode_modifier.drexv
4690 || i.tm.opcode_modifier.drexc)
4692 op = i.drex.modrm_reg;
4693 i.rm.reg = i.op[op].regs->reg_num;
4694 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4699 for (op = 0; op < i.operands; op++)
4700 if (i.types[op].bitfield.reg8
4701 || i.types[op].bitfield.reg16
4702 || i.types[op].bitfield.reg32
4703 || i.types[op].bitfield.reg64
4704 || i.types[op].bitfield.regmmx
4705 || i.types[op].bitfield.regxmm
4706 || i.types[op].bitfield.sreg2
4707 || i.types[op].bitfield.sreg3
4708 || i.types[op].bitfield.control
4709 || i.types[op].bitfield.debug
4710 || i.types[op].bitfield.test)
4713 assert (op < i.operands);
4715 /* If there is an extension opcode to put here, the
4716 register number must be put into the regmem field. */
4717 if (i.tm.extension_opcode != None)
4719 i.rm.regmem = i.op[op].regs->reg_num;
4720 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4725 i.rm.reg = i.op[op].regs->reg_num;
4726 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4731 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4732 must set it to 3 to indicate this is a register operand
4733 in the regmem field. */
4734 if (!i.mem_operands)
4738 /* Fill in i.rm.reg field with extension opcode (if any). */
4739 if (i.tm.extension_opcode != None
4740 && !(i.tm.opcode_modifier.drex
4741 || i.tm.opcode_modifier.drexv
4742 || i.tm.opcode_modifier.drexc))
4743 i.rm.reg = i.tm.extension_opcode;
4749 output_branch (void)
4754 relax_substateT subtype;
4759 if (flag_code == CODE_16BIT)
4763 if (i.prefix[DATA_PREFIX] != 0)
4769 /* Pentium4 branch hints. */
4770 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4771 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4776 if (i.prefix[REX_PREFIX] != 0)
4782 if (i.prefixes != 0 && !intel_syntax)
4783 as_warn (_("skipping prefixes on this instruction"));
4785 /* It's always a symbol; End frag & setup for relax.
4786 Make sure there is enough room in this frag for the largest
4787 instruction we may generate in md_convert_frag. This is 2
4788 bytes for the opcode and room for the prefix and largest
4790 frag_grow (prefix + 2 + 4);
4791 /* Prefix and 1 opcode byte go in fr_fix. */
4792 p = frag_more (prefix + 1);
4793 if (i.prefix[DATA_PREFIX] != 0)
4794 *p++ = DATA_PREFIX_OPCODE;
4795 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4796 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4797 *p++ = i.prefix[SEG_PREFIX];
4798 if (i.prefix[REX_PREFIX] != 0)
4799 *p++ = i.prefix[REX_PREFIX];
4800 *p = i.tm.base_opcode;
4802 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4803 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4804 else if (cpu_arch_flags.bitfield.cpui386)
4805 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4807 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4810 sym = i.op[0].disps->X_add_symbol;
4811 off = i.op[0].disps->X_add_number;
4813 if (i.op[0].disps->X_op != O_constant
4814 && i.op[0].disps->X_op != O_symbol)
4816 /* Handle complex expressions. */
4817 sym = make_expr_symbol (i.op[0].disps);
4821 /* 1 possible extra opcode + 4 byte displacement go in var part.
4822 Pass reloc in fr_var. */
4823 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4833 if (i.tm.opcode_modifier.jumpbyte)
4835 /* This is a loop or jecxz type instruction. */
4837 if (i.prefix[ADDR_PREFIX] != 0)
4839 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4842 /* Pentium4 branch hints. */
4843 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4844 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4846 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4855 if (flag_code == CODE_16BIT)
4858 if (i.prefix[DATA_PREFIX] != 0)
4860 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4870 if (i.prefix[REX_PREFIX] != 0)
4872 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4876 if (i.prefixes != 0 && !intel_syntax)
4877 as_warn (_("skipping prefixes on this instruction"));
4879 p = frag_more (1 + size);
4880 *p++ = i.tm.base_opcode;
4882 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4883 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4885 /* All jumps handled here are signed, but don't use a signed limit
4886 check for 32 and 16 bit jumps as we want to allow wrap around at
4887 4G and 64k respectively. */
4889 fixP->fx_signed = 1;
4893 output_interseg_jump (void)
4901 if (flag_code == CODE_16BIT)
4905 if (i.prefix[DATA_PREFIX] != 0)
4911 if (i.prefix[REX_PREFIX] != 0)
4921 if (i.prefixes != 0 && !intel_syntax)
4922 as_warn (_("skipping prefixes on this instruction"));
4924 /* 1 opcode; 2 segment; offset */
4925 p = frag_more (prefix + 1 + 2 + size);
4927 if (i.prefix[DATA_PREFIX] != 0)
4928 *p++ = DATA_PREFIX_OPCODE;
4930 if (i.prefix[REX_PREFIX] != 0)
4931 *p++ = i.prefix[REX_PREFIX];
4933 *p++ = i.tm.base_opcode;
4934 if (i.op[1].imms->X_op == O_constant)
4936 offsetT n = i.op[1].imms->X_add_number;
4939 && !fits_in_unsigned_word (n)
4940 && !fits_in_signed_word (n))
4942 as_bad (_("16-bit jump out of range"));
4945 md_number_to_chars (p, n, size);
4948 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4949 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4950 if (i.op[0].imms->X_op != O_constant)
4951 as_bad (_("can't handle non absolute segment in `%s'"),
4953 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4959 fragS *insn_start_frag;
4960 offsetT insn_start_off;
4962 /* Tie dwarf2 debug info to the address at the start of the insn.
4963 We can't do this after the insn has been output as the current
4964 frag may have been closed off. eg. by frag_var. */
4965 dwarf2_emit_insn (0);
4967 insn_start_frag = frag_now;
4968 insn_start_off = frag_now_fix ();
4971 if (i.tm.opcode_modifier.jump)
4973 else if (i.tm.opcode_modifier.jumpbyte
4974 || i.tm.opcode_modifier.jumpdword)
4976 else if (i.tm.opcode_modifier.jumpintersegment)
4977 output_interseg_jump ();
4980 /* Output normal instructions here. */
4984 unsigned int prefix;
4986 switch (i.tm.opcode_length)
4989 if (i.tm.base_opcode & 0xff000000)
4991 prefix = (i.tm.base_opcode >> 24) & 0xff;
4996 if ((i.tm.base_opcode & 0xff0000) != 0)
4998 prefix = (i.tm.base_opcode >> 16) & 0xff;
4999 if (i.tm.cpu_flags.bitfield.cpupadlock)
5002 if (prefix != REPE_PREFIX_OPCODE
5003 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5004 add_prefix (prefix);
5007 add_prefix (prefix);
5016 /* The prefix bytes. */
5017 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5019 FRAG_APPEND_1_CHAR (*q);
5021 /* Now the opcode; be careful about word order here! */
5022 if (i.tm.opcode_length == 1)
5024 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5028 switch (i.tm.opcode_length)
5032 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5042 /* Put out high byte first: can't use md_number_to_chars! */
5043 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5044 *p = i.tm.base_opcode & 0xff;
5046 /* On SSE5, encode the OC1 bit in the DREX field if this
5047 encoding has multiple formats. */
5048 if (i.tm.opcode_modifier.drex
5049 && i.tm.opcode_modifier.drexv
5050 && DREX_OC1 (i.tm.extension_opcode))
5051 *p |= DREX_OC1_MASK;
5054 /* Now the modrm byte and sib byte (if present). */
5055 if (i.tm.opcode_modifier.modrm)
5057 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5060 /* If i.rm.regmem == ESP (4)
5061 && i.rm.mode != (Register mode)
5063 ==> need second modrm byte. */
5064 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5066 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5067 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5069 | i.sib.scale << 6));
5072 /* Write the DREX byte if needed. */
5073 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5076 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5078 /* Encode the OC0 bit if this encoding has multiple
5080 if ((i.tm.opcode_modifier.drex
5081 || i.tm.opcode_modifier.drexv)
5082 && DREX_OC0 (i.tm.extension_opcode))
5083 *p |= DREX_OC0_MASK;
5086 if (i.disp_operands)
5087 output_disp (insn_start_frag, insn_start_off);
5090 output_imm (insn_start_frag, insn_start_off);
5096 pi ("" /*line*/, &i);
5098 #endif /* DEBUG386 */
5101 /* Return the size of the displacement operand N. */
5104 disp_size (unsigned int n)
5107 if (i.types[n].bitfield.disp64)
5109 else if (i.types[n].bitfield.disp8)
5111 else if (i.types[n].bitfield.disp16)
5116 /* Return the size of the immediate operand N. */
5119 imm_size (unsigned int n)
5122 if (i.types[n].bitfield.imm64)
5124 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5126 else if (i.types[n].bitfield.imm16)
5132 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5137 for (n = 0; n < i.operands; n++)
5139 if (operand_type_check (i.types[n], disp))
5141 if (i.op[n].disps->X_op == O_constant)
5143 int size = disp_size (n);
5146 val = offset_in_range (i.op[n].disps->X_add_number,
5148 p = frag_more (size);
5149 md_number_to_chars (p, val, size);
5153 enum bfd_reloc_code_real reloc_type;
5154 int size = disp_size (n);
5155 int sign = i.types[n].bitfield.disp32s;
5156 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5158 /* We can't have 8 bit displacement here. */
5159 assert (!i.types[n].bitfield.disp8);
5161 /* The PC relative address is computed relative
5162 to the instruction boundary, so in case immediate
5163 fields follows, we need to adjust the value. */
5164 if (pcrel && i.imm_operands)
5169 for (n1 = 0; n1 < i.operands; n1++)
5170 if (operand_type_check (i.types[n1], imm))
5172 /* Only one immediate is allowed for PC
5173 relative address. */
5176 i.op[n].disps->X_add_number -= sz;
5178 /* We should find the immediate. */
5182 p = frag_more (size);
5183 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5185 && GOT_symbol == i.op[n].disps->X_add_symbol
5186 && (((reloc_type == BFD_RELOC_32
5187 || reloc_type == BFD_RELOC_X86_64_32S
5188 || (reloc_type == BFD_RELOC_64
5190 && (i.op[n].disps->X_op == O_symbol
5191 || (i.op[n].disps->X_op == O_add
5192 && ((symbol_get_value_expression
5193 (i.op[n].disps->X_op_symbol)->X_op)
5195 || reloc_type == BFD_RELOC_32_PCREL))
5199 if (insn_start_frag == frag_now)
5200 add = (p - frag_now->fr_literal) - insn_start_off;
5205 add = insn_start_frag->fr_fix - insn_start_off;
5206 for (fr = insn_start_frag->fr_next;
5207 fr && fr != frag_now; fr = fr->fr_next)
5209 add += p - frag_now->fr_literal;
5214 reloc_type = BFD_RELOC_386_GOTPC;
5215 i.op[n].imms->X_add_number += add;
5217 else if (reloc_type == BFD_RELOC_64)
5218 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5220 /* Don't do the adjustment for x86-64, as there
5221 the pcrel addressing is relative to the _next_
5222 insn, and that is taken care of in other code. */
5223 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5225 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5226 i.op[n].disps, pcrel, reloc_type);
5233 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5238 for (n = 0; n < i.operands; n++)
5240 if (operand_type_check (i.types[n], imm))
5242 if (i.op[n].imms->X_op == O_constant)
5244 int size = imm_size (n);
5247 val = offset_in_range (i.op[n].imms->X_add_number,
5249 p = frag_more (size);
5250 md_number_to_chars (p, val, size);
5254 /* Not absolute_section.
5255 Need a 32-bit fixup (don't support 8bit
5256 non-absolute imms). Try to support other
5258 enum bfd_reloc_code_real reloc_type;
5259 int size = imm_size (n);
5262 if (i.types[n].bitfield.imm32s
5263 && (i.suffix == QWORD_MNEM_SUFFIX
5264 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5269 p = frag_more (size);
5270 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5272 /* This is tough to explain. We end up with this one if we
5273 * have operands that look like
5274 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5275 * obtain the absolute address of the GOT, and it is strongly
5276 * preferable from a performance point of view to avoid using
5277 * a runtime relocation for this. The actual sequence of
5278 * instructions often look something like:
5283 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5285 * The call and pop essentially return the absolute address
5286 * of the label .L66 and store it in %ebx. The linker itself
5287 * will ultimately change the first operand of the addl so
5288 * that %ebx points to the GOT, but to keep things simple, the
5289 * .o file must have this operand set so that it generates not
5290 * the absolute address of .L66, but the absolute address of
5291 * itself. This allows the linker itself simply treat a GOTPC
5292 * relocation as asking for a pcrel offset to the GOT to be
5293 * added in, and the addend of the relocation is stored in the
5294 * operand field for the instruction itself.
5296 * Our job here is to fix the operand so that it would add
5297 * the correct offset so that %ebx would point to itself. The
5298 * thing that is tricky is that .-.L66 will point to the
5299 * beginning of the instruction, so we need to further modify
5300 * the operand so that it will point to itself. There are
5301 * other cases where you have something like:
5303 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5305 * and here no correction would be required. Internally in
5306 * the assembler we treat operands of this form as not being
5307 * pcrel since the '.' is explicitly mentioned, and I wonder
5308 * whether it would simplify matters to do it this way. Who
5309 * knows. In earlier versions of the PIC patches, the
5310 * pcrel_adjust field was used to store the correction, but
5311 * since the expression is not pcrel, I felt it would be
5312 * confusing to do it this way. */
5314 if ((reloc_type == BFD_RELOC_32
5315 || reloc_type == BFD_RELOC_X86_64_32S
5316 || reloc_type == BFD_RELOC_64)
5318 && GOT_symbol == i.op[n].imms->X_add_symbol
5319 && (i.op[n].imms->X_op == O_symbol
5320 || (i.op[n].imms->X_op == O_add
5321 && ((symbol_get_value_expression
5322 (i.op[n].imms->X_op_symbol)->X_op)
5327 if (insn_start_frag == frag_now)
5328 add = (p - frag_now->fr_literal) - insn_start_off;
5333 add = insn_start_frag->fr_fix - insn_start_off;
5334 for (fr = insn_start_frag->fr_next;
5335 fr && fr != frag_now; fr = fr->fr_next)
5337 add += p - frag_now->fr_literal;
5341 reloc_type = BFD_RELOC_386_GOTPC;
5343 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5345 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5346 i.op[n].imms->X_add_number += add;
5348 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5349 i.op[n].imms, 0, reloc_type);
5355 /* x86_cons_fix_new is called via the expression parsing code when a
5356 reloc is needed. We use this hook to get the correct .got reloc. */
5357 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5358 static int cons_sign = -1;
5361 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5364 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5366 got_reloc = NO_RELOC;
5369 if (exp->X_op == O_secrel)
5371 exp->X_op = O_symbol;
5372 r = BFD_RELOC_32_SECREL;
5376 fix_new_exp (frag, off, len, exp, 0, r);
5379 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5380 # define lex_got(reloc, adjust, types) NULL
5382 /* Parse operands of the form
5383 <symbol>@GOTOFF+<nnn>
5384 and similar .plt or .got references.
5386 If we find one, set up the correct relocation in RELOC and copy the
5387 input string, minus the `@GOTOFF' into a malloc'd buffer for
5388 parsing by the calling routine. Return this buffer, and if ADJUST
5389 is non-null set it to the length of the string we removed from the
5390 input line. Otherwise return NULL. */
5392 lex_got (enum bfd_reloc_code_real *reloc,
5394 i386_operand_type *types)
5396 /* Some of the relocations depend on the size of what field is to
5397 be relocated. But in our callers i386_immediate and i386_displacement
5398 we don't yet know the operand size (this will be set by insn
5399 matching). Hence we record the word32 relocation here,
5400 and adjust the reloc according to the real size in reloc(). */
5401 static const struct {
5403 const enum bfd_reloc_code_real rel[2];
5404 const i386_operand_type types64;
5407 BFD_RELOC_X86_64_PLTOFF64 },
5408 OPERAND_TYPE_IMM64 },
5409 { "PLT", { BFD_RELOC_386_PLT32,
5410 BFD_RELOC_X86_64_PLT32 },
5411 OPERAND_TYPE_IMM32_32S_DISP32 },
5413 BFD_RELOC_X86_64_GOTPLT64 },
5414 OPERAND_TYPE_IMM64_DISP64 },
5415 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5416 BFD_RELOC_X86_64_GOTOFF64 },
5417 OPERAND_TYPE_IMM64_DISP64 },
5419 BFD_RELOC_X86_64_GOTPCREL },
5420 OPERAND_TYPE_IMM32_32S_DISP32 },
5421 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5422 BFD_RELOC_X86_64_TLSGD },
5423 OPERAND_TYPE_IMM32_32S_DISP32 },
5424 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5426 OPERAND_TYPE_NONE },
5428 BFD_RELOC_X86_64_TLSLD },
5429 OPERAND_TYPE_IMM32_32S_DISP32 },
5430 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5431 BFD_RELOC_X86_64_GOTTPOFF },
5432 OPERAND_TYPE_IMM32_32S_DISP32 },
5433 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5434 BFD_RELOC_X86_64_TPOFF32 },
5435 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5436 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5438 OPERAND_TYPE_NONE },
5439 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5440 BFD_RELOC_X86_64_DTPOFF32 },
5442 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5443 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5445 OPERAND_TYPE_NONE },
5446 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5448 OPERAND_TYPE_NONE },
5449 { "GOT", { BFD_RELOC_386_GOT32,
5450 BFD_RELOC_X86_64_GOT32 },
5451 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5452 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5453 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5454 OPERAND_TYPE_IMM32_32S_DISP32 },
5455 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5456 BFD_RELOC_X86_64_TLSDESC_CALL },
5457 OPERAND_TYPE_IMM32_32S_DISP32 },
5465 for (cp = input_line_pointer; *cp != '@'; cp++)
5466 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5469 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5473 len = strlen (gotrel[j].str);
5474 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5476 if (gotrel[j].rel[object_64bit] != 0)
5479 char *tmpbuf, *past_reloc;
5481 *reloc = gotrel[j].rel[object_64bit];
5487 if (flag_code != CODE_64BIT)
5489 types->bitfield.imm32 = 1;
5490 types->bitfield.disp32 = 1;
5493 *types = gotrel[j].types64;
5496 if (GOT_symbol == NULL)
5497 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5499 /* The length of the first part of our input line. */
5500 first = cp - input_line_pointer;
5502 /* The second part goes from after the reloc token until
5503 (and including) an end_of_line char or comma. */
5504 past_reloc = cp + 1 + len;
5506 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5508 second = cp + 1 - past_reloc;
5510 /* Allocate and copy string. The trailing NUL shouldn't
5511 be necessary, but be safe. */
5512 tmpbuf = xmalloc (first + second + 2);
5513 memcpy (tmpbuf, input_line_pointer, first);
5514 if (second != 0 && *past_reloc != ' ')
5515 /* Replace the relocation token with ' ', so that
5516 errors like foo@GOTOFF1 will be detected. */
5517 tmpbuf[first++] = ' ';
5518 memcpy (tmpbuf + first, past_reloc, second);
5519 tmpbuf[first + second] = '\0';
5523 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5524 gotrel[j].str, 1 << (5 + object_64bit));
5529 /* Might be a symbol version string. Don't as_bad here. */
5534 x86_cons (expressionS *exp, int size)
5536 if (size == 4 || (object_64bit && size == 8))
5538 /* Handle @GOTOFF and the like in an expression. */
5540 char *gotfree_input_line;
5543 save = input_line_pointer;
5544 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5545 if (gotfree_input_line)
5546 input_line_pointer = gotfree_input_line;
5550 if (gotfree_input_line)
5552 /* expression () has merrily parsed up to the end of line,
5553 or a comma - in the wrong buffer. Transfer how far
5554 input_line_pointer has moved to the right buffer. */
5555 input_line_pointer = (save
5556 + (input_line_pointer - gotfree_input_line)
5558 free (gotfree_input_line);
5559 if (exp->X_op == O_constant
5560 || exp->X_op == O_absent
5561 || exp->X_op == O_illegal
5562 || exp->X_op == O_register
5563 || exp->X_op == O_big)
5565 char c = *input_line_pointer;
5566 *input_line_pointer = 0;
5567 as_bad (_("missing or invalid expression `%s'"), save);
5568 *input_line_pointer = c;
5577 static void signed_cons (int size)
5579 if (flag_code == CODE_64BIT)
5587 pe_directive_secrel (dummy)
5588 int dummy ATTRIBUTE_UNUSED;
5595 if (exp.X_op == O_symbol)
5596 exp.X_op = O_secrel;
5598 emit_expr (&exp, 4);
5600 while (*input_line_pointer++ == ',');
5602 input_line_pointer--;
5603 demand_empty_rest_of_line ();
5608 i386_immediate (char *imm_start)
5610 char *save_input_line_pointer;
5611 char *gotfree_input_line;
5614 i386_operand_type types;
5616 UINTS_SET (types, ~0);
5618 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5620 as_bad (_("at most %d immediate operands are allowed"),
5621 MAX_IMMEDIATE_OPERANDS);
5625 exp = &im_expressions[i.imm_operands++];
5626 i.op[this_operand].imms = exp;
5628 if (is_space_char (*imm_start))
5631 save_input_line_pointer = input_line_pointer;
5632 input_line_pointer = imm_start;
5634 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5635 if (gotfree_input_line)
5636 input_line_pointer = gotfree_input_line;
5638 exp_seg = expression (exp);
5641 if (*input_line_pointer)
5642 as_bad (_("junk `%s' after expression"), input_line_pointer);
5644 input_line_pointer = save_input_line_pointer;
5645 if (gotfree_input_line)
5646 free (gotfree_input_line);
5648 if (exp->X_op == O_absent
5649 || exp->X_op == O_illegal
5650 || exp->X_op == O_big
5651 || (gotfree_input_line
5652 && (exp->X_op == O_constant
5653 || exp->X_op == O_register)))
5655 as_bad (_("missing or invalid immediate expression `%s'"),
5659 else if (exp->X_op == O_constant)
5661 /* Size it properly later. */
5662 i.types[this_operand].bitfield.imm64 = 1;
5663 /* If BFD64, sign extend val. */
5664 if (!use_rela_relocations
5665 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5667 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5669 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5670 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5671 && exp_seg != absolute_section
5672 && exp_seg != text_section
5673 && exp_seg != data_section
5674 && exp_seg != bss_section
5675 && exp_seg != undefined_section
5676 && !bfd_is_com_section (exp_seg))
5678 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5682 else if (!intel_syntax && exp->X_op == O_register)
5684 as_bad (_("illegal immediate register operand %s"), imm_start);
5689 /* This is an address. The size of the address will be
5690 determined later, depending on destination register,
5691 suffix, or the default for the section. */
5692 i.types[this_operand].bitfield.imm8 = 1;
5693 i.types[this_operand].bitfield.imm16 = 1;
5694 i.types[this_operand].bitfield.imm32 = 1;
5695 i.types[this_operand].bitfield.imm32s = 1;
5696 i.types[this_operand].bitfield.imm64 = 1;
5697 i.types[this_operand] = operand_type_and (i.types[this_operand],
5705 i386_scale (char *scale)
5708 char *save = input_line_pointer;
5710 input_line_pointer = scale;
5711 val = get_absolute_expression ();
5716 i.log2_scale_factor = 0;
5719 i.log2_scale_factor = 1;
5722 i.log2_scale_factor = 2;
5725 i.log2_scale_factor = 3;
5729 char sep = *input_line_pointer;
5731 *input_line_pointer = '\0';
5732 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5734 *input_line_pointer = sep;
5735 input_line_pointer = save;
5739 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5741 as_warn (_("scale factor of %d without an index register"),
5742 1 << i.log2_scale_factor);
5743 i.log2_scale_factor = 0;
5745 scale = input_line_pointer;
5746 input_line_pointer = save;
5751 i386_displacement (char *disp_start, char *disp_end)
5755 char *save_input_line_pointer;
5756 char *gotfree_input_line;
5758 i386_operand_type bigdisp, types = anydisp;
5761 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5763 as_bad (_("at most %d displacement operands are allowed"),
5764 MAX_MEMORY_OPERANDS);
5768 UINTS_CLEAR (bigdisp);
5769 if ((i.types[this_operand].bitfield.jumpabsolute)
5770 || (!current_templates->start->opcode_modifier.jump
5771 && !current_templates->start->opcode_modifier.jumpdword))
5773 bigdisp.bitfield.disp32 = 1;
5774 override = (i.prefix[ADDR_PREFIX] != 0);
5775 if (flag_code == CODE_64BIT)
5779 bigdisp.bitfield.disp32s = 1;
5780 bigdisp.bitfield.disp64 = 1;
5783 else if ((flag_code == CODE_16BIT) ^ override)
5785 bigdisp.bitfield.disp32 = 0;
5786 bigdisp.bitfield.disp16 = 1;
5791 /* For PC-relative branches, the width of the displacement
5792 is dependent upon data size, not address size. */
5793 override = (i.prefix[DATA_PREFIX] != 0);
5794 if (flag_code == CODE_64BIT)
5796 if (override || i.suffix == WORD_MNEM_SUFFIX)
5797 bigdisp.bitfield.disp16 = 1;
5800 bigdisp.bitfield.disp32 = 1;
5801 bigdisp.bitfield.disp32s = 1;
5807 override = (i.suffix == (flag_code != CODE_16BIT
5809 : LONG_MNEM_SUFFIX));
5810 bigdisp.bitfield.disp32 = 1;
5811 if ((flag_code == CODE_16BIT) ^ override)
5813 bigdisp.bitfield.disp32 = 0;
5814 bigdisp.bitfield.disp16 = 1;
5818 i.types[this_operand] = operand_type_or (i.types[this_operand],
5821 exp = &disp_expressions[i.disp_operands];
5822 i.op[this_operand].disps = exp;
5824 save_input_line_pointer = input_line_pointer;
5825 input_line_pointer = disp_start;
5826 END_STRING_AND_SAVE (disp_end);
5828 #ifndef GCC_ASM_O_HACK
5829 #define GCC_ASM_O_HACK 0
5832 END_STRING_AND_SAVE (disp_end + 1);
5833 if (i.types[this_operand].bitfield.baseIndex
5834 && displacement_string_end[-1] == '+')
5836 /* This hack is to avoid a warning when using the "o"
5837 constraint within gcc asm statements.
5840 #define _set_tssldt_desc(n,addr,limit,type) \
5841 __asm__ __volatile__ ( \
5843 "movw %w1,2+%0\n\t" \
5845 "movb %b1,4+%0\n\t" \
5846 "movb %4,5+%0\n\t" \
5847 "movb $0,6+%0\n\t" \
5848 "movb %h1,7+%0\n\t" \
5850 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5852 This works great except that the output assembler ends
5853 up looking a bit weird if it turns out that there is
5854 no offset. You end up producing code that looks like:
5867 So here we provide the missing zero. */
5869 *displacement_string_end = '0';
5872 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5873 if (gotfree_input_line)
5874 input_line_pointer = gotfree_input_line;
5876 exp_seg = expression (exp);
5879 if (*input_line_pointer)
5880 as_bad (_("junk `%s' after expression"), input_line_pointer);
5882 RESTORE_END_STRING (disp_end + 1);
5884 input_line_pointer = save_input_line_pointer;
5885 if (gotfree_input_line)
5886 free (gotfree_input_line);
5889 /* We do this to make sure that the section symbol is in
5890 the symbol table. We will ultimately change the relocation
5891 to be relative to the beginning of the section. */
5892 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5893 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5894 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5896 if (exp->X_op != O_symbol)
5899 if (S_IS_LOCAL (exp->X_add_symbol)
5900 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5901 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5902 exp->X_op = O_subtract;
5903 exp->X_op_symbol = GOT_symbol;
5904 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5905 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5906 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5907 i.reloc[this_operand] = BFD_RELOC_64;
5909 i.reloc[this_operand] = BFD_RELOC_32;
5912 else if (exp->X_op == O_absent
5913 || exp->X_op == O_illegal
5914 || exp->X_op == O_big
5915 || (gotfree_input_line
5916 && (exp->X_op == O_constant
5917 || exp->X_op == O_register)))
5920 as_bad (_("missing or invalid displacement expression `%s'"),
5925 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5926 else if (exp->X_op != O_constant
5927 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5928 && exp_seg != absolute_section
5929 && exp_seg != text_section
5930 && exp_seg != data_section
5931 && exp_seg != bss_section
5932 && exp_seg != undefined_section
5933 && !bfd_is_com_section (exp_seg))
5935 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5940 RESTORE_END_STRING (disp_end);
5942 /* Check if this is a displacement only operand. */
5943 bigdisp = i.types[this_operand];
5944 bigdisp.bitfield.disp8 = 0;
5945 bigdisp.bitfield.disp16 = 0;
5946 bigdisp.bitfield.disp32 = 0;
5947 bigdisp.bitfield.disp32s = 0;
5948 bigdisp.bitfield.disp64 = 0;
5949 if (UINTS_ALL_ZERO (bigdisp))
5950 i.types[this_operand] = operand_type_and (i.types[this_operand],
5956 /* Make sure the memory operand we've been dealt is valid.
5957 Return 1 on success, 0 on a failure. */
5960 i386_index_check (const char *operand_string)
5963 #if INFER_ADDR_PREFIX
5969 if (flag_code == CODE_64BIT)
5972 && ((i.prefix[ADDR_PREFIX] == 0
5973 && !i.base_reg->reg_type.bitfield.reg64)
5974 || (i.prefix[ADDR_PREFIX]
5975 && !i.base_reg->reg_type.bitfield.reg32))
5977 || i.base_reg->reg_num !=
5978 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
5980 && (!i.index_reg->reg_type.bitfield.baseindex
5981 || (i.prefix[ADDR_PREFIX] == 0
5982 && i.index_reg->reg_num != RegRiz
5983 && !i.index_reg->reg_type.bitfield.reg64
5985 || (i.prefix[ADDR_PREFIX]
5986 && i.index_reg->reg_num != RegEiz
5987 && !i.index_reg->reg_type.bitfield.reg32))))
5992 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5996 && (!i.base_reg->reg_type.bitfield.reg16
5997 || !i.base_reg->reg_type.bitfield.baseindex))
5999 && (!i.index_reg->reg_type.bitfield.reg16
6000 || !i.index_reg->reg_type.bitfield.baseindex
6002 && i.base_reg->reg_num < 6
6003 && i.index_reg->reg_num >= 6
6004 && i.log2_scale_factor == 0))))
6011 && !i.base_reg->reg_type.bitfield.reg32)
6013 && ((!i.index_reg->reg_type.bitfield.reg32
6014 && i.index_reg->reg_num != RegEiz)
6015 || !i.index_reg->reg_type.bitfield.baseindex)))
6021 #if INFER_ADDR_PREFIX
6022 if (i.prefix[ADDR_PREFIX] == 0)
6024 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6026 /* Change the size of any displacement too. At most one of
6027 Disp16 or Disp32 is set.
6028 FIXME. There doesn't seem to be any real need for separate
6029 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6030 Removing them would probably clean up the code quite a lot. */
6031 if (flag_code != CODE_64BIT
6032 && (i.types[this_operand].bitfield.disp16
6033 || i.types[this_operand].bitfield.disp32))
6034 i.types[this_operand]
6035 = operand_type_xor (i.types[this_operand], disp16_32);
6040 as_bad (_("`%s' is not a valid base/index expression"),
6044 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6046 flag_code_names[flag_code]);
6051 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6055 i386_att_operand (char *operand_string)
6059 char *op_string = operand_string;
6061 if (is_space_char (*op_string))
6064 /* We check for an absolute prefix (differentiating,
6065 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6066 if (*op_string == ABSOLUTE_PREFIX)
6069 if (is_space_char (*op_string))
6071 i.types[this_operand].bitfield.jumpabsolute = 1;
6074 /* Check if operand is a register. */
6075 if ((r = parse_register (op_string, &end_op)) != NULL)
6077 i386_operand_type temp;
6079 /* Check for a segment override by searching for ':' after a
6080 segment register. */
6082 if (is_space_char (*op_string))
6084 if (*op_string == ':'
6085 && (r->reg_type.bitfield.sreg2
6086 || r->reg_type.bitfield.sreg3))
6091 i.seg[i.mem_operands] = &es;
6094 i.seg[i.mem_operands] = &cs;
6097 i.seg[i.mem_operands] = &ss;
6100 i.seg[i.mem_operands] = &ds;
6103 i.seg[i.mem_operands] = &fs;
6106 i.seg[i.mem_operands] = &gs;
6110 /* Skip the ':' and whitespace. */
6112 if (is_space_char (*op_string))
6115 if (!is_digit_char (*op_string)
6116 && !is_identifier_char (*op_string)
6117 && *op_string != '('
6118 && *op_string != ABSOLUTE_PREFIX)
6120 as_bad (_("bad memory operand `%s'"), op_string);
6123 /* Handle case of %es:*foo. */
6124 if (*op_string == ABSOLUTE_PREFIX)
6127 if (is_space_char (*op_string))
6129 i.types[this_operand].bitfield.jumpabsolute = 1;
6131 goto do_memory_reference;
6135 as_bad (_("junk `%s' after register"), op_string);
6139 temp.bitfield.baseindex = 0;
6140 i.types[this_operand] = operand_type_or (i.types[this_operand],
6142 i.op[this_operand].regs = r;
6145 else if (*op_string == REGISTER_PREFIX)
6147 as_bad (_("bad register name `%s'"), op_string);
6150 else if (*op_string == IMMEDIATE_PREFIX)
6153 if (i.types[this_operand].bitfield.jumpabsolute)
6155 as_bad (_("immediate operand illegal with absolute jump"));
6158 if (!i386_immediate (op_string))
6161 else if (is_digit_char (*op_string)
6162 || is_identifier_char (*op_string)
6163 || *op_string == '(')
6165 /* This is a memory reference of some sort. */
6168 /* Start and end of displacement string expression (if found). */
6169 char *displacement_string_start;
6170 char *displacement_string_end;
6172 do_memory_reference:
6173 if ((i.mem_operands == 1
6174 && !current_templates->start->opcode_modifier.isstring)
6175 || i.mem_operands == 2)
6177 as_bad (_("too many memory references for `%s'"),
6178 current_templates->start->name);
6182 /* Check for base index form. We detect the base index form by
6183 looking for an ')' at the end of the operand, searching
6184 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6186 base_string = op_string + strlen (op_string);
6189 if (is_space_char (*base_string))
6192 /* If we only have a displacement, set-up for it to be parsed later. */
6193 displacement_string_start = op_string;
6194 displacement_string_end = base_string + 1;
6196 if (*base_string == ')')
6199 unsigned int parens_balanced = 1;
6200 /* We've already checked that the number of left & right ()'s are
6201 equal, so this loop will not be infinite. */
6205 if (*base_string == ')')
6207 if (*base_string == '(')
6210 while (parens_balanced);
6212 temp_string = base_string;
6214 /* Skip past '(' and whitespace. */
6216 if (is_space_char (*base_string))
6219 if (*base_string == ','
6220 || ((i.base_reg = parse_register (base_string, &end_op))
6223 displacement_string_end = temp_string;
6225 i.types[this_operand].bitfield.baseindex = 1;
6229 base_string = end_op;
6230 if (is_space_char (*base_string))
6234 /* There may be an index reg or scale factor here. */
6235 if (*base_string == ',')
6238 if (is_space_char (*base_string))
6241 if ((i.index_reg = parse_register (base_string, &end_op))
6244 base_string = end_op;
6245 if (is_space_char (*base_string))
6247 if (*base_string == ',')
6250 if (is_space_char (*base_string))
6253 else if (*base_string != ')')
6255 as_bad (_("expecting `,' or `)' "
6256 "after index register in `%s'"),
6261 else if (*base_string == REGISTER_PREFIX)
6263 as_bad (_("bad register name `%s'"), base_string);
6267 /* Check for scale factor. */
6268 if (*base_string != ')')
6270 char *end_scale = i386_scale (base_string);
6275 base_string = end_scale;
6276 if (is_space_char (*base_string))
6278 if (*base_string != ')')
6280 as_bad (_("expecting `)' "
6281 "after scale factor in `%s'"),
6286 else if (!i.index_reg)
6288 as_bad (_("expecting index register or scale factor "
6289 "after `,'; got '%c'"),
6294 else if (*base_string != ')')
6296 as_bad (_("expecting `,' or `)' "
6297 "after base register in `%s'"),
6302 else if (*base_string == REGISTER_PREFIX)
6304 as_bad (_("bad register name `%s'"), base_string);
6309 /* If there's an expression beginning the operand, parse it,
6310 assuming displacement_string_start and
6311 displacement_string_end are meaningful. */
6312 if (displacement_string_start != displacement_string_end)
6314 if (!i386_displacement (displacement_string_start,
6315 displacement_string_end))
6319 /* Special case for (%dx) while doing input/output op. */
6321 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6323 && i.log2_scale_factor == 0
6324 && i.seg[i.mem_operands] == 0
6325 && !operand_type_check (i.types[this_operand], disp))
6327 UINTS_CLEAR (i.types[this_operand]);
6328 i.types[this_operand].bitfield.inoutportreg = 1;
6332 if (i386_index_check (operand_string) == 0)
6338 /* It's not a memory operand; argh! */
6339 as_bad (_("invalid char %s beginning operand %d `%s'"),
6340 output_invalid (*op_string),
6345 return 1; /* Normal return. */
6348 /* md_estimate_size_before_relax()
6350 Called just before relax() for rs_machine_dependent frags. The x86
6351 assembler uses these frags to handle variable size jump
6354 Any symbol that is now undefined will not become defined.
6355 Return the correct fr_subtype in the frag.
6356 Return the initial "guess for variable size of frag" to caller.
6357 The guess is actually the growth beyond the fixed part. Whatever
6358 we do to grow the fixed or variable part contributes to our
6362 md_estimate_size_before_relax (fragP, segment)
6366 /* We've already got fragP->fr_subtype right; all we have to do is
6367 check for un-relaxable symbols. On an ELF system, we can't relax
6368 an externally visible symbol, because it may be overridden by a
6370 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6373 && (S_IS_EXTERNAL (fragP->fr_symbol)
6374 || S_IS_WEAK (fragP->fr_symbol)))
6378 /* Symbol is undefined in this segment, or we need to keep a
6379 reloc so that weak symbols can be overridden. */
6380 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6381 enum bfd_reloc_code_real reloc_type;
6382 unsigned char *opcode;
6385 if (fragP->fr_var != NO_RELOC)
6386 reloc_type = fragP->fr_var;
6388 reloc_type = BFD_RELOC_16_PCREL;
6390 reloc_type = BFD_RELOC_32_PCREL;
6392 old_fr_fix = fragP->fr_fix;
6393 opcode = (unsigned char *) fragP->fr_opcode;
6395 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6398 /* Make jmp (0xeb) a (d)word displacement jump. */
6400 fragP->fr_fix += size;
6401 fix_new (fragP, old_fr_fix, size,
6403 fragP->fr_offset, 1,
6409 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6411 /* Negate the condition, and branch past an
6412 unconditional jump. */
6415 /* Insert an unconditional jump. */
6417 /* We added two extra opcode bytes, and have a two byte
6419 fragP->fr_fix += 2 + 2;
6420 fix_new (fragP, old_fr_fix + 2, 2,
6422 fragP->fr_offset, 1,
6429 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6434 fixP = fix_new (fragP, old_fr_fix, 1,
6436 fragP->fr_offset, 1,
6438 fixP->fx_signed = 1;
6442 /* This changes the byte-displacement jump 0x7N
6443 to the (d)word-displacement jump 0x0f,0x8N. */
6444 opcode[1] = opcode[0] + 0x10;
6445 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6446 /* We've added an opcode byte. */
6447 fragP->fr_fix += 1 + size;
6448 fix_new (fragP, old_fr_fix + 1, size,
6450 fragP->fr_offset, 1,
6455 BAD_CASE (fragP->fr_subtype);
6459 return fragP->fr_fix - old_fr_fix;
6462 /* Guess size depending on current relax state. Initially the relax
6463 state will correspond to a short jump and we return 1, because
6464 the variable part of the frag (the branch offset) is one byte
6465 long. However, we can relax a section more than once and in that
6466 case we must either set fr_subtype back to the unrelaxed state,
6467 or return the value for the appropriate branch. */
6468 return md_relax_table[fragP->fr_subtype].rlx_length;
6471 /* Called after relax() is finished.
6473 In: Address of frag.
6474 fr_type == rs_machine_dependent.
6475 fr_subtype is what the address relaxed to.
6477 Out: Any fixSs and constants are set up.
6478 Caller will turn frag into a ".space 0". */
6481 md_convert_frag (abfd, sec, fragP)
6482 bfd *abfd ATTRIBUTE_UNUSED;
6483 segT sec ATTRIBUTE_UNUSED;
6486 unsigned char *opcode;
6487 unsigned char *where_to_put_displacement = NULL;
6488 offsetT target_address;
6489 offsetT opcode_address;
6490 unsigned int extension = 0;
6491 offsetT displacement_from_opcode_start;
6493 opcode = (unsigned char *) fragP->fr_opcode;
6495 /* Address we want to reach in file space. */
6496 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6498 /* Address opcode resides at in file space. */
6499 opcode_address = fragP->fr_address + fragP->fr_fix;
6501 /* Displacement from opcode start to fill into instruction. */
6502 displacement_from_opcode_start = target_address - opcode_address;
6504 if ((fragP->fr_subtype & BIG) == 0)
6506 /* Don't have to change opcode. */
6507 extension = 1; /* 1 opcode + 1 displacement */
6508 where_to_put_displacement = &opcode[1];
6512 if (no_cond_jump_promotion
6513 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6514 as_warn_where (fragP->fr_file, fragP->fr_line,
6515 _("long jump required"));
6517 switch (fragP->fr_subtype)
6519 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6520 extension = 4; /* 1 opcode + 4 displacement */
6522 where_to_put_displacement = &opcode[1];
6525 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6526 extension = 2; /* 1 opcode + 2 displacement */
6528 where_to_put_displacement = &opcode[1];
6531 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6532 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6533 extension = 5; /* 2 opcode + 4 displacement */
6534 opcode[1] = opcode[0] + 0x10;
6535 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6536 where_to_put_displacement = &opcode[2];
6539 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6540 extension = 3; /* 2 opcode + 2 displacement */
6541 opcode[1] = opcode[0] + 0x10;
6542 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6543 where_to_put_displacement = &opcode[2];
6546 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6551 where_to_put_displacement = &opcode[3];
6555 BAD_CASE (fragP->fr_subtype);
6560 /* If size if less then four we are sure that the operand fits,
6561 but if it's 4, then it could be that the displacement is larger
6563 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6565 && ((addressT) (displacement_from_opcode_start - extension
6566 + ((addressT) 1 << 31))
6567 > (((addressT) 2 << 31) - 1)))
6569 as_bad_where (fragP->fr_file, fragP->fr_line,
6570 _("jump target out of range"));
6571 /* Make us emit 0. */
6572 displacement_from_opcode_start = extension;
6574 /* Now put displacement after opcode. */
6575 md_number_to_chars ((char *) where_to_put_displacement,
6576 (valueT) (displacement_from_opcode_start - extension),
6577 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6578 fragP->fr_fix += extension;
6581 /* Apply a fixup (fixS) to segment data, once it has been determined
6582 by our caller that we have all the info we need to fix it up.
6584 On the 386, immediates, displacements, and data pointers are all in
6585 the same (little-endian) format, so we don't need to care about which
6589 md_apply_fix (fixP, valP, seg)
6590 /* The fix we're to put in. */
6592 /* Pointer to the value of the bits. */
6594 /* Segment fix is from. */
6595 segT seg ATTRIBUTE_UNUSED;
6597 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6598 valueT value = *valP;
6600 #if !defined (TE_Mach)
6603 switch (fixP->fx_r_type)
6609 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6612 case BFD_RELOC_X86_64_32S:
6613 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6616 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6619 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6624 if (fixP->fx_addsy != NULL
6625 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6626 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6627 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6628 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6629 && !use_rela_relocations)
6631 /* This is a hack. There should be a better way to handle this.
6632 This covers for the fact that bfd_install_relocation will
6633 subtract the current location (for partial_inplace, PC relative
6634 relocations); see more below. */
6638 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6641 value += fixP->fx_where + fixP->fx_frag->fr_address;
6643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6646 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6649 || (symbol_section_p (fixP->fx_addsy)
6650 && sym_seg != absolute_section))
6651 && !generic_force_reloc (fixP))
6653 /* Yes, we add the values in twice. This is because
6654 bfd_install_relocation subtracts them out again. I think
6655 bfd_install_relocation is broken, but I don't dare change
6657 value += fixP->fx_where + fixP->fx_frag->fr_address;
6661 #if defined (OBJ_COFF) && defined (TE_PE)
6662 /* For some reason, the PE format does not store a
6663 section address offset for a PC relative symbol. */
6664 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6665 || S_IS_WEAK (fixP->fx_addsy))
6666 value += md_pcrel_from (fixP);
6670 /* Fix a few things - the dynamic linker expects certain values here,
6671 and we must not disappoint it. */
6672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6673 if (IS_ELF && fixP->fx_addsy)
6674 switch (fixP->fx_r_type)
6676 case BFD_RELOC_386_PLT32:
6677 case BFD_RELOC_X86_64_PLT32:
6678 /* Make the jump instruction point to the address of the operand. At
6679 runtime we merely add the offset to the actual PLT entry. */
6683 case BFD_RELOC_386_TLS_GD:
6684 case BFD_RELOC_386_TLS_LDM:
6685 case BFD_RELOC_386_TLS_IE_32:
6686 case BFD_RELOC_386_TLS_IE:
6687 case BFD_RELOC_386_TLS_GOTIE:
6688 case BFD_RELOC_386_TLS_GOTDESC:
6689 case BFD_RELOC_X86_64_TLSGD:
6690 case BFD_RELOC_X86_64_TLSLD:
6691 case BFD_RELOC_X86_64_GOTTPOFF:
6692 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6693 value = 0; /* Fully resolved at runtime. No addend. */
6695 case BFD_RELOC_386_TLS_LE:
6696 case BFD_RELOC_386_TLS_LDO_32:
6697 case BFD_RELOC_386_TLS_LE_32:
6698 case BFD_RELOC_X86_64_DTPOFF32:
6699 case BFD_RELOC_X86_64_DTPOFF64:
6700 case BFD_RELOC_X86_64_TPOFF32:
6701 case BFD_RELOC_X86_64_TPOFF64:
6702 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6705 case BFD_RELOC_386_TLS_DESC_CALL:
6706 case BFD_RELOC_X86_64_TLSDESC_CALL:
6707 value = 0; /* Fully resolved at runtime. No addend. */
6708 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6712 case BFD_RELOC_386_GOT32:
6713 case BFD_RELOC_X86_64_GOT32:
6714 value = 0; /* Fully resolved at runtime. No addend. */
6717 case BFD_RELOC_VTABLE_INHERIT:
6718 case BFD_RELOC_VTABLE_ENTRY:
6725 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6727 #endif /* !defined (TE_Mach) */
6729 /* Are we finished with this relocation now? */
6730 if (fixP->fx_addsy == NULL)
6732 else if (use_rela_relocations)
6734 fixP->fx_no_overflow = 1;
6735 /* Remember value for tc_gen_reloc. */
6736 fixP->fx_addnumber = value;
6740 md_number_to_chars (p, value, fixP->fx_size);
6744 md_atof (int type, char *litP, int *sizeP)
6746 /* This outputs the LITTLENUMs in REVERSE order;
6747 in accord with the bigendian 386. */
6748 return ieee_md_atof (type, litP, sizeP, FALSE);
6751 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6754 output_invalid (int c)
6757 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6760 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6761 "(0x%x)", (unsigned char) c);
6762 return output_invalid_buf;
6765 /* REG_STRING starts *before* REGISTER_PREFIX. */
6767 static const reg_entry *
6768 parse_real_register (char *reg_string, char **end_op)
6770 char *s = reg_string;
6772 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6775 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6776 if (*s == REGISTER_PREFIX)
6779 if (is_space_char (*s))
6783 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6785 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6786 return (const reg_entry *) NULL;
6790 /* For naked regs, make sure that we are not dealing with an identifier.
6791 This prevents confusing an identifier like `eax_var' with register
6793 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6794 return (const reg_entry *) NULL;
6798 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6800 /* Handle floating point regs, allowing spaces in the (i) part. */
6801 if (r == i386_regtab /* %st is first entry of table */)
6803 if (is_space_char (*s))
6808 if (is_space_char (*s))
6810 if (*s >= '0' && *s <= '7')
6814 if (is_space_char (*s))
6819 r = hash_find (reg_hash, "st(0)");
6824 /* We have "%st(" then garbage. */
6825 return (const reg_entry *) NULL;
6829 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6832 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6833 return (const reg_entry *) NULL;
6836 && ((r->reg_flags & (RegRex64 | RegRex))
6837 || r->reg_type.bitfield.reg64)
6838 && (!cpu_arch_flags.bitfield.cpulm
6839 || !UINTS_EQUAL (r->reg_type, control))
6840 && flag_code != CODE_64BIT)
6841 return (const reg_entry *) NULL;
6846 /* REG_STRING starts *before* REGISTER_PREFIX. */
6848 static const reg_entry *
6849 parse_register (char *reg_string, char **end_op)
6853 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6854 r = parse_real_register (reg_string, end_op);
6859 char *save = input_line_pointer;
6863 input_line_pointer = reg_string;
6864 c = get_symbol_end ();
6865 symbolP = symbol_find (reg_string);
6866 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6868 const expressionS *e = symbol_get_value_expression (symbolP);
6870 know (e->X_op == O_register);
6871 know (e->X_add_number >= 0
6872 && (valueT) e->X_add_number < i386_regtab_size);
6873 r = i386_regtab + e->X_add_number;
6874 *end_op = input_line_pointer;
6876 *input_line_pointer = c;
6877 input_line_pointer = save;
6883 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6886 char *end = input_line_pointer;
6889 r = parse_register (name, &input_line_pointer);
6890 if (r && end <= input_line_pointer)
6892 *nextcharP = *input_line_pointer;
6893 *input_line_pointer = 0;
6894 e->X_op = O_register;
6895 e->X_add_number = r - i386_regtab;
6898 input_line_pointer = end;
6904 md_operand (expressionS *e)
6906 if (*input_line_pointer == REGISTER_PREFIX)
6909 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6913 e->X_op = O_register;
6914 e->X_add_number = r - i386_regtab;
6915 input_line_pointer = end;
6921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6922 const char *md_shortopts = "kVQ:sqn";
6924 const char *md_shortopts = "qn";
6927 #define OPTION_32 (OPTION_MD_BASE + 0)
6928 #define OPTION_64 (OPTION_MD_BASE + 1)
6929 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6930 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6931 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6932 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6933 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6934 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6935 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6936 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6938 struct option md_longopts[] =
6940 {"32", no_argument, NULL, OPTION_32},
6941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6942 {"64", no_argument, NULL, OPTION_64},
6944 {"divide", no_argument, NULL, OPTION_DIVIDE},
6945 {"march", required_argument, NULL, OPTION_MARCH},
6946 {"mtune", required_argument, NULL, OPTION_MTUNE},
6947 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6948 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6949 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6950 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6951 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
6952 {NULL, no_argument, NULL, 0}
6954 size_t md_longopts_size = sizeof (md_longopts);
6957 md_parse_option (int c, char *arg)
6964 optimize_align_code = 0;
6971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6972 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6973 should be emitted or not. FIXME: Not implemented. */
6977 /* -V: SVR4 argument to print version ID. */
6979 print_version_id ();
6982 /* -k: Ignore for FreeBSD compatibility. */
6987 /* -s: On i386 Solaris, this tells the native assembler to use
6988 .stab instead of .stab.excl. We always use .stab anyhow. */
6991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6994 const char **list, **l;
6996 list = bfd_target_list ();
6997 for (l = list; *l != NULL; l++)
6998 if (CONST_STRNEQ (*l, "elf64-x86-64")
6999 || strcmp (*l, "coff-x86-64") == 0
7000 || strcmp (*l, "pe-x86-64") == 0
7001 || strcmp (*l, "pei-x86-64") == 0)
7003 default_arch = "x86_64";
7007 as_fatal (_("No compiled in support for x86_64"));
7014 default_arch = "i386";
7018 #ifdef SVR4_COMMENT_CHARS
7023 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7025 for (s = i386_comment_chars; *s != '\0'; s++)
7029 i386_comment_chars = n;
7036 as_fatal (_("Invalid -march= option: `%s'"), arg);
7037 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7039 if (strcmp (arg, cpu_arch [i].name) == 0)
7041 cpu_arch_isa = cpu_arch[i].type;
7042 cpu_arch_isa_flags = cpu_arch[i].flags;
7043 if (!cpu_arch_tune_set)
7045 cpu_arch_tune = cpu_arch_isa;
7046 cpu_arch_tune_flags = cpu_arch_isa_flags;
7051 if (i >= ARRAY_SIZE (cpu_arch))
7052 as_fatal (_("Invalid -march= option: `%s'"), arg);
7057 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7058 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7060 if (strcmp (arg, cpu_arch [i].name) == 0)
7062 cpu_arch_tune_set = 1;
7063 cpu_arch_tune = cpu_arch [i].type;
7064 cpu_arch_tune_flags = cpu_arch[i].flags;
7068 if (i >= ARRAY_SIZE (cpu_arch))
7069 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7072 case OPTION_MMNEMONIC:
7073 if (strcasecmp (arg, "att") == 0)
7075 else if (strcasecmp (arg, "intel") == 0)
7078 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7081 case OPTION_MSYNTAX:
7082 if (strcasecmp (arg, "att") == 0)
7084 else if (strcasecmp (arg, "intel") == 0)
7087 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7090 case OPTION_MINDEX_REG:
7091 allow_index_reg = 1;
7094 case OPTION_MNAKED_REG:
7095 allow_naked_reg = 1;
7098 case OPTION_MOLD_GCC:
7109 md_show_usage (stream)
7112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7113 fprintf (stream, _("\
7115 -V print assembler version number\n\
7118 fprintf (stream, _("\
7119 -n Do not optimize code alignment\n\
7120 -q quieten some warnings\n"));
7121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7122 fprintf (stream, _("\
7125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7126 fprintf (stream, _("\
7127 --32/--64 generate 32bit/64bit code\n"));
7129 #ifdef SVR4_COMMENT_CHARS
7130 fprintf (stream, _("\
7131 --divide do not treat `/' as a comment character\n"));
7133 fprintf (stream, _("\
7134 --divide ignored\n"));
7136 fprintf (stream, _("\
7137 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7138 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7139 core, core2, k6, athlon, k8, generic32, generic64\n"));
7140 fprintf (stream, _("\
7141 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7142 fprintf (stream, _("\
7143 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7144 fprintf (stream, _("\
7145 -mindex-reg support pseudo index registers\n"));
7146 fprintf (stream, _("\
7147 -mnaked-reg don't require `%%' prefix for registers\n"));
7148 fprintf (stream, _("\
7149 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7152 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7153 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7155 /* Pick the target format to use. */
7158 i386_target_format (void)
7160 if (!strcmp (default_arch, "x86_64"))
7162 set_code_flag (CODE_64BIT);
7163 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7165 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7166 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7167 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7168 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7169 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7170 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7171 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7172 cpu_arch_isa_flags.bitfield.cpummx= 1;
7173 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7174 cpu_arch_isa_flags.bitfield.cpusse = 1;
7175 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7177 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7179 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7180 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7181 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7182 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7183 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7184 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7185 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7186 cpu_arch_tune_flags.bitfield.cpummx= 1;
7187 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7188 cpu_arch_tune_flags.bitfield.cpusse = 1;
7189 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7192 else if (!strcmp (default_arch, "i386"))
7194 set_code_flag (CODE_32BIT);
7195 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7197 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7198 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7199 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7201 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7203 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7204 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7205 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7209 as_fatal (_("Unknown architecture"));
7210 switch (OUTPUT_FLAVOR)
7213 case bfd_target_coff_flavour:
7214 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7217 #ifdef OBJ_MAYBE_AOUT
7218 case bfd_target_aout_flavour:
7219 return AOUT_TARGET_FORMAT;
7221 #ifdef OBJ_MAYBE_COFF
7222 case bfd_target_coff_flavour:
7225 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7226 case bfd_target_elf_flavour:
7228 if (flag_code == CODE_64BIT)
7231 use_rela_relocations = 1;
7233 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7242 #endif /* OBJ_MAYBE_ more than one */
7244 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7246 i386_elf_emit_arch_note (void)
7248 if (IS_ELF && cpu_arch_name != NULL)
7251 asection *seg = now_seg;
7252 subsegT subseg = now_subseg;
7253 Elf_Internal_Note i_note;
7254 Elf_External_Note e_note;
7255 asection *note_secp;
7258 /* Create the .note section. */
7259 note_secp = subseg_new (".note", 0);
7260 bfd_set_section_flags (stdoutput,
7262 SEC_HAS_CONTENTS | SEC_READONLY);
7264 /* Process the arch string. */
7265 len = strlen (cpu_arch_name);
7267 i_note.namesz = len + 1;
7269 i_note.type = NT_ARCH;
7270 p = frag_more (sizeof (e_note.namesz));
7271 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7272 p = frag_more (sizeof (e_note.descsz));
7273 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7274 p = frag_more (sizeof (e_note.type));
7275 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7276 p = frag_more (len + 1);
7277 strcpy (p, cpu_arch_name);
7279 frag_align (2, 0, 0);
7281 subseg_set (seg, subseg);
7287 md_undefined_symbol (name)
7290 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7291 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7292 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7293 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7297 if (symbol_find (name))
7298 as_bad (_("GOT already in symbol table"));
7299 GOT_symbol = symbol_new (name, undefined_section,
7300 (valueT) 0, &zero_address_frag);
7307 /* Round up a section size to the appropriate boundary. */
7310 md_section_align (segment, size)
7311 segT segment ATTRIBUTE_UNUSED;
7314 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7315 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7317 /* For a.out, force the section size to be aligned. If we don't do
7318 this, BFD will align it for us, but it will not write out the
7319 final bytes of the section. This may be a bug in BFD, but it is
7320 easier to fix it here since that is how the other a.out targets
7324 align = bfd_get_section_alignment (stdoutput, segment);
7325 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7332 /* On the i386, PC-relative offsets are relative to the start of the
7333 next instruction. That is, the address of the offset, plus its
7334 size, since the offset is always the last part of the insn. */
7337 md_pcrel_from (fixS *fixP)
7339 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7345 s_bss (int ignore ATTRIBUTE_UNUSED)
7349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7351 obj_elf_section_change_hook ();
7353 temp = get_absolute_expression ();
7354 subseg_set (bss_section, (subsegT) temp);
7355 demand_empty_rest_of_line ();
7361 i386_validate_fix (fixS *fixp)
7363 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7365 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7369 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7374 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7376 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7383 tc_gen_reloc (section, fixp)
7384 asection *section ATTRIBUTE_UNUSED;
7388 bfd_reloc_code_real_type code;
7390 switch (fixp->fx_r_type)
7392 case BFD_RELOC_X86_64_PLT32:
7393 case BFD_RELOC_X86_64_GOT32:
7394 case BFD_RELOC_X86_64_GOTPCREL:
7395 case BFD_RELOC_386_PLT32:
7396 case BFD_RELOC_386_GOT32:
7397 case BFD_RELOC_386_GOTOFF:
7398 case BFD_RELOC_386_GOTPC:
7399 case BFD_RELOC_386_TLS_GD:
7400 case BFD_RELOC_386_TLS_LDM:
7401 case BFD_RELOC_386_TLS_LDO_32:
7402 case BFD_RELOC_386_TLS_IE_32:
7403 case BFD_RELOC_386_TLS_IE:
7404 case BFD_RELOC_386_TLS_GOTIE:
7405 case BFD_RELOC_386_TLS_LE_32:
7406 case BFD_RELOC_386_TLS_LE:
7407 case BFD_RELOC_386_TLS_GOTDESC:
7408 case BFD_RELOC_386_TLS_DESC_CALL:
7409 case BFD_RELOC_X86_64_TLSGD:
7410 case BFD_RELOC_X86_64_TLSLD:
7411 case BFD_RELOC_X86_64_DTPOFF32:
7412 case BFD_RELOC_X86_64_DTPOFF64:
7413 case BFD_RELOC_X86_64_GOTTPOFF:
7414 case BFD_RELOC_X86_64_TPOFF32:
7415 case BFD_RELOC_X86_64_TPOFF64:
7416 case BFD_RELOC_X86_64_GOTOFF64:
7417 case BFD_RELOC_X86_64_GOTPC32:
7418 case BFD_RELOC_X86_64_GOT64:
7419 case BFD_RELOC_X86_64_GOTPCREL64:
7420 case BFD_RELOC_X86_64_GOTPC64:
7421 case BFD_RELOC_X86_64_GOTPLT64:
7422 case BFD_RELOC_X86_64_PLTOFF64:
7423 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7424 case BFD_RELOC_X86_64_TLSDESC_CALL:
7426 case BFD_RELOC_VTABLE_ENTRY:
7427 case BFD_RELOC_VTABLE_INHERIT:
7429 case BFD_RELOC_32_SECREL:
7431 code = fixp->fx_r_type;
7433 case BFD_RELOC_X86_64_32S:
7434 if (!fixp->fx_pcrel)
7436 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7437 code = fixp->fx_r_type;
7443 switch (fixp->fx_size)
7446 as_bad_where (fixp->fx_file, fixp->fx_line,
7447 _("can not do %d byte pc-relative relocation"),
7449 code = BFD_RELOC_32_PCREL;
7451 case 1: code = BFD_RELOC_8_PCREL; break;
7452 case 2: code = BFD_RELOC_16_PCREL; break;
7453 case 4: code = BFD_RELOC_32_PCREL; break;
7455 case 8: code = BFD_RELOC_64_PCREL; break;
7461 switch (fixp->fx_size)
7464 as_bad_where (fixp->fx_file, fixp->fx_line,
7465 _("can not do %d byte relocation"),
7467 code = BFD_RELOC_32;
7469 case 1: code = BFD_RELOC_8; break;
7470 case 2: code = BFD_RELOC_16; break;
7471 case 4: code = BFD_RELOC_32; break;
7473 case 8: code = BFD_RELOC_64; break;
7480 if ((code == BFD_RELOC_32
7481 || code == BFD_RELOC_32_PCREL
7482 || code == BFD_RELOC_X86_64_32S)
7484 && fixp->fx_addsy == GOT_symbol)
7487 code = BFD_RELOC_386_GOTPC;
7489 code = BFD_RELOC_X86_64_GOTPC32;
7491 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7493 && fixp->fx_addsy == GOT_symbol)
7495 code = BFD_RELOC_X86_64_GOTPC64;
7498 rel = (arelent *) xmalloc (sizeof (arelent));
7499 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7500 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7502 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7504 if (!use_rela_relocations)
7506 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7507 vtable entry to be used in the relocation's section offset. */
7508 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7509 rel->address = fixp->fx_offset;
7513 /* Use the rela in 64bit mode. */
7516 if (!fixp->fx_pcrel)
7517 rel->addend = fixp->fx_offset;
7521 case BFD_RELOC_X86_64_PLT32:
7522 case BFD_RELOC_X86_64_GOT32:
7523 case BFD_RELOC_X86_64_GOTPCREL:
7524 case BFD_RELOC_X86_64_TLSGD:
7525 case BFD_RELOC_X86_64_TLSLD:
7526 case BFD_RELOC_X86_64_GOTTPOFF:
7527 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7528 case BFD_RELOC_X86_64_TLSDESC_CALL:
7529 rel->addend = fixp->fx_offset - fixp->fx_size;
7532 rel->addend = (section->vma
7534 + fixp->fx_addnumber
7535 + md_pcrel_from (fixp));
7540 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7541 if (rel->howto == NULL)
7543 as_bad_where (fixp->fx_file, fixp->fx_line,
7544 _("cannot represent relocation type %s"),
7545 bfd_get_reloc_code_name (code));
7546 /* Set howto to a garbage value so that we can keep going. */
7547 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7548 assert (rel->howto != NULL);
7555 /* Parse operands using Intel syntax. This implements a recursive descent
7556 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7559 FIXME: We do not recognize the full operand grammar defined in the MASM
7560 documentation. In particular, all the structure/union and
7561 high-level macro operands are missing.
7563 Uppercase words are terminals, lower case words are non-terminals.
7564 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7565 bars '|' denote choices. Most grammar productions are implemented in
7566 functions called 'intel_<production>'.
7568 Initial production is 'expr'.
7574 binOp & | AND | \| | OR | ^ | XOR
7576 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7578 constant digits [[ radixOverride ]]
7580 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7618 => expr expr cmpOp e04
7621 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7622 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7624 hexdigit a | b | c | d | e | f
7625 | A | B | C | D | E | F
7631 mulOp * | / | % | MOD | << | SHL | >> | SHR
7635 register specialRegister
7639 segmentRegister CS | DS | ES | FS | GS | SS
7641 specialRegister CR0 | CR2 | CR3 | CR4
7642 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7643 | TR3 | TR4 | TR5 | TR6 | TR7
7645 We simplify the grammar in obvious places (e.g., register parsing is
7646 done by calling parse_register) and eliminate immediate left recursion
7647 to implement a recursive-descent parser.
7651 expr' cmpOp e04 expr'
7702 /* Parsing structure for the intel syntax parser. Used to implement the
7703 semantic actions for the operand grammar. */
7704 struct intel_parser_s
7706 char *op_string; /* The string being parsed. */
7707 int got_a_float; /* Whether the operand is a float. */
7708 int op_modifier; /* Operand modifier. */
7709 int is_mem; /* 1 if operand is memory reference. */
7710 int in_offset; /* >=1 if parsing operand of offset. */
7711 int in_bracket; /* >=1 if parsing operand in brackets. */
7712 const reg_entry *reg; /* Last register reference found. */
7713 char *disp; /* Displacement string being built. */
7714 char *next_operand; /* Resume point when splitting operands. */
7717 static struct intel_parser_s intel_parser;
7719 /* Token structure for parsing intel syntax. */
7722 int code; /* Token code. */
7723 const reg_entry *reg; /* Register entry for register tokens. */
7724 char *str; /* String representation. */
7727 static struct intel_token cur_token, prev_token;
7729 /* Token codes for the intel parser. Since T_SHORT is already used
7730 by COFF, undefine it first to prevent a warning. */
7749 /* Prototypes for intel parser functions. */
7750 static int intel_match_token (int);
7751 static void intel_putback_token (void);
7752 static void intel_get_token (void);
7753 static int intel_expr (void);
7754 static int intel_e04 (void);
7755 static int intel_e05 (void);
7756 static int intel_e06 (void);
7757 static int intel_e09 (void);
7758 static int intel_e10 (void);
7759 static int intel_e11 (void);
7762 i386_intel_operand (char *operand_string, int got_a_float)
7767 p = intel_parser.op_string = xstrdup (operand_string);
7768 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7772 /* Initialize token holders. */
7773 cur_token.code = prev_token.code = T_NIL;
7774 cur_token.reg = prev_token.reg = NULL;
7775 cur_token.str = prev_token.str = NULL;
7777 /* Initialize parser structure. */
7778 intel_parser.got_a_float = got_a_float;
7779 intel_parser.op_modifier = 0;
7780 intel_parser.is_mem = 0;
7781 intel_parser.in_offset = 0;
7782 intel_parser.in_bracket = 0;
7783 intel_parser.reg = NULL;
7784 intel_parser.disp[0] = '\0';
7785 intel_parser.next_operand = NULL;
7787 /* Read the first token and start the parser. */
7789 ret = intel_expr ();
7794 if (cur_token.code != T_NIL)
7796 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7797 current_templates->start->name, cur_token.str);
7800 /* If we found a memory reference, hand it over to i386_displacement
7801 to fill in the rest of the operand fields. */
7802 else if (intel_parser.is_mem)
7804 if ((i.mem_operands == 1
7805 && !current_templates->start->opcode_modifier.isstring)
7806 || i.mem_operands == 2)
7808 as_bad (_("too many memory references for '%s'"),
7809 current_templates->start->name);
7814 char *s = intel_parser.disp;
7817 if (!quiet_warnings && intel_parser.is_mem < 0)
7818 /* See the comments in intel_bracket_expr. */
7819 as_warn (_("Treating `%s' as memory reference"), operand_string);
7821 /* Add the displacement expression. */
7823 ret = i386_displacement (s, s + strlen (s));
7826 /* Swap base and index in 16-bit memory operands like
7827 [si+bx]. Since i386_index_check is also used in AT&T
7828 mode we have to do that here. */
7831 && i.base_reg->reg_type.bitfield.reg16
7832 && i.index_reg->reg_type.bitfield.reg16
7833 && i.base_reg->reg_num >= 6
7834 && i.index_reg->reg_num < 6)
7836 const reg_entry *base = i.index_reg;
7838 i.index_reg = i.base_reg;
7841 ret = i386_index_check (operand_string);
7846 /* Constant and OFFSET expressions are handled by i386_immediate. */
7847 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7848 || intel_parser.reg == NULL)
7849 ret = i386_immediate (intel_parser.disp);
7851 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7853 if (!ret || !intel_parser.next_operand)
7855 intel_parser.op_string = intel_parser.next_operand;
7856 this_operand = i.operands++;
7860 free (intel_parser.disp);
7865 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7869 expr' cmpOp e04 expr'
7874 /* XXX Implement the comparison operators. */
7875 return intel_e04 ();
7892 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7893 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7895 if (cur_token.code == '+')
7897 else if (cur_token.code == '-')
7898 nregs = NUM_ADDRESS_REGS;
7902 strcat (intel_parser.disp, cur_token.str);
7903 intel_match_token (cur_token.code);
7914 int nregs = ~NUM_ADDRESS_REGS;
7921 if (cur_token.code == '&'
7922 || cur_token.code == '|'
7923 || cur_token.code == '^')
7927 str[0] = cur_token.code;
7929 strcat (intel_parser.disp, str);
7934 intel_match_token (cur_token.code);
7939 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7940 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7951 int nregs = ~NUM_ADDRESS_REGS;
7958 if (cur_token.code == '*'
7959 || cur_token.code == '/'
7960 || cur_token.code == '%')
7964 str[0] = cur_token.code;
7966 strcat (intel_parser.disp, str);
7968 else if (cur_token.code == T_SHL)
7969 strcat (intel_parser.disp, "<<");
7970 else if (cur_token.code == T_SHR)
7971 strcat (intel_parser.disp, ">>");
7975 intel_match_token (cur_token.code);
7980 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7981 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7999 int nregs = ~NUM_ADDRESS_REGS;
8004 /* Don't consume constants here. */
8005 if (cur_token.code == '+' || cur_token.code == '-')
8007 /* Need to look one token ahead - if the next token
8008 is a constant, the current token is its sign. */
8011 intel_match_token (cur_token.code);
8012 next_code = cur_token.code;
8013 intel_putback_token ();
8014 if (next_code == T_CONST)
8018 /* e09 OFFSET e09 */
8019 if (cur_token.code == T_OFFSET)
8022 ++intel_parser.in_offset;
8026 else if (cur_token.code == T_SHORT)
8027 intel_parser.op_modifier |= 1 << T_SHORT;
8030 else if (cur_token.code == '+')
8031 strcat (intel_parser.disp, "+");
8036 else if (cur_token.code == '-' || cur_token.code == '~')
8042 str[0] = cur_token.code;
8044 strcat (intel_parser.disp, str);
8051 intel_match_token (cur_token.code);
8059 /* e09' PTR e10 e09' */
8060 if (cur_token.code == T_PTR)
8064 if (prev_token.code == T_BYTE)
8065 suffix = BYTE_MNEM_SUFFIX;
8067 else if (prev_token.code == T_WORD)
8069 if (current_templates->start->name[0] == 'l'
8070 && current_templates->start->name[2] == 's'
8071 && current_templates->start->name[3] == 0)
8072 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8073 else if (intel_parser.got_a_float == 2) /* "fi..." */
8074 suffix = SHORT_MNEM_SUFFIX;
8076 suffix = WORD_MNEM_SUFFIX;
8079 else if (prev_token.code == T_DWORD)
8081 if (current_templates->start->name[0] == 'l'
8082 && current_templates->start->name[2] == 's'
8083 && current_templates->start->name[3] == 0)
8084 suffix = WORD_MNEM_SUFFIX;
8085 else if (flag_code == CODE_16BIT
8086 && (current_templates->start->opcode_modifier.jump
8087 || current_templates->start->opcode_modifier.jumpdword))
8088 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8089 else if (intel_parser.got_a_float == 1) /* "f..." */
8090 suffix = SHORT_MNEM_SUFFIX;
8092 suffix = LONG_MNEM_SUFFIX;
8095 else if (prev_token.code == T_FWORD)
8097 if (current_templates->start->name[0] == 'l'
8098 && current_templates->start->name[2] == 's'
8099 && current_templates->start->name[3] == 0)
8100 suffix = LONG_MNEM_SUFFIX;
8101 else if (!intel_parser.got_a_float)
8103 if (flag_code == CODE_16BIT)
8104 add_prefix (DATA_PREFIX_OPCODE);
8105 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8108 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8111 else if (prev_token.code == T_QWORD)
8113 if (intel_parser.got_a_float == 1) /* "f..." */
8114 suffix = LONG_MNEM_SUFFIX;
8116 suffix = QWORD_MNEM_SUFFIX;
8119 else if (prev_token.code == T_TBYTE)
8121 if (intel_parser.got_a_float == 1)
8122 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8124 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8127 else if (prev_token.code == T_XMMWORD)
8129 suffix = XMMWORD_MNEM_SUFFIX;
8134 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8138 /* Operands for jump/call using 'ptr' notation denote absolute
8140 if (current_templates->start->opcode_modifier.jump
8141 || current_templates->start->opcode_modifier.jumpdword)
8142 i.types[this_operand].bitfield.jumpabsolute = 1;
8144 if (current_templates->start->base_opcode == 0x8d /* lea */)
8148 else if (i.suffix != suffix)
8150 as_bad (_("Conflicting operand modifiers"));
8156 /* e09' : e10 e09' */
8157 else if (cur_token.code == ':')
8159 if (prev_token.code != T_REG)
8161 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8162 segment/group identifier (which we don't have), using comma
8163 as the operand separator there is even less consistent, since
8164 there all branches only have a single operand. */
8165 if (this_operand != 0
8166 || intel_parser.in_offset
8167 || intel_parser.in_bracket
8168 || (!current_templates->start->opcode_modifier.jump
8169 && !current_templates->start->opcode_modifier.jumpdword
8170 && !current_templates->start->opcode_modifier.jumpintersegment
8171 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8172 return intel_match_token (T_NIL);
8173 /* Remember the start of the 2nd operand and terminate 1st
8175 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8176 another expression), but it gets at least the simplest case
8177 (a plain number or symbol on the left side) right. */
8178 intel_parser.next_operand = intel_parser.op_string;
8179 *--intel_parser.op_string = '\0';
8180 return intel_match_token (':');
8188 intel_match_token (cur_token.code);
8194 --intel_parser.in_offset;
8197 if (NUM_ADDRESS_REGS > nregs)
8199 as_bad (_("Invalid operand to `OFFSET'"));
8202 intel_parser.op_modifier |= 1 << T_OFFSET;
8205 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8206 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8211 intel_bracket_expr (void)
8213 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8214 const char *start = intel_parser.op_string;
8217 if (i.op[this_operand].regs)
8218 return intel_match_token (T_NIL);
8220 intel_match_token ('[');
8222 /* Mark as a memory operand only if it's not already known to be an
8223 offset expression. If it's an offset expression, we need to keep
8225 if (!intel_parser.in_offset)
8227 ++intel_parser.in_bracket;
8229 /* Operands for jump/call inside brackets denote absolute addresses. */
8230 if (current_templates->start->opcode_modifier.jump
8231 || current_templates->start->opcode_modifier.jumpdword)
8232 i.types[this_operand].bitfield.jumpabsolute = 1;
8234 /* Unfortunately gas always diverged from MASM in a respect that can't
8235 be easily fixed without risking to break code sequences likely to be
8236 encountered (the testsuite even check for this): MASM doesn't consider
8237 an expression inside brackets unconditionally as a memory reference.
8238 When that is e.g. a constant, an offset expression, or the sum of the
8239 two, this is still taken as a constant load. gas, however, always
8240 treated these as memory references. As a compromise, we'll try to make
8241 offset expressions inside brackets work the MASM way (since that's
8242 less likely to be found in real world code), but make constants alone
8243 continue to work the traditional gas way. In either case, issue a
8245 intel_parser.op_modifier &= ~was_offset;
8248 strcat (intel_parser.disp, "[");
8250 /* Add a '+' to the displacement string if necessary. */
8251 if (*intel_parser.disp != '\0'
8252 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8253 strcat (intel_parser.disp, "+");
8256 && (len = intel_parser.op_string - start - 1,
8257 intel_match_token (']')))
8259 /* Preserve brackets when the operand is an offset expression. */
8260 if (intel_parser.in_offset)
8261 strcat (intel_parser.disp, "]");
8264 --intel_parser.in_bracket;
8265 if (i.base_reg || i.index_reg)
8266 intel_parser.is_mem = 1;
8267 if (!intel_parser.is_mem)
8269 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8270 /* Defer the warning until all of the operand was parsed. */
8271 intel_parser.is_mem = -1;
8272 else if (!quiet_warnings)
8273 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8274 len, start, len, start);
8277 intel_parser.op_modifier |= was_offset;
8294 while (cur_token.code == '[')
8296 if (!intel_bracket_expr ())
8321 switch (cur_token.code)
8325 intel_match_token ('(');
8326 strcat (intel_parser.disp, "(");
8328 if (intel_expr () && intel_match_token (')'))
8330 strcat (intel_parser.disp, ")");
8337 return intel_bracket_expr ();
8342 strcat (intel_parser.disp, cur_token.str);
8343 intel_match_token (cur_token.code);
8345 /* Mark as a memory operand only if it's not already known to be an
8346 offset expression. */
8347 if (!intel_parser.in_offset)
8348 intel_parser.is_mem = 1;
8355 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8357 intel_match_token (T_REG);
8359 /* Check for segment change. */
8360 if (cur_token.code == ':')
8362 if (!reg->reg_type.bitfield.sreg2
8363 && !reg->reg_type.bitfield.sreg3)
8365 as_bad (_("`%s' is not a valid segment register"),
8369 else if (i.seg[i.mem_operands])
8370 as_warn (_("Extra segment override ignored"));
8373 if (!intel_parser.in_offset)
8374 intel_parser.is_mem = 1;
8375 switch (reg->reg_num)
8378 i.seg[i.mem_operands] = &es;
8381 i.seg[i.mem_operands] = &cs;
8384 i.seg[i.mem_operands] = &ss;
8387 i.seg[i.mem_operands] = &ds;
8390 i.seg[i.mem_operands] = &fs;
8393 i.seg[i.mem_operands] = &gs;
8399 /* Not a segment register. Check for register scaling. */
8400 else if (cur_token.code == '*')
8402 if (!intel_parser.in_bracket)
8404 as_bad (_("Register scaling only allowed in memory operands"));
8408 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8409 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8410 else if (i.index_reg)
8411 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8413 /* What follows must be a valid scale. */
8414 intel_match_token ('*');
8416 i.types[this_operand].bitfield.baseindex = 1;
8418 /* Set the scale after setting the register (otherwise,
8419 i386_scale will complain) */
8420 if (cur_token.code == '+' || cur_token.code == '-')
8422 char *str, sign = cur_token.code;
8423 intel_match_token (cur_token.code);
8424 if (cur_token.code != T_CONST)
8426 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8430 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8431 strcpy (str + 1, cur_token.str);
8433 if (!i386_scale (str))
8437 else if (!i386_scale (cur_token.str))
8439 intel_match_token (cur_token.code);
8442 /* No scaling. If this is a memory operand, the register is either a
8443 base register (first occurrence) or an index register (second
8445 else if (intel_parser.in_bracket)
8450 else if (!i.index_reg)
8454 as_bad (_("Too many register references in memory operand"));
8458 i.types[this_operand].bitfield.baseindex = 1;
8461 /* It's neither base nor index. */
8462 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8464 i386_operand_type temp = reg->reg_type;
8465 temp.bitfield.baseindex = 0;
8466 i.types[this_operand] = operand_type_or (i.types[this_operand],
8468 i.op[this_operand].regs = reg;
8473 as_bad (_("Invalid use of register"));
8477 /* Since registers are not part of the displacement string (except
8478 when we're parsing offset operands), we may need to remove any
8479 preceding '+' from the displacement string. */
8480 if (*intel_parser.disp != '\0'
8481 && !intel_parser.in_offset)
8483 char *s = intel_parser.disp;
8484 s += strlen (s) - 1;
8507 intel_match_token (cur_token.code);
8509 if (cur_token.code == T_PTR)
8512 /* It must have been an identifier. */
8513 intel_putback_token ();
8514 cur_token.code = T_ID;
8520 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8524 /* The identifier represents a memory reference only if it's not
8525 preceded by an offset modifier and if it's not an equate. */
8526 symbolP = symbol_find(cur_token.str);
8527 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8528 intel_parser.is_mem = 1;
8536 char *save_str, sign = 0;
8538 /* Allow constants that start with `+' or `-'. */
8539 if (cur_token.code == '-' || cur_token.code == '+')
8541 sign = cur_token.code;
8542 intel_match_token (cur_token.code);
8543 if (cur_token.code != T_CONST)
8545 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8551 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8552 strcpy (save_str + !!sign, cur_token.str);
8556 /* Get the next token to check for register scaling. */
8557 intel_match_token (cur_token.code);
8559 /* Check if this constant is a scaling factor for an
8561 if (cur_token.code == '*')
8563 if (intel_match_token ('*') && cur_token.code == T_REG)
8565 const reg_entry *reg = cur_token.reg;
8567 if (!intel_parser.in_bracket)
8569 as_bad (_("Register scaling only allowed "
8570 "in memory operands"));
8574 /* Disallow things like [1*si].
8575 sp and esp are invalid as index. */
8576 if (reg->reg_type.bitfield.reg16)
8577 reg = i386_regtab + REGNAM_AX + 4;
8578 else if (i.index_reg)
8579 reg = i386_regtab + REGNAM_EAX + 4;
8581 /* The constant is followed by `* reg', so it must be
8584 i.types[this_operand].bitfield.baseindex = 1;
8586 /* Set the scale after setting the register (otherwise,
8587 i386_scale will complain) */
8588 if (!i386_scale (save_str))
8590 intel_match_token (T_REG);
8592 /* Since registers are not part of the displacement
8593 string, we may need to remove any preceding '+' from
8594 the displacement string. */
8595 if (*intel_parser.disp != '\0')
8597 char *s = intel_parser.disp;
8598 s += strlen (s) - 1;
8608 /* The constant was not used for register scaling. Since we have
8609 already consumed the token following `*' we now need to put it
8610 back in the stream. */
8611 intel_putback_token ();
8614 /* Add the constant to the displacement string. */
8615 strcat (intel_parser.disp, save_str);
8622 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8626 /* Match the given token against cur_token. If they match, read the next
8627 token from the operand string. */
8629 intel_match_token (int code)
8631 if (cur_token.code == code)
8638 as_bad (_("Unexpected token `%s'"), cur_token.str);
8643 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8645 intel_get_token (void)
8648 const reg_entry *reg;
8649 struct intel_token new_token;
8651 new_token.code = T_NIL;
8652 new_token.reg = NULL;
8653 new_token.str = NULL;
8655 /* Free the memory allocated to the previous token and move
8656 cur_token to prev_token. */
8658 free (prev_token.str);
8660 prev_token = cur_token;
8662 /* Skip whitespace. */
8663 while (is_space_char (*intel_parser.op_string))
8664 intel_parser.op_string++;
8666 /* Return an empty token if we find nothing else on the line. */
8667 if (*intel_parser.op_string == '\0')
8669 cur_token = new_token;
8673 /* The new token cannot be larger than the remainder of the operand
8675 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8676 new_token.str[0] = '\0';
8678 if (strchr ("0123456789", *intel_parser.op_string))
8680 char *p = new_token.str;
8681 char *q = intel_parser.op_string;
8682 new_token.code = T_CONST;
8684 /* Allow any kind of identifier char to encompass floating point and
8685 hexadecimal numbers. */
8686 while (is_identifier_char (*q))
8690 /* Recognize special symbol names [0-9][bf]. */
8691 if (strlen (intel_parser.op_string) == 2
8692 && (intel_parser.op_string[1] == 'b'
8693 || intel_parser.op_string[1] == 'f'))
8694 new_token.code = T_ID;
8697 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8699 size_t len = end_op - intel_parser.op_string;
8701 new_token.code = T_REG;
8702 new_token.reg = reg;
8704 memcpy (new_token.str, intel_parser.op_string, len);
8705 new_token.str[len] = '\0';
8708 else if (is_identifier_char (*intel_parser.op_string))
8710 char *p = new_token.str;
8711 char *q = intel_parser.op_string;
8713 /* A '.' or '$' followed by an identifier char is an identifier.
8714 Otherwise, it's operator '.' followed by an expression. */
8715 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8717 new_token.code = '.';
8718 new_token.str[0] = '.';
8719 new_token.str[1] = '\0';
8723 while (is_identifier_char (*q) || *q == '@')
8727 if (strcasecmp (new_token.str, "NOT") == 0)
8728 new_token.code = '~';
8730 else if (strcasecmp (new_token.str, "MOD") == 0)
8731 new_token.code = '%';
8733 else if (strcasecmp (new_token.str, "AND") == 0)
8734 new_token.code = '&';
8736 else if (strcasecmp (new_token.str, "OR") == 0)
8737 new_token.code = '|';
8739 else if (strcasecmp (new_token.str, "XOR") == 0)
8740 new_token.code = '^';
8742 else if (strcasecmp (new_token.str, "SHL") == 0)
8743 new_token.code = T_SHL;
8745 else if (strcasecmp (new_token.str, "SHR") == 0)
8746 new_token.code = T_SHR;
8748 else if (strcasecmp (new_token.str, "BYTE") == 0)
8749 new_token.code = T_BYTE;
8751 else if (strcasecmp (new_token.str, "WORD") == 0)
8752 new_token.code = T_WORD;
8754 else if (strcasecmp (new_token.str, "DWORD") == 0)
8755 new_token.code = T_DWORD;
8757 else if (strcasecmp (new_token.str, "FWORD") == 0)
8758 new_token.code = T_FWORD;
8760 else if (strcasecmp (new_token.str, "QWORD") == 0)
8761 new_token.code = T_QWORD;
8763 else if (strcasecmp (new_token.str, "TBYTE") == 0
8764 /* XXX remove (gcc still uses it) */
8765 || strcasecmp (new_token.str, "XWORD") == 0)
8766 new_token.code = T_TBYTE;
8768 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8769 || strcasecmp (new_token.str, "OWORD") == 0)
8770 new_token.code = T_XMMWORD;
8772 else if (strcasecmp (new_token.str, "PTR") == 0)
8773 new_token.code = T_PTR;
8775 else if (strcasecmp (new_token.str, "SHORT") == 0)
8776 new_token.code = T_SHORT;
8778 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8780 new_token.code = T_OFFSET;
8782 /* ??? This is not mentioned in the MASM grammar but gcc
8783 makes use of it with -mintel-syntax. OFFSET may be
8784 followed by FLAT: */
8785 if (strncasecmp (q, " FLAT:", 6) == 0)
8786 strcat (new_token.str, " FLAT:");
8789 /* ??? This is not mentioned in the MASM grammar. */
8790 else if (strcasecmp (new_token.str, "FLAT") == 0)
8792 new_token.code = T_OFFSET;
8794 strcat (new_token.str, ":");
8796 as_bad (_("`:' expected"));
8800 new_token.code = T_ID;
8804 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8806 new_token.code = *intel_parser.op_string;
8807 new_token.str[0] = *intel_parser.op_string;
8808 new_token.str[1] = '\0';
8811 else if (strchr ("<>", *intel_parser.op_string)
8812 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8814 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8815 new_token.str[0] = *intel_parser.op_string;
8816 new_token.str[1] = *intel_parser.op_string;
8817 new_token.str[2] = '\0';
8821 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8823 intel_parser.op_string += strlen (new_token.str);
8824 cur_token = new_token;
8827 /* Put cur_token back into the token stream and make cur_token point to
8830 intel_putback_token (void)
8832 if (cur_token.code != T_NIL)
8834 intel_parser.op_string -= strlen (cur_token.str);
8835 free (cur_token.str);
8837 cur_token = prev_token;
8839 /* Forget prev_token. */
8840 prev_token.code = T_NIL;
8841 prev_token.reg = NULL;
8842 prev_token.str = NULL;
8846 tc_x86_regname_to_dw2regnum (char *regname)
8848 unsigned int regnum;
8849 unsigned int regnames_count;
8850 static const char *const regnames_32[] =
8852 "eax", "ecx", "edx", "ebx",
8853 "esp", "ebp", "esi", "edi",
8854 "eip", "eflags", NULL,
8855 "st0", "st1", "st2", "st3",
8856 "st4", "st5", "st6", "st7",
8858 "xmm0", "xmm1", "xmm2", "xmm3",
8859 "xmm4", "xmm5", "xmm6", "xmm7",
8860 "mm0", "mm1", "mm2", "mm3",
8861 "mm4", "mm5", "mm6", "mm7",
8862 "fcw", "fsw", "mxcsr",
8863 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8866 static const char *const regnames_64[] =
8868 "rax", "rdx", "rcx", "rbx",
8869 "rsi", "rdi", "rbp", "rsp",
8870 "r8", "r9", "r10", "r11",
8871 "r12", "r13", "r14", "r15",
8873 "xmm0", "xmm1", "xmm2", "xmm3",
8874 "xmm4", "xmm5", "xmm6", "xmm7",
8875 "xmm8", "xmm9", "xmm10", "xmm11",
8876 "xmm12", "xmm13", "xmm14", "xmm15",
8877 "st0", "st1", "st2", "st3",
8878 "st4", "st5", "st6", "st7",
8879 "mm0", "mm1", "mm2", "mm3",
8880 "mm4", "mm5", "mm6", "mm7",
8882 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8883 "fs.base", "gs.base", NULL, NULL,
8885 "mxcsr", "fcw", "fsw"
8887 const char *const *regnames;
8889 if (flag_code == CODE_64BIT)
8891 regnames = regnames_64;
8892 regnames_count = ARRAY_SIZE (regnames_64);
8896 regnames = regnames_32;
8897 regnames_count = ARRAY_SIZE (regnames_32);
8900 for (regnum = 0; regnum < regnames_count; regnum++)
8901 if (regnames[regnum] != NULL
8902 && strcmp (regname, regnames[regnum]) == 0)
8909 tc_x86_frame_initial_instructions (void)
8911 static unsigned int sp_regno;
8914 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8917 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8918 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8922 i386_elf_section_type (const char *str, size_t len)
8924 if (flag_code == CODE_64BIT
8925 && len == sizeof ("unwind") - 1
8926 && strncmp (str, "unwind", 6) == 0)
8927 return SHT_X86_64_UNWIND;
8934 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8938 expr.X_op = O_secrel;
8939 expr.X_add_symbol = symbol;
8940 expr.X_add_number = 0;
8941 emit_expr (&expr, size);
8945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8946 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8949 x86_64_section_letter (int letter, char **ptr_msg)
8951 if (flag_code == CODE_64BIT)
8954 return SHF_X86_64_LARGE;
8956 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8959 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8964 x86_64_section_word (char *str, size_t len)
8966 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8967 return SHF_X86_64_LARGE;
8973 handle_large_common (int small ATTRIBUTE_UNUSED)
8975 if (flag_code != CODE_64BIT)
8977 s_comm_internal (0, elf_common_parse);
8978 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8982 static segT lbss_section;
8983 asection *saved_com_section_ptr = elf_com_section_ptr;
8984 asection *saved_bss_section = bss_section;
8986 if (lbss_section == NULL)
8988 flagword applicable;
8990 subsegT subseg = now_subseg;
8992 /* The .lbss section is for local .largecomm symbols. */
8993 lbss_section = subseg_new (".lbss", 0);
8994 applicable = bfd_applicable_section_flags (stdoutput);
8995 bfd_set_section_flags (stdoutput, lbss_section,
8996 applicable & SEC_ALLOC);
8997 seg_info (lbss_section)->bss = 1;
8999 subseg_set (seg, subseg);
9002 elf_com_section_ptr = &_bfd_elf_large_com_section;
9003 bss_section = lbss_section;
9005 s_comm_internal (0, elf_common_parse);
9007 elf_com_section_ptr = saved_com_section_ptr;
9008 bss_section = saved_bss_section;
9011 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */