1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry *parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry *build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS *, offsetT);
96 static void output_disp (fragS *, offsetT);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED);
104 static const char *default_arch = DEFAULT_ARCH;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry *regs;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 unsigned int types[MAX_OPERANDS];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op[MAX_OPERANDS];
141 /* Flags for operands. */
142 unsigned int flags[MAX_OPERANDS];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry *base_reg;
151 const reg_entry *index_reg;
152 unsigned int log2_scale_factor;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry *seg[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes;
161 unsigned char prefix[MAX_PREFIXES];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars = "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars = "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars[] = "#/";
213 const char line_separator_chars[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars[256];
226 static char register_chars[256];
227 static char operand_chars[256];
228 static char identifier_chars[256];
229 static char digit_chars[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack[32];
247 static char *save_stack_p;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates *current_templates;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
261 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
263 /* Current operand we are working on. */
264 static int this_operand;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code;
276 static unsigned int object_64bit;
277 static int use_rela_relocations = 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names[] =
287 /* 1 for intel syntax,
289 static int intel_syntax = 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg = 0;
294 /* Register prefix used for error message. */
295 static const char *register_prefix = "%";
297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300 static char stackop_size = '\0';
302 /* Non-zero to optimize code alignment. */
303 int optimize_align_code = 1;
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings = 0;
309 static const char *cpu_arch_name = NULL;
310 static const char *cpu_sub_arch_name = NULL;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
315 /* If we have selected a cpu we are generating instructions for. */
316 static int cpu_arch_tune_set = 0;
318 /* Cpu we are generating instructions for. */
319 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321 /* CPU feature flags of cpu we are generating instructions for. */
322 static unsigned int cpu_arch_tune_flags = 0;
324 /* CPU instruction set architecture used. */
325 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of instruction set architecture used. */
328 static unsigned int cpu_arch_isa_flags = 0;
330 /* If set, conditional jumps are not automatically promoted to handle
331 larger than a byte offset. */
332 static unsigned int no_cond_jump_promotion = 0;
334 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
335 static symbolS *GOT_symbol;
337 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
338 unsigned int x86_dwarf2_return_column;
340 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
341 int x86_cie_data_alignment;
343 /* Interface to relax_segment.
344 There are 3 major relax states for 386 jump insns because the
345 different types of jumps add different sizes to frags when we're
346 figuring out what sort of jump to choose to reach a given label. */
349 #define UNCOND_JUMP 0
351 #define COND_JUMP86 2
356 #define SMALL16 (SMALL | CODE16)
358 #define BIG16 (BIG | CODE16)
362 #define INLINE __inline__
368 #define ENCODE_RELAX_STATE(type, size) \
369 ((relax_substateT) (((type) << 2) | (size)))
370 #define TYPE_FROM_RELAX_STATE(s) \
372 #define DISP_SIZE_FROM_RELAX_STATE(s) \
373 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
375 /* This table is used by relax_frag to promote short jumps to long
376 ones where necessary. SMALL (short) jumps may be promoted to BIG
377 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
378 don't allow a short jump in a 32 bit code segment to be promoted to
379 a 16 bit offset jump because it's slower (requires data size
380 prefix), and doesn't work, unless the destination is in the bottom
381 64k of the code segment (The top 16 bits of eip are zeroed). */
383 const relax_typeS md_relax_table[] =
386 1) most positive reach of this state,
387 2) most negative reach of this state,
388 3) how many bytes this mode will have in the variable part of the frag
389 4) which index into the table to try if we can't fit into this one. */
391 /* UNCOND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
394 /* dword jmp adds 4 bytes to frag:
395 0 extra opcode bytes, 4 displacement bytes. */
397 /* word jmp adds 2 byte2 to frag:
398 0 extra opcode bytes, 2 displacement bytes. */
401 /* COND_JUMP states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
407 /* word conditionals add 3 bytes to frag:
408 1 extra opcode byte, 2 displacement bytes. */
411 /* COND_JUMP86 states. */
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
414 /* dword conditionals adds 5 bytes to frag:
415 1 extra opcode byte, 4 displacement bytes. */
417 /* word conditionals add 4 bytes to frag:
418 1 displacement byte and a 3 byte long branch insn. */
422 static const arch_entry cpu_arch[] =
424 {"generic32", PROCESSOR_GENERIC32,
425 Cpu186|Cpu286|Cpu386},
426 {"generic64", PROCESSOR_GENERIC64,
427 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
428 |CpuMMX2|CpuSSE|CpuSSE2},
429 {"i8086", PROCESSOR_UNKNOWN,
431 {"i186", PROCESSOR_UNKNOWN,
433 {"i286", PROCESSOR_UNKNOWN,
435 {"i386", PROCESSOR_GENERIC32,
436 Cpu186|Cpu286|Cpu386},
437 {"i486", PROCESSOR_I486,
438 Cpu186|Cpu286|Cpu386|Cpu486},
439 {"i586", PROCESSOR_PENTIUM,
440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
441 {"i686", PROCESSOR_PENTIUMPRO,
442 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
443 {"pentium", PROCESSOR_PENTIUM,
444 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
446 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
447 {"pentiumii", PROCESSOR_PENTIUMPRO,
448 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
450 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
451 {"pentium4", PROCESSOR_PENTIUM4,
452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
453 |CpuMMX2|CpuSSE|CpuSSE2},
454 {"prescott", PROCESSOR_NOCONA,
455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
456 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
457 {"nocona", PROCESSOR_NOCONA,
458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
459 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
460 {"yonah", PROCESSOR_CORE,
461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
463 {"core", PROCESSOR_CORE,
464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"merom", PROCESSOR_CORE2,
467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
469 {"core2", PROCESSOR_CORE2,
470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
474 {"k6_2", PROCESSOR_K6,
475 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
476 {"athlon", PROCESSOR_ATHLON,
477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"amdfam10", PROCESSOR_AMDFAM10,
489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
492 {".mmx", PROCESSOR_UNKNOWN,
494 {".sse", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE},
496 {".sse2", PROCESSOR_UNKNOWN,
497 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
498 {".sse3", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
500 {".ssse3", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
502 {".3dnow", PROCESSOR_UNKNOWN,
504 {".3dnowa", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
506 {".padlock", PROCESSOR_UNKNOWN,
508 {".pacifica", PROCESSOR_UNKNOWN,
510 {".svme", PROCESSOR_UNKNOWN,
512 {".sse4a", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
514 {".abm", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
550 {"secrel32", pe_directive_secrel, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control *op_hash;
561 /* Hash table for register lookup. */
562 static struct hash_control *reg_hash;
565 i386_align_code (fragS *fragP, int count)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1[] =
572 static const char f32_2[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_15[] =
607 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
608 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
609 static const char f16_3[] =
610 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
611 static const char f16_4[] =
612 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_5[] =
615 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
616 static const char f16_6[] =
617 {0x89,0xf6, /* mov %si,%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_7[] =
620 {0x8d,0x74,0x00, /* lea 0(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char f16_8[] =
623 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
629 static const char *const f16_patt[] = {
630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
631 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
634 static const char alt_3[] =
636 /* nopl 0(%[re]ax) */
637 static const char alt_4[] =
638 {0x0f,0x1f,0x40,0x00};
639 /* nopl 0(%[re]ax,%[re]ax,1) */
640 static const char alt_5[] =
641 {0x0f,0x1f,0x44,0x00,0x00};
642 /* nopw 0(%[re]ax,%[re]ax,1) */
643 static const char alt_6[] =
644 {0x66,0x0f,0x1f,0x44,0x00,0x00};
645 /* nopl 0L(%[re]ax) */
646 static const char alt_7[] =
647 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
648 /* nopl 0L(%[re]ax,%[re]ax,1) */
649 static const char alt_8[] =
650 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
651 /* nopw 0L(%[re]ax,%[re]ax,1) */
652 static const char alt_9[] =
653 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_10[] =
656 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 nopw %cs:0L(%[re]ax,%[re]ax,1) */
659 static const char alt_long_11[] =
661 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_12[] =
668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_13[] =
677 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
682 nopw %cs:0L(%[re]ax,%[re]ax,1) */
683 static const char alt_long_14[] =
688 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 nopw %cs:0L(%[re]ax,%[re]ax,1) */
695 static const char alt_long_15[] =
701 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
702 /* nopl 0(%[re]ax,%[re]ax,1)
703 nopw 0(%[re]ax,%[re]ax,1) */
704 static const char alt_short_11[] =
705 {0x0f,0x1f,0x44,0x00,0x00,
706 0x66,0x0f,0x1f,0x44,0x00,0x00};
707 /* nopw 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_12[] =
710 {0x66,0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
714 static const char alt_short_13[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 static const char alt_short_14[] =
720 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 nopl 0L(%[re]ax,%[re]ax,1) */
724 static const char alt_short_15[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
727 static const char *const alt_short_patt[] = {
728 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
729 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
730 alt_short_14, alt_short_15
732 static const char *const alt_long_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
735 alt_long_14, alt_long_15
738 if (count <= 0 || count > 15)
741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
744 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
745 f32_patt will be used.
746 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code == CODE_16BIT)
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
776 for (i = 0; i < remains; i++)
778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
782 for (; i < nnops; i++)
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
791 const char *const *patt = NULL;
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
806 case PROCESSOR_CORE2:
807 patt = alt_long_patt;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
814 case PROCESSOR_ATHLON:
816 case PROCESSOR_GENERIC64:
817 case PROCESSOR_AMDFAM10:
818 patt = alt_short_patt;
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
829 switch (cpu_arch_tune)
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
844 case PROCESSOR_ATHLON:
846 case PROCESSOR_AMDFAM10:
847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
855 case PROCESSOR_CORE2:
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
867 memcpy (fragP->fr_literal + fragP->fr_fix,
868 patt[count - 1], count);
870 fragP->fr_var = count;
873 static INLINE unsigned int
874 mode_from_disp_size (unsigned int t)
876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
880 fits_in_signed_byte (offsetT num)
882 return (num >= -128) && (num <= 127);
886 fits_in_unsigned_byte (offsetT num)
888 return (num & 0xff) == num;
892 fits_in_unsigned_word (offsetT num)
894 return (num & 0xffff) == num;
898 fits_in_signed_word (offsetT num)
900 return (-32768 <= num) && (num <= 32767);
904 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
912 } /* fits_in_signed_long() */
915 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
922 } /* fits_in_unsigned_long() */
925 smallest_imm_type (offsetT num)
927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
937 return (fits_in_signed_byte (num)
938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
939 : fits_in_unsigned_byte (num)
940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
951 offset_in_range (offsetT val, int size)
957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
959 case 4: mask = ((addressT) 2 << 31) - 1; break;
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
966 /* If BFD64, sign extend val. */
967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
973 char buf1[40], buf2[40];
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
982 /* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
986 add_prefix (unsigned int prefix)
991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
994 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
995 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
996 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1020 case LOCK_PREFIX_OPCODE:
1028 case ADDR_PREFIX_OPCODE:
1032 case DATA_PREFIX_OPCODE:
1036 if (i.prefix[q] != 0)
1044 i.prefix[q] |= prefix;
1047 as_bad (_("same type of prefix used twice"));
1053 set_code_flag (int value)
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1060 as_bad (_("64bit mode not supported on this CPU."));
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1064 as_bad (_("32bit mode not supported on this CPU."));
1066 stackop_size = '\0';
1070 set_16bit_gcc_code_flag (int new_code_flag)
1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1075 stackop_size = LONG_MNEM_SUFFIX;
1079 set_intel_syntax (int syntax_flag)
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1090 if (strcmp (string, "prefix") == 0)
1092 else if (strcmp (string, "noprefix") == 0)
1095 as_bad (_("bad argument to syntax directive."));
1096 *input_line_pointer = e;
1098 demand_empty_rest_of_line ();
1100 intel_syntax = syntax_flag;
1102 if (ask_naked_reg == 0)
1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1106 allow_naked_reg = (ask_naked_reg < 0);
1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
1110 register_prefix = allow_naked_reg ? "" : "%";
1114 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
1133 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1134 cpu_arch_isa = cpu_arch[i].type;
1135 cpu_arch_isa_flags = cpu_arch[i].flags;
1136 if (!cpu_arch_tune_set)
1138 cpu_arch_tune = cpu_arch_isa;
1139 cpu_arch_tune_flags = cpu_arch_isa_flags;
1143 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1145 cpu_sub_arch_name = cpu_arch[i].name;
1146 cpu_arch_flags |= cpu_arch[i].flags;
1148 *input_line_pointer = e;
1149 demand_empty_rest_of_line ();
1153 if (i >= ARRAY_SIZE (cpu_arch))
1154 as_bad (_("no such architecture: `%s'"), string);
1156 *input_line_pointer = e;
1159 as_bad (_("missing cpu architecture"));
1161 no_cond_jump_promotion = 0;
1162 if (*input_line_pointer == ','
1163 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1165 char *string = ++input_line_pointer;
1166 int e = get_symbol_end ();
1168 if (strcmp (string, "nojumps") == 0)
1169 no_cond_jump_promotion = 1;
1170 else if (strcmp (string, "jumps") == 0)
1173 as_bad (_("no such architecture modifier: `%s'"), string);
1175 *input_line_pointer = e;
1178 demand_empty_rest_of_line ();
1184 if (!strcmp (default_arch, "x86_64"))
1185 return bfd_mach_x86_64;
1186 else if (!strcmp (default_arch, "i386"))
1187 return bfd_mach_i386_i386;
1189 as_fatal (_("Unknown architecture"));
1195 const char *hash_err;
1197 /* Initialize op_hash hash table. */
1198 op_hash = hash_new ();
1201 const template *optab;
1202 templates *core_optab;
1204 /* Setup for loop. */
1206 core_optab = (templates *) xmalloc (sizeof (templates));
1207 core_optab->start = optab;
1212 if (optab->name == NULL
1213 || strcmp (optab->name, (optab - 1)->name) != 0)
1215 /* different name --> ship out current template list;
1216 add to hash table; & begin anew. */
1217 core_optab->end = optab;
1218 hash_err = hash_insert (op_hash,
1223 as_fatal (_("Internal Error: Can't hash %s: %s"),
1227 if (optab->name == NULL)
1229 core_optab = (templates *) xmalloc (sizeof (templates));
1230 core_optab->start = optab;
1235 /* Initialize reg_hash hash table. */
1236 reg_hash = hash_new ();
1238 const reg_entry *regtab;
1240 for (regtab = i386_regtab;
1241 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1257 for (c = 0; c < 256; c++)
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1266 else if (ISLOWER (c))
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1272 else if (ISUPPER (c))
1274 mnemonic_chars[c] = TOLOWER (c);
1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1279 if (ISALPHA (c) || ISDIGIT (c))
1280 identifier_chars[c] = c;
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1289 identifier_chars['@'] = '@';
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
1295 digit_chars['-'] = '-';
1296 mnemonic_chars['-'] = '-';
1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1313 if (flag_code == CODE_64BIT)
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1326 i386_print_statistics (FILE *file)
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1334 /* Debugging routines for md_assemble. */
1335 static void pte (template *);
1336 static void pt (unsigned int);
1337 static void pe (expressionS *);
1338 static void ps (symbolS *);
1341 pi (char *line, i386_insn *x)
1345 fprintf (stdout, "%s: template ", line);
1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1352 x->rm.mode, x->rm.reg, x->rm.regmem);
1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1356 (x->rex & REX_MODE64) != 0,
1357 (x->rex & REX_EXTX) != 0,
1358 (x->rex & REX_EXTY) != 0,
1359 (x->rex & REX_EXTZ) != 0);
1360 for (i = 0; i < x->operands; i++)
1362 fprintf (stdout, " #%d: ", i + 1);
1364 fprintf (stdout, "\n");
1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1368 if (x->types[i] & Imm)
1370 if (x->types[i] & Disp)
1371 pe (x->op[i].disps);
1379 fprintf (stdout, " %d operands ", t->operands);
1380 fprintf (stdout, "opcode %x ", t->base_opcode);
1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1399 fprintf (stdout, " operation %d\n", e->X_op);
1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
1402 if (e->X_add_symbol)
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1419 fprintf (stdout, "%s type %s%s",
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1425 static struct type_name
1430 const type_names[] =
1443 { BaseIndex, "BaseIndex" },
1447 { Disp32S, "d32s" },
1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1459 { JumpAbsolute, "Jump Absolute" },
1470 const struct type_name *ty;
1472 for (ty = type_names; ty->mask; ty++)
1474 fprintf (stdout, "%s, ", ty->tname);
1478 #endif /* DEBUG386 */
1480 static bfd_reloc_code_real_type
1481 reloc (unsigned int size,
1484 bfd_reloc_code_real_type other)
1486 if (other != NO_RELOC)
1488 reloc_howto_type *reloc;
1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
1532 as_bad (_("relocated field and relocation type differ in signedness"));
1541 as_bad (_("there are no unsigned pc-relative relocations"));
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
1547 case 8: return BFD_RELOC_64_PCREL;
1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1556 case 4: return BFD_RELOC_X86_64_32S;
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
1571 return BFD_RELOC_NONE;
1574 /* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1580 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
1582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1599 /* adjust_reloc_syms doesn't know about the GOT. */
1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1634 intel_float_operand (const char *mnemonic)
1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1643 switch (mnemonic[1])
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1649 return 2 /* integer op */;
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1667 switch (mnemonic[3])
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1686 /* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1695 char mnemonic[MAX_MNEM_SIZE];
1697 /* Initialize globals. */
1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1700 i.reloc[j] = NO_RELOC;
1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
1703 save_stack_p = save_stack;
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
1707 start of a (possibly prefixed) mnemonic. */
1709 line = parse_insn (line, mnemonic);
1713 line = parse_operands (line, mnemonic);
1717 /* The order of the immediates should be reversed
1718 for 2 immediates extrq and insertq instructions */
1719 if ((i.imm_operands == 2)
1720 && ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
1723 swap_2_operands (0, 1);
1724 /* "extrq" and insertq" are the only two instructions whose operands
1725 have to be reversed even though they have two immediate operands.
1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
1737 precedes the offset, as it does when in AT&T mode. */
1740 && (strcmp (mnemonic, "bound") != 0)
1741 && (strcmp (mnemonic, "invlpga") != 0)
1742 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1748 /* Don't optimize displacement for movabs since it only takes 64bit
1751 && (flag_code != CODE_64BIT
1752 || strcmp (mnemonic, "movabs") != 0))
1755 /* Next, we find a template that matches the given insn,
1756 making sure the overlap of the given operands types is consistent
1757 with the template operand types. */
1759 if (!match_template ())
1764 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1766 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1767 i.tm.base_opcode ^= FloatR;
1769 /* Zap movzx and movsx suffix. The suffix may have been set from
1770 "word ptr" or "byte ptr" on the source operand, but we'll use
1771 the suffix later to choose the destination register. */
1772 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1774 if (i.reg_operands < 2
1776 && (~i.tm.opcode_modifier
1783 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1789 if (i.tm.opcode_modifier & FWait)
1790 if (!add_prefix (FWAIT_OPCODE))
1793 /* Check string instruction segment overrides. */
1794 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1796 if (!check_string ())
1800 if (!process_suffix ())
1803 /* Make still unresolved immediate matches conform to size of immediate
1804 given in i.suffix. */
1805 if (!finalize_imm ())
1808 if (i.types[0] & Imm1)
1809 i.imm_operands = 0; /* kludge for shift insns. */
1810 if (i.types[0] & ImplicitRegister)
1812 if (i.types[1] & ImplicitRegister)
1814 if (i.types[2] & ImplicitRegister)
1817 if (i.tm.opcode_modifier & ImmExt)
1821 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1823 /* Streaming SIMD extensions 3 Instructions have the fixed
1824 operands with an opcode suffix which is coded in the same
1825 place as an 8-bit immediate field would be. Here we check
1826 those operands and remove them afterwards. */
1829 for (x = 0; x < i.operands; x++)
1830 if (i.op[x].regs->reg_num != x)
1831 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1832 i.op[x].regs->reg_name, x + 1, i.tm.name);
1836 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1837 opcode suffix which is coded in the same place as an 8-bit
1838 immediate field would be. Here we fake an 8-bit immediate
1839 operand from the opcode suffix stored in tm.extension_opcode. */
1841 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1843 exp = &im_expressions[i.imm_operands++];
1844 i.op[i.operands].imms = exp;
1845 i.types[i.operands++] = Imm8;
1846 exp->X_op = O_constant;
1847 exp->X_add_number = i.tm.extension_opcode;
1848 i.tm.extension_opcode = None;
1851 /* For insns with operands there are more diddles to do to the opcode. */
1854 if (!process_operands ())
1857 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1859 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1860 as_warn (_("translating to `%sp'"), i.tm.name);
1863 /* Handle conversion of 'int $3' --> special int3 insn. */
1864 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1866 i.tm.base_opcode = INT3_OPCODE;
1870 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1871 && i.op[0].disps->X_op == O_constant)
1873 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1874 the absolute address given by the constant. Since ix86 jumps and
1875 calls are pc relative, we need to generate a reloc. */
1876 i.op[0].disps->X_add_symbol = &abs_symbol;
1877 i.op[0].disps->X_op = O_symbol;
1880 if ((i.tm.opcode_modifier & Rex64) != 0)
1881 i.rex |= REX_MODE64;
1883 /* For 8 bit registers we need an empty rex prefix. Also if the
1884 instruction already has a prefix, we need to convert old
1885 registers to new ones. */
1887 if (((i.types[0] & Reg8) != 0
1888 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1889 || ((i.types[1] & Reg8) != 0
1890 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1891 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1896 i.rex |= REX_OPCODE;
1897 for (x = 0; x < 2; x++)
1899 /* Look for 8 bit operand that uses old registers. */
1900 if ((i.types[x] & Reg8) != 0
1901 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1903 /* In case it is "hi" register, give up. */
1904 if (i.op[x].regs->reg_num > 3)
1905 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1906 i.op[x].regs->reg_name);
1908 /* Otherwise it is equivalent to the extended register.
1909 Since the encoding doesn't change this is merely
1910 cosmetic cleanup for debug output. */
1912 i.op[x].regs = i.op[x].regs + 8;
1918 add_prefix (REX_OPCODE | i.rex);
1920 /* We are ready to output the insn. */
1925 parse_insn (char *line, char *mnemonic)
1928 char *token_start = l;
1933 /* Non-zero if we found a prefix only acceptable with string insns. */
1934 const char *expecting_string_instruction = NULL;
1939 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1942 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1944 as_bad (_("no such instruction: `%s'"), token_start);
1949 if (!is_space_char (*l)
1950 && *l != END_OF_INSN
1952 || (*l != PREFIX_SEPARATOR
1955 as_bad (_("invalid character %s in mnemonic"),
1956 output_invalid (*l));
1959 if (token_start == l)
1961 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1962 as_bad (_("expecting prefix; got nothing"));
1964 as_bad (_("expecting mnemonic; got nothing"));
1968 /* Look up instruction (or prefix) via hash table. */
1969 current_templates = hash_find (op_hash, mnemonic);
1971 if (*l != END_OF_INSN
1972 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1973 && current_templates
1974 && (current_templates->start->opcode_modifier & IsPrefix))
1976 if (current_templates->start->cpu_flags
1977 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1979 as_bad ((flag_code != CODE_64BIT
1980 ? _("`%s' is only supported in 64-bit mode")
1981 : _("`%s' is not supported in 64-bit mode")),
1982 current_templates->start->name);
1985 /* If we are in 16-bit mode, do not allow addr16 or data16.
1986 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1987 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1988 && flag_code != CODE_64BIT
1989 && (((current_templates->start->opcode_modifier & Size32) != 0)
1990 ^ (flag_code == CODE_16BIT)))
1992 as_bad (_("redundant %s prefix"),
1993 current_templates->start->name);
1996 /* Add prefix, checking for repeated prefixes. */
1997 switch (add_prefix (current_templates->start->base_opcode))
2002 expecting_string_instruction = current_templates->start->name;
2005 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2012 if (!current_templates)
2014 /* See if we can get a match by trimming off a suffix. */
2017 case WORD_MNEM_SUFFIX:
2018 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2019 i.suffix = SHORT_MNEM_SUFFIX;
2021 case BYTE_MNEM_SUFFIX:
2022 case QWORD_MNEM_SUFFIX:
2023 i.suffix = mnem_p[-1];
2025 current_templates = hash_find (op_hash, mnemonic);
2027 case SHORT_MNEM_SUFFIX:
2028 case LONG_MNEM_SUFFIX:
2031 i.suffix = mnem_p[-1];
2033 current_templates = hash_find (op_hash, mnemonic);
2041 if (intel_float_operand (mnemonic) == 1)
2042 i.suffix = SHORT_MNEM_SUFFIX;
2044 i.suffix = LONG_MNEM_SUFFIX;
2046 current_templates = hash_find (op_hash, mnemonic);
2050 if (!current_templates)
2052 as_bad (_("no such instruction: `%s'"), token_start);
2057 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2059 /* Check for a branch hint. We allow ",pt" and ",pn" for
2060 predict taken and predict not taken respectively.
2061 I'm not sure that branch hints actually do anything on loop
2062 and jcxz insns (JumpByte) for current Pentium4 chips. They
2063 may work in the future and it doesn't hurt to accept them
2065 if (l[0] == ',' && l[1] == 'p')
2069 if (!add_prefix (DS_PREFIX_OPCODE))
2073 else if (l[2] == 'n')
2075 if (!add_prefix (CS_PREFIX_OPCODE))
2081 /* Any other comma loses. */
2084 as_bad (_("invalid character %s in mnemonic"),
2085 output_invalid (*l));
2089 /* Check if instruction is supported on specified architecture. */
2091 for (t = current_templates->start; t < current_templates->end; ++t)
2093 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2094 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2096 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2099 if (!(supported & 2))
2101 as_bad (flag_code == CODE_64BIT
2102 ? _("`%s' is not supported in 64-bit mode")
2103 : _("`%s' is only supported in 64-bit mode"),
2104 current_templates->start->name);
2107 if (!(supported & 1))
2109 as_warn (_("`%s' is not supported on `%s%s'"),
2110 current_templates->start->name,
2112 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2114 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2116 as_warn (_("use .code16 to ensure correct addressing mode"));
2119 /* Check for rep/repne without a string instruction. */
2120 if (expecting_string_instruction)
2122 static templates override;
2124 for (t = current_templates->start; t < current_templates->end; ++t)
2125 if (t->opcode_modifier & IsString)
2127 if (t >= current_templates->end)
2129 as_bad (_("expecting string instruction after `%s'"),
2130 expecting_string_instruction);
2133 for (override.start = t; t < current_templates->end; ++t)
2134 if (!(t->opcode_modifier & IsString))
2137 current_templates = &override;
2144 parse_operands (char *l, const char *mnemonic)
2148 /* 1 if operand is pending after ','. */
2149 unsigned int expecting_operand = 0;
2151 /* Non-zero if operand parens not balanced. */
2152 unsigned int paren_not_balanced;
2154 while (*l != END_OF_INSN)
2156 /* Skip optional white space before operand. */
2157 if (is_space_char (*l))
2159 if (!is_operand_char (*l) && *l != END_OF_INSN)
2161 as_bad (_("invalid character %s before operand %d"),
2162 output_invalid (*l),
2166 token_start = l; /* after white space */
2167 paren_not_balanced = 0;
2168 while (paren_not_balanced || *l != ',')
2170 if (*l == END_OF_INSN)
2172 if (paren_not_balanced)
2175 as_bad (_("unbalanced parenthesis in operand %d."),
2178 as_bad (_("unbalanced brackets in operand %d."),
2183 break; /* we are done */
2185 else if (!is_operand_char (*l) && !is_space_char (*l))
2187 as_bad (_("invalid character %s in operand %d"),
2188 output_invalid (*l),
2195 ++paren_not_balanced;
2197 --paren_not_balanced;
2202 ++paren_not_balanced;
2204 --paren_not_balanced;
2208 if (l != token_start)
2209 { /* Yes, we've read in another operand. */
2210 unsigned int operand_ok;
2211 this_operand = i.operands++;
2212 if (i.operands > MAX_OPERANDS)
2214 as_bad (_("spurious operands; (%d operands/instruction max)"),
2218 /* Now parse operand adding info to 'i' as we go along. */
2219 END_STRING_AND_SAVE (l);
2223 i386_intel_operand (token_start,
2224 intel_float_operand (mnemonic));
2226 operand_ok = i386_operand (token_start);
2228 RESTORE_END_STRING (l);
2234 if (expecting_operand)
2236 expecting_operand_after_comma:
2237 as_bad (_("expecting operand after ','; got nothing"));
2242 as_bad (_("expecting operand before ','; got nothing"));
2247 /* Now *l must be either ',' or END_OF_INSN. */
2250 if (*++l == END_OF_INSN)
2252 /* Just skip it, if it's \n complain. */
2253 goto expecting_operand_after_comma;
2255 expecting_operand = 1;
2262 swap_2_operands (int xchg1, int xchg2)
2264 union i386_op temp_op;
2265 unsigned int temp_type;
2266 enum bfd_reloc_code_real temp_reloc;
2268 temp_type = i.types[xchg2];
2269 i.types[xchg2] = i.types[xchg1];
2270 i.types[xchg1] = temp_type;
2271 temp_op = i.op[xchg2];
2272 i.op[xchg2] = i.op[xchg1];
2273 i.op[xchg1] = temp_op;
2274 temp_reloc = i.reloc[xchg2];
2275 i.reloc[xchg2] = i.reloc[xchg1];
2276 i.reloc[xchg1] = temp_reloc;
2280 swap_operands (void)
2285 swap_2_operands (1, i.operands - 2);
2288 swap_2_operands (0, i.operands - 1);
2294 if (i.mem_operands == 2)
2296 const seg_entry *temp_seg;
2297 temp_seg = i.seg[0];
2298 i.seg[0] = i.seg[1];
2299 i.seg[1] = temp_seg;
2303 /* Try to ensure constant immediates are represented in the smallest
2308 char guess_suffix = 0;
2312 guess_suffix = i.suffix;
2313 else if (i.reg_operands)
2315 /* Figure out a suffix from the last register operand specified.
2316 We can't do this properly yet, ie. excluding InOutPortReg,
2317 but the following works for instructions with immediates.
2318 In any case, we can't set i.suffix yet. */
2319 for (op = i.operands; --op >= 0;)
2320 if (i.types[op] & Reg)
2322 if (i.types[op] & Reg8)
2323 guess_suffix = BYTE_MNEM_SUFFIX;
2324 else if (i.types[op] & Reg16)
2325 guess_suffix = WORD_MNEM_SUFFIX;
2326 else if (i.types[op] & Reg32)
2327 guess_suffix = LONG_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg64)
2329 guess_suffix = QWORD_MNEM_SUFFIX;
2333 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2334 guess_suffix = WORD_MNEM_SUFFIX;
2336 for (op = i.operands; --op >= 0;)
2337 if (i.types[op] & Imm)
2339 switch (i.op[op].imms->X_op)
2342 /* If a suffix is given, this operand may be shortened. */
2343 switch (guess_suffix)
2345 case LONG_MNEM_SUFFIX:
2346 i.types[op] |= Imm32 | Imm64;
2348 case WORD_MNEM_SUFFIX:
2349 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2351 case BYTE_MNEM_SUFFIX:
2352 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2356 /* If this operand is at most 16 bits, convert it
2357 to a signed 16 bit number before trying to see
2358 whether it will fit in an even smaller size.
2359 This allows a 16-bit operand such as $0xffe0 to
2360 be recognised as within Imm8S range. */
2361 if ((i.types[op] & Imm16)
2362 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2364 i.op[op].imms->X_add_number =
2365 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2367 if ((i.types[op] & Imm32)
2368 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2371 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2372 ^ ((offsetT) 1 << 31))
2373 - ((offsetT) 1 << 31));
2375 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2377 /* We must avoid matching of Imm32 templates when 64bit
2378 only immediate is available. */
2379 if (guess_suffix == QWORD_MNEM_SUFFIX)
2380 i.types[op] &= ~Imm32;
2387 /* Symbols and expressions. */
2389 /* Convert symbolic operand to proper sizes for matching, but don't
2390 prevent matching a set of insns that only supports sizes other
2391 than those matching the insn suffix. */
2393 unsigned int mask, allowed = 0;
2396 for (t = current_templates->start; t < current_templates->end; ++t)
2397 allowed |= t->operand_types[op];
2398 switch (guess_suffix)
2400 case QWORD_MNEM_SUFFIX:
2401 mask = Imm64 | Imm32S;
2403 case LONG_MNEM_SUFFIX:
2406 case WORD_MNEM_SUFFIX:
2409 case BYTE_MNEM_SUFFIX:
2417 i.types[op] &= mask;
2424 /* Try to use the smallest displacement type too. */
2426 optimize_disp (void)
2430 for (op = i.operands; --op >= 0;)
2431 if (i.types[op] & Disp)
2433 if (i.op[op].disps->X_op == O_constant)
2435 offsetT disp = i.op[op].disps->X_add_number;
2437 if ((i.types[op] & Disp16)
2438 && (disp & ~(offsetT) 0xffff) == 0)
2440 /* If this operand is at most 16 bits, convert
2441 to a signed 16 bit number and don't use 64bit
2443 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2444 i.types[op] &= ~Disp64;
2446 if ((i.types[op] & Disp32)
2447 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2449 /* If this operand is at most 32 bits, convert
2450 to a signed 32 bit number and don't use 64bit
2452 disp &= (((offsetT) 2 << 31) - 1);
2453 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2454 i.types[op] &= ~Disp64;
2456 if (!disp && (i.types[op] & BaseIndex))
2458 i.types[op] &= ~Disp;
2462 else if (flag_code == CODE_64BIT)
2464 if (fits_in_signed_long (disp))
2466 i.types[op] &= ~Disp64;
2467 i.types[op] |= Disp32S;
2469 if (fits_in_unsigned_long (disp))
2470 i.types[op] |= Disp32;
2472 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2473 && fits_in_signed_byte (disp))
2474 i.types[op] |= Disp8;
2476 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2477 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2479 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2480 i.op[op].disps, 0, i.reloc[op]);
2481 i.types[op] &= ~Disp;
2484 /* We only support 64bit displacement on constants. */
2485 i.types[op] &= ~Disp64;
2490 match_template (void)
2492 /* Points to template once we've found it. */
2494 unsigned int overlap0, overlap1, overlap2, overlap3;
2495 unsigned int found_reverse_match;
2497 unsigned int operand_types [MAX_OPERANDS];
2498 int addr_prefix_disp;
2501 #if MAX_OPERANDS != 4
2502 # error "MAX_OPERANDS must be 4."
2505 #define MATCH(overlap, given, template) \
2506 ((overlap & ~JumpAbsolute) \
2507 && (((given) & (BaseIndex | JumpAbsolute)) \
2508 == ((overlap) & (BaseIndex | JumpAbsolute))))
2510 /* If given types r0 and r1 are registers they must be of the same type
2511 unless the expected operand type register overlap is null.
2512 Note that Acc in a template matches every size of reg. */
2513 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2514 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2515 || ((g0) & Reg) == ((g1) & Reg) \
2516 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2522 found_reverse_match = 0;
2523 for (j = 0; j < MAX_OPERANDS; j++)
2524 operand_types [j] = 0;
2525 addr_prefix_disp = -1;
2526 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2528 : (i.suffix == WORD_MNEM_SUFFIX
2530 : (i.suffix == SHORT_MNEM_SUFFIX
2532 : (i.suffix == LONG_MNEM_SUFFIX
2534 : (i.suffix == QWORD_MNEM_SUFFIX
2536 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2537 ? No_xSuf : 0))))));
2539 for (t = current_templates->start; t < current_templates->end; t++)
2541 addr_prefix_disp = -1;
2543 /* Must have right number of operands. */
2544 if (i.operands != t->operands)
2547 /* Check the suffix, except for some instructions in intel mode. */
2548 if ((t->opcode_modifier & suffix_check)
2550 && (t->opcode_modifier & IgnoreSize)))
2553 for (j = 0; j < MAX_OPERANDS; j++)
2554 operand_types [j] = t->operand_types [j];
2556 /* In general, don't allow 64-bit operands in 32-bit mode. */
2557 if (i.suffix == QWORD_MNEM_SUFFIX
2558 && flag_code != CODE_64BIT
2560 ? (!(t->opcode_modifier & IgnoreSize)
2561 && !intel_float_operand (t->name))
2562 : intel_float_operand (t->name) != 2)
2563 && (!(operand_types[0] & (RegMMX | RegXMM))
2564 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2565 && (t->base_opcode != 0x0fc7
2566 || t->extension_opcode != 1 /* cmpxchg8b */))
2569 /* Do not verify operands when there are none. */
2570 else if (!t->operands)
2572 if (t->cpu_flags & ~cpu_arch_flags)
2574 /* We've found a match; break out of loop. */
2578 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2579 into Disp32/Disp16/Disp32 operand. */
2580 if (i.prefix[ADDR_PREFIX] != 0)
2582 unsigned int DispOn = 0, DispOff = 0;
2600 for (j = 0; j < MAX_OPERANDS; j++)
2602 /* There should be only one Disp operand. */
2603 if ((operand_types[j] & DispOff))
2605 addr_prefix_disp = j;
2606 operand_types[j] |= DispOn;
2607 operand_types[j] &= ~DispOff;
2613 overlap0 = i.types[0] & operand_types[0];
2614 switch (t->operands)
2617 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2623 overlap1 = i.types[1] & operand_types[1];
2624 if (!MATCH (overlap0, i.types[0], operand_types[0])
2625 || !MATCH (overlap1, i.types[1], operand_types[1])
2626 /* monitor in SSE3 is a very special case. The first
2627 register and the second register may have different
2629 || !((t->base_opcode == 0x0f01
2630 && t->extension_opcode == 0xc8)
2631 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2633 overlap1, i.types[1],
2636 /* Check if other direction is valid ... */
2637 if ((t->opcode_modifier & (D | FloatD)) == 0)
2640 /* Try reversing direction of operands. */
2641 overlap0 = i.types[0] & operand_types[1];
2642 overlap1 = i.types[1] & operand_types[0];
2643 if (!MATCH (overlap0, i.types[0], operand_types[1])
2644 || !MATCH (overlap1, i.types[1], operand_types[0])
2645 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2647 overlap1, i.types[1],
2650 /* Does not match either direction. */
2653 /* found_reverse_match holds which of D or FloatDR
2655 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2659 /* Found a forward 2 operand match here. */
2660 switch (t->operands)
2663 overlap3 = i.types[3] & operand_types[3];
2665 overlap2 = i.types[2] & operand_types[2];
2669 switch (t->operands)
2672 if (!MATCH (overlap3, i.types[3], operand_types[3])
2673 || !CONSISTENT_REGISTER_MATCH (overlap2,
2681 /* Here we make use of the fact that there are no
2682 reverse match 3 operand instructions, and all 3
2683 operand instructions only need to be checked for
2684 register consistency between operands 2 and 3. */
2685 if (!MATCH (overlap2, i.types[2], operand_types[2])
2686 || !CONSISTENT_REGISTER_MATCH (overlap1,
2696 /* Found either forward/reverse 2, 3 or 4 operand match here:
2697 slip through to break. */
2699 if (t->cpu_flags & ~cpu_arch_flags)
2701 found_reverse_match = 0;
2704 /* We've found a match; break out of loop. */
2708 if (t == current_templates->end)
2710 /* We found no match. */
2711 as_bad (_("suffix or operands invalid for `%s'"),
2712 current_templates->start->name);
2716 if (!quiet_warnings)
2719 && ((i.types[0] & JumpAbsolute)
2720 != (operand_types[0] & JumpAbsolute)))
2722 as_warn (_("indirect %s without `*'"), t->name);
2725 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2726 == (IsPrefix | IgnoreSize))
2728 /* Warn them that a data or address size prefix doesn't
2729 affect assembly of the next line of code. */
2730 as_warn (_("stand-alone `%s' prefix"), t->name);
2734 /* Copy the template we found. */
2737 if (addr_prefix_disp != -1)
2738 i.tm.operand_types[addr_prefix_disp]
2739 = operand_types[addr_prefix_disp];
2741 if (found_reverse_match)
2743 /* If we found a reverse match we must alter the opcode
2744 direction bit. found_reverse_match holds bits to change
2745 (different for int & float insns). */
2747 i.tm.base_opcode ^= found_reverse_match;
2749 i.tm.operand_types[0] = operand_types[1];
2750 i.tm.operand_types[1] = operand_types[0];
2759 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2760 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2762 if (i.seg[0] != NULL && i.seg[0] != &es)
2764 as_bad (_("`%s' operand %d must use `%%es' segment"),
2769 /* There's only ever one segment override allowed per instruction.
2770 This instruction possibly has a legal segment override on the
2771 second operand, so copy the segment to where non-string
2772 instructions store it, allowing common code. */
2773 i.seg[0] = i.seg[1];
2775 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2777 if (i.seg[1] != NULL && i.seg[1] != &es)
2779 as_bad (_("`%s' operand %d must use `%%es' segment"),
2789 process_suffix (void)
2791 /* If matched instruction specifies an explicit instruction mnemonic
2793 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2795 if (i.tm.opcode_modifier & Size16)
2796 i.suffix = WORD_MNEM_SUFFIX;
2797 else if (i.tm.opcode_modifier & Size64)
2798 i.suffix = QWORD_MNEM_SUFFIX;
2800 i.suffix = LONG_MNEM_SUFFIX;
2802 else if (i.reg_operands)
2804 /* If there's no instruction mnemonic suffix we try to invent one
2805 based on register operands. */
2808 /* We take i.suffix from the last register operand specified,
2809 Destination register type is more significant than source
2813 for (op = i.operands; --op >= 0;)
2814 if ((i.types[op] & Reg)
2815 && !(i.tm.operand_types[op] & InOutPortReg))
2817 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2818 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2819 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2824 else if (i.suffix == BYTE_MNEM_SUFFIX)
2826 if (!check_byte_reg ())
2829 else if (i.suffix == LONG_MNEM_SUFFIX)
2831 if (!check_long_reg ())
2834 else if (i.suffix == QWORD_MNEM_SUFFIX)
2836 if (!check_qword_reg ())
2839 else if (i.suffix == WORD_MNEM_SUFFIX)
2841 if (!check_word_reg ())
2844 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2845 /* Do nothing if the instruction is going to ignore the prefix. */
2850 else if ((i.tm.opcode_modifier & DefaultSize)
2852 /* exclude fldenv/frstor/fsave/fstenv */
2853 && (i.tm.opcode_modifier & No_sSuf))
2855 i.suffix = stackop_size;
2857 else if (intel_syntax
2859 && ((i.tm.operand_types[0] & JumpAbsolute)
2860 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2861 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2862 && i.tm.extension_opcode <= 3)))
2867 if (!(i.tm.opcode_modifier & No_qSuf))
2869 i.suffix = QWORD_MNEM_SUFFIX;
2873 if (!(i.tm.opcode_modifier & No_lSuf))
2874 i.suffix = LONG_MNEM_SUFFIX;
2877 if (!(i.tm.opcode_modifier & No_wSuf))
2878 i.suffix = WORD_MNEM_SUFFIX;
2887 if (i.tm.opcode_modifier & W)
2889 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2895 unsigned int suffixes = (~i.tm.opcode_modifier
2903 if ((i.tm.opcode_modifier & W)
2904 || ((suffixes & (suffixes - 1))
2905 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2907 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2913 /* Change the opcode based on the operand size given by i.suffix;
2914 We don't need to change things for byte insns. */
2916 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2918 /* It's not a byte, select word/dword operation. */
2919 if (i.tm.opcode_modifier & W)
2921 if (i.tm.opcode_modifier & ShortForm)
2922 i.tm.base_opcode |= 8;
2924 i.tm.base_opcode |= 1;
2927 /* Now select between word & dword operations via the operand
2928 size prefix, except for instructions that will ignore this
2930 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2932 /* monitor in SSE3 is a very special case. The default size
2933 of AX is the size of mode. The address size override
2934 prefix will change the size of AX. */
2935 if (i.op->regs[0].reg_type &
2936 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2937 if (!add_prefix (ADDR_PREFIX_OPCODE))
2940 else if (i.suffix != QWORD_MNEM_SUFFIX
2941 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2942 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2944 || (flag_code == CODE_64BIT
2945 && (i.tm.opcode_modifier & JumpByte))))
2947 unsigned int prefix = DATA_PREFIX_OPCODE;
2949 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2950 prefix = ADDR_PREFIX_OPCODE;
2952 if (!add_prefix (prefix))
2956 /* Set mode64 for an operand. */
2957 if (i.suffix == QWORD_MNEM_SUFFIX
2958 && flag_code == CODE_64BIT
2959 && (i.tm.opcode_modifier & NoRex64) == 0)
2961 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2964 || i.types [0] != (Acc | Reg64)
2965 || i.types [1] != (Acc | Reg64)
2966 || strcmp (i.tm.name, "xchg") != 0)
2967 i.rex |= REX_MODE64;
2970 /* Size floating point instruction. */
2971 if (i.suffix == LONG_MNEM_SUFFIX)
2972 if (i.tm.opcode_modifier & FloatMF)
2973 i.tm.base_opcode ^= 4;
2980 check_byte_reg (void)
2984 for (op = i.operands; --op >= 0;)
2986 /* If this is an eight bit register, it's OK. If it's the 16 or
2987 32 bit version of an eight bit register, we will just use the
2988 low portion, and that's OK too. */
2989 if (i.types[op] & Reg8)
2992 /* movzx and movsx should not generate this warning. */
2994 && (i.tm.base_opcode == 0xfb7
2995 || i.tm.base_opcode == 0xfb6
2996 || i.tm.base_opcode == 0x63
2997 || i.tm.base_opcode == 0xfbe
2998 || i.tm.base_opcode == 0xfbf))
3001 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3003 /* Prohibit these changes in the 64bit mode, since the
3004 lowering is more complicated. */
3005 if (flag_code == CODE_64BIT
3006 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3008 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3009 register_prefix, i.op[op].regs->reg_name,
3013 #if REGISTER_WARNINGS
3015 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3016 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3017 (i.op[op].regs + (i.types[op] & Reg16
3018 ? REGNAM_AL - REGNAM_AX
3019 : REGNAM_AL - REGNAM_EAX))->reg_name,
3020 i.op[op].regs->reg_name,
3025 /* Any other register is bad. */
3026 if (i.types[op] & (Reg | RegMMX | RegXMM
3028 | Control | Debug | Test
3029 | FloatReg | FloatAcc))
3031 as_bad (_("`%%%s' not allowed with `%s%c'"),
3032 i.op[op].regs->reg_name,
3042 check_long_reg (void)
3046 for (op = i.operands; --op >= 0;)
3047 /* Reject eight bit registers, except where the template requires
3048 them. (eg. movzb) */
3049 if ((i.types[op] & Reg8) != 0
3050 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3052 as_bad (_("`%%%s' not allowed with `%s%c'"),
3053 i.op[op].regs->reg_name,
3058 /* Warn if the e prefix on a general reg is missing. */
3059 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3060 && (i.types[op] & Reg16) != 0
3061 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3063 /* Prohibit these changes in the 64bit mode, since the
3064 lowering is more complicated. */
3065 if (flag_code == CODE_64BIT)
3067 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3068 register_prefix, i.op[op].regs->reg_name,
3072 #if REGISTER_WARNINGS
3074 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3075 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3076 i.op[op].regs->reg_name,
3080 /* Warn if the r prefix on a general reg is missing. */
3081 else if ((i.types[op] & Reg64) != 0
3082 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3084 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3085 register_prefix, i.op[op].regs->reg_name,
3093 check_qword_reg (void)
3097 for (op = i.operands; --op >= 0; )
3098 /* Reject eight bit registers, except where the template requires
3099 them. (eg. movzb) */
3100 if ((i.types[op] & Reg8) != 0
3101 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3103 as_bad (_("`%%%s' not allowed with `%s%c'"),
3104 i.op[op].regs->reg_name,
3109 /* Warn if the e prefix on a general reg is missing. */
3110 else if (((i.types[op] & Reg16) != 0
3111 || (i.types[op] & Reg32) != 0)
3112 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3114 /* Prohibit these changes in the 64bit mode, since the
3115 lowering is more complicated. */
3116 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3117 register_prefix, i.op[op].regs->reg_name,
3125 check_word_reg (void)
3128 for (op = i.operands; --op >= 0;)
3129 /* Reject eight bit registers, except where the template requires
3130 them. (eg. movzb) */
3131 if ((i.types[op] & Reg8) != 0
3132 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3134 as_bad (_("`%%%s' not allowed with `%s%c'"),
3135 i.op[op].regs->reg_name,
3140 /* Warn if the e prefix on a general reg is present. */
3141 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3142 && (i.types[op] & Reg32) != 0
3143 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3145 /* Prohibit these changes in the 64bit mode, since the
3146 lowering is more complicated. */
3147 if (flag_code == CODE_64BIT)
3149 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3150 register_prefix, i.op[op].regs->reg_name,
3155 #if REGISTER_WARNINGS
3156 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3157 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3158 i.op[op].regs->reg_name,
3168 unsigned int overlap0, overlap1, overlap2;
3170 overlap0 = i.types[0] & i.tm.operand_types[0];
3171 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3172 && overlap0 != Imm8 && overlap0 != Imm8S
3173 && overlap0 != Imm16 && overlap0 != Imm32S
3174 && overlap0 != Imm32 && overlap0 != Imm64)
3178 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3180 : (i.suffix == WORD_MNEM_SUFFIX
3182 : (i.suffix == QWORD_MNEM_SUFFIX
3186 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3187 || overlap0 == (Imm16 | Imm32)
3188 || overlap0 == (Imm16 | Imm32S))
3190 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3193 if (overlap0 != Imm8 && overlap0 != Imm8S
3194 && overlap0 != Imm16 && overlap0 != Imm32S
3195 && overlap0 != Imm32 && overlap0 != Imm64)
3197 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3201 i.types[0] = overlap0;
3203 overlap1 = i.types[1] & i.tm.operand_types[1];
3204 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3205 && overlap1 != Imm8 && overlap1 != Imm8S
3206 && overlap1 != Imm16 && overlap1 != Imm32S
3207 && overlap1 != Imm32 && overlap1 != Imm64)
3211 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3213 : (i.suffix == WORD_MNEM_SUFFIX
3215 : (i.suffix == QWORD_MNEM_SUFFIX
3219 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3220 || overlap1 == (Imm16 | Imm32)
3221 || overlap1 == (Imm16 | Imm32S))
3223 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3226 if (overlap1 != Imm8 && overlap1 != Imm8S
3227 && overlap1 != Imm16 && overlap1 != Imm32S
3228 && overlap1 != Imm32 && overlap1 != Imm64)
3230 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3234 i.types[1] = overlap1;
3236 overlap2 = i.types[2] & i.tm.operand_types[2];
3237 assert ((overlap2 & Imm) == 0);
3238 i.types[2] = overlap2;
3244 process_operands (void)
3246 /* Default segment register this instruction will use for memory
3247 accesses. 0 means unknown. This is only for optimizing out
3248 unnecessary segment overrides. */
3249 const seg_entry *default_seg = 0;
3251 /* The imul $imm, %reg instruction is converted into
3252 imul $imm, %reg, %reg, and the clr %reg instruction
3253 is converted into xor %reg, %reg. */
3254 if (i.tm.opcode_modifier & regKludge)
3256 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3257 /* Pretend we saw the extra register operand. */
3258 assert (i.reg_operands == 1
3259 && i.op[first_reg_op + 1].regs == 0);
3260 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3261 i.types[first_reg_op + 1] = i.types[first_reg_op];
3266 if (i.tm.opcode_modifier & ShortForm)
3268 /* The register or float register operand is in operand 0 or 1. */
3269 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3270 /* Register goes in low 3 bits of opcode. */
3271 i.tm.base_opcode |= i.op[op].regs->reg_num;
3272 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3274 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3276 /* Warn about some common errors, but press on regardless.
3277 The first case can be generated by gcc (<= 2.8.1). */
3278 if (i.operands == 2)
3280 /* Reversed arguments on faddp, fsubp, etc. */
3281 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3282 i.op[1].regs->reg_name,
3283 i.op[0].regs->reg_name);
3287 /* Extraneous `l' suffix on fp insn. */
3288 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3289 i.op[0].regs->reg_name);
3293 else if (i.tm.opcode_modifier & Modrm)
3295 /* The opcode is completed (modulo i.tm.extension_opcode which
3296 must be put into the modrm byte). Now, we make the modrm and
3297 index base bytes based on all the info we've collected. */
3299 default_seg = build_modrm_byte ();
3301 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3303 if (i.tm.base_opcode == POP_SEG_SHORT
3304 && i.op[0].regs->reg_num == 1)
3306 as_bad (_("you can't `pop %%cs'"));
3309 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3310 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3313 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3317 else if ((i.tm.opcode_modifier & IsString) != 0)
3319 /* For the string instructions that allow a segment override
3320 on one of their operands, the default segment is ds. */
3324 if ((i.tm.base_opcode == 0x8d /* lea */
3325 || (i.tm.cpu_flags & CpuSVME))
3326 && i.seg[0] && !quiet_warnings)
3327 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3329 /* If a segment was explicitly specified, and the specified segment
3330 is not the default, use an opcode prefix to select it. If we
3331 never figured out what the default segment is, then default_seg
3332 will be zero at this point, and the specified segment prefix will
3334 if ((i.seg[0]) && (i.seg[0] != default_seg))
3336 if (!add_prefix (i.seg[0]->seg_prefix))
3342 static const seg_entry *
3343 build_modrm_byte (void)
3345 const seg_entry *default_seg = 0;
3347 /* i.reg_operands MUST be the number of real register operands;
3348 implicit registers do not count. */
3349 if (i.reg_operands == 2)
3351 unsigned int source, dest;
3359 /* When there are 3 operands, one of them may be immediate,
3360 which may be the first or the last operand. Otherwise,
3361 the first operand must be shift count register (cl). */
3362 assert (i.imm_operands == 1
3363 || (i.imm_operands == 0
3364 && (i.types[0] & ShiftCount)));
3365 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
3368 /* When there are 4 operands, the first two must be immediate
3369 operands. The source operand will be the 3rd one. */
3370 assert (i.imm_operands == 2
3371 && (i.types[0] & Imm)
3372 && (i.types[1] & Imm));
3382 /* One of the register operands will be encoded in the i.tm.reg
3383 field, the other in the combined i.tm.mode and i.tm.regmem
3384 fields. If no form of this instruction supports a memory
3385 destination operand, then we assume the source operand may
3386 sometimes be a memory operand and so we need to store the
3387 destination in the i.rm.reg field. */
3388 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3390 i.rm.reg = i.op[dest].regs->reg_num;
3391 i.rm.regmem = i.op[source].regs->reg_num;
3392 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3394 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3399 i.rm.reg = i.op[source].regs->reg_num;
3400 i.rm.regmem = i.op[dest].regs->reg_num;
3401 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3403 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3406 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3408 if (!((i.types[0] | i.types[1]) & Control))
3410 i.rex &= ~(REX_EXTX | REX_EXTZ);
3411 add_prefix (LOCK_PREFIX_OPCODE);
3415 { /* If it's not 2 reg operands... */
3418 unsigned int fake_zero_displacement = 0;
3421 for (op = 0; op < i.operands; op++)
3422 if ((i.types[op] & AnyMem))
3424 assert (op < i.operands);
3428 if (i.base_reg == 0)
3431 if (!i.disp_operands)
3432 fake_zero_displacement = 1;
3433 if (i.index_reg == 0)
3435 /* Operand is just <disp> */
3436 if (flag_code == CODE_64BIT)
3438 /* 64bit mode overwrites the 32bit absolute
3439 addressing by RIP relative addressing and
3440 absolute addressing is encoded by one of the
3441 redundant SIB forms. */
3442 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3443 i.sib.base = NO_BASE_REGISTER;
3444 i.sib.index = NO_INDEX_REGISTER;
3445 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3446 ? Disp32S : Disp32);
3448 else if ((flag_code == CODE_16BIT)
3449 ^ (i.prefix[ADDR_PREFIX] != 0))
3451 i.rm.regmem = NO_BASE_REGISTER_16;
3452 i.types[op] = Disp16;
3456 i.rm.regmem = NO_BASE_REGISTER;
3457 i.types[op] = Disp32;
3460 else /* !i.base_reg && i.index_reg */
3462 i.sib.index = i.index_reg->reg_num;
3463 i.sib.base = NO_BASE_REGISTER;
3464 i.sib.scale = i.log2_scale_factor;
3465 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3466 i.types[op] &= ~Disp;
3467 if (flag_code != CODE_64BIT)
3468 i.types[op] |= Disp32; /* Must be 32 bit */
3470 i.types[op] |= Disp32S;
3471 if ((i.index_reg->reg_flags & RegRex) != 0)
3475 /* RIP addressing for 64bit mode. */
3476 else if (i.base_reg->reg_type == BaseIndex)
3478 i.rm.regmem = NO_BASE_REGISTER;
3479 i.types[op] &= ~ Disp;
3480 i.types[op] |= Disp32S;
3481 i.flags[op] |= Operand_PCrel;
3482 if (! i.disp_operands)
3483 fake_zero_displacement = 1;
3485 else if (i.base_reg->reg_type & Reg16)
3487 switch (i.base_reg->reg_num)
3490 if (i.index_reg == 0)
3492 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3493 i.rm.regmem = i.index_reg->reg_num - 6;
3497 if (i.index_reg == 0)
3500 if ((i.types[op] & Disp) == 0)
3502 /* fake (%bp) into 0(%bp) */
3503 i.types[op] |= Disp8;
3504 fake_zero_displacement = 1;
3507 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3508 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3510 default: /* (%si) -> 4 or (%di) -> 5 */
3511 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3513 i.rm.mode = mode_from_disp_size (i.types[op]);
3515 else /* i.base_reg and 32/64 bit mode */
3517 if (flag_code == CODE_64BIT
3518 && (i.types[op] & Disp))
3519 i.types[op] = ((i.types[op] & Disp8)
3520 | (i.prefix[ADDR_PREFIX] == 0
3521 ? Disp32S : Disp32));
3523 i.rm.regmem = i.base_reg->reg_num;
3524 if ((i.base_reg->reg_flags & RegRex) != 0)
3526 i.sib.base = i.base_reg->reg_num;
3527 /* x86-64 ignores REX prefix bit here to avoid decoder
3529 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3532 if (i.disp_operands == 0)
3534 fake_zero_displacement = 1;
3535 i.types[op] |= Disp8;
3538 else if (i.base_reg->reg_num == ESP_REG_NUM)
3542 i.sib.scale = i.log2_scale_factor;
3543 if (i.index_reg == 0)
3545 /* <disp>(%esp) becomes two byte modrm with no index
3546 register. We've already stored the code for esp
3547 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3548 Any base register besides %esp will not use the
3549 extra modrm byte. */
3550 i.sib.index = NO_INDEX_REGISTER;
3551 #if !SCALE1_WHEN_NO_INDEX
3552 /* Another case where we force the second modrm byte. */
3553 if (i.log2_scale_factor)
3554 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3559 i.sib.index = i.index_reg->reg_num;
3560 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3561 if ((i.index_reg->reg_flags & RegRex) != 0)
3566 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3567 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3570 i.rm.mode = mode_from_disp_size (i.types[op]);
3573 if (fake_zero_displacement)
3575 /* Fakes a zero displacement assuming that i.types[op]
3576 holds the correct displacement size. */
3579 assert (i.op[op].disps == 0);
3580 exp = &disp_expressions[i.disp_operands++];
3581 i.op[op].disps = exp;
3582 exp->X_op = O_constant;
3583 exp->X_add_number = 0;
3584 exp->X_add_symbol = (symbolS *) 0;
3585 exp->X_op_symbol = (symbolS *) 0;
3589 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3590 (if any) based on i.tm.extension_opcode. Again, we must be
3591 careful to make sure that segment/control/debug/test/MMX
3592 registers are coded into the i.rm.reg field. */
3597 for (op = 0; op < i.operands; op++)
3598 if ((i.types[op] & (Reg | RegMMX | RegXMM
3600 | Control | Debug | Test)))
3602 assert (op < i.operands);
3604 /* If there is an extension opcode to put here, the register
3605 number must be put into the regmem field. */
3606 if (i.tm.extension_opcode != None)
3608 i.rm.regmem = i.op[op].regs->reg_num;
3609 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3614 i.rm.reg = i.op[op].regs->reg_num;
3615 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3619 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3620 must set it to 3 to indicate this is a register operand
3621 in the regmem field. */
3622 if (!i.mem_operands)
3626 /* Fill in i.rm.reg field with extension opcode (if any). */
3627 if (i.tm.extension_opcode != None)
3628 i.rm.reg = i.tm.extension_opcode;
3634 output_branch (void)
3639 relax_substateT subtype;
3644 if (flag_code == CODE_16BIT)
3648 if (i.prefix[DATA_PREFIX] != 0)
3654 /* Pentium4 branch hints. */
3655 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3656 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3661 if (i.prefix[REX_PREFIX] != 0)
3667 if (i.prefixes != 0 && !intel_syntax)
3668 as_warn (_("skipping prefixes on this instruction"));
3670 /* It's always a symbol; End frag & setup for relax.
3671 Make sure there is enough room in this frag for the largest
3672 instruction we may generate in md_convert_frag. This is 2
3673 bytes for the opcode and room for the prefix and largest
3675 frag_grow (prefix + 2 + 4);
3676 /* Prefix and 1 opcode byte go in fr_fix. */
3677 p = frag_more (prefix + 1);
3678 if (i.prefix[DATA_PREFIX] != 0)
3679 *p++ = DATA_PREFIX_OPCODE;
3680 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3681 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3682 *p++ = i.prefix[SEG_PREFIX];
3683 if (i.prefix[REX_PREFIX] != 0)
3684 *p++ = i.prefix[REX_PREFIX];
3685 *p = i.tm.base_opcode;
3687 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3688 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3689 else if ((cpu_arch_flags & Cpu386) != 0)
3690 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3692 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3695 sym = i.op[0].disps->X_add_symbol;
3696 off = i.op[0].disps->X_add_number;
3698 if (i.op[0].disps->X_op != O_constant
3699 && i.op[0].disps->X_op != O_symbol)
3701 /* Handle complex expressions. */
3702 sym = make_expr_symbol (i.op[0].disps);
3706 /* 1 possible extra opcode + 4 byte displacement go in var part.
3707 Pass reloc in fr_var. */
3708 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3718 if (i.tm.opcode_modifier & JumpByte)
3720 /* This is a loop or jecxz type instruction. */
3722 if (i.prefix[ADDR_PREFIX] != 0)
3724 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3727 /* Pentium4 branch hints. */
3728 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3729 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3731 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3740 if (flag_code == CODE_16BIT)
3743 if (i.prefix[DATA_PREFIX] != 0)
3745 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3755 if (i.prefix[REX_PREFIX] != 0)
3757 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3761 if (i.prefixes != 0 && !intel_syntax)
3762 as_warn (_("skipping prefixes on this instruction"));
3764 p = frag_more (1 + size);
3765 *p++ = i.tm.base_opcode;
3767 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3768 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3770 /* All jumps handled here are signed, but don't use a signed limit
3771 check for 32 and 16 bit jumps as we want to allow wrap around at
3772 4G and 64k respectively. */
3774 fixP->fx_signed = 1;
3778 output_interseg_jump (void)
3786 if (flag_code == CODE_16BIT)
3790 if (i.prefix[DATA_PREFIX] != 0)
3796 if (i.prefix[REX_PREFIX] != 0)
3806 if (i.prefixes != 0 && !intel_syntax)
3807 as_warn (_("skipping prefixes on this instruction"));
3809 /* 1 opcode; 2 segment; offset */
3810 p = frag_more (prefix + 1 + 2 + size);
3812 if (i.prefix[DATA_PREFIX] != 0)
3813 *p++ = DATA_PREFIX_OPCODE;
3815 if (i.prefix[REX_PREFIX] != 0)
3816 *p++ = i.prefix[REX_PREFIX];
3818 *p++ = i.tm.base_opcode;
3819 if (i.op[1].imms->X_op == O_constant)
3821 offsetT n = i.op[1].imms->X_add_number;
3824 && !fits_in_unsigned_word (n)
3825 && !fits_in_signed_word (n))
3827 as_bad (_("16-bit jump out of range"));
3830 md_number_to_chars (p, n, size);
3833 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3834 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3835 if (i.op[0].imms->X_op != O_constant)
3836 as_bad (_("can't handle non absolute segment in `%s'"),
3838 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3844 fragS *insn_start_frag;
3845 offsetT insn_start_off;
3847 /* Tie dwarf2 debug info to the address at the start of the insn.
3848 We can't do this after the insn has been output as the current
3849 frag may have been closed off. eg. by frag_var. */
3850 dwarf2_emit_insn (0);
3852 insn_start_frag = frag_now;
3853 insn_start_off = frag_now_fix ();
3856 if (i.tm.opcode_modifier & Jump)
3858 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3860 else if (i.tm.opcode_modifier & JumpInterSegment)
3861 output_interseg_jump ();
3864 /* Output normal instructions here. */
3867 unsigned int prefix;
3869 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3870 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3871 use one more higher byte to specify a prefix the instruction
3873 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3875 if (i.tm.base_opcode & 0xff000000)
3877 prefix = (i.tm.base_opcode >> 24) & 0xff;
3881 else if ((i.tm.base_opcode & 0xff0000) != 0)
3883 prefix = (i.tm.base_opcode >> 16) & 0xff;
3884 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3887 if (prefix != REPE_PREFIX_OPCODE
3888 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3889 add_prefix (prefix);
3892 add_prefix (prefix);
3895 /* The prefix bytes. */
3897 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3903 md_number_to_chars (p, (valueT) *q, 1);
3907 /* Now the opcode; be careful about word order here! */
3908 if (fits_in_unsigned_byte (i.tm.base_opcode))
3910 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3914 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3917 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3922 /* Put out high byte first: can't use md_number_to_chars! */
3923 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3924 *p = i.tm.base_opcode & 0xff;
3927 /* Now the modrm byte and sib byte (if present). */
3928 if (i.tm.opcode_modifier & Modrm)
3931 md_number_to_chars (p,
3932 (valueT) (i.rm.regmem << 0
3936 /* If i.rm.regmem == ESP (4)
3937 && i.rm.mode != (Register mode)
3939 ==> need second modrm byte. */
3940 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3942 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3945 md_number_to_chars (p,
3946 (valueT) (i.sib.base << 0
3948 | i.sib.scale << 6),
3953 if (i.disp_operands)
3954 output_disp (insn_start_frag, insn_start_off);
3957 output_imm (insn_start_frag, insn_start_off);
3963 pi ("" /*line*/, &i);
3965 #endif /* DEBUG386 */
3969 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
3974 for (n = 0; n < i.operands; n++)
3976 if (i.types[n] & Disp)
3978 if (i.op[n].disps->X_op == O_constant)
3984 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3987 if (i.types[n] & Disp8)
3989 if (i.types[n] & Disp64)
3992 val = offset_in_range (i.op[n].disps->X_add_number,
3994 p = frag_more (size);
3995 md_number_to_chars (p, val, size);
3999 enum bfd_reloc_code_real reloc_type;
4002 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4004 /* The PC relative address is computed relative
4005 to the instruction boundary, so in case immediate
4006 fields follows, we need to adjust the value. */
4007 if (pcrel && i.imm_operands)
4012 for (n1 = 0; n1 < i.operands; n1++)
4013 if (i.types[n1] & Imm)
4015 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4018 if (i.types[n1] & (Imm8 | Imm8S))
4020 if (i.types[n1] & Imm64)
4025 /* We should find the immediate. */
4026 if (n1 == i.operands)
4028 i.op[n].disps->X_add_number -= imm_size;
4031 if (i.types[n] & Disp32S)
4034 if (i.types[n] & (Disp16 | Disp64))
4037 if (i.types[n] & Disp64)
4041 p = frag_more (size);
4042 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4044 && GOT_symbol == i.op[n].disps->X_add_symbol
4045 && (((reloc_type == BFD_RELOC_32
4046 || reloc_type == BFD_RELOC_X86_64_32S
4047 || (reloc_type == BFD_RELOC_64
4049 && (i.op[n].disps->X_op == O_symbol
4050 || (i.op[n].disps->X_op == O_add
4051 && ((symbol_get_value_expression
4052 (i.op[n].disps->X_op_symbol)->X_op)
4054 || reloc_type == BFD_RELOC_32_PCREL))
4058 if (insn_start_frag == frag_now)
4059 add = (p - frag_now->fr_literal) - insn_start_off;
4064 add = insn_start_frag->fr_fix - insn_start_off;
4065 for (fr = insn_start_frag->fr_next;
4066 fr && fr != frag_now; fr = fr->fr_next)
4068 add += p - frag_now->fr_literal;
4073 reloc_type = BFD_RELOC_386_GOTPC;
4074 i.op[n].imms->X_add_number += add;
4076 else if (reloc_type == BFD_RELOC_64)
4077 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4079 /* Don't do the adjustment for x86-64, as there
4080 the pcrel addressing is relative to the _next_
4081 insn, and that is taken care of in other code. */
4082 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4084 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4085 i.op[n].disps, pcrel, reloc_type);
4092 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4097 for (n = 0; n < i.operands; n++)
4099 if (i.types[n] & Imm)
4101 if (i.op[n].imms->X_op == O_constant)
4107 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4110 if (i.types[n] & (Imm8 | Imm8S))
4112 else if (i.types[n] & Imm64)
4115 val = offset_in_range (i.op[n].imms->X_add_number,
4117 p = frag_more (size);
4118 md_number_to_chars (p, val, size);
4122 /* Not absolute_section.
4123 Need a 32-bit fixup (don't support 8bit
4124 non-absolute imms). Try to support other
4126 enum bfd_reloc_code_real reloc_type;
4130 if ((i.types[n] & (Imm32S))
4131 && (i.suffix == QWORD_MNEM_SUFFIX
4132 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4134 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4137 if (i.types[n] & (Imm8 | Imm8S))
4139 if (i.types[n] & Imm64)
4143 p = frag_more (size);
4144 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4146 /* This is tough to explain. We end up with this one if we
4147 * have operands that look like
4148 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4149 * obtain the absolute address of the GOT, and it is strongly
4150 * preferable from a performance point of view to avoid using
4151 * a runtime relocation for this. The actual sequence of
4152 * instructions often look something like:
4157 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4159 * The call and pop essentially return the absolute address
4160 * of the label .L66 and store it in %ebx. The linker itself
4161 * will ultimately change the first operand of the addl so
4162 * that %ebx points to the GOT, but to keep things simple, the
4163 * .o file must have this operand set so that it generates not
4164 * the absolute address of .L66, but the absolute address of
4165 * itself. This allows the linker itself simply treat a GOTPC
4166 * relocation as asking for a pcrel offset to the GOT to be
4167 * added in, and the addend of the relocation is stored in the
4168 * operand field for the instruction itself.
4170 * Our job here is to fix the operand so that it would add
4171 * the correct offset so that %ebx would point to itself. The
4172 * thing that is tricky is that .-.L66 will point to the
4173 * beginning of the instruction, so we need to further modify
4174 * the operand so that it will point to itself. There are
4175 * other cases where you have something like:
4177 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4179 * and here no correction would be required. Internally in
4180 * the assembler we treat operands of this form as not being
4181 * pcrel since the '.' is explicitly mentioned, and I wonder
4182 * whether it would simplify matters to do it this way. Who
4183 * knows. In earlier versions of the PIC patches, the
4184 * pcrel_adjust field was used to store the correction, but
4185 * since the expression is not pcrel, I felt it would be
4186 * confusing to do it this way. */
4188 if ((reloc_type == BFD_RELOC_32
4189 || reloc_type == BFD_RELOC_X86_64_32S
4190 || reloc_type == BFD_RELOC_64)
4192 && GOT_symbol == i.op[n].imms->X_add_symbol
4193 && (i.op[n].imms->X_op == O_symbol
4194 || (i.op[n].imms->X_op == O_add
4195 && ((symbol_get_value_expression
4196 (i.op[n].imms->X_op_symbol)->X_op)
4201 if (insn_start_frag == frag_now)
4202 add = (p - frag_now->fr_literal) - insn_start_off;
4207 add = insn_start_frag->fr_fix - insn_start_off;
4208 for (fr = insn_start_frag->fr_next;
4209 fr && fr != frag_now; fr = fr->fr_next)
4211 add += p - frag_now->fr_literal;
4215 reloc_type = BFD_RELOC_386_GOTPC;
4217 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4219 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4220 i.op[n].imms->X_add_number += add;
4222 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4223 i.op[n].imms, 0, reloc_type);
4229 /* x86_cons_fix_new is called via the expression parsing code when a
4230 reloc is needed. We use this hook to get the correct .got reloc. */
4231 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4232 static int cons_sign = -1;
4235 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
4238 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4240 got_reloc = NO_RELOC;
4243 if (exp->X_op == O_secrel)
4245 exp->X_op = O_symbol;
4246 r = BFD_RELOC_32_SECREL;
4250 fix_new_exp (frag, off, len, exp, 0, r);
4253 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4254 # define lex_got(reloc, adjust, types) NULL
4256 /* Parse operands of the form
4257 <symbol>@GOTOFF+<nnn>
4258 and similar .plt or .got references.
4260 If we find one, set up the correct relocation in RELOC and copy the
4261 input string, minus the `@GOTOFF' into a malloc'd buffer for
4262 parsing by the calling routine. Return this buffer, and if ADJUST
4263 is non-null set it to the length of the string we removed from the
4264 input line. Otherwise return NULL. */
4266 lex_got (enum bfd_reloc_code_real *reloc,
4268 unsigned int *types)
4270 /* Some of the relocations depend on the size of what field is to
4271 be relocated. But in our callers i386_immediate and i386_displacement
4272 we don't yet know the operand size (this will be set by insn
4273 matching). Hence we record the word32 relocation here,
4274 and adjust the reloc according to the real size in reloc(). */
4275 static const struct {
4277 const enum bfd_reloc_code_real rel[2];
4278 const unsigned int types64;
4280 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4281 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4282 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4283 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4284 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4285 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4286 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4287 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4288 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4289 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4290 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4291 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4292 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4293 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4294 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4295 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4296 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4304 for (cp = input_line_pointer; *cp != '@'; cp++)
4305 if (is_end_of_line[(unsigned char) *cp])
4308 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4312 len = strlen (gotrel[j].str);
4313 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4315 if (gotrel[j].rel[object_64bit] != 0)
4318 char *tmpbuf, *past_reloc;
4320 *reloc = gotrel[j].rel[object_64bit];
4326 if (flag_code != CODE_64BIT)
4327 *types = Imm32|Disp32;
4329 *types = gotrel[j].types64;
4332 if (GOT_symbol == NULL)
4333 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4335 /* Replace the relocation token with ' ', so that
4336 errors like foo@GOTOFF1 will be detected. */
4338 /* The length of the first part of our input line. */
4339 first = cp - input_line_pointer;
4341 /* The second part goes from after the reloc token until
4342 (and including) an end_of_line char. Don't use strlen
4343 here as the end_of_line char may not be a NUL. */
4344 past_reloc = cp + 1 + len;
4345 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4347 second = cp - past_reloc;
4349 /* Allocate and copy string. The trailing NUL shouldn't
4350 be necessary, but be safe. */
4351 tmpbuf = xmalloc (first + second + 2);
4352 memcpy (tmpbuf, input_line_pointer, first);
4353 tmpbuf[first] = ' ';
4354 memcpy (tmpbuf + first + 1, past_reloc, second);
4355 tmpbuf[first + second + 1] = '\0';
4359 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4360 gotrel[j].str, 1 << (5 + object_64bit));
4365 /* Might be a symbol version string. Don't as_bad here. */
4370 x86_cons (expressionS *exp, int size)
4372 if (size == 4 || (object_64bit && size == 8))
4374 /* Handle @GOTOFF and the like in an expression. */
4376 char *gotfree_input_line;
4379 save = input_line_pointer;
4380 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4381 if (gotfree_input_line)
4382 input_line_pointer = gotfree_input_line;
4386 if (gotfree_input_line)
4388 /* expression () has merrily parsed up to the end of line,
4389 or a comma - in the wrong buffer. Transfer how far
4390 input_line_pointer has moved to the right buffer. */
4391 input_line_pointer = (save
4392 + (input_line_pointer - gotfree_input_line)
4394 free (gotfree_input_line);
4402 static void signed_cons (int size)
4404 if (flag_code == CODE_64BIT)
4412 pe_directive_secrel (dummy)
4413 int dummy ATTRIBUTE_UNUSED;
4420 if (exp.X_op == O_symbol)
4421 exp.X_op = O_secrel;
4423 emit_expr (&exp, 4);
4425 while (*input_line_pointer++ == ',');
4427 input_line_pointer--;
4428 demand_empty_rest_of_line ();
4433 i386_immediate (char *imm_start)
4435 char *save_input_line_pointer;
4436 char *gotfree_input_line;
4439 unsigned int types = ~0U;
4441 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4443 as_bad (_("at most %d immediate operands are allowed"),
4444 MAX_IMMEDIATE_OPERANDS);
4448 exp = &im_expressions[i.imm_operands++];
4449 i.op[this_operand].imms = exp;
4451 if (is_space_char (*imm_start))
4454 save_input_line_pointer = input_line_pointer;
4455 input_line_pointer = imm_start;
4457 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4458 if (gotfree_input_line)
4459 input_line_pointer = gotfree_input_line;
4461 exp_seg = expression (exp);
4464 if (*input_line_pointer)
4465 as_bad (_("junk `%s' after expression"), input_line_pointer);
4467 input_line_pointer = save_input_line_pointer;
4468 if (gotfree_input_line)
4469 free (gotfree_input_line);
4471 if (exp->X_op == O_absent || exp->X_op == O_big)
4473 /* Missing or bad expr becomes absolute 0. */
4474 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4476 exp->X_op = O_constant;
4477 exp->X_add_number = 0;
4478 exp->X_add_symbol = (symbolS *) 0;
4479 exp->X_op_symbol = (symbolS *) 0;
4481 else if (exp->X_op == O_constant)
4483 /* Size it properly later. */
4484 i.types[this_operand] |= Imm64;
4485 /* If BFD64, sign extend val. */
4486 if (!use_rela_relocations)
4487 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4488 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4490 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4491 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4492 && exp_seg != absolute_section
4493 && exp_seg != text_section
4494 && exp_seg != data_section
4495 && exp_seg != bss_section
4496 && exp_seg != undefined_section
4497 && !bfd_is_com_section (exp_seg))
4499 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4503 else if (!intel_syntax && exp->X_op == O_register)
4505 as_bad (_("illegal immediate register operand %s"), imm_start);
4510 /* This is an address. The size of the address will be
4511 determined later, depending on destination register,
4512 suffix, or the default for the section. */
4513 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4514 i.types[this_operand] &= types;
4521 i386_scale (char *scale)
4524 char *save = input_line_pointer;
4526 input_line_pointer = scale;
4527 val = get_absolute_expression ();
4532 i.log2_scale_factor = 0;
4535 i.log2_scale_factor = 1;
4538 i.log2_scale_factor = 2;
4541 i.log2_scale_factor = 3;
4545 char sep = *input_line_pointer;
4547 *input_line_pointer = '\0';
4548 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4550 *input_line_pointer = sep;
4551 input_line_pointer = save;
4555 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4557 as_warn (_("scale factor of %d without an index register"),
4558 1 << i.log2_scale_factor);
4559 #if SCALE1_WHEN_NO_INDEX
4560 i.log2_scale_factor = 0;
4563 scale = input_line_pointer;
4564 input_line_pointer = save;
4569 i386_displacement (char *disp_start, char *disp_end)
4573 char *save_input_line_pointer;
4574 char *gotfree_input_line;
4575 int bigdisp, override;
4576 unsigned int types = Disp;
4578 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4580 as_bad (_("at most %d displacement operands are allowed"),
4581 MAX_MEMORY_OPERANDS);
4585 if ((i.types[this_operand] & JumpAbsolute)
4586 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4589 override = (i.prefix[ADDR_PREFIX] != 0);
4593 /* For PC-relative branches, the width of the displacement
4594 is dependent upon data size, not address size. */
4596 override = (i.prefix[DATA_PREFIX] != 0);
4598 if (flag_code == CODE_64BIT)
4601 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4603 : Disp32S | Disp32);
4605 bigdisp = Disp64 | Disp32S | Disp32;
4612 override = (i.suffix == (flag_code != CODE_16BIT
4614 : LONG_MNEM_SUFFIX));
4617 if ((flag_code == CODE_16BIT) ^ override)
4620 i.types[this_operand] |= bigdisp;
4622 exp = &disp_expressions[i.disp_operands];
4623 i.op[this_operand].disps = exp;
4625 save_input_line_pointer = input_line_pointer;
4626 input_line_pointer = disp_start;
4627 END_STRING_AND_SAVE (disp_end);
4629 #ifndef GCC_ASM_O_HACK
4630 #define GCC_ASM_O_HACK 0
4633 END_STRING_AND_SAVE (disp_end + 1);
4634 if ((i.types[this_operand] & BaseIndex) != 0
4635 && displacement_string_end[-1] == '+')
4637 /* This hack is to avoid a warning when using the "o"
4638 constraint within gcc asm statements.
4641 #define _set_tssldt_desc(n,addr,limit,type) \
4642 __asm__ __volatile__ ( \
4644 "movw %w1,2+%0\n\t" \
4646 "movb %b1,4+%0\n\t" \
4647 "movb %4,5+%0\n\t" \
4648 "movb $0,6+%0\n\t" \
4649 "movb %h1,7+%0\n\t" \
4651 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4653 This works great except that the output assembler ends
4654 up looking a bit weird if it turns out that there is
4655 no offset. You end up producing code that looks like:
4668 So here we provide the missing zero. */
4670 *displacement_string_end = '0';
4673 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4674 if (gotfree_input_line)
4675 input_line_pointer = gotfree_input_line;
4677 exp_seg = expression (exp);
4680 if (*input_line_pointer)
4681 as_bad (_("junk `%s' after expression"), input_line_pointer);
4683 RESTORE_END_STRING (disp_end + 1);
4685 RESTORE_END_STRING (disp_end);
4686 input_line_pointer = save_input_line_pointer;
4687 if (gotfree_input_line)
4688 free (gotfree_input_line);
4690 /* We do this to make sure that the section symbol is in
4691 the symbol table. We will ultimately change the relocation
4692 to be relative to the beginning of the section. */
4693 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4694 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4695 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4697 if (exp->X_op != O_symbol)
4699 as_bad (_("bad expression used with @%s"),
4700 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4706 if (S_IS_LOCAL (exp->X_add_symbol)
4707 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4708 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4709 exp->X_op = O_subtract;
4710 exp->X_op_symbol = GOT_symbol;
4711 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4712 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4713 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4714 i.reloc[this_operand] = BFD_RELOC_64;
4716 i.reloc[this_operand] = BFD_RELOC_32;
4719 if (exp->X_op == O_absent || exp->X_op == O_big)
4721 /* Missing or bad expr becomes absolute 0. */
4722 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4724 exp->X_op = O_constant;
4725 exp->X_add_number = 0;
4726 exp->X_add_symbol = (symbolS *) 0;
4727 exp->X_op_symbol = (symbolS *) 0;
4730 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4731 if (exp->X_op != O_constant
4732 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4733 && exp_seg != absolute_section
4734 && exp_seg != text_section
4735 && exp_seg != data_section
4736 && exp_seg != bss_section
4737 && exp_seg != undefined_section
4738 && !bfd_is_com_section (exp_seg))
4740 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4745 if (!(i.types[this_operand] & ~Disp))
4746 i.types[this_operand] &= types;
4751 /* Make sure the memory operand we've been dealt is valid.
4752 Return 1 on success, 0 on a failure. */
4755 i386_index_check (const char *operand_string)
4758 #if INFER_ADDR_PREFIX
4764 if ((current_templates->start->cpu_flags & CpuSVME)
4765 && current_templates->end[-1].operand_types[0] == AnyMem)
4767 /* Memory operands of SVME insns are special in that they only allow
4768 rAX as their memory address and ignore any segment override. */
4771 /* SKINIT is even more restrictive: it always requires EAX. */
4772 if (strcmp (current_templates->start->name, "skinit") == 0)
4774 else if (flag_code == CODE_64BIT)
4775 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4777 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4781 || !(i.base_reg->reg_type & Acc)
4782 || !(i.base_reg->reg_type & RegXX)
4784 || (i.types[0] & Disp))
4787 else if (flag_code == CODE_64BIT)
4789 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4792 && ((i.base_reg->reg_type & RegXX) == 0)
4793 && (i.base_reg->reg_type != BaseIndex
4796 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4797 != (RegXX | BaseIndex))))
4802 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4806 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4807 != (Reg16 | BaseIndex)))
4809 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4810 != (Reg16 | BaseIndex))
4812 && i.base_reg->reg_num < 6
4813 && i.index_reg->reg_num >= 6
4814 && i.log2_scale_factor == 0))))
4821 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4823 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4824 != (Reg32 | BaseIndex))))
4830 #if INFER_ADDR_PREFIX
4831 if (i.prefix[ADDR_PREFIX] == 0)
4833 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4835 /* Change the size of any displacement too. At most one of
4836 Disp16 or Disp32 is set.
4837 FIXME. There doesn't seem to be any real need for separate
4838 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4839 Removing them would probably clean up the code quite a lot. */
4840 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4841 i.types[this_operand] ^= (Disp16 | Disp32);
4846 as_bad (_("`%s' is not a valid base/index expression"),
4850 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4852 flag_code_names[flag_code]);
4857 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4861 i386_operand (char *operand_string)
4865 char *op_string = operand_string;
4867 if (is_space_char (*op_string))
4870 /* We check for an absolute prefix (differentiating,
4871 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4872 if (*op_string == ABSOLUTE_PREFIX)
4875 if (is_space_char (*op_string))
4877 i.types[this_operand] |= JumpAbsolute;
4880 /* Check if operand is a register. */
4881 if ((r = parse_register (op_string, &end_op)) != NULL)
4883 /* Check for a segment override by searching for ':' after a
4884 segment register. */
4886 if (is_space_char (*op_string))
4888 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4893 i.seg[i.mem_operands] = &es;
4896 i.seg[i.mem_operands] = &cs;
4899 i.seg[i.mem_operands] = &ss;
4902 i.seg[i.mem_operands] = &ds;
4905 i.seg[i.mem_operands] = &fs;
4908 i.seg[i.mem_operands] = &gs;
4912 /* Skip the ':' and whitespace. */
4914 if (is_space_char (*op_string))
4917 if (!is_digit_char (*op_string)
4918 && !is_identifier_char (*op_string)
4919 && *op_string != '('
4920 && *op_string != ABSOLUTE_PREFIX)
4922 as_bad (_("bad memory operand `%s'"), op_string);
4925 /* Handle case of %es:*foo. */
4926 if (*op_string == ABSOLUTE_PREFIX)
4929 if (is_space_char (*op_string))
4931 i.types[this_operand] |= JumpAbsolute;
4933 goto do_memory_reference;
4937 as_bad (_("junk `%s' after register"), op_string);
4940 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4941 i.op[this_operand].regs = r;
4944 else if (*op_string == REGISTER_PREFIX)
4946 as_bad (_("bad register name `%s'"), op_string);
4949 else if (*op_string == IMMEDIATE_PREFIX)
4952 if (i.types[this_operand] & JumpAbsolute)
4954 as_bad (_("immediate operand illegal with absolute jump"));
4957 if (!i386_immediate (op_string))
4960 else if (is_digit_char (*op_string)
4961 || is_identifier_char (*op_string)
4962 || *op_string == '(')
4964 /* This is a memory reference of some sort. */
4967 /* Start and end of displacement string expression (if found). */
4968 char *displacement_string_start;
4969 char *displacement_string_end;
4971 do_memory_reference:
4972 if ((i.mem_operands == 1
4973 && (current_templates->start->opcode_modifier & IsString) == 0)
4974 || i.mem_operands == 2)
4976 as_bad (_("too many memory references for `%s'"),
4977 current_templates->start->name);
4981 /* Check for base index form. We detect the base index form by
4982 looking for an ')' at the end of the operand, searching
4983 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4985 base_string = op_string + strlen (op_string);
4988 if (is_space_char (*base_string))
4991 /* If we only have a displacement, set-up for it to be parsed later. */
4992 displacement_string_start = op_string;
4993 displacement_string_end = base_string + 1;
4995 if (*base_string == ')')
4998 unsigned int parens_balanced = 1;
4999 /* We've already checked that the number of left & right ()'s are
5000 equal, so this loop will not be infinite. */
5004 if (*base_string == ')')
5006 if (*base_string == '(')
5009 while (parens_balanced);
5011 temp_string = base_string;
5013 /* Skip past '(' and whitespace. */
5015 if (is_space_char (*base_string))
5018 if (*base_string == ','
5019 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
5021 displacement_string_end = temp_string;
5023 i.types[this_operand] |= BaseIndex;
5027 base_string = end_op;
5028 if (is_space_char (*base_string))
5032 /* There may be an index reg or scale factor here. */
5033 if (*base_string == ',')
5036 if (is_space_char (*base_string))
5039 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5041 base_string = end_op;
5042 if (is_space_char (*base_string))
5044 if (*base_string == ',')
5047 if (is_space_char (*base_string))
5050 else if (*base_string != ')')
5052 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5057 else if (*base_string == REGISTER_PREFIX)
5059 as_bad (_("bad register name `%s'"), base_string);
5063 /* Check for scale factor. */
5064 if (*base_string != ')')
5066 char *end_scale = i386_scale (base_string);
5071 base_string = end_scale;
5072 if (is_space_char (*base_string))
5074 if (*base_string != ')')
5076 as_bad (_("expecting `)' after scale factor in `%s'"),
5081 else if (!i.index_reg)
5083 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5088 else if (*base_string != ')')
5090 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5095 else if (*base_string == REGISTER_PREFIX)
5097 as_bad (_("bad register name `%s'"), base_string);
5102 /* If there's an expression beginning the operand, parse it,
5103 assuming displacement_string_start and
5104 displacement_string_end are meaningful. */
5105 if (displacement_string_start != displacement_string_end)
5107 if (!i386_displacement (displacement_string_start,
5108 displacement_string_end))
5112 /* Special case for (%dx) while doing input/output op. */
5114 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5116 && i.log2_scale_factor == 0
5117 && i.seg[i.mem_operands] == 0
5118 && (i.types[this_operand] & Disp) == 0)
5120 i.types[this_operand] = InOutPortReg;
5124 if (i386_index_check (operand_string) == 0)
5130 /* It's not a memory operand; argh! */
5131 as_bad (_("invalid char %s beginning operand %d `%s'"),
5132 output_invalid (*op_string),
5137 return 1; /* Normal return. */
5140 /* md_estimate_size_before_relax()
5142 Called just before relax() for rs_machine_dependent frags. The x86
5143 assembler uses these frags to handle variable size jump
5146 Any symbol that is now undefined will not become defined.
5147 Return the correct fr_subtype in the frag.
5148 Return the initial "guess for variable size of frag" to caller.
5149 The guess is actually the growth beyond the fixed part. Whatever
5150 we do to grow the fixed or variable part contributes to our
5154 md_estimate_size_before_relax (fragP, segment)
5158 /* We've already got fragP->fr_subtype right; all we have to do is
5159 check for un-relaxable symbols. On an ELF system, we can't relax
5160 an externally visible symbol, because it may be overridden by a
5162 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5163 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5165 && (S_IS_EXTERNAL (fragP->fr_symbol)
5166 || S_IS_WEAK (fragP->fr_symbol)))
5170 /* Symbol is undefined in this segment, or we need to keep a
5171 reloc so that weak symbols can be overridden. */
5172 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5173 enum bfd_reloc_code_real reloc_type;
5174 unsigned char *opcode;
5177 if (fragP->fr_var != NO_RELOC)
5178 reloc_type = fragP->fr_var;
5180 reloc_type = BFD_RELOC_16_PCREL;
5182 reloc_type = BFD_RELOC_32_PCREL;
5184 old_fr_fix = fragP->fr_fix;
5185 opcode = (unsigned char *) fragP->fr_opcode;
5187 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5190 /* Make jmp (0xeb) a (d)word displacement jump. */
5192 fragP->fr_fix += size;
5193 fix_new (fragP, old_fr_fix, size,
5195 fragP->fr_offset, 1,
5201 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5203 /* Negate the condition, and branch past an
5204 unconditional jump. */
5207 /* Insert an unconditional jump. */
5209 /* We added two extra opcode bytes, and have a two byte
5211 fragP->fr_fix += 2 + 2;
5212 fix_new (fragP, old_fr_fix + 2, 2,
5214 fragP->fr_offset, 1,
5221 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5226 fixP = fix_new (fragP, old_fr_fix, 1,
5228 fragP->fr_offset, 1,
5230 fixP->fx_signed = 1;
5234 /* This changes the byte-displacement jump 0x7N
5235 to the (d)word-displacement jump 0x0f,0x8N. */
5236 opcode[1] = opcode[0] + 0x10;
5237 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5238 /* We've added an opcode byte. */
5239 fragP->fr_fix += 1 + size;
5240 fix_new (fragP, old_fr_fix + 1, size,
5242 fragP->fr_offset, 1,
5247 BAD_CASE (fragP->fr_subtype);
5251 return fragP->fr_fix - old_fr_fix;
5254 /* Guess size depending on current relax state. Initially the relax
5255 state will correspond to a short jump and we return 1, because
5256 the variable part of the frag (the branch offset) is one byte
5257 long. However, we can relax a section more than once and in that
5258 case we must either set fr_subtype back to the unrelaxed state,
5259 or return the value for the appropriate branch. */
5260 return md_relax_table[fragP->fr_subtype].rlx_length;
5263 /* Called after relax() is finished.
5265 In: Address of frag.
5266 fr_type == rs_machine_dependent.
5267 fr_subtype is what the address relaxed to.
5269 Out: Any fixSs and constants are set up.
5270 Caller will turn frag into a ".space 0". */
5273 md_convert_frag (abfd, sec, fragP)
5274 bfd *abfd ATTRIBUTE_UNUSED;
5275 segT sec ATTRIBUTE_UNUSED;
5278 unsigned char *opcode;
5279 unsigned char *where_to_put_displacement = NULL;
5280 offsetT target_address;
5281 offsetT opcode_address;
5282 unsigned int extension = 0;
5283 offsetT displacement_from_opcode_start;
5285 opcode = (unsigned char *) fragP->fr_opcode;
5287 /* Address we want to reach in file space. */
5288 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5290 /* Address opcode resides at in file space. */
5291 opcode_address = fragP->fr_address + fragP->fr_fix;
5293 /* Displacement from opcode start to fill into instruction. */
5294 displacement_from_opcode_start = target_address - opcode_address;
5296 if ((fragP->fr_subtype & BIG) == 0)
5298 /* Don't have to change opcode. */
5299 extension = 1; /* 1 opcode + 1 displacement */
5300 where_to_put_displacement = &opcode[1];
5304 if (no_cond_jump_promotion
5305 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5306 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5308 switch (fragP->fr_subtype)
5310 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5311 extension = 4; /* 1 opcode + 4 displacement */
5313 where_to_put_displacement = &opcode[1];
5316 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5317 extension = 2; /* 1 opcode + 2 displacement */
5319 where_to_put_displacement = &opcode[1];
5322 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5323 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5324 extension = 5; /* 2 opcode + 4 displacement */
5325 opcode[1] = opcode[0] + 0x10;
5326 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5327 where_to_put_displacement = &opcode[2];
5330 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5331 extension = 3; /* 2 opcode + 2 displacement */
5332 opcode[1] = opcode[0] + 0x10;
5333 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5334 where_to_put_displacement = &opcode[2];
5337 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5342 where_to_put_displacement = &opcode[3];
5346 BAD_CASE (fragP->fr_subtype);
5351 /* If size if less then four we are sure that the operand fits,
5352 but if it's 4, then it could be that the displacement is larger
5354 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5356 && ((addressT) (displacement_from_opcode_start - extension
5357 + ((addressT) 1 << 31))
5358 > (((addressT) 2 << 31) - 1)))
5360 as_bad_where (fragP->fr_file, fragP->fr_line,
5361 _("jump target out of range"));
5362 /* Make us emit 0. */
5363 displacement_from_opcode_start = extension;
5365 /* Now put displacement after opcode. */
5366 md_number_to_chars ((char *) where_to_put_displacement,
5367 (valueT) (displacement_from_opcode_start - extension),
5368 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5369 fragP->fr_fix += extension;
5372 /* Size of byte displacement jmp. */
5373 int md_short_jump_size = 2;
5375 /* Size of dword displacement jmp. */
5376 int md_long_jump_size = 5;
5379 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5381 addressT from_addr, to_addr;
5382 fragS *frag ATTRIBUTE_UNUSED;
5383 symbolS *to_symbol ATTRIBUTE_UNUSED;
5387 offset = to_addr - (from_addr + 2);
5388 /* Opcode for byte-disp jump. */
5389 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5390 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5394 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5396 addressT from_addr, to_addr;
5397 fragS *frag ATTRIBUTE_UNUSED;
5398 symbolS *to_symbol ATTRIBUTE_UNUSED;
5402 offset = to_addr - (from_addr + 5);
5403 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5404 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5407 /* Apply a fixup (fixS) to segment data, once it has been determined
5408 by our caller that we have all the info we need to fix it up.
5410 On the 386, immediates, displacements, and data pointers are all in
5411 the same (little-endian) format, so we don't need to care about which
5415 md_apply_fix (fixP, valP, seg)
5416 /* The fix we're to put in. */
5418 /* Pointer to the value of the bits. */
5420 /* Segment fix is from. */
5421 segT seg ATTRIBUTE_UNUSED;
5423 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5424 valueT value = *valP;
5426 #if !defined (TE_Mach)
5429 switch (fixP->fx_r_type)
5435 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5438 case BFD_RELOC_X86_64_32S:
5439 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5442 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5445 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5450 if (fixP->fx_addsy != NULL
5451 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5452 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5453 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5454 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5455 && !use_rela_relocations)
5457 /* This is a hack. There should be a better way to handle this.
5458 This covers for the fact that bfd_install_relocation will
5459 subtract the current location (for partial_inplace, PC relative
5460 relocations); see more below. */
5464 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5467 value += fixP->fx_where + fixP->fx_frag->fr_address;
5469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5472 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5475 || (symbol_section_p (fixP->fx_addsy)
5476 && sym_seg != absolute_section))
5477 && !generic_force_reloc (fixP))
5479 /* Yes, we add the values in twice. This is because
5480 bfd_install_relocation subtracts them out again. I think
5481 bfd_install_relocation is broken, but I don't dare change
5483 value += fixP->fx_where + fixP->fx_frag->fr_address;
5487 #if defined (OBJ_COFF) && defined (TE_PE)
5488 /* For some reason, the PE format does not store a
5489 section address offset for a PC relative symbol. */
5490 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5491 || S_IS_WEAK (fixP->fx_addsy))
5492 value += md_pcrel_from (fixP);
5496 /* Fix a few things - the dynamic linker expects certain values here,
5497 and we must not disappoint it. */
5498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5499 if (IS_ELF && fixP->fx_addsy)
5500 switch (fixP->fx_r_type)
5502 case BFD_RELOC_386_PLT32:
5503 case BFD_RELOC_X86_64_PLT32:
5504 /* Make the jump instruction point to the address of the operand. At
5505 runtime we merely add the offset to the actual PLT entry. */
5509 case BFD_RELOC_386_TLS_GD:
5510 case BFD_RELOC_386_TLS_LDM:
5511 case BFD_RELOC_386_TLS_IE_32:
5512 case BFD_RELOC_386_TLS_IE:
5513 case BFD_RELOC_386_TLS_GOTIE:
5514 case BFD_RELOC_386_TLS_GOTDESC:
5515 case BFD_RELOC_X86_64_TLSGD:
5516 case BFD_RELOC_X86_64_TLSLD:
5517 case BFD_RELOC_X86_64_GOTTPOFF:
5518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5519 value = 0; /* Fully resolved at runtime. No addend. */
5521 case BFD_RELOC_386_TLS_LE:
5522 case BFD_RELOC_386_TLS_LDO_32:
5523 case BFD_RELOC_386_TLS_LE_32:
5524 case BFD_RELOC_X86_64_DTPOFF32:
5525 case BFD_RELOC_X86_64_DTPOFF64:
5526 case BFD_RELOC_X86_64_TPOFF32:
5527 case BFD_RELOC_X86_64_TPOFF64:
5528 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5531 case BFD_RELOC_386_TLS_DESC_CALL:
5532 case BFD_RELOC_X86_64_TLSDESC_CALL:
5533 value = 0; /* Fully resolved at runtime. No addend. */
5534 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5538 case BFD_RELOC_386_GOT32:
5539 case BFD_RELOC_X86_64_GOT32:
5540 value = 0; /* Fully resolved at runtime. No addend. */
5543 case BFD_RELOC_VTABLE_INHERIT:
5544 case BFD_RELOC_VTABLE_ENTRY:
5551 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5553 #endif /* !defined (TE_Mach) */
5555 /* Are we finished with this relocation now? */
5556 if (fixP->fx_addsy == NULL)
5558 else if (use_rela_relocations)
5560 fixP->fx_no_overflow = 1;
5561 /* Remember value for tc_gen_reloc. */
5562 fixP->fx_addnumber = value;
5566 md_number_to_chars (p, value, fixP->fx_size);
5569 #define MAX_LITTLENUMS 6
5571 /* Turn the string pointed to by litP into a floating point constant
5572 of type TYPE, and emit the appropriate bytes. The number of
5573 LITTLENUMS emitted is stored in *SIZEP. An error message is
5574 returned, or NULL on OK. */
5577 md_atof (type, litP, sizeP)
5583 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5584 LITTLENUM_TYPE *wordP;
5606 return _("Bad call to md_atof ()");
5608 t = atof_ieee (input_line_pointer, type, words);
5610 input_line_pointer = t;
5612 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5613 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5614 the bigendian 386. */
5615 for (wordP = words + prec - 1; prec--;)
5617 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5618 litP += sizeof (LITTLENUM_TYPE);
5623 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5626 output_invalid (int c)
5629 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5632 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5633 "(0x%x)", (unsigned char) c);
5634 return output_invalid_buf;
5637 /* REG_STRING starts *before* REGISTER_PREFIX. */
5639 static const reg_entry *
5640 parse_real_register (char *reg_string, char **end_op)
5642 char *s = reg_string;
5644 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5647 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5648 if (*s == REGISTER_PREFIX)
5651 if (is_space_char (*s))
5655 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5657 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5658 return (const reg_entry *) NULL;
5662 /* For naked regs, make sure that we are not dealing with an identifier.
5663 This prevents confusing an identifier like `eax_var' with register
5665 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5666 return (const reg_entry *) NULL;
5670 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5672 /* Handle floating point regs, allowing spaces in the (i) part. */
5673 if (r == i386_regtab /* %st is first entry of table */)
5675 if (is_space_char (*s))
5680 if (is_space_char (*s))
5682 if (*s >= '0' && *s <= '7')
5684 r = &i386_float_regtab[*s - '0'];
5686 if (is_space_char (*s))
5694 /* We have "%st(" then garbage. */
5695 return (const reg_entry *) NULL;
5700 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5701 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5702 && flag_code != CODE_64BIT)
5703 return (const reg_entry *) NULL;
5708 /* REG_STRING starts *before* REGISTER_PREFIX. */
5710 static const reg_entry *
5711 parse_register (char *reg_string, char **end_op)
5715 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5716 r = parse_real_register (reg_string, end_op);
5721 char *save = input_line_pointer;
5725 input_line_pointer = reg_string;
5726 c = get_symbol_end ();
5727 symbolP = symbol_find (reg_string);
5728 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5730 const expressionS *e = symbol_get_value_expression (symbolP);
5732 know (e->X_op == O_register);
5733 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5734 r = i386_regtab + e->X_add_number;
5735 *end_op = input_line_pointer;
5737 *input_line_pointer = c;
5738 input_line_pointer = save;
5744 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5747 char *end = input_line_pointer;
5750 r = parse_register (name, &input_line_pointer);
5751 if (r && end <= input_line_pointer)
5753 *nextcharP = *input_line_pointer;
5754 *input_line_pointer = 0;
5755 e->X_op = O_register;
5756 e->X_add_number = r - i386_regtab;
5759 input_line_pointer = end;
5765 md_operand (expressionS *e)
5767 if (*input_line_pointer == REGISTER_PREFIX)
5770 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5774 e->X_op = O_register;
5775 e->X_add_number = r - i386_regtab;
5776 input_line_pointer = end;
5782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5783 const char *md_shortopts = "kVQ:sqn";
5785 const char *md_shortopts = "qn";
5788 #define OPTION_32 (OPTION_MD_BASE + 0)
5789 #define OPTION_64 (OPTION_MD_BASE + 1)
5790 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5791 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5792 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5794 struct option md_longopts[] =
5796 {"32", no_argument, NULL, OPTION_32},
5797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5798 {"64", no_argument, NULL, OPTION_64},
5800 {"divide", no_argument, NULL, OPTION_DIVIDE},
5801 {"march", required_argument, NULL, OPTION_MARCH},
5802 {"mtune", required_argument, NULL, OPTION_MTUNE},
5803 {NULL, no_argument, NULL, 0}
5805 size_t md_longopts_size = sizeof (md_longopts);
5808 md_parse_option (int c, char *arg)
5815 optimize_align_code = 0;
5822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5823 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5824 should be emitted or not. FIXME: Not implemented. */
5828 /* -V: SVR4 argument to print version ID. */
5830 print_version_id ();
5833 /* -k: Ignore for FreeBSD compatibility. */
5838 /* -s: On i386 Solaris, this tells the native assembler to use
5839 .stab instead of .stab.excl. We always use .stab anyhow. */
5842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5845 const char **list, **l;
5847 list = bfd_target_list ();
5848 for (l = list; *l != NULL; l++)
5849 if (CONST_STRNEQ (*l, "elf64-x86-64")
5850 || strcmp (*l, "coff-x86-64") == 0
5851 || strcmp (*l, "pe-x86-64") == 0
5852 || strcmp (*l, "pei-x86-64") == 0)
5854 default_arch = "x86_64";
5858 as_fatal (_("No compiled in support for x86_64"));
5865 default_arch = "i386";
5869 #ifdef SVR4_COMMENT_CHARS
5874 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5876 for (s = i386_comment_chars; *s != '\0'; s++)
5880 i386_comment_chars = n;
5887 as_fatal (_("Invalid -march= option: `%s'"), arg);
5888 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5890 if (strcmp (arg, cpu_arch [i].name) == 0)
5892 cpu_arch_isa = cpu_arch[i].type;
5893 cpu_arch_isa_flags = cpu_arch[i].flags;
5894 if (!cpu_arch_tune_set)
5896 cpu_arch_tune = cpu_arch_isa;
5897 cpu_arch_tune_flags = cpu_arch_isa_flags;
5902 if (i >= ARRAY_SIZE (cpu_arch))
5903 as_fatal (_("Invalid -march= option: `%s'"), arg);
5908 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5909 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5911 if (strcmp (arg, cpu_arch [i].name) == 0)
5913 cpu_arch_tune_set = 1;
5914 cpu_arch_tune = cpu_arch [i].type;
5915 cpu_arch_tune_flags = cpu_arch[i].flags;
5919 if (i >= ARRAY_SIZE (cpu_arch))
5920 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5930 md_show_usage (stream)
5933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5934 fprintf (stream, _("\
5936 -V print assembler version number\n\
5939 fprintf (stream, _("\
5940 -n Do not optimize code alignment\n\
5941 -q quieten some warnings\n"));
5942 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5943 fprintf (stream, _("\
5946 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5947 fprintf (stream, _("\
5948 --32/--64 generate 32bit/64bit code\n"));
5950 #ifdef SVR4_COMMENT_CHARS
5951 fprintf (stream, _("\
5952 --divide do not treat `/' as a comment character\n"));
5954 fprintf (stream, _("\
5955 --divide ignored\n"));
5957 fprintf (stream, _("\
5958 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5959 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5960 core, core2, k6, athlon, k8, generic32, generic64\n"));
5966 x86_64_target_format (void)
5968 if (strcmp (default_arch, "x86_64") == 0)
5970 set_code_flag (CODE_64BIT);
5971 return COFF_TARGET_FORMAT;
5973 else if (strcmp (default_arch, "i386") == 0)
5975 set_code_flag (CODE_32BIT);
5979 as_fatal (_("Unknown architecture"));
5984 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5985 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5987 /* Pick the target format to use. */
5990 i386_target_format (void)
5992 if (!strcmp (default_arch, "x86_64"))
5994 set_code_flag (CODE_64BIT);
5995 if (cpu_arch_isa_flags == 0)
5996 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
5997 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5999 if (cpu_arch_tune_flags == 0)
6000 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6001 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6004 else if (!strcmp (default_arch, "i386"))
6006 set_code_flag (CODE_32BIT);
6007 if (cpu_arch_isa_flags == 0)
6008 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6009 if (cpu_arch_tune_flags == 0)
6010 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6013 as_fatal (_("Unknown architecture"));
6014 switch (OUTPUT_FLAVOR)
6016 #ifdef OBJ_MAYBE_AOUT
6017 case bfd_target_aout_flavour:
6018 return AOUT_TARGET_FORMAT;
6020 #ifdef OBJ_MAYBE_COFF
6021 case bfd_target_coff_flavour:
6024 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6025 case bfd_target_elf_flavour:
6027 if (flag_code == CODE_64BIT)
6030 use_rela_relocations = 1;
6032 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6041 #endif /* OBJ_MAYBE_ more than one */
6043 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6045 i386_elf_emit_arch_note (void)
6047 if (IS_ELF && cpu_arch_name != NULL)
6050 asection *seg = now_seg;
6051 subsegT subseg = now_subseg;
6052 Elf_Internal_Note i_note;
6053 Elf_External_Note e_note;
6054 asection *note_secp;
6057 /* Create the .note section. */
6058 note_secp = subseg_new (".note", 0);
6059 bfd_set_section_flags (stdoutput,
6061 SEC_HAS_CONTENTS | SEC_READONLY);
6063 /* Process the arch string. */
6064 len = strlen (cpu_arch_name);
6066 i_note.namesz = len + 1;
6068 i_note.type = NT_ARCH;
6069 p = frag_more (sizeof (e_note.namesz));
6070 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6071 p = frag_more (sizeof (e_note.descsz));
6072 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6073 p = frag_more (sizeof (e_note.type));
6074 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6075 p = frag_more (len + 1);
6076 strcpy (p, cpu_arch_name);
6078 frag_align (2, 0, 0);
6080 subseg_set (seg, subseg);
6086 md_undefined_symbol (name)
6089 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6090 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6091 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6092 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6096 if (symbol_find (name))
6097 as_bad (_("GOT already in symbol table"));
6098 GOT_symbol = symbol_new (name, undefined_section,
6099 (valueT) 0, &zero_address_frag);
6106 /* Round up a section size to the appropriate boundary. */
6109 md_section_align (segment, size)
6110 segT segment ATTRIBUTE_UNUSED;
6113 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6114 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6116 /* For a.out, force the section size to be aligned. If we don't do
6117 this, BFD will align it for us, but it will not write out the
6118 final bytes of the section. This may be a bug in BFD, but it is
6119 easier to fix it here since that is how the other a.out targets
6123 align = bfd_get_section_alignment (stdoutput, segment);
6124 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6131 /* On the i386, PC-relative offsets are relative to the start of the
6132 next instruction. That is, the address of the offset, plus its
6133 size, since the offset is always the last part of the insn. */
6136 md_pcrel_from (fixS *fixP)
6138 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6144 s_bss (int ignore ATTRIBUTE_UNUSED)
6148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6150 obj_elf_section_change_hook ();
6152 temp = get_absolute_expression ();
6153 subseg_set (bss_section, (subsegT) temp);
6154 demand_empty_rest_of_line ();
6160 i386_validate_fix (fixS *fixp)
6162 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6164 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6168 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6173 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6175 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6182 tc_gen_reloc (section, fixp)
6183 asection *section ATTRIBUTE_UNUSED;
6187 bfd_reloc_code_real_type code;
6189 switch (fixp->fx_r_type)
6191 case BFD_RELOC_X86_64_PLT32:
6192 case BFD_RELOC_X86_64_GOT32:
6193 case BFD_RELOC_X86_64_GOTPCREL:
6194 case BFD_RELOC_386_PLT32:
6195 case BFD_RELOC_386_GOT32:
6196 case BFD_RELOC_386_GOTOFF:
6197 case BFD_RELOC_386_GOTPC:
6198 case BFD_RELOC_386_TLS_GD:
6199 case BFD_RELOC_386_TLS_LDM:
6200 case BFD_RELOC_386_TLS_LDO_32:
6201 case BFD_RELOC_386_TLS_IE_32:
6202 case BFD_RELOC_386_TLS_IE:
6203 case BFD_RELOC_386_TLS_GOTIE:
6204 case BFD_RELOC_386_TLS_LE_32:
6205 case BFD_RELOC_386_TLS_LE:
6206 case BFD_RELOC_386_TLS_GOTDESC:
6207 case BFD_RELOC_386_TLS_DESC_CALL:
6208 case BFD_RELOC_X86_64_TLSGD:
6209 case BFD_RELOC_X86_64_TLSLD:
6210 case BFD_RELOC_X86_64_DTPOFF32:
6211 case BFD_RELOC_X86_64_DTPOFF64:
6212 case BFD_RELOC_X86_64_GOTTPOFF:
6213 case BFD_RELOC_X86_64_TPOFF32:
6214 case BFD_RELOC_X86_64_TPOFF64:
6215 case BFD_RELOC_X86_64_GOTOFF64:
6216 case BFD_RELOC_X86_64_GOTPC32:
6217 case BFD_RELOC_X86_64_GOT64:
6218 case BFD_RELOC_X86_64_GOTPCREL64:
6219 case BFD_RELOC_X86_64_GOTPC64:
6220 case BFD_RELOC_X86_64_GOTPLT64:
6221 case BFD_RELOC_X86_64_PLTOFF64:
6222 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6223 case BFD_RELOC_X86_64_TLSDESC_CALL:
6225 case BFD_RELOC_VTABLE_ENTRY:
6226 case BFD_RELOC_VTABLE_INHERIT:
6228 case BFD_RELOC_32_SECREL:
6230 code = fixp->fx_r_type;
6232 case BFD_RELOC_X86_64_32S:
6233 if (!fixp->fx_pcrel)
6235 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6236 code = fixp->fx_r_type;
6242 switch (fixp->fx_size)
6245 as_bad_where (fixp->fx_file, fixp->fx_line,
6246 _("can not do %d byte pc-relative relocation"),
6248 code = BFD_RELOC_32_PCREL;
6250 case 1: code = BFD_RELOC_8_PCREL; break;
6251 case 2: code = BFD_RELOC_16_PCREL; break;
6252 case 4: code = BFD_RELOC_32_PCREL; break;
6254 case 8: code = BFD_RELOC_64_PCREL; break;
6260 switch (fixp->fx_size)
6263 as_bad_where (fixp->fx_file, fixp->fx_line,
6264 _("can not do %d byte relocation"),
6266 code = BFD_RELOC_32;
6268 case 1: code = BFD_RELOC_8; break;
6269 case 2: code = BFD_RELOC_16; break;
6270 case 4: code = BFD_RELOC_32; break;
6272 case 8: code = BFD_RELOC_64; break;
6279 if ((code == BFD_RELOC_32
6280 || code == BFD_RELOC_32_PCREL
6281 || code == BFD_RELOC_X86_64_32S)
6283 && fixp->fx_addsy == GOT_symbol)
6286 code = BFD_RELOC_386_GOTPC;
6288 code = BFD_RELOC_X86_64_GOTPC32;
6290 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6292 && fixp->fx_addsy == GOT_symbol)
6294 code = BFD_RELOC_X86_64_GOTPC64;
6297 rel = (arelent *) xmalloc (sizeof (arelent));
6298 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6299 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6301 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6303 if (!use_rela_relocations)
6305 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6306 vtable entry to be used in the relocation's section offset. */
6307 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6308 rel->address = fixp->fx_offset;
6312 /* Use the rela in 64bit mode. */
6315 if (!fixp->fx_pcrel)
6316 rel->addend = fixp->fx_offset;
6320 case BFD_RELOC_X86_64_PLT32:
6321 case BFD_RELOC_X86_64_GOT32:
6322 case BFD_RELOC_X86_64_GOTPCREL:
6323 case BFD_RELOC_X86_64_TLSGD:
6324 case BFD_RELOC_X86_64_TLSLD:
6325 case BFD_RELOC_X86_64_GOTTPOFF:
6326 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6327 case BFD_RELOC_X86_64_TLSDESC_CALL:
6328 rel->addend = fixp->fx_offset - fixp->fx_size;
6331 rel->addend = (section->vma
6333 + fixp->fx_addnumber
6334 + md_pcrel_from (fixp));
6339 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6340 if (rel->howto == NULL)
6342 as_bad_where (fixp->fx_file, fixp->fx_line,
6343 _("cannot represent relocation type %s"),
6344 bfd_get_reloc_code_name (code));
6345 /* Set howto to a garbage value so that we can keep going. */
6346 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6347 assert (rel->howto != NULL);
6354 /* Parse operands using Intel syntax. This implements a recursive descent
6355 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6358 FIXME: We do not recognize the full operand grammar defined in the MASM
6359 documentation. In particular, all the structure/union and
6360 high-level macro operands are missing.
6362 Uppercase words are terminals, lower case words are non-terminals.
6363 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6364 bars '|' denote choices. Most grammar productions are implemented in
6365 functions called 'intel_<production>'.
6367 Initial production is 'expr'.
6373 binOp & | AND | \| | OR | ^ | XOR
6375 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6377 constant digits [[ radixOverride ]]
6379 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6417 => expr expr cmpOp e04
6420 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6421 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6423 hexdigit a | b | c | d | e | f
6424 | A | B | C | D | E | F
6430 mulOp * | / | % | MOD | << | SHL | >> | SHR
6434 register specialRegister
6438 segmentRegister CS | DS | ES | FS | GS | SS
6440 specialRegister CR0 | CR2 | CR3 | CR4
6441 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6442 | TR3 | TR4 | TR5 | TR6 | TR7
6444 We simplify the grammar in obvious places (e.g., register parsing is
6445 done by calling parse_register) and eliminate immediate left recursion
6446 to implement a recursive-descent parser.
6450 expr' cmpOp e04 expr'
6501 /* Parsing structure for the intel syntax parser. Used to implement the
6502 semantic actions for the operand grammar. */
6503 struct intel_parser_s
6505 char *op_string; /* The string being parsed. */
6506 int got_a_float; /* Whether the operand is a float. */
6507 int op_modifier; /* Operand modifier. */
6508 int is_mem; /* 1 if operand is memory reference. */
6509 int in_offset; /* >=1 if parsing operand of offset. */
6510 int in_bracket; /* >=1 if parsing operand in brackets. */
6511 const reg_entry *reg; /* Last register reference found. */
6512 char *disp; /* Displacement string being built. */
6513 char *next_operand; /* Resume point when splitting operands. */
6516 static struct intel_parser_s intel_parser;
6518 /* Token structure for parsing intel syntax. */
6521 int code; /* Token code. */
6522 const reg_entry *reg; /* Register entry for register tokens. */
6523 char *str; /* String representation. */
6526 static struct intel_token cur_token, prev_token;
6528 /* Token codes for the intel parser. Since T_SHORT is already used
6529 by COFF, undefine it first to prevent a warning. */
6548 /* Prototypes for intel parser functions. */
6549 static int intel_match_token (int);
6550 static void intel_putback_token (void);
6551 static void intel_get_token (void);
6552 static int intel_expr (void);
6553 static int intel_e04 (void);
6554 static int intel_e05 (void);
6555 static int intel_e06 (void);
6556 static int intel_e09 (void);
6557 static int intel_e10 (void);
6558 static int intel_e11 (void);
6561 i386_intel_operand (char *operand_string, int got_a_float)
6566 p = intel_parser.op_string = xstrdup (operand_string);
6567 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6571 /* Initialize token holders. */
6572 cur_token.code = prev_token.code = T_NIL;
6573 cur_token.reg = prev_token.reg = NULL;
6574 cur_token.str = prev_token.str = NULL;
6576 /* Initialize parser structure. */
6577 intel_parser.got_a_float = got_a_float;
6578 intel_parser.op_modifier = 0;
6579 intel_parser.is_mem = 0;
6580 intel_parser.in_offset = 0;
6581 intel_parser.in_bracket = 0;
6582 intel_parser.reg = NULL;
6583 intel_parser.disp[0] = '\0';
6584 intel_parser.next_operand = NULL;
6586 /* Read the first token and start the parser. */
6588 ret = intel_expr ();
6593 if (cur_token.code != T_NIL)
6595 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6596 current_templates->start->name, cur_token.str);
6599 /* If we found a memory reference, hand it over to i386_displacement
6600 to fill in the rest of the operand fields. */
6601 else if (intel_parser.is_mem)
6603 if ((i.mem_operands == 1
6604 && (current_templates->start->opcode_modifier & IsString) == 0)
6605 || i.mem_operands == 2)
6607 as_bad (_("too many memory references for '%s'"),
6608 current_templates->start->name);
6613 char *s = intel_parser.disp;
6616 if (!quiet_warnings && intel_parser.is_mem < 0)
6617 /* See the comments in intel_bracket_expr. */
6618 as_warn (_("Treating `%s' as memory reference"), operand_string);
6620 /* Add the displacement expression. */
6622 ret = i386_displacement (s, s + strlen (s));
6625 /* Swap base and index in 16-bit memory operands like
6626 [si+bx]. Since i386_index_check is also used in AT&T
6627 mode we have to do that here. */
6630 && (i.base_reg->reg_type & Reg16)
6631 && (i.index_reg->reg_type & Reg16)
6632 && i.base_reg->reg_num >= 6
6633 && i.index_reg->reg_num < 6)
6635 const reg_entry *base = i.index_reg;
6637 i.index_reg = i.base_reg;
6640 ret = i386_index_check (operand_string);
6645 /* Constant and OFFSET expressions are handled by i386_immediate. */
6646 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6647 || intel_parser.reg == NULL)
6648 ret = i386_immediate (intel_parser.disp);
6650 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6652 if (!ret || !intel_parser.next_operand)
6654 intel_parser.op_string = intel_parser.next_operand;
6655 this_operand = i.operands++;
6659 free (intel_parser.disp);
6664 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6668 expr' cmpOp e04 expr'
6673 /* XXX Implement the comparison operators. */
6674 return intel_e04 ();
6691 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6692 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6694 if (cur_token.code == '+')
6696 else if (cur_token.code == '-')
6697 nregs = NUM_ADDRESS_REGS;
6701 strcat (intel_parser.disp, cur_token.str);
6702 intel_match_token (cur_token.code);
6713 int nregs = ~NUM_ADDRESS_REGS;
6720 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6724 str[0] = cur_token.code;
6726 strcat (intel_parser.disp, str);
6731 intel_match_token (cur_token.code);
6736 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6737 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6748 int nregs = ~NUM_ADDRESS_REGS;
6755 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6759 str[0] = cur_token.code;
6761 strcat (intel_parser.disp, str);
6763 else if (cur_token.code == T_SHL)
6764 strcat (intel_parser.disp, "<<");
6765 else if (cur_token.code == T_SHR)
6766 strcat (intel_parser.disp, ">>");
6770 intel_match_token (cur_token.code);
6775 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6776 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6794 int nregs = ~NUM_ADDRESS_REGS;
6799 /* Don't consume constants here. */
6800 if (cur_token.code == '+' || cur_token.code == '-')
6802 /* Need to look one token ahead - if the next token
6803 is a constant, the current token is its sign. */
6806 intel_match_token (cur_token.code);
6807 next_code = cur_token.code;
6808 intel_putback_token ();
6809 if (next_code == T_CONST)
6813 /* e09 OFFSET e09 */
6814 if (cur_token.code == T_OFFSET)
6817 ++intel_parser.in_offset;
6821 else if (cur_token.code == T_SHORT)
6822 intel_parser.op_modifier |= 1 << T_SHORT;
6825 else if (cur_token.code == '+')
6826 strcat (intel_parser.disp, "+");
6831 else if (cur_token.code == '-' || cur_token.code == '~')
6837 str[0] = cur_token.code;
6839 strcat (intel_parser.disp, str);
6846 intel_match_token (cur_token.code);
6854 /* e09' PTR e10 e09' */
6855 if (cur_token.code == T_PTR)
6859 if (prev_token.code == T_BYTE)
6860 suffix = BYTE_MNEM_SUFFIX;
6862 else if (prev_token.code == T_WORD)
6864 if (current_templates->start->name[0] == 'l'
6865 && current_templates->start->name[2] == 's'
6866 && current_templates->start->name[3] == 0)
6867 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6868 else if (intel_parser.got_a_float == 2) /* "fi..." */
6869 suffix = SHORT_MNEM_SUFFIX;
6871 suffix = WORD_MNEM_SUFFIX;
6874 else if (prev_token.code == T_DWORD)
6876 if (current_templates->start->name[0] == 'l'
6877 && current_templates->start->name[2] == 's'
6878 && current_templates->start->name[3] == 0)
6879 suffix = WORD_MNEM_SUFFIX;
6880 else if (flag_code == CODE_16BIT
6881 && (current_templates->start->opcode_modifier
6882 & (Jump | JumpDword)))
6883 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6884 else if (intel_parser.got_a_float == 1) /* "f..." */
6885 suffix = SHORT_MNEM_SUFFIX;
6887 suffix = LONG_MNEM_SUFFIX;
6890 else if (prev_token.code == T_FWORD)
6892 if (current_templates->start->name[0] == 'l'
6893 && current_templates->start->name[2] == 's'
6894 && current_templates->start->name[3] == 0)
6895 suffix = LONG_MNEM_SUFFIX;
6896 else if (!intel_parser.got_a_float)
6898 if (flag_code == CODE_16BIT)
6899 add_prefix (DATA_PREFIX_OPCODE);
6900 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6903 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6906 else if (prev_token.code == T_QWORD)
6908 if (intel_parser.got_a_float == 1) /* "f..." */
6909 suffix = LONG_MNEM_SUFFIX;
6911 suffix = QWORD_MNEM_SUFFIX;
6914 else if (prev_token.code == T_TBYTE)
6916 if (intel_parser.got_a_float == 1)
6917 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6919 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6922 else if (prev_token.code == T_XMMWORD)
6924 /* XXX ignored for now, but accepted since gcc uses it */
6930 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6934 /* Operands for jump/call using 'ptr' notation denote absolute
6936 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6937 i.types[this_operand] |= JumpAbsolute;
6939 if (current_templates->start->base_opcode == 0x8d /* lea */)
6943 else if (i.suffix != suffix)
6945 as_bad (_("Conflicting operand modifiers"));
6951 /* e09' : e10 e09' */
6952 else if (cur_token.code == ':')
6954 if (prev_token.code != T_REG)
6956 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6957 segment/group identifier (which we don't have), using comma
6958 as the operand separator there is even less consistent, since
6959 there all branches only have a single operand. */
6960 if (this_operand != 0
6961 || intel_parser.in_offset
6962 || intel_parser.in_bracket
6963 || (!(current_templates->start->opcode_modifier
6964 & (Jump|JumpDword|JumpInterSegment))
6965 && !(current_templates->start->operand_types[0]
6967 return intel_match_token (T_NIL);
6968 /* Remember the start of the 2nd operand and terminate 1st
6970 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6971 another expression), but it gets at least the simplest case
6972 (a plain number or symbol on the left side) right. */
6973 intel_parser.next_operand = intel_parser.op_string;
6974 *--intel_parser.op_string = '\0';
6975 return intel_match_token (':');
6983 intel_match_token (cur_token.code);
6989 --intel_parser.in_offset;
6992 if (NUM_ADDRESS_REGS > nregs)
6994 as_bad (_("Invalid operand to `OFFSET'"));
6997 intel_parser.op_modifier |= 1 << T_OFFSET;
7000 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7001 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7006 intel_bracket_expr (void)
7008 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7009 const char *start = intel_parser.op_string;
7012 if (i.op[this_operand].regs)
7013 return intel_match_token (T_NIL);
7015 intel_match_token ('[');
7017 /* Mark as a memory operand only if it's not already known to be an
7018 offset expression. If it's an offset expression, we need to keep
7020 if (!intel_parser.in_offset)
7022 ++intel_parser.in_bracket;
7024 /* Operands for jump/call inside brackets denote absolute addresses. */
7025 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7026 i.types[this_operand] |= JumpAbsolute;
7028 /* Unfortunately gas always diverged from MASM in a respect that can't
7029 be easily fixed without risking to break code sequences likely to be
7030 encountered (the testsuite even check for this): MASM doesn't consider
7031 an expression inside brackets unconditionally as a memory reference.
7032 When that is e.g. a constant, an offset expression, or the sum of the
7033 two, this is still taken as a constant load. gas, however, always
7034 treated these as memory references. As a compromise, we'll try to make
7035 offset expressions inside brackets work the MASM way (since that's
7036 less likely to be found in real world code), but make constants alone
7037 continue to work the traditional gas way. In either case, issue a
7039 intel_parser.op_modifier &= ~was_offset;
7042 strcat (intel_parser.disp, "[");
7044 /* Add a '+' to the displacement string if necessary. */
7045 if (*intel_parser.disp != '\0'
7046 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7047 strcat (intel_parser.disp, "+");
7050 && (len = intel_parser.op_string - start - 1,
7051 intel_match_token (']')))
7053 /* Preserve brackets when the operand is an offset expression. */
7054 if (intel_parser.in_offset)
7055 strcat (intel_parser.disp, "]");
7058 --intel_parser.in_bracket;
7059 if (i.base_reg || i.index_reg)
7060 intel_parser.is_mem = 1;
7061 if (!intel_parser.is_mem)
7063 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7064 /* Defer the warning until all of the operand was parsed. */
7065 intel_parser.is_mem = -1;
7066 else if (!quiet_warnings)
7067 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7070 intel_parser.op_modifier |= was_offset;
7087 while (cur_token.code == '[')
7089 if (!intel_bracket_expr ())
7114 switch (cur_token.code)
7118 intel_match_token ('(');
7119 strcat (intel_parser.disp, "(");
7121 if (intel_expr () && intel_match_token (')'))
7123 strcat (intel_parser.disp, ")");
7130 return intel_bracket_expr ();
7135 strcat (intel_parser.disp, cur_token.str);
7136 intel_match_token (cur_token.code);
7138 /* Mark as a memory operand only if it's not already known to be an
7139 offset expression. */
7140 if (!intel_parser.in_offset)
7141 intel_parser.is_mem = 1;
7148 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7150 intel_match_token (T_REG);
7152 /* Check for segment change. */
7153 if (cur_token.code == ':')
7155 if (!(reg->reg_type & (SReg2 | SReg3)))
7157 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7160 else if (i.seg[i.mem_operands])
7161 as_warn (_("Extra segment override ignored"));
7164 if (!intel_parser.in_offset)
7165 intel_parser.is_mem = 1;
7166 switch (reg->reg_num)
7169 i.seg[i.mem_operands] = &es;
7172 i.seg[i.mem_operands] = &cs;
7175 i.seg[i.mem_operands] = &ss;
7178 i.seg[i.mem_operands] = &ds;
7181 i.seg[i.mem_operands] = &fs;
7184 i.seg[i.mem_operands] = &gs;
7190 /* Not a segment register. Check for register scaling. */
7191 else if (cur_token.code == '*')
7193 if (!intel_parser.in_bracket)
7195 as_bad (_("Register scaling only allowed in memory operands"));
7199 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7200 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7201 else if (i.index_reg)
7202 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7204 /* What follows must be a valid scale. */
7205 intel_match_token ('*');
7207 i.types[this_operand] |= BaseIndex;
7209 /* Set the scale after setting the register (otherwise,
7210 i386_scale will complain) */
7211 if (cur_token.code == '+' || cur_token.code == '-')
7213 char *str, sign = cur_token.code;
7214 intel_match_token (cur_token.code);
7215 if (cur_token.code != T_CONST)
7217 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7221 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7222 strcpy (str + 1, cur_token.str);
7224 if (!i386_scale (str))
7228 else if (!i386_scale (cur_token.str))
7230 intel_match_token (cur_token.code);
7233 /* No scaling. If this is a memory operand, the register is either a
7234 base register (first occurrence) or an index register (second
7236 else if (intel_parser.in_bracket)
7241 else if (!i.index_reg)
7245 as_bad (_("Too many register references in memory operand"));
7249 i.types[this_operand] |= BaseIndex;
7252 /* It's neither base nor index. */
7253 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7255 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7256 i.op[this_operand].regs = reg;
7261 as_bad (_("Invalid use of register"));
7265 /* Since registers are not part of the displacement string (except
7266 when we're parsing offset operands), we may need to remove any
7267 preceding '+' from the displacement string. */
7268 if (*intel_parser.disp != '\0'
7269 && !intel_parser.in_offset)
7271 char *s = intel_parser.disp;
7272 s += strlen (s) - 1;
7295 intel_match_token (cur_token.code);
7297 if (cur_token.code == T_PTR)
7300 /* It must have been an identifier. */
7301 intel_putback_token ();
7302 cur_token.code = T_ID;
7308 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7312 /* The identifier represents a memory reference only if it's not
7313 preceded by an offset modifier and if it's not an equate. */
7314 symbolP = symbol_find(cur_token.str);
7315 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7316 intel_parser.is_mem = 1;
7324 char *save_str, sign = 0;
7326 /* Allow constants that start with `+' or `-'. */
7327 if (cur_token.code == '-' || cur_token.code == '+')
7329 sign = cur_token.code;
7330 intel_match_token (cur_token.code);
7331 if (cur_token.code != T_CONST)
7333 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7339 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7340 strcpy (save_str + !!sign, cur_token.str);
7344 /* Get the next token to check for register scaling. */
7345 intel_match_token (cur_token.code);
7347 /* Check if this constant is a scaling factor for an index register. */
7348 if (cur_token.code == '*')
7350 if (intel_match_token ('*') && cur_token.code == T_REG)
7352 const reg_entry *reg = cur_token.reg;
7354 if (!intel_parser.in_bracket)
7356 as_bad (_("Register scaling only allowed in memory operands"));
7360 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7361 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7362 else if (i.index_reg)
7363 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7365 /* The constant is followed by `* reg', so it must be
7368 i.types[this_operand] |= BaseIndex;
7370 /* Set the scale after setting the register (otherwise,
7371 i386_scale will complain) */
7372 if (!i386_scale (save_str))
7374 intel_match_token (T_REG);
7376 /* Since registers are not part of the displacement
7377 string, we may need to remove any preceding '+' from
7378 the displacement string. */
7379 if (*intel_parser.disp != '\0')
7381 char *s = intel_parser.disp;
7382 s += strlen (s) - 1;
7392 /* The constant was not used for register scaling. Since we have
7393 already consumed the token following `*' we now need to put it
7394 back in the stream. */
7395 intel_putback_token ();
7398 /* Add the constant to the displacement string. */
7399 strcat (intel_parser.disp, save_str);
7406 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7410 /* Match the given token against cur_token. If they match, read the next
7411 token from the operand string. */
7413 intel_match_token (int code)
7415 if (cur_token.code == code)
7422 as_bad (_("Unexpected token `%s'"), cur_token.str);
7427 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7429 intel_get_token (void)
7432 const reg_entry *reg;
7433 struct intel_token new_token;
7435 new_token.code = T_NIL;
7436 new_token.reg = NULL;
7437 new_token.str = NULL;
7439 /* Free the memory allocated to the previous token and move
7440 cur_token to prev_token. */
7442 free (prev_token.str);
7444 prev_token = cur_token;
7446 /* Skip whitespace. */
7447 while (is_space_char (*intel_parser.op_string))
7448 intel_parser.op_string++;
7450 /* Return an empty token if we find nothing else on the line. */
7451 if (*intel_parser.op_string == '\0')
7453 cur_token = new_token;
7457 /* The new token cannot be larger than the remainder of the operand
7459 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7460 new_token.str[0] = '\0';
7462 if (strchr ("0123456789", *intel_parser.op_string))
7464 char *p = new_token.str;
7465 char *q = intel_parser.op_string;
7466 new_token.code = T_CONST;
7468 /* Allow any kind of identifier char to encompass floating point and
7469 hexadecimal numbers. */
7470 while (is_identifier_char (*q))
7474 /* Recognize special symbol names [0-9][bf]. */
7475 if (strlen (intel_parser.op_string) == 2
7476 && (intel_parser.op_string[1] == 'b'
7477 || intel_parser.op_string[1] == 'f'))
7478 new_token.code = T_ID;
7481 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7483 size_t len = end_op - intel_parser.op_string;
7485 new_token.code = T_REG;
7486 new_token.reg = reg;
7488 memcpy (new_token.str, intel_parser.op_string, len);
7489 new_token.str[len] = '\0';
7492 else if (is_identifier_char (*intel_parser.op_string))
7494 char *p = new_token.str;
7495 char *q = intel_parser.op_string;
7497 /* A '.' or '$' followed by an identifier char is an identifier.
7498 Otherwise, it's operator '.' followed by an expression. */
7499 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7501 new_token.code = '.';
7502 new_token.str[0] = '.';
7503 new_token.str[1] = '\0';
7507 while (is_identifier_char (*q) || *q == '@')
7511 if (strcasecmp (new_token.str, "NOT") == 0)
7512 new_token.code = '~';
7514 else if (strcasecmp (new_token.str, "MOD") == 0)
7515 new_token.code = '%';
7517 else if (strcasecmp (new_token.str, "AND") == 0)
7518 new_token.code = '&';
7520 else if (strcasecmp (new_token.str, "OR") == 0)
7521 new_token.code = '|';
7523 else if (strcasecmp (new_token.str, "XOR") == 0)
7524 new_token.code = '^';
7526 else if (strcasecmp (new_token.str, "SHL") == 0)
7527 new_token.code = T_SHL;
7529 else if (strcasecmp (new_token.str, "SHR") == 0)
7530 new_token.code = T_SHR;
7532 else if (strcasecmp (new_token.str, "BYTE") == 0)
7533 new_token.code = T_BYTE;
7535 else if (strcasecmp (new_token.str, "WORD") == 0)
7536 new_token.code = T_WORD;
7538 else if (strcasecmp (new_token.str, "DWORD") == 0)
7539 new_token.code = T_DWORD;
7541 else if (strcasecmp (new_token.str, "FWORD") == 0)
7542 new_token.code = T_FWORD;
7544 else if (strcasecmp (new_token.str, "QWORD") == 0)
7545 new_token.code = T_QWORD;
7547 else if (strcasecmp (new_token.str, "TBYTE") == 0
7548 /* XXX remove (gcc still uses it) */
7549 || strcasecmp (new_token.str, "XWORD") == 0)
7550 new_token.code = T_TBYTE;
7552 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7553 || strcasecmp (new_token.str, "OWORD") == 0)
7554 new_token.code = T_XMMWORD;
7556 else if (strcasecmp (new_token.str, "PTR") == 0)
7557 new_token.code = T_PTR;
7559 else if (strcasecmp (new_token.str, "SHORT") == 0)
7560 new_token.code = T_SHORT;
7562 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7564 new_token.code = T_OFFSET;
7566 /* ??? This is not mentioned in the MASM grammar but gcc
7567 makes use of it with -mintel-syntax. OFFSET may be
7568 followed by FLAT: */
7569 if (strncasecmp (q, " FLAT:", 6) == 0)
7570 strcat (new_token.str, " FLAT:");
7573 /* ??? This is not mentioned in the MASM grammar. */
7574 else if (strcasecmp (new_token.str, "FLAT") == 0)
7576 new_token.code = T_OFFSET;
7578 strcat (new_token.str, ":");
7580 as_bad (_("`:' expected"));
7584 new_token.code = T_ID;
7588 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7590 new_token.code = *intel_parser.op_string;
7591 new_token.str[0] = *intel_parser.op_string;
7592 new_token.str[1] = '\0';
7595 else if (strchr ("<>", *intel_parser.op_string)
7596 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7598 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7599 new_token.str[0] = *intel_parser.op_string;
7600 new_token.str[1] = *intel_parser.op_string;
7601 new_token.str[2] = '\0';
7605 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7607 intel_parser.op_string += strlen (new_token.str);
7608 cur_token = new_token;
7611 /* Put cur_token back into the token stream and make cur_token point to
7614 intel_putback_token (void)
7616 if (cur_token.code != T_NIL)
7618 intel_parser.op_string -= strlen (cur_token.str);
7619 free (cur_token.str);
7621 cur_token = prev_token;
7623 /* Forget prev_token. */
7624 prev_token.code = T_NIL;
7625 prev_token.reg = NULL;
7626 prev_token.str = NULL;
7630 tc_x86_regname_to_dw2regnum (char *regname)
7632 unsigned int regnum;
7633 unsigned int regnames_count;
7634 static const char *const regnames_32[] =
7636 "eax", "ecx", "edx", "ebx",
7637 "esp", "ebp", "esi", "edi",
7638 "eip", "eflags", NULL,
7639 "st0", "st1", "st2", "st3",
7640 "st4", "st5", "st6", "st7",
7642 "xmm0", "xmm1", "xmm2", "xmm3",
7643 "xmm4", "xmm5", "xmm6", "xmm7",
7644 "mm0", "mm1", "mm2", "mm3",
7645 "mm4", "mm5", "mm6", "mm7",
7646 "fcw", "fsw", "mxcsr",
7647 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7650 static const char *const regnames_64[] =
7652 "rax", "rdx", "rcx", "rbx",
7653 "rsi", "rdi", "rbp", "rsp",
7654 "r8", "r9", "r10", "r11",
7655 "r12", "r13", "r14", "r15",
7657 "xmm0", "xmm1", "xmm2", "xmm3",
7658 "xmm4", "xmm5", "xmm6", "xmm7",
7659 "xmm8", "xmm9", "xmm10", "xmm11",
7660 "xmm12", "xmm13", "xmm14", "xmm15",
7661 "st0", "st1", "st2", "st3",
7662 "st4", "st5", "st6", "st7",
7663 "mm0", "mm1", "mm2", "mm3",
7664 "mm4", "mm5", "mm6", "mm7",
7666 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7667 "fs.base", "gs.base", NULL, NULL,
7669 "mxcsr", "fcw", "fsw"
7671 const char *const *regnames;
7673 if (flag_code == CODE_64BIT)
7675 regnames = regnames_64;
7676 regnames_count = ARRAY_SIZE (regnames_64);
7680 regnames = regnames_32;
7681 regnames_count = ARRAY_SIZE (regnames_32);
7684 for (regnum = 0; regnum < regnames_count; regnum++)
7685 if (regnames[regnum] != NULL
7686 && strcmp (regname, regnames[regnum]) == 0)
7693 tc_x86_frame_initial_instructions (void)
7695 static unsigned int sp_regno;
7698 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7701 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7702 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7706 i386_elf_section_type (const char *str, size_t len)
7708 if (flag_code == CODE_64BIT
7709 && len == sizeof ("unwind") - 1
7710 && strncmp (str, "unwind", 6) == 0)
7711 return SHT_X86_64_UNWIND;
7718 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7722 expr.X_op = O_secrel;
7723 expr.X_add_symbol = symbol;
7724 expr.X_add_number = 0;
7725 emit_expr (&expr, size);
7729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7730 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7733 x86_64_section_letter (int letter, char **ptr_msg)
7735 if (flag_code == CODE_64BIT)
7738 return SHF_X86_64_LARGE;
7740 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7743 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7748 x86_64_section_word (char *str, size_t len)
7750 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7751 return SHF_X86_64_LARGE;
7757 handle_large_common (int small ATTRIBUTE_UNUSED)
7759 if (flag_code != CODE_64BIT)
7761 s_comm_internal (0, elf_common_parse);
7762 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7766 static segT lbss_section;
7767 asection *saved_com_section_ptr = elf_com_section_ptr;
7768 asection *saved_bss_section = bss_section;
7770 if (lbss_section == NULL)
7772 flagword applicable;
7774 subsegT subseg = now_subseg;
7776 /* The .lbss section is for local .largecomm symbols. */
7777 lbss_section = subseg_new (".lbss", 0);
7778 applicable = bfd_applicable_section_flags (stdoutput);
7779 bfd_set_section_flags (stdoutput, lbss_section,
7780 applicable & SEC_ALLOC);
7781 seg_info (lbss_section)->bss = 1;
7783 subseg_set (seg, subseg);
7786 elf_com_section_ptr = &_bfd_elf_large_com_section;
7787 bss_section = lbss_section;
7789 s_comm_internal (0, elf_common_parse);
7791 elf_com_section_ptr = saved_com_section_ptr;
7792 bss_section = saved_bss_section;
7795 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */