1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry *parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry *build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS *, offsetT);
95 static void output_disp (fragS *, offsetT);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED);
103 static const char *default_arch = DEFAULT_ARCH;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry *regs;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types[MAX_OPERANDS];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op[MAX_OPERANDS];
140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry *seg[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars = "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars = "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars[] = "#/";
212 const char line_separator_chars[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars[256];
225 static char register_chars[256];
226 static char operand_chars[256];
227 static char identifier_chars[256];
228 static char digit_chars[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack[32];
246 static char *save_stack_p;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates *current_templates;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
262 /* Current operand we are working on. */
263 static int this_operand;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code;
275 static unsigned int object_64bit;
276 static int use_rela_relocations = 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names[] =
286 /* 1 for intel syntax,
288 static int intel_syntax = 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg = 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix = "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size = '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code = 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings = 0;
308 static const char *cpu_arch_name = NULL;
309 static const char *cpu_sub_arch_name = NULL;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set = 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags = 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags = 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion = 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS *GOT_symbol;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch[] =
423 {"generic32", PROCESSOR_GENERIC32,
424 Cpu186|Cpu286|Cpu386},
425 {"generic64", PROCESSOR_GENERIC64,
426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
430 {"i186", PROCESSOR_UNKNOWN,
432 {"i286", PROCESSOR_UNKNOWN,
434 {"i386", PROCESSOR_GENERIC32,
435 Cpu186|Cpu286|Cpu386},
436 {"i486", PROCESSOR_I486,
437 Cpu186|Cpu286|Cpu386|Cpu486},
438 {"i586", PROCESSOR_PENTIUM,
439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
440 {"i686", PROCESSOR_PENTIUMPRO,
441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
442 {"pentium", PROCESSOR_PENTIUM,
443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
446 {"pentiumii", PROCESSOR_PENTIUMPRO,
447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
450 {"pentium4", PROCESSOR_PENTIUM4,
451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
459 {"yonah", PROCESSOR_CORE,
460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
462 {"core", PROCESSOR_CORE,
463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
473 {"k6_2", PROCESSOR_K6,
474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
475 {"athlon", PROCESSOR_ATHLON,
476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
487 {"amdfam10", PROCESSOR_AMDFAM10,
488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN,
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
503 {".3dnow", PROCESSOR_UNKNOWN,
505 {".3dnowa", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
507 {".padlock", PROCESSOR_UNKNOWN,
509 {".pacifica", PROCESSOR_UNKNOWN,
511 {".svme", PROCESSOR_UNKNOWN,
513 {".sse4a", PROCESSOR_UNKNOWN,
514 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
515 {".abm", PROCESSOR_UNKNOWN,
519 const pseudo_typeS md_pseudo_table[] =
521 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
522 {"align", s_align_bytes, 0},
524 {"align", s_align_ptwo, 0},
526 {"arch", set_cpu_arch, 0},
530 {"ffloat", float_cons, 'f'},
531 {"dfloat", float_cons, 'd'},
532 {"tfloat", float_cons, 'x'},
534 {"slong", signed_cons, 4},
535 {"noopt", s_ignore, 0},
536 {"optim", s_ignore, 0},
537 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
538 {"code16", set_code_flag, CODE_16BIT},
539 {"code32", set_code_flag, CODE_32BIT},
540 {"code64", set_code_flag, CODE_64BIT},
541 {"intel_syntax", set_intel_syntax, 1},
542 {"att_syntax", set_intel_syntax, 0},
543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
544 {"largecomm", handle_large_common, 0},
546 {"file", (void (*) (int)) dwarf2_directive_file, 0},
547 {"loc", dwarf2_directive_loc, 0},
548 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
551 {"secrel32", pe_directive_secrel, 0},
556 /* For interface with expression (). */
557 extern char *input_line_pointer;
559 /* Hash table for instruction mnemonic lookup. */
560 static struct hash_control *op_hash;
562 /* Hash table for register lookup. */
563 static struct hash_control *reg_hash;
566 i386_align_code (fragS *fragP, int count)
568 /* Various efficient no-op patterns for aligning code labels.
569 Note: Don't try to assemble the instructions in the comments.
570 0L and 0w are not legal. */
571 static const char f32_1[] =
573 static const char f32_2[] =
574 {0x66,0x90}; /* xchg %ax,%ax */
575 static const char f32_3[] =
576 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
577 static const char f32_4[] =
578 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_5[] =
581 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_6[] =
583 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
584 static const char f32_7[] =
585 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_8[] =
588 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_9[] =
590 {0x89,0xf6, /* movl %esi,%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_10[] =
593 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_11[] =
596 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_12[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
601 static const char f32_13[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f32_14[] =
605 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_15[] =
608 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
609 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char *const f32_patt[] = {
627 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
628 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
630 static const char *const f16_patt[] = {
631 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
632 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
635 static const char alt_3[] =
637 /* nopl 0(%[re]ax) */
638 static const char alt_4[] =
639 {0x0f,0x1f,0x40,0x00};
640 /* nopl 0(%[re]ax,%[re]ax,1) */
641 static const char alt_5[] =
642 {0x0f,0x1f,0x44,0x00,0x00};
643 /* nopw 0(%[re]ax,%[re]ax,1) */
644 static const char alt_6[] =
645 {0x66,0x0f,0x1f,0x44,0x00,0x00};
646 /* nopl 0L(%[re]ax) */
647 static const char alt_7[] =
648 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
649 /* nopl 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_8[] =
651 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw 0L(%[re]ax,%[re]ax,1) */
653 static const char alt_9[] =
654 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_10[] =
657 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_long_11[] =
662 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 nopw %cs:0L(%[re]ax,%[re]ax,1) */
666 static const char alt_long_12[] =
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_13[] =
678 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 nopw %cs:0L(%[re]ax,%[re]ax,1) */
684 static const char alt_long_14[] =
689 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 nopw %cs:0L(%[re]ax,%[re]ax,1) */
696 static const char alt_long_15[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* nopl 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_11[] =
706 {0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_12[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
715 static const char alt_short_13[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 static const char alt_short_14[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 nopl 0L(%[re]ax,%[re]ax,1) */
725 static const char alt_short_15[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
728 static const char *const alt_short_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
731 alt_short_14, alt_short_15
733 static const char *const alt_long_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
736 alt_long_14, alt_long_15
739 if (count <= 0 || count > 15)
742 /* We need to decide which NOP sequence to use for 32bit and
743 64bit. When -mtune= is used:
745 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
746 f32_patt will be used.
747 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
748 0x66 prefix will be used.
749 3. For PROCESSOR_CORE2, alt_long_patt will be used.
750 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
751 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
752 and PROCESSOR_GENERIC64, alt_short_patt will be used.
754 When -mtune= isn't used, alt_short_patt will be used if
755 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
757 When -march= or .arch is used, we can't use anything beyond
758 cpu_arch_isa_flags. */
760 if (flag_code == CODE_16BIT)
762 memcpy (fragP->fr_literal + fragP->fr_fix,
763 f16_patt[count - 1], count);
765 /* Adjust jump offset. */
766 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
768 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
771 int nnops = (count + 3) / 4;
772 int len = count / nnops;
773 int remains = count - nnops * len;
776 /* The recommended way to pad 64bit code is to use NOPs preceded
777 by maximally four 0x66 prefixes. Balance the size of nops. */
778 for (i = 0; i < remains; i++)
780 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
781 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
784 for (; i < nnops; i++)
786 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
787 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
793 const char *const *patt = NULL;
795 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
797 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
798 switch (cpu_arch_tune)
800 case PROCESSOR_UNKNOWN:
801 /* We use cpu_arch_isa_flags to check if we SHOULD
802 optimize for Cpu686. */
803 if ((cpu_arch_isa_flags & Cpu686) != 0)
804 patt = alt_short_patt;
808 case PROCESSOR_CORE2:
809 patt = alt_long_patt;
811 case PROCESSOR_PENTIUMPRO:
812 case PROCESSOR_PENTIUM4:
813 case PROCESSOR_NOCONA:
816 case PROCESSOR_ATHLON:
818 case PROCESSOR_GENERIC64:
819 case PROCESSOR_AMDFAM10:
820 patt = alt_short_patt;
823 case PROCESSOR_PENTIUM:
824 case PROCESSOR_GENERIC32:
831 switch (cpu_arch_tune)
833 case PROCESSOR_UNKNOWN:
834 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
835 PROCESSOR_UNKNOWN. */
840 case PROCESSOR_PENTIUM:
841 case PROCESSOR_PENTIUMPRO:
842 case PROCESSOR_PENTIUM4:
843 case PROCESSOR_NOCONA:
846 case PROCESSOR_ATHLON:
848 case PROCESSOR_AMDFAM10:
849 case PROCESSOR_GENERIC32:
850 /* We use cpu_arch_isa_flags to check if we CAN optimize
852 if ((cpu_arch_isa_flags & Cpu686) != 0)
853 patt = alt_short_patt;
857 case PROCESSOR_CORE2:
858 if ((cpu_arch_isa_flags & Cpu686) != 0)
859 patt = alt_long_patt;
863 case PROCESSOR_GENERIC64:
864 patt = alt_short_patt;
869 memcpy (fragP->fr_literal + fragP->fr_fix,
870 patt[count - 1], count);
872 fragP->fr_var = count;
875 static INLINE unsigned int
876 mode_from_disp_size (unsigned int t)
878 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
882 fits_in_signed_byte (offsetT num)
884 return (num >= -128) && (num <= 127);
888 fits_in_unsigned_byte (offsetT num)
890 return (num & 0xff) == num;
894 fits_in_unsigned_word (offsetT num)
896 return (num & 0xffff) == num;
900 fits_in_signed_word (offsetT num)
902 return (-32768 <= num) && (num <= 32767);
906 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
911 return (!(((offsetT) -1 << 31) & num)
912 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
914 } /* fits_in_signed_long() */
917 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
922 return (num & (((offsetT) 2 << 31) - 1)) == num;
924 } /* fits_in_unsigned_long() */
927 smallest_imm_type (offsetT num)
929 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
931 /* This code is disabled on the 486 because all the Imm1 forms
932 in the opcode table are slower on the i486. They're the
933 versions with the implicitly specified single-position
934 displacement, which has another syntax if you really want to
937 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
939 return (fits_in_signed_byte (num)
940 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
941 : fits_in_unsigned_byte (num)
942 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
943 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
944 ? (Imm16 | Imm32 | Imm32S | Imm64)
945 : fits_in_signed_long (num)
946 ? (Imm32 | Imm32S | Imm64)
947 : fits_in_unsigned_long (num)
953 offset_in_range (offsetT val, int size)
959 case 1: mask = ((addressT) 1 << 8) - 1; break;
960 case 2: mask = ((addressT) 1 << 16) - 1; break;
961 case 4: mask = ((addressT) 2 << 31) - 1; break;
963 case 8: mask = ((addressT) 2 << 63) - 1; break;
968 /* If BFD64, sign extend val. */
969 if (!use_rela_relocations)
970 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
971 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
973 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
975 char buf1[40], buf2[40];
977 sprint_value (buf1, val);
978 sprint_value (buf2, val & mask);
979 as_warn (_("%s shortened to %s"), buf1, buf2);
984 /* Returns 0 if attempting to add a prefix where one from the same
985 class already exists, 1 if non rep/repne added, 2 if rep/repne
988 add_prefix (unsigned int prefix)
993 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
994 && flag_code == CODE_64BIT)
996 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
997 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
998 && (prefix & (REX_R | REX_X | REX_B))))
1009 case CS_PREFIX_OPCODE:
1010 case DS_PREFIX_OPCODE:
1011 case ES_PREFIX_OPCODE:
1012 case FS_PREFIX_OPCODE:
1013 case GS_PREFIX_OPCODE:
1014 case SS_PREFIX_OPCODE:
1018 case REPNE_PREFIX_OPCODE:
1019 case REPE_PREFIX_OPCODE:
1022 case LOCK_PREFIX_OPCODE:
1030 case ADDR_PREFIX_OPCODE:
1034 case DATA_PREFIX_OPCODE:
1038 if (i.prefix[q] != 0)
1046 i.prefix[q] |= prefix;
1049 as_bad (_("same type of prefix used twice"));
1055 set_code_flag (int value)
1058 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1059 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1060 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1062 as_bad (_("64bit mode not supported on this CPU."));
1064 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1066 as_bad (_("32bit mode not supported on this CPU."));
1068 stackop_size = '\0';
1072 set_16bit_gcc_code_flag (int new_code_flag)
1074 flag_code = new_code_flag;
1075 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1076 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1077 stackop_size = LONG_MNEM_SUFFIX;
1081 set_intel_syntax (int syntax_flag)
1083 /* Find out if register prefixing is specified. */
1084 int ask_naked_reg = 0;
1087 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1089 char *string = input_line_pointer;
1090 int e = get_symbol_end ();
1092 if (strcmp (string, "prefix") == 0)
1094 else if (strcmp (string, "noprefix") == 0)
1097 as_bad (_("bad argument to syntax directive."));
1098 *input_line_pointer = e;
1100 demand_empty_rest_of_line ();
1102 intel_syntax = syntax_flag;
1104 if (ask_naked_reg == 0)
1105 allow_naked_reg = (intel_syntax
1106 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1108 allow_naked_reg = (ask_naked_reg < 0);
1110 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1111 identifier_chars['$'] = intel_syntax ? '$' : 0;
1112 register_prefix = allow_naked_reg ? "" : "%";
1116 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1120 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1122 char *string = input_line_pointer;
1123 int e = get_symbol_end ();
1126 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1128 if (strcmp (string, cpu_arch[i].name) == 0)
1132 cpu_arch_name = cpu_arch[i].name;
1133 cpu_sub_arch_name = NULL;
1134 cpu_arch_flags = (cpu_arch[i].flags
1135 | (flag_code == CODE_64BIT
1136 ? Cpu64 : CpuNo64));
1137 cpu_arch_isa = cpu_arch[i].type;
1138 cpu_arch_isa_flags = cpu_arch[i].flags;
1139 if (!cpu_arch_tune_set)
1141 cpu_arch_tune = cpu_arch_isa;
1142 cpu_arch_tune_flags = cpu_arch_isa_flags;
1146 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1148 cpu_sub_arch_name = cpu_arch[i].name;
1149 cpu_arch_flags |= cpu_arch[i].flags;
1151 *input_line_pointer = e;
1152 demand_empty_rest_of_line ();
1156 if (i >= ARRAY_SIZE (cpu_arch))
1157 as_bad (_("no such architecture: `%s'"), string);
1159 *input_line_pointer = e;
1162 as_bad (_("missing cpu architecture"));
1164 no_cond_jump_promotion = 0;
1165 if (*input_line_pointer == ','
1166 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1168 char *string = ++input_line_pointer;
1169 int e = get_symbol_end ();
1171 if (strcmp (string, "nojumps") == 0)
1172 no_cond_jump_promotion = 1;
1173 else if (strcmp (string, "jumps") == 0)
1176 as_bad (_("no such architecture modifier: `%s'"), string);
1178 *input_line_pointer = e;
1181 demand_empty_rest_of_line ();
1187 if (!strcmp (default_arch, "x86_64"))
1188 return bfd_mach_x86_64;
1189 else if (!strcmp (default_arch, "i386"))
1190 return bfd_mach_i386_i386;
1192 as_fatal (_("Unknown architecture"));
1198 const char *hash_err;
1200 /* Initialize op_hash hash table. */
1201 op_hash = hash_new ();
1204 const template *optab;
1205 templates *core_optab;
1207 /* Setup for loop. */
1209 core_optab = (templates *) xmalloc (sizeof (templates));
1210 core_optab->start = optab;
1215 if (optab->name == NULL
1216 || strcmp (optab->name, (optab - 1)->name) != 0)
1218 /* different name --> ship out current template list;
1219 add to hash table; & begin anew. */
1220 core_optab->end = optab;
1221 hash_err = hash_insert (op_hash,
1226 as_fatal (_("Internal Error: Can't hash %s: %s"),
1230 if (optab->name == NULL)
1232 core_optab = (templates *) xmalloc (sizeof (templates));
1233 core_optab->start = optab;
1238 /* Initialize reg_hash hash table. */
1239 reg_hash = hash_new ();
1241 const reg_entry *regtab;
1242 unsigned int regtab_size = i386_regtab_size;
1244 for (regtab = i386_regtab; regtab_size--; regtab++)
1246 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1248 as_fatal (_("Internal Error: Can't hash %s: %s"),
1254 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1259 for (c = 0; c < 256; c++)
1264 mnemonic_chars[c] = c;
1265 register_chars[c] = c;
1266 operand_chars[c] = c;
1268 else if (ISLOWER (c))
1270 mnemonic_chars[c] = c;
1271 register_chars[c] = c;
1272 operand_chars[c] = c;
1274 else if (ISUPPER (c))
1276 mnemonic_chars[c] = TOLOWER (c);
1277 register_chars[c] = mnemonic_chars[c];
1278 operand_chars[c] = c;
1281 if (ISALPHA (c) || ISDIGIT (c))
1282 identifier_chars[c] = c;
1285 identifier_chars[c] = c;
1286 operand_chars[c] = c;
1291 identifier_chars['@'] = '@';
1294 identifier_chars['?'] = '?';
1295 operand_chars['?'] = '?';
1297 digit_chars['-'] = '-';
1298 mnemonic_chars['-'] = '-';
1299 mnemonic_chars['.'] = '.';
1300 identifier_chars['_'] = '_';
1301 identifier_chars['.'] = '.';
1303 for (p = operand_special_chars; *p != '\0'; p++)
1304 operand_chars[(unsigned char) *p] = *p;
1307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1310 record_alignment (text_section, 2);
1311 record_alignment (data_section, 2);
1312 record_alignment (bss_section, 2);
1316 if (flag_code == CODE_64BIT)
1318 x86_dwarf2_return_column = 16;
1319 x86_cie_data_alignment = -8;
1323 x86_dwarf2_return_column = 8;
1324 x86_cie_data_alignment = -4;
1329 i386_print_statistics (FILE *file)
1331 hash_print_statistics (file, "i386 opcode", op_hash);
1332 hash_print_statistics (file, "i386 register", reg_hash);
1337 /* Debugging routines for md_assemble. */
1338 static void pte (template *);
1339 static void pt (unsigned int);
1340 static void pe (expressionS *);
1341 static void ps (symbolS *);
1344 pi (char *line, i386_insn *x)
1348 fprintf (stdout, "%s: template ", line);
1350 fprintf (stdout, " address: base %s index %s scale %x\n",
1351 x->base_reg ? x->base_reg->reg_name : "none",
1352 x->index_reg ? x->index_reg->reg_name : "none",
1353 x->log2_scale_factor);
1354 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1355 x->rm.mode, x->rm.reg, x->rm.regmem);
1356 fprintf (stdout, " sib: base %x index %x scale %x\n",
1357 x->sib.base, x->sib.index, x->sib.scale);
1358 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1359 (x->rex & REX_W) != 0,
1360 (x->rex & REX_R) != 0,
1361 (x->rex & REX_X) != 0,
1362 (x->rex & REX_B) != 0);
1363 for (i = 0; i < x->operands; i++)
1365 fprintf (stdout, " #%d: ", i + 1);
1367 fprintf (stdout, "\n");
1369 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1370 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1371 if (x->types[i] & Imm)
1373 if (x->types[i] & Disp)
1374 pe (x->op[i].disps);
1382 fprintf (stdout, " %d operands ", t->operands);
1383 fprintf (stdout, "opcode %x ", t->base_opcode);
1384 if (t->extension_opcode != None)
1385 fprintf (stdout, "ext %x ", t->extension_opcode);
1386 if (t->opcode_modifier & D)
1387 fprintf (stdout, "D");
1388 if (t->opcode_modifier & W)
1389 fprintf (stdout, "W");
1390 fprintf (stdout, "\n");
1391 for (i = 0; i < t->operands; i++)
1393 fprintf (stdout, " #%d type ", i + 1);
1394 pt (t->operand_types[i]);
1395 fprintf (stdout, "\n");
1402 fprintf (stdout, " operation %d\n", e->X_op);
1403 fprintf (stdout, " add_number %ld (%lx)\n",
1404 (long) e->X_add_number, (long) e->X_add_number);
1405 if (e->X_add_symbol)
1407 fprintf (stdout, " add_symbol ");
1408 ps (e->X_add_symbol);
1409 fprintf (stdout, "\n");
1413 fprintf (stdout, " op_symbol ");
1414 ps (e->X_op_symbol);
1415 fprintf (stdout, "\n");
1422 fprintf (stdout, "%s type %s%s",
1424 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1425 segment_name (S_GET_SEGMENT (s)));
1428 static struct type_name
1433 const type_names[] =
1446 { BaseIndex, "BaseIndex" },
1450 { Disp32S, "d32s" },
1452 { InOutPortReg, "InOutPortReg" },
1453 { ShiftCount, "ShiftCount" },
1454 { Control, "control reg" },
1455 { Test, "test reg" },
1456 { Debug, "debug reg" },
1457 { FloatReg, "FReg" },
1458 { FloatAcc, "FAcc" },
1462 { JumpAbsolute, "Jump Absolute" },
1473 const struct type_name *ty;
1475 for (ty = type_names; ty->mask; ty++)
1477 fprintf (stdout, "%s, ", ty->tname);
1481 #endif /* DEBUG386 */
1483 static bfd_reloc_code_real_type
1484 reloc (unsigned int size,
1487 bfd_reloc_code_real_type other)
1489 if (other != NO_RELOC)
1491 reloc_howto_type *reloc;
1496 case BFD_RELOC_X86_64_GOT32:
1497 return BFD_RELOC_X86_64_GOT64;
1499 case BFD_RELOC_X86_64_PLTOFF64:
1500 return BFD_RELOC_X86_64_PLTOFF64;
1502 case BFD_RELOC_X86_64_GOTPC32:
1503 other = BFD_RELOC_X86_64_GOTPC64;
1505 case BFD_RELOC_X86_64_GOTPCREL:
1506 other = BFD_RELOC_X86_64_GOTPCREL64;
1508 case BFD_RELOC_X86_64_TPOFF32:
1509 other = BFD_RELOC_X86_64_TPOFF64;
1511 case BFD_RELOC_X86_64_DTPOFF32:
1512 other = BFD_RELOC_X86_64_DTPOFF64;
1518 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1519 if (size == 4 && flag_code != CODE_64BIT)
1522 reloc = bfd_reloc_type_lookup (stdoutput, other);
1524 as_bad (_("unknown relocation (%u)"), other);
1525 else if (size != bfd_get_reloc_size (reloc))
1526 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1527 bfd_get_reloc_size (reloc),
1529 else if (pcrel && !reloc->pc_relative)
1530 as_bad (_("non-pc-relative relocation for pc-relative field"));
1531 else if ((reloc->complain_on_overflow == complain_overflow_signed
1533 || (reloc->complain_on_overflow == complain_overflow_unsigned
1535 as_bad (_("relocated field and relocation type differ in signedness"));
1544 as_bad (_("there are no unsigned pc-relative relocations"));
1547 case 1: return BFD_RELOC_8_PCREL;
1548 case 2: return BFD_RELOC_16_PCREL;
1549 case 4: return BFD_RELOC_32_PCREL;
1550 case 8: return BFD_RELOC_64_PCREL;
1552 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1559 case 4: return BFD_RELOC_X86_64_32S;
1564 case 1: return BFD_RELOC_8;
1565 case 2: return BFD_RELOC_16;
1566 case 4: return BFD_RELOC_32;
1567 case 8: return BFD_RELOC_64;
1569 as_bad (_("cannot do %s %u byte relocation"),
1570 sign > 0 ? "signed" : "unsigned", size);
1574 return BFD_RELOC_NONE;
1577 /* Here we decide which fixups can be adjusted to make them relative to
1578 the beginning of the section instead of the symbol. Basically we need
1579 to make sure that the dynamic relocations are done correctly, so in
1580 some cases we force the original symbol to be used. */
1583 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
1585 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1589 /* Don't adjust pc-relative references to merge sections in 64-bit
1591 if (use_rela_relocations
1592 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1596 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1597 and changed later by validate_fix. */
1598 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1599 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1602 /* adjust_reloc_syms doesn't know about the GOT. */
1603 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1604 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1605 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1616 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1626 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1629 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1630 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1637 intel_float_operand (const char *mnemonic)
1639 /* Note that the value returned is meaningful only for opcodes with (memory)
1640 operands, hence the code here is free to improperly handle opcodes that
1641 have no operands (for better performance and smaller code). */
1643 if (mnemonic[0] != 'f')
1644 return 0; /* non-math */
1646 switch (mnemonic[1])
1648 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1649 the fs segment override prefix not currently handled because no
1650 call path can make opcodes without operands get here */
1652 return 2 /* integer op */;
1654 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1655 return 3; /* fldcw/fldenv */
1658 if (mnemonic[2] != 'o' /* fnop */)
1659 return 3; /* non-waiting control op */
1662 if (mnemonic[2] == 's')
1663 return 3; /* frstor/frstpm */
1666 if (mnemonic[2] == 'a')
1667 return 3; /* fsave */
1668 if (mnemonic[2] == 't')
1670 switch (mnemonic[3])
1672 case 'c': /* fstcw */
1673 case 'd': /* fstdw */
1674 case 'e': /* fstenv */
1675 case 's': /* fsts[gw] */
1681 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1682 return 0; /* fxsave/fxrstor are not really math ops */
1689 /* This is the guts of the machine-dependent assembler. LINE points to a
1690 machine dependent instruction. This function is supposed to emit
1691 the frags/bytes it assembles to. */
1698 char mnemonic[MAX_MNEM_SIZE];
1700 /* Initialize globals. */
1701 memset (&i, '\0', sizeof (i));
1702 for (j = 0; j < MAX_OPERANDS; j++)
1703 i.reloc[j] = NO_RELOC;
1704 memset (disp_expressions, '\0', sizeof (disp_expressions));
1705 memset (im_expressions, '\0', sizeof (im_expressions));
1706 save_stack_p = save_stack;
1708 /* First parse an instruction mnemonic & call i386_operand for the operands.
1709 We assume that the scrubber has arranged it so that line[0] is the valid
1710 start of a (possibly prefixed) mnemonic. */
1712 line = parse_insn (line, mnemonic);
1716 line = parse_operands (line, mnemonic);
1720 /* The order of the immediates should be reversed
1721 for 2 immediates extrq and insertq instructions */
1722 if ((i.imm_operands == 2)
1723 && ((strcmp (mnemonic, "extrq") == 0)
1724 || (strcmp (mnemonic, "insertq") == 0)))
1726 swap_2_operands (0, 1);
1727 /* "extrq" and insertq" are the only two instructions whose operands
1728 have to be reversed even though they have two immediate operands.
1734 /* Now we've parsed the mnemonic into a set of templates, and have the
1735 operands at hand. */
1737 /* All intel opcodes have reversed operands except for "bound" and
1738 "enter". We also don't reverse intersegment "jmp" and "call"
1739 instructions with 2 immediate operands so that the immediate segment
1740 precedes the offset, as it does when in AT&T mode. */
1743 && (strcmp (mnemonic, "bound") != 0)
1744 && (strcmp (mnemonic, "invlpga") != 0)
1745 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1751 /* Don't optimize displacement for movabs since it only takes 64bit
1754 && (flag_code != CODE_64BIT
1755 || strcmp (mnemonic, "movabs") != 0))
1758 /* Next, we find a template that matches the given insn,
1759 making sure the overlap of the given operands types is consistent
1760 with the template operand types. */
1762 if (!match_template ())
1767 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1769 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1770 i.tm.base_opcode ^= Opcode_FloatR;
1772 /* Zap movzx and movsx suffix. The suffix may have been set from
1773 "word ptr" or "byte ptr" on the source operand, but we'll use
1774 the suffix later to choose the destination register. */
1775 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1777 if (i.reg_operands < 2
1779 && (~i.tm.opcode_modifier
1786 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1792 if (i.tm.opcode_modifier & FWait)
1793 if (!add_prefix (FWAIT_OPCODE))
1796 /* Check string instruction segment overrides. */
1797 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1799 if (!check_string ())
1803 if (!process_suffix ())
1806 /* Make still unresolved immediate matches conform to size of immediate
1807 given in i.suffix. */
1808 if (!finalize_imm ())
1811 if (i.types[0] & Imm1)
1812 i.imm_operands = 0; /* kludge for shift insns. */
1813 if (i.types[0] & ImplicitRegister)
1815 if (i.types[1] & ImplicitRegister)
1817 if (i.types[2] & ImplicitRegister)
1820 if (i.tm.opcode_modifier & ImmExt)
1824 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1826 /* Streaming SIMD extensions 3 Instructions have the fixed
1827 operands with an opcode suffix which is coded in the same
1828 place as an 8-bit immediate field would be. Here we check
1829 those operands and remove them afterwards. */
1832 for (x = 0; x < i.operands; x++)
1833 if (i.op[x].regs->reg_num != x)
1834 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1835 i.op[x].regs->reg_name, x + 1, i.tm.name);
1839 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1840 opcode suffix which is coded in the same place as an 8-bit
1841 immediate field would be. Here we fake an 8-bit immediate
1842 operand from the opcode suffix stored in tm.extension_opcode. */
1844 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1846 exp = &im_expressions[i.imm_operands++];
1847 i.op[i.operands].imms = exp;
1848 i.types[i.operands++] = Imm8;
1849 exp->X_op = O_constant;
1850 exp->X_add_number = i.tm.extension_opcode;
1851 i.tm.extension_opcode = None;
1854 /* For insns with operands there are more diddles to do to the opcode. */
1857 if (!process_operands ())
1860 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1862 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1863 as_warn (_("translating to `%sp'"), i.tm.name);
1866 /* Handle conversion of 'int $3' --> special int3 insn. */
1867 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1869 i.tm.base_opcode = INT3_OPCODE;
1873 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1874 && i.op[0].disps->X_op == O_constant)
1876 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1877 the absolute address given by the constant. Since ix86 jumps and
1878 calls are pc relative, we need to generate a reloc. */
1879 i.op[0].disps->X_add_symbol = &abs_symbol;
1880 i.op[0].disps->X_op = O_symbol;
1883 if ((i.tm.opcode_modifier & Rex64) != 0)
1886 /* For 8 bit registers we need an empty rex prefix. Also if the
1887 instruction already has a prefix, we need to convert old
1888 registers to new ones. */
1890 if (((i.types[0] & Reg8) != 0
1891 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1892 || ((i.types[1] & Reg8) != 0
1893 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1894 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1899 i.rex |= REX_OPCODE;
1900 for (x = 0; x < 2; x++)
1902 /* Look for 8 bit operand that uses old registers. */
1903 if ((i.types[x] & Reg8) != 0
1904 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1906 /* In case it is "hi" register, give up. */
1907 if (i.op[x].regs->reg_num > 3)
1908 as_bad (_("can't encode register '%%%s' in an "
1909 "instruction requiring REX prefix."),
1910 i.op[x].regs->reg_name);
1912 /* Otherwise it is equivalent to the extended register.
1913 Since the encoding doesn't change this is merely
1914 cosmetic cleanup for debug output. */
1916 i.op[x].regs = i.op[x].regs + 8;
1922 add_prefix (REX_OPCODE | i.rex);
1924 /* We are ready to output the insn. */
1929 parse_insn (char *line, char *mnemonic)
1932 char *token_start = l;
1937 /* Non-zero if we found a prefix only acceptable with string insns. */
1938 const char *expecting_string_instruction = NULL;
1943 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1946 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1948 as_bad (_("no such instruction: `%s'"), token_start);
1953 if (!is_space_char (*l)
1954 && *l != END_OF_INSN
1956 || (*l != PREFIX_SEPARATOR
1959 as_bad (_("invalid character %s in mnemonic"),
1960 output_invalid (*l));
1963 if (token_start == l)
1965 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1966 as_bad (_("expecting prefix; got nothing"));
1968 as_bad (_("expecting mnemonic; got nothing"));
1972 /* Look up instruction (or prefix) via hash table. */
1973 current_templates = hash_find (op_hash, mnemonic);
1975 if (*l != END_OF_INSN
1976 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1977 && current_templates
1978 && (current_templates->start->opcode_modifier & IsPrefix))
1980 if (current_templates->start->cpu_flags
1981 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1983 as_bad ((flag_code != CODE_64BIT
1984 ? _("`%s' is only supported in 64-bit mode")
1985 : _("`%s' is not supported in 64-bit mode")),
1986 current_templates->start->name);
1989 /* If we are in 16-bit mode, do not allow addr16 or data16.
1990 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1991 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1992 && flag_code != CODE_64BIT
1993 && (((current_templates->start->opcode_modifier & Size32) != 0)
1994 ^ (flag_code == CODE_16BIT)))
1996 as_bad (_("redundant %s prefix"),
1997 current_templates->start->name);
2000 /* Add prefix, checking for repeated prefixes. */
2001 switch (add_prefix (current_templates->start->base_opcode))
2006 expecting_string_instruction = current_templates->start->name;
2009 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2016 if (!current_templates)
2018 /* See if we can get a match by trimming off a suffix. */
2021 case WORD_MNEM_SUFFIX:
2022 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2023 i.suffix = SHORT_MNEM_SUFFIX;
2025 case BYTE_MNEM_SUFFIX:
2026 case QWORD_MNEM_SUFFIX:
2027 i.suffix = mnem_p[-1];
2029 current_templates = hash_find (op_hash, mnemonic);
2031 case SHORT_MNEM_SUFFIX:
2032 case LONG_MNEM_SUFFIX:
2035 i.suffix = mnem_p[-1];
2037 current_templates = hash_find (op_hash, mnemonic);
2045 if (intel_float_operand (mnemonic) == 1)
2046 i.suffix = SHORT_MNEM_SUFFIX;
2048 i.suffix = LONG_MNEM_SUFFIX;
2050 current_templates = hash_find (op_hash, mnemonic);
2054 if (!current_templates)
2056 as_bad (_("no such instruction: `%s'"), token_start);
2061 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2063 /* Check for a branch hint. We allow ",pt" and ",pn" for
2064 predict taken and predict not taken respectively.
2065 I'm not sure that branch hints actually do anything on loop
2066 and jcxz insns (JumpByte) for current Pentium4 chips. They
2067 may work in the future and it doesn't hurt to accept them
2069 if (l[0] == ',' && l[1] == 'p')
2073 if (!add_prefix (DS_PREFIX_OPCODE))
2077 else if (l[2] == 'n')
2079 if (!add_prefix (CS_PREFIX_OPCODE))
2085 /* Any other comma loses. */
2088 as_bad (_("invalid character %s in mnemonic"),
2089 output_invalid (*l));
2093 /* Check if instruction is supported on specified architecture. */
2095 for (t = current_templates->start; t < current_templates->end; ++t)
2097 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2098 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2100 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2103 if (!(supported & 2))
2105 as_bad (flag_code == CODE_64BIT
2106 ? _("`%s' is not supported in 64-bit mode")
2107 : _("`%s' is only supported in 64-bit mode"),
2108 current_templates->start->name);
2111 if (!(supported & 1))
2113 as_warn (_("`%s' is not supported on `%s%s'"),
2114 current_templates->start->name,
2116 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2118 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2120 as_warn (_("use .code16 to ensure correct addressing mode"));
2123 /* Check for rep/repne without a string instruction. */
2124 if (expecting_string_instruction)
2126 static templates override;
2128 for (t = current_templates->start; t < current_templates->end; ++t)
2129 if (t->opcode_modifier & IsString)
2131 if (t >= current_templates->end)
2133 as_bad (_("expecting string instruction after `%s'"),
2134 expecting_string_instruction);
2137 for (override.start = t; t < current_templates->end; ++t)
2138 if (!(t->opcode_modifier & IsString))
2141 current_templates = &override;
2148 parse_operands (char *l, const char *mnemonic)
2152 /* 1 if operand is pending after ','. */
2153 unsigned int expecting_operand = 0;
2155 /* Non-zero if operand parens not balanced. */
2156 unsigned int paren_not_balanced;
2158 while (*l != END_OF_INSN)
2160 /* Skip optional white space before operand. */
2161 if (is_space_char (*l))
2163 if (!is_operand_char (*l) && *l != END_OF_INSN)
2165 as_bad (_("invalid character %s before operand %d"),
2166 output_invalid (*l),
2170 token_start = l; /* after white space */
2171 paren_not_balanced = 0;
2172 while (paren_not_balanced || *l != ',')
2174 if (*l == END_OF_INSN)
2176 if (paren_not_balanced)
2179 as_bad (_("unbalanced parenthesis in operand %d."),
2182 as_bad (_("unbalanced brackets in operand %d."),
2187 break; /* we are done */
2189 else if (!is_operand_char (*l) && !is_space_char (*l))
2191 as_bad (_("invalid character %s in operand %d"),
2192 output_invalid (*l),
2199 ++paren_not_balanced;
2201 --paren_not_balanced;
2206 ++paren_not_balanced;
2208 --paren_not_balanced;
2212 if (l != token_start)
2213 { /* Yes, we've read in another operand. */
2214 unsigned int operand_ok;
2215 this_operand = i.operands++;
2216 if (i.operands > MAX_OPERANDS)
2218 as_bad (_("spurious operands; (%d operands/instruction max)"),
2222 /* Now parse operand adding info to 'i' as we go along. */
2223 END_STRING_AND_SAVE (l);
2227 i386_intel_operand (token_start,
2228 intel_float_operand (mnemonic));
2230 operand_ok = i386_operand (token_start);
2232 RESTORE_END_STRING (l);
2238 if (expecting_operand)
2240 expecting_operand_after_comma:
2241 as_bad (_("expecting operand after ','; got nothing"));
2246 as_bad (_("expecting operand before ','; got nothing"));
2251 /* Now *l must be either ',' or END_OF_INSN. */
2254 if (*++l == END_OF_INSN)
2256 /* Just skip it, if it's \n complain. */
2257 goto expecting_operand_after_comma;
2259 expecting_operand = 1;
2266 swap_2_operands (int xchg1, int xchg2)
2268 union i386_op temp_op;
2269 unsigned int temp_type;
2270 enum bfd_reloc_code_real temp_reloc;
2272 temp_type = i.types[xchg2];
2273 i.types[xchg2] = i.types[xchg1];
2274 i.types[xchg1] = temp_type;
2275 temp_op = i.op[xchg2];
2276 i.op[xchg2] = i.op[xchg1];
2277 i.op[xchg1] = temp_op;
2278 temp_reloc = i.reloc[xchg2];
2279 i.reloc[xchg2] = i.reloc[xchg1];
2280 i.reloc[xchg1] = temp_reloc;
2284 swap_operands (void)
2289 swap_2_operands (1, i.operands - 2);
2292 swap_2_operands (0, i.operands - 1);
2298 if (i.mem_operands == 2)
2300 const seg_entry *temp_seg;
2301 temp_seg = i.seg[0];
2302 i.seg[0] = i.seg[1];
2303 i.seg[1] = temp_seg;
2307 /* Try to ensure constant immediates are represented in the smallest
2312 char guess_suffix = 0;
2316 guess_suffix = i.suffix;
2317 else if (i.reg_operands)
2319 /* Figure out a suffix from the last register operand specified.
2320 We can't do this properly yet, ie. excluding InOutPortReg,
2321 but the following works for instructions with immediates.
2322 In any case, we can't set i.suffix yet. */
2323 for (op = i.operands; --op >= 0;)
2324 if (i.types[op] & Reg)
2326 if (i.types[op] & Reg8)
2327 guess_suffix = BYTE_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg16)
2329 guess_suffix = WORD_MNEM_SUFFIX;
2330 else if (i.types[op] & Reg32)
2331 guess_suffix = LONG_MNEM_SUFFIX;
2332 else if (i.types[op] & Reg64)
2333 guess_suffix = QWORD_MNEM_SUFFIX;
2337 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2338 guess_suffix = WORD_MNEM_SUFFIX;
2340 for (op = i.operands; --op >= 0;)
2341 if (i.types[op] & Imm)
2343 switch (i.op[op].imms->X_op)
2346 /* If a suffix is given, this operand may be shortened. */
2347 switch (guess_suffix)
2349 case LONG_MNEM_SUFFIX:
2350 i.types[op] |= Imm32 | Imm64;
2352 case WORD_MNEM_SUFFIX:
2353 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2355 case BYTE_MNEM_SUFFIX:
2356 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2360 /* If this operand is at most 16 bits, convert it
2361 to a signed 16 bit number before trying to see
2362 whether it will fit in an even smaller size.
2363 This allows a 16-bit operand such as $0xffe0 to
2364 be recognised as within Imm8S range. */
2365 if ((i.types[op] & Imm16)
2366 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2368 i.op[op].imms->X_add_number =
2369 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2371 if ((i.types[op] & Imm32)
2372 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2375 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2376 ^ ((offsetT) 1 << 31))
2377 - ((offsetT) 1 << 31));
2379 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2381 /* We must avoid matching of Imm32 templates when 64bit
2382 only immediate is available. */
2383 if (guess_suffix == QWORD_MNEM_SUFFIX)
2384 i.types[op] &= ~Imm32;
2391 /* Symbols and expressions. */
2393 /* Convert symbolic operand to proper sizes for matching, but don't
2394 prevent matching a set of insns that only supports sizes other
2395 than those matching the insn suffix. */
2397 unsigned int mask, allowed = 0;
2400 for (t = current_templates->start;
2401 t < current_templates->end;
2403 allowed |= t->operand_types[op];
2404 switch (guess_suffix)
2406 case QWORD_MNEM_SUFFIX:
2407 mask = Imm64 | Imm32S;
2409 case LONG_MNEM_SUFFIX:
2412 case WORD_MNEM_SUFFIX:
2415 case BYTE_MNEM_SUFFIX:
2423 i.types[op] &= mask;
2430 /* Try to use the smallest displacement type too. */
2432 optimize_disp (void)
2436 for (op = i.operands; --op >= 0;)
2437 if (i.types[op] & Disp)
2439 if (i.op[op].disps->X_op == O_constant)
2441 offsetT disp = i.op[op].disps->X_add_number;
2443 if ((i.types[op] & Disp16)
2444 && (disp & ~(offsetT) 0xffff) == 0)
2446 /* If this operand is at most 16 bits, convert
2447 to a signed 16 bit number and don't use 64bit
2449 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2450 i.types[op] &= ~Disp64;
2452 if ((i.types[op] & Disp32)
2453 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2455 /* If this operand is at most 32 bits, convert
2456 to a signed 32 bit number and don't use 64bit
2458 disp &= (((offsetT) 2 << 31) - 1);
2459 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2460 i.types[op] &= ~Disp64;
2462 if (!disp && (i.types[op] & BaseIndex))
2464 i.types[op] &= ~Disp;
2468 else if (flag_code == CODE_64BIT)
2470 if (fits_in_signed_long (disp))
2472 i.types[op] &= ~Disp64;
2473 i.types[op] |= Disp32S;
2475 if (fits_in_unsigned_long (disp))
2476 i.types[op] |= Disp32;
2478 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2479 && fits_in_signed_byte (disp))
2480 i.types[op] |= Disp8;
2482 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2483 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2485 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2486 i.op[op].disps, 0, i.reloc[op]);
2487 i.types[op] &= ~Disp;
2490 /* We only support 64bit displacement on constants. */
2491 i.types[op] &= ~Disp64;
2496 match_template (void)
2498 /* Points to template once we've found it. */
2500 unsigned int overlap0, overlap1, overlap2, overlap3;
2501 unsigned int found_reverse_match;
2503 unsigned int operand_types [MAX_OPERANDS];
2504 int addr_prefix_disp;
2507 #if MAX_OPERANDS != 4
2508 # error "MAX_OPERANDS must be 4."
2511 #define MATCH(overlap, given, template) \
2512 ((overlap & ~JumpAbsolute) \
2513 && (((given) & (BaseIndex | JumpAbsolute)) \
2514 == ((overlap) & (BaseIndex | JumpAbsolute))))
2516 /* If given types r0 and r1 are registers they must be of the same type
2517 unless the expected operand type register overlap is null.
2518 Note that Acc in a template matches every size of reg. */
2519 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2520 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2521 || ((g0) & Reg) == ((g1) & Reg) \
2522 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2528 found_reverse_match = 0;
2529 for (j = 0; j < MAX_OPERANDS; j++)
2530 operand_types [j] = 0;
2531 addr_prefix_disp = -1;
2532 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2534 : (i.suffix == WORD_MNEM_SUFFIX
2536 : (i.suffix == SHORT_MNEM_SUFFIX
2538 : (i.suffix == LONG_MNEM_SUFFIX
2540 : (i.suffix == QWORD_MNEM_SUFFIX
2542 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2543 ? No_xSuf : 0))))));
2545 for (t = current_templates->start; t < current_templates->end; t++)
2547 addr_prefix_disp = -1;
2549 /* Must have right number of operands. */
2550 if (i.operands != t->operands)
2553 /* Check the suffix, except for some instructions in intel mode. */
2554 if ((t->opcode_modifier & suffix_check)
2556 && (t->opcode_modifier & IgnoreSize)))
2559 for (j = 0; j < MAX_OPERANDS; j++)
2560 operand_types [j] = t->operand_types [j];
2562 /* In general, don't allow 64-bit operands in 32-bit mode. */
2563 if (i.suffix == QWORD_MNEM_SUFFIX
2564 && flag_code != CODE_64BIT
2566 ? (!(t->opcode_modifier & IgnoreSize)
2567 && !intel_float_operand (t->name))
2568 : intel_float_operand (t->name) != 2)
2569 && (!(operand_types[0] & (RegMMX | RegXMM))
2570 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2571 && (t->base_opcode != 0x0fc7
2572 || t->extension_opcode != 1 /* cmpxchg8b */))
2575 /* Do not verify operands when there are none. */
2576 else if (!t->operands)
2578 if (t->cpu_flags & ~cpu_arch_flags)
2580 /* We've found a match; break out of loop. */
2584 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2585 into Disp32/Disp16/Disp32 operand. */
2586 if (i.prefix[ADDR_PREFIX] != 0)
2588 unsigned int DispOn = 0, DispOff = 0;
2606 for (j = 0; j < MAX_OPERANDS; j++)
2608 /* There should be only one Disp operand. */
2609 if ((operand_types[j] & DispOff))
2611 addr_prefix_disp = j;
2612 operand_types[j] |= DispOn;
2613 operand_types[j] &= ~DispOff;
2619 overlap0 = i.types[0] & operand_types[0];
2620 switch (t->operands)
2623 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2627 /* xchg %eax, %eax is a special case. It is an aliase for nop
2628 only in 32bit mode and we can use opcode 0x90. In 64bit
2629 mode, we can't use 0x90 for xchg %eax, %eax since it should
2630 zero-extend %eax to %rax. */
2631 if (flag_code == CODE_64BIT
2632 && t->base_opcode == 0x90
2633 && i.types [0] == (Acc | Reg32)
2634 && i.types [1] == (Acc | Reg32))
2638 overlap1 = i.types[1] & operand_types[1];
2639 if (!MATCH (overlap0, i.types[0], operand_types[0])
2640 || !MATCH (overlap1, i.types[1], operand_types[1])
2641 /* monitor in SSE3 is a very special case. The first
2642 register and the second register may have different
2644 || !((t->base_opcode == 0x0f01
2645 && t->extension_opcode == 0xc8)
2646 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2648 overlap1, i.types[1],
2651 /* Check if other direction is valid ... */
2652 if ((t->opcode_modifier & (D | FloatD)) == 0)
2655 /* Try reversing direction of operands. */
2656 overlap0 = i.types[0] & operand_types[1];
2657 overlap1 = i.types[1] & operand_types[0];
2658 if (!MATCH (overlap0, i.types[0], operand_types[1])
2659 || !MATCH (overlap1, i.types[1], operand_types[0])
2660 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2662 overlap1, i.types[1],
2665 /* Does not match either direction. */
2668 /* found_reverse_match holds which of D or FloatDR
2670 if ((t->opcode_modifier & D))
2671 found_reverse_match = Opcode_D;
2672 else if ((t->opcode_modifier & FloatD))
2673 found_reverse_match = Opcode_FloatD;
2675 found_reverse_match = 0;
2676 if ((t->opcode_modifier & FloatR))
2677 found_reverse_match |= Opcode_FloatR;
2681 /* Found a forward 2 operand match here. */
2682 switch (t->operands)
2685 overlap3 = i.types[3] & operand_types[3];
2687 overlap2 = i.types[2] & operand_types[2];
2691 switch (t->operands)
2694 if (!MATCH (overlap3, i.types[3], operand_types[3])
2695 || !CONSISTENT_REGISTER_MATCH (overlap2,
2703 /* Here we make use of the fact that there are no
2704 reverse match 3 operand instructions, and all 3
2705 operand instructions only need to be checked for
2706 register consistency between operands 2 and 3. */
2707 if (!MATCH (overlap2, i.types[2], operand_types[2])
2708 || !CONSISTENT_REGISTER_MATCH (overlap1,
2718 /* Found either forward/reverse 2, 3 or 4 operand match here:
2719 slip through to break. */
2721 if (t->cpu_flags & ~cpu_arch_flags)
2723 found_reverse_match = 0;
2726 /* We've found a match; break out of loop. */
2730 if (t == current_templates->end)
2732 /* We found no match. */
2733 as_bad (_("suffix or operands invalid for `%s'"),
2734 current_templates->start->name);
2738 if (!quiet_warnings)
2741 && ((i.types[0] & JumpAbsolute)
2742 != (operand_types[0] & JumpAbsolute)))
2744 as_warn (_("indirect %s without `*'"), t->name);
2747 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2748 == (IsPrefix | IgnoreSize))
2750 /* Warn them that a data or address size prefix doesn't
2751 affect assembly of the next line of code. */
2752 as_warn (_("stand-alone `%s' prefix"), t->name);
2756 /* Copy the template we found. */
2759 if (addr_prefix_disp != -1)
2760 i.tm.operand_types[addr_prefix_disp]
2761 = operand_types[addr_prefix_disp];
2763 if (found_reverse_match)
2765 /* If we found a reverse match we must alter the opcode
2766 direction bit. found_reverse_match holds bits to change
2767 (different for int & float insns). */
2769 i.tm.base_opcode ^= found_reverse_match;
2771 i.tm.operand_types[0] = operand_types[1];
2772 i.tm.operand_types[1] = operand_types[0];
2781 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2782 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2784 if (i.seg[0] != NULL && i.seg[0] != &es)
2786 as_bad (_("`%s' operand %d must use `%%es' segment"),
2791 /* There's only ever one segment override allowed per instruction.
2792 This instruction possibly has a legal segment override on the
2793 second operand, so copy the segment to where non-string
2794 instructions store it, allowing common code. */
2795 i.seg[0] = i.seg[1];
2797 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2799 if (i.seg[1] != NULL && i.seg[1] != &es)
2801 as_bad (_("`%s' operand %d must use `%%es' segment"),
2811 process_suffix (void)
2813 /* If matched instruction specifies an explicit instruction mnemonic
2815 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2817 if (i.tm.opcode_modifier & Size16)
2818 i.suffix = WORD_MNEM_SUFFIX;
2819 else if (i.tm.opcode_modifier & Size64)
2820 i.suffix = QWORD_MNEM_SUFFIX;
2822 i.suffix = LONG_MNEM_SUFFIX;
2824 else if (i.reg_operands)
2826 /* If there's no instruction mnemonic suffix we try to invent one
2827 based on register operands. */
2830 /* We take i.suffix from the last register operand specified,
2831 Destination register type is more significant than source
2835 for (op = i.operands; --op >= 0;)
2836 if ((i.types[op] & Reg)
2837 && !(i.tm.operand_types[op] & InOutPortReg))
2839 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2840 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2841 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2846 else if (i.suffix == BYTE_MNEM_SUFFIX)
2848 if (!check_byte_reg ())
2851 else if (i.suffix == LONG_MNEM_SUFFIX)
2853 if (!check_long_reg ())
2856 else if (i.suffix == QWORD_MNEM_SUFFIX)
2858 if (!check_qword_reg ())
2861 else if (i.suffix == WORD_MNEM_SUFFIX)
2863 if (!check_word_reg ())
2866 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2867 /* Do nothing if the instruction is going to ignore the prefix. */
2872 else if ((i.tm.opcode_modifier & DefaultSize)
2874 /* exclude fldenv/frstor/fsave/fstenv */
2875 && (i.tm.opcode_modifier & No_sSuf))
2877 i.suffix = stackop_size;
2879 else if (intel_syntax
2881 && ((i.tm.operand_types[0] & JumpAbsolute)
2882 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2883 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2884 && i.tm.extension_opcode <= 3)))
2889 if (!(i.tm.opcode_modifier & No_qSuf))
2891 i.suffix = QWORD_MNEM_SUFFIX;
2895 if (!(i.tm.opcode_modifier & No_lSuf))
2896 i.suffix = LONG_MNEM_SUFFIX;
2899 if (!(i.tm.opcode_modifier & No_wSuf))
2900 i.suffix = WORD_MNEM_SUFFIX;
2909 if (i.tm.opcode_modifier & W)
2911 as_bad (_("no instruction mnemonic suffix given and "
2912 "no register operands; can't size instruction"));
2918 unsigned int suffixes = (~i.tm.opcode_modifier
2926 if ((i.tm.opcode_modifier & W)
2927 || ((suffixes & (suffixes - 1))
2928 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2930 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2936 /* Change the opcode based on the operand size given by i.suffix;
2937 We don't need to change things for byte insns. */
2939 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2941 /* It's not a byte, select word/dword operation. */
2942 if (i.tm.opcode_modifier & W)
2944 if (i.tm.opcode_modifier & ShortForm)
2945 i.tm.base_opcode |= 8;
2947 i.tm.base_opcode |= 1;
2950 /* Now select between word & dword operations via the operand
2951 size prefix, except for instructions that will ignore this
2953 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2955 /* monitor in SSE3 is a very special case. The default size
2956 of AX is the size of mode. The address size override
2957 prefix will change the size of AX. */
2958 if (i.op->regs[0].reg_type &
2959 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2960 if (!add_prefix (ADDR_PREFIX_OPCODE))
2963 else if (i.suffix != QWORD_MNEM_SUFFIX
2964 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2965 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2966 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2967 || (flag_code == CODE_64BIT
2968 && (i.tm.opcode_modifier & JumpByte))))
2970 unsigned int prefix = DATA_PREFIX_OPCODE;
2972 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2973 prefix = ADDR_PREFIX_OPCODE;
2975 if (!add_prefix (prefix))
2979 /* Set mode64 for an operand. */
2980 if (i.suffix == QWORD_MNEM_SUFFIX
2981 && flag_code == CODE_64BIT
2982 && (i.tm.opcode_modifier & NoRex64) == 0)
2984 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2987 || i.types [0] != (Acc | Reg64)
2988 || i.types [1] != (Acc | Reg64)
2989 || i.tm.base_opcode != 0x90)
2993 /* Size floating point instruction. */
2994 if (i.suffix == LONG_MNEM_SUFFIX)
2995 if (i.tm.opcode_modifier & FloatMF)
2996 i.tm.base_opcode ^= 4;
3003 check_byte_reg (void)
3007 for (op = i.operands; --op >= 0;)
3009 /* If this is an eight bit register, it's OK. If it's the 16 or
3010 32 bit version of an eight bit register, we will just use the
3011 low portion, and that's OK too. */
3012 if (i.types[op] & Reg8)
3015 /* movzx and movsx should not generate this warning. */
3017 && (i.tm.base_opcode == 0xfb7
3018 || i.tm.base_opcode == 0xfb6
3019 || i.tm.base_opcode == 0x63
3020 || i.tm.base_opcode == 0xfbe
3021 || i.tm.base_opcode == 0xfbf))
3024 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3026 /* Prohibit these changes in the 64bit mode, since the
3027 lowering is more complicated. */
3028 if (flag_code == CODE_64BIT
3029 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3031 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3032 register_prefix, i.op[op].regs->reg_name,
3036 #if REGISTER_WARNINGS
3038 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3039 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3040 (i.op[op].regs + (i.types[op] & Reg16
3041 ? REGNAM_AL - REGNAM_AX
3042 : REGNAM_AL - REGNAM_EAX))->reg_name,
3043 i.op[op].regs->reg_name,
3048 /* Any other register is bad. */
3049 if (i.types[op] & (Reg | RegMMX | RegXMM
3051 | Control | Debug | Test
3052 | FloatReg | FloatAcc))
3054 as_bad (_("`%%%s' not allowed with `%s%c'"),
3055 i.op[op].regs->reg_name,
3065 check_long_reg (void)
3069 for (op = i.operands; --op >= 0;)
3070 /* Reject eight bit registers, except where the template requires
3071 them. (eg. movzb) */
3072 if ((i.types[op] & Reg8) != 0
3073 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3075 as_bad (_("`%%%s' not allowed with `%s%c'"),
3076 i.op[op].regs->reg_name,
3081 /* Warn if the e prefix on a general reg is missing. */
3082 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3083 && (i.types[op] & Reg16) != 0
3084 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3086 /* Prohibit these changes in the 64bit mode, since the
3087 lowering is more complicated. */
3088 if (flag_code == CODE_64BIT)
3090 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3091 register_prefix, i.op[op].regs->reg_name,
3095 #if REGISTER_WARNINGS
3097 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3098 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3099 i.op[op].regs->reg_name,
3103 /* Warn if the r prefix on a general reg is missing. */
3104 else if ((i.types[op] & Reg64) != 0
3105 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3107 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3108 register_prefix, i.op[op].regs->reg_name,
3116 check_qword_reg (void)
3120 for (op = i.operands; --op >= 0; )
3121 /* Reject eight bit registers, except where the template requires
3122 them. (eg. movzb) */
3123 if ((i.types[op] & Reg8) != 0
3124 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3126 as_bad (_("`%%%s' not allowed with `%s%c'"),
3127 i.op[op].regs->reg_name,
3132 /* Warn if the e prefix on a general reg is missing. */
3133 else if (((i.types[op] & Reg16) != 0
3134 || (i.types[op] & Reg32) != 0)
3135 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3137 /* Prohibit these changes in the 64bit mode, since the
3138 lowering is more complicated. */
3139 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3140 register_prefix, i.op[op].regs->reg_name,
3148 check_word_reg (void)
3151 for (op = i.operands; --op >= 0;)
3152 /* Reject eight bit registers, except where the template requires
3153 them. (eg. movzb) */
3154 if ((i.types[op] & Reg8) != 0
3155 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3157 as_bad (_("`%%%s' not allowed with `%s%c'"),
3158 i.op[op].regs->reg_name,
3163 /* Warn if the e prefix on a general reg is present. */
3164 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3165 && (i.types[op] & Reg32) != 0
3166 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3168 /* Prohibit these changes in the 64bit mode, since the
3169 lowering is more complicated. */
3170 if (flag_code == CODE_64BIT)
3172 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3173 register_prefix, i.op[op].regs->reg_name,
3178 #if REGISTER_WARNINGS
3179 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3180 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3181 i.op[op].regs->reg_name,
3191 unsigned int overlap0, overlap1, overlap2;
3193 overlap0 = i.types[0] & i.tm.operand_types[0];
3194 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3195 && overlap0 != Imm8 && overlap0 != Imm8S
3196 && overlap0 != Imm16 && overlap0 != Imm32S
3197 && overlap0 != Imm32 && overlap0 != Imm64)
3201 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3203 : (i.suffix == WORD_MNEM_SUFFIX
3205 : (i.suffix == QWORD_MNEM_SUFFIX
3209 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3210 || overlap0 == (Imm16 | Imm32)
3211 || overlap0 == (Imm16 | Imm32S))
3213 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3216 if (overlap0 != Imm8 && overlap0 != Imm8S
3217 && overlap0 != Imm16 && overlap0 != Imm32S
3218 && overlap0 != Imm32 && overlap0 != Imm64)
3220 as_bad (_("no instruction mnemonic suffix given; "
3221 "can't determine immediate size"));
3225 i.types[0] = overlap0;
3227 overlap1 = i.types[1] & i.tm.operand_types[1];
3228 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3229 && overlap1 != Imm8 && overlap1 != Imm8S
3230 && overlap1 != Imm16 && overlap1 != Imm32S
3231 && overlap1 != Imm32 && overlap1 != Imm64)
3235 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3237 : (i.suffix == WORD_MNEM_SUFFIX
3239 : (i.suffix == QWORD_MNEM_SUFFIX
3243 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3244 || overlap1 == (Imm16 | Imm32)
3245 || overlap1 == (Imm16 | Imm32S))
3247 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3250 if (overlap1 != Imm8 && overlap1 != Imm8S
3251 && overlap1 != Imm16 && overlap1 != Imm32S
3252 && overlap1 != Imm32 && overlap1 != Imm64)
3254 as_bad (_("no instruction mnemonic suffix given; "
3255 "can't determine immediate size %x %c"),
3256 overlap1, i.suffix);
3260 i.types[1] = overlap1;
3262 overlap2 = i.types[2] & i.tm.operand_types[2];
3263 assert ((overlap2 & Imm) == 0);
3264 i.types[2] = overlap2;
3270 process_operands (void)
3272 /* Default segment register this instruction will use for memory
3273 accesses. 0 means unknown. This is only for optimizing out
3274 unnecessary segment overrides. */
3275 const seg_entry *default_seg = 0;
3277 /* The imul $imm, %reg instruction is converted into
3278 imul $imm, %reg, %reg, and the clr %reg instruction
3279 is converted into xor %reg, %reg. */
3280 if (i.tm.opcode_modifier & regKludge)
3282 if ((i.tm.cpu_flags & CpuSSE4_1))
3284 /* The first operand in instruction blendvpd, blendvps and
3285 pblendvb in SSE4.1 is implicit and must be xmm0. */
3286 assert (i.operands == 3
3287 && i.reg_operands >= 2
3288 && i.types[0] == RegXMM);
3289 if (i.op[0].regs->reg_num != 0)
3292 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3293 i.tm.name, register_prefix);
3295 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3296 i.tm.name, register_prefix);
3301 i.types[0] = i.types[1];
3302 i.types[1] = i.types[2];
3306 /* We need to adjust fields in i.tm since they are used by
3307 build_modrm_byte. */
3308 i.tm.operand_types [0] = i.tm.operand_types [1];
3309 i.tm.operand_types [1] = i.tm.operand_types [2];
3314 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3315 /* Pretend we saw the extra register operand. */
3316 assert (i.reg_operands == 1
3317 && i.op[first_reg_op + 1].regs == 0);
3318 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3319 i.types[first_reg_op + 1] = i.types[first_reg_op];
3325 if (i.tm.opcode_modifier & ShortForm)
3327 if (i.types[0] & (SReg2 | SReg3))
3329 if (i.tm.base_opcode == POP_SEG_SHORT
3330 && i.op[0].regs->reg_num == 1)
3332 as_bad (_("you can't `pop %%cs'"));
3335 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3336 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3341 /* The register or float register operand is in operand 0 or 1. */
3342 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3343 /* Register goes in low 3 bits of opcode. */
3344 i.tm.base_opcode |= i.op[op].regs->reg_num;
3345 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3347 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3349 /* Warn about some common errors, but press on regardless.
3350 The first case can be generated by gcc (<= 2.8.1). */
3351 if (i.operands == 2)
3353 /* Reversed arguments on faddp, fsubp, etc. */
3354 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3355 i.op[1].regs->reg_name,
3356 i.op[0].regs->reg_name);
3360 /* Extraneous `l' suffix on fp insn. */
3361 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3362 i.op[0].regs->reg_name);
3367 else if (i.tm.opcode_modifier & Modrm)
3369 /* The opcode is completed (modulo i.tm.extension_opcode which
3370 must be put into the modrm byte). Now, we make the modrm and
3371 index base bytes based on all the info we've collected. */
3373 default_seg = build_modrm_byte ();
3375 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
3379 else if ((i.tm.opcode_modifier & IsString) != 0)
3381 /* For the string instructions that allow a segment override
3382 on one of their operands, the default segment is ds. */
3386 if ((i.tm.base_opcode == 0x8d /* lea */
3387 || (i.tm.cpu_flags & CpuSVME))
3388 && i.seg[0] && !quiet_warnings)
3389 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3391 /* If a segment was explicitly specified, and the specified segment
3392 is not the default, use an opcode prefix to select it. If we
3393 never figured out what the default segment is, then default_seg
3394 will be zero at this point, and the specified segment prefix will
3396 if ((i.seg[0]) && (i.seg[0] != default_seg))
3398 if (!add_prefix (i.seg[0]->seg_prefix))
3404 static const seg_entry *
3405 build_modrm_byte (void)
3407 const seg_entry *default_seg = 0;
3409 /* i.reg_operands MUST be the number of real register operands;
3410 implicit registers do not count. */
3411 if (i.reg_operands == 2)
3413 unsigned int source, dest;
3421 /* When there are 3 operands, one of them may be immediate,
3422 which may be the first or the last operand. Otherwise,
3423 the first operand must be shift count register (cl). */
3424 assert (i.imm_operands == 1
3425 || (i.imm_operands == 0
3426 && (i.types[0] & ShiftCount)));
3427 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
3430 /* When there are 4 operands, the first two must be immediate
3431 operands. The source operand will be the 3rd one. */
3432 assert (i.imm_operands == 2
3433 && (i.types[0] & Imm)
3434 && (i.types[1] & Imm));
3444 /* One of the register operands will be encoded in the i.tm.reg
3445 field, the other in the combined i.tm.mode and i.tm.regmem
3446 fields. If no form of this instruction supports a memory
3447 destination operand, then we assume the source operand may
3448 sometimes be a memory operand and so we need to store the
3449 destination in the i.rm.reg field. */
3450 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
3452 i.rm.reg = i.op[dest].regs->reg_num;
3453 i.rm.regmem = i.op[source].regs->reg_num;
3454 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3456 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3461 i.rm.reg = i.op[source].regs->reg_num;
3462 i.rm.regmem = i.op[dest].regs->reg_num;
3463 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3465 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3468 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
3470 if (!((i.types[0] | i.types[1]) & Control))
3472 i.rex &= ~(REX_R | REX_B);
3473 add_prefix (LOCK_PREFIX_OPCODE);
3477 { /* If it's not 2 reg operands... */
3480 unsigned int fake_zero_displacement = 0;
3483 for (op = 0; op < i.operands; op++)
3484 if ((i.types[op] & AnyMem))
3486 assert (op < i.operands);
3490 if (i.base_reg == 0)
3493 if (!i.disp_operands)
3494 fake_zero_displacement = 1;
3495 if (i.index_reg == 0)
3497 /* Operand is just <disp> */
3498 if (flag_code == CODE_64BIT)
3500 /* 64bit mode overwrites the 32bit absolute
3501 addressing by RIP relative addressing and
3502 absolute addressing is encoded by one of the
3503 redundant SIB forms. */
3504 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3505 i.sib.base = NO_BASE_REGISTER;
3506 i.sib.index = NO_INDEX_REGISTER;
3507 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3508 ? Disp32S : Disp32);
3510 else if ((flag_code == CODE_16BIT)
3511 ^ (i.prefix[ADDR_PREFIX] != 0))
3513 i.rm.regmem = NO_BASE_REGISTER_16;
3514 i.types[op] = Disp16;
3518 i.rm.regmem = NO_BASE_REGISTER;
3519 i.types[op] = Disp32;
3522 else /* !i.base_reg && i.index_reg */
3524 i.sib.index = i.index_reg->reg_num;
3525 i.sib.base = NO_BASE_REGISTER;
3526 i.sib.scale = i.log2_scale_factor;
3527 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3528 i.types[op] &= ~Disp;
3529 if (flag_code != CODE_64BIT)
3530 i.types[op] |= Disp32; /* Must be 32 bit */
3532 i.types[op] |= Disp32S;
3533 if ((i.index_reg->reg_flags & RegRex) != 0)
3537 /* RIP addressing for 64bit mode. */
3538 else if (i.base_reg->reg_type == BaseIndex)
3540 i.rm.regmem = NO_BASE_REGISTER;
3541 i.types[op] &= ~ Disp;
3542 i.types[op] |= Disp32S;
3543 i.flags[op] |= Operand_PCrel;
3544 if (! i.disp_operands)
3545 fake_zero_displacement = 1;
3547 else if (i.base_reg->reg_type & Reg16)
3549 switch (i.base_reg->reg_num)
3552 if (i.index_reg == 0)
3554 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3555 i.rm.regmem = i.index_reg->reg_num - 6;
3559 if (i.index_reg == 0)
3562 if ((i.types[op] & Disp) == 0)
3564 /* fake (%bp) into 0(%bp) */
3565 i.types[op] |= Disp8;
3566 fake_zero_displacement = 1;
3569 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3570 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3572 default: /* (%si) -> 4 or (%di) -> 5 */
3573 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3575 i.rm.mode = mode_from_disp_size (i.types[op]);
3577 else /* i.base_reg and 32/64 bit mode */
3579 if (flag_code == CODE_64BIT
3580 && (i.types[op] & Disp))
3581 i.types[op] = ((i.types[op] & Disp8)
3582 | (i.prefix[ADDR_PREFIX] == 0
3583 ? Disp32S : Disp32));
3585 i.rm.regmem = i.base_reg->reg_num;
3586 if ((i.base_reg->reg_flags & RegRex) != 0)
3588 i.sib.base = i.base_reg->reg_num;
3589 /* x86-64 ignores REX prefix bit here to avoid decoder
3591 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3594 if (i.disp_operands == 0)
3596 fake_zero_displacement = 1;
3597 i.types[op] |= Disp8;
3600 else if (i.base_reg->reg_num == ESP_REG_NUM)
3604 i.sib.scale = i.log2_scale_factor;
3605 if (i.index_reg == 0)
3607 /* <disp>(%esp) becomes two byte modrm with no index
3608 register. We've already stored the code for esp
3609 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3610 Any base register besides %esp will not use the
3611 extra modrm byte. */
3612 i.sib.index = NO_INDEX_REGISTER;
3613 #if !SCALE1_WHEN_NO_INDEX
3614 /* Another case where we force the second modrm byte. */
3615 if (i.log2_scale_factor)
3616 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3621 i.sib.index = i.index_reg->reg_num;
3622 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3623 if ((i.index_reg->reg_flags & RegRex) != 0)
3628 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3629 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3632 i.rm.mode = mode_from_disp_size (i.types[op]);
3635 if (fake_zero_displacement)
3637 /* Fakes a zero displacement assuming that i.types[op]
3638 holds the correct displacement size. */
3641 assert (i.op[op].disps == 0);
3642 exp = &disp_expressions[i.disp_operands++];
3643 i.op[op].disps = exp;
3644 exp->X_op = O_constant;
3645 exp->X_add_number = 0;
3646 exp->X_add_symbol = (symbolS *) 0;
3647 exp->X_op_symbol = (symbolS *) 0;
3651 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3652 (if any) based on i.tm.extension_opcode. Again, we must be
3653 careful to make sure that segment/control/debug/test/MMX
3654 registers are coded into the i.rm.reg field. */
3659 for (op = 0; op < i.operands; op++)
3660 if ((i.types[op] & (Reg | RegMMX | RegXMM
3662 | Control | Debug | Test)))
3664 assert (op < i.operands);
3666 /* If there is an extension opcode to put here, the register
3667 number must be put into the regmem field. */
3668 if (i.tm.extension_opcode != None)
3670 i.rm.regmem = i.op[op].regs->reg_num;
3671 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3676 i.rm.reg = i.op[op].regs->reg_num;
3677 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3681 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3682 must set it to 3 to indicate this is a register operand
3683 in the regmem field. */
3684 if (!i.mem_operands)
3688 /* Fill in i.rm.reg field with extension opcode (if any). */
3689 if (i.tm.extension_opcode != None)
3690 i.rm.reg = i.tm.extension_opcode;
3696 output_branch (void)
3701 relax_substateT subtype;
3706 if (flag_code == CODE_16BIT)
3710 if (i.prefix[DATA_PREFIX] != 0)
3716 /* Pentium4 branch hints. */
3717 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3718 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3723 if (i.prefix[REX_PREFIX] != 0)
3729 if (i.prefixes != 0 && !intel_syntax)
3730 as_warn (_("skipping prefixes on this instruction"));
3732 /* It's always a symbol; End frag & setup for relax.
3733 Make sure there is enough room in this frag for the largest
3734 instruction we may generate in md_convert_frag. This is 2
3735 bytes for the opcode and room for the prefix and largest
3737 frag_grow (prefix + 2 + 4);
3738 /* Prefix and 1 opcode byte go in fr_fix. */
3739 p = frag_more (prefix + 1);
3740 if (i.prefix[DATA_PREFIX] != 0)
3741 *p++ = DATA_PREFIX_OPCODE;
3742 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3743 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3744 *p++ = i.prefix[SEG_PREFIX];
3745 if (i.prefix[REX_PREFIX] != 0)
3746 *p++ = i.prefix[REX_PREFIX];
3747 *p = i.tm.base_opcode;
3749 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3750 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3751 else if ((cpu_arch_flags & Cpu386) != 0)
3752 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3754 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3757 sym = i.op[0].disps->X_add_symbol;
3758 off = i.op[0].disps->X_add_number;
3760 if (i.op[0].disps->X_op != O_constant
3761 && i.op[0].disps->X_op != O_symbol)
3763 /* Handle complex expressions. */
3764 sym = make_expr_symbol (i.op[0].disps);
3768 /* 1 possible extra opcode + 4 byte displacement go in var part.
3769 Pass reloc in fr_var. */
3770 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3780 if (i.tm.opcode_modifier & JumpByte)
3782 /* This is a loop or jecxz type instruction. */
3784 if (i.prefix[ADDR_PREFIX] != 0)
3786 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3789 /* Pentium4 branch hints. */
3790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3793 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3802 if (flag_code == CODE_16BIT)
3805 if (i.prefix[DATA_PREFIX] != 0)
3807 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3817 if (i.prefix[REX_PREFIX] != 0)
3819 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
3826 p = frag_more (1 + size);
3827 *p++ = i.tm.base_opcode;
3829 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3830 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3832 /* All jumps handled here are signed, but don't use a signed limit
3833 check for 32 and 16 bit jumps as we want to allow wrap around at
3834 4G and 64k respectively. */
3836 fixP->fx_signed = 1;
3840 output_interseg_jump (void)
3848 if (flag_code == CODE_16BIT)
3852 if (i.prefix[DATA_PREFIX] != 0)
3858 if (i.prefix[REX_PREFIX] != 0)
3868 if (i.prefixes != 0 && !intel_syntax)
3869 as_warn (_("skipping prefixes on this instruction"));
3871 /* 1 opcode; 2 segment; offset */
3872 p = frag_more (prefix + 1 + 2 + size);
3874 if (i.prefix[DATA_PREFIX] != 0)
3875 *p++ = DATA_PREFIX_OPCODE;
3877 if (i.prefix[REX_PREFIX] != 0)
3878 *p++ = i.prefix[REX_PREFIX];
3880 *p++ = i.tm.base_opcode;
3881 if (i.op[1].imms->X_op == O_constant)
3883 offsetT n = i.op[1].imms->X_add_number;
3886 && !fits_in_unsigned_word (n)
3887 && !fits_in_signed_word (n))
3889 as_bad (_("16-bit jump out of range"));
3892 md_number_to_chars (p, n, size);
3895 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3896 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3897 if (i.op[0].imms->X_op != O_constant)
3898 as_bad (_("can't handle non absolute segment in `%s'"),
3900 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3906 fragS *insn_start_frag;
3907 offsetT insn_start_off;
3909 /* Tie dwarf2 debug info to the address at the start of the insn.
3910 We can't do this after the insn has been output as the current
3911 frag may have been closed off. eg. by frag_var. */
3912 dwarf2_emit_insn (0);
3914 insn_start_frag = frag_now;
3915 insn_start_off = frag_now_fix ();
3918 if (i.tm.opcode_modifier & Jump)
3920 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3922 else if (i.tm.opcode_modifier & JumpInterSegment)
3923 output_interseg_jump ();
3926 /* Output normal instructions here. */
3929 unsigned int prefix;
3931 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
3932 SSE4.1 instructions have 3 bytes. We may use one more higher
3933 byte to specify a prefix the instruction requires. */
3934 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4_1)) != 0)
3936 if (i.tm.base_opcode & 0xff000000)
3938 prefix = (i.tm.base_opcode >> 24) & 0xff;
3942 else if ((i.tm.base_opcode & 0xff0000) != 0)
3944 prefix = (i.tm.base_opcode >> 16) & 0xff;
3945 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3948 if (prefix != REPE_PREFIX_OPCODE
3949 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3950 add_prefix (prefix);
3953 add_prefix (prefix);
3956 /* The prefix bytes. */
3958 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3964 md_number_to_chars (p, (valueT) *q, 1);
3968 /* Now the opcode; be careful about word order here! */
3969 if (fits_in_unsigned_byte (i.tm.base_opcode))
3971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3975 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4_1)) != 0)
3978 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3983 /* Put out high byte first: can't use md_number_to_chars! */
3984 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3985 *p = i.tm.base_opcode & 0xff;
3988 /* Now the modrm byte and sib byte (if present). */
3989 if (i.tm.opcode_modifier & Modrm)
3992 md_number_to_chars (p,
3993 (valueT) (i.rm.regmem << 0
3997 /* If i.rm.regmem == ESP (4)
3998 && i.rm.mode != (Register mode)
4000 ==> need second modrm byte. */
4001 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4003 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4006 md_number_to_chars (p,
4007 (valueT) (i.sib.base << 0
4009 | i.sib.scale << 6),
4014 if (i.disp_operands)
4015 output_disp (insn_start_frag, insn_start_off);
4018 output_imm (insn_start_frag, insn_start_off);
4024 pi ("" /*line*/, &i);
4026 #endif /* DEBUG386 */
4030 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
4035 for (n = 0; n < i.operands; n++)
4037 if (i.types[n] & Disp)
4039 if (i.op[n].disps->X_op == O_constant)
4045 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4048 if (i.types[n] & Disp8)
4050 if (i.types[n] & Disp64)
4053 val = offset_in_range (i.op[n].disps->X_add_number,
4055 p = frag_more (size);
4056 md_number_to_chars (p, val, size);
4060 enum bfd_reloc_code_real reloc_type;
4063 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4065 /* The PC relative address is computed relative
4066 to the instruction boundary, so in case immediate
4067 fields follows, we need to adjust the value. */
4068 if (pcrel && i.imm_operands)
4073 for (n1 = 0; n1 < i.operands; n1++)
4074 if (i.types[n1] & Imm)
4076 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4079 if (i.types[n1] & (Imm8 | Imm8S))
4081 if (i.types[n1] & Imm64)
4086 /* We should find the immediate. */
4087 if (n1 == i.operands)
4089 i.op[n].disps->X_add_number -= imm_size;
4092 if (i.types[n] & Disp32S)
4095 if (i.types[n] & (Disp16 | Disp64))
4098 if (i.types[n] & Disp64)
4102 p = frag_more (size);
4103 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4105 && GOT_symbol == i.op[n].disps->X_add_symbol
4106 && (((reloc_type == BFD_RELOC_32
4107 || reloc_type == BFD_RELOC_X86_64_32S
4108 || (reloc_type == BFD_RELOC_64
4110 && (i.op[n].disps->X_op == O_symbol
4111 || (i.op[n].disps->X_op == O_add
4112 && ((symbol_get_value_expression
4113 (i.op[n].disps->X_op_symbol)->X_op)
4115 || reloc_type == BFD_RELOC_32_PCREL))
4119 if (insn_start_frag == frag_now)
4120 add = (p - frag_now->fr_literal) - insn_start_off;
4125 add = insn_start_frag->fr_fix - insn_start_off;
4126 for (fr = insn_start_frag->fr_next;
4127 fr && fr != frag_now; fr = fr->fr_next)
4129 add += p - frag_now->fr_literal;
4134 reloc_type = BFD_RELOC_386_GOTPC;
4135 i.op[n].imms->X_add_number += add;
4137 else if (reloc_type == BFD_RELOC_64)
4138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4140 /* Don't do the adjustment for x86-64, as there
4141 the pcrel addressing is relative to the _next_
4142 insn, and that is taken care of in other code. */
4143 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4145 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4146 i.op[n].disps, pcrel, reloc_type);
4153 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4158 for (n = 0; n < i.operands; n++)
4160 if (i.types[n] & Imm)
4162 if (i.op[n].imms->X_op == O_constant)
4168 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4171 if (i.types[n] & (Imm8 | Imm8S))
4173 else if (i.types[n] & Imm64)
4176 val = offset_in_range (i.op[n].imms->X_add_number,
4178 p = frag_more (size);
4179 md_number_to_chars (p, val, size);
4183 /* Not absolute_section.
4184 Need a 32-bit fixup (don't support 8bit
4185 non-absolute imms). Try to support other
4187 enum bfd_reloc_code_real reloc_type;
4191 if ((i.types[n] & (Imm32S))
4192 && (i.suffix == QWORD_MNEM_SUFFIX
4193 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4195 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4198 if (i.types[n] & (Imm8 | Imm8S))
4200 if (i.types[n] & Imm64)
4204 p = frag_more (size);
4205 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4207 /* This is tough to explain. We end up with this one if we
4208 * have operands that look like
4209 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4210 * obtain the absolute address of the GOT, and it is strongly
4211 * preferable from a performance point of view to avoid using
4212 * a runtime relocation for this. The actual sequence of
4213 * instructions often look something like:
4218 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4220 * The call and pop essentially return the absolute address
4221 * of the label .L66 and store it in %ebx. The linker itself
4222 * will ultimately change the first operand of the addl so
4223 * that %ebx points to the GOT, but to keep things simple, the
4224 * .o file must have this operand set so that it generates not
4225 * the absolute address of .L66, but the absolute address of
4226 * itself. This allows the linker itself simply treat a GOTPC
4227 * relocation as asking for a pcrel offset to the GOT to be
4228 * added in, and the addend of the relocation is stored in the
4229 * operand field for the instruction itself.
4231 * Our job here is to fix the operand so that it would add
4232 * the correct offset so that %ebx would point to itself. The
4233 * thing that is tricky is that .-.L66 will point to the
4234 * beginning of the instruction, so we need to further modify
4235 * the operand so that it will point to itself. There are
4236 * other cases where you have something like:
4238 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4240 * and here no correction would be required. Internally in
4241 * the assembler we treat operands of this form as not being
4242 * pcrel since the '.' is explicitly mentioned, and I wonder
4243 * whether it would simplify matters to do it this way. Who
4244 * knows. In earlier versions of the PIC patches, the
4245 * pcrel_adjust field was used to store the correction, but
4246 * since the expression is not pcrel, I felt it would be
4247 * confusing to do it this way. */
4249 if ((reloc_type == BFD_RELOC_32
4250 || reloc_type == BFD_RELOC_X86_64_32S
4251 || reloc_type == BFD_RELOC_64)
4253 && GOT_symbol == i.op[n].imms->X_add_symbol
4254 && (i.op[n].imms->X_op == O_symbol
4255 || (i.op[n].imms->X_op == O_add
4256 && ((symbol_get_value_expression
4257 (i.op[n].imms->X_op_symbol)->X_op)
4262 if (insn_start_frag == frag_now)
4263 add = (p - frag_now->fr_literal) - insn_start_off;
4268 add = insn_start_frag->fr_fix - insn_start_off;
4269 for (fr = insn_start_frag->fr_next;
4270 fr && fr != frag_now; fr = fr->fr_next)
4272 add += p - frag_now->fr_literal;
4276 reloc_type = BFD_RELOC_386_GOTPC;
4278 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4280 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4281 i.op[n].imms->X_add_number += add;
4283 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4284 i.op[n].imms, 0, reloc_type);
4290 /* x86_cons_fix_new is called via the expression parsing code when a
4291 reloc is needed. We use this hook to get the correct .got reloc. */
4292 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4293 static int cons_sign = -1;
4296 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
4299 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4301 got_reloc = NO_RELOC;
4304 if (exp->X_op == O_secrel)
4306 exp->X_op = O_symbol;
4307 r = BFD_RELOC_32_SECREL;
4311 fix_new_exp (frag, off, len, exp, 0, r);
4314 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4315 # define lex_got(reloc, adjust, types) NULL
4317 /* Parse operands of the form
4318 <symbol>@GOTOFF+<nnn>
4319 and similar .plt or .got references.
4321 If we find one, set up the correct relocation in RELOC and copy the
4322 input string, minus the `@GOTOFF' into a malloc'd buffer for
4323 parsing by the calling routine. Return this buffer, and if ADJUST
4324 is non-null set it to the length of the string we removed from the
4325 input line. Otherwise return NULL. */
4327 lex_got (enum bfd_reloc_code_real *reloc,
4329 unsigned int *types)
4331 /* Some of the relocations depend on the size of what field is to
4332 be relocated. But in our callers i386_immediate and i386_displacement
4333 we don't yet know the operand size (this will be set by insn
4334 matching). Hence we record the word32 relocation here,
4335 and adjust the reloc according to the real size in reloc(). */
4336 static const struct {
4338 const enum bfd_reloc_code_real rel[2];
4339 const unsigned int types64;
4342 BFD_RELOC_X86_64_PLTOFF64 },
4344 { "PLT", { BFD_RELOC_386_PLT32,
4345 BFD_RELOC_X86_64_PLT32 },
4346 Imm32 | Imm32S | Disp32 },
4348 BFD_RELOC_X86_64_GOTPLT64 },
4350 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4351 BFD_RELOC_X86_64_GOTOFF64 },
4354 BFD_RELOC_X86_64_GOTPCREL },
4355 Imm32 | Imm32S | Disp32 },
4356 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4357 BFD_RELOC_X86_64_TLSGD },
4358 Imm32 | Imm32S | Disp32 },
4359 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4363 BFD_RELOC_X86_64_TLSLD },
4364 Imm32 | Imm32S | Disp32 },
4365 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4366 BFD_RELOC_X86_64_GOTTPOFF },
4367 Imm32 | Imm32S | Disp32 },
4368 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4369 BFD_RELOC_X86_64_TPOFF32 },
4370 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4371 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4374 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4375 BFD_RELOC_X86_64_DTPOFF32 },
4376 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4377 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4380 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4383 { "GOT", { BFD_RELOC_386_GOT32,
4384 BFD_RELOC_X86_64_GOT32 },
4385 Imm32 | Imm32S | Disp32 | Imm64 },
4386 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4387 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4388 Imm32 | Imm32S | Disp32 },
4389 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4390 BFD_RELOC_X86_64_TLSDESC_CALL },
4391 Imm32 | Imm32S | Disp32 }
4399 for (cp = input_line_pointer; *cp != '@'; cp++)
4400 if (is_end_of_line[(unsigned char) *cp])
4403 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4407 len = strlen (gotrel[j].str);
4408 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4410 if (gotrel[j].rel[object_64bit] != 0)
4413 char *tmpbuf, *past_reloc;
4415 *reloc = gotrel[j].rel[object_64bit];
4421 if (flag_code != CODE_64BIT)
4422 *types = Imm32 | Disp32;
4424 *types = gotrel[j].types64;
4427 if (GOT_symbol == NULL)
4428 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4430 /* Replace the relocation token with ' ', so that
4431 errors like foo@GOTOFF1 will be detected. */
4433 /* The length of the first part of our input line. */
4434 first = cp - input_line_pointer;
4436 /* The second part goes from after the reloc token until
4437 (and including) an end_of_line char. Don't use strlen
4438 here as the end_of_line char may not be a NUL. */
4439 past_reloc = cp + 1 + len;
4440 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4442 second = cp - past_reloc;
4444 /* Allocate and copy string. The trailing NUL shouldn't
4445 be necessary, but be safe. */
4446 tmpbuf = xmalloc (first + second + 2);
4447 memcpy (tmpbuf, input_line_pointer, first);
4448 tmpbuf[first] = ' ';
4449 memcpy (tmpbuf + first + 1, past_reloc, second);
4450 tmpbuf[first + second + 1] = '\0';
4454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4455 gotrel[j].str, 1 << (5 + object_64bit));
4460 /* Might be a symbol version string. Don't as_bad here. */
4465 x86_cons (expressionS *exp, int size)
4467 if (size == 4 || (object_64bit && size == 8))
4469 /* Handle @GOTOFF and the like in an expression. */
4471 char *gotfree_input_line;
4474 save = input_line_pointer;
4475 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4476 if (gotfree_input_line)
4477 input_line_pointer = gotfree_input_line;
4481 if (gotfree_input_line)
4483 /* expression () has merrily parsed up to the end of line,
4484 or a comma - in the wrong buffer. Transfer how far
4485 input_line_pointer has moved to the right buffer. */
4486 input_line_pointer = (save
4487 + (input_line_pointer - gotfree_input_line)
4489 free (gotfree_input_line);
4497 static void signed_cons (int size)
4499 if (flag_code == CODE_64BIT)
4507 pe_directive_secrel (dummy)
4508 int dummy ATTRIBUTE_UNUSED;
4515 if (exp.X_op == O_symbol)
4516 exp.X_op = O_secrel;
4518 emit_expr (&exp, 4);
4520 while (*input_line_pointer++ == ',');
4522 input_line_pointer--;
4523 demand_empty_rest_of_line ();
4528 i386_immediate (char *imm_start)
4530 char *save_input_line_pointer;
4531 char *gotfree_input_line;
4534 unsigned int types = ~0U;
4536 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4538 as_bad (_("at most %d immediate operands are allowed"),
4539 MAX_IMMEDIATE_OPERANDS);
4543 exp = &im_expressions[i.imm_operands++];
4544 i.op[this_operand].imms = exp;
4546 if (is_space_char (*imm_start))
4549 save_input_line_pointer = input_line_pointer;
4550 input_line_pointer = imm_start;
4552 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4553 if (gotfree_input_line)
4554 input_line_pointer = gotfree_input_line;
4556 exp_seg = expression (exp);
4559 if (*input_line_pointer)
4560 as_bad (_("junk `%s' after expression"), input_line_pointer);
4562 input_line_pointer = save_input_line_pointer;
4563 if (gotfree_input_line)
4564 free (gotfree_input_line);
4566 if (exp->X_op == O_absent || exp->X_op == O_big)
4568 /* Missing or bad expr becomes absolute 0. */
4569 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4571 exp->X_op = O_constant;
4572 exp->X_add_number = 0;
4573 exp->X_add_symbol = (symbolS *) 0;
4574 exp->X_op_symbol = (symbolS *) 0;
4576 else if (exp->X_op == O_constant)
4578 /* Size it properly later. */
4579 i.types[this_operand] |= Imm64;
4580 /* If BFD64, sign extend val. */
4581 if (!use_rela_relocations
4582 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4584 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4586 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4587 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4588 && exp_seg != absolute_section
4589 && exp_seg != text_section
4590 && exp_seg != data_section
4591 && exp_seg != bss_section
4592 && exp_seg != undefined_section
4593 && !bfd_is_com_section (exp_seg))
4595 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4599 else if (!intel_syntax && exp->X_op == O_register)
4601 as_bad (_("illegal immediate register operand %s"), imm_start);
4606 /* This is an address. The size of the address will be
4607 determined later, depending on destination register,
4608 suffix, or the default for the section. */
4609 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4610 i.types[this_operand] &= types;
4617 i386_scale (char *scale)
4620 char *save = input_line_pointer;
4622 input_line_pointer = scale;
4623 val = get_absolute_expression ();
4628 i.log2_scale_factor = 0;
4631 i.log2_scale_factor = 1;
4634 i.log2_scale_factor = 2;
4637 i.log2_scale_factor = 3;
4641 char sep = *input_line_pointer;
4643 *input_line_pointer = '\0';
4644 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4646 *input_line_pointer = sep;
4647 input_line_pointer = save;
4651 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4653 as_warn (_("scale factor of %d without an index register"),
4654 1 << i.log2_scale_factor);
4655 #if SCALE1_WHEN_NO_INDEX
4656 i.log2_scale_factor = 0;
4659 scale = input_line_pointer;
4660 input_line_pointer = save;
4665 i386_displacement (char *disp_start, char *disp_end)
4669 char *save_input_line_pointer;
4670 char *gotfree_input_line;
4671 int bigdisp, override;
4672 unsigned int types = Disp;
4674 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4676 as_bad (_("at most %d displacement operands are allowed"),
4677 MAX_MEMORY_OPERANDS);
4681 if ((i.types[this_operand] & JumpAbsolute)
4682 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4685 override = (i.prefix[ADDR_PREFIX] != 0);
4689 /* For PC-relative branches, the width of the displacement
4690 is dependent upon data size, not address size. */
4692 override = (i.prefix[DATA_PREFIX] != 0);
4694 if (flag_code == CODE_64BIT)
4697 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4699 : Disp32S | Disp32);
4701 bigdisp = Disp64 | Disp32S | Disp32;
4708 override = (i.suffix == (flag_code != CODE_16BIT
4710 : LONG_MNEM_SUFFIX));
4713 if ((flag_code == CODE_16BIT) ^ override)
4716 i.types[this_operand] |= bigdisp;
4718 exp = &disp_expressions[i.disp_operands];
4719 i.op[this_operand].disps = exp;
4721 save_input_line_pointer = input_line_pointer;
4722 input_line_pointer = disp_start;
4723 END_STRING_AND_SAVE (disp_end);
4725 #ifndef GCC_ASM_O_HACK
4726 #define GCC_ASM_O_HACK 0
4729 END_STRING_AND_SAVE (disp_end + 1);
4730 if ((i.types[this_operand] & BaseIndex) != 0
4731 && displacement_string_end[-1] == '+')
4733 /* This hack is to avoid a warning when using the "o"
4734 constraint within gcc asm statements.
4737 #define _set_tssldt_desc(n,addr,limit,type) \
4738 __asm__ __volatile__ ( \
4740 "movw %w1,2+%0\n\t" \
4742 "movb %b1,4+%0\n\t" \
4743 "movb %4,5+%0\n\t" \
4744 "movb $0,6+%0\n\t" \
4745 "movb %h1,7+%0\n\t" \
4747 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4749 This works great except that the output assembler ends
4750 up looking a bit weird if it turns out that there is
4751 no offset. You end up producing code that looks like:
4764 So here we provide the missing zero. */
4766 *displacement_string_end = '0';
4769 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4770 if (gotfree_input_line)
4771 input_line_pointer = gotfree_input_line;
4773 exp_seg = expression (exp);
4776 if (*input_line_pointer)
4777 as_bad (_("junk `%s' after expression"), input_line_pointer);
4779 RESTORE_END_STRING (disp_end + 1);
4781 RESTORE_END_STRING (disp_end);
4782 input_line_pointer = save_input_line_pointer;
4783 if (gotfree_input_line)
4784 free (gotfree_input_line);
4786 /* We do this to make sure that the section symbol is in
4787 the symbol table. We will ultimately change the relocation
4788 to be relative to the beginning of the section. */
4789 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4790 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4791 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4793 if (exp->X_op != O_symbol)
4795 as_bad (_("bad expression used with @%s"),
4796 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4802 if (S_IS_LOCAL (exp->X_add_symbol)
4803 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4804 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4805 exp->X_op = O_subtract;
4806 exp->X_op_symbol = GOT_symbol;
4807 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4808 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4809 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4810 i.reloc[this_operand] = BFD_RELOC_64;
4812 i.reloc[this_operand] = BFD_RELOC_32;
4815 if (exp->X_op == O_absent || exp->X_op == O_big)
4817 /* Missing or bad expr becomes absolute 0. */
4818 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4820 exp->X_op = O_constant;
4821 exp->X_add_number = 0;
4822 exp->X_add_symbol = (symbolS *) 0;
4823 exp->X_op_symbol = (symbolS *) 0;
4826 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4827 if (exp->X_op != O_constant
4828 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4829 && exp_seg != absolute_section
4830 && exp_seg != text_section
4831 && exp_seg != data_section
4832 && exp_seg != bss_section
4833 && exp_seg != undefined_section
4834 && !bfd_is_com_section (exp_seg))
4836 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4841 if (!(i.types[this_operand] & ~Disp))
4842 i.types[this_operand] &= types;
4847 /* Make sure the memory operand we've been dealt is valid.
4848 Return 1 on success, 0 on a failure. */
4851 i386_index_check (const char *operand_string)
4854 #if INFER_ADDR_PREFIX
4860 if ((current_templates->start->cpu_flags & CpuSVME)
4861 && current_templates->end[-1].operand_types[0] == AnyMem)
4863 /* Memory operands of SVME insns are special in that they only allow
4864 rAX as their memory address and ignore any segment override. */
4867 /* SKINIT is even more restrictive: it always requires EAX. */
4868 if (strcmp (current_templates->start->name, "skinit") == 0)
4870 else if (flag_code == CODE_64BIT)
4871 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4873 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4877 || !(i.base_reg->reg_type & Acc)
4878 || !(i.base_reg->reg_type & RegXX)
4880 || (i.types[0] & Disp))
4883 else if (flag_code == CODE_64BIT)
4885 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4888 && ((i.base_reg->reg_type & RegXX) == 0)
4889 && (i.base_reg->reg_type != BaseIndex
4892 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4893 != (RegXX | BaseIndex))))
4898 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4902 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4903 != (Reg16 | BaseIndex)))
4905 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4906 != (Reg16 | BaseIndex))
4908 && i.base_reg->reg_num < 6
4909 && i.index_reg->reg_num >= 6
4910 && i.log2_scale_factor == 0))))
4917 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4919 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4920 != (Reg32 | BaseIndex))))
4926 #if INFER_ADDR_PREFIX
4927 if (i.prefix[ADDR_PREFIX] == 0)
4929 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4931 /* Change the size of any displacement too. At most one of
4932 Disp16 or Disp32 is set.
4933 FIXME. There doesn't seem to be any real need for separate
4934 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4935 Removing them would probably clean up the code quite a lot. */
4936 if (flag_code != CODE_64BIT
4937 && (i.types[this_operand] & (Disp16 | Disp32)))
4938 i.types[this_operand] ^= (Disp16 | Disp32);
4943 as_bad (_("`%s' is not a valid base/index expression"),
4947 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4949 flag_code_names[flag_code]);
4954 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4958 i386_operand (char *operand_string)
4962 char *op_string = operand_string;
4964 if (is_space_char (*op_string))
4967 /* We check for an absolute prefix (differentiating,
4968 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4969 if (*op_string == ABSOLUTE_PREFIX)
4972 if (is_space_char (*op_string))
4974 i.types[this_operand] |= JumpAbsolute;
4977 /* Check if operand is a register. */
4978 if ((r = parse_register (op_string, &end_op)) != NULL)
4980 /* Check for a segment override by searching for ':' after a
4981 segment register. */
4983 if (is_space_char (*op_string))
4985 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4990 i.seg[i.mem_operands] = &es;
4993 i.seg[i.mem_operands] = &cs;
4996 i.seg[i.mem_operands] = &ss;
4999 i.seg[i.mem_operands] = &ds;
5002 i.seg[i.mem_operands] = &fs;
5005 i.seg[i.mem_operands] = &gs;
5009 /* Skip the ':' and whitespace. */
5011 if (is_space_char (*op_string))
5014 if (!is_digit_char (*op_string)
5015 && !is_identifier_char (*op_string)
5016 && *op_string != '('
5017 && *op_string != ABSOLUTE_PREFIX)
5019 as_bad (_("bad memory operand `%s'"), op_string);
5022 /* Handle case of %es:*foo. */
5023 if (*op_string == ABSOLUTE_PREFIX)
5026 if (is_space_char (*op_string))
5028 i.types[this_operand] |= JumpAbsolute;
5030 goto do_memory_reference;
5034 as_bad (_("junk `%s' after register"), op_string);
5037 i.types[this_operand] |= r->reg_type & ~BaseIndex;
5038 i.op[this_operand].regs = r;
5041 else if (*op_string == REGISTER_PREFIX)
5043 as_bad (_("bad register name `%s'"), op_string);
5046 else if (*op_string == IMMEDIATE_PREFIX)
5049 if (i.types[this_operand] & JumpAbsolute)
5051 as_bad (_("immediate operand illegal with absolute jump"));
5054 if (!i386_immediate (op_string))
5057 else if (is_digit_char (*op_string)
5058 || is_identifier_char (*op_string)
5059 || *op_string == '(')
5061 /* This is a memory reference of some sort. */
5064 /* Start and end of displacement string expression (if found). */
5065 char *displacement_string_start;
5066 char *displacement_string_end;
5068 do_memory_reference:
5069 if ((i.mem_operands == 1
5070 && (current_templates->start->opcode_modifier & IsString) == 0)
5071 || i.mem_operands == 2)
5073 as_bad (_("too many memory references for `%s'"),
5074 current_templates->start->name);
5078 /* Check for base index form. We detect the base index form by
5079 looking for an ')' at the end of the operand, searching
5080 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5082 base_string = op_string + strlen (op_string);
5085 if (is_space_char (*base_string))
5088 /* If we only have a displacement, set-up for it to be parsed later. */
5089 displacement_string_start = op_string;
5090 displacement_string_end = base_string + 1;
5092 if (*base_string == ')')
5095 unsigned int parens_balanced = 1;
5096 /* We've already checked that the number of left & right ()'s are
5097 equal, so this loop will not be infinite. */
5101 if (*base_string == ')')
5103 if (*base_string == '(')
5106 while (parens_balanced);
5108 temp_string = base_string;
5110 /* Skip past '(' and whitespace. */
5112 if (is_space_char (*base_string))
5115 if (*base_string == ','
5116 || ((i.base_reg = parse_register (base_string, &end_op))
5119 displacement_string_end = temp_string;
5121 i.types[this_operand] |= BaseIndex;
5125 base_string = end_op;
5126 if (is_space_char (*base_string))
5130 /* There may be an index reg or scale factor here. */
5131 if (*base_string == ',')
5134 if (is_space_char (*base_string))
5137 if ((i.index_reg = parse_register (base_string, &end_op))
5140 base_string = end_op;
5141 if (is_space_char (*base_string))
5143 if (*base_string == ',')
5146 if (is_space_char (*base_string))
5149 else if (*base_string != ')')
5151 as_bad (_("expecting `,' or `)' "
5152 "after index register in `%s'"),
5157 else if (*base_string == REGISTER_PREFIX)
5159 as_bad (_("bad register name `%s'"), base_string);
5163 /* Check for scale factor. */
5164 if (*base_string != ')')
5166 char *end_scale = i386_scale (base_string);
5171 base_string = end_scale;
5172 if (is_space_char (*base_string))
5174 if (*base_string != ')')
5176 as_bad (_("expecting `)' "
5177 "after scale factor in `%s'"),
5182 else if (!i.index_reg)
5184 as_bad (_("expecting index register or scale factor "
5185 "after `,'; got '%c'"),
5190 else if (*base_string != ')')
5192 as_bad (_("expecting `,' or `)' "
5193 "after base register in `%s'"),
5198 else if (*base_string == REGISTER_PREFIX)
5200 as_bad (_("bad register name `%s'"), base_string);
5205 /* If there's an expression beginning the operand, parse it,
5206 assuming displacement_string_start and
5207 displacement_string_end are meaningful. */
5208 if (displacement_string_start != displacement_string_end)
5210 if (!i386_displacement (displacement_string_start,
5211 displacement_string_end))
5215 /* Special case for (%dx) while doing input/output op. */
5217 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5219 && i.log2_scale_factor == 0
5220 && i.seg[i.mem_operands] == 0
5221 && (i.types[this_operand] & Disp) == 0)
5223 i.types[this_operand] = InOutPortReg;
5227 if (i386_index_check (operand_string) == 0)
5233 /* It's not a memory operand; argh! */
5234 as_bad (_("invalid char %s beginning operand %d `%s'"),
5235 output_invalid (*op_string),
5240 return 1; /* Normal return. */
5243 /* md_estimate_size_before_relax()
5245 Called just before relax() for rs_machine_dependent frags. The x86
5246 assembler uses these frags to handle variable size jump
5249 Any symbol that is now undefined will not become defined.
5250 Return the correct fr_subtype in the frag.
5251 Return the initial "guess for variable size of frag" to caller.
5252 The guess is actually the growth beyond the fixed part. Whatever
5253 we do to grow the fixed or variable part contributes to our
5257 md_estimate_size_before_relax (fragP, segment)
5261 /* We've already got fragP->fr_subtype right; all we have to do is
5262 check for un-relaxable symbols. On an ELF system, we can't relax
5263 an externally visible symbol, because it may be overridden by a
5265 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5268 && (S_IS_EXTERNAL (fragP->fr_symbol)
5269 || S_IS_WEAK (fragP->fr_symbol)))
5273 /* Symbol is undefined in this segment, or we need to keep a
5274 reloc so that weak symbols can be overridden. */
5275 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5276 enum bfd_reloc_code_real reloc_type;
5277 unsigned char *opcode;
5280 if (fragP->fr_var != NO_RELOC)
5281 reloc_type = fragP->fr_var;
5283 reloc_type = BFD_RELOC_16_PCREL;
5285 reloc_type = BFD_RELOC_32_PCREL;
5287 old_fr_fix = fragP->fr_fix;
5288 opcode = (unsigned char *) fragP->fr_opcode;
5290 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5293 /* Make jmp (0xeb) a (d)word displacement jump. */
5295 fragP->fr_fix += size;
5296 fix_new (fragP, old_fr_fix, size,
5298 fragP->fr_offset, 1,
5304 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5306 /* Negate the condition, and branch past an
5307 unconditional jump. */
5310 /* Insert an unconditional jump. */
5312 /* We added two extra opcode bytes, and have a two byte
5314 fragP->fr_fix += 2 + 2;
5315 fix_new (fragP, old_fr_fix + 2, 2,
5317 fragP->fr_offset, 1,
5324 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5329 fixP = fix_new (fragP, old_fr_fix, 1,
5331 fragP->fr_offset, 1,
5333 fixP->fx_signed = 1;
5337 /* This changes the byte-displacement jump 0x7N
5338 to the (d)word-displacement jump 0x0f,0x8N. */
5339 opcode[1] = opcode[0] + 0x10;
5340 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5341 /* We've added an opcode byte. */
5342 fragP->fr_fix += 1 + size;
5343 fix_new (fragP, old_fr_fix + 1, size,
5345 fragP->fr_offset, 1,
5350 BAD_CASE (fragP->fr_subtype);
5354 return fragP->fr_fix - old_fr_fix;
5357 /* Guess size depending on current relax state. Initially the relax
5358 state will correspond to a short jump and we return 1, because
5359 the variable part of the frag (the branch offset) is one byte
5360 long. However, we can relax a section more than once and in that
5361 case we must either set fr_subtype back to the unrelaxed state,
5362 or return the value for the appropriate branch. */
5363 return md_relax_table[fragP->fr_subtype].rlx_length;
5366 /* Called after relax() is finished.
5368 In: Address of frag.
5369 fr_type == rs_machine_dependent.
5370 fr_subtype is what the address relaxed to.
5372 Out: Any fixSs and constants are set up.
5373 Caller will turn frag into a ".space 0". */
5376 md_convert_frag (abfd, sec, fragP)
5377 bfd *abfd ATTRIBUTE_UNUSED;
5378 segT sec ATTRIBUTE_UNUSED;
5381 unsigned char *opcode;
5382 unsigned char *where_to_put_displacement = NULL;
5383 offsetT target_address;
5384 offsetT opcode_address;
5385 unsigned int extension = 0;
5386 offsetT displacement_from_opcode_start;
5388 opcode = (unsigned char *) fragP->fr_opcode;
5390 /* Address we want to reach in file space. */
5391 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5393 /* Address opcode resides at in file space. */
5394 opcode_address = fragP->fr_address + fragP->fr_fix;
5396 /* Displacement from opcode start to fill into instruction. */
5397 displacement_from_opcode_start = target_address - opcode_address;
5399 if ((fragP->fr_subtype & BIG) == 0)
5401 /* Don't have to change opcode. */
5402 extension = 1; /* 1 opcode + 1 displacement */
5403 where_to_put_displacement = &opcode[1];
5407 if (no_cond_jump_promotion
5408 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5409 as_warn_where (fragP->fr_file, fragP->fr_line,
5410 _("long jump required"));
5412 switch (fragP->fr_subtype)
5414 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5415 extension = 4; /* 1 opcode + 4 displacement */
5417 where_to_put_displacement = &opcode[1];
5420 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5421 extension = 2; /* 1 opcode + 2 displacement */
5423 where_to_put_displacement = &opcode[1];
5426 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5427 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5428 extension = 5; /* 2 opcode + 4 displacement */
5429 opcode[1] = opcode[0] + 0x10;
5430 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5431 where_to_put_displacement = &opcode[2];
5434 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5435 extension = 3; /* 2 opcode + 2 displacement */
5436 opcode[1] = opcode[0] + 0x10;
5437 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5438 where_to_put_displacement = &opcode[2];
5441 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5446 where_to_put_displacement = &opcode[3];
5450 BAD_CASE (fragP->fr_subtype);
5455 /* If size if less then four we are sure that the operand fits,
5456 but if it's 4, then it could be that the displacement is larger
5458 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5460 && ((addressT) (displacement_from_opcode_start - extension
5461 + ((addressT) 1 << 31))
5462 > (((addressT) 2 << 31) - 1)))
5464 as_bad_where (fragP->fr_file, fragP->fr_line,
5465 _("jump target out of range"));
5466 /* Make us emit 0. */
5467 displacement_from_opcode_start = extension;
5469 /* Now put displacement after opcode. */
5470 md_number_to_chars ((char *) where_to_put_displacement,
5471 (valueT) (displacement_from_opcode_start - extension),
5472 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5473 fragP->fr_fix += extension;
5476 /* Size of byte displacement jmp. */
5477 int md_short_jump_size = 2;
5479 /* Size of dword displacement jmp. */
5480 int md_long_jump_size = 5;
5483 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5485 addressT from_addr, to_addr;
5486 fragS *frag ATTRIBUTE_UNUSED;
5487 symbolS *to_symbol ATTRIBUTE_UNUSED;
5491 offset = to_addr - (from_addr + 2);
5492 /* Opcode for byte-disp jump. */
5493 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5494 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5498 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5500 addressT from_addr, to_addr;
5501 fragS *frag ATTRIBUTE_UNUSED;
5502 symbolS *to_symbol ATTRIBUTE_UNUSED;
5506 offset = to_addr - (from_addr + 5);
5507 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5508 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5511 /* Apply a fixup (fixS) to segment data, once it has been determined
5512 by our caller that we have all the info we need to fix it up.
5514 On the 386, immediates, displacements, and data pointers are all in
5515 the same (little-endian) format, so we don't need to care about which
5519 md_apply_fix (fixP, valP, seg)
5520 /* The fix we're to put in. */
5522 /* Pointer to the value of the bits. */
5524 /* Segment fix is from. */
5525 segT seg ATTRIBUTE_UNUSED;
5527 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5528 valueT value = *valP;
5530 #if !defined (TE_Mach)
5533 switch (fixP->fx_r_type)
5539 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5542 case BFD_RELOC_X86_64_32S:
5543 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5546 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5549 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5554 if (fixP->fx_addsy != NULL
5555 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5556 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5557 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5558 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5559 && !use_rela_relocations)
5561 /* This is a hack. There should be a better way to handle this.
5562 This covers for the fact that bfd_install_relocation will
5563 subtract the current location (for partial_inplace, PC relative
5564 relocations); see more below. */
5568 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5571 value += fixP->fx_where + fixP->fx_frag->fr_address;
5573 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5576 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5579 || (symbol_section_p (fixP->fx_addsy)
5580 && sym_seg != absolute_section))
5581 && !generic_force_reloc (fixP))
5583 /* Yes, we add the values in twice. This is because
5584 bfd_install_relocation subtracts them out again. I think
5585 bfd_install_relocation is broken, but I don't dare change
5587 value += fixP->fx_where + fixP->fx_frag->fr_address;
5591 #if defined (OBJ_COFF) && defined (TE_PE)
5592 /* For some reason, the PE format does not store a
5593 section address offset for a PC relative symbol. */
5594 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5595 || S_IS_WEAK (fixP->fx_addsy))
5596 value += md_pcrel_from (fixP);
5600 /* Fix a few things - the dynamic linker expects certain values here,
5601 and we must not disappoint it. */
5602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5603 if (IS_ELF && fixP->fx_addsy)
5604 switch (fixP->fx_r_type)
5606 case BFD_RELOC_386_PLT32:
5607 case BFD_RELOC_X86_64_PLT32:
5608 /* Make the jump instruction point to the address of the operand. At
5609 runtime we merely add the offset to the actual PLT entry. */
5613 case BFD_RELOC_386_TLS_GD:
5614 case BFD_RELOC_386_TLS_LDM:
5615 case BFD_RELOC_386_TLS_IE_32:
5616 case BFD_RELOC_386_TLS_IE:
5617 case BFD_RELOC_386_TLS_GOTIE:
5618 case BFD_RELOC_386_TLS_GOTDESC:
5619 case BFD_RELOC_X86_64_TLSGD:
5620 case BFD_RELOC_X86_64_TLSLD:
5621 case BFD_RELOC_X86_64_GOTTPOFF:
5622 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5623 value = 0; /* Fully resolved at runtime. No addend. */
5625 case BFD_RELOC_386_TLS_LE:
5626 case BFD_RELOC_386_TLS_LDO_32:
5627 case BFD_RELOC_386_TLS_LE_32:
5628 case BFD_RELOC_X86_64_DTPOFF32:
5629 case BFD_RELOC_X86_64_DTPOFF64:
5630 case BFD_RELOC_X86_64_TPOFF32:
5631 case BFD_RELOC_X86_64_TPOFF64:
5632 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5635 case BFD_RELOC_386_TLS_DESC_CALL:
5636 case BFD_RELOC_X86_64_TLSDESC_CALL:
5637 value = 0; /* Fully resolved at runtime. No addend. */
5638 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5642 case BFD_RELOC_386_GOT32:
5643 case BFD_RELOC_X86_64_GOT32:
5644 value = 0; /* Fully resolved at runtime. No addend. */
5647 case BFD_RELOC_VTABLE_INHERIT:
5648 case BFD_RELOC_VTABLE_ENTRY:
5655 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5657 #endif /* !defined (TE_Mach) */
5659 /* Are we finished with this relocation now? */
5660 if (fixP->fx_addsy == NULL)
5662 else if (use_rela_relocations)
5664 fixP->fx_no_overflow = 1;
5665 /* Remember value for tc_gen_reloc. */
5666 fixP->fx_addnumber = value;
5670 md_number_to_chars (p, value, fixP->fx_size);
5673 #define MAX_LITTLENUMS 6
5675 /* Turn the string pointed to by litP into a floating point constant
5676 of type TYPE, and emit the appropriate bytes. The number of
5677 LITTLENUMS emitted is stored in *SIZEP. An error message is
5678 returned, or NULL on OK. */
5681 md_atof (type, litP, sizeP)
5687 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5688 LITTLENUM_TYPE *wordP;
5710 return _("Bad call to md_atof ()");
5712 t = atof_ieee (input_line_pointer, type, words);
5714 input_line_pointer = t;
5716 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5717 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5718 the bigendian 386. */
5719 for (wordP = words + prec - 1; prec--;)
5721 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5722 litP += sizeof (LITTLENUM_TYPE);
5727 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5730 output_invalid (int c)
5733 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5736 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5737 "(0x%x)", (unsigned char) c);
5738 return output_invalid_buf;
5741 /* REG_STRING starts *before* REGISTER_PREFIX. */
5743 static const reg_entry *
5744 parse_real_register (char *reg_string, char **end_op)
5746 char *s = reg_string;
5748 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5751 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5752 if (*s == REGISTER_PREFIX)
5755 if (is_space_char (*s))
5759 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5761 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5762 return (const reg_entry *) NULL;
5766 /* For naked regs, make sure that we are not dealing with an identifier.
5767 This prevents confusing an identifier like `eax_var' with register
5769 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5770 return (const reg_entry *) NULL;
5774 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5776 /* Handle floating point regs, allowing spaces in the (i) part. */
5777 if (r == i386_regtab /* %st is first entry of table */)
5779 if (is_space_char (*s))
5784 if (is_space_char (*s))
5786 if (*s >= '0' && *s <= '7')
5788 r = &i386_float_regtab[*s - '0'];
5790 if (is_space_char (*s))
5798 /* We have "%st(" then garbage. */
5799 return (const reg_entry *) NULL;
5804 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5805 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5806 && flag_code != CODE_64BIT)
5807 return (const reg_entry *) NULL;
5812 /* REG_STRING starts *before* REGISTER_PREFIX. */
5814 static const reg_entry *
5815 parse_register (char *reg_string, char **end_op)
5819 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5820 r = parse_real_register (reg_string, end_op);
5825 char *save = input_line_pointer;
5829 input_line_pointer = reg_string;
5830 c = get_symbol_end ();
5831 symbolP = symbol_find (reg_string);
5832 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5834 const expressionS *e = symbol_get_value_expression (symbolP);
5836 know (e->X_op == O_register);
5837 know (e->X_add_number >= 0
5838 && (valueT) e->X_add_number < i386_regtab_size);
5839 r = i386_regtab + e->X_add_number;
5840 *end_op = input_line_pointer;
5842 *input_line_pointer = c;
5843 input_line_pointer = save;
5849 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5852 char *end = input_line_pointer;
5855 r = parse_register (name, &input_line_pointer);
5856 if (r && end <= input_line_pointer)
5858 *nextcharP = *input_line_pointer;
5859 *input_line_pointer = 0;
5860 e->X_op = O_register;
5861 e->X_add_number = r - i386_regtab;
5864 input_line_pointer = end;
5870 md_operand (expressionS *e)
5872 if (*input_line_pointer == REGISTER_PREFIX)
5875 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5879 e->X_op = O_register;
5880 e->X_add_number = r - i386_regtab;
5881 input_line_pointer = end;
5887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5888 const char *md_shortopts = "kVQ:sqn";
5890 const char *md_shortopts = "qn";
5893 #define OPTION_32 (OPTION_MD_BASE + 0)
5894 #define OPTION_64 (OPTION_MD_BASE + 1)
5895 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5896 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5897 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5899 struct option md_longopts[] =
5901 {"32", no_argument, NULL, OPTION_32},
5902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5903 {"64", no_argument, NULL, OPTION_64},
5905 {"divide", no_argument, NULL, OPTION_DIVIDE},
5906 {"march", required_argument, NULL, OPTION_MARCH},
5907 {"mtune", required_argument, NULL, OPTION_MTUNE},
5908 {NULL, no_argument, NULL, 0}
5910 size_t md_longopts_size = sizeof (md_longopts);
5913 md_parse_option (int c, char *arg)
5920 optimize_align_code = 0;
5927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5928 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5929 should be emitted or not. FIXME: Not implemented. */
5933 /* -V: SVR4 argument to print version ID. */
5935 print_version_id ();
5938 /* -k: Ignore for FreeBSD compatibility. */
5943 /* -s: On i386 Solaris, this tells the native assembler to use
5944 .stab instead of .stab.excl. We always use .stab anyhow. */
5947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5950 const char **list, **l;
5952 list = bfd_target_list ();
5953 for (l = list; *l != NULL; l++)
5954 if (CONST_STRNEQ (*l, "elf64-x86-64")
5955 || strcmp (*l, "coff-x86-64") == 0
5956 || strcmp (*l, "pe-x86-64") == 0
5957 || strcmp (*l, "pei-x86-64") == 0)
5959 default_arch = "x86_64";
5963 as_fatal (_("No compiled in support for x86_64"));
5970 default_arch = "i386";
5974 #ifdef SVR4_COMMENT_CHARS
5979 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5981 for (s = i386_comment_chars; *s != '\0'; s++)
5985 i386_comment_chars = n;
5992 as_fatal (_("Invalid -march= option: `%s'"), arg);
5993 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5995 if (strcmp (arg, cpu_arch [i].name) == 0)
5997 cpu_arch_isa = cpu_arch[i].type;
5998 cpu_arch_isa_flags = cpu_arch[i].flags;
5999 if (!cpu_arch_tune_set)
6001 cpu_arch_tune = cpu_arch_isa;
6002 cpu_arch_tune_flags = cpu_arch_isa_flags;
6007 if (i >= ARRAY_SIZE (cpu_arch))
6008 as_fatal (_("Invalid -march= option: `%s'"), arg);
6013 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6014 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6016 if (strcmp (arg, cpu_arch [i].name) == 0)
6018 cpu_arch_tune_set = 1;
6019 cpu_arch_tune = cpu_arch [i].type;
6020 cpu_arch_tune_flags = cpu_arch[i].flags;
6024 if (i >= ARRAY_SIZE (cpu_arch))
6025 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6035 md_show_usage (stream)
6038 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6039 fprintf (stream, _("\
6041 -V print assembler version number\n\
6044 fprintf (stream, _("\
6045 -n Do not optimize code alignment\n\
6046 -q quieten some warnings\n"));
6047 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6048 fprintf (stream, _("\
6051 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6052 fprintf (stream, _("\
6053 --32/--64 generate 32bit/64bit code\n"));
6055 #ifdef SVR4_COMMENT_CHARS
6056 fprintf (stream, _("\
6057 --divide do not treat `/' as a comment character\n"));
6059 fprintf (stream, _("\
6060 --divide ignored\n"));
6062 fprintf (stream, _("\
6063 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6064 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6065 core, core2, k6, athlon, k8, generic32, generic64\n"));
6071 x86_64_target_format (void)
6073 if (strcmp (default_arch, "x86_64") == 0)
6075 set_code_flag (CODE_64BIT);
6076 return COFF_TARGET_FORMAT;
6078 else if (strcmp (default_arch, "i386") == 0)
6080 set_code_flag (CODE_32BIT);
6084 as_fatal (_("Unknown architecture"));
6089 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6090 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6092 /* Pick the target format to use. */
6095 i386_target_format (void)
6097 if (!strcmp (default_arch, "x86_64"))
6099 set_code_flag (CODE_64BIT);
6100 if (cpu_arch_isa_flags == 0)
6101 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6102 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6104 if (cpu_arch_tune_flags == 0)
6105 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6106 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6109 else if (!strcmp (default_arch, "i386"))
6111 set_code_flag (CODE_32BIT);
6112 if (cpu_arch_isa_flags == 0)
6113 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6114 if (cpu_arch_tune_flags == 0)
6115 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6118 as_fatal (_("Unknown architecture"));
6119 switch (OUTPUT_FLAVOR)
6121 #ifdef OBJ_MAYBE_AOUT
6122 case bfd_target_aout_flavour:
6123 return AOUT_TARGET_FORMAT;
6125 #ifdef OBJ_MAYBE_COFF
6126 case bfd_target_coff_flavour:
6129 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6130 case bfd_target_elf_flavour:
6132 if (flag_code == CODE_64BIT)
6135 use_rela_relocations = 1;
6137 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6146 #endif /* OBJ_MAYBE_ more than one */
6148 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6150 i386_elf_emit_arch_note (void)
6152 if (IS_ELF && cpu_arch_name != NULL)
6155 asection *seg = now_seg;
6156 subsegT subseg = now_subseg;
6157 Elf_Internal_Note i_note;
6158 Elf_External_Note e_note;
6159 asection *note_secp;
6162 /* Create the .note section. */
6163 note_secp = subseg_new (".note", 0);
6164 bfd_set_section_flags (stdoutput,
6166 SEC_HAS_CONTENTS | SEC_READONLY);
6168 /* Process the arch string. */
6169 len = strlen (cpu_arch_name);
6171 i_note.namesz = len + 1;
6173 i_note.type = NT_ARCH;
6174 p = frag_more (sizeof (e_note.namesz));
6175 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6176 p = frag_more (sizeof (e_note.descsz));
6177 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6178 p = frag_more (sizeof (e_note.type));
6179 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6180 p = frag_more (len + 1);
6181 strcpy (p, cpu_arch_name);
6183 frag_align (2, 0, 0);
6185 subseg_set (seg, subseg);
6191 md_undefined_symbol (name)
6194 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6195 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6196 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6197 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6201 if (symbol_find (name))
6202 as_bad (_("GOT already in symbol table"));
6203 GOT_symbol = symbol_new (name, undefined_section,
6204 (valueT) 0, &zero_address_frag);
6211 /* Round up a section size to the appropriate boundary. */
6214 md_section_align (segment, size)
6215 segT segment ATTRIBUTE_UNUSED;
6218 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6219 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6221 /* For a.out, force the section size to be aligned. If we don't do
6222 this, BFD will align it for us, but it will not write out the
6223 final bytes of the section. This may be a bug in BFD, but it is
6224 easier to fix it here since that is how the other a.out targets
6228 align = bfd_get_section_alignment (stdoutput, segment);
6229 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6236 /* On the i386, PC-relative offsets are relative to the start of the
6237 next instruction. That is, the address of the offset, plus its
6238 size, since the offset is always the last part of the insn. */
6241 md_pcrel_from (fixS *fixP)
6243 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6249 s_bss (int ignore ATTRIBUTE_UNUSED)
6253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6255 obj_elf_section_change_hook ();
6257 temp = get_absolute_expression ();
6258 subseg_set (bss_section, (subsegT) temp);
6259 demand_empty_rest_of_line ();
6265 i386_validate_fix (fixS *fixp)
6267 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6269 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6273 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6278 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6280 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6287 tc_gen_reloc (section, fixp)
6288 asection *section ATTRIBUTE_UNUSED;
6292 bfd_reloc_code_real_type code;
6294 switch (fixp->fx_r_type)
6296 case BFD_RELOC_X86_64_PLT32:
6297 case BFD_RELOC_X86_64_GOT32:
6298 case BFD_RELOC_X86_64_GOTPCREL:
6299 case BFD_RELOC_386_PLT32:
6300 case BFD_RELOC_386_GOT32:
6301 case BFD_RELOC_386_GOTOFF:
6302 case BFD_RELOC_386_GOTPC:
6303 case BFD_RELOC_386_TLS_GD:
6304 case BFD_RELOC_386_TLS_LDM:
6305 case BFD_RELOC_386_TLS_LDO_32:
6306 case BFD_RELOC_386_TLS_IE_32:
6307 case BFD_RELOC_386_TLS_IE:
6308 case BFD_RELOC_386_TLS_GOTIE:
6309 case BFD_RELOC_386_TLS_LE_32:
6310 case BFD_RELOC_386_TLS_LE:
6311 case BFD_RELOC_386_TLS_GOTDESC:
6312 case BFD_RELOC_386_TLS_DESC_CALL:
6313 case BFD_RELOC_X86_64_TLSGD:
6314 case BFD_RELOC_X86_64_TLSLD:
6315 case BFD_RELOC_X86_64_DTPOFF32:
6316 case BFD_RELOC_X86_64_DTPOFF64:
6317 case BFD_RELOC_X86_64_GOTTPOFF:
6318 case BFD_RELOC_X86_64_TPOFF32:
6319 case BFD_RELOC_X86_64_TPOFF64:
6320 case BFD_RELOC_X86_64_GOTOFF64:
6321 case BFD_RELOC_X86_64_GOTPC32:
6322 case BFD_RELOC_X86_64_GOT64:
6323 case BFD_RELOC_X86_64_GOTPCREL64:
6324 case BFD_RELOC_X86_64_GOTPC64:
6325 case BFD_RELOC_X86_64_GOTPLT64:
6326 case BFD_RELOC_X86_64_PLTOFF64:
6327 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6328 case BFD_RELOC_X86_64_TLSDESC_CALL:
6330 case BFD_RELOC_VTABLE_ENTRY:
6331 case BFD_RELOC_VTABLE_INHERIT:
6333 case BFD_RELOC_32_SECREL:
6335 code = fixp->fx_r_type;
6337 case BFD_RELOC_X86_64_32S:
6338 if (!fixp->fx_pcrel)
6340 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6341 code = fixp->fx_r_type;
6347 switch (fixp->fx_size)
6350 as_bad_where (fixp->fx_file, fixp->fx_line,
6351 _("can not do %d byte pc-relative relocation"),
6353 code = BFD_RELOC_32_PCREL;
6355 case 1: code = BFD_RELOC_8_PCREL; break;
6356 case 2: code = BFD_RELOC_16_PCREL; break;
6357 case 4: code = BFD_RELOC_32_PCREL; break;
6359 case 8: code = BFD_RELOC_64_PCREL; break;
6365 switch (fixp->fx_size)
6368 as_bad_where (fixp->fx_file, fixp->fx_line,
6369 _("can not do %d byte relocation"),
6371 code = BFD_RELOC_32;
6373 case 1: code = BFD_RELOC_8; break;
6374 case 2: code = BFD_RELOC_16; break;
6375 case 4: code = BFD_RELOC_32; break;
6377 case 8: code = BFD_RELOC_64; break;
6384 if ((code == BFD_RELOC_32
6385 || code == BFD_RELOC_32_PCREL
6386 || code == BFD_RELOC_X86_64_32S)
6388 && fixp->fx_addsy == GOT_symbol)
6391 code = BFD_RELOC_386_GOTPC;
6393 code = BFD_RELOC_X86_64_GOTPC32;
6395 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6397 && fixp->fx_addsy == GOT_symbol)
6399 code = BFD_RELOC_X86_64_GOTPC64;
6402 rel = (arelent *) xmalloc (sizeof (arelent));
6403 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6404 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6406 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6408 if (!use_rela_relocations)
6410 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6411 vtable entry to be used in the relocation's section offset. */
6412 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6413 rel->address = fixp->fx_offset;
6417 /* Use the rela in 64bit mode. */
6420 if (!fixp->fx_pcrel)
6421 rel->addend = fixp->fx_offset;
6425 case BFD_RELOC_X86_64_PLT32:
6426 case BFD_RELOC_X86_64_GOT32:
6427 case BFD_RELOC_X86_64_GOTPCREL:
6428 case BFD_RELOC_X86_64_TLSGD:
6429 case BFD_RELOC_X86_64_TLSLD:
6430 case BFD_RELOC_X86_64_GOTTPOFF:
6431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6432 case BFD_RELOC_X86_64_TLSDESC_CALL:
6433 rel->addend = fixp->fx_offset - fixp->fx_size;
6436 rel->addend = (section->vma
6438 + fixp->fx_addnumber
6439 + md_pcrel_from (fixp));
6444 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6445 if (rel->howto == NULL)
6447 as_bad_where (fixp->fx_file, fixp->fx_line,
6448 _("cannot represent relocation type %s"),
6449 bfd_get_reloc_code_name (code));
6450 /* Set howto to a garbage value so that we can keep going. */
6451 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6452 assert (rel->howto != NULL);
6459 /* Parse operands using Intel syntax. This implements a recursive descent
6460 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6463 FIXME: We do not recognize the full operand grammar defined in the MASM
6464 documentation. In particular, all the structure/union and
6465 high-level macro operands are missing.
6467 Uppercase words are terminals, lower case words are non-terminals.
6468 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6469 bars '|' denote choices. Most grammar productions are implemented in
6470 functions called 'intel_<production>'.
6472 Initial production is 'expr'.
6478 binOp & | AND | \| | OR | ^ | XOR
6480 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6482 constant digits [[ radixOverride ]]
6484 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6522 => expr expr cmpOp e04
6525 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6526 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6528 hexdigit a | b | c | d | e | f
6529 | A | B | C | D | E | F
6535 mulOp * | / | % | MOD | << | SHL | >> | SHR
6539 register specialRegister
6543 segmentRegister CS | DS | ES | FS | GS | SS
6545 specialRegister CR0 | CR2 | CR3 | CR4
6546 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6547 | TR3 | TR4 | TR5 | TR6 | TR7
6549 We simplify the grammar in obvious places (e.g., register parsing is
6550 done by calling parse_register) and eliminate immediate left recursion
6551 to implement a recursive-descent parser.
6555 expr' cmpOp e04 expr'
6606 /* Parsing structure for the intel syntax parser. Used to implement the
6607 semantic actions for the operand grammar. */
6608 struct intel_parser_s
6610 char *op_string; /* The string being parsed. */
6611 int got_a_float; /* Whether the operand is a float. */
6612 int op_modifier; /* Operand modifier. */
6613 int is_mem; /* 1 if operand is memory reference. */
6614 int in_offset; /* >=1 if parsing operand of offset. */
6615 int in_bracket; /* >=1 if parsing operand in brackets. */
6616 const reg_entry *reg; /* Last register reference found. */
6617 char *disp; /* Displacement string being built. */
6618 char *next_operand; /* Resume point when splitting operands. */
6621 static struct intel_parser_s intel_parser;
6623 /* Token structure for parsing intel syntax. */
6626 int code; /* Token code. */
6627 const reg_entry *reg; /* Register entry for register tokens. */
6628 char *str; /* String representation. */
6631 static struct intel_token cur_token, prev_token;
6633 /* Token codes for the intel parser. Since T_SHORT is already used
6634 by COFF, undefine it first to prevent a warning. */
6653 /* Prototypes for intel parser functions. */
6654 static int intel_match_token (int);
6655 static void intel_putback_token (void);
6656 static void intel_get_token (void);
6657 static int intel_expr (void);
6658 static int intel_e04 (void);
6659 static int intel_e05 (void);
6660 static int intel_e06 (void);
6661 static int intel_e09 (void);
6662 static int intel_e10 (void);
6663 static int intel_e11 (void);
6666 i386_intel_operand (char *operand_string, int got_a_float)
6671 p = intel_parser.op_string = xstrdup (operand_string);
6672 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6676 /* Initialize token holders. */
6677 cur_token.code = prev_token.code = T_NIL;
6678 cur_token.reg = prev_token.reg = NULL;
6679 cur_token.str = prev_token.str = NULL;
6681 /* Initialize parser structure. */
6682 intel_parser.got_a_float = got_a_float;
6683 intel_parser.op_modifier = 0;
6684 intel_parser.is_mem = 0;
6685 intel_parser.in_offset = 0;
6686 intel_parser.in_bracket = 0;
6687 intel_parser.reg = NULL;
6688 intel_parser.disp[0] = '\0';
6689 intel_parser.next_operand = NULL;
6691 /* Read the first token and start the parser. */
6693 ret = intel_expr ();
6698 if (cur_token.code != T_NIL)
6700 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6701 current_templates->start->name, cur_token.str);
6704 /* If we found a memory reference, hand it over to i386_displacement
6705 to fill in the rest of the operand fields. */
6706 else if (intel_parser.is_mem)
6708 if ((i.mem_operands == 1
6709 && (current_templates->start->opcode_modifier & IsString) == 0)
6710 || i.mem_operands == 2)
6712 as_bad (_("too many memory references for '%s'"),
6713 current_templates->start->name);
6718 char *s = intel_parser.disp;
6721 if (!quiet_warnings && intel_parser.is_mem < 0)
6722 /* See the comments in intel_bracket_expr. */
6723 as_warn (_("Treating `%s' as memory reference"), operand_string);
6725 /* Add the displacement expression. */
6727 ret = i386_displacement (s, s + strlen (s));
6730 /* Swap base and index in 16-bit memory operands like
6731 [si+bx]. Since i386_index_check is also used in AT&T
6732 mode we have to do that here. */
6735 && (i.base_reg->reg_type & Reg16)
6736 && (i.index_reg->reg_type & Reg16)
6737 && i.base_reg->reg_num >= 6
6738 && i.index_reg->reg_num < 6)
6740 const reg_entry *base = i.index_reg;
6742 i.index_reg = i.base_reg;
6745 ret = i386_index_check (operand_string);
6750 /* Constant and OFFSET expressions are handled by i386_immediate. */
6751 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6752 || intel_parser.reg == NULL)
6753 ret = i386_immediate (intel_parser.disp);
6755 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6757 if (!ret || !intel_parser.next_operand)
6759 intel_parser.op_string = intel_parser.next_operand;
6760 this_operand = i.operands++;
6764 free (intel_parser.disp);
6769 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6773 expr' cmpOp e04 expr'
6778 /* XXX Implement the comparison operators. */
6779 return intel_e04 ();
6796 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6797 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6799 if (cur_token.code == '+')
6801 else if (cur_token.code == '-')
6802 nregs = NUM_ADDRESS_REGS;
6806 strcat (intel_parser.disp, cur_token.str);
6807 intel_match_token (cur_token.code);
6818 int nregs = ~NUM_ADDRESS_REGS;
6825 if (cur_token.code == '&'
6826 || cur_token.code == '|'
6827 || cur_token.code == '^')
6831 str[0] = cur_token.code;
6833 strcat (intel_parser.disp, str);
6838 intel_match_token (cur_token.code);
6843 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6844 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6855 int nregs = ~NUM_ADDRESS_REGS;
6862 if (cur_token.code == '*'
6863 || cur_token.code == '/'
6864 || cur_token.code == '%')
6868 str[0] = cur_token.code;
6870 strcat (intel_parser.disp, str);
6872 else if (cur_token.code == T_SHL)
6873 strcat (intel_parser.disp, "<<");
6874 else if (cur_token.code == T_SHR)
6875 strcat (intel_parser.disp, ">>");
6879 intel_match_token (cur_token.code);
6884 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6885 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6903 int nregs = ~NUM_ADDRESS_REGS;
6908 /* Don't consume constants here. */
6909 if (cur_token.code == '+' || cur_token.code == '-')
6911 /* Need to look one token ahead - if the next token
6912 is a constant, the current token is its sign. */
6915 intel_match_token (cur_token.code);
6916 next_code = cur_token.code;
6917 intel_putback_token ();
6918 if (next_code == T_CONST)
6922 /* e09 OFFSET e09 */
6923 if (cur_token.code == T_OFFSET)
6926 ++intel_parser.in_offset;
6930 else if (cur_token.code == T_SHORT)
6931 intel_parser.op_modifier |= 1 << T_SHORT;
6934 else if (cur_token.code == '+')
6935 strcat (intel_parser.disp, "+");
6940 else if (cur_token.code == '-' || cur_token.code == '~')
6946 str[0] = cur_token.code;
6948 strcat (intel_parser.disp, str);
6955 intel_match_token (cur_token.code);
6963 /* e09' PTR e10 e09' */
6964 if (cur_token.code == T_PTR)
6968 if (prev_token.code == T_BYTE)
6969 suffix = BYTE_MNEM_SUFFIX;
6971 else if (prev_token.code == T_WORD)
6973 if (current_templates->start->name[0] == 'l'
6974 && current_templates->start->name[2] == 's'
6975 && current_templates->start->name[3] == 0)
6976 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6977 else if (intel_parser.got_a_float == 2) /* "fi..." */
6978 suffix = SHORT_MNEM_SUFFIX;
6980 suffix = WORD_MNEM_SUFFIX;
6983 else if (prev_token.code == T_DWORD)
6985 if (current_templates->start->name[0] == 'l'
6986 && current_templates->start->name[2] == 's'
6987 && current_templates->start->name[3] == 0)
6988 suffix = WORD_MNEM_SUFFIX;
6989 else if (flag_code == CODE_16BIT
6990 && (current_templates->start->opcode_modifier
6991 & (Jump | JumpDword)))
6992 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6993 else if (intel_parser.got_a_float == 1) /* "f..." */
6994 suffix = SHORT_MNEM_SUFFIX;
6996 suffix = LONG_MNEM_SUFFIX;
6999 else if (prev_token.code == T_FWORD)
7001 if (current_templates->start->name[0] == 'l'
7002 && current_templates->start->name[2] == 's'
7003 && current_templates->start->name[3] == 0)
7004 suffix = LONG_MNEM_SUFFIX;
7005 else if (!intel_parser.got_a_float)
7007 if (flag_code == CODE_16BIT)
7008 add_prefix (DATA_PREFIX_OPCODE);
7009 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7012 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7015 else if (prev_token.code == T_QWORD)
7017 if (intel_parser.got_a_float == 1) /* "f..." */
7018 suffix = LONG_MNEM_SUFFIX;
7020 suffix = QWORD_MNEM_SUFFIX;
7023 else if (prev_token.code == T_TBYTE)
7025 if (intel_parser.got_a_float == 1)
7026 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7028 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7031 else if (prev_token.code == T_XMMWORD)
7033 /* XXX ignored for now, but accepted since gcc uses it */
7039 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7043 /* Operands for jump/call using 'ptr' notation denote absolute
7045 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7046 i.types[this_operand] |= JumpAbsolute;
7048 if (current_templates->start->base_opcode == 0x8d /* lea */)
7052 else if (i.suffix != suffix)
7054 as_bad (_("Conflicting operand modifiers"));
7060 /* e09' : e10 e09' */
7061 else if (cur_token.code == ':')
7063 if (prev_token.code != T_REG)
7065 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7066 segment/group identifier (which we don't have), using comma
7067 as the operand separator there is even less consistent, since
7068 there all branches only have a single operand. */
7069 if (this_operand != 0
7070 || intel_parser.in_offset
7071 || intel_parser.in_bracket
7072 || (!(current_templates->start->opcode_modifier
7073 & (Jump|JumpDword|JumpInterSegment))
7074 && !(current_templates->start->operand_types[0]
7076 return intel_match_token (T_NIL);
7077 /* Remember the start of the 2nd operand and terminate 1st
7079 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7080 another expression), but it gets at least the simplest case
7081 (a plain number or symbol on the left side) right. */
7082 intel_parser.next_operand = intel_parser.op_string;
7083 *--intel_parser.op_string = '\0';
7084 return intel_match_token (':');
7092 intel_match_token (cur_token.code);
7098 --intel_parser.in_offset;
7101 if (NUM_ADDRESS_REGS > nregs)
7103 as_bad (_("Invalid operand to `OFFSET'"));
7106 intel_parser.op_modifier |= 1 << T_OFFSET;
7109 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7110 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7115 intel_bracket_expr (void)
7117 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7118 const char *start = intel_parser.op_string;
7121 if (i.op[this_operand].regs)
7122 return intel_match_token (T_NIL);
7124 intel_match_token ('[');
7126 /* Mark as a memory operand only if it's not already known to be an
7127 offset expression. If it's an offset expression, we need to keep
7129 if (!intel_parser.in_offset)
7131 ++intel_parser.in_bracket;
7133 /* Operands for jump/call inside brackets denote absolute addresses. */
7134 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7135 i.types[this_operand] |= JumpAbsolute;
7137 /* Unfortunately gas always diverged from MASM in a respect that can't
7138 be easily fixed without risking to break code sequences likely to be
7139 encountered (the testsuite even check for this): MASM doesn't consider
7140 an expression inside brackets unconditionally as a memory reference.
7141 When that is e.g. a constant, an offset expression, or the sum of the
7142 two, this is still taken as a constant load. gas, however, always
7143 treated these as memory references. As a compromise, we'll try to make
7144 offset expressions inside brackets work the MASM way (since that's
7145 less likely to be found in real world code), but make constants alone
7146 continue to work the traditional gas way. In either case, issue a
7148 intel_parser.op_modifier &= ~was_offset;
7151 strcat (intel_parser.disp, "[");
7153 /* Add a '+' to the displacement string if necessary. */
7154 if (*intel_parser.disp != '\0'
7155 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7156 strcat (intel_parser.disp, "+");
7159 && (len = intel_parser.op_string - start - 1,
7160 intel_match_token (']')))
7162 /* Preserve brackets when the operand is an offset expression. */
7163 if (intel_parser.in_offset)
7164 strcat (intel_parser.disp, "]");
7167 --intel_parser.in_bracket;
7168 if (i.base_reg || i.index_reg)
7169 intel_parser.is_mem = 1;
7170 if (!intel_parser.is_mem)
7172 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7173 /* Defer the warning until all of the operand was parsed. */
7174 intel_parser.is_mem = -1;
7175 else if (!quiet_warnings)
7176 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7177 len, start, len, start);
7180 intel_parser.op_modifier |= was_offset;
7197 while (cur_token.code == '[')
7199 if (!intel_bracket_expr ())
7224 switch (cur_token.code)
7228 intel_match_token ('(');
7229 strcat (intel_parser.disp, "(");
7231 if (intel_expr () && intel_match_token (')'))
7233 strcat (intel_parser.disp, ")");
7240 return intel_bracket_expr ();
7245 strcat (intel_parser.disp, cur_token.str);
7246 intel_match_token (cur_token.code);
7248 /* Mark as a memory operand only if it's not already known to be an
7249 offset expression. */
7250 if (!intel_parser.in_offset)
7251 intel_parser.is_mem = 1;
7258 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7260 intel_match_token (T_REG);
7262 /* Check for segment change. */
7263 if (cur_token.code == ':')
7265 if (!(reg->reg_type & (SReg2 | SReg3)))
7267 as_bad (_("`%s' is not a valid segment register"),
7271 else if (i.seg[i.mem_operands])
7272 as_warn (_("Extra segment override ignored"));
7275 if (!intel_parser.in_offset)
7276 intel_parser.is_mem = 1;
7277 switch (reg->reg_num)
7280 i.seg[i.mem_operands] = &es;
7283 i.seg[i.mem_operands] = &cs;
7286 i.seg[i.mem_operands] = &ss;
7289 i.seg[i.mem_operands] = &ds;
7292 i.seg[i.mem_operands] = &fs;
7295 i.seg[i.mem_operands] = &gs;
7301 /* Not a segment register. Check for register scaling. */
7302 else if (cur_token.code == '*')
7304 if (!intel_parser.in_bracket)
7306 as_bad (_("Register scaling only allowed in memory operands"));
7310 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7311 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7312 else if (i.index_reg)
7313 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7315 /* What follows must be a valid scale. */
7316 intel_match_token ('*');
7318 i.types[this_operand] |= BaseIndex;
7320 /* Set the scale after setting the register (otherwise,
7321 i386_scale will complain) */
7322 if (cur_token.code == '+' || cur_token.code == '-')
7324 char *str, sign = cur_token.code;
7325 intel_match_token (cur_token.code);
7326 if (cur_token.code != T_CONST)
7328 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7332 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7333 strcpy (str + 1, cur_token.str);
7335 if (!i386_scale (str))
7339 else if (!i386_scale (cur_token.str))
7341 intel_match_token (cur_token.code);
7344 /* No scaling. If this is a memory operand, the register is either a
7345 base register (first occurrence) or an index register (second
7347 else if (intel_parser.in_bracket)
7352 else if (!i.index_reg)
7356 as_bad (_("Too many register references in memory operand"));
7360 i.types[this_operand] |= BaseIndex;
7363 /* It's neither base nor index. */
7364 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7366 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7367 i.op[this_operand].regs = reg;
7372 as_bad (_("Invalid use of register"));
7376 /* Since registers are not part of the displacement string (except
7377 when we're parsing offset operands), we may need to remove any
7378 preceding '+' from the displacement string. */
7379 if (*intel_parser.disp != '\0'
7380 && !intel_parser.in_offset)
7382 char *s = intel_parser.disp;
7383 s += strlen (s) - 1;
7406 intel_match_token (cur_token.code);
7408 if (cur_token.code == T_PTR)
7411 /* It must have been an identifier. */
7412 intel_putback_token ();
7413 cur_token.code = T_ID;
7419 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7423 /* The identifier represents a memory reference only if it's not
7424 preceded by an offset modifier and if it's not an equate. */
7425 symbolP = symbol_find(cur_token.str);
7426 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7427 intel_parser.is_mem = 1;
7435 char *save_str, sign = 0;
7437 /* Allow constants that start with `+' or `-'. */
7438 if (cur_token.code == '-' || cur_token.code == '+')
7440 sign = cur_token.code;
7441 intel_match_token (cur_token.code);
7442 if (cur_token.code != T_CONST)
7444 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7450 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7451 strcpy (save_str + !!sign, cur_token.str);
7455 /* Get the next token to check for register scaling. */
7456 intel_match_token (cur_token.code);
7458 /* Check if this constant is a scaling factor for an
7460 if (cur_token.code == '*')
7462 if (intel_match_token ('*') && cur_token.code == T_REG)
7464 const reg_entry *reg = cur_token.reg;
7466 if (!intel_parser.in_bracket)
7468 as_bad (_("Register scaling only allowed "
7469 "in memory operands"));
7473 /* Disallow things like [1*si].
7474 sp and esp are invalid as index. */
7475 if (reg->reg_type & Reg16)
7476 reg = i386_regtab + REGNAM_AX + 4;
7477 else if (i.index_reg)
7478 reg = i386_regtab + REGNAM_EAX + 4;
7480 /* The constant is followed by `* reg', so it must be
7483 i.types[this_operand] |= BaseIndex;
7485 /* Set the scale after setting the register (otherwise,
7486 i386_scale will complain) */
7487 if (!i386_scale (save_str))
7489 intel_match_token (T_REG);
7491 /* Since registers are not part of the displacement
7492 string, we may need to remove any preceding '+' from
7493 the displacement string. */
7494 if (*intel_parser.disp != '\0')
7496 char *s = intel_parser.disp;
7497 s += strlen (s) - 1;
7507 /* The constant was not used for register scaling. Since we have
7508 already consumed the token following `*' we now need to put it
7509 back in the stream. */
7510 intel_putback_token ();
7513 /* Add the constant to the displacement string. */
7514 strcat (intel_parser.disp, save_str);
7521 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7525 /* Match the given token against cur_token. If they match, read the next
7526 token from the operand string. */
7528 intel_match_token (int code)
7530 if (cur_token.code == code)
7537 as_bad (_("Unexpected token `%s'"), cur_token.str);
7542 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7544 intel_get_token (void)
7547 const reg_entry *reg;
7548 struct intel_token new_token;
7550 new_token.code = T_NIL;
7551 new_token.reg = NULL;
7552 new_token.str = NULL;
7554 /* Free the memory allocated to the previous token and move
7555 cur_token to prev_token. */
7557 free (prev_token.str);
7559 prev_token = cur_token;
7561 /* Skip whitespace. */
7562 while (is_space_char (*intel_parser.op_string))
7563 intel_parser.op_string++;
7565 /* Return an empty token if we find nothing else on the line. */
7566 if (*intel_parser.op_string == '\0')
7568 cur_token = new_token;
7572 /* The new token cannot be larger than the remainder of the operand
7574 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7575 new_token.str[0] = '\0';
7577 if (strchr ("0123456789", *intel_parser.op_string))
7579 char *p = new_token.str;
7580 char *q = intel_parser.op_string;
7581 new_token.code = T_CONST;
7583 /* Allow any kind of identifier char to encompass floating point and
7584 hexadecimal numbers. */
7585 while (is_identifier_char (*q))
7589 /* Recognize special symbol names [0-9][bf]. */
7590 if (strlen (intel_parser.op_string) == 2
7591 && (intel_parser.op_string[1] == 'b'
7592 || intel_parser.op_string[1] == 'f'))
7593 new_token.code = T_ID;
7596 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7598 size_t len = end_op - intel_parser.op_string;
7600 new_token.code = T_REG;
7601 new_token.reg = reg;
7603 memcpy (new_token.str, intel_parser.op_string, len);
7604 new_token.str[len] = '\0';
7607 else if (is_identifier_char (*intel_parser.op_string))
7609 char *p = new_token.str;
7610 char *q = intel_parser.op_string;
7612 /* A '.' or '$' followed by an identifier char is an identifier.
7613 Otherwise, it's operator '.' followed by an expression. */
7614 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7616 new_token.code = '.';
7617 new_token.str[0] = '.';
7618 new_token.str[1] = '\0';
7622 while (is_identifier_char (*q) || *q == '@')
7626 if (strcasecmp (new_token.str, "NOT") == 0)
7627 new_token.code = '~';
7629 else if (strcasecmp (new_token.str, "MOD") == 0)
7630 new_token.code = '%';
7632 else if (strcasecmp (new_token.str, "AND") == 0)
7633 new_token.code = '&';
7635 else if (strcasecmp (new_token.str, "OR") == 0)
7636 new_token.code = '|';
7638 else if (strcasecmp (new_token.str, "XOR") == 0)
7639 new_token.code = '^';
7641 else if (strcasecmp (new_token.str, "SHL") == 0)
7642 new_token.code = T_SHL;
7644 else if (strcasecmp (new_token.str, "SHR") == 0)
7645 new_token.code = T_SHR;
7647 else if (strcasecmp (new_token.str, "BYTE") == 0)
7648 new_token.code = T_BYTE;
7650 else if (strcasecmp (new_token.str, "WORD") == 0)
7651 new_token.code = T_WORD;
7653 else if (strcasecmp (new_token.str, "DWORD") == 0)
7654 new_token.code = T_DWORD;
7656 else if (strcasecmp (new_token.str, "FWORD") == 0)
7657 new_token.code = T_FWORD;
7659 else if (strcasecmp (new_token.str, "QWORD") == 0)
7660 new_token.code = T_QWORD;
7662 else if (strcasecmp (new_token.str, "TBYTE") == 0
7663 /* XXX remove (gcc still uses it) */
7664 || strcasecmp (new_token.str, "XWORD") == 0)
7665 new_token.code = T_TBYTE;
7667 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7668 || strcasecmp (new_token.str, "OWORD") == 0)
7669 new_token.code = T_XMMWORD;
7671 else if (strcasecmp (new_token.str, "PTR") == 0)
7672 new_token.code = T_PTR;
7674 else if (strcasecmp (new_token.str, "SHORT") == 0)
7675 new_token.code = T_SHORT;
7677 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7679 new_token.code = T_OFFSET;
7681 /* ??? This is not mentioned in the MASM grammar but gcc
7682 makes use of it with -mintel-syntax. OFFSET may be
7683 followed by FLAT: */
7684 if (strncasecmp (q, " FLAT:", 6) == 0)
7685 strcat (new_token.str, " FLAT:");
7688 /* ??? This is not mentioned in the MASM grammar. */
7689 else if (strcasecmp (new_token.str, "FLAT") == 0)
7691 new_token.code = T_OFFSET;
7693 strcat (new_token.str, ":");
7695 as_bad (_("`:' expected"));
7699 new_token.code = T_ID;
7703 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7705 new_token.code = *intel_parser.op_string;
7706 new_token.str[0] = *intel_parser.op_string;
7707 new_token.str[1] = '\0';
7710 else if (strchr ("<>", *intel_parser.op_string)
7711 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7713 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7714 new_token.str[0] = *intel_parser.op_string;
7715 new_token.str[1] = *intel_parser.op_string;
7716 new_token.str[2] = '\0';
7720 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7722 intel_parser.op_string += strlen (new_token.str);
7723 cur_token = new_token;
7726 /* Put cur_token back into the token stream and make cur_token point to
7729 intel_putback_token (void)
7731 if (cur_token.code != T_NIL)
7733 intel_parser.op_string -= strlen (cur_token.str);
7734 free (cur_token.str);
7736 cur_token = prev_token;
7738 /* Forget prev_token. */
7739 prev_token.code = T_NIL;
7740 prev_token.reg = NULL;
7741 prev_token.str = NULL;
7745 tc_x86_regname_to_dw2regnum (char *regname)
7747 unsigned int regnum;
7748 unsigned int regnames_count;
7749 static const char *const regnames_32[] =
7751 "eax", "ecx", "edx", "ebx",
7752 "esp", "ebp", "esi", "edi",
7753 "eip", "eflags", NULL,
7754 "st0", "st1", "st2", "st3",
7755 "st4", "st5", "st6", "st7",
7757 "xmm0", "xmm1", "xmm2", "xmm3",
7758 "xmm4", "xmm5", "xmm6", "xmm7",
7759 "mm0", "mm1", "mm2", "mm3",
7760 "mm4", "mm5", "mm6", "mm7",
7761 "fcw", "fsw", "mxcsr",
7762 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7765 static const char *const regnames_64[] =
7767 "rax", "rdx", "rcx", "rbx",
7768 "rsi", "rdi", "rbp", "rsp",
7769 "r8", "r9", "r10", "r11",
7770 "r12", "r13", "r14", "r15",
7772 "xmm0", "xmm1", "xmm2", "xmm3",
7773 "xmm4", "xmm5", "xmm6", "xmm7",
7774 "xmm8", "xmm9", "xmm10", "xmm11",
7775 "xmm12", "xmm13", "xmm14", "xmm15",
7776 "st0", "st1", "st2", "st3",
7777 "st4", "st5", "st6", "st7",
7778 "mm0", "mm1", "mm2", "mm3",
7779 "mm4", "mm5", "mm6", "mm7",
7781 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7782 "fs.base", "gs.base", NULL, NULL,
7784 "mxcsr", "fcw", "fsw"
7786 const char *const *regnames;
7788 if (flag_code == CODE_64BIT)
7790 regnames = regnames_64;
7791 regnames_count = ARRAY_SIZE (regnames_64);
7795 regnames = regnames_32;
7796 regnames_count = ARRAY_SIZE (regnames_32);
7799 for (regnum = 0; regnum < regnames_count; regnum++)
7800 if (regnames[regnum] != NULL
7801 && strcmp (regname, regnames[regnum]) == 0)
7808 tc_x86_frame_initial_instructions (void)
7810 static unsigned int sp_regno;
7813 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7816 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7817 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7821 i386_elf_section_type (const char *str, size_t len)
7823 if (flag_code == CODE_64BIT
7824 && len == sizeof ("unwind") - 1
7825 && strncmp (str, "unwind", 6) == 0)
7826 return SHT_X86_64_UNWIND;
7833 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7837 expr.X_op = O_secrel;
7838 expr.X_add_symbol = symbol;
7839 expr.X_add_number = 0;
7840 emit_expr (&expr, size);
7844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7845 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7848 x86_64_section_letter (int letter, char **ptr_msg)
7850 if (flag_code == CODE_64BIT)
7853 return SHF_X86_64_LARGE;
7855 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7858 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7863 x86_64_section_word (char *str, size_t len)
7865 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7866 return SHF_X86_64_LARGE;
7872 handle_large_common (int small ATTRIBUTE_UNUSED)
7874 if (flag_code != CODE_64BIT)
7876 s_comm_internal (0, elf_common_parse);
7877 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7881 static segT lbss_section;
7882 asection *saved_com_section_ptr = elf_com_section_ptr;
7883 asection *saved_bss_section = bss_section;
7885 if (lbss_section == NULL)
7887 flagword applicable;
7889 subsegT subseg = now_subseg;
7891 /* The .lbss section is for local .largecomm symbols. */
7892 lbss_section = subseg_new (".lbss", 0);
7893 applicable = bfd_applicable_section_flags (stdoutput);
7894 bfd_set_section_flags (stdoutput, lbss_section,
7895 applicable & SEC_ALLOC);
7896 seg_info (lbss_section)->bss = 1;
7898 subseg_set (seg, subseg);
7901 elf_com_section_ptr = &_bfd_elf_large_com_section;
7902 bss_section = lbss_section;
7904 s_comm_internal (0, elf_common_parse);
7906 elf_com_section_ptr = saved_com_section_ptr;
7907 bss_section = saved_bss_section;
7910 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */