1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry *regs;
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
265 unsupported_with_intel_mnemonic,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
275 mask_not_on_destination,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default = 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default = 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
374 /* How to encode vector instructions. */
377 vex_encoding_default = 0,
384 const char *rep_prefix;
387 const char *hle_prefix;
389 /* Have BND prefix. */
390 const char *bnd_prefix;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
396 enum i386_error error;
399 typedef struct _i386_insn i386_insn;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable[] =
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
460 const char line_separator_chars[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510 /* Current operand we are working on. */
511 static int this_operand = -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
551 /* 1 for intel syntax,
553 static int intel_syntax = 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix = 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590 static enum check_kind
596 sse_check, operand_check = check_warning;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize = 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space = 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
849 CPU_BTVER1_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
851 CPU_BTVER2_FLAGS, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
869 CPU_SSSE3_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_1_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
881 CPU_AVX512F_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
883 CPU_AVX512CD_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
885 CPU_AVX512ER_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
887 CPU_AVX512PF_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
889 CPU_AVX512DQ_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
891 CPU_AVX512BW_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
893 CPU_AVX512VL_FLAGS, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
897 CPU_VMFUNC_FLAGS, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
901 CPU_XSAVE_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEOPT_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEC_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
907 CPU_XSAVES_FLAGS, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
915 CPU_FSGSBASE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
917 CPU_RDRND_FLAGS, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
931 CPU_MOVBE_FLAGS, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
937 CPU_LZCNT_FLAGS, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
943 CPU_INVPCID_FLAGS, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
945 CPU_CLFLUSH_FLAGS, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
949 CPU_SYSCALL_FLAGS, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
951 CPU_RDTSCP_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
953 CPU_3DNOW_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
955 CPU_3DNOWA_FLAGS, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
957 CPU_PADLOCK_FLAGS, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
963 CPU_SSE4A_FLAGS, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
973 CPU_RDSEED_FLAGS, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
975 CPU_PRFCHW_FLAGS, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
983 CPU_CLFLUSHOPT_FLAGS, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
985 CPU_PREFETCHWT1_FLAGS, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
991 CPU_AVX512IFMA_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
993 CPU_AVX512VBMI_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1007 CPU_CLZERO_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1009 CPU_MWAITX_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1011 CPU_OSPKE_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1013 CPU_RDPID_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
1040 static const noarch_entry cpu_noarch[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1089 && *input_line_pointer == ',')
1091 align = parse_align (needs_align - 1);
1093 if (align == (addressT) -1)
1108 bss_alloc (symbolP, size, align);
1113 pe_lcomm (int needs_align)
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1119 const pseudo_typeS md_pseudo_table[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1124 {"align", s_align_ptwo, 0},
1126 {"arch", set_cpu_arch, 0},
1130 {"lcomm", pe_lcomm, 1},
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1136 {"slong", signed_cons, 4},
1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
1143 {"code64", set_code_flag, CODE_64BIT},
1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
1156 {"file", dwarf2_directive_file, 0},
1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1161 {"secrel32", pe_directive_secrel, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control *op_hash;
1172 /* Hash table for register lookup. */
1173 static struct hash_control *reg_hash;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1[] =
1180 static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt[] = {
1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt[] = {
1206 f32_1, f32_2, f16_3, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1238 alt_9, alt_10, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
1261 last = count % max_single_nop_size;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1269 nops = patt[last - 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1280 memcpy (where + offset, nops, last);
1285 fits_in_imm7 (offsetT num)
1287 return (num & 0x7f) == num;
1291 fits_in_imm31 (offsetT num)
1293 return (num & 0x7fffffff) == num;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1302 const unsigned char *const *patt = NULL;
1303 int max_single_nop_size;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
1307 switch (fragP->fr_type)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code == CODE_16BIT)
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
1354 case PROCESSOR_CORE:
1355 case PROCESSOR_CORE2:
1356 case PROCESSOR_COREI7:
1357 case PROCESSOR_L1OM:
1358 case PROCESSOR_K1OM:
1359 case PROCESSOR_GENERIC64:
1361 case PROCESSOR_ATHLON:
1363 case PROCESSOR_AMDFAM10:
1365 case PROCESSOR_ZNVER:
1369 case PROCESSOR_I386:
1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
1372 case PROCESSOR_PENTIUMPRO:
1373 case PROCESSOR_IAMCU:
1374 case PROCESSOR_GENERIC32:
1381 switch (fragP->tc_frag_data.tune)
1383 case PROCESSOR_UNKNOWN:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386:
1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
1392 case PROCESSOR_IAMCU:
1394 case PROCESSOR_ATHLON:
1396 case PROCESSOR_AMDFAM10:
1398 case PROCESSOR_ZNVER:
1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
1412 case PROCESSOR_CORE2:
1413 case PROCESSOR_COREI7:
1414 case PROCESSOR_L1OM:
1415 case PROCESSOR_K1OM:
1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1421 case PROCESSOR_GENERIC64:
1427 if (patt == f32_patt)
1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1442 limit = max_single_nop_size;
1444 if (fragP->fr_type == rs_fill_nop)
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1457 fragP->fr_var = count;
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1465 /* Use "jmp disp8" if possible. */
1467 where[0] = jump_disp8[0];
1473 unsigned int size_of_jump;
1475 if (flag_code == CODE_16BIT)
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1483 where[0] = jump32_disp32[0];
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
1505 operand_type_all_zero (const union i386_operand_type *x)
1507 switch (ARRAY_SIZE(x->array))
1518 return !x->array[0];
1525 operand_type_set (union i386_operand_type *x, unsigned int v)
1527 switch (ARRAY_SIZE(x->array))
1545 operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
1548 switch (ARRAY_SIZE(x->array))
1551 if (x->array[2] != y->array[2])
1555 if (x->array[1] != y->array[1])
1559 return x->array[0] == y->array[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags *x)
1569 switch (ARRAY_SIZE(x->array))
1584 return !x->array[0];
1591 cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1594 switch (ARRAY_SIZE(x->array))
1597 if (x->array[3] != y->array[3])
1601 if (x->array[2] != y->array[2])
1605 if (x->array[1] != y->array[1])
1609 return x->array[0] == y->array[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f)
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1626 switch (ARRAY_SIZE (x.array))
1629 x.array [3] &= y.array [3];
1632 x.array [2] &= y.array [2];
1635 x.array [1] &= y.array [1];
1638 x.array [0] &= y.array [0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1649 switch (ARRAY_SIZE (x.array))
1652 x.array [3] |= y.array [3];
1655 x.array [2] |= y.array [2];
1658 x.array [1] |= y.array [1];
1661 x.array [0] |= y.array [0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1672 switch (ARRAY_SIZE (x.array))
1675 x.array [3] &= ~y.array [3];
1678 x.array [2] &= ~y.array [2];
1681 x.array [1] &= ~y.array [1];
1684 x.array [0] &= ~y.array [0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template *t)
1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1709 if (cpu_flags_all_zero (&x))
1711 /* This instruction is available on all archs. */
1712 match |= CPU_FLAGS_ARCH_MATCH;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu = cpu_arch_flags;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1722 x.bitfield.cpuavx512vl = 0;
1724 cpu = cpu_flags_and (x, cpu);
1725 if (!cpu_flags_all_zero (&cpu))
1727 if (x.bitfield.cpuavx)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
1737 else if (x.bitfield.cpuavx512f)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1747 match |= CPU_FLAGS_ARCH_MATCH;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x, i386_operand_type y)
1756 switch (ARRAY_SIZE (x.array))
1759 x.array [2] &= y.array [2];
1762 x.array [1] &= y.array [1];
1765 x.array [0] &= y.array [0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1776 switch (ARRAY_SIZE (x.array))
1779 x.array [2] &= ~y.array [2];
1782 x.array [1] &= ~y.array [1];
1785 x.array [0] &= ~y.array [0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x, i386_operand_type y)
1796 switch (ARRAY_SIZE (x.array))
1799 x.array [2] |= y.array [2];
1802 x.array [1] |= y.array [1];
1805 x.array [0] |= y.array [0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x, i386_operand_type y)
1816 switch (ARRAY_SIZE (x.array))
1819 x.array [2] ^= y.array [2];
1822 x.array [1] ^= y.array [1];
1825 x.array [0] ^= y.array [0];
1833 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1835 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839 static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
1841 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1842 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1843 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1852 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1863 operand_type_check (i386_operand_type t, enum operand_type c)
1868 return t.bitfield.reg;
1871 return (t.bitfield.imm8
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1900 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1901 operand J for instruction template T. */
1904 match_reg_size (const insn_template *t, unsigned int wanted, unsigned int given)
1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
1918 /* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1922 match_simd_size (const insn_template *t, unsigned int wanted, unsigned int given)
1924 return !((i.types[given].bitfield.xmmword
1925 && !t->operand_types[wanted].bitfield.xmmword)
1926 || (i.types[given].bitfield.ymmword
1927 && !t->operand_types[wanted].bitfield.ymmword)
1928 || (i.types[given].bitfield.zmmword
1929 && !t->operand_types[wanted].bitfield.zmmword));
1932 /* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1936 match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given)
1938 return (match_reg_size (t, wanted, given)
1939 && !((i.types[given].bitfield.unspecified
1941 && !t->operand_types[wanted].bitfield.unspecified)
1942 || (i.types[given].bitfield.fword
1943 && !t->operand_types[wanted].bitfield.fword)
1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
1948 || ((t->operand_types[wanted].bitfield.regsimd
1949 && !t->opcode_modifier.broadcast
1950 && (t->operand_types[wanted].bitfield.byte
1951 || t->operand_types[wanted].bitfield.word
1952 || t->operand_types[wanted].bitfield.dword
1953 || t->operand_types[wanted].bitfield.qword))
1954 ? (i.types[given].bitfield.xmmword
1955 || i.types[given].bitfield.ymmword
1956 || i.types[given].bitfield.zmmword)
1957 : !match_simd_size(t, wanted, given))));
1960 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1961 operands for instruction template T, and it has MATCH_REVERSE set if there
1962 is no size conflict on any operands for the template with operands reversed
1963 (and the template allows for reversing in the first place). */
1965 #define MATCH_STRAIGHT 1
1966 #define MATCH_REVERSE 2
1968 static INLINE unsigned int
1969 operand_size_match (const insn_template *t)
1971 unsigned int j, match = MATCH_STRAIGHT;
1973 /* Don't check jump instructions. */
1974 if (t->opcode_modifier.jump
1975 || t->opcode_modifier.jumpbyte
1976 || t->opcode_modifier.jumpdword
1977 || t->opcode_modifier.jumpintersegment)
1980 /* Check memory and accumulator operand size. */
1981 for (j = 0; j < i.operands; j++)
1983 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1984 && t->operand_types[j].bitfield.anysize)
1987 if (t->operand_types[j].bitfield.reg
1988 && !match_reg_size (t, j, j))
1994 if (t->operand_types[j].bitfield.regsimd
1995 && !match_simd_size (t, j, j))
2001 if (t->operand_types[j].bitfield.acc
2002 && (!match_reg_size (t, j, j) || !match_simd_size (t, j, j)))
2008 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2015 if (!t->opcode_modifier.d)
2019 i.error = operand_size_mismatch;
2023 /* Check reverse. */
2024 gas_assert (i.operands == 2);
2026 for (j = 0; j < 2; j++)
2028 if ((t->operand_types[j].bitfield.reg
2029 || t->operand_types[j].bitfield.acc)
2030 && !match_reg_size (t, j, !j))
2033 if (i.types[!j].bitfield.mem
2034 && !match_mem_size (t, j, !j))
2038 return match | MATCH_REVERSE;
2042 operand_type_match (i386_operand_type overlap,
2043 i386_operand_type given)
2045 i386_operand_type temp = overlap;
2047 temp.bitfield.jumpabsolute = 0;
2048 temp.bitfield.unspecified = 0;
2049 temp.bitfield.byte = 0;
2050 temp.bitfield.word = 0;
2051 temp.bitfield.dword = 0;
2052 temp.bitfield.fword = 0;
2053 temp.bitfield.qword = 0;
2054 temp.bitfield.tbyte = 0;
2055 temp.bitfield.xmmword = 0;
2056 temp.bitfield.ymmword = 0;
2057 temp.bitfield.zmmword = 0;
2058 if (operand_type_all_zero (&temp))
2061 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2062 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2066 i.error = operand_type_mismatch;
2070 /* If given types g0 and g1 are registers they must be of the same type
2071 unless the expected operand type register overlap is null.
2072 Memory operand size of certain SIMD instructions is also being checked
2076 operand_type_register_match (i386_operand_type g0,
2077 i386_operand_type t0,
2078 i386_operand_type g1,
2079 i386_operand_type t1)
2081 if (!g0.bitfield.reg
2082 && !g0.bitfield.regsimd
2083 && (!operand_type_check (g0, anymem)
2084 || g0.bitfield.unspecified
2085 || !t0.bitfield.regsimd))
2088 if (!g1.bitfield.reg
2089 && !g1.bitfield.regsimd
2090 && (!operand_type_check (g1, anymem)
2091 || g1.bitfield.unspecified
2092 || !t1.bitfield.regsimd))
2095 if (g0.bitfield.byte == g1.bitfield.byte
2096 && g0.bitfield.word == g1.bitfield.word
2097 && g0.bitfield.dword == g1.bitfield.dword
2098 && g0.bitfield.qword == g1.bitfield.qword
2099 && g0.bitfield.xmmword == g1.bitfield.xmmword
2100 && g0.bitfield.ymmword == g1.bitfield.ymmword
2101 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2104 if (!(t0.bitfield.byte & t1.bitfield.byte)
2105 && !(t0.bitfield.word & t1.bitfield.word)
2106 && !(t0.bitfield.dword & t1.bitfield.dword)
2107 && !(t0.bitfield.qword & t1.bitfield.qword)
2108 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2109 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2110 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2113 i.error = register_type_mismatch;
2118 static INLINE unsigned int
2119 register_number (const reg_entry *r)
2121 unsigned int nr = r->reg_num;
2123 if (r->reg_flags & RegRex)
2126 if (r->reg_flags & RegVRex)
2132 static INLINE unsigned int
2133 mode_from_disp_size (i386_operand_type t)
2135 if (t.bitfield.disp8)
2137 else if (t.bitfield.disp16
2138 || t.bitfield.disp32
2139 || t.bitfield.disp32s)
2146 fits_in_signed_byte (addressT num)
2148 return num + 0x80 <= 0xff;
2152 fits_in_unsigned_byte (addressT num)
2158 fits_in_unsigned_word (addressT num)
2160 return num <= 0xffff;
2164 fits_in_signed_word (addressT num)
2166 return num + 0x8000 <= 0xffff;
2170 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2175 return num + 0x80000000 <= 0xffffffff;
2177 } /* fits_in_signed_long() */
2180 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2185 return num <= 0xffffffff;
2187 } /* fits_in_unsigned_long() */
2190 fits_in_disp8 (offsetT num)
2192 int shift = i.memshift;
2198 mask = (1 << shift) - 1;
2200 /* Return 0 if NUM isn't properly aligned. */
2204 /* Check if NUM will fit in 8bit after shift. */
2205 return fits_in_signed_byte (num >> shift);
2209 fits_in_imm4 (offsetT num)
2211 return (num & 0xf) == num;
2214 static i386_operand_type
2215 smallest_imm_type (offsetT num)
2217 i386_operand_type t;
2219 operand_type_set (&t, 0);
2220 t.bitfield.imm64 = 1;
2222 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2224 /* This code is disabled on the 486 because all the Imm1 forms
2225 in the opcode table are slower on the i486. They're the
2226 versions with the implicitly specified single-position
2227 displacement, which has another syntax if you really want to
2229 t.bitfield.imm1 = 1;
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2236 else if (fits_in_signed_byte (num))
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm8s = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2244 else if (fits_in_unsigned_byte (num))
2246 t.bitfield.imm8 = 1;
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2251 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2253 t.bitfield.imm16 = 1;
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2257 else if (fits_in_signed_long (num))
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2262 else if (fits_in_unsigned_long (num))
2263 t.bitfield.imm32 = 1;
2269 offset_in_range (offsetT val, int size)
2275 case 1: mask = ((addressT) 1 << 8) - 1; break;
2276 case 2: mask = ((addressT) 1 << 16) - 1; break;
2277 case 4: mask = ((addressT) 2 << 31) - 1; break;
2279 case 8: mask = ((addressT) 2 << 63) - 1; break;
2285 /* If BFD64, sign extend val for 32bit address mode. */
2286 if (flag_code != CODE_64BIT
2287 || i.prefix[ADDR_PREFIX])
2288 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2289 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2292 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2294 char buf1[40], buf2[40];
2296 sprint_value (buf1, val);
2297 sprint_value (buf2, val & mask);
2298 as_warn (_("%s shortened to %s"), buf1, buf2);
2313 a. PREFIX_EXIST if attempting to add a prefix where one from the
2314 same class already exists.
2315 b. PREFIX_LOCK if lock prefix is added.
2316 c. PREFIX_REP if rep/repne prefix is added.
2317 d. PREFIX_DS if ds prefix is added.
2318 e. PREFIX_OTHER if other prefix is added.
2321 static enum PREFIX_GROUP
2322 add_prefix (unsigned int prefix)
2324 enum PREFIX_GROUP ret = PREFIX_OTHER;
2327 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2328 && flag_code == CODE_64BIT)
2330 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2331 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2332 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2333 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2344 case DS_PREFIX_OPCODE:
2347 case CS_PREFIX_OPCODE:
2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
2361 case LOCK_PREFIX_OPCODE:
2370 case ADDR_PREFIX_OPCODE:
2374 case DATA_PREFIX_OPCODE:
2378 if (i.prefix[q] != 0)
2386 i.prefix[q] |= prefix;
2389 as_bad (_("same type of prefix used twice"));
2395 update_code_flag (int value, int check)
2397 PRINTF_LIKE ((*as_error));
2399 flag_code = (enum flag_code) value;
2400 if (flag_code == CODE_64BIT)
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2413 as_error = as_fatal;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2422 as_error = as_fatal;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
2428 stackop_size = '\0';
2432 set_code_flag (int value)
2434 update_code_flag (value, 0);
2438 set_16bit_gcc_code_flag (int new_code_flag)
2440 flag_code = (enum flag_code) new_code_flag;
2441 if (flag_code != CODE_16BIT)
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
2445 stackop_size = LONG_MNEM_SUFFIX;
2449 set_intel_syntax (int syntax_flag)
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2458 int e = get_symbol_name (&string);
2460 if (strcmp (string, "prefix") == 0)
2462 else if (strcmp (string, "noprefix") == 0)
2465 as_bad (_("bad argument to syntax directive."));
2466 (void) restore_line_pointer (e);
2468 demand_empty_rest_of_line ();
2470 intel_syntax = syntax_flag;
2472 if (ask_naked_reg == 0)
2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2476 allow_naked_reg = (ask_naked_reg < 0);
2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
2482 register_prefix = allow_naked_reg ? "" : "%";
2486 set_intel_mnemonic (int mnemonic_flag)
2488 intel_mnemonic = mnemonic_flag;
2492 set_allow_index_reg (int flag)
2494 allow_index_reg = flag;
2498 set_check (int what)
2500 enum check_kind *kind;
2505 kind = &operand_check;
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2519 int e = get_symbol_name (&string);
2521 if (strcmp (string, "none") == 0)
2523 else if (strcmp (string, "warning") == 0)
2524 *kind = check_warning;
2525 else if (strcmp (string, "error") == 0)
2526 *kind = check_error;
2528 as_bad (_("bad argument to %s_check directive."), str);
2529 (void) restore_line_pointer (e);
2532 as_bad (_("missing argument for %s_check directive"), str);
2534 demand_empty_rest_of_line ();
2538 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2544 /* Intel LIOM is only supported on ELF. */
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2554 arch = default_arch;
2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2562 /* If we are targeting Intel L1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2564 || new_flag.bitfield.cpul1om)
2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2577 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2584 int e = get_symbol_name (&string);
2586 i386_cpu_flags flags;
2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2590 if (strcmp (string, cpu_arch[j].name) == 0)
2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2596 cpu_arch_name = cpu_arch[j].name;
2597 cpu_sub_arch_name = NULL;
2598 cpu_arch_flags = cpu_arch[j].flags;
2599 if (flag_code == CODE_64BIT)
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
2611 if (!cpu_arch_tune_set)
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2619 flags = cpu_flags_or (cpu_arch_flags,
2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2624 if (cpu_sub_arch_name)
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
2629 (const char *) NULL);
2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2634 cpu_arch_flags = flags;
2635 cpu_arch_isa_flags = flags;
2639 = cpu_flags_or (cpu_arch_isa_flags,
2641 (void) restore_line_pointer (e);
2642 demand_empty_rest_of_line ();
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2649 /* Disable an ISA extension. */
2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2657 if (cpu_sub_arch_name)
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2674 j = ARRAY_SIZE (cpu_arch);
2677 if (j >= ARRAY_SIZE (cpu_arch))
2678 as_bad (_("no such architecture: `%s'"), string);
2680 *input_line_pointer = e;
2683 as_bad (_("missing cpu architecture"));
2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2702 (void) restore_line_pointer (e);
2705 demand_empty_rest_of_line ();
2708 enum bfd_architecture
2711 if (cpu_arch_isa == PROCESSOR_L1OM)
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2733 return bfd_arch_i386;
2739 if (!strncmp (default_arch, "x86_64", 6))
2741 if (cpu_arch_isa == PROCESSOR_L1OM)
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2755 else if (default_arch[6] == '\0')
2756 return bfd_mach_x86_64;
2758 return bfd_mach_x64_32;
2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2770 return bfd_mach_i386_i386;
2773 as_fatal (_("unknown architecture"));
2779 const char *hash_err;
2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2784 /* Initialize op_hash hash table. */
2785 op_hash = hash_new ();
2788 const insn_template *optab;
2789 templates *core_optab;
2791 /* Setup for loop. */
2793 core_optab = XNEW (templates);
2794 core_optab->start = optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2802 /* different name --> ship out current template list;
2803 add to hash table; & begin anew. */
2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2807 (void *) core_optab);
2810 as_fatal (_("can't hash %s: %s"),
2814 if (optab->name == NULL)
2816 core_optab = XNEW (templates);
2817 core_optab->start = optab;
2822 /* Initialize reg_hash hash table. */
2823 reg_hash = hash_new ();
2825 const reg_entry *regtab;
2826 unsigned int regtab_size = i386_regtab_size;
2828 for (regtab = i386_regtab; regtab_size--; regtab++)
2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2832 as_fatal (_("can't hash %s: %s"),
2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2843 for (c = 0; c < 256; c++)
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2852 else if (ISLOWER (c))
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2858 else if (ISUPPER (c))
2860 mnemonic_chars[c] = TOLOWER (c);
2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2864 else if (c == '{' || c == '}')
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2870 if (ISALPHA (c) || ISDIGIT (c))
2871 identifier_chars[c] = c;
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2880 identifier_chars['@'] = '@';
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
2886 digit_chars['-'] = '-';
2887 mnemonic_chars['_'] = '_';
2888 mnemonic_chars['-'] = '-';
2889 mnemonic_chars['.'] = '.';
2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2897 if (flag_code == CODE_64BIT)
2899 #if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2903 x86_dwarf2_return_column = 16;
2905 x86_cie_data_alignment = -8;
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2915 i386_print_statistics (FILE *file)
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2923 /* Debugging routines for md_assemble. */
2924 static void pte (insn_template *);
2925 static void pt (i386_operand_type);
2926 static void pe (expressionS *);
2927 static void ps (symbolS *);
2930 pi (char *line, i386_insn *x)
2934 fprintf (stdout, "%s: template ", line);
2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2941 x->rm.mode, x->rm.reg, x->rm.regmem);
2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
2949 for (j = 0; j < x->operands; j++)
2951 fprintf (stdout, " #%d: ", j + 1);
2953 fprintf (stdout, "\n");
2954 if (x->types[j].bitfield.reg
2955 || x->types[j].bitfield.regmmx
2956 || x->types[j].bitfield.regsimd
2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
2971 pte (insn_template *t)
2974 fprintf (stdout, " %d operands ", t->operands);
2975 fprintf (stdout, "opcode %x ", t->base_opcode);
2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
2978 if (t->opcode_modifier.d)
2979 fprintf (stdout, "D");
2980 if (t->opcode_modifier.w)
2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
2983 for (j = 0; j < t->operands; j++)
2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
2987 fprintf (stdout, "\n");
2994 fprintf (stdout, " operation %d\n", e->X_op);
2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
2997 if (e->X_add_symbol)
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3014 fprintf (stdout, "%s type %s%s",
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3020 static struct type_name
3022 i386_operand_type mask;
3025 const type_names[] =
3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
3057 { OPERAND_TYPE_REGYMM, "rYMM" },
3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
3060 { OPERAND_TYPE_ESSEG, "es" },
3064 pt (i386_operand_type t)
3067 i386_operand_type a;
3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3071 a = operand_type_and (t, type_names[j].mask);
3072 if (!operand_type_all_zero (&a))
3073 fprintf (stdout, "%s, ", type_names[j].name);
3078 #endif /* DEBUG386 */
3080 static bfd_reloc_code_real_type
3081 reloc (unsigned int size,
3084 bfd_reloc_code_real_type other)
3086 if (other != NO_RELOC)
3088 reloc_howto_type *rel;
3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3119 if (other == BFD_RELOC_SIZE32)
3122 other = BFD_RELOC_SIZE64;
3125 as_bad (_("there are no pc-relative size relocations"));
3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3137 as_bad (_("unknown relocation (%u)"), other);
3138 else if (size != bfd_get_reloc_size (rel))
3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3140 bfd_get_reloc_size (rel),
3142 else if (pcrel && !rel->pc_relative)
3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3146 || (rel->complain_on_overflow == complain_overflow_unsigned
3148 as_bad (_("relocated field and relocation type differ in signedness"));
3157 as_bad (_("there are no unsigned pc-relative relocations"));
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
3162 case 4: return BFD_RELOC_32_PCREL;
3163 case 8: return BFD_RELOC_64_PCREL;
3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3172 case 4: return BFD_RELOC_X86_64_32S;
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
3189 /* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3195 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3255 intel_float_operand (const char *mnemonic)
3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3264 switch (mnemonic[1])
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3270 return 2 /* integer op */;
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3288 switch (mnemonic[3])
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3307 /* Build the VEX prefix. */
3310 build_vex_prefix (const insn_template *t)
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3324 register_specifier = 0xf;
3326 /* Use 2-byte VEX prefix by swapping destination and source
3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
3330 && i.operands == i.reg_operands
3331 && i.tm.opcode_modifier.vexopcode == VEX0F
3332 && i.tm.opcode_modifier.load
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3346 gas_assert (i.rm.mode == 3);
3350 i.rm.regmem = i.rm.reg;
3353 /* Use the next insn. */
3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
3359 else if (i.tm.opcode_modifier.vex == VEX256)
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3381 case DATA_PREFIX_OPCODE:
3384 case REPE_PREFIX_OPCODE:
3387 case REPNE_PREFIX_OPCODE:
3394 /* Use 2-byte VEX prefix if possible. */
3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
3397 && i.tm.opcode_modifier.vexw != VEXW1
3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3400 /* 2-byte VEX prefix. */
3404 i.vex.bytes[0] = 0xc5;
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3415 /* 3-byte VEX prefix. */
3420 switch (i.tm.opcode_modifier.vexopcode)
3424 i.vex.bytes[0] = 0xc4;
3428 i.vex.bytes[0] = 0xc4;
3432 i.vex.bytes[0] = 0xc4;
3436 i.vex.bytes[0] = 0x8f;
3440 i.vex.bytes[0] = 0x8f;
3444 i.vex.bytes[0] = 0x8f;
3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3466 static INLINE bfd_boolean
3467 is_evex_encoding (const insn_template *t)
3469 return t->opcode_modifier.evex
3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3474 /* Build the EVEX prefix. */
3477 build_evex_prefix (void)
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3482 rex_byte vrex_used = 0;
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3487 gas_assert ((i.vrex & REX_X) == 0);
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3500 register_specifier = 0xf;
3502 /* Encode upper 16 vector index register in the fourth byte of
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3515 case DATA_PREFIX_OPCODE:
3518 case REPE_PREFIX_OPCODE:
3521 case REPNE_PREFIX_OPCODE:
3528 /* 4 byte EVEX prefix. */
3530 i.vex.bytes[0] = 0x62;
3533 switch (i.tm.opcode_modifier.vexopcode)
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3569 i.vex.bytes[1] &= ~0x40;
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3584 /* If w is not set it means we are dealing with WIG instruction. */
3587 if (evexwig == evexw1)
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3602 /* Don't always set the broadcast bit if there is no RC. */
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
3631 switch (i.tm.opcode_modifier.evex)
3633 case EVEXLIG: /* LL' is ignored */
3634 vec_length = evexlig << 5;
3637 vec_length = 0 << 5;
3640 vec_length = 1 << 5;
3643 vec_length = 2 << 5;
3649 i.vex.bytes[3] |= vec_length;
3650 /* Encode the broadcast bit. */
3652 i.vex.bytes[3] |= 0x10;
3656 if (i.rounding->type != saeonly)
3657 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3659 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3662 if (i.mask && i.mask->mask)
3663 i.vex.bytes[3] |= i.mask->mask->reg_num;
3667 process_immext (void)
3671 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3674 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3675 with an opcode suffix which is coded in the same place as an
3676 8-bit immediate field would be.
3677 Here we check those operands and remove them afterwards. */
3680 for (x = 0; x < i.operands; x++)
3681 if (register_number (i.op[x].regs) != x)
3682 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3683 register_prefix, i.op[x].regs->reg_name, x + 1,
3689 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3691 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3692 suffix which is coded in the same place as an 8-bit immediate
3694 Here we check those operands and remove them afterwards. */
3697 if (i.operands != 3)
3700 for (x = 0; x < 2; x++)
3701 if (register_number (i.op[x].regs) != x)
3702 goto bad_register_operand;
3704 /* Check for third operand for mwaitx/monitorx insn. */
3705 if (register_number (i.op[x].regs)
3706 != (x + (i.tm.extension_opcode == 0xfb)))
3708 bad_register_operand:
3709 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3710 register_prefix, i.op[x].regs->reg_name, x+1,
3717 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3718 which is coded in the same place as an 8-bit immediate field
3719 would be. Here we fake an 8-bit immediate operand from the
3720 opcode suffix stored in tm.extension_opcode.
3722 AVX instructions also use this encoding, for some of
3723 3 argument instructions. */
3725 gas_assert (i.imm_operands <= 1
3727 || ((i.tm.opcode_modifier.vex
3728 || i.tm.opcode_modifier.vexopcode
3729 || is_evex_encoding (&i.tm))
3730 && i.operands <= 4)));
3732 exp = &im_expressions[i.imm_operands++];
3733 i.op[i.operands].imms = exp;
3734 i.types[i.operands] = imm8;
3736 exp->X_op = O_constant;
3737 exp->X_add_number = i.tm.extension_opcode;
3738 i.tm.extension_opcode = None;
3745 switch (i.tm.opcode_modifier.hleprefixok)
3750 as_bad (_("invalid instruction `%s' after `%s'"),
3751 i.tm.name, i.hle_prefix);
3754 if (i.prefix[LOCK_PREFIX])
3756 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3760 case HLEPrefixRelease:
3761 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3763 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3767 if (i.mem_operands == 0
3768 || !operand_type_check (i.types[i.operands - 1], anymem))
3770 as_bad (_("memory destination needed for instruction `%s'"
3771 " after `xrelease'"), i.tm.name);
3778 /* Try the shortest encoding by shortening operand size. */
3781 optimize_encoding (void)
3785 if (optimize_for_space
3786 && i.reg_operands == 1
3787 && i.imm_operands == 1
3788 && !i.types[1].bitfield.byte
3789 && i.op[0].imms->X_op == O_constant
3790 && fits_in_imm7 (i.op[0].imms->X_add_number)
3791 && ((i.tm.base_opcode == 0xa8
3792 && i.tm.extension_opcode == None)
3793 || (i.tm.base_opcode == 0xf6
3794 && i.tm.extension_opcode == 0x0)))
3797 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3799 unsigned int base_regnum = i.op[1].regs->reg_num;
3800 if (flag_code == CODE_64BIT || base_regnum < 4)
3802 i.types[1].bitfield.byte = 1;
3803 /* Ignore the suffix. */
3805 if (base_regnum >= 4
3806 && !(i.op[1].regs->reg_flags & RegRex))
3808 /* Handle SP, BP, SI and DI registers. */
3809 if (i.types[1].bitfield.word)
3811 else if (i.types[1].bitfield.dword)
3819 else if (flag_code == CODE_64BIT
3820 && ((i.types[1].bitfield.qword
3821 && i.reg_operands == 1
3822 && i.imm_operands == 1
3823 && i.op[0].imms->X_op == O_constant
3824 && ((i.tm.base_opcode == 0xb0
3825 && i.tm.extension_opcode == None
3826 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3827 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3828 && (((i.tm.base_opcode == 0x24
3829 || i.tm.base_opcode == 0xa8)
3830 && i.tm.extension_opcode == None)
3831 || (i.tm.base_opcode == 0x80
3832 && i.tm.extension_opcode == 0x4)
3833 || ((i.tm.base_opcode == 0xf6
3834 || i.tm.base_opcode == 0xc6)
3835 && i.tm.extension_opcode == 0x0)))))
3836 || (i.types[0].bitfield.qword
3837 && ((i.reg_operands == 2
3838 && i.op[0].regs == i.op[1].regs
3839 && ((i.tm.base_opcode == 0x30
3840 || i.tm.base_opcode == 0x28)
3841 && i.tm.extension_opcode == None))
3842 || (i.reg_operands == 1
3844 && i.tm.base_opcode == 0x30
3845 && i.tm.extension_opcode == None)))))
3848 andq $imm31, %r64 -> andl $imm31, %r32
3849 testq $imm31, %r64 -> testl $imm31, %r32
3850 xorq %r64, %r64 -> xorl %r32, %r32
3851 subq %r64, %r64 -> subl %r32, %r32
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3855 i.tm.opcode_modifier.norex64 = 1;
3856 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3859 movq $imm31, %r64 -> movl $imm31, %r32
3860 movq $imm32, %r64 -> movl $imm32, %r32
3862 i.tm.operand_types[0].bitfield.imm32 = 1;
3863 i.tm.operand_types[0].bitfield.imm32s = 0;
3864 i.tm.operand_types[0].bitfield.imm64 = 0;
3865 i.types[0].bitfield.imm32 = 1;
3866 i.types[0].bitfield.imm32s = 0;
3867 i.types[0].bitfield.imm64 = 0;
3868 i.types[1].bitfield.dword = 1;
3869 i.types[1].bitfield.qword = 0;
3870 if (i.tm.base_opcode == 0xc6)
3873 movq $imm31, %r64 -> movl $imm31, %r32
3875 i.tm.base_opcode = 0xb0;
3876 i.tm.extension_opcode = None;
3877 i.tm.opcode_modifier.shortform = 1;
3878 i.tm.opcode_modifier.modrm = 0;
3882 else if (optimize > 1
3883 && i.reg_operands == 3
3884 && i.op[0].regs == i.op[1].regs
3885 && !i.types[2].bitfield.xmmword
3886 && (i.tm.opcode_modifier.vex
3887 || ((!i.mask || i.mask->zeroing)
3889 && is_evex_encoding (&i.tm)
3890 && (i.vec_encoding != vex_encoding_evex
3891 || i.tm.cpu_flags.bitfield.cpuavx512vl
3892 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3893 && ((i.tm.base_opcode == 0x55
3894 || i.tm.base_opcode == 0x6655
3895 || i.tm.base_opcode == 0x66df
3896 || i.tm.base_opcode == 0x57
3897 || i.tm.base_opcode == 0x6657
3898 || i.tm.base_opcode == 0x66ef
3899 || i.tm.base_opcode == 0x66f8
3900 || i.tm.base_opcode == 0x66f9
3901 || i.tm.base_opcode == 0x66fa
3902 || i.tm.base_opcode == 0x66fb)
3903 && i.tm.extension_opcode == None))
3906 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 VEX VOP %ymmM, %ymmM, %ymmN
3915 -> VEX VOP %xmmM, %xmmM, %xmmN
3916 VOP, one of vpandn and vpxor:
3917 VEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX VOP %xmmM, %xmmM, %xmmN
3919 VOP, one of vpandnd and vpandnq:
3920 EVEX VOP %zmmM, %zmmM, %zmmN
3921 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3922 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3923 EVEX VOP %ymmM, %ymmM, %ymmN
3924 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3925 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3926 VOP, one of vpxord and vpxorq:
3927 EVEX VOP %zmmM, %zmmM, %zmmN
3928 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3929 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3930 EVEX VOP %ymmM, %ymmM, %ymmN
3931 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3934 if (is_evex_encoding (&i.tm))
3936 if (i.vec_encoding == vex_encoding_evex)
3937 i.tm.opcode_modifier.evex = EVEX128;
3940 i.tm.opcode_modifier.vex = VEX128;
3941 i.tm.opcode_modifier.vexw = VEXW0;
3942 i.tm.opcode_modifier.evex = 0;
3946 i.tm.opcode_modifier.vex = VEX128;
3948 if (i.tm.opcode_modifier.vex)
3949 for (j = 0; j < 3; j++)
3951 i.types[j].bitfield.xmmword = 1;
3952 i.types[j].bitfield.ymmword = 0;
3957 /* This is the guts of the machine-dependent assembler. LINE points to a
3958 machine dependent instruction. This function is supposed to emit
3959 the frags/bytes it assembles to. */
3962 md_assemble (char *line)
3965 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3966 const insn_template *t;
3968 /* Initialize globals. */
3969 memset (&i, '\0', sizeof (i));
3970 for (j = 0; j < MAX_OPERANDS; j++)
3971 i.reloc[j] = NO_RELOC;
3972 memset (disp_expressions, '\0', sizeof (disp_expressions));
3973 memset (im_expressions, '\0', sizeof (im_expressions));
3974 save_stack_p = save_stack;
3976 /* First parse an instruction mnemonic & call i386_operand for the operands.
3977 We assume that the scrubber has arranged it so that line[0] is the valid
3978 start of a (possibly prefixed) mnemonic. */
3980 line = parse_insn (line, mnemonic);
3983 mnem_suffix = i.suffix;
3985 line = parse_operands (line, mnemonic);
3987 xfree (i.memop1_string);
3988 i.memop1_string = NULL;
3992 /* Now we've parsed the mnemonic into a set of templates, and have the
3993 operands at hand. */
3995 /* All intel opcodes have reversed operands except for "bound" and
3996 "enter". We also don't reverse intersegment "jmp" and "call"
3997 instructions with 2 immediate operands so that the immediate segment
3998 precedes the offset, as it does when in AT&T mode. */
4001 && (strcmp (mnemonic, "bound") != 0)
4002 && (strcmp (mnemonic, "invlpga") != 0)
4003 && !(operand_type_check (i.types[0], imm)
4004 && operand_type_check (i.types[1], imm)))
4007 /* The order of the immediates should be reversed
4008 for 2 immediates extrq and insertq instructions */
4009 if (i.imm_operands == 2
4010 && (strcmp (mnemonic, "extrq") == 0
4011 || strcmp (mnemonic, "insertq") == 0))
4012 swap_2_operands (0, 1);
4017 /* Don't optimize displacement for movabs since it only takes 64bit
4020 && i.disp_encoding != disp_encoding_32bit
4021 && (flag_code != CODE_64BIT
4022 || strcmp (mnemonic, "movabs") != 0))
4025 /* Next, we find a template that matches the given insn,
4026 making sure the overlap of the given operands types is consistent
4027 with the template operand types. */
4029 if (!(t = match_template (mnem_suffix)))
4032 if (sse_check != check_none
4033 && !i.tm.opcode_modifier.noavx
4034 && !i.tm.cpu_flags.bitfield.cpuavx
4035 && (i.tm.cpu_flags.bitfield.cpusse
4036 || i.tm.cpu_flags.bitfield.cpusse2
4037 || i.tm.cpu_flags.bitfield.cpusse3
4038 || i.tm.cpu_flags.bitfield.cpussse3
4039 || i.tm.cpu_flags.bitfield.cpusse4_1
4040 || i.tm.cpu_flags.bitfield.cpusse4_2
4041 || i.tm.cpu_flags.bitfield.cpupclmul
4042 || i.tm.cpu_flags.bitfield.cpuaes
4043 || i.tm.cpu_flags.bitfield.cpugfni))
4045 (sse_check == check_warning
4047 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4050 /* Zap movzx and movsx suffix. The suffix has been set from
4051 "word ptr" or "byte ptr" on the source operand in Intel syntax
4052 or extracted from mnemonic in AT&T syntax. But we'll use
4053 the destination register to choose the suffix for encoding. */
4054 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4056 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4057 there is no suffix, the default will be byte extension. */
4058 if (i.reg_operands != 2
4061 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4066 if (i.tm.opcode_modifier.fwait)
4067 if (!add_prefix (FWAIT_OPCODE))
4070 /* Check if REP prefix is OK. */
4071 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4073 as_bad (_("invalid instruction `%s' after `%s'"),
4074 i.tm.name, i.rep_prefix);
4078 /* Check for lock without a lockable instruction. Destination operand
4079 must be memory unless it is xchg (0x86). */
4080 if (i.prefix[LOCK_PREFIX]
4081 && (!i.tm.opcode_modifier.islockable
4082 || i.mem_operands == 0
4083 || (i.tm.base_opcode != 0x86
4084 && !operand_type_check (i.types[i.operands - 1], anymem))))
4086 as_bad (_("expecting lockable instruction after `lock'"));
4090 /* Check if HLE prefix is OK. */
4091 if (i.hle_prefix && !check_hle ())
4094 /* Check BND prefix. */
4095 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4096 as_bad (_("expecting valid branch instruction after `bnd'"));
4098 /* Check NOTRACK prefix. */
4099 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4100 as_bad (_("expecting indirect branch instruction after `notrack'"));
4102 if (i.tm.cpu_flags.bitfield.cpumpx)
4104 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4105 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4106 else if (flag_code != CODE_16BIT
4107 ? i.prefix[ADDR_PREFIX]
4108 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4109 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4112 /* Insert BND prefix. */
4113 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4115 if (!i.prefix[BND_PREFIX])
4116 add_prefix (BND_PREFIX_OPCODE);
4117 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4119 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4120 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4124 /* Check string instruction segment overrides. */
4125 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4127 if (!check_string ())
4129 i.disp_operands = 0;
4132 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4133 optimize_encoding ();
4135 if (!process_suffix ())
4138 /* Update operand types. */
4139 for (j = 0; j < i.operands; j++)
4140 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4142 /* Make still unresolved immediate matches conform to size of immediate
4143 given in i.suffix. */
4144 if (!finalize_imm ())
4147 if (i.types[0].bitfield.imm1)
4148 i.imm_operands = 0; /* kludge for shift insns. */
4150 /* We only need to check those implicit registers for instructions
4151 with 3 operands or less. */
4152 if (i.operands <= 3)
4153 for (j = 0; j < i.operands; j++)
4154 if (i.types[j].bitfield.inoutportreg
4155 || i.types[j].bitfield.shiftcount
4156 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4159 /* ImmExt should be processed after SSE2AVX. */
4160 if (!i.tm.opcode_modifier.sse2avx
4161 && i.tm.opcode_modifier.immext)
4164 /* For insns with operands there are more diddles to do to the opcode. */
4167 if (!process_operands ())
4170 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4172 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4173 as_warn (_("translating to `%sp'"), i.tm.name);
4176 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4177 || is_evex_encoding (&i.tm))
4179 if (flag_code == CODE_16BIT)
4181 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4186 if (i.tm.opcode_modifier.vex)
4187 build_vex_prefix (t);
4189 build_evex_prefix ();
4192 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4193 instructions may define INT_OPCODE as well, so avoid this corner
4194 case for those instructions that use MODRM. */
4195 if (i.tm.base_opcode == INT_OPCODE
4196 && !i.tm.opcode_modifier.modrm
4197 && i.op[0].imms->X_add_number == 3)
4199 i.tm.base_opcode = INT3_OPCODE;
4203 if ((i.tm.opcode_modifier.jump
4204 || i.tm.opcode_modifier.jumpbyte
4205 || i.tm.opcode_modifier.jumpdword)
4206 && i.op[0].disps->X_op == O_constant)
4208 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4209 the absolute address given by the constant. Since ix86 jumps and
4210 calls are pc relative, we need to generate a reloc. */
4211 i.op[0].disps->X_add_symbol = &abs_symbol;
4212 i.op[0].disps->X_op = O_symbol;
4215 if (i.tm.opcode_modifier.rex64)
4218 /* For 8 bit registers we need an empty rex prefix. Also if the
4219 instruction already has a prefix, we need to convert old
4220 registers to new ones. */
4222 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4223 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4224 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4225 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4226 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4227 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4232 i.rex |= REX_OPCODE;
4233 for (x = 0; x < 2; x++)
4235 /* Look for 8 bit operand that uses old registers. */
4236 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4237 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4239 /* In case it is "hi" register, give up. */
4240 if (i.op[x].regs->reg_num > 3)
4241 as_bad (_("can't encode register '%s%s' in an "
4242 "instruction requiring REX prefix."),
4243 register_prefix, i.op[x].regs->reg_name);
4245 /* Otherwise it is equivalent to the extended register.
4246 Since the encoding doesn't change this is merely
4247 cosmetic cleanup for debug output. */
4249 i.op[x].regs = i.op[x].regs + 8;
4254 if (i.rex == 0 && i.rex_encoding)
4256 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4257 that uses legacy register. If it is "hi" register, don't add
4258 the REX_OPCODE byte. */
4260 for (x = 0; x < 2; x++)
4261 if (i.types[x].bitfield.reg
4262 && i.types[x].bitfield.byte
4263 && (i.op[x].regs->reg_flags & RegRex64) == 0
4264 && i.op[x].regs->reg_num > 3)
4266 i.rex_encoding = FALSE;
4275 add_prefix (REX_OPCODE | i.rex);
4277 /* We are ready to output the insn. */
4282 parse_insn (char *line, char *mnemonic)
4285 char *token_start = l;
4288 const insn_template *t;
4294 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4299 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4301 as_bad (_("no such instruction: `%s'"), token_start);
4306 if (!is_space_char (*l)
4307 && *l != END_OF_INSN
4309 || (*l != PREFIX_SEPARATOR
4312 as_bad (_("invalid character %s in mnemonic"),
4313 output_invalid (*l));
4316 if (token_start == l)
4318 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4319 as_bad (_("expecting prefix; got nothing"));
4321 as_bad (_("expecting mnemonic; got nothing"));
4325 /* Look up instruction (or prefix) via hash table. */
4326 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4328 if (*l != END_OF_INSN
4329 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4330 && current_templates
4331 && current_templates->start->opcode_modifier.isprefix)
4333 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4335 as_bad ((flag_code != CODE_64BIT
4336 ? _("`%s' is only supported in 64-bit mode")
4337 : _("`%s' is not supported in 64-bit mode")),
4338 current_templates->start->name);
4341 /* If we are in 16-bit mode, do not allow addr16 or data16.
4342 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4343 if ((current_templates->start->opcode_modifier.size16
4344 || current_templates->start->opcode_modifier.size32)
4345 && flag_code != CODE_64BIT
4346 && (current_templates->start->opcode_modifier.size32
4347 ^ (flag_code == CODE_16BIT)))
4349 as_bad (_("redundant %s prefix"),
4350 current_templates->start->name);
4353 if (current_templates->start->opcode_length == 0)
4355 /* Handle pseudo prefixes. */
4356 switch (current_templates->start->base_opcode)
4360 i.disp_encoding = disp_encoding_8bit;
4364 i.disp_encoding = disp_encoding_32bit;
4368 i.dir_encoding = dir_encoding_load;
4372 i.dir_encoding = dir_encoding_store;
4376 i.vec_encoding = vex_encoding_vex2;
4380 i.vec_encoding = vex_encoding_vex3;
4384 i.vec_encoding = vex_encoding_evex;
4388 i.rex_encoding = TRUE;
4392 i.no_optimize = TRUE;
4400 /* Add prefix, checking for repeated prefixes. */
4401 switch (add_prefix (current_templates->start->base_opcode))
4406 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4407 i.notrack_prefix = current_templates->start->name;
4410 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4411 i.hle_prefix = current_templates->start->name;
4412 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4413 i.bnd_prefix = current_templates->start->name;
4415 i.rep_prefix = current_templates->start->name;
4421 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4428 if (!current_templates)
4430 /* Check if we should swap operand or force 32bit displacement in
4432 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4433 i.dir_encoding = dir_encoding_store;
4434 else if (mnem_p - 3 == dot_p
4437 i.disp_encoding = disp_encoding_8bit;
4438 else if (mnem_p - 4 == dot_p
4442 i.disp_encoding = disp_encoding_32bit;
4447 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4450 if (!current_templates)
4453 /* See if we can get a match by trimming off a suffix. */
4456 case WORD_MNEM_SUFFIX:
4457 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4458 i.suffix = SHORT_MNEM_SUFFIX;
4461 case BYTE_MNEM_SUFFIX:
4462 case QWORD_MNEM_SUFFIX:
4463 i.suffix = mnem_p[-1];
4465 current_templates = (const templates *) hash_find (op_hash,
4468 case SHORT_MNEM_SUFFIX:
4469 case LONG_MNEM_SUFFIX:
4472 i.suffix = mnem_p[-1];
4474 current_templates = (const templates *) hash_find (op_hash,
4483 if (intel_float_operand (mnemonic) == 1)
4484 i.suffix = SHORT_MNEM_SUFFIX;
4486 i.suffix = LONG_MNEM_SUFFIX;
4488 current_templates = (const templates *) hash_find (op_hash,
4493 if (!current_templates)
4495 as_bad (_("no such instruction: `%s'"), token_start);
4500 if (current_templates->start->opcode_modifier.jump
4501 || current_templates->start->opcode_modifier.jumpbyte)
4503 /* Check for a branch hint. We allow ",pt" and ",pn" for
4504 predict taken and predict not taken respectively.
4505 I'm not sure that branch hints actually do anything on loop
4506 and jcxz insns (JumpByte) for current Pentium4 chips. They
4507 may work in the future and it doesn't hurt to accept them
4509 if (l[0] == ',' && l[1] == 'p')
4513 if (!add_prefix (DS_PREFIX_OPCODE))
4517 else if (l[2] == 'n')
4519 if (!add_prefix (CS_PREFIX_OPCODE))
4525 /* Any other comma loses. */
4528 as_bad (_("invalid character %s in mnemonic"),
4529 output_invalid (*l));
4533 /* Check if instruction is supported on specified architecture. */
4535 for (t = current_templates->start; t < current_templates->end; ++t)
4537 supported |= cpu_flags_match (t);
4538 if (supported == CPU_FLAGS_PERFECT_MATCH)
4540 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4541 as_warn (_("use .code16 to ensure correct addressing mode"));
4547 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4548 as_bad (flag_code == CODE_64BIT
4549 ? _("`%s' is not supported in 64-bit mode")
4550 : _("`%s' is only supported in 64-bit mode"),
4551 current_templates->start->name);
4553 as_bad (_("`%s' is not supported on `%s%s'"),
4554 current_templates->start->name,
4555 cpu_arch_name ? cpu_arch_name : default_arch,
4556 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4562 parse_operands (char *l, const char *mnemonic)
4566 /* 1 if operand is pending after ','. */
4567 unsigned int expecting_operand = 0;
4569 /* Non-zero if operand parens not balanced. */
4570 unsigned int paren_not_balanced;
4572 while (*l != END_OF_INSN)
4574 /* Skip optional white space before operand. */
4575 if (is_space_char (*l))
4577 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4579 as_bad (_("invalid character %s before operand %d"),
4580 output_invalid (*l),
4584 token_start = l; /* After white space. */
4585 paren_not_balanced = 0;
4586 while (paren_not_balanced || *l != ',')
4588 if (*l == END_OF_INSN)
4590 if (paren_not_balanced)
4593 as_bad (_("unbalanced parenthesis in operand %d."),
4596 as_bad (_("unbalanced brackets in operand %d."),
4601 break; /* we are done */
4603 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4605 as_bad (_("invalid character %s in operand %d"),
4606 output_invalid (*l),
4613 ++paren_not_balanced;
4615 --paren_not_balanced;
4620 ++paren_not_balanced;
4622 --paren_not_balanced;
4626 if (l != token_start)
4627 { /* Yes, we've read in another operand. */
4628 unsigned int operand_ok;
4629 this_operand = i.operands++;
4630 if (i.operands > MAX_OPERANDS)
4632 as_bad (_("spurious operands; (%d operands/instruction max)"),
4636 i.types[this_operand].bitfield.unspecified = 1;
4637 /* Now parse operand adding info to 'i' as we go along. */
4638 END_STRING_AND_SAVE (l);
4642 i386_intel_operand (token_start,
4643 intel_float_operand (mnemonic));
4645 operand_ok = i386_att_operand (token_start);
4647 RESTORE_END_STRING (l);
4653 if (expecting_operand)
4655 expecting_operand_after_comma:
4656 as_bad (_("expecting operand after ','; got nothing"));
4661 as_bad (_("expecting operand before ','; got nothing"));
4666 /* Now *l must be either ',' or END_OF_INSN. */
4669 if (*++l == END_OF_INSN)
4671 /* Just skip it, if it's \n complain. */
4672 goto expecting_operand_after_comma;
4674 expecting_operand = 1;
4681 swap_2_operands (int xchg1, int xchg2)
4683 union i386_op temp_op;
4684 i386_operand_type temp_type;
4685 enum bfd_reloc_code_real temp_reloc;
4687 temp_type = i.types[xchg2];
4688 i.types[xchg2] = i.types[xchg1];
4689 i.types[xchg1] = temp_type;
4690 temp_op = i.op[xchg2];
4691 i.op[xchg2] = i.op[xchg1];
4692 i.op[xchg1] = temp_op;
4693 temp_reloc = i.reloc[xchg2];
4694 i.reloc[xchg2] = i.reloc[xchg1];
4695 i.reloc[xchg1] = temp_reloc;
4699 if (i.mask->operand == xchg1)
4700 i.mask->operand = xchg2;
4701 else if (i.mask->operand == xchg2)
4702 i.mask->operand = xchg1;
4706 if (i.broadcast->operand == xchg1)
4707 i.broadcast->operand = xchg2;
4708 else if (i.broadcast->operand == xchg2)
4709 i.broadcast->operand = xchg1;
4713 if (i.rounding->operand == xchg1)
4714 i.rounding->operand = xchg2;
4715 else if (i.rounding->operand == xchg2)
4716 i.rounding->operand = xchg1;
4721 swap_operands (void)
4727 swap_2_operands (1, i.operands - 2);
4731 swap_2_operands (0, i.operands - 1);
4737 if (i.mem_operands == 2)
4739 const seg_entry *temp_seg;
4740 temp_seg = i.seg[0];
4741 i.seg[0] = i.seg[1];
4742 i.seg[1] = temp_seg;
4746 /* Try to ensure constant immediates are represented in the smallest
4751 char guess_suffix = 0;
4755 guess_suffix = i.suffix;
4756 else if (i.reg_operands)
4758 /* Figure out a suffix from the last register operand specified.
4759 We can't do this properly yet, ie. excluding InOutPortReg,
4760 but the following works for instructions with immediates.
4761 In any case, we can't set i.suffix yet. */
4762 for (op = i.operands; --op >= 0;)
4763 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4765 guess_suffix = BYTE_MNEM_SUFFIX;
4768 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4770 guess_suffix = WORD_MNEM_SUFFIX;
4773 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4775 guess_suffix = LONG_MNEM_SUFFIX;
4778 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4780 guess_suffix = QWORD_MNEM_SUFFIX;
4784 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4785 guess_suffix = WORD_MNEM_SUFFIX;
4787 for (op = i.operands; --op >= 0;)
4788 if (operand_type_check (i.types[op], imm))
4790 switch (i.op[op].imms->X_op)
4793 /* If a suffix is given, this operand may be shortened. */
4794 switch (guess_suffix)
4796 case LONG_MNEM_SUFFIX:
4797 i.types[op].bitfield.imm32 = 1;
4798 i.types[op].bitfield.imm64 = 1;
4800 case WORD_MNEM_SUFFIX:
4801 i.types[op].bitfield.imm16 = 1;
4802 i.types[op].bitfield.imm32 = 1;
4803 i.types[op].bitfield.imm32s = 1;
4804 i.types[op].bitfield.imm64 = 1;
4806 case BYTE_MNEM_SUFFIX:
4807 i.types[op].bitfield.imm8 = 1;
4808 i.types[op].bitfield.imm8s = 1;
4809 i.types[op].bitfield.imm16 = 1;
4810 i.types[op].bitfield.imm32 = 1;
4811 i.types[op].bitfield.imm32s = 1;
4812 i.types[op].bitfield.imm64 = 1;
4816 /* If this operand is at most 16 bits, convert it
4817 to a signed 16 bit number before trying to see
4818 whether it will fit in an even smaller size.
4819 This allows a 16-bit operand such as $0xffe0 to
4820 be recognised as within Imm8S range. */
4821 if ((i.types[op].bitfield.imm16)
4822 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4824 i.op[op].imms->X_add_number =
4825 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4828 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4829 if ((i.types[op].bitfield.imm32)
4830 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4833 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4834 ^ ((offsetT) 1 << 31))
4835 - ((offsetT) 1 << 31));
4839 = operand_type_or (i.types[op],
4840 smallest_imm_type (i.op[op].imms->X_add_number));
4842 /* We must avoid matching of Imm32 templates when 64bit
4843 only immediate is available. */
4844 if (guess_suffix == QWORD_MNEM_SUFFIX)
4845 i.types[op].bitfield.imm32 = 0;
4852 /* Symbols and expressions. */
4854 /* Convert symbolic operand to proper sizes for matching, but don't
4855 prevent matching a set of insns that only supports sizes other
4856 than those matching the insn suffix. */
4858 i386_operand_type mask, allowed;
4859 const insn_template *t;
4861 operand_type_set (&mask, 0);
4862 operand_type_set (&allowed, 0);
4864 for (t = current_templates->start;
4865 t < current_templates->end;
4867 allowed = operand_type_or (allowed,
4868 t->operand_types[op]);
4869 switch (guess_suffix)
4871 case QWORD_MNEM_SUFFIX:
4872 mask.bitfield.imm64 = 1;
4873 mask.bitfield.imm32s = 1;
4875 case LONG_MNEM_SUFFIX:
4876 mask.bitfield.imm32 = 1;
4878 case WORD_MNEM_SUFFIX:
4879 mask.bitfield.imm16 = 1;
4881 case BYTE_MNEM_SUFFIX:
4882 mask.bitfield.imm8 = 1;
4887 allowed = operand_type_and (mask, allowed);
4888 if (!operand_type_all_zero (&allowed))
4889 i.types[op] = operand_type_and (i.types[op], mask);
4896 /* Try to use the smallest displacement type too. */
4898 optimize_disp (void)
4902 for (op = i.operands; --op >= 0;)
4903 if (operand_type_check (i.types[op], disp))
4905 if (i.op[op].disps->X_op == O_constant)
4907 offsetT op_disp = i.op[op].disps->X_add_number;
4909 if (i.types[op].bitfield.disp16
4910 && (op_disp & ~(offsetT) 0xffff) == 0)
4912 /* If this operand is at most 16 bits, convert
4913 to a signed 16 bit number and don't use 64bit
4915 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4916 i.types[op].bitfield.disp64 = 0;
4919 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4920 if (i.types[op].bitfield.disp32
4921 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4923 /* If this operand is at most 32 bits, convert
4924 to a signed 32 bit number and don't use 64bit
4926 op_disp &= (((offsetT) 2 << 31) - 1);
4927 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4928 i.types[op].bitfield.disp64 = 0;
4931 if (!op_disp && i.types[op].bitfield.baseindex)
4933 i.types[op].bitfield.disp8 = 0;
4934 i.types[op].bitfield.disp16 = 0;
4935 i.types[op].bitfield.disp32 = 0;
4936 i.types[op].bitfield.disp32s = 0;
4937 i.types[op].bitfield.disp64 = 0;
4941 else if (flag_code == CODE_64BIT)
4943 if (fits_in_signed_long (op_disp))
4945 i.types[op].bitfield.disp64 = 0;
4946 i.types[op].bitfield.disp32s = 1;
4948 if (i.prefix[ADDR_PREFIX]
4949 && fits_in_unsigned_long (op_disp))
4950 i.types[op].bitfield.disp32 = 1;
4952 if ((i.types[op].bitfield.disp32
4953 || i.types[op].bitfield.disp32s
4954 || i.types[op].bitfield.disp16)
4955 && fits_in_disp8 (op_disp))
4956 i.types[op].bitfield.disp8 = 1;
4958 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4959 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4961 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4962 i.op[op].disps, 0, i.reloc[op]);
4963 i.types[op].bitfield.disp8 = 0;
4964 i.types[op].bitfield.disp16 = 0;
4965 i.types[op].bitfield.disp32 = 0;
4966 i.types[op].bitfield.disp32s = 0;
4967 i.types[op].bitfield.disp64 = 0;
4970 /* We only support 64bit displacement on constants. */
4971 i.types[op].bitfield.disp64 = 0;
4975 /* Check if operands are valid for the instruction. */
4978 check_VecOperands (const insn_template *t)
4982 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4984 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4985 any one operand are implicity requiring AVX512VL support if the actual
4986 operand size is YMMword or XMMword. Since this function runs after
4987 template matching, there's no need to check for YMMword/XMMword in
4989 cpu = cpu_flags_and (t->cpu_flags, avx512);
4990 if (!cpu_flags_all_zero (&cpu)
4991 && !t->cpu_flags.bitfield.cpuavx512vl
4992 && !cpu_arch_flags.bitfield.cpuavx512vl)
4994 for (op = 0; op < t->operands; ++op)
4996 if (t->operand_types[op].bitfield.zmmword
4997 && (i.types[op].bitfield.ymmword
4998 || i.types[op].bitfield.xmmword))
5000 i.error = unsupported;
5006 /* Without VSIB byte, we can't have a vector register for index. */
5007 if (!t->opcode_modifier.vecsib
5009 && (i.index_reg->reg_type.bitfield.xmmword
5010 || i.index_reg->reg_type.bitfield.ymmword
5011 || i.index_reg->reg_type.bitfield.zmmword))
5013 i.error = unsupported_vector_index_register;
5017 /* Check if default mask is allowed. */
5018 if (t->opcode_modifier.nodefmask
5019 && (!i.mask || i.mask->mask->reg_num == 0))
5021 i.error = no_default_mask;
5025 /* For VSIB byte, we need a vector register for index, and all vector
5026 registers must be distinct. */
5027 if (t->opcode_modifier.vecsib)
5030 || !((t->opcode_modifier.vecsib == VecSIB128
5031 && i.index_reg->reg_type.bitfield.xmmword)
5032 || (t->opcode_modifier.vecsib == VecSIB256
5033 && i.index_reg->reg_type.bitfield.ymmword)
5034 || (t->opcode_modifier.vecsib == VecSIB512
5035 && i.index_reg->reg_type.bitfield.zmmword)))
5037 i.error = invalid_vsib_address;
5041 gas_assert (i.reg_operands == 2 || i.mask);
5042 if (i.reg_operands == 2 && !i.mask)
5044 gas_assert (i.types[0].bitfield.regsimd);
5045 gas_assert (i.types[0].bitfield.xmmword
5046 || i.types[0].bitfield.ymmword);
5047 gas_assert (i.types[2].bitfield.regsimd);
5048 gas_assert (i.types[2].bitfield.xmmword
5049 || i.types[2].bitfield.ymmword);
5050 if (operand_check == check_none)
5052 if (register_number (i.op[0].regs)
5053 != register_number (i.index_reg)
5054 && register_number (i.op[2].regs)
5055 != register_number (i.index_reg)
5056 && register_number (i.op[0].regs)
5057 != register_number (i.op[2].regs))
5059 if (operand_check == check_error)
5061 i.error = invalid_vector_register_set;
5064 as_warn (_("mask, index, and destination registers should be distinct"));
5066 else if (i.reg_operands == 1 && i.mask)
5068 if (i.types[1].bitfield.regsimd
5069 && (i.types[1].bitfield.xmmword
5070 || i.types[1].bitfield.ymmword
5071 || i.types[1].bitfield.zmmword)
5072 && (register_number (i.op[1].regs)
5073 == register_number (i.index_reg)))
5075 if (operand_check == check_error)
5077 i.error = invalid_vector_register_set;
5080 if (operand_check != check_none)
5081 as_warn (_("index and destination registers should be distinct"));
5086 /* Check if broadcast is supported by the instruction and is applied
5087 to the memory operand. */
5090 i386_operand_type type, overlap;
5092 /* Check if specified broadcast is supported in this instruction,
5093 and it's applied to memory operand of DWORD or QWORD type. */
5094 op = i.broadcast->operand;
5095 if (!t->opcode_modifier.broadcast
5096 || !i.types[op].bitfield.mem
5097 || (!i.types[op].bitfield.unspecified
5098 && (t->operand_types[op].bitfield.dword
5099 ? !i.types[op].bitfield.dword
5100 : !i.types[op].bitfield.qword)))
5103 i.error = unsupported_broadcast;
5107 operand_type_set (&type, 0);
5108 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5111 type.bitfield.qword = 1;
5114 type.bitfield.xmmword = 1;
5117 type.bitfield.ymmword = 1;
5120 type.bitfield.zmmword = 1;
5126 overlap = operand_type_and (type, t->operand_types[op]);
5127 if (operand_type_all_zero (&overlap))
5130 if (t->opcode_modifier.checkregsize)
5134 type.bitfield.baseindex = 1;
5135 for (j = 0; j < i.operands; ++j)
5138 && !operand_type_register_match(i.types[j],
5139 t->operand_types[j],
5141 t->operand_types[op]))
5146 /* If broadcast is supported in this instruction, we need to check if
5147 operand of one-element size isn't specified without broadcast. */
5148 else if (t->opcode_modifier.broadcast && i.mem_operands)
5150 /* Find memory operand. */
5151 for (op = 0; op < i.operands; op++)
5152 if (operand_type_check (i.types[op], anymem))
5154 gas_assert (op < i.operands);
5155 /* Check size of the memory operand. */
5156 if (t->operand_types[op].bitfield.dword
5157 ? i.types[op].bitfield.dword
5158 : i.types[op].bitfield.qword)
5160 i.error = broadcast_needed;
5165 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5167 /* Check if requested masking is supported. */
5169 && (!t->opcode_modifier.masking
5171 && t->opcode_modifier.masking == MERGING_MASKING)))
5173 i.error = unsupported_masking;
5177 /* Check if masking is applied to dest operand. */
5178 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5180 i.error = mask_not_on_destination;
5187 if ((i.rounding->type != saeonly
5188 && !t->opcode_modifier.staticrounding)
5189 || (i.rounding->type == saeonly
5190 && (t->opcode_modifier.staticrounding
5191 || !t->opcode_modifier.sae)))
5193 i.error = unsupported_rc_sae;
5196 /* If the instruction has several immediate operands and one of
5197 them is rounding, the rounding operand should be the last
5198 immediate operand. */
5199 if (i.imm_operands > 1
5200 && i.rounding->operand != (int) (i.imm_operands - 1))
5202 i.error = rc_sae_operand_not_last_imm;
5207 /* Check vector Disp8 operand. */
5208 if (t->opcode_modifier.disp8memshift
5209 && i.disp_encoding != disp_encoding_32bit)
5212 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5214 i.memshift = t->opcode_modifier.disp8memshift;
5216 for (op = 0; op < i.operands; op++)
5217 if (operand_type_check (i.types[op], disp)
5218 && i.op[op].disps->X_op == O_constant)
5220 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5222 i.types[op].bitfield.disp8 = 1;
5225 i.types[op].bitfield.disp8 = 0;
5234 /* Check if operands are valid for the instruction. Update VEX
5238 VEX_check_operands (const insn_template *t)
5240 if (i.vec_encoding == vex_encoding_evex)
5242 /* This instruction must be encoded with EVEX prefix. */
5243 if (!is_evex_encoding (t))
5245 i.error = unsupported;
5251 if (!t->opcode_modifier.vex)
5253 /* This instruction template doesn't have VEX prefix. */
5254 if (i.vec_encoding != vex_encoding_default)
5256 i.error = unsupported;
5262 /* Only check VEX_Imm4, which must be the first operand. */
5263 if (t->operand_types[0].bitfield.vec_imm4)
5265 if (i.op[0].imms->X_op != O_constant
5266 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5272 /* Turn off Imm8 so that update_imm won't complain. */
5273 i.types[0] = vec_imm4;
5279 static const insn_template *
5280 match_template (char mnem_suffix)
5282 /* Points to template once we've found it. */
5283 const insn_template *t;
5284 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5285 i386_operand_type overlap4;
5286 unsigned int found_reverse_match;
5287 i386_opcode_modifier suffix_check, mnemsuf_check;
5288 i386_operand_type operand_types [MAX_OPERANDS];
5289 int addr_prefix_disp;
5291 unsigned int found_cpu_match, size_match;
5292 unsigned int check_register;
5293 enum i386_error specific_error = 0;
5295 #if MAX_OPERANDS != 5
5296 # error "MAX_OPERANDS must be 5."
5299 found_reverse_match = 0;
5300 addr_prefix_disp = -1;
5302 memset (&suffix_check, 0, sizeof (suffix_check));
5303 if (intel_syntax && i.broadcast)
5305 else if (i.suffix == BYTE_MNEM_SUFFIX)
5306 suffix_check.no_bsuf = 1;
5307 else if (i.suffix == WORD_MNEM_SUFFIX)
5308 suffix_check.no_wsuf = 1;
5309 else if (i.suffix == SHORT_MNEM_SUFFIX)
5310 suffix_check.no_ssuf = 1;
5311 else if (i.suffix == LONG_MNEM_SUFFIX)
5312 suffix_check.no_lsuf = 1;
5313 else if (i.suffix == QWORD_MNEM_SUFFIX)
5314 suffix_check.no_qsuf = 1;
5315 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5316 suffix_check.no_ldsuf = 1;
5318 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5321 switch (mnem_suffix)
5323 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5324 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5325 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5326 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5327 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5331 /* Must have right number of operands. */
5332 i.error = number_of_operands_mismatch;
5334 for (t = current_templates->start; t < current_templates->end; t++)
5336 addr_prefix_disp = -1;
5338 if (i.operands != t->operands)
5341 /* Check processor support. */
5342 i.error = unsupported;
5343 found_cpu_match = (cpu_flags_match (t)
5344 == CPU_FLAGS_PERFECT_MATCH);
5345 if (!found_cpu_match)
5348 /* Check AT&T mnemonic. */
5349 i.error = unsupported_with_intel_mnemonic;
5350 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5353 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5354 i.error = unsupported_syntax;
5355 if ((intel_syntax && t->opcode_modifier.attsyntax)
5356 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5357 || (intel64 && t->opcode_modifier.amd64)
5358 || (!intel64 && t->opcode_modifier.intel64))
5361 /* Check the suffix, except for some instructions in intel mode. */
5362 i.error = invalid_instruction_suffix;
5363 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5364 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5365 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5366 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5367 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5368 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5369 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5371 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5372 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5373 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5374 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5375 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5376 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5377 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5380 size_match = operand_size_match (t);
5384 for (j = 0; j < MAX_OPERANDS; j++)
5385 operand_types[j] = t->operand_types[j];
5387 /* In general, don't allow 64-bit operands in 32-bit mode. */
5388 if (i.suffix == QWORD_MNEM_SUFFIX
5389 && flag_code != CODE_64BIT
5391 ? (!t->opcode_modifier.ignoresize
5392 && !intel_float_operand (t->name))
5393 : intel_float_operand (t->name) != 2)
5394 && ((!operand_types[0].bitfield.regmmx
5395 && !operand_types[0].bitfield.regsimd)
5396 || (!operand_types[t->operands > 1].bitfield.regmmx
5397 && !operand_types[t->operands > 1].bitfield.regsimd))
5398 && (t->base_opcode != 0x0fc7
5399 || t->extension_opcode != 1 /* cmpxchg8b */))
5402 /* In general, don't allow 32-bit operands on pre-386. */
5403 else if (i.suffix == LONG_MNEM_SUFFIX
5404 && !cpu_arch_flags.bitfield.cpui386
5406 ? (!t->opcode_modifier.ignoresize
5407 && !intel_float_operand (t->name))
5408 : intel_float_operand (t->name) != 2)
5409 && ((!operand_types[0].bitfield.regmmx
5410 && !operand_types[0].bitfield.regsimd)
5411 || (!operand_types[t->operands > 1].bitfield.regmmx
5412 && !operand_types[t->operands > 1].bitfield.regsimd)))
5415 /* Do not verify operands when there are none. */
5419 /* We've found a match; break out of loop. */
5423 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5424 into Disp32/Disp16/Disp32 operand. */
5425 if (i.prefix[ADDR_PREFIX] != 0)
5427 /* There should be only one Disp operand. */
5431 for (j = 0; j < MAX_OPERANDS; j++)
5433 if (operand_types[j].bitfield.disp16)
5435 addr_prefix_disp = j;
5436 operand_types[j].bitfield.disp32 = 1;
5437 operand_types[j].bitfield.disp16 = 0;
5443 for (j = 0; j < MAX_OPERANDS; j++)
5445 if (operand_types[j].bitfield.disp32)
5447 addr_prefix_disp = j;
5448 operand_types[j].bitfield.disp32 = 0;
5449 operand_types[j].bitfield.disp16 = 1;
5455 for (j = 0; j < MAX_OPERANDS; j++)
5457 if (operand_types[j].bitfield.disp64)
5459 addr_prefix_disp = j;
5460 operand_types[j].bitfield.disp64 = 0;
5461 operand_types[j].bitfield.disp32 = 1;
5469 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5470 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5473 /* We check register size if needed. */
5474 if (t->opcode_modifier.checkregsize)
5476 check_register = (1 << t->operands) - 1;
5478 check_register &= ~(1 << i.broadcast->operand);
5483 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5484 switch (t->operands)
5487 if (!operand_type_match (overlap0, i.types[0]))
5491 /* xchg %eax, %eax is a special case. It is an alias for nop
5492 only in 32bit mode and we can use opcode 0x90. In 64bit
5493 mode, we can't use 0x90 for xchg %eax, %eax since it should
5494 zero-extend %eax to %rax. */
5495 if (flag_code == CODE_64BIT
5496 && t->base_opcode == 0x90
5497 && operand_type_equal (&i.types [0], &acc32)
5498 && operand_type_equal (&i.types [1], &acc32))
5500 /* xrelease mov %eax, <disp> is another special case. It must not
5501 match the accumulator-only encoding of mov. */
5502 if (flag_code != CODE_64BIT
5504 && t->base_opcode == 0xa0
5505 && i.types[0].bitfield.acc
5506 && operand_type_check (i.types[1], anymem))
5508 if (!(size_match & MATCH_STRAIGHT))
5510 /* If we want store form, we reverse direction of operands. */
5511 if (i.dir_encoding == dir_encoding_store
5512 && t->opcode_modifier.d)
5517 /* If we want store form, we skip the current load. */
5518 if (i.dir_encoding == dir_encoding_store
5519 && i.mem_operands == 0
5520 && t->opcode_modifier.load)
5525 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5526 if (!operand_type_match (overlap0, i.types[0])
5527 || !operand_type_match (overlap1, i.types[1])
5528 || ((check_register & 3) == 3
5529 && !operand_type_register_match (i.types[0],
5534 /* Check if other direction is valid ... */
5535 if (!t->opcode_modifier.d)
5539 if (!(size_match & MATCH_REVERSE))
5541 /* Try reversing direction of operands. */
5542 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5543 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5544 if (!operand_type_match (overlap0, i.types[0])
5545 || !operand_type_match (overlap1, i.types[1])
5547 && !operand_type_register_match (i.types[0],
5552 /* Does not match either direction. */
5555 /* found_reverse_match holds which of D or FloatR
5557 if (!t->opcode_modifier.d)
5558 found_reverse_match = 0;
5559 else if (operand_types[0].bitfield.tbyte)
5560 found_reverse_match = Opcode_FloatD;
5562 found_reverse_match = Opcode_D;
5563 if (t->opcode_modifier.floatr)
5564 found_reverse_match |= Opcode_FloatR;
5568 /* Found a forward 2 operand match here. */
5569 switch (t->operands)
5572 overlap4 = operand_type_and (i.types[4],
5576 overlap3 = operand_type_and (i.types[3],
5580 overlap2 = operand_type_and (i.types[2],
5585 switch (t->operands)
5588 if (!operand_type_match (overlap4, i.types[4])
5589 || !operand_type_register_match (i.types[3],
5596 if (!operand_type_match (overlap3, i.types[3])
5597 || ((check_register & 0xa) == 0xa
5598 && !operand_type_register_match (i.types[1],
5602 || ((check_register & 0xc) == 0xc
5603 && !operand_type_register_match (i.types[2],
5610 /* Here we make use of the fact that there are no
5611 reverse match 3 operand instructions. */
5612 if (!operand_type_match (overlap2, i.types[2])
5613 || ((check_register & 5) == 5
5614 && !operand_type_register_match (i.types[0],
5618 || ((check_register & 6) == 6
5619 && !operand_type_register_match (i.types[1],
5627 /* Found either forward/reverse 2, 3 or 4 operand match here:
5628 slip through to break. */
5630 if (!found_cpu_match)
5632 found_reverse_match = 0;
5636 /* Check if vector and VEX operands are valid. */
5637 if (check_VecOperands (t) || VEX_check_operands (t))
5639 specific_error = i.error;
5643 /* We've found a match; break out of loop. */
5647 if (t == current_templates->end)
5649 /* We found no match. */
5650 const char *err_msg;
5651 switch (specific_error ? specific_error : i.error)
5655 case operand_size_mismatch:
5656 err_msg = _("operand size mismatch");
5658 case operand_type_mismatch:
5659 err_msg = _("operand type mismatch");
5661 case register_type_mismatch:
5662 err_msg = _("register type mismatch");
5664 case number_of_operands_mismatch:
5665 err_msg = _("number of operands mismatch");
5667 case invalid_instruction_suffix:
5668 err_msg = _("invalid instruction suffix");
5671 err_msg = _("constant doesn't fit in 4 bits");
5673 case unsupported_with_intel_mnemonic:
5674 err_msg = _("unsupported with Intel mnemonic");
5676 case unsupported_syntax:
5677 err_msg = _("unsupported syntax");
5680 as_bad (_("unsupported instruction `%s'"),
5681 current_templates->start->name);
5683 case invalid_vsib_address:
5684 err_msg = _("invalid VSIB address");
5686 case invalid_vector_register_set:
5687 err_msg = _("mask, index, and destination registers must be distinct");
5689 case unsupported_vector_index_register:
5690 err_msg = _("unsupported vector index register");
5692 case unsupported_broadcast:
5693 err_msg = _("unsupported broadcast");
5695 case broadcast_not_on_src_operand:
5696 err_msg = _("broadcast not on source memory operand");
5698 case broadcast_needed:
5699 err_msg = _("broadcast is needed for operand of such type");
5701 case unsupported_masking:
5702 err_msg = _("unsupported masking");
5704 case mask_not_on_destination:
5705 err_msg = _("mask not on destination operand");
5707 case no_default_mask:
5708 err_msg = _("default mask isn't allowed");
5710 case unsupported_rc_sae:
5711 err_msg = _("unsupported static rounding/sae");
5713 case rc_sae_operand_not_last_imm:
5715 err_msg = _("RC/SAE operand must precede immediate operands");
5717 err_msg = _("RC/SAE operand must follow immediate operands");
5719 case invalid_register_operand:
5720 err_msg = _("invalid register operand");
5723 as_bad (_("%s for `%s'"), err_msg,
5724 current_templates->start->name);
5728 if (!quiet_warnings)
5731 && (i.types[0].bitfield.jumpabsolute
5732 != operand_types[0].bitfield.jumpabsolute))
5734 as_warn (_("indirect %s without `*'"), t->name);
5737 if (t->opcode_modifier.isprefix
5738 && t->opcode_modifier.ignoresize)
5740 /* Warn them that a data or address size prefix doesn't
5741 affect assembly of the next line of code. */
5742 as_warn (_("stand-alone `%s' prefix"), t->name);
5746 /* Copy the template we found. */
5749 if (addr_prefix_disp != -1)
5750 i.tm.operand_types[addr_prefix_disp]
5751 = operand_types[addr_prefix_disp];
5753 if (found_reverse_match)
5755 /* If we found a reverse match we must alter the opcode
5756 direction bit. found_reverse_match holds bits to change
5757 (different for int & float insns). */
5759 i.tm.base_opcode ^= found_reverse_match;
5761 i.tm.operand_types[0] = operand_types[1];
5762 i.tm.operand_types[1] = operand_types[0];
5771 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5772 if (i.tm.operand_types[mem_op].bitfield.esseg)
5774 if (i.seg[0] != NULL && i.seg[0] != &es)
5776 as_bad (_("`%s' operand %d must use `%ses' segment"),
5782 /* There's only ever one segment override allowed per instruction.
5783 This instruction possibly has a legal segment override on the
5784 second operand, so copy the segment to where non-string
5785 instructions store it, allowing common code. */
5786 i.seg[0] = i.seg[1];
5788 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5790 if (i.seg[1] != NULL && i.seg[1] != &es)
5792 as_bad (_("`%s' operand %d must use `%ses' segment"),
5803 process_suffix (void)
5805 /* If matched instruction specifies an explicit instruction mnemonic
5807 if (i.tm.opcode_modifier.size16)
5808 i.suffix = WORD_MNEM_SUFFIX;
5809 else if (i.tm.opcode_modifier.size32)
5810 i.suffix = LONG_MNEM_SUFFIX;
5811 else if (i.tm.opcode_modifier.size64)
5812 i.suffix = QWORD_MNEM_SUFFIX;
5813 else if (i.reg_operands)
5815 /* If there's no instruction mnemonic suffix we try to invent one
5816 based on register operands. */
5819 /* We take i.suffix from the last register operand specified,
5820 Destination register type is more significant than source
5821 register type. crc32 in SSE4.2 prefers source register
5823 if (i.tm.base_opcode == 0xf20f38f1)
5825 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5826 i.suffix = WORD_MNEM_SUFFIX;
5827 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5828 i.suffix = LONG_MNEM_SUFFIX;
5829 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5830 i.suffix = QWORD_MNEM_SUFFIX;
5832 else if (i.tm.base_opcode == 0xf20f38f0)
5834 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5835 i.suffix = BYTE_MNEM_SUFFIX;
5842 if (i.tm.base_opcode == 0xf20f38f1
5843 || i.tm.base_opcode == 0xf20f38f0)
5845 /* We have to know the operand size for crc32. */
5846 as_bad (_("ambiguous memory operand size for `%s`"),
5851 for (op = i.operands; --op >= 0;)
5852 if (!i.tm.operand_types[op].bitfield.inoutportreg
5853 && !i.tm.operand_types[op].bitfield.shiftcount)
5855 if (!i.types[op].bitfield.reg)
5857 if (i.types[op].bitfield.byte)
5858 i.suffix = BYTE_MNEM_SUFFIX;
5859 else if (i.types[op].bitfield.word)
5860 i.suffix = WORD_MNEM_SUFFIX;
5861 else if (i.types[op].bitfield.dword)
5862 i.suffix = LONG_MNEM_SUFFIX;
5863 else if (i.types[op].bitfield.qword)
5864 i.suffix = QWORD_MNEM_SUFFIX;
5871 else if (i.suffix == BYTE_MNEM_SUFFIX)
5874 && i.tm.opcode_modifier.ignoresize
5875 && i.tm.opcode_modifier.no_bsuf)
5877 else if (!check_byte_reg ())
5880 else if (i.suffix == LONG_MNEM_SUFFIX)
5883 && i.tm.opcode_modifier.ignoresize
5884 && i.tm.opcode_modifier.no_lsuf
5885 && !i.tm.opcode_modifier.todword
5886 && !i.tm.opcode_modifier.toqword)
5888 else if (!check_long_reg ())
5891 else if (i.suffix == QWORD_MNEM_SUFFIX)
5894 && i.tm.opcode_modifier.ignoresize
5895 && i.tm.opcode_modifier.no_qsuf
5896 && !i.tm.opcode_modifier.todword
5897 && !i.tm.opcode_modifier.toqword)
5899 else if (!check_qword_reg ())
5902 else if (i.suffix == WORD_MNEM_SUFFIX)
5905 && i.tm.opcode_modifier.ignoresize
5906 && i.tm.opcode_modifier.no_wsuf)
5908 else if (!check_word_reg ())
5911 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5912 /* Do nothing if the instruction is going to ignore the prefix. */
5917 else if (i.tm.opcode_modifier.defaultsize
5919 /* exclude fldenv/frstor/fsave/fstenv */
5920 && i.tm.opcode_modifier.no_ssuf)
5922 i.suffix = stackop_size;
5924 else if (intel_syntax
5926 && (i.tm.operand_types[0].bitfield.jumpabsolute
5927 || i.tm.opcode_modifier.jumpbyte
5928 || i.tm.opcode_modifier.jumpintersegment
5929 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5930 && i.tm.extension_opcode <= 3)))
5935 if (!i.tm.opcode_modifier.no_qsuf)
5937 i.suffix = QWORD_MNEM_SUFFIX;
5942 if (!i.tm.opcode_modifier.no_lsuf)
5943 i.suffix = LONG_MNEM_SUFFIX;
5946 if (!i.tm.opcode_modifier.no_wsuf)
5947 i.suffix = WORD_MNEM_SUFFIX;
5956 if (i.tm.opcode_modifier.w)
5958 as_bad (_("no instruction mnemonic suffix given and "
5959 "no register operands; can't size instruction"));
5965 unsigned int suffixes;
5967 suffixes = !i.tm.opcode_modifier.no_bsuf;
5968 if (!i.tm.opcode_modifier.no_wsuf)
5970 if (!i.tm.opcode_modifier.no_lsuf)
5972 if (!i.tm.opcode_modifier.no_ldsuf)
5974 if (!i.tm.opcode_modifier.no_ssuf)
5976 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5979 /* There are more than suffix matches. */
5980 if (i.tm.opcode_modifier.w
5981 || ((suffixes & (suffixes - 1))
5982 && !i.tm.opcode_modifier.defaultsize
5983 && !i.tm.opcode_modifier.ignoresize))
5985 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5991 /* Change the opcode based on the operand size given by i.suffix. */
5994 /* Size floating point instruction. */
5995 case LONG_MNEM_SUFFIX:
5996 if (i.tm.opcode_modifier.floatmf)
5998 i.tm.base_opcode ^= 4;
6002 case WORD_MNEM_SUFFIX:
6003 case QWORD_MNEM_SUFFIX:
6004 /* It's not a byte, select word/dword operation. */
6005 if (i.tm.opcode_modifier.w)
6007 if (i.tm.opcode_modifier.shortform)
6008 i.tm.base_opcode |= 8;
6010 i.tm.base_opcode |= 1;
6013 case SHORT_MNEM_SUFFIX:
6014 /* Now select between word & dword operations via the operand
6015 size prefix, except for instructions that will ignore this
6017 if (i.reg_operands > 0
6018 && i.types[0].bitfield.reg
6019 && i.tm.opcode_modifier.addrprefixopreg
6020 && (i.tm.opcode_modifier.immext
6021 || i.operands == 1))
6023 /* The address size override prefix changes the size of the
6025 if ((flag_code == CODE_32BIT
6026 && i.op[0].regs->reg_type.bitfield.word)
6027 || (flag_code != CODE_32BIT
6028 && i.op[0].regs->reg_type.bitfield.dword))
6029 if (!add_prefix (ADDR_PREFIX_OPCODE))
6032 else if (i.suffix != QWORD_MNEM_SUFFIX
6033 && !i.tm.opcode_modifier.ignoresize
6034 && !i.tm.opcode_modifier.floatmf
6035 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6036 || (flag_code == CODE_64BIT
6037 && i.tm.opcode_modifier.jumpbyte)))
6039 unsigned int prefix = DATA_PREFIX_OPCODE;
6041 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6042 prefix = ADDR_PREFIX_OPCODE;
6044 if (!add_prefix (prefix))
6048 /* Set mode64 for an operand. */
6049 if (i.suffix == QWORD_MNEM_SUFFIX
6050 && flag_code == CODE_64BIT
6051 && !i.tm.opcode_modifier.norex64
6052 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6054 && ! (i.operands == 2
6055 && i.tm.base_opcode == 0x90
6056 && i.tm.extension_opcode == None
6057 && operand_type_equal (&i.types [0], &acc64)
6058 && operand_type_equal (&i.types [1], &acc64)))
6064 if (i.reg_operands != 0
6066 && i.tm.opcode_modifier.addrprefixopreg
6067 && !i.tm.opcode_modifier.immext)
6069 /* Check invalid register operand when the address size override
6070 prefix changes the size of register operands. */
6072 enum { need_word, need_dword, need_qword } need;
6074 if (flag_code == CODE_32BIT)
6075 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6078 if (i.prefix[ADDR_PREFIX])
6081 need = flag_code == CODE_64BIT ? need_qword : need_word;
6084 for (op = 0; op < i.operands; op++)
6085 if (i.types[op].bitfield.reg
6086 && ((need == need_word
6087 && !i.op[op].regs->reg_type.bitfield.word)
6088 || (need == need_dword
6089 && !i.op[op].regs->reg_type.bitfield.dword)
6090 || (need == need_qword
6091 && !i.op[op].regs->reg_type.bitfield.qword)))
6093 as_bad (_("invalid register operand size for `%s'"),
6103 check_byte_reg (void)
6107 for (op = i.operands; --op >= 0;)
6109 /* Skip non-register operands. */
6110 if (!i.types[op].bitfield.reg)
6113 /* If this is an eight bit register, it's OK. If it's the 16 or
6114 32 bit version of an eight bit register, we will just use the
6115 low portion, and that's OK too. */
6116 if (i.types[op].bitfield.byte)
6119 /* I/O port address operands are OK too. */
6120 if (i.tm.operand_types[op].bitfield.inoutportreg)
6123 /* crc32 doesn't generate this warning. */
6124 if (i.tm.base_opcode == 0xf20f38f0)
6127 if ((i.types[op].bitfield.word
6128 || i.types[op].bitfield.dword
6129 || i.types[op].bitfield.qword)
6130 && i.op[op].regs->reg_num < 4
6131 /* Prohibit these changes in 64bit mode, since the lowering
6132 would be more complicated. */
6133 && flag_code != CODE_64BIT)
6135 #if REGISTER_WARNINGS
6136 if (!quiet_warnings)
6137 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6139 (i.op[op].regs + (i.types[op].bitfield.word
6140 ? REGNAM_AL - REGNAM_AX
6141 : REGNAM_AL - REGNAM_EAX))->reg_name,
6143 i.op[op].regs->reg_name,
6148 /* Any other register is bad. */
6149 if (i.types[op].bitfield.reg
6150 || i.types[op].bitfield.regmmx
6151 || i.types[op].bitfield.regsimd
6152 || i.types[op].bitfield.sreg2
6153 || i.types[op].bitfield.sreg3
6154 || i.types[op].bitfield.control
6155 || i.types[op].bitfield.debug
6156 || i.types[op].bitfield.test)
6158 as_bad (_("`%s%s' not allowed with `%s%c'"),
6160 i.op[op].regs->reg_name,
6170 check_long_reg (void)
6174 for (op = i.operands; --op >= 0;)
6175 /* Skip non-register operands. */
6176 if (!i.types[op].bitfield.reg)
6178 /* Reject eight bit registers, except where the template requires
6179 them. (eg. movzb) */
6180 else if (i.types[op].bitfield.byte
6181 && (i.tm.operand_types[op].bitfield.reg
6182 || i.tm.operand_types[op].bitfield.acc)
6183 && (i.tm.operand_types[op].bitfield.word
6184 || i.tm.operand_types[op].bitfield.dword))
6186 as_bad (_("`%s%s' not allowed with `%s%c'"),
6188 i.op[op].regs->reg_name,
6193 /* Warn if the e prefix on a general reg is missing. */
6194 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6195 && i.types[op].bitfield.word
6196 && (i.tm.operand_types[op].bitfield.reg
6197 || i.tm.operand_types[op].bitfield.acc)
6198 && i.tm.operand_types[op].bitfield.dword)
6200 /* Prohibit these changes in the 64bit mode, since the
6201 lowering is more complicated. */
6202 if (flag_code == CODE_64BIT)
6204 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6205 register_prefix, i.op[op].regs->reg_name,
6209 #if REGISTER_WARNINGS
6210 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6212 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6213 register_prefix, i.op[op].regs->reg_name, i.suffix);
6216 /* Warn if the r prefix on a general reg is present. */
6217 else if (i.types[op].bitfield.qword
6218 && (i.tm.operand_types[op].bitfield.reg
6219 || i.tm.operand_types[op].bitfield.acc)
6220 && i.tm.operand_types[op].bitfield.dword)
6223 && i.tm.opcode_modifier.toqword
6224 && !i.types[0].bitfield.regsimd)
6226 /* Convert to QWORD. We want REX byte. */
6227 i.suffix = QWORD_MNEM_SUFFIX;
6231 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6232 register_prefix, i.op[op].regs->reg_name,
6241 check_qword_reg (void)
6245 for (op = i.operands; --op >= 0; )
6246 /* Skip non-register operands. */
6247 if (!i.types[op].bitfield.reg)
6249 /* Reject eight bit registers, except where the template requires
6250 them. (eg. movzb) */
6251 else if (i.types[op].bitfield.byte
6252 && (i.tm.operand_types[op].bitfield.reg
6253 || i.tm.operand_types[op].bitfield.acc)
6254 && (i.tm.operand_types[op].bitfield.word
6255 || i.tm.operand_types[op].bitfield.dword))
6257 as_bad (_("`%s%s' not allowed with `%s%c'"),
6259 i.op[op].regs->reg_name,
6264 /* Warn if the r prefix on a general reg is missing. */
6265 else if ((i.types[op].bitfield.word
6266 || i.types[op].bitfield.dword)
6267 && (i.tm.operand_types[op].bitfield.reg
6268 || i.tm.operand_types[op].bitfield.acc)
6269 && i.tm.operand_types[op].bitfield.qword)
6271 /* Prohibit these changes in the 64bit mode, since the
6272 lowering is more complicated. */
6274 && i.tm.opcode_modifier.todword
6275 && !i.types[0].bitfield.regsimd)
6277 /* Convert to DWORD. We don't want REX byte. */
6278 i.suffix = LONG_MNEM_SUFFIX;
6282 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6283 register_prefix, i.op[op].regs->reg_name,
6292 check_word_reg (void)
6295 for (op = i.operands; --op >= 0;)
6296 /* Skip non-register operands. */
6297 if (!i.types[op].bitfield.reg)
6299 /* Reject eight bit registers, except where the template requires
6300 them. (eg. movzb) */
6301 else if (i.types[op].bitfield.byte
6302 && (i.tm.operand_types[op].bitfield.reg
6303 || i.tm.operand_types[op].bitfield.acc)
6304 && (i.tm.operand_types[op].bitfield.word
6305 || i.tm.operand_types[op].bitfield.dword))
6307 as_bad (_("`%s%s' not allowed with `%s%c'"),
6309 i.op[op].regs->reg_name,
6314 /* Warn if the e or r prefix on a general reg is present. */
6315 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6316 && (i.types[op].bitfield.dword
6317 || i.types[op].bitfield.qword)
6318 && (i.tm.operand_types[op].bitfield.reg
6319 || i.tm.operand_types[op].bitfield.acc)
6320 && i.tm.operand_types[op].bitfield.word)
6322 /* Prohibit these changes in the 64bit mode, since the
6323 lowering is more complicated. */
6324 if (flag_code == CODE_64BIT)
6326 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6327 register_prefix, i.op[op].regs->reg_name,
6331 #if REGISTER_WARNINGS
6332 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6334 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6335 register_prefix, i.op[op].regs->reg_name, i.suffix);
6342 update_imm (unsigned int j)
6344 i386_operand_type overlap = i.types[j];
6345 if ((overlap.bitfield.imm8
6346 || overlap.bitfield.imm8s
6347 || overlap.bitfield.imm16
6348 || overlap.bitfield.imm32
6349 || overlap.bitfield.imm32s
6350 || overlap.bitfield.imm64)
6351 && !operand_type_equal (&overlap, &imm8)
6352 && !operand_type_equal (&overlap, &imm8s)
6353 && !operand_type_equal (&overlap, &imm16)
6354 && !operand_type_equal (&overlap, &imm32)
6355 && !operand_type_equal (&overlap, &imm32s)
6356 && !operand_type_equal (&overlap, &imm64))
6360 i386_operand_type temp;
6362 operand_type_set (&temp, 0);
6363 if (i.suffix == BYTE_MNEM_SUFFIX)
6365 temp.bitfield.imm8 = overlap.bitfield.imm8;
6366 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6368 else if (i.suffix == WORD_MNEM_SUFFIX)
6369 temp.bitfield.imm16 = overlap.bitfield.imm16;
6370 else if (i.suffix == QWORD_MNEM_SUFFIX)
6372 temp.bitfield.imm64 = overlap.bitfield.imm64;
6373 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6376 temp.bitfield.imm32 = overlap.bitfield.imm32;
6379 else if (operand_type_equal (&overlap, &imm16_32_32s)
6380 || operand_type_equal (&overlap, &imm16_32)
6381 || operand_type_equal (&overlap, &imm16_32s))
6383 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6388 if (!operand_type_equal (&overlap, &imm8)
6389 && !operand_type_equal (&overlap, &imm8s)
6390 && !operand_type_equal (&overlap, &imm16)
6391 && !operand_type_equal (&overlap, &imm32)
6392 && !operand_type_equal (&overlap, &imm32s)
6393 && !operand_type_equal (&overlap, &imm64))
6395 as_bad (_("no instruction mnemonic suffix given; "
6396 "can't determine immediate size"));
6400 i.types[j] = overlap;
6410 /* Update the first 2 immediate operands. */
6411 n = i.operands > 2 ? 2 : i.operands;
6414 for (j = 0; j < n; j++)
6415 if (update_imm (j) == 0)
6418 /* The 3rd operand can't be immediate operand. */
6419 gas_assert (operand_type_check (i.types[2], imm) == 0);
6426 process_operands (void)
6428 /* Default segment register this instruction will use for memory
6429 accesses. 0 means unknown. This is only for optimizing out
6430 unnecessary segment overrides. */
6431 const seg_entry *default_seg = 0;
6433 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6435 unsigned int dupl = i.operands;
6436 unsigned int dest = dupl - 1;
6439 /* The destination must be an xmm register. */
6440 gas_assert (i.reg_operands
6441 && MAX_OPERANDS > dupl
6442 && operand_type_equal (&i.types[dest], ®xmm));
6444 if (i.tm.operand_types[0].bitfield.acc
6445 && i.tm.operand_types[0].bitfield.xmmword)
6447 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6449 /* Keep xmm0 for instructions with VEX prefix and 3
6451 i.tm.operand_types[0].bitfield.acc = 0;
6452 i.tm.operand_types[0].bitfield.regsimd = 1;
6457 /* We remove the first xmm0 and keep the number of
6458 operands unchanged, which in fact duplicates the
6460 for (j = 1; j < i.operands; j++)
6462 i.op[j - 1] = i.op[j];
6463 i.types[j - 1] = i.types[j];
6464 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6468 else if (i.tm.opcode_modifier.implicit1stxmm0)
6470 gas_assert ((MAX_OPERANDS - 1) > dupl
6471 && (i.tm.opcode_modifier.vexsources
6474 /* Add the implicit xmm0 for instructions with VEX prefix
6476 for (j = i.operands; j > 0; j--)
6478 i.op[j] = i.op[j - 1];
6479 i.types[j] = i.types[j - 1];
6480 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6483 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6484 i.types[0] = regxmm;
6485 i.tm.operand_types[0] = regxmm;
6488 i.reg_operands += 2;
6493 i.op[dupl] = i.op[dest];
6494 i.types[dupl] = i.types[dest];
6495 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6504 i.op[dupl] = i.op[dest];
6505 i.types[dupl] = i.types[dest];
6506 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6509 if (i.tm.opcode_modifier.immext)
6512 else if (i.tm.operand_types[0].bitfield.acc
6513 && i.tm.operand_types[0].bitfield.xmmword)
6517 for (j = 1; j < i.operands; j++)
6519 i.op[j - 1] = i.op[j];
6520 i.types[j - 1] = i.types[j];
6522 /* We need to adjust fields in i.tm since they are used by
6523 build_modrm_byte. */
6524 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6531 else if (i.tm.opcode_modifier.implicitquadgroup)
6533 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6535 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6536 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6537 regnum = register_number (i.op[1].regs);
6538 first_reg_in_group = regnum & ~3;
6539 last_reg_in_group = first_reg_in_group + 3;
6540 if (regnum != first_reg_in_group)
6541 as_warn (_("source register `%s%s' implicitly denotes"
6542 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6543 register_prefix, i.op[1].regs->reg_name,
6544 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6545 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6548 else if (i.tm.opcode_modifier.regkludge)
6550 /* The imul $imm, %reg instruction is converted into
6551 imul $imm, %reg, %reg, and the clr %reg instruction
6552 is converted into xor %reg, %reg. */
6554 unsigned int first_reg_op;
6556 if (operand_type_check (i.types[0], reg))
6560 /* Pretend we saw the extra register operand. */
6561 gas_assert (i.reg_operands == 1
6562 && i.op[first_reg_op + 1].regs == 0);
6563 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6564 i.types[first_reg_op + 1] = i.types[first_reg_op];
6569 if (i.tm.opcode_modifier.shortform)
6571 if (i.types[0].bitfield.sreg2
6572 || i.types[0].bitfield.sreg3)
6574 if (i.tm.base_opcode == POP_SEG_SHORT
6575 && i.op[0].regs->reg_num == 1)
6577 as_bad (_("you can't `pop %scs'"), register_prefix);
6580 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6581 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6586 /* The register or float register operand is in operand
6590 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6591 || operand_type_check (i.types[0], reg))
6595 /* Register goes in low 3 bits of opcode. */
6596 i.tm.base_opcode |= i.op[op].regs->reg_num;
6597 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6599 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6601 /* Warn about some common errors, but press on regardless.
6602 The first case can be generated by gcc (<= 2.8.1). */
6603 if (i.operands == 2)
6605 /* Reversed arguments on faddp, fsubp, etc. */
6606 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6607 register_prefix, i.op[!intel_syntax].regs->reg_name,
6608 register_prefix, i.op[intel_syntax].regs->reg_name);
6612 /* Extraneous `l' suffix on fp insn. */
6613 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6614 register_prefix, i.op[0].regs->reg_name);
6619 else if (i.tm.opcode_modifier.modrm)
6621 /* The opcode is completed (modulo i.tm.extension_opcode which
6622 must be put into the modrm byte). Now, we make the modrm and
6623 index base bytes based on all the info we've collected. */
6625 default_seg = build_modrm_byte ();
6627 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6631 else if (i.tm.opcode_modifier.isstring)
6633 /* For the string instructions that allow a segment override
6634 on one of their operands, the default segment is ds. */
6638 if (i.tm.base_opcode == 0x8d /* lea */
6641 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6643 /* If a segment was explicitly specified, and the specified segment
6644 is not the default, use an opcode prefix to select it. If we
6645 never figured out what the default segment is, then default_seg
6646 will be zero at this point, and the specified segment prefix will
6648 if ((i.seg[0]) && (i.seg[0] != default_seg))
6650 if (!add_prefix (i.seg[0]->seg_prefix))
6656 static const seg_entry *
6657 build_modrm_byte (void)
6659 const seg_entry *default_seg = 0;
6660 unsigned int source, dest;
6663 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6666 unsigned int nds, reg_slot;
6669 dest = i.operands - 1;
6672 /* There are 2 kinds of instructions:
6673 1. 5 operands: 4 register operands or 3 register operands
6674 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6675 VexW0 or VexW1. The destination must be either XMM, YMM or
6677 2. 4 operands: 4 register operands or 3 register operands
6678 plus 1 memory operand, with VexXDS. */
6679 gas_assert ((i.reg_operands == 4
6680 || (i.reg_operands == 3 && i.mem_operands == 1))
6681 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6682 && i.tm.opcode_modifier.vexw
6683 && i.tm.operand_types[dest].bitfield.regsimd);
6685 /* If VexW1 is set, the first non-immediate operand is the source and
6686 the second non-immediate one is encoded in the immediate operand. */
6687 if (i.tm.opcode_modifier.vexw == VEXW1)
6689 source = i.imm_operands;
6690 reg_slot = i.imm_operands + 1;
6694 source = i.imm_operands + 1;
6695 reg_slot = i.imm_operands;
6698 if (i.imm_operands == 0)
6700 /* When there is no immediate operand, generate an 8bit
6701 immediate operand to encode the first operand. */
6702 exp = &im_expressions[i.imm_operands++];
6703 i.op[i.operands].imms = exp;
6704 i.types[i.operands] = imm8;
6707 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6708 exp->X_op = O_constant;
6709 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6710 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6714 unsigned int imm_slot;
6716 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6718 if (i.tm.opcode_modifier.immext)
6720 /* When ImmExt is set, the immediate byte is the last
6722 imm_slot = i.operands - 1;
6730 /* Turn on Imm8 so that output_imm will generate it. */
6731 i.types[imm_slot].bitfield.imm8 = 1;
6734 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6735 i.op[imm_slot].imms->X_add_number
6736 |= register_number (i.op[reg_slot].regs) << 4;
6737 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6740 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6741 i.vex.register_specifier = i.op[nds].regs;
6746 /* i.reg_operands MUST be the number of real register operands;
6747 implicit registers do not count. If there are 3 register
6748 operands, it must be a instruction with VexNDS. For a
6749 instruction with VexNDD, the destination register is encoded
6750 in VEX prefix. If there are 4 register operands, it must be
6751 a instruction with VEX prefix and 3 sources. */
6752 if (i.mem_operands == 0
6753 && ((i.reg_operands == 2
6754 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6755 || (i.reg_operands == 3
6756 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6757 || (i.reg_operands == 4 && vex_3_sources)))
6765 /* When there are 3 operands, one of them may be immediate,
6766 which may be the first or the last operand. Otherwise,
6767 the first operand must be shift count register (cl) or it
6768 is an instruction with VexNDS. */
6769 gas_assert (i.imm_operands == 1
6770 || (i.imm_operands == 0
6771 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6772 || i.types[0].bitfield.shiftcount)));
6773 if (operand_type_check (i.types[0], imm)
6774 || i.types[0].bitfield.shiftcount)
6780 /* When there are 4 operands, the first two must be 8bit
6781 immediate operands. The source operand will be the 3rd
6784 For instructions with VexNDS, if the first operand
6785 an imm8, the source operand is the 2nd one. If the last
6786 operand is imm8, the source operand is the first one. */
6787 gas_assert ((i.imm_operands == 2
6788 && i.types[0].bitfield.imm8
6789 && i.types[1].bitfield.imm8)
6790 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6791 && i.imm_operands == 1
6792 && (i.types[0].bitfield.imm8
6793 || i.types[i.operands - 1].bitfield.imm8
6795 if (i.imm_operands == 2)
6799 if (i.types[0].bitfield.imm8)
6806 if (is_evex_encoding (&i.tm))
6808 /* For EVEX instructions, when there are 5 operands, the
6809 first one must be immediate operand. If the second one
6810 is immediate operand, the source operand is the 3th
6811 one. If the last one is immediate operand, the source
6812 operand is the 2nd one. */
6813 gas_assert (i.imm_operands == 2
6814 && i.tm.opcode_modifier.sae
6815 && operand_type_check (i.types[0], imm));
6816 if (operand_type_check (i.types[1], imm))
6818 else if (operand_type_check (i.types[4], imm))
6832 /* RC/SAE operand could be between DEST and SRC. That happens
6833 when one operand is GPR and the other one is XMM/YMM/ZMM
6835 if (i.rounding && i.rounding->operand == (int) dest)
6838 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6840 /* For instructions with VexNDS, the register-only source
6841 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6842 register. It is encoded in VEX prefix. We need to
6843 clear RegMem bit before calling operand_type_equal. */
6845 i386_operand_type op;
6848 /* Check register-only source operand when two source
6849 operands are swapped. */
6850 if (!i.tm.operand_types[source].bitfield.baseindex
6851 && i.tm.operand_types[dest].bitfield.baseindex)
6859 op = i.tm.operand_types[vvvv];
6860 op.bitfield.regmem = 0;
6861 if ((dest + 1) >= i.operands
6862 || ((!op.bitfield.reg
6863 || (!op.bitfield.dword && !op.bitfield.qword))
6864 && !op.bitfield.regsimd
6865 && !operand_type_equal (&op, ®mask)))
6867 i.vex.register_specifier = i.op[vvvv].regs;
6873 /* One of the register operands will be encoded in the i.tm.reg
6874 field, the other in the combined i.tm.mode and i.tm.regmem
6875 fields. If no form of this instruction supports a memory
6876 destination operand, then we assume the source operand may
6877 sometimes be a memory operand and so we need to store the
6878 destination in the i.rm.reg field. */
6879 if (!i.tm.operand_types[dest].bitfield.regmem
6880 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6882 i.rm.reg = i.op[dest].regs->reg_num;
6883 i.rm.regmem = i.op[source].regs->reg_num;
6884 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6886 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6888 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6890 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6895 i.rm.reg = i.op[source].regs->reg_num;
6896 i.rm.regmem = i.op[dest].regs->reg_num;
6897 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6899 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6901 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6903 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6906 if (flag_code != CODE_64BIT && (i.rex & REX_R))
6908 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
6911 add_prefix (LOCK_PREFIX_OPCODE);
6915 { /* If it's not 2 reg operands... */
6920 unsigned int fake_zero_displacement = 0;
6923 for (op = 0; op < i.operands; op++)
6924 if (operand_type_check (i.types[op], anymem))
6926 gas_assert (op < i.operands);
6928 if (i.tm.opcode_modifier.vecsib)
6930 if (i.index_reg->reg_num == RegEiz
6931 || i.index_reg->reg_num == RegRiz)
6934 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6937 i.sib.base = NO_BASE_REGISTER;
6938 i.sib.scale = i.log2_scale_factor;
6939 i.types[op].bitfield.disp8 = 0;
6940 i.types[op].bitfield.disp16 = 0;
6941 i.types[op].bitfield.disp64 = 0;
6942 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6944 /* Must be 32 bit */
6945 i.types[op].bitfield.disp32 = 1;
6946 i.types[op].bitfield.disp32s = 0;
6950 i.types[op].bitfield.disp32 = 0;
6951 i.types[op].bitfield.disp32s = 1;
6954 i.sib.index = i.index_reg->reg_num;
6955 if ((i.index_reg->reg_flags & RegRex) != 0)
6957 if ((i.index_reg->reg_flags & RegVRex) != 0)
6963 if (i.base_reg == 0)
6966 if (!i.disp_operands)
6967 fake_zero_displacement = 1;
6968 if (i.index_reg == 0)
6970 i386_operand_type newdisp;
6972 gas_assert (!i.tm.opcode_modifier.vecsib);
6973 /* Operand is just <disp> */
6974 if (flag_code == CODE_64BIT)
6976 /* 64bit mode overwrites the 32bit absolute
6977 addressing by RIP relative addressing and
6978 absolute addressing is encoded by one of the
6979 redundant SIB forms. */
6980 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6981 i.sib.base = NO_BASE_REGISTER;
6982 i.sib.index = NO_INDEX_REGISTER;
6983 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6985 else if ((flag_code == CODE_16BIT)
6986 ^ (i.prefix[ADDR_PREFIX] != 0))
6988 i.rm.regmem = NO_BASE_REGISTER_16;
6993 i.rm.regmem = NO_BASE_REGISTER;
6996 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6997 i.types[op] = operand_type_or (i.types[op], newdisp);
6999 else if (!i.tm.opcode_modifier.vecsib)
7001 /* !i.base_reg && i.index_reg */
7002 if (i.index_reg->reg_num == RegEiz
7003 || i.index_reg->reg_num == RegRiz)
7004 i.sib.index = NO_INDEX_REGISTER;
7006 i.sib.index = i.index_reg->reg_num;
7007 i.sib.base = NO_BASE_REGISTER;
7008 i.sib.scale = i.log2_scale_factor;
7009 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7010 i.types[op].bitfield.disp8 = 0;
7011 i.types[op].bitfield.disp16 = 0;
7012 i.types[op].bitfield.disp64 = 0;
7013 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7015 /* Must be 32 bit */
7016 i.types[op].bitfield.disp32 = 1;
7017 i.types[op].bitfield.disp32s = 0;
7021 i.types[op].bitfield.disp32 = 0;
7022 i.types[op].bitfield.disp32s = 1;
7024 if ((i.index_reg->reg_flags & RegRex) != 0)
7028 /* RIP addressing for 64bit mode. */
7029 else if (i.base_reg->reg_num == RegRip ||
7030 i.base_reg->reg_num == RegEip)
7032 gas_assert (!i.tm.opcode_modifier.vecsib);
7033 i.rm.regmem = NO_BASE_REGISTER;
7034 i.types[op].bitfield.disp8 = 0;
7035 i.types[op].bitfield.disp16 = 0;
7036 i.types[op].bitfield.disp32 = 0;
7037 i.types[op].bitfield.disp32s = 1;
7038 i.types[op].bitfield.disp64 = 0;
7039 i.flags[op] |= Operand_PCrel;
7040 if (! i.disp_operands)
7041 fake_zero_displacement = 1;
7043 else if (i.base_reg->reg_type.bitfield.word)
7045 gas_assert (!i.tm.opcode_modifier.vecsib);
7046 switch (i.base_reg->reg_num)
7049 if (i.index_reg == 0)
7051 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7052 i.rm.regmem = i.index_reg->reg_num - 6;
7056 if (i.index_reg == 0)
7059 if (operand_type_check (i.types[op], disp) == 0)
7061 /* fake (%bp) into 0(%bp) */
7062 i.types[op].bitfield.disp8 = 1;
7063 fake_zero_displacement = 1;
7066 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7067 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7069 default: /* (%si) -> 4 or (%di) -> 5 */
7070 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7072 i.rm.mode = mode_from_disp_size (i.types[op]);
7074 else /* i.base_reg and 32/64 bit mode */
7076 if (flag_code == CODE_64BIT
7077 && operand_type_check (i.types[op], disp))
7079 i.types[op].bitfield.disp16 = 0;
7080 i.types[op].bitfield.disp64 = 0;
7081 if (i.prefix[ADDR_PREFIX] == 0)
7083 i.types[op].bitfield.disp32 = 0;
7084 i.types[op].bitfield.disp32s = 1;
7088 i.types[op].bitfield.disp32 = 1;
7089 i.types[op].bitfield.disp32s = 0;
7093 if (!i.tm.opcode_modifier.vecsib)
7094 i.rm.regmem = i.base_reg->reg_num;
7095 if ((i.base_reg->reg_flags & RegRex) != 0)
7097 i.sib.base = i.base_reg->reg_num;
7098 /* x86-64 ignores REX prefix bit here to avoid decoder
7100 if (!(i.base_reg->reg_flags & RegRex)
7101 && (i.base_reg->reg_num == EBP_REG_NUM
7102 || i.base_reg->reg_num == ESP_REG_NUM))
7104 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7106 fake_zero_displacement = 1;
7107 i.types[op].bitfield.disp8 = 1;
7109 i.sib.scale = i.log2_scale_factor;
7110 if (i.index_reg == 0)
7112 gas_assert (!i.tm.opcode_modifier.vecsib);
7113 /* <disp>(%esp) becomes two byte modrm with no index
7114 register. We've already stored the code for esp
7115 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7116 Any base register besides %esp will not use the
7117 extra modrm byte. */
7118 i.sib.index = NO_INDEX_REGISTER;
7120 else if (!i.tm.opcode_modifier.vecsib)
7122 if (i.index_reg->reg_num == RegEiz
7123 || i.index_reg->reg_num == RegRiz)
7124 i.sib.index = NO_INDEX_REGISTER;
7126 i.sib.index = i.index_reg->reg_num;
7127 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7128 if ((i.index_reg->reg_flags & RegRex) != 0)
7133 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7134 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7138 if (!fake_zero_displacement
7142 fake_zero_displacement = 1;
7143 if (i.disp_encoding == disp_encoding_8bit)
7144 i.types[op].bitfield.disp8 = 1;
7146 i.types[op].bitfield.disp32 = 1;
7148 i.rm.mode = mode_from_disp_size (i.types[op]);
7152 if (fake_zero_displacement)
7154 /* Fakes a zero displacement assuming that i.types[op]
7155 holds the correct displacement size. */
7158 gas_assert (i.op[op].disps == 0);
7159 exp = &disp_expressions[i.disp_operands++];
7160 i.op[op].disps = exp;
7161 exp->X_op = O_constant;
7162 exp->X_add_number = 0;
7163 exp->X_add_symbol = (symbolS *) 0;
7164 exp->X_op_symbol = (symbolS *) 0;
7172 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7174 if (operand_type_check (i.types[0], imm))
7175 i.vex.register_specifier = NULL;
7178 /* VEX.vvvv encodes one of the sources when the first
7179 operand is not an immediate. */
7180 if (i.tm.opcode_modifier.vexw == VEXW0)
7181 i.vex.register_specifier = i.op[0].regs;
7183 i.vex.register_specifier = i.op[1].regs;
7186 /* Destination is a XMM register encoded in the ModRM.reg
7188 i.rm.reg = i.op[2].regs->reg_num;
7189 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7192 /* ModRM.rm and VEX.B encodes the other source. */
7193 if (!i.mem_operands)
7197 if (i.tm.opcode_modifier.vexw == VEXW0)
7198 i.rm.regmem = i.op[1].regs->reg_num;
7200 i.rm.regmem = i.op[0].regs->reg_num;
7202 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7206 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7208 i.vex.register_specifier = i.op[2].regs;
7209 if (!i.mem_operands)
7212 i.rm.regmem = i.op[1].regs->reg_num;
7213 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7217 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7218 (if any) based on i.tm.extension_opcode. Again, we must be
7219 careful to make sure that segment/control/debug/test/MMX
7220 registers are coded into the i.rm.reg field. */
7221 else if (i.reg_operands)
7224 unsigned int vex_reg = ~0;
7226 for (op = 0; op < i.operands; op++)
7227 if (i.types[op].bitfield.reg
7228 || i.types[op].bitfield.regmmx
7229 || i.types[op].bitfield.regsimd
7230 || i.types[op].bitfield.regbnd
7231 || i.types[op].bitfield.regmask
7232 || i.types[op].bitfield.sreg2
7233 || i.types[op].bitfield.sreg3
7234 || i.types[op].bitfield.control
7235 || i.types[op].bitfield.debug
7236 || i.types[op].bitfield.test)
7241 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7243 /* For instructions with VexNDS, the register-only
7244 source operand is encoded in VEX prefix. */
7245 gas_assert (mem != (unsigned int) ~0);
7250 gas_assert (op < i.operands);
7254 /* Check register-only source operand when two source
7255 operands are swapped. */
7256 if (!i.tm.operand_types[op].bitfield.baseindex
7257 && i.tm.operand_types[op + 1].bitfield.baseindex)
7261 gas_assert (mem == (vex_reg + 1)
7262 && op < i.operands);
7267 gas_assert (vex_reg < i.operands);
7271 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7273 /* For instructions with VexNDD, the register destination
7274 is encoded in VEX prefix. */
7275 if (i.mem_operands == 0)
7277 /* There is no memory operand. */
7278 gas_assert ((op + 2) == i.operands);
7283 /* There are only 2 non-immediate operands. */
7284 gas_assert (op < i.imm_operands + 2
7285 && i.operands == i.imm_operands + 2);
7286 vex_reg = i.imm_operands + 1;
7290 gas_assert (op < i.operands);
7292 if (vex_reg != (unsigned int) ~0)
7294 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7296 if ((!type->bitfield.reg
7297 || (!type->bitfield.dword && !type->bitfield.qword))
7298 && !type->bitfield.regsimd
7299 && !operand_type_equal (type, ®mask))
7302 i.vex.register_specifier = i.op[vex_reg].regs;
7305 /* Don't set OP operand twice. */
7308 /* If there is an extension opcode to put here, the
7309 register number must be put into the regmem field. */
7310 if (i.tm.extension_opcode != None)
7312 i.rm.regmem = i.op[op].regs->reg_num;
7313 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7315 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7320 i.rm.reg = i.op[op].regs->reg_num;
7321 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7323 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7328 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7329 must set it to 3 to indicate this is a register operand
7330 in the regmem field. */
7331 if (!i.mem_operands)
7335 /* Fill in i.rm.reg field with extension opcode (if any). */
7336 if (i.tm.extension_opcode != None)
7337 i.rm.reg = i.tm.extension_opcode;
7343 output_branch (void)
7349 relax_substateT subtype;
7353 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7354 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7357 if (i.prefix[DATA_PREFIX] != 0)
7363 /* Pentium4 branch hints. */
7364 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7365 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7370 if (i.prefix[REX_PREFIX] != 0)
7376 /* BND prefixed jump. */
7377 if (i.prefix[BND_PREFIX] != 0)
7379 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7383 if (i.prefixes != 0 && !intel_syntax)
7384 as_warn (_("skipping prefixes on this instruction"));
7386 /* It's always a symbol; End frag & setup for relax.
7387 Make sure there is enough room in this frag for the largest
7388 instruction we may generate in md_convert_frag. This is 2
7389 bytes for the opcode and room for the prefix and largest
7391 frag_grow (prefix + 2 + 4);
7392 /* Prefix and 1 opcode byte go in fr_fix. */
7393 p = frag_more (prefix + 1);
7394 if (i.prefix[DATA_PREFIX] != 0)
7395 *p++ = DATA_PREFIX_OPCODE;
7396 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7397 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7398 *p++ = i.prefix[SEG_PREFIX];
7399 if (i.prefix[REX_PREFIX] != 0)
7400 *p++ = i.prefix[REX_PREFIX];
7401 *p = i.tm.base_opcode;
7403 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7404 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7405 else if (cpu_arch_flags.bitfield.cpui386)
7406 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7408 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7411 sym = i.op[0].disps->X_add_symbol;
7412 off = i.op[0].disps->X_add_number;
7414 if (i.op[0].disps->X_op != O_constant
7415 && i.op[0].disps->X_op != O_symbol)
7417 /* Handle complex expressions. */
7418 sym = make_expr_symbol (i.op[0].disps);
7422 /* 1 possible extra opcode + 4 byte displacement go in var part.
7423 Pass reloc in fr_var. */
7424 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7428 /* Return TRUE iff PLT32 relocation should be used for branching to
7432 need_plt32_p (symbolS *s)
7434 /* PLT32 relocation is ELF only. */
7438 /* Since there is no need to prepare for PLT branch on x86-64, we
7439 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7440 be used as a marker for 32-bit PC-relative branches. */
7444 /* Weak or undefined symbol need PLT32 relocation. */
7445 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7448 /* Non-global symbol doesn't need PLT32 relocation. */
7449 if (! S_IS_EXTERNAL (s))
7452 /* Other global symbols need PLT32 relocation. NB: Symbol with
7453 non-default visibilities are treated as normal global symbol
7454 so that PLT32 relocation can be used as a marker for 32-bit
7455 PC-relative branches. It is useful for linker relaxation. */
7466 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7468 if (i.tm.opcode_modifier.jumpbyte)
7470 /* This is a loop or jecxz type instruction. */
7472 if (i.prefix[ADDR_PREFIX] != 0)
7474 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7477 /* Pentium4 branch hints. */
7478 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7479 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7481 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7490 if (flag_code == CODE_16BIT)
7493 if (i.prefix[DATA_PREFIX] != 0)
7495 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7505 if (i.prefix[REX_PREFIX] != 0)
7507 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7511 /* BND prefixed jump. */
7512 if (i.prefix[BND_PREFIX] != 0)
7514 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7518 if (i.prefixes != 0 && !intel_syntax)
7519 as_warn (_("skipping prefixes on this instruction"));
7521 p = frag_more (i.tm.opcode_length + size);
7522 switch (i.tm.opcode_length)
7525 *p++ = i.tm.base_opcode >> 8;
7528 *p++ = i.tm.base_opcode;
7534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7536 && jump_reloc == NO_RELOC
7537 && need_plt32_p (i.op[0].disps->X_add_symbol))
7538 jump_reloc = BFD_RELOC_X86_64_PLT32;
7541 jump_reloc = reloc (size, 1, 1, jump_reloc);
7543 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7544 i.op[0].disps, 1, jump_reloc);
7546 /* All jumps handled here are signed, but don't use a signed limit
7547 check for 32 and 16 bit jumps as we want to allow wrap around at
7548 4G and 64k respectively. */
7550 fixP->fx_signed = 1;
7554 output_interseg_jump (void)
7562 if (flag_code == CODE_16BIT)
7566 if (i.prefix[DATA_PREFIX] != 0)
7572 if (i.prefix[REX_PREFIX] != 0)
7582 if (i.prefixes != 0 && !intel_syntax)
7583 as_warn (_("skipping prefixes on this instruction"));
7585 /* 1 opcode; 2 segment; offset */
7586 p = frag_more (prefix + 1 + 2 + size);
7588 if (i.prefix[DATA_PREFIX] != 0)
7589 *p++ = DATA_PREFIX_OPCODE;
7591 if (i.prefix[REX_PREFIX] != 0)
7592 *p++ = i.prefix[REX_PREFIX];
7594 *p++ = i.tm.base_opcode;
7595 if (i.op[1].imms->X_op == O_constant)
7597 offsetT n = i.op[1].imms->X_add_number;
7600 && !fits_in_unsigned_word (n)
7601 && !fits_in_signed_word (n))
7603 as_bad (_("16-bit jump out of range"));
7606 md_number_to_chars (p, n, size);
7609 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7610 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7611 if (i.op[0].imms->X_op != O_constant)
7612 as_bad (_("can't handle non absolute segment in `%s'"),
7614 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7620 fragS *insn_start_frag;
7621 offsetT insn_start_off;
7623 /* Tie dwarf2 debug info to the address at the start of the insn.
7624 We can't do this after the insn has been output as the current
7625 frag may have been closed off. eg. by frag_var. */
7626 dwarf2_emit_insn (0);
7628 insn_start_frag = frag_now;
7629 insn_start_off = frag_now_fix ();
7632 if (i.tm.opcode_modifier.jump)
7634 else if (i.tm.opcode_modifier.jumpbyte
7635 || i.tm.opcode_modifier.jumpdword)
7637 else if (i.tm.opcode_modifier.jumpintersegment)
7638 output_interseg_jump ();
7641 /* Output normal instructions here. */
7645 unsigned int prefix;
7648 && i.tm.base_opcode == 0xfae
7650 && i.imm_operands == 1
7651 && (i.op[0].imms->X_add_number == 0xe8
7652 || i.op[0].imms->X_add_number == 0xf0
7653 || i.op[0].imms->X_add_number == 0xf8))
7655 /* Encode lfence, mfence, and sfence as
7656 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7657 offsetT val = 0x240483f0ULL;
7659 md_number_to_chars (p, val, 5);
7663 /* Some processors fail on LOCK prefix. This options makes
7664 assembler ignore LOCK prefix and serves as a workaround. */
7665 if (omit_lock_prefix)
7667 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7669 i.prefix[LOCK_PREFIX] = 0;
7672 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7673 don't need the explicit prefix. */
7674 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7676 switch (i.tm.opcode_length)
7679 if (i.tm.base_opcode & 0xff000000)
7681 prefix = (i.tm.base_opcode >> 24) & 0xff;
7682 add_prefix (prefix);
7686 if ((i.tm.base_opcode & 0xff0000) != 0)
7688 prefix = (i.tm.base_opcode >> 16) & 0xff;
7689 if (!i.tm.cpu_flags.bitfield.cpupadlock
7690 || prefix != REPE_PREFIX_OPCODE
7691 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7692 add_prefix (prefix);
7698 /* Check for pseudo prefixes. */
7699 as_bad_where (insn_start_frag->fr_file,
7700 insn_start_frag->fr_line,
7701 _("pseudo prefix without instruction"));
7707 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7708 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7709 R_X86_64_GOTTPOFF relocation so that linker can safely
7710 perform IE->LE optimization. */
7711 if (x86_elf_abi == X86_64_X32_ABI
7713 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7714 && i.prefix[REX_PREFIX] == 0)
7715 add_prefix (REX_OPCODE);
7718 /* The prefix bytes. */
7719 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7721 FRAG_APPEND_1_CHAR (*q);
7725 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7730 /* REX byte is encoded in VEX prefix. */
7734 FRAG_APPEND_1_CHAR (*q);
7737 /* There should be no other prefixes for instructions
7742 /* For EVEX instructions i.vrex should become 0 after
7743 build_evex_prefix. For VEX instructions upper 16 registers
7744 aren't available, so VREX should be 0. */
7747 /* Now the VEX prefix. */
7748 p = frag_more (i.vex.length);
7749 for (j = 0; j < i.vex.length; j++)
7750 p[j] = i.vex.bytes[j];
7753 /* Now the opcode; be careful about word order here! */
7754 if (i.tm.opcode_length == 1)
7756 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7760 switch (i.tm.opcode_length)
7764 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7765 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7769 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7779 /* Put out high byte first: can't use md_number_to_chars! */
7780 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7781 *p = i.tm.base_opcode & 0xff;
7784 /* Now the modrm byte and sib byte (if present). */
7785 if (i.tm.opcode_modifier.modrm)
7787 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7790 /* If i.rm.regmem == ESP (4)
7791 && i.rm.mode != (Register mode)
7793 ==> need second modrm byte. */
7794 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7796 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7797 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7799 | i.sib.scale << 6));
7802 if (i.disp_operands)
7803 output_disp (insn_start_frag, insn_start_off);
7806 output_imm (insn_start_frag, insn_start_off);
7812 pi ("" /*line*/, &i);
7814 #endif /* DEBUG386 */
7817 /* Return the size of the displacement operand N. */
7820 disp_size (unsigned int n)
7824 if (i.types[n].bitfield.disp64)
7826 else if (i.types[n].bitfield.disp8)
7828 else if (i.types[n].bitfield.disp16)
7833 /* Return the size of the immediate operand N. */
7836 imm_size (unsigned int n)
7839 if (i.types[n].bitfield.imm64)
7841 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7843 else if (i.types[n].bitfield.imm16)
7849 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7854 for (n = 0; n < i.operands; n++)
7856 if (operand_type_check (i.types[n], disp))
7858 if (i.op[n].disps->X_op == O_constant)
7860 int size = disp_size (n);
7861 offsetT val = i.op[n].disps->X_add_number;
7863 val = offset_in_range (val >> i.memshift, size);
7864 p = frag_more (size);
7865 md_number_to_chars (p, val, size);
7869 enum bfd_reloc_code_real reloc_type;
7870 int size = disp_size (n);
7871 int sign = i.types[n].bitfield.disp32s;
7872 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7875 /* We can't have 8 bit displacement here. */
7876 gas_assert (!i.types[n].bitfield.disp8);
7878 /* The PC relative address is computed relative
7879 to the instruction boundary, so in case immediate
7880 fields follows, we need to adjust the value. */
7881 if (pcrel && i.imm_operands)
7886 for (n1 = 0; n1 < i.operands; n1++)
7887 if (operand_type_check (i.types[n1], imm))
7889 /* Only one immediate is allowed for PC
7890 relative address. */
7891 gas_assert (sz == 0);
7893 i.op[n].disps->X_add_number -= sz;
7895 /* We should find the immediate. */
7896 gas_assert (sz != 0);
7899 p = frag_more (size);
7900 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7902 && GOT_symbol == i.op[n].disps->X_add_symbol
7903 && (((reloc_type == BFD_RELOC_32
7904 || reloc_type == BFD_RELOC_X86_64_32S
7905 || (reloc_type == BFD_RELOC_64
7907 && (i.op[n].disps->X_op == O_symbol
7908 || (i.op[n].disps->X_op == O_add
7909 && ((symbol_get_value_expression
7910 (i.op[n].disps->X_op_symbol)->X_op)
7912 || reloc_type == BFD_RELOC_32_PCREL))
7916 if (insn_start_frag == frag_now)
7917 add = (p - frag_now->fr_literal) - insn_start_off;
7922 add = insn_start_frag->fr_fix - insn_start_off;
7923 for (fr = insn_start_frag->fr_next;
7924 fr && fr != frag_now; fr = fr->fr_next)
7926 add += p - frag_now->fr_literal;
7931 reloc_type = BFD_RELOC_386_GOTPC;
7932 i.op[n].imms->X_add_number += add;
7934 else if (reloc_type == BFD_RELOC_64)
7935 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7937 /* Don't do the adjustment for x86-64, as there
7938 the pcrel addressing is relative to the _next_
7939 insn, and that is taken care of in other code. */
7940 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7942 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7943 size, i.op[n].disps, pcrel,
7945 /* Check for "call/jmp *mem", "mov mem, %reg",
7946 "test %reg, mem" and "binop mem, %reg" where binop
7947 is one of adc, add, and, cmp, or, sbb, sub, xor
7948 instructions. Always generate R_386_GOT32X for
7949 "sym*GOT" operand in 32-bit mode. */
7950 if ((generate_relax_relocations
7953 && i.rm.regmem == 5))
7955 || (i.rm.mode == 0 && i.rm.regmem == 5))
7956 && ((i.operands == 1
7957 && i.tm.base_opcode == 0xff
7958 && (i.rm.reg == 2 || i.rm.reg == 4))
7960 && (i.tm.base_opcode == 0x8b
7961 || i.tm.base_opcode == 0x85
7962 || (i.tm.base_opcode & 0xc7) == 0x03))))
7966 fixP->fx_tcbit = i.rex != 0;
7968 && (i.base_reg->reg_num == RegRip
7969 || i.base_reg->reg_num == RegEip))
7970 fixP->fx_tcbit2 = 1;
7973 fixP->fx_tcbit2 = 1;
7981 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7986 for (n = 0; n < i.operands; n++)
7988 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7989 if (i.rounding && (int) n == i.rounding->operand)
7992 if (operand_type_check (i.types[n], imm))
7994 if (i.op[n].imms->X_op == O_constant)
7996 int size = imm_size (n);
7999 val = offset_in_range (i.op[n].imms->X_add_number,
8001 p = frag_more (size);
8002 md_number_to_chars (p, val, size);
8006 /* Not absolute_section.
8007 Need a 32-bit fixup (don't support 8bit
8008 non-absolute imms). Try to support other
8010 enum bfd_reloc_code_real reloc_type;
8011 int size = imm_size (n);
8014 if (i.types[n].bitfield.imm32s
8015 && (i.suffix == QWORD_MNEM_SUFFIX
8016 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8021 p = frag_more (size);
8022 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8024 /* This is tough to explain. We end up with this one if we
8025 * have operands that look like
8026 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8027 * obtain the absolute address of the GOT, and it is strongly
8028 * preferable from a performance point of view to avoid using
8029 * a runtime relocation for this. The actual sequence of
8030 * instructions often look something like:
8035 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8037 * The call and pop essentially return the absolute address
8038 * of the label .L66 and store it in %ebx. The linker itself
8039 * will ultimately change the first operand of the addl so
8040 * that %ebx points to the GOT, but to keep things simple, the
8041 * .o file must have this operand set so that it generates not
8042 * the absolute address of .L66, but the absolute address of
8043 * itself. This allows the linker itself simply treat a GOTPC
8044 * relocation as asking for a pcrel offset to the GOT to be
8045 * added in, and the addend of the relocation is stored in the
8046 * operand field for the instruction itself.
8048 * Our job here is to fix the operand so that it would add
8049 * the correct offset so that %ebx would point to itself. The
8050 * thing that is tricky is that .-.L66 will point to the
8051 * beginning of the instruction, so we need to further modify
8052 * the operand so that it will point to itself. There are
8053 * other cases where you have something like:
8055 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8057 * and here no correction would be required. Internally in
8058 * the assembler we treat operands of this form as not being
8059 * pcrel since the '.' is explicitly mentioned, and I wonder
8060 * whether it would simplify matters to do it this way. Who
8061 * knows. In earlier versions of the PIC patches, the
8062 * pcrel_adjust field was used to store the correction, but
8063 * since the expression is not pcrel, I felt it would be
8064 * confusing to do it this way. */
8066 if ((reloc_type == BFD_RELOC_32
8067 || reloc_type == BFD_RELOC_X86_64_32S
8068 || reloc_type == BFD_RELOC_64)
8070 && GOT_symbol == i.op[n].imms->X_add_symbol
8071 && (i.op[n].imms->X_op == O_symbol
8072 || (i.op[n].imms->X_op == O_add
8073 && ((symbol_get_value_expression
8074 (i.op[n].imms->X_op_symbol)->X_op)
8079 if (insn_start_frag == frag_now)
8080 add = (p - frag_now->fr_literal) - insn_start_off;
8085 add = insn_start_frag->fr_fix - insn_start_off;
8086 for (fr = insn_start_frag->fr_next;
8087 fr && fr != frag_now; fr = fr->fr_next)
8089 add += p - frag_now->fr_literal;
8093 reloc_type = BFD_RELOC_386_GOTPC;
8095 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8097 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8098 i.op[n].imms->X_add_number += add;
8100 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8101 i.op[n].imms, 0, reloc_type);
8107 /* x86_cons_fix_new is called via the expression parsing code when a
8108 reloc is needed. We use this hook to get the correct .got reloc. */
8109 static int cons_sign = -1;
8112 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8113 expressionS *exp, bfd_reloc_code_real_type r)
8115 r = reloc (len, 0, cons_sign, r);
8118 if (exp->X_op == O_secrel)
8120 exp->X_op = O_symbol;
8121 r = BFD_RELOC_32_SECREL;
8125 fix_new_exp (frag, off, len, exp, 0, r);
8128 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8129 purpose of the `.dc.a' internal pseudo-op. */
8132 x86_address_bytes (void)
8134 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8136 return stdoutput->arch_info->bits_per_address / 8;
8139 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8141 # define lex_got(reloc, adjust, types) NULL
8143 /* Parse operands of the form
8144 <symbol>@GOTOFF+<nnn>
8145 and similar .plt or .got references.
8147 If we find one, set up the correct relocation in RELOC and copy the
8148 input string, minus the `@GOTOFF' into a malloc'd buffer for
8149 parsing by the calling routine. Return this buffer, and if ADJUST
8150 is non-null set it to the length of the string we removed from the
8151 input line. Otherwise return NULL. */
8153 lex_got (enum bfd_reloc_code_real *rel,
8155 i386_operand_type *types)
8157 /* Some of the relocations depend on the size of what field is to
8158 be relocated. But in our callers i386_immediate and i386_displacement
8159 we don't yet know the operand size (this will be set by insn
8160 matching). Hence we record the word32 relocation here,
8161 and adjust the reloc according to the real size in reloc(). */
8162 static const struct {
8165 const enum bfd_reloc_code_real rel[2];
8166 const i386_operand_type types64;
8168 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8169 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8171 OPERAND_TYPE_IMM32_64 },
8173 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8174 BFD_RELOC_X86_64_PLTOFF64 },
8175 OPERAND_TYPE_IMM64 },
8176 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8177 BFD_RELOC_X86_64_PLT32 },
8178 OPERAND_TYPE_IMM32_32S_DISP32 },
8179 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8180 BFD_RELOC_X86_64_GOTPLT64 },
8181 OPERAND_TYPE_IMM64_DISP64 },
8182 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8183 BFD_RELOC_X86_64_GOTOFF64 },
8184 OPERAND_TYPE_IMM64_DISP64 },
8185 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8186 BFD_RELOC_X86_64_GOTPCREL },
8187 OPERAND_TYPE_IMM32_32S_DISP32 },
8188 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8189 BFD_RELOC_X86_64_TLSGD },
8190 OPERAND_TYPE_IMM32_32S_DISP32 },
8191 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8192 _dummy_first_bfd_reloc_code_real },
8193 OPERAND_TYPE_NONE },
8194 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8195 BFD_RELOC_X86_64_TLSLD },
8196 OPERAND_TYPE_IMM32_32S_DISP32 },
8197 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8198 BFD_RELOC_X86_64_GOTTPOFF },
8199 OPERAND_TYPE_IMM32_32S_DISP32 },
8200 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8201 BFD_RELOC_X86_64_TPOFF32 },
8202 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8203 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8204 _dummy_first_bfd_reloc_code_real },
8205 OPERAND_TYPE_NONE },
8206 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8207 BFD_RELOC_X86_64_DTPOFF32 },
8208 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8209 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8210 _dummy_first_bfd_reloc_code_real },
8211 OPERAND_TYPE_NONE },
8212 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8213 _dummy_first_bfd_reloc_code_real },
8214 OPERAND_TYPE_NONE },
8215 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8216 BFD_RELOC_X86_64_GOT32 },
8217 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8218 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8219 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8220 OPERAND_TYPE_IMM32_32S_DISP32 },
8221 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8222 BFD_RELOC_X86_64_TLSDESC_CALL },
8223 OPERAND_TYPE_IMM32_32S_DISP32 },
8228 #if defined (OBJ_MAYBE_ELF)
8233 for (cp = input_line_pointer; *cp != '@'; cp++)
8234 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8237 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8239 int len = gotrel[j].len;
8240 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8242 if (gotrel[j].rel[object_64bit] != 0)
8245 char *tmpbuf, *past_reloc;
8247 *rel = gotrel[j].rel[object_64bit];
8251 if (flag_code != CODE_64BIT)
8253 types->bitfield.imm32 = 1;
8254 types->bitfield.disp32 = 1;
8257 *types = gotrel[j].types64;
8260 if (j != 0 && GOT_symbol == NULL)
8261 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8263 /* The length of the first part of our input line. */
8264 first = cp - input_line_pointer;
8266 /* The second part goes from after the reloc token until
8267 (and including) an end_of_line char or comma. */
8268 past_reloc = cp + 1 + len;
8270 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8272 second = cp + 1 - past_reloc;
8274 /* Allocate and copy string. The trailing NUL shouldn't
8275 be necessary, but be safe. */
8276 tmpbuf = XNEWVEC (char, first + second + 2);
8277 memcpy (tmpbuf, input_line_pointer, first);
8278 if (second != 0 && *past_reloc != ' ')
8279 /* Replace the relocation token with ' ', so that
8280 errors like foo@GOTOFF1 will be detected. */
8281 tmpbuf[first++] = ' ';
8283 /* Increment length by 1 if the relocation token is
8288 memcpy (tmpbuf + first, past_reloc, second);
8289 tmpbuf[first + second] = '\0';
8293 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8294 gotrel[j].str, 1 << (5 + object_64bit));
8299 /* Might be a symbol version string. Don't as_bad here. */
8308 /* Parse operands of the form
8309 <symbol>@SECREL32+<nnn>
8311 If we find one, set up the correct relocation in RELOC and copy the
8312 input string, minus the `@SECREL32' into a malloc'd buffer for
8313 parsing by the calling routine. Return this buffer, and if ADJUST
8314 is non-null set it to the length of the string we removed from the
8315 input line. Otherwise return NULL.
8317 This function is copied from the ELF version above adjusted for PE targets. */
8320 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8321 int *adjust ATTRIBUTE_UNUSED,
8322 i386_operand_type *types)
8328 const enum bfd_reloc_code_real rel[2];
8329 const i386_operand_type types64;
8333 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8334 BFD_RELOC_32_SECREL },
8335 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8341 for (cp = input_line_pointer; *cp != '@'; cp++)
8342 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8345 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8347 int len = gotrel[j].len;
8349 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8351 if (gotrel[j].rel[object_64bit] != 0)
8354 char *tmpbuf, *past_reloc;
8356 *rel = gotrel[j].rel[object_64bit];
8362 if (flag_code != CODE_64BIT)
8364 types->bitfield.imm32 = 1;
8365 types->bitfield.disp32 = 1;
8368 *types = gotrel[j].types64;
8371 /* The length of the first part of our input line. */
8372 first = cp - input_line_pointer;
8374 /* The second part goes from after the reloc token until
8375 (and including) an end_of_line char or comma. */
8376 past_reloc = cp + 1 + len;
8378 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8380 second = cp + 1 - past_reloc;
8382 /* Allocate and copy string. The trailing NUL shouldn't
8383 be necessary, but be safe. */
8384 tmpbuf = XNEWVEC (char, first + second + 2);
8385 memcpy (tmpbuf, input_line_pointer, first);
8386 if (second != 0 && *past_reloc != ' ')
8387 /* Replace the relocation token with ' ', so that
8388 errors like foo@SECLREL321 will be detected. */
8389 tmpbuf[first++] = ' ';
8390 memcpy (tmpbuf + first, past_reloc, second);
8391 tmpbuf[first + second] = '\0';
8395 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8396 gotrel[j].str, 1 << (5 + object_64bit));
8401 /* Might be a symbol version string. Don't as_bad here. */
8407 bfd_reloc_code_real_type
8408 x86_cons (expressionS *exp, int size)
8410 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8412 intel_syntax = -intel_syntax;
8415 if (size == 4 || (object_64bit && size == 8))
8417 /* Handle @GOTOFF and the like in an expression. */
8419 char *gotfree_input_line;
8422 save = input_line_pointer;
8423 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8424 if (gotfree_input_line)
8425 input_line_pointer = gotfree_input_line;
8429 if (gotfree_input_line)
8431 /* expression () has merrily parsed up to the end of line,
8432 or a comma - in the wrong buffer. Transfer how far
8433 input_line_pointer has moved to the right buffer. */
8434 input_line_pointer = (save
8435 + (input_line_pointer - gotfree_input_line)
8437 free (gotfree_input_line);
8438 if (exp->X_op == O_constant
8439 || exp->X_op == O_absent
8440 || exp->X_op == O_illegal
8441 || exp->X_op == O_register
8442 || exp->X_op == O_big)
8444 char c = *input_line_pointer;
8445 *input_line_pointer = 0;
8446 as_bad (_("missing or invalid expression `%s'"), save);
8447 *input_line_pointer = c;
8454 intel_syntax = -intel_syntax;
8457 i386_intel_simplify (exp);
8463 signed_cons (int size)
8465 if (flag_code == CODE_64BIT)
8473 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8480 if (exp.X_op == O_symbol)
8481 exp.X_op = O_secrel;
8483 emit_expr (&exp, 4);
8485 while (*input_line_pointer++ == ',');
8487 input_line_pointer--;
8488 demand_empty_rest_of_line ();
8492 /* Handle Vector operations. */
8495 check_VecOperations (char *op_string, char *op_end)
8497 const reg_entry *mask;
8502 && (op_end == NULL || op_string < op_end))
8505 if (*op_string == '{')
8509 /* Check broadcasts. */
8510 if (strncmp (op_string, "1to", 3) == 0)
8515 goto duplicated_vec_op;
8518 if (*op_string == '8')
8520 else if (*op_string == '4')
8522 else if (*op_string == '2')
8524 else if (*op_string == '1'
8525 && *(op_string+1) == '6')
8532 as_bad (_("Unsupported broadcast: `%s'"), saved);
8537 broadcast_op.type = bcst_type;
8538 broadcast_op.operand = this_operand;
8539 i.broadcast = &broadcast_op;
8541 /* Check masking operation. */
8542 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8544 /* k0 can't be used for write mask. */
8545 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8547 as_bad (_("`%s%s' can't be used for write mask"),
8548 register_prefix, mask->reg_name);
8554 mask_op.mask = mask;
8555 mask_op.zeroing = 0;
8556 mask_op.operand = this_operand;
8562 goto duplicated_vec_op;
8564 i.mask->mask = mask;
8566 /* Only "{z}" is allowed here. No need to check
8567 zeroing mask explicitly. */
8568 if (i.mask->operand != this_operand)
8570 as_bad (_("invalid write mask `%s'"), saved);
8577 /* Check zeroing-flag for masking operation. */
8578 else if (*op_string == 'z')
8582 mask_op.mask = NULL;
8583 mask_op.zeroing = 1;
8584 mask_op.operand = this_operand;
8589 if (i.mask->zeroing)
8592 as_bad (_("duplicated `%s'"), saved);
8596 i.mask->zeroing = 1;
8598 /* Only "{%k}" is allowed here. No need to check mask
8599 register explicitly. */
8600 if (i.mask->operand != this_operand)
8602 as_bad (_("invalid zeroing-masking `%s'"),
8611 goto unknown_vec_op;
8613 if (*op_string != '}')
8615 as_bad (_("missing `}' in `%s'"), saved);
8620 /* Strip whitespace since the addition of pseudo prefixes
8621 changed how the scrubber treats '{'. */
8622 if (is_space_char (*op_string))
8628 /* We don't know this one. */
8629 as_bad (_("unknown vector operation: `%s'"), saved);
8633 if (i.mask && i.mask->zeroing && !i.mask->mask)
8635 as_bad (_("zeroing-masking only allowed with write mask"));
8643 i386_immediate (char *imm_start)
8645 char *save_input_line_pointer;
8646 char *gotfree_input_line;
8649 i386_operand_type types;
8651 operand_type_set (&types, ~0);
8653 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8655 as_bad (_("at most %d immediate operands are allowed"),
8656 MAX_IMMEDIATE_OPERANDS);
8660 exp = &im_expressions[i.imm_operands++];
8661 i.op[this_operand].imms = exp;
8663 if (is_space_char (*imm_start))
8666 save_input_line_pointer = input_line_pointer;
8667 input_line_pointer = imm_start;
8669 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8670 if (gotfree_input_line)
8671 input_line_pointer = gotfree_input_line;
8673 exp_seg = expression (exp);
8677 /* Handle vector operations. */
8678 if (*input_line_pointer == '{')
8680 input_line_pointer = check_VecOperations (input_line_pointer,
8682 if (input_line_pointer == NULL)
8686 if (*input_line_pointer)
8687 as_bad (_("junk `%s' after expression"), input_line_pointer);
8689 input_line_pointer = save_input_line_pointer;
8690 if (gotfree_input_line)
8692 free (gotfree_input_line);
8694 if (exp->X_op == O_constant || exp->X_op == O_register)
8695 exp->X_op = O_illegal;
8698 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8702 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8703 i386_operand_type types, const char *imm_start)
8705 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8708 as_bad (_("missing or invalid immediate expression `%s'"),
8712 else if (exp->X_op == O_constant)
8714 /* Size it properly later. */
8715 i.types[this_operand].bitfield.imm64 = 1;
8716 /* If not 64bit, sign extend val. */
8717 if (flag_code != CODE_64BIT
8718 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8720 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8722 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8723 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8724 && exp_seg != absolute_section
8725 && exp_seg != text_section
8726 && exp_seg != data_section
8727 && exp_seg != bss_section
8728 && exp_seg != undefined_section
8729 && !bfd_is_com_section (exp_seg))
8731 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8735 else if (!intel_syntax && exp_seg == reg_section)
8738 as_bad (_("illegal immediate register operand %s"), imm_start);
8743 /* This is an address. The size of the address will be
8744 determined later, depending on destination register,
8745 suffix, or the default for the section. */
8746 i.types[this_operand].bitfield.imm8 = 1;
8747 i.types[this_operand].bitfield.imm16 = 1;
8748 i.types[this_operand].bitfield.imm32 = 1;
8749 i.types[this_operand].bitfield.imm32s = 1;
8750 i.types[this_operand].bitfield.imm64 = 1;
8751 i.types[this_operand] = operand_type_and (i.types[this_operand],
8759 i386_scale (char *scale)
8762 char *save = input_line_pointer;
8764 input_line_pointer = scale;
8765 val = get_absolute_expression ();
8770 i.log2_scale_factor = 0;
8773 i.log2_scale_factor = 1;
8776 i.log2_scale_factor = 2;
8779 i.log2_scale_factor = 3;
8783 char sep = *input_line_pointer;
8785 *input_line_pointer = '\0';
8786 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8788 *input_line_pointer = sep;
8789 input_line_pointer = save;
8793 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8795 as_warn (_("scale factor of %d without an index register"),
8796 1 << i.log2_scale_factor);
8797 i.log2_scale_factor = 0;
8799 scale = input_line_pointer;
8800 input_line_pointer = save;
8805 i386_displacement (char *disp_start, char *disp_end)
8809 char *save_input_line_pointer;
8810 char *gotfree_input_line;
8812 i386_operand_type bigdisp, types = anydisp;
8815 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8817 as_bad (_("at most %d displacement operands are allowed"),
8818 MAX_MEMORY_OPERANDS);
8822 operand_type_set (&bigdisp, 0);
8823 if ((i.types[this_operand].bitfield.jumpabsolute)
8824 || (!current_templates->start->opcode_modifier.jump
8825 && !current_templates->start->opcode_modifier.jumpdword))
8827 bigdisp.bitfield.disp32 = 1;
8828 override = (i.prefix[ADDR_PREFIX] != 0);
8829 if (flag_code == CODE_64BIT)
8833 bigdisp.bitfield.disp32s = 1;
8834 bigdisp.bitfield.disp64 = 1;
8837 else if ((flag_code == CODE_16BIT) ^ override)
8839 bigdisp.bitfield.disp32 = 0;
8840 bigdisp.bitfield.disp16 = 1;
8845 /* For PC-relative branches, the width of the displacement
8846 is dependent upon data size, not address size. */
8847 override = (i.prefix[DATA_PREFIX] != 0);
8848 if (flag_code == CODE_64BIT)
8850 if (override || i.suffix == WORD_MNEM_SUFFIX)
8851 bigdisp.bitfield.disp16 = 1;
8854 bigdisp.bitfield.disp32 = 1;
8855 bigdisp.bitfield.disp32s = 1;
8861 override = (i.suffix == (flag_code != CODE_16BIT
8863 : LONG_MNEM_SUFFIX));
8864 bigdisp.bitfield.disp32 = 1;
8865 if ((flag_code == CODE_16BIT) ^ override)
8867 bigdisp.bitfield.disp32 = 0;
8868 bigdisp.bitfield.disp16 = 1;
8872 i.types[this_operand] = operand_type_or (i.types[this_operand],
8875 exp = &disp_expressions[i.disp_operands];
8876 i.op[this_operand].disps = exp;
8878 save_input_line_pointer = input_line_pointer;
8879 input_line_pointer = disp_start;
8880 END_STRING_AND_SAVE (disp_end);
8882 #ifndef GCC_ASM_O_HACK
8883 #define GCC_ASM_O_HACK 0
8886 END_STRING_AND_SAVE (disp_end + 1);
8887 if (i.types[this_operand].bitfield.baseIndex
8888 && displacement_string_end[-1] == '+')
8890 /* This hack is to avoid a warning when using the "o"
8891 constraint within gcc asm statements.
8894 #define _set_tssldt_desc(n,addr,limit,type) \
8895 __asm__ __volatile__ ( \
8897 "movw %w1,2+%0\n\t" \
8899 "movb %b1,4+%0\n\t" \
8900 "movb %4,5+%0\n\t" \
8901 "movb $0,6+%0\n\t" \
8902 "movb %h1,7+%0\n\t" \
8904 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8906 This works great except that the output assembler ends
8907 up looking a bit weird if it turns out that there is
8908 no offset. You end up producing code that looks like:
8921 So here we provide the missing zero. */
8923 *displacement_string_end = '0';
8926 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8927 if (gotfree_input_line)
8928 input_line_pointer = gotfree_input_line;
8930 exp_seg = expression (exp);
8933 if (*input_line_pointer)
8934 as_bad (_("junk `%s' after expression"), input_line_pointer);
8936 RESTORE_END_STRING (disp_end + 1);
8938 input_line_pointer = save_input_line_pointer;
8939 if (gotfree_input_line)
8941 free (gotfree_input_line);
8943 if (exp->X_op == O_constant || exp->X_op == O_register)
8944 exp->X_op = O_illegal;
8947 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8949 RESTORE_END_STRING (disp_end);
8955 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8956 i386_operand_type types, const char *disp_start)
8958 i386_operand_type bigdisp;
8961 /* We do this to make sure that the section symbol is in
8962 the symbol table. We will ultimately change the relocation
8963 to be relative to the beginning of the section. */
8964 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8965 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8966 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8968 if (exp->X_op != O_symbol)
8971 if (S_IS_LOCAL (exp->X_add_symbol)
8972 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8973 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8974 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8975 exp->X_op = O_subtract;
8976 exp->X_op_symbol = GOT_symbol;
8977 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8978 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8979 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8980 i.reloc[this_operand] = BFD_RELOC_64;
8982 i.reloc[this_operand] = BFD_RELOC_32;
8985 else if (exp->X_op == O_absent
8986 || exp->X_op == O_illegal
8987 || exp->X_op == O_big)
8990 as_bad (_("missing or invalid displacement expression `%s'"),
8995 else if (flag_code == CODE_64BIT
8996 && !i.prefix[ADDR_PREFIX]
8997 && exp->X_op == O_constant)
8999 /* Since displacement is signed extended to 64bit, don't allow
9000 disp32 and turn off disp32s if they are out of range. */
9001 i.types[this_operand].bitfield.disp32 = 0;
9002 if (!fits_in_signed_long (exp->X_add_number))
9004 i.types[this_operand].bitfield.disp32s = 0;
9005 if (i.types[this_operand].bitfield.baseindex)
9007 as_bad (_("0x%lx out range of signed 32bit displacement"),
9008 (long) exp->X_add_number);
9014 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9015 else if (exp->X_op != O_constant
9016 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9017 && exp_seg != absolute_section
9018 && exp_seg != text_section
9019 && exp_seg != data_section
9020 && exp_seg != bss_section
9021 && exp_seg != undefined_section
9022 && !bfd_is_com_section (exp_seg))
9024 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9029 /* Check if this is a displacement only operand. */
9030 bigdisp = i.types[this_operand];
9031 bigdisp.bitfield.disp8 = 0;
9032 bigdisp.bitfield.disp16 = 0;
9033 bigdisp.bitfield.disp32 = 0;
9034 bigdisp.bitfield.disp32s = 0;
9035 bigdisp.bitfield.disp64 = 0;
9036 if (operand_type_all_zero (&bigdisp))
9037 i.types[this_operand] = operand_type_and (i.types[this_operand],
9043 /* Return the active addressing mode, taking address override and
9044 registers forming the address into consideration. Update the
9045 address override prefix if necessary. */
9047 static enum flag_code
9048 i386_addressing_mode (void)
9050 enum flag_code addr_mode;
9052 if (i.prefix[ADDR_PREFIX])
9053 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9056 addr_mode = flag_code;
9058 #if INFER_ADDR_PREFIX
9059 if (i.mem_operands == 0)
9061 /* Infer address prefix from the first memory operand. */
9062 const reg_entry *addr_reg = i.base_reg;
9064 if (addr_reg == NULL)
9065 addr_reg = i.index_reg;
9069 if (addr_reg->reg_num == RegEip
9070 || addr_reg->reg_num == RegEiz
9071 || addr_reg->reg_type.bitfield.dword)
9072 addr_mode = CODE_32BIT;
9073 else if (flag_code != CODE_64BIT
9074 && addr_reg->reg_type.bitfield.word)
9075 addr_mode = CODE_16BIT;
9077 if (addr_mode != flag_code)
9079 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9081 /* Change the size of any displacement too. At most one
9082 of Disp16 or Disp32 is set.
9083 FIXME. There doesn't seem to be any real need for
9084 separate Disp16 and Disp32 flags. The same goes for
9085 Imm16 and Imm32. Removing them would probably clean
9086 up the code quite a lot. */
9087 if (flag_code != CODE_64BIT
9088 && (i.types[this_operand].bitfield.disp16
9089 || i.types[this_operand].bitfield.disp32))
9090 i.types[this_operand]
9091 = operand_type_xor (i.types[this_operand], disp16_32);
9101 /* Make sure the memory operand we've been dealt is valid.
9102 Return 1 on success, 0 on a failure. */
9105 i386_index_check (const char *operand_string)
9107 const char *kind = "base/index";
9108 enum flag_code addr_mode = i386_addressing_mode ();
9110 if (current_templates->start->opcode_modifier.isstring
9111 && !current_templates->start->opcode_modifier.immext
9112 && (current_templates->end[-1].opcode_modifier.isstring
9115 /* Memory operands of string insns are special in that they only allow
9116 a single register (rDI, rSI, or rBX) as their memory address. */
9117 const reg_entry *expected_reg;
9118 static const char *di_si[][2] =
9124 static const char *bx[] = { "ebx", "bx", "rbx" };
9126 kind = "string address";
9128 if (current_templates->start->opcode_modifier.repprefixok)
9130 i386_operand_type type = current_templates->end[-1].operand_types[0];
9132 if (!type.bitfield.baseindex
9133 || ((!i.mem_operands != !intel_syntax)
9134 && current_templates->end[-1].operand_types[1]
9135 .bitfield.baseindex))
9136 type = current_templates->end[-1].operand_types[1];
9137 expected_reg = hash_find (reg_hash,
9138 di_si[addr_mode][type.bitfield.esseg]);
9142 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9144 if (i.base_reg != expected_reg
9146 || operand_type_check (i.types[this_operand], disp))
9148 /* The second memory operand must have the same size as
9152 && !((addr_mode == CODE_64BIT
9153 && i.base_reg->reg_type.bitfield.qword)
9154 || (addr_mode == CODE_32BIT
9155 ? i.base_reg->reg_type.bitfield.dword
9156 : i.base_reg->reg_type.bitfield.word)))
9159 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9161 intel_syntax ? '[' : '(',
9163 expected_reg->reg_name,
9164 intel_syntax ? ']' : ')');
9171 as_bad (_("`%s' is not a valid %s expression"),
9172 operand_string, kind);
9177 if (addr_mode != CODE_16BIT)
9179 /* 32-bit/64-bit checks. */
9181 && (addr_mode == CODE_64BIT
9182 ? !i.base_reg->reg_type.bitfield.qword
9183 : !i.base_reg->reg_type.bitfield.dword)
9185 || (i.base_reg->reg_num
9186 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9188 && !i.index_reg->reg_type.bitfield.xmmword
9189 && !i.index_reg->reg_type.bitfield.ymmword
9190 && !i.index_reg->reg_type.bitfield.zmmword
9191 && ((addr_mode == CODE_64BIT
9192 ? !(i.index_reg->reg_type.bitfield.qword
9193 || i.index_reg->reg_num == RegRiz)
9194 : !(i.index_reg->reg_type.bitfield.dword
9195 || i.index_reg->reg_num == RegEiz))
9196 || !i.index_reg->reg_type.bitfield.baseindex)))
9199 /* bndmk, bndldx, and bndstx have special restrictions. */
9200 if (current_templates->start->base_opcode == 0xf30f1b
9201 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9203 /* They cannot use RIP-relative addressing. */
9204 if (i.base_reg && i.base_reg->reg_num == RegRip)
9206 as_bad (_("`%s' cannot be used here"), operand_string);
9210 /* bndldx and bndstx ignore their scale factor. */
9211 if (current_templates->start->base_opcode != 0xf30f1b
9212 && i.log2_scale_factor)
9213 as_warn (_("register scaling is being ignored here"));
9218 /* 16-bit checks. */
9220 && (!i.base_reg->reg_type.bitfield.word
9221 || !i.base_reg->reg_type.bitfield.baseindex))
9223 && (!i.index_reg->reg_type.bitfield.word
9224 || !i.index_reg->reg_type.bitfield.baseindex
9226 && i.base_reg->reg_num < 6
9227 && i.index_reg->reg_num >= 6
9228 && i.log2_scale_factor == 0))))
9235 /* Handle vector immediates. */
9238 RC_SAE_immediate (const char *imm_start)
9240 unsigned int match_found, j;
9241 const char *pstr = imm_start;
9249 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9251 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9255 rc_op.type = RC_NamesTable[j].type;
9256 rc_op.operand = this_operand;
9257 i.rounding = &rc_op;
9261 as_bad (_("duplicated `%s'"), imm_start);
9264 pstr += RC_NamesTable[j].len;
9274 as_bad (_("Missing '}': '%s'"), imm_start);
9277 /* RC/SAE immediate string should contain nothing more. */;
9280 as_bad (_("Junk after '}': '%s'"), imm_start);
9284 exp = &im_expressions[i.imm_operands++];
9285 i.op[this_operand].imms = exp;
9287 exp->X_op = O_constant;
9288 exp->X_add_number = 0;
9289 exp->X_add_symbol = (symbolS *) 0;
9290 exp->X_op_symbol = (symbolS *) 0;
9292 i.types[this_operand].bitfield.imm8 = 1;
9296 /* Only string instructions can have a second memory operand, so
9297 reduce current_templates to just those if it contains any. */
9299 maybe_adjust_templates (void)
9301 const insn_template *t;
9303 gas_assert (i.mem_operands == 1);
9305 for (t = current_templates->start; t < current_templates->end; ++t)
9306 if (t->opcode_modifier.isstring)
9309 if (t < current_templates->end)
9311 static templates aux_templates;
9312 bfd_boolean recheck;
9314 aux_templates.start = t;
9315 for (; t < current_templates->end; ++t)
9316 if (!t->opcode_modifier.isstring)
9318 aux_templates.end = t;
9320 /* Determine whether to re-check the first memory operand. */
9321 recheck = (aux_templates.start != current_templates->start
9322 || t != current_templates->end);
9324 current_templates = &aux_templates;
9329 if (i.memop1_string != NULL
9330 && i386_index_check (i.memop1_string) == 0)
9339 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9343 i386_att_operand (char *operand_string)
9347 char *op_string = operand_string;
9349 if (is_space_char (*op_string))
9352 /* We check for an absolute prefix (differentiating,
9353 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9354 if (*op_string == ABSOLUTE_PREFIX)
9357 if (is_space_char (*op_string))
9359 i.types[this_operand].bitfield.jumpabsolute = 1;
9362 /* Check if operand is a register. */
9363 if ((r = parse_register (op_string, &end_op)) != NULL)
9365 i386_operand_type temp;
9367 /* Check for a segment override by searching for ':' after a
9368 segment register. */
9370 if (is_space_char (*op_string))
9372 if (*op_string == ':'
9373 && (r->reg_type.bitfield.sreg2
9374 || r->reg_type.bitfield.sreg3))
9379 i.seg[i.mem_operands] = &es;
9382 i.seg[i.mem_operands] = &cs;
9385 i.seg[i.mem_operands] = &ss;
9388 i.seg[i.mem_operands] = &ds;
9391 i.seg[i.mem_operands] = &fs;
9394 i.seg[i.mem_operands] = &gs;
9398 /* Skip the ':' and whitespace. */
9400 if (is_space_char (*op_string))
9403 if (!is_digit_char (*op_string)
9404 && !is_identifier_char (*op_string)
9405 && *op_string != '('
9406 && *op_string != ABSOLUTE_PREFIX)
9408 as_bad (_("bad memory operand `%s'"), op_string);
9411 /* Handle case of %es:*foo. */
9412 if (*op_string == ABSOLUTE_PREFIX)
9415 if (is_space_char (*op_string))
9417 i.types[this_operand].bitfield.jumpabsolute = 1;
9419 goto do_memory_reference;
9422 /* Handle vector operations. */
9423 if (*op_string == '{')
9425 op_string = check_VecOperations (op_string, NULL);
9426 if (op_string == NULL)
9432 as_bad (_("junk `%s' after register"), op_string);
9436 temp.bitfield.baseindex = 0;
9437 i.types[this_operand] = operand_type_or (i.types[this_operand],
9439 i.types[this_operand].bitfield.unspecified = 0;
9440 i.op[this_operand].regs = r;
9443 else if (*op_string == REGISTER_PREFIX)
9445 as_bad (_("bad register name `%s'"), op_string);
9448 else if (*op_string == IMMEDIATE_PREFIX)
9451 if (i.types[this_operand].bitfield.jumpabsolute)
9453 as_bad (_("immediate operand illegal with absolute jump"));
9456 if (!i386_immediate (op_string))
9459 else if (RC_SAE_immediate (operand_string))
9461 /* If it is a RC or SAE immediate, do nothing. */
9464 else if (is_digit_char (*op_string)
9465 || is_identifier_char (*op_string)
9466 || *op_string == '"'
9467 || *op_string == '(')
9469 /* This is a memory reference of some sort. */
9472 /* Start and end of displacement string expression (if found). */
9473 char *displacement_string_start;
9474 char *displacement_string_end;
9477 do_memory_reference:
9478 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9480 if ((i.mem_operands == 1
9481 && !current_templates->start->opcode_modifier.isstring)
9482 || i.mem_operands == 2)
9484 as_bad (_("too many memory references for `%s'"),
9485 current_templates->start->name);
9489 /* Check for base index form. We detect the base index form by
9490 looking for an ')' at the end of the operand, searching
9491 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9493 base_string = op_string + strlen (op_string);
9495 /* Handle vector operations. */
9496 vop_start = strchr (op_string, '{');
9497 if (vop_start && vop_start < base_string)
9499 if (check_VecOperations (vop_start, base_string) == NULL)
9501 base_string = vop_start;
9505 if (is_space_char (*base_string))
9508 /* If we only have a displacement, set-up for it to be parsed later. */
9509 displacement_string_start = op_string;
9510 displacement_string_end = base_string + 1;
9512 if (*base_string == ')')
9515 unsigned int parens_balanced = 1;
9516 /* We've already checked that the number of left & right ()'s are
9517 equal, so this loop will not be infinite. */
9521 if (*base_string == ')')
9523 if (*base_string == '(')
9526 while (parens_balanced);
9528 temp_string = base_string;
9530 /* Skip past '(' and whitespace. */
9532 if (is_space_char (*base_string))
9535 if (*base_string == ','
9536 || ((i.base_reg = parse_register (base_string, &end_op))
9539 displacement_string_end = temp_string;
9541 i.types[this_operand].bitfield.baseindex = 1;
9545 base_string = end_op;
9546 if (is_space_char (*base_string))
9550 /* There may be an index reg or scale factor here. */
9551 if (*base_string == ',')
9554 if (is_space_char (*base_string))
9557 if ((i.index_reg = parse_register (base_string, &end_op))
9560 base_string = end_op;
9561 if (is_space_char (*base_string))
9563 if (*base_string == ',')
9566 if (is_space_char (*base_string))
9569 else if (*base_string != ')')
9571 as_bad (_("expecting `,' or `)' "
9572 "after index register in `%s'"),
9577 else if (*base_string == REGISTER_PREFIX)
9579 end_op = strchr (base_string, ',');
9582 as_bad (_("bad register name `%s'"), base_string);
9586 /* Check for scale factor. */
9587 if (*base_string != ')')
9589 char *end_scale = i386_scale (base_string);
9594 base_string = end_scale;
9595 if (is_space_char (*base_string))
9597 if (*base_string != ')')
9599 as_bad (_("expecting `)' "
9600 "after scale factor in `%s'"),
9605 else if (!i.index_reg)
9607 as_bad (_("expecting index register or scale factor "
9608 "after `,'; got '%c'"),
9613 else if (*base_string != ')')
9615 as_bad (_("expecting `,' or `)' "
9616 "after base register in `%s'"),
9621 else if (*base_string == REGISTER_PREFIX)
9623 end_op = strchr (base_string, ',');
9626 as_bad (_("bad register name `%s'"), base_string);
9631 /* If there's an expression beginning the operand, parse it,
9632 assuming displacement_string_start and
9633 displacement_string_end are meaningful. */
9634 if (displacement_string_start != displacement_string_end)
9636 if (!i386_displacement (displacement_string_start,
9637 displacement_string_end))
9641 /* Special case for (%dx) while doing input/output op. */
9643 && i.base_reg->reg_type.bitfield.inoutportreg
9645 && i.log2_scale_factor == 0
9646 && i.seg[i.mem_operands] == 0
9647 && !operand_type_check (i.types[this_operand], disp))
9649 i.types[this_operand] = i.base_reg->reg_type;
9653 if (i386_index_check (operand_string) == 0)
9655 i.types[this_operand].bitfield.mem = 1;
9656 if (i.mem_operands == 0)
9657 i.memop1_string = xstrdup (operand_string);
9662 /* It's not a memory operand; argh! */
9663 as_bad (_("invalid char %s beginning operand %d `%s'"),
9664 output_invalid (*op_string),
9669 return 1; /* Normal return. */
9672 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9673 that an rs_machine_dependent frag may reach. */
9676 i386_frag_max_var (fragS *frag)
9678 /* The only relaxable frags are for jumps.
9679 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9680 gas_assert (frag->fr_type == rs_machine_dependent);
9681 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9686 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9688 /* STT_GNU_IFUNC symbol must go through PLT. */
9689 if ((symbol_get_bfdsym (fr_symbol)->flags
9690 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9693 if (!S_IS_EXTERNAL (fr_symbol))
9694 /* Symbol may be weak or local. */
9695 return !S_IS_WEAK (fr_symbol);
9697 /* Global symbols with non-default visibility can't be preempted. */
9698 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9701 if (fr_var != NO_RELOC)
9702 switch ((enum bfd_reloc_code_real) fr_var)
9704 case BFD_RELOC_386_PLT32:
9705 case BFD_RELOC_X86_64_PLT32:
9706 /* Symbol with PLT relocation may be preempted. */
9712 /* Global symbols with default visibility in a shared library may be
9713 preempted by another definition. */
9718 /* md_estimate_size_before_relax()
9720 Called just before relax() for rs_machine_dependent frags. The x86
9721 assembler uses these frags to handle variable size jump
9724 Any symbol that is now undefined will not become defined.
9725 Return the correct fr_subtype in the frag.
9726 Return the initial "guess for variable size of frag" to caller.
9727 The guess is actually the growth beyond the fixed part. Whatever
9728 we do to grow the fixed or variable part contributes to our
9732 md_estimate_size_before_relax (fragS *fragP, segT segment)
9734 /* We've already got fragP->fr_subtype right; all we have to do is
9735 check for un-relaxable symbols. On an ELF system, we can't relax
9736 an externally visible symbol, because it may be overridden by a
9738 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9741 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9744 #if defined (OBJ_COFF) && defined (TE_PE)
9745 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9746 && S_IS_WEAK (fragP->fr_symbol))
9750 /* Symbol is undefined in this segment, or we need to keep a
9751 reloc so that weak symbols can be overridden. */
9752 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9753 enum bfd_reloc_code_real reloc_type;
9754 unsigned char *opcode;
9757 if (fragP->fr_var != NO_RELOC)
9758 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9760 reloc_type = BFD_RELOC_16_PCREL;
9761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9762 else if (need_plt32_p (fragP->fr_symbol))
9763 reloc_type = BFD_RELOC_X86_64_PLT32;
9766 reloc_type = BFD_RELOC_32_PCREL;
9768 old_fr_fix = fragP->fr_fix;
9769 opcode = (unsigned char *) fragP->fr_opcode;
9771 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9774 /* Make jmp (0xeb) a (d)word displacement jump. */
9776 fragP->fr_fix += size;
9777 fix_new (fragP, old_fr_fix, size,
9779 fragP->fr_offset, 1,
9785 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9787 /* Negate the condition, and branch past an
9788 unconditional jump. */
9791 /* Insert an unconditional jump. */
9793 /* We added two extra opcode bytes, and have a two byte
9795 fragP->fr_fix += 2 + 2;
9796 fix_new (fragP, old_fr_fix + 2, 2,
9798 fragP->fr_offset, 1,
9805 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9810 fixP = fix_new (fragP, old_fr_fix, 1,
9812 fragP->fr_offset, 1,
9814 fixP->fx_signed = 1;
9818 /* This changes the byte-displacement jump 0x7N
9819 to the (d)word-displacement jump 0x0f,0x8N. */
9820 opcode[1] = opcode[0] + 0x10;
9821 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9822 /* We've added an opcode byte. */
9823 fragP->fr_fix += 1 + size;
9824 fix_new (fragP, old_fr_fix + 1, size,
9826 fragP->fr_offset, 1,
9831 BAD_CASE (fragP->fr_subtype);
9835 return fragP->fr_fix - old_fr_fix;
9838 /* Guess size depending on current relax state. Initially the relax
9839 state will correspond to a short jump and we return 1, because
9840 the variable part of the frag (the branch offset) is one byte
9841 long. However, we can relax a section more than once and in that
9842 case we must either set fr_subtype back to the unrelaxed state,
9843 or return the value for the appropriate branch. */
9844 return md_relax_table[fragP->fr_subtype].rlx_length;
9847 /* Called after relax() is finished.
9849 In: Address of frag.
9850 fr_type == rs_machine_dependent.
9851 fr_subtype is what the address relaxed to.
9853 Out: Any fixSs and constants are set up.
9854 Caller will turn frag into a ".space 0". */
9857 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9860 unsigned char *opcode;
9861 unsigned char *where_to_put_displacement = NULL;
9862 offsetT target_address;
9863 offsetT opcode_address;
9864 unsigned int extension = 0;
9865 offsetT displacement_from_opcode_start;
9867 opcode = (unsigned char *) fragP->fr_opcode;
9869 /* Address we want to reach in file space. */
9870 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9872 /* Address opcode resides at in file space. */
9873 opcode_address = fragP->fr_address + fragP->fr_fix;
9875 /* Displacement from opcode start to fill into instruction. */
9876 displacement_from_opcode_start = target_address - opcode_address;
9878 if ((fragP->fr_subtype & BIG) == 0)
9880 /* Don't have to change opcode. */
9881 extension = 1; /* 1 opcode + 1 displacement */
9882 where_to_put_displacement = &opcode[1];
9886 if (no_cond_jump_promotion
9887 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9888 as_warn_where (fragP->fr_file, fragP->fr_line,
9889 _("long jump required"));
9891 switch (fragP->fr_subtype)
9893 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9894 extension = 4; /* 1 opcode + 4 displacement */
9896 where_to_put_displacement = &opcode[1];
9899 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9900 extension = 2; /* 1 opcode + 2 displacement */
9902 where_to_put_displacement = &opcode[1];
9905 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9906 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9907 extension = 5; /* 2 opcode + 4 displacement */
9908 opcode[1] = opcode[0] + 0x10;
9909 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9910 where_to_put_displacement = &opcode[2];
9913 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9914 extension = 3; /* 2 opcode + 2 displacement */
9915 opcode[1] = opcode[0] + 0x10;
9916 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9917 where_to_put_displacement = &opcode[2];
9920 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9925 where_to_put_displacement = &opcode[3];
9929 BAD_CASE (fragP->fr_subtype);
9934 /* If size if less then four we are sure that the operand fits,
9935 but if it's 4, then it could be that the displacement is larger
9937 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9939 && ((addressT) (displacement_from_opcode_start - extension
9940 + ((addressT) 1 << 31))
9941 > (((addressT) 2 << 31) - 1)))
9943 as_bad_where (fragP->fr_file, fragP->fr_line,
9944 _("jump target out of range"));
9945 /* Make us emit 0. */
9946 displacement_from_opcode_start = extension;
9948 /* Now put displacement after opcode. */
9949 md_number_to_chars ((char *) where_to_put_displacement,
9950 (valueT) (displacement_from_opcode_start - extension),
9951 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9952 fragP->fr_fix += extension;
9955 /* Apply a fixup (fixP) to segment data, once it has been determined
9956 by our caller that we have all the info we need to fix it up.
9958 Parameter valP is the pointer to the value of the bits.
9960 On the 386, immediates, displacements, and data pointers are all in
9961 the same (little-endian) format, so we don't need to care about which
9965 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9967 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9968 valueT value = *valP;
9970 #if !defined (TE_Mach)
9973 switch (fixP->fx_r_type)
9979 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9982 case BFD_RELOC_X86_64_32S:
9983 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9986 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9989 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9994 if (fixP->fx_addsy != NULL
9995 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9996 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9997 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9998 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9999 && !use_rela_relocations)
10001 /* This is a hack. There should be a better way to handle this.
10002 This covers for the fact that bfd_install_relocation will
10003 subtract the current location (for partial_inplace, PC relative
10004 relocations); see more below. */
10008 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10011 value += fixP->fx_where + fixP->fx_frag->fr_address;
10013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10016 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10018 if ((sym_seg == seg
10019 || (symbol_section_p (fixP->fx_addsy)
10020 && sym_seg != absolute_section))
10021 && !generic_force_reloc (fixP))
10023 /* Yes, we add the values in twice. This is because
10024 bfd_install_relocation subtracts them out again. I think
10025 bfd_install_relocation is broken, but I don't dare change
10027 value += fixP->fx_where + fixP->fx_frag->fr_address;
10031 #if defined (OBJ_COFF) && defined (TE_PE)
10032 /* For some reason, the PE format does not store a
10033 section address offset for a PC relative symbol. */
10034 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10035 || S_IS_WEAK (fixP->fx_addsy))
10036 value += md_pcrel_from (fixP);
10039 #if defined (OBJ_COFF) && defined (TE_PE)
10040 if (fixP->fx_addsy != NULL
10041 && S_IS_WEAK (fixP->fx_addsy)
10042 /* PR 16858: Do not modify weak function references. */
10043 && ! fixP->fx_pcrel)
10045 #if !defined (TE_PEP)
10046 /* For x86 PE weak function symbols are neither PC-relative
10047 nor do they set S_IS_FUNCTION. So the only reliable way
10048 to detect them is to check the flags of their containing
10050 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10051 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10055 value -= S_GET_VALUE (fixP->fx_addsy);
10059 /* Fix a few things - the dynamic linker expects certain values here,
10060 and we must not disappoint it. */
10061 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10062 if (IS_ELF && fixP->fx_addsy)
10063 switch (fixP->fx_r_type)
10065 case BFD_RELOC_386_PLT32:
10066 case BFD_RELOC_X86_64_PLT32:
10067 /* Make the jump instruction point to the address of the operand. At
10068 runtime we merely add the offset to the actual PLT entry. */
10072 case BFD_RELOC_386_TLS_GD:
10073 case BFD_RELOC_386_TLS_LDM:
10074 case BFD_RELOC_386_TLS_IE_32:
10075 case BFD_RELOC_386_TLS_IE:
10076 case BFD_RELOC_386_TLS_GOTIE:
10077 case BFD_RELOC_386_TLS_GOTDESC:
10078 case BFD_RELOC_X86_64_TLSGD:
10079 case BFD_RELOC_X86_64_TLSLD:
10080 case BFD_RELOC_X86_64_GOTTPOFF:
10081 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10082 value = 0; /* Fully resolved at runtime. No addend. */
10084 case BFD_RELOC_386_TLS_LE:
10085 case BFD_RELOC_386_TLS_LDO_32:
10086 case BFD_RELOC_386_TLS_LE_32:
10087 case BFD_RELOC_X86_64_DTPOFF32:
10088 case BFD_RELOC_X86_64_DTPOFF64:
10089 case BFD_RELOC_X86_64_TPOFF32:
10090 case BFD_RELOC_X86_64_TPOFF64:
10091 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10094 case BFD_RELOC_386_TLS_DESC_CALL:
10095 case BFD_RELOC_X86_64_TLSDESC_CALL:
10096 value = 0; /* Fully resolved at runtime. No addend. */
10097 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10101 case BFD_RELOC_VTABLE_INHERIT:
10102 case BFD_RELOC_VTABLE_ENTRY:
10109 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10111 #endif /* !defined (TE_Mach) */
10113 /* Are we finished with this relocation now? */
10114 if (fixP->fx_addsy == NULL)
10116 #if defined (OBJ_COFF) && defined (TE_PE)
10117 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10120 /* Remember value for tc_gen_reloc. */
10121 fixP->fx_addnumber = value;
10122 /* Clear out the frag for now. */
10126 else if (use_rela_relocations)
10128 fixP->fx_no_overflow = 1;
10129 /* Remember value for tc_gen_reloc. */
10130 fixP->fx_addnumber = value;
10134 md_number_to_chars (p, value, fixP->fx_size);
10138 md_atof (int type, char *litP, int *sizeP)
10140 /* This outputs the LITTLENUMs in REVERSE order;
10141 in accord with the bigendian 386. */
10142 return ieee_md_atof (type, litP, sizeP, FALSE);
10145 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10148 output_invalid (int c)
10151 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10154 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10155 "(0x%x)", (unsigned char) c);
10156 return output_invalid_buf;
10159 /* REG_STRING starts *before* REGISTER_PREFIX. */
10161 static const reg_entry *
10162 parse_real_register (char *reg_string, char **end_op)
10164 char *s = reg_string;
10166 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10167 const reg_entry *r;
10169 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10170 if (*s == REGISTER_PREFIX)
10173 if (is_space_char (*s))
10176 p = reg_name_given;
10177 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10179 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10180 return (const reg_entry *) NULL;
10184 /* For naked regs, make sure that we are not dealing with an identifier.
10185 This prevents confusing an identifier like `eax_var' with register
10187 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10188 return (const reg_entry *) NULL;
10192 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10194 /* Handle floating point regs, allowing spaces in the (i) part. */
10195 if (r == i386_regtab /* %st is first entry of table */)
10197 if (!cpu_arch_flags.bitfield.cpu8087
10198 && !cpu_arch_flags.bitfield.cpu287
10199 && !cpu_arch_flags.bitfield.cpu387)
10200 return (const reg_entry *) NULL;
10202 if (is_space_char (*s))
10207 if (is_space_char (*s))
10209 if (*s >= '0' && *s <= '7')
10211 int fpr = *s - '0';
10213 if (is_space_char (*s))
10218 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10223 /* We have "%st(" then garbage. */
10224 return (const reg_entry *) NULL;
10228 if (r == NULL || allow_pseudo_reg)
10231 if (operand_type_all_zero (&r->reg_type))
10232 return (const reg_entry *) NULL;
10234 if ((r->reg_type.bitfield.dword
10235 || r->reg_type.bitfield.sreg3
10236 || r->reg_type.bitfield.control
10237 || r->reg_type.bitfield.debug
10238 || r->reg_type.bitfield.test)
10239 && !cpu_arch_flags.bitfield.cpui386)
10240 return (const reg_entry *) NULL;
10242 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10243 return (const reg_entry *) NULL;
10245 if (!cpu_arch_flags.bitfield.cpuavx512f)
10247 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10248 return (const reg_entry *) NULL;
10250 if (!cpu_arch_flags.bitfield.cpuavx)
10252 if (r->reg_type.bitfield.ymmword)
10253 return (const reg_entry *) NULL;
10255 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10256 return (const reg_entry *) NULL;
10260 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10261 return (const reg_entry *) NULL;
10263 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10264 if (!allow_index_reg
10265 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10266 return (const reg_entry *) NULL;
10268 /* Upper 16 vector registers are only available with VREX in 64bit
10269 mode, and require EVEX encoding. */
10270 if (r->reg_flags & RegVRex)
10272 if (!cpu_arch_flags.bitfield.cpuvrex
10273 || flag_code != CODE_64BIT)
10274 return (const reg_entry *) NULL;
10276 i.vec_encoding = vex_encoding_evex;
10279 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10280 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10281 && flag_code != CODE_64BIT)
10282 return (const reg_entry *) NULL;
10284 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10285 return (const reg_entry *) NULL;
10290 /* REG_STRING starts *before* REGISTER_PREFIX. */
10292 static const reg_entry *
10293 parse_register (char *reg_string, char **end_op)
10295 const reg_entry *r;
10297 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10298 r = parse_real_register (reg_string, end_op);
10303 char *save = input_line_pointer;
10307 input_line_pointer = reg_string;
10308 c = get_symbol_name (®_string);
10309 symbolP = symbol_find (reg_string);
10310 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10312 const expressionS *e = symbol_get_value_expression (symbolP);
10314 know (e->X_op == O_register);
10315 know (e->X_add_number >= 0
10316 && (valueT) e->X_add_number < i386_regtab_size);
10317 r = i386_regtab + e->X_add_number;
10318 if ((r->reg_flags & RegVRex))
10319 i.vec_encoding = vex_encoding_evex;
10320 *end_op = input_line_pointer;
10322 *input_line_pointer = c;
10323 input_line_pointer = save;
10329 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10331 const reg_entry *r;
10332 char *end = input_line_pointer;
10335 r = parse_register (name, &input_line_pointer);
10336 if (r && end <= input_line_pointer)
10338 *nextcharP = *input_line_pointer;
10339 *input_line_pointer = 0;
10340 e->X_op = O_register;
10341 e->X_add_number = r - i386_regtab;
10344 input_line_pointer = end;
10346 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10350 md_operand (expressionS *e)
10353 const reg_entry *r;
10355 switch (*input_line_pointer)
10357 case REGISTER_PREFIX:
10358 r = parse_real_register (input_line_pointer, &end);
10361 e->X_op = O_register;
10362 e->X_add_number = r - i386_regtab;
10363 input_line_pointer = end;
10368 gas_assert (intel_syntax);
10369 end = input_line_pointer++;
10371 if (*input_line_pointer == ']')
10373 ++input_line_pointer;
10374 e->X_op_symbol = make_expr_symbol (e);
10375 e->X_add_symbol = NULL;
10376 e->X_add_number = 0;
10381 e->X_op = O_absent;
10382 input_line_pointer = end;
10389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10390 const char *md_shortopts = "kVQ:sqnO::";
10392 const char *md_shortopts = "qnO::";
10395 #define OPTION_32 (OPTION_MD_BASE + 0)
10396 #define OPTION_64 (OPTION_MD_BASE + 1)
10397 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10398 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10399 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10400 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10401 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10402 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10403 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10404 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10405 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10406 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10407 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10408 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10409 #define OPTION_X32 (OPTION_MD_BASE + 14)
10410 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10411 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10412 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10413 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10414 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10415 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10416 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10417 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10418 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10419 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10421 struct option md_longopts[] =
10423 {"32", no_argument, NULL, OPTION_32},
10424 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10425 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10426 {"64", no_argument, NULL, OPTION_64},
10428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10429 {"x32", no_argument, NULL, OPTION_X32},
10430 {"mshared", no_argument, NULL, OPTION_MSHARED},
10432 {"divide", no_argument, NULL, OPTION_DIVIDE},
10433 {"march", required_argument, NULL, OPTION_MARCH},
10434 {"mtune", required_argument, NULL, OPTION_MTUNE},
10435 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10436 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10437 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10438 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10439 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10440 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10441 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10442 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10443 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10444 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10445 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10446 # if defined (TE_PE) || defined (TE_PEP)
10447 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10449 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10450 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10451 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10452 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10453 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10454 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10455 {NULL, no_argument, NULL, 0}
10457 size_t md_longopts_size = sizeof (md_longopts);
10460 md_parse_option (int c, const char *arg)
10463 char *arch, *next, *saved;
10468 optimize_align_code = 0;
10472 quiet_warnings = 1;
10475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10476 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10477 should be emitted or not. FIXME: Not implemented. */
10481 /* -V: SVR4 argument to print version ID. */
10483 print_version_id ();
10486 /* -k: Ignore for FreeBSD compatibility. */
10491 /* -s: On i386 Solaris, this tells the native assembler to use
10492 .stab instead of .stab.excl. We always use .stab anyhow. */
10495 case OPTION_MSHARED:
10499 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10500 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10503 const char **list, **l;
10505 list = bfd_target_list ();
10506 for (l = list; *l != NULL; l++)
10507 if (CONST_STRNEQ (*l, "elf64-x86-64")
10508 || strcmp (*l, "coff-x86-64") == 0
10509 || strcmp (*l, "pe-x86-64") == 0
10510 || strcmp (*l, "pei-x86-64") == 0
10511 || strcmp (*l, "mach-o-x86-64") == 0)
10513 default_arch = "x86_64";
10517 as_fatal (_("no compiled in support for x86_64"));
10523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10527 const char **list, **l;
10529 list = bfd_target_list ();
10530 for (l = list; *l != NULL; l++)
10531 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10533 default_arch = "x86_64:32";
10537 as_fatal (_("no compiled in support for 32bit x86_64"));
10541 as_fatal (_("32bit x86_64 is only supported for ELF"));
10546 default_arch = "i386";
10549 case OPTION_DIVIDE:
10550 #ifdef SVR4_COMMENT_CHARS
10555 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10557 for (s = i386_comment_chars; *s != '\0'; s++)
10561 i386_comment_chars = n;
10567 saved = xstrdup (arg);
10569 /* Allow -march=+nosse. */
10575 as_fatal (_("invalid -march= option: `%s'"), arg);
10576 next = strchr (arch, '+');
10579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10581 if (strcmp (arch, cpu_arch [j].name) == 0)
10584 if (! cpu_arch[j].flags.bitfield.cpui386)
10587 cpu_arch_name = cpu_arch[j].name;
10588 cpu_sub_arch_name = NULL;
10589 cpu_arch_flags = cpu_arch[j].flags;
10590 cpu_arch_isa = cpu_arch[j].type;
10591 cpu_arch_isa_flags = cpu_arch[j].flags;
10592 if (!cpu_arch_tune_set)
10594 cpu_arch_tune = cpu_arch_isa;
10595 cpu_arch_tune_flags = cpu_arch_isa_flags;
10599 else if (*cpu_arch [j].name == '.'
10600 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10602 /* ISA extension. */
10603 i386_cpu_flags flags;
10605 flags = cpu_flags_or (cpu_arch_flags,
10606 cpu_arch[j].flags);
10608 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10610 if (cpu_sub_arch_name)
10612 char *name = cpu_sub_arch_name;
10613 cpu_sub_arch_name = concat (name,
10615 (const char *) NULL);
10619 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10620 cpu_arch_flags = flags;
10621 cpu_arch_isa_flags = flags;
10625 = cpu_flags_or (cpu_arch_isa_flags,
10626 cpu_arch[j].flags);
10631 if (j >= ARRAY_SIZE (cpu_arch))
10633 /* Disable an ISA extension. */
10634 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10635 if (strcmp (arch, cpu_noarch [j].name) == 0)
10637 i386_cpu_flags flags;
10639 flags = cpu_flags_and_not (cpu_arch_flags,
10640 cpu_noarch[j].flags);
10641 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10643 if (cpu_sub_arch_name)
10645 char *name = cpu_sub_arch_name;
10646 cpu_sub_arch_name = concat (arch,
10647 (const char *) NULL);
10651 cpu_sub_arch_name = xstrdup (arch);
10652 cpu_arch_flags = flags;
10653 cpu_arch_isa_flags = flags;
10658 if (j >= ARRAY_SIZE (cpu_noarch))
10659 j = ARRAY_SIZE (cpu_arch);
10662 if (j >= ARRAY_SIZE (cpu_arch))
10663 as_fatal (_("invalid -march= option: `%s'"), arg);
10667 while (next != NULL);
10673 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10674 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10676 if (strcmp (arg, cpu_arch [j].name) == 0)
10678 cpu_arch_tune_set = 1;
10679 cpu_arch_tune = cpu_arch [j].type;
10680 cpu_arch_tune_flags = cpu_arch[j].flags;
10684 if (j >= ARRAY_SIZE (cpu_arch))
10685 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10688 case OPTION_MMNEMONIC:
10689 if (strcasecmp (arg, "att") == 0)
10690 intel_mnemonic = 0;
10691 else if (strcasecmp (arg, "intel") == 0)
10692 intel_mnemonic = 1;
10694 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10697 case OPTION_MSYNTAX:
10698 if (strcasecmp (arg, "att") == 0)
10700 else if (strcasecmp (arg, "intel") == 0)
10703 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10706 case OPTION_MINDEX_REG:
10707 allow_index_reg = 1;
10710 case OPTION_MNAKED_REG:
10711 allow_naked_reg = 1;
10714 case OPTION_MSSE2AVX:
10718 case OPTION_MSSE_CHECK:
10719 if (strcasecmp (arg, "error") == 0)
10720 sse_check = check_error;
10721 else if (strcasecmp (arg, "warning") == 0)
10722 sse_check = check_warning;
10723 else if (strcasecmp (arg, "none") == 0)
10724 sse_check = check_none;
10726 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10729 case OPTION_MOPERAND_CHECK:
10730 if (strcasecmp (arg, "error") == 0)
10731 operand_check = check_error;
10732 else if (strcasecmp (arg, "warning") == 0)
10733 operand_check = check_warning;
10734 else if (strcasecmp (arg, "none") == 0)
10735 operand_check = check_none;
10737 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10740 case OPTION_MAVXSCALAR:
10741 if (strcasecmp (arg, "128") == 0)
10742 avxscalar = vex128;
10743 else if (strcasecmp (arg, "256") == 0)
10744 avxscalar = vex256;
10746 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10749 case OPTION_MADD_BND_PREFIX:
10750 add_bnd_prefix = 1;
10753 case OPTION_MEVEXLIG:
10754 if (strcmp (arg, "128") == 0)
10755 evexlig = evexl128;
10756 else if (strcmp (arg, "256") == 0)
10757 evexlig = evexl256;
10758 else if (strcmp (arg, "512") == 0)
10759 evexlig = evexl512;
10761 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10764 case OPTION_MEVEXRCIG:
10765 if (strcmp (arg, "rne") == 0)
10767 else if (strcmp (arg, "rd") == 0)
10769 else if (strcmp (arg, "ru") == 0)
10771 else if (strcmp (arg, "rz") == 0)
10774 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10777 case OPTION_MEVEXWIG:
10778 if (strcmp (arg, "0") == 0)
10780 else if (strcmp (arg, "1") == 0)
10783 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10786 # if defined (TE_PE) || defined (TE_PEP)
10787 case OPTION_MBIG_OBJ:
10792 case OPTION_MOMIT_LOCK_PREFIX:
10793 if (strcasecmp (arg, "yes") == 0)
10794 omit_lock_prefix = 1;
10795 else if (strcasecmp (arg, "no") == 0)
10796 omit_lock_prefix = 0;
10798 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10801 case OPTION_MFENCE_AS_LOCK_ADD:
10802 if (strcasecmp (arg, "yes") == 0)
10804 else if (strcasecmp (arg, "no") == 0)
10807 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10810 case OPTION_MRELAX_RELOCATIONS:
10811 if (strcasecmp (arg, "yes") == 0)
10812 generate_relax_relocations = 1;
10813 else if (strcasecmp (arg, "no") == 0)
10814 generate_relax_relocations = 0;
10816 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10819 case OPTION_MAMD64:
10823 case OPTION_MINTEL64:
10831 /* Turn off -Os. */
10832 optimize_for_space = 0;
10834 else if (*arg == 's')
10836 optimize_for_space = 1;
10837 /* Turn on all encoding optimizations. */
10842 optimize = atoi (arg);
10843 /* Turn off -Os. */
10844 optimize_for_space = 0;
10854 #define MESSAGE_TEMPLATE \
10858 output_message (FILE *stream, char *p, char *message, char *start,
10859 int *left_p, const char *name, int len)
10861 int size = sizeof (MESSAGE_TEMPLATE);
10862 int left = *left_p;
10864 /* Reserve 2 spaces for ", " or ",\0" */
10867 /* Check if there is any room. */
10875 p = mempcpy (p, name, len);
10879 /* Output the current message now and start a new one. */
10882 fprintf (stream, "%s\n", message);
10884 left = size - (start - message) - len - 2;
10886 gas_assert (left >= 0);
10888 p = mempcpy (p, name, len);
10896 show_arch (FILE *stream, int ext, int check)
10898 static char message[] = MESSAGE_TEMPLATE;
10899 char *start = message + 27;
10901 int size = sizeof (MESSAGE_TEMPLATE);
10908 left = size - (start - message);
10909 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10911 /* Should it be skipped? */
10912 if (cpu_arch [j].skip)
10915 name = cpu_arch [j].name;
10916 len = cpu_arch [j].len;
10919 /* It is an extension. Skip if we aren't asked to show it. */
10930 /* It is an processor. Skip if we show only extension. */
10933 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10935 /* It is an impossible processor - skip. */
10939 p = output_message (stream, p, message, start, &left, name, len);
10942 /* Display disabled extensions. */
10944 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10946 name = cpu_noarch [j].name;
10947 len = cpu_noarch [j].len;
10948 p = output_message (stream, p, message, start, &left, name,
10953 fprintf (stream, "%s\n", message);
10957 md_show_usage (FILE *stream)
10959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10960 fprintf (stream, _("\
10962 -V print assembler version number\n\
10965 fprintf (stream, _("\
10966 -n Do not optimize code alignment\n\
10967 -q quieten some warnings\n"));
10968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10969 fprintf (stream, _("\
10972 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10973 || defined (TE_PE) || defined (TE_PEP))
10974 fprintf (stream, _("\
10975 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10977 #ifdef SVR4_COMMENT_CHARS
10978 fprintf (stream, _("\
10979 --divide do not treat `/' as a comment character\n"));
10981 fprintf (stream, _("\
10982 --divide ignored\n"));
10984 fprintf (stream, _("\
10985 -march=CPU[,+EXTENSION...]\n\
10986 generate code for CPU and EXTENSION, CPU is one of:\n"));
10987 show_arch (stream, 0, 1);
10988 fprintf (stream, _("\
10989 EXTENSION is combination of:\n"));
10990 show_arch (stream, 1, 0);
10991 fprintf (stream, _("\
10992 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10993 show_arch (stream, 0, 0);
10994 fprintf (stream, _("\
10995 -msse2avx encode SSE instructions with VEX prefix\n"));
10996 fprintf (stream, _("\
10997 -msse-check=[none|error|warning]\n\
10998 check SSE instructions\n"));
10999 fprintf (stream, _("\
11000 -moperand-check=[none|error|warning]\n\
11001 check operand combinations for validity\n"));
11002 fprintf (stream, _("\
11003 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11005 fprintf (stream, _("\
11006 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11008 fprintf (stream, _("\
11009 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11010 for EVEX.W bit ignored instructions\n"));
11011 fprintf (stream, _("\
11012 -mevexrcig=[rne|rd|ru|rz]\n\
11013 encode EVEX instructions with specific EVEX.RC value\n\
11014 for SAE-only ignored instructions\n"));
11015 fprintf (stream, _("\
11016 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11017 fprintf (stream, _("\
11018 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11019 fprintf (stream, _("\
11020 -mindex-reg support pseudo index registers\n"));
11021 fprintf (stream, _("\
11022 -mnaked-reg don't require `%%' prefix for registers\n"));
11023 fprintf (stream, _("\
11024 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11025 fprintf (stream, _("\
11026 -mshared disable branch optimization for shared code\n"));
11027 # if defined (TE_PE) || defined (TE_PEP)
11028 fprintf (stream, _("\
11029 -mbig-obj generate big object files\n"));
11031 fprintf (stream, _("\
11032 -momit-lock-prefix=[no|yes]\n\
11033 strip all lock prefixes\n"));
11034 fprintf (stream, _("\
11035 -mfence-as-lock-add=[no|yes]\n\
11036 encode lfence, mfence and sfence as\n\
11037 lock addl $0x0, (%%{re}sp)\n"));
11038 fprintf (stream, _("\
11039 -mrelax-relocations=[no|yes]\n\
11040 generate relax relocations\n"));
11041 fprintf (stream, _("\
11042 -mamd64 accept only AMD64 ISA\n"));
11043 fprintf (stream, _("\
11044 -mintel64 accept only Intel64 ISA\n"));
11047 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11048 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11049 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11051 /* Pick the target format to use. */
11054 i386_target_format (void)
11056 if (!strncmp (default_arch, "x86_64", 6))
11058 update_code_flag (CODE_64BIT, 1);
11059 if (default_arch[6] == '\0')
11060 x86_elf_abi = X86_64_ABI;
11062 x86_elf_abi = X86_64_X32_ABI;
11064 else if (!strcmp (default_arch, "i386"))
11065 update_code_flag (CODE_32BIT, 1);
11066 else if (!strcmp (default_arch, "iamcu"))
11068 update_code_flag (CODE_32BIT, 1);
11069 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11071 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11072 cpu_arch_name = "iamcu";
11073 cpu_sub_arch_name = NULL;
11074 cpu_arch_flags = iamcu_flags;
11075 cpu_arch_isa = PROCESSOR_IAMCU;
11076 cpu_arch_isa_flags = iamcu_flags;
11077 if (!cpu_arch_tune_set)
11079 cpu_arch_tune = cpu_arch_isa;
11080 cpu_arch_tune_flags = cpu_arch_isa_flags;
11083 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11084 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11088 as_fatal (_("unknown architecture"));
11090 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11091 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11092 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11093 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11095 switch (OUTPUT_FLAVOR)
11097 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11098 case bfd_target_aout_flavour:
11099 return AOUT_TARGET_FORMAT;
11101 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11102 # if defined (TE_PE) || defined (TE_PEP)
11103 case bfd_target_coff_flavour:
11104 if (flag_code == CODE_64BIT)
11105 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11108 # elif defined (TE_GO32)
11109 case bfd_target_coff_flavour:
11110 return "coff-go32";
11112 case bfd_target_coff_flavour:
11113 return "coff-i386";
11116 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11117 case bfd_target_elf_flavour:
11119 const char *format;
11121 switch (x86_elf_abi)
11124 format = ELF_TARGET_FORMAT;
11127 use_rela_relocations = 1;
11129 format = ELF_TARGET_FORMAT64;
11131 case X86_64_X32_ABI:
11132 use_rela_relocations = 1;
11134 disallow_64bit_reloc = 1;
11135 format = ELF_TARGET_FORMAT32;
11138 if (cpu_arch_isa == PROCESSOR_L1OM)
11140 if (x86_elf_abi != X86_64_ABI)
11141 as_fatal (_("Intel L1OM is 64bit only"));
11142 return ELF_TARGET_L1OM_FORMAT;
11144 else if (cpu_arch_isa == PROCESSOR_K1OM)
11146 if (x86_elf_abi != X86_64_ABI)
11147 as_fatal (_("Intel K1OM is 64bit only"));
11148 return ELF_TARGET_K1OM_FORMAT;
11150 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11152 if (x86_elf_abi != I386_ABI)
11153 as_fatal (_("Intel MCU is 32bit only"));
11154 return ELF_TARGET_IAMCU_FORMAT;
11160 #if defined (OBJ_MACH_O)
11161 case bfd_target_mach_o_flavour:
11162 if (flag_code == CODE_64BIT)
11164 use_rela_relocations = 1;
11166 return "mach-o-x86-64";
11169 return "mach-o-i386";
11177 #endif /* OBJ_MAYBE_ more than one */
11180 md_undefined_symbol (char *name)
11182 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11183 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11184 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11185 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11189 if (symbol_find (name))
11190 as_bad (_("GOT already in symbol table"));
11191 GOT_symbol = symbol_new (name, undefined_section,
11192 (valueT) 0, &zero_address_frag);
11199 /* Round up a section size to the appropriate boundary. */
11202 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11204 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11205 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11207 /* For a.out, force the section size to be aligned. If we don't do
11208 this, BFD will align it for us, but it will not write out the
11209 final bytes of the section. This may be a bug in BFD, but it is
11210 easier to fix it here since that is how the other a.out targets
11214 align = bfd_get_section_alignment (stdoutput, segment);
11215 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11222 /* On the i386, PC-relative offsets are relative to the start of the
11223 next instruction. That is, the address of the offset, plus its
11224 size, since the offset is always the last part of the insn. */
11227 md_pcrel_from (fixS *fixP)
11229 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11235 s_bss (int ignore ATTRIBUTE_UNUSED)
11239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11241 obj_elf_section_change_hook ();
11243 temp = get_absolute_expression ();
11244 subseg_set (bss_section, (subsegT) temp);
11245 demand_empty_rest_of_line ();
11251 i386_validate_fix (fixS *fixp)
11253 if (fixp->fx_subsy)
11255 if (fixp->fx_subsy == GOT_symbol)
11257 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11262 if (fixp->fx_tcbit2)
11263 fixp->fx_r_type = (fixp->fx_tcbit
11264 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11265 : BFD_RELOC_X86_64_GOTPCRELX);
11268 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11273 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11275 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11277 fixp->fx_subsy = 0;
11280 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11281 else if (!object_64bit)
11283 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11284 && fixp->fx_tcbit2)
11285 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11291 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11294 bfd_reloc_code_real_type code;
11296 switch (fixp->fx_r_type)
11298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11299 case BFD_RELOC_SIZE32:
11300 case BFD_RELOC_SIZE64:
11301 if (S_IS_DEFINED (fixp->fx_addsy)
11302 && !S_IS_EXTERNAL (fixp->fx_addsy))
11304 /* Resolve size relocation against local symbol to size of
11305 the symbol plus addend. */
11306 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11307 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11308 && !fits_in_unsigned_long (value))
11309 as_bad_where (fixp->fx_file, fixp->fx_line,
11310 _("symbol size computation overflow"));
11311 fixp->fx_addsy = NULL;
11312 fixp->fx_subsy = NULL;
11313 md_apply_fix (fixp, (valueT *) &value, NULL);
11317 /* Fall through. */
11319 case BFD_RELOC_X86_64_PLT32:
11320 case BFD_RELOC_X86_64_GOT32:
11321 case BFD_RELOC_X86_64_GOTPCREL:
11322 case BFD_RELOC_X86_64_GOTPCRELX:
11323 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11324 case BFD_RELOC_386_PLT32:
11325 case BFD_RELOC_386_GOT32:
11326 case BFD_RELOC_386_GOT32X:
11327 case BFD_RELOC_386_GOTOFF:
11328 case BFD_RELOC_386_GOTPC:
11329 case BFD_RELOC_386_TLS_GD:
11330 case BFD_RELOC_386_TLS_LDM:
11331 case BFD_RELOC_386_TLS_LDO_32:
11332 case BFD_RELOC_386_TLS_IE_32:
11333 case BFD_RELOC_386_TLS_IE:
11334 case BFD_RELOC_386_TLS_GOTIE:
11335 case BFD_RELOC_386_TLS_LE_32:
11336 case BFD_RELOC_386_TLS_LE:
11337 case BFD_RELOC_386_TLS_GOTDESC:
11338 case BFD_RELOC_386_TLS_DESC_CALL:
11339 case BFD_RELOC_X86_64_TLSGD:
11340 case BFD_RELOC_X86_64_TLSLD:
11341 case BFD_RELOC_X86_64_DTPOFF32:
11342 case BFD_RELOC_X86_64_DTPOFF64:
11343 case BFD_RELOC_X86_64_GOTTPOFF:
11344 case BFD_RELOC_X86_64_TPOFF32:
11345 case BFD_RELOC_X86_64_TPOFF64:
11346 case BFD_RELOC_X86_64_GOTOFF64:
11347 case BFD_RELOC_X86_64_GOTPC32:
11348 case BFD_RELOC_X86_64_GOT64:
11349 case BFD_RELOC_X86_64_GOTPCREL64:
11350 case BFD_RELOC_X86_64_GOTPC64:
11351 case BFD_RELOC_X86_64_GOTPLT64:
11352 case BFD_RELOC_X86_64_PLTOFF64:
11353 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11354 case BFD_RELOC_X86_64_TLSDESC_CALL:
11355 case BFD_RELOC_RVA:
11356 case BFD_RELOC_VTABLE_ENTRY:
11357 case BFD_RELOC_VTABLE_INHERIT:
11359 case BFD_RELOC_32_SECREL:
11361 code = fixp->fx_r_type;
11363 case BFD_RELOC_X86_64_32S:
11364 if (!fixp->fx_pcrel)
11366 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11367 code = fixp->fx_r_type;
11370 /* Fall through. */
11372 if (fixp->fx_pcrel)
11374 switch (fixp->fx_size)
11377 as_bad_where (fixp->fx_file, fixp->fx_line,
11378 _("can not do %d byte pc-relative relocation"),
11380 code = BFD_RELOC_32_PCREL;
11382 case 1: code = BFD_RELOC_8_PCREL; break;
11383 case 2: code = BFD_RELOC_16_PCREL; break;
11384 case 4: code = BFD_RELOC_32_PCREL; break;
11386 case 8: code = BFD_RELOC_64_PCREL; break;
11392 switch (fixp->fx_size)
11395 as_bad_where (fixp->fx_file, fixp->fx_line,
11396 _("can not do %d byte relocation"),
11398 code = BFD_RELOC_32;
11400 case 1: code = BFD_RELOC_8; break;
11401 case 2: code = BFD_RELOC_16; break;
11402 case 4: code = BFD_RELOC_32; break;
11404 case 8: code = BFD_RELOC_64; break;
11411 if ((code == BFD_RELOC_32
11412 || code == BFD_RELOC_32_PCREL
11413 || code == BFD_RELOC_X86_64_32S)
11415 && fixp->fx_addsy == GOT_symbol)
11418 code = BFD_RELOC_386_GOTPC;
11420 code = BFD_RELOC_X86_64_GOTPC32;
11422 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11424 && fixp->fx_addsy == GOT_symbol)
11426 code = BFD_RELOC_X86_64_GOTPC64;
11429 rel = XNEW (arelent);
11430 rel->sym_ptr_ptr = XNEW (asymbol *);
11431 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11433 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11435 if (!use_rela_relocations)
11437 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11438 vtable entry to be used in the relocation's section offset. */
11439 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11440 rel->address = fixp->fx_offset;
11441 #if defined (OBJ_COFF) && defined (TE_PE)
11442 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11443 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11448 /* Use the rela in 64bit mode. */
11451 if (disallow_64bit_reloc)
11454 case BFD_RELOC_X86_64_DTPOFF64:
11455 case BFD_RELOC_X86_64_TPOFF64:
11456 case BFD_RELOC_64_PCREL:
11457 case BFD_RELOC_X86_64_GOTOFF64:
11458 case BFD_RELOC_X86_64_GOT64:
11459 case BFD_RELOC_X86_64_GOTPCREL64:
11460 case BFD_RELOC_X86_64_GOTPC64:
11461 case BFD_RELOC_X86_64_GOTPLT64:
11462 case BFD_RELOC_X86_64_PLTOFF64:
11463 as_bad_where (fixp->fx_file, fixp->fx_line,
11464 _("cannot represent relocation type %s in x32 mode"),
11465 bfd_get_reloc_code_name (code));
11471 if (!fixp->fx_pcrel)
11472 rel->addend = fixp->fx_offset;
11476 case BFD_RELOC_X86_64_PLT32:
11477 case BFD_RELOC_X86_64_GOT32:
11478 case BFD_RELOC_X86_64_GOTPCREL:
11479 case BFD_RELOC_X86_64_GOTPCRELX:
11480 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11481 case BFD_RELOC_X86_64_TLSGD:
11482 case BFD_RELOC_X86_64_TLSLD:
11483 case BFD_RELOC_X86_64_GOTTPOFF:
11484 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11485 case BFD_RELOC_X86_64_TLSDESC_CALL:
11486 rel->addend = fixp->fx_offset - fixp->fx_size;
11489 rel->addend = (section->vma
11491 + fixp->fx_addnumber
11492 + md_pcrel_from (fixp));
11497 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11498 if (rel->howto == NULL)
11500 as_bad_where (fixp->fx_file, fixp->fx_line,
11501 _("cannot represent relocation type %s"),
11502 bfd_get_reloc_code_name (code));
11503 /* Set howto to a garbage value so that we can keep going. */
11504 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11505 gas_assert (rel->howto != NULL);
11511 #include "tc-i386-intel.c"
11514 tc_x86_parse_to_dw2regnum (expressionS *exp)
11516 int saved_naked_reg;
11517 char saved_register_dot;
11519 saved_naked_reg = allow_naked_reg;
11520 allow_naked_reg = 1;
11521 saved_register_dot = register_chars['.'];
11522 register_chars['.'] = '.';
11523 allow_pseudo_reg = 1;
11524 expression_and_evaluate (exp);
11525 allow_pseudo_reg = 0;
11526 register_chars['.'] = saved_register_dot;
11527 allow_naked_reg = saved_naked_reg;
11529 if (exp->X_op == O_register && exp->X_add_number >= 0)
11531 if ((addressT) exp->X_add_number < i386_regtab_size)
11533 exp->X_op = O_constant;
11534 exp->X_add_number = i386_regtab[exp->X_add_number]
11535 .dw2_regnum[flag_code >> 1];
11538 exp->X_op = O_illegal;
11543 tc_x86_frame_initial_instructions (void)
11545 static unsigned int sp_regno[2];
11547 if (!sp_regno[flag_code >> 1])
11549 char *saved_input = input_line_pointer;
11550 char sp[][4] = {"esp", "rsp"};
11553 input_line_pointer = sp[flag_code >> 1];
11554 tc_x86_parse_to_dw2regnum (&exp);
11555 gas_assert (exp.X_op == O_constant);
11556 sp_regno[flag_code >> 1] = exp.X_add_number;
11557 input_line_pointer = saved_input;
11560 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11561 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11565 x86_dwarf2_addr_size (void)
11567 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11568 if (x86_elf_abi == X86_64_X32_ABI)
11571 return bfd_arch_bits_per_address (stdoutput) / 8;
11575 i386_elf_section_type (const char *str, size_t len)
11577 if (flag_code == CODE_64BIT
11578 && len == sizeof ("unwind") - 1
11579 && strncmp (str, "unwind", 6) == 0)
11580 return SHT_X86_64_UNWIND;
11587 i386_solaris_fix_up_eh_frame (segT sec)
11589 if (flag_code == CODE_64BIT)
11590 elf_section_type (sec) = SHT_X86_64_UNWIND;
11596 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11600 exp.X_op = O_secrel;
11601 exp.X_add_symbol = symbol;
11602 exp.X_add_number = 0;
11603 emit_expr (&exp, size);
11607 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11608 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11611 x86_64_section_letter (int letter, const char **ptr_msg)
11613 if (flag_code == CODE_64BIT)
11616 return SHF_X86_64_LARGE;
11618 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11621 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11626 x86_64_section_word (char *str, size_t len)
11628 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11629 return SHF_X86_64_LARGE;
11635 handle_large_common (int small ATTRIBUTE_UNUSED)
11637 if (flag_code != CODE_64BIT)
11639 s_comm_internal (0, elf_common_parse);
11640 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11644 static segT lbss_section;
11645 asection *saved_com_section_ptr = elf_com_section_ptr;
11646 asection *saved_bss_section = bss_section;
11648 if (lbss_section == NULL)
11650 flagword applicable;
11651 segT seg = now_seg;
11652 subsegT subseg = now_subseg;
11654 /* The .lbss section is for local .largecomm symbols. */
11655 lbss_section = subseg_new (".lbss", 0);
11656 applicable = bfd_applicable_section_flags (stdoutput);
11657 bfd_set_section_flags (stdoutput, lbss_section,
11658 applicable & SEC_ALLOC);
11659 seg_info (lbss_section)->bss = 1;
11661 subseg_set (seg, subseg);
11664 elf_com_section_ptr = &_bfd_elf_large_com_section;
11665 bss_section = lbss_section;
11667 s_comm_internal (0, elf_common_parse);
11669 elf_com_section_ptr = saved_com_section_ptr;
11670 bss_section = saved_bss_section;
11673 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */