1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_allow_index_reg (int);
62 static void set_cpu_arch (int);
64 static void pe_directive_secrel (int);
66 static void signed_cons (int);
67 static char *output_invalid (int c);
68 static int i386_operand (char *);
69 static int i386_intel_operand (char *, int);
70 static const reg_entry *parse_register (char *, char **);
71 static char *parse_insn (char *, char *);
72 static char *parse_operands (char *, const char *);
73 static void swap_operands (void);
74 static void swap_2_operands (int, int);
75 static void optimize_imm (void);
76 static void optimize_disp (void);
77 static int match_template (void);
78 static int check_string (void);
79 static int process_suffix (void);
80 static int check_byte_reg (void);
81 static int check_long_reg (void);
82 static int check_qword_reg (void);
83 static int check_word_reg (void);
84 static int finalize_imm (void);
85 static void process_drex (void);
86 static int process_operands (void);
87 static const seg_entry *build_modrm_byte (void);
88 static void output_insn (void);
89 static void output_imm (fragS *, offsetT);
90 static void output_disp (fragS *, offsetT);
92 static void s_bss (int);
94 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95 static void handle_large_common (int small ATTRIBUTE_UNUSED);
98 static const char *default_arch = DEFAULT_ARCH;
100 /* 'md_assemble ()' gathers together information and puts it into a
107 const reg_entry *regs;
112 /* TM holds the template for the insn were currently assembling. */
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
119 /* OPERANDS gives the number of given operands. */
120 unsigned int operands;
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127 /* TYPES [i] is the type (see above #defines) which tells us how to
128 use OP[i] for the corresponding operand. */
129 i386_operand_type types[MAX_OPERANDS];
131 /* Displacement expression, immediate expression, or register for each
133 union i386_op op[MAX_OPERANDS];
135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137 #define Operand_PCrel 1
139 /* Relocation type for operand */
140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
148 /* SEG gives the seg_entries of this insn. They are zero unless
149 explicit segment overrides are given. */
150 const seg_entry *seg[2];
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
157 /* RM and SIB are the modrm byte and the sib byte where the
158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
167 typedef struct _i386_insn i386_insn;
169 /* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
171 const char extra_symbol_chars[] = "*%-(["
180 #if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
182 && !defined (TE_GNU) \
183 && !defined (TE_LINUX) \
184 && !defined (TE_NETWARE) \
185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190 const char *i386_comment_chars = "#/";
191 #define SVR4_COMMENT_CHARS 1
192 #define PREFIX_SEPARATOR '\\'
195 const char *i386_comment_chars = "#";
196 #define PREFIX_SEPARATOR '/'
199 /* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
203 first line of the input file. This is because the compiler outputs
204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
206 '/' isn't otherwise defined. */
207 const char line_comment_chars[] = "#/";
209 const char line_separator_chars[] = ";";
211 /* Chars that can be used to separate mant from exp in floating point
213 const char EXP_CHARS[] = "eE";
215 /* Chars that mean this number is a floating point constant
218 const char FLT_CHARS[] = "fFdDxX";
220 /* Tables for lexical analysis. */
221 static char mnemonic_chars[256];
222 static char register_chars[256];
223 static char operand_chars[256];
224 static char identifier_chars[256];
225 static char digit_chars[256];
227 /* Lexical macros. */
228 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229 #define is_operand_char(x) (operand_chars[(unsigned char) x])
230 #define is_register_char(x) (register_chars[(unsigned char) x])
231 #define is_space_char(x) ((x) == ' ')
232 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233 #define is_digit_char(x) (digit_chars[(unsigned char) x])
235 /* All non-digit non-letter characters that may occur in an operand. */
236 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238 /* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
241 assembler instruction). */
242 static char save_stack[32];
243 static char *save_stack_p;
244 #define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246 #define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
249 /* The instruction we're assembling. */
252 /* Possible templates for current insn. */
253 static const templates *current_templates;
255 /* Per instruction expressionS buffers: max displacements & immediates. */
256 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
259 /* Current operand we are working on. */
260 static int this_operand;
262 /* We support four different modes. FLAG_CODE variable is used to distinguish
270 static enum flag_code flag_code;
271 static unsigned int object_64bit;
272 static int use_rela_relocations = 0;
274 /* The names used to print error messages. */
275 static const char *flag_code_names[] =
282 /* 1 for intel syntax,
284 static int intel_syntax = 0;
286 /* 1 if register prefix % not required. */
287 static int allow_naked_reg = 0;
289 /* 1 if fake index register, eiz/riz, is allowed . */
290 static int allow_index_reg = 0;
292 /* Register prefix used for error message. */
293 static const char *register_prefix = "%";
295 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298 static char stackop_size = '\0';
300 /* Non-zero to optimize code alignment. */
301 int optimize_align_code = 1;
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings = 0;
307 static const char *cpu_arch_name = NULL;
308 static const char *cpu_sub_arch_name = NULL;
310 /* CPU feature flags. */
311 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
313 /* Bitwise NOT of cpu_arch_flags. */
314 static i386_cpu_flags cpu_arch_flags_not;
316 /* If we have selected a cpu we are generating instructions for. */
317 static int cpu_arch_tune_set = 0;
319 /* Cpu we are generating instructions for. */
320 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
322 /* CPU feature flags of cpu we are generating instructions for. */
323 static i386_cpu_flags cpu_arch_tune_flags;
325 /* CPU instruction set architecture used. */
326 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
328 /* CPU feature flags of instruction set architecture used. */
329 static i386_cpu_flags cpu_arch_isa_flags;
331 /* If set, conditional jumps are not automatically promoted to handle
332 larger than a byte offset. */
333 static unsigned int no_cond_jump_promotion = 0;
335 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
336 static symbolS *GOT_symbol;
338 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
339 unsigned int x86_dwarf2_return_column;
341 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
342 int x86_cie_data_alignment;
344 /* Interface to relax_segment.
345 There are 3 major relax states for 386 jump insns because the
346 different types of jumps add different sizes to frags when we're
347 figuring out what sort of jump to choose to reach a given label. */
350 #define UNCOND_JUMP 0
352 #define COND_JUMP86 2
357 #define SMALL16 (SMALL | CODE16)
359 #define BIG16 (BIG | CODE16)
363 #define INLINE __inline__
369 #define ENCODE_RELAX_STATE(type, size) \
370 ((relax_substateT) (((type) << 2) | (size)))
371 #define TYPE_FROM_RELAX_STATE(s) \
373 #define DISP_SIZE_FROM_RELAX_STATE(s) \
374 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
376 /* This table is used by relax_frag to promote short jumps to long
377 ones where necessary. SMALL (short) jumps may be promoted to BIG
378 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
379 don't allow a short jump in a 32 bit code segment to be promoted to
380 a 16 bit offset jump because it's slower (requires data size
381 prefix), and doesn't work, unless the destination is in the bottom
382 64k of the code segment (The top 16 bits of eip are zeroed). */
384 const relax_typeS md_relax_table[] =
387 1) most positive reach of this state,
388 2) most negative reach of this state,
389 3) how many bytes this mode will have in the variable part of the frag
390 4) which index into the table to try if we can't fit into this one. */
392 /* UNCOND_JUMP states. */
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
395 /* dword jmp adds 4 bytes to frag:
396 0 extra opcode bytes, 4 displacement bytes. */
398 /* word jmp adds 2 byte2 to frag:
399 0 extra opcode bytes, 2 displacement bytes. */
402 /* COND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
408 /* word conditionals add 3 bytes to frag:
409 1 extra opcode byte, 2 displacement bytes. */
412 /* COND_JUMP86 states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
418 /* word conditionals add 4 bytes to frag:
419 1 displacement byte and a 3 byte long branch insn. */
423 static const arch_entry cpu_arch[] =
425 {"generic32", PROCESSOR_GENERIC32,
426 CPU_GENERIC32_FLAGS },
427 {"generic64", PROCESSOR_GENERIC64,
428 CPU_GENERIC64_FLAGS },
429 {"i8086", PROCESSOR_UNKNOWN,
431 {"i186", PROCESSOR_UNKNOWN,
433 {"i286", PROCESSOR_UNKNOWN,
435 {"i386", PROCESSOR_I386,
437 {"i486", PROCESSOR_I486,
439 {"i586", PROCESSOR_PENTIUM,
441 {"i686", PROCESSOR_PENTIUMPRO,
443 {"pentium", PROCESSOR_PENTIUM,
445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
447 {"pentiumii", PROCESSOR_PENTIUMPRO,
449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
451 {"pentium4", PROCESSOR_PENTIUM4,
453 {"prescott", PROCESSOR_NOCONA,
455 {"nocona", PROCESSOR_NOCONA,
457 {"yonah", PROCESSOR_CORE,
459 {"core", PROCESSOR_CORE,
461 {"merom", PROCESSOR_CORE2,
463 {"core2", PROCESSOR_CORE2,
467 {"k6_2", PROCESSOR_K6,
469 {"athlon", PROCESSOR_ATHLON,
471 {"sledgehammer", PROCESSOR_K8,
473 {"opteron", PROCESSOR_K8,
477 {"amdfam10", PROCESSOR_AMDFAM10,
478 CPU_AMDFAM10_FLAGS },
479 {".mmx", PROCESSOR_UNKNOWN,
481 {".sse", PROCESSOR_UNKNOWN,
483 {".sse2", PROCESSOR_UNKNOWN,
485 {".sse3", PROCESSOR_UNKNOWN,
487 {".ssse3", PROCESSOR_UNKNOWN,
489 {".sse4.1", PROCESSOR_UNKNOWN,
491 {".sse4.2", PROCESSOR_UNKNOWN,
493 {".sse4", PROCESSOR_UNKNOWN,
495 {".3dnow", PROCESSOR_UNKNOWN,
497 {".3dnowa", PROCESSOR_UNKNOWN,
499 {".padlock", PROCESSOR_UNKNOWN,
501 {".pacifica", PROCESSOR_UNKNOWN,
503 {".svme", PROCESSOR_UNKNOWN,
505 {".sse4a", PROCESSOR_UNKNOWN,
507 {".abm", PROCESSOR_UNKNOWN,
509 {".sse5", PROCESSOR_UNKNOWN,
513 const pseudo_typeS md_pseudo_table[] =
515 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
518 {"align", s_align_ptwo, 0},
520 {"arch", set_cpu_arch, 0},
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
528 {"slong", signed_cons, 4},
529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
537 {"allow_index_reg", set_allow_index_reg, 1},
538 {"disallow_index_reg", set_allow_index_reg, 0},
539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common, 0},
542 {"file", (void (*) (int)) dwarf2_directive_file, 0},
543 {"loc", dwarf2_directive_loc, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
547 {"secrel32", pe_directive_secrel, 0},
552 /* For interface with expression (). */
553 extern char *input_line_pointer;
555 /* Hash table for instruction mnemonic lookup. */
556 static struct hash_control *op_hash;
558 /* Hash table for register lookup. */
559 static struct hash_control *reg_hash;
562 i386_align_code (fragS *fragP, int count)
564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
567 static const char f32_1[] =
569 static const char f32_2[] =
570 {0x66,0x90}; /* xchg %ax,%ax */
571 static const char f32_3[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5[] =
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8[] =
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f16_3[] =
604 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
605 static const char f16_4[] =
606 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
607 static const char f16_5[] =
609 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_6[] =
611 {0x89,0xf6, /* mov %si,%si */
612 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
613 static const char f16_7[] =
614 {0x8d,0x74,0x00, /* lea 0(%si),%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_8[] =
617 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char jump_31[] =
620 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
628 static const char *const f16_patt[] = {
629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
632 static const char alt_3[] =
634 /* nopl 0(%[re]ax) */
635 static const char alt_4[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11[] =
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14[] =
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15[] =
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
712 static const char alt_short_13[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
717 static const char alt_short_14[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt[] = {
726 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
727 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
728 alt_short_14, alt_short_15
730 static const char *const alt_long_patt[] = {
731 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
732 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
733 alt_long_14, alt_long_15
736 /* Only align for at least a positive non-zero boundary. */
737 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
743 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
744 PROCESSOR_GENERIC32, f32_patt will be used.
745 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
747 alt_long_patt will be used.
748 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
749 PROCESSOR_AMDFAM10, alt_short_patt will be used.
751 When -mtune= isn't used, alt_long_patt will be used if
752 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code == CODE_16BIT)
762 memcpy (fragP->fr_literal + fragP->fr_fix,
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
768 memcpy (fragP->fr_literal + fragP->fr_fix,
769 f16_patt[count - 1], count);
773 const char *const *patt = NULL;
775 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
777 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
778 switch (cpu_arch_tune)
780 case PROCESSOR_UNKNOWN:
781 /* We use cpu_arch_isa_flags to check if we SHOULD
782 optimize for Cpu686. */
783 if (cpu_arch_isa_flags.bitfield.cpui686)
784 patt = alt_long_patt;
788 case PROCESSOR_PENTIUMPRO:
789 case PROCESSOR_PENTIUM4:
790 case PROCESSOR_NOCONA:
792 case PROCESSOR_CORE2:
793 case PROCESSOR_GENERIC64:
794 patt = alt_long_patt;
797 case PROCESSOR_ATHLON:
799 case PROCESSOR_AMDFAM10:
800 patt = alt_short_patt;
804 case PROCESSOR_PENTIUM:
805 case PROCESSOR_GENERIC32:
812 switch (cpu_arch_tune)
814 case PROCESSOR_UNKNOWN:
815 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
816 PROCESSOR_UNKNOWN. */
822 case PROCESSOR_PENTIUM:
824 case PROCESSOR_ATHLON:
826 case PROCESSOR_AMDFAM10:
827 case PROCESSOR_GENERIC32:
828 /* We use cpu_arch_isa_flags to check if we CAN optimize
830 if (cpu_arch_isa_flags.bitfield.cpui686)
831 patt = alt_short_patt;
835 case PROCESSOR_PENTIUMPRO:
836 case PROCESSOR_PENTIUM4:
837 case PROCESSOR_NOCONA:
839 case PROCESSOR_CORE2:
840 if (cpu_arch_isa_flags.bitfield.cpui686)
841 patt = alt_long_patt;
845 case PROCESSOR_GENERIC64:
846 patt = alt_long_patt;
851 if (patt == f32_patt)
853 /* If the padding is less than 15 bytes, we use the normal
854 ones. Otherwise, we use a jump instruction and adjust
857 memcpy (fragP->fr_literal + fragP->fr_fix,
858 patt[count - 1], count);
861 memcpy (fragP->fr_literal + fragP->fr_fix,
863 /* Adjust jump offset. */
864 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
869 /* Maximum length of an instruction is 15 byte. If the
870 padding is greater than 15 bytes and we don't use jump,
871 we have to break it into smaller pieces. */
876 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
881 memcpy (fragP->fr_literal + fragP->fr_fix,
882 patt [padding - 1], padding);
885 fragP->fr_var = count;
889 uints_all_zero (const unsigned int *x, unsigned int size)
907 uints_set (unsigned int *x, unsigned int v, unsigned int size)
924 uints_equal (const unsigned int *x, const unsigned int *y,
936 return x[0] == y [0];
943 #define UINTS_ALL_ZERO(x) \
944 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
945 #define UINTS_SET(x, v) \
946 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
947 #define UINTS_CLEAR(x) \
948 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
949 #define UINTS_EQUAL(x, y) \
950 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
953 cpu_flags_check_cpu64 (i386_cpu_flags f)
955 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
956 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
959 static INLINE i386_cpu_flags
960 cpu_flags_not (i386_cpu_flags x)
962 switch (ARRAY_SIZE (x.array))
965 x.array [2] = ~x.array [2];
967 x.array [1] = ~x.array [1];
969 x.array [0] = ~x.array [0];
976 x.bitfield.unused = 0;
982 static INLINE i386_cpu_flags
983 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
985 switch (ARRAY_SIZE (x.array))
988 x.array [2] &= y.array [2];
990 x.array [1] &= y.array [1];
992 x.array [0] &= y.array [0];
1000 static INLINE i386_cpu_flags
1001 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1003 switch (ARRAY_SIZE (x.array))
1006 x.array [2] |= y.array [2];
1008 x.array [1] |= y.array [1];
1010 x.array [0] |= y.array [0];
1019 cpu_flags_match (i386_cpu_flags x)
1021 i386_cpu_flags not = cpu_arch_flags_not;
1023 not.bitfield.cpu64 = 1;
1024 not.bitfield.cpuno64 = 1;
1026 x.bitfield.cpu64 = 0;
1027 x.bitfield.cpuno64 = 0;
1029 not = cpu_flags_and (x, not);
1030 return UINTS_ALL_ZERO (not);
1033 static INLINE i386_operand_type
1034 operand_type_and (i386_operand_type x, i386_operand_type y)
1036 switch (ARRAY_SIZE (x.array))
1039 x.array [2] &= y.array [2];
1041 x.array [1] &= y.array [1];
1043 x.array [0] &= y.array [0];
1051 static INLINE i386_operand_type
1052 operand_type_or (i386_operand_type x, i386_operand_type y)
1054 switch (ARRAY_SIZE (x.array))
1057 x.array [2] |= y.array [2];
1059 x.array [1] |= y.array [1];
1061 x.array [0] |= y.array [0];
1069 static INLINE i386_operand_type
1070 operand_type_xor (i386_operand_type x, i386_operand_type y)
1072 switch (ARRAY_SIZE (x.array))
1075 x.array [2] ^= y.array [2];
1077 x.array [1] ^= y.array [1];
1079 x.array [0] ^= y.array [0];
1087 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1088 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1089 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1090 static const i386_operand_type reg16_inoutportreg
1091 = OPERAND_TYPE_REG16_INOUTPORTREG;
1092 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1093 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1094 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1095 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1096 static const i386_operand_type anydisp
1097 = OPERAND_TYPE_ANYDISP;
1098 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1099 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1100 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1101 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1102 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1103 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1104 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1105 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1106 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1107 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1118 operand_type_check (i386_operand_type t, enum operand_type c)
1123 return (t.bitfield.reg8
1126 || t.bitfield.reg64);
1129 return (t.bitfield.imm8
1133 || t.bitfield.imm32s
1134 || t.bitfield.imm64);
1137 return (t.bitfield.disp8
1138 || t.bitfield.disp16
1139 || t.bitfield.disp32
1140 || t.bitfield.disp32s
1141 || t.bitfield.disp64);
1144 return (t.bitfield.disp8
1145 || t.bitfield.disp16
1146 || t.bitfield.disp32
1147 || t.bitfield.disp32s
1148 || t.bitfield.disp64
1149 || t.bitfield.baseindex);
1157 operand_type_match (i386_operand_type overlap,
1158 i386_operand_type given)
1160 i386_operand_type temp = overlap;
1162 temp.bitfield.jumpabsolute = 0;
1163 if (UINTS_ALL_ZERO (temp))
1166 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1167 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1170 /* If given types r0 and r1 are registers they must be of the same type
1171 unless the expected operand type register overlap is null.
1172 Note that Acc in a template matches every size of reg. */
1175 operand_type_register_match (i386_operand_type m0,
1176 i386_operand_type g0,
1177 i386_operand_type t0,
1178 i386_operand_type m1,
1179 i386_operand_type g1,
1180 i386_operand_type t1)
1182 if (!operand_type_check (g0, reg))
1185 if (!operand_type_check (g1, reg))
1188 if (g0.bitfield.reg8 == g1.bitfield.reg8
1189 && g0.bitfield.reg16 == g1.bitfield.reg16
1190 && g0.bitfield.reg32 == g1.bitfield.reg32
1191 && g0.bitfield.reg64 == g1.bitfield.reg64)
1194 if (m0.bitfield.acc)
1196 t0.bitfield.reg8 = 1;
1197 t0.bitfield.reg16 = 1;
1198 t0.bitfield.reg32 = 1;
1199 t0.bitfield.reg64 = 1;
1202 if (m1.bitfield.acc)
1204 t1.bitfield.reg8 = 1;
1205 t1.bitfield.reg16 = 1;
1206 t1.bitfield.reg32 = 1;
1207 t1.bitfield.reg64 = 1;
1210 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1211 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1212 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1213 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1216 static INLINE unsigned int
1217 mode_from_disp_size (i386_operand_type t)
1219 if (t.bitfield.disp8)
1221 else if (t.bitfield.disp16
1222 || t.bitfield.disp32
1223 || t.bitfield.disp32s)
1230 fits_in_signed_byte (offsetT num)
1232 return (num >= -128) && (num <= 127);
1236 fits_in_unsigned_byte (offsetT num)
1238 return (num & 0xff) == num;
1242 fits_in_unsigned_word (offsetT num)
1244 return (num & 0xffff) == num;
1248 fits_in_signed_word (offsetT num)
1250 return (-32768 <= num) && (num <= 32767);
1254 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1259 return (!(((offsetT) -1 << 31) & num)
1260 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1262 } /* fits_in_signed_long() */
1265 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1270 return (num & (((offsetT) 2 << 31) - 1)) == num;
1272 } /* fits_in_unsigned_long() */
1274 static i386_operand_type
1275 smallest_imm_type (offsetT num)
1277 i386_operand_type t;
1280 t.bitfield.imm64 = 1;
1282 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1284 /* This code is disabled on the 486 because all the Imm1 forms
1285 in the opcode table are slower on the i486. They're the
1286 versions with the implicitly specified single-position
1287 displacement, which has another syntax if you really want to
1289 t.bitfield.imm1 = 1;
1290 t.bitfield.imm8 = 1;
1291 t.bitfield.imm8s = 1;
1292 t.bitfield.imm16 = 1;
1293 t.bitfield.imm32 = 1;
1294 t.bitfield.imm32s = 1;
1296 else if (fits_in_signed_byte (num))
1298 t.bitfield.imm8 = 1;
1299 t.bitfield.imm8s = 1;
1300 t.bitfield.imm16 = 1;
1301 t.bitfield.imm32 = 1;
1302 t.bitfield.imm32s = 1;
1304 else if (fits_in_unsigned_byte (num))
1306 t.bitfield.imm8 = 1;
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1311 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1313 t.bitfield.imm16 = 1;
1314 t.bitfield.imm32 = 1;
1315 t.bitfield.imm32s = 1;
1317 else if (fits_in_signed_long (num))
1319 t.bitfield.imm32 = 1;
1320 t.bitfield.imm32s = 1;
1322 else if (fits_in_unsigned_long (num))
1323 t.bitfield.imm32 = 1;
1329 offset_in_range (offsetT val, int size)
1335 case 1: mask = ((addressT) 1 << 8) - 1; break;
1336 case 2: mask = ((addressT) 1 << 16) - 1; break;
1337 case 4: mask = ((addressT) 2 << 31) - 1; break;
1339 case 8: mask = ((addressT) 2 << 63) - 1; break;
1344 /* If BFD64, sign extend val. */
1345 if (!use_rela_relocations)
1346 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1347 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1349 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1351 char buf1[40], buf2[40];
1353 sprint_value (buf1, val);
1354 sprint_value (buf2, val & mask);
1355 as_warn (_("%s shortened to %s"), buf1, buf2);
1360 /* Returns 0 if attempting to add a prefix where one from the same
1361 class already exists, 1 if non rep/repne added, 2 if rep/repne
1364 add_prefix (unsigned int prefix)
1369 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1370 && flag_code == CODE_64BIT)
1372 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1373 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1374 && (prefix & (REX_R | REX_X | REX_B))))
1385 case CS_PREFIX_OPCODE:
1386 case DS_PREFIX_OPCODE:
1387 case ES_PREFIX_OPCODE:
1388 case FS_PREFIX_OPCODE:
1389 case GS_PREFIX_OPCODE:
1390 case SS_PREFIX_OPCODE:
1394 case REPNE_PREFIX_OPCODE:
1395 case REPE_PREFIX_OPCODE:
1398 case LOCK_PREFIX_OPCODE:
1406 case ADDR_PREFIX_OPCODE:
1410 case DATA_PREFIX_OPCODE:
1414 if (i.prefix[q] != 0)
1422 i.prefix[q] |= prefix;
1425 as_bad (_("same type of prefix used twice"));
1431 set_code_flag (int value)
1434 if (flag_code == CODE_64BIT)
1436 cpu_arch_flags.bitfield.cpu64 = 1;
1437 cpu_arch_flags.bitfield.cpuno64 = 0;
1438 cpu_arch_flags_not.bitfield.cpu64 = 0;
1439 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1443 cpu_arch_flags.bitfield.cpu64 = 0;
1444 cpu_arch_flags.bitfield.cpuno64 = 1;
1445 cpu_arch_flags_not.bitfield.cpu64 = 1;
1446 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1448 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1450 as_bad (_("64bit mode not supported on this CPU."));
1452 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1454 as_bad (_("32bit mode not supported on this CPU."));
1456 stackop_size = '\0';
1460 set_16bit_gcc_code_flag (int new_code_flag)
1462 flag_code = new_code_flag;
1463 if (flag_code != CODE_16BIT)
1465 cpu_arch_flags.bitfield.cpu64 = 0;
1466 cpu_arch_flags.bitfield.cpuno64 = 1;
1467 cpu_arch_flags_not.bitfield.cpu64 = 1;
1468 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1469 stackop_size = LONG_MNEM_SUFFIX;
1473 set_intel_syntax (int syntax_flag)
1475 /* Find out if register prefixing is specified. */
1476 int ask_naked_reg = 0;
1479 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1481 char *string = input_line_pointer;
1482 int e = get_symbol_end ();
1484 if (strcmp (string, "prefix") == 0)
1486 else if (strcmp (string, "noprefix") == 0)
1489 as_bad (_("bad argument to syntax directive."));
1490 *input_line_pointer = e;
1492 demand_empty_rest_of_line ();
1494 intel_syntax = syntax_flag;
1496 if (ask_naked_reg == 0)
1497 allow_naked_reg = (intel_syntax
1498 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1500 allow_naked_reg = (ask_naked_reg < 0);
1502 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1503 identifier_chars['$'] = intel_syntax ? '$' : 0;
1504 register_prefix = allow_naked_reg ? "" : "%";
1508 set_allow_index_reg (int flag)
1510 allow_index_reg = flag;
1514 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1520 char *string = input_line_pointer;
1521 int e = get_symbol_end ();
1523 i386_cpu_flags flags;
1525 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1527 if (strcmp (string, cpu_arch[i].name) == 0)
1531 cpu_arch_name = cpu_arch[i].name;
1532 cpu_sub_arch_name = NULL;
1533 cpu_arch_flags = cpu_arch[i].flags;
1534 if (flag_code == CODE_64BIT)
1536 cpu_arch_flags.bitfield.cpu64 = 1;
1537 cpu_arch_flags.bitfield.cpuno64 = 0;
1541 cpu_arch_flags.bitfield.cpu64 = 0;
1542 cpu_arch_flags.bitfield.cpuno64 = 1;
1544 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1545 cpu_arch_isa = cpu_arch[i].type;
1546 cpu_arch_isa_flags = cpu_arch[i].flags;
1547 if (!cpu_arch_tune_set)
1549 cpu_arch_tune = cpu_arch_isa;
1550 cpu_arch_tune_flags = cpu_arch_isa_flags;
1555 flags = cpu_flags_or (cpu_arch_flags,
1557 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1559 cpu_sub_arch_name = cpu_arch[i].name;
1560 cpu_arch_flags = flags;
1561 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1563 *input_line_pointer = e;
1564 demand_empty_rest_of_line ();
1568 if (i >= ARRAY_SIZE (cpu_arch))
1569 as_bad (_("no such architecture: `%s'"), string);
1571 *input_line_pointer = e;
1574 as_bad (_("missing cpu architecture"));
1576 no_cond_jump_promotion = 0;
1577 if (*input_line_pointer == ','
1578 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1580 char *string = ++input_line_pointer;
1581 int e = get_symbol_end ();
1583 if (strcmp (string, "nojumps") == 0)
1584 no_cond_jump_promotion = 1;
1585 else if (strcmp (string, "jumps") == 0)
1588 as_bad (_("no such architecture modifier: `%s'"), string);
1590 *input_line_pointer = e;
1593 demand_empty_rest_of_line ();
1599 if (!strcmp (default_arch, "x86_64"))
1600 return bfd_mach_x86_64;
1601 else if (!strcmp (default_arch, "i386"))
1602 return bfd_mach_i386_i386;
1604 as_fatal (_("Unknown architecture"));
1610 const char *hash_err;
1612 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1614 /* Initialize op_hash hash table. */
1615 op_hash = hash_new ();
1618 const template *optab;
1619 templates *core_optab;
1621 /* Setup for loop. */
1623 core_optab = (templates *) xmalloc (sizeof (templates));
1624 core_optab->start = optab;
1629 if (optab->name == NULL
1630 || strcmp (optab->name, (optab - 1)->name) != 0)
1632 /* different name --> ship out current template list;
1633 add to hash table; & begin anew. */
1634 core_optab->end = optab;
1635 hash_err = hash_insert (op_hash,
1640 as_fatal (_("Internal Error: Can't hash %s: %s"),
1644 if (optab->name == NULL)
1646 core_optab = (templates *) xmalloc (sizeof (templates));
1647 core_optab->start = optab;
1652 /* Initialize reg_hash hash table. */
1653 reg_hash = hash_new ();
1655 const reg_entry *regtab;
1656 unsigned int regtab_size = i386_regtab_size;
1658 for (regtab = i386_regtab; regtab_size--; regtab++)
1660 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1662 as_fatal (_("Internal Error: Can't hash %s: %s"),
1668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1673 for (c = 0; c < 256; c++)
1678 mnemonic_chars[c] = c;
1679 register_chars[c] = c;
1680 operand_chars[c] = c;
1682 else if (ISLOWER (c))
1684 mnemonic_chars[c] = c;
1685 register_chars[c] = c;
1686 operand_chars[c] = c;
1688 else if (ISUPPER (c))
1690 mnemonic_chars[c] = TOLOWER (c);
1691 register_chars[c] = mnemonic_chars[c];
1692 operand_chars[c] = c;
1695 if (ISALPHA (c) || ISDIGIT (c))
1696 identifier_chars[c] = c;
1699 identifier_chars[c] = c;
1700 operand_chars[c] = c;
1705 identifier_chars['@'] = '@';
1708 identifier_chars['?'] = '?';
1709 operand_chars['?'] = '?';
1711 digit_chars['-'] = '-';
1712 mnemonic_chars['-'] = '-';
1713 mnemonic_chars['.'] = '.';
1714 identifier_chars['_'] = '_';
1715 identifier_chars['.'] = '.';
1717 for (p = operand_special_chars; *p != '\0'; p++)
1718 operand_chars[(unsigned char) *p] = *p;
1721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1724 record_alignment (text_section, 2);
1725 record_alignment (data_section, 2);
1726 record_alignment (bss_section, 2);
1730 if (flag_code == CODE_64BIT)
1732 x86_dwarf2_return_column = 16;
1733 x86_cie_data_alignment = -8;
1737 x86_dwarf2_return_column = 8;
1738 x86_cie_data_alignment = -4;
1743 i386_print_statistics (FILE *file)
1745 hash_print_statistics (file, "i386 opcode", op_hash);
1746 hash_print_statistics (file, "i386 register", reg_hash);
1751 /* Debugging routines for md_assemble. */
1752 static void pte (template *);
1753 static void pt (i386_operand_type);
1754 static void pe (expressionS *);
1755 static void ps (symbolS *);
1758 pi (char *line, i386_insn *x)
1762 fprintf (stdout, "%s: template ", line);
1764 fprintf (stdout, " address: base %s index %s scale %x\n",
1765 x->base_reg ? x->base_reg->reg_name : "none",
1766 x->index_reg ? x->index_reg->reg_name : "none",
1767 x->log2_scale_factor);
1768 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1769 x->rm.mode, x->rm.reg, x->rm.regmem);
1770 fprintf (stdout, " sib: base %x index %x scale %x\n",
1771 x->sib.base, x->sib.index, x->sib.scale);
1772 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1773 (x->rex & REX_W) != 0,
1774 (x->rex & REX_R) != 0,
1775 (x->rex & REX_X) != 0,
1776 (x->rex & REX_B) != 0);
1777 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1778 x->drex.reg, x->drex.rex);
1779 for (i = 0; i < x->operands; i++)
1781 fprintf (stdout, " #%d: ", i + 1);
1783 fprintf (stdout, "\n");
1784 if (x->types[i].bitfield.reg8
1785 || x->types[i].bitfield.reg16
1786 || x->types[i].bitfield.reg32
1787 || x->types[i].bitfield.reg64
1788 || x->types[i].bitfield.regmmx
1789 || x->types[i].bitfield.regxmm
1790 || x->types[i].bitfield.sreg2
1791 || x->types[i].bitfield.sreg3
1792 || x->types[i].bitfield.control
1793 || x->types[i].bitfield.debug
1794 || x->types[i].bitfield.test)
1795 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1796 if (operand_type_check (x->types[i], imm))
1798 if (operand_type_check (x->types[i], disp))
1799 pe (x->op[i].disps);
1807 fprintf (stdout, " %d operands ", t->operands);
1808 fprintf (stdout, "opcode %x ", t->base_opcode);
1809 if (t->extension_opcode != None)
1810 fprintf (stdout, "ext %x ", t->extension_opcode);
1811 if (t->opcode_modifier.d)
1812 fprintf (stdout, "D");
1813 if (t->opcode_modifier.w)
1814 fprintf (stdout, "W");
1815 fprintf (stdout, "\n");
1816 for (i = 0; i < t->operands; i++)
1818 fprintf (stdout, " #%d type ", i + 1);
1819 pt (t->operand_types[i]);
1820 fprintf (stdout, "\n");
1827 fprintf (stdout, " operation %d\n", e->X_op);
1828 fprintf (stdout, " add_number %ld (%lx)\n",
1829 (long) e->X_add_number, (long) e->X_add_number);
1830 if (e->X_add_symbol)
1832 fprintf (stdout, " add_symbol ");
1833 ps (e->X_add_symbol);
1834 fprintf (stdout, "\n");
1838 fprintf (stdout, " op_symbol ");
1839 ps (e->X_op_symbol);
1840 fprintf (stdout, "\n");
1847 fprintf (stdout, "%s type %s%s",
1849 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1850 segment_name (S_GET_SEGMENT (s)));
1853 static struct type_name
1855 i386_operand_type mask;
1858 const type_names[] =
1860 { OPERAND_TYPE_REG8, "r8" },
1861 { OPERAND_TYPE_REG16, "r16" },
1862 { OPERAND_TYPE_REG32, "r32" },
1863 { OPERAND_TYPE_REG64, "r64" },
1864 { OPERAND_TYPE_IMM8, "i8" },
1865 { OPERAND_TYPE_IMM8, "i8s" },
1866 { OPERAND_TYPE_IMM16, "i16" },
1867 { OPERAND_TYPE_IMM32, "i32" },
1868 { OPERAND_TYPE_IMM32S, "i32s" },
1869 { OPERAND_TYPE_IMM64, "i64" },
1870 { OPERAND_TYPE_IMM1, "i1" },
1871 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1872 { OPERAND_TYPE_DISP8, "d8" },
1873 { OPERAND_TYPE_DISP16, "d16" },
1874 { OPERAND_TYPE_DISP32, "d32" },
1875 { OPERAND_TYPE_DISP32S, "d32s" },
1876 { OPERAND_TYPE_DISP64, "d64" },
1877 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1878 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1879 { OPERAND_TYPE_CONTROL, "control reg" },
1880 { OPERAND_TYPE_TEST, "test reg" },
1881 { OPERAND_TYPE_DEBUG, "debug reg" },
1882 { OPERAND_TYPE_FLOATREG, "FReg" },
1883 { OPERAND_TYPE_FLOATACC, "FAcc" },
1884 { OPERAND_TYPE_SREG2, "SReg2" },
1885 { OPERAND_TYPE_SREG3, "SReg3" },
1886 { OPERAND_TYPE_ACC, "Acc" },
1887 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1888 { OPERAND_TYPE_REGMMX, "rMMX" },
1889 { OPERAND_TYPE_REGXMM, "rXMM" },
1890 { OPERAND_TYPE_ESSEG, "es" },
1894 pt (i386_operand_type t)
1897 i386_operand_type a;
1899 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1901 a = operand_type_and (t, type_names[j].mask);
1902 if (!UINTS_ALL_ZERO (a))
1903 fprintf (stdout, "%s, ", type_names[j].name);
1908 #endif /* DEBUG386 */
1910 static bfd_reloc_code_real_type
1911 reloc (unsigned int size,
1914 bfd_reloc_code_real_type other)
1916 if (other != NO_RELOC)
1918 reloc_howto_type *reloc;
1923 case BFD_RELOC_X86_64_GOT32:
1924 return BFD_RELOC_X86_64_GOT64;
1926 case BFD_RELOC_X86_64_PLTOFF64:
1927 return BFD_RELOC_X86_64_PLTOFF64;
1929 case BFD_RELOC_X86_64_GOTPC32:
1930 other = BFD_RELOC_X86_64_GOTPC64;
1932 case BFD_RELOC_X86_64_GOTPCREL:
1933 other = BFD_RELOC_X86_64_GOTPCREL64;
1935 case BFD_RELOC_X86_64_TPOFF32:
1936 other = BFD_RELOC_X86_64_TPOFF64;
1938 case BFD_RELOC_X86_64_DTPOFF32:
1939 other = BFD_RELOC_X86_64_DTPOFF64;
1945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1946 if (size == 4 && flag_code != CODE_64BIT)
1949 reloc = bfd_reloc_type_lookup (stdoutput, other);
1951 as_bad (_("unknown relocation (%u)"), other);
1952 else if (size != bfd_get_reloc_size (reloc))
1953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1954 bfd_get_reloc_size (reloc),
1956 else if (pcrel && !reloc->pc_relative)
1957 as_bad (_("non-pc-relative relocation for pc-relative field"));
1958 else if ((reloc->complain_on_overflow == complain_overflow_signed
1960 || (reloc->complain_on_overflow == complain_overflow_unsigned
1962 as_bad (_("relocated field and relocation type differ in signedness"));
1971 as_bad (_("there are no unsigned pc-relative relocations"));
1974 case 1: return BFD_RELOC_8_PCREL;
1975 case 2: return BFD_RELOC_16_PCREL;
1976 case 4: return BFD_RELOC_32_PCREL;
1977 case 8: return BFD_RELOC_64_PCREL;
1979 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1986 case 4: return BFD_RELOC_X86_64_32S;
1991 case 1: return BFD_RELOC_8;
1992 case 2: return BFD_RELOC_16;
1993 case 4: return BFD_RELOC_32;
1994 case 8: return BFD_RELOC_64;
1996 as_bad (_("cannot do %s %u byte relocation"),
1997 sign > 0 ? "signed" : "unsigned", size);
2001 return BFD_RELOC_NONE;
2004 /* Here we decide which fixups can be adjusted to make them relative to
2005 the beginning of the section instead of the symbol. Basically we need
2006 to make sure that the dynamic relocations are done correctly, so in
2007 some cases we force the original symbol to be used. */
2010 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2016 /* Don't adjust pc-relative references to merge sections in 64-bit
2018 if (use_rela_relocations
2019 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2023 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2024 and changed later by validate_fix. */
2025 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2026 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2029 /* adjust_reloc_syms doesn't know about the GOT. */
2030 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2031 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2032 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2053 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2055 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2056 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2064 intel_float_operand (const char *mnemonic)
2066 /* Note that the value returned is meaningful only for opcodes with (memory)
2067 operands, hence the code here is free to improperly handle opcodes that
2068 have no operands (for better performance and smaller code). */
2070 if (mnemonic[0] != 'f')
2071 return 0; /* non-math */
2073 switch (mnemonic[1])
2075 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2076 the fs segment override prefix not currently handled because no
2077 call path can make opcodes without operands get here */
2079 return 2 /* integer op */;
2081 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2082 return 3; /* fldcw/fldenv */
2085 if (mnemonic[2] != 'o' /* fnop */)
2086 return 3; /* non-waiting control op */
2089 if (mnemonic[2] == 's')
2090 return 3; /* frstor/frstpm */
2093 if (mnemonic[2] == 'a')
2094 return 3; /* fsave */
2095 if (mnemonic[2] == 't')
2097 switch (mnemonic[3])
2099 case 'c': /* fstcw */
2100 case 'd': /* fstdw */
2101 case 'e': /* fstenv */
2102 case 's': /* fsts[gw] */
2108 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2109 return 0; /* fxsave/fxrstor are not really math ops */
2116 /* This is the guts of the machine-dependent assembler. LINE points to a
2117 machine dependent instruction. This function is supposed to emit
2118 the frags/bytes it assembles to. */
2125 char mnemonic[MAX_MNEM_SIZE];
2127 /* Initialize globals. */
2128 memset (&i, '\0', sizeof (i));
2129 for (j = 0; j < MAX_OPERANDS; j++)
2130 i.reloc[j] = NO_RELOC;
2131 memset (disp_expressions, '\0', sizeof (disp_expressions));
2132 memset (im_expressions, '\0', sizeof (im_expressions));
2133 save_stack_p = save_stack;
2135 /* First parse an instruction mnemonic & call i386_operand for the operands.
2136 We assume that the scrubber has arranged it so that line[0] is the valid
2137 start of a (possibly prefixed) mnemonic. */
2139 line = parse_insn (line, mnemonic);
2143 line = parse_operands (line, mnemonic);
2147 /* Now we've parsed the mnemonic into a set of templates, and have the
2148 operands at hand. */
2150 /* All intel opcodes have reversed operands except for "bound" and
2151 "enter". We also don't reverse intersegment "jmp" and "call"
2152 instructions with 2 immediate operands so that the immediate segment
2153 precedes the offset, as it does when in AT&T mode. */
2156 && (strcmp (mnemonic, "bound") != 0)
2157 && (strcmp (mnemonic, "invlpga") != 0)
2158 && !(operand_type_check (i.types[0], imm)
2159 && operand_type_check (i.types[1], imm)))
2162 /* The order of the immediates should be reversed
2163 for 2 immediates extrq and insertq instructions */
2164 if (i.imm_operands == 2
2165 && (strcmp (mnemonic, "extrq") == 0
2166 || strcmp (mnemonic, "insertq") == 0))
2167 swap_2_operands (0, 1);
2172 /* Don't optimize displacement for movabs since it only takes 64bit
2175 && (flag_code != CODE_64BIT
2176 || strcmp (mnemonic, "movabs") != 0))
2179 /* Next, we find a template that matches the given insn,
2180 making sure the overlap of the given operands types is consistent
2181 with the template operand types. */
2183 if (!match_template ())
2188 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2190 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
2191 i.tm.base_opcode ^= Opcode_FloatR;
2193 /* Zap movzx and movsx suffix. The suffix may have been set from
2194 "word ptr" or "byte ptr" on the source operand, but we'll use
2195 the suffix later to choose the destination register. */
2196 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2198 if (i.reg_operands < 2
2200 && (!i.tm.opcode_modifier.no_bsuf
2201 || !i.tm.opcode_modifier.no_wsuf
2202 || !i.tm.opcode_modifier.no_lsuf
2203 || !i.tm.opcode_modifier.no_ssuf
2204 || !i.tm.opcode_modifier.no_xsuf
2205 || !i.tm.opcode_modifier.no_qsuf))
2206 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2212 if (i.tm.opcode_modifier.fwait)
2213 if (!add_prefix (FWAIT_OPCODE))
2216 /* Check string instruction segment overrides. */
2217 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2219 if (!check_string ())
2223 if (!process_suffix ())
2226 /* Make still unresolved immediate matches conform to size of immediate
2227 given in i.suffix. */
2228 if (!finalize_imm ())
2231 if (i.types[0].bitfield.imm1)
2232 i.imm_operands = 0; /* kludge for shift insns. */
2234 for (j = 0; j < 3; j++)
2235 if (i.types[j].bitfield.inoutportreg
2236 || i.types[j].bitfield.shiftcount
2237 || i.types[j].bitfield.acc
2238 || i.types[j].bitfield.floatacc)
2241 if (i.tm.opcode_modifier.immext)
2245 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2247 /* Streaming SIMD extensions 3 Instructions have the fixed
2248 operands with an opcode suffix which is coded in the same
2249 place as an 8-bit immediate field would be. Here we check
2250 those operands and remove them afterwards. */
2253 for (x = 0; x < i.operands; x++)
2254 if (i.op[x].regs->reg_num != x)
2255 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2257 i.op[x].regs->reg_name,
2263 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2264 opcode suffix which is coded in the same place as an 8-bit
2265 immediate field would be. Here we fake an 8-bit immediate
2266 operand from the opcode suffix stored in tm.extension_opcode.
2267 SSE5 also uses this encoding, for some of its 3 argument
2270 assert (i.imm_operands == 0
2272 || (i.tm.cpu_flags.bitfield.cpusse5
2273 && i.operands <= 3)));
2275 exp = &im_expressions[i.imm_operands++];
2276 i.op[i.operands].imms = exp;
2277 UINTS_CLEAR (i.types[i.operands]);
2278 i.types[i.operands].bitfield.imm8 = 1;
2280 exp->X_op = O_constant;
2281 exp->X_add_number = i.tm.extension_opcode;
2282 i.tm.extension_opcode = None;
2285 /* For insns with operands there are more diddles to do to the opcode. */
2288 if (!process_operands ())
2291 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2293 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2294 as_warn (_("translating to `%sp'"), i.tm.name);
2297 /* Handle conversion of 'int $3' --> special int3 insn. */
2298 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2300 i.tm.base_opcode = INT3_OPCODE;
2304 if ((i.tm.opcode_modifier.jump
2305 || i.tm.opcode_modifier.jumpbyte
2306 || i.tm.opcode_modifier.jumpdword)
2307 && i.op[0].disps->X_op == O_constant)
2309 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2310 the absolute address given by the constant. Since ix86 jumps and
2311 calls are pc relative, we need to generate a reloc. */
2312 i.op[0].disps->X_add_symbol = &abs_symbol;
2313 i.op[0].disps->X_op = O_symbol;
2316 if (i.tm.opcode_modifier.rex64)
2319 /* For 8 bit registers we need an empty rex prefix. Also if the
2320 instruction already has a prefix, we need to convert old
2321 registers to new ones. */
2323 if ((i.types[0].bitfield.reg8
2324 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2325 || (i.types[1].bitfield.reg8
2326 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2327 || ((i.types[0].bitfield.reg8
2328 || i.types[1].bitfield.reg8)
2333 i.rex |= REX_OPCODE;
2334 for (x = 0; x < 2; x++)
2336 /* Look for 8 bit operand that uses old registers. */
2337 if (i.types[x].bitfield.reg8
2338 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2340 /* In case it is "hi" register, give up. */
2341 if (i.op[x].regs->reg_num > 3)
2342 as_bad (_("can't encode register '%s%s' in an "
2343 "instruction requiring REX prefix."),
2344 register_prefix, i.op[x].regs->reg_name);
2346 /* Otherwise it is equivalent to the extended register.
2347 Since the encoding doesn't change this is merely
2348 cosmetic cleanup for debug output. */
2350 i.op[x].regs = i.op[x].regs + 8;
2355 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2357 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2362 else if (i.rex != 0)
2363 add_prefix (REX_OPCODE | i.rex);
2365 /* We are ready to output the insn. */
2370 parse_insn (char *line, char *mnemonic)
2373 char *token_start = l;
2378 /* Non-zero if we found a prefix only acceptable with string insns. */
2379 const char *expecting_string_instruction = NULL;
2384 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2387 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2389 as_bad (_("no such instruction: `%s'"), token_start);
2394 if (!is_space_char (*l)
2395 && *l != END_OF_INSN
2397 || (*l != PREFIX_SEPARATOR
2400 as_bad (_("invalid character %s in mnemonic"),
2401 output_invalid (*l));
2404 if (token_start == l)
2406 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2407 as_bad (_("expecting prefix; got nothing"));
2409 as_bad (_("expecting mnemonic; got nothing"));
2413 /* Look up instruction (or prefix) via hash table. */
2414 current_templates = hash_find (op_hash, mnemonic);
2416 if (*l != END_OF_INSN
2417 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2418 && current_templates
2419 && current_templates->start->opcode_modifier.isprefix)
2421 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2423 as_bad ((flag_code != CODE_64BIT
2424 ? _("`%s' is only supported in 64-bit mode")
2425 : _("`%s' is not supported in 64-bit mode")),
2426 current_templates->start->name);
2429 /* If we are in 16-bit mode, do not allow addr16 or data16.
2430 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2431 if ((current_templates->start->opcode_modifier.size16
2432 || current_templates->start->opcode_modifier.size32)
2433 && flag_code != CODE_64BIT
2434 && (current_templates->start->opcode_modifier.size32
2435 ^ (flag_code == CODE_16BIT)))
2437 as_bad (_("redundant %s prefix"),
2438 current_templates->start->name);
2441 /* Add prefix, checking for repeated prefixes. */
2442 switch (add_prefix (current_templates->start->base_opcode))
2447 expecting_string_instruction = current_templates->start->name;
2450 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2457 if (!current_templates)
2459 /* See if we can get a match by trimming off a suffix. */
2462 case WORD_MNEM_SUFFIX:
2463 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2464 i.suffix = SHORT_MNEM_SUFFIX;
2466 case BYTE_MNEM_SUFFIX:
2467 case QWORD_MNEM_SUFFIX:
2468 i.suffix = mnem_p[-1];
2470 current_templates = hash_find (op_hash, mnemonic);
2472 case SHORT_MNEM_SUFFIX:
2473 case LONG_MNEM_SUFFIX:
2476 i.suffix = mnem_p[-1];
2478 current_templates = hash_find (op_hash, mnemonic);
2486 if (intel_float_operand (mnemonic) == 1)
2487 i.suffix = SHORT_MNEM_SUFFIX;
2489 i.suffix = LONG_MNEM_SUFFIX;
2491 current_templates = hash_find (op_hash, mnemonic);
2495 if (!current_templates)
2497 as_bad (_("no such instruction: `%s'"), token_start);
2502 if (current_templates->start->opcode_modifier.jump
2503 || current_templates->start->opcode_modifier.jumpbyte)
2505 /* Check for a branch hint. We allow ",pt" and ",pn" for
2506 predict taken and predict not taken respectively.
2507 I'm not sure that branch hints actually do anything on loop
2508 and jcxz insns (JumpByte) for current Pentium4 chips. They
2509 may work in the future and it doesn't hurt to accept them
2511 if (l[0] == ',' && l[1] == 'p')
2515 if (!add_prefix (DS_PREFIX_OPCODE))
2519 else if (l[2] == 'n')
2521 if (!add_prefix (CS_PREFIX_OPCODE))
2527 /* Any other comma loses. */
2530 as_bad (_("invalid character %s in mnemonic"),
2531 output_invalid (*l));
2535 /* Check if instruction is supported on specified architecture. */
2537 for (t = current_templates->start; t < current_templates->end; ++t)
2539 if (cpu_flags_match (t->cpu_flags))
2541 if (cpu_flags_check_cpu64 (t->cpu_flags))
2544 if (!(supported & 2))
2546 as_bad (flag_code == CODE_64BIT
2547 ? _("`%s' is not supported in 64-bit mode")
2548 : _("`%s' is only supported in 64-bit mode"),
2549 current_templates->start->name);
2552 if (!(supported & 1))
2554 as_warn (_("`%s' is not supported on `%s%s'"),
2555 current_templates->start->name,
2557 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2559 else if (!cpu_arch_flags.bitfield.cpui386
2560 && (flag_code != CODE_16BIT))
2562 as_warn (_("use .code16 to ensure correct addressing mode"));
2565 /* Check for rep/repne without a string instruction. */
2566 if (expecting_string_instruction)
2568 static templates override;
2570 for (t = current_templates->start; t < current_templates->end; ++t)
2571 if (t->opcode_modifier.isstring)
2573 if (t >= current_templates->end)
2575 as_bad (_("expecting string instruction after `%s'"),
2576 expecting_string_instruction);
2579 for (override.start = t; t < current_templates->end; ++t)
2580 if (!t->opcode_modifier.isstring)
2583 current_templates = &override;
2590 parse_operands (char *l, const char *mnemonic)
2594 /* 1 if operand is pending after ','. */
2595 unsigned int expecting_operand = 0;
2597 /* Non-zero if operand parens not balanced. */
2598 unsigned int paren_not_balanced;
2600 while (*l != END_OF_INSN)
2602 /* Skip optional white space before operand. */
2603 if (is_space_char (*l))
2605 if (!is_operand_char (*l) && *l != END_OF_INSN)
2607 as_bad (_("invalid character %s before operand %d"),
2608 output_invalid (*l),
2612 token_start = l; /* after white space */
2613 paren_not_balanced = 0;
2614 while (paren_not_balanced || *l != ',')
2616 if (*l == END_OF_INSN)
2618 if (paren_not_balanced)
2621 as_bad (_("unbalanced parenthesis in operand %d."),
2624 as_bad (_("unbalanced brackets in operand %d."),
2629 break; /* we are done */
2631 else if (!is_operand_char (*l) && !is_space_char (*l))
2633 as_bad (_("invalid character %s in operand %d"),
2634 output_invalid (*l),
2641 ++paren_not_balanced;
2643 --paren_not_balanced;
2648 ++paren_not_balanced;
2650 --paren_not_balanced;
2654 if (l != token_start)
2655 { /* Yes, we've read in another operand. */
2656 unsigned int operand_ok;
2657 this_operand = i.operands++;
2658 if (i.operands > MAX_OPERANDS)
2660 as_bad (_("spurious operands; (%d operands/instruction max)"),
2664 /* Now parse operand adding info to 'i' as we go along. */
2665 END_STRING_AND_SAVE (l);
2669 i386_intel_operand (token_start,
2670 intel_float_operand (mnemonic));
2672 operand_ok = i386_operand (token_start);
2674 RESTORE_END_STRING (l);
2680 if (expecting_operand)
2682 expecting_operand_after_comma:
2683 as_bad (_("expecting operand after ','; got nothing"));
2688 as_bad (_("expecting operand before ','; got nothing"));
2693 /* Now *l must be either ',' or END_OF_INSN. */
2696 if (*++l == END_OF_INSN)
2698 /* Just skip it, if it's \n complain. */
2699 goto expecting_operand_after_comma;
2701 expecting_operand = 1;
2708 swap_2_operands (int xchg1, int xchg2)
2710 union i386_op temp_op;
2711 i386_operand_type temp_type;
2712 enum bfd_reloc_code_real temp_reloc;
2714 temp_type = i.types[xchg2];
2715 i.types[xchg2] = i.types[xchg1];
2716 i.types[xchg1] = temp_type;
2717 temp_op = i.op[xchg2];
2718 i.op[xchg2] = i.op[xchg1];
2719 i.op[xchg1] = temp_op;
2720 temp_reloc = i.reloc[xchg2];
2721 i.reloc[xchg2] = i.reloc[xchg1];
2722 i.reloc[xchg1] = temp_reloc;
2726 swap_operands (void)
2731 swap_2_operands (1, i.operands - 2);
2734 swap_2_operands (0, i.operands - 1);
2740 if (i.mem_operands == 2)
2742 const seg_entry *temp_seg;
2743 temp_seg = i.seg[0];
2744 i.seg[0] = i.seg[1];
2745 i.seg[1] = temp_seg;
2749 /* Try to ensure constant immediates are represented in the smallest
2754 char guess_suffix = 0;
2758 guess_suffix = i.suffix;
2759 else if (i.reg_operands)
2761 /* Figure out a suffix from the last register operand specified.
2762 We can't do this properly yet, ie. excluding InOutPortReg,
2763 but the following works for instructions with immediates.
2764 In any case, we can't set i.suffix yet. */
2765 for (op = i.operands; --op >= 0;)
2766 if (i.types[op].bitfield.reg8)
2768 guess_suffix = BYTE_MNEM_SUFFIX;
2771 else if (i.types[op].bitfield.reg16)
2773 guess_suffix = WORD_MNEM_SUFFIX;
2776 else if (i.types[op].bitfield.reg32)
2778 guess_suffix = LONG_MNEM_SUFFIX;
2781 else if (i.types[op].bitfield.reg64)
2783 guess_suffix = QWORD_MNEM_SUFFIX;
2787 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2788 guess_suffix = WORD_MNEM_SUFFIX;
2790 for (op = i.operands; --op >= 0;)
2791 if (operand_type_check (i.types[op], imm))
2793 switch (i.op[op].imms->X_op)
2796 /* If a suffix is given, this operand may be shortened. */
2797 switch (guess_suffix)
2799 case LONG_MNEM_SUFFIX:
2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm64 = 1;
2803 case WORD_MNEM_SUFFIX:
2804 i.types[op].bitfield.imm16 = 1;
2805 i.types[op].bitfield.imm32 = 1;
2806 i.types[op].bitfield.imm32s = 1;
2807 i.types[op].bitfield.imm64 = 1;
2809 case BYTE_MNEM_SUFFIX:
2810 i.types[op].bitfield.imm8 = 1;
2811 i.types[op].bitfield.imm8s = 1;
2812 i.types[op].bitfield.imm16 = 1;
2813 i.types[op].bitfield.imm32 = 1;
2814 i.types[op].bitfield.imm32s = 1;
2815 i.types[op].bitfield.imm64 = 1;
2819 /* If this operand is at most 16 bits, convert it
2820 to a signed 16 bit number before trying to see
2821 whether it will fit in an even smaller size.
2822 This allows a 16-bit operand such as $0xffe0 to
2823 be recognised as within Imm8S range. */
2824 if ((i.types[op].bitfield.imm16)
2825 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2827 i.op[op].imms->X_add_number =
2828 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2830 if ((i.types[op].bitfield.imm32)
2831 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2834 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2835 ^ ((offsetT) 1 << 31))
2836 - ((offsetT) 1 << 31));
2839 = operand_type_or (i.types[op],
2840 smallest_imm_type (i.op[op].imms->X_add_number));
2842 /* We must avoid matching of Imm32 templates when 64bit
2843 only immediate is available. */
2844 if (guess_suffix == QWORD_MNEM_SUFFIX)
2845 i.types[op].bitfield.imm32 = 0;
2852 /* Symbols and expressions. */
2854 /* Convert symbolic operand to proper sizes for matching, but don't
2855 prevent matching a set of insns that only supports sizes other
2856 than those matching the insn suffix. */
2858 i386_operand_type mask, allowed;
2862 UINTS_CLEAR (allowed);
2864 for (t = current_templates->start;
2865 t < current_templates->end;
2867 allowed = operand_type_or (allowed,
2868 t->operand_types[op]);
2869 switch (guess_suffix)
2871 case QWORD_MNEM_SUFFIX:
2872 mask.bitfield.imm64 = 1;
2873 mask.bitfield.imm32s = 1;
2875 case LONG_MNEM_SUFFIX:
2876 mask.bitfield.imm32 = 1;
2878 case WORD_MNEM_SUFFIX:
2879 mask.bitfield.imm16 = 1;
2881 case BYTE_MNEM_SUFFIX:
2882 mask.bitfield.imm8 = 1;
2887 allowed = operand_type_and (mask, allowed);
2888 if (!UINTS_ALL_ZERO (allowed))
2889 i.types[op] = operand_type_and (i.types[op], mask);
2896 /* Try to use the smallest displacement type too. */
2898 optimize_disp (void)
2902 for (op = i.operands; --op >= 0;)
2903 if (operand_type_check (i.types[op], disp))
2905 if (i.op[op].disps->X_op == O_constant)
2907 offsetT disp = i.op[op].disps->X_add_number;
2909 if (i.types[op].bitfield.disp16
2910 && (disp & ~(offsetT) 0xffff) == 0)
2912 /* If this operand is at most 16 bits, convert
2913 to a signed 16 bit number and don't use 64bit
2915 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2916 i.types[op].bitfield.disp64 = 0;
2918 if (i.types[op].bitfield.disp32
2919 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2921 /* If this operand is at most 32 bits, convert
2922 to a signed 32 bit number and don't use 64bit
2924 disp &= (((offsetT) 2 << 31) - 1);
2925 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2926 i.types[op].bitfield.disp64 = 0;
2928 if (!disp && i.types[op].bitfield.baseindex)
2930 i.types[op].bitfield.disp8 = 0;
2931 i.types[op].bitfield.disp16 = 0;
2932 i.types[op].bitfield.disp32 = 0;
2933 i.types[op].bitfield.disp32s = 0;
2934 i.types[op].bitfield.disp64 = 0;
2938 else if (flag_code == CODE_64BIT)
2940 if (fits_in_signed_long (disp))
2942 i.types[op].bitfield.disp64 = 0;
2943 i.types[op].bitfield.disp32s = 1;
2945 if (fits_in_unsigned_long (disp))
2946 i.types[op].bitfield.disp32 = 1;
2948 if ((i.types[op].bitfield.disp32
2949 || i.types[op].bitfield.disp32s
2950 || i.types[op].bitfield.disp16)
2951 && fits_in_signed_byte (disp))
2952 i.types[op].bitfield.disp8 = 1;
2954 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2955 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2957 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2958 i.op[op].disps, 0, i.reloc[op]);
2959 i.types[op].bitfield.disp8 = 0;
2960 i.types[op].bitfield.disp16 = 0;
2961 i.types[op].bitfield.disp32 = 0;
2962 i.types[op].bitfield.disp32s = 0;
2963 i.types[op].bitfield.disp64 = 0;
2966 /* We only support 64bit displacement on constants. */
2967 i.types[op].bitfield.disp64 = 0;
2972 match_template (void)
2974 /* Points to template once we've found it. */
2976 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2977 unsigned int found_reverse_match;
2978 i386_opcode_modifier suffix_check;
2979 i386_operand_type operand_types [MAX_OPERANDS];
2980 int addr_prefix_disp;
2982 i386_cpu_flags overlap;
2984 #if MAX_OPERANDS != 4
2985 # error "MAX_OPERANDS must be 4."
2988 found_reverse_match = 0;
2989 addr_prefix_disp = -1;
2991 memset (&suffix_check, 0, sizeof (suffix_check));
2992 if (i.suffix == BYTE_MNEM_SUFFIX)
2993 suffix_check.no_bsuf = 1;
2994 else if (i.suffix == WORD_MNEM_SUFFIX)
2995 suffix_check.no_wsuf = 1;
2996 else if (i.suffix == SHORT_MNEM_SUFFIX)
2997 suffix_check.no_ssuf = 1;
2998 else if (i.suffix == LONG_MNEM_SUFFIX)
2999 suffix_check.no_lsuf = 1;
3000 else if (i.suffix == QWORD_MNEM_SUFFIX)
3001 suffix_check.no_qsuf = 1;
3002 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3003 suffix_check.no_xsuf = 1;
3005 for (t = current_templates->start; t < current_templates->end; t++)
3007 addr_prefix_disp = -1;
3009 /* Must have right number of operands. */
3010 if (i.operands != t->operands)
3013 /* Check the suffix, except for some instructions in intel mode. */
3014 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3015 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3016 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3017 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3018 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3019 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3020 && !(intel_syntax && t->opcode_modifier.ignoresize))
3023 for (j = 0; j < MAX_OPERANDS; j++)
3024 operand_types [j] = t->operand_types [j];
3026 /* In general, don't allow 64-bit operands in 32-bit mode. */
3027 if (i.suffix == QWORD_MNEM_SUFFIX
3028 && flag_code != CODE_64BIT
3030 ? (!t->opcode_modifier.ignoresize
3031 && !intel_float_operand (t->name))
3032 : intel_float_operand (t->name) != 2)
3033 && ((!operand_types[0].bitfield.regmmx
3034 && !operand_types[0].bitfield.regxmm)
3035 || (!operand_types[t->operands > 1].bitfield.regmmx
3036 && !!operand_types[t->operands > 1].bitfield.regxmm))
3037 && (t->base_opcode != 0x0fc7
3038 || t->extension_opcode != 1 /* cmpxchg8b */))
3041 /* Do not verify operands when there are none. */
3044 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3047 if (!UINTS_ALL_ZERO (overlap))
3049 /* We've found a match; break out of loop. */
3054 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3055 into Disp32/Disp16/Disp32 operand. */
3056 if (i.prefix[ADDR_PREFIX] != 0)
3058 /* There should be only one Disp operand. */
3062 for (j = 0; j < MAX_OPERANDS; j++)
3064 if (operand_types[j].bitfield.disp16)
3066 addr_prefix_disp = j;
3067 operand_types[j].bitfield.disp32 = 1;
3068 operand_types[j].bitfield.disp16 = 0;
3074 for (j = 0; j < MAX_OPERANDS; j++)
3076 if (operand_types[j].bitfield.disp32)
3078 addr_prefix_disp = j;
3079 operand_types[j].bitfield.disp32 = 0;
3080 operand_types[j].bitfield.disp16 = 1;
3086 for (j = 0; j < MAX_OPERANDS; j++)
3088 if (operand_types[j].bitfield.disp64)
3090 addr_prefix_disp = j;
3091 operand_types[j].bitfield.disp64 = 0;
3092 operand_types[j].bitfield.disp32 = 1;
3100 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3101 switch (t->operands)
3104 if (!operand_type_match (overlap0, i.types[0]))
3108 /* xchg %eax, %eax is a special case. It is an aliase for nop
3109 only in 32bit mode and we can use opcode 0x90. In 64bit
3110 mode, we can't use 0x90 for xchg %eax, %eax since it should
3111 zero-extend %eax to %rax. */
3112 if (flag_code == CODE_64BIT
3113 && t->base_opcode == 0x90
3114 && UINTS_EQUAL (i.types [0], acc32)
3115 && UINTS_EQUAL (i.types [1], acc32))
3119 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3120 if (!operand_type_match (overlap0, i.types[0])
3121 || !operand_type_match (overlap1, i.types[1])
3122 /* monitor in SSE3 is a very special case. The first
3123 register and the second register may have different
3124 sizes. The same applies to crc32 in SSE4.2. It is
3125 also true for invlpga, vmload, vmrun and vmsave in
3127 || !((t->base_opcode == 0x0f01
3128 && (t->extension_opcode == 0xc8
3129 || t->extension_opcode == 0xd8
3130 || t->extension_opcode == 0xda
3131 || t->extension_opcode == 0xdb
3132 || t->extension_opcode == 0xdf))
3133 || t->base_opcode == 0xf20f38f1
3134 || operand_type_register_match (overlap0, i.types[0],
3136 overlap1, i.types[1],
3139 /* Check if other direction is valid ... */
3140 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3143 /* Try reversing direction of operands. */
3144 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3145 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3146 if (!operand_type_match (overlap0, i.types[0])
3147 || !operand_type_match (overlap1, i.types[1])
3148 || !operand_type_register_match (overlap0, i.types[0],
3150 overlap1, i.types[1],
3153 /* Does not match either direction. */
3156 /* found_reverse_match holds which of D or FloatDR
3158 if (t->opcode_modifier.d)
3159 found_reverse_match = Opcode_D;
3160 else if (t->opcode_modifier.floatd)
3161 found_reverse_match = Opcode_FloatD;
3163 found_reverse_match = 0;
3164 if (t->opcode_modifier.floatr)
3165 found_reverse_match |= Opcode_FloatR;
3169 /* Found a forward 2 operand match here. */
3170 switch (t->operands)
3173 overlap3 = operand_type_and (i.types[3],
3176 overlap2 = operand_type_and (i.types[2],
3181 switch (t->operands)
3184 if (!operand_type_match (overlap3, i.types[3])
3185 || !operand_type_register_match (overlap2,
3193 /* Here we make use of the fact that there are no
3194 reverse match 3 operand instructions, and all 3
3195 operand instructions only need to be checked for
3196 register consistency between operands 2 and 3. */
3197 if (!operand_type_match (overlap2, i.types[2])
3198 || !operand_type_register_match (overlap1,
3208 /* Found either forward/reverse 2, 3 or 4 operand match here:
3209 slip through to break. */
3211 if (!UINTS_ALL_ZERO (overlap))
3213 found_reverse_match = 0;
3216 /* We've found a match; break out of loop. */
3220 if (t == current_templates->end)
3222 /* We found no match. */
3223 as_bad (_("suffix or operands invalid for `%s'"),
3224 current_templates->start->name);
3228 if (!quiet_warnings)
3231 && (i.types[0].bitfield.jumpabsolute
3232 != operand_types[0].bitfield.jumpabsolute))
3234 as_warn (_("indirect %s without `*'"), t->name);
3237 if (t->opcode_modifier.isprefix
3238 && t->opcode_modifier.ignoresize)
3240 /* Warn them that a data or address size prefix doesn't
3241 affect assembly of the next line of code. */
3242 as_warn (_("stand-alone `%s' prefix"), t->name);
3246 /* Copy the template we found. */
3249 if (addr_prefix_disp != -1)
3250 i.tm.operand_types[addr_prefix_disp]
3251 = operand_types[addr_prefix_disp];
3253 if (found_reverse_match)
3255 /* If we found a reverse match we must alter the opcode
3256 direction bit. found_reverse_match holds bits to change
3257 (different for int & float insns). */
3259 i.tm.base_opcode ^= found_reverse_match;
3261 i.tm.operand_types[0] = operand_types[1];
3262 i.tm.operand_types[1] = operand_types[0];
3271 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3272 if (i.tm.operand_types[mem_op].bitfield.esseg)
3274 if (i.seg[0] != NULL && i.seg[0] != &es)
3276 as_bad (_("`%s' operand %d must use `%%es' segment"),
3281 /* There's only ever one segment override allowed per instruction.
3282 This instruction possibly has a legal segment override on the
3283 second operand, so copy the segment to where non-string
3284 instructions store it, allowing common code. */
3285 i.seg[0] = i.seg[1];
3287 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3289 if (i.seg[1] != NULL && i.seg[1] != &es)
3291 as_bad (_("`%s' operand %d must use `%%es' segment"),
3301 process_suffix (void)
3303 /* If matched instruction specifies an explicit instruction mnemonic
3305 if (i.tm.opcode_modifier.size16)
3306 i.suffix = WORD_MNEM_SUFFIX;
3307 else if (i.tm.opcode_modifier.size32)
3308 i.suffix = LONG_MNEM_SUFFIX;
3309 else if (i.tm.opcode_modifier.size64)
3310 i.suffix = QWORD_MNEM_SUFFIX;
3311 else if (i.reg_operands)
3313 /* If there's no instruction mnemonic suffix we try to invent one
3314 based on register operands. */
3317 /* We take i.suffix from the last register operand specified,
3318 Destination register type is more significant than source
3319 register type. crc32 in SSE4.2 prefers source register
3321 if (i.tm.base_opcode == 0xf20f38f1)
3323 if (i.types[0].bitfield.reg16)
3324 i.suffix = WORD_MNEM_SUFFIX;
3325 else if (i.types[0].bitfield.reg32)
3326 i.suffix = LONG_MNEM_SUFFIX;
3327 else if (i.types[0].bitfield.reg64)
3328 i.suffix = QWORD_MNEM_SUFFIX;
3330 else if (i.tm.base_opcode == 0xf20f38f0)
3332 if (i.types[0].bitfield.reg8)
3333 i.suffix = BYTE_MNEM_SUFFIX;
3340 if (i.tm.base_opcode == 0xf20f38f1
3341 || i.tm.base_opcode == 0xf20f38f0)
3343 /* We have to know the operand size for crc32. */
3344 as_bad (_("ambiguous memory operand size for `%s`"),
3349 for (op = i.operands; --op >= 0;)
3350 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3352 if (i.types[op].bitfield.reg8)
3354 i.suffix = BYTE_MNEM_SUFFIX;
3357 else if (i.types[op].bitfield.reg16)
3359 i.suffix = WORD_MNEM_SUFFIX;
3362 else if (i.types[op].bitfield.reg32)
3364 i.suffix = LONG_MNEM_SUFFIX;
3367 else if (i.types[op].bitfield.reg64)
3369 i.suffix = QWORD_MNEM_SUFFIX;
3375 else if (i.suffix == BYTE_MNEM_SUFFIX)
3377 if (!check_byte_reg ())
3380 else if (i.suffix == LONG_MNEM_SUFFIX)
3382 if (!check_long_reg ())
3385 else if (i.suffix == QWORD_MNEM_SUFFIX)
3388 && i.tm.opcode_modifier.ignoresize
3389 && i.tm.opcode_modifier.no_qsuf)
3391 else if (!check_qword_reg ())
3394 else if (i.suffix == WORD_MNEM_SUFFIX)
3396 if (!check_word_reg ())
3399 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3400 /* Do nothing if the instruction is going to ignore the prefix. */
3405 else if (i.tm.opcode_modifier.defaultsize
3407 /* exclude fldenv/frstor/fsave/fstenv */
3408 && i.tm.opcode_modifier.no_ssuf)
3410 i.suffix = stackop_size;
3412 else if (intel_syntax
3414 && (i.tm.operand_types[0].bitfield.jumpabsolute
3415 || i.tm.opcode_modifier.jumpbyte
3416 || i.tm.opcode_modifier.jumpintersegment
3417 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3418 && i.tm.extension_opcode <= 3)))
3423 if (!i.tm.opcode_modifier.no_qsuf)
3425 i.suffix = QWORD_MNEM_SUFFIX;
3429 if (!i.tm.opcode_modifier.no_lsuf)
3430 i.suffix = LONG_MNEM_SUFFIX;
3433 if (!i.tm.opcode_modifier.no_wsuf)
3434 i.suffix = WORD_MNEM_SUFFIX;
3443 if (i.tm.opcode_modifier.w)
3445 as_bad (_("no instruction mnemonic suffix given and "
3446 "no register operands; can't size instruction"));
3452 unsigned int suffixes;
3454 suffixes = !i.tm.opcode_modifier.no_bsuf;
3455 if (!i.tm.opcode_modifier.no_wsuf)
3457 if (!i.tm.opcode_modifier.no_lsuf)
3459 if (!i.tm.opcode_modifier.no_lsuf)
3461 if (!i.tm.opcode_modifier.no_ssuf)
3463 if (!i.tm.opcode_modifier.no_qsuf)
3466 /* There are more than suffix matches. */
3467 if (i.tm.opcode_modifier.w
3468 || ((suffixes & (suffixes - 1))
3469 && !i.tm.opcode_modifier.defaultsize
3470 && !i.tm.opcode_modifier.ignoresize))
3472 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3478 /* Change the opcode based on the operand size given by i.suffix;
3479 We don't need to change things for byte insns. */
3481 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3483 /* It's not a byte, select word/dword operation. */
3484 if (i.tm.opcode_modifier.w)
3486 if (i.tm.opcode_modifier.shortform)
3487 i.tm.base_opcode |= 8;
3489 i.tm.base_opcode |= 1;
3492 /* Now select between word & dword operations via the operand
3493 size prefix, except for instructions that will ignore this
3495 if (i.tm.base_opcode == 0x0f01
3496 && (i.tm.extension_opcode == 0xc8
3497 || i.tm.extension_opcode == 0xd8
3498 || i.tm.extension_opcode == 0xda
3499 || i.tm.extension_opcode == 0xdb
3500 || i.tm.extension_opcode == 0xdf))
3502 /* monitor in SSE3 is a very special case. The default size
3503 of AX is the size of mode. The address size override
3504 prefix will change the size of AX. It is also true for
3505 invlpga, vmload, vmrun and vmsave in SVME. */
3506 if ((flag_code == CODE_32BIT
3507 && i.op->regs[0].reg_type.bitfield.reg16)
3508 || (flag_code != CODE_32BIT
3509 && i.op->regs[0].reg_type.bitfield.reg32))
3510 if (!add_prefix (ADDR_PREFIX_OPCODE))
3513 else if (i.suffix != QWORD_MNEM_SUFFIX
3514 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3515 && !i.tm.opcode_modifier.ignoresize
3516 && !i.tm.opcode_modifier.floatmf
3517 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3518 || (flag_code == CODE_64BIT
3519 && i.tm.opcode_modifier.jumpbyte)))
3521 unsigned int prefix = DATA_PREFIX_OPCODE;
3523 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3524 prefix = ADDR_PREFIX_OPCODE;
3526 if (!add_prefix (prefix))
3530 /* Set mode64 for an operand. */
3531 if (i.suffix == QWORD_MNEM_SUFFIX
3532 && flag_code == CODE_64BIT
3533 && !i.tm.opcode_modifier.norex64)
3535 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3536 need rex64. cmpxchg8b is also a special case. */
3537 if (! (i.operands == 2
3538 && i.tm.base_opcode == 0x90
3539 && i.tm.extension_opcode == None
3540 && UINTS_EQUAL (i.types [0], acc64)
3541 && UINTS_EQUAL (i.types [1], acc64))
3542 && ! (i.operands == 1
3543 && i.tm.base_opcode == 0xfc7
3544 && i.tm.extension_opcode == 1
3545 && !operand_type_check (i.types [0], reg)
3546 && operand_type_check (i.types [0], anymem)))
3550 /* Size floating point instruction. */
3551 if (i.suffix == LONG_MNEM_SUFFIX)
3552 if (i.tm.opcode_modifier.floatmf)
3553 i.tm.base_opcode ^= 4;
3560 check_byte_reg (void)
3564 for (op = i.operands; --op >= 0;)
3566 /* If this is an eight bit register, it's OK. If it's the 16 or
3567 32 bit version of an eight bit register, we will just use the
3568 low portion, and that's OK too. */
3569 if (i.types[op].bitfield.reg8)
3572 /* movzx, movsx, pextrb and pinsrb should not generate this
3575 && (i.tm.base_opcode == 0xfb7
3576 || i.tm.base_opcode == 0xfb6
3577 || i.tm.base_opcode == 0x63
3578 || i.tm.base_opcode == 0xfbe
3579 || i.tm.base_opcode == 0xfbf
3580 || i.tm.base_opcode == 0x660f3a14
3581 || i.tm.base_opcode == 0x660f3a20))
3584 /* crc32 doesn't generate this warning. */
3585 if (i.tm.base_opcode == 0xf20f38f0)
3588 if ((i.types[op].bitfield.reg16
3589 || i.types[op].bitfield.reg32
3590 || i.types[op].bitfield.reg64)
3591 && i.op[op].regs->reg_num < 4)
3593 /* Prohibit these changes in the 64bit mode, since the
3594 lowering is more complicated. */
3595 if (flag_code == CODE_64BIT
3596 && !i.tm.operand_types[op].bitfield.inoutportreg)
3598 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3599 register_prefix, i.op[op].regs->reg_name,
3603 #if REGISTER_WARNINGS
3605 && !i.tm.operand_types[op].bitfield.inoutportreg)
3606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3608 (i.op[op].regs + (i.types[op].bitfield.reg16
3609 ? REGNAM_AL - REGNAM_AX
3610 : REGNAM_AL - REGNAM_EAX))->reg_name,
3612 i.op[op].regs->reg_name,
3617 /* Any other register is bad. */
3618 if (i.types[op].bitfield.reg16
3619 || i.types[op].bitfield.reg32
3620 || i.types[op].bitfield.reg64
3621 || i.types[op].bitfield.regmmx
3622 || i.types[op].bitfield.regxmm
3623 || i.types[op].bitfield.sreg2
3624 || i.types[op].bitfield.sreg3
3625 || i.types[op].bitfield.control
3626 || i.types[op].bitfield.debug
3627 || i.types[op].bitfield.test
3628 || i.types[op].bitfield.floatreg
3629 || i.types[op].bitfield.floatacc)
3631 as_bad (_("`%s%s' not allowed with `%s%c'"),
3633 i.op[op].regs->reg_name,
3643 check_long_reg (void)
3647 for (op = i.operands; --op >= 0;)
3648 /* Reject eight bit registers, except where the template requires
3649 them. (eg. movzb) */
3650 if (i.types[op].bitfield.reg8
3651 && (i.tm.operand_types[op].bitfield.reg16
3652 || i.tm.operand_types[op].bitfield.reg32
3653 || i.tm.operand_types[op].bitfield.acc))
3655 as_bad (_("`%s%s' not allowed with `%s%c'"),
3657 i.op[op].regs->reg_name,
3662 /* Warn if the e prefix on a general reg is missing. */
3663 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3664 && i.types[op].bitfield.reg16
3665 && (i.tm.operand_types[op].bitfield.reg32
3666 || i.tm.operand_types[op].bitfield.acc))
3668 /* Prohibit these changes in the 64bit mode, since the
3669 lowering is more complicated. */
3670 if (flag_code == CODE_64BIT)
3672 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3673 register_prefix, i.op[op].regs->reg_name,
3677 #if REGISTER_WARNINGS
3679 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3681 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3683 i.op[op].regs->reg_name,
3687 /* Warn if the r prefix on a general reg is missing. */
3688 else if (i.types[op].bitfield.reg64
3689 && (i.tm.operand_types[op].bitfield.reg32
3690 || i.tm.operand_types[op].bitfield.acc))
3693 && (i.tm.base_opcode == 0xf30f2d
3694 || i.tm.base_opcode == 0xf30f2c)
3695 && !i.types[0].bitfield.regxmm)
3697 /* cvtss2si/cvttss2si convert DWORD memory to Reg64. We
3699 i.suffix = QWORD_MNEM_SUFFIX;
3703 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3704 register_prefix, i.op[op].regs->reg_name,
3713 check_qword_reg (void)
3717 for (op = i.operands; --op >= 0; )
3718 /* Reject eight bit registers, except where the template requires
3719 them. (eg. movzb) */
3720 if (i.types[op].bitfield.reg8
3721 && (i.tm.operand_types[op].bitfield.reg16
3722 || i.tm.operand_types[op].bitfield.reg32
3723 || i.tm.operand_types[op].bitfield.acc))
3725 as_bad (_("`%s%s' not allowed with `%s%c'"),
3727 i.op[op].regs->reg_name,
3732 /* Warn if the e prefix on a general reg is missing. */
3733 else if ((i.types[op].bitfield.reg16
3734 || i.types[op].bitfield.reg32)
3735 && (i.tm.operand_types[op].bitfield.reg32
3736 || i.tm.operand_types[op].bitfield.acc))
3738 /* Prohibit these changes in the 64bit mode, since the
3739 lowering is more complicated. */
3741 && (i.tm.base_opcode == 0xf20f2d
3742 || i.tm.base_opcode == 0xf20f2c)
3743 && !i.types[0].bitfield.regxmm)
3745 /* cvtsd2si/cvttsd2si convert QWORD memory to Reg32. We
3746 don't want REX byte. */
3747 i.suffix = LONG_MNEM_SUFFIX;
3751 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3752 register_prefix, i.op[op].regs->reg_name,
3761 check_word_reg (void)
3764 for (op = i.operands; --op >= 0;)
3765 /* Reject eight bit registers, except where the template requires
3766 them. (eg. movzb) */
3767 if (i.types[op].bitfield.reg8
3768 && (i.tm.operand_types[op].bitfield.reg16
3769 || i.tm.operand_types[op].bitfield.reg32
3770 || i.tm.operand_types[op].bitfield.acc))
3772 as_bad (_("`%s%s' not allowed with `%s%c'"),
3774 i.op[op].regs->reg_name,
3779 /* Warn if the e prefix on a general reg is present. */
3780 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3781 && i.types[op].bitfield.reg32
3782 && (i.tm.operand_types[op].bitfield.reg16
3783 || i.tm.operand_types[op].bitfield.acc))
3785 /* Prohibit these changes in the 64bit mode, since the
3786 lowering is more complicated. */
3787 if (flag_code == CODE_64BIT)
3789 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3790 register_prefix, i.op[op].regs->reg_name,
3795 #if REGISTER_WARNINGS
3796 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3798 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3800 i.op[op].regs->reg_name,
3808 update_imm (unsigned int j)
3810 i386_operand_type overlap;
3812 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3813 if ((overlap.bitfield.imm8
3814 || overlap.bitfield.imm8s
3815 || overlap.bitfield.imm16
3816 || overlap.bitfield.imm32
3817 || overlap.bitfield.imm32s
3818 || overlap.bitfield.imm64)
3819 && !UINTS_EQUAL (overlap, imm8)
3820 && !UINTS_EQUAL (overlap, imm8s)
3821 && !UINTS_EQUAL (overlap, imm16)
3822 && !UINTS_EQUAL (overlap, imm32)
3823 && !UINTS_EQUAL (overlap, imm32s)
3824 && !UINTS_EQUAL (overlap, imm64))
3828 i386_operand_type temp;
3831 if (i.suffix == BYTE_MNEM_SUFFIX)
3833 temp.bitfield.imm8 = overlap.bitfield.imm8;
3834 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3836 else if (i.suffix == WORD_MNEM_SUFFIX)
3837 temp.bitfield.imm16 = overlap.bitfield.imm16;
3838 else if (i.suffix == QWORD_MNEM_SUFFIX)
3840 temp.bitfield.imm64 = overlap.bitfield.imm64;
3841 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3844 temp.bitfield.imm32 = overlap.bitfield.imm32;
3847 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3848 || UINTS_EQUAL (overlap, imm16_32)
3849 || UINTS_EQUAL (overlap, imm16_32s))
3851 UINTS_CLEAR (overlap);
3852 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3853 overlap.bitfield.imm16 = 1;
3855 overlap.bitfield.imm32s = 1;
3857 if (!UINTS_EQUAL (overlap, imm8)
3858 && !UINTS_EQUAL (overlap, imm8s)
3859 && !UINTS_EQUAL (overlap, imm16)
3860 && !UINTS_EQUAL (overlap, imm32)
3861 && !UINTS_EQUAL (overlap, imm32s)
3862 && !UINTS_EQUAL (overlap, imm64))
3864 as_bad (_("no instruction mnemonic suffix given; "
3865 "can't determine immediate size"));
3869 i.types[j] = overlap;
3879 for (j = 0; j < 2; j++)
3880 if (update_imm (j) == 0)
3883 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3884 assert (operand_type_check (i.types[2], imm) == 0);
3892 i.drex.modrm_reg = None;
3893 i.drex.modrm_regmem = None;
3895 /* SSE5 4 operand instructions must have the destination the same as
3896 one of the inputs. Figure out the destination register and cache
3897 it away in the drex field, and remember which fields to use for
3899 if (i.tm.opcode_modifier.drex
3900 && i.tm.opcode_modifier.drexv
3903 i.tm.extension_opcode = None;
3905 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3906 if (i.types[0].bitfield.regxmm != 0
3907 && i.types[1].bitfield.regxmm != 0
3908 && i.types[2].bitfield.regxmm != 0
3909 && i.types[3].bitfield.regxmm != 0
3910 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3911 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3913 /* Clear the arguments that are stored in drex. */
3914 UINTS_CLEAR (i.types[0]);
3915 UINTS_CLEAR (i.types[3]);
3916 i.reg_operands -= 2;
3918 /* There are two different ways to encode a 4 operand
3919 instruction with all registers that uses OC1 set to
3920 0 or 1. Favor setting OC1 to 0 since this mimics the
3921 actions of other SSE5 assemblers. Use modrm encoding 2
3922 for register/register. Include the high order bit that
3923 is normally stored in the REX byte in the register
3925 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3926 i.drex.modrm_reg = 2;
3927 i.drex.modrm_regmem = 1;
3928 i.drex.reg = (i.op[3].regs->reg_num
3929 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3932 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3933 else if (i.types[0].bitfield.regxmm != 0
3934 && i.types[1].bitfield.regxmm != 0
3935 && (i.types[2].bitfield.regxmm
3936 || operand_type_check (i.types[2], anymem))
3937 && i.types[3].bitfield.regxmm != 0
3938 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3939 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3941 /* clear the arguments that are stored in drex */
3942 UINTS_CLEAR (i.types[0]);
3943 UINTS_CLEAR (i.types[3]);
3944 i.reg_operands -= 2;
3946 /* Specify the modrm encoding for memory addressing. Include
3947 the high order bit that is normally stored in the REX byte
3948 in the register field. */
3949 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3950 i.drex.modrm_reg = 1;
3951 i.drex.modrm_regmem = 2;
3952 i.drex.reg = (i.op[3].regs->reg_num
3953 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3956 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3957 else if (i.types[0].bitfield.regxmm != 0
3958 && operand_type_check (i.types[1], anymem) != 0
3959 && i.types[2].bitfield.regxmm != 0
3960 && i.types[3].bitfield.regxmm != 0
3961 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3962 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3964 /* Clear the arguments that are stored in drex. */
3965 UINTS_CLEAR (i.types[0]);
3966 UINTS_CLEAR (i.types[3]);
3967 i.reg_operands -= 2;
3969 /* Specify the modrm encoding for memory addressing. Include
3970 the high order bit that is normally stored in the REX byte
3971 in the register field. */
3972 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3973 i.drex.modrm_reg = 2;
3974 i.drex.modrm_regmem = 1;
3975 i.drex.reg = (i.op[3].regs->reg_num
3976 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3979 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3980 else if (i.types[0].bitfield.regxmm != 0
3981 && i.types[1].bitfield.regxmm != 0
3982 && i.types[2].bitfield.regxmm != 0
3983 && i.types[3].bitfield.regxmm != 0
3984 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3985 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3987 /* clear the arguments that are stored in drex */
3988 UINTS_CLEAR (i.types[2]);
3989 UINTS_CLEAR (i.types[3]);
3990 i.reg_operands -= 2;
3992 /* There are two different ways to encode a 4 operand
3993 instruction with all registers that uses OC1 set to
3994 0 or 1. Favor setting OC1 to 0 since this mimics the
3995 actions of other SSE5 assemblers. Use modrm encoding
3996 2 for register/register. Include the high order bit that
3997 is normally stored in the REX byte in the register
3999 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4000 i.drex.modrm_reg = 1;
4001 i.drex.modrm_regmem = 0;
4003 /* Remember the register, including the upper bits */
4004 i.drex.reg = (i.op[3].regs->reg_num
4005 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4008 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4009 else if (i.types[0].bitfield.regxmm != 0
4010 && (i.types[1].bitfield.regxmm
4011 || operand_type_check (i.types[1], anymem))
4012 && i.types[2].bitfield.regxmm != 0
4013 && i.types[3].bitfield.regxmm != 0
4014 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4015 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4017 /* Clear the arguments that are stored in drex. */
4018 UINTS_CLEAR (i.types[2]);
4019 UINTS_CLEAR (i.types[3]);
4020 i.reg_operands -= 2;
4022 /* Specify the modrm encoding and remember the register
4023 including the bits normally stored in the REX byte. */
4024 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4025 i.drex.modrm_reg = 0;
4026 i.drex.modrm_regmem = 1;
4027 i.drex.reg = (i.op[3].regs->reg_num
4028 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4031 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4032 else if (operand_type_check (i.types[0], anymem) != 0
4033 && i.types[1].bitfield.regxmm != 0
4034 && i.types[2].bitfield.regxmm != 0
4035 && i.types[3].bitfield.regxmm != 0
4036 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4037 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4039 /* clear the arguments that are stored in drex */
4040 UINTS_CLEAR (i.types[2]);
4041 UINTS_CLEAR (i.types[3]);
4042 i.reg_operands -= 2;
4044 /* Specify the modrm encoding and remember the register
4045 including the bits normally stored in the REX byte. */
4046 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4047 i.drex.modrm_reg = 1;
4048 i.drex.modrm_regmem = 0;
4049 i.drex.reg = (i.op[3].regs->reg_num
4050 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4054 as_bad (_("Incorrect operands for the '%s' instruction"),
4058 /* SSE5 instructions with the DREX byte where the only memory operand
4059 is in the 2nd argument, and the first and last xmm register must
4060 match, and is encoded in the DREX byte. */
4061 else if (i.tm.opcode_modifier.drex
4062 && !i.tm.opcode_modifier.drexv
4065 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4066 if (i.types[0].bitfield.regxmm != 0
4067 && (i.types[1].bitfield.regxmm
4068 || operand_type_check(i.types[1], anymem))
4069 && i.types[2].bitfield.regxmm != 0
4070 && i.types[3].bitfield.regxmm != 0
4071 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4072 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4074 /* clear the arguments that are stored in drex */
4075 UINTS_CLEAR (i.types[0]);
4076 UINTS_CLEAR (i.types[3]);
4077 i.reg_operands -= 2;
4079 /* Specify the modrm encoding and remember the register
4080 including the high bit normally stored in the REX
4082 i.drex.modrm_reg = 2;
4083 i.drex.modrm_regmem = 1;
4084 i.drex.reg = (i.op[3].regs->reg_num
4085 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4089 as_bad (_("Incorrect operands for the '%s' instruction"),
4093 /* SSE5 3 operand instructions that the result is a register, being
4094 either operand can be a memory operand, using OC0 to note which
4095 one is the memory. */
4096 else if (i.tm.opcode_modifier.drex
4097 && i.tm.opcode_modifier.drexv
4100 i.tm.extension_opcode = None;
4102 /* Case 1: 3 operand insn, src1 = register. */
4103 if (i.types[0].bitfield.regxmm != 0
4104 && i.types[1].bitfield.regxmm != 0
4105 && i.types[2].bitfield.regxmm != 0)
4107 /* Clear the arguments that are stored in drex. */
4108 UINTS_CLEAR (i.types[2]);
4111 /* Specify the modrm encoding and remember the register
4112 including the high bit normally stored in the REX byte. */
4113 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4114 i.drex.modrm_reg = 1;
4115 i.drex.modrm_regmem = 0;
4116 i.drex.reg = (i.op[2].regs->reg_num
4117 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4120 /* Case 2: 3 operand insn, src1 = memory. */
4121 else if (operand_type_check (i.types[0], anymem) != 0
4122 && i.types[1].bitfield.regxmm != 0
4123 && i.types[2].bitfield.regxmm != 0)
4125 /* Clear the arguments that are stored in drex. */
4126 UINTS_CLEAR (i.types[2]);
4129 /* Specify the modrm encoding and remember the register
4130 including the high bit normally stored in the REX
4132 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4133 i.drex.modrm_reg = 1;
4134 i.drex.modrm_regmem = 0;
4135 i.drex.reg = (i.op[2].regs->reg_num
4136 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4139 /* Case 3: 3 operand insn, src2 = memory. */
4140 else if (i.types[0].bitfield.regxmm != 0
4141 && operand_type_check (i.types[1], anymem) != 0
4142 && i.types[2].bitfield.regxmm != 0)
4144 /* Clear the arguments that are stored in drex. */
4145 UINTS_CLEAR (i.types[2]);
4148 /* Specify the modrm encoding and remember the register
4149 including the high bit normally stored in the REX byte. */
4150 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4151 i.drex.modrm_reg = 0;
4152 i.drex.modrm_regmem = 1;
4153 i.drex.reg = (i.op[2].regs->reg_num
4154 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4158 as_bad (_("Incorrect operands for the '%s' instruction"),
4162 /* SSE5 4 operand instructions that are the comparison instructions
4163 where the first operand is the immediate value of the comparison
4165 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4167 /* Case 1: 4 operand insn, src1 = reg/memory. */
4168 if (operand_type_check (i.types[0], imm) != 0
4169 && (i.types[1].bitfield.regxmm
4170 || operand_type_check (i.types[1], anymem))
4171 && i.types[2].bitfield.regxmm != 0
4172 && i.types[3].bitfield.regxmm != 0)
4174 /* clear the arguments that are stored in drex */
4175 UINTS_CLEAR (i.types[3]);
4178 /* Specify the modrm encoding and remember the register
4179 including the high bit normally stored in the REX byte. */
4180 i.drex.modrm_reg = 2;
4181 i.drex.modrm_regmem = 1;
4182 i.drex.reg = (i.op[3].regs->reg_num
4183 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4186 /* Case 2: 3 operand insn with ImmExt that places the
4187 opcode_extension as an immediate argument. This is used for
4188 all of the varients of comparison that supplies the appropriate
4189 value as part of the instruction. */
4190 else if ((i.types[0].bitfield.regxmm
4191 || operand_type_check (i.types[0], anymem))
4192 && i.types[1].bitfield.regxmm != 0
4193 && i.types[2].bitfield.regxmm != 0
4194 && operand_type_check (i.types[3], imm) != 0)
4196 /* clear the arguments that are stored in drex */
4197 UINTS_CLEAR (i.types[2]);
4200 /* Specify the modrm encoding and remember the register
4201 including the high bit normally stored in the REX byte. */
4202 i.drex.modrm_reg = 1;
4203 i.drex.modrm_regmem = 0;
4204 i.drex.reg = (i.op[2].regs->reg_num
4205 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4209 as_bad (_("Incorrect operands for the '%s' instruction"),
4213 else if (i.tm.opcode_modifier.drex
4214 || i.tm.opcode_modifier.drexv
4215 || i.tm.opcode_modifier.drexc)
4216 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4220 process_operands (void)
4222 /* Default segment register this instruction will use for memory
4223 accesses. 0 means unknown. This is only for optimizing out
4224 unnecessary segment overrides. */
4225 const seg_entry *default_seg = 0;
4227 /* Handle all of the DREX munging that SSE5 needs. */
4228 if (i.tm.opcode_modifier.drex
4229 || i.tm.opcode_modifier.drexv
4230 || i.tm.opcode_modifier.drexc)
4233 /* The imul $imm, %reg instruction is converted into
4234 imul $imm, %reg, %reg, and the clr %reg instruction
4235 is converted into xor %reg, %reg. */
4236 if (i.tm.opcode_modifier.regkludge)
4238 if (i.tm.cpu_flags.bitfield.cpusse4_1)
4240 /* The first operand in instruction blendvpd, blendvps and
4241 pblendvb in SSE4.1 is implicit and must be xmm0. */
4242 assert (i.operands == 3
4243 && i.reg_operands >= 2
4244 && UINTS_EQUAL (i.types[0], regxmm));
4245 if (i.op[0].regs->reg_num != 0)
4248 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4249 i.tm.name, register_prefix);
4251 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4252 i.tm.name, register_prefix);
4257 i.types[0] = i.types[1];
4258 i.types[1] = i.types[2];
4262 /* We need to adjust fields in i.tm since they are used by
4263 build_modrm_byte. */
4264 i.tm.operand_types [0] = i.tm.operand_types [1];
4265 i.tm.operand_types [1] = i.tm.operand_types [2];
4270 unsigned int first_reg_op;
4272 if (operand_type_check (i.types[0], reg))
4276 /* Pretend we saw the extra register operand. */
4277 assert (i.reg_operands == 1
4278 && i.op[first_reg_op + 1].regs == 0);
4279 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4280 i.types[first_reg_op + 1] = i.types[first_reg_op];
4286 if (i.tm.opcode_modifier.shortform)
4288 if (i.types[0].bitfield.sreg2
4289 || i.types[0].bitfield.sreg3)
4291 if (i.tm.base_opcode == POP_SEG_SHORT
4292 && i.op[0].regs->reg_num == 1)
4294 as_bad (_("you can't `pop %%cs'"));
4297 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4298 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4303 /* The register or float register operand is in operand
4307 if (i.types[0].bitfield.floatreg
4308 || operand_type_check (i.types[0], reg))
4312 /* Register goes in low 3 bits of opcode. */
4313 i.tm.base_opcode |= i.op[op].regs->reg_num;
4314 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4316 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4318 /* Warn about some common errors, but press on regardless.
4319 The first case can be generated by gcc (<= 2.8.1). */
4320 if (i.operands == 2)
4322 /* Reversed arguments on faddp, fsubp, etc. */
4323 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4324 register_prefix, i.op[1].regs->reg_name,
4325 register_prefix, i.op[0].regs->reg_name);
4329 /* Extraneous `l' suffix on fp insn. */
4330 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4331 register_prefix, i.op[0].regs->reg_name);
4336 else if (i.tm.opcode_modifier.modrm)
4338 /* The opcode is completed (modulo i.tm.extension_opcode which
4339 must be put into the modrm byte). Now, we make the modrm and
4340 index base bytes based on all the info we've collected. */
4342 default_seg = build_modrm_byte ();
4344 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4348 else if (i.tm.opcode_modifier.isstring)
4350 /* For the string instructions that allow a segment override
4351 on one of their operands, the default segment is ds. */
4355 if (i.tm.base_opcode == 0x8d /* lea */
4358 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4360 /* If a segment was explicitly specified, and the specified segment
4361 is not the default, use an opcode prefix to select it. If we
4362 never figured out what the default segment is, then default_seg
4363 will be zero at this point, and the specified segment prefix will
4365 if ((i.seg[0]) && (i.seg[0] != default_seg))
4367 if (!add_prefix (i.seg[0]->seg_prefix))
4373 static const seg_entry *
4374 build_modrm_byte (void)
4376 const seg_entry *default_seg = 0;
4378 /* SSE5 4 operand instructions are encoded in such a way that one of
4379 the inputs must match the destination register. Process_drex hides
4380 the 3rd argument in the drex field, so that by the time we get
4381 here, it looks to GAS as if this is a 2 operand instruction. */
4382 if ((i.tm.opcode_modifier.drex
4383 || i.tm.opcode_modifier.drexv
4384 || i.tm.opcode_modifier.drexc)
4385 && i.reg_operands == 2)
4387 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4388 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4390 i.rm.reg = reg->reg_num;
4391 i.rm.regmem = regmem->reg_num;
4393 if ((reg->reg_flags & RegRex) != 0)
4395 if ((regmem->reg_flags & RegRex) != 0)
4399 /* i.reg_operands MUST be the number of real register operands;
4400 implicit registers do not count. */
4401 else if (i.reg_operands == 2)
4403 unsigned int source, dest;
4411 /* When there are 3 operands, one of them may be immediate,
4412 which may be the first or the last operand. Otherwise,
4413 the first operand must be shift count register (cl). */
4414 assert (i.imm_operands == 1
4415 || (i.imm_operands == 0
4416 && i.types[0].bitfield.shiftcount));
4417 if (operand_type_check (i.types[0], imm)
4418 || i.types[0].bitfield.shiftcount)
4424 /* When there are 4 operands, the first two must be 8bit
4425 immediate operands. The source operand will be the 3rd
4427 assert (i.imm_operands == 2
4428 && i.types[0].bitfield.imm8
4429 && i.types[1].bitfield.imm8);
4439 /* One of the register operands will be encoded in the i.tm.reg
4440 field, the other in the combined i.tm.mode and i.tm.regmem
4441 fields. If no form of this instruction supports a memory
4442 destination operand, then we assume the source operand may
4443 sometimes be a memory operand and so we need to store the
4444 destination in the i.rm.reg field. */
4445 if (!i.tm.operand_types[dest].bitfield.regmem
4446 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4448 i.rm.reg = i.op[dest].regs->reg_num;
4449 i.rm.regmem = i.op[source].regs->reg_num;
4450 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4452 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4457 i.rm.reg = i.op[source].regs->reg_num;
4458 i.rm.regmem = i.op[dest].regs->reg_num;
4459 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4461 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4464 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4466 if (!i.types[0].bitfield.control
4467 && !i.types[1].bitfield.control)
4469 i.rex &= ~(REX_R | REX_B);
4470 add_prefix (LOCK_PREFIX_OPCODE);
4474 { /* If it's not 2 reg operands... */
4477 unsigned int fake_zero_displacement = 0;
4480 /* This has been precalculated for SSE5 instructions
4481 that have a DREX field earlier in process_drex. */
4482 if (i.tm.opcode_modifier.drex
4483 || i.tm.opcode_modifier.drexv
4484 || i.tm.opcode_modifier.drexc)
4485 op = i.drex.modrm_regmem;
4488 for (op = 0; op < i.operands; op++)
4489 if (operand_type_check (i.types[op], anymem))
4491 assert (op < i.operands);
4496 if (i.base_reg == 0)
4499 if (!i.disp_operands)
4500 fake_zero_displacement = 1;
4501 if (i.index_reg == 0)
4503 /* Operand is just <disp> */
4504 if (flag_code == CODE_64BIT)
4506 /* 64bit mode overwrites the 32bit absolute
4507 addressing by RIP relative addressing and
4508 absolute addressing is encoded by one of the
4509 redundant SIB forms. */
4510 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4511 i.sib.base = NO_BASE_REGISTER;
4512 i.sib.index = NO_INDEX_REGISTER;
4513 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4514 ? disp32s : disp32);
4516 else if ((flag_code == CODE_16BIT)
4517 ^ (i.prefix[ADDR_PREFIX] != 0))
4519 i.rm.regmem = NO_BASE_REGISTER_16;
4520 i.types[op] = disp16;
4524 i.rm.regmem = NO_BASE_REGISTER;
4525 i.types[op] = disp32;
4528 else /* !i.base_reg && i.index_reg */
4530 if (i.index_reg->reg_num == RegEiz
4531 || i.index_reg->reg_num == RegRiz)
4532 i.sib.index = NO_INDEX_REGISTER;
4534 i.sib.index = i.index_reg->reg_num;
4535 i.sib.base = NO_BASE_REGISTER;
4536 i.sib.scale = i.log2_scale_factor;
4537 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4538 i.types[op].bitfield.disp8 = 0;
4539 i.types[op].bitfield.disp16 = 0;
4540 i.types[op].bitfield.disp64 = 0;
4541 if (flag_code != CODE_64BIT)
4543 /* Must be 32 bit */
4544 i.types[op].bitfield.disp32 = 1;
4545 i.types[op].bitfield.disp32s = 0;
4549 i.types[op].bitfield.disp32 = 0;
4550 i.types[op].bitfield.disp32s = 1;
4552 if ((i.index_reg->reg_flags & RegRex) != 0)
4556 /* RIP addressing for 64bit mode. */
4557 else if (i.base_reg->reg_num == RegRip ||
4558 i.base_reg->reg_num == RegEip)
4560 i.rm.regmem = NO_BASE_REGISTER;
4561 i.types[op].bitfield.disp8 = 0;
4562 i.types[op].bitfield.disp16 = 0;
4563 i.types[op].bitfield.disp32 = 0;
4564 i.types[op].bitfield.disp32s = 1;
4565 i.types[op].bitfield.disp64 = 0;
4566 i.flags[op] |= Operand_PCrel;
4567 if (! i.disp_operands)
4568 fake_zero_displacement = 1;
4570 else if (i.base_reg->reg_type.bitfield.reg16)
4572 switch (i.base_reg->reg_num)
4575 if (i.index_reg == 0)
4577 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4578 i.rm.regmem = i.index_reg->reg_num - 6;
4582 if (i.index_reg == 0)
4585 if (operand_type_check (i.types[op], disp) == 0)
4587 /* fake (%bp) into 0(%bp) */
4588 i.types[op].bitfield.disp8 = 1;
4589 fake_zero_displacement = 1;
4592 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4593 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4595 default: /* (%si) -> 4 or (%di) -> 5 */
4596 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4598 i.rm.mode = mode_from_disp_size (i.types[op]);
4600 else /* i.base_reg and 32/64 bit mode */
4602 if (flag_code == CODE_64BIT
4603 && operand_type_check (i.types[op], disp))
4605 i386_operand_type temp;
4607 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4609 if (i.prefix[ADDR_PREFIX] == 0)
4610 i.types[op].bitfield.disp32s = 1;
4612 i.types[op].bitfield.disp32 = 1;
4615 i.rm.regmem = i.base_reg->reg_num;
4616 if ((i.base_reg->reg_flags & RegRex) != 0)
4618 i.sib.base = i.base_reg->reg_num;
4619 /* x86-64 ignores REX prefix bit here to avoid decoder
4621 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4624 if (i.disp_operands == 0)
4626 fake_zero_displacement = 1;
4627 i.types[op].bitfield.disp8 = 1;
4630 else if (i.base_reg->reg_num == ESP_REG_NUM)
4634 i.sib.scale = i.log2_scale_factor;
4635 if (i.index_reg == 0)
4637 /* <disp>(%esp) becomes two byte modrm with no index
4638 register. We've already stored the code for esp
4639 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4640 Any base register besides %esp will not use the
4641 extra modrm byte. */
4642 i.sib.index = NO_INDEX_REGISTER;
4646 if (i.index_reg->reg_num == RegEiz
4647 || i.index_reg->reg_num == RegRiz)
4648 i.sib.index = NO_INDEX_REGISTER;
4650 i.sib.index = i.index_reg->reg_num;
4651 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4652 if ((i.index_reg->reg_flags & RegRex) != 0)
4657 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4658 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4661 i.rm.mode = mode_from_disp_size (i.types[op]);
4664 if (fake_zero_displacement)
4666 /* Fakes a zero displacement assuming that i.types[op]
4667 holds the correct displacement size. */
4670 assert (i.op[op].disps == 0);
4671 exp = &disp_expressions[i.disp_operands++];
4672 i.op[op].disps = exp;
4673 exp->X_op = O_constant;
4674 exp->X_add_number = 0;
4675 exp->X_add_symbol = (symbolS *) 0;
4676 exp->X_op_symbol = (symbolS *) 0;
4680 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4681 (if any) based on i.tm.extension_opcode. Again, we must be
4682 careful to make sure that segment/control/debug/test/MMX
4683 registers are coded into the i.rm.reg field. */
4688 /* This has been precalculated for SSE5 instructions
4689 that have a DREX field earlier in process_drex. */
4690 if (i.tm.opcode_modifier.drex
4691 || i.tm.opcode_modifier.drexv
4692 || i.tm.opcode_modifier.drexc)
4694 op = i.drex.modrm_reg;
4695 i.rm.reg = i.op[op].regs->reg_num;
4696 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4701 for (op = 0; op < i.operands; op++)
4702 if (i.types[op].bitfield.reg8
4703 || i.types[op].bitfield.reg16
4704 || i.types[op].bitfield.reg32
4705 || i.types[op].bitfield.reg64
4706 || i.types[op].bitfield.regmmx
4707 || i.types[op].bitfield.regxmm
4708 || i.types[op].bitfield.sreg2
4709 || i.types[op].bitfield.sreg3
4710 || i.types[op].bitfield.control
4711 || i.types[op].bitfield.debug
4712 || i.types[op].bitfield.test)
4715 assert (op < i.operands);
4717 /* If there is an extension opcode to put here, the
4718 register number must be put into the regmem field. */
4719 if (i.tm.extension_opcode != None)
4721 i.rm.regmem = i.op[op].regs->reg_num;
4722 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4727 i.rm.reg = i.op[op].regs->reg_num;
4728 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4733 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4734 must set it to 3 to indicate this is a register operand
4735 in the regmem field. */
4736 if (!i.mem_operands)
4740 /* Fill in i.rm.reg field with extension opcode (if any). */
4741 if (i.tm.extension_opcode != None
4742 && !(i.tm.opcode_modifier.drex
4743 || i.tm.opcode_modifier.drexv
4744 || i.tm.opcode_modifier.drexc))
4745 i.rm.reg = i.tm.extension_opcode;
4751 output_branch (void)
4756 relax_substateT subtype;
4761 if (flag_code == CODE_16BIT)
4765 if (i.prefix[DATA_PREFIX] != 0)
4771 /* Pentium4 branch hints. */
4772 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4773 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4778 if (i.prefix[REX_PREFIX] != 0)
4784 if (i.prefixes != 0 && !intel_syntax)
4785 as_warn (_("skipping prefixes on this instruction"));
4787 /* It's always a symbol; End frag & setup for relax.
4788 Make sure there is enough room in this frag for the largest
4789 instruction we may generate in md_convert_frag. This is 2
4790 bytes for the opcode and room for the prefix and largest
4792 frag_grow (prefix + 2 + 4);
4793 /* Prefix and 1 opcode byte go in fr_fix. */
4794 p = frag_more (prefix + 1);
4795 if (i.prefix[DATA_PREFIX] != 0)
4796 *p++ = DATA_PREFIX_OPCODE;
4797 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4798 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4799 *p++ = i.prefix[SEG_PREFIX];
4800 if (i.prefix[REX_PREFIX] != 0)
4801 *p++ = i.prefix[REX_PREFIX];
4802 *p = i.tm.base_opcode;
4804 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4805 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4806 else if (cpu_arch_flags.bitfield.cpui386)
4807 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4809 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4812 sym = i.op[0].disps->X_add_symbol;
4813 off = i.op[0].disps->X_add_number;
4815 if (i.op[0].disps->X_op != O_constant
4816 && i.op[0].disps->X_op != O_symbol)
4818 /* Handle complex expressions. */
4819 sym = make_expr_symbol (i.op[0].disps);
4823 /* 1 possible extra opcode + 4 byte displacement go in var part.
4824 Pass reloc in fr_var. */
4825 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4835 if (i.tm.opcode_modifier.jumpbyte)
4837 /* This is a loop or jecxz type instruction. */
4839 if (i.prefix[ADDR_PREFIX] != 0)
4841 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4844 /* Pentium4 branch hints. */
4845 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4846 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4848 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4857 if (flag_code == CODE_16BIT)
4860 if (i.prefix[DATA_PREFIX] != 0)
4862 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4872 if (i.prefix[REX_PREFIX] != 0)
4874 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4878 if (i.prefixes != 0 && !intel_syntax)
4879 as_warn (_("skipping prefixes on this instruction"));
4881 p = frag_more (1 + size);
4882 *p++ = i.tm.base_opcode;
4884 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4885 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4887 /* All jumps handled here are signed, but don't use a signed limit
4888 check for 32 and 16 bit jumps as we want to allow wrap around at
4889 4G and 64k respectively. */
4891 fixP->fx_signed = 1;
4895 output_interseg_jump (void)
4903 if (flag_code == CODE_16BIT)
4907 if (i.prefix[DATA_PREFIX] != 0)
4913 if (i.prefix[REX_PREFIX] != 0)
4923 if (i.prefixes != 0 && !intel_syntax)
4924 as_warn (_("skipping prefixes on this instruction"));
4926 /* 1 opcode; 2 segment; offset */
4927 p = frag_more (prefix + 1 + 2 + size);
4929 if (i.prefix[DATA_PREFIX] != 0)
4930 *p++ = DATA_PREFIX_OPCODE;
4932 if (i.prefix[REX_PREFIX] != 0)
4933 *p++ = i.prefix[REX_PREFIX];
4935 *p++ = i.tm.base_opcode;
4936 if (i.op[1].imms->X_op == O_constant)
4938 offsetT n = i.op[1].imms->X_add_number;
4941 && !fits_in_unsigned_word (n)
4942 && !fits_in_signed_word (n))
4944 as_bad (_("16-bit jump out of range"));
4947 md_number_to_chars (p, n, size);
4950 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4951 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4952 if (i.op[0].imms->X_op != O_constant)
4953 as_bad (_("can't handle non absolute segment in `%s'"),
4955 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4961 fragS *insn_start_frag;
4962 offsetT insn_start_off;
4964 /* Tie dwarf2 debug info to the address at the start of the insn.
4965 We can't do this after the insn has been output as the current
4966 frag may have been closed off. eg. by frag_var. */
4967 dwarf2_emit_insn (0);
4969 insn_start_frag = frag_now;
4970 insn_start_off = frag_now_fix ();
4973 if (i.tm.opcode_modifier.jump)
4975 else if (i.tm.opcode_modifier.jumpbyte
4976 || i.tm.opcode_modifier.jumpdword)
4978 else if (i.tm.opcode_modifier.jumpintersegment)
4979 output_interseg_jump ();
4982 /* Output normal instructions here. */
4985 unsigned int prefix;
4987 switch (i.tm.opcode_length)
4990 if (i.tm.base_opcode & 0xff000000)
4992 prefix = (i.tm.base_opcode >> 24) & 0xff;
4997 if ((i.tm.base_opcode & 0xff0000) != 0)
4999 prefix = (i.tm.base_opcode >> 16) & 0xff;
5000 if (i.tm.cpu_flags.bitfield.cpupadlock)
5003 if (prefix != REPE_PREFIX_OPCODE
5004 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5005 add_prefix (prefix);
5008 add_prefix (prefix);
5017 /* The prefix bytes. */
5019 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5025 md_number_to_chars (p, (valueT) *q, 1);
5029 /* Now the opcode; be careful about word order here! */
5030 if (i.tm.opcode_length == 1)
5032 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5036 switch (i.tm.opcode_length)
5040 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5050 /* Put out high byte first: can't use md_number_to_chars! */
5051 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5052 *p = i.tm.base_opcode & 0xff;
5054 /* On SSE5, encode the OC1 bit in the DREX field if this
5055 encoding has multiple formats. */
5056 if (i.tm.opcode_modifier.drex
5057 && i.tm.opcode_modifier.drexv
5058 && DREX_OC1 (i.tm.extension_opcode))
5059 *p |= DREX_OC1_MASK;
5062 /* Now the modrm byte and sib byte (if present). */
5063 if (i.tm.opcode_modifier.modrm)
5066 md_number_to_chars (p,
5067 (valueT) (i.rm.regmem << 0
5071 /* If i.rm.regmem == ESP (4)
5072 && i.rm.mode != (Register mode)
5074 ==> need second modrm byte. */
5075 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5077 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5080 md_number_to_chars (p,
5081 (valueT) (i.sib.base << 0
5083 | i.sib.scale << 6),
5088 /* Write the DREX byte if needed. */
5089 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5092 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5094 /* Encode the OC0 bit if this encoding has multiple
5096 if ((i.tm.opcode_modifier.drex
5097 || i.tm.opcode_modifier.drexv)
5098 && DREX_OC0 (i.tm.extension_opcode))
5099 *p |= DREX_OC0_MASK;
5102 if (i.disp_operands)
5103 output_disp (insn_start_frag, insn_start_off);
5106 output_imm (insn_start_frag, insn_start_off);
5112 pi ("" /*line*/, &i);
5114 #endif /* DEBUG386 */
5117 /* Return the size of the displacement operand N. */
5120 disp_size (unsigned int n)
5123 if (i.types[n].bitfield.disp64)
5125 else if (i.types[n].bitfield.disp8)
5127 else if (i.types[n].bitfield.disp16)
5132 /* Return the size of the immediate operand N. */
5135 imm_size (unsigned int n)
5138 if (i.types[n].bitfield.imm64)
5140 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5142 else if (i.types[n].bitfield.imm16)
5148 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5153 for (n = 0; n < i.operands; n++)
5155 if (operand_type_check (i.types[n], disp))
5157 if (i.op[n].disps->X_op == O_constant)
5159 int size = disp_size (n);
5162 val = offset_in_range (i.op[n].disps->X_add_number,
5164 p = frag_more (size);
5165 md_number_to_chars (p, val, size);
5169 enum bfd_reloc_code_real reloc_type;
5170 int size = disp_size (n);
5171 int sign = i.types[n].bitfield.disp32s;
5172 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5174 /* We can't have 8 bit displacement here. */
5175 assert (!i.types[n].bitfield.disp8);
5177 /* The PC relative address is computed relative
5178 to the instruction boundary, so in case immediate
5179 fields follows, we need to adjust the value. */
5180 if (pcrel && i.imm_operands)
5185 for (n1 = 0; n1 < i.operands; n1++)
5186 if (operand_type_check (i.types[n1], imm))
5188 /* Only one immediate is allowed for PC
5189 relative address. */
5192 i.op[n].disps->X_add_number -= sz;
5194 /* We should find the immediate. */
5198 p = frag_more (size);
5199 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5201 && GOT_symbol == i.op[n].disps->X_add_symbol
5202 && (((reloc_type == BFD_RELOC_32
5203 || reloc_type == BFD_RELOC_X86_64_32S
5204 || (reloc_type == BFD_RELOC_64
5206 && (i.op[n].disps->X_op == O_symbol
5207 || (i.op[n].disps->X_op == O_add
5208 && ((symbol_get_value_expression
5209 (i.op[n].disps->X_op_symbol)->X_op)
5211 || reloc_type == BFD_RELOC_32_PCREL))
5215 if (insn_start_frag == frag_now)
5216 add = (p - frag_now->fr_literal) - insn_start_off;
5221 add = insn_start_frag->fr_fix - insn_start_off;
5222 for (fr = insn_start_frag->fr_next;
5223 fr && fr != frag_now; fr = fr->fr_next)
5225 add += p - frag_now->fr_literal;
5230 reloc_type = BFD_RELOC_386_GOTPC;
5231 i.op[n].imms->X_add_number += add;
5233 else if (reloc_type == BFD_RELOC_64)
5234 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5236 /* Don't do the adjustment for x86-64, as there
5237 the pcrel addressing is relative to the _next_
5238 insn, and that is taken care of in other code. */
5239 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5241 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5242 i.op[n].disps, pcrel, reloc_type);
5249 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5254 for (n = 0; n < i.operands; n++)
5256 if (operand_type_check (i.types[n], imm))
5258 if (i.op[n].imms->X_op == O_constant)
5260 int size = imm_size (n);
5263 val = offset_in_range (i.op[n].imms->X_add_number,
5265 p = frag_more (size);
5266 md_number_to_chars (p, val, size);
5270 /* Not absolute_section.
5271 Need a 32-bit fixup (don't support 8bit
5272 non-absolute imms). Try to support other
5274 enum bfd_reloc_code_real reloc_type;
5275 int size = imm_size (n);
5278 if (i.types[n].bitfield.imm32s
5279 && (i.suffix == QWORD_MNEM_SUFFIX
5280 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5285 p = frag_more (size);
5286 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5288 /* This is tough to explain. We end up with this one if we
5289 * have operands that look like
5290 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5291 * obtain the absolute address of the GOT, and it is strongly
5292 * preferable from a performance point of view to avoid using
5293 * a runtime relocation for this. The actual sequence of
5294 * instructions often look something like:
5299 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5301 * The call and pop essentially return the absolute address
5302 * of the label .L66 and store it in %ebx. The linker itself
5303 * will ultimately change the first operand of the addl so
5304 * that %ebx points to the GOT, but to keep things simple, the
5305 * .o file must have this operand set so that it generates not
5306 * the absolute address of .L66, but the absolute address of
5307 * itself. This allows the linker itself simply treat a GOTPC
5308 * relocation as asking for a pcrel offset to the GOT to be
5309 * added in, and the addend of the relocation is stored in the
5310 * operand field for the instruction itself.
5312 * Our job here is to fix the operand so that it would add
5313 * the correct offset so that %ebx would point to itself. The
5314 * thing that is tricky is that .-.L66 will point to the
5315 * beginning of the instruction, so we need to further modify
5316 * the operand so that it will point to itself. There are
5317 * other cases where you have something like:
5319 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5321 * and here no correction would be required. Internally in
5322 * the assembler we treat operands of this form as not being
5323 * pcrel since the '.' is explicitly mentioned, and I wonder
5324 * whether it would simplify matters to do it this way. Who
5325 * knows. In earlier versions of the PIC patches, the
5326 * pcrel_adjust field was used to store the correction, but
5327 * since the expression is not pcrel, I felt it would be
5328 * confusing to do it this way. */
5330 if ((reloc_type == BFD_RELOC_32
5331 || reloc_type == BFD_RELOC_X86_64_32S
5332 || reloc_type == BFD_RELOC_64)
5334 && GOT_symbol == i.op[n].imms->X_add_symbol
5335 && (i.op[n].imms->X_op == O_symbol
5336 || (i.op[n].imms->X_op == O_add
5337 && ((symbol_get_value_expression
5338 (i.op[n].imms->X_op_symbol)->X_op)
5343 if (insn_start_frag == frag_now)
5344 add = (p - frag_now->fr_literal) - insn_start_off;
5349 add = insn_start_frag->fr_fix - insn_start_off;
5350 for (fr = insn_start_frag->fr_next;
5351 fr && fr != frag_now; fr = fr->fr_next)
5353 add += p - frag_now->fr_literal;
5357 reloc_type = BFD_RELOC_386_GOTPC;
5359 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5361 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5362 i.op[n].imms->X_add_number += add;
5364 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5365 i.op[n].imms, 0, reloc_type);
5371 /* x86_cons_fix_new is called via the expression parsing code when a
5372 reloc is needed. We use this hook to get the correct .got reloc. */
5373 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5374 static int cons_sign = -1;
5377 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5380 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5382 got_reloc = NO_RELOC;
5385 if (exp->X_op == O_secrel)
5387 exp->X_op = O_symbol;
5388 r = BFD_RELOC_32_SECREL;
5392 fix_new_exp (frag, off, len, exp, 0, r);
5395 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5396 # define lex_got(reloc, adjust, types) NULL
5398 /* Parse operands of the form
5399 <symbol>@GOTOFF+<nnn>
5400 and similar .plt or .got references.
5402 If we find one, set up the correct relocation in RELOC and copy the
5403 input string, minus the `@GOTOFF' into a malloc'd buffer for
5404 parsing by the calling routine. Return this buffer, and if ADJUST
5405 is non-null set it to the length of the string we removed from the
5406 input line. Otherwise return NULL. */
5408 lex_got (enum bfd_reloc_code_real *reloc,
5410 i386_operand_type *types)
5412 /* Some of the relocations depend on the size of what field is to
5413 be relocated. But in our callers i386_immediate and i386_displacement
5414 we don't yet know the operand size (this will be set by insn
5415 matching). Hence we record the word32 relocation here,
5416 and adjust the reloc according to the real size in reloc(). */
5417 static const struct {
5419 const enum bfd_reloc_code_real rel[2];
5420 const i386_operand_type types64;
5423 BFD_RELOC_X86_64_PLTOFF64 },
5424 OPERAND_TYPE_IMM64 },
5425 { "PLT", { BFD_RELOC_386_PLT32,
5426 BFD_RELOC_X86_64_PLT32 },
5427 OPERAND_TYPE_IMM32_32S_DISP32 },
5429 BFD_RELOC_X86_64_GOTPLT64 },
5430 OPERAND_TYPE_IMM64_DISP64 },
5431 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5432 BFD_RELOC_X86_64_GOTOFF64 },
5433 OPERAND_TYPE_IMM64_DISP64 },
5435 BFD_RELOC_X86_64_GOTPCREL },
5436 OPERAND_TYPE_IMM32_32S_DISP32 },
5437 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5438 BFD_RELOC_X86_64_TLSGD },
5439 OPERAND_TYPE_IMM32_32S_DISP32 },
5440 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5442 OPERAND_TYPE_NONE },
5444 BFD_RELOC_X86_64_TLSLD },
5445 OPERAND_TYPE_IMM32_32S_DISP32 },
5446 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5447 BFD_RELOC_X86_64_GOTTPOFF },
5448 OPERAND_TYPE_IMM32_32S_DISP32 },
5449 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5450 BFD_RELOC_X86_64_TPOFF32 },
5451 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5452 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5454 OPERAND_TYPE_NONE },
5455 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5456 BFD_RELOC_X86_64_DTPOFF32 },
5458 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5459 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5461 OPERAND_TYPE_NONE },
5462 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5464 OPERAND_TYPE_NONE },
5465 { "GOT", { BFD_RELOC_386_GOT32,
5466 BFD_RELOC_X86_64_GOT32 },
5467 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5468 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5469 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5470 OPERAND_TYPE_IMM32_32S_DISP32 },
5471 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5472 BFD_RELOC_X86_64_TLSDESC_CALL },
5473 OPERAND_TYPE_IMM32_32S_DISP32 },
5481 for (cp = input_line_pointer; *cp != '@'; cp++)
5482 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5485 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5489 len = strlen (gotrel[j].str);
5490 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5492 if (gotrel[j].rel[object_64bit] != 0)
5495 char *tmpbuf, *past_reloc;
5497 *reloc = gotrel[j].rel[object_64bit];
5503 if (flag_code != CODE_64BIT)
5505 types->bitfield.imm32 = 1;
5506 types->bitfield.disp32 = 1;
5509 *types = gotrel[j].types64;
5512 if (GOT_symbol == NULL)
5513 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5515 /* The length of the first part of our input line. */
5516 first = cp - input_line_pointer;
5518 /* The second part goes from after the reloc token until
5519 (and including) an end_of_line char or comma. */
5520 past_reloc = cp + 1 + len;
5522 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5524 second = cp + 1 - past_reloc;
5526 /* Allocate and copy string. The trailing NUL shouldn't
5527 be necessary, but be safe. */
5528 tmpbuf = xmalloc (first + second + 2);
5529 memcpy (tmpbuf, input_line_pointer, first);
5530 if (second != 0 && *past_reloc != ' ')
5531 /* Replace the relocation token with ' ', so that
5532 errors like foo@GOTOFF1 will be detected. */
5533 tmpbuf[first++] = ' ';
5534 memcpy (tmpbuf + first, past_reloc, second);
5535 tmpbuf[first + second] = '\0';
5539 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5540 gotrel[j].str, 1 << (5 + object_64bit));
5545 /* Might be a symbol version string. Don't as_bad here. */
5550 x86_cons (expressionS *exp, int size)
5552 if (size == 4 || (object_64bit && size == 8))
5554 /* Handle @GOTOFF and the like in an expression. */
5556 char *gotfree_input_line;
5559 save = input_line_pointer;
5560 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5561 if (gotfree_input_line)
5562 input_line_pointer = gotfree_input_line;
5566 if (gotfree_input_line)
5568 /* expression () has merrily parsed up to the end of line,
5569 or a comma - in the wrong buffer. Transfer how far
5570 input_line_pointer has moved to the right buffer. */
5571 input_line_pointer = (save
5572 + (input_line_pointer - gotfree_input_line)
5574 free (gotfree_input_line);
5575 if (exp->X_op == O_constant
5576 || exp->X_op == O_absent
5577 || exp->X_op == O_illegal
5578 || exp->X_op == O_register
5579 || exp->X_op == O_big)
5581 char c = *input_line_pointer;
5582 *input_line_pointer = 0;
5583 as_bad (_("missing or invalid expression `%s'"), save);
5584 *input_line_pointer = c;
5593 static void signed_cons (int size)
5595 if (flag_code == CODE_64BIT)
5603 pe_directive_secrel (dummy)
5604 int dummy ATTRIBUTE_UNUSED;
5611 if (exp.X_op == O_symbol)
5612 exp.X_op = O_secrel;
5614 emit_expr (&exp, 4);
5616 while (*input_line_pointer++ == ',');
5618 input_line_pointer--;
5619 demand_empty_rest_of_line ();
5624 i386_immediate (char *imm_start)
5626 char *save_input_line_pointer;
5627 char *gotfree_input_line;
5630 i386_operand_type types;
5632 UINTS_SET (types, ~0);
5634 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5636 as_bad (_("at most %d immediate operands are allowed"),
5637 MAX_IMMEDIATE_OPERANDS);
5641 exp = &im_expressions[i.imm_operands++];
5642 i.op[this_operand].imms = exp;
5644 if (is_space_char (*imm_start))
5647 save_input_line_pointer = input_line_pointer;
5648 input_line_pointer = imm_start;
5650 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5651 if (gotfree_input_line)
5652 input_line_pointer = gotfree_input_line;
5654 exp_seg = expression (exp);
5657 if (*input_line_pointer)
5658 as_bad (_("junk `%s' after expression"), input_line_pointer);
5660 input_line_pointer = save_input_line_pointer;
5661 if (gotfree_input_line)
5662 free (gotfree_input_line);
5664 if (exp->X_op == O_absent
5665 || exp->X_op == O_illegal
5666 || exp->X_op == O_big
5667 || (gotfree_input_line
5668 && (exp->X_op == O_constant
5669 || exp->X_op == O_register)))
5671 as_bad (_("missing or invalid immediate expression `%s'"),
5675 else if (exp->X_op == O_constant)
5677 /* Size it properly later. */
5678 i.types[this_operand].bitfield.imm64 = 1;
5679 /* If BFD64, sign extend val. */
5680 if (!use_rela_relocations
5681 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5683 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5685 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5686 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5687 && exp_seg != absolute_section
5688 && exp_seg != text_section
5689 && exp_seg != data_section
5690 && exp_seg != bss_section
5691 && exp_seg != undefined_section
5692 && !bfd_is_com_section (exp_seg))
5694 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5698 else if (!intel_syntax && exp->X_op == O_register)
5700 as_bad (_("illegal immediate register operand %s"), imm_start);
5705 /* This is an address. The size of the address will be
5706 determined later, depending on destination register,
5707 suffix, or the default for the section. */
5708 i.types[this_operand].bitfield.imm8 = 1;
5709 i.types[this_operand].bitfield.imm16 = 1;
5710 i.types[this_operand].bitfield.imm32 = 1;
5711 i.types[this_operand].bitfield.imm32s = 1;
5712 i.types[this_operand].bitfield.imm64 = 1;
5713 i.types[this_operand] = operand_type_and (i.types[this_operand],
5721 i386_scale (char *scale)
5724 char *save = input_line_pointer;
5726 input_line_pointer = scale;
5727 val = get_absolute_expression ();
5732 i.log2_scale_factor = 0;
5735 i.log2_scale_factor = 1;
5738 i.log2_scale_factor = 2;
5741 i.log2_scale_factor = 3;
5745 char sep = *input_line_pointer;
5747 *input_line_pointer = '\0';
5748 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5750 *input_line_pointer = sep;
5751 input_line_pointer = save;
5755 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5757 as_warn (_("scale factor of %d without an index register"),
5758 1 << i.log2_scale_factor);
5759 i.log2_scale_factor = 0;
5761 scale = input_line_pointer;
5762 input_line_pointer = save;
5767 i386_displacement (char *disp_start, char *disp_end)
5771 char *save_input_line_pointer;
5772 char *gotfree_input_line;
5774 i386_operand_type bigdisp, types = anydisp;
5777 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5779 as_bad (_("at most %d displacement operands are allowed"),
5780 MAX_MEMORY_OPERANDS);
5784 UINTS_CLEAR (bigdisp);
5785 if ((i.types[this_operand].bitfield.jumpabsolute)
5786 || (!current_templates->start->opcode_modifier.jump
5787 && !current_templates->start->opcode_modifier.jumpdword))
5789 bigdisp.bitfield.disp32 = 1;
5790 override = (i.prefix[ADDR_PREFIX] != 0);
5791 if (flag_code == CODE_64BIT)
5795 bigdisp.bitfield.disp32s = 1;
5796 bigdisp.bitfield.disp64 = 1;
5799 else if ((flag_code == CODE_16BIT) ^ override)
5801 bigdisp.bitfield.disp32 = 0;
5802 bigdisp.bitfield.disp16 = 1;
5807 /* For PC-relative branches, the width of the displacement
5808 is dependent upon data size, not address size. */
5809 override = (i.prefix[DATA_PREFIX] != 0);
5810 if (flag_code == CODE_64BIT)
5812 if (override || i.suffix == WORD_MNEM_SUFFIX)
5813 bigdisp.bitfield.disp16 = 1;
5816 bigdisp.bitfield.disp32 = 1;
5817 bigdisp.bitfield.disp32s = 1;
5823 override = (i.suffix == (flag_code != CODE_16BIT
5825 : LONG_MNEM_SUFFIX));
5826 bigdisp.bitfield.disp32 = 1;
5827 if ((flag_code == CODE_16BIT) ^ override)
5829 bigdisp.bitfield.disp32 = 0;
5830 bigdisp.bitfield.disp16 = 1;
5834 i.types[this_operand] = operand_type_or (i.types[this_operand],
5837 exp = &disp_expressions[i.disp_operands];
5838 i.op[this_operand].disps = exp;
5840 save_input_line_pointer = input_line_pointer;
5841 input_line_pointer = disp_start;
5842 END_STRING_AND_SAVE (disp_end);
5844 #ifndef GCC_ASM_O_HACK
5845 #define GCC_ASM_O_HACK 0
5848 END_STRING_AND_SAVE (disp_end + 1);
5849 if (i.types[this_operand].bitfield.baseIndex
5850 && displacement_string_end[-1] == '+')
5852 /* This hack is to avoid a warning when using the "o"
5853 constraint within gcc asm statements.
5856 #define _set_tssldt_desc(n,addr,limit,type) \
5857 __asm__ __volatile__ ( \
5859 "movw %w1,2+%0\n\t" \
5861 "movb %b1,4+%0\n\t" \
5862 "movb %4,5+%0\n\t" \
5863 "movb $0,6+%0\n\t" \
5864 "movb %h1,7+%0\n\t" \
5866 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5868 This works great except that the output assembler ends
5869 up looking a bit weird if it turns out that there is
5870 no offset. You end up producing code that looks like:
5883 So here we provide the missing zero. */
5885 *displacement_string_end = '0';
5888 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5889 if (gotfree_input_line)
5890 input_line_pointer = gotfree_input_line;
5892 exp_seg = expression (exp);
5895 if (*input_line_pointer)
5896 as_bad (_("junk `%s' after expression"), input_line_pointer);
5898 RESTORE_END_STRING (disp_end + 1);
5900 input_line_pointer = save_input_line_pointer;
5901 if (gotfree_input_line)
5902 free (gotfree_input_line);
5905 /* We do this to make sure that the section symbol is in
5906 the symbol table. We will ultimately change the relocation
5907 to be relative to the beginning of the section. */
5908 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5909 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5910 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5912 if (exp->X_op != O_symbol)
5915 if (S_IS_LOCAL (exp->X_add_symbol)
5916 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5917 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5918 exp->X_op = O_subtract;
5919 exp->X_op_symbol = GOT_symbol;
5920 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5921 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5922 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5923 i.reloc[this_operand] = BFD_RELOC_64;
5925 i.reloc[this_operand] = BFD_RELOC_32;
5928 else if (exp->X_op == O_absent
5929 || exp->X_op == O_illegal
5930 || exp->X_op == O_big
5931 || (gotfree_input_line
5932 && (exp->X_op == O_constant
5933 || exp->X_op == O_register)))
5936 as_bad (_("missing or invalid displacement expression `%s'"),
5941 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5942 else if (exp->X_op != O_constant
5943 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5944 && exp_seg != absolute_section
5945 && exp_seg != text_section
5946 && exp_seg != data_section
5947 && exp_seg != bss_section
5948 && exp_seg != undefined_section
5949 && !bfd_is_com_section (exp_seg))
5951 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5956 RESTORE_END_STRING (disp_end);
5958 /* Check if this is a displacement only operand. */
5959 bigdisp = i.types[this_operand];
5960 bigdisp.bitfield.disp8 = 0;
5961 bigdisp.bitfield.disp16 = 0;
5962 bigdisp.bitfield.disp32 = 0;
5963 bigdisp.bitfield.disp32s = 0;
5964 bigdisp.bitfield.disp64 = 0;
5965 if (UINTS_ALL_ZERO (bigdisp))
5966 i.types[this_operand] = operand_type_and (i.types[this_operand],
5972 /* Make sure the memory operand we've been dealt is valid.
5973 Return 1 on success, 0 on a failure. */
5976 i386_index_check (const char *operand_string)
5979 #if INFER_ADDR_PREFIX
5985 if (flag_code == CODE_64BIT)
5988 && ((i.prefix[ADDR_PREFIX] == 0
5989 && !i.base_reg->reg_type.bitfield.reg64)
5990 || (i.prefix[ADDR_PREFIX]
5991 && !i.base_reg->reg_type.bitfield.reg32))
5993 || i.base_reg->reg_num !=
5994 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
5996 && (!i.index_reg->reg_type.bitfield.baseindex
5997 || (i.prefix[ADDR_PREFIX] == 0
5998 && i.index_reg->reg_num != RegRiz
5999 && !i.index_reg->reg_type.bitfield.reg64
6001 || (i.prefix[ADDR_PREFIX]
6002 && i.index_reg->reg_num != RegEiz
6003 && !i.index_reg->reg_type.bitfield.reg32))))
6008 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6012 && (!i.base_reg->reg_type.bitfield.reg16
6013 || !i.base_reg->reg_type.bitfield.baseindex))
6015 && (!i.index_reg->reg_type.bitfield.reg16
6016 || !i.index_reg->reg_type.bitfield.baseindex
6018 && i.base_reg->reg_num < 6
6019 && i.index_reg->reg_num >= 6
6020 && i.log2_scale_factor == 0))))
6027 && !i.base_reg->reg_type.bitfield.reg32)
6029 && ((!i.index_reg->reg_type.bitfield.reg32
6030 && i.index_reg->reg_num != RegEiz)
6031 || !i.index_reg->reg_type.bitfield.baseindex)))
6037 #if INFER_ADDR_PREFIX
6038 if (i.prefix[ADDR_PREFIX] == 0)
6040 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6042 /* Change the size of any displacement too. At most one of
6043 Disp16 or Disp32 is set.
6044 FIXME. There doesn't seem to be any real need for separate
6045 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6046 Removing them would probably clean up the code quite a lot. */
6047 if (flag_code != CODE_64BIT
6048 && (i.types[this_operand].bitfield.disp16
6049 || i.types[this_operand].bitfield.disp32))
6050 i.types[this_operand]
6051 = operand_type_xor (i.types[this_operand], disp16_32);
6056 as_bad (_("`%s' is not a valid base/index expression"),
6060 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6062 flag_code_names[flag_code]);
6067 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6071 i386_operand (char *operand_string)
6075 char *op_string = operand_string;
6077 if (is_space_char (*op_string))
6080 /* We check for an absolute prefix (differentiating,
6081 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6082 if (*op_string == ABSOLUTE_PREFIX)
6085 if (is_space_char (*op_string))
6087 i.types[this_operand].bitfield.jumpabsolute = 1;
6090 /* Check if operand is a register. */
6091 if ((r = parse_register (op_string, &end_op)) != NULL)
6093 i386_operand_type temp;
6095 /* Check for a segment override by searching for ':' after a
6096 segment register. */
6098 if (is_space_char (*op_string))
6100 if (*op_string == ':'
6101 && (r->reg_type.bitfield.sreg2
6102 || r->reg_type.bitfield.sreg3))
6107 i.seg[i.mem_operands] = &es;
6110 i.seg[i.mem_operands] = &cs;
6113 i.seg[i.mem_operands] = &ss;
6116 i.seg[i.mem_operands] = &ds;
6119 i.seg[i.mem_operands] = &fs;
6122 i.seg[i.mem_operands] = &gs;
6126 /* Skip the ':' and whitespace. */
6128 if (is_space_char (*op_string))
6131 if (!is_digit_char (*op_string)
6132 && !is_identifier_char (*op_string)
6133 && *op_string != '('
6134 && *op_string != ABSOLUTE_PREFIX)
6136 as_bad (_("bad memory operand `%s'"), op_string);
6139 /* Handle case of %es:*foo. */
6140 if (*op_string == ABSOLUTE_PREFIX)
6143 if (is_space_char (*op_string))
6145 i.types[this_operand].bitfield.jumpabsolute = 1;
6147 goto do_memory_reference;
6151 as_bad (_("junk `%s' after register"), op_string);
6155 temp.bitfield.baseindex = 0;
6156 i.types[this_operand] = operand_type_or (i.types[this_operand],
6158 i.op[this_operand].regs = r;
6161 else if (*op_string == REGISTER_PREFIX)
6163 as_bad (_("bad register name `%s'"), op_string);
6166 else if (*op_string == IMMEDIATE_PREFIX)
6169 if (i.types[this_operand].bitfield.jumpabsolute)
6171 as_bad (_("immediate operand illegal with absolute jump"));
6174 if (!i386_immediate (op_string))
6177 else if (is_digit_char (*op_string)
6178 || is_identifier_char (*op_string)
6179 || *op_string == '(')
6181 /* This is a memory reference of some sort. */
6184 /* Start and end of displacement string expression (if found). */
6185 char *displacement_string_start;
6186 char *displacement_string_end;
6188 do_memory_reference:
6189 if ((i.mem_operands == 1
6190 && !current_templates->start->opcode_modifier.isstring)
6191 || i.mem_operands == 2)
6193 as_bad (_("too many memory references for `%s'"),
6194 current_templates->start->name);
6198 /* Check for base index form. We detect the base index form by
6199 looking for an ')' at the end of the operand, searching
6200 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6202 base_string = op_string + strlen (op_string);
6205 if (is_space_char (*base_string))
6208 /* If we only have a displacement, set-up for it to be parsed later. */
6209 displacement_string_start = op_string;
6210 displacement_string_end = base_string + 1;
6212 if (*base_string == ')')
6215 unsigned int parens_balanced = 1;
6216 /* We've already checked that the number of left & right ()'s are
6217 equal, so this loop will not be infinite. */
6221 if (*base_string == ')')
6223 if (*base_string == '(')
6226 while (parens_balanced);
6228 temp_string = base_string;
6230 /* Skip past '(' and whitespace. */
6232 if (is_space_char (*base_string))
6235 if (*base_string == ','
6236 || ((i.base_reg = parse_register (base_string, &end_op))
6239 displacement_string_end = temp_string;
6241 i.types[this_operand].bitfield.baseindex = 1;
6245 base_string = end_op;
6246 if (is_space_char (*base_string))
6250 /* There may be an index reg or scale factor here. */
6251 if (*base_string == ',')
6254 if (is_space_char (*base_string))
6257 if ((i.index_reg = parse_register (base_string, &end_op))
6260 base_string = end_op;
6261 if (is_space_char (*base_string))
6263 if (*base_string == ',')
6266 if (is_space_char (*base_string))
6269 else if (*base_string != ')')
6271 as_bad (_("expecting `,' or `)' "
6272 "after index register in `%s'"),
6277 else if (*base_string == REGISTER_PREFIX)
6279 as_bad (_("bad register name `%s'"), base_string);
6283 /* Check for scale factor. */
6284 if (*base_string != ')')
6286 char *end_scale = i386_scale (base_string);
6291 base_string = end_scale;
6292 if (is_space_char (*base_string))
6294 if (*base_string != ')')
6296 as_bad (_("expecting `)' "
6297 "after scale factor in `%s'"),
6302 else if (!i.index_reg)
6304 as_bad (_("expecting index register or scale factor "
6305 "after `,'; got '%c'"),
6310 else if (*base_string != ')')
6312 as_bad (_("expecting `,' or `)' "
6313 "after base register in `%s'"),
6318 else if (*base_string == REGISTER_PREFIX)
6320 as_bad (_("bad register name `%s'"), base_string);
6325 /* If there's an expression beginning the operand, parse it,
6326 assuming displacement_string_start and
6327 displacement_string_end are meaningful. */
6328 if (displacement_string_start != displacement_string_end)
6330 if (!i386_displacement (displacement_string_start,
6331 displacement_string_end))
6335 /* Special case for (%dx) while doing input/output op. */
6337 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6339 && i.log2_scale_factor == 0
6340 && i.seg[i.mem_operands] == 0
6341 && !operand_type_check (i.types[this_operand], disp))
6343 UINTS_CLEAR (i.types[this_operand]);
6344 i.types[this_operand].bitfield.inoutportreg = 1;
6348 if (i386_index_check (operand_string) == 0)
6354 /* It's not a memory operand; argh! */
6355 as_bad (_("invalid char %s beginning operand %d `%s'"),
6356 output_invalid (*op_string),
6361 return 1; /* Normal return. */
6364 /* md_estimate_size_before_relax()
6366 Called just before relax() for rs_machine_dependent frags. The x86
6367 assembler uses these frags to handle variable size jump
6370 Any symbol that is now undefined will not become defined.
6371 Return the correct fr_subtype in the frag.
6372 Return the initial "guess for variable size of frag" to caller.
6373 The guess is actually the growth beyond the fixed part. Whatever
6374 we do to grow the fixed or variable part contributes to our
6378 md_estimate_size_before_relax (fragP, segment)
6382 /* We've already got fragP->fr_subtype right; all we have to do is
6383 check for un-relaxable symbols. On an ELF system, we can't relax
6384 an externally visible symbol, because it may be overridden by a
6386 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6389 && (S_IS_EXTERNAL (fragP->fr_symbol)
6390 || S_IS_WEAK (fragP->fr_symbol)))
6394 /* Symbol is undefined in this segment, or we need to keep a
6395 reloc so that weak symbols can be overridden. */
6396 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6397 enum bfd_reloc_code_real reloc_type;
6398 unsigned char *opcode;
6401 if (fragP->fr_var != NO_RELOC)
6402 reloc_type = fragP->fr_var;
6404 reloc_type = BFD_RELOC_16_PCREL;
6406 reloc_type = BFD_RELOC_32_PCREL;
6408 old_fr_fix = fragP->fr_fix;
6409 opcode = (unsigned char *) fragP->fr_opcode;
6411 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6414 /* Make jmp (0xeb) a (d)word displacement jump. */
6416 fragP->fr_fix += size;
6417 fix_new (fragP, old_fr_fix, size,
6419 fragP->fr_offset, 1,
6425 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6427 /* Negate the condition, and branch past an
6428 unconditional jump. */
6431 /* Insert an unconditional jump. */
6433 /* We added two extra opcode bytes, and have a two byte
6435 fragP->fr_fix += 2 + 2;
6436 fix_new (fragP, old_fr_fix + 2, 2,
6438 fragP->fr_offset, 1,
6445 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6450 fixP = fix_new (fragP, old_fr_fix, 1,
6452 fragP->fr_offset, 1,
6454 fixP->fx_signed = 1;
6458 /* This changes the byte-displacement jump 0x7N
6459 to the (d)word-displacement jump 0x0f,0x8N. */
6460 opcode[1] = opcode[0] + 0x10;
6461 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6462 /* We've added an opcode byte. */
6463 fragP->fr_fix += 1 + size;
6464 fix_new (fragP, old_fr_fix + 1, size,
6466 fragP->fr_offset, 1,
6471 BAD_CASE (fragP->fr_subtype);
6475 return fragP->fr_fix - old_fr_fix;
6478 /* Guess size depending on current relax state. Initially the relax
6479 state will correspond to a short jump and we return 1, because
6480 the variable part of the frag (the branch offset) is one byte
6481 long. However, we can relax a section more than once and in that
6482 case we must either set fr_subtype back to the unrelaxed state,
6483 or return the value for the appropriate branch. */
6484 return md_relax_table[fragP->fr_subtype].rlx_length;
6487 /* Called after relax() is finished.
6489 In: Address of frag.
6490 fr_type == rs_machine_dependent.
6491 fr_subtype is what the address relaxed to.
6493 Out: Any fixSs and constants are set up.
6494 Caller will turn frag into a ".space 0". */
6497 md_convert_frag (abfd, sec, fragP)
6498 bfd *abfd ATTRIBUTE_UNUSED;
6499 segT sec ATTRIBUTE_UNUSED;
6502 unsigned char *opcode;
6503 unsigned char *where_to_put_displacement = NULL;
6504 offsetT target_address;
6505 offsetT opcode_address;
6506 unsigned int extension = 0;
6507 offsetT displacement_from_opcode_start;
6509 opcode = (unsigned char *) fragP->fr_opcode;
6511 /* Address we want to reach in file space. */
6512 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6514 /* Address opcode resides at in file space. */
6515 opcode_address = fragP->fr_address + fragP->fr_fix;
6517 /* Displacement from opcode start to fill into instruction. */
6518 displacement_from_opcode_start = target_address - opcode_address;
6520 if ((fragP->fr_subtype & BIG) == 0)
6522 /* Don't have to change opcode. */
6523 extension = 1; /* 1 opcode + 1 displacement */
6524 where_to_put_displacement = &opcode[1];
6528 if (no_cond_jump_promotion
6529 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6530 as_warn_where (fragP->fr_file, fragP->fr_line,
6531 _("long jump required"));
6533 switch (fragP->fr_subtype)
6535 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6536 extension = 4; /* 1 opcode + 4 displacement */
6538 where_to_put_displacement = &opcode[1];
6541 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6542 extension = 2; /* 1 opcode + 2 displacement */
6544 where_to_put_displacement = &opcode[1];
6547 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6548 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6549 extension = 5; /* 2 opcode + 4 displacement */
6550 opcode[1] = opcode[0] + 0x10;
6551 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6552 where_to_put_displacement = &opcode[2];
6555 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6556 extension = 3; /* 2 opcode + 2 displacement */
6557 opcode[1] = opcode[0] + 0x10;
6558 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6559 where_to_put_displacement = &opcode[2];
6562 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6567 where_to_put_displacement = &opcode[3];
6571 BAD_CASE (fragP->fr_subtype);
6576 /* If size if less then four we are sure that the operand fits,
6577 but if it's 4, then it could be that the displacement is larger
6579 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6581 && ((addressT) (displacement_from_opcode_start - extension
6582 + ((addressT) 1 << 31))
6583 > (((addressT) 2 << 31) - 1)))
6585 as_bad_where (fragP->fr_file, fragP->fr_line,
6586 _("jump target out of range"));
6587 /* Make us emit 0. */
6588 displacement_from_opcode_start = extension;
6590 /* Now put displacement after opcode. */
6591 md_number_to_chars ((char *) where_to_put_displacement,
6592 (valueT) (displacement_from_opcode_start - extension),
6593 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6594 fragP->fr_fix += extension;
6597 /* Size of byte displacement jmp. */
6598 int md_short_jump_size = 2;
6600 /* Size of dword displacement jmp. */
6601 int md_long_jump_size = 5;
6604 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6606 addressT from_addr, to_addr;
6607 fragS *frag ATTRIBUTE_UNUSED;
6608 symbolS *to_symbol ATTRIBUTE_UNUSED;
6612 offset = to_addr - (from_addr + 2);
6613 /* Opcode for byte-disp jump. */
6614 md_number_to_chars (ptr, (valueT) 0xeb, 1);
6615 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6619 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6621 addressT from_addr, to_addr;
6622 fragS *frag ATTRIBUTE_UNUSED;
6623 symbolS *to_symbol ATTRIBUTE_UNUSED;
6627 offset = to_addr - (from_addr + 5);
6628 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6629 md_number_to_chars (ptr + 1, (valueT) offset, 4);
6632 /* Apply a fixup (fixS) to segment data, once it has been determined
6633 by our caller that we have all the info we need to fix it up.
6635 On the 386, immediates, displacements, and data pointers are all in
6636 the same (little-endian) format, so we don't need to care about which
6640 md_apply_fix (fixP, valP, seg)
6641 /* The fix we're to put in. */
6643 /* Pointer to the value of the bits. */
6645 /* Segment fix is from. */
6646 segT seg ATTRIBUTE_UNUSED;
6648 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6649 valueT value = *valP;
6651 #if !defined (TE_Mach)
6654 switch (fixP->fx_r_type)
6660 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6663 case BFD_RELOC_X86_64_32S:
6664 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6667 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6670 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6675 if (fixP->fx_addsy != NULL
6676 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6677 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6678 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6679 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6680 && !use_rela_relocations)
6682 /* This is a hack. There should be a better way to handle this.
6683 This covers for the fact that bfd_install_relocation will
6684 subtract the current location (for partial_inplace, PC relative
6685 relocations); see more below. */
6689 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6692 value += fixP->fx_where + fixP->fx_frag->fr_address;
6694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6697 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6700 || (symbol_section_p (fixP->fx_addsy)
6701 && sym_seg != absolute_section))
6702 && !generic_force_reloc (fixP))
6704 /* Yes, we add the values in twice. This is because
6705 bfd_install_relocation subtracts them out again. I think
6706 bfd_install_relocation is broken, but I don't dare change
6708 value += fixP->fx_where + fixP->fx_frag->fr_address;
6712 #if defined (OBJ_COFF) && defined (TE_PE)
6713 /* For some reason, the PE format does not store a
6714 section address offset for a PC relative symbol. */
6715 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6716 || S_IS_WEAK (fixP->fx_addsy))
6717 value += md_pcrel_from (fixP);
6721 /* Fix a few things - the dynamic linker expects certain values here,
6722 and we must not disappoint it. */
6723 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6724 if (IS_ELF && fixP->fx_addsy)
6725 switch (fixP->fx_r_type)
6727 case BFD_RELOC_386_PLT32:
6728 case BFD_RELOC_X86_64_PLT32:
6729 /* Make the jump instruction point to the address of the operand. At
6730 runtime we merely add the offset to the actual PLT entry. */
6734 case BFD_RELOC_386_TLS_GD:
6735 case BFD_RELOC_386_TLS_LDM:
6736 case BFD_RELOC_386_TLS_IE_32:
6737 case BFD_RELOC_386_TLS_IE:
6738 case BFD_RELOC_386_TLS_GOTIE:
6739 case BFD_RELOC_386_TLS_GOTDESC:
6740 case BFD_RELOC_X86_64_TLSGD:
6741 case BFD_RELOC_X86_64_TLSLD:
6742 case BFD_RELOC_X86_64_GOTTPOFF:
6743 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6744 value = 0; /* Fully resolved at runtime. No addend. */
6746 case BFD_RELOC_386_TLS_LE:
6747 case BFD_RELOC_386_TLS_LDO_32:
6748 case BFD_RELOC_386_TLS_LE_32:
6749 case BFD_RELOC_X86_64_DTPOFF32:
6750 case BFD_RELOC_X86_64_DTPOFF64:
6751 case BFD_RELOC_X86_64_TPOFF32:
6752 case BFD_RELOC_X86_64_TPOFF64:
6753 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6756 case BFD_RELOC_386_TLS_DESC_CALL:
6757 case BFD_RELOC_X86_64_TLSDESC_CALL:
6758 value = 0; /* Fully resolved at runtime. No addend. */
6759 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6763 case BFD_RELOC_386_GOT32:
6764 case BFD_RELOC_X86_64_GOT32:
6765 value = 0; /* Fully resolved at runtime. No addend. */
6768 case BFD_RELOC_VTABLE_INHERIT:
6769 case BFD_RELOC_VTABLE_ENTRY:
6776 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6778 #endif /* !defined (TE_Mach) */
6780 /* Are we finished with this relocation now? */
6781 if (fixP->fx_addsy == NULL)
6783 else if (use_rela_relocations)
6785 fixP->fx_no_overflow = 1;
6786 /* Remember value for tc_gen_reloc. */
6787 fixP->fx_addnumber = value;
6791 md_number_to_chars (p, value, fixP->fx_size);
6794 #define MAX_LITTLENUMS 6
6796 /* Turn the string pointed to by litP into a floating point constant
6797 of type TYPE, and emit the appropriate bytes. The number of
6798 LITTLENUMS emitted is stored in *SIZEP. An error message is
6799 returned, or NULL on OK. */
6802 md_atof (type, litP, sizeP)
6808 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6809 LITTLENUM_TYPE *wordP;
6831 return _("Bad call to md_atof ()");
6833 t = atof_ieee (input_line_pointer, type, words);
6835 input_line_pointer = t;
6837 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6838 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6839 the bigendian 386. */
6840 for (wordP = words + prec - 1; prec--;)
6842 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6843 litP += sizeof (LITTLENUM_TYPE);
6848 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6851 output_invalid (int c)
6854 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6857 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6858 "(0x%x)", (unsigned char) c);
6859 return output_invalid_buf;
6862 /* REG_STRING starts *before* REGISTER_PREFIX. */
6864 static const reg_entry *
6865 parse_real_register (char *reg_string, char **end_op)
6867 char *s = reg_string;
6869 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6872 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6873 if (*s == REGISTER_PREFIX)
6876 if (is_space_char (*s))
6880 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6882 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6883 return (const reg_entry *) NULL;
6887 /* For naked regs, make sure that we are not dealing with an identifier.
6888 This prevents confusing an identifier like `eax_var' with register
6890 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6891 return (const reg_entry *) NULL;
6895 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6897 /* Handle floating point regs, allowing spaces in the (i) part. */
6898 if (r == i386_regtab /* %st is first entry of table */)
6900 if (is_space_char (*s))
6905 if (is_space_char (*s))
6907 if (*s >= '0' && *s <= '7')
6911 if (is_space_char (*s))
6916 r = hash_find (reg_hash, "st(0)");
6921 /* We have "%st(" then garbage. */
6922 return (const reg_entry *) NULL;
6926 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6929 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6930 return (const reg_entry *) NULL;
6933 && ((r->reg_flags & (RegRex64 | RegRex))
6934 || r->reg_type.bitfield.reg64)
6935 && (!cpu_arch_flags.bitfield.cpulm
6936 || !UINTS_EQUAL (r->reg_type, control))
6937 && flag_code != CODE_64BIT)
6938 return (const reg_entry *) NULL;
6943 /* REG_STRING starts *before* REGISTER_PREFIX. */
6945 static const reg_entry *
6946 parse_register (char *reg_string, char **end_op)
6950 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6951 r = parse_real_register (reg_string, end_op);
6956 char *save = input_line_pointer;
6960 input_line_pointer = reg_string;
6961 c = get_symbol_end ();
6962 symbolP = symbol_find (reg_string);
6963 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6965 const expressionS *e = symbol_get_value_expression (symbolP);
6967 know (e->X_op == O_register);
6968 know (e->X_add_number >= 0
6969 && (valueT) e->X_add_number < i386_regtab_size);
6970 r = i386_regtab + e->X_add_number;
6971 *end_op = input_line_pointer;
6973 *input_line_pointer = c;
6974 input_line_pointer = save;
6980 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6983 char *end = input_line_pointer;
6986 r = parse_register (name, &input_line_pointer);
6987 if (r && end <= input_line_pointer)
6989 *nextcharP = *input_line_pointer;
6990 *input_line_pointer = 0;
6991 e->X_op = O_register;
6992 e->X_add_number = r - i386_regtab;
6995 input_line_pointer = end;
7001 md_operand (expressionS *e)
7003 if (*input_line_pointer == REGISTER_PREFIX)
7006 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7010 e->X_op = O_register;
7011 e->X_add_number = r - i386_regtab;
7012 input_line_pointer = end;
7018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7019 const char *md_shortopts = "kVQ:sqn";
7021 const char *md_shortopts = "qn";
7024 #define OPTION_32 (OPTION_MD_BASE + 0)
7025 #define OPTION_64 (OPTION_MD_BASE + 1)
7026 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7027 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7028 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7030 struct option md_longopts[] =
7032 {"32", no_argument, NULL, OPTION_32},
7033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7034 {"64", no_argument, NULL, OPTION_64},
7036 {"divide", no_argument, NULL, OPTION_DIVIDE},
7037 {"march", required_argument, NULL, OPTION_MARCH},
7038 {"mtune", required_argument, NULL, OPTION_MTUNE},
7039 {NULL, no_argument, NULL, 0}
7041 size_t md_longopts_size = sizeof (md_longopts);
7044 md_parse_option (int c, char *arg)
7051 optimize_align_code = 0;
7058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7059 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7060 should be emitted or not. FIXME: Not implemented. */
7064 /* -V: SVR4 argument to print version ID. */
7066 print_version_id ();
7069 /* -k: Ignore for FreeBSD compatibility. */
7074 /* -s: On i386 Solaris, this tells the native assembler to use
7075 .stab instead of .stab.excl. We always use .stab anyhow. */
7078 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7081 const char **list, **l;
7083 list = bfd_target_list ();
7084 for (l = list; *l != NULL; l++)
7085 if (CONST_STRNEQ (*l, "elf64-x86-64")
7086 || strcmp (*l, "coff-x86-64") == 0
7087 || strcmp (*l, "pe-x86-64") == 0
7088 || strcmp (*l, "pei-x86-64") == 0)
7090 default_arch = "x86_64";
7094 as_fatal (_("No compiled in support for x86_64"));
7101 default_arch = "i386";
7105 #ifdef SVR4_COMMENT_CHARS
7110 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7112 for (s = i386_comment_chars; *s != '\0'; s++)
7116 i386_comment_chars = n;
7123 as_fatal (_("Invalid -march= option: `%s'"), arg);
7124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7126 if (strcmp (arg, cpu_arch [i].name) == 0)
7128 cpu_arch_isa = cpu_arch[i].type;
7129 cpu_arch_isa_flags = cpu_arch[i].flags;
7130 if (!cpu_arch_tune_set)
7132 cpu_arch_tune = cpu_arch_isa;
7133 cpu_arch_tune_flags = cpu_arch_isa_flags;
7138 if (i >= ARRAY_SIZE (cpu_arch))
7139 as_fatal (_("Invalid -march= option: `%s'"), arg);
7144 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7145 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7147 if (strcmp (arg, cpu_arch [i].name) == 0)
7149 cpu_arch_tune_set = 1;
7150 cpu_arch_tune = cpu_arch [i].type;
7151 cpu_arch_tune_flags = cpu_arch[i].flags;
7155 if (i >= ARRAY_SIZE (cpu_arch))
7156 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7166 md_show_usage (stream)
7169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7170 fprintf (stream, _("\
7172 -V print assembler version number\n\
7175 fprintf (stream, _("\
7176 -n Do not optimize code alignment\n\
7177 -q quieten some warnings\n"));
7178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7179 fprintf (stream, _("\
7182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7183 fprintf (stream, _("\
7184 --32/--64 generate 32bit/64bit code\n"));
7186 #ifdef SVR4_COMMENT_CHARS
7187 fprintf (stream, _("\
7188 --divide do not treat `/' as a comment character\n"));
7190 fprintf (stream, _("\
7191 --divide ignored\n"));
7193 fprintf (stream, _("\
7194 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7195 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7196 core, core2, k6, athlon, k8, generic32, generic64\n"));
7200 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7201 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7203 /* Pick the target format to use. */
7206 i386_target_format (void)
7208 if (!strcmp (default_arch, "x86_64"))
7210 set_code_flag (CODE_64BIT);
7211 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7213 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7214 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7215 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7216 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7217 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7218 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7219 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7220 cpu_arch_isa_flags.bitfield.cpummx= 1;
7221 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7222 cpu_arch_isa_flags.bitfield.cpusse = 1;
7223 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7225 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7227 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7228 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7229 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7230 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7231 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7232 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7233 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7234 cpu_arch_tune_flags.bitfield.cpummx= 1;
7235 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7236 cpu_arch_tune_flags.bitfield.cpusse = 1;
7237 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7240 else if (!strcmp (default_arch, "i386"))
7242 set_code_flag (CODE_32BIT);
7243 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7245 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7246 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7247 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7249 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7251 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7252 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7253 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7257 as_fatal (_("Unknown architecture"));
7258 switch (OUTPUT_FLAVOR)
7261 case bfd_target_coff_flavour:
7262 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7265 #ifdef OBJ_MAYBE_AOUT
7266 case bfd_target_aout_flavour:
7267 return AOUT_TARGET_FORMAT;
7269 #ifdef OBJ_MAYBE_COFF
7270 case bfd_target_coff_flavour:
7273 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7274 case bfd_target_elf_flavour:
7276 if (flag_code == CODE_64BIT)
7279 use_rela_relocations = 1;
7281 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7290 #endif /* OBJ_MAYBE_ more than one */
7292 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7294 i386_elf_emit_arch_note (void)
7296 if (IS_ELF && cpu_arch_name != NULL)
7299 asection *seg = now_seg;
7300 subsegT subseg = now_subseg;
7301 Elf_Internal_Note i_note;
7302 Elf_External_Note e_note;
7303 asection *note_secp;
7306 /* Create the .note section. */
7307 note_secp = subseg_new (".note", 0);
7308 bfd_set_section_flags (stdoutput,
7310 SEC_HAS_CONTENTS | SEC_READONLY);
7312 /* Process the arch string. */
7313 len = strlen (cpu_arch_name);
7315 i_note.namesz = len + 1;
7317 i_note.type = NT_ARCH;
7318 p = frag_more (sizeof (e_note.namesz));
7319 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7320 p = frag_more (sizeof (e_note.descsz));
7321 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7322 p = frag_more (sizeof (e_note.type));
7323 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7324 p = frag_more (len + 1);
7325 strcpy (p, cpu_arch_name);
7327 frag_align (2, 0, 0);
7329 subseg_set (seg, subseg);
7335 md_undefined_symbol (name)
7338 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7339 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7340 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7341 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7345 if (symbol_find (name))
7346 as_bad (_("GOT already in symbol table"));
7347 GOT_symbol = symbol_new (name, undefined_section,
7348 (valueT) 0, &zero_address_frag);
7355 /* Round up a section size to the appropriate boundary. */
7358 md_section_align (segment, size)
7359 segT segment ATTRIBUTE_UNUSED;
7362 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7363 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7365 /* For a.out, force the section size to be aligned. If we don't do
7366 this, BFD will align it for us, but it will not write out the
7367 final bytes of the section. This may be a bug in BFD, but it is
7368 easier to fix it here since that is how the other a.out targets
7372 align = bfd_get_section_alignment (stdoutput, segment);
7373 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7380 /* On the i386, PC-relative offsets are relative to the start of the
7381 next instruction. That is, the address of the offset, plus its
7382 size, since the offset is always the last part of the insn. */
7385 md_pcrel_from (fixS *fixP)
7387 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7393 s_bss (int ignore ATTRIBUTE_UNUSED)
7397 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7399 obj_elf_section_change_hook ();
7401 temp = get_absolute_expression ();
7402 subseg_set (bss_section, (subsegT) temp);
7403 demand_empty_rest_of_line ();
7409 i386_validate_fix (fixS *fixp)
7411 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7413 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7417 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7422 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7424 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7431 tc_gen_reloc (section, fixp)
7432 asection *section ATTRIBUTE_UNUSED;
7436 bfd_reloc_code_real_type code;
7438 switch (fixp->fx_r_type)
7440 case BFD_RELOC_X86_64_PLT32:
7441 case BFD_RELOC_X86_64_GOT32:
7442 case BFD_RELOC_X86_64_GOTPCREL:
7443 case BFD_RELOC_386_PLT32:
7444 case BFD_RELOC_386_GOT32:
7445 case BFD_RELOC_386_GOTOFF:
7446 case BFD_RELOC_386_GOTPC:
7447 case BFD_RELOC_386_TLS_GD:
7448 case BFD_RELOC_386_TLS_LDM:
7449 case BFD_RELOC_386_TLS_LDO_32:
7450 case BFD_RELOC_386_TLS_IE_32:
7451 case BFD_RELOC_386_TLS_IE:
7452 case BFD_RELOC_386_TLS_GOTIE:
7453 case BFD_RELOC_386_TLS_LE_32:
7454 case BFD_RELOC_386_TLS_LE:
7455 case BFD_RELOC_386_TLS_GOTDESC:
7456 case BFD_RELOC_386_TLS_DESC_CALL:
7457 case BFD_RELOC_X86_64_TLSGD:
7458 case BFD_RELOC_X86_64_TLSLD:
7459 case BFD_RELOC_X86_64_DTPOFF32:
7460 case BFD_RELOC_X86_64_DTPOFF64:
7461 case BFD_RELOC_X86_64_GOTTPOFF:
7462 case BFD_RELOC_X86_64_TPOFF32:
7463 case BFD_RELOC_X86_64_TPOFF64:
7464 case BFD_RELOC_X86_64_GOTOFF64:
7465 case BFD_RELOC_X86_64_GOTPC32:
7466 case BFD_RELOC_X86_64_GOT64:
7467 case BFD_RELOC_X86_64_GOTPCREL64:
7468 case BFD_RELOC_X86_64_GOTPC64:
7469 case BFD_RELOC_X86_64_GOTPLT64:
7470 case BFD_RELOC_X86_64_PLTOFF64:
7471 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7472 case BFD_RELOC_X86_64_TLSDESC_CALL:
7474 case BFD_RELOC_VTABLE_ENTRY:
7475 case BFD_RELOC_VTABLE_INHERIT:
7477 case BFD_RELOC_32_SECREL:
7479 code = fixp->fx_r_type;
7481 case BFD_RELOC_X86_64_32S:
7482 if (!fixp->fx_pcrel)
7484 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7485 code = fixp->fx_r_type;
7491 switch (fixp->fx_size)
7494 as_bad_where (fixp->fx_file, fixp->fx_line,
7495 _("can not do %d byte pc-relative relocation"),
7497 code = BFD_RELOC_32_PCREL;
7499 case 1: code = BFD_RELOC_8_PCREL; break;
7500 case 2: code = BFD_RELOC_16_PCREL; break;
7501 case 4: code = BFD_RELOC_32_PCREL; break;
7503 case 8: code = BFD_RELOC_64_PCREL; break;
7509 switch (fixp->fx_size)
7512 as_bad_where (fixp->fx_file, fixp->fx_line,
7513 _("can not do %d byte relocation"),
7515 code = BFD_RELOC_32;
7517 case 1: code = BFD_RELOC_8; break;
7518 case 2: code = BFD_RELOC_16; break;
7519 case 4: code = BFD_RELOC_32; break;
7521 case 8: code = BFD_RELOC_64; break;
7528 if ((code == BFD_RELOC_32
7529 || code == BFD_RELOC_32_PCREL
7530 || code == BFD_RELOC_X86_64_32S)
7532 && fixp->fx_addsy == GOT_symbol)
7535 code = BFD_RELOC_386_GOTPC;
7537 code = BFD_RELOC_X86_64_GOTPC32;
7539 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7541 && fixp->fx_addsy == GOT_symbol)
7543 code = BFD_RELOC_X86_64_GOTPC64;
7546 rel = (arelent *) xmalloc (sizeof (arelent));
7547 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7548 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7550 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7552 if (!use_rela_relocations)
7554 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7555 vtable entry to be used in the relocation's section offset. */
7556 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7557 rel->address = fixp->fx_offset;
7561 /* Use the rela in 64bit mode. */
7564 if (!fixp->fx_pcrel)
7565 rel->addend = fixp->fx_offset;
7569 case BFD_RELOC_X86_64_PLT32:
7570 case BFD_RELOC_X86_64_GOT32:
7571 case BFD_RELOC_X86_64_GOTPCREL:
7572 case BFD_RELOC_X86_64_TLSGD:
7573 case BFD_RELOC_X86_64_TLSLD:
7574 case BFD_RELOC_X86_64_GOTTPOFF:
7575 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7576 case BFD_RELOC_X86_64_TLSDESC_CALL:
7577 rel->addend = fixp->fx_offset - fixp->fx_size;
7580 rel->addend = (section->vma
7582 + fixp->fx_addnumber
7583 + md_pcrel_from (fixp));
7588 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7589 if (rel->howto == NULL)
7591 as_bad_where (fixp->fx_file, fixp->fx_line,
7592 _("cannot represent relocation type %s"),
7593 bfd_get_reloc_code_name (code));
7594 /* Set howto to a garbage value so that we can keep going. */
7595 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7596 assert (rel->howto != NULL);
7603 /* Parse operands using Intel syntax. This implements a recursive descent
7604 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7607 FIXME: We do not recognize the full operand grammar defined in the MASM
7608 documentation. In particular, all the structure/union and
7609 high-level macro operands are missing.
7611 Uppercase words are terminals, lower case words are non-terminals.
7612 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7613 bars '|' denote choices. Most grammar productions are implemented in
7614 functions called 'intel_<production>'.
7616 Initial production is 'expr'.
7622 binOp & | AND | \| | OR | ^ | XOR
7624 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7626 constant digits [[ radixOverride ]]
7628 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7666 => expr expr cmpOp e04
7669 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7670 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7672 hexdigit a | b | c | d | e | f
7673 | A | B | C | D | E | F
7679 mulOp * | / | % | MOD | << | SHL | >> | SHR
7683 register specialRegister
7687 segmentRegister CS | DS | ES | FS | GS | SS
7689 specialRegister CR0 | CR2 | CR3 | CR4
7690 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7691 | TR3 | TR4 | TR5 | TR6 | TR7
7693 We simplify the grammar in obvious places (e.g., register parsing is
7694 done by calling parse_register) and eliminate immediate left recursion
7695 to implement a recursive-descent parser.
7699 expr' cmpOp e04 expr'
7750 /* Parsing structure for the intel syntax parser. Used to implement the
7751 semantic actions for the operand grammar. */
7752 struct intel_parser_s
7754 char *op_string; /* The string being parsed. */
7755 int got_a_float; /* Whether the operand is a float. */
7756 int op_modifier; /* Operand modifier. */
7757 int is_mem; /* 1 if operand is memory reference. */
7758 int in_offset; /* >=1 if parsing operand of offset. */
7759 int in_bracket; /* >=1 if parsing operand in brackets. */
7760 const reg_entry *reg; /* Last register reference found. */
7761 char *disp; /* Displacement string being built. */
7762 char *next_operand; /* Resume point when splitting operands. */
7765 static struct intel_parser_s intel_parser;
7767 /* Token structure for parsing intel syntax. */
7770 int code; /* Token code. */
7771 const reg_entry *reg; /* Register entry for register tokens. */
7772 char *str; /* String representation. */
7775 static struct intel_token cur_token, prev_token;
7777 /* Token codes for the intel parser. Since T_SHORT is already used
7778 by COFF, undefine it first to prevent a warning. */
7797 /* Prototypes for intel parser functions. */
7798 static int intel_match_token (int);
7799 static void intel_putback_token (void);
7800 static void intel_get_token (void);
7801 static int intel_expr (void);
7802 static int intel_e04 (void);
7803 static int intel_e05 (void);
7804 static int intel_e06 (void);
7805 static int intel_e09 (void);
7806 static int intel_e10 (void);
7807 static int intel_e11 (void);
7810 i386_intel_operand (char *operand_string, int got_a_float)
7815 p = intel_parser.op_string = xstrdup (operand_string);
7816 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7820 /* Initialize token holders. */
7821 cur_token.code = prev_token.code = T_NIL;
7822 cur_token.reg = prev_token.reg = NULL;
7823 cur_token.str = prev_token.str = NULL;
7825 /* Initialize parser structure. */
7826 intel_parser.got_a_float = got_a_float;
7827 intel_parser.op_modifier = 0;
7828 intel_parser.is_mem = 0;
7829 intel_parser.in_offset = 0;
7830 intel_parser.in_bracket = 0;
7831 intel_parser.reg = NULL;
7832 intel_parser.disp[0] = '\0';
7833 intel_parser.next_operand = NULL;
7835 /* Read the first token and start the parser. */
7837 ret = intel_expr ();
7842 if (cur_token.code != T_NIL)
7844 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7845 current_templates->start->name, cur_token.str);
7848 /* If we found a memory reference, hand it over to i386_displacement
7849 to fill in the rest of the operand fields. */
7850 else if (intel_parser.is_mem)
7852 if ((i.mem_operands == 1
7853 && !current_templates->start->opcode_modifier.isstring)
7854 || i.mem_operands == 2)
7856 as_bad (_("too many memory references for '%s'"),
7857 current_templates->start->name);
7862 char *s = intel_parser.disp;
7865 if (!quiet_warnings && intel_parser.is_mem < 0)
7866 /* See the comments in intel_bracket_expr. */
7867 as_warn (_("Treating `%s' as memory reference"), operand_string);
7869 /* Add the displacement expression. */
7871 ret = i386_displacement (s, s + strlen (s));
7874 /* Swap base and index in 16-bit memory operands like
7875 [si+bx]. Since i386_index_check is also used in AT&T
7876 mode we have to do that here. */
7879 && i.base_reg->reg_type.bitfield.reg16
7880 && i.index_reg->reg_type.bitfield.reg16
7881 && i.base_reg->reg_num >= 6
7882 && i.index_reg->reg_num < 6)
7884 const reg_entry *base = i.index_reg;
7886 i.index_reg = i.base_reg;
7889 ret = i386_index_check (operand_string);
7894 /* Constant and OFFSET expressions are handled by i386_immediate. */
7895 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7896 || intel_parser.reg == NULL)
7897 ret = i386_immediate (intel_parser.disp);
7899 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7901 if (!ret || !intel_parser.next_operand)
7903 intel_parser.op_string = intel_parser.next_operand;
7904 this_operand = i.operands++;
7908 free (intel_parser.disp);
7913 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7917 expr' cmpOp e04 expr'
7922 /* XXX Implement the comparison operators. */
7923 return intel_e04 ();
7940 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7941 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7943 if (cur_token.code == '+')
7945 else if (cur_token.code == '-')
7946 nregs = NUM_ADDRESS_REGS;
7950 strcat (intel_parser.disp, cur_token.str);
7951 intel_match_token (cur_token.code);
7962 int nregs = ~NUM_ADDRESS_REGS;
7969 if (cur_token.code == '&'
7970 || cur_token.code == '|'
7971 || cur_token.code == '^')
7975 str[0] = cur_token.code;
7977 strcat (intel_parser.disp, str);
7982 intel_match_token (cur_token.code);
7987 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7988 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7999 int nregs = ~NUM_ADDRESS_REGS;
8006 if (cur_token.code == '*'
8007 || cur_token.code == '/'
8008 || cur_token.code == '%')
8012 str[0] = cur_token.code;
8014 strcat (intel_parser.disp, str);
8016 else if (cur_token.code == T_SHL)
8017 strcat (intel_parser.disp, "<<");
8018 else if (cur_token.code == T_SHR)
8019 strcat (intel_parser.disp, ">>");
8023 intel_match_token (cur_token.code);
8028 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8029 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8047 int nregs = ~NUM_ADDRESS_REGS;
8052 /* Don't consume constants here. */
8053 if (cur_token.code == '+' || cur_token.code == '-')
8055 /* Need to look one token ahead - if the next token
8056 is a constant, the current token is its sign. */
8059 intel_match_token (cur_token.code);
8060 next_code = cur_token.code;
8061 intel_putback_token ();
8062 if (next_code == T_CONST)
8066 /* e09 OFFSET e09 */
8067 if (cur_token.code == T_OFFSET)
8070 ++intel_parser.in_offset;
8074 else if (cur_token.code == T_SHORT)
8075 intel_parser.op_modifier |= 1 << T_SHORT;
8078 else if (cur_token.code == '+')
8079 strcat (intel_parser.disp, "+");
8084 else if (cur_token.code == '-' || cur_token.code == '~')
8090 str[0] = cur_token.code;
8092 strcat (intel_parser.disp, str);
8099 intel_match_token (cur_token.code);
8107 /* e09' PTR e10 e09' */
8108 if (cur_token.code == T_PTR)
8112 if (prev_token.code == T_BYTE)
8113 suffix = BYTE_MNEM_SUFFIX;
8115 else if (prev_token.code == T_WORD)
8117 if (current_templates->start->name[0] == 'l'
8118 && current_templates->start->name[2] == 's'
8119 && current_templates->start->name[3] == 0)
8120 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8121 else if (intel_parser.got_a_float == 2) /* "fi..." */
8122 suffix = SHORT_MNEM_SUFFIX;
8124 suffix = WORD_MNEM_SUFFIX;
8127 else if (prev_token.code == T_DWORD)
8129 if (current_templates->start->name[0] == 'l'
8130 && current_templates->start->name[2] == 's'
8131 && current_templates->start->name[3] == 0)
8132 suffix = WORD_MNEM_SUFFIX;
8133 else if (flag_code == CODE_16BIT
8134 && (current_templates->start->opcode_modifier.jump
8135 || current_templates->start->opcode_modifier.jumpdword))
8136 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8137 else if (intel_parser.got_a_float == 1) /* "f..." */
8138 suffix = SHORT_MNEM_SUFFIX;
8140 suffix = LONG_MNEM_SUFFIX;
8143 else if (prev_token.code == T_FWORD)
8145 if (current_templates->start->name[0] == 'l'
8146 && current_templates->start->name[2] == 's'
8147 && current_templates->start->name[3] == 0)
8148 suffix = LONG_MNEM_SUFFIX;
8149 else if (!intel_parser.got_a_float)
8151 if (flag_code == CODE_16BIT)
8152 add_prefix (DATA_PREFIX_OPCODE);
8153 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8156 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8159 else if (prev_token.code == T_QWORD)
8161 if (intel_parser.got_a_float == 1) /* "f..." */
8162 suffix = LONG_MNEM_SUFFIX;
8164 suffix = QWORD_MNEM_SUFFIX;
8167 else if (prev_token.code == T_TBYTE)
8169 if (intel_parser.got_a_float == 1)
8170 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8172 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8175 else if (prev_token.code == T_XMMWORD)
8177 /* XXX ignored for now, but accepted since gcc uses it */
8183 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8187 /* Operands for jump/call using 'ptr' notation denote absolute
8189 if (current_templates->start->opcode_modifier.jump
8190 || current_templates->start->opcode_modifier.jumpdword)
8191 i.types[this_operand].bitfield.jumpabsolute = 1;
8193 if (current_templates->start->base_opcode == 0x8d /* lea */)
8197 else if (i.suffix != suffix)
8199 as_bad (_("Conflicting operand modifiers"));
8205 /* e09' : e10 e09' */
8206 else if (cur_token.code == ':')
8208 if (prev_token.code != T_REG)
8210 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8211 segment/group identifier (which we don't have), using comma
8212 as the operand separator there is even less consistent, since
8213 there all branches only have a single operand. */
8214 if (this_operand != 0
8215 || intel_parser.in_offset
8216 || intel_parser.in_bracket
8217 || (!current_templates->start->opcode_modifier.jump
8218 && !current_templates->start->opcode_modifier.jumpdword
8219 && !current_templates->start->opcode_modifier.jumpintersegment
8220 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8221 return intel_match_token (T_NIL);
8222 /* Remember the start of the 2nd operand and terminate 1st
8224 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8225 another expression), but it gets at least the simplest case
8226 (a plain number or symbol on the left side) right. */
8227 intel_parser.next_operand = intel_parser.op_string;
8228 *--intel_parser.op_string = '\0';
8229 return intel_match_token (':');
8237 intel_match_token (cur_token.code);
8243 --intel_parser.in_offset;
8246 if (NUM_ADDRESS_REGS > nregs)
8248 as_bad (_("Invalid operand to `OFFSET'"));
8251 intel_parser.op_modifier |= 1 << T_OFFSET;
8254 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8255 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8260 intel_bracket_expr (void)
8262 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8263 const char *start = intel_parser.op_string;
8266 if (i.op[this_operand].regs)
8267 return intel_match_token (T_NIL);
8269 intel_match_token ('[');
8271 /* Mark as a memory operand only if it's not already known to be an
8272 offset expression. If it's an offset expression, we need to keep
8274 if (!intel_parser.in_offset)
8276 ++intel_parser.in_bracket;
8278 /* Operands for jump/call inside brackets denote absolute addresses. */
8279 if (current_templates->start->opcode_modifier.jump
8280 || current_templates->start->opcode_modifier.jumpdword)
8281 i.types[this_operand].bitfield.jumpabsolute = 1;
8283 /* Unfortunately gas always diverged from MASM in a respect that can't
8284 be easily fixed without risking to break code sequences likely to be
8285 encountered (the testsuite even check for this): MASM doesn't consider
8286 an expression inside brackets unconditionally as a memory reference.
8287 When that is e.g. a constant, an offset expression, or the sum of the
8288 two, this is still taken as a constant load. gas, however, always
8289 treated these as memory references. As a compromise, we'll try to make
8290 offset expressions inside brackets work the MASM way (since that's
8291 less likely to be found in real world code), but make constants alone
8292 continue to work the traditional gas way. In either case, issue a
8294 intel_parser.op_modifier &= ~was_offset;
8297 strcat (intel_parser.disp, "[");
8299 /* Add a '+' to the displacement string if necessary. */
8300 if (*intel_parser.disp != '\0'
8301 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8302 strcat (intel_parser.disp, "+");
8305 && (len = intel_parser.op_string - start - 1,
8306 intel_match_token (']')))
8308 /* Preserve brackets when the operand is an offset expression. */
8309 if (intel_parser.in_offset)
8310 strcat (intel_parser.disp, "]");
8313 --intel_parser.in_bracket;
8314 if (i.base_reg || i.index_reg)
8315 intel_parser.is_mem = 1;
8316 if (!intel_parser.is_mem)
8318 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8319 /* Defer the warning until all of the operand was parsed. */
8320 intel_parser.is_mem = -1;
8321 else if (!quiet_warnings)
8322 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8323 len, start, len, start);
8326 intel_parser.op_modifier |= was_offset;
8343 while (cur_token.code == '[')
8345 if (!intel_bracket_expr ())
8370 switch (cur_token.code)
8374 intel_match_token ('(');
8375 strcat (intel_parser.disp, "(");
8377 if (intel_expr () && intel_match_token (')'))
8379 strcat (intel_parser.disp, ")");
8386 return intel_bracket_expr ();
8391 strcat (intel_parser.disp, cur_token.str);
8392 intel_match_token (cur_token.code);
8394 /* Mark as a memory operand only if it's not already known to be an
8395 offset expression. */
8396 if (!intel_parser.in_offset)
8397 intel_parser.is_mem = 1;
8404 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8406 intel_match_token (T_REG);
8408 /* Check for segment change. */
8409 if (cur_token.code == ':')
8411 if (!reg->reg_type.bitfield.sreg2
8412 && !reg->reg_type.bitfield.sreg3)
8414 as_bad (_("`%s' is not a valid segment register"),
8418 else if (i.seg[i.mem_operands])
8419 as_warn (_("Extra segment override ignored"));
8422 if (!intel_parser.in_offset)
8423 intel_parser.is_mem = 1;
8424 switch (reg->reg_num)
8427 i.seg[i.mem_operands] = &es;
8430 i.seg[i.mem_operands] = &cs;
8433 i.seg[i.mem_operands] = &ss;
8436 i.seg[i.mem_operands] = &ds;
8439 i.seg[i.mem_operands] = &fs;
8442 i.seg[i.mem_operands] = &gs;
8448 /* Not a segment register. Check for register scaling. */
8449 else if (cur_token.code == '*')
8451 if (!intel_parser.in_bracket)
8453 as_bad (_("Register scaling only allowed in memory operands"));
8457 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8458 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8459 else if (i.index_reg)
8460 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8462 /* What follows must be a valid scale. */
8463 intel_match_token ('*');
8465 i.types[this_operand].bitfield.baseindex = 1;
8467 /* Set the scale after setting the register (otherwise,
8468 i386_scale will complain) */
8469 if (cur_token.code == '+' || cur_token.code == '-')
8471 char *str, sign = cur_token.code;
8472 intel_match_token (cur_token.code);
8473 if (cur_token.code != T_CONST)
8475 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8479 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8480 strcpy (str + 1, cur_token.str);
8482 if (!i386_scale (str))
8486 else if (!i386_scale (cur_token.str))
8488 intel_match_token (cur_token.code);
8491 /* No scaling. If this is a memory operand, the register is either a
8492 base register (first occurrence) or an index register (second
8494 else if (intel_parser.in_bracket)
8499 else if (!i.index_reg)
8503 as_bad (_("Too many register references in memory operand"));
8507 i.types[this_operand].bitfield.baseindex = 1;
8510 /* It's neither base nor index. */
8511 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8513 i386_operand_type temp = reg->reg_type;
8514 temp.bitfield.baseindex = 0;
8515 i.types[this_operand] = operand_type_or (i.types[this_operand],
8517 i.op[this_operand].regs = reg;
8522 as_bad (_("Invalid use of register"));
8526 /* Since registers are not part of the displacement string (except
8527 when we're parsing offset operands), we may need to remove any
8528 preceding '+' from the displacement string. */
8529 if (*intel_parser.disp != '\0'
8530 && !intel_parser.in_offset)
8532 char *s = intel_parser.disp;
8533 s += strlen (s) - 1;
8556 intel_match_token (cur_token.code);
8558 if (cur_token.code == T_PTR)
8561 /* It must have been an identifier. */
8562 intel_putback_token ();
8563 cur_token.code = T_ID;
8569 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8573 /* The identifier represents a memory reference only if it's not
8574 preceded by an offset modifier and if it's not an equate. */
8575 symbolP = symbol_find(cur_token.str);
8576 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8577 intel_parser.is_mem = 1;
8585 char *save_str, sign = 0;
8587 /* Allow constants that start with `+' or `-'. */
8588 if (cur_token.code == '-' || cur_token.code == '+')
8590 sign = cur_token.code;
8591 intel_match_token (cur_token.code);
8592 if (cur_token.code != T_CONST)
8594 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8600 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8601 strcpy (save_str + !!sign, cur_token.str);
8605 /* Get the next token to check for register scaling. */
8606 intel_match_token (cur_token.code);
8608 /* Check if this constant is a scaling factor for an
8610 if (cur_token.code == '*')
8612 if (intel_match_token ('*') && cur_token.code == T_REG)
8614 const reg_entry *reg = cur_token.reg;
8616 if (!intel_parser.in_bracket)
8618 as_bad (_("Register scaling only allowed "
8619 "in memory operands"));
8623 /* Disallow things like [1*si].
8624 sp and esp are invalid as index. */
8625 if (reg->reg_type.bitfield.reg16)
8626 reg = i386_regtab + REGNAM_AX + 4;
8627 else if (i.index_reg)
8628 reg = i386_regtab + REGNAM_EAX + 4;
8630 /* The constant is followed by `* reg', so it must be
8633 i.types[this_operand].bitfield.baseindex = 1;
8635 /* Set the scale after setting the register (otherwise,
8636 i386_scale will complain) */
8637 if (!i386_scale (save_str))
8639 intel_match_token (T_REG);
8641 /* Since registers are not part of the displacement
8642 string, we may need to remove any preceding '+' from
8643 the displacement string. */
8644 if (*intel_parser.disp != '\0')
8646 char *s = intel_parser.disp;
8647 s += strlen (s) - 1;
8657 /* The constant was not used for register scaling. Since we have
8658 already consumed the token following `*' we now need to put it
8659 back in the stream. */
8660 intel_putback_token ();
8663 /* Add the constant to the displacement string. */
8664 strcat (intel_parser.disp, save_str);
8671 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8675 /* Match the given token against cur_token. If they match, read the next
8676 token from the operand string. */
8678 intel_match_token (int code)
8680 if (cur_token.code == code)
8687 as_bad (_("Unexpected token `%s'"), cur_token.str);
8692 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8694 intel_get_token (void)
8697 const reg_entry *reg;
8698 struct intel_token new_token;
8700 new_token.code = T_NIL;
8701 new_token.reg = NULL;
8702 new_token.str = NULL;
8704 /* Free the memory allocated to the previous token and move
8705 cur_token to prev_token. */
8707 free (prev_token.str);
8709 prev_token = cur_token;
8711 /* Skip whitespace. */
8712 while (is_space_char (*intel_parser.op_string))
8713 intel_parser.op_string++;
8715 /* Return an empty token if we find nothing else on the line. */
8716 if (*intel_parser.op_string == '\0')
8718 cur_token = new_token;
8722 /* The new token cannot be larger than the remainder of the operand
8724 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8725 new_token.str[0] = '\0';
8727 if (strchr ("0123456789", *intel_parser.op_string))
8729 char *p = new_token.str;
8730 char *q = intel_parser.op_string;
8731 new_token.code = T_CONST;
8733 /* Allow any kind of identifier char to encompass floating point and
8734 hexadecimal numbers. */
8735 while (is_identifier_char (*q))
8739 /* Recognize special symbol names [0-9][bf]. */
8740 if (strlen (intel_parser.op_string) == 2
8741 && (intel_parser.op_string[1] == 'b'
8742 || intel_parser.op_string[1] == 'f'))
8743 new_token.code = T_ID;
8746 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8748 size_t len = end_op - intel_parser.op_string;
8750 new_token.code = T_REG;
8751 new_token.reg = reg;
8753 memcpy (new_token.str, intel_parser.op_string, len);
8754 new_token.str[len] = '\0';
8757 else if (is_identifier_char (*intel_parser.op_string))
8759 char *p = new_token.str;
8760 char *q = intel_parser.op_string;
8762 /* A '.' or '$' followed by an identifier char is an identifier.
8763 Otherwise, it's operator '.' followed by an expression. */
8764 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8766 new_token.code = '.';
8767 new_token.str[0] = '.';
8768 new_token.str[1] = '\0';
8772 while (is_identifier_char (*q) || *q == '@')
8776 if (strcasecmp (new_token.str, "NOT") == 0)
8777 new_token.code = '~';
8779 else if (strcasecmp (new_token.str, "MOD") == 0)
8780 new_token.code = '%';
8782 else if (strcasecmp (new_token.str, "AND") == 0)
8783 new_token.code = '&';
8785 else if (strcasecmp (new_token.str, "OR") == 0)
8786 new_token.code = '|';
8788 else if (strcasecmp (new_token.str, "XOR") == 0)
8789 new_token.code = '^';
8791 else if (strcasecmp (new_token.str, "SHL") == 0)
8792 new_token.code = T_SHL;
8794 else if (strcasecmp (new_token.str, "SHR") == 0)
8795 new_token.code = T_SHR;
8797 else if (strcasecmp (new_token.str, "BYTE") == 0)
8798 new_token.code = T_BYTE;
8800 else if (strcasecmp (new_token.str, "WORD") == 0)
8801 new_token.code = T_WORD;
8803 else if (strcasecmp (new_token.str, "DWORD") == 0)
8804 new_token.code = T_DWORD;
8806 else if (strcasecmp (new_token.str, "FWORD") == 0)
8807 new_token.code = T_FWORD;
8809 else if (strcasecmp (new_token.str, "QWORD") == 0)
8810 new_token.code = T_QWORD;
8812 else if (strcasecmp (new_token.str, "TBYTE") == 0
8813 /* XXX remove (gcc still uses it) */
8814 || strcasecmp (new_token.str, "XWORD") == 0)
8815 new_token.code = T_TBYTE;
8817 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8818 || strcasecmp (new_token.str, "OWORD") == 0)
8819 new_token.code = T_XMMWORD;
8821 else if (strcasecmp (new_token.str, "PTR") == 0)
8822 new_token.code = T_PTR;
8824 else if (strcasecmp (new_token.str, "SHORT") == 0)
8825 new_token.code = T_SHORT;
8827 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8829 new_token.code = T_OFFSET;
8831 /* ??? This is not mentioned in the MASM grammar but gcc
8832 makes use of it with -mintel-syntax. OFFSET may be
8833 followed by FLAT: */
8834 if (strncasecmp (q, " FLAT:", 6) == 0)
8835 strcat (new_token.str, " FLAT:");
8838 /* ??? This is not mentioned in the MASM grammar. */
8839 else if (strcasecmp (new_token.str, "FLAT") == 0)
8841 new_token.code = T_OFFSET;
8843 strcat (new_token.str, ":");
8845 as_bad (_("`:' expected"));
8849 new_token.code = T_ID;
8853 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8855 new_token.code = *intel_parser.op_string;
8856 new_token.str[0] = *intel_parser.op_string;
8857 new_token.str[1] = '\0';
8860 else if (strchr ("<>", *intel_parser.op_string)
8861 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8863 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8864 new_token.str[0] = *intel_parser.op_string;
8865 new_token.str[1] = *intel_parser.op_string;
8866 new_token.str[2] = '\0';
8870 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8872 intel_parser.op_string += strlen (new_token.str);
8873 cur_token = new_token;
8876 /* Put cur_token back into the token stream and make cur_token point to
8879 intel_putback_token (void)
8881 if (cur_token.code != T_NIL)
8883 intel_parser.op_string -= strlen (cur_token.str);
8884 free (cur_token.str);
8886 cur_token = prev_token;
8888 /* Forget prev_token. */
8889 prev_token.code = T_NIL;
8890 prev_token.reg = NULL;
8891 prev_token.str = NULL;
8895 tc_x86_regname_to_dw2regnum (char *regname)
8897 unsigned int regnum;
8898 unsigned int regnames_count;
8899 static const char *const regnames_32[] =
8901 "eax", "ecx", "edx", "ebx",
8902 "esp", "ebp", "esi", "edi",
8903 "eip", "eflags", NULL,
8904 "st0", "st1", "st2", "st3",
8905 "st4", "st5", "st6", "st7",
8907 "xmm0", "xmm1", "xmm2", "xmm3",
8908 "xmm4", "xmm5", "xmm6", "xmm7",
8909 "mm0", "mm1", "mm2", "mm3",
8910 "mm4", "mm5", "mm6", "mm7",
8911 "fcw", "fsw", "mxcsr",
8912 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8915 static const char *const regnames_64[] =
8917 "rax", "rdx", "rcx", "rbx",
8918 "rsi", "rdi", "rbp", "rsp",
8919 "r8", "r9", "r10", "r11",
8920 "r12", "r13", "r14", "r15",
8922 "xmm0", "xmm1", "xmm2", "xmm3",
8923 "xmm4", "xmm5", "xmm6", "xmm7",
8924 "xmm8", "xmm9", "xmm10", "xmm11",
8925 "xmm12", "xmm13", "xmm14", "xmm15",
8926 "st0", "st1", "st2", "st3",
8927 "st4", "st5", "st6", "st7",
8928 "mm0", "mm1", "mm2", "mm3",
8929 "mm4", "mm5", "mm6", "mm7",
8931 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8932 "fs.base", "gs.base", NULL, NULL,
8934 "mxcsr", "fcw", "fsw"
8936 const char *const *regnames;
8938 if (flag_code == CODE_64BIT)
8940 regnames = regnames_64;
8941 regnames_count = ARRAY_SIZE (regnames_64);
8945 regnames = regnames_32;
8946 regnames_count = ARRAY_SIZE (regnames_32);
8949 for (regnum = 0; regnum < regnames_count; regnum++)
8950 if (regnames[regnum] != NULL
8951 && strcmp (regname, regnames[regnum]) == 0)
8958 tc_x86_frame_initial_instructions (void)
8960 static unsigned int sp_regno;
8963 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8966 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8967 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8971 i386_elf_section_type (const char *str, size_t len)
8973 if (flag_code == CODE_64BIT
8974 && len == sizeof ("unwind") - 1
8975 && strncmp (str, "unwind", 6) == 0)
8976 return SHT_X86_64_UNWIND;
8983 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8987 expr.X_op = O_secrel;
8988 expr.X_add_symbol = symbol;
8989 expr.X_add_number = 0;
8990 emit_expr (&expr, size);
8994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8995 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8998 x86_64_section_letter (int letter, char **ptr_msg)
9000 if (flag_code == CODE_64BIT)
9003 return SHF_X86_64_LARGE;
9005 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9008 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9013 x86_64_section_word (char *str, size_t len)
9015 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9016 return SHF_X86_64_LARGE;
9022 handle_large_common (int small ATTRIBUTE_UNUSED)
9024 if (flag_code != CODE_64BIT)
9026 s_comm_internal (0, elf_common_parse);
9027 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9031 static segT lbss_section;
9032 asection *saved_com_section_ptr = elf_com_section_ptr;
9033 asection *saved_bss_section = bss_section;
9035 if (lbss_section == NULL)
9037 flagword applicable;
9039 subsegT subseg = now_subseg;
9041 /* The .lbss section is for local .largecomm symbols. */
9042 lbss_section = subseg_new (".lbss", 0);
9043 applicable = bfd_applicable_section_flags (stdoutput);
9044 bfd_set_section_flags (stdoutput, lbss_section,
9045 applicable & SEC_ALLOC);
9046 seg_info (lbss_section)->bss = 1;
9048 subseg_set (seg, subseg);
9051 elf_com_section_ptr = &_bfd_elf_large_com_section;
9052 bss_section = lbss_section;
9054 s_comm_internal (0, elf_common_parse);
9056 elf_com_section_ptr = saved_com_section_ptr;
9057 bss_section = saved_bss_section;
9060 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */