1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c);
69 static int i386_att_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry *parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry *build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS *, offsetT);
91 static void output_disp (fragS *, offsetT);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED);
99 static const char *default_arch = DEFAULT_ARCH;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry *regs;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types[MAX_OPERANDS];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op[MAX_OPERANDS];
136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry *seg[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars = "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars = "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "#/";
210 const char line_separator_chars[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars[256];
223 static char register_chars[256];
224 static char operand_chars[256];
225 static char identifier_chars[256];
226 static char digit_chars[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack[32];
244 static char *save_stack_p;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates *current_templates;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
260 /* Current operand we are working on. */
261 static int this_operand;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code;
272 static unsigned int object_64bit;
273 static int use_rela_relocations = 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names[] =
283 /* 1 for intel syntax,
285 static int intel_syntax = 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic = !SYSV386_COMPAT;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc = OLDGCC_COMPAT;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg = 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix = "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code = 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings = 0;
315 static const char *cpu_arch_name = NULL;
316 static const char *cpu_sub_arch_name = NULL;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragS *fragP, int count)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1[] =
576 static const char f32_2[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
639 static const char alt_3[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code == CODE_16BIT)
769 memcpy (fragP->fr_literal + fragP->fr_fix,
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
780 const char *const *patt = NULL;
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags.bitfield.cpui686)
791 patt = alt_long_patt;
795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
804 case PROCESSOR_ATHLON:
806 case PROCESSOR_AMDFAM10:
807 patt = alt_short_patt;
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
819 switch (cpu_arch_tune)
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM:
831 case PROCESSOR_ATHLON:
833 case PROCESSOR_AMDFAM10:
834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags.bitfield.cpui686)
838 patt = alt_short_patt;
842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE2:
847 if (cpu_arch_isa_flags.bitfield.cpui686)
848 patt = alt_long_patt;
852 case PROCESSOR_GENERIC64:
853 patt = alt_long_patt;
858 if (patt == f32_patt)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
868 memcpy (fragP->fr_literal + fragP->fr_fix,
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
892 fragP->fr_var = count;
896 uints_all_zero (const unsigned int *x, unsigned int size)
914 uints_set (unsigned int *x, unsigned int v, unsigned int size)
931 uints_equal (const unsigned int *x, const unsigned int *y,
943 return x[0] == y [0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f)
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
969 switch (ARRAY_SIZE (x.array))
972 x.array [2] &= y.array [2];
974 x.array [1] &= y.array [1];
976 x.array [0] &= y.array [0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
987 switch (ARRAY_SIZE (x.array))
990 x.array [2] |= y.array [2];
992 x.array [1] |= y.array [1];
994 x.array [0] |= y.array [0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x)
1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1013 if (UINTS_ALL_ZERO (x))
1017 i386_cpu_flags cpu = cpu_arch_flags;
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x, i386_operand_type y)
1030 switch (ARRAY_SIZE (x.array))
1033 x.array [2] &= y.array [2];
1035 x.array [1] &= y.array [1];
1037 x.array [0] &= y.array [0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x, i386_operand_type y)
1048 switch (ARRAY_SIZE (x.array))
1051 x.array [2] |= y.array [2];
1053 x.array [1] |= y.array [1];
1055 x.array [0] |= y.array [0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x, i386_operand_type y)
1066 switch (ARRAY_SIZE (x.array))
1069 x.array [2] ^= y.array [2];
1071 x.array [1] ^= y.array [1];
1073 x.array [0] ^= y.array [0];
1081 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
1092 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1112 operand_type_check (i386_operand_type t, enum operand_type c)
1117 return (t.bitfield.reg8
1120 || t.bitfield.reg64);
1123 return (t.bitfield.imm8
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1150 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1151 operand J for instruction template T. */
1154 match_reg_size (const template *t, unsigned int j)
1156 return !((i.types[j].bitfield.byte
1157 && !t->operand_types[j].bitfield.byte)
1158 || (i.types[j].bitfield.word
1159 && !t->operand_types[j].bitfield.word)
1160 || (i.types[j].bitfield.dword
1161 && !t->operand_types[j].bitfield.dword)
1162 || (i.types[j].bitfield.qword
1163 && !t->operand_types[j].bitfield.qword));
1166 /* Return 1 if there is no conflict in any size on operand J for
1167 instruction template T. */
1170 match_mem_size (const template *t, unsigned int j)
1172 return (match_reg_size (t, j)
1173 && !((i.types[j].bitfield.unspecified
1174 && !t->operand_types[j].bitfield.unspecified)
1175 || (i.types[j].bitfield.fword
1176 && !t->operand_types[j].bitfield.fword)
1177 || (i.types[j].bitfield.tbyte
1178 && !t->operand_types[j].bitfield.tbyte)
1179 || (i.types[j].bitfield.xmmword
1180 && !t->operand_types[j].bitfield.xmmword)));
1183 /* Return 1 if there is no size conflict on any operands for
1184 instruction template T. */
1187 operand_size_match (const template *t)
1192 /* Don't check jump instructions. */
1193 if (t->opcode_modifier.jump
1194 || t->opcode_modifier.jumpbyte
1195 || t->opcode_modifier.jumpdword
1196 || t->opcode_modifier.jumpintersegment)
1199 /* Check memory and accumulator operand size. */
1200 for (j = 0; j < i.operands; j++)
1202 if (t->operand_types[j].bitfield.anysize)
1205 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1211 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1219 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1222 /* Check reverse. */
1223 assert (i.operands == 2);
1226 for (j = 0; j < 2; j++)
1228 if (t->operand_types[j].bitfield.acc
1229 && !match_reg_size (t, j ? 0 : 1))
1235 if (i.types[j].bitfield.mem
1236 && !match_mem_size (t, j ? 0 : 1))
1247 operand_type_match (i386_operand_type overlap,
1248 i386_operand_type given)
1250 i386_operand_type temp = overlap;
1252 temp.bitfield.jumpabsolute = 0;
1253 temp.bitfield.unspecified = 0;
1254 temp.bitfield.byte = 0;
1255 temp.bitfield.word = 0;
1256 temp.bitfield.dword = 0;
1257 temp.bitfield.fword = 0;
1258 temp.bitfield.qword = 0;
1259 temp.bitfield.tbyte = 0;
1260 temp.bitfield.xmmword = 0;
1261 if (UINTS_ALL_ZERO (temp))
1264 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1265 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1268 /* If given types g0 and g1 are registers they must be of the same type
1269 unless the expected operand type register overlap is null.
1270 Note that Acc in a template matches every size of reg. */
1273 operand_type_register_match (i386_operand_type m0,
1274 i386_operand_type g0,
1275 i386_operand_type t0,
1276 i386_operand_type m1,
1277 i386_operand_type g1,
1278 i386_operand_type t1)
1280 if (!operand_type_check (g0, reg))
1283 if (!operand_type_check (g1, reg))
1286 if (g0.bitfield.reg8 == g1.bitfield.reg8
1287 && g0.bitfield.reg16 == g1.bitfield.reg16
1288 && g0.bitfield.reg32 == g1.bitfield.reg32
1289 && g0.bitfield.reg64 == g1.bitfield.reg64)
1292 if (m0.bitfield.acc)
1294 t0.bitfield.reg8 = 1;
1295 t0.bitfield.reg16 = 1;
1296 t0.bitfield.reg32 = 1;
1297 t0.bitfield.reg64 = 1;
1300 if (m1.bitfield.acc)
1302 t1.bitfield.reg8 = 1;
1303 t1.bitfield.reg16 = 1;
1304 t1.bitfield.reg32 = 1;
1305 t1.bitfield.reg64 = 1;
1308 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1309 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1310 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1311 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1314 static INLINE unsigned int
1315 mode_from_disp_size (i386_operand_type t)
1317 if (t.bitfield.disp8)
1319 else if (t.bitfield.disp16
1320 || t.bitfield.disp32
1321 || t.bitfield.disp32s)
1328 fits_in_signed_byte (offsetT num)
1330 return (num >= -128) && (num <= 127);
1334 fits_in_unsigned_byte (offsetT num)
1336 return (num & 0xff) == num;
1340 fits_in_unsigned_word (offsetT num)
1342 return (num & 0xffff) == num;
1346 fits_in_signed_word (offsetT num)
1348 return (-32768 <= num) && (num <= 32767);
1352 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1357 return (!(((offsetT) -1 << 31) & num)
1358 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1360 } /* fits_in_signed_long() */
1363 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1368 return (num & (((offsetT) 2 << 31) - 1)) == num;
1370 } /* fits_in_unsigned_long() */
1372 static i386_operand_type
1373 smallest_imm_type (offsetT num)
1375 i386_operand_type t;
1378 t.bitfield.imm64 = 1;
1380 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1382 /* This code is disabled on the 486 because all the Imm1 forms
1383 in the opcode table are slower on the i486. They're the
1384 versions with the implicitly specified single-position
1385 displacement, which has another syntax if you really want to
1387 t.bitfield.imm1 = 1;
1388 t.bitfield.imm8 = 1;
1389 t.bitfield.imm8s = 1;
1390 t.bitfield.imm16 = 1;
1391 t.bitfield.imm32 = 1;
1392 t.bitfield.imm32s = 1;
1394 else if (fits_in_signed_byte (num))
1396 t.bitfield.imm8 = 1;
1397 t.bitfield.imm8s = 1;
1398 t.bitfield.imm16 = 1;
1399 t.bitfield.imm32 = 1;
1400 t.bitfield.imm32s = 1;
1402 else if (fits_in_unsigned_byte (num))
1404 t.bitfield.imm8 = 1;
1405 t.bitfield.imm16 = 1;
1406 t.bitfield.imm32 = 1;
1407 t.bitfield.imm32s = 1;
1409 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1411 t.bitfield.imm16 = 1;
1412 t.bitfield.imm32 = 1;
1413 t.bitfield.imm32s = 1;
1415 else if (fits_in_signed_long (num))
1417 t.bitfield.imm32 = 1;
1418 t.bitfield.imm32s = 1;
1420 else if (fits_in_unsigned_long (num))
1421 t.bitfield.imm32 = 1;
1427 offset_in_range (offsetT val, int size)
1433 case 1: mask = ((addressT) 1 << 8) - 1; break;
1434 case 2: mask = ((addressT) 1 << 16) - 1; break;
1435 case 4: mask = ((addressT) 2 << 31) - 1; break;
1437 case 8: mask = ((addressT) 2 << 63) - 1; break;
1442 /* If BFD64, sign extend val. */
1443 if (!use_rela_relocations)
1444 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1445 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1447 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1449 char buf1[40], buf2[40];
1451 sprint_value (buf1, val);
1452 sprint_value (buf2, val & mask);
1453 as_warn (_("%s shortened to %s"), buf1, buf2);
1458 /* Returns 0 if attempting to add a prefix where one from the same
1459 class already exists, 1 if non rep/repne added, 2 if rep/repne
1462 add_prefix (unsigned int prefix)
1467 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1468 && flag_code == CODE_64BIT)
1470 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1471 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1472 && (prefix & (REX_R | REX_X | REX_B))))
1483 case CS_PREFIX_OPCODE:
1484 case DS_PREFIX_OPCODE:
1485 case ES_PREFIX_OPCODE:
1486 case FS_PREFIX_OPCODE:
1487 case GS_PREFIX_OPCODE:
1488 case SS_PREFIX_OPCODE:
1492 case REPNE_PREFIX_OPCODE:
1493 case REPE_PREFIX_OPCODE:
1496 case LOCK_PREFIX_OPCODE:
1504 case ADDR_PREFIX_OPCODE:
1508 case DATA_PREFIX_OPCODE:
1512 if (i.prefix[q] != 0)
1520 i.prefix[q] |= prefix;
1523 as_bad (_("same type of prefix used twice"));
1529 set_code_flag (int value)
1532 if (flag_code == CODE_64BIT)
1534 cpu_arch_flags.bitfield.cpu64 = 1;
1535 cpu_arch_flags.bitfield.cpuno64 = 0;
1539 cpu_arch_flags.bitfield.cpu64 = 0;
1540 cpu_arch_flags.bitfield.cpuno64 = 1;
1542 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1544 as_bad (_("64bit mode not supported on this CPU."));
1546 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1548 as_bad (_("32bit mode not supported on this CPU."));
1550 stackop_size = '\0';
1554 set_16bit_gcc_code_flag (int new_code_flag)
1556 flag_code = new_code_flag;
1557 if (flag_code != CODE_16BIT)
1559 cpu_arch_flags.bitfield.cpu64 = 0;
1560 cpu_arch_flags.bitfield.cpuno64 = 1;
1561 stackop_size = LONG_MNEM_SUFFIX;
1565 set_intel_syntax (int syntax_flag)
1567 /* Find out if register prefixing is specified. */
1568 int ask_naked_reg = 0;
1571 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1573 char *string = input_line_pointer;
1574 int e = get_symbol_end ();
1576 if (strcmp (string, "prefix") == 0)
1578 else if (strcmp (string, "noprefix") == 0)
1581 as_bad (_("bad argument to syntax directive."));
1582 *input_line_pointer = e;
1584 demand_empty_rest_of_line ();
1586 intel_syntax = syntax_flag;
1588 if (ask_naked_reg == 0)
1589 allow_naked_reg = (intel_syntax
1590 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1592 allow_naked_reg = (ask_naked_reg < 0);
1594 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1595 identifier_chars['$'] = intel_syntax ? '$' : 0;
1596 register_prefix = allow_naked_reg ? "" : "%";
1600 set_intel_mnemonic (int mnemonic_flag)
1602 intel_mnemonic = mnemonic_flag;
1606 set_allow_index_reg (int flag)
1608 allow_index_reg = flag;
1612 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1616 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1618 char *string = input_line_pointer;
1619 int e = get_symbol_end ();
1621 i386_cpu_flags flags;
1623 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1625 if (strcmp (string, cpu_arch[i].name) == 0)
1629 cpu_arch_name = cpu_arch[i].name;
1630 cpu_sub_arch_name = NULL;
1631 cpu_arch_flags = cpu_arch[i].flags;
1632 if (flag_code == CODE_64BIT)
1634 cpu_arch_flags.bitfield.cpu64 = 1;
1635 cpu_arch_flags.bitfield.cpuno64 = 0;
1639 cpu_arch_flags.bitfield.cpu64 = 0;
1640 cpu_arch_flags.bitfield.cpuno64 = 1;
1642 cpu_arch_isa = cpu_arch[i].type;
1643 cpu_arch_isa_flags = cpu_arch[i].flags;
1644 if (!cpu_arch_tune_set)
1646 cpu_arch_tune = cpu_arch_isa;
1647 cpu_arch_tune_flags = cpu_arch_isa_flags;
1652 flags = cpu_flags_or (cpu_arch_flags,
1654 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1656 cpu_sub_arch_name = cpu_arch[i].name;
1657 cpu_arch_flags = flags;
1659 *input_line_pointer = e;
1660 demand_empty_rest_of_line ();
1664 if (i >= ARRAY_SIZE (cpu_arch))
1665 as_bad (_("no such architecture: `%s'"), string);
1667 *input_line_pointer = e;
1670 as_bad (_("missing cpu architecture"));
1672 no_cond_jump_promotion = 0;
1673 if (*input_line_pointer == ','
1674 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1676 char *string = ++input_line_pointer;
1677 int e = get_symbol_end ();
1679 if (strcmp (string, "nojumps") == 0)
1680 no_cond_jump_promotion = 1;
1681 else if (strcmp (string, "jumps") == 0)
1684 as_bad (_("no such architecture modifier: `%s'"), string);
1686 *input_line_pointer = e;
1689 demand_empty_rest_of_line ();
1695 if (!strcmp (default_arch, "x86_64"))
1696 return bfd_mach_x86_64;
1697 else if (!strcmp (default_arch, "i386"))
1698 return bfd_mach_i386_i386;
1700 as_fatal (_("Unknown architecture"));
1706 const char *hash_err;
1708 /* Initialize op_hash hash table. */
1709 op_hash = hash_new ();
1712 const template *optab;
1713 templates *core_optab;
1715 /* Setup for loop. */
1717 core_optab = (templates *) xmalloc (sizeof (templates));
1718 core_optab->start = optab;
1723 if (optab->name == NULL
1724 || strcmp (optab->name, (optab - 1)->name) != 0)
1726 /* different name --> ship out current template list;
1727 add to hash table; & begin anew. */
1728 core_optab->end = optab;
1729 hash_err = hash_insert (op_hash,
1734 as_fatal (_("Internal Error: Can't hash %s: %s"),
1738 if (optab->name == NULL)
1740 core_optab = (templates *) xmalloc (sizeof (templates));
1741 core_optab->start = optab;
1746 /* Initialize reg_hash hash table. */
1747 reg_hash = hash_new ();
1749 const reg_entry *regtab;
1750 unsigned int regtab_size = i386_regtab_size;
1752 for (regtab = i386_regtab; regtab_size--; regtab++)
1754 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1756 as_fatal (_("Internal Error: Can't hash %s: %s"),
1762 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1767 for (c = 0; c < 256; c++)
1772 mnemonic_chars[c] = c;
1773 register_chars[c] = c;
1774 operand_chars[c] = c;
1776 else if (ISLOWER (c))
1778 mnemonic_chars[c] = c;
1779 register_chars[c] = c;
1780 operand_chars[c] = c;
1782 else if (ISUPPER (c))
1784 mnemonic_chars[c] = TOLOWER (c);
1785 register_chars[c] = mnemonic_chars[c];
1786 operand_chars[c] = c;
1789 if (ISALPHA (c) || ISDIGIT (c))
1790 identifier_chars[c] = c;
1793 identifier_chars[c] = c;
1794 operand_chars[c] = c;
1799 identifier_chars['@'] = '@';
1802 identifier_chars['?'] = '?';
1803 operand_chars['?'] = '?';
1805 digit_chars['-'] = '-';
1806 mnemonic_chars['-'] = '-';
1807 mnemonic_chars['.'] = '.';
1808 identifier_chars['_'] = '_';
1809 identifier_chars['.'] = '.';
1811 for (p = operand_special_chars; *p != '\0'; p++)
1812 operand_chars[(unsigned char) *p] = *p;
1815 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1818 record_alignment (text_section, 2);
1819 record_alignment (data_section, 2);
1820 record_alignment (bss_section, 2);
1824 if (flag_code == CODE_64BIT)
1826 x86_dwarf2_return_column = 16;
1827 x86_cie_data_alignment = -8;
1831 x86_dwarf2_return_column = 8;
1832 x86_cie_data_alignment = -4;
1837 i386_print_statistics (FILE *file)
1839 hash_print_statistics (file, "i386 opcode", op_hash);
1840 hash_print_statistics (file, "i386 register", reg_hash);
1845 /* Debugging routines for md_assemble. */
1846 static void pte (template *);
1847 static void pt (i386_operand_type);
1848 static void pe (expressionS *);
1849 static void ps (symbolS *);
1852 pi (char *line, i386_insn *x)
1856 fprintf (stdout, "%s: template ", line);
1858 fprintf (stdout, " address: base %s index %s scale %x\n",
1859 x->base_reg ? x->base_reg->reg_name : "none",
1860 x->index_reg ? x->index_reg->reg_name : "none",
1861 x->log2_scale_factor);
1862 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1863 x->rm.mode, x->rm.reg, x->rm.regmem);
1864 fprintf (stdout, " sib: base %x index %x scale %x\n",
1865 x->sib.base, x->sib.index, x->sib.scale);
1866 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1867 (x->rex & REX_W) != 0,
1868 (x->rex & REX_R) != 0,
1869 (x->rex & REX_X) != 0,
1870 (x->rex & REX_B) != 0);
1871 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1872 x->drex.reg, x->drex.rex);
1873 for (i = 0; i < x->operands; i++)
1875 fprintf (stdout, " #%d: ", i + 1);
1877 fprintf (stdout, "\n");
1878 if (x->types[i].bitfield.reg8
1879 || x->types[i].bitfield.reg16
1880 || x->types[i].bitfield.reg32
1881 || x->types[i].bitfield.reg64
1882 || x->types[i].bitfield.regmmx
1883 || x->types[i].bitfield.regxmm
1884 || x->types[i].bitfield.sreg2
1885 || x->types[i].bitfield.sreg3
1886 || x->types[i].bitfield.control
1887 || x->types[i].bitfield.debug
1888 || x->types[i].bitfield.test)
1889 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1890 if (operand_type_check (x->types[i], imm))
1892 if (operand_type_check (x->types[i], disp))
1893 pe (x->op[i].disps);
1901 fprintf (stdout, " %d operands ", t->operands);
1902 fprintf (stdout, "opcode %x ", t->base_opcode);
1903 if (t->extension_opcode != None)
1904 fprintf (stdout, "ext %x ", t->extension_opcode);
1905 if (t->opcode_modifier.d)
1906 fprintf (stdout, "D");
1907 if (t->opcode_modifier.w)
1908 fprintf (stdout, "W");
1909 fprintf (stdout, "\n");
1910 for (i = 0; i < t->operands; i++)
1912 fprintf (stdout, " #%d type ", i + 1);
1913 pt (t->operand_types[i]);
1914 fprintf (stdout, "\n");
1921 fprintf (stdout, " operation %d\n", e->X_op);
1922 fprintf (stdout, " add_number %ld (%lx)\n",
1923 (long) e->X_add_number, (long) e->X_add_number);
1924 if (e->X_add_symbol)
1926 fprintf (stdout, " add_symbol ");
1927 ps (e->X_add_symbol);
1928 fprintf (stdout, "\n");
1932 fprintf (stdout, " op_symbol ");
1933 ps (e->X_op_symbol);
1934 fprintf (stdout, "\n");
1941 fprintf (stdout, "%s type %s%s",
1943 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1944 segment_name (S_GET_SEGMENT (s)));
1947 static struct type_name
1949 i386_operand_type mask;
1952 const type_names[] =
1954 { OPERAND_TYPE_REG8, "r8" },
1955 { OPERAND_TYPE_REG16, "r16" },
1956 { OPERAND_TYPE_REG32, "r32" },
1957 { OPERAND_TYPE_REG64, "r64" },
1958 { OPERAND_TYPE_IMM8, "i8" },
1959 { OPERAND_TYPE_IMM8, "i8s" },
1960 { OPERAND_TYPE_IMM16, "i16" },
1961 { OPERAND_TYPE_IMM32, "i32" },
1962 { OPERAND_TYPE_IMM32S, "i32s" },
1963 { OPERAND_TYPE_IMM64, "i64" },
1964 { OPERAND_TYPE_IMM1, "i1" },
1965 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1966 { OPERAND_TYPE_DISP8, "d8" },
1967 { OPERAND_TYPE_DISP16, "d16" },
1968 { OPERAND_TYPE_DISP32, "d32" },
1969 { OPERAND_TYPE_DISP32S, "d32s" },
1970 { OPERAND_TYPE_DISP64, "d64" },
1971 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1972 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1973 { OPERAND_TYPE_CONTROL, "control reg" },
1974 { OPERAND_TYPE_TEST, "test reg" },
1975 { OPERAND_TYPE_DEBUG, "debug reg" },
1976 { OPERAND_TYPE_FLOATREG, "FReg" },
1977 { OPERAND_TYPE_FLOATACC, "FAcc" },
1978 { OPERAND_TYPE_SREG2, "SReg2" },
1979 { OPERAND_TYPE_SREG3, "SReg3" },
1980 { OPERAND_TYPE_ACC, "Acc" },
1981 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1982 { OPERAND_TYPE_REGMMX, "rMMX" },
1983 { OPERAND_TYPE_REGXMM, "rXMM" },
1984 { OPERAND_TYPE_ESSEG, "es" },
1988 pt (i386_operand_type t)
1991 i386_operand_type a;
1993 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1995 a = operand_type_and (t, type_names[j].mask);
1996 if (!UINTS_ALL_ZERO (a))
1997 fprintf (stdout, "%s, ", type_names[j].name);
2002 #endif /* DEBUG386 */
2004 static bfd_reloc_code_real_type
2005 reloc (unsigned int size,
2008 bfd_reloc_code_real_type other)
2010 if (other != NO_RELOC)
2012 reloc_howto_type *reloc;
2017 case BFD_RELOC_X86_64_GOT32:
2018 return BFD_RELOC_X86_64_GOT64;
2020 case BFD_RELOC_X86_64_PLTOFF64:
2021 return BFD_RELOC_X86_64_PLTOFF64;
2023 case BFD_RELOC_X86_64_GOTPC32:
2024 other = BFD_RELOC_X86_64_GOTPC64;
2026 case BFD_RELOC_X86_64_GOTPCREL:
2027 other = BFD_RELOC_X86_64_GOTPCREL64;
2029 case BFD_RELOC_X86_64_TPOFF32:
2030 other = BFD_RELOC_X86_64_TPOFF64;
2032 case BFD_RELOC_X86_64_DTPOFF32:
2033 other = BFD_RELOC_X86_64_DTPOFF64;
2039 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2040 if (size == 4 && flag_code != CODE_64BIT)
2043 reloc = bfd_reloc_type_lookup (stdoutput, other);
2045 as_bad (_("unknown relocation (%u)"), other);
2046 else if (size != bfd_get_reloc_size (reloc))
2047 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2048 bfd_get_reloc_size (reloc),
2050 else if (pcrel && !reloc->pc_relative)
2051 as_bad (_("non-pc-relative relocation for pc-relative field"));
2052 else if ((reloc->complain_on_overflow == complain_overflow_signed
2054 || (reloc->complain_on_overflow == complain_overflow_unsigned
2056 as_bad (_("relocated field and relocation type differ in signedness"));
2065 as_bad (_("there are no unsigned pc-relative relocations"));
2068 case 1: return BFD_RELOC_8_PCREL;
2069 case 2: return BFD_RELOC_16_PCREL;
2070 case 4: return BFD_RELOC_32_PCREL;
2071 case 8: return BFD_RELOC_64_PCREL;
2073 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2080 case 4: return BFD_RELOC_X86_64_32S;
2085 case 1: return BFD_RELOC_8;
2086 case 2: return BFD_RELOC_16;
2087 case 4: return BFD_RELOC_32;
2088 case 8: return BFD_RELOC_64;
2090 as_bad (_("cannot do %s %u byte relocation"),
2091 sign > 0 ? "signed" : "unsigned", size);
2095 return BFD_RELOC_NONE;
2098 /* Here we decide which fixups can be adjusted to make them relative to
2099 the beginning of the section instead of the symbol. Basically we need
2100 to make sure that the dynamic relocations are done correctly, so in
2101 some cases we force the original symbol to be used. */
2104 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2110 /* Don't adjust pc-relative references to merge sections in 64-bit
2112 if (use_rela_relocations
2113 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2117 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2118 and changed later by validate_fix. */
2119 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2120 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2123 /* adjust_reloc_syms doesn't know about the GOT. */
2124 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2125 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2126 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2127 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2128 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2129 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2130 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2131 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2132 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2133 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2134 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2135 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2136 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2137 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2138 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2140 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2141 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2142 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2143 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2144 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2145 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2146 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2148 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2149 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2150 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2151 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2158 intel_float_operand (const char *mnemonic)
2160 /* Note that the value returned is meaningful only for opcodes with (memory)
2161 operands, hence the code here is free to improperly handle opcodes that
2162 have no operands (for better performance and smaller code). */
2164 if (mnemonic[0] != 'f')
2165 return 0; /* non-math */
2167 switch (mnemonic[1])
2169 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2170 the fs segment override prefix not currently handled because no
2171 call path can make opcodes without operands get here */
2173 return 2 /* integer op */;
2175 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2176 return 3; /* fldcw/fldenv */
2179 if (mnemonic[2] != 'o' /* fnop */)
2180 return 3; /* non-waiting control op */
2183 if (mnemonic[2] == 's')
2184 return 3; /* frstor/frstpm */
2187 if (mnemonic[2] == 'a')
2188 return 3; /* fsave */
2189 if (mnemonic[2] == 't')
2191 switch (mnemonic[3])
2193 case 'c': /* fstcw */
2194 case 'd': /* fstdw */
2195 case 'e': /* fstenv */
2196 case 's': /* fsts[gw] */
2202 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2203 return 0; /* fxsave/fxrstor are not really math ops */
2210 /* This is the guts of the machine-dependent assembler. LINE points to a
2211 machine dependent instruction. This function is supposed to emit
2212 the frags/bytes it assembles to. */
2219 char mnemonic[MAX_MNEM_SIZE];
2221 /* Initialize globals. */
2222 memset (&i, '\0', sizeof (i));
2223 for (j = 0; j < MAX_OPERANDS; j++)
2224 i.reloc[j] = NO_RELOC;
2225 memset (disp_expressions, '\0', sizeof (disp_expressions));
2226 memset (im_expressions, '\0', sizeof (im_expressions));
2227 save_stack_p = save_stack;
2229 /* First parse an instruction mnemonic & call i386_operand for the operands.
2230 We assume that the scrubber has arranged it so that line[0] is the valid
2231 start of a (possibly prefixed) mnemonic. */
2233 line = parse_insn (line, mnemonic);
2237 line = parse_operands (line, mnemonic);
2241 /* Now we've parsed the mnemonic into a set of templates, and have the
2242 operands at hand. */
2244 /* All intel opcodes have reversed operands except for "bound" and
2245 "enter". We also don't reverse intersegment "jmp" and "call"
2246 instructions with 2 immediate operands so that the immediate segment
2247 precedes the offset, as it does when in AT&T mode. */
2250 && (strcmp (mnemonic, "bound") != 0)
2251 && (strcmp (mnemonic, "invlpga") != 0)
2252 && !(operand_type_check (i.types[0], imm)
2253 && operand_type_check (i.types[1], imm)))
2256 /* The order of the immediates should be reversed
2257 for 2 immediates extrq and insertq instructions */
2258 if (i.imm_operands == 2
2259 && (strcmp (mnemonic, "extrq") == 0
2260 || strcmp (mnemonic, "insertq") == 0))
2261 swap_2_operands (0, 1);
2266 /* Don't optimize displacement for movabs since it only takes 64bit
2269 && (flag_code != CODE_64BIT
2270 || strcmp (mnemonic, "movabs") != 0))
2273 /* Next, we find a template that matches the given insn,
2274 making sure the overlap of the given operands types is consistent
2275 with the template operand types. */
2277 if (!match_template ())
2280 /* Zap movzx and movsx suffix. The suffix has been set from
2281 "word ptr" or "byte ptr" on the source operand in Intel syntax
2282 or extracted from mnemonic in AT&T syntax. But we'll use
2283 the destination register to choose the suffix for encoding. */
2284 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2286 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2287 there is no suffix, the default will be byte extension. */
2288 if (i.reg_operands != 2
2291 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2296 if (i.tm.opcode_modifier.fwait)
2297 if (!add_prefix (FWAIT_OPCODE))
2300 /* Check string instruction segment overrides. */
2301 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2303 if (!check_string ())
2307 if (!process_suffix ())
2310 /* Make still unresolved immediate matches conform to size of immediate
2311 given in i.suffix. */
2312 if (!finalize_imm ())
2315 if (i.types[0].bitfield.imm1)
2316 i.imm_operands = 0; /* kludge for shift insns. */
2318 for (j = 0; j < 3; j++)
2319 if (i.types[j].bitfield.inoutportreg
2320 || i.types[j].bitfield.shiftcount
2321 || i.types[j].bitfield.acc
2322 || i.types[j].bitfield.floatacc)
2325 if (i.tm.opcode_modifier.immext)
2329 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2331 /* Streaming SIMD extensions 3 Instructions have the fixed
2332 operands with an opcode suffix which is coded in the same
2333 place as an 8-bit immediate field would be. Here we check
2334 those operands and remove them afterwards. */
2337 for (x = 0; x < i.operands; x++)
2338 if (i.op[x].regs->reg_num != x)
2339 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2341 i.op[x].regs->reg_name,
2347 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2348 opcode suffix which is coded in the same place as an 8-bit
2349 immediate field would be. Here we fake an 8-bit immediate
2350 operand from the opcode suffix stored in tm.extension_opcode.
2351 SSE5 also uses this encoding, for some of its 3 argument
2354 assert (i.imm_operands == 0
2356 || (i.tm.cpu_flags.bitfield.cpusse5
2357 && i.operands <= 3)));
2359 exp = &im_expressions[i.imm_operands++];
2360 i.op[i.operands].imms = exp;
2361 UINTS_CLEAR (i.types[i.operands]);
2362 i.types[i.operands].bitfield.imm8 = 1;
2364 exp->X_op = O_constant;
2365 exp->X_add_number = i.tm.extension_opcode;
2366 i.tm.extension_opcode = None;
2369 /* For insns with operands there are more diddles to do to the opcode. */
2372 if (!process_operands ())
2375 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2377 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2378 as_warn (_("translating to `%sp'"), i.tm.name);
2381 /* Handle conversion of 'int $3' --> special int3 insn. */
2382 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2384 i.tm.base_opcode = INT3_OPCODE;
2388 if ((i.tm.opcode_modifier.jump
2389 || i.tm.opcode_modifier.jumpbyte
2390 || i.tm.opcode_modifier.jumpdword)
2391 && i.op[0].disps->X_op == O_constant)
2393 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2394 the absolute address given by the constant. Since ix86 jumps and
2395 calls are pc relative, we need to generate a reloc. */
2396 i.op[0].disps->X_add_symbol = &abs_symbol;
2397 i.op[0].disps->X_op = O_symbol;
2400 if (i.tm.opcode_modifier.rex64)
2403 /* For 8 bit registers we need an empty rex prefix. Also if the
2404 instruction already has a prefix, we need to convert old
2405 registers to new ones. */
2407 if ((i.types[0].bitfield.reg8
2408 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2409 || (i.types[1].bitfield.reg8
2410 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2411 || ((i.types[0].bitfield.reg8
2412 || i.types[1].bitfield.reg8)
2417 i.rex |= REX_OPCODE;
2418 for (x = 0; x < 2; x++)
2420 /* Look for 8 bit operand that uses old registers. */
2421 if (i.types[x].bitfield.reg8
2422 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2424 /* In case it is "hi" register, give up. */
2425 if (i.op[x].regs->reg_num > 3)
2426 as_bad (_("can't encode register '%s%s' in an "
2427 "instruction requiring REX prefix."),
2428 register_prefix, i.op[x].regs->reg_name);
2430 /* Otherwise it is equivalent to the extended register.
2431 Since the encoding doesn't change this is merely
2432 cosmetic cleanup for debug output. */
2434 i.op[x].regs = i.op[x].regs + 8;
2439 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2441 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2446 else if (i.rex != 0)
2447 add_prefix (REX_OPCODE | i.rex);
2449 /* We are ready to output the insn. */
2454 parse_insn (char *line, char *mnemonic)
2457 char *token_start = l;
2462 /* Non-zero if we found a prefix only acceptable with string insns. */
2463 const char *expecting_string_instruction = NULL;
2468 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2471 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2473 as_bad (_("no such instruction: `%s'"), token_start);
2478 if (!is_space_char (*l)
2479 && *l != END_OF_INSN
2481 || (*l != PREFIX_SEPARATOR
2484 as_bad (_("invalid character %s in mnemonic"),
2485 output_invalid (*l));
2488 if (token_start == l)
2490 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2491 as_bad (_("expecting prefix; got nothing"));
2493 as_bad (_("expecting mnemonic; got nothing"));
2497 /* Look up instruction (or prefix) via hash table. */
2498 current_templates = hash_find (op_hash, mnemonic);
2500 if (*l != END_OF_INSN
2501 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2502 && current_templates
2503 && current_templates->start->opcode_modifier.isprefix)
2505 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2507 as_bad ((flag_code != CODE_64BIT
2508 ? _("`%s' is only supported in 64-bit mode")
2509 : _("`%s' is not supported in 64-bit mode")),
2510 current_templates->start->name);
2513 /* If we are in 16-bit mode, do not allow addr16 or data16.
2514 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2515 if ((current_templates->start->opcode_modifier.size16
2516 || current_templates->start->opcode_modifier.size32)
2517 && flag_code != CODE_64BIT
2518 && (current_templates->start->opcode_modifier.size32
2519 ^ (flag_code == CODE_16BIT)))
2521 as_bad (_("redundant %s prefix"),
2522 current_templates->start->name);
2525 /* Add prefix, checking for repeated prefixes. */
2526 switch (add_prefix (current_templates->start->base_opcode))
2531 expecting_string_instruction = current_templates->start->name;
2534 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2541 if (!current_templates)
2543 /* See if we can get a match by trimming off a suffix. */
2546 case WORD_MNEM_SUFFIX:
2547 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2548 i.suffix = SHORT_MNEM_SUFFIX;
2550 case BYTE_MNEM_SUFFIX:
2551 case QWORD_MNEM_SUFFIX:
2552 i.suffix = mnem_p[-1];
2554 current_templates = hash_find (op_hash, mnemonic);
2556 case SHORT_MNEM_SUFFIX:
2557 case LONG_MNEM_SUFFIX:
2560 i.suffix = mnem_p[-1];
2562 current_templates = hash_find (op_hash, mnemonic);
2570 if (intel_float_operand (mnemonic) == 1)
2571 i.suffix = SHORT_MNEM_SUFFIX;
2573 i.suffix = LONG_MNEM_SUFFIX;
2575 current_templates = hash_find (op_hash, mnemonic);
2579 if (!current_templates)
2581 as_bad (_("no such instruction: `%s'"), token_start);
2586 if (current_templates->start->opcode_modifier.jump
2587 || current_templates->start->opcode_modifier.jumpbyte)
2589 /* Check for a branch hint. We allow ",pt" and ",pn" for
2590 predict taken and predict not taken respectively.
2591 I'm not sure that branch hints actually do anything on loop
2592 and jcxz insns (JumpByte) for current Pentium4 chips. They
2593 may work in the future and it doesn't hurt to accept them
2595 if (l[0] == ',' && l[1] == 'p')
2599 if (!add_prefix (DS_PREFIX_OPCODE))
2603 else if (l[2] == 'n')
2605 if (!add_prefix (CS_PREFIX_OPCODE))
2611 /* Any other comma loses. */
2614 as_bad (_("invalid character %s in mnemonic"),
2615 output_invalid (*l));
2619 /* Check if instruction is supported on specified architecture. */
2621 for (t = current_templates->start; t < current_templates->end; ++t)
2623 supported |= cpu_flags_match (t->cpu_flags);
2628 if (!(supported & 2))
2630 as_bad (flag_code == CODE_64BIT
2631 ? _("`%s' is not supported in 64-bit mode")
2632 : _("`%s' is only supported in 64-bit mode"),
2633 current_templates->start->name);
2636 if (!(supported & 1))
2638 as_bad (_("`%s' is not supported on `%s%s'"),
2639 current_templates->start->name, cpu_arch_name,
2640 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2645 if (!cpu_arch_flags.bitfield.cpui386
2646 && (flag_code != CODE_16BIT))
2648 as_warn (_("use .code16 to ensure correct addressing mode"));
2651 /* Check for rep/repne without a string instruction. */
2652 if (expecting_string_instruction)
2654 static templates override;
2656 for (t = current_templates->start; t < current_templates->end; ++t)
2657 if (t->opcode_modifier.isstring)
2659 if (t >= current_templates->end)
2661 as_bad (_("expecting string instruction after `%s'"),
2662 expecting_string_instruction);
2665 for (override.start = t; t < current_templates->end; ++t)
2666 if (!t->opcode_modifier.isstring)
2669 current_templates = &override;
2676 parse_operands (char *l, const char *mnemonic)
2680 /* 1 if operand is pending after ','. */
2681 unsigned int expecting_operand = 0;
2683 /* Non-zero if operand parens not balanced. */
2684 unsigned int paren_not_balanced;
2686 while (*l != END_OF_INSN)
2688 /* Skip optional white space before operand. */
2689 if (is_space_char (*l))
2691 if (!is_operand_char (*l) && *l != END_OF_INSN)
2693 as_bad (_("invalid character %s before operand %d"),
2694 output_invalid (*l),
2698 token_start = l; /* after white space */
2699 paren_not_balanced = 0;
2700 while (paren_not_balanced || *l != ',')
2702 if (*l == END_OF_INSN)
2704 if (paren_not_balanced)
2707 as_bad (_("unbalanced parenthesis in operand %d."),
2710 as_bad (_("unbalanced brackets in operand %d."),
2715 break; /* we are done */
2717 else if (!is_operand_char (*l) && !is_space_char (*l))
2719 as_bad (_("invalid character %s in operand %d"),
2720 output_invalid (*l),
2727 ++paren_not_balanced;
2729 --paren_not_balanced;
2734 ++paren_not_balanced;
2736 --paren_not_balanced;
2740 if (l != token_start)
2741 { /* Yes, we've read in another operand. */
2742 unsigned int operand_ok;
2743 this_operand = i.operands++;
2744 i.types[this_operand].bitfield.unspecified = 1;
2745 if (i.operands > MAX_OPERANDS)
2747 as_bad (_("spurious operands; (%d operands/instruction max)"),
2751 /* Now parse operand adding info to 'i' as we go along. */
2752 END_STRING_AND_SAVE (l);
2756 i386_intel_operand (token_start,
2757 intel_float_operand (mnemonic));
2759 operand_ok = i386_att_operand (token_start);
2761 RESTORE_END_STRING (l);
2767 if (expecting_operand)
2769 expecting_operand_after_comma:
2770 as_bad (_("expecting operand after ','; got nothing"));
2775 as_bad (_("expecting operand before ','; got nothing"));
2780 /* Now *l must be either ',' or END_OF_INSN. */
2783 if (*++l == END_OF_INSN)
2785 /* Just skip it, if it's \n complain. */
2786 goto expecting_operand_after_comma;
2788 expecting_operand = 1;
2795 swap_2_operands (int xchg1, int xchg2)
2797 union i386_op temp_op;
2798 i386_operand_type temp_type;
2799 enum bfd_reloc_code_real temp_reloc;
2801 temp_type = i.types[xchg2];
2802 i.types[xchg2] = i.types[xchg1];
2803 i.types[xchg1] = temp_type;
2804 temp_op = i.op[xchg2];
2805 i.op[xchg2] = i.op[xchg1];
2806 i.op[xchg1] = temp_op;
2807 temp_reloc = i.reloc[xchg2];
2808 i.reloc[xchg2] = i.reloc[xchg1];
2809 i.reloc[xchg1] = temp_reloc;
2813 swap_operands (void)
2818 swap_2_operands (1, i.operands - 2);
2821 swap_2_operands (0, i.operands - 1);
2827 if (i.mem_operands == 2)
2829 const seg_entry *temp_seg;
2830 temp_seg = i.seg[0];
2831 i.seg[0] = i.seg[1];
2832 i.seg[1] = temp_seg;
2836 /* Try to ensure constant immediates are represented in the smallest
2841 char guess_suffix = 0;
2845 guess_suffix = i.suffix;
2846 else if (i.reg_operands)
2848 /* Figure out a suffix from the last register operand specified.
2849 We can't do this properly yet, ie. excluding InOutPortReg,
2850 but the following works for instructions with immediates.
2851 In any case, we can't set i.suffix yet. */
2852 for (op = i.operands; --op >= 0;)
2853 if (i.types[op].bitfield.reg8)
2855 guess_suffix = BYTE_MNEM_SUFFIX;
2858 else if (i.types[op].bitfield.reg16)
2860 guess_suffix = WORD_MNEM_SUFFIX;
2863 else if (i.types[op].bitfield.reg32)
2865 guess_suffix = LONG_MNEM_SUFFIX;
2868 else if (i.types[op].bitfield.reg64)
2870 guess_suffix = QWORD_MNEM_SUFFIX;
2874 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2875 guess_suffix = WORD_MNEM_SUFFIX;
2877 for (op = i.operands; --op >= 0;)
2878 if (operand_type_check (i.types[op], imm))
2880 switch (i.op[op].imms->X_op)
2883 /* If a suffix is given, this operand may be shortened. */
2884 switch (guess_suffix)
2886 case LONG_MNEM_SUFFIX:
2887 i.types[op].bitfield.imm32 = 1;
2888 i.types[op].bitfield.imm64 = 1;
2890 case WORD_MNEM_SUFFIX:
2891 i.types[op].bitfield.imm16 = 1;
2892 i.types[op].bitfield.imm32 = 1;
2893 i.types[op].bitfield.imm32s = 1;
2894 i.types[op].bitfield.imm64 = 1;
2896 case BYTE_MNEM_SUFFIX:
2897 i.types[op].bitfield.imm8 = 1;
2898 i.types[op].bitfield.imm8s = 1;
2899 i.types[op].bitfield.imm16 = 1;
2900 i.types[op].bitfield.imm32 = 1;
2901 i.types[op].bitfield.imm32s = 1;
2902 i.types[op].bitfield.imm64 = 1;
2906 /* If this operand is at most 16 bits, convert it
2907 to a signed 16 bit number before trying to see
2908 whether it will fit in an even smaller size.
2909 This allows a 16-bit operand such as $0xffe0 to
2910 be recognised as within Imm8S range. */
2911 if ((i.types[op].bitfield.imm16)
2912 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2914 i.op[op].imms->X_add_number =
2915 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2917 if ((i.types[op].bitfield.imm32)
2918 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2921 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2922 ^ ((offsetT) 1 << 31))
2923 - ((offsetT) 1 << 31));
2926 = operand_type_or (i.types[op],
2927 smallest_imm_type (i.op[op].imms->X_add_number));
2929 /* We must avoid matching of Imm32 templates when 64bit
2930 only immediate is available. */
2931 if (guess_suffix == QWORD_MNEM_SUFFIX)
2932 i.types[op].bitfield.imm32 = 0;
2939 /* Symbols and expressions. */
2941 /* Convert symbolic operand to proper sizes for matching, but don't
2942 prevent matching a set of insns that only supports sizes other
2943 than those matching the insn suffix. */
2945 i386_operand_type mask, allowed;
2949 UINTS_CLEAR (allowed);
2951 for (t = current_templates->start;
2952 t < current_templates->end;
2954 allowed = operand_type_or (allowed,
2955 t->operand_types[op]);
2956 switch (guess_suffix)
2958 case QWORD_MNEM_SUFFIX:
2959 mask.bitfield.imm64 = 1;
2960 mask.bitfield.imm32s = 1;
2962 case LONG_MNEM_SUFFIX:
2963 mask.bitfield.imm32 = 1;
2965 case WORD_MNEM_SUFFIX:
2966 mask.bitfield.imm16 = 1;
2968 case BYTE_MNEM_SUFFIX:
2969 mask.bitfield.imm8 = 1;
2974 allowed = operand_type_and (mask, allowed);
2975 if (!UINTS_ALL_ZERO (allowed))
2976 i.types[op] = operand_type_and (i.types[op], mask);
2983 /* Try to use the smallest displacement type too. */
2985 optimize_disp (void)
2989 for (op = i.operands; --op >= 0;)
2990 if (operand_type_check (i.types[op], disp))
2992 if (i.op[op].disps->X_op == O_constant)
2994 offsetT disp = i.op[op].disps->X_add_number;
2996 if (i.types[op].bitfield.disp16
2997 && (disp & ~(offsetT) 0xffff) == 0)
2999 /* If this operand is at most 16 bits, convert
3000 to a signed 16 bit number and don't use 64bit
3002 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3003 i.types[op].bitfield.disp64 = 0;
3005 if (i.types[op].bitfield.disp32
3006 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3008 /* If this operand is at most 32 bits, convert
3009 to a signed 32 bit number and don't use 64bit
3011 disp &= (((offsetT) 2 << 31) - 1);
3012 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3013 i.types[op].bitfield.disp64 = 0;
3015 if (!disp && i.types[op].bitfield.baseindex)
3017 i.types[op].bitfield.disp8 = 0;
3018 i.types[op].bitfield.disp16 = 0;
3019 i.types[op].bitfield.disp32 = 0;
3020 i.types[op].bitfield.disp32s = 0;
3021 i.types[op].bitfield.disp64 = 0;
3025 else if (flag_code == CODE_64BIT)
3027 if (fits_in_signed_long (disp))
3029 i.types[op].bitfield.disp64 = 0;
3030 i.types[op].bitfield.disp32s = 1;
3032 if (fits_in_unsigned_long (disp))
3033 i.types[op].bitfield.disp32 = 1;
3035 if ((i.types[op].bitfield.disp32
3036 || i.types[op].bitfield.disp32s
3037 || i.types[op].bitfield.disp16)
3038 && fits_in_signed_byte (disp))
3039 i.types[op].bitfield.disp8 = 1;
3041 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3042 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3044 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3045 i.op[op].disps, 0, i.reloc[op]);
3046 i.types[op].bitfield.disp8 = 0;
3047 i.types[op].bitfield.disp16 = 0;
3048 i.types[op].bitfield.disp32 = 0;
3049 i.types[op].bitfield.disp32s = 0;
3050 i.types[op].bitfield.disp64 = 0;
3053 /* We only support 64bit displacement on constants. */
3054 i.types[op].bitfield.disp64 = 0;
3059 match_template (void)
3061 /* Points to template once we've found it. */
3063 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3064 unsigned int found_reverse_match;
3065 i386_opcode_modifier suffix_check;
3066 i386_operand_type operand_types [MAX_OPERANDS];
3067 int addr_prefix_disp;
3069 unsigned int found_cpu_match;
3070 unsigned int check_register;
3072 #if MAX_OPERANDS != 4
3073 # error "MAX_OPERANDS must be 4."
3076 found_reverse_match = 0;
3077 addr_prefix_disp = -1;
3079 memset (&suffix_check, 0, sizeof (suffix_check));
3080 if (i.suffix == BYTE_MNEM_SUFFIX)
3081 suffix_check.no_bsuf = 1;
3082 else if (i.suffix == WORD_MNEM_SUFFIX)
3083 suffix_check.no_wsuf = 1;
3084 else if (i.suffix == SHORT_MNEM_SUFFIX)
3085 suffix_check.no_ssuf = 1;
3086 else if (i.suffix == LONG_MNEM_SUFFIX)
3087 suffix_check.no_lsuf = 1;
3088 else if (i.suffix == QWORD_MNEM_SUFFIX)
3089 suffix_check.no_qsuf = 1;
3090 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3091 suffix_check.no_ldsuf = 1;
3093 for (t = current_templates->start; t < current_templates->end; t++)
3095 addr_prefix_disp = -1;
3097 /* Must have right number of operands. */
3098 if (i.operands != t->operands)
3101 /* Check processor support. */
3102 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3103 if (!found_cpu_match)
3106 /* Check old gcc support. */
3107 if (!old_gcc && t->opcode_modifier.oldgcc)
3110 /* Check AT&T mnemonic. */
3111 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3114 /* Check AT&T syntax Intel syntax. */
3115 if ((intel_syntax && t->opcode_modifier.attsyntax)
3116 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3119 /* Check the suffix, except for some instructions in intel mode. */
3120 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3121 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3122 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3123 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3124 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3125 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3126 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3129 if (!operand_size_match (t))
3132 for (j = 0; j < MAX_OPERANDS; j++)
3133 operand_types[j] = t->operand_types[j];
3135 /* In general, don't allow 64-bit operands in 32-bit mode. */
3136 if (i.suffix == QWORD_MNEM_SUFFIX
3137 && flag_code != CODE_64BIT
3139 ? (!t->opcode_modifier.ignoresize
3140 && !intel_float_operand (t->name))
3141 : intel_float_operand (t->name) != 2)
3142 && ((!operand_types[0].bitfield.regmmx
3143 && !operand_types[0].bitfield.regxmm)
3144 || (!operand_types[t->operands > 1].bitfield.regmmx
3145 && !!operand_types[t->operands > 1].bitfield.regxmm))
3146 && (t->base_opcode != 0x0fc7
3147 || t->extension_opcode != 1 /* cmpxchg8b */))
3150 /* Do not verify operands when there are none. */
3154 /* We've found a match; break out of loop. */
3158 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3159 into Disp32/Disp16/Disp32 operand. */
3160 if (i.prefix[ADDR_PREFIX] != 0)
3162 /* There should be only one Disp operand. */
3166 for (j = 0; j < MAX_OPERANDS; j++)
3168 if (operand_types[j].bitfield.disp16)
3170 addr_prefix_disp = j;
3171 operand_types[j].bitfield.disp32 = 1;
3172 operand_types[j].bitfield.disp16 = 0;
3178 for (j = 0; j < MAX_OPERANDS; j++)
3180 if (operand_types[j].bitfield.disp32)
3182 addr_prefix_disp = j;
3183 operand_types[j].bitfield.disp32 = 0;
3184 operand_types[j].bitfield.disp16 = 1;
3190 for (j = 0; j < MAX_OPERANDS; j++)
3192 if (operand_types[j].bitfield.disp64)
3194 addr_prefix_disp = j;
3195 operand_types[j].bitfield.disp64 = 0;
3196 operand_types[j].bitfield.disp32 = 1;
3204 /* We check register size only if size of operands can be
3205 encoded the canonical way. */
3206 check_register = t->opcode_modifier.w;
3207 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3208 switch (t->operands)
3211 if (!operand_type_match (overlap0, i.types[0]))
3215 /* xchg %eax, %eax is a special case. It is an aliase for nop
3216 only in 32bit mode and we can use opcode 0x90. In 64bit
3217 mode, we can't use 0x90 for xchg %eax, %eax since it should
3218 zero-extend %eax to %rax. */
3219 if (flag_code == CODE_64BIT
3220 && t->base_opcode == 0x90
3221 && UINTS_EQUAL (i.types [0], acc32)
3222 && UINTS_EQUAL (i.types [1], acc32))
3226 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3227 if (!operand_type_match (overlap0, i.types[0])
3228 || !operand_type_match (overlap1, i.types[1])
3230 && !operand_type_register_match (overlap0, i.types[0],
3232 overlap1, i.types[1],
3235 /* Check if other direction is valid ... */
3236 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3239 /* Try reversing direction of operands. */
3240 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3241 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3242 if (!operand_type_match (overlap0, i.types[0])
3243 || !operand_type_match (overlap1, i.types[1])
3245 && !operand_type_register_match (overlap0,
3252 /* Does not match either direction. */
3255 /* found_reverse_match holds which of D or FloatDR
3257 if (t->opcode_modifier.d)
3258 found_reverse_match = Opcode_D;
3259 else if (t->opcode_modifier.floatd)
3260 found_reverse_match = Opcode_FloatD;
3262 found_reverse_match = 0;
3263 if (t->opcode_modifier.floatr)
3264 found_reverse_match |= Opcode_FloatR;
3268 /* Found a forward 2 operand match here. */
3269 switch (t->operands)
3272 overlap3 = operand_type_and (i.types[3],
3275 overlap2 = operand_type_and (i.types[2],
3280 switch (t->operands)
3283 if (!operand_type_match (overlap3, i.types[3])
3285 && !operand_type_register_match (overlap2,
3293 /* Here we make use of the fact that there are no
3294 reverse match 3 operand instructions, and all 3
3295 operand instructions only need to be checked for
3296 register consistency between operands 2 and 3. */
3297 if (!operand_type_match (overlap2, i.types[2])
3299 && !operand_type_register_match (overlap1,
3309 /* Found either forward/reverse 2, 3 or 4 operand match here:
3310 slip through to break. */
3312 if (!found_cpu_match)
3314 found_reverse_match = 0;
3317 /* We've found a match; break out of loop. */
3321 if (t == current_templates->end)
3323 /* We found no match. */
3324 as_bad (_("suffix or operands invalid for `%s'"),
3325 current_templates->start->name);
3329 if (!quiet_warnings)
3332 && (i.types[0].bitfield.jumpabsolute
3333 != operand_types[0].bitfield.jumpabsolute))
3335 as_warn (_("indirect %s without `*'"), t->name);
3338 if (t->opcode_modifier.isprefix
3339 && t->opcode_modifier.ignoresize)
3341 /* Warn them that a data or address size prefix doesn't
3342 affect assembly of the next line of code. */
3343 as_warn (_("stand-alone `%s' prefix"), t->name);
3347 /* Copy the template we found. */
3350 if (addr_prefix_disp != -1)
3351 i.tm.operand_types[addr_prefix_disp]
3352 = operand_types[addr_prefix_disp];
3354 if (found_reverse_match)
3356 /* If we found a reverse match we must alter the opcode
3357 direction bit. found_reverse_match holds bits to change
3358 (different for int & float insns). */
3360 i.tm.base_opcode ^= found_reverse_match;
3362 i.tm.operand_types[0] = operand_types[1];
3363 i.tm.operand_types[1] = operand_types[0];
3372 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3373 if (i.tm.operand_types[mem_op].bitfield.esseg)
3375 if (i.seg[0] != NULL && i.seg[0] != &es)
3377 as_bad (_("`%s' operand %d must use `%%es' segment"),
3382 /* There's only ever one segment override allowed per instruction.
3383 This instruction possibly has a legal segment override on the
3384 second operand, so copy the segment to where non-string
3385 instructions store it, allowing common code. */
3386 i.seg[0] = i.seg[1];
3388 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3390 if (i.seg[1] != NULL && i.seg[1] != &es)
3392 as_bad (_("`%s' operand %d must use `%%es' segment"),
3402 process_suffix (void)
3404 /* If matched instruction specifies an explicit instruction mnemonic
3406 if (i.tm.opcode_modifier.size16)
3407 i.suffix = WORD_MNEM_SUFFIX;
3408 else if (i.tm.opcode_modifier.size32)
3409 i.suffix = LONG_MNEM_SUFFIX;
3410 else if (i.tm.opcode_modifier.size64)
3411 i.suffix = QWORD_MNEM_SUFFIX;
3412 else if (i.reg_operands)
3414 /* If there's no instruction mnemonic suffix we try to invent one
3415 based on register operands. */
3418 /* We take i.suffix from the last register operand specified,
3419 Destination register type is more significant than source
3420 register type. crc32 in SSE4.2 prefers source register
3422 if (i.tm.base_opcode == 0xf20f38f1)
3424 if (i.types[0].bitfield.reg16)
3425 i.suffix = WORD_MNEM_SUFFIX;
3426 else if (i.types[0].bitfield.reg32)
3427 i.suffix = LONG_MNEM_SUFFIX;
3428 else if (i.types[0].bitfield.reg64)
3429 i.suffix = QWORD_MNEM_SUFFIX;
3431 else if (i.tm.base_opcode == 0xf20f38f0)
3433 if (i.types[0].bitfield.reg8)
3434 i.suffix = BYTE_MNEM_SUFFIX;
3441 if (i.tm.base_opcode == 0xf20f38f1
3442 || i.tm.base_opcode == 0xf20f38f0)
3444 /* We have to know the operand size for crc32. */
3445 as_bad (_("ambiguous memory operand size for `%s`"),
3450 for (op = i.operands; --op >= 0;)
3451 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3453 if (i.types[op].bitfield.reg8)
3455 i.suffix = BYTE_MNEM_SUFFIX;
3458 else if (i.types[op].bitfield.reg16)
3460 i.suffix = WORD_MNEM_SUFFIX;
3463 else if (i.types[op].bitfield.reg32)
3465 i.suffix = LONG_MNEM_SUFFIX;
3468 else if (i.types[op].bitfield.reg64)
3470 i.suffix = QWORD_MNEM_SUFFIX;
3476 else if (i.suffix == BYTE_MNEM_SUFFIX)
3478 if (!check_byte_reg ())
3481 else if (i.suffix == LONG_MNEM_SUFFIX)
3483 if (!check_long_reg ())
3486 else if (i.suffix == QWORD_MNEM_SUFFIX)
3489 && i.tm.opcode_modifier.ignoresize
3490 && i.tm.opcode_modifier.no_qsuf)
3492 else if (!check_qword_reg ())
3495 else if (i.suffix == WORD_MNEM_SUFFIX)
3497 if (!check_word_reg ())
3500 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3502 /* Skip if the instruction has x suffix. match_template
3503 should check if it is a valid suffix. */
3505 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3506 /* Do nothing if the instruction is going to ignore the prefix. */
3511 else if (i.tm.opcode_modifier.defaultsize
3513 /* exclude fldenv/frstor/fsave/fstenv */
3514 && i.tm.opcode_modifier.no_ssuf)
3516 i.suffix = stackop_size;
3518 else if (intel_syntax
3520 && (i.tm.operand_types[0].bitfield.jumpabsolute
3521 || i.tm.opcode_modifier.jumpbyte
3522 || i.tm.opcode_modifier.jumpintersegment
3523 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3524 && i.tm.extension_opcode <= 3)))
3529 if (!i.tm.opcode_modifier.no_qsuf)
3531 i.suffix = QWORD_MNEM_SUFFIX;
3535 if (!i.tm.opcode_modifier.no_lsuf)
3536 i.suffix = LONG_MNEM_SUFFIX;
3539 if (!i.tm.opcode_modifier.no_wsuf)
3540 i.suffix = WORD_MNEM_SUFFIX;
3549 if (i.tm.opcode_modifier.w)
3551 as_bad (_("no instruction mnemonic suffix given and "
3552 "no register operands; can't size instruction"));
3558 unsigned int suffixes;
3560 suffixes = !i.tm.opcode_modifier.no_bsuf;
3561 if (!i.tm.opcode_modifier.no_wsuf)
3563 if (!i.tm.opcode_modifier.no_lsuf)
3565 if (!i.tm.opcode_modifier.no_ldsuf)
3567 if (!i.tm.opcode_modifier.no_ssuf)
3569 if (!i.tm.opcode_modifier.no_qsuf)
3572 /* There are more than suffix matches. */
3573 if (i.tm.opcode_modifier.w
3574 || ((suffixes & (suffixes - 1))
3575 && !i.tm.opcode_modifier.defaultsize
3576 && !i.tm.opcode_modifier.ignoresize))
3578 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3584 /* Change the opcode based on the operand size given by i.suffix;
3585 We don't need to change things for byte insns. */
3588 && i.suffix != BYTE_MNEM_SUFFIX
3589 && i.suffix != XMMWORD_MNEM_SUFFIX)
3591 /* It's not a byte, select word/dword operation. */
3592 if (i.tm.opcode_modifier.w)
3594 if (i.tm.opcode_modifier.shortform)
3595 i.tm.base_opcode |= 8;
3597 i.tm.base_opcode |= 1;
3600 /* Now select between word & dword operations via the operand
3601 size prefix, except for instructions that will ignore this
3603 if (i.tm.opcode_modifier.addrprefixop0)
3605 /* The address size override prefix changes the size of the
3607 if ((flag_code == CODE_32BIT
3608 && i.op->regs[0].reg_type.bitfield.reg16)
3609 || (flag_code != CODE_32BIT
3610 && i.op->regs[0].reg_type.bitfield.reg32))
3611 if (!add_prefix (ADDR_PREFIX_OPCODE))
3614 else if (i.suffix != QWORD_MNEM_SUFFIX
3615 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3616 && !i.tm.opcode_modifier.ignoresize
3617 && !i.tm.opcode_modifier.floatmf
3618 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3619 || (flag_code == CODE_64BIT
3620 && i.tm.opcode_modifier.jumpbyte)))
3622 unsigned int prefix = DATA_PREFIX_OPCODE;
3624 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3625 prefix = ADDR_PREFIX_OPCODE;
3627 if (!add_prefix (prefix))
3631 /* Set mode64 for an operand. */
3632 if (i.suffix == QWORD_MNEM_SUFFIX
3633 && flag_code == CODE_64BIT
3634 && !i.tm.opcode_modifier.norex64)
3636 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3637 need rex64. cmpxchg8b is also a special case. */
3638 if (! (i.operands == 2
3639 && i.tm.base_opcode == 0x90
3640 && i.tm.extension_opcode == None
3641 && UINTS_EQUAL (i.types [0], acc64)
3642 && UINTS_EQUAL (i.types [1], acc64))
3643 && ! (i.operands == 1
3644 && i.tm.base_opcode == 0xfc7
3645 && i.tm.extension_opcode == 1
3646 && !operand_type_check (i.types [0], reg)
3647 && operand_type_check (i.types [0], anymem)))
3651 /* Size floating point instruction. */
3652 if (i.suffix == LONG_MNEM_SUFFIX)
3653 if (i.tm.opcode_modifier.floatmf)
3654 i.tm.base_opcode ^= 4;
3661 check_byte_reg (void)
3665 for (op = i.operands; --op >= 0;)
3667 /* If this is an eight bit register, it's OK. If it's the 16 or
3668 32 bit version of an eight bit register, we will just use the
3669 low portion, and that's OK too. */
3670 if (i.types[op].bitfield.reg8)
3673 /* Don't generate this warning if not needed. */
3674 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3677 /* crc32 doesn't generate this warning. */
3678 if (i.tm.base_opcode == 0xf20f38f0)
3681 if ((i.types[op].bitfield.reg16
3682 || i.types[op].bitfield.reg32
3683 || i.types[op].bitfield.reg64)
3684 && i.op[op].regs->reg_num < 4)
3686 /* Prohibit these changes in the 64bit mode, since the
3687 lowering is more complicated. */
3688 if (flag_code == CODE_64BIT
3689 && !i.tm.operand_types[op].bitfield.inoutportreg)
3691 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3692 register_prefix, i.op[op].regs->reg_name,
3696 #if REGISTER_WARNINGS
3698 && !i.tm.operand_types[op].bitfield.inoutportreg)
3699 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3701 (i.op[op].regs + (i.types[op].bitfield.reg16
3702 ? REGNAM_AL - REGNAM_AX
3703 : REGNAM_AL - REGNAM_EAX))->reg_name,
3705 i.op[op].regs->reg_name,
3710 /* Any other register is bad. */
3711 if (i.types[op].bitfield.reg16
3712 || i.types[op].bitfield.reg32
3713 || i.types[op].bitfield.reg64
3714 || i.types[op].bitfield.regmmx
3715 || i.types[op].bitfield.regxmm
3716 || i.types[op].bitfield.sreg2
3717 || i.types[op].bitfield.sreg3
3718 || i.types[op].bitfield.control
3719 || i.types[op].bitfield.debug
3720 || i.types[op].bitfield.test
3721 || i.types[op].bitfield.floatreg
3722 || i.types[op].bitfield.floatacc)
3724 as_bad (_("`%s%s' not allowed with `%s%c'"),
3726 i.op[op].regs->reg_name,
3736 check_long_reg (void)
3740 for (op = i.operands; --op >= 0;)
3741 /* Reject eight bit registers, except where the template requires
3742 them. (eg. movzb) */
3743 if (i.types[op].bitfield.reg8
3744 && (i.tm.operand_types[op].bitfield.reg16
3745 || i.tm.operand_types[op].bitfield.reg32
3746 || i.tm.operand_types[op].bitfield.acc))
3748 as_bad (_("`%s%s' not allowed with `%s%c'"),
3750 i.op[op].regs->reg_name,
3755 /* Warn if the e prefix on a general reg is missing. */
3756 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3757 && i.types[op].bitfield.reg16
3758 && (i.tm.operand_types[op].bitfield.reg32
3759 || i.tm.operand_types[op].bitfield.acc))
3761 /* Prohibit these changes in the 64bit mode, since the
3762 lowering is more complicated. */
3763 if (flag_code == CODE_64BIT)
3765 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3766 register_prefix, i.op[op].regs->reg_name,
3770 #if REGISTER_WARNINGS
3772 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3774 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3776 i.op[op].regs->reg_name,
3780 /* Warn if the r prefix on a general reg is missing. */
3781 else if (i.types[op].bitfield.reg64
3782 && (i.tm.operand_types[op].bitfield.reg32
3783 || i.tm.operand_types[op].bitfield.acc))
3786 && i.tm.opcode_modifier.toqword
3787 && !i.types[0].bitfield.regxmm)
3789 /* Convert to QWORD. We want REX byte. */
3790 i.suffix = QWORD_MNEM_SUFFIX;
3794 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3795 register_prefix, i.op[op].regs->reg_name,
3804 check_qword_reg (void)
3808 for (op = i.operands; --op >= 0; )
3809 /* Reject eight bit registers, except where the template requires
3810 them. (eg. movzb) */
3811 if (i.types[op].bitfield.reg8
3812 && (i.tm.operand_types[op].bitfield.reg16
3813 || i.tm.operand_types[op].bitfield.reg32
3814 || i.tm.operand_types[op].bitfield.acc))
3816 as_bad (_("`%s%s' not allowed with `%s%c'"),
3818 i.op[op].regs->reg_name,
3823 /* Warn if the e prefix on a general reg is missing. */
3824 else if ((i.types[op].bitfield.reg16
3825 || i.types[op].bitfield.reg32)
3826 && (i.tm.operand_types[op].bitfield.reg32
3827 || i.tm.operand_types[op].bitfield.acc))
3829 /* Prohibit these changes in the 64bit mode, since the
3830 lowering is more complicated. */
3832 && i.tm.opcode_modifier.todword
3833 && !i.types[0].bitfield.regxmm)
3835 /* Convert to DWORD. We don't want REX byte. */
3836 i.suffix = LONG_MNEM_SUFFIX;
3840 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3841 register_prefix, i.op[op].regs->reg_name,
3850 check_word_reg (void)
3853 for (op = i.operands; --op >= 0;)
3854 /* Reject eight bit registers, except where the template requires
3855 them. (eg. movzb) */
3856 if (i.types[op].bitfield.reg8
3857 && (i.tm.operand_types[op].bitfield.reg16
3858 || i.tm.operand_types[op].bitfield.reg32
3859 || i.tm.operand_types[op].bitfield.acc))
3861 as_bad (_("`%s%s' not allowed with `%s%c'"),
3863 i.op[op].regs->reg_name,
3868 /* Warn if the e prefix on a general reg is present. */
3869 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3870 && i.types[op].bitfield.reg32
3871 && (i.tm.operand_types[op].bitfield.reg16
3872 || i.tm.operand_types[op].bitfield.acc))
3874 /* Prohibit these changes in the 64bit mode, since the
3875 lowering is more complicated. */
3876 if (flag_code == CODE_64BIT)
3878 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3879 register_prefix, i.op[op].regs->reg_name,
3884 #if REGISTER_WARNINGS
3885 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3887 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3889 i.op[op].regs->reg_name,
3897 update_imm (unsigned int j)
3899 i386_operand_type overlap;
3901 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3902 if ((overlap.bitfield.imm8
3903 || overlap.bitfield.imm8s
3904 || overlap.bitfield.imm16
3905 || overlap.bitfield.imm32
3906 || overlap.bitfield.imm32s
3907 || overlap.bitfield.imm64)
3908 && !UINTS_EQUAL (overlap, imm8)
3909 && !UINTS_EQUAL (overlap, imm8s)
3910 && !UINTS_EQUAL (overlap, imm16)
3911 && !UINTS_EQUAL (overlap, imm32)
3912 && !UINTS_EQUAL (overlap, imm32s)
3913 && !UINTS_EQUAL (overlap, imm64))
3917 i386_operand_type temp;
3920 if (i.suffix == BYTE_MNEM_SUFFIX)
3922 temp.bitfield.imm8 = overlap.bitfield.imm8;
3923 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3925 else if (i.suffix == WORD_MNEM_SUFFIX)
3926 temp.bitfield.imm16 = overlap.bitfield.imm16;
3927 else if (i.suffix == QWORD_MNEM_SUFFIX)
3929 temp.bitfield.imm64 = overlap.bitfield.imm64;
3930 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3933 temp.bitfield.imm32 = overlap.bitfield.imm32;
3936 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3937 || UINTS_EQUAL (overlap, imm16_32)
3938 || UINTS_EQUAL (overlap, imm16_32s))
3940 UINTS_CLEAR (overlap);
3941 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3942 overlap.bitfield.imm16 = 1;
3944 overlap.bitfield.imm32s = 1;
3946 if (!UINTS_EQUAL (overlap, imm8)
3947 && !UINTS_EQUAL (overlap, imm8s)
3948 && !UINTS_EQUAL (overlap, imm16)
3949 && !UINTS_EQUAL (overlap, imm32)
3950 && !UINTS_EQUAL (overlap, imm32s)
3951 && !UINTS_EQUAL (overlap, imm64))
3953 as_bad (_("no instruction mnemonic suffix given; "
3954 "can't determine immediate size"));
3958 i.types[j] = overlap;
3968 for (j = 0; j < 2; j++)
3969 if (update_imm (j) == 0)
3972 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3973 assert (operand_type_check (i.types[2], imm) == 0);
3981 i.drex.modrm_reg = 0;
3982 i.drex.modrm_regmem = 0;
3984 /* SSE5 4 operand instructions must have the destination the same as
3985 one of the inputs. Figure out the destination register and cache
3986 it away in the drex field, and remember which fields to use for
3988 if (i.tm.opcode_modifier.drex
3989 && i.tm.opcode_modifier.drexv
3992 i.tm.extension_opcode = None;
3994 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3995 if (i.types[0].bitfield.regxmm != 0
3996 && i.types[1].bitfield.regxmm != 0
3997 && i.types[2].bitfield.regxmm != 0
3998 && i.types[3].bitfield.regxmm != 0
3999 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4000 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4002 /* Clear the arguments that are stored in drex. */
4003 UINTS_CLEAR (i.types[0]);
4004 UINTS_CLEAR (i.types[3]);
4005 i.reg_operands -= 2;
4007 /* There are two different ways to encode a 4 operand
4008 instruction with all registers that uses OC1 set to
4009 0 or 1. Favor setting OC1 to 0 since this mimics the
4010 actions of other SSE5 assemblers. Use modrm encoding 2
4011 for register/register. Include the high order bit that
4012 is normally stored in the REX byte in the register
4014 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4015 i.drex.modrm_reg = 2;
4016 i.drex.modrm_regmem = 1;
4017 i.drex.reg = (i.op[3].regs->reg_num
4018 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4021 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4022 else if (i.types[0].bitfield.regxmm != 0
4023 && i.types[1].bitfield.regxmm != 0
4024 && (i.types[2].bitfield.regxmm
4025 || operand_type_check (i.types[2], anymem))
4026 && i.types[3].bitfield.regxmm != 0
4027 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4028 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4030 /* clear the arguments that are stored in drex */
4031 UINTS_CLEAR (i.types[0]);
4032 UINTS_CLEAR (i.types[3]);
4033 i.reg_operands -= 2;
4035 /* Specify the modrm encoding for memory addressing. Include
4036 the high order bit that is normally stored in the REX byte
4037 in the register field. */
4038 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4039 i.drex.modrm_reg = 1;
4040 i.drex.modrm_regmem = 2;
4041 i.drex.reg = (i.op[3].regs->reg_num
4042 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4045 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4046 else if (i.types[0].bitfield.regxmm != 0
4047 && operand_type_check (i.types[1], anymem) != 0
4048 && i.types[2].bitfield.regxmm != 0
4049 && i.types[3].bitfield.regxmm != 0
4050 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4051 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4053 /* Clear the arguments that are stored in drex. */
4054 UINTS_CLEAR (i.types[0]);
4055 UINTS_CLEAR (i.types[3]);
4056 i.reg_operands -= 2;
4058 /* Specify the modrm encoding for memory addressing. Include
4059 the high order bit that is normally stored in the REX byte
4060 in the register field. */
4061 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4062 i.drex.modrm_reg = 2;
4063 i.drex.modrm_regmem = 1;
4064 i.drex.reg = (i.op[3].regs->reg_num
4065 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4068 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4069 else if (i.types[0].bitfield.regxmm != 0
4070 && i.types[1].bitfield.regxmm != 0
4071 && i.types[2].bitfield.regxmm != 0
4072 && i.types[3].bitfield.regxmm != 0
4073 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4074 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4076 /* clear the arguments that are stored in drex */
4077 UINTS_CLEAR (i.types[2]);
4078 UINTS_CLEAR (i.types[3]);
4079 i.reg_operands -= 2;
4081 /* There are two different ways to encode a 4 operand
4082 instruction with all registers that uses OC1 set to
4083 0 or 1. Favor setting OC1 to 0 since this mimics the
4084 actions of other SSE5 assemblers. Use modrm encoding
4085 2 for register/register. Include the high order bit that
4086 is normally stored in the REX byte in the register
4088 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4089 i.drex.modrm_reg = 1;
4090 i.drex.modrm_regmem = 0;
4092 /* Remember the register, including the upper bits */
4093 i.drex.reg = (i.op[3].regs->reg_num
4094 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4097 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4098 else if (i.types[0].bitfield.regxmm != 0
4099 && (i.types[1].bitfield.regxmm
4100 || operand_type_check (i.types[1], anymem))
4101 && i.types[2].bitfield.regxmm != 0
4102 && i.types[3].bitfield.regxmm != 0
4103 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4104 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4106 /* Clear the arguments that are stored in drex. */
4107 UINTS_CLEAR (i.types[2]);
4108 UINTS_CLEAR (i.types[3]);
4109 i.reg_operands -= 2;
4111 /* Specify the modrm encoding and remember the register
4112 including the bits normally stored in the REX byte. */
4113 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4114 i.drex.modrm_reg = 0;
4115 i.drex.modrm_regmem = 1;
4116 i.drex.reg = (i.op[3].regs->reg_num
4117 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4120 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4121 else if (operand_type_check (i.types[0], anymem) != 0
4122 && i.types[1].bitfield.regxmm != 0
4123 && i.types[2].bitfield.regxmm != 0
4124 && i.types[3].bitfield.regxmm != 0
4125 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4126 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4128 /* clear the arguments that are stored in drex */
4129 UINTS_CLEAR (i.types[2]);
4130 UINTS_CLEAR (i.types[3]);
4131 i.reg_operands -= 2;
4133 /* Specify the modrm encoding and remember the register
4134 including the bits normally stored in the REX byte. */
4135 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4136 i.drex.modrm_reg = 1;
4137 i.drex.modrm_regmem = 0;
4138 i.drex.reg = (i.op[3].regs->reg_num
4139 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4143 as_bad (_("Incorrect operands for the '%s' instruction"),
4147 /* SSE5 instructions with the DREX byte where the only memory operand
4148 is in the 2nd argument, and the first and last xmm register must
4149 match, and is encoded in the DREX byte. */
4150 else if (i.tm.opcode_modifier.drex
4151 && !i.tm.opcode_modifier.drexv
4154 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4155 if (i.types[0].bitfield.regxmm != 0
4156 && (i.types[1].bitfield.regxmm
4157 || operand_type_check(i.types[1], anymem))
4158 && i.types[2].bitfield.regxmm != 0
4159 && i.types[3].bitfield.regxmm != 0
4160 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4161 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4163 /* clear the arguments that are stored in drex */
4164 UINTS_CLEAR (i.types[0]);
4165 UINTS_CLEAR (i.types[3]);
4166 i.reg_operands -= 2;
4168 /* Specify the modrm encoding and remember the register
4169 including the high bit normally stored in the REX
4171 i.drex.modrm_reg = 2;
4172 i.drex.modrm_regmem = 1;
4173 i.drex.reg = (i.op[3].regs->reg_num
4174 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4178 as_bad (_("Incorrect operands for the '%s' instruction"),
4182 /* SSE5 3 operand instructions that the result is a register, being
4183 either operand can be a memory operand, using OC0 to note which
4184 one is the memory. */
4185 else if (i.tm.opcode_modifier.drex
4186 && i.tm.opcode_modifier.drexv
4189 i.tm.extension_opcode = None;
4191 /* Case 1: 3 operand insn, src1 = register. */
4192 if (i.types[0].bitfield.regxmm != 0
4193 && i.types[1].bitfield.regxmm != 0
4194 && i.types[2].bitfield.regxmm != 0)
4196 /* Clear the arguments that are stored in drex. */
4197 UINTS_CLEAR (i.types[2]);
4200 /* Specify the modrm encoding and remember the register
4201 including the high bit normally stored in the REX byte. */
4202 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4203 i.drex.modrm_reg = 1;
4204 i.drex.modrm_regmem = 0;
4205 i.drex.reg = (i.op[2].regs->reg_num
4206 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4209 /* Case 2: 3 operand insn, src1 = memory. */
4210 else if (operand_type_check (i.types[0], anymem) != 0
4211 && i.types[1].bitfield.regxmm != 0
4212 && i.types[2].bitfield.regxmm != 0)
4214 /* Clear the arguments that are stored in drex. */
4215 UINTS_CLEAR (i.types[2]);
4218 /* Specify the modrm encoding and remember the register
4219 including the high bit normally stored in the REX
4221 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4222 i.drex.modrm_reg = 1;
4223 i.drex.modrm_regmem = 0;
4224 i.drex.reg = (i.op[2].regs->reg_num
4225 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4228 /* Case 3: 3 operand insn, src2 = memory. */
4229 else if (i.types[0].bitfield.regxmm != 0
4230 && operand_type_check (i.types[1], anymem) != 0
4231 && i.types[2].bitfield.regxmm != 0)
4233 /* Clear the arguments that are stored in drex. */
4234 UINTS_CLEAR (i.types[2]);
4237 /* Specify the modrm encoding and remember the register
4238 including the high bit normally stored in the REX byte. */
4239 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4240 i.drex.modrm_reg = 0;
4241 i.drex.modrm_regmem = 1;
4242 i.drex.reg = (i.op[2].regs->reg_num
4243 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4247 as_bad (_("Incorrect operands for the '%s' instruction"),
4251 /* SSE5 4 operand instructions that are the comparison instructions
4252 where the first operand is the immediate value of the comparison
4254 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4256 /* Case 1: 4 operand insn, src1 = reg/memory. */
4257 if (operand_type_check (i.types[0], imm) != 0
4258 && (i.types[1].bitfield.regxmm
4259 || operand_type_check (i.types[1], anymem))
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0)
4263 /* clear the arguments that are stored in drex */
4264 UINTS_CLEAR (i.types[3]);
4267 /* Specify the modrm encoding and remember the register
4268 including the high bit normally stored in the REX byte. */
4269 i.drex.modrm_reg = 2;
4270 i.drex.modrm_regmem = 1;
4271 i.drex.reg = (i.op[3].regs->reg_num
4272 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4275 /* Case 2: 3 operand insn with ImmExt that places the
4276 opcode_extension as an immediate argument. This is used for
4277 all of the varients of comparison that supplies the appropriate
4278 value as part of the instruction. */
4279 else if ((i.types[0].bitfield.regxmm
4280 || operand_type_check (i.types[0], anymem))
4281 && i.types[1].bitfield.regxmm != 0
4282 && i.types[2].bitfield.regxmm != 0
4283 && operand_type_check (i.types[3], imm) != 0)
4285 /* clear the arguments that are stored in drex */
4286 UINTS_CLEAR (i.types[2]);
4289 /* Specify the modrm encoding and remember the register
4290 including the high bit normally stored in the REX byte. */
4291 i.drex.modrm_reg = 1;
4292 i.drex.modrm_regmem = 0;
4293 i.drex.reg = (i.op[2].regs->reg_num
4294 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4298 as_bad (_("Incorrect operands for the '%s' instruction"),
4302 else if (i.tm.opcode_modifier.drex
4303 || i.tm.opcode_modifier.drexv
4304 || i.tm.opcode_modifier.drexc)
4305 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4309 process_operands (void)
4311 /* Default segment register this instruction will use for memory
4312 accesses. 0 means unknown. This is only for optimizing out
4313 unnecessary segment overrides. */
4314 const seg_entry *default_seg = 0;
4316 /* Handle all of the DREX munging that SSE5 needs. */
4317 if (i.tm.opcode_modifier.drex
4318 || i.tm.opcode_modifier.drexv
4319 || i.tm.opcode_modifier.drexc)
4322 if (i.tm.opcode_modifier.firstxmm0)
4326 /* The first operand is implicit and must be xmm0. */
4327 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4328 if (i.op[0].regs->reg_num != 0)
4331 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4332 i.tm.name, register_prefix);
4334 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4335 i.tm.name, register_prefix);
4339 for (j = 1; j < i.operands; j++)
4341 i.op[j - 1] = i.op[j];
4342 i.types[j - 1] = i.types[j];
4344 /* We need to adjust fields in i.tm since they are used by
4345 build_modrm_byte. */
4346 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4353 else if (i.tm.opcode_modifier.regkludge)
4355 /* The imul $imm, %reg instruction is converted into
4356 imul $imm, %reg, %reg, and the clr %reg instruction
4357 is converted into xor %reg, %reg. */
4359 unsigned int first_reg_op;
4361 if (operand_type_check (i.types[0], reg))
4365 /* Pretend we saw the extra register operand. */
4366 assert (i.reg_operands == 1
4367 && i.op[first_reg_op + 1].regs == 0);
4368 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4369 i.types[first_reg_op + 1] = i.types[first_reg_op];
4374 if (i.tm.opcode_modifier.shortform)
4376 if (i.types[0].bitfield.sreg2
4377 || i.types[0].bitfield.sreg3)
4379 if (i.tm.base_opcode == POP_SEG_SHORT
4380 && i.op[0].regs->reg_num == 1)
4382 as_bad (_("you can't `pop %%cs'"));
4385 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4386 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4391 /* The register or float register operand is in operand
4395 if (i.types[0].bitfield.floatreg
4396 || operand_type_check (i.types[0], reg))
4400 /* Register goes in low 3 bits of opcode. */
4401 i.tm.base_opcode |= i.op[op].regs->reg_num;
4402 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4404 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4406 /* Warn about some common errors, but press on regardless.
4407 The first case can be generated by gcc (<= 2.8.1). */
4408 if (i.operands == 2)
4410 /* Reversed arguments on faddp, fsubp, etc. */
4411 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4412 register_prefix, i.op[1].regs->reg_name,
4413 register_prefix, i.op[0].regs->reg_name);
4417 /* Extraneous `l' suffix on fp insn. */
4418 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4419 register_prefix, i.op[0].regs->reg_name);
4424 else if (i.tm.opcode_modifier.modrm)
4426 /* The opcode is completed (modulo i.tm.extension_opcode which
4427 must be put into the modrm byte). Now, we make the modrm and
4428 index base bytes based on all the info we've collected. */
4430 default_seg = build_modrm_byte ();
4432 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4436 else if (i.tm.opcode_modifier.isstring)
4438 /* For the string instructions that allow a segment override
4439 on one of their operands, the default segment is ds. */
4443 if (i.tm.base_opcode == 0x8d /* lea */
4446 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4448 /* If a segment was explicitly specified, and the specified segment
4449 is not the default, use an opcode prefix to select it. If we
4450 never figured out what the default segment is, then default_seg
4451 will be zero at this point, and the specified segment prefix will
4453 if ((i.seg[0]) && (i.seg[0] != default_seg))
4455 if (!add_prefix (i.seg[0]->seg_prefix))
4461 static const seg_entry *
4462 build_modrm_byte (void)
4464 const seg_entry *default_seg = 0;
4466 /* SSE5 4 operand instructions are encoded in such a way that one of
4467 the inputs must match the destination register. Process_drex hides
4468 the 3rd argument in the drex field, so that by the time we get
4469 here, it looks to GAS as if this is a 2 operand instruction. */
4470 if ((i.tm.opcode_modifier.drex
4471 || i.tm.opcode_modifier.drexv
4472 || i.tm.opcode_modifier.drexc)
4473 && i.reg_operands == 2)
4475 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4476 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4478 i.rm.reg = reg->reg_num;
4479 i.rm.regmem = regmem->reg_num;
4481 if ((reg->reg_flags & RegRex) != 0)
4483 if ((regmem->reg_flags & RegRex) != 0)
4487 /* i.reg_operands MUST be the number of real register operands;
4488 implicit registers do not count. */
4489 else if (i.reg_operands == 2)
4491 unsigned int source, dest;
4499 /* When there are 3 operands, one of them may be immediate,
4500 which may be the first or the last operand. Otherwise,
4501 the first operand must be shift count register (cl). */
4502 assert (i.imm_operands == 1
4503 || (i.imm_operands == 0
4504 && i.types[0].bitfield.shiftcount));
4505 if (operand_type_check (i.types[0], imm)
4506 || i.types[0].bitfield.shiftcount)
4512 /* When there are 4 operands, the first two must be 8bit
4513 immediate operands. The source operand will be the 3rd
4515 assert (i.imm_operands == 2
4516 && i.types[0].bitfield.imm8
4517 && i.types[1].bitfield.imm8);
4527 /* One of the register operands will be encoded in the i.tm.reg
4528 field, the other in the combined i.tm.mode and i.tm.regmem
4529 fields. If no form of this instruction supports a memory
4530 destination operand, then we assume the source operand may
4531 sometimes be a memory operand and so we need to store the
4532 destination in the i.rm.reg field. */
4533 if (!i.tm.operand_types[dest].bitfield.regmem
4534 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4536 i.rm.reg = i.op[dest].regs->reg_num;
4537 i.rm.regmem = i.op[source].regs->reg_num;
4538 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4540 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4545 i.rm.reg = i.op[source].regs->reg_num;
4546 i.rm.regmem = i.op[dest].regs->reg_num;
4547 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4549 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4552 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4554 if (!i.types[0].bitfield.control
4555 && !i.types[1].bitfield.control)
4557 i.rex &= ~(REX_R | REX_B);
4558 add_prefix (LOCK_PREFIX_OPCODE);
4562 { /* If it's not 2 reg operands... */
4565 unsigned int fake_zero_displacement = 0;
4568 /* This has been precalculated for SSE5 instructions
4569 that have a DREX field earlier in process_drex. */
4570 if (i.tm.opcode_modifier.drex
4571 || i.tm.opcode_modifier.drexv
4572 || i.tm.opcode_modifier.drexc)
4573 op = i.drex.modrm_regmem;
4576 for (op = 0; op < i.operands; op++)
4577 if (operand_type_check (i.types[op], anymem))
4579 assert (op < i.operands);
4584 if (i.base_reg == 0)
4587 if (!i.disp_operands)
4588 fake_zero_displacement = 1;
4589 if (i.index_reg == 0)
4591 /* Operand is just <disp> */
4592 if (flag_code == CODE_64BIT)
4594 /* 64bit mode overwrites the 32bit absolute
4595 addressing by RIP relative addressing and
4596 absolute addressing is encoded by one of the
4597 redundant SIB forms. */
4598 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4599 i.sib.base = NO_BASE_REGISTER;
4600 i.sib.index = NO_INDEX_REGISTER;
4601 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4602 ? disp32s : disp32);
4604 else if ((flag_code == CODE_16BIT)
4605 ^ (i.prefix[ADDR_PREFIX] != 0))
4607 i.rm.regmem = NO_BASE_REGISTER_16;
4608 i.types[op] = disp16;
4612 i.rm.regmem = NO_BASE_REGISTER;
4613 i.types[op] = disp32;
4616 else /* !i.base_reg && i.index_reg */
4618 if (i.index_reg->reg_num == RegEiz
4619 || i.index_reg->reg_num == RegRiz)
4620 i.sib.index = NO_INDEX_REGISTER;
4622 i.sib.index = i.index_reg->reg_num;
4623 i.sib.base = NO_BASE_REGISTER;
4624 i.sib.scale = i.log2_scale_factor;
4625 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4626 i.types[op].bitfield.disp8 = 0;
4627 i.types[op].bitfield.disp16 = 0;
4628 i.types[op].bitfield.disp64 = 0;
4629 if (flag_code != CODE_64BIT)
4631 /* Must be 32 bit */
4632 i.types[op].bitfield.disp32 = 1;
4633 i.types[op].bitfield.disp32s = 0;
4637 i.types[op].bitfield.disp32 = 0;
4638 i.types[op].bitfield.disp32s = 1;
4640 if ((i.index_reg->reg_flags & RegRex) != 0)
4644 /* RIP addressing for 64bit mode. */
4645 else if (i.base_reg->reg_num == RegRip ||
4646 i.base_reg->reg_num == RegEip)
4648 i.rm.regmem = NO_BASE_REGISTER;
4649 i.types[op].bitfield.disp8 = 0;
4650 i.types[op].bitfield.disp16 = 0;
4651 i.types[op].bitfield.disp32 = 0;
4652 i.types[op].bitfield.disp32s = 1;
4653 i.types[op].bitfield.disp64 = 0;
4654 i.flags[op] |= Operand_PCrel;
4655 if (! i.disp_operands)
4656 fake_zero_displacement = 1;
4658 else if (i.base_reg->reg_type.bitfield.reg16)
4660 switch (i.base_reg->reg_num)
4663 if (i.index_reg == 0)
4665 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4666 i.rm.regmem = i.index_reg->reg_num - 6;
4670 if (i.index_reg == 0)
4673 if (operand_type_check (i.types[op], disp) == 0)
4675 /* fake (%bp) into 0(%bp) */
4676 i.types[op].bitfield.disp8 = 1;
4677 fake_zero_displacement = 1;
4680 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4681 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4683 default: /* (%si) -> 4 or (%di) -> 5 */
4684 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4686 i.rm.mode = mode_from_disp_size (i.types[op]);
4688 else /* i.base_reg and 32/64 bit mode */
4690 if (flag_code == CODE_64BIT
4691 && operand_type_check (i.types[op], disp))
4693 i386_operand_type temp;
4695 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4697 if (i.prefix[ADDR_PREFIX] == 0)
4698 i.types[op].bitfield.disp32s = 1;
4700 i.types[op].bitfield.disp32 = 1;
4703 i.rm.regmem = i.base_reg->reg_num;
4704 if ((i.base_reg->reg_flags & RegRex) != 0)
4706 i.sib.base = i.base_reg->reg_num;
4707 /* x86-64 ignores REX prefix bit here to avoid decoder
4709 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4712 if (i.disp_operands == 0)
4714 fake_zero_displacement = 1;
4715 i.types[op].bitfield.disp8 = 1;
4718 else if (i.base_reg->reg_num == ESP_REG_NUM)
4722 i.sib.scale = i.log2_scale_factor;
4723 if (i.index_reg == 0)
4725 /* <disp>(%esp) becomes two byte modrm with no index
4726 register. We've already stored the code for esp
4727 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4728 Any base register besides %esp will not use the
4729 extra modrm byte. */
4730 i.sib.index = NO_INDEX_REGISTER;
4734 if (i.index_reg->reg_num == RegEiz
4735 || i.index_reg->reg_num == RegRiz)
4736 i.sib.index = NO_INDEX_REGISTER;
4738 i.sib.index = i.index_reg->reg_num;
4739 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4740 if ((i.index_reg->reg_flags & RegRex) != 0)
4745 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4746 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4749 i.rm.mode = mode_from_disp_size (i.types[op]);
4752 if (fake_zero_displacement)
4754 /* Fakes a zero displacement assuming that i.types[op]
4755 holds the correct displacement size. */
4758 assert (i.op[op].disps == 0);
4759 exp = &disp_expressions[i.disp_operands++];
4760 i.op[op].disps = exp;
4761 exp->X_op = O_constant;
4762 exp->X_add_number = 0;
4763 exp->X_add_symbol = (symbolS *) 0;
4764 exp->X_op_symbol = (symbolS *) 0;
4768 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4769 (if any) based on i.tm.extension_opcode. Again, we must be
4770 careful to make sure that segment/control/debug/test/MMX
4771 registers are coded into the i.rm.reg field. */
4776 /* This has been precalculated for SSE5 instructions
4777 that have a DREX field earlier in process_drex. */
4778 if (i.tm.opcode_modifier.drex
4779 || i.tm.opcode_modifier.drexv
4780 || i.tm.opcode_modifier.drexc)
4782 op = i.drex.modrm_reg;
4783 i.rm.reg = i.op[op].regs->reg_num;
4784 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4789 for (op = 0; op < i.operands; op++)
4790 if (i.types[op].bitfield.reg8
4791 || i.types[op].bitfield.reg16
4792 || i.types[op].bitfield.reg32
4793 || i.types[op].bitfield.reg64
4794 || i.types[op].bitfield.regmmx
4795 || i.types[op].bitfield.regxmm
4796 || i.types[op].bitfield.sreg2
4797 || i.types[op].bitfield.sreg3
4798 || i.types[op].bitfield.control
4799 || i.types[op].bitfield.debug
4800 || i.types[op].bitfield.test)
4803 assert (op < i.operands);
4805 /* If there is an extension opcode to put here, the
4806 register number must be put into the regmem field. */
4807 if (i.tm.extension_opcode != None)
4809 i.rm.regmem = i.op[op].regs->reg_num;
4810 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4815 i.rm.reg = i.op[op].regs->reg_num;
4816 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4821 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4822 must set it to 3 to indicate this is a register operand
4823 in the regmem field. */
4824 if (!i.mem_operands)
4828 /* Fill in i.rm.reg field with extension opcode (if any). */
4829 if (i.tm.extension_opcode != None
4830 && !(i.tm.opcode_modifier.drex
4831 || i.tm.opcode_modifier.drexv
4832 || i.tm.opcode_modifier.drexc))
4833 i.rm.reg = i.tm.extension_opcode;
4839 output_branch (void)
4844 relax_substateT subtype;
4849 if (flag_code == CODE_16BIT)
4853 if (i.prefix[DATA_PREFIX] != 0)
4859 /* Pentium4 branch hints. */
4860 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4861 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4866 if (i.prefix[REX_PREFIX] != 0)
4872 if (i.prefixes != 0 && !intel_syntax)
4873 as_warn (_("skipping prefixes on this instruction"));
4875 /* It's always a symbol; End frag & setup for relax.
4876 Make sure there is enough room in this frag for the largest
4877 instruction we may generate in md_convert_frag. This is 2
4878 bytes for the opcode and room for the prefix and largest
4880 frag_grow (prefix + 2 + 4);
4881 /* Prefix and 1 opcode byte go in fr_fix. */
4882 p = frag_more (prefix + 1);
4883 if (i.prefix[DATA_PREFIX] != 0)
4884 *p++ = DATA_PREFIX_OPCODE;
4885 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4886 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4887 *p++ = i.prefix[SEG_PREFIX];
4888 if (i.prefix[REX_PREFIX] != 0)
4889 *p++ = i.prefix[REX_PREFIX];
4890 *p = i.tm.base_opcode;
4892 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4893 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4894 else if (cpu_arch_flags.bitfield.cpui386)
4895 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4897 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4900 sym = i.op[0].disps->X_add_symbol;
4901 off = i.op[0].disps->X_add_number;
4903 if (i.op[0].disps->X_op != O_constant
4904 && i.op[0].disps->X_op != O_symbol)
4906 /* Handle complex expressions. */
4907 sym = make_expr_symbol (i.op[0].disps);
4911 /* 1 possible extra opcode + 4 byte displacement go in var part.
4912 Pass reloc in fr_var. */
4913 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4923 if (i.tm.opcode_modifier.jumpbyte)
4925 /* This is a loop or jecxz type instruction. */
4927 if (i.prefix[ADDR_PREFIX] != 0)
4929 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4932 /* Pentium4 branch hints. */
4933 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4934 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4936 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4945 if (flag_code == CODE_16BIT)
4948 if (i.prefix[DATA_PREFIX] != 0)
4950 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4960 if (i.prefix[REX_PREFIX] != 0)
4962 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4966 if (i.prefixes != 0 && !intel_syntax)
4967 as_warn (_("skipping prefixes on this instruction"));
4969 p = frag_more (1 + size);
4970 *p++ = i.tm.base_opcode;
4972 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4973 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4975 /* All jumps handled here are signed, but don't use a signed limit
4976 check for 32 and 16 bit jumps as we want to allow wrap around at
4977 4G and 64k respectively. */
4979 fixP->fx_signed = 1;
4983 output_interseg_jump (void)
4991 if (flag_code == CODE_16BIT)
4995 if (i.prefix[DATA_PREFIX] != 0)
5001 if (i.prefix[REX_PREFIX] != 0)
5011 if (i.prefixes != 0 && !intel_syntax)
5012 as_warn (_("skipping prefixes on this instruction"));
5014 /* 1 opcode; 2 segment; offset */
5015 p = frag_more (prefix + 1 + 2 + size);
5017 if (i.prefix[DATA_PREFIX] != 0)
5018 *p++ = DATA_PREFIX_OPCODE;
5020 if (i.prefix[REX_PREFIX] != 0)
5021 *p++ = i.prefix[REX_PREFIX];
5023 *p++ = i.tm.base_opcode;
5024 if (i.op[1].imms->X_op == O_constant)
5026 offsetT n = i.op[1].imms->X_add_number;
5029 && !fits_in_unsigned_word (n)
5030 && !fits_in_signed_word (n))
5032 as_bad (_("16-bit jump out of range"));
5035 md_number_to_chars (p, n, size);
5038 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5039 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5040 if (i.op[0].imms->X_op != O_constant)
5041 as_bad (_("can't handle non absolute segment in `%s'"),
5043 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5049 fragS *insn_start_frag;
5050 offsetT insn_start_off;
5052 /* Tie dwarf2 debug info to the address at the start of the insn.
5053 We can't do this after the insn has been output as the current
5054 frag may have been closed off. eg. by frag_var. */
5055 dwarf2_emit_insn (0);
5057 insn_start_frag = frag_now;
5058 insn_start_off = frag_now_fix ();
5061 if (i.tm.opcode_modifier.jump)
5063 else if (i.tm.opcode_modifier.jumpbyte
5064 || i.tm.opcode_modifier.jumpdword)
5066 else if (i.tm.opcode_modifier.jumpintersegment)
5067 output_interseg_jump ();
5070 /* Output normal instructions here. */
5074 unsigned int prefix;
5076 switch (i.tm.opcode_length)
5079 if (i.tm.base_opcode & 0xff000000)
5081 prefix = (i.tm.base_opcode >> 24) & 0xff;
5086 if ((i.tm.base_opcode & 0xff0000) != 0)
5088 prefix = (i.tm.base_opcode >> 16) & 0xff;
5089 if (i.tm.cpu_flags.bitfield.cpupadlock)
5092 if (prefix != REPE_PREFIX_OPCODE
5093 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5094 add_prefix (prefix);
5097 add_prefix (prefix);
5106 /* The prefix bytes. */
5107 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5109 FRAG_APPEND_1_CHAR (*q);
5111 /* Now the opcode; be careful about word order here! */
5112 if (i.tm.opcode_length == 1)
5114 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5118 switch (i.tm.opcode_length)
5122 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5132 /* Put out high byte first: can't use md_number_to_chars! */
5133 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5134 *p = i.tm.base_opcode & 0xff;
5136 /* On SSE5, encode the OC1 bit in the DREX field if this
5137 encoding has multiple formats. */
5138 if (i.tm.opcode_modifier.drex
5139 && i.tm.opcode_modifier.drexv
5140 && DREX_OC1 (i.tm.extension_opcode))
5141 *p |= DREX_OC1_MASK;
5144 /* Now the modrm byte and sib byte (if present). */
5145 if (i.tm.opcode_modifier.modrm)
5147 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5150 /* If i.rm.regmem == ESP (4)
5151 && i.rm.mode != (Register mode)
5153 ==> need second modrm byte. */
5154 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5156 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5157 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5159 | i.sib.scale << 6));
5162 /* Write the DREX byte if needed. */
5163 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5166 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5168 /* Encode the OC0 bit if this encoding has multiple
5170 if ((i.tm.opcode_modifier.drex
5171 || i.tm.opcode_modifier.drexv)
5172 && DREX_OC0 (i.tm.extension_opcode))
5173 *p |= DREX_OC0_MASK;
5176 if (i.disp_operands)
5177 output_disp (insn_start_frag, insn_start_off);
5180 output_imm (insn_start_frag, insn_start_off);
5186 pi ("" /*line*/, &i);
5188 #endif /* DEBUG386 */
5191 /* Return the size of the displacement operand N. */
5194 disp_size (unsigned int n)
5197 if (i.types[n].bitfield.disp64)
5199 else if (i.types[n].bitfield.disp8)
5201 else if (i.types[n].bitfield.disp16)
5206 /* Return the size of the immediate operand N. */
5209 imm_size (unsigned int n)
5212 if (i.types[n].bitfield.imm64)
5214 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5216 else if (i.types[n].bitfield.imm16)
5222 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5227 for (n = 0; n < i.operands; n++)
5229 if (operand_type_check (i.types[n], disp))
5231 if (i.op[n].disps->X_op == O_constant)
5233 int size = disp_size (n);
5236 val = offset_in_range (i.op[n].disps->X_add_number,
5238 p = frag_more (size);
5239 md_number_to_chars (p, val, size);
5243 enum bfd_reloc_code_real reloc_type;
5244 int size = disp_size (n);
5245 int sign = i.types[n].bitfield.disp32s;
5246 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5248 /* We can't have 8 bit displacement here. */
5249 assert (!i.types[n].bitfield.disp8);
5251 /* The PC relative address is computed relative
5252 to the instruction boundary, so in case immediate
5253 fields follows, we need to adjust the value. */
5254 if (pcrel && i.imm_operands)
5259 for (n1 = 0; n1 < i.operands; n1++)
5260 if (operand_type_check (i.types[n1], imm))
5262 /* Only one immediate is allowed for PC
5263 relative address. */
5266 i.op[n].disps->X_add_number -= sz;
5268 /* We should find the immediate. */
5272 p = frag_more (size);
5273 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5275 && GOT_symbol == i.op[n].disps->X_add_symbol
5276 && (((reloc_type == BFD_RELOC_32
5277 || reloc_type == BFD_RELOC_X86_64_32S
5278 || (reloc_type == BFD_RELOC_64
5280 && (i.op[n].disps->X_op == O_symbol
5281 || (i.op[n].disps->X_op == O_add
5282 && ((symbol_get_value_expression
5283 (i.op[n].disps->X_op_symbol)->X_op)
5285 || reloc_type == BFD_RELOC_32_PCREL))
5289 if (insn_start_frag == frag_now)
5290 add = (p - frag_now->fr_literal) - insn_start_off;
5295 add = insn_start_frag->fr_fix - insn_start_off;
5296 for (fr = insn_start_frag->fr_next;
5297 fr && fr != frag_now; fr = fr->fr_next)
5299 add += p - frag_now->fr_literal;
5304 reloc_type = BFD_RELOC_386_GOTPC;
5305 i.op[n].imms->X_add_number += add;
5307 else if (reloc_type == BFD_RELOC_64)
5308 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5310 /* Don't do the adjustment for x86-64, as there
5311 the pcrel addressing is relative to the _next_
5312 insn, and that is taken care of in other code. */
5313 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5315 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5316 i.op[n].disps, pcrel, reloc_type);
5323 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5328 for (n = 0; n < i.operands; n++)
5330 if (operand_type_check (i.types[n], imm))
5332 if (i.op[n].imms->X_op == O_constant)
5334 int size = imm_size (n);
5337 val = offset_in_range (i.op[n].imms->X_add_number,
5339 p = frag_more (size);
5340 md_number_to_chars (p, val, size);
5344 /* Not absolute_section.
5345 Need a 32-bit fixup (don't support 8bit
5346 non-absolute imms). Try to support other
5348 enum bfd_reloc_code_real reloc_type;
5349 int size = imm_size (n);
5352 if (i.types[n].bitfield.imm32s
5353 && (i.suffix == QWORD_MNEM_SUFFIX
5354 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5359 p = frag_more (size);
5360 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5362 /* This is tough to explain. We end up with this one if we
5363 * have operands that look like
5364 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5365 * obtain the absolute address of the GOT, and it is strongly
5366 * preferable from a performance point of view to avoid using
5367 * a runtime relocation for this. The actual sequence of
5368 * instructions often look something like:
5373 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5375 * The call and pop essentially return the absolute address
5376 * of the label .L66 and store it in %ebx. The linker itself
5377 * will ultimately change the first operand of the addl so
5378 * that %ebx points to the GOT, but to keep things simple, the
5379 * .o file must have this operand set so that it generates not
5380 * the absolute address of .L66, but the absolute address of
5381 * itself. This allows the linker itself simply treat a GOTPC
5382 * relocation as asking for a pcrel offset to the GOT to be
5383 * added in, and the addend of the relocation is stored in the
5384 * operand field for the instruction itself.
5386 * Our job here is to fix the operand so that it would add
5387 * the correct offset so that %ebx would point to itself. The
5388 * thing that is tricky is that .-.L66 will point to the
5389 * beginning of the instruction, so we need to further modify
5390 * the operand so that it will point to itself. There are
5391 * other cases where you have something like:
5393 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5395 * and here no correction would be required. Internally in
5396 * the assembler we treat operands of this form as not being
5397 * pcrel since the '.' is explicitly mentioned, and I wonder
5398 * whether it would simplify matters to do it this way. Who
5399 * knows. In earlier versions of the PIC patches, the
5400 * pcrel_adjust field was used to store the correction, but
5401 * since the expression is not pcrel, I felt it would be
5402 * confusing to do it this way. */
5404 if ((reloc_type == BFD_RELOC_32
5405 || reloc_type == BFD_RELOC_X86_64_32S
5406 || reloc_type == BFD_RELOC_64)
5408 && GOT_symbol == i.op[n].imms->X_add_symbol
5409 && (i.op[n].imms->X_op == O_symbol
5410 || (i.op[n].imms->X_op == O_add
5411 && ((symbol_get_value_expression
5412 (i.op[n].imms->X_op_symbol)->X_op)
5417 if (insn_start_frag == frag_now)
5418 add = (p - frag_now->fr_literal) - insn_start_off;
5423 add = insn_start_frag->fr_fix - insn_start_off;
5424 for (fr = insn_start_frag->fr_next;
5425 fr && fr != frag_now; fr = fr->fr_next)
5427 add += p - frag_now->fr_literal;
5431 reloc_type = BFD_RELOC_386_GOTPC;
5433 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5435 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5436 i.op[n].imms->X_add_number += add;
5438 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5439 i.op[n].imms, 0, reloc_type);
5445 /* x86_cons_fix_new is called via the expression parsing code when a
5446 reloc is needed. We use this hook to get the correct .got reloc. */
5447 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5448 static int cons_sign = -1;
5451 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5454 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5456 got_reloc = NO_RELOC;
5459 if (exp->X_op == O_secrel)
5461 exp->X_op = O_symbol;
5462 r = BFD_RELOC_32_SECREL;
5466 fix_new_exp (frag, off, len, exp, 0, r);
5469 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5470 # define lex_got(reloc, adjust, types) NULL
5472 /* Parse operands of the form
5473 <symbol>@GOTOFF+<nnn>
5474 and similar .plt or .got references.
5476 If we find one, set up the correct relocation in RELOC and copy the
5477 input string, minus the `@GOTOFF' into a malloc'd buffer for
5478 parsing by the calling routine. Return this buffer, and if ADJUST
5479 is non-null set it to the length of the string we removed from the
5480 input line. Otherwise return NULL. */
5482 lex_got (enum bfd_reloc_code_real *reloc,
5484 i386_operand_type *types)
5486 /* Some of the relocations depend on the size of what field is to
5487 be relocated. But in our callers i386_immediate and i386_displacement
5488 we don't yet know the operand size (this will be set by insn
5489 matching). Hence we record the word32 relocation here,
5490 and adjust the reloc according to the real size in reloc(). */
5491 static const struct {
5493 const enum bfd_reloc_code_real rel[2];
5494 const i386_operand_type types64;
5497 BFD_RELOC_X86_64_PLTOFF64 },
5498 OPERAND_TYPE_IMM64 },
5499 { "PLT", { BFD_RELOC_386_PLT32,
5500 BFD_RELOC_X86_64_PLT32 },
5501 OPERAND_TYPE_IMM32_32S_DISP32 },
5503 BFD_RELOC_X86_64_GOTPLT64 },
5504 OPERAND_TYPE_IMM64_DISP64 },
5505 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5506 BFD_RELOC_X86_64_GOTOFF64 },
5507 OPERAND_TYPE_IMM64_DISP64 },
5509 BFD_RELOC_X86_64_GOTPCREL },
5510 OPERAND_TYPE_IMM32_32S_DISP32 },
5511 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5512 BFD_RELOC_X86_64_TLSGD },
5513 OPERAND_TYPE_IMM32_32S_DISP32 },
5514 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5516 OPERAND_TYPE_NONE },
5518 BFD_RELOC_X86_64_TLSLD },
5519 OPERAND_TYPE_IMM32_32S_DISP32 },
5520 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5521 BFD_RELOC_X86_64_GOTTPOFF },
5522 OPERAND_TYPE_IMM32_32S_DISP32 },
5523 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5524 BFD_RELOC_X86_64_TPOFF32 },
5525 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5526 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5528 OPERAND_TYPE_NONE },
5529 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5530 BFD_RELOC_X86_64_DTPOFF32 },
5532 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5533 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5535 OPERAND_TYPE_NONE },
5536 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5538 OPERAND_TYPE_NONE },
5539 { "GOT", { BFD_RELOC_386_GOT32,
5540 BFD_RELOC_X86_64_GOT32 },
5541 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5542 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5543 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5544 OPERAND_TYPE_IMM32_32S_DISP32 },
5545 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5546 BFD_RELOC_X86_64_TLSDESC_CALL },
5547 OPERAND_TYPE_IMM32_32S_DISP32 },
5555 for (cp = input_line_pointer; *cp != '@'; cp++)
5556 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5559 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5563 len = strlen (gotrel[j].str);
5564 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5566 if (gotrel[j].rel[object_64bit] != 0)
5569 char *tmpbuf, *past_reloc;
5571 *reloc = gotrel[j].rel[object_64bit];
5577 if (flag_code != CODE_64BIT)
5579 types->bitfield.imm32 = 1;
5580 types->bitfield.disp32 = 1;
5583 *types = gotrel[j].types64;
5586 if (GOT_symbol == NULL)
5587 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5589 /* The length of the first part of our input line. */
5590 first = cp - input_line_pointer;
5592 /* The second part goes from after the reloc token until
5593 (and including) an end_of_line char or comma. */
5594 past_reloc = cp + 1 + len;
5596 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5598 second = cp + 1 - past_reloc;
5600 /* Allocate and copy string. The trailing NUL shouldn't
5601 be necessary, but be safe. */
5602 tmpbuf = xmalloc (first + second + 2);
5603 memcpy (tmpbuf, input_line_pointer, first);
5604 if (second != 0 && *past_reloc != ' ')
5605 /* Replace the relocation token with ' ', so that
5606 errors like foo@GOTOFF1 will be detected. */
5607 tmpbuf[first++] = ' ';
5608 memcpy (tmpbuf + first, past_reloc, second);
5609 tmpbuf[first + second] = '\0';
5613 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5614 gotrel[j].str, 1 << (5 + object_64bit));
5619 /* Might be a symbol version string. Don't as_bad here. */
5624 x86_cons (expressionS *exp, int size)
5626 if (size == 4 || (object_64bit && size == 8))
5628 /* Handle @GOTOFF and the like in an expression. */
5630 char *gotfree_input_line;
5633 save = input_line_pointer;
5634 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5635 if (gotfree_input_line)
5636 input_line_pointer = gotfree_input_line;
5640 if (gotfree_input_line)
5642 /* expression () has merrily parsed up to the end of line,
5643 or a comma - in the wrong buffer. Transfer how far
5644 input_line_pointer has moved to the right buffer. */
5645 input_line_pointer = (save
5646 + (input_line_pointer - gotfree_input_line)
5648 free (gotfree_input_line);
5649 if (exp->X_op == O_constant
5650 || exp->X_op == O_absent
5651 || exp->X_op == O_illegal
5652 || exp->X_op == O_register
5653 || exp->X_op == O_big)
5655 char c = *input_line_pointer;
5656 *input_line_pointer = 0;
5657 as_bad (_("missing or invalid expression `%s'"), save);
5658 *input_line_pointer = c;
5667 static void signed_cons (int size)
5669 if (flag_code == CODE_64BIT)
5677 pe_directive_secrel (dummy)
5678 int dummy ATTRIBUTE_UNUSED;
5685 if (exp.X_op == O_symbol)
5686 exp.X_op = O_secrel;
5688 emit_expr (&exp, 4);
5690 while (*input_line_pointer++ == ',');
5692 input_line_pointer--;
5693 demand_empty_rest_of_line ();
5698 i386_immediate (char *imm_start)
5700 char *save_input_line_pointer;
5701 char *gotfree_input_line;
5704 i386_operand_type types;
5706 UINTS_SET (types, ~0);
5708 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5710 as_bad (_("at most %d immediate operands are allowed"),
5711 MAX_IMMEDIATE_OPERANDS);
5715 exp = &im_expressions[i.imm_operands++];
5716 i.op[this_operand].imms = exp;
5718 if (is_space_char (*imm_start))
5721 save_input_line_pointer = input_line_pointer;
5722 input_line_pointer = imm_start;
5724 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5725 if (gotfree_input_line)
5726 input_line_pointer = gotfree_input_line;
5728 exp_seg = expression (exp);
5731 if (*input_line_pointer)
5732 as_bad (_("junk `%s' after expression"), input_line_pointer);
5734 input_line_pointer = save_input_line_pointer;
5735 if (gotfree_input_line)
5736 free (gotfree_input_line);
5738 if (exp->X_op == O_absent
5739 || exp->X_op == O_illegal
5740 || exp->X_op == O_big
5741 || (gotfree_input_line
5742 && (exp->X_op == O_constant
5743 || exp->X_op == O_register)))
5745 as_bad (_("missing or invalid immediate expression `%s'"),
5749 else if (exp->X_op == O_constant)
5751 /* Size it properly later. */
5752 i.types[this_operand].bitfield.imm64 = 1;
5753 /* If BFD64, sign extend val. */
5754 if (!use_rela_relocations
5755 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5757 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5759 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5760 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5761 && exp_seg != absolute_section
5762 && exp_seg != text_section
5763 && exp_seg != data_section
5764 && exp_seg != bss_section
5765 && exp_seg != undefined_section
5766 && !bfd_is_com_section (exp_seg))
5768 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5772 else if (!intel_syntax && exp->X_op == O_register)
5774 as_bad (_("illegal immediate register operand %s"), imm_start);
5779 /* This is an address. The size of the address will be
5780 determined later, depending on destination register,
5781 suffix, or the default for the section. */
5782 i.types[this_operand].bitfield.imm8 = 1;
5783 i.types[this_operand].bitfield.imm16 = 1;
5784 i.types[this_operand].bitfield.imm32 = 1;
5785 i.types[this_operand].bitfield.imm32s = 1;
5786 i.types[this_operand].bitfield.imm64 = 1;
5787 i.types[this_operand] = operand_type_and (i.types[this_operand],
5795 i386_scale (char *scale)
5798 char *save = input_line_pointer;
5800 input_line_pointer = scale;
5801 val = get_absolute_expression ();
5806 i.log2_scale_factor = 0;
5809 i.log2_scale_factor = 1;
5812 i.log2_scale_factor = 2;
5815 i.log2_scale_factor = 3;
5819 char sep = *input_line_pointer;
5821 *input_line_pointer = '\0';
5822 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5824 *input_line_pointer = sep;
5825 input_line_pointer = save;
5829 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5831 as_warn (_("scale factor of %d without an index register"),
5832 1 << i.log2_scale_factor);
5833 i.log2_scale_factor = 0;
5835 scale = input_line_pointer;
5836 input_line_pointer = save;
5841 i386_displacement (char *disp_start, char *disp_end)
5845 char *save_input_line_pointer;
5846 char *gotfree_input_line;
5848 i386_operand_type bigdisp, types = anydisp;
5851 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5853 as_bad (_("at most %d displacement operands are allowed"),
5854 MAX_MEMORY_OPERANDS);
5858 UINTS_CLEAR (bigdisp);
5859 if ((i.types[this_operand].bitfield.jumpabsolute)
5860 || (!current_templates->start->opcode_modifier.jump
5861 && !current_templates->start->opcode_modifier.jumpdword))
5863 bigdisp.bitfield.disp32 = 1;
5864 override = (i.prefix[ADDR_PREFIX] != 0);
5865 if (flag_code == CODE_64BIT)
5869 bigdisp.bitfield.disp32s = 1;
5870 bigdisp.bitfield.disp64 = 1;
5873 else if ((flag_code == CODE_16BIT) ^ override)
5875 bigdisp.bitfield.disp32 = 0;
5876 bigdisp.bitfield.disp16 = 1;
5881 /* For PC-relative branches, the width of the displacement
5882 is dependent upon data size, not address size. */
5883 override = (i.prefix[DATA_PREFIX] != 0);
5884 if (flag_code == CODE_64BIT)
5886 if (override || i.suffix == WORD_MNEM_SUFFIX)
5887 bigdisp.bitfield.disp16 = 1;
5890 bigdisp.bitfield.disp32 = 1;
5891 bigdisp.bitfield.disp32s = 1;
5897 override = (i.suffix == (flag_code != CODE_16BIT
5899 : LONG_MNEM_SUFFIX));
5900 bigdisp.bitfield.disp32 = 1;
5901 if ((flag_code == CODE_16BIT) ^ override)
5903 bigdisp.bitfield.disp32 = 0;
5904 bigdisp.bitfield.disp16 = 1;
5908 i.types[this_operand] = operand_type_or (i.types[this_operand],
5911 exp = &disp_expressions[i.disp_operands];
5912 i.op[this_operand].disps = exp;
5914 save_input_line_pointer = input_line_pointer;
5915 input_line_pointer = disp_start;
5916 END_STRING_AND_SAVE (disp_end);
5918 #ifndef GCC_ASM_O_HACK
5919 #define GCC_ASM_O_HACK 0
5922 END_STRING_AND_SAVE (disp_end + 1);
5923 if (i.types[this_operand].bitfield.baseIndex
5924 && displacement_string_end[-1] == '+')
5926 /* This hack is to avoid a warning when using the "o"
5927 constraint within gcc asm statements.
5930 #define _set_tssldt_desc(n,addr,limit,type) \
5931 __asm__ __volatile__ ( \
5933 "movw %w1,2+%0\n\t" \
5935 "movb %b1,4+%0\n\t" \
5936 "movb %4,5+%0\n\t" \
5937 "movb $0,6+%0\n\t" \
5938 "movb %h1,7+%0\n\t" \
5940 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5942 This works great except that the output assembler ends
5943 up looking a bit weird if it turns out that there is
5944 no offset. You end up producing code that looks like:
5957 So here we provide the missing zero. */
5959 *displacement_string_end = '0';
5962 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5963 if (gotfree_input_line)
5964 input_line_pointer = gotfree_input_line;
5966 exp_seg = expression (exp);
5969 if (*input_line_pointer)
5970 as_bad (_("junk `%s' after expression"), input_line_pointer);
5972 RESTORE_END_STRING (disp_end + 1);
5974 input_line_pointer = save_input_line_pointer;
5975 if (gotfree_input_line)
5976 free (gotfree_input_line);
5979 /* We do this to make sure that the section symbol is in
5980 the symbol table. We will ultimately change the relocation
5981 to be relative to the beginning of the section. */
5982 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5983 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5984 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5986 if (exp->X_op != O_symbol)
5989 if (S_IS_LOCAL (exp->X_add_symbol)
5990 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5991 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5992 exp->X_op = O_subtract;
5993 exp->X_op_symbol = GOT_symbol;
5994 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5995 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5996 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5997 i.reloc[this_operand] = BFD_RELOC_64;
5999 i.reloc[this_operand] = BFD_RELOC_32;
6002 else if (exp->X_op == O_absent
6003 || exp->X_op == O_illegal
6004 || exp->X_op == O_big
6005 || (gotfree_input_line
6006 && (exp->X_op == O_constant
6007 || exp->X_op == O_register)))
6010 as_bad (_("missing or invalid displacement expression `%s'"),
6015 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6016 else if (exp->X_op != O_constant
6017 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6018 && exp_seg != absolute_section
6019 && exp_seg != text_section
6020 && exp_seg != data_section
6021 && exp_seg != bss_section
6022 && exp_seg != undefined_section
6023 && !bfd_is_com_section (exp_seg))
6025 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6030 RESTORE_END_STRING (disp_end);
6032 /* Check if this is a displacement only operand. */
6033 bigdisp = i.types[this_operand];
6034 bigdisp.bitfield.disp8 = 0;
6035 bigdisp.bitfield.disp16 = 0;
6036 bigdisp.bitfield.disp32 = 0;
6037 bigdisp.bitfield.disp32s = 0;
6038 bigdisp.bitfield.disp64 = 0;
6039 if (UINTS_ALL_ZERO (bigdisp))
6040 i.types[this_operand] = operand_type_and (i.types[this_operand],
6046 /* Make sure the memory operand we've been dealt is valid.
6047 Return 1 on success, 0 on a failure. */
6050 i386_index_check (const char *operand_string)
6053 #if INFER_ADDR_PREFIX
6059 if (flag_code == CODE_64BIT)
6062 && ((i.prefix[ADDR_PREFIX] == 0
6063 && !i.base_reg->reg_type.bitfield.reg64)
6064 || (i.prefix[ADDR_PREFIX]
6065 && !i.base_reg->reg_type.bitfield.reg32))
6067 || i.base_reg->reg_num !=
6068 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6070 && (!i.index_reg->reg_type.bitfield.baseindex
6071 || (i.prefix[ADDR_PREFIX] == 0
6072 && i.index_reg->reg_num != RegRiz
6073 && !i.index_reg->reg_type.bitfield.reg64
6075 || (i.prefix[ADDR_PREFIX]
6076 && i.index_reg->reg_num != RegEiz
6077 && !i.index_reg->reg_type.bitfield.reg32))))
6082 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6086 && (!i.base_reg->reg_type.bitfield.reg16
6087 || !i.base_reg->reg_type.bitfield.baseindex))
6089 && (!i.index_reg->reg_type.bitfield.reg16
6090 || !i.index_reg->reg_type.bitfield.baseindex
6092 && i.base_reg->reg_num < 6
6093 && i.index_reg->reg_num >= 6
6094 && i.log2_scale_factor == 0))))
6101 && !i.base_reg->reg_type.bitfield.reg32)
6103 && ((!i.index_reg->reg_type.bitfield.reg32
6104 && i.index_reg->reg_num != RegEiz)
6105 || !i.index_reg->reg_type.bitfield.baseindex)))
6111 #if INFER_ADDR_PREFIX
6112 if (i.prefix[ADDR_PREFIX] == 0)
6114 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6116 /* Change the size of any displacement too. At most one of
6117 Disp16 or Disp32 is set.
6118 FIXME. There doesn't seem to be any real need for separate
6119 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6120 Removing them would probably clean up the code quite a lot. */
6121 if (flag_code != CODE_64BIT
6122 && (i.types[this_operand].bitfield.disp16
6123 || i.types[this_operand].bitfield.disp32))
6124 i.types[this_operand]
6125 = operand_type_xor (i.types[this_operand], disp16_32);
6130 as_bad (_("`%s' is not a valid base/index expression"),
6134 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6136 flag_code_names[flag_code]);
6141 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6145 i386_att_operand (char *operand_string)
6149 char *op_string = operand_string;
6151 if (is_space_char (*op_string))
6154 /* We check for an absolute prefix (differentiating,
6155 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6156 if (*op_string == ABSOLUTE_PREFIX)
6159 if (is_space_char (*op_string))
6161 i.types[this_operand].bitfield.jumpabsolute = 1;
6164 /* Check if operand is a register. */
6165 if ((r = parse_register (op_string, &end_op)) != NULL)
6167 i386_operand_type temp;
6169 /* Check for a segment override by searching for ':' after a
6170 segment register. */
6172 if (is_space_char (*op_string))
6174 if (*op_string == ':'
6175 && (r->reg_type.bitfield.sreg2
6176 || r->reg_type.bitfield.sreg3))
6181 i.seg[i.mem_operands] = &es;
6184 i.seg[i.mem_operands] = &cs;
6187 i.seg[i.mem_operands] = &ss;
6190 i.seg[i.mem_operands] = &ds;
6193 i.seg[i.mem_operands] = &fs;
6196 i.seg[i.mem_operands] = &gs;
6200 /* Skip the ':' and whitespace. */
6202 if (is_space_char (*op_string))
6205 if (!is_digit_char (*op_string)
6206 && !is_identifier_char (*op_string)
6207 && *op_string != '('
6208 && *op_string != ABSOLUTE_PREFIX)
6210 as_bad (_("bad memory operand `%s'"), op_string);
6213 /* Handle case of %es:*foo. */
6214 if (*op_string == ABSOLUTE_PREFIX)
6217 if (is_space_char (*op_string))
6219 i.types[this_operand].bitfield.jumpabsolute = 1;
6221 goto do_memory_reference;
6225 as_bad (_("junk `%s' after register"), op_string);
6229 temp.bitfield.baseindex = 0;
6230 i.types[this_operand] = operand_type_or (i.types[this_operand],
6232 i.types[this_operand].bitfield.unspecified = 0;
6233 i.op[this_operand].regs = r;
6236 else if (*op_string == REGISTER_PREFIX)
6238 as_bad (_("bad register name `%s'"), op_string);
6241 else if (*op_string == IMMEDIATE_PREFIX)
6244 if (i.types[this_operand].bitfield.jumpabsolute)
6246 as_bad (_("immediate operand illegal with absolute jump"));
6249 if (!i386_immediate (op_string))
6252 else if (is_digit_char (*op_string)
6253 || is_identifier_char (*op_string)
6254 || *op_string == '(')
6256 /* This is a memory reference of some sort. */
6259 /* Start and end of displacement string expression (if found). */
6260 char *displacement_string_start;
6261 char *displacement_string_end;
6263 do_memory_reference:
6264 if ((i.mem_operands == 1
6265 && !current_templates->start->opcode_modifier.isstring)
6266 || i.mem_operands == 2)
6268 as_bad (_("too many memory references for `%s'"),
6269 current_templates->start->name);
6273 /* Check for base index form. We detect the base index form by
6274 looking for an ')' at the end of the operand, searching
6275 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6277 base_string = op_string + strlen (op_string);
6280 if (is_space_char (*base_string))
6283 /* If we only have a displacement, set-up for it to be parsed later. */
6284 displacement_string_start = op_string;
6285 displacement_string_end = base_string + 1;
6287 if (*base_string == ')')
6290 unsigned int parens_balanced = 1;
6291 /* We've already checked that the number of left & right ()'s are
6292 equal, so this loop will not be infinite. */
6296 if (*base_string == ')')
6298 if (*base_string == '(')
6301 while (parens_balanced);
6303 temp_string = base_string;
6305 /* Skip past '(' and whitespace. */
6307 if (is_space_char (*base_string))
6310 if (*base_string == ','
6311 || ((i.base_reg = parse_register (base_string, &end_op))
6314 displacement_string_end = temp_string;
6316 i.types[this_operand].bitfield.baseindex = 1;
6320 base_string = end_op;
6321 if (is_space_char (*base_string))
6325 /* There may be an index reg or scale factor here. */
6326 if (*base_string == ',')
6329 if (is_space_char (*base_string))
6332 if ((i.index_reg = parse_register (base_string, &end_op))
6335 base_string = end_op;
6336 if (is_space_char (*base_string))
6338 if (*base_string == ',')
6341 if (is_space_char (*base_string))
6344 else if (*base_string != ')')
6346 as_bad (_("expecting `,' or `)' "
6347 "after index register in `%s'"),
6352 else if (*base_string == REGISTER_PREFIX)
6354 as_bad (_("bad register name `%s'"), base_string);
6358 /* Check for scale factor. */
6359 if (*base_string != ')')
6361 char *end_scale = i386_scale (base_string);
6366 base_string = end_scale;
6367 if (is_space_char (*base_string))
6369 if (*base_string != ')')
6371 as_bad (_("expecting `)' "
6372 "after scale factor in `%s'"),
6377 else if (!i.index_reg)
6379 as_bad (_("expecting index register or scale factor "
6380 "after `,'; got '%c'"),
6385 else if (*base_string != ')')
6387 as_bad (_("expecting `,' or `)' "
6388 "after base register in `%s'"),
6393 else if (*base_string == REGISTER_PREFIX)
6395 as_bad (_("bad register name `%s'"), base_string);
6400 /* If there's an expression beginning the operand, parse it,
6401 assuming displacement_string_start and
6402 displacement_string_end are meaningful. */
6403 if (displacement_string_start != displacement_string_end)
6405 if (!i386_displacement (displacement_string_start,
6406 displacement_string_end))
6410 /* Special case for (%dx) while doing input/output op. */
6412 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6414 && i.log2_scale_factor == 0
6415 && i.seg[i.mem_operands] == 0
6416 && !operand_type_check (i.types[this_operand], disp))
6418 UINTS_CLEAR (i.types[this_operand]);
6419 i.types[this_operand].bitfield.inoutportreg = 1;
6423 if (i386_index_check (operand_string) == 0)
6425 i.types[this_operand].bitfield.mem = 1;
6430 /* It's not a memory operand; argh! */
6431 as_bad (_("invalid char %s beginning operand %d `%s'"),
6432 output_invalid (*op_string),
6437 return 1; /* Normal return. */
6440 /* md_estimate_size_before_relax()
6442 Called just before relax() for rs_machine_dependent frags. The x86
6443 assembler uses these frags to handle variable size jump
6446 Any symbol that is now undefined will not become defined.
6447 Return the correct fr_subtype in the frag.
6448 Return the initial "guess for variable size of frag" to caller.
6449 The guess is actually the growth beyond the fixed part. Whatever
6450 we do to grow the fixed or variable part contributes to our
6454 md_estimate_size_before_relax (fragP, segment)
6458 /* We've already got fragP->fr_subtype right; all we have to do is
6459 check for un-relaxable symbols. On an ELF system, we can't relax
6460 an externally visible symbol, because it may be overridden by a
6462 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6463 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6465 && (S_IS_EXTERNAL (fragP->fr_symbol)
6466 || S_IS_WEAK (fragP->fr_symbol)))
6470 /* Symbol is undefined in this segment, or we need to keep a
6471 reloc so that weak symbols can be overridden. */
6472 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6473 enum bfd_reloc_code_real reloc_type;
6474 unsigned char *opcode;
6477 if (fragP->fr_var != NO_RELOC)
6478 reloc_type = fragP->fr_var;
6480 reloc_type = BFD_RELOC_16_PCREL;
6482 reloc_type = BFD_RELOC_32_PCREL;
6484 old_fr_fix = fragP->fr_fix;
6485 opcode = (unsigned char *) fragP->fr_opcode;
6487 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6490 /* Make jmp (0xeb) a (d)word displacement jump. */
6492 fragP->fr_fix += size;
6493 fix_new (fragP, old_fr_fix, size,
6495 fragP->fr_offset, 1,
6501 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6503 /* Negate the condition, and branch past an
6504 unconditional jump. */
6507 /* Insert an unconditional jump. */
6509 /* We added two extra opcode bytes, and have a two byte
6511 fragP->fr_fix += 2 + 2;
6512 fix_new (fragP, old_fr_fix + 2, 2,
6514 fragP->fr_offset, 1,
6521 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6526 fixP = fix_new (fragP, old_fr_fix, 1,
6528 fragP->fr_offset, 1,
6530 fixP->fx_signed = 1;
6534 /* This changes the byte-displacement jump 0x7N
6535 to the (d)word-displacement jump 0x0f,0x8N. */
6536 opcode[1] = opcode[0] + 0x10;
6537 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6538 /* We've added an opcode byte. */
6539 fragP->fr_fix += 1 + size;
6540 fix_new (fragP, old_fr_fix + 1, size,
6542 fragP->fr_offset, 1,
6547 BAD_CASE (fragP->fr_subtype);
6551 return fragP->fr_fix - old_fr_fix;
6554 /* Guess size depending on current relax state. Initially the relax
6555 state will correspond to a short jump and we return 1, because
6556 the variable part of the frag (the branch offset) is one byte
6557 long. However, we can relax a section more than once and in that
6558 case we must either set fr_subtype back to the unrelaxed state,
6559 or return the value for the appropriate branch. */
6560 return md_relax_table[fragP->fr_subtype].rlx_length;
6563 /* Called after relax() is finished.
6565 In: Address of frag.
6566 fr_type == rs_machine_dependent.
6567 fr_subtype is what the address relaxed to.
6569 Out: Any fixSs and constants are set up.
6570 Caller will turn frag into a ".space 0". */
6573 md_convert_frag (abfd, sec, fragP)
6574 bfd *abfd ATTRIBUTE_UNUSED;
6575 segT sec ATTRIBUTE_UNUSED;
6578 unsigned char *opcode;
6579 unsigned char *where_to_put_displacement = NULL;
6580 offsetT target_address;
6581 offsetT opcode_address;
6582 unsigned int extension = 0;
6583 offsetT displacement_from_opcode_start;
6585 opcode = (unsigned char *) fragP->fr_opcode;
6587 /* Address we want to reach in file space. */
6588 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6590 /* Address opcode resides at in file space. */
6591 opcode_address = fragP->fr_address + fragP->fr_fix;
6593 /* Displacement from opcode start to fill into instruction. */
6594 displacement_from_opcode_start = target_address - opcode_address;
6596 if ((fragP->fr_subtype & BIG) == 0)
6598 /* Don't have to change opcode. */
6599 extension = 1; /* 1 opcode + 1 displacement */
6600 where_to_put_displacement = &opcode[1];
6604 if (no_cond_jump_promotion
6605 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6606 as_warn_where (fragP->fr_file, fragP->fr_line,
6607 _("long jump required"));
6609 switch (fragP->fr_subtype)
6611 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6612 extension = 4; /* 1 opcode + 4 displacement */
6614 where_to_put_displacement = &opcode[1];
6617 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6618 extension = 2; /* 1 opcode + 2 displacement */
6620 where_to_put_displacement = &opcode[1];
6623 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6624 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6625 extension = 5; /* 2 opcode + 4 displacement */
6626 opcode[1] = opcode[0] + 0x10;
6627 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6628 where_to_put_displacement = &opcode[2];
6631 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6632 extension = 3; /* 2 opcode + 2 displacement */
6633 opcode[1] = opcode[0] + 0x10;
6634 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6635 where_to_put_displacement = &opcode[2];
6638 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6643 where_to_put_displacement = &opcode[3];
6647 BAD_CASE (fragP->fr_subtype);
6652 /* If size if less then four we are sure that the operand fits,
6653 but if it's 4, then it could be that the displacement is larger
6655 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6657 && ((addressT) (displacement_from_opcode_start - extension
6658 + ((addressT) 1 << 31))
6659 > (((addressT) 2 << 31) - 1)))
6661 as_bad_where (fragP->fr_file, fragP->fr_line,
6662 _("jump target out of range"));
6663 /* Make us emit 0. */
6664 displacement_from_opcode_start = extension;
6666 /* Now put displacement after opcode. */
6667 md_number_to_chars ((char *) where_to_put_displacement,
6668 (valueT) (displacement_from_opcode_start - extension),
6669 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6670 fragP->fr_fix += extension;
6673 /* Apply a fixup (fixS) to segment data, once it has been determined
6674 by our caller that we have all the info we need to fix it up.
6676 On the 386, immediates, displacements, and data pointers are all in
6677 the same (little-endian) format, so we don't need to care about which
6681 md_apply_fix (fixP, valP, seg)
6682 /* The fix we're to put in. */
6684 /* Pointer to the value of the bits. */
6686 /* Segment fix is from. */
6687 segT seg ATTRIBUTE_UNUSED;
6689 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6690 valueT value = *valP;
6692 #if !defined (TE_Mach)
6695 switch (fixP->fx_r_type)
6701 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6704 case BFD_RELOC_X86_64_32S:
6705 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6708 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6711 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6716 if (fixP->fx_addsy != NULL
6717 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6718 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6719 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6720 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6721 && !use_rela_relocations)
6723 /* This is a hack. There should be a better way to handle this.
6724 This covers for the fact that bfd_install_relocation will
6725 subtract the current location (for partial_inplace, PC relative
6726 relocations); see more below. */
6730 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6733 value += fixP->fx_where + fixP->fx_frag->fr_address;
6735 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6738 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6741 || (symbol_section_p (fixP->fx_addsy)
6742 && sym_seg != absolute_section))
6743 && !generic_force_reloc (fixP))
6745 /* Yes, we add the values in twice. This is because
6746 bfd_install_relocation subtracts them out again. I think
6747 bfd_install_relocation is broken, but I don't dare change
6749 value += fixP->fx_where + fixP->fx_frag->fr_address;
6753 #if defined (OBJ_COFF) && defined (TE_PE)
6754 /* For some reason, the PE format does not store a
6755 section address offset for a PC relative symbol. */
6756 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6757 || S_IS_WEAK (fixP->fx_addsy))
6758 value += md_pcrel_from (fixP);
6762 /* Fix a few things - the dynamic linker expects certain values here,
6763 and we must not disappoint it. */
6764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6765 if (IS_ELF && fixP->fx_addsy)
6766 switch (fixP->fx_r_type)
6768 case BFD_RELOC_386_PLT32:
6769 case BFD_RELOC_X86_64_PLT32:
6770 /* Make the jump instruction point to the address of the operand. At
6771 runtime we merely add the offset to the actual PLT entry. */
6775 case BFD_RELOC_386_TLS_GD:
6776 case BFD_RELOC_386_TLS_LDM:
6777 case BFD_RELOC_386_TLS_IE_32:
6778 case BFD_RELOC_386_TLS_IE:
6779 case BFD_RELOC_386_TLS_GOTIE:
6780 case BFD_RELOC_386_TLS_GOTDESC:
6781 case BFD_RELOC_X86_64_TLSGD:
6782 case BFD_RELOC_X86_64_TLSLD:
6783 case BFD_RELOC_X86_64_GOTTPOFF:
6784 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6785 value = 0; /* Fully resolved at runtime. No addend. */
6787 case BFD_RELOC_386_TLS_LE:
6788 case BFD_RELOC_386_TLS_LDO_32:
6789 case BFD_RELOC_386_TLS_LE_32:
6790 case BFD_RELOC_X86_64_DTPOFF32:
6791 case BFD_RELOC_X86_64_DTPOFF64:
6792 case BFD_RELOC_X86_64_TPOFF32:
6793 case BFD_RELOC_X86_64_TPOFF64:
6794 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6797 case BFD_RELOC_386_TLS_DESC_CALL:
6798 case BFD_RELOC_X86_64_TLSDESC_CALL:
6799 value = 0; /* Fully resolved at runtime. No addend. */
6800 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6804 case BFD_RELOC_386_GOT32:
6805 case BFD_RELOC_X86_64_GOT32:
6806 value = 0; /* Fully resolved at runtime. No addend. */
6809 case BFD_RELOC_VTABLE_INHERIT:
6810 case BFD_RELOC_VTABLE_ENTRY:
6817 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6819 #endif /* !defined (TE_Mach) */
6821 /* Are we finished with this relocation now? */
6822 if (fixP->fx_addsy == NULL)
6824 else if (use_rela_relocations)
6826 fixP->fx_no_overflow = 1;
6827 /* Remember value for tc_gen_reloc. */
6828 fixP->fx_addnumber = value;
6832 md_number_to_chars (p, value, fixP->fx_size);
6836 md_atof (int type, char *litP, int *sizeP)
6838 /* This outputs the LITTLENUMs in REVERSE order;
6839 in accord with the bigendian 386. */
6840 return ieee_md_atof (type, litP, sizeP, FALSE);
6843 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6846 output_invalid (int c)
6849 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6852 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6853 "(0x%x)", (unsigned char) c);
6854 return output_invalid_buf;
6857 /* REG_STRING starts *before* REGISTER_PREFIX. */
6859 static const reg_entry *
6860 parse_real_register (char *reg_string, char **end_op)
6862 char *s = reg_string;
6864 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6867 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6868 if (*s == REGISTER_PREFIX)
6871 if (is_space_char (*s))
6875 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6877 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6878 return (const reg_entry *) NULL;
6882 /* For naked regs, make sure that we are not dealing with an identifier.
6883 This prevents confusing an identifier like `eax_var' with register
6885 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6886 return (const reg_entry *) NULL;
6890 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6892 /* Handle floating point regs, allowing spaces in the (i) part. */
6893 if (r == i386_regtab /* %st is first entry of table */)
6895 if (is_space_char (*s))
6900 if (is_space_char (*s))
6902 if (*s >= '0' && *s <= '7')
6906 if (is_space_char (*s))
6911 r = hash_find (reg_hash, "st(0)");
6916 /* We have "%st(" then garbage. */
6917 return (const reg_entry *) NULL;
6921 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6924 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6925 return (const reg_entry *) NULL;
6928 && ((r->reg_flags & (RegRex64 | RegRex))
6929 || r->reg_type.bitfield.reg64)
6930 && (!cpu_arch_flags.bitfield.cpulm
6931 || !UINTS_EQUAL (r->reg_type, control))
6932 && flag_code != CODE_64BIT)
6933 return (const reg_entry *) NULL;
6938 /* REG_STRING starts *before* REGISTER_PREFIX. */
6940 static const reg_entry *
6941 parse_register (char *reg_string, char **end_op)
6945 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6946 r = parse_real_register (reg_string, end_op);
6951 char *save = input_line_pointer;
6955 input_line_pointer = reg_string;
6956 c = get_symbol_end ();
6957 symbolP = symbol_find (reg_string);
6958 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6960 const expressionS *e = symbol_get_value_expression (symbolP);
6962 know (e->X_op == O_register);
6963 know (e->X_add_number >= 0
6964 && (valueT) e->X_add_number < i386_regtab_size);
6965 r = i386_regtab + e->X_add_number;
6966 *end_op = input_line_pointer;
6968 *input_line_pointer = c;
6969 input_line_pointer = save;
6975 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6978 char *end = input_line_pointer;
6981 r = parse_register (name, &input_line_pointer);
6982 if (r && end <= input_line_pointer)
6984 *nextcharP = *input_line_pointer;
6985 *input_line_pointer = 0;
6986 e->X_op = O_register;
6987 e->X_add_number = r - i386_regtab;
6990 input_line_pointer = end;
6996 md_operand (expressionS *e)
6998 if (*input_line_pointer == REGISTER_PREFIX)
7001 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7005 e->X_op = O_register;
7006 e->X_add_number = r - i386_regtab;
7007 input_line_pointer = end;
7013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7014 const char *md_shortopts = "kVQ:sqn";
7016 const char *md_shortopts = "qn";
7019 #define OPTION_32 (OPTION_MD_BASE + 0)
7020 #define OPTION_64 (OPTION_MD_BASE + 1)
7021 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7022 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7023 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7024 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7025 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7026 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7027 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7028 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7030 struct option md_longopts[] =
7032 {"32", no_argument, NULL, OPTION_32},
7033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7034 {"64", no_argument, NULL, OPTION_64},
7036 {"divide", no_argument, NULL, OPTION_DIVIDE},
7037 {"march", required_argument, NULL, OPTION_MARCH},
7038 {"mtune", required_argument, NULL, OPTION_MTUNE},
7039 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7040 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7041 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7042 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7043 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7044 {NULL, no_argument, NULL, 0}
7046 size_t md_longopts_size = sizeof (md_longopts);
7049 md_parse_option (int c, char *arg)
7056 optimize_align_code = 0;
7063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7064 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7065 should be emitted or not. FIXME: Not implemented. */
7069 /* -V: SVR4 argument to print version ID. */
7071 print_version_id ();
7074 /* -k: Ignore for FreeBSD compatibility. */
7079 /* -s: On i386 Solaris, this tells the native assembler to use
7080 .stab instead of .stab.excl. We always use .stab anyhow. */
7083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7086 const char **list, **l;
7088 list = bfd_target_list ();
7089 for (l = list; *l != NULL; l++)
7090 if (CONST_STRNEQ (*l, "elf64-x86-64")
7091 || strcmp (*l, "coff-x86-64") == 0
7092 || strcmp (*l, "pe-x86-64") == 0
7093 || strcmp (*l, "pei-x86-64") == 0)
7095 default_arch = "x86_64";
7099 as_fatal (_("No compiled in support for x86_64"));
7106 default_arch = "i386";
7110 #ifdef SVR4_COMMENT_CHARS
7115 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7117 for (s = i386_comment_chars; *s != '\0'; s++)
7121 i386_comment_chars = n;
7128 as_fatal (_("Invalid -march= option: `%s'"), arg);
7129 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7131 if (strcmp (arg, cpu_arch [i].name) == 0)
7133 cpu_arch_isa = cpu_arch[i].type;
7134 cpu_arch_isa_flags = cpu_arch[i].flags;
7135 if (!cpu_arch_tune_set)
7137 cpu_arch_tune = cpu_arch_isa;
7138 cpu_arch_tune_flags = cpu_arch_isa_flags;
7143 if (i >= ARRAY_SIZE (cpu_arch))
7144 as_fatal (_("Invalid -march= option: `%s'"), arg);
7149 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7150 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7152 if (strcmp (arg, cpu_arch [i].name) == 0)
7154 cpu_arch_tune_set = 1;
7155 cpu_arch_tune = cpu_arch [i].type;
7156 cpu_arch_tune_flags = cpu_arch[i].flags;
7160 if (i >= ARRAY_SIZE (cpu_arch))
7161 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7164 case OPTION_MMNEMONIC:
7165 if (strcasecmp (arg, "att") == 0)
7167 else if (strcasecmp (arg, "intel") == 0)
7170 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7173 case OPTION_MSYNTAX:
7174 if (strcasecmp (arg, "att") == 0)
7176 else if (strcasecmp (arg, "intel") == 0)
7179 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7182 case OPTION_MINDEX_REG:
7183 allow_index_reg = 1;
7186 case OPTION_MNAKED_REG:
7187 allow_naked_reg = 1;
7190 case OPTION_MOLD_GCC:
7201 md_show_usage (stream)
7204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7205 fprintf (stream, _("\
7207 -V print assembler version number\n\
7210 fprintf (stream, _("\
7211 -n Do not optimize code alignment\n\
7212 -q quieten some warnings\n"));
7213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7214 fprintf (stream, _("\
7217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7218 fprintf (stream, _("\
7219 --32/--64 generate 32bit/64bit code\n"));
7221 #ifdef SVR4_COMMENT_CHARS
7222 fprintf (stream, _("\
7223 --divide do not treat `/' as a comment character\n"));
7225 fprintf (stream, _("\
7226 --divide ignored\n"));
7228 fprintf (stream, _("\
7229 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7230 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7231 core, core2, k6, athlon, k8, generic32, generic64\n"));
7232 fprintf (stream, _("\
7233 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7234 fprintf (stream, _("\
7235 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7236 fprintf (stream, _("\
7237 -mindex-reg support pseudo index registers\n"));
7238 fprintf (stream, _("\
7239 -mnaked-reg don't require `%%' prefix for registers\n"));
7240 fprintf (stream, _("\
7241 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7244 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7245 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7247 /* Pick the target format to use. */
7250 i386_target_format (void)
7252 if (!strcmp (default_arch, "x86_64"))
7254 set_code_flag (CODE_64BIT);
7255 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7257 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7258 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7259 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7260 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7261 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7262 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7263 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7264 cpu_arch_isa_flags.bitfield.cpummx= 1;
7265 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7266 cpu_arch_isa_flags.bitfield.cpusse = 1;
7267 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7269 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7271 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7272 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7273 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7274 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7275 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7276 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7277 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7278 cpu_arch_tune_flags.bitfield.cpummx= 1;
7279 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7280 cpu_arch_tune_flags.bitfield.cpusse = 1;
7281 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7284 else if (!strcmp (default_arch, "i386"))
7286 set_code_flag (CODE_32BIT);
7287 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7289 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7290 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7291 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7293 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7295 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7296 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7297 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7301 as_fatal (_("Unknown architecture"));
7302 switch (OUTPUT_FLAVOR)
7305 case bfd_target_coff_flavour:
7306 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7309 #ifdef OBJ_MAYBE_AOUT
7310 case bfd_target_aout_flavour:
7311 return AOUT_TARGET_FORMAT;
7313 #ifdef OBJ_MAYBE_COFF
7314 case bfd_target_coff_flavour:
7317 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7318 case bfd_target_elf_flavour:
7320 if (flag_code == CODE_64BIT)
7323 use_rela_relocations = 1;
7325 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7334 #endif /* OBJ_MAYBE_ more than one */
7336 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7338 i386_elf_emit_arch_note (void)
7340 if (IS_ELF && cpu_arch_name != NULL)
7343 asection *seg = now_seg;
7344 subsegT subseg = now_subseg;
7345 Elf_Internal_Note i_note;
7346 Elf_External_Note e_note;
7347 asection *note_secp;
7350 /* Create the .note section. */
7351 note_secp = subseg_new (".note", 0);
7352 bfd_set_section_flags (stdoutput,
7354 SEC_HAS_CONTENTS | SEC_READONLY);
7356 /* Process the arch string. */
7357 len = strlen (cpu_arch_name);
7359 i_note.namesz = len + 1;
7361 i_note.type = NT_ARCH;
7362 p = frag_more (sizeof (e_note.namesz));
7363 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7364 p = frag_more (sizeof (e_note.descsz));
7365 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7366 p = frag_more (sizeof (e_note.type));
7367 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7368 p = frag_more (len + 1);
7369 strcpy (p, cpu_arch_name);
7371 frag_align (2, 0, 0);
7373 subseg_set (seg, subseg);
7379 md_undefined_symbol (name)
7382 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7383 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7384 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7385 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7389 if (symbol_find (name))
7390 as_bad (_("GOT already in symbol table"));
7391 GOT_symbol = symbol_new (name, undefined_section,
7392 (valueT) 0, &zero_address_frag);
7399 /* Round up a section size to the appropriate boundary. */
7402 md_section_align (segment, size)
7403 segT segment ATTRIBUTE_UNUSED;
7406 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7407 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7409 /* For a.out, force the section size to be aligned. If we don't do
7410 this, BFD will align it for us, but it will not write out the
7411 final bytes of the section. This may be a bug in BFD, but it is
7412 easier to fix it here since that is how the other a.out targets
7416 align = bfd_get_section_alignment (stdoutput, segment);
7417 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7424 /* On the i386, PC-relative offsets are relative to the start of the
7425 next instruction. That is, the address of the offset, plus its
7426 size, since the offset is always the last part of the insn. */
7429 md_pcrel_from (fixS *fixP)
7431 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7437 s_bss (int ignore ATTRIBUTE_UNUSED)
7441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7443 obj_elf_section_change_hook ();
7445 temp = get_absolute_expression ();
7446 subseg_set (bss_section, (subsegT) temp);
7447 demand_empty_rest_of_line ();
7453 i386_validate_fix (fixS *fixp)
7455 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7457 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7461 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7466 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7468 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7475 tc_gen_reloc (section, fixp)
7476 asection *section ATTRIBUTE_UNUSED;
7480 bfd_reloc_code_real_type code;
7482 switch (fixp->fx_r_type)
7484 case BFD_RELOC_X86_64_PLT32:
7485 case BFD_RELOC_X86_64_GOT32:
7486 case BFD_RELOC_X86_64_GOTPCREL:
7487 case BFD_RELOC_386_PLT32:
7488 case BFD_RELOC_386_GOT32:
7489 case BFD_RELOC_386_GOTOFF:
7490 case BFD_RELOC_386_GOTPC:
7491 case BFD_RELOC_386_TLS_GD:
7492 case BFD_RELOC_386_TLS_LDM:
7493 case BFD_RELOC_386_TLS_LDO_32:
7494 case BFD_RELOC_386_TLS_IE_32:
7495 case BFD_RELOC_386_TLS_IE:
7496 case BFD_RELOC_386_TLS_GOTIE:
7497 case BFD_RELOC_386_TLS_LE_32:
7498 case BFD_RELOC_386_TLS_LE:
7499 case BFD_RELOC_386_TLS_GOTDESC:
7500 case BFD_RELOC_386_TLS_DESC_CALL:
7501 case BFD_RELOC_X86_64_TLSGD:
7502 case BFD_RELOC_X86_64_TLSLD:
7503 case BFD_RELOC_X86_64_DTPOFF32:
7504 case BFD_RELOC_X86_64_DTPOFF64:
7505 case BFD_RELOC_X86_64_GOTTPOFF:
7506 case BFD_RELOC_X86_64_TPOFF32:
7507 case BFD_RELOC_X86_64_TPOFF64:
7508 case BFD_RELOC_X86_64_GOTOFF64:
7509 case BFD_RELOC_X86_64_GOTPC32:
7510 case BFD_RELOC_X86_64_GOT64:
7511 case BFD_RELOC_X86_64_GOTPCREL64:
7512 case BFD_RELOC_X86_64_GOTPC64:
7513 case BFD_RELOC_X86_64_GOTPLT64:
7514 case BFD_RELOC_X86_64_PLTOFF64:
7515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7516 case BFD_RELOC_X86_64_TLSDESC_CALL:
7518 case BFD_RELOC_VTABLE_ENTRY:
7519 case BFD_RELOC_VTABLE_INHERIT:
7521 case BFD_RELOC_32_SECREL:
7523 code = fixp->fx_r_type;
7525 case BFD_RELOC_X86_64_32S:
7526 if (!fixp->fx_pcrel)
7528 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7529 code = fixp->fx_r_type;
7535 switch (fixp->fx_size)
7538 as_bad_where (fixp->fx_file, fixp->fx_line,
7539 _("can not do %d byte pc-relative relocation"),
7541 code = BFD_RELOC_32_PCREL;
7543 case 1: code = BFD_RELOC_8_PCREL; break;
7544 case 2: code = BFD_RELOC_16_PCREL; break;
7545 case 4: code = BFD_RELOC_32_PCREL; break;
7547 case 8: code = BFD_RELOC_64_PCREL; break;
7553 switch (fixp->fx_size)
7556 as_bad_where (fixp->fx_file, fixp->fx_line,
7557 _("can not do %d byte relocation"),
7559 code = BFD_RELOC_32;
7561 case 1: code = BFD_RELOC_8; break;
7562 case 2: code = BFD_RELOC_16; break;
7563 case 4: code = BFD_RELOC_32; break;
7565 case 8: code = BFD_RELOC_64; break;
7572 if ((code == BFD_RELOC_32
7573 || code == BFD_RELOC_32_PCREL
7574 || code == BFD_RELOC_X86_64_32S)
7576 && fixp->fx_addsy == GOT_symbol)
7579 code = BFD_RELOC_386_GOTPC;
7581 code = BFD_RELOC_X86_64_GOTPC32;
7583 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7585 && fixp->fx_addsy == GOT_symbol)
7587 code = BFD_RELOC_X86_64_GOTPC64;
7590 rel = (arelent *) xmalloc (sizeof (arelent));
7591 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7592 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7594 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7596 if (!use_rela_relocations)
7598 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7599 vtable entry to be used in the relocation's section offset. */
7600 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7601 rel->address = fixp->fx_offset;
7605 /* Use the rela in 64bit mode. */
7608 if (!fixp->fx_pcrel)
7609 rel->addend = fixp->fx_offset;
7613 case BFD_RELOC_X86_64_PLT32:
7614 case BFD_RELOC_X86_64_GOT32:
7615 case BFD_RELOC_X86_64_GOTPCREL:
7616 case BFD_RELOC_X86_64_TLSGD:
7617 case BFD_RELOC_X86_64_TLSLD:
7618 case BFD_RELOC_X86_64_GOTTPOFF:
7619 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7620 case BFD_RELOC_X86_64_TLSDESC_CALL:
7621 rel->addend = fixp->fx_offset - fixp->fx_size;
7624 rel->addend = (section->vma
7626 + fixp->fx_addnumber
7627 + md_pcrel_from (fixp));
7632 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7633 if (rel->howto == NULL)
7635 as_bad_where (fixp->fx_file, fixp->fx_line,
7636 _("cannot represent relocation type %s"),
7637 bfd_get_reloc_code_name (code));
7638 /* Set howto to a garbage value so that we can keep going. */
7639 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7640 assert (rel->howto != NULL);
7647 /* Parse operands using Intel syntax. This implements a recursive descent
7648 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7651 FIXME: We do not recognize the full operand grammar defined in the MASM
7652 documentation. In particular, all the structure/union and
7653 high-level macro operands are missing.
7655 Uppercase words are terminals, lower case words are non-terminals.
7656 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7657 bars '|' denote choices. Most grammar productions are implemented in
7658 functions called 'intel_<production>'.
7660 Initial production is 'expr'.
7666 binOp & | AND | \| | OR | ^ | XOR
7668 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7670 constant digits [[ radixOverride ]]
7672 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7710 => expr expr cmpOp e04
7713 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7714 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7716 hexdigit a | b | c | d | e | f
7717 | A | B | C | D | E | F
7723 mulOp * | / | % | MOD | << | SHL | >> | SHR
7727 register specialRegister
7731 segmentRegister CS | DS | ES | FS | GS | SS
7733 specialRegister CR0 | CR2 | CR3 | CR4
7734 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7735 | TR3 | TR4 | TR5 | TR6 | TR7
7737 We simplify the grammar in obvious places (e.g., register parsing is
7738 done by calling parse_register) and eliminate immediate left recursion
7739 to implement a recursive-descent parser.
7743 expr' cmpOp e04 expr'
7794 /* Parsing structure for the intel syntax parser. Used to implement the
7795 semantic actions for the operand grammar. */
7796 struct intel_parser_s
7798 char *op_string; /* The string being parsed. */
7799 int got_a_float; /* Whether the operand is a float. */
7800 int op_modifier; /* Operand modifier. */
7801 int is_mem; /* 1 if operand is memory reference. */
7802 int in_offset; /* >=1 if parsing operand of offset. */
7803 int in_bracket; /* >=1 if parsing operand in brackets. */
7804 const reg_entry *reg; /* Last register reference found. */
7805 char *disp; /* Displacement string being built. */
7806 char *next_operand; /* Resume point when splitting operands. */
7809 static struct intel_parser_s intel_parser;
7811 /* Token structure for parsing intel syntax. */
7814 int code; /* Token code. */
7815 const reg_entry *reg; /* Register entry for register tokens. */
7816 char *str; /* String representation. */
7819 static struct intel_token cur_token, prev_token;
7821 /* Token codes for the intel parser. Since T_SHORT is already used
7822 by COFF, undefine it first to prevent a warning. */
7841 /* Prototypes for intel parser functions. */
7842 static int intel_match_token (int);
7843 static void intel_putback_token (void);
7844 static void intel_get_token (void);
7845 static int intel_expr (void);
7846 static int intel_e04 (void);
7847 static int intel_e05 (void);
7848 static int intel_e06 (void);
7849 static int intel_e09 (void);
7850 static int intel_e10 (void);
7851 static int intel_e11 (void);
7854 i386_intel_operand (char *operand_string, int got_a_float)
7859 p = intel_parser.op_string = xstrdup (operand_string);
7860 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7864 /* Initialize token holders. */
7865 cur_token.code = prev_token.code = T_NIL;
7866 cur_token.reg = prev_token.reg = NULL;
7867 cur_token.str = prev_token.str = NULL;
7869 /* Initialize parser structure. */
7870 intel_parser.got_a_float = got_a_float;
7871 intel_parser.op_modifier = 0;
7872 intel_parser.is_mem = 0;
7873 intel_parser.in_offset = 0;
7874 intel_parser.in_bracket = 0;
7875 intel_parser.reg = NULL;
7876 intel_parser.disp[0] = '\0';
7877 intel_parser.next_operand = NULL;
7879 /* Read the first token and start the parser. */
7881 ret = intel_expr ();
7886 if (cur_token.code != T_NIL)
7888 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7889 current_templates->start->name, cur_token.str);
7892 /* If we found a memory reference, hand it over to i386_displacement
7893 to fill in the rest of the operand fields. */
7894 else if (intel_parser.is_mem)
7896 if ((i.mem_operands == 1
7897 && !current_templates->start->opcode_modifier.isstring)
7898 || i.mem_operands == 2)
7900 as_bad (_("too many memory references for '%s'"),
7901 current_templates->start->name);
7906 char *s = intel_parser.disp;
7907 i.types[this_operand].bitfield.mem = 1;
7910 if (!quiet_warnings && intel_parser.is_mem < 0)
7911 /* See the comments in intel_bracket_expr. */
7912 as_warn (_("Treating `%s' as memory reference"), operand_string);
7914 /* Add the displacement expression. */
7916 ret = i386_displacement (s, s + strlen (s));
7919 /* Swap base and index in 16-bit memory operands like
7920 [si+bx]. Since i386_index_check is also used in AT&T
7921 mode we have to do that here. */
7924 && i.base_reg->reg_type.bitfield.reg16
7925 && i.index_reg->reg_type.bitfield.reg16
7926 && i.base_reg->reg_num >= 6
7927 && i.index_reg->reg_num < 6)
7929 const reg_entry *base = i.index_reg;
7931 i.index_reg = i.base_reg;
7934 ret = i386_index_check (operand_string);
7939 /* Constant and OFFSET expressions are handled by i386_immediate. */
7940 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7941 || intel_parser.reg == NULL)
7942 ret = i386_immediate (intel_parser.disp);
7944 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7946 if (!ret || !intel_parser.next_operand)
7948 intel_parser.op_string = intel_parser.next_operand;
7949 this_operand = i.operands++;
7950 i.types[this_operand].bitfield.unspecified = 1;
7954 free (intel_parser.disp);
7959 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7963 expr' cmpOp e04 expr'
7968 /* XXX Implement the comparison operators. */
7969 return intel_e04 ();
7986 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7987 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7989 if (cur_token.code == '+')
7991 else if (cur_token.code == '-')
7992 nregs = NUM_ADDRESS_REGS;
7996 strcat (intel_parser.disp, cur_token.str);
7997 intel_match_token (cur_token.code);
8008 int nregs = ~NUM_ADDRESS_REGS;
8015 if (cur_token.code == '&'
8016 || cur_token.code == '|'
8017 || cur_token.code == '^')
8021 str[0] = cur_token.code;
8023 strcat (intel_parser.disp, str);
8028 intel_match_token (cur_token.code);
8033 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8034 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8045 int nregs = ~NUM_ADDRESS_REGS;
8052 if (cur_token.code == '*'
8053 || cur_token.code == '/'
8054 || cur_token.code == '%')
8058 str[0] = cur_token.code;
8060 strcat (intel_parser.disp, str);
8062 else if (cur_token.code == T_SHL)
8063 strcat (intel_parser.disp, "<<");
8064 else if (cur_token.code == T_SHR)
8065 strcat (intel_parser.disp, ">>");
8069 intel_match_token (cur_token.code);
8074 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8075 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8093 int nregs = ~NUM_ADDRESS_REGS;
8098 /* Don't consume constants here. */
8099 if (cur_token.code == '+' || cur_token.code == '-')
8101 /* Need to look one token ahead - if the next token
8102 is a constant, the current token is its sign. */
8105 intel_match_token (cur_token.code);
8106 next_code = cur_token.code;
8107 intel_putback_token ();
8108 if (next_code == T_CONST)
8112 /* e09 OFFSET e09 */
8113 if (cur_token.code == T_OFFSET)
8116 ++intel_parser.in_offset;
8120 else if (cur_token.code == T_SHORT)
8121 intel_parser.op_modifier |= 1 << T_SHORT;
8124 else if (cur_token.code == '+')
8125 strcat (intel_parser.disp, "+");
8130 else if (cur_token.code == '-' || cur_token.code == '~')
8136 str[0] = cur_token.code;
8138 strcat (intel_parser.disp, str);
8145 intel_match_token (cur_token.code);
8153 /* e09' PTR e10 e09' */
8154 if (cur_token.code == T_PTR)
8158 if (prev_token.code == T_BYTE)
8160 suffix = BYTE_MNEM_SUFFIX;
8161 i.types[this_operand].bitfield.byte = 1;
8164 else if (prev_token.code == T_WORD)
8166 if (current_templates->start->name[0] == 'l'
8167 && current_templates->start->name[2] == 's'
8168 && current_templates->start->name[3] == 0)
8169 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8170 else if (intel_parser.got_a_float == 2) /* "fi..." */
8171 suffix = SHORT_MNEM_SUFFIX;
8173 suffix = WORD_MNEM_SUFFIX;
8174 i.types[this_operand].bitfield.word = 1;
8177 else if (prev_token.code == T_DWORD)
8179 if (current_templates->start->name[0] == 'l'
8180 && current_templates->start->name[2] == 's'
8181 && current_templates->start->name[3] == 0)
8182 suffix = WORD_MNEM_SUFFIX;
8183 else if (flag_code == CODE_16BIT
8184 && (current_templates->start->opcode_modifier.jump
8185 || current_templates->start->opcode_modifier.jumpdword))
8186 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8187 else if (intel_parser.got_a_float == 1) /* "f..." */
8188 suffix = SHORT_MNEM_SUFFIX;
8190 suffix = LONG_MNEM_SUFFIX;
8191 i.types[this_operand].bitfield.dword = 1;
8194 else if (prev_token.code == T_FWORD)
8196 if (current_templates->start->name[0] == 'l'
8197 && current_templates->start->name[2] == 's'
8198 && current_templates->start->name[3] == 0)
8199 suffix = LONG_MNEM_SUFFIX;
8200 else if (!intel_parser.got_a_float)
8202 if (flag_code == CODE_16BIT)
8203 add_prefix (DATA_PREFIX_OPCODE);
8204 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8207 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8208 i.types[this_operand].bitfield.fword = 1;
8211 else if (prev_token.code == T_QWORD)
8213 if (intel_parser.got_a_float == 1) /* "f..." */
8214 suffix = LONG_MNEM_SUFFIX;
8216 suffix = QWORD_MNEM_SUFFIX;
8217 i.types[this_operand].bitfield.qword = 1;
8220 else if (prev_token.code == T_TBYTE)
8222 if (intel_parser.got_a_float == 1)
8223 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8225 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8228 else if (prev_token.code == T_XMMWORD)
8230 suffix = XMMWORD_MNEM_SUFFIX;
8231 i.types[this_operand].bitfield.xmmword = 1;
8236 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8240 i.types[this_operand].bitfield.unspecified = 0;
8242 /* Operands for jump/call using 'ptr' notation denote absolute
8244 if (current_templates->start->opcode_modifier.jump
8245 || current_templates->start->opcode_modifier.jumpdword)
8246 i.types[this_operand].bitfield.jumpabsolute = 1;
8248 if (current_templates->start->base_opcode == 0x8d /* lea */)
8252 else if (i.suffix != suffix)
8254 as_bad (_("Conflicting operand modifiers"));
8260 /* e09' : e10 e09' */
8261 else if (cur_token.code == ':')
8263 if (prev_token.code != T_REG)
8265 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8266 segment/group identifier (which we don't have), using comma
8267 as the operand separator there is even less consistent, since
8268 there all branches only have a single operand. */
8269 if (this_operand != 0
8270 || intel_parser.in_offset
8271 || intel_parser.in_bracket
8272 || (!current_templates->start->opcode_modifier.jump
8273 && !current_templates->start->opcode_modifier.jumpdword
8274 && !current_templates->start->opcode_modifier.jumpintersegment
8275 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8276 return intel_match_token (T_NIL);
8277 /* Remember the start of the 2nd operand and terminate 1st
8279 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8280 another expression), but it gets at least the simplest case
8281 (a plain number or symbol on the left side) right. */
8282 intel_parser.next_operand = intel_parser.op_string;
8283 *--intel_parser.op_string = '\0';
8284 return intel_match_token (':');
8292 intel_match_token (cur_token.code);
8298 --intel_parser.in_offset;
8301 if (NUM_ADDRESS_REGS > nregs)
8303 as_bad (_("Invalid operand to `OFFSET'"));
8306 intel_parser.op_modifier |= 1 << T_OFFSET;
8309 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8310 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8315 intel_bracket_expr (void)
8317 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8318 const char *start = intel_parser.op_string;
8321 if (i.op[this_operand].regs)
8322 return intel_match_token (T_NIL);
8324 intel_match_token ('[');
8326 /* Mark as a memory operand only if it's not already known to be an
8327 offset expression. If it's an offset expression, we need to keep
8329 if (!intel_parser.in_offset)
8331 ++intel_parser.in_bracket;
8333 /* Operands for jump/call inside brackets denote absolute addresses. */
8334 if (current_templates->start->opcode_modifier.jump
8335 || current_templates->start->opcode_modifier.jumpdword)
8336 i.types[this_operand].bitfield.jumpabsolute = 1;
8338 /* Unfortunately gas always diverged from MASM in a respect that can't
8339 be easily fixed without risking to break code sequences likely to be
8340 encountered (the testsuite even check for this): MASM doesn't consider
8341 an expression inside brackets unconditionally as a memory reference.
8342 When that is e.g. a constant, an offset expression, or the sum of the
8343 two, this is still taken as a constant load. gas, however, always
8344 treated these as memory references. As a compromise, we'll try to make
8345 offset expressions inside brackets work the MASM way (since that's
8346 less likely to be found in real world code), but make constants alone
8347 continue to work the traditional gas way. In either case, issue a
8349 intel_parser.op_modifier &= ~was_offset;
8352 strcat (intel_parser.disp, "[");
8354 /* Add a '+' to the displacement string if necessary. */
8355 if (*intel_parser.disp != '\0'
8356 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8357 strcat (intel_parser.disp, "+");
8360 && (len = intel_parser.op_string - start - 1,
8361 intel_match_token (']')))
8363 /* Preserve brackets when the operand is an offset expression. */
8364 if (intel_parser.in_offset)
8365 strcat (intel_parser.disp, "]");
8368 --intel_parser.in_bracket;
8369 if (i.base_reg || i.index_reg)
8370 intel_parser.is_mem = 1;
8371 if (!intel_parser.is_mem)
8373 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8374 /* Defer the warning until all of the operand was parsed. */
8375 intel_parser.is_mem = -1;
8376 else if (!quiet_warnings)
8377 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8378 len, start, len, start);
8381 intel_parser.op_modifier |= was_offset;
8398 while (cur_token.code == '[')
8400 if (!intel_bracket_expr ())
8425 switch (cur_token.code)
8429 intel_match_token ('(');
8430 strcat (intel_parser.disp, "(");
8432 if (intel_expr () && intel_match_token (')'))
8434 strcat (intel_parser.disp, ")");
8441 return intel_bracket_expr ();
8446 strcat (intel_parser.disp, cur_token.str);
8447 intel_match_token (cur_token.code);
8449 /* Mark as a memory operand only if it's not already known to be an
8450 offset expression. */
8451 if (!intel_parser.in_offset)
8452 intel_parser.is_mem = 1;
8459 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8461 intel_match_token (T_REG);
8463 /* Check for segment change. */
8464 if (cur_token.code == ':')
8466 if (!reg->reg_type.bitfield.sreg2
8467 && !reg->reg_type.bitfield.sreg3)
8469 as_bad (_("`%s' is not a valid segment register"),
8473 else if (i.seg[i.mem_operands])
8474 as_warn (_("Extra segment override ignored"));
8477 if (!intel_parser.in_offset)
8478 intel_parser.is_mem = 1;
8479 switch (reg->reg_num)
8482 i.seg[i.mem_operands] = &es;
8485 i.seg[i.mem_operands] = &cs;
8488 i.seg[i.mem_operands] = &ss;
8491 i.seg[i.mem_operands] = &ds;
8494 i.seg[i.mem_operands] = &fs;
8497 i.seg[i.mem_operands] = &gs;
8503 /* Not a segment register. Check for register scaling. */
8504 else if (cur_token.code == '*')
8506 if (!intel_parser.in_bracket)
8508 as_bad (_("Register scaling only allowed in memory operands"));
8512 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8513 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8514 else if (i.index_reg)
8515 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8517 /* What follows must be a valid scale. */
8518 intel_match_token ('*');
8520 i.types[this_operand].bitfield.baseindex = 1;
8522 /* Set the scale after setting the register (otherwise,
8523 i386_scale will complain) */
8524 if (cur_token.code == '+' || cur_token.code == '-')
8526 char *str, sign = cur_token.code;
8527 intel_match_token (cur_token.code);
8528 if (cur_token.code != T_CONST)
8530 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8534 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8535 strcpy (str + 1, cur_token.str);
8537 if (!i386_scale (str))
8541 else if (!i386_scale (cur_token.str))
8543 intel_match_token (cur_token.code);
8546 /* No scaling. If this is a memory operand, the register is either a
8547 base register (first occurrence) or an index register (second
8549 else if (intel_parser.in_bracket)
8554 else if (!i.index_reg)
8558 as_bad (_("Too many register references in memory operand"));
8562 i.types[this_operand].bitfield.baseindex = 1;
8565 /* It's neither base nor index. */
8566 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8568 i386_operand_type temp = reg->reg_type;
8569 temp.bitfield.baseindex = 0;
8570 i.types[this_operand] = operand_type_or (i.types[this_operand],
8572 i.types[this_operand].bitfield.unspecified = 0;
8573 i.op[this_operand].regs = reg;
8578 as_bad (_("Invalid use of register"));
8582 /* Since registers are not part of the displacement string (except
8583 when we're parsing offset operands), we may need to remove any
8584 preceding '+' from the displacement string. */
8585 if (*intel_parser.disp != '\0'
8586 && !intel_parser.in_offset)
8588 char *s = intel_parser.disp;
8589 s += strlen (s) - 1;
8612 intel_match_token (cur_token.code);
8614 if (cur_token.code == T_PTR)
8617 /* It must have been an identifier. */
8618 intel_putback_token ();
8619 cur_token.code = T_ID;
8625 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8629 /* The identifier represents a memory reference only if it's not
8630 preceded by an offset modifier and if it's not an equate. */
8631 symbolP = symbol_find(cur_token.str);
8632 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8633 intel_parser.is_mem = 1;
8641 char *save_str, sign = 0;
8643 /* Allow constants that start with `+' or `-'. */
8644 if (cur_token.code == '-' || cur_token.code == '+')
8646 sign = cur_token.code;
8647 intel_match_token (cur_token.code);
8648 if (cur_token.code != T_CONST)
8650 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8656 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8657 strcpy (save_str + !!sign, cur_token.str);
8661 /* Get the next token to check for register scaling. */
8662 intel_match_token (cur_token.code);
8664 /* Check if this constant is a scaling factor for an
8666 if (cur_token.code == '*')
8668 if (intel_match_token ('*') && cur_token.code == T_REG)
8670 const reg_entry *reg = cur_token.reg;
8672 if (!intel_parser.in_bracket)
8674 as_bad (_("Register scaling only allowed "
8675 "in memory operands"));
8679 /* Disallow things like [1*si].
8680 sp and esp are invalid as index. */
8681 if (reg->reg_type.bitfield.reg16)
8682 reg = i386_regtab + REGNAM_AX + 4;
8683 else if (i.index_reg)
8684 reg = i386_regtab + REGNAM_EAX + 4;
8686 /* The constant is followed by `* reg', so it must be
8689 i.types[this_operand].bitfield.baseindex = 1;
8691 /* Set the scale after setting the register (otherwise,
8692 i386_scale will complain) */
8693 if (!i386_scale (save_str))
8695 intel_match_token (T_REG);
8697 /* Since registers are not part of the displacement
8698 string, we may need to remove any preceding '+' from
8699 the displacement string. */
8700 if (*intel_parser.disp != '\0')
8702 char *s = intel_parser.disp;
8703 s += strlen (s) - 1;
8713 /* The constant was not used for register scaling. Since we have
8714 already consumed the token following `*' we now need to put it
8715 back in the stream. */
8716 intel_putback_token ();
8719 /* Add the constant to the displacement string. */
8720 strcat (intel_parser.disp, save_str);
8727 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8731 /* Match the given token against cur_token. If they match, read the next
8732 token from the operand string. */
8734 intel_match_token (int code)
8736 if (cur_token.code == code)
8743 as_bad (_("Unexpected token `%s'"), cur_token.str);
8748 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8750 intel_get_token (void)
8753 const reg_entry *reg;
8754 struct intel_token new_token;
8756 new_token.code = T_NIL;
8757 new_token.reg = NULL;
8758 new_token.str = NULL;
8760 /* Free the memory allocated to the previous token and move
8761 cur_token to prev_token. */
8763 free (prev_token.str);
8765 prev_token = cur_token;
8767 /* Skip whitespace. */
8768 while (is_space_char (*intel_parser.op_string))
8769 intel_parser.op_string++;
8771 /* Return an empty token if we find nothing else on the line. */
8772 if (*intel_parser.op_string == '\0')
8774 cur_token = new_token;
8778 /* The new token cannot be larger than the remainder of the operand
8780 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8781 new_token.str[0] = '\0';
8783 if (strchr ("0123456789", *intel_parser.op_string))
8785 char *p = new_token.str;
8786 char *q = intel_parser.op_string;
8787 new_token.code = T_CONST;
8789 /* Allow any kind of identifier char to encompass floating point and
8790 hexadecimal numbers. */
8791 while (is_identifier_char (*q))
8795 /* Recognize special symbol names [0-9][bf]. */
8796 if (strlen (intel_parser.op_string) == 2
8797 && (intel_parser.op_string[1] == 'b'
8798 || intel_parser.op_string[1] == 'f'))
8799 new_token.code = T_ID;
8802 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8804 size_t len = end_op - intel_parser.op_string;
8806 new_token.code = T_REG;
8807 new_token.reg = reg;
8809 memcpy (new_token.str, intel_parser.op_string, len);
8810 new_token.str[len] = '\0';
8813 else if (is_identifier_char (*intel_parser.op_string))
8815 char *p = new_token.str;
8816 char *q = intel_parser.op_string;
8818 /* A '.' or '$' followed by an identifier char is an identifier.
8819 Otherwise, it's operator '.' followed by an expression. */
8820 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8822 new_token.code = '.';
8823 new_token.str[0] = '.';
8824 new_token.str[1] = '\0';
8828 while (is_identifier_char (*q) || *q == '@')
8832 if (strcasecmp (new_token.str, "NOT") == 0)
8833 new_token.code = '~';
8835 else if (strcasecmp (new_token.str, "MOD") == 0)
8836 new_token.code = '%';
8838 else if (strcasecmp (new_token.str, "AND") == 0)
8839 new_token.code = '&';
8841 else if (strcasecmp (new_token.str, "OR") == 0)
8842 new_token.code = '|';
8844 else if (strcasecmp (new_token.str, "XOR") == 0)
8845 new_token.code = '^';
8847 else if (strcasecmp (new_token.str, "SHL") == 0)
8848 new_token.code = T_SHL;
8850 else if (strcasecmp (new_token.str, "SHR") == 0)
8851 new_token.code = T_SHR;
8853 else if (strcasecmp (new_token.str, "BYTE") == 0)
8854 new_token.code = T_BYTE;
8856 else if (strcasecmp (new_token.str, "WORD") == 0)
8857 new_token.code = T_WORD;
8859 else if (strcasecmp (new_token.str, "DWORD") == 0)
8860 new_token.code = T_DWORD;
8862 else if (strcasecmp (new_token.str, "FWORD") == 0)
8863 new_token.code = T_FWORD;
8865 else if (strcasecmp (new_token.str, "QWORD") == 0)
8866 new_token.code = T_QWORD;
8868 else if (strcasecmp (new_token.str, "TBYTE") == 0
8869 /* XXX remove (gcc still uses it) */
8870 || strcasecmp (new_token.str, "XWORD") == 0)
8871 new_token.code = T_TBYTE;
8873 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8874 || strcasecmp (new_token.str, "OWORD") == 0)
8875 new_token.code = T_XMMWORD;
8877 else if (strcasecmp (new_token.str, "PTR") == 0)
8878 new_token.code = T_PTR;
8880 else if (strcasecmp (new_token.str, "SHORT") == 0)
8881 new_token.code = T_SHORT;
8883 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8885 new_token.code = T_OFFSET;
8887 /* ??? This is not mentioned in the MASM grammar but gcc
8888 makes use of it with -mintel-syntax. OFFSET may be
8889 followed by FLAT: */
8890 if (strncasecmp (q, " FLAT:", 6) == 0)
8891 strcat (new_token.str, " FLAT:");
8894 /* ??? This is not mentioned in the MASM grammar. */
8895 else if (strcasecmp (new_token.str, "FLAT") == 0)
8897 new_token.code = T_OFFSET;
8899 strcat (new_token.str, ":");
8901 as_bad (_("`:' expected"));
8905 new_token.code = T_ID;
8909 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8911 new_token.code = *intel_parser.op_string;
8912 new_token.str[0] = *intel_parser.op_string;
8913 new_token.str[1] = '\0';
8916 else if (strchr ("<>", *intel_parser.op_string)
8917 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8919 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8920 new_token.str[0] = *intel_parser.op_string;
8921 new_token.str[1] = *intel_parser.op_string;
8922 new_token.str[2] = '\0';
8926 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8928 intel_parser.op_string += strlen (new_token.str);
8929 cur_token = new_token;
8932 /* Put cur_token back into the token stream and make cur_token point to
8935 intel_putback_token (void)
8937 if (cur_token.code != T_NIL)
8939 intel_parser.op_string -= strlen (cur_token.str);
8940 free (cur_token.str);
8942 cur_token = prev_token;
8944 /* Forget prev_token. */
8945 prev_token.code = T_NIL;
8946 prev_token.reg = NULL;
8947 prev_token.str = NULL;
8951 tc_x86_regname_to_dw2regnum (char *regname)
8953 unsigned int regnum;
8954 unsigned int regnames_count;
8955 static const char *const regnames_32[] =
8957 "eax", "ecx", "edx", "ebx",
8958 "esp", "ebp", "esi", "edi",
8959 "eip", "eflags", NULL,
8960 "st0", "st1", "st2", "st3",
8961 "st4", "st5", "st6", "st7",
8963 "xmm0", "xmm1", "xmm2", "xmm3",
8964 "xmm4", "xmm5", "xmm6", "xmm7",
8965 "mm0", "mm1", "mm2", "mm3",
8966 "mm4", "mm5", "mm6", "mm7",
8967 "fcw", "fsw", "mxcsr",
8968 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8971 static const char *const regnames_64[] =
8973 "rax", "rdx", "rcx", "rbx",
8974 "rsi", "rdi", "rbp", "rsp",
8975 "r8", "r9", "r10", "r11",
8976 "r12", "r13", "r14", "r15",
8978 "xmm0", "xmm1", "xmm2", "xmm3",
8979 "xmm4", "xmm5", "xmm6", "xmm7",
8980 "xmm8", "xmm9", "xmm10", "xmm11",
8981 "xmm12", "xmm13", "xmm14", "xmm15",
8982 "st0", "st1", "st2", "st3",
8983 "st4", "st5", "st6", "st7",
8984 "mm0", "mm1", "mm2", "mm3",
8985 "mm4", "mm5", "mm6", "mm7",
8987 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8988 "fs.base", "gs.base", NULL, NULL,
8990 "mxcsr", "fcw", "fsw"
8992 const char *const *regnames;
8994 if (flag_code == CODE_64BIT)
8996 regnames = regnames_64;
8997 regnames_count = ARRAY_SIZE (regnames_64);
9001 regnames = regnames_32;
9002 regnames_count = ARRAY_SIZE (regnames_32);
9005 for (regnum = 0; regnum < regnames_count; regnum++)
9006 if (regnames[regnum] != NULL
9007 && strcmp (regname, regnames[regnum]) == 0)
9014 tc_x86_frame_initial_instructions (void)
9016 static unsigned int sp_regno;
9019 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9022 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9023 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9027 i386_elf_section_type (const char *str, size_t len)
9029 if (flag_code == CODE_64BIT
9030 && len == sizeof ("unwind") - 1
9031 && strncmp (str, "unwind", 6) == 0)
9032 return SHT_X86_64_UNWIND;
9039 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9043 expr.X_op = O_secrel;
9044 expr.X_add_symbol = symbol;
9045 expr.X_add_number = 0;
9046 emit_expr (&expr, size);
9050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9051 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9054 x86_64_section_letter (int letter, char **ptr_msg)
9056 if (flag_code == CODE_64BIT)
9059 return SHF_X86_64_LARGE;
9061 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9064 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9069 x86_64_section_word (char *str, size_t len)
9071 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9072 return SHF_X86_64_LARGE;
9078 handle_large_common (int small ATTRIBUTE_UNUSED)
9080 if (flag_code != CODE_64BIT)
9082 s_comm_internal (0, elf_common_parse);
9083 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9087 static segT lbss_section;
9088 asection *saved_com_section_ptr = elf_com_section_ptr;
9089 asection *saved_bss_section = bss_section;
9091 if (lbss_section == NULL)
9093 flagword applicable;
9095 subsegT subseg = now_subseg;
9097 /* The .lbss section is for local .largecomm symbols. */
9098 lbss_section = subseg_new (".lbss", 0);
9099 applicable = bfd_applicable_section_flags (stdoutput);
9100 bfd_set_section_flags (stdoutput, lbss_section,
9101 applicable & SEC_ALLOC);
9102 seg_info (lbss_section)->bss = 1;
9104 subseg_set (seg, subseg);
9107 elf_com_section_ptr = &_bfd_elf_large_com_section;
9108 bss_section = lbss_section;
9110 s_comm_internal (0, elf_common_parse);
9112 elf_com_section_ptr = saved_com_section_ptr;
9113 bss_section = saved_bss_section;
9116 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */