1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void swap_imm_operands PARAMS ((void));
93 static void optimize_imm PARAMS ((void));
94 static void optimize_disp PARAMS ((void));
95 static int match_template PARAMS ((void));
96 static int check_string PARAMS ((void));
97 static int process_suffix PARAMS ((void));
98 static int check_byte_reg PARAMS ((void));
99 static int check_long_reg PARAMS ((void));
100 static int check_qword_reg PARAMS ((void));
101 static int check_word_reg PARAMS ((void));
102 static int finalize_imm PARAMS ((void));
103 static int process_operands PARAMS ((void));
104 static const seg_entry *build_modrm_byte PARAMS ((void));
105 static void output_insn PARAMS ((void));
106 static void output_branch PARAMS ((void));
107 static void output_jump PARAMS ((void));
108 static void output_interseg_jump PARAMS ((void));
109 static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111 static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
114 static void s_bss PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED);
120 static const char *default_arch = DEFAULT_ARCH;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry *regs;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types[MAX_OPERANDS];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op[MAX_OPERANDS];
157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry *seg[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars = "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars = "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars[] = "#/";
229 const char line_separator_chars[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars[256];
242 static char register_chars[256];
243 static char operand_chars[256];
244 static char identifier_chars[256];
245 static char digit_chars[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack[32];
263 static char *save_stack_p;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates *current_templates;
275 /* Per instruction expressionS buffers: max displacements & immediates. */
276 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
277 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
279 /* Current operand we are working on. */
280 static int this_operand;
282 /* We support four different modes. FLAG_CODE variable is used to distinguish
289 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
291 static enum flag_code flag_code;
292 static unsigned int object_64bit;
293 static int use_rela_relocations = 0;
295 /* The names used to print error messages. */
296 static const char *flag_code_names[] =
303 /* 1 for intel syntax,
305 static int intel_syntax = 0;
307 /* 1 if register prefix % not required. */
308 static int allow_naked_reg = 0;
310 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
311 leave, push, and pop instructions so that gcc has the same stack
312 frame as in 32 bit mode. */
313 static char stackop_size = '\0';
315 /* Non-zero to optimize code alignment. */
316 int optimize_align_code = 1;
318 /* Non-zero to quieten some warnings. */
319 static int quiet_warnings = 0;
322 static const char *cpu_arch_name = NULL;
323 static const char *cpu_sub_arch_name = NULL;
325 /* CPU feature flags. */
326 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
328 /* If we have selected a cpu we are generating instructions for. */
329 static int cpu_arch_tune_set = 0;
331 /* Cpu we are generating instructions for. */
332 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
334 /* CPU feature flags of cpu we are generating instructions for. */
335 static unsigned int cpu_arch_tune_flags = 0;
337 /* CPU instruction set architecture used. */
338 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
340 /* CPU feature flags of instruction set architecture used. */
341 static unsigned int cpu_arch_isa_flags = 0;
343 /* If set, conditional jumps are not automatically promoted to handle
344 larger than a byte offset. */
345 static unsigned int no_cond_jump_promotion = 0;
347 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
348 static symbolS *GOT_symbol;
350 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
351 unsigned int x86_dwarf2_return_column;
353 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
354 int x86_cie_data_alignment;
356 /* Interface to relax_segment.
357 There are 3 major relax states for 386 jump insns because the
358 different types of jumps add different sizes to frags when we're
359 figuring out what sort of jump to choose to reach a given label. */
362 #define UNCOND_JUMP 0
364 #define COND_JUMP86 2
369 #define SMALL16 (SMALL | CODE16)
371 #define BIG16 (BIG | CODE16)
375 #define INLINE __inline__
381 #define ENCODE_RELAX_STATE(type, size) \
382 ((relax_substateT) (((type) << 2) | (size)))
383 #define TYPE_FROM_RELAX_STATE(s) \
385 #define DISP_SIZE_FROM_RELAX_STATE(s) \
386 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
388 /* This table is used by relax_frag to promote short jumps to long
389 ones where necessary. SMALL (short) jumps may be promoted to BIG
390 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
391 don't allow a short jump in a 32 bit code segment to be promoted to
392 a 16 bit offset jump because it's slower (requires data size
393 prefix), and doesn't work, unless the destination is in the bottom
394 64k of the code segment (The top 16 bits of eip are zeroed). */
396 const relax_typeS md_relax_table[] =
399 1) most positive reach of this state,
400 2) most negative reach of this state,
401 3) how many bytes this mode will have in the variable part of the frag
402 4) which index into the table to try if we can't fit into this one. */
404 /* UNCOND_JUMP states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
407 /* dword jmp adds 4 bytes to frag:
408 0 extra opcode bytes, 4 displacement bytes. */
410 /* word jmp adds 2 byte2 to frag:
411 0 extra opcode bytes, 2 displacement bytes. */
414 /* COND_JUMP states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
420 /* word conditionals add 3 bytes to frag:
421 1 extra opcode byte, 2 displacement bytes. */
424 /* COND_JUMP86 states. */
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
426 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
427 /* dword conditionals adds 5 bytes to frag:
428 1 extra opcode byte, 4 displacement bytes. */
430 /* word conditionals add 4 bytes to frag:
431 1 displacement byte and a 3 byte long branch insn. */
435 static const arch_entry cpu_arch[] =
437 {"generic32", PROCESSOR_GENERIC32,
438 Cpu186|Cpu286|Cpu386},
439 {"generic64", PROCESSOR_GENERIC64,
440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
441 |CpuMMX2|CpuSSE|CpuSSE2},
442 {"i8086", PROCESSOR_UNKNOWN,
444 {"i186", PROCESSOR_UNKNOWN,
446 {"i286", PROCESSOR_UNKNOWN,
448 {"i386", PROCESSOR_GENERIC32,
449 Cpu186|Cpu286|Cpu386},
450 {"i486", PROCESSOR_I486,
451 Cpu186|Cpu286|Cpu386|Cpu486},
452 {"i586", PROCESSOR_PENTIUM,
453 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
454 {"i686", PROCESSOR_PENTIUMPRO,
455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
456 {"pentium", PROCESSOR_PENTIUM,
457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
458 {"pentiumpro",PROCESSOR_PENTIUMPRO,
459 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
460 {"pentiumii", PROCESSOR_PENTIUMPRO,
461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
462 {"pentiumiii",PROCESSOR_PENTIUMPRO,
463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
464 {"pentium4", PROCESSOR_PENTIUM4,
465 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
466 |CpuMMX2|CpuSSE|CpuSSE2},
467 {"prescott", PROCESSOR_NOCONA,
468 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
469 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
470 {"nocona", PROCESSOR_NOCONA,
471 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
472 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
473 {"yonah", PROCESSOR_CORE,
474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
475 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
476 {"core", PROCESSOR_CORE,
477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
478 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
479 {"merom", PROCESSOR_CORE2,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
481 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
482 {"core2", PROCESSOR_CORE2,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
484 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
487 {"k6_2", PROCESSOR_K6,
488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
489 {"athlon", PROCESSOR_ATHLON,
490 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
491 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
492 {"sledgehammer", PROCESSOR_K8,
493 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
494 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
495 {"opteron", PROCESSOR_K8,
496 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
497 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
499 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
500 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
501 {"amdfam10", PROCESSOR_AMDFAM10,
502 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
503 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
505 {".mmx", PROCESSOR_UNKNOWN,
507 {".sse", PROCESSOR_UNKNOWN,
508 CpuMMX|CpuMMX2|CpuSSE},
509 {".sse2", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
511 {".sse3", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
513 {".ssse3", PROCESSOR_UNKNOWN,
514 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
515 {".3dnow", PROCESSOR_UNKNOWN,
517 {".3dnowa", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
519 {".padlock", PROCESSOR_UNKNOWN,
521 {".pacifica", PROCESSOR_UNKNOWN,
523 {".svme", PROCESSOR_UNKNOWN,
525 {".sse4a", PROCESSOR_UNKNOWN,
526 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
527 {".abm", PROCESSOR_UNKNOWN,
531 const pseudo_typeS md_pseudo_table[] =
533 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
534 {"align", s_align_bytes, 0},
536 {"align", s_align_ptwo, 0},
538 {"arch", set_cpu_arch, 0},
542 {"ffloat", float_cons, 'f'},
543 {"dfloat", float_cons, 'd'},
544 {"tfloat", float_cons, 'x'},
546 {"slong", signed_cons, 4},
547 {"noopt", s_ignore, 0},
548 {"optim", s_ignore, 0},
549 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
550 {"code16", set_code_flag, CODE_16BIT},
551 {"code32", set_code_flag, CODE_32BIT},
552 {"code64", set_code_flag, CODE_64BIT},
553 {"intel_syntax", set_intel_syntax, 1},
554 {"att_syntax", set_intel_syntax, 0},
555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
556 {"largecomm", handle_large_common, 0},
558 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
559 {"loc", dwarf2_directive_loc, 0},
560 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
563 {"secrel32", pe_directive_secrel, 0},
568 /* For interface with expression (). */
569 extern char *input_line_pointer;
571 /* Hash table for instruction mnemonic lookup. */
572 static struct hash_control *op_hash;
574 /* Hash table for register lookup. */
575 static struct hash_control *reg_hash;
578 i386_align_code (fragP, count)
582 /* Various efficient no-op patterns for aligning code labels.
583 Note: Don't try to assemble the instructions in the comments.
584 0L and 0w are not legal. */
585 static const char f32_1[] =
587 static const char f32_2[] =
588 {0x66,0x90}; /* xchg %ax,%ax */
589 static const char f32_3[] =
590 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
591 static const char f32_4[] =
592 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
593 static const char f32_5[] =
595 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
596 static const char f32_6[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
598 static const char f32_7[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
600 static const char f32_8[] =
602 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
603 static const char f32_9[] =
604 {0x89,0xf6, /* movl %esi,%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_10[] =
607 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_11[] =
610 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_12[] =
613 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
614 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
615 static const char f32_13[] =
616 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
617 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
618 static const char f32_14[] =
619 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
620 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
621 static const char f32_15[] =
622 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
624 static const char f16_3[] =
625 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
626 static const char f16_4[] =
627 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
628 static const char f16_5[] =
630 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
631 static const char f16_6[] =
632 {0x89,0xf6, /* mov %si,%si */
633 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
634 static const char f16_7[] =
635 {0x8d,0x74,0x00, /* lea 0(%si),%si */
636 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
637 static const char f16_8[] =
638 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
639 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
640 static const char *const f32_patt[] = {
641 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
642 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
644 static const char *const f16_patt[] = {
645 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
646 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
649 static const char alt_3[] =
651 /* nopl 0(%[re]ax) */
652 static const char alt_4[] =
653 {0x0f,0x1f,0x40,0x00};
654 /* nopl 0(%[re]ax,%[re]ax,1) */
655 static const char alt_5[] =
656 {0x0f,0x1f,0x44,0x00,0x00};
657 /* nopw 0(%[re]ax,%[re]ax,1) */
658 static const char alt_6[] =
659 {0x66,0x0f,0x1f,0x44,0x00,0x00};
660 /* nopl 0L(%[re]ax) */
661 static const char alt_7[] =
662 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
663 /* nopl 0L(%[re]ax,%[re]ax,1) */
664 static const char alt_8[] =
665 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
666 /* nopw 0L(%[re]ax,%[re]ax,1) */
667 static const char alt_9[] =
668 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_10[] =
671 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_11[] =
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
679 nopw %cs:0L(%[re]ax,%[re]ax,1) */
680 static const char alt_long_12[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_13[] =
692 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
697 nopw %cs:0L(%[re]ax,%[re]ax,1) */
698 static const char alt_long_14[] =
703 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
709 nopw %cs:0L(%[re]ax,%[re]ax,1) */
710 static const char alt_long_15[] =
716 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
717 /* nopl 0(%[re]ax,%[re]ax,1)
718 nopw 0(%[re]ax,%[re]ax,1) */
719 static const char alt_short_11[] =
720 {0x0f,0x1f,0x44,0x00,0x00,
721 0x66,0x0f,0x1f,0x44,0x00,0x00};
722 /* nopw 0(%[re]ax,%[re]ax,1)
723 nopw 0(%[re]ax,%[re]ax,1) */
724 static const char alt_short_12[] =
725 {0x66,0x0f,0x1f,0x44,0x00,0x00,
726 0x66,0x0f,0x1f,0x44,0x00,0x00};
727 /* nopw 0(%[re]ax,%[re]ax,1)
729 static const char alt_short_13[] =
730 {0x66,0x0f,0x1f,0x44,0x00,0x00,
731 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
734 static const char alt_short_14[] =
735 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
736 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
738 nopl 0L(%[re]ax,%[re]ax,1) */
739 static const char alt_short_15[] =
740 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
741 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
742 static const char *const alt_short_patt[] = {
743 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
744 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
745 alt_short_14, alt_short_15
747 static const char *const alt_long_patt[] = {
748 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
749 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
750 alt_long_14, alt_long_15
753 if (count <= 0 || count > 15)
756 /* We need to decide which NOP sequence to use for 32bit and
757 64bit. When -mtune= is used:
759 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
760 f32_patt will be used.
761 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
762 3. For PROCESSOR_CORE2, alt_long_patt will be used.
763 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
764 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
765 and PROCESSOR_GENERIC64, alt_short_patt will be used.
767 When -mtune= isn't used, alt_short_patt will be used if
768 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
770 When -march= or .arch is used, we can't use anything beyond
771 cpu_arch_isa_flags. */
773 if (flag_code == CODE_16BIT)
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
778 /* Adjust jump offset. */
779 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
781 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
784 int nnops = (count + 3) / 4;
785 int len = count / nnops;
786 int remains = count - nnops * len;
789 /* The recommended way to pad 64bit code is to use NOPs preceded
790 by maximally four 0x66 prefixes. Balance the size of nops. */
791 for (i = 0; i < remains; i++)
793 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
794 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
797 for (; i < nnops; i++)
799 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
800 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
806 const char *const *patt = NULL;
808 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
810 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
811 switch (cpu_arch_tune)
813 case PROCESSOR_UNKNOWN:
814 /* We use cpu_arch_isa_flags to check if we SHOULD
815 optimize for Cpu686. */
816 if ((cpu_arch_isa_flags & Cpu686) != 0)
817 patt = alt_short_patt;
821 case PROCESSOR_CORE2:
822 patt = alt_long_patt;
824 case PROCESSOR_PENTIUMPRO:
825 case PROCESSOR_PENTIUM4:
826 case PROCESSOR_NOCONA:
829 case PROCESSOR_ATHLON:
831 case PROCESSOR_GENERIC64:
832 case PROCESSOR_AMDFAM10:
833 patt = alt_short_patt;
836 case PROCESSOR_PENTIUM:
837 case PROCESSOR_GENERIC32:
844 switch (cpu_arch_tune)
846 case PROCESSOR_UNKNOWN:
847 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
848 PROCESSOR_UNKNOWN. */
853 case PROCESSOR_PENTIUM:
854 case PROCESSOR_PENTIUMPRO:
855 case PROCESSOR_PENTIUM4:
856 case PROCESSOR_NOCONA:
859 case PROCESSOR_ATHLON:
861 case PROCESSOR_AMDFAM10:
862 case PROCESSOR_GENERIC32:
863 /* We use cpu_arch_isa_flags to check if we CAN optimize
865 if ((cpu_arch_isa_flags & Cpu686) != 0)
866 patt = alt_short_patt;
870 case PROCESSOR_CORE2:
871 if ((cpu_arch_isa_flags & Cpu686) != 0)
872 patt = alt_long_patt;
876 case PROCESSOR_GENERIC64:
877 patt = alt_short_patt;
882 memcpy (fragP->fr_literal + fragP->fr_fix,
883 patt[count - 1], count);
885 fragP->fr_var = count;
888 static INLINE unsigned int
889 mode_from_disp_size (t)
892 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
896 fits_in_signed_byte (num)
899 return (num >= -128) && (num <= 127);
903 fits_in_unsigned_byte (num)
906 return (num & 0xff) == num;
910 fits_in_unsigned_word (num)
913 return (num & 0xffff) == num;
917 fits_in_signed_word (num)
920 return (-32768 <= num) && (num <= 32767);
924 fits_in_signed_long (num)
925 offsetT num ATTRIBUTE_UNUSED;
930 return (!(((offsetT) -1 << 31) & num)
931 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
933 } /* fits_in_signed_long() */
936 fits_in_unsigned_long (num)
937 offsetT num ATTRIBUTE_UNUSED;
942 return (num & (((offsetT) 2 << 31) - 1)) == num;
944 } /* fits_in_unsigned_long() */
947 smallest_imm_type (num)
950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
960 return (fits_in_signed_byte (num)
961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
962 : fits_in_unsigned_byte (num)
963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
974 offset_in_range (val, size)
982 case 1: mask = ((addressT) 1 << 8) - 1; break;
983 case 2: mask = ((addressT) 1 << 16) - 1; break;
984 case 4: mask = ((addressT) 2 << 31) - 1; break;
986 case 8: mask = ((addressT) 2 << 63) - 1; break;
991 /* If BFD64, sign extend val. */
992 if (!use_rela_relocations)
993 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
994 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
996 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
998 char buf1[40], buf2[40];
1000 sprint_value (buf1, val);
1001 sprint_value (buf2, val & mask);
1002 as_warn (_("%s shortened to %s"), buf1, buf2);
1007 /* Returns 0 if attempting to add a prefix where one from the same
1008 class already exists, 1 if non rep/repne added, 2 if rep/repne
1012 unsigned int prefix;
1017 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1018 && flag_code == CODE_64BIT)
1020 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1021 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1022 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1033 case CS_PREFIX_OPCODE:
1034 case DS_PREFIX_OPCODE:
1035 case ES_PREFIX_OPCODE:
1036 case FS_PREFIX_OPCODE:
1037 case GS_PREFIX_OPCODE:
1038 case SS_PREFIX_OPCODE:
1042 case REPNE_PREFIX_OPCODE:
1043 case REPE_PREFIX_OPCODE:
1046 case LOCK_PREFIX_OPCODE:
1054 case ADDR_PREFIX_OPCODE:
1058 case DATA_PREFIX_OPCODE:
1062 if (i.prefix[q] != 0)
1070 i.prefix[q] |= prefix;
1073 as_bad (_("same type of prefix used twice"));
1079 set_code_flag (value)
1083 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1084 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1085 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1087 as_bad (_("64bit mode not supported on this CPU."));
1089 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1091 as_bad (_("32bit mode not supported on this CPU."));
1093 stackop_size = '\0';
1097 set_16bit_gcc_code_flag (new_code_flag)
1100 flag_code = new_code_flag;
1101 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1102 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1103 stackop_size = LONG_MNEM_SUFFIX;
1107 set_intel_syntax (syntax_flag)
1110 /* Find out if register prefixing is specified. */
1111 int ask_naked_reg = 0;
1114 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1116 char *string = input_line_pointer;
1117 int e = get_symbol_end ();
1119 if (strcmp (string, "prefix") == 0)
1121 else if (strcmp (string, "noprefix") == 0)
1124 as_bad (_("bad argument to syntax directive."));
1125 *input_line_pointer = e;
1127 demand_empty_rest_of_line ();
1129 intel_syntax = syntax_flag;
1131 if (ask_naked_reg == 0)
1132 allow_naked_reg = (intel_syntax
1133 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1135 allow_naked_reg = (ask_naked_reg < 0);
1137 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1138 identifier_chars['$'] = intel_syntax ? '$' : 0;
1142 set_cpu_arch (dummy)
1143 int dummy ATTRIBUTE_UNUSED;
1147 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1149 char *string = input_line_pointer;
1150 int e = get_symbol_end ();
1153 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1155 if (strcmp (string, cpu_arch[i].name) == 0)
1159 cpu_arch_name = cpu_arch[i].name;
1160 cpu_sub_arch_name = NULL;
1161 cpu_arch_flags = (cpu_arch[i].flags
1162 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1163 cpu_arch_isa = cpu_arch[i].type;
1164 cpu_arch_isa_flags = cpu_arch[i].flags;
1165 if (!cpu_arch_tune_set)
1167 cpu_arch_tune = cpu_arch_isa;
1168 cpu_arch_tune_flags = cpu_arch_isa_flags;
1172 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1174 cpu_sub_arch_name = cpu_arch[i].name;
1175 cpu_arch_flags |= cpu_arch[i].flags;
1177 *input_line_pointer = e;
1178 demand_empty_rest_of_line ();
1182 if (i >= ARRAY_SIZE (cpu_arch))
1183 as_bad (_("no such architecture: `%s'"), string);
1185 *input_line_pointer = e;
1188 as_bad (_("missing cpu architecture"));
1190 no_cond_jump_promotion = 0;
1191 if (*input_line_pointer == ','
1192 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1194 char *string = ++input_line_pointer;
1195 int e = get_symbol_end ();
1197 if (strcmp (string, "nojumps") == 0)
1198 no_cond_jump_promotion = 1;
1199 else if (strcmp (string, "jumps") == 0)
1202 as_bad (_("no such architecture modifier: `%s'"), string);
1204 *input_line_pointer = e;
1207 demand_empty_rest_of_line ();
1213 if (!strcmp (default_arch, "x86_64"))
1214 return bfd_mach_x86_64;
1215 else if (!strcmp (default_arch, "i386"))
1216 return bfd_mach_i386_i386;
1218 as_fatal (_("Unknown architecture"));
1224 const char *hash_err;
1226 /* Initialize op_hash hash table. */
1227 op_hash = hash_new ();
1230 const template *optab;
1231 templates *core_optab;
1233 /* Setup for loop. */
1235 core_optab = (templates *) xmalloc (sizeof (templates));
1236 core_optab->start = optab;
1241 if (optab->name == NULL
1242 || strcmp (optab->name, (optab - 1)->name) != 0)
1244 /* different name --> ship out current template list;
1245 add to hash table; & begin anew. */
1246 core_optab->end = optab;
1247 hash_err = hash_insert (op_hash,
1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1256 if (optab->name == NULL)
1258 core_optab = (templates *) xmalloc (sizeof (templates));
1259 core_optab->start = optab;
1264 /* Initialize reg_hash hash table. */
1265 reg_hash = hash_new ();
1267 const reg_entry *regtab;
1269 for (regtab = i386_regtab;
1270 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1273 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1275 as_fatal (_("Internal Error: Can't hash %s: %s"),
1281 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1286 for (c = 0; c < 256; c++)
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1295 else if (ISLOWER (c))
1297 mnemonic_chars[c] = c;
1298 register_chars[c] = c;
1299 operand_chars[c] = c;
1301 else if (ISUPPER (c))
1303 mnemonic_chars[c] = TOLOWER (c);
1304 register_chars[c] = mnemonic_chars[c];
1305 operand_chars[c] = c;
1308 if (ISALPHA (c) || ISDIGIT (c))
1309 identifier_chars[c] = c;
1312 identifier_chars[c] = c;
1313 operand_chars[c] = c;
1318 identifier_chars['@'] = '@';
1321 identifier_chars['?'] = '?';
1322 operand_chars['?'] = '?';
1324 digit_chars['-'] = '-';
1325 mnemonic_chars['-'] = '-';
1326 identifier_chars['_'] = '_';
1327 identifier_chars['.'] = '.';
1329 for (p = operand_special_chars; *p != '\0'; p++)
1330 operand_chars[(unsigned char) *p] = *p;
1333 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1336 record_alignment (text_section, 2);
1337 record_alignment (data_section, 2);
1338 record_alignment (bss_section, 2);
1342 if (flag_code == CODE_64BIT)
1344 x86_dwarf2_return_column = 16;
1345 x86_cie_data_alignment = -8;
1349 x86_dwarf2_return_column = 8;
1350 x86_cie_data_alignment = -4;
1355 i386_print_statistics (file)
1358 hash_print_statistics (file, "i386 opcode", op_hash);
1359 hash_print_statistics (file, "i386 register", reg_hash);
1364 /* Debugging routines for md_assemble. */
1365 static void pi PARAMS ((char *, i386_insn *));
1366 static void pte PARAMS ((template *));
1367 static void pt PARAMS ((unsigned int));
1368 static void pe PARAMS ((expressionS *));
1369 static void ps PARAMS ((symbolS *));
1378 fprintf (stdout, "%s: template ", line);
1380 fprintf (stdout, " address: base %s index %s scale %x\n",
1381 x->base_reg ? x->base_reg->reg_name : "none",
1382 x->index_reg ? x->index_reg->reg_name : "none",
1383 x->log2_scale_factor);
1384 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1385 x->rm.mode, x->rm.reg, x->rm.regmem);
1386 fprintf (stdout, " sib: base %x index %x scale %x\n",
1387 x->sib.base, x->sib.index, x->sib.scale);
1388 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1389 (x->rex & REX_MODE64) != 0,
1390 (x->rex & REX_EXTX) != 0,
1391 (x->rex & REX_EXTY) != 0,
1392 (x->rex & REX_EXTZ) != 0);
1393 for (i = 0; i < x->operands; i++)
1395 fprintf (stdout, " #%d: ", i + 1);
1397 fprintf (stdout, "\n");
1399 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1400 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1401 if (x->types[i] & Imm)
1403 if (x->types[i] & Disp)
1404 pe (x->op[i].disps);
1413 fprintf (stdout, " %d operands ", t->operands);
1414 fprintf (stdout, "opcode %x ", t->base_opcode);
1415 if (t->extension_opcode != None)
1416 fprintf (stdout, "ext %x ", t->extension_opcode);
1417 if (t->opcode_modifier & D)
1418 fprintf (stdout, "D");
1419 if (t->opcode_modifier & W)
1420 fprintf (stdout, "W");
1421 fprintf (stdout, "\n");
1422 for (i = 0; i < t->operands; i++)
1424 fprintf (stdout, " #%d type ", i + 1);
1425 pt (t->operand_types[i]);
1426 fprintf (stdout, "\n");
1434 fprintf (stdout, " operation %d\n", e->X_op);
1435 fprintf (stdout, " add_number %ld (%lx)\n",
1436 (long) e->X_add_number, (long) e->X_add_number);
1437 if (e->X_add_symbol)
1439 fprintf (stdout, " add_symbol ");
1440 ps (e->X_add_symbol);
1441 fprintf (stdout, "\n");
1445 fprintf (stdout, " op_symbol ");
1446 ps (e->X_op_symbol);
1447 fprintf (stdout, "\n");
1455 fprintf (stdout, "%s type %s%s",
1457 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1458 segment_name (S_GET_SEGMENT (s)));
1461 static struct type_name
1466 const type_names[] =
1479 { BaseIndex, "BaseIndex" },
1483 { Disp32S, "d32s" },
1485 { InOutPortReg, "InOutPortReg" },
1486 { ShiftCount, "ShiftCount" },
1487 { Control, "control reg" },
1488 { Test, "test reg" },
1489 { Debug, "debug reg" },
1490 { FloatReg, "FReg" },
1491 { FloatAcc, "FAcc" },
1495 { JumpAbsolute, "Jump Absolute" },
1506 const struct type_name *ty;
1508 for (ty = type_names; ty->mask; ty++)
1510 fprintf (stdout, "%s, ", ty->tname);
1514 #endif /* DEBUG386 */
1516 static bfd_reloc_code_real_type
1517 reloc (unsigned int size,
1520 bfd_reloc_code_real_type other)
1522 if (other != NO_RELOC)
1524 reloc_howto_type *reloc;
1529 case BFD_RELOC_X86_64_GOT32:
1530 return BFD_RELOC_X86_64_GOT64;
1532 case BFD_RELOC_X86_64_PLTOFF64:
1533 return BFD_RELOC_X86_64_PLTOFF64;
1535 case BFD_RELOC_X86_64_GOTPC32:
1536 other = BFD_RELOC_X86_64_GOTPC64;
1538 case BFD_RELOC_X86_64_GOTPCREL:
1539 other = BFD_RELOC_X86_64_GOTPCREL64;
1541 case BFD_RELOC_X86_64_TPOFF32:
1542 other = BFD_RELOC_X86_64_TPOFF64;
1544 case BFD_RELOC_X86_64_DTPOFF32:
1545 other = BFD_RELOC_X86_64_DTPOFF64;
1551 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1552 if (size == 4 && flag_code != CODE_64BIT)
1555 reloc = bfd_reloc_type_lookup (stdoutput, other);
1557 as_bad (_("unknown relocation (%u)"), other);
1558 else if (size != bfd_get_reloc_size (reloc))
1559 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1560 bfd_get_reloc_size (reloc),
1562 else if (pcrel && !reloc->pc_relative)
1563 as_bad (_("non-pc-relative relocation for pc-relative field"));
1564 else if ((reloc->complain_on_overflow == complain_overflow_signed
1566 || (reloc->complain_on_overflow == complain_overflow_unsigned
1568 as_bad (_("relocated field and relocation type differ in signedness"));
1577 as_bad (_("there are no unsigned pc-relative relocations"));
1580 case 1: return BFD_RELOC_8_PCREL;
1581 case 2: return BFD_RELOC_16_PCREL;
1582 case 4: return BFD_RELOC_32_PCREL;
1583 case 8: return BFD_RELOC_64_PCREL;
1585 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1592 case 4: return BFD_RELOC_X86_64_32S;
1597 case 1: return BFD_RELOC_8;
1598 case 2: return BFD_RELOC_16;
1599 case 4: return BFD_RELOC_32;
1600 case 8: return BFD_RELOC_64;
1602 as_bad (_("cannot do %s %u byte relocation"),
1603 sign > 0 ? "signed" : "unsigned", size);
1607 return BFD_RELOC_NONE;
1610 /* Here we decide which fixups can be adjusted to make them relative to
1611 the beginning of the section instead of the symbol. Basically we need
1612 to make sure that the dynamic relocations are done correctly, so in
1613 some cases we force the original symbol to be used. */
1616 tc_i386_fix_adjustable (fixP)
1617 fixS *fixP ATTRIBUTE_UNUSED;
1619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1623 /* Don't adjust pc-relative references to merge sections in 64-bit
1625 if (use_rela_relocations
1626 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1630 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1631 and changed later by validate_fix. */
1632 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1633 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1636 /* adjust_reloc_syms doesn't know about the GOT. */
1637 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1638 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1639 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1647 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1648 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1649 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1650 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1652 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1653 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1654 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1656 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1658 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1661 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1662 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1663 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1664 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1670 static int intel_float_operand PARAMS ((const char *mnemonic));
1673 intel_float_operand (mnemonic)
1674 const char *mnemonic;
1676 /* Note that the value returned is meaningful only for opcodes with (memory)
1677 operands, hence the code here is free to improperly handle opcodes that
1678 have no operands (for better performance and smaller code). */
1680 if (mnemonic[0] != 'f')
1681 return 0; /* non-math */
1683 switch (mnemonic[1])
1685 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1686 the fs segment override prefix not currently handled because no
1687 call path can make opcodes without operands get here */
1689 return 2 /* integer op */;
1691 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1692 return 3; /* fldcw/fldenv */
1695 if (mnemonic[2] != 'o' /* fnop */)
1696 return 3; /* non-waiting control op */
1699 if (mnemonic[2] == 's')
1700 return 3; /* frstor/frstpm */
1703 if (mnemonic[2] == 'a')
1704 return 3; /* fsave */
1705 if (mnemonic[2] == 't')
1707 switch (mnemonic[3])
1709 case 'c': /* fstcw */
1710 case 'd': /* fstdw */
1711 case 'e': /* fstenv */
1712 case 's': /* fsts[gw] */
1718 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1719 return 0; /* fxsave/fxrstor are not really math ops */
1726 /* This is the guts of the machine-dependent assembler. LINE points to a
1727 machine dependent instruction. This function is supposed to emit
1728 the frags/bytes it assembles to. */
1735 char mnemonic[MAX_MNEM_SIZE];
1737 /* Initialize globals. */
1738 memset (&i, '\0', sizeof (i));
1739 for (j = 0; j < MAX_OPERANDS; j++)
1740 i.reloc[j] = NO_RELOC;
1741 memset (disp_expressions, '\0', sizeof (disp_expressions));
1742 memset (im_expressions, '\0', sizeof (im_expressions));
1743 save_stack_p = save_stack;
1745 /* First parse an instruction mnemonic & call i386_operand for the operands.
1746 We assume that the scrubber has arranged it so that line[0] is the valid
1747 start of a (possibly prefixed) mnemonic. */
1749 line = parse_insn (line, mnemonic);
1753 line = parse_operands (line, mnemonic);
1757 /* The order of the immediates should be reversed
1758 for 2 immediates extrq and insertq instructions */
1759 if ((i.imm_operands == 2) &&
1760 ((strcmp (mnemonic, "extrq") == 0)
1761 || (strcmp (mnemonic, "insertq") == 0)))
1763 swap_imm_operands ();
1764 /* "extrq" and insertq" are the only two instructions whose operands
1765 have to be reversed even though they have two immediate operands.
1771 /* Now we've parsed the mnemonic into a set of templates, and have the
1772 operands at hand. */
1774 /* All intel opcodes have reversed operands except for "bound" and
1775 "enter". We also don't reverse intersegment "jmp" and "call"
1776 instructions with 2 immediate operands so that the immediate segment
1777 precedes the offset, as it does when in AT&T mode. */
1778 if (intel_syntax && i.operands > 1
1779 && (strcmp (mnemonic, "bound") != 0)
1780 && (strcmp (mnemonic, "invlpga") != 0)
1781 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1787 /* Don't optimize displacement for movabs since it only takes 64bit
1790 && (flag_code != CODE_64BIT
1791 || strcmp (mnemonic, "movabs") != 0))
1794 /* Next, we find a template that matches the given insn,
1795 making sure the overlap of the given operands types is consistent
1796 with the template operand types. */
1798 if (!match_template ())
1803 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1805 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1806 i.tm.base_opcode ^= FloatR;
1808 /* Zap movzx and movsx suffix. The suffix may have been set from
1809 "word ptr" or "byte ptr" on the source operand, but we'll use
1810 the suffix later to choose the destination register. */
1811 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1813 if (i.reg_operands < 2
1815 && (~i.tm.opcode_modifier
1822 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1828 if (i.tm.opcode_modifier & FWait)
1829 if (!add_prefix (FWAIT_OPCODE))
1832 /* Check string instruction segment overrides. */
1833 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1835 if (!check_string ())
1839 if (!process_suffix ())
1842 /* Make still unresolved immediate matches conform to size of immediate
1843 given in i.suffix. */
1844 if (!finalize_imm ())
1847 if (i.types[0] & Imm1)
1848 i.imm_operands = 0; /* kludge for shift insns. */
1849 if (i.types[0] & ImplicitRegister)
1851 if (i.types[1] & ImplicitRegister)
1853 if (i.types[2] & ImplicitRegister)
1856 if (i.tm.opcode_modifier & ImmExt)
1860 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1862 /* Streaming SIMD extensions 3 Instructions have the fixed
1863 operands with an opcode suffix which is coded in the same
1864 place as an 8-bit immediate field would be. Here we check
1865 those operands and remove them afterwards. */
1868 for (x = 0; x < i.operands; x++)
1869 if (i.op[x].regs->reg_num != x)
1870 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1871 i.op[x].regs->reg_name, x + 1, i.tm.name);
1875 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1876 opcode suffix which is coded in the same place as an 8-bit
1877 immediate field would be. Here we fake an 8-bit immediate
1878 operand from the opcode suffix stored in tm.extension_opcode. */
1880 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1882 exp = &im_expressions[i.imm_operands++];
1883 i.op[i.operands].imms = exp;
1884 i.types[i.operands++] = Imm8;
1885 exp->X_op = O_constant;
1886 exp->X_add_number = i.tm.extension_opcode;
1887 i.tm.extension_opcode = None;
1890 /* For insns with operands there are more diddles to do to the opcode. */
1893 if (!process_operands ())
1896 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1898 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1899 as_warn (_("translating to `%sp'"), i.tm.name);
1902 /* Handle conversion of 'int $3' --> special int3 insn. */
1903 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1905 i.tm.base_opcode = INT3_OPCODE;
1909 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1910 && i.op[0].disps->X_op == O_constant)
1912 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1913 the absolute address given by the constant. Since ix86 jumps and
1914 calls are pc relative, we need to generate a reloc. */
1915 i.op[0].disps->X_add_symbol = &abs_symbol;
1916 i.op[0].disps->X_op = O_symbol;
1919 if ((i.tm.opcode_modifier & Rex64) != 0)
1920 i.rex |= REX_MODE64;
1922 /* For 8 bit registers we need an empty rex prefix. Also if the
1923 instruction already has a prefix, we need to convert old
1924 registers to new ones. */
1926 if (((i.types[0] & Reg8) != 0
1927 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1928 || ((i.types[1] & Reg8) != 0
1929 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1930 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1935 i.rex |= REX_OPCODE;
1936 for (x = 0; x < 2; x++)
1938 /* Look for 8 bit operand that uses old registers. */
1939 if ((i.types[x] & Reg8) != 0
1940 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1942 /* In case it is "hi" register, give up. */
1943 if (i.op[x].regs->reg_num > 3)
1944 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1945 i.op[x].regs->reg_name);
1947 /* Otherwise it is equivalent to the extended register.
1948 Since the encoding doesn't change this is merely
1949 cosmetic cleanup for debug output. */
1951 i.op[x].regs = i.op[x].regs + 8;
1957 add_prefix (REX_OPCODE | i.rex);
1959 /* We are ready to output the insn. */
1964 parse_insn (line, mnemonic)
1969 char *token_start = l;
1974 /* Non-zero if we found a prefix only acceptable with string insns. */
1975 const char *expecting_string_instruction = NULL;
1980 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1983 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1985 as_bad (_("no such instruction: `%s'"), token_start);
1990 if (!is_space_char (*l)
1991 && *l != END_OF_INSN
1993 || (*l != PREFIX_SEPARATOR
1996 as_bad (_("invalid character %s in mnemonic"),
1997 output_invalid (*l));
2000 if (token_start == l)
2002 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2003 as_bad (_("expecting prefix; got nothing"));
2005 as_bad (_("expecting mnemonic; got nothing"));
2009 /* Look up instruction (or prefix) via hash table. */
2010 current_templates = hash_find (op_hash, mnemonic);
2012 if (*l != END_OF_INSN
2013 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2014 && current_templates
2015 && (current_templates->start->opcode_modifier & IsPrefix))
2017 if (current_templates->start->cpu_flags
2018 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2020 as_bad ((flag_code != CODE_64BIT
2021 ? _("`%s' is only supported in 64-bit mode")
2022 : _("`%s' is not supported in 64-bit mode")),
2023 current_templates->start->name);
2026 /* If we are in 16-bit mode, do not allow addr16 or data16.
2027 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2028 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2029 && flag_code != CODE_64BIT
2030 && (((current_templates->start->opcode_modifier & Size32) != 0)
2031 ^ (flag_code == CODE_16BIT)))
2033 as_bad (_("redundant %s prefix"),
2034 current_templates->start->name);
2037 /* Add prefix, checking for repeated prefixes. */
2038 switch (add_prefix (current_templates->start->base_opcode))
2043 expecting_string_instruction = current_templates->start->name;
2046 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2053 if (!current_templates)
2055 /* See if we can get a match by trimming off a suffix. */
2058 case WORD_MNEM_SUFFIX:
2059 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2060 i.suffix = SHORT_MNEM_SUFFIX;
2062 case BYTE_MNEM_SUFFIX:
2063 case QWORD_MNEM_SUFFIX:
2064 i.suffix = mnem_p[-1];
2066 current_templates = hash_find (op_hash, mnemonic);
2068 case SHORT_MNEM_SUFFIX:
2069 case LONG_MNEM_SUFFIX:
2072 i.suffix = mnem_p[-1];
2074 current_templates = hash_find (op_hash, mnemonic);
2082 if (intel_float_operand (mnemonic) == 1)
2083 i.suffix = SHORT_MNEM_SUFFIX;
2085 i.suffix = LONG_MNEM_SUFFIX;
2087 current_templates = hash_find (op_hash, mnemonic);
2091 if (!current_templates)
2093 as_bad (_("no such instruction: `%s'"), token_start);
2098 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2100 /* Check for a branch hint. We allow ",pt" and ",pn" for
2101 predict taken and predict not taken respectively.
2102 I'm not sure that branch hints actually do anything on loop
2103 and jcxz insns (JumpByte) for current Pentium4 chips. They
2104 may work in the future and it doesn't hurt to accept them
2106 if (l[0] == ',' && l[1] == 'p')
2110 if (!add_prefix (DS_PREFIX_OPCODE))
2114 else if (l[2] == 'n')
2116 if (!add_prefix (CS_PREFIX_OPCODE))
2122 /* Any other comma loses. */
2125 as_bad (_("invalid character %s in mnemonic"),
2126 output_invalid (*l));
2130 /* Check if instruction is supported on specified architecture. */
2132 for (t = current_templates->start; t < current_templates->end; ++t)
2134 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2135 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2137 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2140 if (!(supported & 2))
2142 as_bad (flag_code == CODE_64BIT
2143 ? _("`%s' is not supported in 64-bit mode")
2144 : _("`%s' is only supported in 64-bit mode"),
2145 current_templates->start->name);
2148 if (!(supported & 1))
2150 as_warn (_("`%s' is not supported on `%s%s'"),
2151 current_templates->start->name,
2153 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2155 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2157 as_warn (_("use .code16 to ensure correct addressing mode"));
2160 /* Check for rep/repne without a string instruction. */
2161 if (expecting_string_instruction)
2163 static templates override;
2165 for (t = current_templates->start; t < current_templates->end; ++t)
2166 if (t->opcode_modifier & IsString)
2168 if (t >= current_templates->end)
2170 as_bad (_("expecting string instruction after `%s'"),
2171 expecting_string_instruction);
2174 for (override.start = t; t < current_templates->end; ++t)
2175 if (!(t->opcode_modifier & IsString))
2178 current_templates = &override;
2185 parse_operands (l, mnemonic)
2187 const char *mnemonic;
2191 /* 1 if operand is pending after ','. */
2192 unsigned int expecting_operand = 0;
2194 /* Non-zero if operand parens not balanced. */
2195 unsigned int paren_not_balanced;
2197 while (*l != END_OF_INSN)
2199 /* Skip optional white space before operand. */
2200 if (is_space_char (*l))
2202 if (!is_operand_char (*l) && *l != END_OF_INSN)
2204 as_bad (_("invalid character %s before operand %d"),
2205 output_invalid (*l),
2209 token_start = l; /* after white space */
2210 paren_not_balanced = 0;
2211 while (paren_not_balanced || *l != ',')
2213 if (*l == END_OF_INSN)
2215 if (paren_not_balanced)
2218 as_bad (_("unbalanced parenthesis in operand %d."),
2221 as_bad (_("unbalanced brackets in operand %d."),
2226 break; /* we are done */
2228 else if (!is_operand_char (*l) && !is_space_char (*l))
2230 as_bad (_("invalid character %s in operand %d"),
2231 output_invalid (*l),
2238 ++paren_not_balanced;
2240 --paren_not_balanced;
2245 ++paren_not_balanced;
2247 --paren_not_balanced;
2251 if (l != token_start)
2252 { /* Yes, we've read in another operand. */
2253 unsigned int operand_ok;
2254 this_operand = i.operands++;
2255 if (i.operands > MAX_OPERANDS)
2257 as_bad (_("spurious operands; (%d operands/instruction max)"),
2261 /* Now parse operand adding info to 'i' as we go along. */
2262 END_STRING_AND_SAVE (l);
2266 i386_intel_operand (token_start,
2267 intel_float_operand (mnemonic));
2269 operand_ok = i386_operand (token_start);
2271 RESTORE_END_STRING (l);
2277 if (expecting_operand)
2279 expecting_operand_after_comma:
2280 as_bad (_("expecting operand after ','; got nothing"));
2285 as_bad (_("expecting operand before ','; got nothing"));
2290 /* Now *l must be either ',' or END_OF_INSN. */
2293 if (*++l == END_OF_INSN)
2295 /* Just skip it, if it's \n complain. */
2296 goto expecting_operand_after_comma;
2298 expecting_operand = 1;
2305 swap_imm_operands ()
2307 union i386_op temp_op;
2308 unsigned int temp_type;
2309 enum bfd_reloc_code_real temp_reloc;
2313 temp_type = i.types[xchg2];
2314 i.types[xchg2] = i.types[xchg1];
2315 i.types[xchg1] = temp_type;
2316 temp_op = i.op[xchg2];
2317 i.op[xchg2] = i.op[xchg1];
2318 i.op[xchg1] = temp_op;
2319 temp_reloc = i.reloc[xchg2];
2320 i.reloc[xchg2] = i.reloc[xchg1];
2321 i.reloc[xchg1] = temp_reloc;
2328 union i386_op temp_op;
2329 unsigned int temp_type;
2330 enum bfd_reloc_code_real temp_reloc;
2334 if (i.operands == 4)
2335 /* There will be two exchanges in a 4 operand instruction.
2336 First exchange is the done inside this block.(1st and 4rth operand)
2337 The next exchange is done outside this block.(2nd and 3rd operand) */
2341 temp_type = i.types[xchg2];
2342 i.types[xchg2] = i.types[xchg1];
2343 i.types[xchg1] = temp_type;
2344 temp_op = i.op[xchg2];
2345 i.op[xchg2] = i.op[xchg1];
2346 i.op[xchg1] = temp_op;
2347 temp_reloc = i.reloc[xchg2];
2348 i.reloc[xchg2] = i.reloc[xchg1];
2349 i.reloc[xchg1] = temp_reloc;
2354 if (i.operands == 2)
2359 else if (i.operands == 3)
2364 temp_type = i.types[xchg2];
2365 i.types[xchg2] = i.types[xchg1];
2366 i.types[xchg1] = temp_type;
2367 temp_op = i.op[xchg2];
2368 i.op[xchg2] = i.op[xchg1];
2369 i.op[xchg1] = temp_op;
2370 temp_reloc = i.reloc[xchg2];
2371 i.reloc[xchg2] = i.reloc[xchg1];
2372 i.reloc[xchg1] = temp_reloc;
2374 if (i.mem_operands == 2)
2376 const seg_entry *temp_seg;
2377 temp_seg = i.seg[0];
2378 i.seg[0] = i.seg[1];
2379 i.seg[1] = temp_seg;
2383 /* Try to ensure constant immediates are represented in the smallest
2388 char guess_suffix = 0;
2392 guess_suffix = i.suffix;
2393 else if (i.reg_operands)
2395 /* Figure out a suffix from the last register operand specified.
2396 We can't do this properly yet, ie. excluding InOutPortReg,
2397 but the following works for instructions with immediates.
2398 In any case, we can't set i.suffix yet. */
2399 for (op = i.operands; --op >= 0;)
2400 if (i.types[op] & Reg)
2402 if (i.types[op] & Reg8)
2403 guess_suffix = BYTE_MNEM_SUFFIX;
2404 else if (i.types[op] & Reg16)
2405 guess_suffix = WORD_MNEM_SUFFIX;
2406 else if (i.types[op] & Reg32)
2407 guess_suffix = LONG_MNEM_SUFFIX;
2408 else if (i.types[op] & Reg64)
2409 guess_suffix = QWORD_MNEM_SUFFIX;
2413 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2414 guess_suffix = WORD_MNEM_SUFFIX;
2416 for (op = i.operands; --op >= 0;)
2417 if (i.types[op] & Imm)
2419 switch (i.op[op].imms->X_op)
2422 /* If a suffix is given, this operand may be shortened. */
2423 switch (guess_suffix)
2425 case LONG_MNEM_SUFFIX:
2426 i.types[op] |= Imm32 | Imm64;
2428 case WORD_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2431 case BYTE_MNEM_SUFFIX:
2432 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2436 /* If this operand is at most 16 bits, convert it
2437 to a signed 16 bit number before trying to see
2438 whether it will fit in an even smaller size.
2439 This allows a 16-bit operand such as $0xffe0 to
2440 be recognised as within Imm8S range. */
2441 if ((i.types[op] & Imm16)
2442 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2444 i.op[op].imms->X_add_number =
2445 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2447 if ((i.types[op] & Imm32)
2448 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2451 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2452 ^ ((offsetT) 1 << 31))
2453 - ((offsetT) 1 << 31));
2455 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2457 /* We must avoid matching of Imm32 templates when 64bit
2458 only immediate is available. */
2459 if (guess_suffix == QWORD_MNEM_SUFFIX)
2460 i.types[op] &= ~Imm32;
2467 /* Symbols and expressions. */
2469 /* Convert symbolic operand to proper sizes for matching, but don't
2470 prevent matching a set of insns that only supports sizes other
2471 than those matching the insn suffix. */
2473 unsigned int mask, allowed = 0;
2476 for (t = current_templates->start; t < current_templates->end; ++t)
2477 allowed |= t->operand_types[op];
2478 switch (guess_suffix)
2480 case QWORD_MNEM_SUFFIX:
2481 mask = Imm64 | Imm32S;
2483 case LONG_MNEM_SUFFIX:
2486 case WORD_MNEM_SUFFIX:
2489 case BYTE_MNEM_SUFFIX:
2497 i.types[op] &= mask;
2504 /* Try to use the smallest displacement type too. */
2510 for (op = i.operands; --op >= 0;)
2511 if (i.types[op] & Disp)
2513 if (i.op[op].disps->X_op == O_constant)
2515 offsetT disp = i.op[op].disps->X_add_number;
2517 if ((i.types[op] & Disp16)
2518 && (disp & ~(offsetT) 0xffff) == 0)
2520 /* If this operand is at most 16 bits, convert
2521 to a signed 16 bit number and don't use 64bit
2523 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2524 i.types[op] &= ~Disp64;
2526 if ((i.types[op] & Disp32)
2527 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2529 /* If this operand is at most 32 bits, convert
2530 to a signed 32 bit number and don't use 64bit
2532 disp &= (((offsetT) 2 << 31) - 1);
2533 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2534 i.types[op] &= ~Disp64;
2536 if (!disp && (i.types[op] & BaseIndex))
2538 i.types[op] &= ~Disp;
2542 else if (flag_code == CODE_64BIT)
2544 if (fits_in_signed_long (disp))
2546 i.types[op] &= ~Disp64;
2547 i.types[op] |= Disp32S;
2549 if (fits_in_unsigned_long (disp))
2550 i.types[op] |= Disp32;
2552 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2553 && fits_in_signed_byte (disp))
2554 i.types[op] |= Disp8;
2556 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2557 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2559 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2560 i.op[op].disps, 0, i.reloc[op]);
2561 i.types[op] &= ~Disp;
2564 /* We only support 64bit displacement on constants. */
2565 i.types[op] &= ~Disp64;
2572 /* Points to template once we've found it. */
2574 unsigned int overlap0, overlap1, overlap2, overlap3;
2575 unsigned int found_reverse_match;
2577 unsigned int operand_types [MAX_OPERANDS];
2578 int addr_prefix_disp;
2581 #if MAX_OPERANDS != 4
2582 # error "MAX_OPERANDS must be 4."
2585 #define MATCH(overlap, given, template) \
2586 ((overlap & ~JumpAbsolute) \
2587 && (((given) & (BaseIndex | JumpAbsolute)) \
2588 == ((overlap) & (BaseIndex | JumpAbsolute))))
2590 /* If given types r0 and r1 are registers they must be of the same type
2591 unless the expected operand type register overlap is null.
2592 Note that Acc in a template matches every size of reg. */
2593 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2594 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2595 || ((g0) & Reg) == ((g1) & Reg) \
2596 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2602 found_reverse_match = 0;
2603 for (j = 0; j < MAX_OPERANDS; j++)
2604 operand_types [j] = 0;
2605 addr_prefix_disp = -1;
2606 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2608 : (i.suffix == WORD_MNEM_SUFFIX
2610 : (i.suffix == SHORT_MNEM_SUFFIX
2612 : (i.suffix == LONG_MNEM_SUFFIX
2614 : (i.suffix == QWORD_MNEM_SUFFIX
2616 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2617 ? No_xSuf : 0))))));
2619 for (t = current_templates->start; t < current_templates->end; t++)
2621 addr_prefix_disp = -1;
2623 /* Must have right number of operands. */
2624 if (i.operands != t->operands)
2627 /* Check the suffix, except for some instructions in intel mode. */
2628 if ((t->opcode_modifier & suffix_check)
2630 && (t->opcode_modifier & IgnoreSize)))
2633 for (j = 0; j < MAX_OPERANDS; j++)
2634 operand_types [j] = t->operand_types [j];
2636 /* In general, don't allow 64-bit operands in 32-bit mode. */
2637 if (i.suffix == QWORD_MNEM_SUFFIX
2638 && flag_code != CODE_64BIT
2640 ? (!(t->opcode_modifier & IgnoreSize)
2641 && !intel_float_operand (t->name))
2642 : intel_float_operand (t->name) != 2)
2643 && (!(operand_types[0] & (RegMMX | RegXMM))
2644 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2645 && (t->base_opcode != 0x0fc7
2646 || t->extension_opcode != 1 /* cmpxchg8b */))
2649 /* Do not verify operands when there are none. */
2650 else if (!t->operands)
2652 if (t->cpu_flags & ~cpu_arch_flags)
2654 /* We've found a match; break out of loop. */
2658 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2659 into Disp32/Disp16/Disp32 operand. */
2660 if (i.prefix[ADDR_PREFIX] != 0)
2662 unsigned int DispOn = 0, DispOff = 0;
2680 for (j = 0; j < MAX_OPERANDS; j++)
2682 /* There should be only one Disp operand. */
2683 if ((operand_types[j] & DispOff))
2685 addr_prefix_disp = j;
2686 operand_types[j] |= DispOn;
2687 operand_types[j] &= ~DispOff;
2693 overlap0 = i.types[0] & operand_types[0];
2694 switch (t->operands)
2697 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2703 overlap1 = i.types[1] & operand_types[1];
2704 if (!MATCH (overlap0, i.types[0], operand_types[0])
2705 || !MATCH (overlap1, i.types[1], operand_types[1])
2706 /* monitor in SSE3 is a very special case. The first
2707 register and the second register may have different
2709 || !((t->base_opcode == 0x0f01
2710 && t->extension_opcode == 0xc8)
2711 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2713 overlap1, i.types[1],
2716 /* Check if other direction is valid ... */
2717 if ((t->opcode_modifier & (D | FloatD)) == 0)
2720 /* Try reversing direction of operands. */
2721 overlap0 = i.types[0] & operand_types[1];
2722 overlap1 = i.types[1] & operand_types[0];
2723 if (!MATCH (overlap0, i.types[0], operand_types[1])
2724 || !MATCH (overlap1, i.types[1], operand_types[0])
2725 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2727 overlap1, i.types[1],
2730 /* Does not match either direction. */
2733 /* found_reverse_match holds which of D or FloatDR
2735 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2739 /* Found a forward 2 operand match here. */
2740 switch (t->operands)
2743 overlap3 = i.types[3] & operand_types[3];
2745 overlap2 = i.types[2] & operand_types[2];
2749 switch (t->operands)
2752 if (!MATCH (overlap3, i.types[3], operand_types[3])
2753 || !CONSISTENT_REGISTER_MATCH (overlap2,
2761 /* Here we make use of the fact that there are no
2762 reverse match 3 operand instructions, and all 3
2763 operand instructions only need to be checked for
2764 register consistency between operands 2 and 3. */
2765 if (!MATCH (overlap2, i.types[2], operand_types[2])
2766 || !CONSISTENT_REGISTER_MATCH (overlap1,
2776 /* Found either forward/reverse 2, 3 or 4 operand match here:
2777 slip through to break. */
2779 if (t->cpu_flags & ~cpu_arch_flags)
2781 found_reverse_match = 0;
2784 /* We've found a match; break out of loop. */
2788 if (t == current_templates->end)
2790 /* We found no match. */
2791 as_bad (_("suffix or operands invalid for `%s'"),
2792 current_templates->start->name);
2796 if (!quiet_warnings)
2799 && ((i.types[0] & JumpAbsolute)
2800 != (operand_types[0] & JumpAbsolute)))
2802 as_warn (_("indirect %s without `*'"), t->name);
2805 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2806 == (IsPrefix | IgnoreSize))
2808 /* Warn them that a data or address size prefix doesn't
2809 affect assembly of the next line of code. */
2810 as_warn (_("stand-alone `%s' prefix"), t->name);
2814 /* Copy the template we found. */
2817 if (addr_prefix_disp != -1)
2818 i.tm.operand_types[addr_prefix_disp]
2819 = operand_types[addr_prefix_disp];
2821 if (found_reverse_match)
2823 /* If we found a reverse match we must alter the opcode
2824 direction bit. found_reverse_match holds bits to change
2825 (different for int & float insns). */
2827 i.tm.base_opcode ^= found_reverse_match;
2829 i.tm.operand_types[0] = operand_types[1];
2830 i.tm.operand_types[1] = operand_types[0];
2839 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2840 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2842 if (i.seg[0] != NULL && i.seg[0] != &es)
2844 as_bad (_("`%s' operand %d must use `%%es' segment"),
2849 /* There's only ever one segment override allowed per instruction.
2850 This instruction possibly has a legal segment override on the
2851 second operand, so copy the segment to where non-string
2852 instructions store it, allowing common code. */
2853 i.seg[0] = i.seg[1];
2855 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2857 if (i.seg[1] != NULL && i.seg[1] != &es)
2859 as_bad (_("`%s' operand %d must use `%%es' segment"),
2869 process_suffix (void)
2871 /* If matched instruction specifies an explicit instruction mnemonic
2873 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2875 if (i.tm.opcode_modifier & Size16)
2876 i.suffix = WORD_MNEM_SUFFIX;
2877 else if (i.tm.opcode_modifier & Size64)
2878 i.suffix = QWORD_MNEM_SUFFIX;
2880 i.suffix = LONG_MNEM_SUFFIX;
2882 else if (i.reg_operands)
2884 /* If there's no instruction mnemonic suffix we try to invent one
2885 based on register operands. */
2888 /* We take i.suffix from the last register operand specified,
2889 Destination register type is more significant than source
2893 for (op = i.operands; --op >= 0;)
2894 if ((i.types[op] & Reg)
2895 && !(i.tm.operand_types[op] & InOutPortReg))
2897 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2898 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2899 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2904 else if (i.suffix == BYTE_MNEM_SUFFIX)
2906 if (!check_byte_reg ())
2909 else if (i.suffix == LONG_MNEM_SUFFIX)
2911 if (!check_long_reg ())
2914 else if (i.suffix == QWORD_MNEM_SUFFIX)
2916 if (!check_qword_reg ())
2919 else if (i.suffix == WORD_MNEM_SUFFIX)
2921 if (!check_word_reg ())
2924 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2925 /* Do nothing if the instruction is going to ignore the prefix. */
2930 else if ((i.tm.opcode_modifier & DefaultSize)
2932 /* exclude fldenv/frstor/fsave/fstenv */
2933 && (i.tm.opcode_modifier & No_sSuf))
2935 i.suffix = stackop_size;
2937 else if (intel_syntax
2939 && ((i.tm.operand_types[0] & JumpAbsolute)
2940 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2941 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2942 && i.tm.extension_opcode <= 3)))
2947 if (!(i.tm.opcode_modifier & No_qSuf))
2949 i.suffix = QWORD_MNEM_SUFFIX;
2953 if (!(i.tm.opcode_modifier & No_lSuf))
2954 i.suffix = LONG_MNEM_SUFFIX;
2957 if (!(i.tm.opcode_modifier & No_wSuf))
2958 i.suffix = WORD_MNEM_SUFFIX;
2967 if (i.tm.opcode_modifier & W)
2969 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2975 unsigned int suffixes = (~i.tm.opcode_modifier
2983 if ((i.tm.opcode_modifier & W)
2984 || ((suffixes & (suffixes - 1))
2985 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2987 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2993 /* Change the opcode based on the operand size given by i.suffix;
2994 We don't need to change things for byte insns. */
2996 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2998 /* It's not a byte, select word/dword operation. */
2999 if (i.tm.opcode_modifier & W)
3001 if (i.tm.opcode_modifier & ShortForm)
3002 i.tm.base_opcode |= 8;
3004 i.tm.base_opcode |= 1;
3007 /* Now select between word & dword operations via the operand
3008 size prefix, except for instructions that will ignore this
3010 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3012 /* monitor in SSE3 is a very special case. The default size
3013 of AX is the size of mode. The address size override
3014 prefix will change the size of AX. */
3015 if (i.op->regs[0].reg_type &
3016 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3017 if (!add_prefix (ADDR_PREFIX_OPCODE))
3020 else if (i.suffix != QWORD_MNEM_SUFFIX
3021 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3022 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3023 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3024 || (flag_code == CODE_64BIT
3025 && (i.tm.opcode_modifier & JumpByte))))
3027 unsigned int prefix = DATA_PREFIX_OPCODE;
3029 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3030 prefix = ADDR_PREFIX_OPCODE;
3032 if (!add_prefix (prefix))
3036 /* Set mode64 for an operand. */
3037 if (i.suffix == QWORD_MNEM_SUFFIX
3038 && flag_code == CODE_64BIT
3039 && (i.tm.opcode_modifier & NoRex64) == 0)
3041 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3044 || i.types [0] != (Acc | Reg64)
3045 || i.types [1] != (Acc | Reg64)
3046 || strcmp (i.tm.name, "xchg") != 0)
3047 i.rex |= REX_MODE64;
3050 /* Size floating point instruction. */
3051 if (i.suffix == LONG_MNEM_SUFFIX)
3052 if (i.tm.opcode_modifier & FloatMF)
3053 i.tm.base_opcode ^= 4;
3060 check_byte_reg (void)
3064 for (op = i.operands; --op >= 0;)
3066 /* If this is an eight bit register, it's OK. If it's the 16 or
3067 32 bit version of an eight bit register, we will just use the
3068 low portion, and that's OK too. */
3069 if (i.types[op] & Reg8)
3072 /* movzx and movsx should not generate this warning. */
3074 && (i.tm.base_opcode == 0xfb7
3075 || i.tm.base_opcode == 0xfb6
3076 || i.tm.base_opcode == 0x63
3077 || i.tm.base_opcode == 0xfbe
3078 || i.tm.base_opcode == 0xfbf))
3081 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3083 /* Prohibit these changes in the 64bit mode, since the
3084 lowering is more complicated. */
3085 if (flag_code == CODE_64BIT
3086 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3088 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3089 i.op[op].regs->reg_name,
3093 #if REGISTER_WARNINGS
3095 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3096 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3097 (i.op[op].regs + (i.types[op] & Reg16
3098 ? REGNAM_AL - REGNAM_AX
3099 : REGNAM_AL - REGNAM_EAX))->reg_name,
3100 i.op[op].regs->reg_name,
3105 /* Any other register is bad. */
3106 if (i.types[op] & (Reg | RegMMX | RegXMM
3108 | Control | Debug | Test
3109 | FloatReg | FloatAcc))
3111 as_bad (_("`%%%s' not allowed with `%s%c'"),
3112 i.op[op].regs->reg_name,
3126 for (op = i.operands; --op >= 0;)
3127 /* Reject eight bit registers, except where the template requires
3128 them. (eg. movzb) */
3129 if ((i.types[op] & Reg8) != 0
3130 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3132 as_bad (_("`%%%s' not allowed with `%s%c'"),
3133 i.op[op].regs->reg_name,
3138 /* Warn if the e prefix on a general reg is missing. */
3139 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3140 && (i.types[op] & Reg16) != 0
3141 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3143 /* Prohibit these changes in the 64bit mode, since the
3144 lowering is more complicated. */
3145 if (flag_code == CODE_64BIT)
3147 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3148 i.op[op].regs->reg_name,
3152 #if REGISTER_WARNINGS
3154 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3155 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3156 i.op[op].regs->reg_name,
3160 /* Warn if the r prefix on a general reg is missing. */
3161 else if ((i.types[op] & Reg64) != 0
3162 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3164 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3165 i.op[op].regs->reg_name,
3177 for (op = i.operands; --op >= 0; )
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i.types[op] & Reg8) != 0
3181 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3183 as_bad (_("`%%%s' not allowed with `%s%c'"),
3184 i.op[op].regs->reg_name,
3189 /* Warn if the e prefix on a general reg is missing. */
3190 else if (((i.types[op] & Reg16) != 0
3191 || (i.types[op] & Reg32) != 0)
3192 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3194 /* Prohibit these changes in the 64bit mode, since the
3195 lowering is more complicated. */
3196 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3197 i.op[op].regs->reg_name,
3208 for (op = i.operands; --op >= 0;)
3209 /* Reject eight bit registers, except where the template requires
3210 them. (eg. movzb) */
3211 if ((i.types[op] & Reg8) != 0
3212 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3214 as_bad (_("`%%%s' not allowed with `%s%c'"),
3215 i.op[op].regs->reg_name,
3220 /* Warn if the e prefix on a general reg is present. */
3221 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3222 && (i.types[op] & Reg32) != 0
3223 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3225 /* Prohibit these changes in the 64bit mode, since the
3226 lowering is more complicated. */
3227 if (flag_code == CODE_64BIT)
3229 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3230 i.op[op].regs->reg_name,
3235 #if REGISTER_WARNINGS
3236 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3237 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3238 i.op[op].regs->reg_name,
3248 unsigned int overlap0, overlap1, overlap2;
3250 overlap0 = i.types[0] & i.tm.operand_types[0];
3251 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3252 && overlap0 != Imm8 && overlap0 != Imm8S
3253 && overlap0 != Imm16 && overlap0 != Imm32S
3254 && overlap0 != Imm32 && overlap0 != Imm64)
3258 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3260 : (i.suffix == WORD_MNEM_SUFFIX
3262 : (i.suffix == QWORD_MNEM_SUFFIX
3266 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3267 || overlap0 == (Imm16 | Imm32)
3268 || overlap0 == (Imm16 | Imm32S))
3270 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3273 if (overlap0 != Imm8 && overlap0 != Imm8S
3274 && overlap0 != Imm16 && overlap0 != Imm32S
3275 && overlap0 != Imm32 && overlap0 != Imm64)
3277 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3281 i.types[0] = overlap0;
3283 overlap1 = i.types[1] & i.tm.operand_types[1];
3284 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3285 && overlap1 != Imm8 && overlap1 != Imm8S
3286 && overlap1 != Imm16 && overlap1 != Imm32S
3287 && overlap1 != Imm32 && overlap1 != Imm64)
3291 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3293 : (i.suffix == WORD_MNEM_SUFFIX
3295 : (i.suffix == QWORD_MNEM_SUFFIX
3299 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3300 || overlap1 == (Imm16 | Imm32)
3301 || overlap1 == (Imm16 | Imm32S))
3303 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3306 if (overlap1 != Imm8 && overlap1 != Imm8S
3307 && overlap1 != Imm16 && overlap1 != Imm32S
3308 && overlap1 != Imm32 && overlap1 != Imm64)
3310 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3314 i.types[1] = overlap1;
3316 overlap2 = i.types[2] & i.tm.operand_types[2];
3317 assert ((overlap2 & Imm) == 0);
3318 i.types[2] = overlap2;
3326 /* Default segment register this instruction will use for memory
3327 accesses. 0 means unknown. This is only for optimizing out
3328 unnecessary segment overrides. */
3329 const seg_entry *default_seg = 0;
3331 /* The imul $imm, %reg instruction is converted into
3332 imul $imm, %reg, %reg, and the clr %reg instruction
3333 is converted into xor %reg, %reg. */
3334 if (i.tm.opcode_modifier & regKludge)
3336 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3337 /* Pretend we saw the extra register operand. */
3338 assert (i.op[first_reg_op + 1].regs == 0);
3339 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3340 i.types[first_reg_op + 1] = i.types[first_reg_op];
3344 if (i.tm.opcode_modifier & ShortForm)
3346 /* The register or float register operand is in operand 0 or 1. */
3347 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3348 /* Register goes in low 3 bits of opcode. */
3349 i.tm.base_opcode |= i.op[op].regs->reg_num;
3350 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3352 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3354 /* Warn about some common errors, but press on regardless.
3355 The first case can be generated by gcc (<= 2.8.1). */
3356 if (i.operands == 2)
3358 /* Reversed arguments on faddp, fsubp, etc. */
3359 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3360 i.op[1].regs->reg_name,
3361 i.op[0].regs->reg_name);
3365 /* Extraneous `l' suffix on fp insn. */
3366 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3367 i.op[0].regs->reg_name);
3371 else if (i.tm.opcode_modifier & Modrm)
3373 /* The opcode is completed (modulo i.tm.extension_opcode which
3374 must be put into the modrm byte). Now, we make the modrm and
3375 index base bytes based on all the info we've collected. */
3377 default_seg = build_modrm_byte ();
3379 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3381 if (i.tm.base_opcode == POP_SEG_SHORT
3382 && i.op[0].regs->reg_num == 1)
3384 as_bad (_("you can't `pop %%cs'"));
3387 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3388 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3391 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3395 else if ((i.tm.opcode_modifier & IsString) != 0)
3397 /* For the string instructions that allow a segment override
3398 on one of their operands, the default segment is ds. */
3402 if ((i.tm.base_opcode == 0x8d /* lea */
3403 || (i.tm.cpu_flags & CpuSVME))
3404 && i.seg[0] && !quiet_warnings)
3405 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3407 /* If a segment was explicitly specified, and the specified segment
3408 is not the default, use an opcode prefix to select it. If we
3409 never figured out what the default segment is, then default_seg
3410 will be zero at this point, and the specified segment prefix will
3412 if ((i.seg[0]) && (i.seg[0] != default_seg))
3414 if (!add_prefix (i.seg[0]->seg_prefix))
3420 static const seg_entry *
3423 const seg_entry *default_seg = 0;
3425 /* i.reg_operands MUST be the number of real register operands;
3426 implicit registers do not count. */
3427 if (i.reg_operands == 2)
3429 unsigned int source, dest;
3430 source = ((i.types[0]
3431 & (Reg | RegMMX | RegXMM
3433 | Control | Debug | Test))
3436 /* In 4 operands instructions with 2 immediate operands, the first
3437 two are immediate bytes and hence source operand will be in the
3438 next byte after the immediates */
3439 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
3443 /* One of the register operands will be encoded in the i.tm.reg
3444 field, the other in the combined i.tm.mode and i.tm.regmem
3445 fields. If no form of this instruction supports a memory
3446 destination operand, then we assume the source operand may
3447 sometimes be a memory operand and so we need to store the
3448 destination in the i.rm.reg field. */
3449 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3451 i.rm.reg = i.op[dest].regs->reg_num;
3452 i.rm.regmem = i.op[source].regs->reg_num;
3453 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3455 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3460 i.rm.reg = i.op[source].regs->reg_num;
3461 i.rm.regmem = i.op[dest].regs->reg_num;
3462 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3464 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3467 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3469 if (!((i.types[0] | i.types[1]) & Control))
3471 i.rex &= ~(REX_EXTX | REX_EXTZ);
3472 add_prefix (LOCK_PREFIX_OPCODE);
3476 { /* If it's not 2 reg operands... */
3479 unsigned int fake_zero_displacement = 0;
3480 unsigned int op = ((i.types[0] & AnyMem)
3482 : (i.types[1] & AnyMem) ? 1 : 2);
3486 if (i.base_reg == 0)
3489 if (!i.disp_operands)
3490 fake_zero_displacement = 1;
3491 if (i.index_reg == 0)
3493 /* Operand is just <disp> */
3494 if (flag_code == CODE_64BIT)
3496 /* 64bit mode overwrites the 32bit absolute
3497 addressing by RIP relative addressing and
3498 absolute addressing is encoded by one of the
3499 redundant SIB forms. */
3500 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3501 i.sib.base = NO_BASE_REGISTER;
3502 i.sib.index = NO_INDEX_REGISTER;
3503 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3504 ? Disp32S : Disp32);
3506 else if ((flag_code == CODE_16BIT)
3507 ^ (i.prefix[ADDR_PREFIX] != 0))
3509 i.rm.regmem = NO_BASE_REGISTER_16;
3510 i.types[op] = Disp16;
3514 i.rm.regmem = NO_BASE_REGISTER;
3515 i.types[op] = Disp32;
3518 else /* !i.base_reg && i.index_reg */
3520 i.sib.index = i.index_reg->reg_num;
3521 i.sib.base = NO_BASE_REGISTER;
3522 i.sib.scale = i.log2_scale_factor;
3523 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3524 i.types[op] &= ~Disp;
3525 if (flag_code != CODE_64BIT)
3526 i.types[op] |= Disp32; /* Must be 32 bit */
3528 i.types[op] |= Disp32S;
3529 if ((i.index_reg->reg_flags & RegRex) != 0)
3533 /* RIP addressing for 64bit mode. */
3534 else if (i.base_reg->reg_type == BaseIndex)
3536 i.rm.regmem = NO_BASE_REGISTER;
3537 i.types[op] &= ~ Disp;
3538 i.types[op] |= Disp32S;
3539 i.flags[op] |= Operand_PCrel;
3540 if (! i.disp_operands)
3541 fake_zero_displacement = 1;
3543 else if (i.base_reg->reg_type & Reg16)
3545 switch (i.base_reg->reg_num)
3548 if (i.index_reg == 0)
3550 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3551 i.rm.regmem = i.index_reg->reg_num - 6;
3555 if (i.index_reg == 0)
3558 if ((i.types[op] & Disp) == 0)
3560 /* fake (%bp) into 0(%bp) */
3561 i.types[op] |= Disp8;
3562 fake_zero_displacement = 1;
3565 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3566 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3568 default: /* (%si) -> 4 or (%di) -> 5 */
3569 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3571 i.rm.mode = mode_from_disp_size (i.types[op]);
3573 else /* i.base_reg and 32/64 bit mode */
3575 if (flag_code == CODE_64BIT
3576 && (i.types[op] & Disp))
3577 i.types[op] = ((i.types[op] & Disp8)
3578 | (i.prefix[ADDR_PREFIX] == 0
3579 ? Disp32S : Disp32));
3581 i.rm.regmem = i.base_reg->reg_num;
3582 if ((i.base_reg->reg_flags & RegRex) != 0)
3584 i.sib.base = i.base_reg->reg_num;
3585 /* x86-64 ignores REX prefix bit here to avoid decoder
3587 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3590 if (i.disp_operands == 0)
3592 fake_zero_displacement = 1;
3593 i.types[op] |= Disp8;
3596 else if (i.base_reg->reg_num == ESP_REG_NUM)
3600 i.sib.scale = i.log2_scale_factor;
3601 if (i.index_reg == 0)
3603 /* <disp>(%esp) becomes two byte modrm with no index
3604 register. We've already stored the code for esp
3605 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3606 Any base register besides %esp will not use the
3607 extra modrm byte. */
3608 i.sib.index = NO_INDEX_REGISTER;
3609 #if !SCALE1_WHEN_NO_INDEX
3610 /* Another case where we force the second modrm byte. */
3611 if (i.log2_scale_factor)
3612 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3617 i.sib.index = i.index_reg->reg_num;
3618 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3619 if ((i.index_reg->reg_flags & RegRex) != 0)
3624 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3625 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3628 i.rm.mode = mode_from_disp_size (i.types[op]);
3631 if (fake_zero_displacement)
3633 /* Fakes a zero displacement assuming that i.types[op]
3634 holds the correct displacement size. */
3637 assert (i.op[op].disps == 0);
3638 exp = &disp_expressions[i.disp_operands++];
3639 i.op[op].disps = exp;
3640 exp->X_op = O_constant;
3641 exp->X_add_number = 0;
3642 exp->X_add_symbol = (symbolS *) 0;
3643 exp->X_op_symbol = (symbolS *) 0;
3647 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3648 (if any) based on i.tm.extension_opcode. Again, we must be
3649 careful to make sure that segment/control/debug/test/MMX
3650 registers are coded into the i.rm.reg field. */
3655 & (Reg | RegMMX | RegXMM
3657 | Control | Debug | Test))
3660 & (Reg | RegMMX | RegXMM
3662 | Control | Debug | Test))
3665 /* If there is an extension opcode to put here, the register
3666 number must be put into the regmem field. */
3667 if (i.tm.extension_opcode != None)
3669 i.rm.regmem = i.op[op].regs->reg_num;
3670 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3675 i.rm.reg = i.op[op].regs->reg_num;
3676 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3680 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3681 must set it to 3 to indicate this is a register operand
3682 in the regmem field. */
3683 if (!i.mem_operands)
3687 /* Fill in i.rm.reg field with extension opcode (if any). */
3688 if (i.tm.extension_opcode != None)
3689 i.rm.reg = i.tm.extension_opcode;
3700 relax_substateT subtype;
3705 if (flag_code == CODE_16BIT)
3709 if (i.prefix[DATA_PREFIX] != 0)
3715 /* Pentium4 branch hints. */
3716 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3717 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3722 if (i.prefix[REX_PREFIX] != 0)
3728 if (i.prefixes != 0 && !intel_syntax)
3729 as_warn (_("skipping prefixes on this instruction"));
3731 /* It's always a symbol; End frag & setup for relax.
3732 Make sure there is enough room in this frag for the largest
3733 instruction we may generate in md_convert_frag. This is 2
3734 bytes for the opcode and room for the prefix and largest
3736 frag_grow (prefix + 2 + 4);
3737 /* Prefix and 1 opcode byte go in fr_fix. */
3738 p = frag_more (prefix + 1);
3739 if (i.prefix[DATA_PREFIX] != 0)
3740 *p++ = DATA_PREFIX_OPCODE;
3741 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3742 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3743 *p++ = i.prefix[SEG_PREFIX];
3744 if (i.prefix[REX_PREFIX] != 0)
3745 *p++ = i.prefix[REX_PREFIX];
3746 *p = i.tm.base_opcode;
3748 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3749 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3750 else if ((cpu_arch_flags & Cpu386) != 0)
3751 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3753 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3756 sym = i.op[0].disps->X_add_symbol;
3757 off = i.op[0].disps->X_add_number;
3759 if (i.op[0].disps->X_op != O_constant
3760 && i.op[0].disps->X_op != O_symbol)
3762 /* Handle complex expressions. */
3763 sym = make_expr_symbol (i.op[0].disps);
3767 /* 1 possible extra opcode + 4 byte displacement go in var part.
3768 Pass reloc in fr_var. */
3769 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3779 if (i.tm.opcode_modifier & JumpByte)
3781 /* This is a loop or jecxz type instruction. */
3783 if (i.prefix[ADDR_PREFIX] != 0)
3785 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3788 /* Pentium4 branch hints. */
3789 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3790 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3792 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3801 if (flag_code == CODE_16BIT)
3804 if (i.prefix[DATA_PREFIX] != 0)
3806 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3816 if (i.prefix[REX_PREFIX] != 0)
3818 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3822 if (i.prefixes != 0 && !intel_syntax)
3823 as_warn (_("skipping prefixes on this instruction"));
3825 p = frag_more (1 + size);
3826 *p++ = i.tm.base_opcode;
3828 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3829 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3831 /* All jumps handled here are signed, but don't use a signed limit
3832 check for 32 and 16 bit jumps as we want to allow wrap around at
3833 4G and 64k respectively. */
3835 fixP->fx_signed = 1;
3839 output_interseg_jump ()
3847 if (flag_code == CODE_16BIT)
3851 if (i.prefix[DATA_PREFIX] != 0)
3857 if (i.prefix[REX_PREFIX] != 0)
3867 if (i.prefixes != 0 && !intel_syntax)
3868 as_warn (_("skipping prefixes on this instruction"));
3870 /* 1 opcode; 2 segment; offset */
3871 p = frag_more (prefix + 1 + 2 + size);
3873 if (i.prefix[DATA_PREFIX] != 0)
3874 *p++ = DATA_PREFIX_OPCODE;
3876 if (i.prefix[REX_PREFIX] != 0)
3877 *p++ = i.prefix[REX_PREFIX];
3879 *p++ = i.tm.base_opcode;
3880 if (i.op[1].imms->X_op == O_constant)
3882 offsetT n = i.op[1].imms->X_add_number;
3885 && !fits_in_unsigned_word (n)
3886 && !fits_in_signed_word (n))
3888 as_bad (_("16-bit jump out of range"));
3891 md_number_to_chars (p, n, size);
3894 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3895 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3896 if (i.op[0].imms->X_op != O_constant)
3897 as_bad (_("can't handle non absolute segment in `%s'"),
3899 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3905 fragS *insn_start_frag;
3906 offsetT insn_start_off;
3908 /* Tie dwarf2 debug info to the address at the start of the insn.
3909 We can't do this after the insn has been output as the current
3910 frag may have been closed off. eg. by frag_var. */
3911 dwarf2_emit_insn (0);
3913 insn_start_frag = frag_now;
3914 insn_start_off = frag_now_fix ();
3917 if (i.tm.opcode_modifier & Jump)
3919 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3921 else if (i.tm.opcode_modifier & JumpInterSegment)
3922 output_interseg_jump ();
3925 /* Output normal instructions here. */
3928 unsigned int prefix;
3930 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3931 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3932 use one more higher byte to specify a prefix the instruction
3934 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3936 if (i.tm.base_opcode & 0xff000000)
3938 prefix = (i.tm.base_opcode >> 24) & 0xff;
3942 else if ((i.tm.base_opcode & 0xff0000) != 0)
3944 prefix = (i.tm.base_opcode >> 16) & 0xff;
3945 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3948 if (prefix != REPE_PREFIX_OPCODE
3949 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3950 add_prefix (prefix);
3953 add_prefix (prefix);
3956 /* The prefix bytes. */
3958 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3964 md_number_to_chars (p, (valueT) *q, 1);
3968 /* Now the opcode; be careful about word order here! */
3969 if (fits_in_unsigned_byte (i.tm.base_opcode))
3971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3975 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3978 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3983 /* Put out high byte first: can't use md_number_to_chars! */
3984 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3985 *p = i.tm.base_opcode & 0xff;
3988 /* Now the modrm byte and sib byte (if present). */
3989 if (i.tm.opcode_modifier & Modrm)
3992 md_number_to_chars (p,
3993 (valueT) (i.rm.regmem << 0
3997 /* If i.rm.regmem == ESP (4)
3998 && i.rm.mode != (Register mode)
4000 ==> need second modrm byte. */
4001 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4003 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4006 md_number_to_chars (p,
4007 (valueT) (i.sib.base << 0
4009 | i.sib.scale << 6),
4014 if (i.disp_operands)
4015 output_disp (insn_start_frag, insn_start_off);
4018 output_imm (insn_start_frag, insn_start_off);
4024 pi ("" /*line*/, &i);
4026 #endif /* DEBUG386 */
4030 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
4035 for (n = 0; n < i.operands; n++)
4037 if (i.types[n] & Disp)
4039 if (i.op[n].disps->X_op == O_constant)
4045 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4048 if (i.types[n] & Disp8)
4050 if (i.types[n] & Disp64)
4053 val = offset_in_range (i.op[n].disps->X_add_number,
4055 p = frag_more (size);
4056 md_number_to_chars (p, val, size);
4060 enum bfd_reloc_code_real reloc_type;
4063 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4065 /* The PC relative address is computed relative
4066 to the instruction boundary, so in case immediate
4067 fields follows, we need to adjust the value. */
4068 if (pcrel && i.imm_operands)
4073 for (n1 = 0; n1 < i.operands; n1++)
4074 if (i.types[n1] & Imm)
4076 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4079 if (i.types[n1] & (Imm8 | Imm8S))
4081 if (i.types[n1] & Imm64)
4086 /* We should find the immediate. */
4087 if (n1 == i.operands)
4089 i.op[n].disps->X_add_number -= imm_size;
4092 if (i.types[n] & Disp32S)
4095 if (i.types[n] & (Disp16 | Disp64))
4098 if (i.types[n] & Disp64)
4102 p = frag_more (size);
4103 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4105 && GOT_symbol == i.op[n].disps->X_add_symbol
4106 && (((reloc_type == BFD_RELOC_32
4107 || reloc_type == BFD_RELOC_X86_64_32S
4108 || (reloc_type == BFD_RELOC_64
4110 && (i.op[n].disps->X_op == O_symbol
4111 || (i.op[n].disps->X_op == O_add
4112 && ((symbol_get_value_expression
4113 (i.op[n].disps->X_op_symbol)->X_op)
4115 || reloc_type == BFD_RELOC_32_PCREL))
4119 if (insn_start_frag == frag_now)
4120 add = (p - frag_now->fr_literal) - insn_start_off;
4125 add = insn_start_frag->fr_fix - insn_start_off;
4126 for (fr = insn_start_frag->fr_next;
4127 fr && fr != frag_now; fr = fr->fr_next)
4129 add += p - frag_now->fr_literal;
4134 reloc_type = BFD_RELOC_386_GOTPC;
4135 i.op[n].imms->X_add_number += add;
4137 else if (reloc_type == BFD_RELOC_64)
4138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4140 /* Don't do the adjustment for x86-64, as there
4141 the pcrel addressing is relative to the _next_
4142 insn, and that is taken care of in other code. */
4143 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4145 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4146 i.op[n].disps, pcrel, reloc_type);
4153 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4158 for (n = 0; n < i.operands; n++)
4160 if (i.types[n] & Imm)
4162 if (i.op[n].imms->X_op == O_constant)
4168 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4171 if (i.types[n] & (Imm8 | Imm8S))
4173 else if (i.types[n] & Imm64)
4176 val = offset_in_range (i.op[n].imms->X_add_number,
4178 p = frag_more (size);
4179 md_number_to_chars (p, val, size);
4183 /* Not absolute_section.
4184 Need a 32-bit fixup (don't support 8bit
4185 non-absolute imms). Try to support other
4187 enum bfd_reloc_code_real reloc_type;
4191 if ((i.types[n] & (Imm32S))
4192 && (i.suffix == QWORD_MNEM_SUFFIX
4193 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4195 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4198 if (i.types[n] & (Imm8 | Imm8S))
4200 if (i.types[n] & Imm64)
4204 p = frag_more (size);
4205 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4207 /* This is tough to explain. We end up with this one if we
4208 * have operands that look like
4209 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4210 * obtain the absolute address of the GOT, and it is strongly
4211 * preferable from a performance point of view to avoid using
4212 * a runtime relocation for this. The actual sequence of
4213 * instructions often look something like:
4218 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4220 * The call and pop essentially return the absolute address
4221 * of the label .L66 and store it in %ebx. The linker itself
4222 * will ultimately change the first operand of the addl so
4223 * that %ebx points to the GOT, but to keep things simple, the
4224 * .o file must have this operand set so that it generates not
4225 * the absolute address of .L66, but the absolute address of
4226 * itself. This allows the linker itself simply treat a GOTPC
4227 * relocation as asking for a pcrel offset to the GOT to be
4228 * added in, and the addend of the relocation is stored in the
4229 * operand field for the instruction itself.
4231 * Our job here is to fix the operand so that it would add
4232 * the correct offset so that %ebx would point to itself. The
4233 * thing that is tricky is that .-.L66 will point to the
4234 * beginning of the instruction, so we need to further modify
4235 * the operand so that it will point to itself. There are
4236 * other cases where you have something like:
4238 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4240 * and here no correction would be required. Internally in
4241 * the assembler we treat operands of this form as not being
4242 * pcrel since the '.' is explicitly mentioned, and I wonder
4243 * whether it would simplify matters to do it this way. Who
4244 * knows. In earlier versions of the PIC patches, the
4245 * pcrel_adjust field was used to store the correction, but
4246 * since the expression is not pcrel, I felt it would be
4247 * confusing to do it this way. */
4249 if ((reloc_type == BFD_RELOC_32
4250 || reloc_type == BFD_RELOC_X86_64_32S
4251 || reloc_type == BFD_RELOC_64)
4253 && GOT_symbol == i.op[n].imms->X_add_symbol
4254 && (i.op[n].imms->X_op == O_symbol
4255 || (i.op[n].imms->X_op == O_add
4256 && ((symbol_get_value_expression
4257 (i.op[n].imms->X_op_symbol)->X_op)
4262 if (insn_start_frag == frag_now)
4263 add = (p - frag_now->fr_literal) - insn_start_off;
4268 add = insn_start_frag->fr_fix - insn_start_off;
4269 for (fr = insn_start_frag->fr_next;
4270 fr && fr != frag_now; fr = fr->fr_next)
4272 add += p - frag_now->fr_literal;
4276 reloc_type = BFD_RELOC_386_GOTPC;
4278 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4280 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4281 i.op[n].imms->X_add_number += add;
4283 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4284 i.op[n].imms, 0, reloc_type);
4290 /* x86_cons_fix_new is called via the expression parsing code when a
4291 reloc is needed. We use this hook to get the correct .got reloc. */
4292 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4293 static int cons_sign = -1;
4296 x86_cons_fix_new (fragS *frag,
4301 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4303 got_reloc = NO_RELOC;
4306 if (exp->X_op == O_secrel)
4308 exp->X_op = O_symbol;
4309 r = BFD_RELOC_32_SECREL;
4313 fix_new_exp (frag, off, len, exp, 0, r);
4316 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4317 # define lex_got(reloc, adjust, types) NULL
4319 /* Parse operands of the form
4320 <symbol>@GOTOFF+<nnn>
4321 and similar .plt or .got references.
4323 If we find one, set up the correct relocation in RELOC and copy the
4324 input string, minus the `@GOTOFF' into a malloc'd buffer for
4325 parsing by the calling routine. Return this buffer, and if ADJUST
4326 is non-null set it to the length of the string we removed from the
4327 input line. Otherwise return NULL. */
4329 lex_got (enum bfd_reloc_code_real *reloc,
4331 unsigned int *types)
4333 /* Some of the relocations depend on the size of what field is to
4334 be relocated. But in our callers i386_immediate and i386_displacement
4335 we don't yet know the operand size (this will be set by insn
4336 matching). Hence we record the word32 relocation here,
4337 and adjust the reloc according to the real size in reloc(). */
4338 static const struct {
4340 const enum bfd_reloc_code_real rel[2];
4341 const unsigned int types64;
4343 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4344 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4345 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4346 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4347 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4348 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4349 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4350 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4351 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4352 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4353 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4354 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4355 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4356 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4357 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4358 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4359 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4367 for (cp = input_line_pointer; *cp != '@'; cp++)
4368 if (is_end_of_line[(unsigned char) *cp])
4371 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4375 len = strlen (gotrel[j].str);
4376 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4378 if (gotrel[j].rel[object_64bit] != 0)
4381 char *tmpbuf, *past_reloc;
4383 *reloc = gotrel[j].rel[object_64bit];
4389 if (flag_code != CODE_64BIT)
4390 *types = Imm32|Disp32;
4392 *types = gotrel[j].types64;
4395 if (GOT_symbol == NULL)
4396 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4398 /* Replace the relocation token with ' ', so that
4399 errors like foo@GOTOFF1 will be detected. */
4401 /* The length of the first part of our input line. */
4402 first = cp - input_line_pointer;
4404 /* The second part goes from after the reloc token until
4405 (and including) an end_of_line char. Don't use strlen
4406 here as the end_of_line char may not be a NUL. */
4407 past_reloc = cp + 1 + len;
4408 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4410 second = cp - past_reloc;
4412 /* Allocate and copy string. The trailing NUL shouldn't
4413 be necessary, but be safe. */
4414 tmpbuf = xmalloc (first + second + 2);
4415 memcpy (tmpbuf, input_line_pointer, first);
4416 tmpbuf[first] = ' ';
4417 memcpy (tmpbuf + first + 1, past_reloc, second);
4418 tmpbuf[first + second + 1] = '\0';
4422 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4423 gotrel[j].str, 1 << (5 + object_64bit));
4428 /* Might be a symbol version string. Don't as_bad here. */
4433 x86_cons (exp, size)
4437 if (size == 4 || (object_64bit && size == 8))
4439 /* Handle @GOTOFF and the like in an expression. */
4441 char *gotfree_input_line;
4444 save = input_line_pointer;
4445 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4446 if (gotfree_input_line)
4447 input_line_pointer = gotfree_input_line;
4451 if (gotfree_input_line)
4453 /* expression () has merrily parsed up to the end of line,
4454 or a comma - in the wrong buffer. Transfer how far
4455 input_line_pointer has moved to the right buffer. */
4456 input_line_pointer = (save
4457 + (input_line_pointer - gotfree_input_line)
4459 free (gotfree_input_line);
4467 static void signed_cons (int size)
4469 if (flag_code == CODE_64BIT)
4477 pe_directive_secrel (dummy)
4478 int dummy ATTRIBUTE_UNUSED;
4485 if (exp.X_op == O_symbol)
4486 exp.X_op = O_secrel;
4488 emit_expr (&exp, 4);
4490 while (*input_line_pointer++ == ',');
4492 input_line_pointer--;
4493 demand_empty_rest_of_line ();
4498 i386_immediate (char *imm_start)
4500 char *save_input_line_pointer;
4501 char *gotfree_input_line;
4504 unsigned int types = ~0U;
4506 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4508 as_bad (_("at most %d immediate operands are allowed"),
4509 MAX_IMMEDIATE_OPERANDS);
4513 exp = &im_expressions[i.imm_operands++];
4514 i.op[this_operand].imms = exp;
4516 if (is_space_char (*imm_start))
4519 save_input_line_pointer = input_line_pointer;
4520 input_line_pointer = imm_start;
4522 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4523 if (gotfree_input_line)
4524 input_line_pointer = gotfree_input_line;
4526 exp_seg = expression (exp);
4529 if (*input_line_pointer)
4530 as_bad (_("junk `%s' after expression"), input_line_pointer);
4532 input_line_pointer = save_input_line_pointer;
4533 if (gotfree_input_line)
4534 free (gotfree_input_line);
4536 if (exp->X_op == O_absent || exp->X_op == O_big)
4538 /* Missing or bad expr becomes absolute 0. */
4539 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4541 exp->X_op = O_constant;
4542 exp->X_add_number = 0;
4543 exp->X_add_symbol = (symbolS *) 0;
4544 exp->X_op_symbol = (symbolS *) 0;
4546 else if (exp->X_op == O_constant)
4548 /* Size it properly later. */
4549 i.types[this_operand] |= Imm64;
4550 /* If BFD64, sign extend val. */
4551 if (!use_rela_relocations)
4552 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4553 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4555 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4556 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4557 && exp_seg != absolute_section
4558 && exp_seg != text_section
4559 && exp_seg != data_section
4560 && exp_seg != bss_section
4561 && exp_seg != undefined_section
4562 && !bfd_is_com_section (exp_seg))
4564 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4568 else if (!intel_syntax && exp->X_op == O_register)
4570 as_bad (_("illegal immediate register operand %s"), imm_start);
4575 /* This is an address. The size of the address will be
4576 determined later, depending on destination register,
4577 suffix, or the default for the section. */
4578 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4579 i.types[this_operand] &= types;
4585 static char *i386_scale PARAMS ((char *));
4592 char *save = input_line_pointer;
4594 input_line_pointer = scale;
4595 val = get_absolute_expression ();
4600 i.log2_scale_factor = 0;
4603 i.log2_scale_factor = 1;
4606 i.log2_scale_factor = 2;
4609 i.log2_scale_factor = 3;
4613 char sep = *input_line_pointer;
4615 *input_line_pointer = '\0';
4616 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4618 *input_line_pointer = sep;
4619 input_line_pointer = save;
4623 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4625 as_warn (_("scale factor of %d without an index register"),
4626 1 << i.log2_scale_factor);
4627 #if SCALE1_WHEN_NO_INDEX
4628 i.log2_scale_factor = 0;
4631 scale = input_line_pointer;
4632 input_line_pointer = save;
4636 static int i386_displacement PARAMS ((char *, char *));
4639 i386_displacement (disp_start, disp_end)
4645 char *save_input_line_pointer;
4646 char *gotfree_input_line;
4647 int bigdisp, override;
4648 unsigned int types = Disp;
4650 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4652 as_bad (_("at most %d displacement operands are allowed"),
4653 MAX_MEMORY_OPERANDS);
4657 if ((i.types[this_operand] & JumpAbsolute)
4658 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4661 override = (i.prefix[ADDR_PREFIX] != 0);
4665 /* For PC-relative branches, the width of the displacement
4666 is dependent upon data size, not address size. */
4668 override = (i.prefix[DATA_PREFIX] != 0);
4670 if (flag_code == CODE_64BIT)
4673 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4675 : Disp32S | Disp32);
4677 bigdisp = Disp64 | Disp32S | Disp32;
4684 override = (i.suffix == (flag_code != CODE_16BIT
4686 : LONG_MNEM_SUFFIX));
4689 if ((flag_code == CODE_16BIT) ^ override)
4692 i.types[this_operand] |= bigdisp;
4694 exp = &disp_expressions[i.disp_operands];
4695 i.op[this_operand].disps = exp;
4697 save_input_line_pointer = input_line_pointer;
4698 input_line_pointer = disp_start;
4699 END_STRING_AND_SAVE (disp_end);
4701 #ifndef GCC_ASM_O_HACK
4702 #define GCC_ASM_O_HACK 0
4705 END_STRING_AND_SAVE (disp_end + 1);
4706 if ((i.types[this_operand] & BaseIndex) != 0
4707 && displacement_string_end[-1] == '+')
4709 /* This hack is to avoid a warning when using the "o"
4710 constraint within gcc asm statements.
4713 #define _set_tssldt_desc(n,addr,limit,type) \
4714 __asm__ __volatile__ ( \
4716 "movw %w1,2+%0\n\t" \
4718 "movb %b1,4+%0\n\t" \
4719 "movb %4,5+%0\n\t" \
4720 "movb $0,6+%0\n\t" \
4721 "movb %h1,7+%0\n\t" \
4723 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4725 This works great except that the output assembler ends
4726 up looking a bit weird if it turns out that there is
4727 no offset. You end up producing code that looks like:
4740 So here we provide the missing zero. */
4742 *displacement_string_end = '0';
4745 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4746 if (gotfree_input_line)
4747 input_line_pointer = gotfree_input_line;
4749 exp_seg = expression (exp);
4752 if (*input_line_pointer)
4753 as_bad (_("junk `%s' after expression"), input_line_pointer);
4755 RESTORE_END_STRING (disp_end + 1);
4757 RESTORE_END_STRING (disp_end);
4758 input_line_pointer = save_input_line_pointer;
4759 if (gotfree_input_line)
4760 free (gotfree_input_line);
4762 /* We do this to make sure that the section symbol is in
4763 the symbol table. We will ultimately change the relocation
4764 to be relative to the beginning of the section. */
4765 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4766 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4767 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4769 if (exp->X_op != O_symbol)
4771 as_bad (_("bad expression used with @%s"),
4772 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4778 if (S_IS_LOCAL (exp->X_add_symbol)
4779 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4780 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4781 exp->X_op = O_subtract;
4782 exp->X_op_symbol = GOT_symbol;
4783 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4784 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4785 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4786 i.reloc[this_operand] = BFD_RELOC_64;
4788 i.reloc[this_operand] = BFD_RELOC_32;
4791 if (exp->X_op == O_absent || exp->X_op == O_big)
4793 /* Missing or bad expr becomes absolute 0. */
4794 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4796 exp->X_op = O_constant;
4797 exp->X_add_number = 0;
4798 exp->X_add_symbol = (symbolS *) 0;
4799 exp->X_op_symbol = (symbolS *) 0;
4802 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4803 if (exp->X_op != O_constant
4804 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4805 && exp_seg != absolute_section
4806 && exp_seg != text_section
4807 && exp_seg != data_section
4808 && exp_seg != bss_section
4809 && exp_seg != undefined_section
4810 && !bfd_is_com_section (exp_seg))
4812 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4817 if (!(i.types[this_operand] & ~Disp))
4818 i.types[this_operand] &= types;
4823 static int i386_index_check PARAMS ((const char *));
4825 /* Make sure the memory operand we've been dealt is valid.
4826 Return 1 on success, 0 on a failure. */
4829 i386_index_check (operand_string)
4830 const char *operand_string;
4833 #if INFER_ADDR_PREFIX
4839 if ((current_templates->start->cpu_flags & CpuSVME)
4840 && current_templates->end[-1].operand_types[0] == AnyMem)
4842 /* Memory operands of SVME insns are special in that they only allow
4843 rAX as their memory address and ignore any segment override. */
4846 /* SKINIT is even more restrictive: it always requires EAX. */
4847 if (strcmp (current_templates->start->name, "skinit") == 0)
4849 else if (flag_code == CODE_64BIT)
4850 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4852 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4856 || !(i.base_reg->reg_type & Acc)
4857 || !(i.base_reg->reg_type & RegXX)
4859 || (i.types[0] & Disp))
4862 else if (flag_code == CODE_64BIT)
4864 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4867 && ((i.base_reg->reg_type & RegXX) == 0)
4868 && (i.base_reg->reg_type != BaseIndex
4871 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4872 != (RegXX | BaseIndex))))
4877 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4881 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4882 != (Reg16 | BaseIndex)))
4884 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4885 != (Reg16 | BaseIndex))
4887 && i.base_reg->reg_num < 6
4888 && i.index_reg->reg_num >= 6
4889 && i.log2_scale_factor == 0))))
4896 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4898 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4899 != (Reg32 | BaseIndex))))
4905 #if INFER_ADDR_PREFIX
4906 if (i.prefix[ADDR_PREFIX] == 0)
4908 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4910 /* Change the size of any displacement too. At most one of
4911 Disp16 or Disp32 is set.
4912 FIXME. There doesn't seem to be any real need for separate
4913 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4914 Removing them would probably clean up the code quite a lot. */
4915 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4916 i.types[this_operand] ^= (Disp16 | Disp32);
4921 as_bad (_("`%s' is not a valid base/index expression"),
4925 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4927 flag_code_names[flag_code]);
4932 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4936 i386_operand (operand_string)
4937 char *operand_string;
4941 char *op_string = operand_string;
4943 if (is_space_char (*op_string))
4946 /* We check for an absolute prefix (differentiating,
4947 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4948 if (*op_string == ABSOLUTE_PREFIX)
4951 if (is_space_char (*op_string))
4953 i.types[this_operand] |= JumpAbsolute;
4956 /* Check if operand is a register. */
4957 if ((r = parse_register (op_string, &end_op)) != NULL)
4959 /* Check for a segment override by searching for ':' after a
4960 segment register. */
4962 if (is_space_char (*op_string))
4964 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4969 i.seg[i.mem_operands] = &es;
4972 i.seg[i.mem_operands] = &cs;
4975 i.seg[i.mem_operands] = &ss;
4978 i.seg[i.mem_operands] = &ds;
4981 i.seg[i.mem_operands] = &fs;
4984 i.seg[i.mem_operands] = &gs;
4988 /* Skip the ':' and whitespace. */
4990 if (is_space_char (*op_string))
4993 if (!is_digit_char (*op_string)
4994 && !is_identifier_char (*op_string)
4995 && *op_string != '('
4996 && *op_string != ABSOLUTE_PREFIX)
4998 as_bad (_("bad memory operand `%s'"), op_string);
5001 /* Handle case of %es:*foo. */
5002 if (*op_string == ABSOLUTE_PREFIX)
5005 if (is_space_char (*op_string))
5007 i.types[this_operand] |= JumpAbsolute;
5009 goto do_memory_reference;
5013 as_bad (_("junk `%s' after register"), op_string);
5016 i.types[this_operand] |= r->reg_type & ~BaseIndex;
5017 i.op[this_operand].regs = r;
5020 else if (*op_string == REGISTER_PREFIX)
5022 as_bad (_("bad register name `%s'"), op_string);
5025 else if (*op_string == IMMEDIATE_PREFIX)
5028 if (i.types[this_operand] & JumpAbsolute)
5030 as_bad (_("immediate operand illegal with absolute jump"));
5033 if (!i386_immediate (op_string))
5036 else if (is_digit_char (*op_string)
5037 || is_identifier_char (*op_string)
5038 || *op_string == '(')
5040 /* This is a memory reference of some sort. */
5043 /* Start and end of displacement string expression (if found). */
5044 char *displacement_string_start;
5045 char *displacement_string_end;
5047 do_memory_reference:
5048 if ((i.mem_operands == 1
5049 && (current_templates->start->opcode_modifier & IsString) == 0)
5050 || i.mem_operands == 2)
5052 as_bad (_("too many memory references for `%s'"),
5053 current_templates->start->name);
5057 /* Check for base index form. We detect the base index form by
5058 looking for an ')' at the end of the operand, searching
5059 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5061 base_string = op_string + strlen (op_string);
5064 if (is_space_char (*base_string))
5067 /* If we only have a displacement, set-up for it to be parsed later. */
5068 displacement_string_start = op_string;
5069 displacement_string_end = base_string + 1;
5071 if (*base_string == ')')
5074 unsigned int parens_balanced = 1;
5075 /* We've already checked that the number of left & right ()'s are
5076 equal, so this loop will not be infinite. */
5080 if (*base_string == ')')
5082 if (*base_string == '(')
5085 while (parens_balanced);
5087 temp_string = base_string;
5089 /* Skip past '(' and whitespace. */
5091 if (is_space_char (*base_string))
5094 if (*base_string == ','
5095 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
5097 displacement_string_end = temp_string;
5099 i.types[this_operand] |= BaseIndex;
5103 base_string = end_op;
5104 if (is_space_char (*base_string))
5108 /* There may be an index reg or scale factor here. */
5109 if (*base_string == ',')
5112 if (is_space_char (*base_string))
5115 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5117 base_string = end_op;
5118 if (is_space_char (*base_string))
5120 if (*base_string == ',')
5123 if (is_space_char (*base_string))
5126 else if (*base_string != ')')
5128 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5133 else if (*base_string == REGISTER_PREFIX)
5135 as_bad (_("bad register name `%s'"), base_string);
5139 /* Check for scale factor. */
5140 if (*base_string != ')')
5142 char *end_scale = i386_scale (base_string);
5147 base_string = end_scale;
5148 if (is_space_char (*base_string))
5150 if (*base_string != ')')
5152 as_bad (_("expecting `)' after scale factor in `%s'"),
5157 else if (!i.index_reg)
5159 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5164 else if (*base_string != ')')
5166 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5171 else if (*base_string == REGISTER_PREFIX)
5173 as_bad (_("bad register name `%s'"), base_string);
5178 /* If there's an expression beginning the operand, parse it,
5179 assuming displacement_string_start and
5180 displacement_string_end are meaningful. */
5181 if (displacement_string_start != displacement_string_end)
5183 if (!i386_displacement (displacement_string_start,
5184 displacement_string_end))
5188 /* Special case for (%dx) while doing input/output op. */
5190 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5192 && i.log2_scale_factor == 0
5193 && i.seg[i.mem_operands] == 0
5194 && (i.types[this_operand] & Disp) == 0)
5196 i.types[this_operand] = InOutPortReg;
5200 if (i386_index_check (operand_string) == 0)
5206 /* It's not a memory operand; argh! */
5207 as_bad (_("invalid char %s beginning operand %d `%s'"),
5208 output_invalid (*op_string),
5213 return 1; /* Normal return. */
5216 /* md_estimate_size_before_relax()
5218 Called just before relax() for rs_machine_dependent frags. The x86
5219 assembler uses these frags to handle variable size jump
5222 Any symbol that is now undefined will not become defined.
5223 Return the correct fr_subtype in the frag.
5224 Return the initial "guess for variable size of frag" to caller.
5225 The guess is actually the growth beyond the fixed part. Whatever
5226 we do to grow the fixed or variable part contributes to our
5230 md_estimate_size_before_relax (fragP, segment)
5234 /* We've already got fragP->fr_subtype right; all we have to do is
5235 check for un-relaxable symbols. On an ELF system, we can't relax
5236 an externally visible symbol, because it may be overridden by a
5238 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5241 && (S_IS_EXTERNAL (fragP->fr_symbol)
5242 || S_IS_WEAK (fragP->fr_symbol)))
5246 /* Symbol is undefined in this segment, or we need to keep a
5247 reloc so that weak symbols can be overridden. */
5248 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5249 enum bfd_reloc_code_real reloc_type;
5250 unsigned char *opcode;
5253 if (fragP->fr_var != NO_RELOC)
5254 reloc_type = fragP->fr_var;
5256 reloc_type = BFD_RELOC_16_PCREL;
5258 reloc_type = BFD_RELOC_32_PCREL;
5260 old_fr_fix = fragP->fr_fix;
5261 opcode = (unsigned char *) fragP->fr_opcode;
5263 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5266 /* Make jmp (0xeb) a (d)word displacement jump. */
5268 fragP->fr_fix += size;
5269 fix_new (fragP, old_fr_fix, size,
5271 fragP->fr_offset, 1,
5277 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5279 /* Negate the condition, and branch past an
5280 unconditional jump. */
5283 /* Insert an unconditional jump. */
5285 /* We added two extra opcode bytes, and have a two byte
5287 fragP->fr_fix += 2 + 2;
5288 fix_new (fragP, old_fr_fix + 2, 2,
5290 fragP->fr_offset, 1,
5297 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5302 fixP = fix_new (fragP, old_fr_fix, 1,
5304 fragP->fr_offset, 1,
5306 fixP->fx_signed = 1;
5310 /* This changes the byte-displacement jump 0x7N
5311 to the (d)word-displacement jump 0x0f,0x8N. */
5312 opcode[1] = opcode[0] + 0x10;
5313 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5314 /* We've added an opcode byte. */
5315 fragP->fr_fix += 1 + size;
5316 fix_new (fragP, old_fr_fix + 1, size,
5318 fragP->fr_offset, 1,
5323 BAD_CASE (fragP->fr_subtype);
5327 return fragP->fr_fix - old_fr_fix;
5330 /* Guess size depending on current relax state. Initially the relax
5331 state will correspond to a short jump and we return 1, because
5332 the variable part of the frag (the branch offset) is one byte
5333 long. However, we can relax a section more than once and in that
5334 case we must either set fr_subtype back to the unrelaxed state,
5335 or return the value for the appropriate branch. */
5336 return md_relax_table[fragP->fr_subtype].rlx_length;
5339 /* Called after relax() is finished.
5341 In: Address of frag.
5342 fr_type == rs_machine_dependent.
5343 fr_subtype is what the address relaxed to.
5345 Out: Any fixSs and constants are set up.
5346 Caller will turn frag into a ".space 0". */
5349 md_convert_frag (abfd, sec, fragP)
5350 bfd *abfd ATTRIBUTE_UNUSED;
5351 segT sec ATTRIBUTE_UNUSED;
5354 unsigned char *opcode;
5355 unsigned char *where_to_put_displacement = NULL;
5356 offsetT target_address;
5357 offsetT opcode_address;
5358 unsigned int extension = 0;
5359 offsetT displacement_from_opcode_start;
5361 opcode = (unsigned char *) fragP->fr_opcode;
5363 /* Address we want to reach in file space. */
5364 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5366 /* Address opcode resides at in file space. */
5367 opcode_address = fragP->fr_address + fragP->fr_fix;
5369 /* Displacement from opcode start to fill into instruction. */
5370 displacement_from_opcode_start = target_address - opcode_address;
5372 if ((fragP->fr_subtype & BIG) == 0)
5374 /* Don't have to change opcode. */
5375 extension = 1; /* 1 opcode + 1 displacement */
5376 where_to_put_displacement = &opcode[1];
5380 if (no_cond_jump_promotion
5381 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5382 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5384 switch (fragP->fr_subtype)
5386 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5387 extension = 4; /* 1 opcode + 4 displacement */
5389 where_to_put_displacement = &opcode[1];
5392 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5393 extension = 2; /* 1 opcode + 2 displacement */
5395 where_to_put_displacement = &opcode[1];
5398 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5399 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5400 extension = 5; /* 2 opcode + 4 displacement */
5401 opcode[1] = opcode[0] + 0x10;
5402 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5403 where_to_put_displacement = &opcode[2];
5406 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5407 extension = 3; /* 2 opcode + 2 displacement */
5408 opcode[1] = opcode[0] + 0x10;
5409 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5410 where_to_put_displacement = &opcode[2];
5413 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5418 where_to_put_displacement = &opcode[3];
5422 BAD_CASE (fragP->fr_subtype);
5427 /* If size if less then four we are sure that the operand fits,
5428 but if it's 4, then it could be that the displacement is larger
5430 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5432 && ((addressT) (displacement_from_opcode_start - extension
5433 + ((addressT) 1 << 31))
5434 > (((addressT) 2 << 31) - 1)))
5436 as_bad_where (fragP->fr_file, fragP->fr_line,
5437 _("jump target out of range"));
5438 /* Make us emit 0. */
5439 displacement_from_opcode_start = extension;
5441 /* Now put displacement after opcode. */
5442 md_number_to_chars ((char *) where_to_put_displacement,
5443 (valueT) (displacement_from_opcode_start - extension),
5444 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5445 fragP->fr_fix += extension;
5448 /* Size of byte displacement jmp. */
5449 int md_short_jump_size = 2;
5451 /* Size of dword displacement jmp. */
5452 int md_long_jump_size = 5;
5455 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5457 addressT from_addr, to_addr;
5458 fragS *frag ATTRIBUTE_UNUSED;
5459 symbolS *to_symbol ATTRIBUTE_UNUSED;
5463 offset = to_addr - (from_addr + 2);
5464 /* Opcode for byte-disp jump. */
5465 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5466 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5470 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5472 addressT from_addr, to_addr;
5473 fragS *frag ATTRIBUTE_UNUSED;
5474 symbolS *to_symbol ATTRIBUTE_UNUSED;
5478 offset = to_addr - (from_addr + 5);
5479 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5480 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5483 /* Apply a fixup (fixS) to segment data, once it has been determined
5484 by our caller that we have all the info we need to fix it up.
5486 On the 386, immediates, displacements, and data pointers are all in
5487 the same (little-endian) format, so we don't need to care about which
5491 md_apply_fix (fixP, valP, seg)
5492 /* The fix we're to put in. */
5494 /* Pointer to the value of the bits. */
5496 /* Segment fix is from. */
5497 segT seg ATTRIBUTE_UNUSED;
5499 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5500 valueT value = *valP;
5502 #if !defined (TE_Mach)
5505 switch (fixP->fx_r_type)
5511 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5514 case BFD_RELOC_X86_64_32S:
5515 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5518 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5521 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5526 if (fixP->fx_addsy != NULL
5527 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5528 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5529 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5530 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5531 && !use_rela_relocations)
5533 /* This is a hack. There should be a better way to handle this.
5534 This covers for the fact that bfd_install_relocation will
5535 subtract the current location (for partial_inplace, PC relative
5536 relocations); see more below. */
5540 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5543 value += fixP->fx_where + fixP->fx_frag->fr_address;
5545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5548 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5551 || (symbol_section_p (fixP->fx_addsy)
5552 && sym_seg != absolute_section))
5553 && !generic_force_reloc (fixP))
5555 /* Yes, we add the values in twice. This is because
5556 bfd_install_relocation subtracts them out again. I think
5557 bfd_install_relocation is broken, but I don't dare change
5559 value += fixP->fx_where + fixP->fx_frag->fr_address;
5563 #if defined (OBJ_COFF) && defined (TE_PE)
5564 /* For some reason, the PE format does not store a
5565 section address offset for a PC relative symbol. */
5566 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5567 || S_IS_WEAK (fixP->fx_addsy))
5568 value += md_pcrel_from (fixP);
5572 /* Fix a few things - the dynamic linker expects certain values here,
5573 and we must not disappoint it. */
5574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5575 if (IS_ELF && fixP->fx_addsy)
5576 switch (fixP->fx_r_type)
5578 case BFD_RELOC_386_PLT32:
5579 case BFD_RELOC_X86_64_PLT32:
5580 /* Make the jump instruction point to the address of the operand. At
5581 runtime we merely add the offset to the actual PLT entry. */
5585 case BFD_RELOC_386_TLS_GD:
5586 case BFD_RELOC_386_TLS_LDM:
5587 case BFD_RELOC_386_TLS_IE_32:
5588 case BFD_RELOC_386_TLS_IE:
5589 case BFD_RELOC_386_TLS_GOTIE:
5590 case BFD_RELOC_386_TLS_GOTDESC:
5591 case BFD_RELOC_X86_64_TLSGD:
5592 case BFD_RELOC_X86_64_TLSLD:
5593 case BFD_RELOC_X86_64_GOTTPOFF:
5594 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5595 value = 0; /* Fully resolved at runtime. No addend. */
5597 case BFD_RELOC_386_TLS_LE:
5598 case BFD_RELOC_386_TLS_LDO_32:
5599 case BFD_RELOC_386_TLS_LE_32:
5600 case BFD_RELOC_X86_64_DTPOFF32:
5601 case BFD_RELOC_X86_64_DTPOFF64:
5602 case BFD_RELOC_X86_64_TPOFF32:
5603 case BFD_RELOC_X86_64_TPOFF64:
5604 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5607 case BFD_RELOC_386_TLS_DESC_CALL:
5608 case BFD_RELOC_X86_64_TLSDESC_CALL:
5609 value = 0; /* Fully resolved at runtime. No addend. */
5610 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5614 case BFD_RELOC_386_GOT32:
5615 case BFD_RELOC_X86_64_GOT32:
5616 value = 0; /* Fully resolved at runtime. No addend. */
5619 case BFD_RELOC_VTABLE_INHERIT:
5620 case BFD_RELOC_VTABLE_ENTRY:
5627 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5629 #endif /* !defined (TE_Mach) */
5631 /* Are we finished with this relocation now? */
5632 if (fixP->fx_addsy == NULL)
5634 else if (use_rela_relocations)
5636 fixP->fx_no_overflow = 1;
5637 /* Remember value for tc_gen_reloc. */
5638 fixP->fx_addnumber = value;
5642 md_number_to_chars (p, value, fixP->fx_size);
5645 #define MAX_LITTLENUMS 6
5647 /* Turn the string pointed to by litP into a floating point constant
5648 of type TYPE, and emit the appropriate bytes. The number of
5649 LITTLENUMS emitted is stored in *SIZEP. An error message is
5650 returned, or NULL on OK. */
5653 md_atof (type, litP, sizeP)
5659 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5660 LITTLENUM_TYPE *wordP;
5682 return _("Bad call to md_atof ()");
5684 t = atof_ieee (input_line_pointer, type, words);
5686 input_line_pointer = t;
5688 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5689 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5690 the bigendian 386. */
5691 for (wordP = words + prec - 1; prec--;)
5693 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5694 litP += sizeof (LITTLENUM_TYPE);
5699 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5706 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5709 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5710 "(0x%x)", (unsigned char) c);
5711 return output_invalid_buf;
5714 /* REG_STRING starts *before* REGISTER_PREFIX. */
5716 static const reg_entry *
5717 parse_real_register (char *reg_string, char **end_op)
5719 char *s = reg_string;
5721 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5724 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5725 if (*s == REGISTER_PREFIX)
5728 if (is_space_char (*s))
5732 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5734 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5735 return (const reg_entry *) NULL;
5739 /* For naked regs, make sure that we are not dealing with an identifier.
5740 This prevents confusing an identifier like `eax_var' with register
5742 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5743 return (const reg_entry *) NULL;
5747 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5749 /* Handle floating point regs, allowing spaces in the (i) part. */
5750 if (r == i386_regtab /* %st is first entry of table */)
5752 if (is_space_char (*s))
5757 if (is_space_char (*s))
5759 if (*s >= '0' && *s <= '7')
5761 r = &i386_float_regtab[*s - '0'];
5763 if (is_space_char (*s))
5771 /* We have "%st(" then garbage. */
5772 return (const reg_entry *) NULL;
5777 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5778 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5779 && flag_code != CODE_64BIT)
5780 return (const reg_entry *) NULL;
5785 /* REG_STRING starts *before* REGISTER_PREFIX. */
5787 static const reg_entry *
5788 parse_register (char *reg_string, char **end_op)
5792 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5793 r = parse_real_register (reg_string, end_op);
5798 char *save = input_line_pointer;
5802 input_line_pointer = reg_string;
5803 c = get_symbol_end ();
5804 symbolP = symbol_find (reg_string);
5805 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5807 const expressionS *e = symbol_get_value_expression (symbolP);
5809 know (e->X_op == O_register);
5810 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5811 r = i386_regtab + e->X_add_number;
5812 *end_op = input_line_pointer;
5814 *input_line_pointer = c;
5815 input_line_pointer = save;
5821 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5824 char *end = input_line_pointer;
5827 r = parse_register (name, &input_line_pointer);
5828 if (r && end <= input_line_pointer)
5830 *nextcharP = *input_line_pointer;
5831 *input_line_pointer = 0;
5832 e->X_op = O_register;
5833 e->X_add_number = r - i386_regtab;
5836 input_line_pointer = end;
5842 md_operand (expressionS *e)
5844 if (*input_line_pointer == REGISTER_PREFIX)
5847 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5851 e->X_op = O_register;
5852 e->X_add_number = r - i386_regtab;
5853 input_line_pointer = end;
5859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5860 const char *md_shortopts = "kVQ:sqn";
5862 const char *md_shortopts = "qn";
5865 #define OPTION_32 (OPTION_MD_BASE + 0)
5866 #define OPTION_64 (OPTION_MD_BASE + 1)
5867 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5868 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5869 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5871 struct option md_longopts[] =
5873 {"32", no_argument, NULL, OPTION_32},
5874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5875 {"64", no_argument, NULL, OPTION_64},
5877 {"divide", no_argument, NULL, OPTION_DIVIDE},
5878 {"march", required_argument, NULL, OPTION_MARCH},
5879 {"mtune", required_argument, NULL, OPTION_MTUNE},
5880 {NULL, no_argument, NULL, 0}
5882 size_t md_longopts_size = sizeof (md_longopts);
5885 md_parse_option (int c, char *arg)
5892 optimize_align_code = 0;
5899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5900 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5901 should be emitted or not. FIXME: Not implemented. */
5905 /* -V: SVR4 argument to print version ID. */
5907 print_version_id ();
5910 /* -k: Ignore for FreeBSD compatibility. */
5915 /* -s: On i386 Solaris, this tells the native assembler to use
5916 .stab instead of .stab.excl. We always use .stab anyhow. */
5919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5922 const char **list, **l;
5924 list = bfd_target_list ();
5925 for (l = list; *l != NULL; l++)
5926 if (CONST_STRNEQ (*l, "elf64-x86-64")
5927 || strcmp (*l, "coff-x86-64") == 0
5928 || strcmp (*l, "pe-x86-64") == 0
5929 || strcmp (*l, "pei-x86-64") == 0)
5931 default_arch = "x86_64";
5935 as_fatal (_("No compiled in support for x86_64"));
5942 default_arch = "i386";
5946 #ifdef SVR4_COMMENT_CHARS
5951 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5953 for (s = i386_comment_chars; *s != '\0'; s++)
5957 i386_comment_chars = n;
5964 as_fatal (_("Invalid -march= option: `%s'"), arg);
5965 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5967 if (strcmp (arg, cpu_arch [i].name) == 0)
5969 cpu_arch_isa = cpu_arch[i].type;
5970 cpu_arch_isa_flags = cpu_arch[i].flags;
5971 if (!cpu_arch_tune_set)
5973 cpu_arch_tune = cpu_arch_isa;
5974 cpu_arch_tune_flags = cpu_arch_isa_flags;
5979 if (i >= ARRAY_SIZE (cpu_arch))
5980 as_fatal (_("Invalid -march= option: `%s'"), arg);
5985 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5986 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5988 if (strcmp (arg, cpu_arch [i].name) == 0)
5990 cpu_arch_tune_set = 1;
5991 cpu_arch_tune = cpu_arch [i].type;
5992 cpu_arch_tune_flags = cpu_arch[i].flags;
5996 if (i >= ARRAY_SIZE (cpu_arch))
5997 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6007 md_show_usage (stream)
6010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6011 fprintf (stream, _("\
6013 -V print assembler version number\n\
6016 fprintf (stream, _("\
6017 -n Do not optimize code alignment\n\
6018 -q quieten some warnings\n"));
6019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6020 fprintf (stream, _("\
6023 #ifdef SVR4_COMMENT_CHARS
6024 fprintf (stream, _("\
6025 --divide do not treat `/' as a comment character\n"));
6027 fprintf (stream, _("\
6028 --divide ignored\n"));
6030 fprintf (stream, _("\
6031 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6032 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6033 core, core2, k6, athlon, k8, generic32, generic64\n"));
6039 x86_64_target_format (void)
6041 if (strcmp (default_arch, "x86_64") == 0)
6043 set_code_flag (CODE_64BIT);
6044 return COFF_TARGET_FORMAT;
6046 else if (strcmp (default_arch, "i386") == 0)
6048 set_code_flag (CODE_32BIT);
6052 as_fatal (_("Unknown architecture"));
6057 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6058 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6060 /* Pick the target format to use. */
6063 i386_target_format ()
6065 if (!strcmp (default_arch, "x86_64"))
6067 set_code_flag (CODE_64BIT);
6068 if (cpu_arch_isa_flags == 0)
6069 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6070 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6072 if (cpu_arch_tune_flags == 0)
6073 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6074 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6077 else if (!strcmp (default_arch, "i386"))
6079 set_code_flag (CODE_32BIT);
6080 if (cpu_arch_isa_flags == 0)
6081 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6082 if (cpu_arch_tune_flags == 0)
6083 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6086 as_fatal (_("Unknown architecture"));
6087 switch (OUTPUT_FLAVOR)
6089 #ifdef OBJ_MAYBE_AOUT
6090 case bfd_target_aout_flavour:
6091 return AOUT_TARGET_FORMAT;
6093 #ifdef OBJ_MAYBE_COFF
6094 case bfd_target_coff_flavour:
6097 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6098 case bfd_target_elf_flavour:
6100 if (flag_code == CODE_64BIT)
6103 use_rela_relocations = 1;
6105 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6114 #endif /* OBJ_MAYBE_ more than one */
6116 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6117 void i386_elf_emit_arch_note ()
6119 if (IS_ELF && cpu_arch_name != NULL)
6122 asection *seg = now_seg;
6123 subsegT subseg = now_subseg;
6124 Elf_Internal_Note i_note;
6125 Elf_External_Note e_note;
6126 asection *note_secp;
6129 /* Create the .note section. */
6130 note_secp = subseg_new (".note", 0);
6131 bfd_set_section_flags (stdoutput,
6133 SEC_HAS_CONTENTS | SEC_READONLY);
6135 /* Process the arch string. */
6136 len = strlen (cpu_arch_name);
6138 i_note.namesz = len + 1;
6140 i_note.type = NT_ARCH;
6141 p = frag_more (sizeof (e_note.namesz));
6142 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6143 p = frag_more (sizeof (e_note.descsz));
6144 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6145 p = frag_more (sizeof (e_note.type));
6146 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6147 p = frag_more (len + 1);
6148 strcpy (p, cpu_arch_name);
6150 frag_align (2, 0, 0);
6152 subseg_set (seg, subseg);
6158 md_undefined_symbol (name)
6161 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6162 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6163 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6164 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6168 if (symbol_find (name))
6169 as_bad (_("GOT already in symbol table"));
6170 GOT_symbol = symbol_new (name, undefined_section,
6171 (valueT) 0, &zero_address_frag);
6178 /* Round up a section size to the appropriate boundary. */
6181 md_section_align (segment, size)
6182 segT segment ATTRIBUTE_UNUSED;
6185 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6186 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6188 /* For a.out, force the section size to be aligned. If we don't do
6189 this, BFD will align it for us, but it will not write out the
6190 final bytes of the section. This may be a bug in BFD, but it is
6191 easier to fix it here since that is how the other a.out targets
6195 align = bfd_get_section_alignment (stdoutput, segment);
6196 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6203 /* On the i386, PC-relative offsets are relative to the start of the
6204 next instruction. That is, the address of the offset, plus its
6205 size, since the offset is always the last part of the insn. */
6208 md_pcrel_from (fixP)
6211 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6218 int ignore ATTRIBUTE_UNUSED;
6222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6224 obj_elf_section_change_hook ();
6226 temp = get_absolute_expression ();
6227 subseg_set (bss_section, (subsegT) temp);
6228 demand_empty_rest_of_line ();
6234 i386_validate_fix (fixp)
6237 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6239 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6243 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6248 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6250 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6257 tc_gen_reloc (section, fixp)
6258 asection *section ATTRIBUTE_UNUSED;
6262 bfd_reloc_code_real_type code;
6264 switch (fixp->fx_r_type)
6266 case BFD_RELOC_X86_64_PLT32:
6267 case BFD_RELOC_X86_64_GOT32:
6268 case BFD_RELOC_X86_64_GOTPCREL:
6269 case BFD_RELOC_386_PLT32:
6270 case BFD_RELOC_386_GOT32:
6271 case BFD_RELOC_386_GOTOFF:
6272 case BFD_RELOC_386_GOTPC:
6273 case BFD_RELOC_386_TLS_GD:
6274 case BFD_RELOC_386_TLS_LDM:
6275 case BFD_RELOC_386_TLS_LDO_32:
6276 case BFD_RELOC_386_TLS_IE_32:
6277 case BFD_RELOC_386_TLS_IE:
6278 case BFD_RELOC_386_TLS_GOTIE:
6279 case BFD_RELOC_386_TLS_LE_32:
6280 case BFD_RELOC_386_TLS_LE:
6281 case BFD_RELOC_386_TLS_GOTDESC:
6282 case BFD_RELOC_386_TLS_DESC_CALL:
6283 case BFD_RELOC_X86_64_TLSGD:
6284 case BFD_RELOC_X86_64_TLSLD:
6285 case BFD_RELOC_X86_64_DTPOFF32:
6286 case BFD_RELOC_X86_64_DTPOFF64:
6287 case BFD_RELOC_X86_64_GOTTPOFF:
6288 case BFD_RELOC_X86_64_TPOFF32:
6289 case BFD_RELOC_X86_64_TPOFF64:
6290 case BFD_RELOC_X86_64_GOTOFF64:
6291 case BFD_RELOC_X86_64_GOTPC32:
6292 case BFD_RELOC_X86_64_GOT64:
6293 case BFD_RELOC_X86_64_GOTPCREL64:
6294 case BFD_RELOC_X86_64_GOTPC64:
6295 case BFD_RELOC_X86_64_GOTPLT64:
6296 case BFD_RELOC_X86_64_PLTOFF64:
6297 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6298 case BFD_RELOC_X86_64_TLSDESC_CALL:
6300 case BFD_RELOC_VTABLE_ENTRY:
6301 case BFD_RELOC_VTABLE_INHERIT:
6303 case BFD_RELOC_32_SECREL:
6305 code = fixp->fx_r_type;
6307 case BFD_RELOC_X86_64_32S:
6308 if (!fixp->fx_pcrel)
6310 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6311 code = fixp->fx_r_type;
6317 switch (fixp->fx_size)
6320 as_bad_where (fixp->fx_file, fixp->fx_line,
6321 _("can not do %d byte pc-relative relocation"),
6323 code = BFD_RELOC_32_PCREL;
6325 case 1: code = BFD_RELOC_8_PCREL; break;
6326 case 2: code = BFD_RELOC_16_PCREL; break;
6327 case 4: code = BFD_RELOC_32_PCREL; break;
6329 case 8: code = BFD_RELOC_64_PCREL; break;
6335 switch (fixp->fx_size)
6338 as_bad_where (fixp->fx_file, fixp->fx_line,
6339 _("can not do %d byte relocation"),
6341 code = BFD_RELOC_32;
6343 case 1: code = BFD_RELOC_8; break;
6344 case 2: code = BFD_RELOC_16; break;
6345 case 4: code = BFD_RELOC_32; break;
6347 case 8: code = BFD_RELOC_64; break;
6354 if ((code == BFD_RELOC_32
6355 || code == BFD_RELOC_32_PCREL
6356 || code == BFD_RELOC_X86_64_32S)
6358 && fixp->fx_addsy == GOT_symbol)
6361 code = BFD_RELOC_386_GOTPC;
6363 code = BFD_RELOC_X86_64_GOTPC32;
6365 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6367 && fixp->fx_addsy == GOT_symbol)
6369 code = BFD_RELOC_X86_64_GOTPC64;
6372 rel = (arelent *) xmalloc (sizeof (arelent));
6373 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6374 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6376 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6378 if (!use_rela_relocations)
6380 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6381 vtable entry to be used in the relocation's section offset. */
6382 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6383 rel->address = fixp->fx_offset;
6387 /* Use the rela in 64bit mode. */
6390 if (!fixp->fx_pcrel)
6391 rel->addend = fixp->fx_offset;
6395 case BFD_RELOC_X86_64_PLT32:
6396 case BFD_RELOC_X86_64_GOT32:
6397 case BFD_RELOC_X86_64_GOTPCREL:
6398 case BFD_RELOC_X86_64_TLSGD:
6399 case BFD_RELOC_X86_64_TLSLD:
6400 case BFD_RELOC_X86_64_GOTTPOFF:
6401 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6402 case BFD_RELOC_X86_64_TLSDESC_CALL:
6403 rel->addend = fixp->fx_offset - fixp->fx_size;
6406 rel->addend = (section->vma
6408 + fixp->fx_addnumber
6409 + md_pcrel_from (fixp));
6414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6415 if (rel->howto == NULL)
6417 as_bad_where (fixp->fx_file, fixp->fx_line,
6418 _("cannot represent relocation type %s"),
6419 bfd_get_reloc_code_name (code));
6420 /* Set howto to a garbage value so that we can keep going. */
6421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6422 assert (rel->howto != NULL);
6429 /* Parse operands using Intel syntax. This implements a recursive descent
6430 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6433 FIXME: We do not recognize the full operand grammar defined in the MASM
6434 documentation. In particular, all the structure/union and
6435 high-level macro operands are missing.
6437 Uppercase words are terminals, lower case words are non-terminals.
6438 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6439 bars '|' denote choices. Most grammar productions are implemented in
6440 functions called 'intel_<production>'.
6442 Initial production is 'expr'.
6448 binOp & | AND | \| | OR | ^ | XOR
6450 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6452 constant digits [[ radixOverride ]]
6454 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6492 => expr expr cmpOp e04
6495 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6496 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6498 hexdigit a | b | c | d | e | f
6499 | A | B | C | D | E | F
6505 mulOp * | / | % | MOD | << | SHL | >> | SHR
6509 register specialRegister
6513 segmentRegister CS | DS | ES | FS | GS | SS
6515 specialRegister CR0 | CR2 | CR3 | CR4
6516 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6517 | TR3 | TR4 | TR5 | TR6 | TR7
6519 We simplify the grammar in obvious places (e.g., register parsing is
6520 done by calling parse_register) and eliminate immediate left recursion
6521 to implement a recursive-descent parser.
6525 expr' cmpOp e04 expr'
6576 /* Parsing structure for the intel syntax parser. Used to implement the
6577 semantic actions for the operand grammar. */
6578 struct intel_parser_s
6580 char *op_string; /* The string being parsed. */
6581 int got_a_float; /* Whether the operand is a float. */
6582 int op_modifier; /* Operand modifier. */
6583 int is_mem; /* 1 if operand is memory reference. */
6584 int in_offset; /* >=1 if parsing operand of offset. */
6585 int in_bracket; /* >=1 if parsing operand in brackets. */
6586 const reg_entry *reg; /* Last register reference found. */
6587 char *disp; /* Displacement string being built. */
6588 char *next_operand; /* Resume point when splitting operands. */
6591 static struct intel_parser_s intel_parser;
6593 /* Token structure for parsing intel syntax. */
6596 int code; /* Token code. */
6597 const reg_entry *reg; /* Register entry for register tokens. */
6598 char *str; /* String representation. */
6601 static struct intel_token cur_token, prev_token;
6603 /* Token codes for the intel parser. Since T_SHORT is already used
6604 by COFF, undefine it first to prevent a warning. */
6623 /* Prototypes for intel parser functions. */
6624 static int intel_match_token PARAMS ((int code));
6625 static void intel_get_token PARAMS ((void));
6626 static void intel_putback_token PARAMS ((void));
6627 static int intel_expr PARAMS ((void));
6628 static int intel_e04 PARAMS ((void));
6629 static int intel_e05 PARAMS ((void));
6630 static int intel_e06 PARAMS ((void));
6631 static int intel_e09 PARAMS ((void));
6632 static int intel_bracket_expr PARAMS ((void));
6633 static int intel_e10 PARAMS ((void));
6634 static int intel_e11 PARAMS ((void));
6637 i386_intel_operand (operand_string, got_a_float)
6638 char *operand_string;
6644 p = intel_parser.op_string = xstrdup (operand_string);
6645 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6649 /* Initialize token holders. */
6650 cur_token.code = prev_token.code = T_NIL;
6651 cur_token.reg = prev_token.reg = NULL;
6652 cur_token.str = prev_token.str = NULL;
6654 /* Initialize parser structure. */
6655 intel_parser.got_a_float = got_a_float;
6656 intel_parser.op_modifier = 0;
6657 intel_parser.is_mem = 0;
6658 intel_parser.in_offset = 0;
6659 intel_parser.in_bracket = 0;
6660 intel_parser.reg = NULL;
6661 intel_parser.disp[0] = '\0';
6662 intel_parser.next_operand = NULL;
6664 /* Read the first token and start the parser. */
6666 ret = intel_expr ();
6671 if (cur_token.code != T_NIL)
6673 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6674 current_templates->start->name, cur_token.str);
6677 /* If we found a memory reference, hand it over to i386_displacement
6678 to fill in the rest of the operand fields. */
6679 else if (intel_parser.is_mem)
6681 if ((i.mem_operands == 1
6682 && (current_templates->start->opcode_modifier & IsString) == 0)
6683 || i.mem_operands == 2)
6685 as_bad (_("too many memory references for '%s'"),
6686 current_templates->start->name);
6691 char *s = intel_parser.disp;
6694 if (!quiet_warnings && intel_parser.is_mem < 0)
6695 /* See the comments in intel_bracket_expr. */
6696 as_warn (_("Treating `%s' as memory reference"), operand_string);
6698 /* Add the displacement expression. */
6700 ret = i386_displacement (s, s + strlen (s));
6703 /* Swap base and index in 16-bit memory operands like
6704 [si+bx]. Since i386_index_check is also used in AT&T
6705 mode we have to do that here. */
6708 && (i.base_reg->reg_type & Reg16)
6709 && (i.index_reg->reg_type & Reg16)
6710 && i.base_reg->reg_num >= 6
6711 && i.index_reg->reg_num < 6)
6713 const reg_entry *base = i.index_reg;
6715 i.index_reg = i.base_reg;
6718 ret = i386_index_check (operand_string);
6723 /* Constant and OFFSET expressions are handled by i386_immediate. */
6724 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6725 || intel_parser.reg == NULL)
6726 ret = i386_immediate (intel_parser.disp);
6728 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6730 if (!ret || !intel_parser.next_operand)
6732 intel_parser.op_string = intel_parser.next_operand;
6733 this_operand = i.operands++;
6737 free (intel_parser.disp);
6742 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6746 expr' cmpOp e04 expr'
6751 /* XXX Implement the comparison operators. */
6752 return intel_e04 ();
6769 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6770 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6772 if (cur_token.code == '+')
6774 else if (cur_token.code == '-')
6775 nregs = NUM_ADDRESS_REGS;
6779 strcat (intel_parser.disp, cur_token.str);
6780 intel_match_token (cur_token.code);
6791 int nregs = ~NUM_ADDRESS_REGS;
6798 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6802 str[0] = cur_token.code;
6804 strcat (intel_parser.disp, str);
6809 intel_match_token (cur_token.code);
6814 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6815 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6826 int nregs = ~NUM_ADDRESS_REGS;
6833 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6837 str[0] = cur_token.code;
6839 strcat (intel_parser.disp, str);
6841 else if (cur_token.code == T_SHL)
6842 strcat (intel_parser.disp, "<<");
6843 else if (cur_token.code == T_SHR)
6844 strcat (intel_parser.disp, ">>");
6848 intel_match_token (cur_token.code);
6853 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6854 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6872 int nregs = ~NUM_ADDRESS_REGS;
6877 /* Don't consume constants here. */
6878 if (cur_token.code == '+' || cur_token.code == '-')
6880 /* Need to look one token ahead - if the next token
6881 is a constant, the current token is its sign. */
6884 intel_match_token (cur_token.code);
6885 next_code = cur_token.code;
6886 intel_putback_token ();
6887 if (next_code == T_CONST)
6891 /* e09 OFFSET e09 */
6892 if (cur_token.code == T_OFFSET)
6895 ++intel_parser.in_offset;
6899 else if (cur_token.code == T_SHORT)
6900 intel_parser.op_modifier |= 1 << T_SHORT;
6903 else if (cur_token.code == '+')
6904 strcat (intel_parser.disp, "+");
6909 else if (cur_token.code == '-' || cur_token.code == '~')
6915 str[0] = cur_token.code;
6917 strcat (intel_parser.disp, str);
6924 intel_match_token (cur_token.code);
6932 /* e09' PTR e10 e09' */
6933 if (cur_token.code == T_PTR)
6937 if (prev_token.code == T_BYTE)
6938 suffix = BYTE_MNEM_SUFFIX;
6940 else if (prev_token.code == T_WORD)
6942 if (current_templates->start->name[0] == 'l'
6943 && current_templates->start->name[2] == 's'
6944 && current_templates->start->name[3] == 0)
6945 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6946 else if (intel_parser.got_a_float == 2) /* "fi..." */
6947 suffix = SHORT_MNEM_SUFFIX;
6949 suffix = WORD_MNEM_SUFFIX;
6952 else if (prev_token.code == T_DWORD)
6954 if (current_templates->start->name[0] == 'l'
6955 && current_templates->start->name[2] == 's'
6956 && current_templates->start->name[3] == 0)
6957 suffix = WORD_MNEM_SUFFIX;
6958 else if (flag_code == CODE_16BIT
6959 && (current_templates->start->opcode_modifier
6960 & (Jump | JumpDword)))
6961 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6962 else if (intel_parser.got_a_float == 1) /* "f..." */
6963 suffix = SHORT_MNEM_SUFFIX;
6965 suffix = LONG_MNEM_SUFFIX;
6968 else if (prev_token.code == T_FWORD)
6970 if (current_templates->start->name[0] == 'l'
6971 && current_templates->start->name[2] == 's'
6972 && current_templates->start->name[3] == 0)
6973 suffix = LONG_MNEM_SUFFIX;
6974 else if (!intel_parser.got_a_float)
6976 if (flag_code == CODE_16BIT)
6977 add_prefix (DATA_PREFIX_OPCODE);
6978 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6981 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6984 else if (prev_token.code == T_QWORD)
6986 if (intel_parser.got_a_float == 1) /* "f..." */
6987 suffix = LONG_MNEM_SUFFIX;
6989 suffix = QWORD_MNEM_SUFFIX;
6992 else if (prev_token.code == T_TBYTE)
6994 if (intel_parser.got_a_float == 1)
6995 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6997 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7000 else if (prev_token.code == T_XMMWORD)
7002 /* XXX ignored for now, but accepted since gcc uses it */
7008 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7012 /* Operands for jump/call using 'ptr' notation denote absolute
7014 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7015 i.types[this_operand] |= JumpAbsolute;
7017 if (current_templates->start->base_opcode == 0x8d /* lea */)
7021 else if (i.suffix != suffix)
7023 as_bad (_("Conflicting operand modifiers"));
7029 /* e09' : e10 e09' */
7030 else if (cur_token.code == ':')
7032 if (prev_token.code != T_REG)
7034 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7035 segment/group identifier (which we don't have), using comma
7036 as the operand separator there is even less consistent, since
7037 there all branches only have a single operand. */
7038 if (this_operand != 0
7039 || intel_parser.in_offset
7040 || intel_parser.in_bracket
7041 || (!(current_templates->start->opcode_modifier
7042 & (Jump|JumpDword|JumpInterSegment))
7043 && !(current_templates->start->operand_types[0]
7045 return intel_match_token (T_NIL);
7046 /* Remember the start of the 2nd operand and terminate 1st
7048 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7049 another expression), but it gets at least the simplest case
7050 (a plain number or symbol on the left side) right. */
7051 intel_parser.next_operand = intel_parser.op_string;
7052 *--intel_parser.op_string = '\0';
7053 return intel_match_token (':');
7061 intel_match_token (cur_token.code);
7067 --intel_parser.in_offset;
7070 if (NUM_ADDRESS_REGS > nregs)
7072 as_bad (_("Invalid operand to `OFFSET'"));
7075 intel_parser.op_modifier |= 1 << T_OFFSET;
7078 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7079 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7084 intel_bracket_expr ()
7086 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7087 const char *start = intel_parser.op_string;
7090 if (i.op[this_operand].regs)
7091 return intel_match_token (T_NIL);
7093 intel_match_token ('[');
7095 /* Mark as a memory operand only if it's not already known to be an
7096 offset expression. If it's an offset expression, we need to keep
7098 if (!intel_parser.in_offset)
7100 ++intel_parser.in_bracket;
7102 /* Operands for jump/call inside brackets denote absolute addresses. */
7103 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7104 i.types[this_operand] |= JumpAbsolute;
7106 /* Unfortunately gas always diverged from MASM in a respect that can't
7107 be easily fixed without risking to break code sequences likely to be
7108 encountered (the testsuite even check for this): MASM doesn't consider
7109 an expression inside brackets unconditionally as a memory reference.
7110 When that is e.g. a constant, an offset expression, or the sum of the
7111 two, this is still taken as a constant load. gas, however, always
7112 treated these as memory references. As a compromise, we'll try to make
7113 offset expressions inside brackets work the MASM way (since that's
7114 less likely to be found in real world code), but make constants alone
7115 continue to work the traditional gas way. In either case, issue a
7117 intel_parser.op_modifier &= ~was_offset;
7120 strcat (intel_parser.disp, "[");
7122 /* Add a '+' to the displacement string if necessary. */
7123 if (*intel_parser.disp != '\0'
7124 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7125 strcat (intel_parser.disp, "+");
7128 && (len = intel_parser.op_string - start - 1,
7129 intel_match_token (']')))
7131 /* Preserve brackets when the operand is an offset expression. */
7132 if (intel_parser.in_offset)
7133 strcat (intel_parser.disp, "]");
7136 --intel_parser.in_bracket;
7137 if (i.base_reg || i.index_reg)
7138 intel_parser.is_mem = 1;
7139 if (!intel_parser.is_mem)
7141 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7142 /* Defer the warning until all of the operand was parsed. */
7143 intel_parser.is_mem = -1;
7144 else if (!quiet_warnings)
7145 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7148 intel_parser.op_modifier |= was_offset;
7165 while (cur_token.code == '[')
7167 if (!intel_bracket_expr ())
7192 switch (cur_token.code)
7196 intel_match_token ('(');
7197 strcat (intel_parser.disp, "(");
7199 if (intel_expr () && intel_match_token (')'))
7201 strcat (intel_parser.disp, ")");
7208 return intel_bracket_expr ();
7213 strcat (intel_parser.disp, cur_token.str);
7214 intel_match_token (cur_token.code);
7216 /* Mark as a memory operand only if it's not already known to be an
7217 offset expression. */
7218 if (!intel_parser.in_offset)
7219 intel_parser.is_mem = 1;
7226 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7228 intel_match_token (T_REG);
7230 /* Check for segment change. */
7231 if (cur_token.code == ':')
7233 if (!(reg->reg_type & (SReg2 | SReg3)))
7235 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7238 else if (i.seg[i.mem_operands])
7239 as_warn (_("Extra segment override ignored"));
7242 if (!intel_parser.in_offset)
7243 intel_parser.is_mem = 1;
7244 switch (reg->reg_num)
7247 i.seg[i.mem_operands] = &es;
7250 i.seg[i.mem_operands] = &cs;
7253 i.seg[i.mem_operands] = &ss;
7256 i.seg[i.mem_operands] = &ds;
7259 i.seg[i.mem_operands] = &fs;
7262 i.seg[i.mem_operands] = &gs;
7268 /* Not a segment register. Check for register scaling. */
7269 else if (cur_token.code == '*')
7271 if (!intel_parser.in_bracket)
7273 as_bad (_("Register scaling only allowed in memory operands"));
7277 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7278 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7279 else if (i.index_reg)
7280 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7282 /* What follows must be a valid scale. */
7283 intel_match_token ('*');
7285 i.types[this_operand] |= BaseIndex;
7287 /* Set the scale after setting the register (otherwise,
7288 i386_scale will complain) */
7289 if (cur_token.code == '+' || cur_token.code == '-')
7291 char *str, sign = cur_token.code;
7292 intel_match_token (cur_token.code);
7293 if (cur_token.code != T_CONST)
7295 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7299 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7300 strcpy (str + 1, cur_token.str);
7302 if (!i386_scale (str))
7306 else if (!i386_scale (cur_token.str))
7308 intel_match_token (cur_token.code);
7311 /* No scaling. If this is a memory operand, the register is either a
7312 base register (first occurrence) or an index register (second
7314 else if (intel_parser.in_bracket)
7319 else if (!i.index_reg)
7323 as_bad (_("Too many register references in memory operand"));
7327 i.types[this_operand] |= BaseIndex;
7330 /* It's neither base nor index. */
7331 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7333 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7334 i.op[this_operand].regs = reg;
7339 as_bad (_("Invalid use of register"));
7343 /* Since registers are not part of the displacement string (except
7344 when we're parsing offset operands), we may need to remove any
7345 preceding '+' from the displacement string. */
7346 if (*intel_parser.disp != '\0'
7347 && !intel_parser.in_offset)
7349 char *s = intel_parser.disp;
7350 s += strlen (s) - 1;
7373 intel_match_token (cur_token.code);
7375 if (cur_token.code == T_PTR)
7378 /* It must have been an identifier. */
7379 intel_putback_token ();
7380 cur_token.code = T_ID;
7386 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7390 /* The identifier represents a memory reference only if it's not
7391 preceded by an offset modifier and if it's not an equate. */
7392 symbolP = symbol_find(cur_token.str);
7393 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7394 intel_parser.is_mem = 1;
7402 char *save_str, sign = 0;
7404 /* Allow constants that start with `+' or `-'. */
7405 if (cur_token.code == '-' || cur_token.code == '+')
7407 sign = cur_token.code;
7408 intel_match_token (cur_token.code);
7409 if (cur_token.code != T_CONST)
7411 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7417 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7418 strcpy (save_str + !!sign, cur_token.str);
7422 /* Get the next token to check for register scaling. */
7423 intel_match_token (cur_token.code);
7425 /* Check if this constant is a scaling factor for an index register. */
7426 if (cur_token.code == '*')
7428 if (intel_match_token ('*') && cur_token.code == T_REG)
7430 const reg_entry *reg = cur_token.reg;
7432 if (!intel_parser.in_bracket)
7434 as_bad (_("Register scaling only allowed in memory operands"));
7438 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7439 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7440 else if (i.index_reg)
7441 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7443 /* The constant is followed by `* reg', so it must be
7446 i.types[this_operand] |= BaseIndex;
7448 /* Set the scale after setting the register (otherwise,
7449 i386_scale will complain) */
7450 if (!i386_scale (save_str))
7452 intel_match_token (T_REG);
7454 /* Since registers are not part of the displacement
7455 string, we may need to remove any preceding '+' from
7456 the displacement string. */
7457 if (*intel_parser.disp != '\0')
7459 char *s = intel_parser.disp;
7460 s += strlen (s) - 1;
7470 /* The constant was not used for register scaling. Since we have
7471 already consumed the token following `*' we now need to put it
7472 back in the stream. */
7473 intel_putback_token ();
7476 /* Add the constant to the displacement string. */
7477 strcat (intel_parser.disp, save_str);
7484 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7488 /* Match the given token against cur_token. If they match, read the next
7489 token from the operand string. */
7491 intel_match_token (code)
7494 if (cur_token.code == code)
7501 as_bad (_("Unexpected token `%s'"), cur_token.str);
7506 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7511 const reg_entry *reg;
7512 struct intel_token new_token;
7514 new_token.code = T_NIL;
7515 new_token.reg = NULL;
7516 new_token.str = NULL;
7518 /* Free the memory allocated to the previous token and move
7519 cur_token to prev_token. */
7521 free (prev_token.str);
7523 prev_token = cur_token;
7525 /* Skip whitespace. */
7526 while (is_space_char (*intel_parser.op_string))
7527 intel_parser.op_string++;
7529 /* Return an empty token if we find nothing else on the line. */
7530 if (*intel_parser.op_string == '\0')
7532 cur_token = new_token;
7536 /* The new token cannot be larger than the remainder of the operand
7538 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7539 new_token.str[0] = '\0';
7541 if (strchr ("0123456789", *intel_parser.op_string))
7543 char *p = new_token.str;
7544 char *q = intel_parser.op_string;
7545 new_token.code = T_CONST;
7547 /* Allow any kind of identifier char to encompass floating point and
7548 hexadecimal numbers. */
7549 while (is_identifier_char (*q))
7553 /* Recognize special symbol names [0-9][bf]. */
7554 if (strlen (intel_parser.op_string) == 2
7555 && (intel_parser.op_string[1] == 'b'
7556 || intel_parser.op_string[1] == 'f'))
7557 new_token.code = T_ID;
7560 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7562 size_t len = end_op - intel_parser.op_string;
7564 new_token.code = T_REG;
7565 new_token.reg = reg;
7567 memcpy (new_token.str, intel_parser.op_string, len);
7568 new_token.str[len] = '\0';
7571 else if (is_identifier_char (*intel_parser.op_string))
7573 char *p = new_token.str;
7574 char *q = intel_parser.op_string;
7576 /* A '.' or '$' followed by an identifier char is an identifier.
7577 Otherwise, it's operator '.' followed by an expression. */
7578 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7580 new_token.code = '.';
7581 new_token.str[0] = '.';
7582 new_token.str[1] = '\0';
7586 while (is_identifier_char (*q) || *q == '@')
7590 if (strcasecmp (new_token.str, "NOT") == 0)
7591 new_token.code = '~';
7593 else if (strcasecmp (new_token.str, "MOD") == 0)
7594 new_token.code = '%';
7596 else if (strcasecmp (new_token.str, "AND") == 0)
7597 new_token.code = '&';
7599 else if (strcasecmp (new_token.str, "OR") == 0)
7600 new_token.code = '|';
7602 else if (strcasecmp (new_token.str, "XOR") == 0)
7603 new_token.code = '^';
7605 else if (strcasecmp (new_token.str, "SHL") == 0)
7606 new_token.code = T_SHL;
7608 else if (strcasecmp (new_token.str, "SHR") == 0)
7609 new_token.code = T_SHR;
7611 else if (strcasecmp (new_token.str, "BYTE") == 0)
7612 new_token.code = T_BYTE;
7614 else if (strcasecmp (new_token.str, "WORD") == 0)
7615 new_token.code = T_WORD;
7617 else if (strcasecmp (new_token.str, "DWORD") == 0)
7618 new_token.code = T_DWORD;
7620 else if (strcasecmp (new_token.str, "FWORD") == 0)
7621 new_token.code = T_FWORD;
7623 else if (strcasecmp (new_token.str, "QWORD") == 0)
7624 new_token.code = T_QWORD;
7626 else if (strcasecmp (new_token.str, "TBYTE") == 0
7627 /* XXX remove (gcc still uses it) */
7628 || strcasecmp (new_token.str, "XWORD") == 0)
7629 new_token.code = T_TBYTE;
7631 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7632 || strcasecmp (new_token.str, "OWORD") == 0)
7633 new_token.code = T_XMMWORD;
7635 else if (strcasecmp (new_token.str, "PTR") == 0)
7636 new_token.code = T_PTR;
7638 else if (strcasecmp (new_token.str, "SHORT") == 0)
7639 new_token.code = T_SHORT;
7641 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7643 new_token.code = T_OFFSET;
7645 /* ??? This is not mentioned in the MASM grammar but gcc
7646 makes use of it with -mintel-syntax. OFFSET may be
7647 followed by FLAT: */
7648 if (strncasecmp (q, " FLAT:", 6) == 0)
7649 strcat (new_token.str, " FLAT:");
7652 /* ??? This is not mentioned in the MASM grammar. */
7653 else if (strcasecmp (new_token.str, "FLAT") == 0)
7655 new_token.code = T_OFFSET;
7657 strcat (new_token.str, ":");
7659 as_bad (_("`:' expected"));
7663 new_token.code = T_ID;
7667 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7669 new_token.code = *intel_parser.op_string;
7670 new_token.str[0] = *intel_parser.op_string;
7671 new_token.str[1] = '\0';
7674 else if (strchr ("<>", *intel_parser.op_string)
7675 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7677 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7678 new_token.str[0] = *intel_parser.op_string;
7679 new_token.str[1] = *intel_parser.op_string;
7680 new_token.str[2] = '\0';
7684 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7686 intel_parser.op_string += strlen (new_token.str);
7687 cur_token = new_token;
7690 /* Put cur_token back into the token stream and make cur_token point to
7693 intel_putback_token ()
7695 if (cur_token.code != T_NIL)
7697 intel_parser.op_string -= strlen (cur_token.str);
7698 free (cur_token.str);
7700 cur_token = prev_token;
7702 /* Forget prev_token. */
7703 prev_token.code = T_NIL;
7704 prev_token.reg = NULL;
7705 prev_token.str = NULL;
7709 tc_x86_regname_to_dw2regnum (char *regname)
7711 unsigned int regnum;
7712 unsigned int regnames_count;
7713 static const char *const regnames_32[] =
7715 "eax", "ecx", "edx", "ebx",
7716 "esp", "ebp", "esi", "edi",
7717 "eip", "eflags", NULL,
7718 "st0", "st1", "st2", "st3",
7719 "st4", "st5", "st6", "st7",
7721 "xmm0", "xmm1", "xmm2", "xmm3",
7722 "xmm4", "xmm5", "xmm6", "xmm7",
7723 "mm0", "mm1", "mm2", "mm3",
7724 "mm4", "mm5", "mm6", "mm7",
7725 "fcw", "fsw", "mxcsr",
7726 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7729 static const char *const regnames_64[] =
7731 "rax", "rdx", "rcx", "rbx",
7732 "rsi", "rdi", "rbp", "rsp",
7733 "r8", "r9", "r10", "r11",
7734 "r12", "r13", "r14", "r15",
7736 "xmm0", "xmm1", "xmm2", "xmm3",
7737 "xmm4", "xmm5", "xmm6", "xmm7",
7738 "xmm8", "xmm9", "xmm10", "xmm11",
7739 "xmm12", "xmm13", "xmm14", "xmm15",
7740 "st0", "st1", "st2", "st3",
7741 "st4", "st5", "st6", "st7",
7742 "mm0", "mm1", "mm2", "mm3",
7743 "mm4", "mm5", "mm6", "mm7",
7745 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7746 "fs.base", "gs.base", NULL, NULL,
7748 "mxcsr", "fcw", "fsw"
7750 const char *const *regnames;
7752 if (flag_code == CODE_64BIT)
7754 regnames = regnames_64;
7755 regnames_count = ARRAY_SIZE (regnames_64);
7759 regnames = regnames_32;
7760 regnames_count = ARRAY_SIZE (regnames_32);
7763 for (regnum = 0; regnum < regnames_count; regnum++)
7764 if (regnames[regnum] != NULL
7765 && strcmp (regname, regnames[regnum]) == 0)
7772 tc_x86_frame_initial_instructions (void)
7774 static unsigned int sp_regno;
7777 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7780 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7781 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7785 i386_elf_section_type (const char *str, size_t len)
7787 if (flag_code == CODE_64BIT
7788 && len == sizeof ("unwind") - 1
7789 && strncmp (str, "unwind", 6) == 0)
7790 return SHT_X86_64_UNWIND;
7797 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7801 expr.X_op = O_secrel;
7802 expr.X_add_symbol = symbol;
7803 expr.X_add_number = 0;
7804 emit_expr (&expr, size);
7808 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7809 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7812 x86_64_section_letter (int letter, char **ptr_msg)
7814 if (flag_code == CODE_64BIT)
7817 return SHF_X86_64_LARGE;
7819 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7822 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7827 x86_64_section_word (char *str, size_t len)
7829 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7830 return SHF_X86_64_LARGE;
7836 handle_large_common (int small ATTRIBUTE_UNUSED)
7838 if (flag_code != CODE_64BIT)
7840 s_comm_internal (0, elf_common_parse);
7841 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7845 static segT lbss_section;
7846 asection *saved_com_section_ptr = elf_com_section_ptr;
7847 asection *saved_bss_section = bss_section;
7849 if (lbss_section == NULL)
7851 flagword applicable;
7853 subsegT subseg = now_subseg;
7855 /* The .lbss section is for local .largecomm symbols. */
7856 lbss_section = subseg_new (".lbss", 0);
7857 applicable = bfd_applicable_section_flags (stdoutput);
7858 bfd_set_section_flags (stdoutput, lbss_section,
7859 applicable & SEC_ALLOC);
7860 seg_info (lbss_section)->bss = 1;
7862 subseg_set (seg, subseg);
7865 elf_com_section_ptr = &_bfd_elf_large_com_section;
7866 bss_section = lbss_section;
7868 s_comm_internal (0, elf_common_parse);
7870 elf_com_section_ptr = saved_com_section_ptr;
7871 bss_section = saved_bss_section;
7874 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */