1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c);
69 static int i386_att_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry *parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry *build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS *, offsetT);
91 static void output_disp (fragS *, offsetT);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED);
99 static const char *default_arch = DEFAULT_ARCH;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry *regs;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types[MAX_OPERANDS];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op[MAX_OPERANDS];
136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry *seg[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars = "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars = "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "#/";
210 const char line_separator_chars[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars[256];
223 static char register_chars[256];
224 static char operand_chars[256];
225 static char identifier_chars[256];
226 static char digit_chars[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack[32];
244 static char *save_stack_p;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates *current_templates;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
260 /* Current operand we are working on. */
261 static int this_operand;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code;
272 static unsigned int object_64bit;
273 static int use_rela_relocations = 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names[] =
283 /* 1 for intel syntax,
285 static int intel_syntax = 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic = !SYSV386_COMPAT;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc = OLDGCC_COMPAT;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg = 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix = "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code = 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings = 0;
315 static const char *cpu_arch_name = NULL;
316 static const char *cpu_sub_arch_name = NULL;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragS *fragP, int count)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1[] =
576 static const char f32_2[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
639 static const char alt_3[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code == CODE_16BIT)
769 memcpy (fragP->fr_literal + fragP->fr_fix,
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
780 const char *const *patt = NULL;
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags.bitfield.cpui686)
791 patt = alt_long_patt;
795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
804 case PROCESSOR_ATHLON:
806 case PROCESSOR_AMDFAM10:
807 patt = alt_short_patt;
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
819 switch (cpu_arch_tune)
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM:
831 case PROCESSOR_ATHLON:
833 case PROCESSOR_AMDFAM10:
834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags.bitfield.cpui686)
838 patt = alt_short_patt;
842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE2:
847 if (cpu_arch_isa_flags.bitfield.cpui686)
848 patt = alt_long_patt;
852 case PROCESSOR_GENERIC64:
853 patt = alt_long_patt;
858 if (patt == f32_patt)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
868 memcpy (fragP->fr_literal + fragP->fr_fix,
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
892 fragP->fr_var = count;
896 uints_all_zero (const unsigned int *x, unsigned int size)
914 uints_set (unsigned int *x, unsigned int v, unsigned int size)
931 uints_equal (const unsigned int *x, const unsigned int *y,
943 return x[0] == y [0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f)
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
969 switch (ARRAY_SIZE (x.array))
972 x.array [2] &= y.array [2];
974 x.array [1] &= y.array [1];
976 x.array [0] &= y.array [0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
987 switch (ARRAY_SIZE (x.array))
990 x.array [2] |= y.array [2];
992 x.array [1] |= y.array [1];
994 x.array [0] |= y.array [0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x)
1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1013 if (UINTS_ALL_ZERO (x))
1017 i386_cpu_flags cpu = cpu_arch_flags;
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x, i386_operand_type y)
1030 switch (ARRAY_SIZE (x.array))
1033 x.array [2] &= y.array [2];
1035 x.array [1] &= y.array [1];
1037 x.array [0] &= y.array [0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x, i386_operand_type y)
1048 switch (ARRAY_SIZE (x.array))
1051 x.array [2] |= y.array [2];
1053 x.array [1] |= y.array [1];
1055 x.array [0] |= y.array [0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x, i386_operand_type y)
1066 switch (ARRAY_SIZE (x.array))
1069 x.array [2] ^= y.array [2];
1071 x.array [1] ^= y.array [1];
1073 x.array [0] ^= y.array [0];
1081 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
1092 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1112 operand_type_check (i386_operand_type t, enum operand_type c)
1117 return (t.bitfield.reg8
1120 || t.bitfield.reg64);
1123 return (t.bitfield.imm8
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1151 operand_type_match (i386_operand_type overlap,
1152 i386_operand_type given)
1154 i386_operand_type temp = overlap;
1156 temp.bitfield.jumpabsolute = 0;
1157 if (UINTS_ALL_ZERO (temp))
1160 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1161 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1164 /* If given types r0 and r1 are registers they must be of the same type
1165 unless the expected operand type register overlap is null.
1166 Note that Acc in a template matches every size of reg. */
1169 operand_type_register_match (i386_operand_type m0,
1170 i386_operand_type g0,
1171 i386_operand_type t0,
1172 i386_operand_type m1,
1173 i386_operand_type g1,
1174 i386_operand_type t1)
1176 if (!operand_type_check (g0, reg))
1179 if (!operand_type_check (g1, reg))
1182 if (g0.bitfield.reg8 == g1.bitfield.reg8
1183 && g0.bitfield.reg16 == g1.bitfield.reg16
1184 && g0.bitfield.reg32 == g1.bitfield.reg32
1185 && g0.bitfield.reg64 == g1.bitfield.reg64)
1188 if (m0.bitfield.acc)
1190 t0.bitfield.reg8 = 1;
1191 t0.bitfield.reg16 = 1;
1192 t0.bitfield.reg32 = 1;
1193 t0.bitfield.reg64 = 1;
1196 if (m1.bitfield.acc)
1198 t1.bitfield.reg8 = 1;
1199 t1.bitfield.reg16 = 1;
1200 t1.bitfield.reg32 = 1;
1201 t1.bitfield.reg64 = 1;
1204 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1205 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1206 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1207 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1210 static INLINE unsigned int
1211 mode_from_disp_size (i386_operand_type t)
1213 if (t.bitfield.disp8)
1215 else if (t.bitfield.disp16
1216 || t.bitfield.disp32
1217 || t.bitfield.disp32s)
1224 fits_in_signed_byte (offsetT num)
1226 return (num >= -128) && (num <= 127);
1230 fits_in_unsigned_byte (offsetT num)
1232 return (num & 0xff) == num;
1236 fits_in_unsigned_word (offsetT num)
1238 return (num & 0xffff) == num;
1242 fits_in_signed_word (offsetT num)
1244 return (-32768 <= num) && (num <= 32767);
1248 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1253 return (!(((offsetT) -1 << 31) & num)
1254 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1256 } /* fits_in_signed_long() */
1259 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1264 return (num & (((offsetT) 2 << 31) - 1)) == num;
1266 } /* fits_in_unsigned_long() */
1268 static i386_operand_type
1269 smallest_imm_type (offsetT num)
1271 i386_operand_type t;
1274 t.bitfield.imm64 = 1;
1276 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1278 /* This code is disabled on the 486 because all the Imm1 forms
1279 in the opcode table are slower on the i486. They're the
1280 versions with the implicitly specified single-position
1281 displacement, which has another syntax if you really want to
1283 t.bitfield.imm1 = 1;
1284 t.bitfield.imm8 = 1;
1285 t.bitfield.imm8s = 1;
1286 t.bitfield.imm16 = 1;
1287 t.bitfield.imm32 = 1;
1288 t.bitfield.imm32s = 1;
1290 else if (fits_in_signed_byte (num))
1292 t.bitfield.imm8 = 1;
1293 t.bitfield.imm8s = 1;
1294 t.bitfield.imm16 = 1;
1295 t.bitfield.imm32 = 1;
1296 t.bitfield.imm32s = 1;
1298 else if (fits_in_unsigned_byte (num))
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1305 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1311 else if (fits_in_signed_long (num))
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1316 else if (fits_in_unsigned_long (num))
1317 t.bitfield.imm32 = 1;
1323 offset_in_range (offsetT val, int size)
1329 case 1: mask = ((addressT) 1 << 8) - 1; break;
1330 case 2: mask = ((addressT) 1 << 16) - 1; break;
1331 case 4: mask = ((addressT) 2 << 31) - 1; break;
1333 case 8: mask = ((addressT) 2 << 63) - 1; break;
1338 /* If BFD64, sign extend val. */
1339 if (!use_rela_relocations)
1340 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1341 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1343 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1345 char buf1[40], buf2[40];
1347 sprint_value (buf1, val);
1348 sprint_value (buf2, val & mask);
1349 as_warn (_("%s shortened to %s"), buf1, buf2);
1354 /* Returns 0 if attempting to add a prefix where one from the same
1355 class already exists, 1 if non rep/repne added, 2 if rep/repne
1358 add_prefix (unsigned int prefix)
1363 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1364 && flag_code == CODE_64BIT)
1366 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1367 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1368 && (prefix & (REX_R | REX_X | REX_B))))
1379 case CS_PREFIX_OPCODE:
1380 case DS_PREFIX_OPCODE:
1381 case ES_PREFIX_OPCODE:
1382 case FS_PREFIX_OPCODE:
1383 case GS_PREFIX_OPCODE:
1384 case SS_PREFIX_OPCODE:
1388 case REPNE_PREFIX_OPCODE:
1389 case REPE_PREFIX_OPCODE:
1392 case LOCK_PREFIX_OPCODE:
1400 case ADDR_PREFIX_OPCODE:
1404 case DATA_PREFIX_OPCODE:
1408 if (i.prefix[q] != 0)
1416 i.prefix[q] |= prefix;
1419 as_bad (_("same type of prefix used twice"));
1425 set_code_flag (int value)
1428 if (flag_code == CODE_64BIT)
1430 cpu_arch_flags.bitfield.cpu64 = 1;
1431 cpu_arch_flags.bitfield.cpuno64 = 0;
1435 cpu_arch_flags.bitfield.cpu64 = 0;
1436 cpu_arch_flags.bitfield.cpuno64 = 1;
1438 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1440 as_bad (_("64bit mode not supported on this CPU."));
1442 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1444 as_bad (_("32bit mode not supported on this CPU."));
1446 stackop_size = '\0';
1450 set_16bit_gcc_code_flag (int new_code_flag)
1452 flag_code = new_code_flag;
1453 if (flag_code != CODE_16BIT)
1455 cpu_arch_flags.bitfield.cpu64 = 0;
1456 cpu_arch_flags.bitfield.cpuno64 = 1;
1457 stackop_size = LONG_MNEM_SUFFIX;
1461 set_intel_syntax (int syntax_flag)
1463 /* Find out if register prefixing is specified. */
1464 int ask_naked_reg = 0;
1467 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1469 char *string = input_line_pointer;
1470 int e = get_symbol_end ();
1472 if (strcmp (string, "prefix") == 0)
1474 else if (strcmp (string, "noprefix") == 0)
1477 as_bad (_("bad argument to syntax directive."));
1478 *input_line_pointer = e;
1480 demand_empty_rest_of_line ();
1482 intel_syntax = syntax_flag;
1484 if (ask_naked_reg == 0)
1485 allow_naked_reg = (intel_syntax
1486 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1488 allow_naked_reg = (ask_naked_reg < 0);
1490 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1491 identifier_chars['$'] = intel_syntax ? '$' : 0;
1492 register_prefix = allow_naked_reg ? "" : "%";
1496 set_intel_mnemonic (int mnemonic_flag)
1498 intel_mnemonic = mnemonic_flag;
1502 set_allow_index_reg (int flag)
1504 allow_index_reg = flag;
1508 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1512 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1514 char *string = input_line_pointer;
1515 int e = get_symbol_end ();
1517 i386_cpu_flags flags;
1519 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1521 if (strcmp (string, cpu_arch[i].name) == 0)
1525 cpu_arch_name = cpu_arch[i].name;
1526 cpu_sub_arch_name = NULL;
1527 cpu_arch_flags = cpu_arch[i].flags;
1528 if (flag_code == CODE_64BIT)
1530 cpu_arch_flags.bitfield.cpu64 = 1;
1531 cpu_arch_flags.bitfield.cpuno64 = 0;
1535 cpu_arch_flags.bitfield.cpu64 = 0;
1536 cpu_arch_flags.bitfield.cpuno64 = 1;
1538 cpu_arch_isa = cpu_arch[i].type;
1539 cpu_arch_isa_flags = cpu_arch[i].flags;
1540 if (!cpu_arch_tune_set)
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1548 flags = cpu_flags_or (cpu_arch_flags,
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1552 cpu_sub_arch_name = cpu_arch[i].name;
1553 cpu_arch_flags = flags;
1555 *input_line_pointer = e;
1556 demand_empty_rest_of_line ();
1560 if (i >= ARRAY_SIZE (cpu_arch))
1561 as_bad (_("no such architecture: `%s'"), string);
1563 *input_line_pointer = e;
1566 as_bad (_("missing cpu architecture"));
1568 no_cond_jump_promotion = 0;
1569 if (*input_line_pointer == ','
1570 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1572 char *string = ++input_line_pointer;
1573 int e = get_symbol_end ();
1575 if (strcmp (string, "nojumps") == 0)
1576 no_cond_jump_promotion = 1;
1577 else if (strcmp (string, "jumps") == 0)
1580 as_bad (_("no such architecture modifier: `%s'"), string);
1582 *input_line_pointer = e;
1585 demand_empty_rest_of_line ();
1591 if (!strcmp (default_arch, "x86_64"))
1592 return bfd_mach_x86_64;
1593 else if (!strcmp (default_arch, "i386"))
1594 return bfd_mach_i386_i386;
1596 as_fatal (_("Unknown architecture"));
1602 const char *hash_err;
1604 /* Initialize op_hash hash table. */
1605 op_hash = hash_new ();
1608 const template *optab;
1609 templates *core_optab;
1611 /* Setup for loop. */
1613 core_optab = (templates *) xmalloc (sizeof (templates));
1614 core_optab->start = optab;
1619 if (optab->name == NULL
1620 || strcmp (optab->name, (optab - 1)->name) != 0)
1622 /* different name --> ship out current template list;
1623 add to hash table; & begin anew. */
1624 core_optab->end = optab;
1625 hash_err = hash_insert (op_hash,
1630 as_fatal (_("Internal Error: Can't hash %s: %s"),
1634 if (optab->name == NULL)
1636 core_optab = (templates *) xmalloc (sizeof (templates));
1637 core_optab->start = optab;
1642 /* Initialize reg_hash hash table. */
1643 reg_hash = hash_new ();
1645 const reg_entry *regtab;
1646 unsigned int regtab_size = i386_regtab_size;
1648 for (regtab = i386_regtab; regtab_size--; regtab++)
1650 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1652 as_fatal (_("Internal Error: Can't hash %s: %s"),
1658 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1663 for (c = 0; c < 256; c++)
1668 mnemonic_chars[c] = c;
1669 register_chars[c] = c;
1670 operand_chars[c] = c;
1672 else if (ISLOWER (c))
1674 mnemonic_chars[c] = c;
1675 register_chars[c] = c;
1676 operand_chars[c] = c;
1678 else if (ISUPPER (c))
1680 mnemonic_chars[c] = TOLOWER (c);
1681 register_chars[c] = mnemonic_chars[c];
1682 operand_chars[c] = c;
1685 if (ISALPHA (c) || ISDIGIT (c))
1686 identifier_chars[c] = c;
1689 identifier_chars[c] = c;
1690 operand_chars[c] = c;
1695 identifier_chars['@'] = '@';
1698 identifier_chars['?'] = '?';
1699 operand_chars['?'] = '?';
1701 digit_chars['-'] = '-';
1702 mnemonic_chars['-'] = '-';
1703 mnemonic_chars['.'] = '.';
1704 identifier_chars['_'] = '_';
1705 identifier_chars['.'] = '.';
1707 for (p = operand_special_chars; *p != '\0'; p++)
1708 operand_chars[(unsigned char) *p] = *p;
1711 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1714 record_alignment (text_section, 2);
1715 record_alignment (data_section, 2);
1716 record_alignment (bss_section, 2);
1720 if (flag_code == CODE_64BIT)
1722 x86_dwarf2_return_column = 16;
1723 x86_cie_data_alignment = -8;
1727 x86_dwarf2_return_column = 8;
1728 x86_cie_data_alignment = -4;
1733 i386_print_statistics (FILE *file)
1735 hash_print_statistics (file, "i386 opcode", op_hash);
1736 hash_print_statistics (file, "i386 register", reg_hash);
1741 /* Debugging routines for md_assemble. */
1742 static void pte (template *);
1743 static void pt (i386_operand_type);
1744 static void pe (expressionS *);
1745 static void ps (symbolS *);
1748 pi (char *line, i386_insn *x)
1752 fprintf (stdout, "%s: template ", line);
1754 fprintf (stdout, " address: base %s index %s scale %x\n",
1755 x->base_reg ? x->base_reg->reg_name : "none",
1756 x->index_reg ? x->index_reg->reg_name : "none",
1757 x->log2_scale_factor);
1758 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1759 x->rm.mode, x->rm.reg, x->rm.regmem);
1760 fprintf (stdout, " sib: base %x index %x scale %x\n",
1761 x->sib.base, x->sib.index, x->sib.scale);
1762 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1763 (x->rex & REX_W) != 0,
1764 (x->rex & REX_R) != 0,
1765 (x->rex & REX_X) != 0,
1766 (x->rex & REX_B) != 0);
1767 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1768 x->drex.reg, x->drex.rex);
1769 for (i = 0; i < x->operands; i++)
1771 fprintf (stdout, " #%d: ", i + 1);
1773 fprintf (stdout, "\n");
1774 if (x->types[i].bitfield.reg8
1775 || x->types[i].bitfield.reg16
1776 || x->types[i].bitfield.reg32
1777 || x->types[i].bitfield.reg64
1778 || x->types[i].bitfield.regmmx
1779 || x->types[i].bitfield.regxmm
1780 || x->types[i].bitfield.sreg2
1781 || x->types[i].bitfield.sreg3
1782 || x->types[i].bitfield.control
1783 || x->types[i].bitfield.debug
1784 || x->types[i].bitfield.test)
1785 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1786 if (operand_type_check (x->types[i], imm))
1788 if (operand_type_check (x->types[i], disp))
1789 pe (x->op[i].disps);
1797 fprintf (stdout, " %d operands ", t->operands);
1798 fprintf (stdout, "opcode %x ", t->base_opcode);
1799 if (t->extension_opcode != None)
1800 fprintf (stdout, "ext %x ", t->extension_opcode);
1801 if (t->opcode_modifier.d)
1802 fprintf (stdout, "D");
1803 if (t->opcode_modifier.w)
1804 fprintf (stdout, "W");
1805 fprintf (stdout, "\n");
1806 for (i = 0; i < t->operands; i++)
1808 fprintf (stdout, " #%d type ", i + 1);
1809 pt (t->operand_types[i]);
1810 fprintf (stdout, "\n");
1817 fprintf (stdout, " operation %d\n", e->X_op);
1818 fprintf (stdout, " add_number %ld (%lx)\n",
1819 (long) e->X_add_number, (long) e->X_add_number);
1820 if (e->X_add_symbol)
1822 fprintf (stdout, " add_symbol ");
1823 ps (e->X_add_symbol);
1824 fprintf (stdout, "\n");
1828 fprintf (stdout, " op_symbol ");
1829 ps (e->X_op_symbol);
1830 fprintf (stdout, "\n");
1837 fprintf (stdout, "%s type %s%s",
1839 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1840 segment_name (S_GET_SEGMENT (s)));
1843 static struct type_name
1845 i386_operand_type mask;
1848 const type_names[] =
1850 { OPERAND_TYPE_REG8, "r8" },
1851 { OPERAND_TYPE_REG16, "r16" },
1852 { OPERAND_TYPE_REG32, "r32" },
1853 { OPERAND_TYPE_REG64, "r64" },
1854 { OPERAND_TYPE_IMM8, "i8" },
1855 { OPERAND_TYPE_IMM8, "i8s" },
1856 { OPERAND_TYPE_IMM16, "i16" },
1857 { OPERAND_TYPE_IMM32, "i32" },
1858 { OPERAND_TYPE_IMM32S, "i32s" },
1859 { OPERAND_TYPE_IMM64, "i64" },
1860 { OPERAND_TYPE_IMM1, "i1" },
1861 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1862 { OPERAND_TYPE_DISP8, "d8" },
1863 { OPERAND_TYPE_DISP16, "d16" },
1864 { OPERAND_TYPE_DISP32, "d32" },
1865 { OPERAND_TYPE_DISP32S, "d32s" },
1866 { OPERAND_TYPE_DISP64, "d64" },
1867 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1868 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1869 { OPERAND_TYPE_CONTROL, "control reg" },
1870 { OPERAND_TYPE_TEST, "test reg" },
1871 { OPERAND_TYPE_DEBUG, "debug reg" },
1872 { OPERAND_TYPE_FLOATREG, "FReg" },
1873 { OPERAND_TYPE_FLOATACC, "FAcc" },
1874 { OPERAND_TYPE_SREG2, "SReg2" },
1875 { OPERAND_TYPE_SREG3, "SReg3" },
1876 { OPERAND_TYPE_ACC, "Acc" },
1877 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1878 { OPERAND_TYPE_REGMMX, "rMMX" },
1879 { OPERAND_TYPE_REGXMM, "rXMM" },
1880 { OPERAND_TYPE_ESSEG, "es" },
1884 pt (i386_operand_type t)
1887 i386_operand_type a;
1889 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1891 a = operand_type_and (t, type_names[j].mask);
1892 if (!UINTS_ALL_ZERO (a))
1893 fprintf (stdout, "%s, ", type_names[j].name);
1898 #endif /* DEBUG386 */
1900 static bfd_reloc_code_real_type
1901 reloc (unsigned int size,
1904 bfd_reloc_code_real_type other)
1906 if (other != NO_RELOC)
1908 reloc_howto_type *reloc;
1913 case BFD_RELOC_X86_64_GOT32:
1914 return BFD_RELOC_X86_64_GOT64;
1916 case BFD_RELOC_X86_64_PLTOFF64:
1917 return BFD_RELOC_X86_64_PLTOFF64;
1919 case BFD_RELOC_X86_64_GOTPC32:
1920 other = BFD_RELOC_X86_64_GOTPC64;
1922 case BFD_RELOC_X86_64_GOTPCREL:
1923 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 case BFD_RELOC_X86_64_TPOFF32:
1926 other = BFD_RELOC_X86_64_TPOFF64;
1928 case BFD_RELOC_X86_64_DTPOFF32:
1929 other = BFD_RELOC_X86_64_DTPOFF64;
1935 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1936 if (size == 4 && flag_code != CODE_64BIT)
1939 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 as_bad (_("unknown relocation (%u)"), other);
1942 else if (size != bfd_get_reloc_size (reloc))
1943 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1944 bfd_get_reloc_size (reloc),
1946 else if (pcrel && !reloc->pc_relative)
1947 as_bad (_("non-pc-relative relocation for pc-relative field"));
1948 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 || (reloc->complain_on_overflow == complain_overflow_unsigned
1952 as_bad (_("relocated field and relocation type differ in signedness"));
1961 as_bad (_("there are no unsigned pc-relative relocations"));
1964 case 1: return BFD_RELOC_8_PCREL;
1965 case 2: return BFD_RELOC_16_PCREL;
1966 case 4: return BFD_RELOC_32_PCREL;
1967 case 8: return BFD_RELOC_64_PCREL;
1969 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1976 case 4: return BFD_RELOC_X86_64_32S;
1981 case 1: return BFD_RELOC_8;
1982 case 2: return BFD_RELOC_16;
1983 case 4: return BFD_RELOC_32;
1984 case 8: return BFD_RELOC_64;
1986 as_bad (_("cannot do %s %u byte relocation"),
1987 sign > 0 ? "signed" : "unsigned", size);
1991 return BFD_RELOC_NONE;
1994 /* Here we decide which fixups can be adjusted to make them relative to
1995 the beginning of the section instead of the symbol. Basically we need
1996 to make sure that the dynamic relocations are done correctly, so in
1997 some cases we force the original symbol to be used. */
2000 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2006 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 if (use_rela_relocations
2009 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2013 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2014 and changed later by validate_fix. */
2015 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2016 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2019 /* adjust_reloc_syms doesn't know about the GOT. */
2020 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2021 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2022 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2023 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2033 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2040 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2046 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2054 intel_float_operand (const char *mnemonic)
2056 /* Note that the value returned is meaningful only for opcodes with (memory)
2057 operands, hence the code here is free to improperly handle opcodes that
2058 have no operands (for better performance and smaller code). */
2060 if (mnemonic[0] != 'f')
2061 return 0; /* non-math */
2063 switch (mnemonic[1])
2065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2066 the fs segment override prefix not currently handled because no
2067 call path can make opcodes without operands get here */
2069 return 2 /* integer op */;
2071 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2072 return 3; /* fldcw/fldenv */
2075 if (mnemonic[2] != 'o' /* fnop */)
2076 return 3; /* non-waiting control op */
2079 if (mnemonic[2] == 's')
2080 return 3; /* frstor/frstpm */
2083 if (mnemonic[2] == 'a')
2084 return 3; /* fsave */
2085 if (mnemonic[2] == 't')
2087 switch (mnemonic[3])
2089 case 'c': /* fstcw */
2090 case 'd': /* fstdw */
2091 case 'e': /* fstenv */
2092 case 's': /* fsts[gw] */
2098 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2099 return 0; /* fxsave/fxrstor are not really math ops */
2106 /* This is the guts of the machine-dependent assembler. LINE points to a
2107 machine dependent instruction. This function is supposed to emit
2108 the frags/bytes it assembles to. */
2115 char mnemonic[MAX_MNEM_SIZE];
2117 /* Initialize globals. */
2118 memset (&i, '\0', sizeof (i));
2119 for (j = 0; j < MAX_OPERANDS; j++)
2120 i.reloc[j] = NO_RELOC;
2121 memset (disp_expressions, '\0', sizeof (disp_expressions));
2122 memset (im_expressions, '\0', sizeof (im_expressions));
2123 save_stack_p = save_stack;
2125 /* First parse an instruction mnemonic & call i386_operand for the operands.
2126 We assume that the scrubber has arranged it so that line[0] is the valid
2127 start of a (possibly prefixed) mnemonic. */
2129 line = parse_insn (line, mnemonic);
2133 line = parse_operands (line, mnemonic);
2137 /* Now we've parsed the mnemonic into a set of templates, and have the
2138 operands at hand. */
2140 /* All intel opcodes have reversed operands except for "bound" and
2141 "enter". We also don't reverse intersegment "jmp" and "call"
2142 instructions with 2 immediate operands so that the immediate segment
2143 precedes the offset, as it does when in AT&T mode. */
2146 && (strcmp (mnemonic, "bound") != 0)
2147 && (strcmp (mnemonic, "invlpga") != 0)
2148 && !(operand_type_check (i.types[0], imm)
2149 && operand_type_check (i.types[1], imm)))
2152 /* The order of the immediates should be reversed
2153 for 2 immediates extrq and insertq instructions */
2154 if (i.imm_operands == 2
2155 && (strcmp (mnemonic, "extrq") == 0
2156 || strcmp (mnemonic, "insertq") == 0))
2157 swap_2_operands (0, 1);
2162 /* Don't optimize displacement for movabs since it only takes 64bit
2165 && (flag_code != CODE_64BIT
2166 || strcmp (mnemonic, "movabs") != 0))
2169 /* Next, we find a template that matches the given insn,
2170 making sure the overlap of the given operands types is consistent
2171 with the template operand types. */
2173 if (!match_template ())
2178 /* Zap movzx and movsx suffix. The suffix may have been set from
2179 "word ptr" or "byte ptr" on the source operand, but we'll use
2180 the suffix later to choose the destination register. */
2181 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2183 if (i.reg_operands < 2
2185 && (!i.tm.opcode_modifier.no_bsuf
2186 || !i.tm.opcode_modifier.no_wsuf
2187 || !i.tm.opcode_modifier.no_lsuf
2188 || !i.tm.opcode_modifier.no_ssuf
2189 || !i.tm.opcode_modifier.no_ldsuf
2190 || !i.tm.opcode_modifier.no_qsuf))
2191 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2197 if (i.tm.opcode_modifier.fwait)
2198 if (!add_prefix (FWAIT_OPCODE))
2201 /* Check string instruction segment overrides. */
2202 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2204 if (!check_string ())
2208 if (!process_suffix ())
2211 /* Make still unresolved immediate matches conform to size of immediate
2212 given in i.suffix. */
2213 if (!finalize_imm ())
2216 if (i.types[0].bitfield.imm1)
2217 i.imm_operands = 0; /* kludge for shift insns. */
2219 for (j = 0; j < 3; j++)
2220 if (i.types[j].bitfield.inoutportreg
2221 || i.types[j].bitfield.shiftcount
2222 || i.types[j].bitfield.acc
2223 || i.types[j].bitfield.floatacc)
2226 if (i.tm.opcode_modifier.immext)
2230 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2232 /* Streaming SIMD extensions 3 Instructions have the fixed
2233 operands with an opcode suffix which is coded in the same
2234 place as an 8-bit immediate field would be. Here we check
2235 those operands and remove them afterwards. */
2238 for (x = 0; x < i.operands; x++)
2239 if (i.op[x].regs->reg_num != x)
2240 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2242 i.op[x].regs->reg_name,
2248 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2249 opcode suffix which is coded in the same place as an 8-bit
2250 immediate field would be. Here we fake an 8-bit immediate
2251 operand from the opcode suffix stored in tm.extension_opcode.
2252 SSE5 also uses this encoding, for some of its 3 argument
2255 assert (i.imm_operands == 0
2257 || (i.tm.cpu_flags.bitfield.cpusse5
2258 && i.operands <= 3)));
2260 exp = &im_expressions[i.imm_operands++];
2261 i.op[i.operands].imms = exp;
2262 UINTS_CLEAR (i.types[i.operands]);
2263 i.types[i.operands].bitfield.imm8 = 1;
2265 exp->X_op = O_constant;
2266 exp->X_add_number = i.tm.extension_opcode;
2267 i.tm.extension_opcode = None;
2270 /* For insns with operands there are more diddles to do to the opcode. */
2273 if (!process_operands ())
2276 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2278 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2279 as_warn (_("translating to `%sp'"), i.tm.name);
2282 /* Handle conversion of 'int $3' --> special int3 insn. */
2283 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2285 i.tm.base_opcode = INT3_OPCODE;
2289 if ((i.tm.opcode_modifier.jump
2290 || i.tm.opcode_modifier.jumpbyte
2291 || i.tm.opcode_modifier.jumpdword)
2292 && i.op[0].disps->X_op == O_constant)
2294 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2295 the absolute address given by the constant. Since ix86 jumps and
2296 calls are pc relative, we need to generate a reloc. */
2297 i.op[0].disps->X_add_symbol = &abs_symbol;
2298 i.op[0].disps->X_op = O_symbol;
2301 if (i.tm.opcode_modifier.rex64)
2304 /* For 8 bit registers we need an empty rex prefix. Also if the
2305 instruction already has a prefix, we need to convert old
2306 registers to new ones. */
2308 if ((i.types[0].bitfield.reg8
2309 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2310 || (i.types[1].bitfield.reg8
2311 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2312 || ((i.types[0].bitfield.reg8
2313 || i.types[1].bitfield.reg8)
2318 i.rex |= REX_OPCODE;
2319 for (x = 0; x < 2; x++)
2321 /* Look for 8 bit operand that uses old registers. */
2322 if (i.types[x].bitfield.reg8
2323 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2325 /* In case it is "hi" register, give up. */
2326 if (i.op[x].regs->reg_num > 3)
2327 as_bad (_("can't encode register '%s%s' in an "
2328 "instruction requiring REX prefix."),
2329 register_prefix, i.op[x].regs->reg_name);
2331 /* Otherwise it is equivalent to the extended register.
2332 Since the encoding doesn't change this is merely
2333 cosmetic cleanup for debug output. */
2335 i.op[x].regs = i.op[x].regs + 8;
2340 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2342 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2347 else if (i.rex != 0)
2348 add_prefix (REX_OPCODE | i.rex);
2350 /* We are ready to output the insn. */
2355 parse_insn (char *line, char *mnemonic)
2358 char *token_start = l;
2363 /* Non-zero if we found a prefix only acceptable with string insns. */
2364 const char *expecting_string_instruction = NULL;
2369 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2372 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2374 as_bad (_("no such instruction: `%s'"), token_start);
2379 if (!is_space_char (*l)
2380 && *l != END_OF_INSN
2382 || (*l != PREFIX_SEPARATOR
2385 as_bad (_("invalid character %s in mnemonic"),
2386 output_invalid (*l));
2389 if (token_start == l)
2391 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2392 as_bad (_("expecting prefix; got nothing"));
2394 as_bad (_("expecting mnemonic; got nothing"));
2398 /* Look up instruction (or prefix) via hash table. */
2399 current_templates = hash_find (op_hash, mnemonic);
2401 if (*l != END_OF_INSN
2402 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2403 && current_templates
2404 && current_templates->start->opcode_modifier.isprefix)
2406 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2408 as_bad ((flag_code != CODE_64BIT
2409 ? _("`%s' is only supported in 64-bit mode")
2410 : _("`%s' is not supported in 64-bit mode")),
2411 current_templates->start->name);
2414 /* If we are in 16-bit mode, do not allow addr16 or data16.
2415 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2416 if ((current_templates->start->opcode_modifier.size16
2417 || current_templates->start->opcode_modifier.size32)
2418 && flag_code != CODE_64BIT
2419 && (current_templates->start->opcode_modifier.size32
2420 ^ (flag_code == CODE_16BIT)))
2422 as_bad (_("redundant %s prefix"),
2423 current_templates->start->name);
2426 /* Add prefix, checking for repeated prefixes. */
2427 switch (add_prefix (current_templates->start->base_opcode))
2432 expecting_string_instruction = current_templates->start->name;
2435 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2442 if (!current_templates)
2444 /* See if we can get a match by trimming off a suffix. */
2447 case WORD_MNEM_SUFFIX:
2448 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2449 i.suffix = SHORT_MNEM_SUFFIX;
2451 case BYTE_MNEM_SUFFIX:
2452 case QWORD_MNEM_SUFFIX:
2453 i.suffix = mnem_p[-1];
2455 current_templates = hash_find (op_hash, mnemonic);
2457 case SHORT_MNEM_SUFFIX:
2458 case LONG_MNEM_SUFFIX:
2461 i.suffix = mnem_p[-1];
2463 current_templates = hash_find (op_hash, mnemonic);
2471 if (intel_float_operand (mnemonic) == 1)
2472 i.suffix = SHORT_MNEM_SUFFIX;
2474 i.suffix = LONG_MNEM_SUFFIX;
2476 current_templates = hash_find (op_hash, mnemonic);
2480 if (!current_templates)
2482 as_bad (_("no such instruction: `%s'"), token_start);
2487 if (current_templates->start->opcode_modifier.jump
2488 || current_templates->start->opcode_modifier.jumpbyte)
2490 /* Check for a branch hint. We allow ",pt" and ",pn" for
2491 predict taken and predict not taken respectively.
2492 I'm not sure that branch hints actually do anything on loop
2493 and jcxz insns (JumpByte) for current Pentium4 chips. They
2494 may work in the future and it doesn't hurt to accept them
2496 if (l[0] == ',' && l[1] == 'p')
2500 if (!add_prefix (DS_PREFIX_OPCODE))
2504 else if (l[2] == 'n')
2506 if (!add_prefix (CS_PREFIX_OPCODE))
2512 /* Any other comma loses. */
2515 as_bad (_("invalid character %s in mnemonic"),
2516 output_invalid (*l));
2520 /* Check if instruction is supported on specified architecture. */
2522 for (t = current_templates->start; t < current_templates->end; ++t)
2524 supported |= cpu_flags_match (t->cpu_flags);
2529 if (!(supported & 2))
2531 as_bad (flag_code == CODE_64BIT
2532 ? _("`%s' is not supported in 64-bit mode")
2533 : _("`%s' is only supported in 64-bit mode"),
2534 current_templates->start->name);
2537 if (!(supported & 1))
2539 as_bad (_("`%s' is not supported on `%s%s'"),
2540 current_templates->start->name, cpu_arch_name,
2541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2546 if (!cpu_arch_flags.bitfield.cpui386
2547 && (flag_code != CODE_16BIT))
2549 as_warn (_("use .code16 to ensure correct addressing mode"));
2552 /* Check for rep/repne without a string instruction. */
2553 if (expecting_string_instruction)
2555 static templates override;
2557 for (t = current_templates->start; t < current_templates->end; ++t)
2558 if (t->opcode_modifier.isstring)
2560 if (t >= current_templates->end)
2562 as_bad (_("expecting string instruction after `%s'"),
2563 expecting_string_instruction);
2566 for (override.start = t; t < current_templates->end; ++t)
2567 if (!t->opcode_modifier.isstring)
2570 current_templates = &override;
2577 parse_operands (char *l, const char *mnemonic)
2581 /* 1 if operand is pending after ','. */
2582 unsigned int expecting_operand = 0;
2584 /* Non-zero if operand parens not balanced. */
2585 unsigned int paren_not_balanced;
2587 while (*l != END_OF_INSN)
2589 /* Skip optional white space before operand. */
2590 if (is_space_char (*l))
2592 if (!is_operand_char (*l) && *l != END_OF_INSN)
2594 as_bad (_("invalid character %s before operand %d"),
2595 output_invalid (*l),
2599 token_start = l; /* after white space */
2600 paren_not_balanced = 0;
2601 while (paren_not_balanced || *l != ',')
2603 if (*l == END_OF_INSN)
2605 if (paren_not_balanced)
2608 as_bad (_("unbalanced parenthesis in operand %d."),
2611 as_bad (_("unbalanced brackets in operand %d."),
2616 break; /* we are done */
2618 else if (!is_operand_char (*l) && !is_space_char (*l))
2620 as_bad (_("invalid character %s in operand %d"),
2621 output_invalid (*l),
2628 ++paren_not_balanced;
2630 --paren_not_balanced;
2635 ++paren_not_balanced;
2637 --paren_not_balanced;
2641 if (l != token_start)
2642 { /* Yes, we've read in another operand. */
2643 unsigned int operand_ok;
2644 this_operand = i.operands++;
2645 if (i.operands > MAX_OPERANDS)
2647 as_bad (_("spurious operands; (%d operands/instruction max)"),
2651 /* Now parse operand adding info to 'i' as we go along. */
2652 END_STRING_AND_SAVE (l);
2656 i386_intel_operand (token_start,
2657 intel_float_operand (mnemonic));
2659 operand_ok = i386_att_operand (token_start);
2661 RESTORE_END_STRING (l);
2667 if (expecting_operand)
2669 expecting_operand_after_comma:
2670 as_bad (_("expecting operand after ','; got nothing"));
2675 as_bad (_("expecting operand before ','; got nothing"));
2680 /* Now *l must be either ',' or END_OF_INSN. */
2683 if (*++l == END_OF_INSN)
2685 /* Just skip it, if it's \n complain. */
2686 goto expecting_operand_after_comma;
2688 expecting_operand = 1;
2695 swap_2_operands (int xchg1, int xchg2)
2697 union i386_op temp_op;
2698 i386_operand_type temp_type;
2699 enum bfd_reloc_code_real temp_reloc;
2701 temp_type = i.types[xchg2];
2702 i.types[xchg2] = i.types[xchg1];
2703 i.types[xchg1] = temp_type;
2704 temp_op = i.op[xchg2];
2705 i.op[xchg2] = i.op[xchg1];
2706 i.op[xchg1] = temp_op;
2707 temp_reloc = i.reloc[xchg2];
2708 i.reloc[xchg2] = i.reloc[xchg1];
2709 i.reloc[xchg1] = temp_reloc;
2713 swap_operands (void)
2718 swap_2_operands (1, i.operands - 2);
2721 swap_2_operands (0, i.operands - 1);
2727 if (i.mem_operands == 2)
2729 const seg_entry *temp_seg;
2730 temp_seg = i.seg[0];
2731 i.seg[0] = i.seg[1];
2732 i.seg[1] = temp_seg;
2736 /* Try to ensure constant immediates are represented in the smallest
2741 char guess_suffix = 0;
2745 guess_suffix = i.suffix;
2746 else if (i.reg_operands)
2748 /* Figure out a suffix from the last register operand specified.
2749 We can't do this properly yet, ie. excluding InOutPortReg,
2750 but the following works for instructions with immediates.
2751 In any case, we can't set i.suffix yet. */
2752 for (op = i.operands; --op >= 0;)
2753 if (i.types[op].bitfield.reg8)
2755 guess_suffix = BYTE_MNEM_SUFFIX;
2758 else if (i.types[op].bitfield.reg16)
2760 guess_suffix = WORD_MNEM_SUFFIX;
2763 else if (i.types[op].bitfield.reg32)
2765 guess_suffix = LONG_MNEM_SUFFIX;
2768 else if (i.types[op].bitfield.reg64)
2770 guess_suffix = QWORD_MNEM_SUFFIX;
2774 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2775 guess_suffix = WORD_MNEM_SUFFIX;
2777 for (op = i.operands; --op >= 0;)
2778 if (operand_type_check (i.types[op], imm))
2780 switch (i.op[op].imms->X_op)
2783 /* If a suffix is given, this operand may be shortened. */
2784 switch (guess_suffix)
2786 case LONG_MNEM_SUFFIX:
2787 i.types[op].bitfield.imm32 = 1;
2788 i.types[op].bitfield.imm64 = 1;
2790 case WORD_MNEM_SUFFIX:
2791 i.types[op].bitfield.imm16 = 1;
2792 i.types[op].bitfield.imm32 = 1;
2793 i.types[op].bitfield.imm32s = 1;
2794 i.types[op].bitfield.imm64 = 1;
2796 case BYTE_MNEM_SUFFIX:
2797 i.types[op].bitfield.imm8 = 1;
2798 i.types[op].bitfield.imm8s = 1;
2799 i.types[op].bitfield.imm16 = 1;
2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm32s = 1;
2802 i.types[op].bitfield.imm64 = 1;
2806 /* If this operand is at most 16 bits, convert it
2807 to a signed 16 bit number before trying to see
2808 whether it will fit in an even smaller size.
2809 This allows a 16-bit operand such as $0xffe0 to
2810 be recognised as within Imm8S range. */
2811 if ((i.types[op].bitfield.imm16)
2812 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2814 i.op[op].imms->X_add_number =
2815 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2817 if ((i.types[op].bitfield.imm32)
2818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2822 ^ ((offsetT) 1 << 31))
2823 - ((offsetT) 1 << 31));
2826 = operand_type_or (i.types[op],
2827 smallest_imm_type (i.op[op].imms->X_add_number));
2829 /* We must avoid matching of Imm32 templates when 64bit
2830 only immediate is available. */
2831 if (guess_suffix == QWORD_MNEM_SUFFIX)
2832 i.types[op].bitfield.imm32 = 0;
2839 /* Symbols and expressions. */
2841 /* Convert symbolic operand to proper sizes for matching, but don't
2842 prevent matching a set of insns that only supports sizes other
2843 than those matching the insn suffix. */
2845 i386_operand_type mask, allowed;
2849 UINTS_CLEAR (allowed);
2851 for (t = current_templates->start;
2852 t < current_templates->end;
2854 allowed = operand_type_or (allowed,
2855 t->operand_types[op]);
2856 switch (guess_suffix)
2858 case QWORD_MNEM_SUFFIX:
2859 mask.bitfield.imm64 = 1;
2860 mask.bitfield.imm32s = 1;
2862 case LONG_MNEM_SUFFIX:
2863 mask.bitfield.imm32 = 1;
2865 case WORD_MNEM_SUFFIX:
2866 mask.bitfield.imm16 = 1;
2868 case BYTE_MNEM_SUFFIX:
2869 mask.bitfield.imm8 = 1;
2874 allowed = operand_type_and (mask, allowed);
2875 if (!UINTS_ALL_ZERO (allowed))
2876 i.types[op] = operand_type_and (i.types[op], mask);
2883 /* Try to use the smallest displacement type too. */
2885 optimize_disp (void)
2889 for (op = i.operands; --op >= 0;)
2890 if (operand_type_check (i.types[op], disp))
2892 if (i.op[op].disps->X_op == O_constant)
2894 offsetT disp = i.op[op].disps->X_add_number;
2896 if (i.types[op].bitfield.disp16
2897 && (disp & ~(offsetT) 0xffff) == 0)
2899 /* If this operand is at most 16 bits, convert
2900 to a signed 16 bit number and don't use 64bit
2902 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2903 i.types[op].bitfield.disp64 = 0;
2905 if (i.types[op].bitfield.disp32
2906 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2908 /* If this operand is at most 32 bits, convert
2909 to a signed 32 bit number and don't use 64bit
2911 disp &= (((offsetT) 2 << 31) - 1);
2912 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2913 i.types[op].bitfield.disp64 = 0;
2915 if (!disp && i.types[op].bitfield.baseindex)
2917 i.types[op].bitfield.disp8 = 0;
2918 i.types[op].bitfield.disp16 = 0;
2919 i.types[op].bitfield.disp32 = 0;
2920 i.types[op].bitfield.disp32s = 0;
2921 i.types[op].bitfield.disp64 = 0;
2925 else if (flag_code == CODE_64BIT)
2927 if (fits_in_signed_long (disp))
2929 i.types[op].bitfield.disp64 = 0;
2930 i.types[op].bitfield.disp32s = 1;
2932 if (fits_in_unsigned_long (disp))
2933 i.types[op].bitfield.disp32 = 1;
2935 if ((i.types[op].bitfield.disp32
2936 || i.types[op].bitfield.disp32s
2937 || i.types[op].bitfield.disp16)
2938 && fits_in_signed_byte (disp))
2939 i.types[op].bitfield.disp8 = 1;
2941 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2942 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2944 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2945 i.op[op].disps, 0, i.reloc[op]);
2946 i.types[op].bitfield.disp8 = 0;
2947 i.types[op].bitfield.disp16 = 0;
2948 i.types[op].bitfield.disp32 = 0;
2949 i.types[op].bitfield.disp32s = 0;
2950 i.types[op].bitfield.disp64 = 0;
2953 /* We only support 64bit displacement on constants. */
2954 i.types[op].bitfield.disp64 = 0;
2959 match_template (void)
2961 /* Points to template once we've found it. */
2963 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2964 unsigned int found_reverse_match;
2965 i386_opcode_modifier suffix_check;
2966 i386_operand_type operand_types [MAX_OPERANDS];
2967 int addr_prefix_disp;
2969 unsigned int found_cpu_match;
2970 unsigned int check_register;
2972 #if MAX_OPERANDS != 4
2973 # error "MAX_OPERANDS must be 4."
2976 found_reverse_match = 0;
2977 addr_prefix_disp = -1;
2979 memset (&suffix_check, 0, sizeof (suffix_check));
2980 if (i.suffix == BYTE_MNEM_SUFFIX)
2981 suffix_check.no_bsuf = 1;
2982 else if (i.suffix == WORD_MNEM_SUFFIX)
2983 suffix_check.no_wsuf = 1;
2984 else if (i.suffix == SHORT_MNEM_SUFFIX)
2985 suffix_check.no_ssuf = 1;
2986 else if (i.suffix == LONG_MNEM_SUFFIX)
2987 suffix_check.no_lsuf = 1;
2988 else if (i.suffix == QWORD_MNEM_SUFFIX)
2989 suffix_check.no_qsuf = 1;
2990 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
2991 suffix_check.no_ldsuf = 1;
2992 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
2993 suffix_check.xmmword = 1;
2995 for (t = current_templates->start; t < current_templates->end; t++)
2997 addr_prefix_disp = -1;
2999 /* Must have right number of operands. */
3000 if (i.operands != t->operands)
3003 /* Check old gcc support. */
3004 if (!old_gcc && t->opcode_modifier.oldgcc)
3007 /* Check AT&T mnemonic. */
3008 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3011 /* Check Intel syntax. */
3012 if (intel_syntax && t->opcode_modifier.attsyntax)
3015 /* Check the suffix, except for some instructions in intel mode. */
3016 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3017 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3018 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3019 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3020 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3021 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3022 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3025 /* Check the memory size in Intel mode when it is provided if
3029 && t->opcode_modifier.checksize
3030 && (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
3031 && (!t->opcode_modifier.word || !suffix_check.no_wsuf)
3032 && (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
3033 && (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
3034 && (!t->opcode_modifier.xmmword || !suffix_check.xmmword))
3037 for (j = 0; j < MAX_OPERANDS; j++)
3038 operand_types [j] = t->operand_types [j];
3040 /* In general, don't allow 64-bit operands in 32-bit mode. */
3041 if (i.suffix == QWORD_MNEM_SUFFIX
3042 && flag_code != CODE_64BIT
3044 ? (!t->opcode_modifier.ignoresize
3045 && !intel_float_operand (t->name))
3046 : intel_float_operand (t->name) != 2)
3047 && ((!operand_types[0].bitfield.regmmx
3048 && !operand_types[0].bitfield.regxmm)
3049 || (!operand_types[t->operands > 1].bitfield.regmmx
3050 && !!operand_types[t->operands > 1].bitfield.regxmm))
3051 && (t->base_opcode != 0x0fc7
3052 || t->extension_opcode != 1 /* cmpxchg8b */))
3055 /* Do not verify operands when there are none. */
3058 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3059 if (!found_cpu_match)
3062 /* We've found a match; break out of loop. */
3066 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3067 into Disp32/Disp16/Disp32 operand. */
3068 if (i.prefix[ADDR_PREFIX] != 0)
3070 /* There should be only one Disp operand. */
3074 for (j = 0; j < MAX_OPERANDS; j++)
3076 if (operand_types[j].bitfield.disp16)
3078 addr_prefix_disp = j;
3079 operand_types[j].bitfield.disp32 = 1;
3080 operand_types[j].bitfield.disp16 = 0;
3086 for (j = 0; j < MAX_OPERANDS; j++)
3088 if (operand_types[j].bitfield.disp32)
3090 addr_prefix_disp = j;
3091 operand_types[j].bitfield.disp32 = 0;
3092 operand_types[j].bitfield.disp16 = 1;
3098 for (j = 0; j < MAX_OPERANDS; j++)
3100 if (operand_types[j].bitfield.disp64)
3102 addr_prefix_disp = j;
3103 operand_types[j].bitfield.disp64 = 0;
3104 operand_types[j].bitfield.disp32 = 1;
3112 /* We check register size only if size of operands can be
3113 encoded the canonical way. */
3114 check_register = t->opcode_modifier.w;
3115 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3116 switch (t->operands)
3119 if (!operand_type_match (overlap0, i.types[0]))
3123 /* xchg %eax, %eax is a special case. It is an aliase for nop
3124 only in 32bit mode and we can use opcode 0x90. In 64bit
3125 mode, we can't use 0x90 for xchg %eax, %eax since it should
3126 zero-extend %eax to %rax. */
3127 if (flag_code == CODE_64BIT
3128 && t->base_opcode == 0x90
3129 && UINTS_EQUAL (i.types [0], acc32)
3130 && UINTS_EQUAL (i.types [1], acc32))
3134 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3135 if (!operand_type_match (overlap0, i.types[0])
3136 || !operand_type_match (overlap1, i.types[1])
3138 && !operand_type_register_match (overlap0, i.types[0],
3140 overlap1, i.types[1],
3143 /* Check if other direction is valid ... */
3144 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3147 /* Try reversing direction of operands. */
3148 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3149 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3150 if (!operand_type_match (overlap0, i.types[0])
3151 || !operand_type_match (overlap1, i.types[1])
3153 && !operand_type_register_match (overlap0,
3160 /* Does not match either direction. */
3163 /* found_reverse_match holds which of D or FloatDR
3165 if (t->opcode_modifier.d)
3166 found_reverse_match = Opcode_D;
3167 else if (t->opcode_modifier.floatd)
3168 found_reverse_match = Opcode_FloatD;
3170 found_reverse_match = 0;
3171 if (t->opcode_modifier.floatr)
3172 found_reverse_match |= Opcode_FloatR;
3176 /* Found a forward 2 operand match here. */
3177 switch (t->operands)
3180 overlap3 = operand_type_and (i.types[3],
3183 overlap2 = operand_type_and (i.types[2],
3188 switch (t->operands)
3191 if (!operand_type_match (overlap3, i.types[3])
3193 && !operand_type_register_match (overlap2,
3201 /* Here we make use of the fact that there are no
3202 reverse match 3 operand instructions, and all 3
3203 operand instructions only need to be checked for
3204 register consistency between operands 2 and 3. */
3205 if (!operand_type_match (overlap2, i.types[2])
3207 && !operand_type_register_match (overlap1,
3217 /* Found either forward/reverse 2, 3 or 4 operand match here:
3218 slip through to break. */
3220 if (!found_cpu_match)
3222 found_reverse_match = 0;
3225 /* We've found a match; break out of loop. */
3229 if (t == current_templates->end)
3231 /* We found no match. */
3232 as_bad (_("suffix or operands invalid for `%s'"),
3233 current_templates->start->name);
3237 if (!quiet_warnings)
3240 && (i.types[0].bitfield.jumpabsolute
3241 != operand_types[0].bitfield.jumpabsolute))
3243 as_warn (_("indirect %s without `*'"), t->name);
3246 if (t->opcode_modifier.isprefix
3247 && t->opcode_modifier.ignoresize)
3249 /* Warn them that a data or address size prefix doesn't
3250 affect assembly of the next line of code. */
3251 as_warn (_("stand-alone `%s' prefix"), t->name);
3255 /* Copy the template we found. */
3258 if (addr_prefix_disp != -1)
3259 i.tm.operand_types[addr_prefix_disp]
3260 = operand_types[addr_prefix_disp];
3262 if (found_reverse_match)
3264 /* If we found a reverse match we must alter the opcode
3265 direction bit. found_reverse_match holds bits to change
3266 (different for int & float insns). */
3268 i.tm.base_opcode ^= found_reverse_match;
3270 i.tm.operand_types[0] = operand_types[1];
3271 i.tm.operand_types[1] = operand_types[0];
3280 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3281 if (i.tm.operand_types[mem_op].bitfield.esseg)
3283 if (i.seg[0] != NULL && i.seg[0] != &es)
3285 as_bad (_("`%s' operand %d must use `%%es' segment"),
3290 /* There's only ever one segment override allowed per instruction.
3291 This instruction possibly has a legal segment override on the
3292 second operand, so copy the segment to where non-string
3293 instructions store it, allowing common code. */
3294 i.seg[0] = i.seg[1];
3296 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3298 if (i.seg[1] != NULL && i.seg[1] != &es)
3300 as_bad (_("`%s' operand %d must use `%%es' segment"),
3310 process_suffix (void)
3312 /* If matched instruction specifies an explicit instruction mnemonic
3314 if (i.tm.opcode_modifier.size16)
3315 i.suffix = WORD_MNEM_SUFFIX;
3316 else if (i.tm.opcode_modifier.size32)
3317 i.suffix = LONG_MNEM_SUFFIX;
3318 else if (i.tm.opcode_modifier.size64)
3319 i.suffix = QWORD_MNEM_SUFFIX;
3320 else if (i.reg_operands)
3322 /* If there's no instruction mnemonic suffix we try to invent one
3323 based on register operands. */
3326 /* We take i.suffix from the last register operand specified,
3327 Destination register type is more significant than source
3328 register type. crc32 in SSE4.2 prefers source register
3330 if (i.tm.base_opcode == 0xf20f38f1)
3332 if (i.types[0].bitfield.reg16)
3333 i.suffix = WORD_MNEM_SUFFIX;
3334 else if (i.types[0].bitfield.reg32)
3335 i.suffix = LONG_MNEM_SUFFIX;
3336 else if (i.types[0].bitfield.reg64)
3337 i.suffix = QWORD_MNEM_SUFFIX;
3339 else if (i.tm.base_opcode == 0xf20f38f0)
3341 if (i.types[0].bitfield.reg8)
3342 i.suffix = BYTE_MNEM_SUFFIX;
3349 if (i.tm.base_opcode == 0xf20f38f1
3350 || i.tm.base_opcode == 0xf20f38f0)
3352 /* We have to know the operand size for crc32. */
3353 as_bad (_("ambiguous memory operand size for `%s`"),
3358 for (op = i.operands; --op >= 0;)
3359 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3361 if (i.types[op].bitfield.reg8)
3363 i.suffix = BYTE_MNEM_SUFFIX;
3366 else if (i.types[op].bitfield.reg16)
3368 i.suffix = WORD_MNEM_SUFFIX;
3371 else if (i.types[op].bitfield.reg32)
3373 i.suffix = LONG_MNEM_SUFFIX;
3376 else if (i.types[op].bitfield.reg64)
3378 i.suffix = QWORD_MNEM_SUFFIX;
3384 else if (i.suffix == BYTE_MNEM_SUFFIX)
3386 if (!check_byte_reg ())
3389 else if (i.suffix == LONG_MNEM_SUFFIX)
3391 if (!check_long_reg ())
3394 else if (i.suffix == QWORD_MNEM_SUFFIX)
3397 && i.tm.opcode_modifier.ignoresize
3398 && i.tm.opcode_modifier.no_qsuf)
3400 else if (!check_qword_reg ())
3403 else if (i.suffix == WORD_MNEM_SUFFIX)
3405 if (!check_word_reg ())
3408 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3410 /* Skip if the instruction has x suffix. match_template
3411 should check if it is a valid suffix. */
3413 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3414 /* Do nothing if the instruction is going to ignore the prefix. */
3419 else if (i.tm.opcode_modifier.defaultsize
3421 /* exclude fldenv/frstor/fsave/fstenv */
3422 && i.tm.opcode_modifier.no_ssuf)
3424 i.suffix = stackop_size;
3426 else if (intel_syntax
3428 && (i.tm.operand_types[0].bitfield.jumpabsolute
3429 || i.tm.opcode_modifier.jumpbyte
3430 || i.tm.opcode_modifier.jumpintersegment
3431 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3432 && i.tm.extension_opcode <= 3)))
3437 if (!i.tm.opcode_modifier.no_qsuf)
3439 i.suffix = QWORD_MNEM_SUFFIX;
3443 if (!i.tm.opcode_modifier.no_lsuf)
3444 i.suffix = LONG_MNEM_SUFFIX;
3447 if (!i.tm.opcode_modifier.no_wsuf)
3448 i.suffix = WORD_MNEM_SUFFIX;
3457 if (i.tm.opcode_modifier.w)
3459 as_bad (_("no instruction mnemonic suffix given and "
3460 "no register operands; can't size instruction"));
3466 unsigned int suffixes;
3468 suffixes = !i.tm.opcode_modifier.no_bsuf;
3469 if (!i.tm.opcode_modifier.no_wsuf)
3471 if (!i.tm.opcode_modifier.no_lsuf)
3473 if (!i.tm.opcode_modifier.no_ldsuf)
3475 if (!i.tm.opcode_modifier.no_ssuf)
3477 if (!i.tm.opcode_modifier.no_qsuf)
3480 /* There are more than suffix matches. */
3481 if (i.tm.opcode_modifier.w
3482 || ((suffixes & (suffixes - 1))
3483 && !i.tm.opcode_modifier.defaultsize
3484 && !i.tm.opcode_modifier.ignoresize))
3486 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3492 /* Change the opcode based on the operand size given by i.suffix;
3493 We don't need to change things for byte insns. */
3496 && i.suffix != BYTE_MNEM_SUFFIX
3497 && i.suffix != XMMWORD_MNEM_SUFFIX)
3499 /* It's not a byte, select word/dword operation. */
3500 if (i.tm.opcode_modifier.w)
3502 if (i.tm.opcode_modifier.shortform)
3503 i.tm.base_opcode |= 8;
3505 i.tm.base_opcode |= 1;
3508 /* Now select between word & dword operations via the operand
3509 size prefix, except for instructions that will ignore this
3511 if (i.tm.opcode_modifier.addrprefixop0)
3513 /* The address size override prefix changes the size of the
3515 if ((flag_code == CODE_32BIT
3516 && i.op->regs[0].reg_type.bitfield.reg16)
3517 || (flag_code != CODE_32BIT
3518 && i.op->regs[0].reg_type.bitfield.reg32))
3519 if (!add_prefix (ADDR_PREFIX_OPCODE))
3522 else if (i.suffix != QWORD_MNEM_SUFFIX
3523 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3524 && !i.tm.opcode_modifier.ignoresize
3525 && !i.tm.opcode_modifier.floatmf
3526 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3527 || (flag_code == CODE_64BIT
3528 && i.tm.opcode_modifier.jumpbyte)))
3530 unsigned int prefix = DATA_PREFIX_OPCODE;
3532 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3533 prefix = ADDR_PREFIX_OPCODE;
3535 if (!add_prefix (prefix))
3539 /* Set mode64 for an operand. */
3540 if (i.suffix == QWORD_MNEM_SUFFIX
3541 && flag_code == CODE_64BIT
3542 && !i.tm.opcode_modifier.norex64)
3544 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3545 need rex64. cmpxchg8b is also a special case. */
3546 if (! (i.operands == 2
3547 && i.tm.base_opcode == 0x90
3548 && i.tm.extension_opcode == None
3549 && UINTS_EQUAL (i.types [0], acc64)
3550 && UINTS_EQUAL (i.types [1], acc64))
3551 && ! (i.operands == 1
3552 && i.tm.base_opcode == 0xfc7
3553 && i.tm.extension_opcode == 1
3554 && !operand_type_check (i.types [0], reg)
3555 && operand_type_check (i.types [0], anymem)))
3559 /* Size floating point instruction. */
3560 if (i.suffix == LONG_MNEM_SUFFIX)
3561 if (i.tm.opcode_modifier.floatmf)
3562 i.tm.base_opcode ^= 4;
3569 check_byte_reg (void)
3573 for (op = i.operands; --op >= 0;)
3575 /* If this is an eight bit register, it's OK. If it's the 16 or
3576 32 bit version of an eight bit register, we will just use the
3577 low portion, and that's OK too. */
3578 if (i.types[op].bitfield.reg8)
3581 /* Don't generate this warning if not needed. */
3582 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3585 /* crc32 doesn't generate this warning. */
3586 if (i.tm.base_opcode == 0xf20f38f0)
3589 if ((i.types[op].bitfield.reg16
3590 || i.types[op].bitfield.reg32
3591 || i.types[op].bitfield.reg64)
3592 && i.op[op].regs->reg_num < 4)
3594 /* Prohibit these changes in the 64bit mode, since the
3595 lowering is more complicated. */
3596 if (flag_code == CODE_64BIT
3597 && !i.tm.operand_types[op].bitfield.inoutportreg)
3599 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3600 register_prefix, i.op[op].regs->reg_name,
3604 #if REGISTER_WARNINGS
3606 && !i.tm.operand_types[op].bitfield.inoutportreg)
3607 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3609 (i.op[op].regs + (i.types[op].bitfield.reg16
3610 ? REGNAM_AL - REGNAM_AX
3611 : REGNAM_AL - REGNAM_EAX))->reg_name,
3613 i.op[op].regs->reg_name,
3618 /* Any other register is bad. */
3619 if (i.types[op].bitfield.reg16
3620 || i.types[op].bitfield.reg32
3621 || i.types[op].bitfield.reg64
3622 || i.types[op].bitfield.regmmx
3623 || i.types[op].bitfield.regxmm
3624 || i.types[op].bitfield.sreg2
3625 || i.types[op].bitfield.sreg3
3626 || i.types[op].bitfield.control
3627 || i.types[op].bitfield.debug
3628 || i.types[op].bitfield.test
3629 || i.types[op].bitfield.floatreg
3630 || i.types[op].bitfield.floatacc)
3632 as_bad (_("`%s%s' not allowed with `%s%c'"),
3634 i.op[op].regs->reg_name,
3644 check_long_reg (void)
3648 for (op = i.operands; --op >= 0;)
3649 /* Reject eight bit registers, except where the template requires
3650 them. (eg. movzb) */
3651 if (i.types[op].bitfield.reg8
3652 && (i.tm.operand_types[op].bitfield.reg16
3653 || i.tm.operand_types[op].bitfield.reg32
3654 || i.tm.operand_types[op].bitfield.acc))
3656 as_bad (_("`%s%s' not allowed with `%s%c'"),
3658 i.op[op].regs->reg_name,
3663 /* Warn if the e prefix on a general reg is missing. */
3664 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3665 && i.types[op].bitfield.reg16
3666 && (i.tm.operand_types[op].bitfield.reg32
3667 || i.tm.operand_types[op].bitfield.acc))
3669 /* Prohibit these changes in the 64bit mode, since the
3670 lowering is more complicated. */
3671 if (flag_code == CODE_64BIT)
3673 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3674 register_prefix, i.op[op].regs->reg_name,
3678 #if REGISTER_WARNINGS
3680 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3682 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3684 i.op[op].regs->reg_name,
3688 /* Warn if the r prefix on a general reg is missing. */
3689 else if (i.types[op].bitfield.reg64
3690 && (i.tm.operand_types[op].bitfield.reg32
3691 || i.tm.operand_types[op].bitfield.acc))
3694 && i.tm.opcode_modifier.toqword
3695 && !i.types[0].bitfield.regxmm)
3697 /* Convert to QWORD. We want REX byte. */
3698 i.suffix = QWORD_MNEM_SUFFIX;
3702 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3703 register_prefix, i.op[op].regs->reg_name,
3712 check_qword_reg (void)
3716 for (op = i.operands; --op >= 0; )
3717 /* Reject eight bit registers, except where the template requires
3718 them. (eg. movzb) */
3719 if (i.types[op].bitfield.reg8
3720 && (i.tm.operand_types[op].bitfield.reg16
3721 || i.tm.operand_types[op].bitfield.reg32
3722 || i.tm.operand_types[op].bitfield.acc))
3724 as_bad (_("`%s%s' not allowed with `%s%c'"),
3726 i.op[op].regs->reg_name,
3731 /* Warn if the e prefix on a general reg is missing. */
3732 else if ((i.types[op].bitfield.reg16
3733 || i.types[op].bitfield.reg32)
3734 && (i.tm.operand_types[op].bitfield.reg32
3735 || i.tm.operand_types[op].bitfield.acc))
3737 /* Prohibit these changes in the 64bit mode, since the
3738 lowering is more complicated. */
3740 && i.tm.opcode_modifier.todword
3741 && !i.types[0].bitfield.regxmm)
3743 /* Convert to DWORD. We don't want REX byte. */
3744 i.suffix = LONG_MNEM_SUFFIX;
3748 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3749 register_prefix, i.op[op].regs->reg_name,
3758 check_word_reg (void)
3761 for (op = i.operands; --op >= 0;)
3762 /* Reject eight bit registers, except where the template requires
3763 them. (eg. movzb) */
3764 if (i.types[op].bitfield.reg8
3765 && (i.tm.operand_types[op].bitfield.reg16
3766 || i.tm.operand_types[op].bitfield.reg32
3767 || i.tm.operand_types[op].bitfield.acc))
3769 as_bad (_("`%s%s' not allowed with `%s%c'"),
3771 i.op[op].regs->reg_name,
3776 /* Warn if the e prefix on a general reg is present. */
3777 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3778 && i.types[op].bitfield.reg32
3779 && (i.tm.operand_types[op].bitfield.reg16
3780 || i.tm.operand_types[op].bitfield.acc))
3782 /* Prohibit these changes in the 64bit mode, since the
3783 lowering is more complicated. */
3784 if (flag_code == CODE_64BIT)
3786 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3787 register_prefix, i.op[op].regs->reg_name,
3792 #if REGISTER_WARNINGS
3793 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3795 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3797 i.op[op].regs->reg_name,
3805 update_imm (unsigned int j)
3807 i386_operand_type overlap;
3809 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3810 if ((overlap.bitfield.imm8
3811 || overlap.bitfield.imm8s
3812 || overlap.bitfield.imm16
3813 || overlap.bitfield.imm32
3814 || overlap.bitfield.imm32s
3815 || overlap.bitfield.imm64)
3816 && !UINTS_EQUAL (overlap, imm8)
3817 && !UINTS_EQUAL (overlap, imm8s)
3818 && !UINTS_EQUAL (overlap, imm16)
3819 && !UINTS_EQUAL (overlap, imm32)
3820 && !UINTS_EQUAL (overlap, imm32s)
3821 && !UINTS_EQUAL (overlap, imm64))
3825 i386_operand_type temp;
3828 if (i.suffix == BYTE_MNEM_SUFFIX)
3830 temp.bitfield.imm8 = overlap.bitfield.imm8;
3831 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3833 else if (i.suffix == WORD_MNEM_SUFFIX)
3834 temp.bitfield.imm16 = overlap.bitfield.imm16;
3835 else if (i.suffix == QWORD_MNEM_SUFFIX)
3837 temp.bitfield.imm64 = overlap.bitfield.imm64;
3838 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3841 temp.bitfield.imm32 = overlap.bitfield.imm32;
3844 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3845 || UINTS_EQUAL (overlap, imm16_32)
3846 || UINTS_EQUAL (overlap, imm16_32s))
3848 UINTS_CLEAR (overlap);
3849 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3850 overlap.bitfield.imm16 = 1;
3852 overlap.bitfield.imm32s = 1;
3854 if (!UINTS_EQUAL (overlap, imm8)
3855 && !UINTS_EQUAL (overlap, imm8s)
3856 && !UINTS_EQUAL (overlap, imm16)
3857 && !UINTS_EQUAL (overlap, imm32)
3858 && !UINTS_EQUAL (overlap, imm32s)
3859 && !UINTS_EQUAL (overlap, imm64))
3861 as_bad (_("no instruction mnemonic suffix given; "
3862 "can't determine immediate size"));
3866 i.types[j] = overlap;
3876 for (j = 0; j < 2; j++)
3877 if (update_imm (j) == 0)
3880 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3881 assert (operand_type_check (i.types[2], imm) == 0);
3889 i.drex.modrm_reg = 0;
3890 i.drex.modrm_regmem = 0;
3892 /* SSE5 4 operand instructions must have the destination the same as
3893 one of the inputs. Figure out the destination register and cache
3894 it away in the drex field, and remember which fields to use for
3896 if (i.tm.opcode_modifier.drex
3897 && i.tm.opcode_modifier.drexv
3900 i.tm.extension_opcode = None;
3902 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3903 if (i.types[0].bitfield.regxmm != 0
3904 && i.types[1].bitfield.regxmm != 0
3905 && i.types[2].bitfield.regxmm != 0
3906 && i.types[3].bitfield.regxmm != 0
3907 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3908 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3910 /* Clear the arguments that are stored in drex. */
3911 UINTS_CLEAR (i.types[0]);
3912 UINTS_CLEAR (i.types[3]);
3913 i.reg_operands -= 2;
3915 /* There are two different ways to encode a 4 operand
3916 instruction with all registers that uses OC1 set to
3917 0 or 1. Favor setting OC1 to 0 since this mimics the
3918 actions of other SSE5 assemblers. Use modrm encoding 2
3919 for register/register. Include the high order bit that
3920 is normally stored in the REX byte in the register
3922 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3923 i.drex.modrm_reg = 2;
3924 i.drex.modrm_regmem = 1;
3925 i.drex.reg = (i.op[3].regs->reg_num
3926 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3929 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3930 else if (i.types[0].bitfield.regxmm != 0
3931 && i.types[1].bitfield.regxmm != 0
3932 && (i.types[2].bitfield.regxmm
3933 || operand_type_check (i.types[2], anymem))
3934 && i.types[3].bitfield.regxmm != 0
3935 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3936 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3938 /* clear the arguments that are stored in drex */
3939 UINTS_CLEAR (i.types[0]);
3940 UINTS_CLEAR (i.types[3]);
3941 i.reg_operands -= 2;
3943 /* Specify the modrm encoding for memory addressing. Include
3944 the high order bit that is normally stored in the REX byte
3945 in the register field. */
3946 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3947 i.drex.modrm_reg = 1;
3948 i.drex.modrm_regmem = 2;
3949 i.drex.reg = (i.op[3].regs->reg_num
3950 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3953 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3954 else if (i.types[0].bitfield.regxmm != 0
3955 && operand_type_check (i.types[1], anymem) != 0
3956 && i.types[2].bitfield.regxmm != 0
3957 && i.types[3].bitfield.regxmm != 0
3958 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3959 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3961 /* Clear the arguments that are stored in drex. */
3962 UINTS_CLEAR (i.types[0]);
3963 UINTS_CLEAR (i.types[3]);
3964 i.reg_operands -= 2;
3966 /* Specify the modrm encoding for memory addressing. Include
3967 the high order bit that is normally stored in the REX byte
3968 in the register field. */
3969 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3970 i.drex.modrm_reg = 2;
3971 i.drex.modrm_regmem = 1;
3972 i.drex.reg = (i.op[3].regs->reg_num
3973 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3976 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3977 else if (i.types[0].bitfield.regxmm != 0
3978 && i.types[1].bitfield.regxmm != 0
3979 && i.types[2].bitfield.regxmm != 0
3980 && i.types[3].bitfield.regxmm != 0
3981 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3982 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3984 /* clear the arguments that are stored in drex */
3985 UINTS_CLEAR (i.types[2]);
3986 UINTS_CLEAR (i.types[3]);
3987 i.reg_operands -= 2;
3989 /* There are two different ways to encode a 4 operand
3990 instruction with all registers that uses OC1 set to
3991 0 or 1. Favor setting OC1 to 0 since this mimics the
3992 actions of other SSE5 assemblers. Use modrm encoding
3993 2 for register/register. Include the high order bit that
3994 is normally stored in the REX byte in the register
3996 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3997 i.drex.modrm_reg = 1;
3998 i.drex.modrm_regmem = 0;
4000 /* Remember the register, including the upper bits */
4001 i.drex.reg = (i.op[3].regs->reg_num
4002 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4005 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4006 else if (i.types[0].bitfield.regxmm != 0
4007 && (i.types[1].bitfield.regxmm
4008 || operand_type_check (i.types[1], anymem))
4009 && i.types[2].bitfield.regxmm != 0
4010 && i.types[3].bitfield.regxmm != 0
4011 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4012 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4014 /* Clear the arguments that are stored in drex. */
4015 UINTS_CLEAR (i.types[2]);
4016 UINTS_CLEAR (i.types[3]);
4017 i.reg_operands -= 2;
4019 /* Specify the modrm encoding and remember the register
4020 including the bits normally stored in the REX byte. */
4021 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4022 i.drex.modrm_reg = 0;
4023 i.drex.modrm_regmem = 1;
4024 i.drex.reg = (i.op[3].regs->reg_num
4025 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4028 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4029 else if (operand_type_check (i.types[0], anymem) != 0
4030 && i.types[1].bitfield.regxmm != 0
4031 && i.types[2].bitfield.regxmm != 0
4032 && i.types[3].bitfield.regxmm != 0
4033 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4034 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4036 /* clear the arguments that are stored in drex */
4037 UINTS_CLEAR (i.types[2]);
4038 UINTS_CLEAR (i.types[3]);
4039 i.reg_operands -= 2;
4041 /* Specify the modrm encoding and remember the register
4042 including the bits normally stored in the REX byte. */
4043 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4044 i.drex.modrm_reg = 1;
4045 i.drex.modrm_regmem = 0;
4046 i.drex.reg = (i.op[3].regs->reg_num
4047 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4051 as_bad (_("Incorrect operands for the '%s' instruction"),
4055 /* SSE5 instructions with the DREX byte where the only memory operand
4056 is in the 2nd argument, and the first and last xmm register must
4057 match, and is encoded in the DREX byte. */
4058 else if (i.tm.opcode_modifier.drex
4059 && !i.tm.opcode_modifier.drexv
4062 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4063 if (i.types[0].bitfield.regxmm != 0
4064 && (i.types[1].bitfield.regxmm
4065 || operand_type_check(i.types[1], anymem))
4066 && i.types[2].bitfield.regxmm != 0
4067 && i.types[3].bitfield.regxmm != 0
4068 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4069 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4071 /* clear the arguments that are stored in drex */
4072 UINTS_CLEAR (i.types[0]);
4073 UINTS_CLEAR (i.types[3]);
4074 i.reg_operands -= 2;
4076 /* Specify the modrm encoding and remember the register
4077 including the high bit normally stored in the REX
4079 i.drex.modrm_reg = 2;
4080 i.drex.modrm_regmem = 1;
4081 i.drex.reg = (i.op[3].regs->reg_num
4082 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4086 as_bad (_("Incorrect operands for the '%s' instruction"),
4090 /* SSE5 3 operand instructions that the result is a register, being
4091 either operand can be a memory operand, using OC0 to note which
4092 one is the memory. */
4093 else if (i.tm.opcode_modifier.drex
4094 && i.tm.opcode_modifier.drexv
4097 i.tm.extension_opcode = None;
4099 /* Case 1: 3 operand insn, src1 = register. */
4100 if (i.types[0].bitfield.regxmm != 0
4101 && i.types[1].bitfield.regxmm != 0
4102 && i.types[2].bitfield.regxmm != 0)
4104 /* Clear the arguments that are stored in drex. */
4105 UINTS_CLEAR (i.types[2]);
4108 /* Specify the modrm encoding and remember the register
4109 including the high bit normally stored in the REX byte. */
4110 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4111 i.drex.modrm_reg = 1;
4112 i.drex.modrm_regmem = 0;
4113 i.drex.reg = (i.op[2].regs->reg_num
4114 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4117 /* Case 2: 3 operand insn, src1 = memory. */
4118 else if (operand_type_check (i.types[0], anymem) != 0
4119 && i.types[1].bitfield.regxmm != 0
4120 && i.types[2].bitfield.regxmm != 0)
4122 /* Clear the arguments that are stored in drex. */
4123 UINTS_CLEAR (i.types[2]);
4126 /* Specify the modrm encoding and remember the register
4127 including the high bit normally stored in the REX
4129 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4130 i.drex.modrm_reg = 1;
4131 i.drex.modrm_regmem = 0;
4132 i.drex.reg = (i.op[2].regs->reg_num
4133 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4136 /* Case 3: 3 operand insn, src2 = memory. */
4137 else if (i.types[0].bitfield.regxmm != 0
4138 && operand_type_check (i.types[1], anymem) != 0
4139 && i.types[2].bitfield.regxmm != 0)
4141 /* Clear the arguments that are stored in drex. */
4142 UINTS_CLEAR (i.types[2]);
4145 /* Specify the modrm encoding and remember the register
4146 including the high bit normally stored in the REX byte. */
4147 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4148 i.drex.modrm_reg = 0;
4149 i.drex.modrm_regmem = 1;
4150 i.drex.reg = (i.op[2].regs->reg_num
4151 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4155 as_bad (_("Incorrect operands for the '%s' instruction"),
4159 /* SSE5 4 operand instructions that are the comparison instructions
4160 where the first operand is the immediate value of the comparison
4162 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4164 /* Case 1: 4 operand insn, src1 = reg/memory. */
4165 if (operand_type_check (i.types[0], imm) != 0
4166 && (i.types[1].bitfield.regxmm
4167 || operand_type_check (i.types[1], anymem))
4168 && i.types[2].bitfield.regxmm != 0
4169 && i.types[3].bitfield.regxmm != 0)
4171 /* clear the arguments that are stored in drex */
4172 UINTS_CLEAR (i.types[3]);
4175 /* Specify the modrm encoding and remember the register
4176 including the high bit normally stored in the REX byte. */
4177 i.drex.modrm_reg = 2;
4178 i.drex.modrm_regmem = 1;
4179 i.drex.reg = (i.op[3].regs->reg_num
4180 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4183 /* Case 2: 3 operand insn with ImmExt that places the
4184 opcode_extension as an immediate argument. This is used for
4185 all of the varients of comparison that supplies the appropriate
4186 value as part of the instruction. */
4187 else if ((i.types[0].bitfield.regxmm
4188 || operand_type_check (i.types[0], anymem))
4189 && i.types[1].bitfield.regxmm != 0
4190 && i.types[2].bitfield.regxmm != 0
4191 && operand_type_check (i.types[3], imm) != 0)
4193 /* clear the arguments that are stored in drex */
4194 UINTS_CLEAR (i.types[2]);
4197 /* Specify the modrm encoding and remember the register
4198 including the high bit normally stored in the REX byte. */
4199 i.drex.modrm_reg = 1;
4200 i.drex.modrm_regmem = 0;
4201 i.drex.reg = (i.op[2].regs->reg_num
4202 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4206 as_bad (_("Incorrect operands for the '%s' instruction"),
4210 else if (i.tm.opcode_modifier.drex
4211 || i.tm.opcode_modifier.drexv
4212 || i.tm.opcode_modifier.drexc)
4213 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4217 process_operands (void)
4219 /* Default segment register this instruction will use for memory
4220 accesses. 0 means unknown. This is only for optimizing out
4221 unnecessary segment overrides. */
4222 const seg_entry *default_seg = 0;
4224 /* Handle all of the DREX munging that SSE5 needs. */
4225 if (i.tm.opcode_modifier.drex
4226 || i.tm.opcode_modifier.drexv
4227 || i.tm.opcode_modifier.drexc)
4230 if (i.tm.opcode_modifier.firstxmm0)
4234 /* The first operand is implicit and must be xmm0. */
4235 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4236 if (i.op[0].regs->reg_num != 0)
4239 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4240 i.tm.name, register_prefix);
4242 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4243 i.tm.name, register_prefix);
4247 for (j = 1; j < i.operands; j++)
4249 i.op[j - 1] = i.op[j];
4250 i.types[j - 1] = i.types[j];
4252 /* We need to adjust fields in i.tm since they are used by
4253 build_modrm_byte. */
4254 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4261 else if (i.tm.opcode_modifier.regkludge)
4263 /* The imul $imm, %reg instruction is converted into
4264 imul $imm, %reg, %reg, and the clr %reg instruction
4265 is converted into xor %reg, %reg. */
4267 unsigned int first_reg_op;
4269 if (operand_type_check (i.types[0], reg))
4273 /* Pretend we saw the extra register operand. */
4274 assert (i.reg_operands == 1
4275 && i.op[first_reg_op + 1].regs == 0);
4276 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4277 i.types[first_reg_op + 1] = i.types[first_reg_op];
4282 if (i.tm.opcode_modifier.shortform)
4284 if (i.types[0].bitfield.sreg2
4285 || i.types[0].bitfield.sreg3)
4287 if (i.tm.base_opcode == POP_SEG_SHORT
4288 && i.op[0].regs->reg_num == 1)
4290 as_bad (_("you can't `pop %%cs'"));
4293 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4294 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4299 /* The register or float register operand is in operand
4303 if (i.types[0].bitfield.floatreg
4304 || operand_type_check (i.types[0], reg))
4308 /* Register goes in low 3 bits of opcode. */
4309 i.tm.base_opcode |= i.op[op].regs->reg_num;
4310 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4312 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4314 /* Warn about some common errors, but press on regardless.
4315 The first case can be generated by gcc (<= 2.8.1). */
4316 if (i.operands == 2)
4318 /* Reversed arguments on faddp, fsubp, etc. */
4319 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4320 register_prefix, i.op[1].regs->reg_name,
4321 register_prefix, i.op[0].regs->reg_name);
4325 /* Extraneous `l' suffix on fp insn. */
4326 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4327 register_prefix, i.op[0].regs->reg_name);
4332 else if (i.tm.opcode_modifier.modrm)
4334 /* The opcode is completed (modulo i.tm.extension_opcode which
4335 must be put into the modrm byte). Now, we make the modrm and
4336 index base bytes based on all the info we've collected. */
4338 default_seg = build_modrm_byte ();
4340 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4344 else if (i.tm.opcode_modifier.isstring)
4346 /* For the string instructions that allow a segment override
4347 on one of their operands, the default segment is ds. */
4351 if (i.tm.base_opcode == 0x8d /* lea */
4354 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4356 /* If a segment was explicitly specified, and the specified segment
4357 is not the default, use an opcode prefix to select it. If we
4358 never figured out what the default segment is, then default_seg
4359 will be zero at this point, and the specified segment prefix will
4361 if ((i.seg[0]) && (i.seg[0] != default_seg))
4363 if (!add_prefix (i.seg[0]->seg_prefix))
4369 static const seg_entry *
4370 build_modrm_byte (void)
4372 const seg_entry *default_seg = 0;
4374 /* SSE5 4 operand instructions are encoded in such a way that one of
4375 the inputs must match the destination register. Process_drex hides
4376 the 3rd argument in the drex field, so that by the time we get
4377 here, it looks to GAS as if this is a 2 operand instruction. */
4378 if ((i.tm.opcode_modifier.drex
4379 || i.tm.opcode_modifier.drexv
4380 || i.tm.opcode_modifier.drexc)
4381 && i.reg_operands == 2)
4383 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4384 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4386 i.rm.reg = reg->reg_num;
4387 i.rm.regmem = regmem->reg_num;
4389 if ((reg->reg_flags & RegRex) != 0)
4391 if ((regmem->reg_flags & RegRex) != 0)
4395 /* i.reg_operands MUST be the number of real register operands;
4396 implicit registers do not count. */
4397 else if (i.reg_operands == 2)
4399 unsigned int source, dest;
4407 /* When there are 3 operands, one of them may be immediate,
4408 which may be the first or the last operand. Otherwise,
4409 the first operand must be shift count register (cl). */
4410 assert (i.imm_operands == 1
4411 || (i.imm_operands == 0
4412 && i.types[0].bitfield.shiftcount));
4413 if (operand_type_check (i.types[0], imm)
4414 || i.types[0].bitfield.shiftcount)
4420 /* When there are 4 operands, the first two must be 8bit
4421 immediate operands. The source operand will be the 3rd
4423 assert (i.imm_operands == 2
4424 && i.types[0].bitfield.imm8
4425 && i.types[1].bitfield.imm8);
4435 /* One of the register operands will be encoded in the i.tm.reg
4436 field, the other in the combined i.tm.mode and i.tm.regmem
4437 fields. If no form of this instruction supports a memory
4438 destination operand, then we assume the source operand may
4439 sometimes be a memory operand and so we need to store the
4440 destination in the i.rm.reg field. */
4441 if (!i.tm.operand_types[dest].bitfield.regmem
4442 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4444 i.rm.reg = i.op[dest].regs->reg_num;
4445 i.rm.regmem = i.op[source].regs->reg_num;
4446 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4448 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4453 i.rm.reg = i.op[source].regs->reg_num;
4454 i.rm.regmem = i.op[dest].regs->reg_num;
4455 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4457 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4460 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4462 if (!i.types[0].bitfield.control
4463 && !i.types[1].bitfield.control)
4465 i.rex &= ~(REX_R | REX_B);
4466 add_prefix (LOCK_PREFIX_OPCODE);
4470 { /* If it's not 2 reg operands... */
4473 unsigned int fake_zero_displacement = 0;
4476 /* This has been precalculated for SSE5 instructions
4477 that have a DREX field earlier in process_drex. */
4478 if (i.tm.opcode_modifier.drex
4479 || i.tm.opcode_modifier.drexv
4480 || i.tm.opcode_modifier.drexc)
4481 op = i.drex.modrm_regmem;
4484 for (op = 0; op < i.operands; op++)
4485 if (operand_type_check (i.types[op], anymem))
4487 assert (op < i.operands);
4492 if (i.base_reg == 0)
4495 if (!i.disp_operands)
4496 fake_zero_displacement = 1;
4497 if (i.index_reg == 0)
4499 /* Operand is just <disp> */
4500 if (flag_code == CODE_64BIT)
4502 /* 64bit mode overwrites the 32bit absolute
4503 addressing by RIP relative addressing and
4504 absolute addressing is encoded by one of the
4505 redundant SIB forms. */
4506 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4507 i.sib.base = NO_BASE_REGISTER;
4508 i.sib.index = NO_INDEX_REGISTER;
4509 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4510 ? disp32s : disp32);
4512 else if ((flag_code == CODE_16BIT)
4513 ^ (i.prefix[ADDR_PREFIX] != 0))
4515 i.rm.regmem = NO_BASE_REGISTER_16;
4516 i.types[op] = disp16;
4520 i.rm.regmem = NO_BASE_REGISTER;
4521 i.types[op] = disp32;
4524 else /* !i.base_reg && i.index_reg */
4526 if (i.index_reg->reg_num == RegEiz
4527 || i.index_reg->reg_num == RegRiz)
4528 i.sib.index = NO_INDEX_REGISTER;
4530 i.sib.index = i.index_reg->reg_num;
4531 i.sib.base = NO_BASE_REGISTER;
4532 i.sib.scale = i.log2_scale_factor;
4533 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4534 i.types[op].bitfield.disp8 = 0;
4535 i.types[op].bitfield.disp16 = 0;
4536 i.types[op].bitfield.disp64 = 0;
4537 if (flag_code != CODE_64BIT)
4539 /* Must be 32 bit */
4540 i.types[op].bitfield.disp32 = 1;
4541 i.types[op].bitfield.disp32s = 0;
4545 i.types[op].bitfield.disp32 = 0;
4546 i.types[op].bitfield.disp32s = 1;
4548 if ((i.index_reg->reg_flags & RegRex) != 0)
4552 /* RIP addressing for 64bit mode. */
4553 else if (i.base_reg->reg_num == RegRip ||
4554 i.base_reg->reg_num == RegEip)
4556 i.rm.regmem = NO_BASE_REGISTER;
4557 i.types[op].bitfield.disp8 = 0;
4558 i.types[op].bitfield.disp16 = 0;
4559 i.types[op].bitfield.disp32 = 0;
4560 i.types[op].bitfield.disp32s = 1;
4561 i.types[op].bitfield.disp64 = 0;
4562 i.flags[op] |= Operand_PCrel;
4563 if (! i.disp_operands)
4564 fake_zero_displacement = 1;
4566 else if (i.base_reg->reg_type.bitfield.reg16)
4568 switch (i.base_reg->reg_num)
4571 if (i.index_reg == 0)
4573 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4574 i.rm.regmem = i.index_reg->reg_num - 6;
4578 if (i.index_reg == 0)
4581 if (operand_type_check (i.types[op], disp) == 0)
4583 /* fake (%bp) into 0(%bp) */
4584 i.types[op].bitfield.disp8 = 1;
4585 fake_zero_displacement = 1;
4588 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4589 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4591 default: /* (%si) -> 4 or (%di) -> 5 */
4592 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4594 i.rm.mode = mode_from_disp_size (i.types[op]);
4596 else /* i.base_reg and 32/64 bit mode */
4598 if (flag_code == CODE_64BIT
4599 && operand_type_check (i.types[op], disp))
4601 i386_operand_type temp;
4603 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4605 if (i.prefix[ADDR_PREFIX] == 0)
4606 i.types[op].bitfield.disp32s = 1;
4608 i.types[op].bitfield.disp32 = 1;
4611 i.rm.regmem = i.base_reg->reg_num;
4612 if ((i.base_reg->reg_flags & RegRex) != 0)
4614 i.sib.base = i.base_reg->reg_num;
4615 /* x86-64 ignores REX prefix bit here to avoid decoder
4617 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4620 if (i.disp_operands == 0)
4622 fake_zero_displacement = 1;
4623 i.types[op].bitfield.disp8 = 1;
4626 else if (i.base_reg->reg_num == ESP_REG_NUM)
4630 i.sib.scale = i.log2_scale_factor;
4631 if (i.index_reg == 0)
4633 /* <disp>(%esp) becomes two byte modrm with no index
4634 register. We've already stored the code for esp
4635 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4636 Any base register besides %esp will not use the
4637 extra modrm byte. */
4638 i.sib.index = NO_INDEX_REGISTER;
4642 if (i.index_reg->reg_num == RegEiz
4643 || i.index_reg->reg_num == RegRiz)
4644 i.sib.index = NO_INDEX_REGISTER;
4646 i.sib.index = i.index_reg->reg_num;
4647 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4648 if ((i.index_reg->reg_flags & RegRex) != 0)
4653 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4654 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4657 i.rm.mode = mode_from_disp_size (i.types[op]);
4660 if (fake_zero_displacement)
4662 /* Fakes a zero displacement assuming that i.types[op]
4663 holds the correct displacement size. */
4666 assert (i.op[op].disps == 0);
4667 exp = &disp_expressions[i.disp_operands++];
4668 i.op[op].disps = exp;
4669 exp->X_op = O_constant;
4670 exp->X_add_number = 0;
4671 exp->X_add_symbol = (symbolS *) 0;
4672 exp->X_op_symbol = (symbolS *) 0;
4676 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4677 (if any) based on i.tm.extension_opcode. Again, we must be
4678 careful to make sure that segment/control/debug/test/MMX
4679 registers are coded into the i.rm.reg field. */
4684 /* This has been precalculated for SSE5 instructions
4685 that have a DREX field earlier in process_drex. */
4686 if (i.tm.opcode_modifier.drex
4687 || i.tm.opcode_modifier.drexv
4688 || i.tm.opcode_modifier.drexc)
4690 op = i.drex.modrm_reg;
4691 i.rm.reg = i.op[op].regs->reg_num;
4692 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4697 for (op = 0; op < i.operands; op++)
4698 if (i.types[op].bitfield.reg8
4699 || i.types[op].bitfield.reg16
4700 || i.types[op].bitfield.reg32
4701 || i.types[op].bitfield.reg64
4702 || i.types[op].bitfield.regmmx
4703 || i.types[op].bitfield.regxmm
4704 || i.types[op].bitfield.sreg2
4705 || i.types[op].bitfield.sreg3
4706 || i.types[op].bitfield.control
4707 || i.types[op].bitfield.debug
4708 || i.types[op].bitfield.test)
4711 assert (op < i.operands);
4713 /* If there is an extension opcode to put here, the
4714 register number must be put into the regmem field. */
4715 if (i.tm.extension_opcode != None)
4717 i.rm.regmem = i.op[op].regs->reg_num;
4718 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4723 i.rm.reg = i.op[op].regs->reg_num;
4724 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4729 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4730 must set it to 3 to indicate this is a register operand
4731 in the regmem field. */
4732 if (!i.mem_operands)
4736 /* Fill in i.rm.reg field with extension opcode (if any). */
4737 if (i.tm.extension_opcode != None
4738 && !(i.tm.opcode_modifier.drex
4739 || i.tm.opcode_modifier.drexv
4740 || i.tm.opcode_modifier.drexc))
4741 i.rm.reg = i.tm.extension_opcode;
4747 output_branch (void)
4752 relax_substateT subtype;
4757 if (flag_code == CODE_16BIT)
4761 if (i.prefix[DATA_PREFIX] != 0)
4767 /* Pentium4 branch hints. */
4768 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4769 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4774 if (i.prefix[REX_PREFIX] != 0)
4780 if (i.prefixes != 0 && !intel_syntax)
4781 as_warn (_("skipping prefixes on this instruction"));
4783 /* It's always a symbol; End frag & setup for relax.
4784 Make sure there is enough room in this frag for the largest
4785 instruction we may generate in md_convert_frag. This is 2
4786 bytes for the opcode and room for the prefix and largest
4788 frag_grow (prefix + 2 + 4);
4789 /* Prefix and 1 opcode byte go in fr_fix. */
4790 p = frag_more (prefix + 1);
4791 if (i.prefix[DATA_PREFIX] != 0)
4792 *p++ = DATA_PREFIX_OPCODE;
4793 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4794 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4795 *p++ = i.prefix[SEG_PREFIX];
4796 if (i.prefix[REX_PREFIX] != 0)
4797 *p++ = i.prefix[REX_PREFIX];
4798 *p = i.tm.base_opcode;
4800 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4801 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4802 else if (cpu_arch_flags.bitfield.cpui386)
4803 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4805 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4808 sym = i.op[0].disps->X_add_symbol;
4809 off = i.op[0].disps->X_add_number;
4811 if (i.op[0].disps->X_op != O_constant
4812 && i.op[0].disps->X_op != O_symbol)
4814 /* Handle complex expressions. */
4815 sym = make_expr_symbol (i.op[0].disps);
4819 /* 1 possible extra opcode + 4 byte displacement go in var part.
4820 Pass reloc in fr_var. */
4821 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4831 if (i.tm.opcode_modifier.jumpbyte)
4833 /* This is a loop or jecxz type instruction. */
4835 if (i.prefix[ADDR_PREFIX] != 0)
4837 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4840 /* Pentium4 branch hints. */
4841 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4842 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4844 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4853 if (flag_code == CODE_16BIT)
4856 if (i.prefix[DATA_PREFIX] != 0)
4858 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4868 if (i.prefix[REX_PREFIX] != 0)
4870 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4874 if (i.prefixes != 0 && !intel_syntax)
4875 as_warn (_("skipping prefixes on this instruction"));
4877 p = frag_more (1 + size);
4878 *p++ = i.tm.base_opcode;
4880 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4881 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4883 /* All jumps handled here are signed, but don't use a signed limit
4884 check for 32 and 16 bit jumps as we want to allow wrap around at
4885 4G and 64k respectively. */
4887 fixP->fx_signed = 1;
4891 output_interseg_jump (void)
4899 if (flag_code == CODE_16BIT)
4903 if (i.prefix[DATA_PREFIX] != 0)
4909 if (i.prefix[REX_PREFIX] != 0)
4919 if (i.prefixes != 0 && !intel_syntax)
4920 as_warn (_("skipping prefixes on this instruction"));
4922 /* 1 opcode; 2 segment; offset */
4923 p = frag_more (prefix + 1 + 2 + size);
4925 if (i.prefix[DATA_PREFIX] != 0)
4926 *p++ = DATA_PREFIX_OPCODE;
4928 if (i.prefix[REX_PREFIX] != 0)
4929 *p++ = i.prefix[REX_PREFIX];
4931 *p++ = i.tm.base_opcode;
4932 if (i.op[1].imms->X_op == O_constant)
4934 offsetT n = i.op[1].imms->X_add_number;
4937 && !fits_in_unsigned_word (n)
4938 && !fits_in_signed_word (n))
4940 as_bad (_("16-bit jump out of range"));
4943 md_number_to_chars (p, n, size);
4946 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4947 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4948 if (i.op[0].imms->X_op != O_constant)
4949 as_bad (_("can't handle non absolute segment in `%s'"),
4951 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4957 fragS *insn_start_frag;
4958 offsetT insn_start_off;
4960 /* Tie dwarf2 debug info to the address at the start of the insn.
4961 We can't do this after the insn has been output as the current
4962 frag may have been closed off. eg. by frag_var. */
4963 dwarf2_emit_insn (0);
4965 insn_start_frag = frag_now;
4966 insn_start_off = frag_now_fix ();
4969 if (i.tm.opcode_modifier.jump)
4971 else if (i.tm.opcode_modifier.jumpbyte
4972 || i.tm.opcode_modifier.jumpdword)
4974 else if (i.tm.opcode_modifier.jumpintersegment)
4975 output_interseg_jump ();
4978 /* Output normal instructions here. */
4982 unsigned int prefix;
4984 switch (i.tm.opcode_length)
4987 if (i.tm.base_opcode & 0xff000000)
4989 prefix = (i.tm.base_opcode >> 24) & 0xff;
4994 if ((i.tm.base_opcode & 0xff0000) != 0)
4996 prefix = (i.tm.base_opcode >> 16) & 0xff;
4997 if (i.tm.cpu_flags.bitfield.cpupadlock)
5000 if (prefix != REPE_PREFIX_OPCODE
5001 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5002 add_prefix (prefix);
5005 add_prefix (prefix);
5014 /* The prefix bytes. */
5015 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5017 FRAG_APPEND_1_CHAR (*q);
5019 /* Now the opcode; be careful about word order here! */
5020 if (i.tm.opcode_length == 1)
5022 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5026 switch (i.tm.opcode_length)
5030 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5040 /* Put out high byte first: can't use md_number_to_chars! */
5041 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5042 *p = i.tm.base_opcode & 0xff;
5044 /* On SSE5, encode the OC1 bit in the DREX field if this
5045 encoding has multiple formats. */
5046 if (i.tm.opcode_modifier.drex
5047 && i.tm.opcode_modifier.drexv
5048 && DREX_OC1 (i.tm.extension_opcode))
5049 *p |= DREX_OC1_MASK;
5052 /* Now the modrm byte and sib byte (if present). */
5053 if (i.tm.opcode_modifier.modrm)
5055 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5058 /* If i.rm.regmem == ESP (4)
5059 && i.rm.mode != (Register mode)
5061 ==> need second modrm byte. */
5062 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5064 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5065 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5067 | i.sib.scale << 6));
5070 /* Write the DREX byte if needed. */
5071 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5074 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5076 /* Encode the OC0 bit if this encoding has multiple
5078 if ((i.tm.opcode_modifier.drex
5079 || i.tm.opcode_modifier.drexv)
5080 && DREX_OC0 (i.tm.extension_opcode))
5081 *p |= DREX_OC0_MASK;
5084 if (i.disp_operands)
5085 output_disp (insn_start_frag, insn_start_off);
5088 output_imm (insn_start_frag, insn_start_off);
5094 pi ("" /*line*/, &i);
5096 #endif /* DEBUG386 */
5099 /* Return the size of the displacement operand N. */
5102 disp_size (unsigned int n)
5105 if (i.types[n].bitfield.disp64)
5107 else if (i.types[n].bitfield.disp8)
5109 else if (i.types[n].bitfield.disp16)
5114 /* Return the size of the immediate operand N. */
5117 imm_size (unsigned int n)
5120 if (i.types[n].bitfield.imm64)
5122 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5124 else if (i.types[n].bitfield.imm16)
5130 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5135 for (n = 0; n < i.operands; n++)
5137 if (operand_type_check (i.types[n], disp))
5139 if (i.op[n].disps->X_op == O_constant)
5141 int size = disp_size (n);
5144 val = offset_in_range (i.op[n].disps->X_add_number,
5146 p = frag_more (size);
5147 md_number_to_chars (p, val, size);
5151 enum bfd_reloc_code_real reloc_type;
5152 int size = disp_size (n);
5153 int sign = i.types[n].bitfield.disp32s;
5154 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5156 /* We can't have 8 bit displacement here. */
5157 assert (!i.types[n].bitfield.disp8);
5159 /* The PC relative address is computed relative
5160 to the instruction boundary, so in case immediate
5161 fields follows, we need to adjust the value. */
5162 if (pcrel && i.imm_operands)
5167 for (n1 = 0; n1 < i.operands; n1++)
5168 if (operand_type_check (i.types[n1], imm))
5170 /* Only one immediate is allowed for PC
5171 relative address. */
5174 i.op[n].disps->X_add_number -= sz;
5176 /* We should find the immediate. */
5180 p = frag_more (size);
5181 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5183 && GOT_symbol == i.op[n].disps->X_add_symbol
5184 && (((reloc_type == BFD_RELOC_32
5185 || reloc_type == BFD_RELOC_X86_64_32S
5186 || (reloc_type == BFD_RELOC_64
5188 && (i.op[n].disps->X_op == O_symbol
5189 || (i.op[n].disps->X_op == O_add
5190 && ((symbol_get_value_expression
5191 (i.op[n].disps->X_op_symbol)->X_op)
5193 || reloc_type == BFD_RELOC_32_PCREL))
5197 if (insn_start_frag == frag_now)
5198 add = (p - frag_now->fr_literal) - insn_start_off;
5203 add = insn_start_frag->fr_fix - insn_start_off;
5204 for (fr = insn_start_frag->fr_next;
5205 fr && fr != frag_now; fr = fr->fr_next)
5207 add += p - frag_now->fr_literal;
5212 reloc_type = BFD_RELOC_386_GOTPC;
5213 i.op[n].imms->X_add_number += add;
5215 else if (reloc_type == BFD_RELOC_64)
5216 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5218 /* Don't do the adjustment for x86-64, as there
5219 the pcrel addressing is relative to the _next_
5220 insn, and that is taken care of in other code. */
5221 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5223 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5224 i.op[n].disps, pcrel, reloc_type);
5231 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5236 for (n = 0; n < i.operands; n++)
5238 if (operand_type_check (i.types[n], imm))
5240 if (i.op[n].imms->X_op == O_constant)
5242 int size = imm_size (n);
5245 val = offset_in_range (i.op[n].imms->X_add_number,
5247 p = frag_more (size);
5248 md_number_to_chars (p, val, size);
5252 /* Not absolute_section.
5253 Need a 32-bit fixup (don't support 8bit
5254 non-absolute imms). Try to support other
5256 enum bfd_reloc_code_real reloc_type;
5257 int size = imm_size (n);
5260 if (i.types[n].bitfield.imm32s
5261 && (i.suffix == QWORD_MNEM_SUFFIX
5262 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5267 p = frag_more (size);
5268 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5270 /* This is tough to explain. We end up with this one if we
5271 * have operands that look like
5272 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5273 * obtain the absolute address of the GOT, and it is strongly
5274 * preferable from a performance point of view to avoid using
5275 * a runtime relocation for this. The actual sequence of
5276 * instructions often look something like:
5281 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5283 * The call and pop essentially return the absolute address
5284 * of the label .L66 and store it in %ebx. The linker itself
5285 * will ultimately change the first operand of the addl so
5286 * that %ebx points to the GOT, but to keep things simple, the
5287 * .o file must have this operand set so that it generates not
5288 * the absolute address of .L66, but the absolute address of
5289 * itself. This allows the linker itself simply treat a GOTPC
5290 * relocation as asking for a pcrel offset to the GOT to be
5291 * added in, and the addend of the relocation is stored in the
5292 * operand field for the instruction itself.
5294 * Our job here is to fix the operand so that it would add
5295 * the correct offset so that %ebx would point to itself. The
5296 * thing that is tricky is that .-.L66 will point to the
5297 * beginning of the instruction, so we need to further modify
5298 * the operand so that it will point to itself. There are
5299 * other cases where you have something like:
5301 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5303 * and here no correction would be required. Internally in
5304 * the assembler we treat operands of this form as not being
5305 * pcrel since the '.' is explicitly mentioned, and I wonder
5306 * whether it would simplify matters to do it this way. Who
5307 * knows. In earlier versions of the PIC patches, the
5308 * pcrel_adjust field was used to store the correction, but
5309 * since the expression is not pcrel, I felt it would be
5310 * confusing to do it this way. */
5312 if ((reloc_type == BFD_RELOC_32
5313 || reloc_type == BFD_RELOC_X86_64_32S
5314 || reloc_type == BFD_RELOC_64)
5316 && GOT_symbol == i.op[n].imms->X_add_symbol
5317 && (i.op[n].imms->X_op == O_symbol
5318 || (i.op[n].imms->X_op == O_add
5319 && ((symbol_get_value_expression
5320 (i.op[n].imms->X_op_symbol)->X_op)
5325 if (insn_start_frag == frag_now)
5326 add = (p - frag_now->fr_literal) - insn_start_off;
5331 add = insn_start_frag->fr_fix - insn_start_off;
5332 for (fr = insn_start_frag->fr_next;
5333 fr && fr != frag_now; fr = fr->fr_next)
5335 add += p - frag_now->fr_literal;
5339 reloc_type = BFD_RELOC_386_GOTPC;
5341 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5343 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5344 i.op[n].imms->X_add_number += add;
5346 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5347 i.op[n].imms, 0, reloc_type);
5353 /* x86_cons_fix_new is called via the expression parsing code when a
5354 reloc is needed. We use this hook to get the correct .got reloc. */
5355 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5356 static int cons_sign = -1;
5359 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5362 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5364 got_reloc = NO_RELOC;
5367 if (exp->X_op == O_secrel)
5369 exp->X_op = O_symbol;
5370 r = BFD_RELOC_32_SECREL;
5374 fix_new_exp (frag, off, len, exp, 0, r);
5377 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5378 # define lex_got(reloc, adjust, types) NULL
5380 /* Parse operands of the form
5381 <symbol>@GOTOFF+<nnn>
5382 and similar .plt or .got references.
5384 If we find one, set up the correct relocation in RELOC and copy the
5385 input string, minus the `@GOTOFF' into a malloc'd buffer for
5386 parsing by the calling routine. Return this buffer, and if ADJUST
5387 is non-null set it to the length of the string we removed from the
5388 input line. Otherwise return NULL. */
5390 lex_got (enum bfd_reloc_code_real *reloc,
5392 i386_operand_type *types)
5394 /* Some of the relocations depend on the size of what field is to
5395 be relocated. But in our callers i386_immediate and i386_displacement
5396 we don't yet know the operand size (this will be set by insn
5397 matching). Hence we record the word32 relocation here,
5398 and adjust the reloc according to the real size in reloc(). */
5399 static const struct {
5401 const enum bfd_reloc_code_real rel[2];
5402 const i386_operand_type types64;
5405 BFD_RELOC_X86_64_PLTOFF64 },
5406 OPERAND_TYPE_IMM64 },
5407 { "PLT", { BFD_RELOC_386_PLT32,
5408 BFD_RELOC_X86_64_PLT32 },
5409 OPERAND_TYPE_IMM32_32S_DISP32 },
5411 BFD_RELOC_X86_64_GOTPLT64 },
5412 OPERAND_TYPE_IMM64_DISP64 },
5413 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5414 BFD_RELOC_X86_64_GOTOFF64 },
5415 OPERAND_TYPE_IMM64_DISP64 },
5417 BFD_RELOC_X86_64_GOTPCREL },
5418 OPERAND_TYPE_IMM32_32S_DISP32 },
5419 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5420 BFD_RELOC_X86_64_TLSGD },
5421 OPERAND_TYPE_IMM32_32S_DISP32 },
5422 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5424 OPERAND_TYPE_NONE },
5426 BFD_RELOC_X86_64_TLSLD },
5427 OPERAND_TYPE_IMM32_32S_DISP32 },
5428 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5429 BFD_RELOC_X86_64_GOTTPOFF },
5430 OPERAND_TYPE_IMM32_32S_DISP32 },
5431 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5432 BFD_RELOC_X86_64_TPOFF32 },
5433 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5434 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5436 OPERAND_TYPE_NONE },
5437 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5438 BFD_RELOC_X86_64_DTPOFF32 },
5440 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5441 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5443 OPERAND_TYPE_NONE },
5444 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5446 OPERAND_TYPE_NONE },
5447 { "GOT", { BFD_RELOC_386_GOT32,
5448 BFD_RELOC_X86_64_GOT32 },
5449 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5450 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5451 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5452 OPERAND_TYPE_IMM32_32S_DISP32 },
5453 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5454 BFD_RELOC_X86_64_TLSDESC_CALL },
5455 OPERAND_TYPE_IMM32_32S_DISP32 },
5463 for (cp = input_line_pointer; *cp != '@'; cp++)
5464 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5467 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5471 len = strlen (gotrel[j].str);
5472 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5474 if (gotrel[j].rel[object_64bit] != 0)
5477 char *tmpbuf, *past_reloc;
5479 *reloc = gotrel[j].rel[object_64bit];
5485 if (flag_code != CODE_64BIT)
5487 types->bitfield.imm32 = 1;
5488 types->bitfield.disp32 = 1;
5491 *types = gotrel[j].types64;
5494 if (GOT_symbol == NULL)
5495 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5497 /* The length of the first part of our input line. */
5498 first = cp - input_line_pointer;
5500 /* The second part goes from after the reloc token until
5501 (and including) an end_of_line char or comma. */
5502 past_reloc = cp + 1 + len;
5504 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5506 second = cp + 1 - past_reloc;
5508 /* Allocate and copy string. The trailing NUL shouldn't
5509 be necessary, but be safe. */
5510 tmpbuf = xmalloc (first + second + 2);
5511 memcpy (tmpbuf, input_line_pointer, first);
5512 if (second != 0 && *past_reloc != ' ')
5513 /* Replace the relocation token with ' ', so that
5514 errors like foo@GOTOFF1 will be detected. */
5515 tmpbuf[first++] = ' ';
5516 memcpy (tmpbuf + first, past_reloc, second);
5517 tmpbuf[first + second] = '\0';
5521 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5522 gotrel[j].str, 1 << (5 + object_64bit));
5527 /* Might be a symbol version string. Don't as_bad here. */
5532 x86_cons (expressionS *exp, int size)
5534 if (size == 4 || (object_64bit && size == 8))
5536 /* Handle @GOTOFF and the like in an expression. */
5538 char *gotfree_input_line;
5541 save = input_line_pointer;
5542 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5543 if (gotfree_input_line)
5544 input_line_pointer = gotfree_input_line;
5548 if (gotfree_input_line)
5550 /* expression () has merrily parsed up to the end of line,
5551 or a comma - in the wrong buffer. Transfer how far
5552 input_line_pointer has moved to the right buffer. */
5553 input_line_pointer = (save
5554 + (input_line_pointer - gotfree_input_line)
5556 free (gotfree_input_line);
5557 if (exp->X_op == O_constant
5558 || exp->X_op == O_absent
5559 || exp->X_op == O_illegal
5560 || exp->X_op == O_register
5561 || exp->X_op == O_big)
5563 char c = *input_line_pointer;
5564 *input_line_pointer = 0;
5565 as_bad (_("missing or invalid expression `%s'"), save);
5566 *input_line_pointer = c;
5575 static void signed_cons (int size)
5577 if (flag_code == CODE_64BIT)
5585 pe_directive_secrel (dummy)
5586 int dummy ATTRIBUTE_UNUSED;
5593 if (exp.X_op == O_symbol)
5594 exp.X_op = O_secrel;
5596 emit_expr (&exp, 4);
5598 while (*input_line_pointer++ == ',');
5600 input_line_pointer--;
5601 demand_empty_rest_of_line ();
5606 i386_immediate (char *imm_start)
5608 char *save_input_line_pointer;
5609 char *gotfree_input_line;
5612 i386_operand_type types;
5614 UINTS_SET (types, ~0);
5616 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5618 as_bad (_("at most %d immediate operands are allowed"),
5619 MAX_IMMEDIATE_OPERANDS);
5623 exp = &im_expressions[i.imm_operands++];
5624 i.op[this_operand].imms = exp;
5626 if (is_space_char (*imm_start))
5629 save_input_line_pointer = input_line_pointer;
5630 input_line_pointer = imm_start;
5632 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5633 if (gotfree_input_line)
5634 input_line_pointer = gotfree_input_line;
5636 exp_seg = expression (exp);
5639 if (*input_line_pointer)
5640 as_bad (_("junk `%s' after expression"), input_line_pointer);
5642 input_line_pointer = save_input_line_pointer;
5643 if (gotfree_input_line)
5644 free (gotfree_input_line);
5646 if (exp->X_op == O_absent
5647 || exp->X_op == O_illegal
5648 || exp->X_op == O_big
5649 || (gotfree_input_line
5650 && (exp->X_op == O_constant
5651 || exp->X_op == O_register)))
5653 as_bad (_("missing or invalid immediate expression `%s'"),
5657 else if (exp->X_op == O_constant)
5659 /* Size it properly later. */
5660 i.types[this_operand].bitfield.imm64 = 1;
5661 /* If BFD64, sign extend val. */
5662 if (!use_rela_relocations
5663 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5665 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5667 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5668 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5669 && exp_seg != absolute_section
5670 && exp_seg != text_section
5671 && exp_seg != data_section
5672 && exp_seg != bss_section
5673 && exp_seg != undefined_section
5674 && !bfd_is_com_section (exp_seg))
5676 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5680 else if (!intel_syntax && exp->X_op == O_register)
5682 as_bad (_("illegal immediate register operand %s"), imm_start);
5687 /* This is an address. The size of the address will be
5688 determined later, depending on destination register,
5689 suffix, or the default for the section. */
5690 i.types[this_operand].bitfield.imm8 = 1;
5691 i.types[this_operand].bitfield.imm16 = 1;
5692 i.types[this_operand].bitfield.imm32 = 1;
5693 i.types[this_operand].bitfield.imm32s = 1;
5694 i.types[this_operand].bitfield.imm64 = 1;
5695 i.types[this_operand] = operand_type_and (i.types[this_operand],
5703 i386_scale (char *scale)
5706 char *save = input_line_pointer;
5708 input_line_pointer = scale;
5709 val = get_absolute_expression ();
5714 i.log2_scale_factor = 0;
5717 i.log2_scale_factor = 1;
5720 i.log2_scale_factor = 2;
5723 i.log2_scale_factor = 3;
5727 char sep = *input_line_pointer;
5729 *input_line_pointer = '\0';
5730 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5732 *input_line_pointer = sep;
5733 input_line_pointer = save;
5737 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5739 as_warn (_("scale factor of %d without an index register"),
5740 1 << i.log2_scale_factor);
5741 i.log2_scale_factor = 0;
5743 scale = input_line_pointer;
5744 input_line_pointer = save;
5749 i386_displacement (char *disp_start, char *disp_end)
5753 char *save_input_line_pointer;
5754 char *gotfree_input_line;
5756 i386_operand_type bigdisp, types = anydisp;
5759 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5761 as_bad (_("at most %d displacement operands are allowed"),
5762 MAX_MEMORY_OPERANDS);
5766 UINTS_CLEAR (bigdisp);
5767 if ((i.types[this_operand].bitfield.jumpabsolute)
5768 || (!current_templates->start->opcode_modifier.jump
5769 && !current_templates->start->opcode_modifier.jumpdword))
5771 bigdisp.bitfield.disp32 = 1;
5772 override = (i.prefix[ADDR_PREFIX] != 0);
5773 if (flag_code == CODE_64BIT)
5777 bigdisp.bitfield.disp32s = 1;
5778 bigdisp.bitfield.disp64 = 1;
5781 else if ((flag_code == CODE_16BIT) ^ override)
5783 bigdisp.bitfield.disp32 = 0;
5784 bigdisp.bitfield.disp16 = 1;
5789 /* For PC-relative branches, the width of the displacement
5790 is dependent upon data size, not address size. */
5791 override = (i.prefix[DATA_PREFIX] != 0);
5792 if (flag_code == CODE_64BIT)
5794 if (override || i.suffix == WORD_MNEM_SUFFIX)
5795 bigdisp.bitfield.disp16 = 1;
5798 bigdisp.bitfield.disp32 = 1;
5799 bigdisp.bitfield.disp32s = 1;
5805 override = (i.suffix == (flag_code != CODE_16BIT
5807 : LONG_MNEM_SUFFIX));
5808 bigdisp.bitfield.disp32 = 1;
5809 if ((flag_code == CODE_16BIT) ^ override)
5811 bigdisp.bitfield.disp32 = 0;
5812 bigdisp.bitfield.disp16 = 1;
5816 i.types[this_operand] = operand_type_or (i.types[this_operand],
5819 exp = &disp_expressions[i.disp_operands];
5820 i.op[this_operand].disps = exp;
5822 save_input_line_pointer = input_line_pointer;
5823 input_line_pointer = disp_start;
5824 END_STRING_AND_SAVE (disp_end);
5826 #ifndef GCC_ASM_O_HACK
5827 #define GCC_ASM_O_HACK 0
5830 END_STRING_AND_SAVE (disp_end + 1);
5831 if (i.types[this_operand].bitfield.baseIndex
5832 && displacement_string_end[-1] == '+')
5834 /* This hack is to avoid a warning when using the "o"
5835 constraint within gcc asm statements.
5838 #define _set_tssldt_desc(n,addr,limit,type) \
5839 __asm__ __volatile__ ( \
5841 "movw %w1,2+%0\n\t" \
5843 "movb %b1,4+%0\n\t" \
5844 "movb %4,5+%0\n\t" \
5845 "movb $0,6+%0\n\t" \
5846 "movb %h1,7+%0\n\t" \
5848 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5850 This works great except that the output assembler ends
5851 up looking a bit weird if it turns out that there is
5852 no offset. You end up producing code that looks like:
5865 So here we provide the missing zero. */
5867 *displacement_string_end = '0';
5870 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5871 if (gotfree_input_line)
5872 input_line_pointer = gotfree_input_line;
5874 exp_seg = expression (exp);
5877 if (*input_line_pointer)
5878 as_bad (_("junk `%s' after expression"), input_line_pointer);
5880 RESTORE_END_STRING (disp_end + 1);
5882 input_line_pointer = save_input_line_pointer;
5883 if (gotfree_input_line)
5884 free (gotfree_input_line);
5887 /* We do this to make sure that the section symbol is in
5888 the symbol table. We will ultimately change the relocation
5889 to be relative to the beginning of the section. */
5890 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5891 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5892 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5894 if (exp->X_op != O_symbol)
5897 if (S_IS_LOCAL (exp->X_add_symbol)
5898 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5899 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5900 exp->X_op = O_subtract;
5901 exp->X_op_symbol = GOT_symbol;
5902 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5903 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5904 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5905 i.reloc[this_operand] = BFD_RELOC_64;
5907 i.reloc[this_operand] = BFD_RELOC_32;
5910 else if (exp->X_op == O_absent
5911 || exp->X_op == O_illegal
5912 || exp->X_op == O_big
5913 || (gotfree_input_line
5914 && (exp->X_op == O_constant
5915 || exp->X_op == O_register)))
5918 as_bad (_("missing or invalid displacement expression `%s'"),
5923 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5924 else if (exp->X_op != O_constant
5925 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5926 && exp_seg != absolute_section
5927 && exp_seg != text_section
5928 && exp_seg != data_section
5929 && exp_seg != bss_section
5930 && exp_seg != undefined_section
5931 && !bfd_is_com_section (exp_seg))
5933 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5938 RESTORE_END_STRING (disp_end);
5940 /* Check if this is a displacement only operand. */
5941 bigdisp = i.types[this_operand];
5942 bigdisp.bitfield.disp8 = 0;
5943 bigdisp.bitfield.disp16 = 0;
5944 bigdisp.bitfield.disp32 = 0;
5945 bigdisp.bitfield.disp32s = 0;
5946 bigdisp.bitfield.disp64 = 0;
5947 if (UINTS_ALL_ZERO (bigdisp))
5948 i.types[this_operand] = operand_type_and (i.types[this_operand],
5954 /* Make sure the memory operand we've been dealt is valid.
5955 Return 1 on success, 0 on a failure. */
5958 i386_index_check (const char *operand_string)
5961 #if INFER_ADDR_PREFIX
5967 if (flag_code == CODE_64BIT)
5970 && ((i.prefix[ADDR_PREFIX] == 0
5971 && !i.base_reg->reg_type.bitfield.reg64)
5972 || (i.prefix[ADDR_PREFIX]
5973 && !i.base_reg->reg_type.bitfield.reg32))
5975 || i.base_reg->reg_num !=
5976 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
5978 && (!i.index_reg->reg_type.bitfield.baseindex
5979 || (i.prefix[ADDR_PREFIX] == 0
5980 && i.index_reg->reg_num != RegRiz
5981 && !i.index_reg->reg_type.bitfield.reg64
5983 || (i.prefix[ADDR_PREFIX]
5984 && i.index_reg->reg_num != RegEiz
5985 && !i.index_reg->reg_type.bitfield.reg32))))
5990 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5994 && (!i.base_reg->reg_type.bitfield.reg16
5995 || !i.base_reg->reg_type.bitfield.baseindex))
5997 && (!i.index_reg->reg_type.bitfield.reg16
5998 || !i.index_reg->reg_type.bitfield.baseindex
6000 && i.base_reg->reg_num < 6
6001 && i.index_reg->reg_num >= 6
6002 && i.log2_scale_factor == 0))))
6009 && !i.base_reg->reg_type.bitfield.reg32)
6011 && ((!i.index_reg->reg_type.bitfield.reg32
6012 && i.index_reg->reg_num != RegEiz)
6013 || !i.index_reg->reg_type.bitfield.baseindex)))
6019 #if INFER_ADDR_PREFIX
6020 if (i.prefix[ADDR_PREFIX] == 0)
6022 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6024 /* Change the size of any displacement too. At most one of
6025 Disp16 or Disp32 is set.
6026 FIXME. There doesn't seem to be any real need for separate
6027 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6028 Removing them would probably clean up the code quite a lot. */
6029 if (flag_code != CODE_64BIT
6030 && (i.types[this_operand].bitfield.disp16
6031 || i.types[this_operand].bitfield.disp32))
6032 i.types[this_operand]
6033 = operand_type_xor (i.types[this_operand], disp16_32);
6038 as_bad (_("`%s' is not a valid base/index expression"),
6042 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6044 flag_code_names[flag_code]);
6049 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6053 i386_att_operand (char *operand_string)
6057 char *op_string = operand_string;
6059 if (is_space_char (*op_string))
6062 /* We check for an absolute prefix (differentiating,
6063 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6064 if (*op_string == ABSOLUTE_PREFIX)
6067 if (is_space_char (*op_string))
6069 i.types[this_operand].bitfield.jumpabsolute = 1;
6072 /* Check if operand is a register. */
6073 if ((r = parse_register (op_string, &end_op)) != NULL)
6075 i386_operand_type temp;
6077 /* Check for a segment override by searching for ':' after a
6078 segment register. */
6080 if (is_space_char (*op_string))
6082 if (*op_string == ':'
6083 && (r->reg_type.bitfield.sreg2
6084 || r->reg_type.bitfield.sreg3))
6089 i.seg[i.mem_operands] = &es;
6092 i.seg[i.mem_operands] = &cs;
6095 i.seg[i.mem_operands] = &ss;
6098 i.seg[i.mem_operands] = &ds;
6101 i.seg[i.mem_operands] = &fs;
6104 i.seg[i.mem_operands] = &gs;
6108 /* Skip the ':' and whitespace. */
6110 if (is_space_char (*op_string))
6113 if (!is_digit_char (*op_string)
6114 && !is_identifier_char (*op_string)
6115 && *op_string != '('
6116 && *op_string != ABSOLUTE_PREFIX)
6118 as_bad (_("bad memory operand `%s'"), op_string);
6121 /* Handle case of %es:*foo. */
6122 if (*op_string == ABSOLUTE_PREFIX)
6125 if (is_space_char (*op_string))
6127 i.types[this_operand].bitfield.jumpabsolute = 1;
6129 goto do_memory_reference;
6133 as_bad (_("junk `%s' after register"), op_string);
6137 temp.bitfield.baseindex = 0;
6138 i.types[this_operand] = operand_type_or (i.types[this_operand],
6140 i.op[this_operand].regs = r;
6143 else if (*op_string == REGISTER_PREFIX)
6145 as_bad (_("bad register name `%s'"), op_string);
6148 else if (*op_string == IMMEDIATE_PREFIX)
6151 if (i.types[this_operand].bitfield.jumpabsolute)
6153 as_bad (_("immediate operand illegal with absolute jump"));
6156 if (!i386_immediate (op_string))
6159 else if (is_digit_char (*op_string)
6160 || is_identifier_char (*op_string)
6161 || *op_string == '(')
6163 /* This is a memory reference of some sort. */
6166 /* Start and end of displacement string expression (if found). */
6167 char *displacement_string_start;
6168 char *displacement_string_end;
6170 do_memory_reference:
6171 if ((i.mem_operands == 1
6172 && !current_templates->start->opcode_modifier.isstring)
6173 || i.mem_operands == 2)
6175 as_bad (_("too many memory references for `%s'"),
6176 current_templates->start->name);
6180 /* Check for base index form. We detect the base index form by
6181 looking for an ')' at the end of the operand, searching
6182 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6184 base_string = op_string + strlen (op_string);
6187 if (is_space_char (*base_string))
6190 /* If we only have a displacement, set-up for it to be parsed later. */
6191 displacement_string_start = op_string;
6192 displacement_string_end = base_string + 1;
6194 if (*base_string == ')')
6197 unsigned int parens_balanced = 1;
6198 /* We've already checked that the number of left & right ()'s are
6199 equal, so this loop will not be infinite. */
6203 if (*base_string == ')')
6205 if (*base_string == '(')
6208 while (parens_balanced);
6210 temp_string = base_string;
6212 /* Skip past '(' and whitespace. */
6214 if (is_space_char (*base_string))
6217 if (*base_string == ','
6218 || ((i.base_reg = parse_register (base_string, &end_op))
6221 displacement_string_end = temp_string;
6223 i.types[this_operand].bitfield.baseindex = 1;
6227 base_string = end_op;
6228 if (is_space_char (*base_string))
6232 /* There may be an index reg or scale factor here. */
6233 if (*base_string == ',')
6236 if (is_space_char (*base_string))
6239 if ((i.index_reg = parse_register (base_string, &end_op))
6242 base_string = end_op;
6243 if (is_space_char (*base_string))
6245 if (*base_string == ',')
6248 if (is_space_char (*base_string))
6251 else if (*base_string != ')')
6253 as_bad (_("expecting `,' or `)' "
6254 "after index register in `%s'"),
6259 else if (*base_string == REGISTER_PREFIX)
6261 as_bad (_("bad register name `%s'"), base_string);
6265 /* Check for scale factor. */
6266 if (*base_string != ')')
6268 char *end_scale = i386_scale (base_string);
6273 base_string = end_scale;
6274 if (is_space_char (*base_string))
6276 if (*base_string != ')')
6278 as_bad (_("expecting `)' "
6279 "after scale factor in `%s'"),
6284 else if (!i.index_reg)
6286 as_bad (_("expecting index register or scale factor "
6287 "after `,'; got '%c'"),
6292 else if (*base_string != ')')
6294 as_bad (_("expecting `,' or `)' "
6295 "after base register in `%s'"),
6300 else if (*base_string == REGISTER_PREFIX)
6302 as_bad (_("bad register name `%s'"), base_string);
6307 /* If there's an expression beginning the operand, parse it,
6308 assuming displacement_string_start and
6309 displacement_string_end are meaningful. */
6310 if (displacement_string_start != displacement_string_end)
6312 if (!i386_displacement (displacement_string_start,
6313 displacement_string_end))
6317 /* Special case for (%dx) while doing input/output op. */
6319 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6321 && i.log2_scale_factor == 0
6322 && i.seg[i.mem_operands] == 0
6323 && !operand_type_check (i.types[this_operand], disp))
6325 UINTS_CLEAR (i.types[this_operand]);
6326 i.types[this_operand].bitfield.inoutportreg = 1;
6330 if (i386_index_check (operand_string) == 0)
6336 /* It's not a memory operand; argh! */
6337 as_bad (_("invalid char %s beginning operand %d `%s'"),
6338 output_invalid (*op_string),
6343 return 1; /* Normal return. */
6346 /* md_estimate_size_before_relax()
6348 Called just before relax() for rs_machine_dependent frags. The x86
6349 assembler uses these frags to handle variable size jump
6352 Any symbol that is now undefined will not become defined.
6353 Return the correct fr_subtype in the frag.
6354 Return the initial "guess for variable size of frag" to caller.
6355 The guess is actually the growth beyond the fixed part. Whatever
6356 we do to grow the fixed or variable part contributes to our
6360 md_estimate_size_before_relax (fragP, segment)
6364 /* We've already got fragP->fr_subtype right; all we have to do is
6365 check for un-relaxable symbols. On an ELF system, we can't relax
6366 an externally visible symbol, because it may be overridden by a
6368 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6371 && (S_IS_EXTERNAL (fragP->fr_symbol)
6372 || S_IS_WEAK (fragP->fr_symbol)))
6376 /* Symbol is undefined in this segment, or we need to keep a
6377 reloc so that weak symbols can be overridden. */
6378 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6379 enum bfd_reloc_code_real reloc_type;
6380 unsigned char *opcode;
6383 if (fragP->fr_var != NO_RELOC)
6384 reloc_type = fragP->fr_var;
6386 reloc_type = BFD_RELOC_16_PCREL;
6388 reloc_type = BFD_RELOC_32_PCREL;
6390 old_fr_fix = fragP->fr_fix;
6391 opcode = (unsigned char *) fragP->fr_opcode;
6393 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6396 /* Make jmp (0xeb) a (d)word displacement jump. */
6398 fragP->fr_fix += size;
6399 fix_new (fragP, old_fr_fix, size,
6401 fragP->fr_offset, 1,
6407 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6409 /* Negate the condition, and branch past an
6410 unconditional jump. */
6413 /* Insert an unconditional jump. */
6415 /* We added two extra opcode bytes, and have a two byte
6417 fragP->fr_fix += 2 + 2;
6418 fix_new (fragP, old_fr_fix + 2, 2,
6420 fragP->fr_offset, 1,
6427 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6432 fixP = fix_new (fragP, old_fr_fix, 1,
6434 fragP->fr_offset, 1,
6436 fixP->fx_signed = 1;
6440 /* This changes the byte-displacement jump 0x7N
6441 to the (d)word-displacement jump 0x0f,0x8N. */
6442 opcode[1] = opcode[0] + 0x10;
6443 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6444 /* We've added an opcode byte. */
6445 fragP->fr_fix += 1 + size;
6446 fix_new (fragP, old_fr_fix + 1, size,
6448 fragP->fr_offset, 1,
6453 BAD_CASE (fragP->fr_subtype);
6457 return fragP->fr_fix - old_fr_fix;
6460 /* Guess size depending on current relax state. Initially the relax
6461 state will correspond to a short jump and we return 1, because
6462 the variable part of the frag (the branch offset) is one byte
6463 long. However, we can relax a section more than once and in that
6464 case we must either set fr_subtype back to the unrelaxed state,
6465 or return the value for the appropriate branch. */
6466 return md_relax_table[fragP->fr_subtype].rlx_length;
6469 /* Called after relax() is finished.
6471 In: Address of frag.
6472 fr_type == rs_machine_dependent.
6473 fr_subtype is what the address relaxed to.
6475 Out: Any fixSs and constants are set up.
6476 Caller will turn frag into a ".space 0". */
6479 md_convert_frag (abfd, sec, fragP)
6480 bfd *abfd ATTRIBUTE_UNUSED;
6481 segT sec ATTRIBUTE_UNUSED;
6484 unsigned char *opcode;
6485 unsigned char *where_to_put_displacement = NULL;
6486 offsetT target_address;
6487 offsetT opcode_address;
6488 unsigned int extension = 0;
6489 offsetT displacement_from_opcode_start;
6491 opcode = (unsigned char *) fragP->fr_opcode;
6493 /* Address we want to reach in file space. */
6494 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6496 /* Address opcode resides at in file space. */
6497 opcode_address = fragP->fr_address + fragP->fr_fix;
6499 /* Displacement from opcode start to fill into instruction. */
6500 displacement_from_opcode_start = target_address - opcode_address;
6502 if ((fragP->fr_subtype & BIG) == 0)
6504 /* Don't have to change opcode. */
6505 extension = 1; /* 1 opcode + 1 displacement */
6506 where_to_put_displacement = &opcode[1];
6510 if (no_cond_jump_promotion
6511 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6512 as_warn_where (fragP->fr_file, fragP->fr_line,
6513 _("long jump required"));
6515 switch (fragP->fr_subtype)
6517 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6518 extension = 4; /* 1 opcode + 4 displacement */
6520 where_to_put_displacement = &opcode[1];
6523 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6524 extension = 2; /* 1 opcode + 2 displacement */
6526 where_to_put_displacement = &opcode[1];
6529 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6530 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6531 extension = 5; /* 2 opcode + 4 displacement */
6532 opcode[1] = opcode[0] + 0x10;
6533 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6534 where_to_put_displacement = &opcode[2];
6537 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6538 extension = 3; /* 2 opcode + 2 displacement */
6539 opcode[1] = opcode[0] + 0x10;
6540 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6541 where_to_put_displacement = &opcode[2];
6544 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6549 where_to_put_displacement = &opcode[3];
6553 BAD_CASE (fragP->fr_subtype);
6558 /* If size if less then four we are sure that the operand fits,
6559 but if it's 4, then it could be that the displacement is larger
6561 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6563 && ((addressT) (displacement_from_opcode_start - extension
6564 + ((addressT) 1 << 31))
6565 > (((addressT) 2 << 31) - 1)))
6567 as_bad_where (fragP->fr_file, fragP->fr_line,
6568 _("jump target out of range"));
6569 /* Make us emit 0. */
6570 displacement_from_opcode_start = extension;
6572 /* Now put displacement after opcode. */
6573 md_number_to_chars ((char *) where_to_put_displacement,
6574 (valueT) (displacement_from_opcode_start - extension),
6575 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6576 fragP->fr_fix += extension;
6579 /* Apply a fixup (fixS) to segment data, once it has been determined
6580 by our caller that we have all the info we need to fix it up.
6582 On the 386, immediates, displacements, and data pointers are all in
6583 the same (little-endian) format, so we don't need to care about which
6587 md_apply_fix (fixP, valP, seg)
6588 /* The fix we're to put in. */
6590 /* Pointer to the value of the bits. */
6592 /* Segment fix is from. */
6593 segT seg ATTRIBUTE_UNUSED;
6595 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6596 valueT value = *valP;
6598 #if !defined (TE_Mach)
6601 switch (fixP->fx_r_type)
6607 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6610 case BFD_RELOC_X86_64_32S:
6611 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6614 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6617 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6622 if (fixP->fx_addsy != NULL
6623 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6624 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6625 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6626 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6627 && !use_rela_relocations)
6629 /* This is a hack. There should be a better way to handle this.
6630 This covers for the fact that bfd_install_relocation will
6631 subtract the current location (for partial_inplace, PC relative
6632 relocations); see more below. */
6636 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6639 value += fixP->fx_where + fixP->fx_frag->fr_address;
6641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6644 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6647 || (symbol_section_p (fixP->fx_addsy)
6648 && sym_seg != absolute_section))
6649 && !generic_force_reloc (fixP))
6651 /* Yes, we add the values in twice. This is because
6652 bfd_install_relocation subtracts them out again. I think
6653 bfd_install_relocation is broken, but I don't dare change
6655 value += fixP->fx_where + fixP->fx_frag->fr_address;
6659 #if defined (OBJ_COFF) && defined (TE_PE)
6660 /* For some reason, the PE format does not store a
6661 section address offset for a PC relative symbol. */
6662 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6663 || S_IS_WEAK (fixP->fx_addsy))
6664 value += md_pcrel_from (fixP);
6668 /* Fix a few things - the dynamic linker expects certain values here,
6669 and we must not disappoint it. */
6670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6671 if (IS_ELF && fixP->fx_addsy)
6672 switch (fixP->fx_r_type)
6674 case BFD_RELOC_386_PLT32:
6675 case BFD_RELOC_X86_64_PLT32:
6676 /* Make the jump instruction point to the address of the operand. At
6677 runtime we merely add the offset to the actual PLT entry. */
6681 case BFD_RELOC_386_TLS_GD:
6682 case BFD_RELOC_386_TLS_LDM:
6683 case BFD_RELOC_386_TLS_IE_32:
6684 case BFD_RELOC_386_TLS_IE:
6685 case BFD_RELOC_386_TLS_GOTIE:
6686 case BFD_RELOC_386_TLS_GOTDESC:
6687 case BFD_RELOC_X86_64_TLSGD:
6688 case BFD_RELOC_X86_64_TLSLD:
6689 case BFD_RELOC_X86_64_GOTTPOFF:
6690 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6691 value = 0; /* Fully resolved at runtime. No addend. */
6693 case BFD_RELOC_386_TLS_LE:
6694 case BFD_RELOC_386_TLS_LDO_32:
6695 case BFD_RELOC_386_TLS_LE_32:
6696 case BFD_RELOC_X86_64_DTPOFF32:
6697 case BFD_RELOC_X86_64_DTPOFF64:
6698 case BFD_RELOC_X86_64_TPOFF32:
6699 case BFD_RELOC_X86_64_TPOFF64:
6700 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6703 case BFD_RELOC_386_TLS_DESC_CALL:
6704 case BFD_RELOC_X86_64_TLSDESC_CALL:
6705 value = 0; /* Fully resolved at runtime. No addend. */
6706 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6710 case BFD_RELOC_386_GOT32:
6711 case BFD_RELOC_X86_64_GOT32:
6712 value = 0; /* Fully resolved at runtime. No addend. */
6715 case BFD_RELOC_VTABLE_INHERIT:
6716 case BFD_RELOC_VTABLE_ENTRY:
6723 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6725 #endif /* !defined (TE_Mach) */
6727 /* Are we finished with this relocation now? */
6728 if (fixP->fx_addsy == NULL)
6730 else if (use_rela_relocations)
6732 fixP->fx_no_overflow = 1;
6733 /* Remember value for tc_gen_reloc. */
6734 fixP->fx_addnumber = value;
6738 md_number_to_chars (p, value, fixP->fx_size);
6742 md_atof (int type, char *litP, int *sizeP)
6744 /* This outputs the LITTLENUMs in REVERSE order;
6745 in accord with the bigendian 386. */
6746 return ieee_md_atof (type, litP, sizeP, FALSE);
6749 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6752 output_invalid (int c)
6755 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6758 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6759 "(0x%x)", (unsigned char) c);
6760 return output_invalid_buf;
6763 /* REG_STRING starts *before* REGISTER_PREFIX. */
6765 static const reg_entry *
6766 parse_real_register (char *reg_string, char **end_op)
6768 char *s = reg_string;
6770 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6773 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6774 if (*s == REGISTER_PREFIX)
6777 if (is_space_char (*s))
6781 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6783 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6784 return (const reg_entry *) NULL;
6788 /* For naked regs, make sure that we are not dealing with an identifier.
6789 This prevents confusing an identifier like `eax_var' with register
6791 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6792 return (const reg_entry *) NULL;
6796 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6798 /* Handle floating point regs, allowing spaces in the (i) part. */
6799 if (r == i386_regtab /* %st is first entry of table */)
6801 if (is_space_char (*s))
6806 if (is_space_char (*s))
6808 if (*s >= '0' && *s <= '7')
6812 if (is_space_char (*s))
6817 r = hash_find (reg_hash, "st(0)");
6822 /* We have "%st(" then garbage. */
6823 return (const reg_entry *) NULL;
6827 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6830 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6831 return (const reg_entry *) NULL;
6834 && ((r->reg_flags & (RegRex64 | RegRex))
6835 || r->reg_type.bitfield.reg64)
6836 && (!cpu_arch_flags.bitfield.cpulm
6837 || !UINTS_EQUAL (r->reg_type, control))
6838 && flag_code != CODE_64BIT)
6839 return (const reg_entry *) NULL;
6844 /* REG_STRING starts *before* REGISTER_PREFIX. */
6846 static const reg_entry *
6847 parse_register (char *reg_string, char **end_op)
6851 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6852 r = parse_real_register (reg_string, end_op);
6857 char *save = input_line_pointer;
6861 input_line_pointer = reg_string;
6862 c = get_symbol_end ();
6863 symbolP = symbol_find (reg_string);
6864 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6866 const expressionS *e = symbol_get_value_expression (symbolP);
6868 know (e->X_op == O_register);
6869 know (e->X_add_number >= 0
6870 && (valueT) e->X_add_number < i386_regtab_size);
6871 r = i386_regtab + e->X_add_number;
6872 *end_op = input_line_pointer;
6874 *input_line_pointer = c;
6875 input_line_pointer = save;
6881 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6884 char *end = input_line_pointer;
6887 r = parse_register (name, &input_line_pointer);
6888 if (r && end <= input_line_pointer)
6890 *nextcharP = *input_line_pointer;
6891 *input_line_pointer = 0;
6892 e->X_op = O_register;
6893 e->X_add_number = r - i386_regtab;
6896 input_line_pointer = end;
6902 md_operand (expressionS *e)
6904 if (*input_line_pointer == REGISTER_PREFIX)
6907 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6911 e->X_op = O_register;
6912 e->X_add_number = r - i386_regtab;
6913 input_line_pointer = end;
6919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6920 const char *md_shortopts = "kVQ:sqn";
6922 const char *md_shortopts = "qn";
6925 #define OPTION_32 (OPTION_MD_BASE + 0)
6926 #define OPTION_64 (OPTION_MD_BASE + 1)
6927 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6928 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6929 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6930 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6931 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6932 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6933 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6934 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
6936 struct option md_longopts[] =
6938 {"32", no_argument, NULL, OPTION_32},
6939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6940 {"64", no_argument, NULL, OPTION_64},
6942 {"divide", no_argument, NULL, OPTION_DIVIDE},
6943 {"march", required_argument, NULL, OPTION_MARCH},
6944 {"mtune", required_argument, NULL, OPTION_MTUNE},
6945 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6946 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6947 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6948 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6949 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
6950 {NULL, no_argument, NULL, 0}
6952 size_t md_longopts_size = sizeof (md_longopts);
6955 md_parse_option (int c, char *arg)
6962 optimize_align_code = 0;
6969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6970 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6971 should be emitted or not. FIXME: Not implemented. */
6975 /* -V: SVR4 argument to print version ID. */
6977 print_version_id ();
6980 /* -k: Ignore for FreeBSD compatibility. */
6985 /* -s: On i386 Solaris, this tells the native assembler to use
6986 .stab instead of .stab.excl. We always use .stab anyhow. */
6989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6992 const char **list, **l;
6994 list = bfd_target_list ();
6995 for (l = list; *l != NULL; l++)
6996 if (CONST_STRNEQ (*l, "elf64-x86-64")
6997 || strcmp (*l, "coff-x86-64") == 0
6998 || strcmp (*l, "pe-x86-64") == 0
6999 || strcmp (*l, "pei-x86-64") == 0)
7001 default_arch = "x86_64";
7005 as_fatal (_("No compiled in support for x86_64"));
7012 default_arch = "i386";
7016 #ifdef SVR4_COMMENT_CHARS
7021 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7023 for (s = i386_comment_chars; *s != '\0'; s++)
7027 i386_comment_chars = n;
7034 as_fatal (_("Invalid -march= option: `%s'"), arg);
7035 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7037 if (strcmp (arg, cpu_arch [i].name) == 0)
7039 cpu_arch_isa = cpu_arch[i].type;
7040 cpu_arch_isa_flags = cpu_arch[i].flags;
7041 if (!cpu_arch_tune_set)
7043 cpu_arch_tune = cpu_arch_isa;
7044 cpu_arch_tune_flags = cpu_arch_isa_flags;
7049 if (i >= ARRAY_SIZE (cpu_arch))
7050 as_fatal (_("Invalid -march= option: `%s'"), arg);
7055 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7056 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7058 if (strcmp (arg, cpu_arch [i].name) == 0)
7060 cpu_arch_tune_set = 1;
7061 cpu_arch_tune = cpu_arch [i].type;
7062 cpu_arch_tune_flags = cpu_arch[i].flags;
7066 if (i >= ARRAY_SIZE (cpu_arch))
7067 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7070 case OPTION_MMNEMONIC:
7071 if (strcasecmp (arg, "att") == 0)
7073 else if (strcasecmp (arg, "intel") == 0)
7076 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7079 case OPTION_MSYNTAX:
7080 if (strcasecmp (arg, "att") == 0)
7082 else if (strcasecmp (arg, "intel") == 0)
7085 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7088 case OPTION_MINDEX_REG:
7089 allow_index_reg = 1;
7092 case OPTION_MNAKED_REG:
7093 allow_naked_reg = 1;
7096 case OPTION_MOLD_GCC:
7107 md_show_usage (stream)
7110 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7111 fprintf (stream, _("\
7113 -V print assembler version number\n\
7116 fprintf (stream, _("\
7117 -n Do not optimize code alignment\n\
7118 -q quieten some warnings\n"));
7119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7120 fprintf (stream, _("\
7123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7124 fprintf (stream, _("\
7125 --32/--64 generate 32bit/64bit code\n"));
7127 #ifdef SVR4_COMMENT_CHARS
7128 fprintf (stream, _("\
7129 --divide do not treat `/' as a comment character\n"));
7131 fprintf (stream, _("\
7132 --divide ignored\n"));
7134 fprintf (stream, _("\
7135 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7136 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7137 core, core2, k6, athlon, k8, generic32, generic64\n"));
7138 fprintf (stream, _("\
7139 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7140 fprintf (stream, _("\
7141 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7142 fprintf (stream, _("\
7143 -mindex-reg support pseudo index registers\n"));
7144 fprintf (stream, _("\
7145 -mnaked-reg don't require `%%' prefix for registers\n"));
7146 fprintf (stream, _("\
7147 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7150 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7151 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7153 /* Pick the target format to use. */
7156 i386_target_format (void)
7158 if (!strcmp (default_arch, "x86_64"))
7160 set_code_flag (CODE_64BIT);
7161 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7163 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7164 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7165 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7166 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7167 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7168 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7169 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7170 cpu_arch_isa_flags.bitfield.cpummx= 1;
7171 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7172 cpu_arch_isa_flags.bitfield.cpusse = 1;
7173 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7175 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7177 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7178 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7179 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7180 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7181 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7182 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7183 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7184 cpu_arch_tune_flags.bitfield.cpummx= 1;
7185 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7186 cpu_arch_tune_flags.bitfield.cpusse = 1;
7187 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7190 else if (!strcmp (default_arch, "i386"))
7192 set_code_flag (CODE_32BIT);
7193 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7195 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7196 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7197 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7199 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7201 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7202 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7203 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7207 as_fatal (_("Unknown architecture"));
7208 switch (OUTPUT_FLAVOR)
7211 case bfd_target_coff_flavour:
7212 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7215 #ifdef OBJ_MAYBE_AOUT
7216 case bfd_target_aout_flavour:
7217 return AOUT_TARGET_FORMAT;
7219 #ifdef OBJ_MAYBE_COFF
7220 case bfd_target_coff_flavour:
7223 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7224 case bfd_target_elf_flavour:
7226 if (flag_code == CODE_64BIT)
7229 use_rela_relocations = 1;
7231 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7240 #endif /* OBJ_MAYBE_ more than one */
7242 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7244 i386_elf_emit_arch_note (void)
7246 if (IS_ELF && cpu_arch_name != NULL)
7249 asection *seg = now_seg;
7250 subsegT subseg = now_subseg;
7251 Elf_Internal_Note i_note;
7252 Elf_External_Note e_note;
7253 asection *note_secp;
7256 /* Create the .note section. */
7257 note_secp = subseg_new (".note", 0);
7258 bfd_set_section_flags (stdoutput,
7260 SEC_HAS_CONTENTS | SEC_READONLY);
7262 /* Process the arch string. */
7263 len = strlen (cpu_arch_name);
7265 i_note.namesz = len + 1;
7267 i_note.type = NT_ARCH;
7268 p = frag_more (sizeof (e_note.namesz));
7269 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7270 p = frag_more (sizeof (e_note.descsz));
7271 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7272 p = frag_more (sizeof (e_note.type));
7273 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7274 p = frag_more (len + 1);
7275 strcpy (p, cpu_arch_name);
7277 frag_align (2, 0, 0);
7279 subseg_set (seg, subseg);
7285 md_undefined_symbol (name)
7288 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7289 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7290 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7291 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7295 if (symbol_find (name))
7296 as_bad (_("GOT already in symbol table"));
7297 GOT_symbol = symbol_new (name, undefined_section,
7298 (valueT) 0, &zero_address_frag);
7305 /* Round up a section size to the appropriate boundary. */
7308 md_section_align (segment, size)
7309 segT segment ATTRIBUTE_UNUSED;
7312 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7313 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7315 /* For a.out, force the section size to be aligned. If we don't do
7316 this, BFD will align it for us, but it will not write out the
7317 final bytes of the section. This may be a bug in BFD, but it is
7318 easier to fix it here since that is how the other a.out targets
7322 align = bfd_get_section_alignment (stdoutput, segment);
7323 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7330 /* On the i386, PC-relative offsets are relative to the start of the
7331 next instruction. That is, the address of the offset, plus its
7332 size, since the offset is always the last part of the insn. */
7335 md_pcrel_from (fixS *fixP)
7337 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7343 s_bss (int ignore ATTRIBUTE_UNUSED)
7347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7349 obj_elf_section_change_hook ();
7351 temp = get_absolute_expression ();
7352 subseg_set (bss_section, (subsegT) temp);
7353 demand_empty_rest_of_line ();
7359 i386_validate_fix (fixS *fixp)
7361 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7363 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7367 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7372 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7374 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7381 tc_gen_reloc (section, fixp)
7382 asection *section ATTRIBUTE_UNUSED;
7386 bfd_reloc_code_real_type code;
7388 switch (fixp->fx_r_type)
7390 case BFD_RELOC_X86_64_PLT32:
7391 case BFD_RELOC_X86_64_GOT32:
7392 case BFD_RELOC_X86_64_GOTPCREL:
7393 case BFD_RELOC_386_PLT32:
7394 case BFD_RELOC_386_GOT32:
7395 case BFD_RELOC_386_GOTOFF:
7396 case BFD_RELOC_386_GOTPC:
7397 case BFD_RELOC_386_TLS_GD:
7398 case BFD_RELOC_386_TLS_LDM:
7399 case BFD_RELOC_386_TLS_LDO_32:
7400 case BFD_RELOC_386_TLS_IE_32:
7401 case BFD_RELOC_386_TLS_IE:
7402 case BFD_RELOC_386_TLS_GOTIE:
7403 case BFD_RELOC_386_TLS_LE_32:
7404 case BFD_RELOC_386_TLS_LE:
7405 case BFD_RELOC_386_TLS_GOTDESC:
7406 case BFD_RELOC_386_TLS_DESC_CALL:
7407 case BFD_RELOC_X86_64_TLSGD:
7408 case BFD_RELOC_X86_64_TLSLD:
7409 case BFD_RELOC_X86_64_DTPOFF32:
7410 case BFD_RELOC_X86_64_DTPOFF64:
7411 case BFD_RELOC_X86_64_GOTTPOFF:
7412 case BFD_RELOC_X86_64_TPOFF32:
7413 case BFD_RELOC_X86_64_TPOFF64:
7414 case BFD_RELOC_X86_64_GOTOFF64:
7415 case BFD_RELOC_X86_64_GOTPC32:
7416 case BFD_RELOC_X86_64_GOT64:
7417 case BFD_RELOC_X86_64_GOTPCREL64:
7418 case BFD_RELOC_X86_64_GOTPC64:
7419 case BFD_RELOC_X86_64_GOTPLT64:
7420 case BFD_RELOC_X86_64_PLTOFF64:
7421 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7422 case BFD_RELOC_X86_64_TLSDESC_CALL:
7424 case BFD_RELOC_VTABLE_ENTRY:
7425 case BFD_RELOC_VTABLE_INHERIT:
7427 case BFD_RELOC_32_SECREL:
7429 code = fixp->fx_r_type;
7431 case BFD_RELOC_X86_64_32S:
7432 if (!fixp->fx_pcrel)
7434 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7435 code = fixp->fx_r_type;
7441 switch (fixp->fx_size)
7444 as_bad_where (fixp->fx_file, fixp->fx_line,
7445 _("can not do %d byte pc-relative relocation"),
7447 code = BFD_RELOC_32_PCREL;
7449 case 1: code = BFD_RELOC_8_PCREL; break;
7450 case 2: code = BFD_RELOC_16_PCREL; break;
7451 case 4: code = BFD_RELOC_32_PCREL; break;
7453 case 8: code = BFD_RELOC_64_PCREL; break;
7459 switch (fixp->fx_size)
7462 as_bad_where (fixp->fx_file, fixp->fx_line,
7463 _("can not do %d byte relocation"),
7465 code = BFD_RELOC_32;
7467 case 1: code = BFD_RELOC_8; break;
7468 case 2: code = BFD_RELOC_16; break;
7469 case 4: code = BFD_RELOC_32; break;
7471 case 8: code = BFD_RELOC_64; break;
7478 if ((code == BFD_RELOC_32
7479 || code == BFD_RELOC_32_PCREL
7480 || code == BFD_RELOC_X86_64_32S)
7482 && fixp->fx_addsy == GOT_symbol)
7485 code = BFD_RELOC_386_GOTPC;
7487 code = BFD_RELOC_X86_64_GOTPC32;
7489 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7491 && fixp->fx_addsy == GOT_symbol)
7493 code = BFD_RELOC_X86_64_GOTPC64;
7496 rel = (arelent *) xmalloc (sizeof (arelent));
7497 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7498 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7500 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7502 if (!use_rela_relocations)
7504 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7505 vtable entry to be used in the relocation's section offset. */
7506 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7507 rel->address = fixp->fx_offset;
7511 /* Use the rela in 64bit mode. */
7514 if (!fixp->fx_pcrel)
7515 rel->addend = fixp->fx_offset;
7519 case BFD_RELOC_X86_64_PLT32:
7520 case BFD_RELOC_X86_64_GOT32:
7521 case BFD_RELOC_X86_64_GOTPCREL:
7522 case BFD_RELOC_X86_64_TLSGD:
7523 case BFD_RELOC_X86_64_TLSLD:
7524 case BFD_RELOC_X86_64_GOTTPOFF:
7525 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7526 case BFD_RELOC_X86_64_TLSDESC_CALL:
7527 rel->addend = fixp->fx_offset - fixp->fx_size;
7530 rel->addend = (section->vma
7532 + fixp->fx_addnumber
7533 + md_pcrel_from (fixp));
7538 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7539 if (rel->howto == NULL)
7541 as_bad_where (fixp->fx_file, fixp->fx_line,
7542 _("cannot represent relocation type %s"),
7543 bfd_get_reloc_code_name (code));
7544 /* Set howto to a garbage value so that we can keep going. */
7545 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7546 assert (rel->howto != NULL);
7553 /* Parse operands using Intel syntax. This implements a recursive descent
7554 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7557 FIXME: We do not recognize the full operand grammar defined in the MASM
7558 documentation. In particular, all the structure/union and
7559 high-level macro operands are missing.
7561 Uppercase words are terminals, lower case words are non-terminals.
7562 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7563 bars '|' denote choices. Most grammar productions are implemented in
7564 functions called 'intel_<production>'.
7566 Initial production is 'expr'.
7572 binOp & | AND | \| | OR | ^ | XOR
7574 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7576 constant digits [[ radixOverride ]]
7578 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7616 => expr expr cmpOp e04
7619 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7620 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7622 hexdigit a | b | c | d | e | f
7623 | A | B | C | D | E | F
7629 mulOp * | / | % | MOD | << | SHL | >> | SHR
7633 register specialRegister
7637 segmentRegister CS | DS | ES | FS | GS | SS
7639 specialRegister CR0 | CR2 | CR3 | CR4
7640 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7641 | TR3 | TR4 | TR5 | TR6 | TR7
7643 We simplify the grammar in obvious places (e.g., register parsing is
7644 done by calling parse_register) and eliminate immediate left recursion
7645 to implement a recursive-descent parser.
7649 expr' cmpOp e04 expr'
7700 /* Parsing structure for the intel syntax parser. Used to implement the
7701 semantic actions for the operand grammar. */
7702 struct intel_parser_s
7704 char *op_string; /* The string being parsed. */
7705 int got_a_float; /* Whether the operand is a float. */
7706 int op_modifier; /* Operand modifier. */
7707 int is_mem; /* 1 if operand is memory reference. */
7708 int in_offset; /* >=1 if parsing operand of offset. */
7709 int in_bracket; /* >=1 if parsing operand in brackets. */
7710 const reg_entry *reg; /* Last register reference found. */
7711 char *disp; /* Displacement string being built. */
7712 char *next_operand; /* Resume point when splitting operands. */
7715 static struct intel_parser_s intel_parser;
7717 /* Token structure for parsing intel syntax. */
7720 int code; /* Token code. */
7721 const reg_entry *reg; /* Register entry for register tokens. */
7722 char *str; /* String representation. */
7725 static struct intel_token cur_token, prev_token;
7727 /* Token codes for the intel parser. Since T_SHORT is already used
7728 by COFF, undefine it first to prevent a warning. */
7747 /* Prototypes for intel parser functions. */
7748 static int intel_match_token (int);
7749 static void intel_putback_token (void);
7750 static void intel_get_token (void);
7751 static int intel_expr (void);
7752 static int intel_e04 (void);
7753 static int intel_e05 (void);
7754 static int intel_e06 (void);
7755 static int intel_e09 (void);
7756 static int intel_e10 (void);
7757 static int intel_e11 (void);
7760 i386_intel_operand (char *operand_string, int got_a_float)
7765 p = intel_parser.op_string = xstrdup (operand_string);
7766 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7770 /* Initialize token holders. */
7771 cur_token.code = prev_token.code = T_NIL;
7772 cur_token.reg = prev_token.reg = NULL;
7773 cur_token.str = prev_token.str = NULL;
7775 /* Initialize parser structure. */
7776 intel_parser.got_a_float = got_a_float;
7777 intel_parser.op_modifier = 0;
7778 intel_parser.is_mem = 0;
7779 intel_parser.in_offset = 0;
7780 intel_parser.in_bracket = 0;
7781 intel_parser.reg = NULL;
7782 intel_parser.disp[0] = '\0';
7783 intel_parser.next_operand = NULL;
7785 /* Read the first token and start the parser. */
7787 ret = intel_expr ();
7792 if (cur_token.code != T_NIL)
7794 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7795 current_templates->start->name, cur_token.str);
7798 /* If we found a memory reference, hand it over to i386_displacement
7799 to fill in the rest of the operand fields. */
7800 else if (intel_parser.is_mem)
7802 if ((i.mem_operands == 1
7803 && !current_templates->start->opcode_modifier.isstring)
7804 || i.mem_operands == 2)
7806 as_bad (_("too many memory references for '%s'"),
7807 current_templates->start->name);
7812 char *s = intel_parser.disp;
7815 if (!quiet_warnings && intel_parser.is_mem < 0)
7816 /* See the comments in intel_bracket_expr. */
7817 as_warn (_("Treating `%s' as memory reference"), operand_string);
7819 /* Add the displacement expression. */
7821 ret = i386_displacement (s, s + strlen (s));
7824 /* Swap base and index in 16-bit memory operands like
7825 [si+bx]. Since i386_index_check is also used in AT&T
7826 mode we have to do that here. */
7829 && i.base_reg->reg_type.bitfield.reg16
7830 && i.index_reg->reg_type.bitfield.reg16
7831 && i.base_reg->reg_num >= 6
7832 && i.index_reg->reg_num < 6)
7834 const reg_entry *base = i.index_reg;
7836 i.index_reg = i.base_reg;
7839 ret = i386_index_check (operand_string);
7844 /* Constant and OFFSET expressions are handled by i386_immediate. */
7845 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7846 || intel_parser.reg == NULL)
7847 ret = i386_immediate (intel_parser.disp);
7849 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7851 if (!ret || !intel_parser.next_operand)
7853 intel_parser.op_string = intel_parser.next_operand;
7854 this_operand = i.operands++;
7858 free (intel_parser.disp);
7863 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7867 expr' cmpOp e04 expr'
7872 /* XXX Implement the comparison operators. */
7873 return intel_e04 ();
7890 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7891 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7893 if (cur_token.code == '+')
7895 else if (cur_token.code == '-')
7896 nregs = NUM_ADDRESS_REGS;
7900 strcat (intel_parser.disp, cur_token.str);
7901 intel_match_token (cur_token.code);
7912 int nregs = ~NUM_ADDRESS_REGS;
7919 if (cur_token.code == '&'
7920 || cur_token.code == '|'
7921 || cur_token.code == '^')
7925 str[0] = cur_token.code;
7927 strcat (intel_parser.disp, str);
7932 intel_match_token (cur_token.code);
7937 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7938 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7949 int nregs = ~NUM_ADDRESS_REGS;
7956 if (cur_token.code == '*'
7957 || cur_token.code == '/'
7958 || cur_token.code == '%')
7962 str[0] = cur_token.code;
7964 strcat (intel_parser.disp, str);
7966 else if (cur_token.code == T_SHL)
7967 strcat (intel_parser.disp, "<<");
7968 else if (cur_token.code == T_SHR)
7969 strcat (intel_parser.disp, ">>");
7973 intel_match_token (cur_token.code);
7978 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7979 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7997 int nregs = ~NUM_ADDRESS_REGS;
8002 /* Don't consume constants here. */
8003 if (cur_token.code == '+' || cur_token.code == '-')
8005 /* Need to look one token ahead - if the next token
8006 is a constant, the current token is its sign. */
8009 intel_match_token (cur_token.code);
8010 next_code = cur_token.code;
8011 intel_putback_token ();
8012 if (next_code == T_CONST)
8016 /* e09 OFFSET e09 */
8017 if (cur_token.code == T_OFFSET)
8020 ++intel_parser.in_offset;
8024 else if (cur_token.code == T_SHORT)
8025 intel_parser.op_modifier |= 1 << T_SHORT;
8028 else if (cur_token.code == '+')
8029 strcat (intel_parser.disp, "+");
8034 else if (cur_token.code == '-' || cur_token.code == '~')
8040 str[0] = cur_token.code;
8042 strcat (intel_parser.disp, str);
8049 intel_match_token (cur_token.code);
8057 /* e09' PTR e10 e09' */
8058 if (cur_token.code == T_PTR)
8062 if (prev_token.code == T_BYTE)
8063 suffix = BYTE_MNEM_SUFFIX;
8065 else if (prev_token.code == T_WORD)
8067 if (current_templates->start->name[0] == 'l'
8068 && current_templates->start->name[2] == 's'
8069 && current_templates->start->name[3] == 0)
8070 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8071 else if (intel_parser.got_a_float == 2) /* "fi..." */
8072 suffix = SHORT_MNEM_SUFFIX;
8074 suffix = WORD_MNEM_SUFFIX;
8077 else if (prev_token.code == T_DWORD)
8079 if (current_templates->start->name[0] == 'l'
8080 && current_templates->start->name[2] == 's'
8081 && current_templates->start->name[3] == 0)
8082 suffix = WORD_MNEM_SUFFIX;
8083 else if (flag_code == CODE_16BIT
8084 && (current_templates->start->opcode_modifier.jump
8085 || current_templates->start->opcode_modifier.jumpdword))
8086 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8087 else if (intel_parser.got_a_float == 1) /* "f..." */
8088 suffix = SHORT_MNEM_SUFFIX;
8090 suffix = LONG_MNEM_SUFFIX;
8093 else if (prev_token.code == T_FWORD)
8095 if (current_templates->start->name[0] == 'l'
8096 && current_templates->start->name[2] == 's'
8097 && current_templates->start->name[3] == 0)
8098 suffix = LONG_MNEM_SUFFIX;
8099 else if (!intel_parser.got_a_float)
8101 if (flag_code == CODE_16BIT)
8102 add_prefix (DATA_PREFIX_OPCODE);
8103 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8106 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8109 else if (prev_token.code == T_QWORD)
8111 if (intel_parser.got_a_float == 1) /* "f..." */
8112 suffix = LONG_MNEM_SUFFIX;
8114 suffix = QWORD_MNEM_SUFFIX;
8117 else if (prev_token.code == T_TBYTE)
8119 if (intel_parser.got_a_float == 1)
8120 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8122 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8125 else if (prev_token.code == T_XMMWORD)
8127 suffix = XMMWORD_MNEM_SUFFIX;
8132 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8136 /* Operands for jump/call using 'ptr' notation denote absolute
8138 if (current_templates->start->opcode_modifier.jump
8139 || current_templates->start->opcode_modifier.jumpdword)
8140 i.types[this_operand].bitfield.jumpabsolute = 1;
8142 if (current_templates->start->base_opcode == 0x8d /* lea */)
8146 else if (i.suffix != suffix)
8148 as_bad (_("Conflicting operand modifiers"));
8154 /* e09' : e10 e09' */
8155 else if (cur_token.code == ':')
8157 if (prev_token.code != T_REG)
8159 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8160 segment/group identifier (which we don't have), using comma
8161 as the operand separator there is even less consistent, since
8162 there all branches only have a single operand. */
8163 if (this_operand != 0
8164 || intel_parser.in_offset
8165 || intel_parser.in_bracket
8166 || (!current_templates->start->opcode_modifier.jump
8167 && !current_templates->start->opcode_modifier.jumpdword
8168 && !current_templates->start->opcode_modifier.jumpintersegment
8169 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8170 return intel_match_token (T_NIL);
8171 /* Remember the start of the 2nd operand and terminate 1st
8173 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8174 another expression), but it gets at least the simplest case
8175 (a plain number or symbol on the left side) right. */
8176 intel_parser.next_operand = intel_parser.op_string;
8177 *--intel_parser.op_string = '\0';
8178 return intel_match_token (':');
8186 intel_match_token (cur_token.code);
8192 --intel_parser.in_offset;
8195 if (NUM_ADDRESS_REGS > nregs)
8197 as_bad (_("Invalid operand to `OFFSET'"));
8200 intel_parser.op_modifier |= 1 << T_OFFSET;
8203 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8204 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8209 intel_bracket_expr (void)
8211 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8212 const char *start = intel_parser.op_string;
8215 if (i.op[this_operand].regs)
8216 return intel_match_token (T_NIL);
8218 intel_match_token ('[');
8220 /* Mark as a memory operand only if it's not already known to be an
8221 offset expression. If it's an offset expression, we need to keep
8223 if (!intel_parser.in_offset)
8225 ++intel_parser.in_bracket;
8227 /* Operands for jump/call inside brackets denote absolute addresses. */
8228 if (current_templates->start->opcode_modifier.jump
8229 || current_templates->start->opcode_modifier.jumpdword)
8230 i.types[this_operand].bitfield.jumpabsolute = 1;
8232 /* Unfortunately gas always diverged from MASM in a respect that can't
8233 be easily fixed without risking to break code sequences likely to be
8234 encountered (the testsuite even check for this): MASM doesn't consider
8235 an expression inside brackets unconditionally as a memory reference.
8236 When that is e.g. a constant, an offset expression, or the sum of the
8237 two, this is still taken as a constant load. gas, however, always
8238 treated these as memory references. As a compromise, we'll try to make
8239 offset expressions inside brackets work the MASM way (since that's
8240 less likely to be found in real world code), but make constants alone
8241 continue to work the traditional gas way. In either case, issue a
8243 intel_parser.op_modifier &= ~was_offset;
8246 strcat (intel_parser.disp, "[");
8248 /* Add a '+' to the displacement string if necessary. */
8249 if (*intel_parser.disp != '\0'
8250 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8251 strcat (intel_parser.disp, "+");
8254 && (len = intel_parser.op_string - start - 1,
8255 intel_match_token (']')))
8257 /* Preserve brackets when the operand is an offset expression. */
8258 if (intel_parser.in_offset)
8259 strcat (intel_parser.disp, "]");
8262 --intel_parser.in_bracket;
8263 if (i.base_reg || i.index_reg)
8264 intel_parser.is_mem = 1;
8265 if (!intel_parser.is_mem)
8267 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8268 /* Defer the warning until all of the operand was parsed. */
8269 intel_parser.is_mem = -1;
8270 else if (!quiet_warnings)
8271 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8272 len, start, len, start);
8275 intel_parser.op_modifier |= was_offset;
8292 while (cur_token.code == '[')
8294 if (!intel_bracket_expr ())
8319 switch (cur_token.code)
8323 intel_match_token ('(');
8324 strcat (intel_parser.disp, "(");
8326 if (intel_expr () && intel_match_token (')'))
8328 strcat (intel_parser.disp, ")");
8335 return intel_bracket_expr ();
8340 strcat (intel_parser.disp, cur_token.str);
8341 intel_match_token (cur_token.code);
8343 /* Mark as a memory operand only if it's not already known to be an
8344 offset expression. */
8345 if (!intel_parser.in_offset)
8346 intel_parser.is_mem = 1;
8353 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8355 intel_match_token (T_REG);
8357 /* Check for segment change. */
8358 if (cur_token.code == ':')
8360 if (!reg->reg_type.bitfield.sreg2
8361 && !reg->reg_type.bitfield.sreg3)
8363 as_bad (_("`%s' is not a valid segment register"),
8367 else if (i.seg[i.mem_operands])
8368 as_warn (_("Extra segment override ignored"));
8371 if (!intel_parser.in_offset)
8372 intel_parser.is_mem = 1;
8373 switch (reg->reg_num)
8376 i.seg[i.mem_operands] = &es;
8379 i.seg[i.mem_operands] = &cs;
8382 i.seg[i.mem_operands] = &ss;
8385 i.seg[i.mem_operands] = &ds;
8388 i.seg[i.mem_operands] = &fs;
8391 i.seg[i.mem_operands] = &gs;
8397 /* Not a segment register. Check for register scaling. */
8398 else if (cur_token.code == '*')
8400 if (!intel_parser.in_bracket)
8402 as_bad (_("Register scaling only allowed in memory operands"));
8406 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8407 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8408 else if (i.index_reg)
8409 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8411 /* What follows must be a valid scale. */
8412 intel_match_token ('*');
8414 i.types[this_operand].bitfield.baseindex = 1;
8416 /* Set the scale after setting the register (otherwise,
8417 i386_scale will complain) */
8418 if (cur_token.code == '+' || cur_token.code == '-')
8420 char *str, sign = cur_token.code;
8421 intel_match_token (cur_token.code);
8422 if (cur_token.code != T_CONST)
8424 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8428 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8429 strcpy (str + 1, cur_token.str);
8431 if (!i386_scale (str))
8435 else if (!i386_scale (cur_token.str))
8437 intel_match_token (cur_token.code);
8440 /* No scaling. If this is a memory operand, the register is either a
8441 base register (first occurrence) or an index register (second
8443 else if (intel_parser.in_bracket)
8448 else if (!i.index_reg)
8452 as_bad (_("Too many register references in memory operand"));
8456 i.types[this_operand].bitfield.baseindex = 1;
8459 /* It's neither base nor index. */
8460 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8462 i386_operand_type temp = reg->reg_type;
8463 temp.bitfield.baseindex = 0;
8464 i.types[this_operand] = operand_type_or (i.types[this_operand],
8466 i.op[this_operand].regs = reg;
8471 as_bad (_("Invalid use of register"));
8475 /* Since registers are not part of the displacement string (except
8476 when we're parsing offset operands), we may need to remove any
8477 preceding '+' from the displacement string. */
8478 if (*intel_parser.disp != '\0'
8479 && !intel_parser.in_offset)
8481 char *s = intel_parser.disp;
8482 s += strlen (s) - 1;
8505 intel_match_token (cur_token.code);
8507 if (cur_token.code == T_PTR)
8510 /* It must have been an identifier. */
8511 intel_putback_token ();
8512 cur_token.code = T_ID;
8518 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8522 /* The identifier represents a memory reference only if it's not
8523 preceded by an offset modifier and if it's not an equate. */
8524 symbolP = symbol_find(cur_token.str);
8525 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8526 intel_parser.is_mem = 1;
8534 char *save_str, sign = 0;
8536 /* Allow constants that start with `+' or `-'. */
8537 if (cur_token.code == '-' || cur_token.code == '+')
8539 sign = cur_token.code;
8540 intel_match_token (cur_token.code);
8541 if (cur_token.code != T_CONST)
8543 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8549 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8550 strcpy (save_str + !!sign, cur_token.str);
8554 /* Get the next token to check for register scaling. */
8555 intel_match_token (cur_token.code);
8557 /* Check if this constant is a scaling factor for an
8559 if (cur_token.code == '*')
8561 if (intel_match_token ('*') && cur_token.code == T_REG)
8563 const reg_entry *reg = cur_token.reg;
8565 if (!intel_parser.in_bracket)
8567 as_bad (_("Register scaling only allowed "
8568 "in memory operands"));
8572 /* Disallow things like [1*si].
8573 sp and esp are invalid as index. */
8574 if (reg->reg_type.bitfield.reg16)
8575 reg = i386_regtab + REGNAM_AX + 4;
8576 else if (i.index_reg)
8577 reg = i386_regtab + REGNAM_EAX + 4;
8579 /* The constant is followed by `* reg', so it must be
8582 i.types[this_operand].bitfield.baseindex = 1;
8584 /* Set the scale after setting the register (otherwise,
8585 i386_scale will complain) */
8586 if (!i386_scale (save_str))
8588 intel_match_token (T_REG);
8590 /* Since registers are not part of the displacement
8591 string, we may need to remove any preceding '+' from
8592 the displacement string. */
8593 if (*intel_parser.disp != '\0')
8595 char *s = intel_parser.disp;
8596 s += strlen (s) - 1;
8606 /* The constant was not used for register scaling. Since we have
8607 already consumed the token following `*' we now need to put it
8608 back in the stream. */
8609 intel_putback_token ();
8612 /* Add the constant to the displacement string. */
8613 strcat (intel_parser.disp, save_str);
8620 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8624 /* Match the given token against cur_token. If they match, read the next
8625 token from the operand string. */
8627 intel_match_token (int code)
8629 if (cur_token.code == code)
8636 as_bad (_("Unexpected token `%s'"), cur_token.str);
8641 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8643 intel_get_token (void)
8646 const reg_entry *reg;
8647 struct intel_token new_token;
8649 new_token.code = T_NIL;
8650 new_token.reg = NULL;
8651 new_token.str = NULL;
8653 /* Free the memory allocated to the previous token and move
8654 cur_token to prev_token. */
8656 free (prev_token.str);
8658 prev_token = cur_token;
8660 /* Skip whitespace. */
8661 while (is_space_char (*intel_parser.op_string))
8662 intel_parser.op_string++;
8664 /* Return an empty token if we find nothing else on the line. */
8665 if (*intel_parser.op_string == '\0')
8667 cur_token = new_token;
8671 /* The new token cannot be larger than the remainder of the operand
8673 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8674 new_token.str[0] = '\0';
8676 if (strchr ("0123456789", *intel_parser.op_string))
8678 char *p = new_token.str;
8679 char *q = intel_parser.op_string;
8680 new_token.code = T_CONST;
8682 /* Allow any kind of identifier char to encompass floating point and
8683 hexadecimal numbers. */
8684 while (is_identifier_char (*q))
8688 /* Recognize special symbol names [0-9][bf]. */
8689 if (strlen (intel_parser.op_string) == 2
8690 && (intel_parser.op_string[1] == 'b'
8691 || intel_parser.op_string[1] == 'f'))
8692 new_token.code = T_ID;
8695 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8697 size_t len = end_op - intel_parser.op_string;
8699 new_token.code = T_REG;
8700 new_token.reg = reg;
8702 memcpy (new_token.str, intel_parser.op_string, len);
8703 new_token.str[len] = '\0';
8706 else if (is_identifier_char (*intel_parser.op_string))
8708 char *p = new_token.str;
8709 char *q = intel_parser.op_string;
8711 /* A '.' or '$' followed by an identifier char is an identifier.
8712 Otherwise, it's operator '.' followed by an expression. */
8713 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8715 new_token.code = '.';
8716 new_token.str[0] = '.';
8717 new_token.str[1] = '\0';
8721 while (is_identifier_char (*q) || *q == '@')
8725 if (strcasecmp (new_token.str, "NOT") == 0)
8726 new_token.code = '~';
8728 else if (strcasecmp (new_token.str, "MOD") == 0)
8729 new_token.code = '%';
8731 else if (strcasecmp (new_token.str, "AND") == 0)
8732 new_token.code = '&';
8734 else if (strcasecmp (new_token.str, "OR") == 0)
8735 new_token.code = '|';
8737 else if (strcasecmp (new_token.str, "XOR") == 0)
8738 new_token.code = '^';
8740 else if (strcasecmp (new_token.str, "SHL") == 0)
8741 new_token.code = T_SHL;
8743 else if (strcasecmp (new_token.str, "SHR") == 0)
8744 new_token.code = T_SHR;
8746 else if (strcasecmp (new_token.str, "BYTE") == 0)
8747 new_token.code = T_BYTE;
8749 else if (strcasecmp (new_token.str, "WORD") == 0)
8750 new_token.code = T_WORD;
8752 else if (strcasecmp (new_token.str, "DWORD") == 0)
8753 new_token.code = T_DWORD;
8755 else if (strcasecmp (new_token.str, "FWORD") == 0)
8756 new_token.code = T_FWORD;
8758 else if (strcasecmp (new_token.str, "QWORD") == 0)
8759 new_token.code = T_QWORD;
8761 else if (strcasecmp (new_token.str, "TBYTE") == 0
8762 /* XXX remove (gcc still uses it) */
8763 || strcasecmp (new_token.str, "XWORD") == 0)
8764 new_token.code = T_TBYTE;
8766 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8767 || strcasecmp (new_token.str, "OWORD") == 0)
8768 new_token.code = T_XMMWORD;
8770 else if (strcasecmp (new_token.str, "PTR") == 0)
8771 new_token.code = T_PTR;
8773 else if (strcasecmp (new_token.str, "SHORT") == 0)
8774 new_token.code = T_SHORT;
8776 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8778 new_token.code = T_OFFSET;
8780 /* ??? This is not mentioned in the MASM grammar but gcc
8781 makes use of it with -mintel-syntax. OFFSET may be
8782 followed by FLAT: */
8783 if (strncasecmp (q, " FLAT:", 6) == 0)
8784 strcat (new_token.str, " FLAT:");
8787 /* ??? This is not mentioned in the MASM grammar. */
8788 else if (strcasecmp (new_token.str, "FLAT") == 0)
8790 new_token.code = T_OFFSET;
8792 strcat (new_token.str, ":");
8794 as_bad (_("`:' expected"));
8798 new_token.code = T_ID;
8802 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8804 new_token.code = *intel_parser.op_string;
8805 new_token.str[0] = *intel_parser.op_string;
8806 new_token.str[1] = '\0';
8809 else if (strchr ("<>", *intel_parser.op_string)
8810 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8812 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8813 new_token.str[0] = *intel_parser.op_string;
8814 new_token.str[1] = *intel_parser.op_string;
8815 new_token.str[2] = '\0';
8819 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8821 intel_parser.op_string += strlen (new_token.str);
8822 cur_token = new_token;
8825 /* Put cur_token back into the token stream and make cur_token point to
8828 intel_putback_token (void)
8830 if (cur_token.code != T_NIL)
8832 intel_parser.op_string -= strlen (cur_token.str);
8833 free (cur_token.str);
8835 cur_token = prev_token;
8837 /* Forget prev_token. */
8838 prev_token.code = T_NIL;
8839 prev_token.reg = NULL;
8840 prev_token.str = NULL;
8844 tc_x86_regname_to_dw2regnum (char *regname)
8846 unsigned int regnum;
8847 unsigned int regnames_count;
8848 static const char *const regnames_32[] =
8850 "eax", "ecx", "edx", "ebx",
8851 "esp", "ebp", "esi", "edi",
8852 "eip", "eflags", NULL,
8853 "st0", "st1", "st2", "st3",
8854 "st4", "st5", "st6", "st7",
8856 "xmm0", "xmm1", "xmm2", "xmm3",
8857 "xmm4", "xmm5", "xmm6", "xmm7",
8858 "mm0", "mm1", "mm2", "mm3",
8859 "mm4", "mm5", "mm6", "mm7",
8860 "fcw", "fsw", "mxcsr",
8861 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8864 static const char *const regnames_64[] =
8866 "rax", "rdx", "rcx", "rbx",
8867 "rsi", "rdi", "rbp", "rsp",
8868 "r8", "r9", "r10", "r11",
8869 "r12", "r13", "r14", "r15",
8871 "xmm0", "xmm1", "xmm2", "xmm3",
8872 "xmm4", "xmm5", "xmm6", "xmm7",
8873 "xmm8", "xmm9", "xmm10", "xmm11",
8874 "xmm12", "xmm13", "xmm14", "xmm15",
8875 "st0", "st1", "st2", "st3",
8876 "st4", "st5", "st6", "st7",
8877 "mm0", "mm1", "mm2", "mm3",
8878 "mm4", "mm5", "mm6", "mm7",
8880 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8881 "fs.base", "gs.base", NULL, NULL,
8883 "mxcsr", "fcw", "fsw"
8885 const char *const *regnames;
8887 if (flag_code == CODE_64BIT)
8889 regnames = regnames_64;
8890 regnames_count = ARRAY_SIZE (regnames_64);
8894 regnames = regnames_32;
8895 regnames_count = ARRAY_SIZE (regnames_32);
8898 for (regnum = 0; regnum < regnames_count; regnum++)
8899 if (regnames[regnum] != NULL
8900 && strcmp (regname, regnames[regnum]) == 0)
8907 tc_x86_frame_initial_instructions (void)
8909 static unsigned int sp_regno;
8912 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8915 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8916 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8920 i386_elf_section_type (const char *str, size_t len)
8922 if (flag_code == CODE_64BIT
8923 && len == sizeof ("unwind") - 1
8924 && strncmp (str, "unwind", 6) == 0)
8925 return SHT_X86_64_UNWIND;
8932 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8936 expr.X_op = O_secrel;
8937 expr.X_add_symbol = symbol;
8938 expr.X_add_number = 0;
8939 emit_expr (&expr, size);
8943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8944 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8947 x86_64_section_letter (int letter, char **ptr_msg)
8949 if (flag_code == CODE_64BIT)
8952 return SHF_X86_64_LARGE;
8954 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8957 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8962 x86_64_section_word (char *str, size_t len)
8964 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8965 return SHF_X86_64_LARGE;
8971 handle_large_common (int small ATTRIBUTE_UNUSED)
8973 if (flag_code != CODE_64BIT)
8975 s_comm_internal (0, elf_common_parse);
8976 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8980 static segT lbss_section;
8981 asection *saved_com_section_ptr = elf_com_section_ptr;
8982 asection *saved_bss_section = bss_section;
8984 if (lbss_section == NULL)
8986 flagword applicable;
8988 subsegT subseg = now_subseg;
8990 /* The .lbss section is for local .largecomm symbols. */
8991 lbss_section = subseg_new (".lbss", 0);
8992 applicable = bfd_applicable_section_flags (stdoutput);
8993 bfd_set_section_flags (stdoutput, lbss_section,
8994 applicable & SEC_ALLOC);
8995 seg_info (lbss_section)->bss = 1;
8997 subseg_set (seg, subseg);
9000 elf_com_section_ptr = &_bfd_elf_large_com_section;
9001 bss_section = lbss_section;
9003 s_comm_internal (0, elf_common_parse);
9005 elf_com_section_ptr = saved_com_section_ptr;
9006 bss_section = saved_bss_section;
9009 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */