1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static char *output_invalid PARAMS ((int c));
84 static int i386_operand PARAMS ((char *operand_string));
85 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86 static const reg_entry *parse_register PARAMS ((char *reg_string,
88 static char *parse_insn PARAMS ((char *, char *));
89 static char *parse_operands PARAMS ((char *, const char *));
90 static void swap_operands PARAMS ((void));
91 static void optimize_imm PARAMS ((void));
92 static void optimize_disp PARAMS ((void));
93 static int match_template PARAMS ((void));
94 static int check_string PARAMS ((void));
95 static int process_suffix PARAMS ((void));
96 static int check_byte_reg PARAMS ((void));
97 static int check_long_reg PARAMS ((void));
98 static int check_qword_reg PARAMS ((void));
99 static int check_word_reg PARAMS ((void));
100 static int finalize_imm PARAMS ((void));
101 static int process_operands PARAMS ((void));
102 static const seg_entry *build_modrm_byte PARAMS ((void));
103 static void output_insn PARAMS ((void));
104 static void output_branch PARAMS ((void));
105 static void output_jump PARAMS ((void));
106 static void output_interseg_jump PARAMS ((void));
107 static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109 static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
112 static void s_bss PARAMS ((int));
115 static const char *default_arch = DEFAULT_ARCH;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry *regs;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types[MAX_OPERANDS];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op[MAX_OPERANDS];
152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry *seg[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars[] = "/#";
225 const char line_separator_chars[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars[256];
238 static char register_chars[256];
239 static char operand_chars[256];
240 static char identifier_chars[256];
241 static char digit_chars[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack[32];
259 static char *save_stack_p;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates *current_templates;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions[2], im_expressions[2];
274 /* Current operand we are working on. */
275 static int this_operand;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code;
287 static int use_rela_relocations = 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names[] =
297 /* 1 for intel syntax,
299 static int intel_syntax = 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg = 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size = '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code = 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings = 0;
316 static const char *cpu_arch_name = NULL;
317 static const char *cpu_sub_arch_name = NULL;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion = 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS *GOT_symbol;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch[] = {
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
432 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
434 {".sse", CpuMMX|CpuMMX2|CpuSSE },
435 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
436 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
437 {".3dnow", CpuMMX|Cpu3dnow },
438 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
439 {".padlock", CpuPadLock },
440 {".pacifica", CpuSVME },
445 const pseudo_typeS md_pseudo_table[] =
447 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
448 {"align", s_align_bytes, 0},
450 {"align", s_align_ptwo, 0},
452 {"arch", set_cpu_arch, 0},
456 {"ffloat", float_cons, 'f'},
457 {"dfloat", float_cons, 'd'},
458 {"tfloat", float_cons, 'x'},
460 {"noopt", s_ignore, 0},
461 {"optim", s_ignore, 0},
462 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
463 {"code16", set_code_flag, CODE_16BIT},
464 {"code32", set_code_flag, CODE_32BIT},
465 {"code64", set_code_flag, CODE_64BIT},
466 {"intel_syntax", set_intel_syntax, 1},
467 {"att_syntax", set_intel_syntax, 0},
468 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
469 {"loc", dwarf2_directive_loc, 0},
471 {"secrel32", pe_directive_secrel, 0},
476 /* For interface with expression (). */
477 extern char *input_line_pointer;
479 /* Hash table for instruction mnemonic lookup. */
480 static struct hash_control *op_hash;
482 /* Hash table for register lookup. */
483 static struct hash_control *reg_hash;
486 i386_align_code (fragP, count)
490 /* Various efficient no-op patterns for aligning code labels.
491 Note: Don't try to assemble the instructions in the comments.
492 0L and 0w are not legal. */
493 static const char f32_1[] =
495 static const char f32_2[] =
496 {0x89,0xf6}; /* movl %esi,%esi */
497 static const char f32_3[] =
498 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
499 static const char f32_4[] =
500 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
501 static const char f32_5[] =
503 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
504 static const char f32_6[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
506 static const char f32_7[] =
507 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
508 static const char f32_8[] =
510 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
511 static const char f32_9[] =
512 {0x89,0xf6, /* movl %esi,%esi */
513 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
514 static const char f32_10[] =
515 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
516 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
517 static const char f32_11[] =
518 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_12[] =
521 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
522 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
523 static const char f32_13[] =
524 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_14[] =
527 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_15[] =
530 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
531 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
532 static const char f16_3[] =
533 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
534 static const char f16_4[] =
535 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
536 static const char f16_5[] =
538 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
539 static const char f16_6[] =
540 {0x89,0xf6, /* mov %si,%si */
541 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
542 static const char f16_7[] =
543 {0x8d,0x74,0x00, /* lea 0(%si),%si */
544 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
545 static const char f16_8[] =
546 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char *const f32_patt[] = {
549 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
550 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
552 static const char *const f16_patt[] = {
553 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
554 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
557 if (count <= 0 || count > 15)
560 /* The recommended way to pad 64bit code is to use NOPs preceded by
561 maximally four 0x66 prefixes. Balance the size of nops. */
562 if (flag_code == CODE_64BIT)
565 int nnops = (count + 3) / 4;
566 int len = count / nnops;
567 int remains = count - nnops * len;
570 for (i = 0; i < remains; i++)
572 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
573 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
576 for (; i < nnops; i++)
578 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
579 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
584 if (flag_code == CODE_16BIT)
586 memcpy (fragP->fr_literal + fragP->fr_fix,
587 f16_patt[count - 1], count);
589 /* Adjust jump offset. */
590 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
593 memcpy (fragP->fr_literal + fragP->fr_fix,
594 f32_patt[count - 1], count);
595 fragP->fr_var = count;
598 static INLINE unsigned int
599 mode_from_disp_size (t)
602 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
606 fits_in_signed_byte (num)
609 return (num >= -128) && (num <= 127);
613 fits_in_unsigned_byte (num)
616 return (num & 0xff) == num;
620 fits_in_unsigned_word (num)
623 return (num & 0xffff) == num;
627 fits_in_signed_word (num)
630 return (-32768 <= num) && (num <= 32767);
633 fits_in_signed_long (num)
634 offsetT num ATTRIBUTE_UNUSED;
639 return (!(((offsetT) -1 << 31) & num)
640 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
642 } /* fits_in_signed_long() */
644 fits_in_unsigned_long (num)
645 offsetT num ATTRIBUTE_UNUSED;
650 return (num & (((offsetT) 2 << 31) - 1)) == num;
652 } /* fits_in_unsigned_long() */
655 smallest_imm_type (num)
658 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
660 /* This code is disabled on the 486 because all the Imm1 forms
661 in the opcode table are slower on the i486. They're the
662 versions with the implicitly specified single-position
663 displacement, which has another syntax if you really want to
666 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
668 return (fits_in_signed_byte (num)
669 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_unsigned_byte (num)
671 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
672 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
673 ? (Imm16 | Imm32 | Imm32S | Imm64)
674 : fits_in_signed_long (num)
675 ? (Imm32 | Imm32S | Imm64)
676 : fits_in_unsigned_long (num)
682 offset_in_range (val, size)
690 case 1: mask = ((addressT) 1 << 8) - 1; break;
691 case 2: mask = ((addressT) 1 << 16) - 1; break;
692 case 4: mask = ((addressT) 2 << 31) - 1; break;
694 case 8: mask = ((addressT) 2 << 63) - 1; break;
699 /* If BFD64, sign extend val. */
700 if (!use_rela_relocations)
701 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
702 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
704 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
706 char buf1[40], buf2[40];
708 sprint_value (buf1, val);
709 sprint_value (buf2, val & mask);
710 as_warn (_("%s shortened to %s"), buf1, buf2);
715 /* Returns 0 if attempting to add a prefix where one from the same
716 class already exists, 1 if non rep/repne added, 2 if rep/repne
725 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
726 && flag_code == CODE_64BIT)
734 case CS_PREFIX_OPCODE:
735 case DS_PREFIX_OPCODE:
736 case ES_PREFIX_OPCODE:
737 case FS_PREFIX_OPCODE:
738 case GS_PREFIX_OPCODE:
739 case SS_PREFIX_OPCODE:
743 case REPNE_PREFIX_OPCODE:
744 case REPE_PREFIX_OPCODE:
747 case LOCK_PREFIX_OPCODE:
755 case ADDR_PREFIX_OPCODE:
759 case DATA_PREFIX_OPCODE:
764 if (i.prefix[q] != 0)
766 as_bad (_("same type of prefix used twice"));
771 i.prefix[q] = prefix;
776 set_code_flag (value)
780 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
781 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
782 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
784 as_bad (_("64bit mode not supported on this CPU."));
786 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
788 as_bad (_("32bit mode not supported on this CPU."));
794 set_16bit_gcc_code_flag (new_code_flag)
797 flag_code = new_code_flag;
798 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
799 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
800 stackop_size = LONG_MNEM_SUFFIX;
804 set_intel_syntax (syntax_flag)
807 /* Find out if register prefixing is specified. */
808 int ask_naked_reg = 0;
811 if (!is_end_of_line[(unsigned char) *input_line_pointer])
813 char *string = input_line_pointer;
814 int e = get_symbol_end ();
816 if (strcmp (string, "prefix") == 0)
818 else if (strcmp (string, "noprefix") == 0)
821 as_bad (_("bad argument to syntax directive."));
822 *input_line_pointer = e;
824 demand_empty_rest_of_line ();
826 intel_syntax = syntax_flag;
828 if (ask_naked_reg == 0)
829 allow_naked_reg = (intel_syntax
830 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
832 allow_naked_reg = (ask_naked_reg < 0);
834 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
835 identifier_chars['$'] = intel_syntax ? '$' : 0;
840 int dummy ATTRIBUTE_UNUSED;
844 if (!is_end_of_line[(unsigned char) *input_line_pointer])
846 char *string = input_line_pointer;
847 int e = get_symbol_end ();
850 for (i = 0; cpu_arch[i].name; i++)
852 if (strcmp (string, cpu_arch[i].name) == 0)
856 cpu_arch_name = cpu_arch[i].name;
857 cpu_sub_arch_name = NULL;
858 cpu_arch_flags = (cpu_arch[i].flags
859 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
862 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
864 cpu_sub_arch_name = cpu_arch[i].name;
865 cpu_arch_flags |= cpu_arch[i].flags;
867 *input_line_pointer = e;
868 demand_empty_rest_of_line ();
872 if (!cpu_arch[i].name)
873 as_bad (_("no such architecture: `%s'"), string);
875 *input_line_pointer = e;
878 as_bad (_("missing cpu architecture"));
880 no_cond_jump_promotion = 0;
881 if (*input_line_pointer == ','
882 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
884 char *string = ++input_line_pointer;
885 int e = get_symbol_end ();
887 if (strcmp (string, "nojumps") == 0)
888 no_cond_jump_promotion = 1;
889 else if (strcmp (string, "jumps") == 0)
892 as_bad (_("no such architecture modifier: `%s'"), string);
894 *input_line_pointer = e;
897 demand_empty_rest_of_line ();
903 if (!strcmp (default_arch, "x86_64"))
904 return bfd_mach_x86_64;
905 else if (!strcmp (default_arch, "i386"))
906 return bfd_mach_i386_i386;
908 as_fatal (_("Unknown architecture"));
914 const char *hash_err;
916 /* Initialize op_hash hash table. */
917 op_hash = hash_new ();
920 const template *optab;
921 templates *core_optab;
923 /* Setup for loop. */
925 core_optab = (templates *) xmalloc (sizeof (templates));
926 core_optab->start = optab;
931 if (optab->name == NULL
932 || strcmp (optab->name, (optab - 1)->name) != 0)
934 /* different name --> ship out current template list;
935 add to hash table; & begin anew. */
936 core_optab->end = optab;
937 hash_err = hash_insert (op_hash,
942 as_fatal (_("Internal Error: Can't hash %s: %s"),
946 if (optab->name == NULL)
948 core_optab = (templates *) xmalloc (sizeof (templates));
949 core_optab->start = optab;
954 /* Initialize reg_hash hash table. */
955 reg_hash = hash_new ();
957 const reg_entry *regtab;
959 for (regtab = i386_regtab;
960 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
963 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
965 as_fatal (_("Internal Error: Can't hash %s: %s"),
971 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
976 for (c = 0; c < 256; c++)
981 mnemonic_chars[c] = c;
982 register_chars[c] = c;
983 operand_chars[c] = c;
985 else if (ISLOWER (c))
987 mnemonic_chars[c] = c;
988 register_chars[c] = c;
989 operand_chars[c] = c;
991 else if (ISUPPER (c))
993 mnemonic_chars[c] = TOLOWER (c);
994 register_chars[c] = mnemonic_chars[c];
995 operand_chars[c] = c;
998 if (ISALPHA (c) || ISDIGIT (c))
999 identifier_chars[c] = c;
1002 identifier_chars[c] = c;
1003 operand_chars[c] = c;
1008 identifier_chars['@'] = '@';
1011 identifier_chars['?'] = '?';
1012 operand_chars['?'] = '?';
1014 digit_chars['-'] = '-';
1015 mnemonic_chars['-'] = '-';
1016 identifier_chars['_'] = '_';
1017 identifier_chars['.'] = '.';
1019 for (p = operand_special_chars; *p != '\0'; p++)
1020 operand_chars[(unsigned char) *p] = *p;
1023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1024 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1026 record_alignment (text_section, 2);
1027 record_alignment (data_section, 2);
1028 record_alignment (bss_section, 2);
1032 if (flag_code == CODE_64BIT)
1034 x86_dwarf2_return_column = 16;
1035 x86_cie_data_alignment = -8;
1039 x86_dwarf2_return_column = 8;
1040 x86_cie_data_alignment = -4;
1045 i386_print_statistics (file)
1048 hash_print_statistics (file, "i386 opcode", op_hash);
1049 hash_print_statistics (file, "i386 register", reg_hash);
1054 /* Debugging routines for md_assemble. */
1055 static void pi PARAMS ((char *, i386_insn *));
1056 static void pte PARAMS ((template *));
1057 static void pt PARAMS ((unsigned int));
1058 static void pe PARAMS ((expressionS *));
1059 static void ps PARAMS ((symbolS *));
1068 fprintf (stdout, "%s: template ", line);
1070 fprintf (stdout, " address: base %s index %s scale %x\n",
1071 x->base_reg ? x->base_reg->reg_name : "none",
1072 x->index_reg ? x->index_reg->reg_name : "none",
1073 x->log2_scale_factor);
1074 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1075 x->rm.mode, x->rm.reg, x->rm.regmem);
1076 fprintf (stdout, " sib: base %x index %x scale %x\n",
1077 x->sib.base, x->sib.index, x->sib.scale);
1078 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1079 (x->rex & REX_MODE64) != 0,
1080 (x->rex & REX_EXTX) != 0,
1081 (x->rex & REX_EXTY) != 0,
1082 (x->rex & REX_EXTZ) != 0);
1083 for (i = 0; i < x->operands; i++)
1085 fprintf (stdout, " #%d: ", i + 1);
1087 fprintf (stdout, "\n");
1089 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1090 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1091 if (x->types[i] & Imm)
1093 if (x->types[i] & Disp)
1094 pe (x->op[i].disps);
1103 fprintf (stdout, " %d operands ", t->operands);
1104 fprintf (stdout, "opcode %x ", t->base_opcode);
1105 if (t->extension_opcode != None)
1106 fprintf (stdout, "ext %x ", t->extension_opcode);
1107 if (t->opcode_modifier & D)
1108 fprintf (stdout, "D");
1109 if (t->opcode_modifier & W)
1110 fprintf (stdout, "W");
1111 fprintf (stdout, "\n");
1112 for (i = 0; i < t->operands; i++)
1114 fprintf (stdout, " #%d type ", i + 1);
1115 pt (t->operand_types[i]);
1116 fprintf (stdout, "\n");
1124 fprintf (stdout, " operation %d\n", e->X_op);
1125 fprintf (stdout, " add_number %ld (%lx)\n",
1126 (long) e->X_add_number, (long) e->X_add_number);
1127 if (e->X_add_symbol)
1129 fprintf (stdout, " add_symbol ");
1130 ps (e->X_add_symbol);
1131 fprintf (stdout, "\n");
1135 fprintf (stdout, " op_symbol ");
1136 ps (e->X_op_symbol);
1137 fprintf (stdout, "\n");
1145 fprintf (stdout, "%s type %s%s",
1147 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1148 segment_name (S_GET_SEGMENT (s)));
1157 static const type_names[] =
1170 { BaseIndex, "BaseIndex" },
1174 { Disp32S, "d32s" },
1176 { InOutPortReg, "InOutPortReg" },
1177 { ShiftCount, "ShiftCount" },
1178 { Control, "control reg" },
1179 { Test, "test reg" },
1180 { Debug, "debug reg" },
1181 { FloatReg, "FReg" },
1182 { FloatAcc, "FAcc" },
1186 { JumpAbsolute, "Jump Absolute" },
1197 const struct type_name *ty;
1199 for (ty = type_names; ty->mask; ty++)
1201 fprintf (stdout, "%s, ", ty->tname);
1205 #endif /* DEBUG386 */
1207 static bfd_reloc_code_real_type reloc
1208 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1210 static bfd_reloc_code_real_type
1211 reloc (size, pcrel, sign, other)
1215 bfd_reloc_code_real_type other;
1217 if (other != NO_RELOC)
1223 as_bad (_("There are no unsigned pc-relative relocations"));
1226 case 1: return BFD_RELOC_8_PCREL;
1227 case 2: return BFD_RELOC_16_PCREL;
1228 case 4: return BFD_RELOC_32_PCREL;
1229 case 8: return BFD_RELOC_64_PCREL;
1231 as_bad (_("can not do %d byte pc-relative relocation"), size);
1238 case 4: return BFD_RELOC_X86_64_32S;
1243 case 1: return BFD_RELOC_8;
1244 case 2: return BFD_RELOC_16;
1245 case 4: return BFD_RELOC_32;
1246 case 8: return BFD_RELOC_64;
1248 as_bad (_("can not do %s %d byte relocation"),
1249 sign ? "signed" : "unsigned", size);
1253 return BFD_RELOC_NONE;
1256 /* Here we decide which fixups can be adjusted to make them relative to
1257 the beginning of the section instead of the symbol. Basically we need
1258 to make sure that the dynamic relocations are done correctly, so in
1259 some cases we force the original symbol to be used. */
1262 tc_i386_fix_adjustable (fixP)
1263 fixS *fixP ATTRIBUTE_UNUSED;
1265 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1266 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1269 /* Don't adjust pc-relative references to merge sections in 64-bit
1271 if (use_rela_relocations
1272 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1276 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1277 and changed later by validate_fix. */
1278 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1279 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1282 /* adjust_reloc_syms doesn't know about the GOT. */
1283 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1284 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1285 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1288 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1289 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1290 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1291 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1292 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1293 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1296 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1297 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1298 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1299 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1300 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1301 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1302 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1303 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1304 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1305 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1306 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1312 static int intel_float_operand PARAMS ((const char *mnemonic));
1315 intel_float_operand (mnemonic)
1316 const char *mnemonic;
1318 /* Note that the value returned is meaningful only for opcodes with (memory)
1319 operands, hence the code here is free to improperly handle opcodes that
1320 have no operands (for better performance and smaller code). */
1322 if (mnemonic[0] != 'f')
1323 return 0; /* non-math */
1325 switch (mnemonic[1])
1327 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1328 the fs segment override prefix not currently handled because no
1329 call path can make opcodes without operands get here */
1331 return 2 /* integer op */;
1333 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1334 return 3; /* fldcw/fldenv */
1337 if (mnemonic[2] != 'o' /* fnop */)
1338 return 3; /* non-waiting control op */
1341 if (mnemonic[2] == 's')
1342 return 3; /* frstor/frstpm */
1345 if (mnemonic[2] == 'a')
1346 return 3; /* fsave */
1347 if (mnemonic[2] == 't')
1349 switch (mnemonic[3])
1351 case 'c': /* fstcw */
1352 case 'd': /* fstdw */
1353 case 'e': /* fstenv */
1354 case 's': /* fsts[gw] */
1360 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1361 return 0; /* fxsave/fxrstor are not really math ops */
1368 /* This is the guts of the machine-dependent assembler. LINE points to a
1369 machine dependent instruction. This function is supposed to emit
1370 the frags/bytes it assembles to. */
1377 char mnemonic[MAX_MNEM_SIZE];
1379 /* Initialize globals. */
1380 memset (&i, '\0', sizeof (i));
1381 for (j = 0; j < MAX_OPERANDS; j++)
1382 i.reloc[j] = NO_RELOC;
1383 memset (disp_expressions, '\0', sizeof (disp_expressions));
1384 memset (im_expressions, '\0', sizeof (im_expressions));
1385 save_stack_p = save_stack;
1387 /* First parse an instruction mnemonic & call i386_operand for the operands.
1388 We assume that the scrubber has arranged it so that line[0] is the valid
1389 start of a (possibly prefixed) mnemonic. */
1391 line = parse_insn (line, mnemonic);
1395 line = parse_operands (line, mnemonic);
1399 /* Now we've parsed the mnemonic into a set of templates, and have the
1400 operands at hand. */
1402 /* All intel opcodes have reversed operands except for "bound" and
1403 "enter". We also don't reverse intersegment "jmp" and "call"
1404 instructions with 2 immediate operands so that the immediate segment
1405 precedes the offset, as it does when in AT&T mode. "enter" and the
1406 intersegment "jmp" and "call" instructions are the only ones that
1407 have two immediate operands. */
1408 if (intel_syntax && i.operands > 1
1409 && (strcmp (mnemonic, "bound") != 0)
1410 && (strcmp (mnemonic, "invlpga") != 0)
1411 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1417 /* Don't optimize displacement for movabs since it only takes 64bit
1420 && (flag_code != CODE_64BIT
1421 || strcmp (mnemonic, "movabs") != 0))
1424 /* Next, we find a template that matches the given insn,
1425 making sure the overlap of the given operands types is consistent
1426 with the template operand types. */
1428 if (!match_template ())
1433 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1435 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1436 i.tm.base_opcode ^= FloatR;
1438 /* Zap movzx and movsx suffix. The suffix may have been set from
1439 "word ptr" or "byte ptr" on the source operand, but we'll use
1440 the suffix later to choose the destination register. */
1441 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1443 if (i.reg_operands < 2
1445 && (~i.tm.opcode_modifier
1452 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1458 if (i.tm.opcode_modifier & FWait)
1459 if (!add_prefix (FWAIT_OPCODE))
1462 /* Check string instruction segment overrides. */
1463 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1465 if (!check_string ())
1469 if (!process_suffix ())
1472 /* Make still unresolved immediate matches conform to size of immediate
1473 given in i.suffix. */
1474 if (!finalize_imm ())
1477 if (i.types[0] & Imm1)
1478 i.imm_operands = 0; /* kludge for shift insns. */
1479 if (i.types[0] & ImplicitRegister)
1481 if (i.types[1] & ImplicitRegister)
1483 if (i.types[2] & ImplicitRegister)
1486 if (i.tm.opcode_modifier & ImmExt)
1490 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1492 /* These Intel Prescott New Instructions have the fixed
1493 operands with an opcode suffix which is coded in the same
1494 place as an 8-bit immediate field would be. Here we check
1495 those operands and remove them afterwards. */
1498 for (x = 0; x < i.operands; x++)
1499 if (i.op[x].regs->reg_num != x)
1500 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1501 i.op[x].regs->reg_name, x + 1, i.tm.name);
1505 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1506 opcode suffix which is coded in the same place as an 8-bit
1507 immediate field would be. Here we fake an 8-bit immediate
1508 operand from the opcode suffix stored in tm.extension_opcode. */
1510 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1512 exp = &im_expressions[i.imm_operands++];
1513 i.op[i.operands].imms = exp;
1514 i.types[i.operands++] = Imm8;
1515 exp->X_op = O_constant;
1516 exp->X_add_number = i.tm.extension_opcode;
1517 i.tm.extension_opcode = None;
1520 /* For insns with operands there are more diddles to do to the opcode. */
1523 if (!process_operands ())
1526 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1528 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1529 as_warn (_("translating to `%sp'"), i.tm.name);
1532 /* Handle conversion of 'int $3' --> special int3 insn. */
1533 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1535 i.tm.base_opcode = INT3_OPCODE;
1539 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1540 && i.op[0].disps->X_op == O_constant)
1542 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1543 the absolute address given by the constant. Since ix86 jumps and
1544 calls are pc relative, we need to generate a reloc. */
1545 i.op[0].disps->X_add_symbol = &abs_symbol;
1546 i.op[0].disps->X_op = O_symbol;
1549 if ((i.tm.opcode_modifier & Rex64) != 0)
1550 i.rex |= REX_MODE64;
1552 /* For 8 bit registers we need an empty rex prefix. Also if the
1553 instruction already has a prefix, we need to convert old
1554 registers to new ones. */
1556 if (((i.types[0] & Reg8) != 0
1557 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1558 || ((i.types[1] & Reg8) != 0
1559 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1560 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1565 i.rex |= REX_OPCODE;
1566 for (x = 0; x < 2; x++)
1568 /* Look for 8 bit operand that uses old registers. */
1569 if ((i.types[x] & Reg8) != 0
1570 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1572 /* In case it is "hi" register, give up. */
1573 if (i.op[x].regs->reg_num > 3)
1574 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1575 i.op[x].regs->reg_name);
1577 /* Otherwise it is equivalent to the extended register.
1578 Since the encoding doesn't change this is merely
1579 cosmetic cleanup for debug output. */
1581 i.op[x].regs = i.op[x].regs + 8;
1587 add_prefix (REX_OPCODE | i.rex);
1589 /* We are ready to output the insn. */
1594 parse_insn (line, mnemonic)
1599 char *token_start = l;
1604 /* Non-zero if we found a prefix only acceptable with string insns. */
1605 const char *expecting_string_instruction = NULL;
1610 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1613 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1615 as_bad (_("no such instruction: `%s'"), token_start);
1620 if (!is_space_char (*l)
1621 && *l != END_OF_INSN
1623 || (*l != PREFIX_SEPARATOR
1626 as_bad (_("invalid character %s in mnemonic"),
1627 output_invalid (*l));
1630 if (token_start == l)
1632 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1633 as_bad (_("expecting prefix; got nothing"));
1635 as_bad (_("expecting mnemonic; got nothing"));
1639 /* Look up instruction (or prefix) via hash table. */
1640 current_templates = hash_find (op_hash, mnemonic);
1642 if (*l != END_OF_INSN
1643 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1644 && current_templates
1645 && (current_templates->start->opcode_modifier & IsPrefix))
1647 /* If we are in 16-bit mode, do not allow addr16 or data16.
1648 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1649 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1650 && flag_code != CODE_64BIT
1651 && (((current_templates->start->opcode_modifier & Size32) != 0)
1652 ^ (flag_code == CODE_16BIT)))
1654 as_bad (_("redundant %s prefix"),
1655 current_templates->start->name);
1658 /* Add prefix, checking for repeated prefixes. */
1659 switch (add_prefix (current_templates->start->base_opcode))
1664 expecting_string_instruction = current_templates->start->name;
1667 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1674 if (!current_templates)
1676 /* See if we can get a match by trimming off a suffix. */
1679 case WORD_MNEM_SUFFIX:
1680 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1681 i.suffix = SHORT_MNEM_SUFFIX;
1683 case BYTE_MNEM_SUFFIX:
1684 case QWORD_MNEM_SUFFIX:
1685 i.suffix = mnem_p[-1];
1687 current_templates = hash_find (op_hash, mnemonic);
1689 case SHORT_MNEM_SUFFIX:
1690 case LONG_MNEM_SUFFIX:
1693 i.suffix = mnem_p[-1];
1695 current_templates = hash_find (op_hash, mnemonic);
1703 if (intel_float_operand (mnemonic) == 1)
1704 i.suffix = SHORT_MNEM_SUFFIX;
1706 i.suffix = LONG_MNEM_SUFFIX;
1708 current_templates = hash_find (op_hash, mnemonic);
1712 if (!current_templates)
1714 as_bad (_("no such instruction: `%s'"), token_start);
1719 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1721 /* Check for a branch hint. We allow ",pt" and ",pn" for
1722 predict taken and predict not taken respectively.
1723 I'm not sure that branch hints actually do anything on loop
1724 and jcxz insns (JumpByte) for current Pentium4 chips. They
1725 may work in the future and it doesn't hurt to accept them
1727 if (l[0] == ',' && l[1] == 'p')
1731 if (!add_prefix (DS_PREFIX_OPCODE))
1735 else if (l[2] == 'n')
1737 if (!add_prefix (CS_PREFIX_OPCODE))
1743 /* Any other comma loses. */
1746 as_bad (_("invalid character %s in mnemonic"),
1747 output_invalid (*l));
1751 /* Check if instruction is supported on specified architecture. */
1753 for (t = current_templates->start; t < current_templates->end; ++t)
1755 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1756 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1758 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1761 if (!(supported & 2))
1763 as_bad (flag_code == CODE_64BIT
1764 ? _("`%s' is not supported in 64-bit mode")
1765 : _("`%s' is only supported in 64-bit mode"),
1766 current_templates->start->name);
1769 if (!(supported & 1))
1771 as_warn (_("`%s' is not supported on `%s%s'"),
1772 current_templates->start->name,
1774 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1776 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1778 as_warn (_("use .code16 to ensure correct addressing mode"));
1781 /* Check for rep/repne without a string instruction. */
1782 if (expecting_string_instruction)
1784 static templates override;
1786 for (t = current_templates->start; t < current_templates->end; ++t)
1787 if (t->opcode_modifier & IsString)
1789 if (t >= current_templates->end)
1791 as_bad (_("expecting string instruction after `%s'"),
1792 expecting_string_instruction);
1795 for (override.start = t; t < current_templates->end; ++t)
1796 if (!(t->opcode_modifier & IsString))
1799 current_templates = &override;
1806 parse_operands (l, mnemonic)
1808 const char *mnemonic;
1812 /* 1 if operand is pending after ','. */
1813 unsigned int expecting_operand = 0;
1815 /* Non-zero if operand parens not balanced. */
1816 unsigned int paren_not_balanced;
1818 while (*l != END_OF_INSN)
1820 /* Skip optional white space before operand. */
1821 if (is_space_char (*l))
1823 if (!is_operand_char (*l) && *l != END_OF_INSN)
1825 as_bad (_("invalid character %s before operand %d"),
1826 output_invalid (*l),
1830 token_start = l; /* after white space */
1831 paren_not_balanced = 0;
1832 while (paren_not_balanced || *l != ',')
1834 if (*l == END_OF_INSN)
1836 if (paren_not_balanced)
1839 as_bad (_("unbalanced parenthesis in operand %d."),
1842 as_bad (_("unbalanced brackets in operand %d."),
1847 break; /* we are done */
1849 else if (!is_operand_char (*l) && !is_space_char (*l))
1851 as_bad (_("invalid character %s in operand %d"),
1852 output_invalid (*l),
1859 ++paren_not_balanced;
1861 --paren_not_balanced;
1866 ++paren_not_balanced;
1868 --paren_not_balanced;
1872 if (l != token_start)
1873 { /* Yes, we've read in another operand. */
1874 unsigned int operand_ok;
1875 this_operand = i.operands++;
1876 if (i.operands > MAX_OPERANDS)
1878 as_bad (_("spurious operands; (%d operands/instruction max)"),
1882 /* Now parse operand adding info to 'i' as we go along. */
1883 END_STRING_AND_SAVE (l);
1887 i386_intel_operand (token_start,
1888 intel_float_operand (mnemonic));
1890 operand_ok = i386_operand (token_start);
1892 RESTORE_END_STRING (l);
1898 if (expecting_operand)
1900 expecting_operand_after_comma:
1901 as_bad (_("expecting operand after ','; got nothing"));
1906 as_bad (_("expecting operand before ','; got nothing"));
1911 /* Now *l must be either ',' or END_OF_INSN. */
1914 if (*++l == END_OF_INSN)
1916 /* Just skip it, if it's \n complain. */
1917 goto expecting_operand_after_comma;
1919 expecting_operand = 1;
1928 union i386_op temp_op;
1929 unsigned int temp_type;
1930 enum bfd_reloc_code_real temp_reloc;
1934 if (i.operands == 2)
1939 else if (i.operands == 3)
1944 temp_type = i.types[xchg2];
1945 i.types[xchg2] = i.types[xchg1];
1946 i.types[xchg1] = temp_type;
1947 temp_op = i.op[xchg2];
1948 i.op[xchg2] = i.op[xchg1];
1949 i.op[xchg1] = temp_op;
1950 temp_reloc = i.reloc[xchg2];
1951 i.reloc[xchg2] = i.reloc[xchg1];
1952 i.reloc[xchg1] = temp_reloc;
1954 if (i.mem_operands == 2)
1956 const seg_entry *temp_seg;
1957 temp_seg = i.seg[0];
1958 i.seg[0] = i.seg[1];
1959 i.seg[1] = temp_seg;
1963 /* Try to ensure constant immediates are represented in the smallest
1968 char guess_suffix = 0;
1972 guess_suffix = i.suffix;
1973 else if (i.reg_operands)
1975 /* Figure out a suffix from the last register operand specified.
1976 We can't do this properly yet, ie. excluding InOutPortReg,
1977 but the following works for instructions with immediates.
1978 In any case, we can't set i.suffix yet. */
1979 for (op = i.operands; --op >= 0;)
1980 if (i.types[op] & Reg)
1982 if (i.types[op] & Reg8)
1983 guess_suffix = BYTE_MNEM_SUFFIX;
1984 else if (i.types[op] & Reg16)
1985 guess_suffix = WORD_MNEM_SUFFIX;
1986 else if (i.types[op] & Reg32)
1987 guess_suffix = LONG_MNEM_SUFFIX;
1988 else if (i.types[op] & Reg64)
1989 guess_suffix = QWORD_MNEM_SUFFIX;
1993 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1994 guess_suffix = WORD_MNEM_SUFFIX;
1996 for (op = i.operands; --op >= 0;)
1997 if (i.types[op] & Imm)
1999 switch (i.op[op].imms->X_op)
2002 /* If a suffix is given, this operand may be shortened. */
2003 switch (guess_suffix)
2005 case LONG_MNEM_SUFFIX:
2006 i.types[op] |= Imm32 | Imm64;
2008 case WORD_MNEM_SUFFIX:
2009 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2011 case BYTE_MNEM_SUFFIX:
2012 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2016 /* If this operand is at most 16 bits, convert it
2017 to a signed 16 bit number before trying to see
2018 whether it will fit in an even smaller size.
2019 This allows a 16-bit operand such as $0xffe0 to
2020 be recognised as within Imm8S range. */
2021 if ((i.types[op] & Imm16)
2022 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2024 i.op[op].imms->X_add_number =
2025 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2027 if ((i.types[op] & Imm32)
2028 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2031 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2032 ^ ((offsetT) 1 << 31))
2033 - ((offsetT) 1 << 31));
2035 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2037 /* We must avoid matching of Imm32 templates when 64bit
2038 only immediate is available. */
2039 if (guess_suffix == QWORD_MNEM_SUFFIX)
2040 i.types[op] &= ~Imm32;
2047 /* Symbols and expressions. */
2049 /* Convert symbolic operand to proper sizes for matching. */
2050 switch (guess_suffix)
2052 case QWORD_MNEM_SUFFIX:
2053 i.types[op] = Imm64 | Imm32S;
2055 case LONG_MNEM_SUFFIX:
2056 i.types[op] = Imm32;
2058 case WORD_MNEM_SUFFIX:
2059 i.types[op] = Imm16;
2061 case BYTE_MNEM_SUFFIX:
2062 i.types[op] = Imm8 | Imm8S;
2070 /* Try to use the smallest displacement type too. */
2076 for (op = i.operands; --op >= 0;)
2077 if (i.types[op] & Disp)
2079 if (i.op[op].disps->X_op == O_constant)
2081 offsetT disp = i.op[op].disps->X_add_number;
2083 if ((i.types[op] & Disp16)
2084 && (disp & ~(offsetT) 0xffff) == 0)
2086 /* If this operand is at most 16 bits, convert
2087 to a signed 16 bit number and don't use 64bit
2089 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2090 i.types[op] &= ~Disp64;
2092 if ((i.types[op] & Disp32)
2093 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2095 /* If this operand is at most 32 bits, convert
2096 to a signed 32 bit number and don't use 64bit
2098 disp &= (((offsetT) 2 << 31) - 1);
2099 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2100 i.types[op] &= ~Disp64;
2102 if (!disp && (i.types[op] & BaseIndex))
2104 i.types[op] &= ~Disp;
2108 else if (flag_code == CODE_64BIT)
2110 if (fits_in_signed_long (disp))
2112 i.types[op] &= ~Disp64;
2113 i.types[op] |= Disp32S;
2115 if (fits_in_unsigned_long (disp))
2116 i.types[op] |= Disp32;
2118 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2119 && fits_in_signed_byte (disp))
2120 i.types[op] |= Disp8;
2123 /* We only support 64bit displacement on constants. */
2124 i.types[op] &= ~Disp64;
2131 /* Points to template once we've found it. */
2133 unsigned int overlap0, overlap1, overlap2;
2134 unsigned int found_reverse_match;
2137 #define MATCH(overlap, given, template) \
2138 ((overlap & ~JumpAbsolute) \
2139 && (((given) & (BaseIndex | JumpAbsolute)) \
2140 == ((overlap) & (BaseIndex | JumpAbsolute))))
2142 /* If given types r0 and r1 are registers they must be of the same type
2143 unless the expected operand type register overlap is null.
2144 Note that Acc in a template matches every size of reg. */
2145 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2146 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2147 || ((g0) & Reg) == ((g1) & Reg) \
2148 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2153 found_reverse_match = 0;
2154 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2156 : (i.suffix == WORD_MNEM_SUFFIX
2158 : (i.suffix == SHORT_MNEM_SUFFIX
2160 : (i.suffix == LONG_MNEM_SUFFIX
2162 : (i.suffix == QWORD_MNEM_SUFFIX
2164 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2165 ? No_xSuf : 0))))));
2167 t = current_templates->start;
2168 if (i.suffix == QWORD_MNEM_SUFFIX
2169 && flag_code != CODE_64BIT
2171 ? !(t->opcode_modifier & IgnoreSize)
2172 && !intel_float_operand (t->name)
2173 : intel_float_operand (t->name) != 2)
2174 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2175 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2176 && (t->base_opcode != 0x0fc7
2177 || t->extension_opcode != 1 /* cmpxchg8b */))
2178 t = current_templates->end;
2179 for (; t < current_templates->end; t++)
2181 /* Must have right number of operands. */
2182 if (i.operands != t->operands)
2185 /* Check the suffix, except for some instructions in intel mode. */
2186 if ((t->opcode_modifier & suffix_check)
2188 && (t->opcode_modifier & IgnoreSize)))
2191 /* Do not verify operands when there are none. */
2192 else if (!t->operands)
2194 if (t->cpu_flags & ~cpu_arch_flags)
2196 /* We've found a match; break out of loop. */
2200 overlap0 = i.types[0] & t->operand_types[0];
2201 switch (t->operands)
2204 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2209 overlap1 = i.types[1] & t->operand_types[1];
2210 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2211 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2212 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2213 t->operand_types[0],
2214 overlap1, i.types[1],
2215 t->operand_types[1]))
2217 /* Check if other direction is valid ... */
2218 if ((t->opcode_modifier & (D | FloatD)) == 0)
2221 /* Try reversing direction of operands. */
2222 overlap0 = i.types[0] & t->operand_types[1];
2223 overlap1 = i.types[1] & t->operand_types[0];
2224 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2225 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2226 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2227 t->operand_types[1],
2228 overlap1, i.types[1],
2229 t->operand_types[0]))
2231 /* Does not match either direction. */
2234 /* found_reverse_match holds which of D or FloatDR
2236 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2238 /* Found a forward 2 operand match here. */
2239 else if (t->operands == 3)
2241 /* Here we make use of the fact that there are no
2242 reverse match 3 operand instructions, and all 3
2243 operand instructions only need to be checked for
2244 register consistency between operands 2 and 3. */
2245 overlap2 = i.types[2] & t->operand_types[2];
2246 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2247 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2248 t->operand_types[1],
2249 overlap2, i.types[2],
2250 t->operand_types[2]))
2254 /* Found either forward/reverse 2 or 3 operand match here:
2255 slip through to break. */
2257 if (t->cpu_flags & ~cpu_arch_flags)
2259 found_reverse_match = 0;
2262 /* We've found a match; break out of loop. */
2266 if (t == current_templates->end)
2268 /* We found no match. */
2269 as_bad (_("suffix or operands invalid for `%s'"),
2270 current_templates->start->name);
2274 if (!quiet_warnings)
2277 && ((i.types[0] & JumpAbsolute)
2278 != (t->operand_types[0] & JumpAbsolute)))
2280 as_warn (_("indirect %s without `*'"), t->name);
2283 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2284 == (IsPrefix | IgnoreSize))
2286 /* Warn them that a data or address size prefix doesn't
2287 affect assembly of the next line of code. */
2288 as_warn (_("stand-alone `%s' prefix"), t->name);
2292 /* Copy the template we found. */
2294 if (found_reverse_match)
2296 /* If we found a reverse match we must alter the opcode
2297 direction bit. found_reverse_match holds bits to change
2298 (different for int & float insns). */
2300 i.tm.base_opcode ^= found_reverse_match;
2302 i.tm.operand_types[0] = t->operand_types[1];
2303 i.tm.operand_types[1] = t->operand_types[0];
2312 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2313 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2315 if (i.seg[0] != NULL && i.seg[0] != &es)
2317 as_bad (_("`%s' operand %d must use `%%es' segment"),
2322 /* There's only ever one segment override allowed per instruction.
2323 This instruction possibly has a legal segment override on the
2324 second operand, so copy the segment to where non-string
2325 instructions store it, allowing common code. */
2326 i.seg[0] = i.seg[1];
2328 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2330 if (i.seg[1] != NULL && i.seg[1] != &es)
2332 as_bad (_("`%s' operand %d must use `%%es' segment"),
2342 process_suffix (void)
2344 /* If matched instruction specifies an explicit instruction mnemonic
2346 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2348 if (i.tm.opcode_modifier & Size16)
2349 i.suffix = WORD_MNEM_SUFFIX;
2350 else if (i.tm.opcode_modifier & Size64)
2351 i.suffix = QWORD_MNEM_SUFFIX;
2353 i.suffix = LONG_MNEM_SUFFIX;
2355 else if (i.reg_operands)
2357 /* If there's no instruction mnemonic suffix we try to invent one
2358 based on register operands. */
2361 /* We take i.suffix from the last register operand specified,
2362 Destination register type is more significant than source
2366 for (op = i.operands; --op >= 0;)
2367 if ((i.types[op] & Reg)
2368 && !(i.tm.operand_types[op] & InOutPortReg))
2370 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2371 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2372 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2377 else if (i.suffix == BYTE_MNEM_SUFFIX)
2379 if (!check_byte_reg ())
2382 else if (i.suffix == LONG_MNEM_SUFFIX)
2384 if (!check_long_reg ())
2387 else if (i.suffix == QWORD_MNEM_SUFFIX)
2389 if (!check_qword_reg ())
2392 else if (i.suffix == WORD_MNEM_SUFFIX)
2394 if (!check_word_reg ())
2397 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2398 /* Do nothing if the instruction is going to ignore the prefix. */
2403 else if ((i.tm.opcode_modifier & DefaultSize)
2405 /* exclude fldenv/frstor/fsave/fstenv */
2406 && (i.tm.opcode_modifier & No_sSuf))
2408 i.suffix = stackop_size;
2410 else if (intel_syntax
2412 && ((i.tm.operand_types[0] & JumpAbsolute)
2413 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2414 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2415 && i.tm.extension_opcode <= 3)))
2420 if (!(i.tm.opcode_modifier & No_qSuf))
2422 i.suffix = QWORD_MNEM_SUFFIX;
2426 if (!(i.tm.opcode_modifier & No_lSuf))
2427 i.suffix = LONG_MNEM_SUFFIX;
2430 if (!(i.tm.opcode_modifier & No_wSuf))
2431 i.suffix = WORD_MNEM_SUFFIX;
2440 if (i.tm.opcode_modifier & W)
2442 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2448 unsigned int suffixes = ~i.tm.opcode_modifier
2456 if ((i.tm.opcode_modifier & W)
2457 || ((suffixes & (suffixes - 1))
2458 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2460 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2466 /* Change the opcode based on the operand size given by i.suffix;
2467 We don't need to change things for byte insns. */
2469 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2471 /* It's not a byte, select word/dword operation. */
2472 if (i.tm.opcode_modifier & W)
2474 if (i.tm.opcode_modifier & ShortForm)
2475 i.tm.base_opcode |= 8;
2477 i.tm.base_opcode |= 1;
2480 /* Now select between word & dword operations via the operand
2481 size prefix, except for instructions that will ignore this
2483 if (i.suffix != QWORD_MNEM_SUFFIX
2484 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2485 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2486 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2487 || (flag_code == CODE_64BIT
2488 && (i.tm.opcode_modifier & JumpByte))))
2490 unsigned int prefix = DATA_PREFIX_OPCODE;
2492 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2493 prefix = ADDR_PREFIX_OPCODE;
2495 if (!add_prefix (prefix))
2499 /* Set mode64 for an operand. */
2500 if (i.suffix == QWORD_MNEM_SUFFIX
2501 && flag_code == CODE_64BIT
2502 && (i.tm.opcode_modifier & NoRex64) == 0)
2503 i.rex |= REX_MODE64;
2505 /* Size floating point instruction. */
2506 if (i.suffix == LONG_MNEM_SUFFIX)
2507 if (i.tm.opcode_modifier & FloatMF)
2508 i.tm.base_opcode ^= 4;
2515 check_byte_reg (void)
2519 for (op = i.operands; --op >= 0;)
2521 /* If this is an eight bit register, it's OK. If it's the 16 or
2522 32 bit version of an eight bit register, we will just use the
2523 low portion, and that's OK too. */
2524 if (i.types[op] & Reg8)
2527 /* movzx and movsx should not generate this warning. */
2529 && (i.tm.base_opcode == 0xfb7
2530 || i.tm.base_opcode == 0xfb6
2531 || i.tm.base_opcode == 0x63
2532 || i.tm.base_opcode == 0xfbe
2533 || i.tm.base_opcode == 0xfbf))
2536 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2538 /* Prohibit these changes in the 64bit mode, since the
2539 lowering is more complicated. */
2540 if (flag_code == CODE_64BIT
2541 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2543 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2544 i.op[op].regs->reg_name,
2548 #if REGISTER_WARNINGS
2550 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2551 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2552 (i.op[op].regs + (i.types[op] & Reg16
2553 ? REGNAM_AL - REGNAM_AX
2554 : REGNAM_AL - REGNAM_EAX))->reg_name,
2555 i.op[op].regs->reg_name,
2560 /* Any other register is bad. */
2561 if (i.types[op] & (Reg | RegMMX | RegXMM
2563 | Control | Debug | Test
2564 | FloatReg | FloatAcc))
2566 as_bad (_("`%%%s' not allowed with `%s%c'"),
2567 i.op[op].regs->reg_name,
2581 for (op = i.operands; --op >= 0;)
2582 /* Reject eight bit registers, except where the template requires
2583 them. (eg. movzb) */
2584 if ((i.types[op] & Reg8) != 0
2585 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2587 as_bad (_("`%%%s' not allowed with `%s%c'"),
2588 i.op[op].regs->reg_name,
2593 /* Warn if the e prefix on a general reg is missing. */
2594 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2595 && (i.types[op] & Reg16) != 0
2596 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2598 /* Prohibit these changes in the 64bit mode, since the
2599 lowering is more complicated. */
2600 if (flag_code == CODE_64BIT)
2602 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2603 i.op[op].regs->reg_name,
2607 #if REGISTER_WARNINGS
2609 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2610 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2611 i.op[op].regs->reg_name,
2615 /* Warn if the r prefix on a general reg is missing. */
2616 else if ((i.types[op] & Reg64) != 0
2617 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2619 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2620 i.op[op].regs->reg_name,
2632 for (op = i.operands; --op >= 0; )
2633 /* Reject eight bit registers, except where the template requires
2634 them. (eg. movzb) */
2635 if ((i.types[op] & Reg8) != 0
2636 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2638 as_bad (_("`%%%s' not allowed with `%s%c'"),
2639 i.op[op].regs->reg_name,
2644 /* Warn if the e prefix on a general reg is missing. */
2645 else if (((i.types[op] & Reg16) != 0
2646 || (i.types[op] & Reg32) != 0)
2647 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2649 /* Prohibit these changes in the 64bit mode, since the
2650 lowering is more complicated. */
2651 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2652 i.op[op].regs->reg_name,
2663 for (op = i.operands; --op >= 0;)
2664 /* Reject eight bit registers, except where the template requires
2665 them. (eg. movzb) */
2666 if ((i.types[op] & Reg8) != 0
2667 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2669 as_bad (_("`%%%s' not allowed with `%s%c'"),
2670 i.op[op].regs->reg_name,
2675 /* Warn if the e prefix on a general reg is present. */
2676 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2677 && (i.types[op] & Reg32) != 0
2678 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2680 /* Prohibit these changes in the 64bit mode, since the
2681 lowering is more complicated. */
2682 if (flag_code == CODE_64BIT)
2684 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2685 i.op[op].regs->reg_name,
2690 #if REGISTER_WARNINGS
2691 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2692 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2693 i.op[op].regs->reg_name,
2703 unsigned int overlap0, overlap1, overlap2;
2705 overlap0 = i.types[0] & i.tm.operand_types[0];
2706 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2707 && overlap0 != Imm8 && overlap0 != Imm8S
2708 && overlap0 != Imm16 && overlap0 != Imm32S
2709 && overlap0 != Imm32 && overlap0 != Imm64)
2713 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2715 : (i.suffix == WORD_MNEM_SUFFIX
2717 : (i.suffix == QWORD_MNEM_SUFFIX
2721 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2722 || overlap0 == (Imm16 | Imm32)
2723 || overlap0 == (Imm16 | Imm32S))
2725 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2728 if (overlap0 != Imm8 && overlap0 != Imm8S
2729 && overlap0 != Imm16 && overlap0 != Imm32S
2730 && overlap0 != Imm32 && overlap0 != Imm64)
2732 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2736 i.types[0] = overlap0;
2738 overlap1 = i.types[1] & i.tm.operand_types[1];
2739 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2740 && overlap1 != Imm8 && overlap1 != Imm8S
2741 && overlap1 != Imm16 && overlap1 != Imm32S
2742 && overlap1 != Imm32 && overlap1 != Imm64)
2746 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2748 : (i.suffix == WORD_MNEM_SUFFIX
2750 : (i.suffix == QWORD_MNEM_SUFFIX
2754 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2755 || overlap1 == (Imm16 | Imm32)
2756 || overlap1 == (Imm16 | Imm32S))
2758 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2761 if (overlap1 != Imm8 && overlap1 != Imm8S
2762 && overlap1 != Imm16 && overlap1 != Imm32S
2763 && overlap1 != Imm32 && overlap1 != Imm64)
2765 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2769 i.types[1] = overlap1;
2771 overlap2 = i.types[2] & i.tm.operand_types[2];
2772 assert ((overlap2 & Imm) == 0);
2773 i.types[2] = overlap2;
2781 /* Default segment register this instruction will use for memory
2782 accesses. 0 means unknown. This is only for optimizing out
2783 unnecessary segment overrides. */
2784 const seg_entry *default_seg = 0;
2786 /* The imul $imm, %reg instruction is converted into
2787 imul $imm, %reg, %reg, and the clr %reg instruction
2788 is converted into xor %reg, %reg. */
2789 if (i.tm.opcode_modifier & regKludge)
2791 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2792 /* Pretend we saw the extra register operand. */
2793 assert (i.op[first_reg_op + 1].regs == 0);
2794 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2795 i.types[first_reg_op + 1] = i.types[first_reg_op];
2799 if (i.tm.opcode_modifier & ShortForm)
2801 /* The register or float register operand is in operand 0 or 1. */
2802 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2803 /* Register goes in low 3 bits of opcode. */
2804 i.tm.base_opcode |= i.op[op].regs->reg_num;
2805 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2807 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2809 /* Warn about some common errors, but press on regardless.
2810 The first case can be generated by gcc (<= 2.8.1). */
2811 if (i.operands == 2)
2813 /* Reversed arguments on faddp, fsubp, etc. */
2814 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2815 i.op[1].regs->reg_name,
2816 i.op[0].regs->reg_name);
2820 /* Extraneous `l' suffix on fp insn. */
2821 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2822 i.op[0].regs->reg_name);
2826 else if (i.tm.opcode_modifier & Modrm)
2828 /* The opcode is completed (modulo i.tm.extension_opcode which
2829 must be put into the modrm byte). Now, we make the modrm and
2830 index base bytes based on all the info we've collected. */
2832 default_seg = build_modrm_byte ();
2834 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2836 if (i.tm.base_opcode == POP_SEG_SHORT
2837 && i.op[0].regs->reg_num == 1)
2839 as_bad (_("you can't `pop %%cs'"));
2842 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2843 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2846 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2850 else if ((i.tm.opcode_modifier & IsString) != 0)
2852 /* For the string instructions that allow a segment override
2853 on one of their operands, the default segment is ds. */
2857 if ((i.tm.base_opcode == 0x8d /* lea */
2858 || (i.tm.cpu_flags & CpuSVME))
2859 && i.seg[0] && !quiet_warnings)
2860 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
2862 /* If a segment was explicitly specified, and the specified segment
2863 is not the default, use an opcode prefix to select it. If we
2864 never figured out what the default segment is, then default_seg
2865 will be zero at this point, and the specified segment prefix will
2867 if ((i.seg[0]) && (i.seg[0] != default_seg))
2869 if (!add_prefix (i.seg[0]->seg_prefix))
2875 static const seg_entry *
2878 const seg_entry *default_seg = 0;
2880 /* i.reg_operands MUST be the number of real register operands;
2881 implicit registers do not count. */
2882 if (i.reg_operands == 2)
2884 unsigned int source, dest;
2885 source = ((i.types[0]
2886 & (Reg | RegMMX | RegXMM
2888 | Control | Debug | Test))
2893 /* One of the register operands will be encoded in the i.tm.reg
2894 field, the other in the combined i.tm.mode and i.tm.regmem
2895 fields. If no form of this instruction supports a memory
2896 destination operand, then we assume the source operand may
2897 sometimes be a memory operand and so we need to store the
2898 destination in the i.rm.reg field. */
2899 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2901 i.rm.reg = i.op[dest].regs->reg_num;
2902 i.rm.regmem = i.op[source].regs->reg_num;
2903 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2905 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2910 i.rm.reg = i.op[source].regs->reg_num;
2911 i.rm.regmem = i.op[dest].regs->reg_num;
2912 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2914 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2917 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2919 if (!((i.types[0] | i.types[1]) & Control))
2921 i.rex &= ~(REX_EXTX | REX_EXTZ);
2922 add_prefix (LOCK_PREFIX_OPCODE);
2926 { /* If it's not 2 reg operands... */
2929 unsigned int fake_zero_displacement = 0;
2930 unsigned int op = ((i.types[0] & AnyMem)
2932 : (i.types[1] & AnyMem) ? 1 : 2);
2936 if (i.base_reg == 0)
2939 if (!i.disp_operands)
2940 fake_zero_displacement = 1;
2941 if (i.index_reg == 0)
2943 /* Operand is just <disp> */
2944 if (flag_code == CODE_64BIT)
2946 /* 64bit mode overwrites the 32bit absolute
2947 addressing by RIP relative addressing and
2948 absolute addressing is encoded by one of the
2949 redundant SIB forms. */
2950 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2951 i.sib.base = NO_BASE_REGISTER;
2952 i.sib.index = NO_INDEX_REGISTER;
2953 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2955 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2957 i.rm.regmem = NO_BASE_REGISTER_16;
2958 i.types[op] = Disp16;
2962 i.rm.regmem = NO_BASE_REGISTER;
2963 i.types[op] = Disp32;
2966 else /* !i.base_reg && i.index_reg */
2968 i.sib.index = i.index_reg->reg_num;
2969 i.sib.base = NO_BASE_REGISTER;
2970 i.sib.scale = i.log2_scale_factor;
2971 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2972 i.types[op] &= ~Disp;
2973 if (flag_code != CODE_64BIT)
2974 i.types[op] |= Disp32; /* Must be 32 bit */
2976 i.types[op] |= Disp32S;
2977 if ((i.index_reg->reg_flags & RegRex) != 0)
2981 /* RIP addressing for 64bit mode. */
2982 else if (i.base_reg->reg_type == BaseIndex)
2984 i.rm.regmem = NO_BASE_REGISTER;
2985 i.types[op] &= ~ Disp;
2986 i.types[op] |= Disp32S;
2987 i.flags[op] = Operand_PCrel;
2988 if (! i.disp_operands)
2989 fake_zero_displacement = 1;
2991 else if (i.base_reg->reg_type & Reg16)
2993 switch (i.base_reg->reg_num)
2996 if (i.index_reg == 0)
2998 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2999 i.rm.regmem = i.index_reg->reg_num - 6;
3003 if (i.index_reg == 0)
3006 if ((i.types[op] & Disp) == 0)
3008 /* fake (%bp) into 0(%bp) */
3009 i.types[op] |= Disp8;
3010 fake_zero_displacement = 1;
3013 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3014 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3016 default: /* (%si) -> 4 or (%di) -> 5 */
3017 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3019 i.rm.mode = mode_from_disp_size (i.types[op]);
3021 else /* i.base_reg and 32/64 bit mode */
3023 if (flag_code == CODE_64BIT
3024 && (i.types[op] & Disp))
3025 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3027 i.rm.regmem = i.base_reg->reg_num;
3028 if ((i.base_reg->reg_flags & RegRex) != 0)
3030 i.sib.base = i.base_reg->reg_num;
3031 /* x86-64 ignores REX prefix bit here to avoid decoder
3033 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3036 if (i.disp_operands == 0)
3038 fake_zero_displacement = 1;
3039 i.types[op] |= Disp8;
3042 else if (i.base_reg->reg_num == ESP_REG_NUM)
3046 i.sib.scale = i.log2_scale_factor;
3047 if (i.index_reg == 0)
3049 /* <disp>(%esp) becomes two byte modrm with no index
3050 register. We've already stored the code for esp
3051 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3052 Any base register besides %esp will not use the
3053 extra modrm byte. */
3054 i.sib.index = NO_INDEX_REGISTER;
3055 #if !SCALE1_WHEN_NO_INDEX
3056 /* Another case where we force the second modrm byte. */
3057 if (i.log2_scale_factor)
3058 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3063 i.sib.index = i.index_reg->reg_num;
3064 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3065 if ((i.index_reg->reg_flags & RegRex) != 0)
3068 i.rm.mode = mode_from_disp_size (i.types[op]);
3071 if (fake_zero_displacement)
3073 /* Fakes a zero displacement assuming that i.types[op]
3074 holds the correct displacement size. */
3077 assert (i.op[op].disps == 0);
3078 exp = &disp_expressions[i.disp_operands++];
3079 i.op[op].disps = exp;
3080 exp->X_op = O_constant;
3081 exp->X_add_number = 0;
3082 exp->X_add_symbol = (symbolS *) 0;
3083 exp->X_op_symbol = (symbolS *) 0;
3087 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3088 (if any) based on i.tm.extension_opcode. Again, we must be
3089 careful to make sure that segment/control/debug/test/MMX
3090 registers are coded into the i.rm.reg field. */
3095 & (Reg | RegMMX | RegXMM
3097 | Control | Debug | Test))
3100 & (Reg | RegMMX | RegXMM
3102 | Control | Debug | Test))
3105 /* If there is an extension opcode to put here, the register
3106 number must be put into the regmem field. */
3107 if (i.tm.extension_opcode != None)
3109 i.rm.regmem = i.op[op].regs->reg_num;
3110 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3115 i.rm.reg = i.op[op].regs->reg_num;
3116 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3120 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3121 must set it to 3 to indicate this is a register operand
3122 in the regmem field. */
3123 if (!i.mem_operands)
3127 /* Fill in i.rm.reg field with extension opcode (if any). */
3128 if (i.tm.extension_opcode != None)
3129 i.rm.reg = i.tm.extension_opcode;
3140 relax_substateT subtype;
3145 if (flag_code == CODE_16BIT)
3149 if (i.prefix[DATA_PREFIX] != 0)
3155 /* Pentium4 branch hints. */
3156 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3157 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3162 if (i.prefix[REX_PREFIX] != 0)
3168 if (i.prefixes != 0 && !intel_syntax)
3169 as_warn (_("skipping prefixes on this instruction"));
3171 /* It's always a symbol; End frag & setup for relax.
3172 Make sure there is enough room in this frag for the largest
3173 instruction we may generate in md_convert_frag. This is 2
3174 bytes for the opcode and room for the prefix and largest
3176 frag_grow (prefix + 2 + 4);
3177 /* Prefix and 1 opcode byte go in fr_fix. */
3178 p = frag_more (prefix + 1);
3179 if (i.prefix[DATA_PREFIX] != 0)
3180 *p++ = DATA_PREFIX_OPCODE;
3181 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3182 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3183 *p++ = i.prefix[SEG_PREFIX];
3184 if (i.prefix[REX_PREFIX] != 0)
3185 *p++ = i.prefix[REX_PREFIX];
3186 *p = i.tm.base_opcode;
3188 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3189 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3190 else if ((cpu_arch_flags & Cpu386) != 0)
3191 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3193 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3196 sym = i.op[0].disps->X_add_symbol;
3197 off = i.op[0].disps->X_add_number;
3199 if (i.op[0].disps->X_op != O_constant
3200 && i.op[0].disps->X_op != O_symbol)
3202 /* Handle complex expressions. */
3203 sym = make_expr_symbol (i.op[0].disps);
3207 /* 1 possible extra opcode + 4 byte displacement go in var part.
3208 Pass reloc in fr_var. */
3209 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3219 if (i.tm.opcode_modifier & JumpByte)
3221 /* This is a loop or jecxz type instruction. */
3223 if (i.prefix[ADDR_PREFIX] != 0)
3225 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3228 /* Pentium4 branch hints. */
3229 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3230 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3232 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3241 if (flag_code == CODE_16BIT)
3244 if (i.prefix[DATA_PREFIX] != 0)
3246 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3256 if (i.prefix[REX_PREFIX] != 0)
3258 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3262 if (i.prefixes != 0 && !intel_syntax)
3263 as_warn (_("skipping prefixes on this instruction"));
3265 p = frag_more (1 + size);
3266 *p++ = i.tm.base_opcode;
3268 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3269 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3271 /* All jumps handled here are signed, but don't use a signed limit
3272 check for 32 and 16 bit jumps as we want to allow wrap around at
3273 4G and 64k respectively. */
3275 fixP->fx_signed = 1;
3279 output_interseg_jump ()
3287 if (flag_code == CODE_16BIT)
3291 if (i.prefix[DATA_PREFIX] != 0)
3297 if (i.prefix[REX_PREFIX] != 0)
3307 if (i.prefixes != 0 && !intel_syntax)
3308 as_warn (_("skipping prefixes on this instruction"));
3310 /* 1 opcode; 2 segment; offset */
3311 p = frag_more (prefix + 1 + 2 + size);
3313 if (i.prefix[DATA_PREFIX] != 0)
3314 *p++ = DATA_PREFIX_OPCODE;
3316 if (i.prefix[REX_PREFIX] != 0)
3317 *p++ = i.prefix[REX_PREFIX];
3319 *p++ = i.tm.base_opcode;
3320 if (i.op[1].imms->X_op == O_constant)
3322 offsetT n = i.op[1].imms->X_add_number;
3325 && !fits_in_unsigned_word (n)
3326 && !fits_in_signed_word (n))
3328 as_bad (_("16-bit jump out of range"));
3331 md_number_to_chars (p, n, size);
3334 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3335 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3336 if (i.op[0].imms->X_op != O_constant)
3337 as_bad (_("can't handle non absolute segment in `%s'"),
3339 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3345 fragS *insn_start_frag;
3346 offsetT insn_start_off;
3348 /* Tie dwarf2 debug info to the address at the start of the insn.
3349 We can't do this after the insn has been output as the current
3350 frag may have been closed off. eg. by frag_var. */
3351 dwarf2_emit_insn (0);
3353 insn_start_frag = frag_now;
3354 insn_start_off = frag_now_fix ();
3357 if (i.tm.opcode_modifier & Jump)
3359 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3361 else if (i.tm.opcode_modifier & JumpInterSegment)
3362 output_interseg_jump ();
3365 /* Output normal instructions here. */
3369 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3370 more higher byte to specify a prefix the instruction
3372 if ((i.tm.base_opcode & 0xff0000) != 0)
3374 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3376 unsigned int prefix;
3377 prefix = (i.tm.base_opcode >> 16) & 0xff;
3379 if (prefix != REPE_PREFIX_OPCODE
3380 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3381 add_prefix (prefix);
3384 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3387 /* The prefix bytes. */
3389 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3395 md_number_to_chars (p, (valueT) *q, 1);
3399 /* Now the opcode; be careful about word order here! */
3400 if (fits_in_unsigned_byte (i.tm.base_opcode))
3402 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3408 /* Put out high byte first: can't use md_number_to_chars! */
3409 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3410 *p = i.tm.base_opcode & 0xff;
3413 /* Now the modrm byte and sib byte (if present). */
3414 if (i.tm.opcode_modifier & Modrm)
3417 md_number_to_chars (p,
3418 (valueT) (i.rm.regmem << 0
3422 /* If i.rm.regmem == ESP (4)
3423 && i.rm.mode != (Register mode)
3425 ==> need second modrm byte. */
3426 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3428 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3431 md_number_to_chars (p,
3432 (valueT) (i.sib.base << 0
3434 | i.sib.scale << 6),
3439 if (i.disp_operands)
3440 output_disp (insn_start_frag, insn_start_off);
3443 output_imm (insn_start_frag, insn_start_off);
3451 #endif /* DEBUG386 */
3455 output_disp (insn_start_frag, insn_start_off)
3456 fragS *insn_start_frag;
3457 offsetT insn_start_off;
3462 for (n = 0; n < i.operands; n++)
3464 if (i.types[n] & Disp)
3466 if (i.op[n].disps->X_op == O_constant)
3472 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3475 if (i.types[n] & Disp8)
3477 if (i.types[n] & Disp64)
3480 val = offset_in_range (i.op[n].disps->X_add_number,
3482 p = frag_more (size);
3483 md_number_to_chars (p, val, size);
3487 enum bfd_reloc_code_real reloc_type;
3490 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3492 /* The PC relative address is computed relative
3493 to the instruction boundary, so in case immediate
3494 fields follows, we need to adjust the value. */
3495 if (pcrel && i.imm_operands)
3500 for (n1 = 0; n1 < i.operands; n1++)
3501 if (i.types[n1] & Imm)
3503 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3506 if (i.types[n1] & (Imm8 | Imm8S))
3508 if (i.types[n1] & Imm64)
3513 /* We should find the immediate. */
3514 if (n1 == i.operands)
3516 i.op[n].disps->X_add_number -= imm_size;
3519 if (i.types[n] & Disp32S)
3522 if (i.types[n] & (Disp16 | Disp64))
3525 if (i.types[n] & Disp64)
3529 p = frag_more (size);
3530 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3532 && GOT_symbol == i.op[n].disps->X_add_symbol
3533 && (((reloc_type == BFD_RELOC_32
3534 || reloc_type == BFD_RELOC_X86_64_32S)
3535 && (i.op[n].disps->X_op == O_symbol
3536 || (i.op[n].disps->X_op == O_add
3537 && ((symbol_get_value_expression
3538 (i.op[n].disps->X_op_symbol)->X_op)
3540 || reloc_type == BFD_RELOC_32_PCREL))
3544 if (insn_start_frag == frag_now)
3545 add = (p - frag_now->fr_literal) - insn_start_off;
3550 add = insn_start_frag->fr_fix - insn_start_off;
3551 for (fr = insn_start_frag->fr_next;
3552 fr && fr != frag_now; fr = fr->fr_next)
3554 add += p - frag_now->fr_literal;
3557 if (flag_code != CODE_64BIT)
3558 reloc_type = BFD_RELOC_386_GOTPC;
3560 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3561 i.op[n].disps->X_add_number += add;
3563 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3564 i.op[n].disps, pcrel, reloc_type);
3571 output_imm (insn_start_frag, insn_start_off)
3572 fragS *insn_start_frag;
3573 offsetT insn_start_off;
3578 for (n = 0; n < i.operands; n++)
3580 if (i.types[n] & Imm)
3582 if (i.op[n].imms->X_op == O_constant)
3588 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3591 if (i.types[n] & (Imm8 | Imm8S))
3593 else if (i.types[n] & Imm64)
3596 val = offset_in_range (i.op[n].imms->X_add_number,
3598 p = frag_more (size);
3599 md_number_to_chars (p, val, size);
3603 /* Not absolute_section.
3604 Need a 32-bit fixup (don't support 8bit
3605 non-absolute imms). Try to support other
3607 enum bfd_reloc_code_real reloc_type;
3611 if ((i.types[n] & (Imm32S))
3612 && (i.suffix == QWORD_MNEM_SUFFIX
3613 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
3615 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3618 if (i.types[n] & (Imm8 | Imm8S))
3620 if (i.types[n] & Imm64)
3624 p = frag_more (size);
3625 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3627 /* This is tough to explain. We end up with this one if we
3628 * have operands that look like
3629 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3630 * obtain the absolute address of the GOT, and it is strongly
3631 * preferable from a performance point of view to avoid using
3632 * a runtime relocation for this. The actual sequence of
3633 * instructions often look something like:
3638 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3640 * The call and pop essentially return the absolute address
3641 * of the label .L66 and store it in %ebx. The linker itself
3642 * will ultimately change the first operand of the addl so
3643 * that %ebx points to the GOT, but to keep things simple, the
3644 * .o file must have this operand set so that it generates not
3645 * the absolute address of .L66, but the absolute address of
3646 * itself. This allows the linker itself simply treat a GOTPC
3647 * relocation as asking for a pcrel offset to the GOT to be
3648 * added in, and the addend of the relocation is stored in the
3649 * operand field for the instruction itself.
3651 * Our job here is to fix the operand so that it would add
3652 * the correct offset so that %ebx would point to itself. The
3653 * thing that is tricky is that .-.L66 will point to the
3654 * beginning of the instruction, so we need to further modify
3655 * the operand so that it will point to itself. There are
3656 * other cases where you have something like:
3658 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3660 * and here no correction would be required. Internally in
3661 * the assembler we treat operands of this form as not being
3662 * pcrel since the '.' is explicitly mentioned, and I wonder
3663 * whether it would simplify matters to do it this way. Who
3664 * knows. In earlier versions of the PIC patches, the
3665 * pcrel_adjust field was used to store the correction, but
3666 * since the expression is not pcrel, I felt it would be
3667 * confusing to do it this way. */
3669 if ((reloc_type == BFD_RELOC_32
3670 || reloc_type == BFD_RELOC_X86_64_32S)
3672 && GOT_symbol == i.op[n].imms->X_add_symbol
3673 && (i.op[n].imms->X_op == O_symbol
3674 || (i.op[n].imms->X_op == O_add
3675 && ((symbol_get_value_expression
3676 (i.op[n].imms->X_op_symbol)->X_op)
3681 if (insn_start_frag == frag_now)
3682 add = (p - frag_now->fr_literal) - insn_start_off;
3687 add = insn_start_frag->fr_fix - insn_start_off;
3688 for (fr = insn_start_frag->fr_next;
3689 fr && fr != frag_now; fr = fr->fr_next)
3691 add += p - frag_now->fr_literal;
3694 if (flag_code != CODE_64BIT)
3695 reloc_type = BFD_RELOC_386_GOTPC;
3697 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3698 i.op[n].imms->X_add_number += add;
3700 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3701 i.op[n].imms, 0, reloc_type);
3708 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
3710 /* Parse operands of the form
3711 <symbol>@GOTOFF+<nnn>
3712 and similar .plt or .got references.
3714 If we find one, set up the correct relocation in RELOC and copy the
3715 input string, minus the `@GOTOFF' into a malloc'd buffer for
3716 parsing by the calling routine. Return this buffer, and if ADJUST
3717 is non-null set it to the length of the string we removed from the
3718 input line. Otherwise return NULL. */
3720 lex_got (reloc, adjust)
3721 enum bfd_reloc_code_real *reloc;
3724 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3725 static const struct {
3727 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3729 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3730 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 } },
3731 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3732 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
3733 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3734 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3735 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3736 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
3737 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3738 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
3739 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3740 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
3741 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3746 for (cp = input_line_pointer; *cp != '@'; cp++)
3747 if (is_end_of_line[(unsigned char) *cp])
3750 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3754 len = strlen (gotrel[j].str);
3755 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3757 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3760 char *tmpbuf, *past_reloc;
3762 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3766 if (GOT_symbol == NULL)
3767 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3769 /* Replace the relocation token with ' ', so that
3770 errors like foo@GOTOFF1 will be detected. */
3772 /* The length of the first part of our input line. */
3773 first = cp - input_line_pointer;
3775 /* The second part goes from after the reloc token until
3776 (and including) an end_of_line char. Don't use strlen
3777 here as the end_of_line char may not be a NUL. */
3778 past_reloc = cp + 1 + len;
3779 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3781 second = cp - past_reloc;
3783 /* Allocate and copy string. The trailing NUL shouldn't
3784 be necessary, but be safe. */
3785 tmpbuf = xmalloc (first + second + 2);
3786 memcpy (tmpbuf, input_line_pointer, first);
3787 tmpbuf[first] = ' ';
3788 memcpy (tmpbuf + first + 1, past_reloc, second);
3789 tmpbuf[first + second + 1] = '\0';
3793 as_bad (_("@%s reloc is not supported in %s bit mode"),
3794 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3799 /* Might be a symbol version string. Don't as_bad here. */
3803 /* x86_cons_fix_new is called via the expression parsing code when a
3804 reloc is needed. We use this hook to get the correct .got reloc. */
3805 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3808 x86_cons_fix_new (frag, off, len, exp)
3814 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
3815 got_reloc = NO_RELOC;
3816 fix_new_exp (frag, off, len, exp, 0, r);
3820 x86_cons (exp, size)
3824 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
3826 /* Handle @GOTOFF and the like in an expression. */
3828 char *gotfree_input_line;
3831 save = input_line_pointer;
3832 gotfree_input_line = lex_got (&got_reloc, &adjust);
3833 if (gotfree_input_line)
3834 input_line_pointer = gotfree_input_line;
3838 if (gotfree_input_line)
3840 /* expression () has merrily parsed up to the end of line,
3841 or a comma - in the wrong buffer. Transfer how far
3842 input_line_pointer has moved to the right buffer. */
3843 input_line_pointer = (save
3844 + (input_line_pointer - gotfree_input_line)
3846 free (gotfree_input_line);
3857 x86_pe_cons_fix_new (frag, off, len, exp)
3863 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3865 if (exp->X_op == O_secrel)
3867 exp->X_op = O_symbol;
3868 r = BFD_RELOC_32_SECREL;
3871 fix_new_exp (frag, off, len, exp, 0, r);
3875 pe_directive_secrel (dummy)
3876 int dummy ATTRIBUTE_UNUSED;
3883 if (exp.X_op == O_symbol)
3884 exp.X_op = O_secrel;
3886 emit_expr (&exp, 4);
3888 while (*input_line_pointer++ == ',');
3890 input_line_pointer--;
3891 demand_empty_rest_of_line ();
3896 static int i386_immediate PARAMS ((char *));
3899 i386_immediate (imm_start)
3902 char *save_input_line_pointer;
3904 char *gotfree_input_line;
3909 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3911 as_bad (_("only 1 or 2 immediate operands are allowed"));
3915 exp = &im_expressions[i.imm_operands++];
3916 i.op[this_operand].imms = exp;
3918 if (is_space_char (*imm_start))
3921 save_input_line_pointer = input_line_pointer;
3922 input_line_pointer = imm_start;
3925 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3926 if (gotfree_input_line)
3927 input_line_pointer = gotfree_input_line;
3930 exp_seg = expression (exp);
3933 if (*input_line_pointer)
3934 as_bad (_("junk `%s' after expression"), input_line_pointer);
3936 input_line_pointer = save_input_line_pointer;
3938 if (gotfree_input_line)
3939 free (gotfree_input_line);
3942 if (exp->X_op == O_absent || exp->X_op == O_big)
3944 /* Missing or bad expr becomes absolute 0. */
3945 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3947 exp->X_op = O_constant;
3948 exp->X_add_number = 0;
3949 exp->X_add_symbol = (symbolS *) 0;
3950 exp->X_op_symbol = (symbolS *) 0;
3952 else if (exp->X_op == O_constant)
3954 /* Size it properly later. */
3955 i.types[this_operand] |= Imm64;
3956 /* If BFD64, sign extend val. */
3957 if (!use_rela_relocations)
3958 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3959 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3961 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3962 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3963 && exp_seg != absolute_section
3964 && exp_seg != text_section
3965 && exp_seg != data_section
3966 && exp_seg != bss_section
3967 && exp_seg != undefined_section
3968 && !bfd_is_com_section (exp_seg))
3970 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3976 /* This is an address. The size of the address will be
3977 determined later, depending on destination register,
3978 suffix, or the default for the section. */
3979 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3985 static char *i386_scale PARAMS ((char *));
3992 char *save = input_line_pointer;
3994 input_line_pointer = scale;
3995 val = get_absolute_expression ();
4000 i.log2_scale_factor = 0;
4003 i.log2_scale_factor = 1;
4006 i.log2_scale_factor = 2;
4009 i.log2_scale_factor = 3;
4013 char sep = *input_line_pointer;
4015 *input_line_pointer = '\0';
4016 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4018 *input_line_pointer = sep;
4019 input_line_pointer = save;
4023 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4025 as_warn (_("scale factor of %d without an index register"),
4026 1 << i.log2_scale_factor);
4027 #if SCALE1_WHEN_NO_INDEX
4028 i.log2_scale_factor = 0;
4031 scale = input_line_pointer;
4032 input_line_pointer = save;
4036 static int i386_displacement PARAMS ((char *, char *));
4039 i386_displacement (disp_start, disp_end)
4045 char *save_input_line_pointer;
4047 char *gotfree_input_line;
4049 int bigdisp = Disp32;
4051 if (flag_code == CODE_64BIT)
4053 if (i.prefix[ADDR_PREFIX] == 0)
4056 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4058 i.types[this_operand] |= bigdisp;
4060 exp = &disp_expressions[i.disp_operands];
4061 i.op[this_operand].disps = exp;
4063 save_input_line_pointer = input_line_pointer;
4064 input_line_pointer = disp_start;
4065 END_STRING_AND_SAVE (disp_end);
4067 #ifndef GCC_ASM_O_HACK
4068 #define GCC_ASM_O_HACK 0
4071 END_STRING_AND_SAVE (disp_end + 1);
4072 if ((i.types[this_operand] & BaseIndex) != 0
4073 && displacement_string_end[-1] == '+')
4075 /* This hack is to avoid a warning when using the "o"
4076 constraint within gcc asm statements.
4079 #define _set_tssldt_desc(n,addr,limit,type) \
4080 __asm__ __volatile__ ( \
4082 "movw %w1,2+%0\n\t" \
4084 "movb %b1,4+%0\n\t" \
4085 "movb %4,5+%0\n\t" \
4086 "movb $0,6+%0\n\t" \
4087 "movb %h1,7+%0\n\t" \
4089 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4091 This works great except that the output assembler ends
4092 up looking a bit weird if it turns out that there is
4093 no offset. You end up producing code that looks like:
4106 So here we provide the missing zero. */
4108 *displacement_string_end = '0';
4112 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4113 if (gotfree_input_line)
4114 input_line_pointer = gotfree_input_line;
4117 exp_seg = expression (exp);
4120 if (*input_line_pointer)
4121 as_bad (_("junk `%s' after expression"), input_line_pointer);
4123 RESTORE_END_STRING (disp_end + 1);
4125 RESTORE_END_STRING (disp_end);
4126 input_line_pointer = save_input_line_pointer;
4128 if (gotfree_input_line)
4129 free (gotfree_input_line);
4132 /* We do this to make sure that the section symbol is in
4133 the symbol table. We will ultimately change the relocation
4134 to be relative to the beginning of the section. */
4135 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4136 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4137 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4139 if (exp->X_op != O_symbol)
4141 as_bad (_("bad expression used with @%s"),
4142 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4148 if (S_IS_LOCAL (exp->X_add_symbol)
4149 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4150 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4151 exp->X_op = O_subtract;
4152 exp->X_op_symbol = GOT_symbol;
4153 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4154 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4155 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4156 i.reloc[this_operand] = BFD_RELOC_64;
4158 i.reloc[this_operand] = BFD_RELOC_32;
4161 if (exp->X_op == O_absent || exp->X_op == O_big)
4163 /* Missing or bad expr becomes absolute 0. */
4164 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4166 exp->X_op = O_constant;
4167 exp->X_add_number = 0;
4168 exp->X_add_symbol = (symbolS *) 0;
4169 exp->X_op_symbol = (symbolS *) 0;
4172 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4173 if (exp->X_op != O_constant
4174 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4175 && exp_seg != absolute_section
4176 && exp_seg != text_section
4177 && exp_seg != data_section
4178 && exp_seg != bss_section
4179 && exp_seg != undefined_section
4180 && !bfd_is_com_section (exp_seg))
4182 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4186 else if (flag_code == CODE_64BIT)
4187 i.types[this_operand] |= Disp32S | Disp32;
4191 static int i386_index_check PARAMS ((const char *));
4193 /* Make sure the memory operand we've been dealt is valid.
4194 Return 1 on success, 0 on a failure. */
4197 i386_index_check (operand_string)
4198 const char *operand_string;
4201 #if INFER_ADDR_PREFIX
4207 if ((current_templates->start->cpu_flags & CpuSVME)
4208 && current_templates->end[-1].operand_types[0] == AnyMem)
4210 /* Memory operands of SVME insns are special in that they only allow
4211 rAX as their memory address and ignore any segment override. */
4214 /* SKINIT is even more restrictive: it always requires EAX. */
4215 if (strcmp (current_templates->start->name, "skinit") == 0)
4217 else if (flag_code == CODE_64BIT)
4218 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4220 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4224 || !(i.base_reg->reg_type & Acc)
4225 || !(i.base_reg->reg_type & RegXX)
4227 || (i.types[0] & Disp))
4230 else if (flag_code == CODE_64BIT)
4232 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4235 && ((i.base_reg->reg_type & RegXX) == 0)
4236 && (i.base_reg->reg_type != BaseIndex
4239 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4240 != (RegXX | BaseIndex))))
4245 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4249 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4250 != (Reg16 | BaseIndex)))
4252 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4253 != (Reg16 | BaseIndex))
4255 && i.base_reg->reg_num < 6
4256 && i.index_reg->reg_num >= 6
4257 && i.log2_scale_factor == 0))))
4264 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4266 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4267 != (Reg32 | BaseIndex))))
4273 #if INFER_ADDR_PREFIX
4274 if (i.prefix[ADDR_PREFIX] == 0)
4276 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4278 /* Change the size of any displacement too. At most one of
4279 Disp16 or Disp32 is set.
4280 FIXME. There doesn't seem to be any real need for separate
4281 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4282 Removing them would probably clean up the code quite a lot. */
4283 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4284 i.types[this_operand] ^= (Disp16 | Disp32);
4289 as_bad (_("`%s' is not a valid base/index expression"),
4293 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4295 flag_code_names[flag_code]);
4300 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4304 i386_operand (operand_string)
4305 char *operand_string;
4309 char *op_string = operand_string;
4311 if (is_space_char (*op_string))
4314 /* We check for an absolute prefix (differentiating,
4315 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4316 if (*op_string == ABSOLUTE_PREFIX)
4319 if (is_space_char (*op_string))
4321 i.types[this_operand] |= JumpAbsolute;
4324 /* Check if operand is a register. */
4325 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4326 && (r = parse_register (op_string, &end_op)) != NULL)
4328 /* Check for a segment override by searching for ':' after a
4329 segment register. */
4331 if (is_space_char (*op_string))
4333 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4338 i.seg[i.mem_operands] = &es;
4341 i.seg[i.mem_operands] = &cs;
4344 i.seg[i.mem_operands] = &ss;
4347 i.seg[i.mem_operands] = &ds;
4350 i.seg[i.mem_operands] = &fs;
4353 i.seg[i.mem_operands] = &gs;
4357 /* Skip the ':' and whitespace. */
4359 if (is_space_char (*op_string))
4362 if (!is_digit_char (*op_string)
4363 && !is_identifier_char (*op_string)
4364 && *op_string != '('
4365 && *op_string != ABSOLUTE_PREFIX)
4367 as_bad (_("bad memory operand `%s'"), op_string);
4370 /* Handle case of %es:*foo. */
4371 if (*op_string == ABSOLUTE_PREFIX)
4374 if (is_space_char (*op_string))
4376 i.types[this_operand] |= JumpAbsolute;
4378 goto do_memory_reference;
4382 as_bad (_("junk `%s' after register"), op_string);
4385 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4386 i.op[this_operand].regs = r;
4389 else if (*op_string == REGISTER_PREFIX)
4391 as_bad (_("bad register name `%s'"), op_string);
4394 else if (*op_string == IMMEDIATE_PREFIX)
4397 if (i.types[this_operand] & JumpAbsolute)
4399 as_bad (_("immediate operand illegal with absolute jump"));
4402 if (!i386_immediate (op_string))
4405 else if (is_digit_char (*op_string)
4406 || is_identifier_char (*op_string)
4407 || *op_string == '(')
4409 /* This is a memory reference of some sort. */
4412 /* Start and end of displacement string expression (if found). */
4413 char *displacement_string_start;
4414 char *displacement_string_end;
4416 do_memory_reference:
4417 if ((i.mem_operands == 1
4418 && (current_templates->start->opcode_modifier & IsString) == 0)
4419 || i.mem_operands == 2)
4421 as_bad (_("too many memory references for `%s'"),
4422 current_templates->start->name);
4426 /* Check for base index form. We detect the base index form by
4427 looking for an ')' at the end of the operand, searching
4428 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4430 base_string = op_string + strlen (op_string);
4433 if (is_space_char (*base_string))
4436 /* If we only have a displacement, set-up for it to be parsed later. */
4437 displacement_string_start = op_string;
4438 displacement_string_end = base_string + 1;
4440 if (*base_string == ')')
4443 unsigned int parens_balanced = 1;
4444 /* We've already checked that the number of left & right ()'s are
4445 equal, so this loop will not be infinite. */
4449 if (*base_string == ')')
4451 if (*base_string == '(')
4454 while (parens_balanced);
4456 temp_string = base_string;
4458 /* Skip past '(' and whitespace. */
4460 if (is_space_char (*base_string))
4463 if (*base_string == ','
4464 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4465 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4467 displacement_string_end = temp_string;
4469 i.types[this_operand] |= BaseIndex;
4473 base_string = end_op;
4474 if (is_space_char (*base_string))
4478 /* There may be an index reg or scale factor here. */
4479 if (*base_string == ',')
4482 if (is_space_char (*base_string))
4485 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4486 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4488 base_string = end_op;
4489 if (is_space_char (*base_string))
4491 if (*base_string == ',')
4494 if (is_space_char (*base_string))
4497 else if (*base_string != ')')
4499 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4504 else if (*base_string == REGISTER_PREFIX)
4506 as_bad (_("bad register name `%s'"), base_string);
4510 /* Check for scale factor. */
4511 if (*base_string != ')')
4513 char *end_scale = i386_scale (base_string);
4518 base_string = end_scale;
4519 if (is_space_char (*base_string))
4521 if (*base_string != ')')
4523 as_bad (_("expecting `)' after scale factor in `%s'"),
4528 else if (!i.index_reg)
4530 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4535 else if (*base_string != ')')
4537 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4542 else if (*base_string == REGISTER_PREFIX)
4544 as_bad (_("bad register name `%s'"), base_string);
4549 /* If there's an expression beginning the operand, parse it,
4550 assuming displacement_string_start and
4551 displacement_string_end are meaningful. */
4552 if (displacement_string_start != displacement_string_end)
4554 if (!i386_displacement (displacement_string_start,
4555 displacement_string_end))
4559 /* Special case for (%dx) while doing input/output op. */
4561 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4563 && i.log2_scale_factor == 0
4564 && i.seg[i.mem_operands] == 0
4565 && (i.types[this_operand] & Disp) == 0)
4567 i.types[this_operand] = InOutPortReg;
4571 if (i386_index_check (operand_string) == 0)
4577 /* It's not a memory operand; argh! */
4578 as_bad (_("invalid char %s beginning operand %d `%s'"),
4579 output_invalid (*op_string),
4584 return 1; /* Normal return. */
4587 /* md_estimate_size_before_relax()
4589 Called just before relax() for rs_machine_dependent frags. The x86
4590 assembler uses these frags to handle variable size jump
4593 Any symbol that is now undefined will not become defined.
4594 Return the correct fr_subtype in the frag.
4595 Return the initial "guess for variable size of frag" to caller.
4596 The guess is actually the growth beyond the fixed part. Whatever
4597 we do to grow the fixed or variable part contributes to our
4601 md_estimate_size_before_relax (fragP, segment)
4605 /* We've already got fragP->fr_subtype right; all we have to do is
4606 check for un-relaxable symbols. On an ELF system, we can't relax
4607 an externally visible symbol, because it may be overridden by a
4609 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4611 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4612 && (S_IS_EXTERNAL (fragP->fr_symbol)
4613 || S_IS_WEAK (fragP->fr_symbol)))
4617 /* Symbol is undefined in this segment, or we need to keep a
4618 reloc so that weak symbols can be overridden. */
4619 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4620 enum bfd_reloc_code_real reloc_type;
4621 unsigned char *opcode;
4624 if (fragP->fr_var != NO_RELOC)
4625 reloc_type = fragP->fr_var;
4627 reloc_type = BFD_RELOC_16_PCREL;
4629 reloc_type = BFD_RELOC_32_PCREL;
4631 old_fr_fix = fragP->fr_fix;
4632 opcode = (unsigned char *) fragP->fr_opcode;
4634 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4637 /* Make jmp (0xeb) a (d)word displacement jump. */
4639 fragP->fr_fix += size;
4640 fix_new (fragP, old_fr_fix, size,
4642 fragP->fr_offset, 1,
4648 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4650 /* Negate the condition, and branch past an
4651 unconditional jump. */
4654 /* Insert an unconditional jump. */
4656 /* We added two extra opcode bytes, and have a two byte
4658 fragP->fr_fix += 2 + 2;
4659 fix_new (fragP, old_fr_fix + 2, 2,
4661 fragP->fr_offset, 1,
4668 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4673 fixP = fix_new (fragP, old_fr_fix, 1,
4675 fragP->fr_offset, 1,
4677 fixP->fx_signed = 1;
4681 /* This changes the byte-displacement jump 0x7N
4682 to the (d)word-displacement jump 0x0f,0x8N. */
4683 opcode[1] = opcode[0] + 0x10;
4684 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4685 /* We've added an opcode byte. */
4686 fragP->fr_fix += 1 + size;
4687 fix_new (fragP, old_fr_fix + 1, size,
4689 fragP->fr_offset, 1,
4694 BAD_CASE (fragP->fr_subtype);
4698 return fragP->fr_fix - old_fr_fix;
4701 /* Guess size depending on current relax state. Initially the relax
4702 state will correspond to a short jump and we return 1, because
4703 the variable part of the frag (the branch offset) is one byte
4704 long. However, we can relax a section more than once and in that
4705 case we must either set fr_subtype back to the unrelaxed state,
4706 or return the value for the appropriate branch. */
4707 return md_relax_table[fragP->fr_subtype].rlx_length;
4710 /* Called after relax() is finished.
4712 In: Address of frag.
4713 fr_type == rs_machine_dependent.
4714 fr_subtype is what the address relaxed to.
4716 Out: Any fixSs and constants are set up.
4717 Caller will turn frag into a ".space 0". */
4720 md_convert_frag (abfd, sec, fragP)
4721 bfd *abfd ATTRIBUTE_UNUSED;
4722 segT sec ATTRIBUTE_UNUSED;
4725 unsigned char *opcode;
4726 unsigned char *where_to_put_displacement = NULL;
4727 offsetT target_address;
4728 offsetT opcode_address;
4729 unsigned int extension = 0;
4730 offsetT displacement_from_opcode_start;
4732 opcode = (unsigned char *) fragP->fr_opcode;
4734 /* Address we want to reach in file space. */
4735 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4737 /* Address opcode resides at in file space. */
4738 opcode_address = fragP->fr_address + fragP->fr_fix;
4740 /* Displacement from opcode start to fill into instruction. */
4741 displacement_from_opcode_start = target_address - opcode_address;
4743 if ((fragP->fr_subtype & BIG) == 0)
4745 /* Don't have to change opcode. */
4746 extension = 1; /* 1 opcode + 1 displacement */
4747 where_to_put_displacement = &opcode[1];
4751 if (no_cond_jump_promotion
4752 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4753 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4755 switch (fragP->fr_subtype)
4757 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4758 extension = 4; /* 1 opcode + 4 displacement */
4760 where_to_put_displacement = &opcode[1];
4763 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4764 extension = 2; /* 1 opcode + 2 displacement */
4766 where_to_put_displacement = &opcode[1];
4769 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4770 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4771 extension = 5; /* 2 opcode + 4 displacement */
4772 opcode[1] = opcode[0] + 0x10;
4773 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4774 where_to_put_displacement = &opcode[2];
4777 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4778 extension = 3; /* 2 opcode + 2 displacement */
4779 opcode[1] = opcode[0] + 0x10;
4780 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4781 where_to_put_displacement = &opcode[2];
4784 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4789 where_to_put_displacement = &opcode[3];
4793 BAD_CASE (fragP->fr_subtype);
4798 /* Now put displacement after opcode. */
4799 md_number_to_chars ((char *) where_to_put_displacement,
4800 (valueT) (displacement_from_opcode_start - extension),
4801 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4802 fragP->fr_fix += extension;
4805 /* Size of byte displacement jmp. */
4806 int md_short_jump_size = 2;
4808 /* Size of dword displacement jmp. */
4809 int md_long_jump_size = 5;
4811 /* Size of relocation record. */
4812 const int md_reloc_size = 8;
4815 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4817 addressT from_addr, to_addr;
4818 fragS *frag ATTRIBUTE_UNUSED;
4819 symbolS *to_symbol ATTRIBUTE_UNUSED;
4823 offset = to_addr - (from_addr + 2);
4824 /* Opcode for byte-disp jump. */
4825 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4826 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4830 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4832 addressT from_addr, to_addr;
4833 fragS *frag ATTRIBUTE_UNUSED;
4834 symbolS *to_symbol ATTRIBUTE_UNUSED;
4838 offset = to_addr - (from_addr + 5);
4839 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4840 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4843 /* Apply a fixup (fixS) to segment data, once it has been determined
4844 by our caller that we have all the info we need to fix it up.
4846 On the 386, immediates, displacements, and data pointers are all in
4847 the same (little-endian) format, so we don't need to care about which
4851 md_apply_fix (fixP, valP, seg)
4852 /* The fix we're to put in. */
4854 /* Pointer to the value of the bits. */
4856 /* Segment fix is from. */
4857 segT seg ATTRIBUTE_UNUSED;
4859 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4860 valueT value = *valP;
4862 #if !defined (TE_Mach)
4865 switch (fixP->fx_r_type)
4871 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4874 case BFD_RELOC_X86_64_32S:
4875 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4878 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4881 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4886 if (fixP->fx_addsy != NULL
4887 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4888 || fixP->fx_r_type == BFD_RELOC_64_PCREL
4889 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4890 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4891 && !use_rela_relocations)
4893 /* This is a hack. There should be a better way to handle this.
4894 This covers for the fact that bfd_install_relocation will
4895 subtract the current location (for partial_inplace, PC relative
4896 relocations); see more below. */
4898 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4900 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4903 value += fixP->fx_where + fixP->fx_frag->fr_address;
4905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4906 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4908 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
4911 || (symbol_section_p (fixP->fx_addsy)
4912 && sym_seg != absolute_section))
4913 && !generic_force_reloc (fixP))
4915 /* Yes, we add the values in twice. This is because
4916 bfd_install_relocation subtracts them out again. I think
4917 bfd_install_relocation is broken, but I don't dare change
4919 value += fixP->fx_where + fixP->fx_frag->fr_address;
4923 #if defined (OBJ_COFF) && defined (TE_PE)
4924 /* For some reason, the PE format does not store a
4925 section address offset for a PC relative symbol. */
4926 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4927 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4928 || S_IS_WEAK (fixP->fx_addsy)
4931 value += md_pcrel_from (fixP);
4935 /* Fix a few things - the dynamic linker expects certain values here,
4936 and we must not disappoint it. */
4937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4938 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4940 switch (fixP->fx_r_type)
4942 case BFD_RELOC_386_PLT32:
4943 case BFD_RELOC_X86_64_PLT32:
4944 /* Make the jump instruction point to the address of the operand. At
4945 runtime we merely add the offset to the actual PLT entry. */
4949 case BFD_RELOC_386_TLS_GD:
4950 case BFD_RELOC_386_TLS_LDM:
4951 case BFD_RELOC_386_TLS_IE_32:
4952 case BFD_RELOC_386_TLS_IE:
4953 case BFD_RELOC_386_TLS_GOTIE:
4954 case BFD_RELOC_X86_64_TLSGD:
4955 case BFD_RELOC_X86_64_TLSLD:
4956 case BFD_RELOC_X86_64_GOTTPOFF:
4957 value = 0; /* Fully resolved at runtime. No addend. */
4959 case BFD_RELOC_386_TLS_LE:
4960 case BFD_RELOC_386_TLS_LDO_32:
4961 case BFD_RELOC_386_TLS_LE_32:
4962 case BFD_RELOC_X86_64_DTPOFF32:
4963 case BFD_RELOC_X86_64_DTPOFF64:
4964 case BFD_RELOC_X86_64_TPOFF32:
4965 case BFD_RELOC_X86_64_TPOFF64:
4966 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4969 case BFD_RELOC_386_GOT32:
4970 case BFD_RELOC_X86_64_GOT32:
4971 value = 0; /* Fully resolved at runtime. No addend. */
4974 case BFD_RELOC_VTABLE_INHERIT:
4975 case BFD_RELOC_VTABLE_ENTRY:
4982 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4984 #endif /* !defined (TE_Mach) */
4986 /* Are we finished with this relocation now? */
4987 if (fixP->fx_addsy == NULL)
4989 else if (use_rela_relocations)
4991 fixP->fx_no_overflow = 1;
4992 /* Remember value for tc_gen_reloc. */
4993 fixP->fx_addnumber = value;
4997 md_number_to_chars (p, value, fixP->fx_size);
5000 #define MAX_LITTLENUMS 6
5002 /* Turn the string pointed to by litP into a floating point constant
5003 of type TYPE, and emit the appropriate bytes. The number of
5004 LITTLENUMS emitted is stored in *SIZEP. An error message is
5005 returned, or NULL on OK. */
5008 md_atof (type, litP, sizeP)
5014 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5015 LITTLENUM_TYPE *wordP;
5037 return _("Bad call to md_atof ()");
5039 t = atof_ieee (input_line_pointer, type, words);
5041 input_line_pointer = t;
5043 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5044 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5045 the bigendian 386. */
5046 for (wordP = words + prec - 1; prec--;)
5048 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5049 litP += sizeof (LITTLENUM_TYPE);
5054 static char output_invalid_buf[8];
5061 sprintf (output_invalid_buf, "'%c'", c);
5063 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5064 return output_invalid_buf;
5067 /* REG_STRING starts *before* REGISTER_PREFIX. */
5069 static const reg_entry *
5070 parse_register (reg_string, end_op)
5074 char *s = reg_string;
5076 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5079 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5080 if (*s == REGISTER_PREFIX)
5083 if (is_space_char (*s))
5087 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5089 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5090 return (const reg_entry *) NULL;
5094 /* For naked regs, make sure that we are not dealing with an identifier.
5095 This prevents confusing an identifier like `eax_var' with register
5097 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5098 return (const reg_entry *) NULL;
5102 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5104 /* Handle floating point regs, allowing spaces in the (i) part. */
5105 if (r == i386_regtab /* %st is first entry of table */)
5107 if (is_space_char (*s))
5112 if (is_space_char (*s))
5114 if (*s >= '0' && *s <= '7')
5116 r = &i386_float_regtab[*s - '0'];
5118 if (is_space_char (*s))
5126 /* We have "%st(" then garbage. */
5127 return (const reg_entry *) NULL;
5132 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5133 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5134 && flag_code != CODE_64BIT)
5135 return (const reg_entry *) NULL;
5140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5141 const char *md_shortopts = "kVQ:sqn";
5143 const char *md_shortopts = "qn";
5146 struct option md_longopts[] = {
5147 #define OPTION_32 (OPTION_MD_BASE + 0)
5148 {"32", no_argument, NULL, OPTION_32},
5149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5150 #define OPTION_64 (OPTION_MD_BASE + 1)
5151 {"64", no_argument, NULL, OPTION_64},
5153 {NULL, no_argument, NULL, 0}
5155 size_t md_longopts_size = sizeof (md_longopts);
5158 md_parse_option (c, arg)
5160 char *arg ATTRIBUTE_UNUSED;
5165 optimize_align_code = 0;
5172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5173 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5174 should be emitted or not. FIXME: Not implemented. */
5178 /* -V: SVR4 argument to print version ID. */
5180 print_version_id ();
5183 /* -k: Ignore for FreeBSD compatibility. */
5188 /* -s: On i386 Solaris, this tells the native assembler to use
5189 .stab instead of .stab.excl. We always use .stab anyhow. */
5194 const char **list, **l;
5196 list = bfd_target_list ();
5197 for (l = list; *l != NULL; l++)
5198 if (strcmp (*l, "elf64-x86-64") == 0)
5200 default_arch = "x86_64";
5204 as_fatal (_("No compiled in support for x86_64"));
5211 default_arch = "i386";
5221 md_show_usage (stream)
5224 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5225 fprintf (stream, _("\
5227 -V print assembler version number\n\
5229 -n Do not optimize code alignment\n\
5230 -q quieten some warnings\n\
5233 fprintf (stream, _("\
5234 -n Do not optimize code alignment\n\
5235 -q quieten some warnings\n"));
5239 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5240 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5242 /* Pick the target format to use. */
5245 i386_target_format ()
5247 if (!strcmp (default_arch, "x86_64"))
5248 set_code_flag (CODE_64BIT);
5249 else if (!strcmp (default_arch, "i386"))
5250 set_code_flag (CODE_32BIT);
5252 as_fatal (_("Unknown architecture"));
5253 switch (OUTPUT_FLAVOR)
5255 #ifdef OBJ_MAYBE_AOUT
5256 case bfd_target_aout_flavour:
5257 return AOUT_TARGET_FORMAT;
5259 #ifdef OBJ_MAYBE_COFF
5260 case bfd_target_coff_flavour:
5263 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5264 case bfd_target_elf_flavour:
5266 if (flag_code == CODE_64BIT)
5267 use_rela_relocations = 1;
5268 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5277 #endif /* OBJ_MAYBE_ more than one */
5279 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5280 void i386_elf_emit_arch_note ()
5282 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5283 && cpu_arch_name != NULL)
5286 asection *seg = now_seg;
5287 subsegT subseg = now_subseg;
5288 Elf_Internal_Note i_note;
5289 Elf_External_Note e_note;
5290 asection *note_secp;
5293 /* Create the .note section. */
5294 note_secp = subseg_new (".note", 0);
5295 bfd_set_section_flags (stdoutput,
5297 SEC_HAS_CONTENTS | SEC_READONLY);
5299 /* Process the arch string. */
5300 len = strlen (cpu_arch_name);
5302 i_note.namesz = len + 1;
5304 i_note.type = NT_ARCH;
5305 p = frag_more (sizeof (e_note.namesz));
5306 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5307 p = frag_more (sizeof (e_note.descsz));
5308 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5309 p = frag_more (sizeof (e_note.type));
5310 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5311 p = frag_more (len + 1);
5312 strcpy (p, cpu_arch_name);
5314 frag_align (2, 0, 0);
5316 subseg_set (seg, subseg);
5322 md_undefined_symbol (name)
5325 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5326 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5327 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5328 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5332 if (symbol_find (name))
5333 as_bad (_("GOT already in symbol table"));
5334 GOT_symbol = symbol_new (name, undefined_section,
5335 (valueT) 0, &zero_address_frag);
5342 /* Round up a section size to the appropriate boundary. */
5345 md_section_align (segment, size)
5346 segT segment ATTRIBUTE_UNUSED;
5349 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5350 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5352 /* For a.out, force the section size to be aligned. If we don't do
5353 this, BFD will align it for us, but it will not write out the
5354 final bytes of the section. This may be a bug in BFD, but it is
5355 easier to fix it here since that is how the other a.out targets
5359 align = bfd_get_section_alignment (stdoutput, segment);
5360 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5367 /* On the i386, PC-relative offsets are relative to the start of the
5368 next instruction. That is, the address of the offset, plus its
5369 size, since the offset is always the last part of the insn. */
5372 md_pcrel_from (fixP)
5375 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5382 int ignore ATTRIBUTE_UNUSED;
5386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5388 obj_elf_section_change_hook ();
5390 temp = get_absolute_expression ();
5391 subseg_set (bss_section, (subsegT) temp);
5392 demand_empty_rest_of_line ();
5398 i386_validate_fix (fixp)
5401 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5403 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5405 if (flag_code != CODE_64BIT)
5407 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5411 if (flag_code != CODE_64BIT)
5412 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5414 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
5421 tc_gen_reloc (section, fixp)
5422 asection *section ATTRIBUTE_UNUSED;
5426 bfd_reloc_code_real_type code;
5428 switch (fixp->fx_r_type)
5430 case BFD_RELOC_X86_64_PLT32:
5431 case BFD_RELOC_X86_64_GOT32:
5432 case BFD_RELOC_X86_64_GOTPCREL:
5433 case BFD_RELOC_386_PLT32:
5434 case BFD_RELOC_386_GOT32:
5435 case BFD_RELOC_386_GOTOFF:
5436 case BFD_RELOC_386_GOTPC:
5437 case BFD_RELOC_386_TLS_GD:
5438 case BFD_RELOC_386_TLS_LDM:
5439 case BFD_RELOC_386_TLS_LDO_32:
5440 case BFD_RELOC_386_TLS_IE_32:
5441 case BFD_RELOC_386_TLS_IE:
5442 case BFD_RELOC_386_TLS_GOTIE:
5443 case BFD_RELOC_386_TLS_LE_32:
5444 case BFD_RELOC_386_TLS_LE:
5445 case BFD_RELOC_X86_64_TLSGD:
5446 case BFD_RELOC_X86_64_TLSLD:
5447 case BFD_RELOC_X86_64_DTPOFF32:
5448 case BFD_RELOC_X86_64_DTPOFF64:
5449 case BFD_RELOC_X86_64_GOTTPOFF:
5450 case BFD_RELOC_X86_64_TPOFF32:
5451 case BFD_RELOC_X86_64_TPOFF64:
5452 case BFD_RELOC_X86_64_GOTOFF64:
5453 case BFD_RELOC_X86_64_GOTPC32:
5455 case BFD_RELOC_VTABLE_ENTRY:
5456 case BFD_RELOC_VTABLE_INHERIT:
5458 case BFD_RELOC_32_SECREL:
5460 code = fixp->fx_r_type;
5462 case BFD_RELOC_X86_64_32S:
5463 if (!fixp->fx_pcrel)
5465 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5466 code = fixp->fx_r_type;
5472 switch (fixp->fx_size)
5475 as_bad_where (fixp->fx_file, fixp->fx_line,
5476 _("can not do %d byte pc-relative relocation"),
5478 code = BFD_RELOC_32_PCREL;
5480 case 1: code = BFD_RELOC_8_PCREL; break;
5481 case 2: code = BFD_RELOC_16_PCREL; break;
5482 case 4: code = BFD_RELOC_32_PCREL; break;
5484 case 8: code = BFD_RELOC_64_PCREL; break;
5490 switch (fixp->fx_size)
5493 as_bad_where (fixp->fx_file, fixp->fx_line,
5494 _("can not do %d byte relocation"),
5496 code = BFD_RELOC_32;
5498 case 1: code = BFD_RELOC_8; break;
5499 case 2: code = BFD_RELOC_16; break;
5500 case 4: code = BFD_RELOC_32; break;
5502 case 8: code = BFD_RELOC_64; break;
5509 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
5511 && fixp->fx_addsy == GOT_symbol)
5513 if (flag_code != CODE_64BIT)
5514 code = BFD_RELOC_386_GOTPC;
5516 code = BFD_RELOC_X86_64_GOTPC32;
5519 rel = (arelent *) xmalloc (sizeof (arelent));
5520 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5521 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5523 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5525 if (!use_rela_relocations)
5527 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5528 vtable entry to be used in the relocation's section offset. */
5529 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5530 rel->address = fixp->fx_offset;
5534 /* Use the rela in 64bit mode. */
5537 if (!fixp->fx_pcrel)
5538 rel->addend = fixp->fx_offset;
5542 case BFD_RELOC_X86_64_PLT32:
5543 case BFD_RELOC_X86_64_GOT32:
5544 case BFD_RELOC_X86_64_GOTPCREL:
5545 case BFD_RELOC_X86_64_TLSGD:
5546 case BFD_RELOC_X86_64_TLSLD:
5547 case BFD_RELOC_X86_64_GOTTPOFF:
5548 rel->addend = fixp->fx_offset - fixp->fx_size;
5551 rel->addend = (section->vma
5553 + fixp->fx_addnumber
5554 + md_pcrel_from (fixp));
5559 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5560 if (rel->howto == NULL)
5562 as_bad_where (fixp->fx_file, fixp->fx_line,
5563 _("cannot represent relocation type %s"),
5564 bfd_get_reloc_code_name (code));
5565 /* Set howto to a garbage value so that we can keep going. */
5566 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5567 assert (rel->howto != NULL);
5574 /* Parse operands using Intel syntax. This implements a recursive descent
5575 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5578 FIXME: We do not recognize the full operand grammar defined in the MASM
5579 documentation. In particular, all the structure/union and
5580 high-level macro operands are missing.
5582 Uppercase words are terminals, lower case words are non-terminals.
5583 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5584 bars '|' denote choices. Most grammar productions are implemented in
5585 functions called 'intel_<production>'.
5587 Initial production is 'expr'.
5593 binOp & | AND | \| | OR | ^ | XOR
5595 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5597 constant digits [[ radixOverride ]]
5599 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5637 => expr expr cmpOp e04
5640 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5641 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5643 hexdigit a | b | c | d | e | f
5644 | A | B | C | D | E | F
5650 mulOp * | / | % | MOD | << | SHL | >> | SHR
5654 register specialRegister
5658 segmentRegister CS | DS | ES | FS | GS | SS
5660 specialRegister CR0 | CR2 | CR3 | CR4
5661 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5662 | TR3 | TR4 | TR5 | TR6 | TR7
5664 We simplify the grammar in obvious places (e.g., register parsing is
5665 done by calling parse_register) and eliminate immediate left recursion
5666 to implement a recursive-descent parser.
5670 expr' cmpOp e04 expr'
5721 /* Parsing structure for the intel syntax parser. Used to implement the
5722 semantic actions for the operand grammar. */
5723 struct intel_parser_s
5725 char *op_string; /* The string being parsed. */
5726 int got_a_float; /* Whether the operand is a float. */
5727 int op_modifier; /* Operand modifier. */
5728 int is_mem; /* 1 if operand is memory reference. */
5729 int in_offset; /* >=1 if parsing operand of offset. */
5730 int in_bracket; /* >=1 if parsing operand in brackets. */
5731 const reg_entry *reg; /* Last register reference found. */
5732 char *disp; /* Displacement string being built. */
5733 char *next_operand; /* Resume point when splitting operands. */
5736 static struct intel_parser_s intel_parser;
5738 /* Token structure for parsing intel syntax. */
5741 int code; /* Token code. */
5742 const reg_entry *reg; /* Register entry for register tokens. */
5743 char *str; /* String representation. */
5746 static struct intel_token cur_token, prev_token;
5748 /* Token codes for the intel parser. Since T_SHORT is already used
5749 by COFF, undefine it first to prevent a warning. */
5768 /* Prototypes for intel parser functions. */
5769 static int intel_match_token PARAMS ((int code));
5770 static void intel_get_token PARAMS ((void));
5771 static void intel_putback_token PARAMS ((void));
5772 static int intel_expr PARAMS ((void));
5773 static int intel_e04 PARAMS ((void));
5774 static int intel_e05 PARAMS ((void));
5775 static int intel_e06 PARAMS ((void));
5776 static int intel_e09 PARAMS ((void));
5777 static int intel_bracket_expr PARAMS ((void));
5778 static int intel_e10 PARAMS ((void));
5779 static int intel_e11 PARAMS ((void));
5782 i386_intel_operand (operand_string, got_a_float)
5783 char *operand_string;
5789 p = intel_parser.op_string = xstrdup (operand_string);
5790 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5794 /* Initialize token holders. */
5795 cur_token.code = prev_token.code = T_NIL;
5796 cur_token.reg = prev_token.reg = NULL;
5797 cur_token.str = prev_token.str = NULL;
5799 /* Initialize parser structure. */
5800 intel_parser.got_a_float = got_a_float;
5801 intel_parser.op_modifier = 0;
5802 intel_parser.is_mem = 0;
5803 intel_parser.in_offset = 0;
5804 intel_parser.in_bracket = 0;
5805 intel_parser.reg = NULL;
5806 intel_parser.disp[0] = '\0';
5807 intel_parser.next_operand = NULL;
5809 /* Read the first token and start the parser. */
5811 ret = intel_expr ();
5816 if (cur_token.code != T_NIL)
5818 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5819 current_templates->start->name, cur_token.str);
5822 /* If we found a memory reference, hand it over to i386_displacement
5823 to fill in the rest of the operand fields. */
5824 else if (intel_parser.is_mem)
5826 if ((i.mem_operands == 1
5827 && (current_templates->start->opcode_modifier & IsString) == 0)
5828 || i.mem_operands == 2)
5830 as_bad (_("too many memory references for '%s'"),
5831 current_templates->start->name);
5836 char *s = intel_parser.disp;
5839 if (!quiet_warnings && intel_parser.is_mem < 0)
5840 /* See the comments in intel_bracket_expr. */
5841 as_warn (_("Treating `%s' as memory reference"), operand_string);
5843 /* Add the displacement expression. */
5845 ret = i386_displacement (s, s + strlen (s));
5848 /* Swap base and index in 16-bit memory operands like
5849 [si+bx]. Since i386_index_check is also used in AT&T
5850 mode we have to do that here. */
5853 && (i.base_reg->reg_type & Reg16)
5854 && (i.index_reg->reg_type & Reg16)
5855 && i.base_reg->reg_num >= 6
5856 && i.index_reg->reg_num < 6)
5858 const reg_entry *base = i.index_reg;
5860 i.index_reg = i.base_reg;
5863 ret = i386_index_check (operand_string);
5868 /* Constant and OFFSET expressions are handled by i386_immediate. */
5869 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
5870 || intel_parser.reg == NULL)
5871 ret = i386_immediate (intel_parser.disp);
5873 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5875 if (!ret || !intel_parser.next_operand)
5877 intel_parser.op_string = intel_parser.next_operand;
5878 this_operand = i.operands++;
5882 free (intel_parser.disp);
5887 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5891 expr' cmpOp e04 expr'
5896 /* XXX Implement the comparison operators. */
5897 return intel_e04 ();
5914 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5915 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
5917 if (cur_token.code == '+')
5919 else if (cur_token.code == '-')
5920 nregs = NUM_ADDRESS_REGS;
5924 strcat (intel_parser.disp, cur_token.str);
5925 intel_match_token (cur_token.code);
5936 int nregs = ~NUM_ADDRESS_REGS;
5943 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5947 str[0] = cur_token.code;
5949 strcat (intel_parser.disp, str);
5954 intel_match_token (cur_token.code);
5959 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5960 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
5971 int nregs = ~NUM_ADDRESS_REGS;
5978 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
5982 str[0] = cur_token.code;
5984 strcat (intel_parser.disp, str);
5986 else if (cur_token.code == T_SHL)
5987 strcat (intel_parser.disp, "<<");
5988 else if (cur_token.code == T_SHR)
5989 strcat (intel_parser.disp, ">>");
5993 intel_match_token (cur_token.code);
5998 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5999 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6017 int nregs = ~NUM_ADDRESS_REGS;
6022 /* Don't consume constants here. */
6023 if (cur_token.code == '+' || cur_token.code == '-')
6025 /* Need to look one token ahead - if the next token
6026 is a constant, the current token is its sign. */
6029 intel_match_token (cur_token.code);
6030 next_code = cur_token.code;
6031 intel_putback_token ();
6032 if (next_code == T_CONST)
6036 /* e09 OFFSET e09 */
6037 if (cur_token.code == T_OFFSET)
6040 ++intel_parser.in_offset;
6044 else if (cur_token.code == T_SHORT)
6045 intel_parser.op_modifier |= 1 << T_SHORT;
6048 else if (cur_token.code == '+')
6049 strcat (intel_parser.disp, "+");
6054 else if (cur_token.code == '-' || cur_token.code == '~')
6060 str[0] = cur_token.code;
6062 strcat (intel_parser.disp, str);
6069 intel_match_token (cur_token.code);
6077 /* e09' PTR e10 e09' */
6078 if (cur_token.code == T_PTR)
6082 if (prev_token.code == T_BYTE)
6083 suffix = BYTE_MNEM_SUFFIX;
6085 else if (prev_token.code == T_WORD)
6087 if (current_templates->start->name[0] == 'l'
6088 && current_templates->start->name[2] == 's'
6089 && current_templates->start->name[3] == 0)
6090 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6091 else if (intel_parser.got_a_float == 2) /* "fi..." */
6092 suffix = SHORT_MNEM_SUFFIX;
6094 suffix = WORD_MNEM_SUFFIX;
6097 else if (prev_token.code == T_DWORD)
6099 if (current_templates->start->name[0] == 'l'
6100 && current_templates->start->name[2] == 's'
6101 && current_templates->start->name[3] == 0)
6102 suffix = WORD_MNEM_SUFFIX;
6103 else if (flag_code == CODE_16BIT
6104 && (current_templates->start->opcode_modifier
6105 & (Jump|JumpDword|JumpInterSegment)))
6106 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6107 else if (intel_parser.got_a_float == 1) /* "f..." */
6108 suffix = SHORT_MNEM_SUFFIX;
6110 suffix = LONG_MNEM_SUFFIX;
6113 else if (prev_token.code == T_FWORD)
6115 if (current_templates->start->name[0] == 'l'
6116 && current_templates->start->name[2] == 's'
6117 && current_templates->start->name[3] == 0)
6118 suffix = LONG_MNEM_SUFFIX;
6119 else if (!intel_parser.got_a_float)
6121 if (flag_code == CODE_16BIT)
6122 add_prefix (DATA_PREFIX_OPCODE);
6123 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6126 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6129 else if (prev_token.code == T_QWORD)
6131 if (intel_parser.got_a_float == 1) /* "f..." */
6132 suffix = LONG_MNEM_SUFFIX;
6134 suffix = QWORD_MNEM_SUFFIX;
6137 else if (prev_token.code == T_TBYTE)
6139 if (intel_parser.got_a_float == 1)
6140 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6142 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6145 else if (prev_token.code == T_XMMWORD)
6147 /* XXX ignored for now, but accepted since gcc uses it */
6153 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6157 if (current_templates->start->base_opcode == 0x8d /* lea */)
6161 else if (i.suffix != suffix)
6163 as_bad (_("Conflicting operand modifiers"));
6169 /* e09' : e10 e09' */
6170 else if (cur_token.code == ':')
6172 if (prev_token.code != T_REG)
6174 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6175 segment/group identifier (which we don't have), using comma
6176 as the operand separator there is even less consistent, since
6177 there all branches only have a single operand. */
6178 if (this_operand != 0
6179 || intel_parser.in_offset
6180 || intel_parser.in_bracket
6181 || (!(current_templates->start->opcode_modifier
6182 & (Jump|JumpDword|JumpInterSegment))
6183 && !(current_templates->start->operand_types[0]
6185 return intel_match_token (T_NIL);
6186 /* Remember the start of the 2nd operand and terminate 1st
6188 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6189 another expression), but it gets at least the simplest case
6190 (a plain number or symbol on the left side) right. */
6191 intel_parser.next_operand = intel_parser.op_string;
6192 *--intel_parser.op_string = '\0';
6193 return intel_match_token (':');
6201 intel_match_token (cur_token.code);
6207 --intel_parser.in_offset;
6210 if (NUM_ADDRESS_REGS > nregs)
6212 as_bad (_("Invalid operand to `OFFSET'"));
6215 intel_parser.op_modifier |= 1 << T_OFFSET;
6218 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6219 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6224 intel_bracket_expr ()
6226 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6227 const char *start = intel_parser.op_string;
6230 if (i.op[this_operand].regs)
6231 return intel_match_token (T_NIL);
6233 intel_match_token ('[');
6235 /* Mark as a memory operand only if it's not already known to be an
6236 offset expression. If it's an offset expression, we need to keep
6238 if (!intel_parser.in_offset)
6240 ++intel_parser.in_bracket;
6241 /* Unfortunately gas always diverged from MASM in a respect that can't
6242 be easily fixed without risking to break code sequences likely to be
6243 encountered (the testsuite even check for this): MASM doesn't consider
6244 an expression inside brackets unconditionally as a memory reference.
6245 When that is e.g. a constant, an offset expression, or the sum of the
6246 two, this is still taken as a constant load. gas, however, always
6247 treated these as memory references. As a compromise, we'll try to make
6248 offset expressions inside brackets work the MASM way (since that's
6249 less likely to be found in real world code), but make constants alone
6250 continue to work the traditional gas way. In either case, issue a
6252 intel_parser.op_modifier &= ~was_offset;
6255 strcat (intel_parser.disp, "[");
6257 /* Add a '+' to the displacement string if necessary. */
6258 if (*intel_parser.disp != '\0'
6259 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6260 strcat (intel_parser.disp, "+");
6263 && (len = intel_parser.op_string - start - 1,
6264 intel_match_token (']')))
6266 /* Preserve brackets when the operand is an offset expression. */
6267 if (intel_parser.in_offset)
6268 strcat (intel_parser.disp, "]");
6271 --intel_parser.in_bracket;
6272 if (i.base_reg || i.index_reg)
6273 intel_parser.is_mem = 1;
6274 if (!intel_parser.is_mem)
6276 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6277 /* Defer the warning until all of the operand was parsed. */
6278 intel_parser.is_mem = -1;
6279 else if (!quiet_warnings)
6280 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6283 intel_parser.op_modifier |= was_offset;
6300 while (cur_token.code == '[')
6302 if (!intel_bracket_expr ())
6327 switch (cur_token.code)
6331 intel_match_token ('(');
6332 strcat (intel_parser.disp, "(");
6334 if (intel_expr () && intel_match_token (')'))
6336 strcat (intel_parser.disp, ")");
6343 /* Operands for jump/call inside brackets denote absolute addresses.
6344 XXX This shouldn't be needed anymore (or if it should rather live
6345 in intel_bracket_expr). */
6346 if (current_templates->start->opcode_modifier
6347 & (Jump|JumpDword|JumpByte|JumpInterSegment))
6348 i.types[this_operand] |= JumpAbsolute;
6350 return intel_bracket_expr ();
6355 strcat (intel_parser.disp, cur_token.str);
6356 intel_match_token (cur_token.code);
6358 /* Mark as a memory operand only if it's not already known to be an
6359 offset expression. */
6360 if (!intel_parser.in_offset)
6361 intel_parser.is_mem = 1;
6368 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6370 intel_match_token (T_REG);
6372 /* Check for segment change. */
6373 if (cur_token.code == ':')
6375 if (!(reg->reg_type & (SReg2 | SReg3)))
6377 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6380 else if (i.seg[i.mem_operands])
6381 as_warn (_("Extra segment override ignored"));
6384 if (!intel_parser.in_offset)
6385 intel_parser.is_mem = 1;
6386 switch (reg->reg_num)
6389 i.seg[i.mem_operands] = &es;
6392 i.seg[i.mem_operands] = &cs;
6395 i.seg[i.mem_operands] = &ss;
6398 i.seg[i.mem_operands] = &ds;
6401 i.seg[i.mem_operands] = &fs;
6404 i.seg[i.mem_operands] = &gs;
6410 /* Not a segment register. Check for register scaling. */
6411 else if (cur_token.code == '*')
6413 if (!intel_parser.in_bracket)
6415 as_bad (_("Register scaling only allowed in memory operands"));
6419 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6420 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6421 else if (i.index_reg)
6422 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6424 /* What follows must be a valid scale. */
6425 intel_match_token ('*');
6427 i.types[this_operand] |= BaseIndex;
6429 /* Set the scale after setting the register (otherwise,
6430 i386_scale will complain) */
6431 if (cur_token.code == '+' || cur_token.code == '-')
6433 char *str, sign = cur_token.code;
6434 intel_match_token (cur_token.code);
6435 if (cur_token.code != T_CONST)
6437 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6441 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6442 strcpy (str + 1, cur_token.str);
6444 if (!i386_scale (str))
6448 else if (!i386_scale (cur_token.str))
6450 intel_match_token (cur_token.code);
6453 /* No scaling. If this is a memory operand, the register is either a
6454 base register (first occurrence) or an index register (second
6456 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6461 else if (!i.index_reg)
6465 as_bad (_("Too many register references in memory operand"));
6469 i.types[this_operand] |= BaseIndex;
6472 /* Offset modifier. Add the register to the displacement string to be
6473 parsed as an immediate expression after we're done. */
6474 else if (intel_parser.in_offset)
6476 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6477 strcat (intel_parser.disp, reg->reg_name);
6480 /* It's neither base nor index nor offset. */
6481 else if (!intel_parser.is_mem)
6483 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6484 i.op[this_operand].regs = reg;
6489 as_bad (_("Invalid use of register"));
6493 /* Since registers are not part of the displacement string (except
6494 when we're parsing offset operands), we may need to remove any
6495 preceding '+' from the displacement string. */
6496 if (*intel_parser.disp != '\0'
6497 && !intel_parser.in_offset)
6499 char *s = intel_parser.disp;
6500 s += strlen (s) - 1;
6523 intel_match_token (cur_token.code);
6525 if (cur_token.code == T_PTR)
6528 /* It must have been an identifier. */
6529 intel_putback_token ();
6530 cur_token.code = T_ID;
6536 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
6540 /* The identifier represents a memory reference only if it's not
6541 preceded by an offset modifier and if it's not an equate. */
6542 symbolP = symbol_find(cur_token.str);
6543 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6544 intel_parser.is_mem = 1;
6552 char *save_str, sign = 0;
6554 /* Allow constants that start with `+' or `-'. */
6555 if (cur_token.code == '-' || cur_token.code == '+')
6557 sign = cur_token.code;
6558 intel_match_token (cur_token.code);
6559 if (cur_token.code != T_CONST)
6561 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6567 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6568 strcpy (save_str + !!sign, cur_token.str);
6572 /* Get the next token to check for register scaling. */
6573 intel_match_token (cur_token.code);
6575 /* Check if this constant is a scaling factor for an index register. */
6576 if (cur_token.code == '*')
6578 if (intel_match_token ('*') && cur_token.code == T_REG)
6580 const reg_entry *reg = cur_token.reg;
6582 if (!intel_parser.in_bracket)
6584 as_bad (_("Register scaling only allowed in memory operands"));
6588 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6589 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6590 else if (i.index_reg)
6591 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6593 /* The constant is followed by `* reg', so it must be
6596 i.types[this_operand] |= BaseIndex;
6598 /* Set the scale after setting the register (otherwise,
6599 i386_scale will complain) */
6600 if (!i386_scale (save_str))
6602 intel_match_token (T_REG);
6604 /* Since registers are not part of the displacement
6605 string, we may need to remove any preceding '+' from
6606 the displacement string. */
6607 if (*intel_parser.disp != '\0')
6609 char *s = intel_parser.disp;
6610 s += strlen (s) - 1;
6620 /* The constant was not used for register scaling. Since we have
6621 already consumed the token following `*' we now need to put it
6622 back in the stream. */
6623 intel_putback_token ();
6626 /* Add the constant to the displacement string. */
6627 strcat (intel_parser.disp, save_str);
6634 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6638 /* Match the given token against cur_token. If they match, read the next
6639 token from the operand string. */
6641 intel_match_token (code)
6644 if (cur_token.code == code)
6651 as_bad (_("Unexpected token `%s'"), cur_token.str);
6656 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6661 const reg_entry *reg;
6662 struct intel_token new_token;
6664 new_token.code = T_NIL;
6665 new_token.reg = NULL;
6666 new_token.str = NULL;
6668 /* Free the memory allocated to the previous token and move
6669 cur_token to prev_token. */
6671 free (prev_token.str);
6673 prev_token = cur_token;
6675 /* Skip whitespace. */
6676 while (is_space_char (*intel_parser.op_string))
6677 intel_parser.op_string++;
6679 /* Return an empty token if we find nothing else on the line. */
6680 if (*intel_parser.op_string == '\0')
6682 cur_token = new_token;
6686 /* The new token cannot be larger than the remainder of the operand
6688 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
6689 new_token.str[0] = '\0';
6691 if (strchr ("0123456789", *intel_parser.op_string))
6693 char *p = new_token.str;
6694 char *q = intel_parser.op_string;
6695 new_token.code = T_CONST;
6697 /* Allow any kind of identifier char to encompass floating point and
6698 hexadecimal numbers. */
6699 while (is_identifier_char (*q))
6703 /* Recognize special symbol names [0-9][bf]. */
6704 if (strlen (intel_parser.op_string) == 2
6705 && (intel_parser.op_string[1] == 'b'
6706 || intel_parser.op_string[1] == 'f'))
6707 new_token.code = T_ID;
6710 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6711 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6713 new_token.code = T_REG;
6714 new_token.reg = reg;
6716 if (*intel_parser.op_string == REGISTER_PREFIX)
6718 new_token.str[0] = REGISTER_PREFIX;
6719 new_token.str[1] = '\0';
6722 strcat (new_token.str, reg->reg_name);
6725 else if (is_identifier_char (*intel_parser.op_string))
6727 char *p = new_token.str;
6728 char *q = intel_parser.op_string;
6730 /* A '.' or '$' followed by an identifier char is an identifier.
6731 Otherwise, it's operator '.' followed by an expression. */
6732 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6734 new_token.code = '.';
6735 new_token.str[0] = '.';
6736 new_token.str[1] = '\0';
6740 while (is_identifier_char (*q) || *q == '@')
6744 if (strcasecmp (new_token.str, "NOT") == 0)
6745 new_token.code = '~';
6747 else if (strcasecmp (new_token.str, "MOD") == 0)
6748 new_token.code = '%';
6750 else if (strcasecmp (new_token.str, "AND") == 0)
6751 new_token.code = '&';
6753 else if (strcasecmp (new_token.str, "OR") == 0)
6754 new_token.code = '|';
6756 else if (strcasecmp (new_token.str, "XOR") == 0)
6757 new_token.code = '^';
6759 else if (strcasecmp (new_token.str, "SHL") == 0)
6760 new_token.code = T_SHL;
6762 else if (strcasecmp (new_token.str, "SHR") == 0)
6763 new_token.code = T_SHR;
6765 else if (strcasecmp (new_token.str, "BYTE") == 0)
6766 new_token.code = T_BYTE;
6768 else if (strcasecmp (new_token.str, "WORD") == 0)
6769 new_token.code = T_WORD;
6771 else if (strcasecmp (new_token.str, "DWORD") == 0)
6772 new_token.code = T_DWORD;
6774 else if (strcasecmp (new_token.str, "FWORD") == 0)
6775 new_token.code = T_FWORD;
6777 else if (strcasecmp (new_token.str, "QWORD") == 0)
6778 new_token.code = T_QWORD;
6780 else if (strcasecmp (new_token.str, "TBYTE") == 0
6781 /* XXX remove (gcc still uses it) */
6782 || strcasecmp (new_token.str, "XWORD") == 0)
6783 new_token.code = T_TBYTE;
6785 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6786 || strcasecmp (new_token.str, "OWORD") == 0)
6787 new_token.code = T_XMMWORD;
6789 else if (strcasecmp (new_token.str, "PTR") == 0)
6790 new_token.code = T_PTR;
6792 else if (strcasecmp (new_token.str, "SHORT") == 0)
6793 new_token.code = T_SHORT;
6795 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6797 new_token.code = T_OFFSET;
6799 /* ??? This is not mentioned in the MASM grammar but gcc
6800 makes use of it with -mintel-syntax. OFFSET may be
6801 followed by FLAT: */
6802 if (strncasecmp (q, " FLAT:", 6) == 0)
6803 strcat (new_token.str, " FLAT:");
6806 /* ??? This is not mentioned in the MASM grammar. */
6807 else if (strcasecmp (new_token.str, "FLAT") == 0)
6809 new_token.code = T_OFFSET;
6811 strcat (new_token.str, ":");
6813 as_bad (_("`:' expected"));
6817 new_token.code = T_ID;
6821 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6823 new_token.code = *intel_parser.op_string;
6824 new_token.str[0] = *intel_parser.op_string;
6825 new_token.str[1] = '\0';
6828 else if (strchr ("<>", *intel_parser.op_string)
6829 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6831 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6832 new_token.str[0] = *intel_parser.op_string;
6833 new_token.str[1] = *intel_parser.op_string;
6834 new_token.str[2] = '\0';
6838 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
6840 intel_parser.op_string += strlen (new_token.str);
6841 cur_token = new_token;
6844 /* Put cur_token back into the token stream and make cur_token point to
6847 intel_putback_token ()
6849 if (cur_token.code != T_NIL)
6851 intel_parser.op_string -= strlen (cur_token.str);
6852 free (cur_token.str);
6854 cur_token = prev_token;
6856 /* Forget prev_token. */
6857 prev_token.code = T_NIL;
6858 prev_token.reg = NULL;
6859 prev_token.str = NULL;
6863 tc_x86_regname_to_dw2regnum (const char *regname)
6865 unsigned int regnum;
6866 unsigned int regnames_count;
6867 static const char *const regnames_32[] =
6869 "eax", "ecx", "edx", "ebx",
6870 "esp", "ebp", "esi", "edi",
6871 "eip", "eflags", NULL,
6872 "st0", "st1", "st2", "st3",
6873 "st4", "st5", "st6", "st7",
6875 "xmm0", "xmm1", "xmm2", "xmm3",
6876 "xmm4", "xmm5", "xmm6", "xmm7",
6877 "mm0", "mm1", "mm2", "mm3",
6878 "mm4", "mm5", "mm6", "mm7"
6880 static const char *const regnames_64[] =
6882 "rax", "rdx", "rcx", "rbx",
6883 "rsi", "rdi", "rbp", "rsp",
6884 "r8", "r9", "r10", "r11",
6885 "r12", "r13", "r14", "r15",
6887 "xmm0", "xmm1", "xmm2", "xmm3",
6888 "xmm4", "xmm5", "xmm6", "xmm7",
6889 "xmm8", "xmm9", "xmm10", "xmm11",
6890 "xmm12", "xmm13", "xmm14", "xmm15",
6891 "st0", "st1", "st2", "st3",
6892 "st4", "st5", "st6", "st7",
6893 "mm0", "mm1", "mm2", "mm3",
6894 "mm4", "mm5", "mm6", "mm7"
6896 const char *const *regnames;
6898 if (flag_code == CODE_64BIT)
6900 regnames = regnames_64;
6901 regnames_count = ARRAY_SIZE (regnames_64);
6905 regnames = regnames_32;
6906 regnames_count = ARRAY_SIZE (regnames_32);
6909 for (regnum = 0; regnum < regnames_count; regnum++)
6910 if (regnames[regnum] != NULL
6911 && strcmp (regname, regnames[regnum]) == 0)
6918 tc_x86_frame_initial_instructions (void)
6920 static unsigned int sp_regno;
6923 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6926 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6927 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
6931 i386_elf_section_type (const char *str, size_t len)
6933 if (flag_code == CODE_64BIT
6934 && len == sizeof ("unwind") - 1
6935 && strncmp (str, "unwind", 6) == 0)
6936 return SHT_X86_64_UNWIND;
6943 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6947 expr.X_op = O_secrel;
6948 expr.X_add_symbol = symbol;
6949 expr.X_add_number = 0;
6950 emit_expr (&expr, size);