1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry *parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static void process_drex (void);
93 static int process_operands (void);
94 static const seg_entry *build_modrm_byte (void);
95 static void output_insn (void);
96 static void output_imm (fragS *, offsetT);
97 static void output_disp (fragS *, offsetT);
99 static void s_bss (int);
101 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
102 static void handle_large_common (int small ATTRIBUTE_UNUSED);
105 static const char *default_arch = DEFAULT_ARCH;
107 /* 'md_assemble ()' gathers together information and puts it into a
114 const reg_entry *regs;
119 /* TM holds the template for the insn were currently assembling. */
122 /* SUFFIX holds the instruction mnemonic suffix if given.
123 (e.g. 'l' for 'movl') */
126 /* OPERANDS gives the number of given operands. */
127 unsigned int operands;
129 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
130 of given register, displacement, memory operands and immediate
132 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
134 /* TYPES [i] is the type (see above #defines) which tells us how to
135 use OP[i] for the corresponding operand. */
136 i386_operand_type types[MAX_OPERANDS];
138 /* Displacement expression, immediate expression, or register for each
140 union i386_op op[MAX_OPERANDS];
142 /* Flags for operands. */
143 unsigned int flags[MAX_OPERANDS];
144 #define Operand_PCrel 1
146 /* Relocation type for operand */
147 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
149 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
150 the base index byte below. */
151 const reg_entry *base_reg;
152 const reg_entry *index_reg;
153 unsigned int log2_scale_factor;
155 /* SEG gives the seg_entries of this insn. They are zero unless
156 explicit segment overrides are given. */
157 const seg_entry *seg[2];
159 /* PREFIX holds all the given prefix opcodes (usually null).
160 PREFIXES is the number of prefix opcodes. */
161 unsigned int prefixes;
162 unsigned char prefix[MAX_PREFIXES];
164 /* RM and SIB are the modrm byte and the sib byte where the
165 addressing modes of this insn are encoded. DREX is the byte
166 added by the SSE5 instructions. */
174 typedef struct _i386_insn i386_insn;
176 /* List of chars besides those in app.c:symbol_chars that can start an
177 operand. Used to prevent the scrubber eating vital white-space. */
178 const char extra_symbol_chars[] = "*%-(["
187 #if (defined (TE_I386AIX) \
188 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
189 && !defined (TE_GNU) \
190 && !defined (TE_LINUX) \
191 && !defined (TE_NETWARE) \
192 && !defined (TE_FreeBSD) \
193 && !defined (TE_NetBSD)))
194 /* This array holds the chars that always start a comment. If the
195 pre-processor is disabled, these aren't very useful. The option
196 --divide will remove '/' from this list. */
197 const char *i386_comment_chars = "#/";
198 #define SVR4_COMMENT_CHARS 1
199 #define PREFIX_SEPARATOR '\\'
202 const char *i386_comment_chars = "#";
203 #define PREFIX_SEPARATOR '/'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars[] = "#/";
216 const char line_separator_chars[] = ";";
218 /* Chars that can be used to separate mant from exp in floating point
220 const char EXP_CHARS[] = "eE";
222 /* Chars that mean this number is a floating point constant
225 const char FLT_CHARS[] = "fFdDxX";
227 /* Tables for lexical analysis. */
228 static char mnemonic_chars[256];
229 static char register_chars[256];
230 static char operand_chars[256];
231 static char identifier_chars[256];
232 static char digit_chars[256];
234 /* Lexical macros. */
235 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
236 #define is_operand_char(x) (operand_chars[(unsigned char) x])
237 #define is_register_char(x) (register_chars[(unsigned char) x])
238 #define is_space_char(x) ((x) == ' ')
239 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
240 #define is_digit_char(x) (digit_chars[(unsigned char) x])
242 /* All non-digit non-letter characters that may occur in an operand. */
243 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
245 /* md_assemble() always leaves the strings it's passed unaltered. To
246 effect this we maintain a stack of saved characters that we've smashed
247 with '\0's (indicating end of strings for various sub-fields of the
248 assembler instruction). */
249 static char save_stack[32];
250 static char *save_stack_p;
251 #define END_STRING_AND_SAVE(s) \
252 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
253 #define RESTORE_END_STRING(s) \
254 do { *(s) = *--save_stack_p; } while (0)
256 /* The instruction we're assembling. */
259 /* Possible templates for current insn. */
260 static const templates *current_templates;
262 /* Per instruction expressionS buffers: max displacements & immediates. */
263 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
264 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
266 /* Current operand we are working on. */
267 static int this_operand;
269 /* We support four different modes. FLAG_CODE variable is used to distinguish
276 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
278 static enum flag_code flag_code;
279 static unsigned int object_64bit;
280 static int use_rela_relocations = 0;
282 /* The names used to print error messages. */
283 static const char *flag_code_names[] =
290 /* 1 for intel syntax,
292 static int intel_syntax = 0;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* Register prefix used for error message. */
298 static const char *register_prefix = "%";
300 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303 static char stackop_size = '\0';
305 /* Non-zero to optimize code alignment. */
306 int optimize_align_code = 1;
308 /* Non-zero to quieten some warnings. */
309 static int quiet_warnings = 0;
312 static const char *cpu_arch_name = NULL;
313 static const char *cpu_sub_arch_name = NULL;
315 /* CPU feature flags. */
316 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
318 /* Bitwise NOT of cpu_arch_flags. */
319 static i386_cpu_flags cpu_arch_flags_not;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
550 {"secrel32", pe_directive_secrel, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control *op_hash;
561 /* Hash table for register lookup. */
562 static struct hash_control *reg_hash;
565 i386_align_code (fragS *fragP, int count)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1[] =
572 static const char f32_2[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f16_3[] =
607 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
608 static const char f16_4[] =
609 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_5[] =
612 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_6[] =
614 {0x89,0xf6, /* mov %si,%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_7[] =
617 {0x8d,0x74,0x00, /* lea 0(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_8[] =
620 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char jump_31[] =
623 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
625 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
626 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
627 static const char *const f32_patt[] = {
628 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
629 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
631 static const char *const f16_patt[] = {
632 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
635 static const char alt_3[] =
637 /* nopl 0(%[re]ax) */
638 static const char alt_4[] =
639 {0x0f,0x1f,0x40,0x00};
640 /* nopl 0(%[re]ax,%[re]ax,1) */
641 static const char alt_5[] =
642 {0x0f,0x1f,0x44,0x00,0x00};
643 /* nopw 0(%[re]ax,%[re]ax,1) */
644 static const char alt_6[] =
645 {0x66,0x0f,0x1f,0x44,0x00,0x00};
646 /* nopl 0L(%[re]ax) */
647 static const char alt_7[] =
648 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
649 /* nopl 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_8[] =
651 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw 0L(%[re]ax,%[re]ax,1) */
653 static const char alt_9[] =
654 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_10[] =
657 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_long_11[] =
662 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 nopw %cs:0L(%[re]ax,%[re]ax,1) */
666 static const char alt_long_12[] =
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_13[] =
678 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 nopw %cs:0L(%[re]ax,%[re]ax,1) */
684 static const char alt_long_14[] =
689 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 nopw %cs:0L(%[re]ax,%[re]ax,1) */
696 static const char alt_long_15[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* nopl 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_11[] =
706 {0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_12[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
715 static const char alt_short_13[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 static const char alt_short_14[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 nopl 0L(%[re]ax,%[re]ax,1) */
725 static const char alt_short_15[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
728 static const char *const alt_short_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
731 alt_short_14, alt_short_15
733 static const char *const alt_long_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
736 alt_long_14, alt_long_15
739 /* Only align for at least a positive non-zero boundary. */
740 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
743 /* We need to decide which NOP sequence to use for 32bit and
744 64bit. When -mtune= is used:
746 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
747 PROCESSOR_GENERIC32, f32_patt will be used.
748 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
750 alt_long_patt will be used.
751 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
752 PROCESSOR_AMDFAM10, alt_short_patt will be used.
754 When -mtune= isn't used, alt_long_patt will be used if
755 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
758 When -march= or .arch is used, we can't use anything beyond
759 cpu_arch_isa_flags. */
761 if (flag_code == CODE_16BIT)
765 memcpy (fragP->fr_literal + fragP->fr_fix,
767 /* Adjust jump offset. */
768 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 memcpy (fragP->fr_literal + fragP->fr_fix,
772 f16_patt[count - 1], count);
776 const char *const *patt = NULL;
778 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
780 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
781 switch (cpu_arch_tune)
783 case PROCESSOR_UNKNOWN:
784 /* We use cpu_arch_isa_flags to check if we SHOULD
785 optimize for Cpu686. */
786 if (cpu_arch_isa_flags.bitfield.cpui686)
787 patt = alt_long_patt;
791 case PROCESSOR_PENTIUMPRO:
792 case PROCESSOR_PENTIUM4:
793 case PROCESSOR_NOCONA:
795 case PROCESSOR_CORE2:
796 case PROCESSOR_GENERIC64:
797 patt = alt_long_patt;
800 case PROCESSOR_ATHLON:
802 case PROCESSOR_AMDFAM10:
803 patt = alt_short_patt;
807 case PROCESSOR_PENTIUM:
808 case PROCESSOR_GENERIC32:
815 switch (cpu_arch_tune)
817 case PROCESSOR_UNKNOWN:
818 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
819 PROCESSOR_UNKNOWN. */
825 case PROCESSOR_PENTIUM:
827 case PROCESSOR_ATHLON:
829 case PROCESSOR_AMDFAM10:
830 case PROCESSOR_GENERIC32:
831 /* We use cpu_arch_isa_flags to check if we CAN optimize
833 if (cpu_arch_isa_flags.bitfield.cpui686)
834 patt = alt_short_patt;
838 case PROCESSOR_PENTIUMPRO:
839 case PROCESSOR_PENTIUM4:
840 case PROCESSOR_NOCONA:
842 case PROCESSOR_CORE2:
843 if (cpu_arch_isa_flags.bitfield.cpui686)
844 patt = alt_long_patt;
848 case PROCESSOR_GENERIC64:
849 patt = alt_long_patt;
854 if (patt == f32_patt)
856 /* If the padding is less than 15 bytes, we use the normal
857 ones. Otherwise, we use a jump instruction and adjust
860 memcpy (fragP->fr_literal + fragP->fr_fix,
861 patt[count - 1], count);
864 memcpy (fragP->fr_literal + fragP->fr_fix,
866 /* Adjust jump offset. */
867 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 /* Maximum length of an instruction is 15 byte. If the
873 padding is greater than 15 bytes and we don't use jump,
874 we have to break it into smaller pieces. */
879 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 memcpy (fragP->fr_literal + fragP->fr_fix,
885 patt [padding - 1], padding);
888 fragP->fr_var = count;
892 uints_all_zero (const unsigned int *x, unsigned int size)
910 uints_set (unsigned int *x, unsigned int v, unsigned int size)
927 uints_equal (const unsigned int *x, const unsigned int *y,
939 return x[0] == y [0];
946 #define UINTS_ALL_ZERO(x) \
947 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
948 #define UINTS_SET(x, v) \
949 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
950 #define UINTS_CLEAR(x) \
951 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
952 #define UINTS_EQUAL(x, y) \
953 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
956 cpu_flags_check_cpu64 (i386_cpu_flags f)
958 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
959 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
962 static INLINE i386_cpu_flags
963 cpu_flags_not (i386_cpu_flags x)
965 switch (ARRAY_SIZE (x.array))
968 x.array [2] = ~x.array [2];
970 x.array [1] = ~x.array [1];
972 x.array [0] = ~x.array [0];
979 x.bitfield.unused = 0;
985 static INLINE i386_cpu_flags
986 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
988 switch (ARRAY_SIZE (x.array))
991 x.array [2] &= y.array [2];
993 x.array [1] &= y.array [1];
995 x.array [0] &= y.array [0];
1003 static INLINE i386_cpu_flags
1004 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1006 switch (ARRAY_SIZE (x.array))
1009 x.array [2] |= y.array [2];
1011 x.array [1] |= y.array [1];
1013 x.array [0] |= y.array [0];
1022 cpu_flags_match (i386_cpu_flags x)
1024 i386_cpu_flags not = cpu_arch_flags_not;
1026 not.bitfield.cpu64 = 1;
1027 not.bitfield.cpuno64 = 1;
1029 x.bitfield.cpu64 = 0;
1030 x.bitfield.cpuno64 = 0;
1032 not = cpu_flags_and (x, not);
1033 return UINTS_ALL_ZERO (not);
1036 static INLINE i386_operand_type
1037 operand_type_and (i386_operand_type x, i386_operand_type y)
1039 switch (ARRAY_SIZE (x.array))
1042 x.array [2] &= y.array [2];
1044 x.array [1] &= y.array [1];
1046 x.array [0] &= y.array [0];
1054 static INLINE i386_operand_type
1055 operand_type_or (i386_operand_type x, i386_operand_type y)
1057 switch (ARRAY_SIZE (x.array))
1060 x.array [2] |= y.array [2];
1062 x.array [1] |= y.array [1];
1064 x.array [0] |= y.array [0];
1072 static INLINE i386_operand_type
1073 operand_type_xor (i386_operand_type x, i386_operand_type y)
1075 switch (ARRAY_SIZE (x.array))
1078 x.array [2] ^= y.array [2];
1080 x.array [1] ^= y.array [1];
1082 x.array [0] ^= y.array [0];
1090 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1091 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1092 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1093 static const i386_operand_type reg16_inoutportreg
1094 = OPERAND_TYPE_REG16_INOUTPORTREG;
1095 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1096 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1097 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1098 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1099 static const i386_operand_type anydisp
1100 = OPERAND_TYPE_ANYDISP;
1101 static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
1102 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1103 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1104 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1105 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1106 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1107 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1108 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1109 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1110 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1111 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1122 operand_type_check (i386_operand_type t, enum operand_type c)
1127 return (t.bitfield.reg8
1130 || t.bitfield.reg64);
1133 return (t.bitfield.imm8
1137 || t.bitfield.imm32s
1138 || t.bitfield.imm64);
1141 return (t.bitfield.disp8
1142 || t.bitfield.disp16
1143 || t.bitfield.disp32
1144 || t.bitfield.disp32s
1145 || t.bitfield.disp64);
1148 return (t.bitfield.disp8
1149 || t.bitfield.disp16
1150 || t.bitfield.disp32
1151 || t.bitfield.disp32s
1152 || t.bitfield.disp64
1153 || t.bitfield.baseindex);
1161 operand_type_match (i386_operand_type overlap,
1162 i386_operand_type given)
1164 i386_operand_type temp = overlap;
1166 temp.bitfield.jumpabsolute = 0;
1167 if (UINTS_ALL_ZERO (temp))
1170 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1171 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1174 /* If given types r0 and r1 are registers they must be of the same type
1175 unless the expected operand type register overlap is null.
1176 Note that Acc in a template matches every size of reg. */
1179 operand_type_register_match (i386_operand_type m0,
1180 i386_operand_type g0,
1181 i386_operand_type t0,
1182 i386_operand_type m1,
1183 i386_operand_type g1,
1184 i386_operand_type t1)
1186 if (!operand_type_check (g0, reg))
1189 if (!operand_type_check (g1, reg))
1192 if (g0.bitfield.reg8 == g1.bitfield.reg8
1193 && g0.bitfield.reg16 == g1.bitfield.reg16
1194 && g0.bitfield.reg32 == g1.bitfield.reg32
1195 && g0.bitfield.reg64 == g1.bitfield.reg64)
1198 if (m0.bitfield.acc)
1200 t0.bitfield.reg8 = 1;
1201 t0.bitfield.reg16 = 1;
1202 t0.bitfield.reg32 = 1;
1203 t0.bitfield.reg64 = 1;
1206 if (m1.bitfield.acc)
1208 t1.bitfield.reg8 = 1;
1209 t1.bitfield.reg16 = 1;
1210 t1.bitfield.reg32 = 1;
1211 t1.bitfield.reg64 = 1;
1214 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1215 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1216 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1217 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1220 static INLINE unsigned int
1221 mode_from_disp_size (i386_operand_type t)
1223 if (t.bitfield.disp8)
1225 else if (t.bitfield.disp16
1226 || t.bitfield.disp32
1227 || t.bitfield.disp32s)
1234 fits_in_signed_byte (offsetT num)
1236 return (num >= -128) && (num <= 127);
1240 fits_in_unsigned_byte (offsetT num)
1242 return (num & 0xff) == num;
1246 fits_in_unsigned_word (offsetT num)
1248 return (num & 0xffff) == num;
1252 fits_in_signed_word (offsetT num)
1254 return (-32768 <= num) && (num <= 32767);
1258 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1263 return (!(((offsetT) -1 << 31) & num)
1264 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1266 } /* fits_in_signed_long() */
1269 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1274 return (num & (((offsetT) 2 << 31) - 1)) == num;
1276 } /* fits_in_unsigned_long() */
1278 static i386_operand_type
1279 smallest_imm_type (offsetT num)
1281 i386_operand_type t;
1284 t.bitfield.imm64 = 1;
1286 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1288 /* This code is disabled on the 486 because all the Imm1 forms
1289 in the opcode table are slower on the i486. They're the
1290 versions with the implicitly specified single-position
1291 displacement, which has another syntax if you really want to
1293 t.bitfield.imm1 = 1;
1294 t.bitfield.imm8 = 1;
1295 t.bitfield.imm8s = 1;
1296 t.bitfield.imm16 = 1;
1297 t.bitfield.imm32 = 1;
1298 t.bitfield.imm32s = 1;
1300 else if (fits_in_signed_byte (num))
1302 t.bitfield.imm8 = 1;
1303 t.bitfield.imm8s = 1;
1304 t.bitfield.imm16 = 1;
1305 t.bitfield.imm32 = 1;
1306 t.bitfield.imm32s = 1;
1308 else if (fits_in_unsigned_byte (num))
1310 t.bitfield.imm8 = 1;
1311 t.bitfield.imm16 = 1;
1312 t.bitfield.imm32 = 1;
1313 t.bitfield.imm32s = 1;
1315 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1317 t.bitfield.imm16 = 1;
1318 t.bitfield.imm32 = 1;
1319 t.bitfield.imm32s = 1;
1321 else if (fits_in_signed_long (num))
1323 t.bitfield.imm32 = 1;
1324 t.bitfield.imm32s = 1;
1326 else if (fits_in_unsigned_long (num))
1327 t.bitfield.imm32 = 1;
1333 offset_in_range (offsetT val, int size)
1339 case 1: mask = ((addressT) 1 << 8) - 1; break;
1340 case 2: mask = ((addressT) 1 << 16) - 1; break;
1341 case 4: mask = ((addressT) 2 << 31) - 1; break;
1343 case 8: mask = ((addressT) 2 << 63) - 1; break;
1348 /* If BFD64, sign extend val. */
1349 if (!use_rela_relocations)
1350 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1351 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1353 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1355 char buf1[40], buf2[40];
1357 sprint_value (buf1, val);
1358 sprint_value (buf2, val & mask);
1359 as_warn (_("%s shortened to %s"), buf1, buf2);
1364 /* Returns 0 if attempting to add a prefix where one from the same
1365 class already exists, 1 if non rep/repne added, 2 if rep/repne
1368 add_prefix (unsigned int prefix)
1373 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1374 && flag_code == CODE_64BIT)
1376 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1377 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1378 && (prefix & (REX_R | REX_X | REX_B))))
1389 case CS_PREFIX_OPCODE:
1390 case DS_PREFIX_OPCODE:
1391 case ES_PREFIX_OPCODE:
1392 case FS_PREFIX_OPCODE:
1393 case GS_PREFIX_OPCODE:
1394 case SS_PREFIX_OPCODE:
1398 case REPNE_PREFIX_OPCODE:
1399 case REPE_PREFIX_OPCODE:
1402 case LOCK_PREFIX_OPCODE:
1410 case ADDR_PREFIX_OPCODE:
1414 case DATA_PREFIX_OPCODE:
1418 if (i.prefix[q] != 0)
1426 i.prefix[q] |= prefix;
1429 as_bad (_("same type of prefix used twice"));
1435 set_code_flag (int value)
1438 if (flag_code == CODE_64BIT)
1440 cpu_arch_flags.bitfield.cpu64 = 1;
1441 cpu_arch_flags.bitfield.cpuno64 = 0;
1442 cpu_arch_flags_not.bitfield.cpu64 = 0;
1443 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1447 cpu_arch_flags.bitfield.cpu64 = 0;
1448 cpu_arch_flags.bitfield.cpuno64 = 1;
1449 cpu_arch_flags_not.bitfield.cpu64 = 1;
1450 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1452 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1454 as_bad (_("64bit mode not supported on this CPU."));
1456 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1458 as_bad (_("32bit mode not supported on this CPU."));
1460 stackop_size = '\0';
1464 set_16bit_gcc_code_flag (int new_code_flag)
1466 flag_code = new_code_flag;
1467 if (flag_code != CODE_16BIT)
1469 cpu_arch_flags.bitfield.cpu64 = 0;
1470 cpu_arch_flags.bitfield.cpuno64 = 1;
1471 cpu_arch_flags_not.bitfield.cpu64 = 1;
1472 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1473 stackop_size = LONG_MNEM_SUFFIX;
1477 set_intel_syntax (int syntax_flag)
1479 /* Find out if register prefixing is specified. */
1480 int ask_naked_reg = 0;
1483 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1485 char *string = input_line_pointer;
1486 int e = get_symbol_end ();
1488 if (strcmp (string, "prefix") == 0)
1490 else if (strcmp (string, "noprefix") == 0)
1493 as_bad (_("bad argument to syntax directive."));
1494 *input_line_pointer = e;
1496 demand_empty_rest_of_line ();
1498 intel_syntax = syntax_flag;
1500 if (ask_naked_reg == 0)
1501 allow_naked_reg = (intel_syntax
1502 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1504 allow_naked_reg = (ask_naked_reg < 0);
1506 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1507 identifier_chars['$'] = intel_syntax ? '$' : 0;
1508 register_prefix = allow_naked_reg ? "" : "%";
1512 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1518 char *string = input_line_pointer;
1519 int e = get_symbol_end ();
1521 i386_cpu_flags flags;
1523 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1525 if (strcmp (string, cpu_arch[i].name) == 0)
1529 cpu_arch_name = cpu_arch[i].name;
1530 cpu_sub_arch_name = NULL;
1531 cpu_arch_flags = cpu_arch[i].flags;
1532 if (flag_code == CODE_64BIT)
1534 cpu_arch_flags.bitfield.cpu64 = 1;
1535 cpu_arch_flags.bitfield.cpuno64 = 0;
1539 cpu_arch_flags.bitfield.cpu64 = 0;
1540 cpu_arch_flags.bitfield.cpuno64 = 1;
1542 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1543 cpu_arch_isa = cpu_arch[i].type;
1544 cpu_arch_isa_flags = cpu_arch[i].flags;
1545 if (!cpu_arch_tune_set)
1547 cpu_arch_tune = cpu_arch_isa;
1548 cpu_arch_tune_flags = cpu_arch_isa_flags;
1553 flags = cpu_flags_or (cpu_arch_flags,
1555 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1557 cpu_sub_arch_name = cpu_arch[i].name;
1558 cpu_arch_flags = flags;
1559 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1561 *input_line_pointer = e;
1562 demand_empty_rest_of_line ();
1566 if (i >= ARRAY_SIZE (cpu_arch))
1567 as_bad (_("no such architecture: `%s'"), string);
1569 *input_line_pointer = e;
1572 as_bad (_("missing cpu architecture"));
1574 no_cond_jump_promotion = 0;
1575 if (*input_line_pointer == ','
1576 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1578 char *string = ++input_line_pointer;
1579 int e = get_symbol_end ();
1581 if (strcmp (string, "nojumps") == 0)
1582 no_cond_jump_promotion = 1;
1583 else if (strcmp (string, "jumps") == 0)
1586 as_bad (_("no such architecture modifier: `%s'"), string);
1588 *input_line_pointer = e;
1591 demand_empty_rest_of_line ();
1597 if (!strcmp (default_arch, "x86_64"))
1598 return bfd_mach_x86_64;
1599 else if (!strcmp (default_arch, "i386"))
1600 return bfd_mach_i386_i386;
1602 as_fatal (_("Unknown architecture"));
1608 const char *hash_err;
1610 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1612 /* Initialize op_hash hash table. */
1613 op_hash = hash_new ();
1616 const template *optab;
1617 templates *core_optab;
1619 /* Setup for loop. */
1621 core_optab = (templates *) xmalloc (sizeof (templates));
1622 core_optab->start = optab;
1627 if (optab->name == NULL
1628 || strcmp (optab->name, (optab - 1)->name) != 0)
1630 /* different name --> ship out current template list;
1631 add to hash table; & begin anew. */
1632 core_optab->end = optab;
1633 hash_err = hash_insert (op_hash,
1638 as_fatal (_("Internal Error: Can't hash %s: %s"),
1642 if (optab->name == NULL)
1644 core_optab = (templates *) xmalloc (sizeof (templates));
1645 core_optab->start = optab;
1650 /* Initialize reg_hash hash table. */
1651 reg_hash = hash_new ();
1653 const reg_entry *regtab;
1654 unsigned int regtab_size = i386_regtab_size;
1656 for (regtab = i386_regtab; regtab_size--; regtab++)
1658 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1660 as_fatal (_("Internal Error: Can't hash %s: %s"),
1666 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1671 for (c = 0; c < 256; c++)
1676 mnemonic_chars[c] = c;
1677 register_chars[c] = c;
1678 operand_chars[c] = c;
1680 else if (ISLOWER (c))
1682 mnemonic_chars[c] = c;
1683 register_chars[c] = c;
1684 operand_chars[c] = c;
1686 else if (ISUPPER (c))
1688 mnemonic_chars[c] = TOLOWER (c);
1689 register_chars[c] = mnemonic_chars[c];
1690 operand_chars[c] = c;
1693 if (ISALPHA (c) || ISDIGIT (c))
1694 identifier_chars[c] = c;
1697 identifier_chars[c] = c;
1698 operand_chars[c] = c;
1703 identifier_chars['@'] = '@';
1706 identifier_chars['?'] = '?';
1707 operand_chars['?'] = '?';
1709 digit_chars['-'] = '-';
1710 mnemonic_chars['-'] = '-';
1711 mnemonic_chars['.'] = '.';
1712 identifier_chars['_'] = '_';
1713 identifier_chars['.'] = '.';
1715 for (p = operand_special_chars; *p != '\0'; p++)
1716 operand_chars[(unsigned char) *p] = *p;
1719 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1722 record_alignment (text_section, 2);
1723 record_alignment (data_section, 2);
1724 record_alignment (bss_section, 2);
1728 if (flag_code == CODE_64BIT)
1730 x86_dwarf2_return_column = 16;
1731 x86_cie_data_alignment = -8;
1735 x86_dwarf2_return_column = 8;
1736 x86_cie_data_alignment = -4;
1741 i386_print_statistics (FILE *file)
1743 hash_print_statistics (file, "i386 opcode", op_hash);
1744 hash_print_statistics (file, "i386 register", reg_hash);
1749 /* Debugging routines for md_assemble. */
1750 static void pte (template *);
1751 static void pt (i386_operand_type);
1752 static void pe (expressionS *);
1753 static void ps (symbolS *);
1756 pi (char *line, i386_insn *x)
1760 fprintf (stdout, "%s: template ", line);
1762 fprintf (stdout, " address: base %s index %s scale %x\n",
1763 x->base_reg ? x->base_reg->reg_name : "none",
1764 x->index_reg ? x->index_reg->reg_name : "none",
1765 x->log2_scale_factor);
1766 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1767 x->rm.mode, x->rm.reg, x->rm.regmem);
1768 fprintf (stdout, " sib: base %x index %x scale %x\n",
1769 x->sib.base, x->sib.index, x->sib.scale);
1770 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1771 (x->rex & REX_W) != 0,
1772 (x->rex & REX_R) != 0,
1773 (x->rex & REX_X) != 0,
1774 (x->rex & REX_B) != 0);
1775 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1776 x->drex.reg, x->drex.rex);
1777 for (i = 0; i < x->operands; i++)
1779 fprintf (stdout, " #%d: ", i + 1);
1781 fprintf (stdout, "\n");
1782 if (x->types[i].bitfield.reg8
1783 || x->types[i].bitfield.reg16
1784 || x->types[i].bitfield.reg32
1785 || x->types[i].bitfield.reg64
1786 || x->types[i].bitfield.regmmx
1787 || x->types[i].bitfield.regxmm
1788 || x->types[i].bitfield.sreg2
1789 || x->types[i].bitfield.sreg3
1790 || x->types[i].bitfield.control
1791 || x->types[i].bitfield.debug
1792 || x->types[i].bitfield.test)
1793 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1794 if (operand_type_check (x->types[i], imm))
1796 if (operand_type_check (x->types[i], disp))
1797 pe (x->op[i].disps);
1805 fprintf (stdout, " %d operands ", t->operands);
1806 fprintf (stdout, "opcode %x ", t->base_opcode);
1807 if (t->extension_opcode != None)
1808 fprintf (stdout, "ext %x ", t->extension_opcode);
1809 if (t->opcode_modifier.d)
1810 fprintf (stdout, "D");
1811 if (t->opcode_modifier.w)
1812 fprintf (stdout, "W");
1813 fprintf (stdout, "\n");
1814 for (i = 0; i < t->operands; i++)
1816 fprintf (stdout, " #%d type ", i + 1);
1817 pt (t->operand_types[i]);
1818 fprintf (stdout, "\n");
1825 fprintf (stdout, " operation %d\n", e->X_op);
1826 fprintf (stdout, " add_number %ld (%lx)\n",
1827 (long) e->X_add_number, (long) e->X_add_number);
1828 if (e->X_add_symbol)
1830 fprintf (stdout, " add_symbol ");
1831 ps (e->X_add_symbol);
1832 fprintf (stdout, "\n");
1836 fprintf (stdout, " op_symbol ");
1837 ps (e->X_op_symbol);
1838 fprintf (stdout, "\n");
1845 fprintf (stdout, "%s type %s%s",
1847 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1848 segment_name (S_GET_SEGMENT (s)));
1851 static struct type_name
1853 i386_operand_type mask;
1856 const type_names[] =
1858 { OPERAND_TYPE_REG8, "r8" },
1859 { OPERAND_TYPE_REG16, "r16" },
1860 { OPERAND_TYPE_REG32, "r32" },
1861 { OPERAND_TYPE_REG64, "r64" },
1862 { OPERAND_TYPE_IMM8, "i8" },
1863 { OPERAND_TYPE_IMM8, "i8s" },
1864 { OPERAND_TYPE_IMM16, "i16" },
1865 { OPERAND_TYPE_IMM32, "i32" },
1866 { OPERAND_TYPE_IMM32S, "i32s" },
1867 { OPERAND_TYPE_IMM64, "i64" },
1868 { OPERAND_TYPE_IMM1, "i1" },
1869 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1870 { OPERAND_TYPE_DISP8, "d8" },
1871 { OPERAND_TYPE_DISP16, "d16" },
1872 { OPERAND_TYPE_DISP32, "d32" },
1873 { OPERAND_TYPE_DISP32S, "d32s" },
1874 { OPERAND_TYPE_DISP64, "d64" },
1875 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1876 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1877 { OPERAND_TYPE_CONTROL, "control reg" },
1878 { OPERAND_TYPE_TEST, "test reg" },
1879 { OPERAND_TYPE_DEBUG, "debug reg" },
1880 { OPERAND_TYPE_FLOATREG, "FReg" },
1881 { OPERAND_TYPE_FLOATACC, "FAcc" },
1882 { OPERAND_TYPE_SREG2, "SReg2" },
1883 { OPERAND_TYPE_SREG3, "SReg3" },
1884 { OPERAND_TYPE_ACC, "Acc" },
1885 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1886 { OPERAND_TYPE_REGMMX, "rMMX" },
1887 { OPERAND_TYPE_REGXMM, "rXMM" },
1888 { OPERAND_TYPE_ESSEG, "es" },
1892 pt (i386_operand_type t)
1895 i386_operand_type a;
1897 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1899 a = operand_type_and (t, type_names[j].mask);
1900 if (!UINTS_ALL_ZERO (a))
1901 fprintf (stdout, "%s, ", type_names[j].name);
1906 #endif /* DEBUG386 */
1908 static bfd_reloc_code_real_type
1909 reloc (unsigned int size,
1912 bfd_reloc_code_real_type other)
1914 if (other != NO_RELOC)
1916 reloc_howto_type *reloc;
1921 case BFD_RELOC_X86_64_GOT32:
1922 return BFD_RELOC_X86_64_GOT64;
1924 case BFD_RELOC_X86_64_PLTOFF64:
1925 return BFD_RELOC_X86_64_PLTOFF64;
1927 case BFD_RELOC_X86_64_GOTPC32:
1928 other = BFD_RELOC_X86_64_GOTPC64;
1930 case BFD_RELOC_X86_64_GOTPCREL:
1931 other = BFD_RELOC_X86_64_GOTPCREL64;
1933 case BFD_RELOC_X86_64_TPOFF32:
1934 other = BFD_RELOC_X86_64_TPOFF64;
1936 case BFD_RELOC_X86_64_DTPOFF32:
1937 other = BFD_RELOC_X86_64_DTPOFF64;
1943 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1944 if (size == 4 && flag_code != CODE_64BIT)
1947 reloc = bfd_reloc_type_lookup (stdoutput, other);
1949 as_bad (_("unknown relocation (%u)"), other);
1950 else if (size != bfd_get_reloc_size (reloc))
1951 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1952 bfd_get_reloc_size (reloc),
1954 else if (pcrel && !reloc->pc_relative)
1955 as_bad (_("non-pc-relative relocation for pc-relative field"));
1956 else if ((reloc->complain_on_overflow == complain_overflow_signed
1958 || (reloc->complain_on_overflow == complain_overflow_unsigned
1960 as_bad (_("relocated field and relocation type differ in signedness"));
1969 as_bad (_("there are no unsigned pc-relative relocations"));
1972 case 1: return BFD_RELOC_8_PCREL;
1973 case 2: return BFD_RELOC_16_PCREL;
1974 case 4: return BFD_RELOC_32_PCREL;
1975 case 8: return BFD_RELOC_64_PCREL;
1977 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1984 case 4: return BFD_RELOC_X86_64_32S;
1989 case 1: return BFD_RELOC_8;
1990 case 2: return BFD_RELOC_16;
1991 case 4: return BFD_RELOC_32;
1992 case 8: return BFD_RELOC_64;
1994 as_bad (_("cannot do %s %u byte relocation"),
1995 sign > 0 ? "signed" : "unsigned", size);
1999 return BFD_RELOC_NONE;
2002 /* Here we decide which fixups can be adjusted to make them relative to
2003 the beginning of the section instead of the symbol. Basically we need
2004 to make sure that the dynamic relocations are done correctly, so in
2005 some cases we force the original symbol to be used. */
2008 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2014 /* Don't adjust pc-relative references to merge sections in 64-bit
2016 if (use_rela_relocations
2017 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2021 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2022 and changed later by validate_fix. */
2023 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2024 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2027 /* adjust_reloc_syms doesn't know about the GOT. */
2028 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2029 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2030 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2049 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2050 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2053 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2054 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2055 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2062 intel_float_operand (const char *mnemonic)
2064 /* Note that the value returned is meaningful only for opcodes with (memory)
2065 operands, hence the code here is free to improperly handle opcodes that
2066 have no operands (for better performance and smaller code). */
2068 if (mnemonic[0] != 'f')
2069 return 0; /* non-math */
2071 switch (mnemonic[1])
2073 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2074 the fs segment override prefix not currently handled because no
2075 call path can make opcodes without operands get here */
2077 return 2 /* integer op */;
2079 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2080 return 3; /* fldcw/fldenv */
2083 if (mnemonic[2] != 'o' /* fnop */)
2084 return 3; /* non-waiting control op */
2087 if (mnemonic[2] == 's')
2088 return 3; /* frstor/frstpm */
2091 if (mnemonic[2] == 'a')
2092 return 3; /* fsave */
2093 if (mnemonic[2] == 't')
2095 switch (mnemonic[3])
2097 case 'c': /* fstcw */
2098 case 'd': /* fstdw */
2099 case 'e': /* fstenv */
2100 case 's': /* fsts[gw] */
2106 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2107 return 0; /* fxsave/fxrstor are not really math ops */
2114 /* This is the guts of the machine-dependent assembler. LINE points to a
2115 machine dependent instruction. This function is supposed to emit
2116 the frags/bytes it assembles to. */
2123 char mnemonic[MAX_MNEM_SIZE];
2125 /* Initialize globals. */
2126 memset (&i, '\0', sizeof (i));
2127 for (j = 0; j < MAX_OPERANDS; j++)
2128 i.reloc[j] = NO_RELOC;
2129 memset (disp_expressions, '\0', sizeof (disp_expressions));
2130 memset (im_expressions, '\0', sizeof (im_expressions));
2131 save_stack_p = save_stack;
2133 /* First parse an instruction mnemonic & call i386_operand for the operands.
2134 We assume that the scrubber has arranged it so that line[0] is the valid
2135 start of a (possibly prefixed) mnemonic. */
2137 line = parse_insn (line, mnemonic);
2141 line = parse_operands (line, mnemonic);
2145 /* Now we've parsed the mnemonic into a set of templates, and have the
2146 operands at hand. */
2148 /* All intel opcodes have reversed operands except for "bound" and
2149 "enter". We also don't reverse intersegment "jmp" and "call"
2150 instructions with 2 immediate operands so that the immediate segment
2151 precedes the offset, as it does when in AT&T mode. */
2154 && (strcmp (mnemonic, "bound") != 0)
2155 && (strcmp (mnemonic, "invlpga") != 0)
2156 && !(operand_type_check (i.types[0], imm)
2157 && operand_type_check (i.types[1], imm)))
2160 /* The order of the immediates should be reversed
2161 for 2 immediates extrq and insertq instructions */
2162 if (i.imm_operands == 2
2163 && (strcmp (mnemonic, "extrq") == 0
2164 || strcmp (mnemonic, "insertq") == 0))
2165 swap_2_operands (0, 1);
2170 /* Don't optimize displacement for movabs since it only takes 64bit
2173 && (flag_code != CODE_64BIT
2174 || strcmp (mnemonic, "movabs") != 0))
2177 /* Next, we find a template that matches the given insn,
2178 making sure the overlap of the given operands types is consistent
2179 with the template operand types. */
2181 if (!match_template ())
2186 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2188 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
2189 i.tm.base_opcode ^= Opcode_FloatR;
2191 /* Zap movzx and movsx suffix. The suffix may have been set from
2192 "word ptr" or "byte ptr" on the source operand, but we'll use
2193 the suffix later to choose the destination register. */
2194 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2196 if (i.reg_operands < 2
2198 && (!i.tm.opcode_modifier.no_bsuf
2199 || !i.tm.opcode_modifier.no_wsuf
2200 || !i.tm.opcode_modifier.no_lsuf
2201 || !i.tm.opcode_modifier.no_ssuf
2202 || !i.tm.opcode_modifier.no_xsuf
2203 || !i.tm.opcode_modifier.no_qsuf))
2204 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2210 if (i.tm.opcode_modifier.fwait)
2211 if (!add_prefix (FWAIT_OPCODE))
2214 /* Check string instruction segment overrides. */
2215 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2217 if (!check_string ())
2221 if (!process_suffix ())
2224 /* Make still unresolved immediate matches conform to size of immediate
2225 given in i.suffix. */
2226 if (!finalize_imm ())
2229 if (i.types[0].bitfield.imm1)
2230 i.imm_operands = 0; /* kludge for shift insns. */
2232 for (j = 0; j < 3; j++)
2233 if (i.types[j].bitfield.inoutportreg
2234 || i.types[j].bitfield.shiftcount
2235 || i.types[j].bitfield.acc
2236 || i.types[j].bitfield.floatacc)
2239 if (i.tm.opcode_modifier.immext)
2243 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2245 /* Streaming SIMD extensions 3 Instructions have the fixed
2246 operands with an opcode suffix which is coded in the same
2247 place as an 8-bit immediate field would be. Here we check
2248 those operands and remove them afterwards. */
2251 for (x = 0; x < i.operands; x++)
2252 if (i.op[x].regs->reg_num != x)
2253 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2255 i.op[x].regs->reg_name,
2261 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2262 opcode suffix which is coded in the same place as an 8-bit
2263 immediate field would be. Here we fake an 8-bit immediate
2264 operand from the opcode suffix stored in tm.extension_opcode.
2265 SSE5 also uses this encoding, for some of its 3 argument
2268 assert (i.imm_operands == 0
2270 || (i.tm.cpu_flags.bitfield.cpusse5
2271 && i.operands <= 3)));
2273 exp = &im_expressions[i.imm_operands++];
2274 i.op[i.operands].imms = exp;
2275 UINTS_CLEAR (i.types[i.operands]);
2276 i.types[i.operands].bitfield.imm8 = 1;
2278 exp->X_op = O_constant;
2279 exp->X_add_number = i.tm.extension_opcode;
2280 i.tm.extension_opcode = None;
2283 /* For insns with operands there are more diddles to do to the opcode. */
2286 if (!process_operands ())
2289 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2291 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2292 as_warn (_("translating to `%sp'"), i.tm.name);
2295 /* Handle conversion of 'int $3' --> special int3 insn. */
2296 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2298 i.tm.base_opcode = INT3_OPCODE;
2302 if ((i.tm.opcode_modifier.jump
2303 || i.tm.opcode_modifier.jumpbyte
2304 || i.tm.opcode_modifier.jumpdword)
2305 && i.op[0].disps->X_op == O_constant)
2307 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2308 the absolute address given by the constant. Since ix86 jumps and
2309 calls are pc relative, we need to generate a reloc. */
2310 i.op[0].disps->X_add_symbol = &abs_symbol;
2311 i.op[0].disps->X_op = O_symbol;
2314 if (i.tm.opcode_modifier.rex64)
2317 /* For 8 bit registers we need an empty rex prefix. Also if the
2318 instruction already has a prefix, we need to convert old
2319 registers to new ones. */
2321 if ((i.types[0].bitfield.reg8
2322 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2323 || (i.types[1].bitfield.reg8
2324 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2325 || ((i.types[0].bitfield.reg8
2326 || i.types[1].bitfield.reg8)
2331 i.rex |= REX_OPCODE;
2332 for (x = 0; x < 2; x++)
2334 /* Look for 8 bit operand that uses old registers. */
2335 if (i.types[x].bitfield.reg8
2336 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2338 /* In case it is "hi" register, give up. */
2339 if (i.op[x].regs->reg_num > 3)
2340 as_bad (_("can't encode register '%s%s' in an "
2341 "instruction requiring REX prefix."),
2342 register_prefix, i.op[x].regs->reg_name);
2344 /* Otherwise it is equivalent to the extended register.
2345 Since the encoding doesn't change this is merely
2346 cosmetic cleanup for debug output. */
2348 i.op[x].regs = i.op[x].regs + 8;
2353 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2355 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2360 else if (i.rex != 0)
2361 add_prefix (REX_OPCODE | i.rex);
2363 /* We are ready to output the insn. */
2368 parse_insn (char *line, char *mnemonic)
2371 char *token_start = l;
2376 /* Non-zero if we found a prefix only acceptable with string insns. */
2377 const char *expecting_string_instruction = NULL;
2382 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2385 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2387 as_bad (_("no such instruction: `%s'"), token_start);
2392 if (!is_space_char (*l)
2393 && *l != END_OF_INSN
2395 || (*l != PREFIX_SEPARATOR
2398 as_bad (_("invalid character %s in mnemonic"),
2399 output_invalid (*l));
2402 if (token_start == l)
2404 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2405 as_bad (_("expecting prefix; got nothing"));
2407 as_bad (_("expecting mnemonic; got nothing"));
2411 /* Look up instruction (or prefix) via hash table. */
2412 current_templates = hash_find (op_hash, mnemonic);
2414 if (*l != END_OF_INSN
2415 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2416 && current_templates
2417 && current_templates->start->opcode_modifier.isprefix)
2419 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2421 as_bad ((flag_code != CODE_64BIT
2422 ? _("`%s' is only supported in 64-bit mode")
2423 : _("`%s' is not supported in 64-bit mode")),
2424 current_templates->start->name);
2427 /* If we are in 16-bit mode, do not allow addr16 or data16.
2428 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2429 if ((current_templates->start->opcode_modifier.size16
2430 || current_templates->start->opcode_modifier.size32)
2431 && flag_code != CODE_64BIT
2432 && (current_templates->start->opcode_modifier.size32
2433 ^ (flag_code == CODE_16BIT)))
2435 as_bad (_("redundant %s prefix"),
2436 current_templates->start->name);
2439 /* Add prefix, checking for repeated prefixes. */
2440 switch (add_prefix (current_templates->start->base_opcode))
2445 expecting_string_instruction = current_templates->start->name;
2448 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2455 if (!current_templates)
2457 /* See if we can get a match by trimming off a suffix. */
2460 case WORD_MNEM_SUFFIX:
2461 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2462 i.suffix = SHORT_MNEM_SUFFIX;
2464 case BYTE_MNEM_SUFFIX:
2465 case QWORD_MNEM_SUFFIX:
2466 i.suffix = mnem_p[-1];
2468 current_templates = hash_find (op_hash, mnemonic);
2470 case SHORT_MNEM_SUFFIX:
2471 case LONG_MNEM_SUFFIX:
2474 i.suffix = mnem_p[-1];
2476 current_templates = hash_find (op_hash, mnemonic);
2484 if (intel_float_operand (mnemonic) == 1)
2485 i.suffix = SHORT_MNEM_SUFFIX;
2487 i.suffix = LONG_MNEM_SUFFIX;
2489 current_templates = hash_find (op_hash, mnemonic);
2493 if (!current_templates)
2495 as_bad (_("no such instruction: `%s'"), token_start);
2500 if (current_templates->start->opcode_modifier.jump
2501 || current_templates->start->opcode_modifier.jumpbyte)
2503 /* Check for a branch hint. We allow ",pt" and ",pn" for
2504 predict taken and predict not taken respectively.
2505 I'm not sure that branch hints actually do anything on loop
2506 and jcxz insns (JumpByte) for current Pentium4 chips. They
2507 may work in the future and it doesn't hurt to accept them
2509 if (l[0] == ',' && l[1] == 'p')
2513 if (!add_prefix (DS_PREFIX_OPCODE))
2517 else if (l[2] == 'n')
2519 if (!add_prefix (CS_PREFIX_OPCODE))
2525 /* Any other comma loses. */
2528 as_bad (_("invalid character %s in mnemonic"),
2529 output_invalid (*l));
2533 /* Check if instruction is supported on specified architecture. */
2535 for (t = current_templates->start; t < current_templates->end; ++t)
2537 if (cpu_flags_match (t->cpu_flags))
2539 if (cpu_flags_check_cpu64 (t->cpu_flags))
2542 if (!(supported & 2))
2544 as_bad (flag_code == CODE_64BIT
2545 ? _("`%s' is not supported in 64-bit mode")
2546 : _("`%s' is only supported in 64-bit mode"),
2547 current_templates->start->name);
2550 if (!(supported & 1))
2552 as_warn (_("`%s' is not supported on `%s%s'"),
2553 current_templates->start->name,
2555 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2557 else if (!cpu_arch_flags.bitfield.cpui386
2558 && (flag_code != CODE_16BIT))
2560 as_warn (_("use .code16 to ensure correct addressing mode"));
2563 /* Check for rep/repne without a string instruction. */
2564 if (expecting_string_instruction)
2566 static templates override;
2568 for (t = current_templates->start; t < current_templates->end; ++t)
2569 if (t->opcode_modifier.isstring)
2571 if (t >= current_templates->end)
2573 as_bad (_("expecting string instruction after `%s'"),
2574 expecting_string_instruction);
2577 for (override.start = t; t < current_templates->end; ++t)
2578 if (!t->opcode_modifier.isstring)
2581 current_templates = &override;
2588 parse_operands (char *l, const char *mnemonic)
2592 /* 1 if operand is pending after ','. */
2593 unsigned int expecting_operand = 0;
2595 /* Non-zero if operand parens not balanced. */
2596 unsigned int paren_not_balanced;
2598 while (*l != END_OF_INSN)
2600 /* Skip optional white space before operand. */
2601 if (is_space_char (*l))
2603 if (!is_operand_char (*l) && *l != END_OF_INSN)
2605 as_bad (_("invalid character %s before operand %d"),
2606 output_invalid (*l),
2610 token_start = l; /* after white space */
2611 paren_not_balanced = 0;
2612 while (paren_not_balanced || *l != ',')
2614 if (*l == END_OF_INSN)
2616 if (paren_not_balanced)
2619 as_bad (_("unbalanced parenthesis in operand %d."),
2622 as_bad (_("unbalanced brackets in operand %d."),
2627 break; /* we are done */
2629 else if (!is_operand_char (*l) && !is_space_char (*l))
2631 as_bad (_("invalid character %s in operand %d"),
2632 output_invalid (*l),
2639 ++paren_not_balanced;
2641 --paren_not_balanced;
2646 ++paren_not_balanced;
2648 --paren_not_balanced;
2652 if (l != token_start)
2653 { /* Yes, we've read in another operand. */
2654 unsigned int operand_ok;
2655 this_operand = i.operands++;
2656 if (i.operands > MAX_OPERANDS)
2658 as_bad (_("spurious operands; (%d operands/instruction max)"),
2662 /* Now parse operand adding info to 'i' as we go along. */
2663 END_STRING_AND_SAVE (l);
2667 i386_intel_operand (token_start,
2668 intel_float_operand (mnemonic));
2670 operand_ok = i386_operand (token_start);
2672 RESTORE_END_STRING (l);
2678 if (expecting_operand)
2680 expecting_operand_after_comma:
2681 as_bad (_("expecting operand after ','; got nothing"));
2686 as_bad (_("expecting operand before ','; got nothing"));
2691 /* Now *l must be either ',' or END_OF_INSN. */
2694 if (*++l == END_OF_INSN)
2696 /* Just skip it, if it's \n complain. */
2697 goto expecting_operand_after_comma;
2699 expecting_operand = 1;
2706 swap_2_operands (int xchg1, int xchg2)
2708 union i386_op temp_op;
2709 i386_operand_type temp_type;
2710 enum bfd_reloc_code_real temp_reloc;
2712 temp_type = i.types[xchg2];
2713 i.types[xchg2] = i.types[xchg1];
2714 i.types[xchg1] = temp_type;
2715 temp_op = i.op[xchg2];
2716 i.op[xchg2] = i.op[xchg1];
2717 i.op[xchg1] = temp_op;
2718 temp_reloc = i.reloc[xchg2];
2719 i.reloc[xchg2] = i.reloc[xchg1];
2720 i.reloc[xchg1] = temp_reloc;
2724 swap_operands (void)
2729 swap_2_operands (1, i.operands - 2);
2732 swap_2_operands (0, i.operands - 1);
2738 if (i.mem_operands == 2)
2740 const seg_entry *temp_seg;
2741 temp_seg = i.seg[0];
2742 i.seg[0] = i.seg[1];
2743 i.seg[1] = temp_seg;
2747 /* Try to ensure constant immediates are represented in the smallest
2752 char guess_suffix = 0;
2756 guess_suffix = i.suffix;
2757 else if (i.reg_operands)
2759 /* Figure out a suffix from the last register operand specified.
2760 We can't do this properly yet, ie. excluding InOutPortReg,
2761 but the following works for instructions with immediates.
2762 In any case, we can't set i.suffix yet. */
2763 for (op = i.operands; --op >= 0;)
2764 if (i.types[op].bitfield.reg8)
2766 guess_suffix = BYTE_MNEM_SUFFIX;
2769 else if (i.types[op].bitfield.reg16)
2771 guess_suffix = WORD_MNEM_SUFFIX;
2774 else if (i.types[op].bitfield.reg32)
2776 guess_suffix = LONG_MNEM_SUFFIX;
2779 else if (i.types[op].bitfield.reg64)
2781 guess_suffix = QWORD_MNEM_SUFFIX;
2785 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2786 guess_suffix = WORD_MNEM_SUFFIX;
2788 for (op = i.operands; --op >= 0;)
2789 if (operand_type_check (i.types[op], imm))
2791 switch (i.op[op].imms->X_op)
2794 /* If a suffix is given, this operand may be shortened. */
2795 switch (guess_suffix)
2797 case LONG_MNEM_SUFFIX:
2798 i.types[op].bitfield.imm32 = 1;
2799 i.types[op].bitfield.imm64 = 1;
2801 case WORD_MNEM_SUFFIX:
2802 i.types[op].bitfield.imm16 = 1;
2803 i.types[op].bitfield.imm32 = 1;
2804 i.types[op].bitfield.imm32s = 1;
2805 i.types[op].bitfield.imm64 = 1;
2807 case BYTE_MNEM_SUFFIX:
2808 i.types[op].bitfield.imm8 = 1;
2809 i.types[op].bitfield.imm8s = 1;
2810 i.types[op].bitfield.imm16 = 1;
2811 i.types[op].bitfield.imm32 = 1;
2812 i.types[op].bitfield.imm32s = 1;
2813 i.types[op].bitfield.imm64 = 1;
2817 /* If this operand is at most 16 bits, convert it
2818 to a signed 16 bit number before trying to see
2819 whether it will fit in an even smaller size.
2820 This allows a 16-bit operand such as $0xffe0 to
2821 be recognised as within Imm8S range. */
2822 if ((i.types[op].bitfield.imm16)
2823 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2825 i.op[op].imms->X_add_number =
2826 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2828 if ((i.types[op].bitfield.imm32)
2829 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2832 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2833 ^ ((offsetT) 1 << 31))
2834 - ((offsetT) 1 << 31));
2837 = operand_type_or (i.types[op],
2838 smallest_imm_type (i.op[op].imms->X_add_number));
2840 /* We must avoid matching of Imm32 templates when 64bit
2841 only immediate is available. */
2842 if (guess_suffix == QWORD_MNEM_SUFFIX)
2843 i.types[op].bitfield.imm32 = 0;
2850 /* Symbols and expressions. */
2852 /* Convert symbolic operand to proper sizes for matching, but don't
2853 prevent matching a set of insns that only supports sizes other
2854 than those matching the insn suffix. */
2856 i386_operand_type mask, allowed;
2860 UINTS_CLEAR (allowed);
2862 for (t = current_templates->start;
2863 t < current_templates->end;
2865 allowed = operand_type_or (allowed,
2866 t->operand_types[op]);
2867 switch (guess_suffix)
2869 case QWORD_MNEM_SUFFIX:
2870 mask.bitfield.imm64 = 1;
2871 mask.bitfield.imm32s = 1;
2873 case LONG_MNEM_SUFFIX:
2874 mask.bitfield.imm32 = 1;
2876 case WORD_MNEM_SUFFIX:
2877 mask.bitfield.imm16 = 1;
2879 case BYTE_MNEM_SUFFIX:
2880 mask.bitfield.imm8 = 1;
2885 allowed = operand_type_and (mask, allowed);
2886 if (!UINTS_ALL_ZERO (allowed))
2887 i.types[op] = operand_type_and (i.types[op], mask);
2894 /* Try to use the smallest displacement type too. */
2896 optimize_disp (void)
2900 for (op = i.operands; --op >= 0;)
2901 if (operand_type_check (i.types[op], disp))
2903 if (i.op[op].disps->X_op == O_constant)
2905 offsetT disp = i.op[op].disps->X_add_number;
2907 if (i.types[op].bitfield.disp16
2908 && (disp & ~(offsetT) 0xffff) == 0)
2910 /* If this operand is at most 16 bits, convert
2911 to a signed 16 bit number and don't use 64bit
2913 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2914 i.types[op].bitfield.disp64 = 0;
2916 if (i.types[op].bitfield.disp32
2917 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2919 /* If this operand is at most 32 bits, convert
2920 to a signed 32 bit number and don't use 64bit
2922 disp &= (((offsetT) 2 << 31) - 1);
2923 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2924 i.types[op].bitfield.disp64 = 0;
2926 if (!disp && i.types[op].bitfield.baseindex)
2928 i.types[op].bitfield.disp8 = 0;
2929 i.types[op].bitfield.disp16 = 0;
2930 i.types[op].bitfield.disp32 = 0;
2931 i.types[op].bitfield.disp32s = 0;
2932 i.types[op].bitfield.disp64 = 0;
2936 else if (flag_code == CODE_64BIT)
2938 if (fits_in_signed_long (disp))
2940 i.types[op].bitfield.disp64 = 0;
2941 i.types[op].bitfield.disp32s = 1;
2943 if (fits_in_unsigned_long (disp))
2944 i.types[op].bitfield.disp32 = 1;
2946 if ((i.types[op].bitfield.disp32
2947 || i.types[op].bitfield.disp32s
2948 || i.types[op].bitfield.disp16)
2949 && fits_in_signed_byte (disp))
2950 i.types[op].bitfield.disp8 = 1;
2952 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2953 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2955 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2956 i.op[op].disps, 0, i.reloc[op]);
2957 i.types[op].bitfield.disp8 = 0;
2958 i.types[op].bitfield.disp16 = 0;
2959 i.types[op].bitfield.disp32 = 0;
2960 i.types[op].bitfield.disp32s = 0;
2961 i.types[op].bitfield.disp64 = 0;
2964 /* We only support 64bit displacement on constants. */
2965 i.types[op].bitfield.disp64 = 0;
2970 match_template (void)
2972 /* Points to template once we've found it. */
2974 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2975 unsigned int found_reverse_match;
2976 i386_opcode_modifier suffix_check;
2977 i386_operand_type operand_types [MAX_OPERANDS];
2978 int addr_prefix_disp;
2980 i386_cpu_flags overlap;
2982 #if MAX_OPERANDS != 4
2983 # error "MAX_OPERANDS must be 4."
2986 found_reverse_match = 0;
2987 addr_prefix_disp = -1;
2989 memset (&suffix_check, 0, sizeof (suffix_check));
2990 if (i.suffix == BYTE_MNEM_SUFFIX)
2991 suffix_check.no_bsuf = 1;
2992 else if (i.suffix == WORD_MNEM_SUFFIX)
2993 suffix_check.no_wsuf = 1;
2994 else if (i.suffix == SHORT_MNEM_SUFFIX)
2995 suffix_check.no_ssuf = 1;
2996 else if (i.suffix == LONG_MNEM_SUFFIX)
2997 suffix_check.no_lsuf = 1;
2998 else if (i.suffix == QWORD_MNEM_SUFFIX)
2999 suffix_check.no_qsuf = 1;
3000 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3001 suffix_check.no_xsuf = 1;
3003 for (t = current_templates->start; t < current_templates->end; t++)
3005 addr_prefix_disp = -1;
3007 /* Must have right number of operands. */
3008 if (i.operands != t->operands)
3011 /* Check the suffix, except for some instructions in intel mode. */
3012 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3013 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3014 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3015 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3016 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3017 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3018 && !(intel_syntax && t->opcode_modifier.ignoresize))
3021 for (j = 0; j < MAX_OPERANDS; j++)
3022 operand_types [j] = t->operand_types [j];
3024 /* In general, don't allow 64-bit operands in 32-bit mode. */
3025 if (i.suffix == QWORD_MNEM_SUFFIX
3026 && flag_code != CODE_64BIT
3028 ? (!t->opcode_modifier.ignoresize
3029 && !intel_float_operand (t->name))
3030 : intel_float_operand (t->name) != 2)
3031 && ((!operand_types[0].bitfield.regmmx
3032 && !operand_types[0].bitfield.regxmm)
3033 || (!operand_types[t->operands > 1].bitfield.regmmx
3034 && !!operand_types[t->operands > 1].bitfield.regxmm))
3035 && (t->base_opcode != 0x0fc7
3036 || t->extension_opcode != 1 /* cmpxchg8b */))
3039 /* Do not verify operands when there are none. */
3042 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3045 if (!UINTS_ALL_ZERO (overlap))
3047 /* We've found a match; break out of loop. */
3052 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3053 into Disp32/Disp16/Disp32 operand. */
3054 if (i.prefix[ADDR_PREFIX] != 0)
3056 /* There should be only one Disp operand. */
3060 for (j = 0; j < MAX_OPERANDS; j++)
3062 if (operand_types[j].bitfield.disp16)
3064 addr_prefix_disp = j;
3065 operand_types[j].bitfield.disp32 = 1;
3066 operand_types[j].bitfield.disp16 = 0;
3072 for (j = 0; j < MAX_OPERANDS; j++)
3074 if (operand_types[j].bitfield.disp32)
3076 addr_prefix_disp = j;
3077 operand_types[j].bitfield.disp32 = 0;
3078 operand_types[j].bitfield.disp16 = 1;
3084 for (j = 0; j < MAX_OPERANDS; j++)
3086 if (operand_types[j].bitfield.disp64)
3088 addr_prefix_disp = j;
3089 operand_types[j].bitfield.disp64 = 0;
3090 operand_types[j].bitfield.disp32 = 1;
3098 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3099 switch (t->operands)
3102 if (!operand_type_match (overlap0, i.types[0]))
3106 /* xchg %eax, %eax is a special case. It is an aliase for nop
3107 only in 32bit mode and we can use opcode 0x90. In 64bit
3108 mode, we can't use 0x90 for xchg %eax, %eax since it should
3109 zero-extend %eax to %rax. */
3110 if (flag_code == CODE_64BIT
3111 && t->base_opcode == 0x90
3112 && UINTS_EQUAL (i.types [0], acc32)
3113 && UINTS_EQUAL (i.types [1], acc32))
3117 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3118 if (!operand_type_match (overlap0, i.types[0])
3119 || !operand_type_match (overlap1, i.types[1])
3120 /* monitor in SSE3 is a very special case. The first
3121 register and the second register may have different
3122 sizes. The same applies to crc32 in SSE4.2. It is
3123 also true for invlpga, vmload, vmrun and vmsave in
3125 || !((t->base_opcode == 0x0f01
3126 && (t->extension_opcode == 0xc8
3127 || t->extension_opcode == 0xd8
3128 || t->extension_opcode == 0xda
3129 || t->extension_opcode == 0xdb
3130 || t->extension_opcode == 0xdf))
3131 || t->base_opcode == 0xf20f38f1
3132 || operand_type_register_match (overlap0, i.types[0],
3134 overlap1, i.types[1],
3137 /* Check if other direction is valid ... */
3138 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3141 /* Try reversing direction of operands. */
3142 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3143 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3144 if (!operand_type_match (overlap0, i.types[0])
3145 || !operand_type_match (overlap1, i.types[1])
3146 || !operand_type_register_match (overlap0, i.types[0],
3148 overlap1, i.types[1],
3151 /* Does not match either direction. */
3154 /* found_reverse_match holds which of D or FloatDR
3156 if (t->opcode_modifier.d)
3157 found_reverse_match = Opcode_D;
3158 else if (t->opcode_modifier.floatd)
3159 found_reverse_match = Opcode_FloatD;
3161 found_reverse_match = 0;
3162 if (t->opcode_modifier.floatr)
3163 found_reverse_match |= Opcode_FloatR;
3167 /* Found a forward 2 operand match here. */
3168 switch (t->operands)
3171 overlap3 = operand_type_and (i.types[3],
3174 overlap2 = operand_type_and (i.types[2],
3179 switch (t->operands)
3182 if (!operand_type_match (overlap3, i.types[3])
3183 || !operand_type_register_match (overlap2,
3191 /* Here we make use of the fact that there are no
3192 reverse match 3 operand instructions, and all 3
3193 operand instructions only need to be checked for
3194 register consistency between operands 2 and 3. */
3195 if (!operand_type_match (overlap2, i.types[2])
3196 || !operand_type_register_match (overlap1,
3206 /* Found either forward/reverse 2, 3 or 4 operand match here:
3207 slip through to break. */
3209 if (!UINTS_ALL_ZERO (overlap))
3211 found_reverse_match = 0;
3214 /* We've found a match; break out of loop. */
3218 if (t == current_templates->end)
3220 /* We found no match. */
3221 as_bad (_("suffix or operands invalid for `%s'"),
3222 current_templates->start->name);
3226 if (!quiet_warnings)
3229 && (i.types[0].bitfield.jumpabsolute
3230 != operand_types[0].bitfield.jumpabsolute))
3232 as_warn (_("indirect %s without `*'"), t->name);
3235 if (t->opcode_modifier.isprefix
3236 && t->opcode_modifier.ignoresize)
3238 /* Warn them that a data or address size prefix doesn't
3239 affect assembly of the next line of code. */
3240 as_warn (_("stand-alone `%s' prefix"), t->name);
3244 /* Copy the template we found. */
3247 if (addr_prefix_disp != -1)
3248 i.tm.operand_types[addr_prefix_disp]
3249 = operand_types[addr_prefix_disp];
3251 if (found_reverse_match)
3253 /* If we found a reverse match we must alter the opcode
3254 direction bit. found_reverse_match holds bits to change
3255 (different for int & float insns). */
3257 i.tm.base_opcode ^= found_reverse_match;
3259 i.tm.operand_types[0] = operand_types[1];
3260 i.tm.operand_types[1] = operand_types[0];
3269 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3270 if (i.tm.operand_types[mem_op].bitfield.esseg)
3272 if (i.seg[0] != NULL && i.seg[0] != &es)
3274 as_bad (_("`%s' operand %d must use `%%es' segment"),
3279 /* There's only ever one segment override allowed per instruction.
3280 This instruction possibly has a legal segment override on the
3281 second operand, so copy the segment to where non-string
3282 instructions store it, allowing common code. */
3283 i.seg[0] = i.seg[1];
3285 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3287 if (i.seg[1] != NULL && i.seg[1] != &es)
3289 as_bad (_("`%s' operand %d must use `%%es' segment"),
3299 process_suffix (void)
3301 /* If matched instruction specifies an explicit instruction mnemonic
3303 if (i.tm.opcode_modifier.size16)
3304 i.suffix = WORD_MNEM_SUFFIX;
3305 else if (i.tm.opcode_modifier.size32)
3306 i.suffix = LONG_MNEM_SUFFIX;
3307 else if (i.tm.opcode_modifier.size64)
3308 i.suffix = QWORD_MNEM_SUFFIX;
3309 else if (i.reg_operands)
3311 /* If there's no instruction mnemonic suffix we try to invent one
3312 based on register operands. */
3315 /* We take i.suffix from the last register operand specified,
3316 Destination register type is more significant than source
3317 register type. crc32 in SSE4.2 prefers source register
3319 if (i.tm.base_opcode == 0xf20f38f1)
3321 if (i.types[0].bitfield.reg16)
3322 i.suffix = WORD_MNEM_SUFFIX;
3323 else if (i.types[0].bitfield.reg32)
3324 i.suffix = LONG_MNEM_SUFFIX;
3325 else if (i.types[0].bitfield.reg64)
3326 i.suffix = QWORD_MNEM_SUFFIX;
3328 else if (i.tm.base_opcode == 0xf20f38f0)
3330 if (i.types[0].bitfield.reg8)
3331 i.suffix = BYTE_MNEM_SUFFIX;
3338 if (i.tm.base_opcode == 0xf20f38f1
3339 || i.tm.base_opcode == 0xf20f38f0)
3341 /* We have to know the operand size for crc32. */
3342 as_bad (_("ambiguous memory operand size for `%s`"),
3347 for (op = i.operands; --op >= 0;)
3348 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3350 if (i.types[op].bitfield.reg8)
3352 i.suffix = BYTE_MNEM_SUFFIX;
3355 else if (i.types[op].bitfield.reg16)
3357 i.suffix = WORD_MNEM_SUFFIX;
3360 else if (i.types[op].bitfield.reg32)
3362 i.suffix = LONG_MNEM_SUFFIX;
3365 else if (i.types[op].bitfield.reg64)
3367 i.suffix = QWORD_MNEM_SUFFIX;
3373 else if (i.suffix == BYTE_MNEM_SUFFIX)
3375 if (!check_byte_reg ())
3378 else if (i.suffix == LONG_MNEM_SUFFIX)
3380 if (!check_long_reg ())
3383 else if (i.suffix == QWORD_MNEM_SUFFIX)
3385 if (!check_qword_reg ())
3388 else if (i.suffix == WORD_MNEM_SUFFIX)
3390 if (!check_word_reg ())
3393 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3394 /* Do nothing if the instruction is going to ignore the prefix. */
3399 else if (i.tm.opcode_modifier.defaultsize
3401 /* exclude fldenv/frstor/fsave/fstenv */
3402 && i.tm.opcode_modifier.no_ssuf)
3404 i.suffix = stackop_size;
3406 else if (intel_syntax
3408 && (i.tm.operand_types[0].bitfield.jumpabsolute
3409 || i.tm.opcode_modifier.jumpbyte
3410 || i.tm.opcode_modifier.jumpintersegment
3411 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3412 && i.tm.extension_opcode <= 3)))
3417 if (!i.tm.opcode_modifier.no_qsuf)
3419 i.suffix = QWORD_MNEM_SUFFIX;
3423 if (!i.tm.opcode_modifier.no_lsuf)
3424 i.suffix = LONG_MNEM_SUFFIX;
3427 if (!i.tm.opcode_modifier.no_wsuf)
3428 i.suffix = WORD_MNEM_SUFFIX;
3437 if (i.tm.opcode_modifier.w)
3439 as_bad (_("no instruction mnemonic suffix given and "
3440 "no register operands; can't size instruction"));
3446 unsigned int suffixes;
3448 suffixes = !i.tm.opcode_modifier.no_bsuf;
3449 if (!i.tm.opcode_modifier.no_wsuf)
3451 if (!i.tm.opcode_modifier.no_lsuf)
3453 if (!i.tm.opcode_modifier.no_lsuf)
3455 if (!i.tm.opcode_modifier.no_ssuf)
3457 if (!i.tm.opcode_modifier.no_qsuf)
3460 /* There are more than suffix matches. */
3461 if (i.tm.opcode_modifier.w
3462 || ((suffixes & (suffixes - 1))
3463 && !i.tm.opcode_modifier.defaultsize
3464 && !i.tm.opcode_modifier.ignoresize))
3466 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3472 /* Change the opcode based on the operand size given by i.suffix;
3473 We don't need to change things for byte insns. */
3475 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3477 /* It's not a byte, select word/dword operation. */
3478 if (i.tm.opcode_modifier.w)
3480 if (i.tm.opcode_modifier.shortform)
3481 i.tm.base_opcode |= 8;
3483 i.tm.base_opcode |= 1;
3486 /* Now select between word & dword operations via the operand
3487 size prefix, except for instructions that will ignore this
3489 if (i.tm.base_opcode == 0x0f01
3490 && (i.tm.extension_opcode == 0xc8
3491 || i.tm.extension_opcode == 0xd8
3492 || i.tm.extension_opcode == 0xda
3493 || i.tm.extension_opcode == 0xdb
3494 || i.tm.extension_opcode == 0xdf))
3496 /* monitor in SSE3 is a very special case. The default size
3497 of AX is the size of mode. The address size override
3498 prefix will change the size of AX. It is also true for
3499 invlpga, vmload, vmrun and vmsave in SVME. */
3500 if ((flag_code == CODE_32BIT
3501 && i.op->regs[0].reg_type.bitfield.reg16)
3502 || (flag_code != CODE_32BIT
3503 && i.op->regs[0].reg_type.bitfield.reg32))
3504 if (!add_prefix (ADDR_PREFIX_OPCODE))
3507 else if (i.suffix != QWORD_MNEM_SUFFIX
3508 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3509 && !i.tm.opcode_modifier.ignoresize
3510 && !i.tm.opcode_modifier.floatmf
3511 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3512 || (flag_code == CODE_64BIT
3513 && i.tm.opcode_modifier.jumpbyte)))
3515 unsigned int prefix = DATA_PREFIX_OPCODE;
3517 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3518 prefix = ADDR_PREFIX_OPCODE;
3520 if (!add_prefix (prefix))
3524 /* Set mode64 for an operand. */
3525 if (i.suffix == QWORD_MNEM_SUFFIX
3526 && flag_code == CODE_64BIT
3527 && !i.tm.opcode_modifier.norex64)
3529 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3530 need rex64. cmpxchg8b is also a special case. */
3531 if (! (i.operands == 2
3532 && i.tm.base_opcode == 0x90
3533 && i.tm.extension_opcode == None
3534 && UINTS_EQUAL (i.types [0], acc64)
3535 && UINTS_EQUAL (i.types [1], acc64))
3536 && ! (i.operands == 1
3537 && i.tm.base_opcode == 0xfc7
3538 && i.tm.extension_opcode == 1
3539 && !operand_type_check (i.types [0], reg)
3540 && operand_type_check (i.types [0], anymem)))
3544 /* Size floating point instruction. */
3545 if (i.suffix == LONG_MNEM_SUFFIX)
3546 if (i.tm.opcode_modifier.floatmf)
3547 i.tm.base_opcode ^= 4;
3554 check_byte_reg (void)
3558 for (op = i.operands; --op >= 0;)
3560 /* If this is an eight bit register, it's OK. If it's the 16 or
3561 32 bit version of an eight bit register, we will just use the
3562 low portion, and that's OK too. */
3563 if (i.types[op].bitfield.reg8)
3566 /* movzx, movsx, pextrb and pinsrb should not generate this
3569 && (i.tm.base_opcode == 0xfb7
3570 || i.tm.base_opcode == 0xfb6
3571 || i.tm.base_opcode == 0x63
3572 || i.tm.base_opcode == 0xfbe
3573 || i.tm.base_opcode == 0xfbf
3574 || i.tm.base_opcode == 0x660f3a14
3575 || i.tm.base_opcode == 0x660f3a20))
3578 /* crc32 doesn't generate this warning. */
3579 if (i.tm.base_opcode == 0xf20f38f0)
3582 if ((i.types[op].bitfield.reg16
3583 || i.types[op].bitfield.reg32
3584 || i.types[op].bitfield.reg64)
3585 && i.op[op].regs->reg_num < 4)
3587 /* Prohibit these changes in the 64bit mode, since the
3588 lowering is more complicated. */
3589 if (flag_code == CODE_64BIT
3590 && !i.tm.operand_types[op].bitfield.inoutportreg)
3592 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3593 register_prefix, i.op[op].regs->reg_name,
3597 #if REGISTER_WARNINGS
3599 && !i.tm.operand_types[op].bitfield.inoutportreg)
3600 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3602 (i.op[op].regs + (i.types[op].bitfield.reg16
3603 ? REGNAM_AL - REGNAM_AX
3604 : REGNAM_AL - REGNAM_EAX))->reg_name,
3606 i.op[op].regs->reg_name,
3611 /* Any other register is bad. */
3612 if (i.types[op].bitfield.reg16
3613 || i.types[op].bitfield.reg32
3614 || i.types[op].bitfield.reg64
3615 || i.types[op].bitfield.regmmx
3616 || i.types[op].bitfield.regxmm
3617 || i.types[op].bitfield.sreg2
3618 || i.types[op].bitfield.sreg3
3619 || i.types[op].bitfield.control
3620 || i.types[op].bitfield.debug
3621 || i.types[op].bitfield.test
3622 || i.types[op].bitfield.floatreg
3623 || i.types[op].bitfield.floatacc)
3625 as_bad (_("`%s%s' not allowed with `%s%c'"),
3627 i.op[op].regs->reg_name,
3637 check_long_reg (void)
3641 for (op = i.operands; --op >= 0;)
3642 /* Reject eight bit registers, except where the template requires
3643 them. (eg. movzb) */
3644 if (i.types[op].bitfield.reg8
3645 && (i.tm.operand_types[op].bitfield.reg16
3646 || i.tm.operand_types[op].bitfield.reg32
3647 || i.tm.operand_types[op].bitfield.acc))
3649 as_bad (_("`%s%s' not allowed with `%s%c'"),
3651 i.op[op].regs->reg_name,
3656 /* Warn if the e prefix on a general reg is missing. */
3657 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3658 && i.types[op].bitfield.reg16
3659 && (i.tm.operand_types[op].bitfield.reg32
3660 || i.tm.operand_types[op].bitfield.acc))
3662 /* Prohibit these changes in the 64bit mode, since the
3663 lowering is more complicated. */
3664 if (flag_code == CODE_64BIT)
3666 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3667 register_prefix, i.op[op].regs->reg_name,
3671 #if REGISTER_WARNINGS
3673 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3675 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3677 i.op[op].regs->reg_name,
3681 /* Warn if the r prefix on a general reg is missing. */
3682 else if (i.types[op].bitfield.reg64
3683 && (i.tm.operand_types[op].bitfield.reg32
3684 || i.tm.operand_types[op].bitfield.acc))
3687 && i.tm.base_opcode == 0xf30f2d
3688 && !i.types[0].bitfield.regxmm)
3690 /* cvtss2si converts DWORD memory to Reg64. We want
3692 i.suffix = QWORD_MNEM_SUFFIX;
3696 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3697 register_prefix, i.op[op].regs->reg_name,
3706 check_qword_reg (void)
3710 for (op = i.operands; --op >= 0; )
3711 /* Reject eight bit registers, except where the template requires
3712 them. (eg. movzb) */
3713 if (i.types[op].bitfield.reg8
3714 && (i.tm.operand_types[op].bitfield.reg16
3715 || i.tm.operand_types[op].bitfield.reg32
3716 || i.tm.operand_types[op].bitfield.acc))
3718 as_bad (_("`%s%s' not allowed with `%s%c'"),
3720 i.op[op].regs->reg_name,
3725 /* Warn if the e prefix on a general reg is missing. */
3726 else if ((i.types[op].bitfield.reg16
3727 || i.types[op].bitfield.reg32)
3728 && (i.tm.operand_types[op].bitfield.reg32
3729 || i.tm.operand_types[op].bitfield.acc))
3731 /* Prohibit these changes in the 64bit mode, since the
3732 lowering is more complicated. */
3734 && i.tm.base_opcode == 0xf20f2d
3735 && !i.types[0].bitfield.regxmm)
3737 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3739 i.suffix = LONG_MNEM_SUFFIX;
3743 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3744 register_prefix, i.op[op].regs->reg_name,
3753 check_word_reg (void)
3756 for (op = i.operands; --op >= 0;)
3757 /* Reject eight bit registers, except where the template requires
3758 them. (eg. movzb) */
3759 if (i.types[op].bitfield.reg8
3760 && (i.tm.operand_types[op].bitfield.reg16
3761 || i.tm.operand_types[op].bitfield.reg32
3762 || i.tm.operand_types[op].bitfield.acc))
3764 as_bad (_("`%s%s' not allowed with `%s%c'"),
3766 i.op[op].regs->reg_name,
3771 /* Warn if the e prefix on a general reg is present. */
3772 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3773 && i.types[op].bitfield.reg32
3774 && (i.tm.operand_types[op].bitfield.reg16
3775 || i.tm.operand_types[op].bitfield.acc))
3777 /* Prohibit these changes in the 64bit mode, since the
3778 lowering is more complicated. */
3779 if (flag_code == CODE_64BIT)
3781 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3782 register_prefix, i.op[op].regs->reg_name,
3787 #if REGISTER_WARNINGS
3788 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3790 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3792 i.op[op].regs->reg_name,
3800 update_imm (unsigned int j)
3802 i386_operand_type overlap;
3804 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3805 if ((overlap.bitfield.imm8
3806 || overlap.bitfield.imm8s
3807 || overlap.bitfield.imm16
3808 || overlap.bitfield.imm32
3809 || overlap.bitfield.imm32s
3810 || overlap.bitfield.imm64)
3811 && !UINTS_EQUAL (overlap, imm8)
3812 && !UINTS_EQUAL (overlap, imm8s)
3813 && !UINTS_EQUAL (overlap, imm16)
3814 && !UINTS_EQUAL (overlap, imm32)
3815 && !UINTS_EQUAL (overlap, imm32s)
3816 && !UINTS_EQUAL (overlap, imm64))
3820 i386_operand_type temp;
3823 if (i.suffix == BYTE_MNEM_SUFFIX)
3825 temp.bitfield.imm8 = overlap.bitfield.imm8;
3826 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3828 else if (i.suffix == WORD_MNEM_SUFFIX)
3829 temp.bitfield.imm16 = overlap.bitfield.imm16;
3830 else if (i.suffix == QWORD_MNEM_SUFFIX)
3832 temp.bitfield.imm64 = overlap.bitfield.imm64;
3833 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3836 temp.bitfield.imm32 = overlap.bitfield.imm32;
3839 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3840 || UINTS_EQUAL (overlap, imm16_32)
3841 || UINTS_EQUAL (overlap, imm16_32s))
3843 UINTS_CLEAR (overlap);
3844 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3845 overlap.bitfield.imm16 = 1;
3847 overlap.bitfield.imm32s = 1;
3849 if (!UINTS_EQUAL (overlap, imm8)
3850 && !UINTS_EQUAL (overlap, imm8s)
3851 && !UINTS_EQUAL (overlap, imm16)
3852 && !UINTS_EQUAL (overlap, imm32)
3853 && !UINTS_EQUAL (overlap, imm32s)
3854 && !UINTS_EQUAL (overlap, imm64))
3856 as_bad (_("no instruction mnemonic suffix given; "
3857 "can't determine immediate size"));
3861 i.types[j] = overlap;
3871 for (j = 0; j < 2; j++)
3872 if (update_imm (j) == 0)
3875 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3876 assert (operand_type_check (i.types[2], imm) == 0);
3884 i.drex.modrm_reg = None;
3885 i.drex.modrm_regmem = None;
3887 /* SSE5 4 operand instructions must have the destination the same as
3888 one of the inputs. Figure out the destination register and cache
3889 it away in the drex field, and remember which fields to use for
3891 if (i.tm.opcode_modifier.drex
3892 && i.tm.opcode_modifier.drexv
3895 i.tm.extension_opcode = None;
3897 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3898 if (i.types[0].bitfield.regxmm != 0
3899 && i.types[1].bitfield.regxmm != 0
3900 && i.types[2].bitfield.regxmm != 0
3901 && i.types[3].bitfield.regxmm != 0
3902 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3903 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3905 /* Clear the arguments that are stored in drex. */
3906 UINTS_CLEAR (i.types[0]);
3907 UINTS_CLEAR (i.types[3]);
3908 i.reg_operands -= 2;
3910 /* There are two different ways to encode a 4 operand
3911 instruction with all registers that uses OC1 set to
3912 0 or 1. Favor setting OC1 to 0 since this mimics the
3913 actions of other SSE5 assemblers. Use modrm encoding 2
3914 for register/register. Include the high order bit that
3915 is normally stored in the REX byte in the register
3917 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3918 i.drex.modrm_reg = 2;
3919 i.drex.modrm_regmem = 1;
3920 i.drex.reg = (i.op[3].regs->reg_num
3921 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3924 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3925 else if (i.types[0].bitfield.regxmm != 0
3926 && i.types[1].bitfield.regxmm != 0
3927 && (i.types[2].bitfield.regxmm
3928 || operand_type_check (i.types[2], anymem))
3929 && i.types[3].bitfield.regxmm != 0
3930 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3931 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3933 /* clear the arguments that are stored in drex */
3934 UINTS_CLEAR (i.types[0]);
3935 UINTS_CLEAR (i.types[3]);
3936 i.reg_operands -= 2;
3938 /* Specify the modrm encoding for memory addressing. Include
3939 the high order bit that is normally stored in the REX byte
3940 in the register field. */
3941 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3942 i.drex.modrm_reg = 1;
3943 i.drex.modrm_regmem = 2;
3944 i.drex.reg = (i.op[3].regs->reg_num
3945 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3948 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3949 else if (i.types[0].bitfield.regxmm != 0
3950 && operand_type_check (i.types[1], anymem) != 0
3951 && i.types[2].bitfield.regxmm != 0
3952 && i.types[3].bitfield.regxmm != 0
3953 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3954 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3956 /* Clear the arguments that are stored in drex. */
3957 UINTS_CLEAR (i.types[0]);
3958 UINTS_CLEAR (i.types[3]);
3959 i.reg_operands -= 2;
3961 /* Specify the modrm encoding for memory addressing. Include
3962 the high order bit that is normally stored in the REX byte
3963 in the register field. */
3964 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3965 i.drex.modrm_reg = 2;
3966 i.drex.modrm_regmem = 1;
3967 i.drex.reg = (i.op[3].regs->reg_num
3968 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3971 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3972 else if (i.types[0].bitfield.regxmm != 0
3973 && i.types[1].bitfield.regxmm != 0
3974 && i.types[2].bitfield.regxmm != 0
3975 && i.types[3].bitfield.regxmm != 0
3976 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3977 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3979 /* clear the arguments that are stored in drex */
3980 UINTS_CLEAR (i.types[2]);
3981 UINTS_CLEAR (i.types[3]);
3982 i.reg_operands -= 2;
3984 /* There are two different ways to encode a 4 operand
3985 instruction with all registers that uses OC1 set to
3986 0 or 1. Favor setting OC1 to 0 since this mimics the
3987 actions of other SSE5 assemblers. Use modrm encoding
3988 2 for register/register. Include the high order bit that
3989 is normally stored in the REX byte in the register
3991 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3992 i.drex.modrm_reg = 1;
3993 i.drex.modrm_regmem = 0;
3995 /* Remember the register, including the upper bits */
3996 i.drex.reg = (i.op[3].regs->reg_num
3997 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4000 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4001 else if (i.types[0].bitfield.regxmm != 0
4002 && (i.types[1].bitfield.regxmm
4003 || operand_type_check (i.types[1], anymem))
4004 && i.types[2].bitfield.regxmm != 0
4005 && i.types[3].bitfield.regxmm != 0
4006 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4007 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4009 /* Clear the arguments that are stored in drex. */
4010 UINTS_CLEAR (i.types[2]);
4011 UINTS_CLEAR (i.types[3]);
4012 i.reg_operands -= 2;
4014 /* Specify the modrm encoding and remember the register
4015 including the bits normally stored in the REX byte. */
4016 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4017 i.drex.modrm_reg = 0;
4018 i.drex.modrm_regmem = 1;
4019 i.drex.reg = (i.op[3].regs->reg_num
4020 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4023 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4024 else if (operand_type_check (i.types[0], anymem) != 0
4025 && i.types[1].bitfield.regxmm != 0
4026 && i.types[2].bitfield.regxmm != 0
4027 && i.types[3].bitfield.regxmm != 0
4028 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4029 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4031 /* clear the arguments that are stored in drex */
4032 UINTS_CLEAR (i.types[2]);
4033 UINTS_CLEAR (i.types[3]);
4034 i.reg_operands -= 2;
4036 /* Specify the modrm encoding and remember the register
4037 including the bits normally stored in the REX byte. */
4038 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4039 i.drex.modrm_reg = 1;
4040 i.drex.modrm_regmem = 0;
4041 i.drex.reg = (i.op[3].regs->reg_num
4042 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4046 as_bad (_("Incorrect operands for the '%s' instruction"),
4050 /* SSE5 instructions with the DREX byte where the only memory operand
4051 is in the 2nd argument, and the first and last xmm register must
4052 match, and is encoded in the DREX byte. */
4053 else if (i.tm.opcode_modifier.drex
4054 && !i.tm.opcode_modifier.drexv
4057 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4058 if (i.types[0].bitfield.regxmm != 0
4059 && (i.types[1].bitfield.regxmm
4060 || operand_type_check(i.types[1], anymem))
4061 && i.types[2].bitfield.regxmm != 0
4062 && i.types[3].bitfield.regxmm != 0
4063 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4064 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4066 /* clear the arguments that are stored in drex */
4067 UINTS_CLEAR (i.types[0]);
4068 UINTS_CLEAR (i.types[3]);
4069 i.reg_operands -= 2;
4071 /* Specify the modrm encoding and remember the register
4072 including the high bit normally stored in the REX
4074 i.drex.modrm_reg = 2;
4075 i.drex.modrm_regmem = 1;
4076 i.drex.reg = (i.op[3].regs->reg_num
4077 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4081 as_bad (_("Incorrect operands for the '%s' instruction"),
4085 /* SSE5 3 operand instructions that the result is a register, being
4086 either operand can be a memory operand, using OC0 to note which
4087 one is the memory. */
4088 else if (i.tm.opcode_modifier.drex
4089 && i.tm.opcode_modifier.drexv
4092 i.tm.extension_opcode = None;
4094 /* Case 1: 3 operand insn, src1 = register. */
4095 if (i.types[0].bitfield.regxmm != 0
4096 && i.types[1].bitfield.regxmm != 0
4097 && i.types[2].bitfield.regxmm != 0)
4099 /* Clear the arguments that are stored in drex. */
4100 UINTS_CLEAR (i.types[2]);
4103 /* Specify the modrm encoding and remember the register
4104 including the high bit normally stored in the REX byte. */
4105 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4106 i.drex.modrm_reg = 1;
4107 i.drex.modrm_regmem = 0;
4108 i.drex.reg = (i.op[2].regs->reg_num
4109 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4112 /* Case 2: 3 operand insn, src1 = memory. */
4113 else if (operand_type_check (i.types[0], anymem) != 0
4114 && i.types[1].bitfield.regxmm != 0
4115 && i.types[2].bitfield.regxmm != 0)
4117 /* Clear the arguments that are stored in drex. */
4118 UINTS_CLEAR (i.types[2]);
4121 /* Specify the modrm encoding and remember the register
4122 including the high bit normally stored in the REX
4124 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4125 i.drex.modrm_reg = 1;
4126 i.drex.modrm_regmem = 0;
4127 i.drex.reg = (i.op[2].regs->reg_num
4128 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4131 /* Case 3: 3 operand insn, src2 = memory. */
4132 else if (i.types[0].bitfield.regxmm != 0
4133 && operand_type_check (i.types[1], anymem) != 0
4134 && i.types[2].bitfield.regxmm != 0)
4136 /* Clear the arguments that are stored in drex. */
4137 UINTS_CLEAR (i.types[2]);
4140 /* Specify the modrm encoding and remember the register
4141 including the high bit normally stored in the REX byte. */
4142 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4143 i.drex.modrm_reg = 0;
4144 i.drex.modrm_regmem = 1;
4145 i.drex.reg = (i.op[2].regs->reg_num
4146 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4150 as_bad (_("Incorrect operands for the '%s' instruction"),
4154 /* SSE5 4 operand instructions that are the comparison instructions
4155 where the first operand is the immediate value of the comparison
4157 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4159 /* Case 1: 4 operand insn, src1 = reg/memory. */
4160 if (operand_type_check (i.types[0], imm) != 0
4161 && (i.types[1].bitfield.regxmm
4162 || operand_type_check (i.types[1], anymem))
4163 && i.types[2].bitfield.regxmm != 0
4164 && i.types[3].bitfield.regxmm != 0)
4166 /* clear the arguments that are stored in drex */
4167 UINTS_CLEAR (i.types[3]);
4170 /* Specify the modrm encoding and remember the register
4171 including the high bit normally stored in the REX byte. */
4172 i.drex.modrm_reg = 2;
4173 i.drex.modrm_regmem = 1;
4174 i.drex.reg = (i.op[3].regs->reg_num
4175 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4178 /* Case 2: 3 operand insn with ImmExt that places the
4179 opcode_extension as an immediate argument. This is used for
4180 all of the varients of comparison that supplies the appropriate
4181 value as part of the instruction. */
4182 else if ((i.types[0].bitfield.regxmm
4183 || operand_type_check (i.types[0], anymem))
4184 && i.types[1].bitfield.regxmm != 0
4185 && i.types[2].bitfield.regxmm != 0
4186 && operand_type_check (i.types[3], imm) != 0)
4188 /* clear the arguments that are stored in drex */
4189 UINTS_CLEAR (i.types[2]);
4192 /* Specify the modrm encoding and remember the register
4193 including the high bit normally stored in the REX byte. */
4194 i.drex.modrm_reg = 1;
4195 i.drex.modrm_regmem = 0;
4196 i.drex.reg = (i.op[2].regs->reg_num
4197 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4201 as_bad (_("Incorrect operands for the '%s' instruction"),
4205 else if (i.tm.opcode_modifier.drex
4206 || i.tm.opcode_modifier.drexv
4207 || i.tm.opcode_modifier.drexc)
4208 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4212 process_operands (void)
4214 /* Default segment register this instruction will use for memory
4215 accesses. 0 means unknown. This is only for optimizing out
4216 unnecessary segment overrides. */
4217 const seg_entry *default_seg = 0;
4219 /* Handle all of the DREX munging that SSE5 needs. */
4220 if (i.tm.opcode_modifier.drex
4221 || i.tm.opcode_modifier.drexv
4222 || i.tm.opcode_modifier.drexc)
4225 /* The imul $imm, %reg instruction is converted into
4226 imul $imm, %reg, %reg, and the clr %reg instruction
4227 is converted into xor %reg, %reg. */
4228 if (i.tm.opcode_modifier.regkludge)
4230 if (i.tm.cpu_flags.bitfield.cpusse4_1)
4232 /* The first operand in instruction blendvpd, blendvps and
4233 pblendvb in SSE4.1 is implicit and must be xmm0. */
4234 assert (i.operands == 3
4235 && i.reg_operands >= 2
4236 && UINTS_EQUAL (i.types[0], regxmm));
4237 if (i.op[0].regs->reg_num != 0)
4240 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4241 i.tm.name, register_prefix);
4243 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4244 i.tm.name, register_prefix);
4249 i.types[0] = i.types[1];
4250 i.types[1] = i.types[2];
4254 /* We need to adjust fields in i.tm since they are used by
4255 build_modrm_byte. */
4256 i.tm.operand_types [0] = i.tm.operand_types [1];
4257 i.tm.operand_types [1] = i.tm.operand_types [2];
4262 unsigned int first_reg_op;
4264 if (operand_type_check (i.types[0], reg))
4268 /* Pretend we saw the extra register operand. */
4269 assert (i.reg_operands == 1
4270 && i.op[first_reg_op + 1].regs == 0);
4271 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4272 i.types[first_reg_op + 1] = i.types[first_reg_op];
4278 if (i.tm.opcode_modifier.shortform)
4280 if (i.types[0].bitfield.sreg2
4281 || i.types[0].bitfield.sreg3)
4283 if (i.tm.base_opcode == POP_SEG_SHORT
4284 && i.op[0].regs->reg_num == 1)
4286 as_bad (_("you can't `pop %%cs'"));
4289 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4290 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4295 /* The register or float register operand is in operand
4299 if (i.types[0].bitfield.floatreg
4300 || operand_type_check (i.types[0], reg))
4304 /* Register goes in low 3 bits of opcode. */
4305 i.tm.base_opcode |= i.op[op].regs->reg_num;
4306 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4308 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4310 /* Warn about some common errors, but press on regardless.
4311 The first case can be generated by gcc (<= 2.8.1). */
4312 if (i.operands == 2)
4314 /* Reversed arguments on faddp, fsubp, etc. */
4315 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4316 register_prefix, i.op[1].regs->reg_name,
4317 register_prefix, i.op[0].regs->reg_name);
4321 /* Extraneous `l' suffix on fp insn. */
4322 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4323 register_prefix, i.op[0].regs->reg_name);
4328 else if (i.tm.opcode_modifier.modrm)
4330 /* The opcode is completed (modulo i.tm.extension_opcode which
4331 must be put into the modrm byte). Now, we make the modrm and
4332 index base bytes based on all the info we've collected. */
4334 default_seg = build_modrm_byte ();
4336 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4340 else if (i.tm.opcode_modifier.isstring)
4342 /* For the string instructions that allow a segment override
4343 on one of their operands, the default segment is ds. */
4347 if (i.tm.base_opcode == 0x8d /* lea */
4350 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4352 /* If a segment was explicitly specified, and the specified segment
4353 is not the default, use an opcode prefix to select it. If we
4354 never figured out what the default segment is, then default_seg
4355 will be zero at this point, and the specified segment prefix will
4357 if ((i.seg[0]) && (i.seg[0] != default_seg))
4359 if (!add_prefix (i.seg[0]->seg_prefix))
4365 static const seg_entry *
4366 build_modrm_byte (void)
4368 const seg_entry *default_seg = 0;
4370 /* SSE5 4 operand instructions are encoded in such a way that one of
4371 the inputs must match the destination register. Process_drex hides
4372 the 3rd argument in the drex field, so that by the time we get
4373 here, it looks to GAS as if this is a 2 operand instruction. */
4374 if ((i.tm.opcode_modifier.drex
4375 || i.tm.opcode_modifier.drexv
4376 || i.tm.opcode_modifier.drexc)
4377 && i.reg_operands == 2)
4379 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4380 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4382 i.rm.reg = reg->reg_num;
4383 i.rm.regmem = regmem->reg_num;
4385 if ((reg->reg_flags & RegRex) != 0)
4387 if ((regmem->reg_flags & RegRex) != 0)
4391 /* i.reg_operands MUST be the number of real register operands;
4392 implicit registers do not count. */
4393 else if (i.reg_operands == 2)
4395 unsigned int source, dest;
4403 /* When there are 3 operands, one of them may be immediate,
4404 which may be the first or the last operand. Otherwise,
4405 the first operand must be shift count register (cl). */
4406 assert (i.imm_operands == 1
4407 || (i.imm_operands == 0
4408 && i.types[0].bitfield.shiftcount));
4409 if (operand_type_check (i.types[0], imm)
4410 || i.types[0].bitfield.shiftcount)
4416 /* When there are 4 operands, the first two must be immediate
4417 operands. The source operand will be the 3rd one. */
4418 assert (i.imm_operands == 2
4419 && operand_type_check (i.types[0], imm)
4420 && operand_type_check (i.types[1], imm));
4430 /* One of the register operands will be encoded in the i.tm.reg
4431 field, the other in the combined i.tm.mode and i.tm.regmem
4432 fields. If no form of this instruction supports a memory
4433 destination operand, then we assume the source operand may
4434 sometimes be a memory operand and so we need to store the
4435 destination in the i.rm.reg field. */
4436 if (!i.tm.operand_types[dest].bitfield.regmem
4437 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4439 i.rm.reg = i.op[dest].regs->reg_num;
4440 i.rm.regmem = i.op[source].regs->reg_num;
4441 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4443 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4448 i.rm.reg = i.op[source].regs->reg_num;
4449 i.rm.regmem = i.op[dest].regs->reg_num;
4450 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4452 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4455 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4457 if (!i.types[0].bitfield.control
4458 && !i.types[1].bitfield.control)
4460 i.rex &= ~(REX_R | REX_B);
4461 add_prefix (LOCK_PREFIX_OPCODE);
4465 { /* If it's not 2 reg operands... */
4468 unsigned int fake_zero_displacement = 0;
4471 /* This has been precalculated for SSE5 instructions
4472 that have a DREX field earlier in process_drex. */
4473 if (i.tm.opcode_modifier.drex
4474 || i.tm.opcode_modifier.drexv
4475 || i.tm.opcode_modifier.drexc)
4476 op = i.drex.modrm_regmem;
4479 for (op = 0; op < i.operands; op++)
4480 if (operand_type_check (i.types[op], anymem))
4482 assert (op < i.operands);
4487 if (i.base_reg == 0)
4490 if (!i.disp_operands)
4491 fake_zero_displacement = 1;
4492 if (i.index_reg == 0)
4494 /* Operand is just <disp> */
4495 if (flag_code == CODE_64BIT)
4497 /* 64bit mode overwrites the 32bit absolute
4498 addressing by RIP relative addressing and
4499 absolute addressing is encoded by one of the
4500 redundant SIB forms. */
4501 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4502 i.sib.base = NO_BASE_REGISTER;
4503 i.sib.index = NO_INDEX_REGISTER;
4504 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4505 ? disp32s : disp32);
4507 else if ((flag_code == CODE_16BIT)
4508 ^ (i.prefix[ADDR_PREFIX] != 0))
4510 i.rm.regmem = NO_BASE_REGISTER_16;
4511 i.types[op] = disp16;
4515 i.rm.regmem = NO_BASE_REGISTER;
4516 i.types[op] = disp32;
4519 else /* !i.base_reg && i.index_reg */
4521 i.sib.index = i.index_reg->reg_num;
4522 i.sib.base = NO_BASE_REGISTER;
4523 i.sib.scale = i.log2_scale_factor;
4524 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4525 i.types[op].bitfield.disp8 = 0;
4526 i.types[op].bitfield.disp16 = 0;
4527 i.types[op].bitfield.disp64 = 0;
4528 if (flag_code != CODE_64BIT)
4530 /* Must be 32 bit */
4531 i.types[op].bitfield.disp32 = 1;
4532 i.types[op].bitfield.disp32s = 0;
4536 i.types[op].bitfield.disp32 = 0;
4537 i.types[op].bitfield.disp32s = 1;
4539 if ((i.index_reg->reg_flags & RegRex) != 0)
4543 /* RIP addressing for 64bit mode. */
4544 else if (UINTS_EQUAL (i.base_reg->reg_type, baseindex))
4546 i.rm.regmem = NO_BASE_REGISTER;
4547 i.types[op].bitfield.disp8 = 0;
4548 i.types[op].bitfield.disp16 = 0;
4549 i.types[op].bitfield.disp32 = 0;
4550 i.types[op].bitfield.disp32s = 1;
4551 i.types[op].bitfield.disp64 = 0;
4552 i.flags[op] |= Operand_PCrel;
4553 if (! i.disp_operands)
4554 fake_zero_displacement = 1;
4556 else if (i.base_reg->reg_type.bitfield.reg16)
4558 switch (i.base_reg->reg_num)
4561 if (i.index_reg == 0)
4563 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4564 i.rm.regmem = i.index_reg->reg_num - 6;
4568 if (i.index_reg == 0)
4571 if (operand_type_check (i.types[op], disp) == 0)
4573 /* fake (%bp) into 0(%bp) */
4574 i.types[op].bitfield.disp8 = 1;
4575 fake_zero_displacement = 1;
4578 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4579 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4581 default: /* (%si) -> 4 or (%di) -> 5 */
4582 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4584 i.rm.mode = mode_from_disp_size (i.types[op]);
4586 else /* i.base_reg and 32/64 bit mode */
4588 if (flag_code == CODE_64BIT
4589 && operand_type_check (i.types[op], disp))
4591 i386_operand_type temp;
4593 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4595 if (i.prefix[ADDR_PREFIX] == 0)
4596 i.types[op].bitfield.disp32s = 1;
4598 i.types[op].bitfield.disp32 = 1;
4601 i.rm.regmem = i.base_reg->reg_num;
4602 if ((i.base_reg->reg_flags & RegRex) != 0)
4604 i.sib.base = i.base_reg->reg_num;
4605 /* x86-64 ignores REX prefix bit here to avoid decoder
4607 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4610 if (i.disp_operands == 0)
4612 fake_zero_displacement = 1;
4613 i.types[op].bitfield.disp8 = 1;
4616 else if (i.base_reg->reg_num == ESP_REG_NUM)
4620 i.sib.scale = i.log2_scale_factor;
4621 if (i.index_reg == 0)
4623 /* <disp>(%esp) becomes two byte modrm with no index
4624 register. We've already stored the code for esp
4625 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4626 Any base register besides %esp will not use the
4627 extra modrm byte. */
4628 i.sib.index = NO_INDEX_REGISTER;
4629 #if !SCALE1_WHEN_NO_INDEX
4630 /* Another case where we force the second modrm
4632 if (i.log2_scale_factor)
4633 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4638 i.sib.index = i.index_reg->reg_num;
4639 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4640 if ((i.index_reg->reg_flags & RegRex) != 0)
4645 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4646 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4649 i.rm.mode = mode_from_disp_size (i.types[op]);
4652 if (fake_zero_displacement)
4654 /* Fakes a zero displacement assuming that i.types[op]
4655 holds the correct displacement size. */
4658 assert (i.op[op].disps == 0);
4659 exp = &disp_expressions[i.disp_operands++];
4660 i.op[op].disps = exp;
4661 exp->X_op = O_constant;
4662 exp->X_add_number = 0;
4663 exp->X_add_symbol = (symbolS *) 0;
4664 exp->X_op_symbol = (symbolS *) 0;
4668 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4669 (if any) based on i.tm.extension_opcode. Again, we must be
4670 careful to make sure that segment/control/debug/test/MMX
4671 registers are coded into the i.rm.reg field. */
4676 /* This has been precalculated for SSE5 instructions
4677 that have a DREX field earlier in process_drex. */
4678 if (i.tm.opcode_modifier.drex
4679 || i.tm.opcode_modifier.drexv
4680 || i.tm.opcode_modifier.drexc)
4682 op = i.drex.modrm_reg;
4683 i.rm.reg = i.op[op].regs->reg_num;
4684 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4689 for (op = 0; op < i.operands; op++)
4690 if (i.types[op].bitfield.reg8
4691 || i.types[op].bitfield.reg16
4692 || i.types[op].bitfield.reg32
4693 || i.types[op].bitfield.reg64
4694 || i.types[op].bitfield.regmmx
4695 || i.types[op].bitfield.regxmm
4696 || i.types[op].bitfield.sreg2
4697 || i.types[op].bitfield.sreg3
4698 || i.types[op].bitfield.control
4699 || i.types[op].bitfield.debug
4700 || i.types[op].bitfield.test)
4703 assert (op < i.operands);
4705 /* If there is an extension opcode to put here, the
4706 register number must be put into the regmem field. */
4707 if (i.tm.extension_opcode != None)
4709 i.rm.regmem = i.op[op].regs->reg_num;
4710 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4715 i.rm.reg = i.op[op].regs->reg_num;
4716 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4721 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4722 must set it to 3 to indicate this is a register operand
4723 in the regmem field. */
4724 if (!i.mem_operands)
4728 /* Fill in i.rm.reg field with extension opcode (if any). */
4729 if (i.tm.extension_opcode != None
4730 && !(i.tm.opcode_modifier.drex
4731 || i.tm.opcode_modifier.drexv
4732 || i.tm.opcode_modifier.drexc))
4733 i.rm.reg = i.tm.extension_opcode;
4739 output_branch (void)
4744 relax_substateT subtype;
4749 if (flag_code == CODE_16BIT)
4753 if (i.prefix[DATA_PREFIX] != 0)
4759 /* Pentium4 branch hints. */
4760 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4761 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4766 if (i.prefix[REX_PREFIX] != 0)
4772 if (i.prefixes != 0 && !intel_syntax)
4773 as_warn (_("skipping prefixes on this instruction"));
4775 /* It's always a symbol; End frag & setup for relax.
4776 Make sure there is enough room in this frag for the largest
4777 instruction we may generate in md_convert_frag. This is 2
4778 bytes for the opcode and room for the prefix and largest
4780 frag_grow (prefix + 2 + 4);
4781 /* Prefix and 1 opcode byte go in fr_fix. */
4782 p = frag_more (prefix + 1);
4783 if (i.prefix[DATA_PREFIX] != 0)
4784 *p++ = DATA_PREFIX_OPCODE;
4785 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4786 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4787 *p++ = i.prefix[SEG_PREFIX];
4788 if (i.prefix[REX_PREFIX] != 0)
4789 *p++ = i.prefix[REX_PREFIX];
4790 *p = i.tm.base_opcode;
4792 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4793 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4794 else if (cpu_arch_flags.bitfield.cpui386)
4795 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4797 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4800 sym = i.op[0].disps->X_add_symbol;
4801 off = i.op[0].disps->X_add_number;
4803 if (i.op[0].disps->X_op != O_constant
4804 && i.op[0].disps->X_op != O_symbol)
4806 /* Handle complex expressions. */
4807 sym = make_expr_symbol (i.op[0].disps);
4811 /* 1 possible extra opcode + 4 byte displacement go in var part.
4812 Pass reloc in fr_var. */
4813 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4823 if (i.tm.opcode_modifier.jumpbyte)
4825 /* This is a loop or jecxz type instruction. */
4827 if (i.prefix[ADDR_PREFIX] != 0)
4829 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4832 /* Pentium4 branch hints. */
4833 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4834 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4836 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4845 if (flag_code == CODE_16BIT)
4848 if (i.prefix[DATA_PREFIX] != 0)
4850 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4860 if (i.prefix[REX_PREFIX] != 0)
4862 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4866 if (i.prefixes != 0 && !intel_syntax)
4867 as_warn (_("skipping prefixes on this instruction"));
4869 p = frag_more (1 + size);
4870 *p++ = i.tm.base_opcode;
4872 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4873 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4875 /* All jumps handled here are signed, but don't use a signed limit
4876 check for 32 and 16 bit jumps as we want to allow wrap around at
4877 4G and 64k respectively. */
4879 fixP->fx_signed = 1;
4883 output_interseg_jump (void)
4891 if (flag_code == CODE_16BIT)
4895 if (i.prefix[DATA_PREFIX] != 0)
4901 if (i.prefix[REX_PREFIX] != 0)
4911 if (i.prefixes != 0 && !intel_syntax)
4912 as_warn (_("skipping prefixes on this instruction"));
4914 /* 1 opcode; 2 segment; offset */
4915 p = frag_more (prefix + 1 + 2 + size);
4917 if (i.prefix[DATA_PREFIX] != 0)
4918 *p++ = DATA_PREFIX_OPCODE;
4920 if (i.prefix[REX_PREFIX] != 0)
4921 *p++ = i.prefix[REX_PREFIX];
4923 *p++ = i.tm.base_opcode;
4924 if (i.op[1].imms->X_op == O_constant)
4926 offsetT n = i.op[1].imms->X_add_number;
4929 && !fits_in_unsigned_word (n)
4930 && !fits_in_signed_word (n))
4932 as_bad (_("16-bit jump out of range"));
4935 md_number_to_chars (p, n, size);
4938 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4939 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4940 if (i.op[0].imms->X_op != O_constant)
4941 as_bad (_("can't handle non absolute segment in `%s'"),
4943 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4949 fragS *insn_start_frag;
4950 offsetT insn_start_off;
4952 /* Tie dwarf2 debug info to the address at the start of the insn.
4953 We can't do this after the insn has been output as the current
4954 frag may have been closed off. eg. by frag_var. */
4955 dwarf2_emit_insn (0);
4957 insn_start_frag = frag_now;
4958 insn_start_off = frag_now_fix ();
4961 if (i.tm.opcode_modifier.jump)
4963 else if (i.tm.opcode_modifier.jumpbyte
4964 || i.tm.opcode_modifier.jumpdword)
4966 else if (i.tm.opcode_modifier.jumpintersegment)
4967 output_interseg_jump ();
4970 /* Output normal instructions here. */
4973 unsigned int prefix;
4976 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4977 SSE4 and SSE5 instructions have 3 bytes. We may use one
4978 more higher byte to specify a prefix the instruction
4979 requires. Exclude instructions which are in both SSE4.2
4981 opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
4982 || i.tm.cpu_flags.bitfield.cpusse5
4983 || i.tm.cpu_flags.bitfield.cpusse4_1
4984 || (i.tm.cpu_flags.bitfield.cpusse4_2
4985 && !i.tm.cpu_flags.bitfield.cpuabm));
4988 if (i.tm.base_opcode & 0xff000000)
4990 prefix = (i.tm.base_opcode >> 24) & 0xff;
4994 else if ((i.tm.base_opcode & 0xff0000) != 0)
4996 prefix = (i.tm.base_opcode >> 16) & 0xff;
4997 if (i.tm.cpu_flags.bitfield.cpupadlock)
5000 if (prefix != REPE_PREFIX_OPCODE
5001 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5002 add_prefix (prefix);
5005 add_prefix (prefix);
5008 /* The prefix bytes. */
5010 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5016 md_number_to_chars (p, (valueT) *q, 1);
5020 /* Now the opcode; be careful about word order here! */
5021 if (fits_in_unsigned_byte (i.tm.base_opcode))
5023 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5030 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5035 /* Put out high byte first: can't use md_number_to_chars! */
5036 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5037 *p = i.tm.base_opcode & 0xff;
5039 /* On SSE5, encode the OC1 bit in the DREX field if this
5040 encoding has multiple formats. */
5041 if (i.tm.opcode_modifier.drex
5042 && i.tm.opcode_modifier.drexv
5043 && DREX_OC1 (i.tm.extension_opcode))
5044 *p |= DREX_OC1_MASK;
5047 /* Now the modrm byte and sib byte (if present). */
5048 if (i.tm.opcode_modifier.modrm)
5051 md_number_to_chars (p,
5052 (valueT) (i.rm.regmem << 0
5056 /* If i.rm.regmem == ESP (4)
5057 && i.rm.mode != (Register mode)
5059 ==> need second modrm byte. */
5060 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5062 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5065 md_number_to_chars (p,
5066 (valueT) (i.sib.base << 0
5068 | i.sib.scale << 6),
5073 /* Write the DREX byte if needed. */
5074 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5077 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5079 /* Encode the OC0 bit if this encoding has multiple
5081 if ((i.tm.opcode_modifier.drex
5082 || i.tm.opcode_modifier.drexv)
5083 && DREX_OC0 (i.tm.extension_opcode))
5084 *p |= DREX_OC0_MASK;
5087 if (i.disp_operands)
5088 output_disp (insn_start_frag, insn_start_off);
5091 output_imm (insn_start_frag, insn_start_off);
5097 pi ("" /*line*/, &i);
5099 #endif /* DEBUG386 */
5102 /* Return the size of the displacement operand N. */
5105 disp_size (unsigned int n)
5108 if (i.types[n].bitfield.disp64)
5110 else if (i.types[n].bitfield.disp8)
5112 else if (i.types[n].bitfield.disp16)
5117 /* Return the size of the immediate operand N. */
5120 imm_size (unsigned int n)
5123 if (i.types[n].bitfield.imm64)
5125 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5127 else if (i.types[n].bitfield.imm16)
5133 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5138 for (n = 0; n < i.operands; n++)
5140 if (operand_type_check (i.types[n], disp))
5142 if (i.op[n].disps->X_op == O_constant)
5144 int size = disp_size (n);
5147 val = offset_in_range (i.op[n].disps->X_add_number,
5149 p = frag_more (size);
5150 md_number_to_chars (p, val, size);
5154 enum bfd_reloc_code_real reloc_type;
5155 int size = disp_size (n);
5156 int sign = i.types[n].bitfield.disp32s;
5157 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5159 /* We can't have 8 bit displacement here. */
5160 assert (!i.types[n].bitfield.disp8);
5162 /* The PC relative address is computed relative
5163 to the instruction boundary, so in case immediate
5164 fields follows, we need to adjust the value. */
5165 if (pcrel && i.imm_operands)
5170 for (n1 = 0; n1 < i.operands; n1++)
5171 if (operand_type_check (i.types[n1], imm))
5173 /* Only one immediate is allowed for PC
5174 relative address. */
5177 i.op[n].disps->X_add_number -= sz;
5179 /* We should find the immediate. */
5183 p = frag_more (size);
5184 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5186 && GOT_symbol == i.op[n].disps->X_add_symbol
5187 && (((reloc_type == BFD_RELOC_32
5188 || reloc_type == BFD_RELOC_X86_64_32S
5189 || (reloc_type == BFD_RELOC_64
5191 && (i.op[n].disps->X_op == O_symbol
5192 || (i.op[n].disps->X_op == O_add
5193 && ((symbol_get_value_expression
5194 (i.op[n].disps->X_op_symbol)->X_op)
5196 || reloc_type == BFD_RELOC_32_PCREL))
5200 if (insn_start_frag == frag_now)
5201 add = (p - frag_now->fr_literal) - insn_start_off;
5206 add = insn_start_frag->fr_fix - insn_start_off;
5207 for (fr = insn_start_frag->fr_next;
5208 fr && fr != frag_now; fr = fr->fr_next)
5210 add += p - frag_now->fr_literal;
5215 reloc_type = BFD_RELOC_386_GOTPC;
5216 i.op[n].imms->X_add_number += add;
5218 else if (reloc_type == BFD_RELOC_64)
5219 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5221 /* Don't do the adjustment for x86-64, as there
5222 the pcrel addressing is relative to the _next_
5223 insn, and that is taken care of in other code. */
5224 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5226 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5227 i.op[n].disps, pcrel, reloc_type);
5234 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5239 for (n = 0; n < i.operands; n++)
5241 if (operand_type_check (i.types[n], imm))
5243 if (i.op[n].imms->X_op == O_constant)
5245 int size = imm_size (n);
5248 val = offset_in_range (i.op[n].imms->X_add_number,
5250 p = frag_more (size);
5251 md_number_to_chars (p, val, size);
5255 /* Not absolute_section.
5256 Need a 32-bit fixup (don't support 8bit
5257 non-absolute imms). Try to support other
5259 enum bfd_reloc_code_real reloc_type;
5260 int size = imm_size (n);
5263 if (i.types[n].bitfield.imm32s
5264 && (i.suffix == QWORD_MNEM_SUFFIX
5265 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5270 p = frag_more (size);
5271 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5273 /* This is tough to explain. We end up with this one if we
5274 * have operands that look like
5275 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5276 * obtain the absolute address of the GOT, and it is strongly
5277 * preferable from a performance point of view to avoid using
5278 * a runtime relocation for this. The actual sequence of
5279 * instructions often look something like:
5284 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5286 * The call and pop essentially return the absolute address
5287 * of the label .L66 and store it in %ebx. The linker itself
5288 * will ultimately change the first operand of the addl so
5289 * that %ebx points to the GOT, but to keep things simple, the
5290 * .o file must have this operand set so that it generates not
5291 * the absolute address of .L66, but the absolute address of
5292 * itself. This allows the linker itself simply treat a GOTPC
5293 * relocation as asking for a pcrel offset to the GOT to be
5294 * added in, and the addend of the relocation is stored in the
5295 * operand field for the instruction itself.
5297 * Our job here is to fix the operand so that it would add
5298 * the correct offset so that %ebx would point to itself. The
5299 * thing that is tricky is that .-.L66 will point to the
5300 * beginning of the instruction, so we need to further modify
5301 * the operand so that it will point to itself. There are
5302 * other cases where you have something like:
5304 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5306 * and here no correction would be required. Internally in
5307 * the assembler we treat operands of this form as not being
5308 * pcrel since the '.' is explicitly mentioned, and I wonder
5309 * whether it would simplify matters to do it this way. Who
5310 * knows. In earlier versions of the PIC patches, the
5311 * pcrel_adjust field was used to store the correction, but
5312 * since the expression is not pcrel, I felt it would be
5313 * confusing to do it this way. */
5315 if ((reloc_type == BFD_RELOC_32
5316 || reloc_type == BFD_RELOC_X86_64_32S
5317 || reloc_type == BFD_RELOC_64)
5319 && GOT_symbol == i.op[n].imms->X_add_symbol
5320 && (i.op[n].imms->X_op == O_symbol
5321 || (i.op[n].imms->X_op == O_add
5322 && ((symbol_get_value_expression
5323 (i.op[n].imms->X_op_symbol)->X_op)
5328 if (insn_start_frag == frag_now)
5329 add = (p - frag_now->fr_literal) - insn_start_off;
5334 add = insn_start_frag->fr_fix - insn_start_off;
5335 for (fr = insn_start_frag->fr_next;
5336 fr && fr != frag_now; fr = fr->fr_next)
5338 add += p - frag_now->fr_literal;
5342 reloc_type = BFD_RELOC_386_GOTPC;
5344 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5346 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5347 i.op[n].imms->X_add_number += add;
5349 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5350 i.op[n].imms, 0, reloc_type);
5356 /* x86_cons_fix_new is called via the expression parsing code when a
5357 reloc is needed. We use this hook to get the correct .got reloc. */
5358 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5359 static int cons_sign = -1;
5362 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5365 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5367 got_reloc = NO_RELOC;
5370 if (exp->X_op == O_secrel)
5372 exp->X_op = O_symbol;
5373 r = BFD_RELOC_32_SECREL;
5377 fix_new_exp (frag, off, len, exp, 0, r);
5380 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5381 # define lex_got(reloc, adjust, types) NULL
5383 /* Parse operands of the form
5384 <symbol>@GOTOFF+<nnn>
5385 and similar .plt or .got references.
5387 If we find one, set up the correct relocation in RELOC and copy the
5388 input string, minus the `@GOTOFF' into a malloc'd buffer for
5389 parsing by the calling routine. Return this buffer, and if ADJUST
5390 is non-null set it to the length of the string we removed from the
5391 input line. Otherwise return NULL. */
5393 lex_got (enum bfd_reloc_code_real *reloc,
5395 i386_operand_type *types)
5397 /* Some of the relocations depend on the size of what field is to
5398 be relocated. But in our callers i386_immediate and i386_displacement
5399 we don't yet know the operand size (this will be set by insn
5400 matching). Hence we record the word32 relocation here,
5401 and adjust the reloc according to the real size in reloc(). */
5402 static const struct {
5404 const enum bfd_reloc_code_real rel[2];
5405 const i386_operand_type types64;
5408 BFD_RELOC_X86_64_PLTOFF64 },
5409 OPERAND_TYPE_IMM64 },
5410 { "PLT", { BFD_RELOC_386_PLT32,
5411 BFD_RELOC_X86_64_PLT32 },
5412 OPERAND_TYPE_IMM32_32S_DISP32 },
5414 BFD_RELOC_X86_64_GOTPLT64 },
5415 OPERAND_TYPE_IMM64_DISP64 },
5416 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5417 BFD_RELOC_X86_64_GOTOFF64 },
5418 OPERAND_TYPE_IMM64_DISP64 },
5420 BFD_RELOC_X86_64_GOTPCREL },
5421 OPERAND_TYPE_IMM32_32S_DISP32 },
5422 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5423 BFD_RELOC_X86_64_TLSGD },
5424 OPERAND_TYPE_IMM32_32S_DISP32 },
5425 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5427 OPERAND_TYPE_NONE },
5429 BFD_RELOC_X86_64_TLSLD },
5430 OPERAND_TYPE_IMM32_32S_DISP32 },
5431 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5432 BFD_RELOC_X86_64_GOTTPOFF },
5433 OPERAND_TYPE_IMM32_32S_DISP32 },
5434 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5435 BFD_RELOC_X86_64_TPOFF32 },
5436 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5437 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5439 OPERAND_TYPE_NONE },
5440 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5441 BFD_RELOC_X86_64_DTPOFF32 },
5443 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5444 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5446 OPERAND_TYPE_NONE },
5447 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5449 OPERAND_TYPE_NONE },
5450 { "GOT", { BFD_RELOC_386_GOT32,
5451 BFD_RELOC_X86_64_GOT32 },
5452 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5453 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5454 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5455 OPERAND_TYPE_IMM32_32S_DISP32 },
5456 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5457 BFD_RELOC_X86_64_TLSDESC_CALL },
5458 OPERAND_TYPE_IMM32_32S_DISP32 },
5466 for (cp = input_line_pointer; *cp != '@'; cp++)
5467 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5470 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5474 len = strlen (gotrel[j].str);
5475 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5477 if (gotrel[j].rel[object_64bit] != 0)
5480 char *tmpbuf, *past_reloc;
5482 *reloc = gotrel[j].rel[object_64bit];
5488 if (flag_code != CODE_64BIT)
5490 types->bitfield.imm32 = 1;
5491 types->bitfield.disp32 = 1;
5494 *types = gotrel[j].types64;
5497 if (GOT_symbol == NULL)
5498 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5500 /* The length of the first part of our input line. */
5501 first = cp - input_line_pointer;
5503 /* The second part goes from after the reloc token until
5504 (and including) an end_of_line char or comma. */
5505 past_reloc = cp + 1 + len;
5507 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5509 second = cp + 1 - past_reloc;
5511 /* Allocate and copy string. The trailing NUL shouldn't
5512 be necessary, but be safe. */
5513 tmpbuf = xmalloc (first + second + 2);
5514 memcpy (tmpbuf, input_line_pointer, first);
5515 if (second != 0 && *past_reloc != ' ')
5516 /* Replace the relocation token with ' ', so that
5517 errors like foo@GOTOFF1 will be detected. */
5518 tmpbuf[first++] = ' ';
5519 memcpy (tmpbuf + first, past_reloc, second);
5520 tmpbuf[first + second] = '\0';
5524 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5525 gotrel[j].str, 1 << (5 + object_64bit));
5530 /* Might be a symbol version string. Don't as_bad here. */
5535 x86_cons (expressionS *exp, int size)
5537 if (size == 4 || (object_64bit && size == 8))
5539 /* Handle @GOTOFF and the like in an expression. */
5541 char *gotfree_input_line;
5544 save = input_line_pointer;
5545 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5546 if (gotfree_input_line)
5547 input_line_pointer = gotfree_input_line;
5551 if (gotfree_input_line)
5553 /* expression () has merrily parsed up to the end of line,
5554 or a comma - in the wrong buffer. Transfer how far
5555 input_line_pointer has moved to the right buffer. */
5556 input_line_pointer = (save
5557 + (input_line_pointer - gotfree_input_line)
5559 free (gotfree_input_line);
5560 if (exp->X_op == O_constant
5561 || exp->X_op == O_absent
5562 || exp->X_op == O_illegal
5563 || exp->X_op == O_register
5564 || exp->X_op == O_big)
5566 char c = *input_line_pointer;
5567 *input_line_pointer = 0;
5568 as_bad (_("missing or invalid expression `%s'"), save);
5569 *input_line_pointer = c;
5578 static void signed_cons (int size)
5580 if (flag_code == CODE_64BIT)
5588 pe_directive_secrel (dummy)
5589 int dummy ATTRIBUTE_UNUSED;
5596 if (exp.X_op == O_symbol)
5597 exp.X_op = O_secrel;
5599 emit_expr (&exp, 4);
5601 while (*input_line_pointer++ == ',');
5603 input_line_pointer--;
5604 demand_empty_rest_of_line ();
5609 i386_immediate (char *imm_start)
5611 char *save_input_line_pointer;
5612 char *gotfree_input_line;
5615 i386_operand_type types;
5617 UINTS_SET (types, ~0);
5619 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5621 as_bad (_("at most %d immediate operands are allowed"),
5622 MAX_IMMEDIATE_OPERANDS);
5626 exp = &im_expressions[i.imm_operands++];
5627 i.op[this_operand].imms = exp;
5629 if (is_space_char (*imm_start))
5632 save_input_line_pointer = input_line_pointer;
5633 input_line_pointer = imm_start;
5635 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5636 if (gotfree_input_line)
5637 input_line_pointer = gotfree_input_line;
5639 exp_seg = expression (exp);
5642 if (*input_line_pointer)
5643 as_bad (_("junk `%s' after expression"), input_line_pointer);
5645 input_line_pointer = save_input_line_pointer;
5646 if (gotfree_input_line)
5647 free (gotfree_input_line);
5649 if (exp->X_op == O_absent
5650 || exp->X_op == O_illegal
5651 || exp->X_op == O_big
5652 || (gotfree_input_line
5653 && (exp->X_op == O_constant
5654 || exp->X_op == O_register)))
5656 as_bad (_("missing or invalid immediate expression `%s'"),
5660 else if (exp->X_op == O_constant)
5662 /* Size it properly later. */
5663 i.types[this_operand].bitfield.imm64 = 1;
5664 /* If BFD64, sign extend val. */
5665 if (!use_rela_relocations
5666 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5668 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5670 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5671 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5672 && exp_seg != absolute_section
5673 && exp_seg != text_section
5674 && exp_seg != data_section
5675 && exp_seg != bss_section
5676 && exp_seg != undefined_section
5677 && !bfd_is_com_section (exp_seg))
5679 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5683 else if (!intel_syntax && exp->X_op == O_register)
5685 as_bad (_("illegal immediate register operand %s"), imm_start);
5690 /* This is an address. The size of the address will be
5691 determined later, depending on destination register,
5692 suffix, or the default for the section. */
5693 i.types[this_operand].bitfield.imm8 = 1;
5694 i.types[this_operand].bitfield.imm16 = 1;
5695 i.types[this_operand].bitfield.imm32 = 1;
5696 i.types[this_operand].bitfield.imm32s = 1;
5697 i.types[this_operand].bitfield.imm64 = 1;
5698 i.types[this_operand] = operand_type_and (i.types[this_operand],
5706 i386_scale (char *scale)
5709 char *save = input_line_pointer;
5711 input_line_pointer = scale;
5712 val = get_absolute_expression ();
5717 i.log2_scale_factor = 0;
5720 i.log2_scale_factor = 1;
5723 i.log2_scale_factor = 2;
5726 i.log2_scale_factor = 3;
5730 char sep = *input_line_pointer;
5732 *input_line_pointer = '\0';
5733 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5735 *input_line_pointer = sep;
5736 input_line_pointer = save;
5740 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5742 as_warn (_("scale factor of %d without an index register"),
5743 1 << i.log2_scale_factor);
5744 #if SCALE1_WHEN_NO_INDEX
5745 i.log2_scale_factor = 0;
5748 scale = input_line_pointer;
5749 input_line_pointer = save;
5754 i386_displacement (char *disp_start, char *disp_end)
5758 char *save_input_line_pointer;
5759 char *gotfree_input_line;
5761 i386_operand_type bigdisp, types = anydisp;
5764 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5766 as_bad (_("at most %d displacement operands are allowed"),
5767 MAX_MEMORY_OPERANDS);
5771 UINTS_CLEAR (bigdisp);
5772 if ((i.types[this_operand].bitfield.jumpabsolute)
5773 || (!current_templates->start->opcode_modifier.jump
5774 && !current_templates->start->opcode_modifier.jumpdword))
5776 bigdisp.bitfield.disp32 = 1;
5777 override = (i.prefix[ADDR_PREFIX] != 0);
5778 if (flag_code == CODE_64BIT)
5782 bigdisp.bitfield.disp32s = 1;
5783 bigdisp.bitfield.disp64 = 1;
5786 else if ((flag_code == CODE_16BIT) ^ override)
5788 bigdisp.bitfield.disp32 = 0;
5789 bigdisp.bitfield.disp16 = 1;
5794 /* For PC-relative branches, the width of the displacement
5795 is dependent upon data size, not address size. */
5796 override = (i.prefix[DATA_PREFIX] != 0);
5797 if (flag_code == CODE_64BIT)
5799 if (override || i.suffix == WORD_MNEM_SUFFIX)
5800 bigdisp.bitfield.disp16 = 1;
5803 bigdisp.bitfield.disp32 = 1;
5804 bigdisp.bitfield.disp32s = 1;
5810 override = (i.suffix == (flag_code != CODE_16BIT
5812 : LONG_MNEM_SUFFIX));
5813 bigdisp.bitfield.disp32 = 1;
5814 if ((flag_code == CODE_16BIT) ^ override)
5816 bigdisp.bitfield.disp32 = 0;
5817 bigdisp.bitfield.disp16 = 1;
5821 i.types[this_operand] = operand_type_or (i.types[this_operand],
5824 exp = &disp_expressions[i.disp_operands];
5825 i.op[this_operand].disps = exp;
5827 save_input_line_pointer = input_line_pointer;
5828 input_line_pointer = disp_start;
5829 END_STRING_AND_SAVE (disp_end);
5831 #ifndef GCC_ASM_O_HACK
5832 #define GCC_ASM_O_HACK 0
5835 END_STRING_AND_SAVE (disp_end + 1);
5836 if (i.types[this_operand].bitfield.baseIndex
5837 && displacement_string_end[-1] == '+')
5839 /* This hack is to avoid a warning when using the "o"
5840 constraint within gcc asm statements.
5843 #define _set_tssldt_desc(n,addr,limit,type) \
5844 __asm__ __volatile__ ( \
5846 "movw %w1,2+%0\n\t" \
5848 "movb %b1,4+%0\n\t" \
5849 "movb %4,5+%0\n\t" \
5850 "movb $0,6+%0\n\t" \
5851 "movb %h1,7+%0\n\t" \
5853 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5855 This works great except that the output assembler ends
5856 up looking a bit weird if it turns out that there is
5857 no offset. You end up producing code that looks like:
5870 So here we provide the missing zero. */
5872 *displacement_string_end = '0';
5875 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5876 if (gotfree_input_line)
5877 input_line_pointer = gotfree_input_line;
5879 exp_seg = expression (exp);
5882 if (*input_line_pointer)
5883 as_bad (_("junk `%s' after expression"), input_line_pointer);
5885 RESTORE_END_STRING (disp_end + 1);
5887 input_line_pointer = save_input_line_pointer;
5888 if (gotfree_input_line)
5889 free (gotfree_input_line);
5892 /* We do this to make sure that the section symbol is in
5893 the symbol table. We will ultimately change the relocation
5894 to be relative to the beginning of the section. */
5895 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5897 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5899 if (exp->X_op != O_symbol)
5902 if (S_IS_LOCAL (exp->X_add_symbol)
5903 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5904 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5905 exp->X_op = O_subtract;
5906 exp->X_op_symbol = GOT_symbol;
5907 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5908 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5909 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5910 i.reloc[this_operand] = BFD_RELOC_64;
5912 i.reloc[this_operand] = BFD_RELOC_32;
5915 else if (exp->X_op == O_absent
5916 || exp->X_op == O_illegal
5917 || exp->X_op == O_big
5918 || (gotfree_input_line
5919 && (exp->X_op == O_constant
5920 || exp->X_op == O_register)))
5923 as_bad (_("missing or invalid displacement expression `%s'"),
5928 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5929 else if (exp->X_op != O_constant
5930 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5931 && exp_seg != absolute_section
5932 && exp_seg != text_section
5933 && exp_seg != data_section
5934 && exp_seg != bss_section
5935 && exp_seg != undefined_section
5936 && !bfd_is_com_section (exp_seg))
5938 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5943 RESTORE_END_STRING (disp_end);
5945 /* Check if this is a displacement only operand. */
5946 bigdisp = i.types[this_operand];
5947 bigdisp.bitfield.disp8 = 0;
5948 bigdisp.bitfield.disp16 = 0;
5949 bigdisp.bitfield.disp32 = 0;
5950 bigdisp.bitfield.disp32s = 0;
5951 bigdisp.bitfield.disp64 = 0;
5952 if (UINTS_ALL_ZERO (bigdisp))
5953 i.types[this_operand] = operand_type_and (i.types[this_operand],
5959 /* Make sure the memory operand we've been dealt is valid.
5960 Return 1 on success, 0 on a failure. */
5963 i386_index_check (const char *operand_string)
5966 #if INFER_ADDR_PREFIX
5972 if (flag_code == CODE_64BIT)
5975 && ((i.prefix[ADDR_PREFIX] == 0
5976 && !i.base_reg->reg_type.bitfield.reg64)
5977 || (i.prefix[ADDR_PREFIX]
5978 && !i.base_reg->reg_type.bitfield.reg32))
5980 || !UINTS_EQUAL (i.base_reg->reg_type, baseindex)))
5982 && (!i.index_reg->reg_type.bitfield.baseindex
5983 || (i.prefix[ADDR_PREFIX] == 0
5984 && !i.index_reg->reg_type.bitfield.reg64)
5985 || (i.prefix[ADDR_PREFIX]
5986 && !i.index_reg->reg_type.bitfield.reg32))))
5991 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5995 && (!i.base_reg->reg_type.bitfield.reg16
5996 || !i.base_reg->reg_type.bitfield.baseindex))
5998 && (!i.index_reg->reg_type.bitfield.reg16
5999 || !i.index_reg->reg_type.bitfield.baseindex
6001 && i.base_reg->reg_num < 6
6002 && i.index_reg->reg_num >= 6
6003 && i.log2_scale_factor == 0))))
6010 && !i.base_reg->reg_type.bitfield.reg32)
6012 && (!i.index_reg->reg_type.bitfield.reg32
6013 || !i.index_reg->reg_type.bitfield.baseindex)))
6019 #if INFER_ADDR_PREFIX
6020 if (i.prefix[ADDR_PREFIX] == 0)
6022 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6024 /* Change the size of any displacement too. At most one of
6025 Disp16 or Disp32 is set.
6026 FIXME. There doesn't seem to be any real need for separate
6027 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6028 Removing them would probably clean up the code quite a lot. */
6029 if (flag_code != CODE_64BIT
6030 && (i.types[this_operand].bitfield.disp16
6031 || i.types[this_operand].bitfield.disp32))
6032 i.types[this_operand]
6033 = operand_type_xor (i.types[this_operand], disp16_32);
6038 as_bad (_("`%s' is not a valid base/index expression"),
6042 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6044 flag_code_names[flag_code]);
6049 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6053 i386_operand (char *operand_string)
6057 char *op_string = operand_string;
6059 if (is_space_char (*op_string))
6062 /* We check for an absolute prefix (differentiating,
6063 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6064 if (*op_string == ABSOLUTE_PREFIX)
6067 if (is_space_char (*op_string))
6069 i.types[this_operand].bitfield.jumpabsolute = 1;
6072 /* Check if operand is a register. */
6073 if ((r = parse_register (op_string, &end_op)) != NULL)
6075 i386_operand_type temp;
6077 /* Check for a segment override by searching for ':' after a
6078 segment register. */
6080 if (is_space_char (*op_string))
6082 if (*op_string == ':'
6083 && (r->reg_type.bitfield.sreg2
6084 || r->reg_type.bitfield.sreg3))
6089 i.seg[i.mem_operands] = &es;
6092 i.seg[i.mem_operands] = &cs;
6095 i.seg[i.mem_operands] = &ss;
6098 i.seg[i.mem_operands] = &ds;
6101 i.seg[i.mem_operands] = &fs;
6104 i.seg[i.mem_operands] = &gs;
6108 /* Skip the ':' and whitespace. */
6110 if (is_space_char (*op_string))
6113 if (!is_digit_char (*op_string)
6114 && !is_identifier_char (*op_string)
6115 && *op_string != '('
6116 && *op_string != ABSOLUTE_PREFIX)
6118 as_bad (_("bad memory operand `%s'"), op_string);
6121 /* Handle case of %es:*foo. */
6122 if (*op_string == ABSOLUTE_PREFIX)
6125 if (is_space_char (*op_string))
6127 i.types[this_operand].bitfield.jumpabsolute = 1;
6129 goto do_memory_reference;
6133 as_bad (_("junk `%s' after register"), op_string);
6137 temp.bitfield.baseindex = 0;
6138 i.types[this_operand] = operand_type_or (i.types[this_operand],
6140 i.op[this_operand].regs = r;
6143 else if (*op_string == REGISTER_PREFIX)
6145 as_bad (_("bad register name `%s'"), op_string);
6148 else if (*op_string == IMMEDIATE_PREFIX)
6151 if (i.types[this_operand].bitfield.jumpabsolute)
6153 as_bad (_("immediate operand illegal with absolute jump"));
6156 if (!i386_immediate (op_string))
6159 else if (is_digit_char (*op_string)
6160 || is_identifier_char (*op_string)
6161 || *op_string == '(')
6163 /* This is a memory reference of some sort. */
6166 /* Start and end of displacement string expression (if found). */
6167 char *displacement_string_start;
6168 char *displacement_string_end;
6170 do_memory_reference:
6171 if ((i.mem_operands == 1
6172 && !current_templates->start->opcode_modifier.isstring)
6173 || i.mem_operands == 2)
6175 as_bad (_("too many memory references for `%s'"),
6176 current_templates->start->name);
6180 /* Check for base index form. We detect the base index form by
6181 looking for an ')' at the end of the operand, searching
6182 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6184 base_string = op_string + strlen (op_string);
6187 if (is_space_char (*base_string))
6190 /* If we only have a displacement, set-up for it to be parsed later. */
6191 displacement_string_start = op_string;
6192 displacement_string_end = base_string + 1;
6194 if (*base_string == ')')
6197 unsigned int parens_balanced = 1;
6198 /* We've already checked that the number of left & right ()'s are
6199 equal, so this loop will not be infinite. */
6203 if (*base_string == ')')
6205 if (*base_string == '(')
6208 while (parens_balanced);
6210 temp_string = base_string;
6212 /* Skip past '(' and whitespace. */
6214 if (is_space_char (*base_string))
6217 if (*base_string == ','
6218 || ((i.base_reg = parse_register (base_string, &end_op))
6221 displacement_string_end = temp_string;
6223 i.types[this_operand].bitfield.baseindex = 1;
6227 base_string = end_op;
6228 if (is_space_char (*base_string))
6232 /* There may be an index reg or scale factor here. */
6233 if (*base_string == ',')
6236 if (is_space_char (*base_string))
6239 if ((i.index_reg = parse_register (base_string, &end_op))
6242 base_string = end_op;
6243 if (is_space_char (*base_string))
6245 if (*base_string == ',')
6248 if (is_space_char (*base_string))
6251 else if (*base_string != ')')
6253 as_bad (_("expecting `,' or `)' "
6254 "after index register in `%s'"),
6259 else if (*base_string == REGISTER_PREFIX)
6261 as_bad (_("bad register name `%s'"), base_string);
6265 /* Check for scale factor. */
6266 if (*base_string != ')')
6268 char *end_scale = i386_scale (base_string);
6273 base_string = end_scale;
6274 if (is_space_char (*base_string))
6276 if (*base_string != ')')
6278 as_bad (_("expecting `)' "
6279 "after scale factor in `%s'"),
6284 else if (!i.index_reg)
6286 as_bad (_("expecting index register or scale factor "
6287 "after `,'; got '%c'"),
6292 else if (*base_string != ')')
6294 as_bad (_("expecting `,' or `)' "
6295 "after base register in `%s'"),
6300 else if (*base_string == REGISTER_PREFIX)
6302 as_bad (_("bad register name `%s'"), base_string);
6307 /* If there's an expression beginning the operand, parse it,
6308 assuming displacement_string_start and
6309 displacement_string_end are meaningful. */
6310 if (displacement_string_start != displacement_string_end)
6312 if (!i386_displacement (displacement_string_start,
6313 displacement_string_end))
6317 /* Special case for (%dx) while doing input/output op. */
6319 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6321 && i.log2_scale_factor == 0
6322 && i.seg[i.mem_operands] == 0
6323 && !operand_type_check (i.types[this_operand], disp))
6325 UINTS_CLEAR (i.types[this_operand]);
6326 i.types[this_operand].bitfield.inoutportreg = 1;
6330 if (i386_index_check (operand_string) == 0)
6336 /* It's not a memory operand; argh! */
6337 as_bad (_("invalid char %s beginning operand %d `%s'"),
6338 output_invalid (*op_string),
6343 return 1; /* Normal return. */
6346 /* md_estimate_size_before_relax()
6348 Called just before relax() for rs_machine_dependent frags. The x86
6349 assembler uses these frags to handle variable size jump
6352 Any symbol that is now undefined will not become defined.
6353 Return the correct fr_subtype in the frag.
6354 Return the initial "guess for variable size of frag" to caller.
6355 The guess is actually the growth beyond the fixed part. Whatever
6356 we do to grow the fixed or variable part contributes to our
6360 md_estimate_size_before_relax (fragP, segment)
6364 /* We've already got fragP->fr_subtype right; all we have to do is
6365 check for un-relaxable symbols. On an ELF system, we can't relax
6366 an externally visible symbol, because it may be overridden by a
6368 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6371 && (S_IS_EXTERNAL (fragP->fr_symbol)
6372 || S_IS_WEAK (fragP->fr_symbol)))
6376 /* Symbol is undefined in this segment, or we need to keep a
6377 reloc so that weak symbols can be overridden. */
6378 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6379 enum bfd_reloc_code_real reloc_type;
6380 unsigned char *opcode;
6383 if (fragP->fr_var != NO_RELOC)
6384 reloc_type = fragP->fr_var;
6386 reloc_type = BFD_RELOC_16_PCREL;
6388 reloc_type = BFD_RELOC_32_PCREL;
6390 old_fr_fix = fragP->fr_fix;
6391 opcode = (unsigned char *) fragP->fr_opcode;
6393 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6396 /* Make jmp (0xeb) a (d)word displacement jump. */
6398 fragP->fr_fix += size;
6399 fix_new (fragP, old_fr_fix, size,
6401 fragP->fr_offset, 1,
6407 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6409 /* Negate the condition, and branch past an
6410 unconditional jump. */
6413 /* Insert an unconditional jump. */
6415 /* We added two extra opcode bytes, and have a two byte
6417 fragP->fr_fix += 2 + 2;
6418 fix_new (fragP, old_fr_fix + 2, 2,
6420 fragP->fr_offset, 1,
6427 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6432 fixP = fix_new (fragP, old_fr_fix, 1,
6434 fragP->fr_offset, 1,
6436 fixP->fx_signed = 1;
6440 /* This changes the byte-displacement jump 0x7N
6441 to the (d)word-displacement jump 0x0f,0x8N. */
6442 opcode[1] = opcode[0] + 0x10;
6443 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6444 /* We've added an opcode byte. */
6445 fragP->fr_fix += 1 + size;
6446 fix_new (fragP, old_fr_fix + 1, size,
6448 fragP->fr_offset, 1,
6453 BAD_CASE (fragP->fr_subtype);
6457 return fragP->fr_fix - old_fr_fix;
6460 /* Guess size depending on current relax state. Initially the relax
6461 state will correspond to a short jump and we return 1, because
6462 the variable part of the frag (the branch offset) is one byte
6463 long. However, we can relax a section more than once and in that
6464 case we must either set fr_subtype back to the unrelaxed state,
6465 or return the value for the appropriate branch. */
6466 return md_relax_table[fragP->fr_subtype].rlx_length;
6469 /* Called after relax() is finished.
6471 In: Address of frag.
6472 fr_type == rs_machine_dependent.
6473 fr_subtype is what the address relaxed to.
6475 Out: Any fixSs and constants are set up.
6476 Caller will turn frag into a ".space 0". */
6479 md_convert_frag (abfd, sec, fragP)
6480 bfd *abfd ATTRIBUTE_UNUSED;
6481 segT sec ATTRIBUTE_UNUSED;
6484 unsigned char *opcode;
6485 unsigned char *where_to_put_displacement = NULL;
6486 offsetT target_address;
6487 offsetT opcode_address;
6488 unsigned int extension = 0;
6489 offsetT displacement_from_opcode_start;
6491 opcode = (unsigned char *) fragP->fr_opcode;
6493 /* Address we want to reach in file space. */
6494 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6496 /* Address opcode resides at in file space. */
6497 opcode_address = fragP->fr_address + fragP->fr_fix;
6499 /* Displacement from opcode start to fill into instruction. */
6500 displacement_from_opcode_start = target_address - opcode_address;
6502 if ((fragP->fr_subtype & BIG) == 0)
6504 /* Don't have to change opcode. */
6505 extension = 1; /* 1 opcode + 1 displacement */
6506 where_to_put_displacement = &opcode[1];
6510 if (no_cond_jump_promotion
6511 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6512 as_warn_where (fragP->fr_file, fragP->fr_line,
6513 _("long jump required"));
6515 switch (fragP->fr_subtype)
6517 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6518 extension = 4; /* 1 opcode + 4 displacement */
6520 where_to_put_displacement = &opcode[1];
6523 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6524 extension = 2; /* 1 opcode + 2 displacement */
6526 where_to_put_displacement = &opcode[1];
6529 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6530 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6531 extension = 5; /* 2 opcode + 4 displacement */
6532 opcode[1] = opcode[0] + 0x10;
6533 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6534 where_to_put_displacement = &opcode[2];
6537 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6538 extension = 3; /* 2 opcode + 2 displacement */
6539 opcode[1] = opcode[0] + 0x10;
6540 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6541 where_to_put_displacement = &opcode[2];
6544 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6549 where_to_put_displacement = &opcode[3];
6553 BAD_CASE (fragP->fr_subtype);
6558 /* If size if less then four we are sure that the operand fits,
6559 but if it's 4, then it could be that the displacement is larger
6561 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6563 && ((addressT) (displacement_from_opcode_start - extension
6564 + ((addressT) 1 << 31))
6565 > (((addressT) 2 << 31) - 1)))
6567 as_bad_where (fragP->fr_file, fragP->fr_line,
6568 _("jump target out of range"));
6569 /* Make us emit 0. */
6570 displacement_from_opcode_start = extension;
6572 /* Now put displacement after opcode. */
6573 md_number_to_chars ((char *) where_to_put_displacement,
6574 (valueT) (displacement_from_opcode_start - extension),
6575 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6576 fragP->fr_fix += extension;
6579 /* Size of byte displacement jmp. */
6580 int md_short_jump_size = 2;
6582 /* Size of dword displacement jmp. */
6583 int md_long_jump_size = 5;
6586 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6588 addressT from_addr, to_addr;
6589 fragS *frag ATTRIBUTE_UNUSED;
6590 symbolS *to_symbol ATTRIBUTE_UNUSED;
6594 offset = to_addr - (from_addr + 2);
6595 /* Opcode for byte-disp jump. */
6596 md_number_to_chars (ptr, (valueT) 0xeb, 1);
6597 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6601 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6603 addressT from_addr, to_addr;
6604 fragS *frag ATTRIBUTE_UNUSED;
6605 symbolS *to_symbol ATTRIBUTE_UNUSED;
6609 offset = to_addr - (from_addr + 5);
6610 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6611 md_number_to_chars (ptr + 1, (valueT) offset, 4);
6614 /* Apply a fixup (fixS) to segment data, once it has been determined
6615 by our caller that we have all the info we need to fix it up.
6617 On the 386, immediates, displacements, and data pointers are all in
6618 the same (little-endian) format, so we don't need to care about which
6622 md_apply_fix (fixP, valP, seg)
6623 /* The fix we're to put in. */
6625 /* Pointer to the value of the bits. */
6627 /* Segment fix is from. */
6628 segT seg ATTRIBUTE_UNUSED;
6630 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6631 valueT value = *valP;
6633 #if !defined (TE_Mach)
6636 switch (fixP->fx_r_type)
6642 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6645 case BFD_RELOC_X86_64_32S:
6646 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6649 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6652 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6657 if (fixP->fx_addsy != NULL
6658 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6659 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6660 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6661 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6662 && !use_rela_relocations)
6664 /* This is a hack. There should be a better way to handle this.
6665 This covers for the fact that bfd_install_relocation will
6666 subtract the current location (for partial_inplace, PC relative
6667 relocations); see more below. */
6671 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6674 value += fixP->fx_where + fixP->fx_frag->fr_address;
6676 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6679 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6682 || (symbol_section_p (fixP->fx_addsy)
6683 && sym_seg != absolute_section))
6684 && !generic_force_reloc (fixP))
6686 /* Yes, we add the values in twice. This is because
6687 bfd_install_relocation subtracts them out again. I think
6688 bfd_install_relocation is broken, but I don't dare change
6690 value += fixP->fx_where + fixP->fx_frag->fr_address;
6694 #if defined (OBJ_COFF) && defined (TE_PE)
6695 /* For some reason, the PE format does not store a
6696 section address offset for a PC relative symbol. */
6697 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6698 || S_IS_WEAK (fixP->fx_addsy))
6699 value += md_pcrel_from (fixP);
6703 /* Fix a few things - the dynamic linker expects certain values here,
6704 and we must not disappoint it. */
6705 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6706 if (IS_ELF && fixP->fx_addsy)
6707 switch (fixP->fx_r_type)
6709 case BFD_RELOC_386_PLT32:
6710 case BFD_RELOC_X86_64_PLT32:
6711 /* Make the jump instruction point to the address of the operand. At
6712 runtime we merely add the offset to the actual PLT entry. */
6716 case BFD_RELOC_386_TLS_GD:
6717 case BFD_RELOC_386_TLS_LDM:
6718 case BFD_RELOC_386_TLS_IE_32:
6719 case BFD_RELOC_386_TLS_IE:
6720 case BFD_RELOC_386_TLS_GOTIE:
6721 case BFD_RELOC_386_TLS_GOTDESC:
6722 case BFD_RELOC_X86_64_TLSGD:
6723 case BFD_RELOC_X86_64_TLSLD:
6724 case BFD_RELOC_X86_64_GOTTPOFF:
6725 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6726 value = 0; /* Fully resolved at runtime. No addend. */
6728 case BFD_RELOC_386_TLS_LE:
6729 case BFD_RELOC_386_TLS_LDO_32:
6730 case BFD_RELOC_386_TLS_LE_32:
6731 case BFD_RELOC_X86_64_DTPOFF32:
6732 case BFD_RELOC_X86_64_DTPOFF64:
6733 case BFD_RELOC_X86_64_TPOFF32:
6734 case BFD_RELOC_X86_64_TPOFF64:
6735 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6738 case BFD_RELOC_386_TLS_DESC_CALL:
6739 case BFD_RELOC_X86_64_TLSDESC_CALL:
6740 value = 0; /* Fully resolved at runtime. No addend. */
6741 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6745 case BFD_RELOC_386_GOT32:
6746 case BFD_RELOC_X86_64_GOT32:
6747 value = 0; /* Fully resolved at runtime. No addend. */
6750 case BFD_RELOC_VTABLE_INHERIT:
6751 case BFD_RELOC_VTABLE_ENTRY:
6758 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6760 #endif /* !defined (TE_Mach) */
6762 /* Are we finished with this relocation now? */
6763 if (fixP->fx_addsy == NULL)
6765 else if (use_rela_relocations)
6767 fixP->fx_no_overflow = 1;
6768 /* Remember value for tc_gen_reloc. */
6769 fixP->fx_addnumber = value;
6773 md_number_to_chars (p, value, fixP->fx_size);
6776 #define MAX_LITTLENUMS 6
6778 /* Turn the string pointed to by litP into a floating point constant
6779 of type TYPE, and emit the appropriate bytes. The number of
6780 LITTLENUMS emitted is stored in *SIZEP. An error message is
6781 returned, or NULL on OK. */
6784 md_atof (type, litP, sizeP)
6790 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6791 LITTLENUM_TYPE *wordP;
6813 return _("Bad call to md_atof ()");
6815 t = atof_ieee (input_line_pointer, type, words);
6817 input_line_pointer = t;
6819 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6820 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6821 the bigendian 386. */
6822 for (wordP = words + prec - 1; prec--;)
6824 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6825 litP += sizeof (LITTLENUM_TYPE);
6830 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6833 output_invalid (int c)
6836 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6839 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6840 "(0x%x)", (unsigned char) c);
6841 return output_invalid_buf;
6844 /* REG_STRING starts *before* REGISTER_PREFIX. */
6846 static const reg_entry *
6847 parse_real_register (char *reg_string, char **end_op)
6849 char *s = reg_string;
6851 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6854 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6855 if (*s == REGISTER_PREFIX)
6858 if (is_space_char (*s))
6862 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6864 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6865 return (const reg_entry *) NULL;
6869 /* For naked regs, make sure that we are not dealing with an identifier.
6870 This prevents confusing an identifier like `eax_var' with register
6872 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6873 return (const reg_entry *) NULL;
6877 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6879 /* Handle floating point regs, allowing spaces in the (i) part. */
6880 if (r == i386_regtab /* %st is first entry of table */)
6882 if (is_space_char (*s))
6887 if (is_space_char (*s))
6889 if (*s >= '0' && *s <= '7')
6893 if (is_space_char (*s))
6898 r = hash_find (reg_hash, "st(0)");
6903 /* We have "%st(" then garbage. */
6904 return (const reg_entry *) NULL;
6909 && ((r->reg_flags & (RegRex64 | RegRex))
6910 || r->reg_type.bitfield.reg64)
6911 && (!cpu_arch_flags.bitfield.cpulm
6912 || !UINTS_EQUAL (r->reg_type, control))
6913 && flag_code != CODE_64BIT)
6914 return (const reg_entry *) NULL;
6919 /* REG_STRING starts *before* REGISTER_PREFIX. */
6921 static const reg_entry *
6922 parse_register (char *reg_string, char **end_op)
6926 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6927 r = parse_real_register (reg_string, end_op);
6932 char *save = input_line_pointer;
6936 input_line_pointer = reg_string;
6937 c = get_symbol_end ();
6938 symbolP = symbol_find (reg_string);
6939 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6941 const expressionS *e = symbol_get_value_expression (symbolP);
6943 know (e->X_op == O_register);
6944 know (e->X_add_number >= 0
6945 && (valueT) e->X_add_number < i386_regtab_size);
6946 r = i386_regtab + e->X_add_number;
6947 *end_op = input_line_pointer;
6949 *input_line_pointer = c;
6950 input_line_pointer = save;
6956 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6959 char *end = input_line_pointer;
6962 r = parse_register (name, &input_line_pointer);
6963 if (r && end <= input_line_pointer)
6965 *nextcharP = *input_line_pointer;
6966 *input_line_pointer = 0;
6967 e->X_op = O_register;
6968 e->X_add_number = r - i386_regtab;
6971 input_line_pointer = end;
6977 md_operand (expressionS *e)
6979 if (*input_line_pointer == REGISTER_PREFIX)
6982 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6986 e->X_op = O_register;
6987 e->X_add_number = r - i386_regtab;
6988 input_line_pointer = end;
6994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6995 const char *md_shortopts = "kVQ:sqn";
6997 const char *md_shortopts = "qn";
7000 #define OPTION_32 (OPTION_MD_BASE + 0)
7001 #define OPTION_64 (OPTION_MD_BASE + 1)
7002 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7003 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7004 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7006 struct option md_longopts[] =
7008 {"32", no_argument, NULL, OPTION_32},
7009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7010 {"64", no_argument, NULL, OPTION_64},
7012 {"divide", no_argument, NULL, OPTION_DIVIDE},
7013 {"march", required_argument, NULL, OPTION_MARCH},
7014 {"mtune", required_argument, NULL, OPTION_MTUNE},
7015 {NULL, no_argument, NULL, 0}
7017 size_t md_longopts_size = sizeof (md_longopts);
7020 md_parse_option (int c, char *arg)
7027 optimize_align_code = 0;
7034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7035 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7036 should be emitted or not. FIXME: Not implemented. */
7040 /* -V: SVR4 argument to print version ID. */
7042 print_version_id ();
7045 /* -k: Ignore for FreeBSD compatibility. */
7050 /* -s: On i386 Solaris, this tells the native assembler to use
7051 .stab instead of .stab.excl. We always use .stab anyhow. */
7054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7057 const char **list, **l;
7059 list = bfd_target_list ();
7060 for (l = list; *l != NULL; l++)
7061 if (CONST_STRNEQ (*l, "elf64-x86-64")
7062 || strcmp (*l, "coff-x86-64") == 0
7063 || strcmp (*l, "pe-x86-64") == 0
7064 || strcmp (*l, "pei-x86-64") == 0)
7066 default_arch = "x86_64";
7070 as_fatal (_("No compiled in support for x86_64"));
7077 default_arch = "i386";
7081 #ifdef SVR4_COMMENT_CHARS
7086 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7088 for (s = i386_comment_chars; *s != '\0'; s++)
7092 i386_comment_chars = n;
7099 as_fatal (_("Invalid -march= option: `%s'"), arg);
7100 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7102 if (strcmp (arg, cpu_arch [i].name) == 0)
7104 cpu_arch_isa = cpu_arch[i].type;
7105 cpu_arch_isa_flags = cpu_arch[i].flags;
7106 if (!cpu_arch_tune_set)
7108 cpu_arch_tune = cpu_arch_isa;
7109 cpu_arch_tune_flags = cpu_arch_isa_flags;
7114 if (i >= ARRAY_SIZE (cpu_arch))
7115 as_fatal (_("Invalid -march= option: `%s'"), arg);
7120 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7121 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7123 if (strcmp (arg, cpu_arch [i].name) == 0)
7125 cpu_arch_tune_set = 1;
7126 cpu_arch_tune = cpu_arch [i].type;
7127 cpu_arch_tune_flags = cpu_arch[i].flags;
7131 if (i >= ARRAY_SIZE (cpu_arch))
7132 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7142 md_show_usage (stream)
7145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7146 fprintf (stream, _("\
7148 -V print assembler version number\n\
7151 fprintf (stream, _("\
7152 -n Do not optimize code alignment\n\
7153 -q quieten some warnings\n"));
7154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7155 fprintf (stream, _("\
7158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7159 fprintf (stream, _("\
7160 --32/--64 generate 32bit/64bit code\n"));
7162 #ifdef SVR4_COMMENT_CHARS
7163 fprintf (stream, _("\
7164 --divide do not treat `/' as a comment character\n"));
7166 fprintf (stream, _("\
7167 --divide ignored\n"));
7169 fprintf (stream, _("\
7170 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7171 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7172 core, core2, k6, athlon, k8, generic32, generic64\n"));
7176 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7177 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7179 /* Pick the target format to use. */
7182 i386_target_format (void)
7184 if (!strcmp (default_arch, "x86_64"))
7186 set_code_flag (CODE_64BIT);
7187 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7189 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7190 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7191 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7192 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7193 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7194 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7195 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7196 cpu_arch_isa_flags.bitfield.cpummx= 1;
7197 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7198 cpu_arch_isa_flags.bitfield.cpusse = 1;
7199 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7201 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7203 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7204 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7205 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7207 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7208 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7209 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7210 cpu_arch_tune_flags.bitfield.cpummx= 1;
7211 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7212 cpu_arch_tune_flags.bitfield.cpusse = 1;
7213 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7216 else if (!strcmp (default_arch, "i386"))
7218 set_code_flag (CODE_32BIT);
7219 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7221 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7222 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7223 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7225 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7227 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7228 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7229 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7233 as_fatal (_("Unknown architecture"));
7234 switch (OUTPUT_FLAVOR)
7237 case bfd_target_coff_flavour:
7238 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7241 #ifdef OBJ_MAYBE_AOUT
7242 case bfd_target_aout_flavour:
7243 return AOUT_TARGET_FORMAT;
7245 #ifdef OBJ_MAYBE_COFF
7246 case bfd_target_coff_flavour:
7249 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7250 case bfd_target_elf_flavour:
7252 if (flag_code == CODE_64BIT)
7255 use_rela_relocations = 1;
7257 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7266 #endif /* OBJ_MAYBE_ more than one */
7268 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7270 i386_elf_emit_arch_note (void)
7272 if (IS_ELF && cpu_arch_name != NULL)
7275 asection *seg = now_seg;
7276 subsegT subseg = now_subseg;
7277 Elf_Internal_Note i_note;
7278 Elf_External_Note e_note;
7279 asection *note_secp;
7282 /* Create the .note section. */
7283 note_secp = subseg_new (".note", 0);
7284 bfd_set_section_flags (stdoutput,
7286 SEC_HAS_CONTENTS | SEC_READONLY);
7288 /* Process the arch string. */
7289 len = strlen (cpu_arch_name);
7291 i_note.namesz = len + 1;
7293 i_note.type = NT_ARCH;
7294 p = frag_more (sizeof (e_note.namesz));
7295 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7296 p = frag_more (sizeof (e_note.descsz));
7297 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7298 p = frag_more (sizeof (e_note.type));
7299 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7300 p = frag_more (len + 1);
7301 strcpy (p, cpu_arch_name);
7303 frag_align (2, 0, 0);
7305 subseg_set (seg, subseg);
7311 md_undefined_symbol (name)
7314 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7315 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7316 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7317 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7321 if (symbol_find (name))
7322 as_bad (_("GOT already in symbol table"));
7323 GOT_symbol = symbol_new (name, undefined_section,
7324 (valueT) 0, &zero_address_frag);
7331 /* Round up a section size to the appropriate boundary. */
7334 md_section_align (segment, size)
7335 segT segment ATTRIBUTE_UNUSED;
7338 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7339 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7341 /* For a.out, force the section size to be aligned. If we don't do
7342 this, BFD will align it for us, but it will not write out the
7343 final bytes of the section. This may be a bug in BFD, but it is
7344 easier to fix it here since that is how the other a.out targets
7348 align = bfd_get_section_alignment (stdoutput, segment);
7349 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7356 /* On the i386, PC-relative offsets are relative to the start of the
7357 next instruction. That is, the address of the offset, plus its
7358 size, since the offset is always the last part of the insn. */
7361 md_pcrel_from (fixS *fixP)
7363 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7369 s_bss (int ignore ATTRIBUTE_UNUSED)
7373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7375 obj_elf_section_change_hook ();
7377 temp = get_absolute_expression ();
7378 subseg_set (bss_section, (subsegT) temp);
7379 demand_empty_rest_of_line ();
7385 i386_validate_fix (fixS *fixp)
7387 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7389 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7393 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7398 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7400 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7407 tc_gen_reloc (section, fixp)
7408 asection *section ATTRIBUTE_UNUSED;
7412 bfd_reloc_code_real_type code;
7414 switch (fixp->fx_r_type)
7416 case BFD_RELOC_X86_64_PLT32:
7417 case BFD_RELOC_X86_64_GOT32:
7418 case BFD_RELOC_X86_64_GOTPCREL:
7419 case BFD_RELOC_386_PLT32:
7420 case BFD_RELOC_386_GOT32:
7421 case BFD_RELOC_386_GOTOFF:
7422 case BFD_RELOC_386_GOTPC:
7423 case BFD_RELOC_386_TLS_GD:
7424 case BFD_RELOC_386_TLS_LDM:
7425 case BFD_RELOC_386_TLS_LDO_32:
7426 case BFD_RELOC_386_TLS_IE_32:
7427 case BFD_RELOC_386_TLS_IE:
7428 case BFD_RELOC_386_TLS_GOTIE:
7429 case BFD_RELOC_386_TLS_LE_32:
7430 case BFD_RELOC_386_TLS_LE:
7431 case BFD_RELOC_386_TLS_GOTDESC:
7432 case BFD_RELOC_386_TLS_DESC_CALL:
7433 case BFD_RELOC_X86_64_TLSGD:
7434 case BFD_RELOC_X86_64_TLSLD:
7435 case BFD_RELOC_X86_64_DTPOFF32:
7436 case BFD_RELOC_X86_64_DTPOFF64:
7437 case BFD_RELOC_X86_64_GOTTPOFF:
7438 case BFD_RELOC_X86_64_TPOFF32:
7439 case BFD_RELOC_X86_64_TPOFF64:
7440 case BFD_RELOC_X86_64_GOTOFF64:
7441 case BFD_RELOC_X86_64_GOTPC32:
7442 case BFD_RELOC_X86_64_GOT64:
7443 case BFD_RELOC_X86_64_GOTPCREL64:
7444 case BFD_RELOC_X86_64_GOTPC64:
7445 case BFD_RELOC_X86_64_GOTPLT64:
7446 case BFD_RELOC_X86_64_PLTOFF64:
7447 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7448 case BFD_RELOC_X86_64_TLSDESC_CALL:
7450 case BFD_RELOC_VTABLE_ENTRY:
7451 case BFD_RELOC_VTABLE_INHERIT:
7453 case BFD_RELOC_32_SECREL:
7455 code = fixp->fx_r_type;
7457 case BFD_RELOC_X86_64_32S:
7458 if (!fixp->fx_pcrel)
7460 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7461 code = fixp->fx_r_type;
7467 switch (fixp->fx_size)
7470 as_bad_where (fixp->fx_file, fixp->fx_line,
7471 _("can not do %d byte pc-relative relocation"),
7473 code = BFD_RELOC_32_PCREL;
7475 case 1: code = BFD_RELOC_8_PCREL; break;
7476 case 2: code = BFD_RELOC_16_PCREL; break;
7477 case 4: code = BFD_RELOC_32_PCREL; break;
7479 case 8: code = BFD_RELOC_64_PCREL; break;
7485 switch (fixp->fx_size)
7488 as_bad_where (fixp->fx_file, fixp->fx_line,
7489 _("can not do %d byte relocation"),
7491 code = BFD_RELOC_32;
7493 case 1: code = BFD_RELOC_8; break;
7494 case 2: code = BFD_RELOC_16; break;
7495 case 4: code = BFD_RELOC_32; break;
7497 case 8: code = BFD_RELOC_64; break;
7504 if ((code == BFD_RELOC_32
7505 || code == BFD_RELOC_32_PCREL
7506 || code == BFD_RELOC_X86_64_32S)
7508 && fixp->fx_addsy == GOT_symbol)
7511 code = BFD_RELOC_386_GOTPC;
7513 code = BFD_RELOC_X86_64_GOTPC32;
7515 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7517 && fixp->fx_addsy == GOT_symbol)
7519 code = BFD_RELOC_X86_64_GOTPC64;
7522 rel = (arelent *) xmalloc (sizeof (arelent));
7523 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7524 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7526 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7528 if (!use_rela_relocations)
7530 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7531 vtable entry to be used in the relocation's section offset. */
7532 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7533 rel->address = fixp->fx_offset;
7537 /* Use the rela in 64bit mode. */
7540 if (!fixp->fx_pcrel)
7541 rel->addend = fixp->fx_offset;
7545 case BFD_RELOC_X86_64_PLT32:
7546 case BFD_RELOC_X86_64_GOT32:
7547 case BFD_RELOC_X86_64_GOTPCREL:
7548 case BFD_RELOC_X86_64_TLSGD:
7549 case BFD_RELOC_X86_64_TLSLD:
7550 case BFD_RELOC_X86_64_GOTTPOFF:
7551 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7552 case BFD_RELOC_X86_64_TLSDESC_CALL:
7553 rel->addend = fixp->fx_offset - fixp->fx_size;
7556 rel->addend = (section->vma
7558 + fixp->fx_addnumber
7559 + md_pcrel_from (fixp));
7564 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7565 if (rel->howto == NULL)
7567 as_bad_where (fixp->fx_file, fixp->fx_line,
7568 _("cannot represent relocation type %s"),
7569 bfd_get_reloc_code_name (code));
7570 /* Set howto to a garbage value so that we can keep going. */
7571 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7572 assert (rel->howto != NULL);
7579 /* Parse operands using Intel syntax. This implements a recursive descent
7580 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7583 FIXME: We do not recognize the full operand grammar defined in the MASM
7584 documentation. In particular, all the structure/union and
7585 high-level macro operands are missing.
7587 Uppercase words are terminals, lower case words are non-terminals.
7588 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7589 bars '|' denote choices. Most grammar productions are implemented in
7590 functions called 'intel_<production>'.
7592 Initial production is 'expr'.
7598 binOp & | AND | \| | OR | ^ | XOR
7600 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7602 constant digits [[ radixOverride ]]
7604 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7642 => expr expr cmpOp e04
7645 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7646 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7648 hexdigit a | b | c | d | e | f
7649 | A | B | C | D | E | F
7655 mulOp * | / | % | MOD | << | SHL | >> | SHR
7659 register specialRegister
7663 segmentRegister CS | DS | ES | FS | GS | SS
7665 specialRegister CR0 | CR2 | CR3 | CR4
7666 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7667 | TR3 | TR4 | TR5 | TR6 | TR7
7669 We simplify the grammar in obvious places (e.g., register parsing is
7670 done by calling parse_register) and eliminate immediate left recursion
7671 to implement a recursive-descent parser.
7675 expr' cmpOp e04 expr'
7726 /* Parsing structure for the intel syntax parser. Used to implement the
7727 semantic actions for the operand grammar. */
7728 struct intel_parser_s
7730 char *op_string; /* The string being parsed. */
7731 int got_a_float; /* Whether the operand is a float. */
7732 int op_modifier; /* Operand modifier. */
7733 int is_mem; /* 1 if operand is memory reference. */
7734 int in_offset; /* >=1 if parsing operand of offset. */
7735 int in_bracket; /* >=1 if parsing operand in brackets. */
7736 const reg_entry *reg; /* Last register reference found. */
7737 char *disp; /* Displacement string being built. */
7738 char *next_operand; /* Resume point when splitting operands. */
7741 static struct intel_parser_s intel_parser;
7743 /* Token structure for parsing intel syntax. */
7746 int code; /* Token code. */
7747 const reg_entry *reg; /* Register entry for register tokens. */
7748 char *str; /* String representation. */
7751 static struct intel_token cur_token, prev_token;
7753 /* Token codes for the intel parser. Since T_SHORT is already used
7754 by COFF, undefine it first to prevent a warning. */
7773 /* Prototypes for intel parser functions. */
7774 static int intel_match_token (int);
7775 static void intel_putback_token (void);
7776 static void intel_get_token (void);
7777 static int intel_expr (void);
7778 static int intel_e04 (void);
7779 static int intel_e05 (void);
7780 static int intel_e06 (void);
7781 static int intel_e09 (void);
7782 static int intel_e10 (void);
7783 static int intel_e11 (void);
7786 i386_intel_operand (char *operand_string, int got_a_float)
7791 p = intel_parser.op_string = xstrdup (operand_string);
7792 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7796 /* Initialize token holders. */
7797 cur_token.code = prev_token.code = T_NIL;
7798 cur_token.reg = prev_token.reg = NULL;
7799 cur_token.str = prev_token.str = NULL;
7801 /* Initialize parser structure. */
7802 intel_parser.got_a_float = got_a_float;
7803 intel_parser.op_modifier = 0;
7804 intel_parser.is_mem = 0;
7805 intel_parser.in_offset = 0;
7806 intel_parser.in_bracket = 0;
7807 intel_parser.reg = NULL;
7808 intel_parser.disp[0] = '\0';
7809 intel_parser.next_operand = NULL;
7811 /* Read the first token and start the parser. */
7813 ret = intel_expr ();
7818 if (cur_token.code != T_NIL)
7820 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7821 current_templates->start->name, cur_token.str);
7824 /* If we found a memory reference, hand it over to i386_displacement
7825 to fill in the rest of the operand fields. */
7826 else if (intel_parser.is_mem)
7828 if ((i.mem_operands == 1
7829 && !current_templates->start->opcode_modifier.isstring)
7830 || i.mem_operands == 2)
7832 as_bad (_("too many memory references for '%s'"),
7833 current_templates->start->name);
7838 char *s = intel_parser.disp;
7841 if (!quiet_warnings && intel_parser.is_mem < 0)
7842 /* See the comments in intel_bracket_expr. */
7843 as_warn (_("Treating `%s' as memory reference"), operand_string);
7845 /* Add the displacement expression. */
7847 ret = i386_displacement (s, s + strlen (s));
7850 /* Swap base and index in 16-bit memory operands like
7851 [si+bx]. Since i386_index_check is also used in AT&T
7852 mode we have to do that here. */
7855 && i.base_reg->reg_type.bitfield.reg16
7856 && i.index_reg->reg_type.bitfield.reg16
7857 && i.base_reg->reg_num >= 6
7858 && i.index_reg->reg_num < 6)
7860 const reg_entry *base = i.index_reg;
7862 i.index_reg = i.base_reg;
7865 ret = i386_index_check (operand_string);
7870 /* Constant and OFFSET expressions are handled by i386_immediate. */
7871 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7872 || intel_parser.reg == NULL)
7873 ret = i386_immediate (intel_parser.disp);
7875 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7877 if (!ret || !intel_parser.next_operand)
7879 intel_parser.op_string = intel_parser.next_operand;
7880 this_operand = i.operands++;
7884 free (intel_parser.disp);
7889 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7893 expr' cmpOp e04 expr'
7898 /* XXX Implement the comparison operators. */
7899 return intel_e04 ();
7916 if (cur_token.code == T_NIL)
7919 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7920 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7922 if (cur_token.code == '+')
7924 else if (cur_token.code == '-')
7925 nregs = NUM_ADDRESS_REGS;
7929 strcat (intel_parser.disp, cur_token.str);
7930 intel_match_token (cur_token.code);
7941 int nregs = ~NUM_ADDRESS_REGS;
7948 if (cur_token.code == '&'
7949 || cur_token.code == '|'
7950 || cur_token.code == '^')
7954 str[0] = cur_token.code;
7956 strcat (intel_parser.disp, str);
7961 intel_match_token (cur_token.code);
7966 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7967 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7978 int nregs = ~NUM_ADDRESS_REGS;
7985 if (cur_token.code == '*'
7986 || cur_token.code == '/'
7987 || cur_token.code == '%')
7991 str[0] = cur_token.code;
7993 strcat (intel_parser.disp, str);
7995 else if (cur_token.code == T_SHL)
7996 strcat (intel_parser.disp, "<<");
7997 else if (cur_token.code == T_SHR)
7998 strcat (intel_parser.disp, ">>");
8002 intel_match_token (cur_token.code);
8007 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8008 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8026 int nregs = ~NUM_ADDRESS_REGS;
8031 /* Don't consume constants here. */
8032 if (cur_token.code == '+' || cur_token.code == '-')
8034 /* Need to look one token ahead - if the next token
8035 is a constant, the current token is its sign. */
8038 intel_match_token (cur_token.code);
8039 next_code = cur_token.code;
8040 intel_putback_token ();
8041 if (next_code == T_CONST)
8045 /* e09 OFFSET e09 */
8046 if (cur_token.code == T_OFFSET)
8049 ++intel_parser.in_offset;
8053 else if (cur_token.code == T_SHORT)
8054 intel_parser.op_modifier |= 1 << T_SHORT;
8057 else if (cur_token.code == '+')
8058 strcat (intel_parser.disp, "+");
8063 else if (cur_token.code == '-' || cur_token.code == '~')
8069 str[0] = cur_token.code;
8071 strcat (intel_parser.disp, str);
8078 intel_match_token (cur_token.code);
8086 /* e09' PTR e10 e09' */
8087 if (cur_token.code == T_PTR)
8091 if (prev_token.code == T_BYTE)
8092 suffix = BYTE_MNEM_SUFFIX;
8094 else if (prev_token.code == T_WORD)
8096 if (current_templates->start->name[0] == 'l'
8097 && current_templates->start->name[2] == 's'
8098 && current_templates->start->name[3] == 0)
8099 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8100 else if (intel_parser.got_a_float == 2) /* "fi..." */
8101 suffix = SHORT_MNEM_SUFFIX;
8103 suffix = WORD_MNEM_SUFFIX;
8106 else if (prev_token.code == T_DWORD)
8108 if (current_templates->start->name[0] == 'l'
8109 && current_templates->start->name[2] == 's'
8110 && current_templates->start->name[3] == 0)
8111 suffix = WORD_MNEM_SUFFIX;
8112 else if (flag_code == CODE_16BIT
8113 && (current_templates->start->opcode_modifier.jump
8114 || current_templates->start->opcode_modifier.jumpdword))
8115 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8116 else if (intel_parser.got_a_float == 1) /* "f..." */
8117 suffix = SHORT_MNEM_SUFFIX;
8119 suffix = LONG_MNEM_SUFFIX;
8122 else if (prev_token.code == T_FWORD)
8124 if (current_templates->start->name[0] == 'l'
8125 && current_templates->start->name[2] == 's'
8126 && current_templates->start->name[3] == 0)
8127 suffix = LONG_MNEM_SUFFIX;
8128 else if (!intel_parser.got_a_float)
8130 if (flag_code == CODE_16BIT)
8131 add_prefix (DATA_PREFIX_OPCODE);
8132 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8135 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8138 else if (prev_token.code == T_QWORD)
8140 if (intel_parser.got_a_float == 1) /* "f..." */
8141 suffix = LONG_MNEM_SUFFIX;
8143 suffix = QWORD_MNEM_SUFFIX;
8146 else if (prev_token.code == T_TBYTE)
8148 if (intel_parser.got_a_float == 1)
8149 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8151 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8154 else if (prev_token.code == T_XMMWORD)
8156 /* XXX ignored for now, but accepted since gcc uses it */
8162 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8166 /* Operands for jump/call using 'ptr' notation denote absolute
8168 if (current_templates->start->opcode_modifier.jump
8169 || current_templates->start->opcode_modifier.jumpdword)
8170 i.types[this_operand].bitfield.jumpabsolute = 1;
8172 if (current_templates->start->base_opcode == 0x8d /* lea */)
8176 else if (i.suffix != suffix)
8178 as_bad (_("Conflicting operand modifiers"));
8184 /* e09' : e10 e09' */
8185 else if (cur_token.code == ':')
8187 if (prev_token.code != T_REG)
8189 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8190 segment/group identifier (which we don't have), using comma
8191 as the operand separator there is even less consistent, since
8192 there all branches only have a single operand. */
8193 if (this_operand != 0
8194 || intel_parser.in_offset
8195 || intel_parser.in_bracket
8196 || (!current_templates->start->opcode_modifier.jump
8197 && !current_templates->start->opcode_modifier.jumpdword
8198 && !current_templates->start->opcode_modifier.jumpintersegment
8199 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8200 return intel_match_token (T_NIL);
8201 /* Remember the start of the 2nd operand and terminate 1st
8203 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8204 another expression), but it gets at least the simplest case
8205 (a plain number or symbol on the left side) right. */
8206 intel_parser.next_operand = intel_parser.op_string;
8207 *--intel_parser.op_string = '\0';
8208 return intel_match_token (':');
8216 intel_match_token (cur_token.code);
8222 --intel_parser.in_offset;
8225 if (NUM_ADDRESS_REGS > nregs)
8227 as_bad (_("Invalid operand to `OFFSET'"));
8230 intel_parser.op_modifier |= 1 << T_OFFSET;
8233 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8234 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8239 intel_bracket_expr (void)
8241 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8242 const char *start = intel_parser.op_string;
8245 if (i.op[this_operand].regs)
8246 return intel_match_token (T_NIL);
8248 intel_match_token ('[');
8250 /* Mark as a memory operand only if it's not already known to be an
8251 offset expression. If it's an offset expression, we need to keep
8253 if (!intel_parser.in_offset)
8255 ++intel_parser.in_bracket;
8257 /* Operands for jump/call inside brackets denote absolute addresses. */
8258 if (current_templates->start->opcode_modifier.jump
8259 || current_templates->start->opcode_modifier.jumpdword)
8260 i.types[this_operand].bitfield.jumpabsolute = 1;
8262 /* Unfortunately gas always diverged from MASM in a respect that can't
8263 be easily fixed without risking to break code sequences likely to be
8264 encountered (the testsuite even check for this): MASM doesn't consider
8265 an expression inside brackets unconditionally as a memory reference.
8266 When that is e.g. a constant, an offset expression, or the sum of the
8267 two, this is still taken as a constant load. gas, however, always
8268 treated these as memory references. As a compromise, we'll try to make
8269 offset expressions inside brackets work the MASM way (since that's
8270 less likely to be found in real world code), but make constants alone
8271 continue to work the traditional gas way. In either case, issue a
8273 intel_parser.op_modifier &= ~was_offset;
8276 strcat (intel_parser.disp, "[");
8278 /* Add a '+' to the displacement string if necessary. */
8279 if (*intel_parser.disp != '\0'
8280 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8281 strcat (intel_parser.disp, "+");
8284 && (len = intel_parser.op_string - start - 1,
8285 intel_match_token (']')))
8287 /* Preserve brackets when the operand is an offset expression. */
8288 if (intel_parser.in_offset)
8289 strcat (intel_parser.disp, "]");
8292 --intel_parser.in_bracket;
8293 if (i.base_reg || i.index_reg)
8294 intel_parser.is_mem = 1;
8295 if (!intel_parser.is_mem)
8297 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8298 /* Defer the warning until all of the operand was parsed. */
8299 intel_parser.is_mem = -1;
8300 else if (!quiet_warnings)
8301 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8302 len, start, len, start);
8305 intel_parser.op_modifier |= was_offset;
8322 while (cur_token.code == '[')
8324 if (!intel_bracket_expr ())
8349 switch (cur_token.code)
8353 intel_match_token ('(');
8354 strcat (intel_parser.disp, "(");
8356 if (intel_expr () && intel_match_token (')'))
8358 strcat (intel_parser.disp, ")");
8365 return intel_bracket_expr ();
8370 strcat (intel_parser.disp, cur_token.str);
8371 intel_match_token (cur_token.code);
8373 /* Mark as a memory operand only if it's not already known to be an
8374 offset expression. */
8375 if (!intel_parser.in_offset)
8376 intel_parser.is_mem = 1;
8383 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8385 intel_match_token (T_REG);
8387 /* Check for segment change. */
8388 if (cur_token.code == ':')
8390 if (!reg->reg_type.bitfield.sreg2
8391 && !reg->reg_type.bitfield.sreg3)
8393 as_bad (_("`%s' is not a valid segment register"),
8397 else if (i.seg[i.mem_operands])
8398 as_warn (_("Extra segment override ignored"));
8401 if (!intel_parser.in_offset)
8402 intel_parser.is_mem = 1;
8403 switch (reg->reg_num)
8406 i.seg[i.mem_operands] = &es;
8409 i.seg[i.mem_operands] = &cs;
8412 i.seg[i.mem_operands] = &ss;
8415 i.seg[i.mem_operands] = &ds;
8418 i.seg[i.mem_operands] = &fs;
8421 i.seg[i.mem_operands] = &gs;
8427 /* Not a segment register. Check for register scaling. */
8428 else if (cur_token.code == '*')
8430 if (!intel_parser.in_bracket)
8432 as_bad (_("Register scaling only allowed in memory operands"));
8436 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8437 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8438 else if (i.index_reg)
8439 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8441 /* What follows must be a valid scale. */
8442 intel_match_token ('*');
8444 i.types[this_operand].bitfield.baseindex = 1;
8446 /* Set the scale after setting the register (otherwise,
8447 i386_scale will complain) */
8448 if (cur_token.code == '+' || cur_token.code == '-')
8450 char *str, sign = cur_token.code;
8451 intel_match_token (cur_token.code);
8452 if (cur_token.code != T_CONST)
8454 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8458 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8459 strcpy (str + 1, cur_token.str);
8461 if (!i386_scale (str))
8465 else if (!i386_scale (cur_token.str))
8467 intel_match_token (cur_token.code);
8470 /* No scaling. If this is a memory operand, the register is either a
8471 base register (first occurrence) or an index register (second
8473 else if (intel_parser.in_bracket)
8478 else if (!i.index_reg)
8482 as_bad (_("Too many register references in memory operand"));
8486 i.types[this_operand].bitfield.baseindex = 1;
8489 /* It's neither base nor index. */
8490 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8492 i386_operand_type temp = reg->reg_type;
8493 temp.bitfield.baseindex = 0;
8494 i.types[this_operand] = operand_type_or (i.types[this_operand],
8496 i.op[this_operand].regs = reg;
8501 as_bad (_("Invalid use of register"));
8505 /* Since registers are not part of the displacement string (except
8506 when we're parsing offset operands), we may need to remove any
8507 preceding '+' from the displacement string. */
8508 if (*intel_parser.disp != '\0'
8509 && !intel_parser.in_offset)
8511 char *s = intel_parser.disp;
8512 s += strlen (s) - 1;
8535 intel_match_token (cur_token.code);
8537 if (cur_token.code == T_PTR)
8540 /* It must have been an identifier. */
8541 intel_putback_token ();
8542 cur_token.code = T_ID;
8548 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8552 /* The identifier represents a memory reference only if it's not
8553 preceded by an offset modifier and if it's not an equate. */
8554 symbolP = symbol_find(cur_token.str);
8555 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8556 intel_parser.is_mem = 1;
8564 char *save_str, sign = 0;
8566 /* Allow constants that start with `+' or `-'. */
8567 if (cur_token.code == '-' || cur_token.code == '+')
8569 sign = cur_token.code;
8570 intel_match_token (cur_token.code);
8571 if (cur_token.code != T_CONST)
8573 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8579 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8580 strcpy (save_str + !!sign, cur_token.str);
8584 /* Get the next token to check for register scaling. */
8585 intel_match_token (cur_token.code);
8587 /* Check if this constant is a scaling factor for an
8589 if (cur_token.code == '*')
8591 if (intel_match_token ('*') && cur_token.code == T_REG)
8593 const reg_entry *reg = cur_token.reg;
8595 if (!intel_parser.in_bracket)
8597 as_bad (_("Register scaling only allowed "
8598 "in memory operands"));
8602 /* Disallow things like [1*si].
8603 sp and esp are invalid as index. */
8604 if (reg->reg_type.bitfield.reg16)
8605 reg = i386_regtab + REGNAM_AX + 4;
8606 else if (i.index_reg)
8607 reg = i386_regtab + REGNAM_EAX + 4;
8609 /* The constant is followed by `* reg', so it must be
8612 i.types[this_operand].bitfield.baseindex = 1;
8614 /* Set the scale after setting the register (otherwise,
8615 i386_scale will complain) */
8616 if (!i386_scale (save_str))
8618 intel_match_token (T_REG);
8620 /* Since registers are not part of the displacement
8621 string, we may need to remove any preceding '+' from
8622 the displacement string. */
8623 if (*intel_parser.disp != '\0')
8625 char *s = intel_parser.disp;
8626 s += strlen (s) - 1;
8636 /* The constant was not used for register scaling. Since we have
8637 already consumed the token following `*' we now need to put it
8638 back in the stream. */
8639 intel_putback_token ();
8642 /* Add the constant to the displacement string. */
8643 strcat (intel_parser.disp, save_str);
8650 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8654 /* Match the given token against cur_token. If they match, read the next
8655 token from the operand string. */
8657 intel_match_token (int code)
8659 if (cur_token.code == code)
8666 as_bad (_("Unexpected token `%s'"), cur_token.str);
8671 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8673 intel_get_token (void)
8676 const reg_entry *reg;
8677 struct intel_token new_token;
8679 new_token.code = T_NIL;
8680 new_token.reg = NULL;
8681 new_token.str = NULL;
8683 /* Free the memory allocated to the previous token and move
8684 cur_token to prev_token. */
8686 free (prev_token.str);
8688 prev_token = cur_token;
8690 /* Skip whitespace. */
8691 while (is_space_char (*intel_parser.op_string))
8692 intel_parser.op_string++;
8694 /* Return an empty token if we find nothing else on the line. */
8695 if (*intel_parser.op_string == '\0')
8697 cur_token = new_token;
8701 /* The new token cannot be larger than the remainder of the operand
8703 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8704 new_token.str[0] = '\0';
8706 if (strchr ("0123456789", *intel_parser.op_string))
8708 char *p = new_token.str;
8709 char *q = intel_parser.op_string;
8710 new_token.code = T_CONST;
8712 /* Allow any kind of identifier char to encompass floating point and
8713 hexadecimal numbers. */
8714 while (is_identifier_char (*q))
8718 /* Recognize special symbol names [0-9][bf]. */
8719 if (strlen (intel_parser.op_string) == 2
8720 && (intel_parser.op_string[1] == 'b'
8721 || intel_parser.op_string[1] == 'f'))
8722 new_token.code = T_ID;
8725 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8727 size_t len = end_op - intel_parser.op_string;
8729 new_token.code = T_REG;
8730 new_token.reg = reg;
8732 memcpy (new_token.str, intel_parser.op_string, len);
8733 new_token.str[len] = '\0';
8736 else if (is_identifier_char (*intel_parser.op_string))
8738 char *p = new_token.str;
8739 char *q = intel_parser.op_string;
8741 /* A '.' or '$' followed by an identifier char is an identifier.
8742 Otherwise, it's operator '.' followed by an expression. */
8743 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8745 new_token.code = '.';
8746 new_token.str[0] = '.';
8747 new_token.str[1] = '\0';
8751 while (is_identifier_char (*q) || *q == '@')
8755 if (strcasecmp (new_token.str, "NOT") == 0)
8756 new_token.code = '~';
8758 else if (strcasecmp (new_token.str, "MOD") == 0)
8759 new_token.code = '%';
8761 else if (strcasecmp (new_token.str, "AND") == 0)
8762 new_token.code = '&';
8764 else if (strcasecmp (new_token.str, "OR") == 0)
8765 new_token.code = '|';
8767 else if (strcasecmp (new_token.str, "XOR") == 0)
8768 new_token.code = '^';
8770 else if (strcasecmp (new_token.str, "SHL") == 0)
8771 new_token.code = T_SHL;
8773 else if (strcasecmp (new_token.str, "SHR") == 0)
8774 new_token.code = T_SHR;
8776 else if (strcasecmp (new_token.str, "BYTE") == 0)
8777 new_token.code = T_BYTE;
8779 else if (strcasecmp (new_token.str, "WORD") == 0)
8780 new_token.code = T_WORD;
8782 else if (strcasecmp (new_token.str, "DWORD") == 0)
8783 new_token.code = T_DWORD;
8785 else if (strcasecmp (new_token.str, "FWORD") == 0)
8786 new_token.code = T_FWORD;
8788 else if (strcasecmp (new_token.str, "QWORD") == 0)
8789 new_token.code = T_QWORD;
8791 else if (strcasecmp (new_token.str, "TBYTE") == 0
8792 /* XXX remove (gcc still uses it) */
8793 || strcasecmp (new_token.str, "XWORD") == 0)
8794 new_token.code = T_TBYTE;
8796 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8797 || strcasecmp (new_token.str, "OWORD") == 0)
8798 new_token.code = T_XMMWORD;
8800 else if (strcasecmp (new_token.str, "PTR") == 0)
8801 new_token.code = T_PTR;
8803 else if (strcasecmp (new_token.str, "SHORT") == 0)
8804 new_token.code = T_SHORT;
8806 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8808 new_token.code = T_OFFSET;
8810 /* ??? This is not mentioned in the MASM grammar but gcc
8811 makes use of it with -mintel-syntax. OFFSET may be
8812 followed by FLAT: */
8813 if (strncasecmp (q, " FLAT:", 6) == 0)
8814 strcat (new_token.str, " FLAT:");
8817 /* ??? This is not mentioned in the MASM grammar. */
8818 else if (strcasecmp (new_token.str, "FLAT") == 0)
8820 new_token.code = T_OFFSET;
8822 strcat (new_token.str, ":");
8824 as_bad (_("`:' expected"));
8828 new_token.code = T_ID;
8832 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8834 new_token.code = *intel_parser.op_string;
8835 new_token.str[0] = *intel_parser.op_string;
8836 new_token.str[1] = '\0';
8839 else if (strchr ("<>", *intel_parser.op_string)
8840 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8842 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8843 new_token.str[0] = *intel_parser.op_string;
8844 new_token.str[1] = *intel_parser.op_string;
8845 new_token.str[2] = '\0';
8849 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8851 intel_parser.op_string += strlen (new_token.str);
8852 cur_token = new_token;
8855 /* Put cur_token back into the token stream and make cur_token point to
8858 intel_putback_token (void)
8860 if (cur_token.code != T_NIL)
8862 intel_parser.op_string -= strlen (cur_token.str);
8863 free (cur_token.str);
8865 cur_token = prev_token;
8867 /* Forget prev_token. */
8868 prev_token.code = T_NIL;
8869 prev_token.reg = NULL;
8870 prev_token.str = NULL;
8874 tc_x86_regname_to_dw2regnum (char *regname)
8876 unsigned int regnum;
8877 unsigned int regnames_count;
8878 static const char *const regnames_32[] =
8880 "eax", "ecx", "edx", "ebx",
8881 "esp", "ebp", "esi", "edi",
8882 "eip", "eflags", NULL,
8883 "st0", "st1", "st2", "st3",
8884 "st4", "st5", "st6", "st7",
8886 "xmm0", "xmm1", "xmm2", "xmm3",
8887 "xmm4", "xmm5", "xmm6", "xmm7",
8888 "mm0", "mm1", "mm2", "mm3",
8889 "mm4", "mm5", "mm6", "mm7",
8890 "fcw", "fsw", "mxcsr",
8891 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8894 static const char *const regnames_64[] =
8896 "rax", "rdx", "rcx", "rbx",
8897 "rsi", "rdi", "rbp", "rsp",
8898 "r8", "r9", "r10", "r11",
8899 "r12", "r13", "r14", "r15",
8901 "xmm0", "xmm1", "xmm2", "xmm3",
8902 "xmm4", "xmm5", "xmm6", "xmm7",
8903 "xmm8", "xmm9", "xmm10", "xmm11",
8904 "xmm12", "xmm13", "xmm14", "xmm15",
8905 "st0", "st1", "st2", "st3",
8906 "st4", "st5", "st6", "st7",
8907 "mm0", "mm1", "mm2", "mm3",
8908 "mm4", "mm5", "mm6", "mm7",
8910 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8911 "fs.base", "gs.base", NULL, NULL,
8913 "mxcsr", "fcw", "fsw"
8915 const char *const *regnames;
8917 if (flag_code == CODE_64BIT)
8919 regnames = regnames_64;
8920 regnames_count = ARRAY_SIZE (regnames_64);
8924 regnames = regnames_32;
8925 regnames_count = ARRAY_SIZE (regnames_32);
8928 for (regnum = 0; regnum < regnames_count; regnum++)
8929 if (regnames[regnum] != NULL
8930 && strcmp (regname, regnames[regnum]) == 0)
8937 tc_x86_frame_initial_instructions (void)
8939 static unsigned int sp_regno;
8942 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8945 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8946 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8950 i386_elf_section_type (const char *str, size_t len)
8952 if (flag_code == CODE_64BIT
8953 && len == sizeof ("unwind") - 1
8954 && strncmp (str, "unwind", 6) == 0)
8955 return SHT_X86_64_UNWIND;
8962 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8966 expr.X_op = O_secrel;
8967 expr.X_add_symbol = symbol;
8968 expr.X_add_number = 0;
8969 emit_expr (&expr, size);
8973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8974 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8977 x86_64_section_letter (int letter, char **ptr_msg)
8979 if (flag_code == CODE_64BIT)
8982 return SHF_X86_64_LARGE;
8984 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8987 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8992 x86_64_section_word (char *str, size_t len)
8994 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8995 return SHF_X86_64_LARGE;
9001 handle_large_common (int small ATTRIBUTE_UNUSED)
9003 if (flag_code != CODE_64BIT)
9005 s_comm_internal (0, elf_common_parse);
9006 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9010 static segT lbss_section;
9011 asection *saved_com_section_ptr = elf_com_section_ptr;
9012 asection *saved_bss_section = bss_section;
9014 if (lbss_section == NULL)
9016 flagword applicable;
9018 subsegT subseg = now_subseg;
9020 /* The .lbss section is for local .largecomm symbols. */
9021 lbss_section = subseg_new (".lbss", 0);
9022 applicable = bfd_applicable_section_flags (stdoutput);
9023 bfd_set_section_flags (stdoutput, lbss_section,
9024 applicable & SEC_ALLOC);
9025 seg_info (lbss_section)->bss = 1;
9027 subseg_set (seg, subseg);
9030 elf_com_section_ptr = &_bfd_elf_large_com_section;
9031 bss_section = lbss_section;
9033 s_comm_internal (0, elf_common_parse);
9035 elf_com_section_ptr = saved_com_section_ptr;
9036 bss_section = saved_bss_section;
9039 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */