1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
196 static const char *default_arch = DEFAULT_ARCH;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
269 unsupported_with_intel_mnemonic,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
279 mask_not_on_destination,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op[MAX_OPERANDS];
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default = 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default = 0,
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
378 /* How to encode vector instructions. */
381 vex_encoding_default = 0,
388 const char *rep_prefix;
391 const char *hle_prefix;
393 /* Have BND prefix. */
394 const char *bnd_prefix;
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
400 enum i386_error error;
403 typedef struct _i386_insn i386_insn;
405 /* Link RC type with corresponding string, that'll be looked for in
414 static const struct RC_name RC_NamesTable[] =
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
465 const char line_separator_chars[] = ";";
467 /* Chars that can be used to separate mant from exp in floating point
469 const char EXP_CHARS[] = "eE";
471 /* Chars that mean this number is a floating point constant
474 const char FLT_CHARS[] = "fFdDxX";
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
505 /* The instruction we're assembling. */
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
515 /* Current operand we are working on. */
516 static int this_operand = -1;
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
535 /* The ELF ABI to use. */
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
556 /* 1 for intel syntax,
558 static int intel_syntax = 0;
560 /* 1 for Intel64 ISA,
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
580 static int add_bnd_prefix = 0;
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
593 /* 1 if the assembler should generate relax relocations. */
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
598 static enum check_kind
604 sse_check, operand_check = check_warning;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
611 static int optimize = 0;
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
620 static int optimize_for_space = 0;
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
665 /* Encode scalar AVX instructions with specific vector length. */
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
680 /* Encode EVEX WIG instructions with specific evex.w. */
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
705 #define UNCOND_JUMP 0
707 #define COND_JUMP86 2
712 #define SMALL16 (SMALL | CODE16)
714 #define BIG16 (BIG | CODE16)
718 #define INLINE __inline__
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
739 const relax_typeS md_relax_table[] =
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
778 static const arch_entry cpu_arch[] =
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1038 static const noarch_entry cpu_noarch[] =
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1085 && *input_line_pointer == ',')
1087 align = parse_align (needs_align - 1);
1089 if (align == (addressT) -1)
1104 bss_alloc (symbolP, size, align);
1109 pe_lcomm (int needs_align)
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1115 const pseudo_typeS md_pseudo_table[] =
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1120 {"align", s_align_ptwo, 0},
1122 {"arch", set_cpu_arch, 0},
1126 {"lcomm", pe_lcomm, 1},
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1139 {"code64", set_code_flag, CODE_64BIT},
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1157 {"secrel32", pe_directive_secrel, 0},
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1234 alt_9, alt_10, alt_11
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1241 i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1245 /* Place the longer NOP first. */
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1250 /* Use the smaller one if the requsted one isn't available. */
1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
1257 last = count % max_single_nop_size;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1265 nops = patt[last - 1];
1268 /* Use the smaller one plus one-byte NOP if the needed one
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1276 memcpy (where + offset, nops, last);
1281 fits_in_imm7 (offsetT num)
1283 return (num & 0x7f) == num;
1287 fits_in_imm31 (offsetT num)
1289 return (num & 0x7fffffff) == num;
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1296 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1298 const unsigned char *const *patt = NULL;
1299 int max_single_nop_size;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
1303 switch (fragP->fr_type)
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1326 if (flag_code == CODE_16BIT)
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
1350 case PROCESSOR_CORE:
1351 case PROCESSOR_CORE2:
1352 case PROCESSOR_COREI7:
1353 case PROCESSOR_L1OM:
1354 case PROCESSOR_K1OM:
1355 case PROCESSOR_GENERIC64:
1357 case PROCESSOR_ATHLON:
1359 case PROCESSOR_AMDFAM10:
1361 case PROCESSOR_ZNVER:
1365 case PROCESSOR_I386:
1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
1368 case PROCESSOR_PENTIUMPRO:
1369 case PROCESSOR_IAMCU:
1370 case PROCESSOR_GENERIC32:
1377 switch (fragP->tc_frag_data.tune)
1379 case PROCESSOR_UNKNOWN:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1385 case PROCESSOR_I386:
1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
1388 case PROCESSOR_IAMCU:
1390 case PROCESSOR_ATHLON:
1392 case PROCESSOR_AMDFAM10:
1394 case PROCESSOR_ZNVER:
1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
1408 case PROCESSOR_CORE2:
1409 case PROCESSOR_COREI7:
1410 case PROCESSOR_L1OM:
1411 case PROCESSOR_K1OM:
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1417 case PROCESSOR_GENERIC64:
1423 if (patt == f32_patt)
1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1438 limit = max_single_nop_size;
1440 if (fragP->fr_type == rs_fill_nop)
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1453 fragP->fr_var = count;
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1461 /* Use "jmp disp8" if possible. */
1463 where[0] = jump_disp8[0];
1469 unsigned int size_of_jump;
1471 if (flag_code == CODE_16BIT)
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1479 where[0] = jump32_disp32[0];
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
1501 operand_type_all_zero (const union i386_operand_type *x)
1503 switch (ARRAY_SIZE(x->array))
1514 return !x->array[0];
1521 operand_type_set (union i386_operand_type *x, unsigned int v)
1523 switch (ARRAY_SIZE(x->array))
1541 operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
1544 switch (ARRAY_SIZE(x->array))
1547 if (x->array[2] != y->array[2])
1551 if (x->array[1] != y->array[1])
1555 return x->array[0] == y->array[0];
1563 cpu_flags_all_zero (const union i386_cpu_flags *x)
1565 switch (ARRAY_SIZE(x->array))
1580 return !x->array[0];
1587 cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1590 switch (ARRAY_SIZE(x->array))
1593 if (x->array[3] != y->array[3])
1597 if (x->array[2] != y->array[2])
1601 if (x->array[1] != y->array[1])
1605 return x->array[0] == y->array[0];
1613 cpu_flags_check_cpu64 (i386_cpu_flags f)
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1622 switch (ARRAY_SIZE (x.array))
1625 x.array [3] &= y.array [3];
1628 x.array [2] &= y.array [2];
1631 x.array [1] &= y.array [1];
1634 x.array [0] &= y.array [0];
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1645 switch (ARRAY_SIZE (x.array))
1648 x.array [3] |= y.array [3];
1651 x.array [2] |= y.array [2];
1654 x.array [1] |= y.array [1];
1657 x.array [0] |= y.array [0];
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1668 switch (ARRAY_SIZE (x.array))
1671 x.array [3] &= ~y.array [3];
1674 x.array [2] &= ~y.array [2];
1677 x.array [1] &= ~y.array [1];
1680 x.array [0] &= ~y.array [0];
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1691 #define CPU_FLAGS_PERFECT_MATCH \
1692 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1694 /* Return CPU flags match bits. */
1697 cpu_flags_match (const insn_template *t)
1699 i386_cpu_flags x = t->cpu_flags;
1700 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1702 x.bitfield.cpu64 = 0;
1703 x.bitfield.cpuno64 = 0;
1705 if (cpu_flags_all_zero (&x))
1707 /* This instruction is available on all archs. */
1708 match |= CPU_FLAGS_ARCH_MATCH;
1712 /* This instruction is available only on some archs. */
1713 i386_cpu_flags cpu = cpu_arch_flags;
1715 /* AVX512VL is no standalone feature - match it and then strip it. */
1716 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1718 x.bitfield.cpuavx512vl = 0;
1720 cpu = cpu_flags_and (x, cpu);
1721 if (!cpu_flags_all_zero (&cpu))
1723 if (x.bitfield.cpuavx)
1725 /* We need to check a few extra flags with AVX. */
1726 if (cpu.bitfield.cpuavx
1727 && (!t->opcode_modifier.sse2avx || sse2avx)
1728 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1729 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1730 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1731 match |= CPU_FLAGS_ARCH_MATCH;
1733 else if (x.bitfield.cpuavx512f)
1735 /* We need to check a few extra flags with AVX512F. */
1736 if (cpu.bitfield.cpuavx512f
1737 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1738 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1739 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1740 match |= CPU_FLAGS_ARCH_MATCH;
1743 match |= CPU_FLAGS_ARCH_MATCH;
1749 static INLINE i386_operand_type
1750 operand_type_and (i386_operand_type x, i386_operand_type y)
1752 switch (ARRAY_SIZE (x.array))
1755 x.array [2] &= y.array [2];
1758 x.array [1] &= y.array [1];
1761 x.array [0] &= y.array [0];
1769 static INLINE i386_operand_type
1770 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1772 switch (ARRAY_SIZE (x.array))
1775 x.array [2] &= ~y.array [2];
1778 x.array [1] &= ~y.array [1];
1781 x.array [0] &= ~y.array [0];
1789 static INLINE i386_operand_type
1790 operand_type_or (i386_operand_type x, i386_operand_type y)
1792 switch (ARRAY_SIZE (x.array))
1795 x.array [2] |= y.array [2];
1798 x.array [1] |= y.array [1];
1801 x.array [0] |= y.array [0];
1809 static INLINE i386_operand_type
1810 operand_type_xor (i386_operand_type x, i386_operand_type y)
1812 switch (ARRAY_SIZE (x.array))
1815 x.array [2] ^= y.array [2];
1818 x.array [1] ^= y.array [1];
1821 x.array [0] ^= y.array [0];
1829 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1830 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1831 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1832 static const i386_operand_type inoutportreg
1833 = OPERAND_TYPE_INOUTPORTREG;
1834 static const i386_operand_type reg16_inoutportreg
1835 = OPERAND_TYPE_REG16_INOUTPORTREG;
1836 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1837 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1838 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1839 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1840 static const i386_operand_type anydisp
1841 = OPERAND_TYPE_ANYDISP;
1842 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1843 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1844 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1845 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1846 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1847 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1848 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1849 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1850 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1851 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1852 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1853 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1864 operand_type_check (i386_operand_type t, enum operand_type c)
1869 return t.bitfield.reg;
1872 return (t.bitfield.imm8
1876 || t.bitfield.imm32s
1877 || t.bitfield.imm64);
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64);
1887 return (t.bitfield.disp8
1888 || t.bitfield.disp16
1889 || t.bitfield.disp32
1890 || t.bitfield.disp32s
1891 || t.bitfield.disp64
1892 || t.bitfield.baseindex);
1901 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1902 operand J for instruction template T. */
1905 match_reg_size (const insn_template *t, unsigned int j)
1907 return !((i.types[j].bitfield.byte
1908 && !t->operand_types[j].bitfield.byte)
1909 || (i.types[j].bitfield.word
1910 && !t->operand_types[j].bitfield.word)
1911 || (i.types[j].bitfield.dword
1912 && !t->operand_types[j].bitfield.dword)
1913 || (i.types[j].bitfield.qword
1914 && !t->operand_types[j].bitfield.qword)
1915 || (i.types[j].bitfield.tbyte
1916 && !t->operand_types[j].bitfield.tbyte));
1919 /* Return 1 if there is no conflict in SIMD register on
1920 operand J for instruction template T. */
1923 match_simd_size (const insn_template *t, unsigned int j)
1925 return !((i.types[j].bitfield.xmmword
1926 && !t->operand_types[j].bitfield.xmmword)
1927 || (i.types[j].bitfield.ymmword
1928 && !t->operand_types[j].bitfield.ymmword)
1929 || (i.types[j].bitfield.zmmword
1930 && !t->operand_types[j].bitfield.zmmword));
1933 /* Return 1 if there is no conflict in any size on operand J for
1934 instruction template T. */
1937 match_mem_size (const insn_template *t, unsigned int j)
1939 return (match_reg_size (t, j)
1940 && !((i.types[j].bitfield.unspecified
1942 && !t->operand_types[j].bitfield.unspecified)
1943 || (i.types[j].bitfield.fword
1944 && !t->operand_types[j].bitfield.fword)
1945 /* For scalar opcode templates to allow register and memory
1946 operands at the same time, some special casing is needed
1948 || ((t->operand_types[j].bitfield.regsimd
1949 && !t->opcode_modifier.broadcast
1950 && (t->operand_types[j].bitfield.dword
1951 || t->operand_types[j].bitfield.qword))
1952 ? (i.types[j].bitfield.xmmword
1953 || i.types[j].bitfield.ymmword
1954 || i.types[j].bitfield.zmmword)
1955 : !match_simd_size(t, j))));
1958 /* Return 1 if there is no size conflict on any operands for
1959 instruction template T. */
1962 operand_size_match (const insn_template *t)
1967 /* Don't check jump instructions. */
1968 if (t->opcode_modifier.jump
1969 || t->opcode_modifier.jumpbyte
1970 || t->opcode_modifier.jumpdword
1971 || t->opcode_modifier.jumpintersegment)
1974 /* Check memory and accumulator operand size. */
1975 for (j = 0; j < i.operands; j++)
1977 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1978 && t->operand_types[j].bitfield.anysize)
1981 if (t->operand_types[j].bitfield.reg
1982 && !match_reg_size (t, j))
1988 if (t->operand_types[j].bitfield.regsimd
1989 && !match_simd_size (t, j))
1995 if (t->operand_types[j].bitfield.acc
1996 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2002 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2011 else if (!t->opcode_modifier.d)
2014 i.error = operand_size_mismatch;
2018 /* Check reverse. */
2019 gas_assert (i.operands == 2);
2022 for (j = 0; j < 2; j++)
2024 if ((t->operand_types[j].bitfield.reg
2025 || t->operand_types[j].bitfield.acc)
2026 && !match_reg_size (t, j ? 0 : 1))
2029 if (i.types[j].bitfield.mem
2030 && !match_mem_size (t, j ? 0 : 1))
2038 operand_type_match (i386_operand_type overlap,
2039 i386_operand_type given)
2041 i386_operand_type temp = overlap;
2043 temp.bitfield.jumpabsolute = 0;
2044 temp.bitfield.unspecified = 0;
2045 temp.bitfield.byte = 0;
2046 temp.bitfield.word = 0;
2047 temp.bitfield.dword = 0;
2048 temp.bitfield.fword = 0;
2049 temp.bitfield.qword = 0;
2050 temp.bitfield.tbyte = 0;
2051 temp.bitfield.xmmword = 0;
2052 temp.bitfield.ymmword = 0;
2053 temp.bitfield.zmmword = 0;
2054 if (operand_type_all_zero (&temp))
2057 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2058 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2062 i.error = operand_type_mismatch;
2066 /* If given types g0 and g1 are registers they must be of the same type
2067 unless the expected operand type register overlap is null.
2068 Memory operand size of certain SIMD instructions is also being checked
2072 operand_type_register_match (i386_operand_type g0,
2073 i386_operand_type t0,
2074 i386_operand_type g1,
2075 i386_operand_type t1)
2077 if (!g0.bitfield.reg
2078 && !g0.bitfield.regsimd
2079 && (!operand_type_check (g0, anymem)
2080 || g0.bitfield.unspecified
2081 || !t0.bitfield.regsimd))
2084 if (!g1.bitfield.reg
2085 && !g1.bitfield.regsimd
2086 && (!operand_type_check (g1, anymem)
2087 || g1.bitfield.unspecified
2088 || !t1.bitfield.regsimd))
2091 if (g0.bitfield.byte == g1.bitfield.byte
2092 && g0.bitfield.word == g1.bitfield.word
2093 && g0.bitfield.dword == g1.bitfield.dword
2094 && g0.bitfield.qword == g1.bitfield.qword
2095 && g0.bitfield.xmmword == g1.bitfield.xmmword
2096 && g0.bitfield.ymmword == g1.bitfield.ymmword
2097 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2100 if (!(t0.bitfield.byte & t1.bitfield.byte)
2101 && !(t0.bitfield.word & t1.bitfield.word)
2102 && !(t0.bitfield.dword & t1.bitfield.dword)
2103 && !(t0.bitfield.qword & t1.bitfield.qword)
2104 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2105 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2106 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2109 i.error = register_type_mismatch;
2114 static INLINE unsigned int
2115 register_number (const reg_entry *r)
2117 unsigned int nr = r->reg_num;
2119 if (r->reg_flags & RegRex)
2122 if (r->reg_flags & RegVRex)
2128 static INLINE unsigned int
2129 mode_from_disp_size (i386_operand_type t)
2131 if (t.bitfield.disp8)
2133 else if (t.bitfield.disp16
2134 || t.bitfield.disp32
2135 || t.bitfield.disp32s)
2142 fits_in_signed_byte (addressT num)
2144 return num + 0x80 <= 0xff;
2148 fits_in_unsigned_byte (addressT num)
2154 fits_in_unsigned_word (addressT num)
2156 return num <= 0xffff;
2160 fits_in_signed_word (addressT num)
2162 return num + 0x8000 <= 0xffff;
2166 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2171 return num + 0x80000000 <= 0xffffffff;
2173 } /* fits_in_signed_long() */
2176 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2181 return num <= 0xffffffff;
2183 } /* fits_in_unsigned_long() */
2186 fits_in_disp8 (offsetT num)
2188 int shift = i.memshift;
2194 mask = (1 << shift) - 1;
2196 /* Return 0 if NUM isn't properly aligned. */
2200 /* Check if NUM will fit in 8bit after shift. */
2201 return fits_in_signed_byte (num >> shift);
2205 fits_in_imm4 (offsetT num)
2207 return (num & 0xf) == num;
2210 static i386_operand_type
2211 smallest_imm_type (offsetT num)
2213 i386_operand_type t;
2215 operand_type_set (&t, 0);
2216 t.bitfield.imm64 = 1;
2218 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2220 /* This code is disabled on the 486 because all the Imm1 forms
2221 in the opcode table are slower on the i486. They're the
2222 versions with the implicitly specified single-position
2223 displacement, which has another syntax if you really want to
2225 t.bitfield.imm1 = 1;
2226 t.bitfield.imm8 = 1;
2227 t.bitfield.imm8s = 1;
2228 t.bitfield.imm16 = 1;
2229 t.bitfield.imm32 = 1;
2230 t.bitfield.imm32s = 1;
2232 else if (fits_in_signed_byte (num))
2234 t.bitfield.imm8 = 1;
2235 t.bitfield.imm8s = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2240 else if (fits_in_unsigned_byte (num))
2242 t.bitfield.imm8 = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2247 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2253 else if (fits_in_signed_long (num))
2255 t.bitfield.imm32 = 1;
2256 t.bitfield.imm32s = 1;
2258 else if (fits_in_unsigned_long (num))
2259 t.bitfield.imm32 = 1;
2265 offset_in_range (offsetT val, int size)
2271 case 1: mask = ((addressT) 1 << 8) - 1; break;
2272 case 2: mask = ((addressT) 1 << 16) - 1; break;
2273 case 4: mask = ((addressT) 2 << 31) - 1; break;
2275 case 8: mask = ((addressT) 2 << 63) - 1; break;
2281 /* If BFD64, sign extend val for 32bit address mode. */
2282 if (flag_code != CODE_64BIT
2283 || i.prefix[ADDR_PREFIX])
2284 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2285 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2288 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2290 char buf1[40], buf2[40];
2292 sprint_value (buf1, val);
2293 sprint_value (buf2, val & mask);
2294 as_warn (_("%s shortened to %s"), buf1, buf2);
2309 a. PREFIX_EXIST if attempting to add a prefix where one from the
2310 same class already exists.
2311 b. PREFIX_LOCK if lock prefix is added.
2312 c. PREFIX_REP if rep/repne prefix is added.
2313 d. PREFIX_DS if ds prefix is added.
2314 e. PREFIX_OTHER if other prefix is added.
2317 static enum PREFIX_GROUP
2318 add_prefix (unsigned int prefix)
2320 enum PREFIX_GROUP ret = PREFIX_OTHER;
2323 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2324 && flag_code == CODE_64BIT)
2326 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2327 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2328 && (prefix & (REX_R | REX_X | REX_B))))
2339 case DS_PREFIX_OPCODE:
2342 case CS_PREFIX_OPCODE:
2343 case ES_PREFIX_OPCODE:
2344 case FS_PREFIX_OPCODE:
2345 case GS_PREFIX_OPCODE:
2346 case SS_PREFIX_OPCODE:
2350 case REPNE_PREFIX_OPCODE:
2351 case REPE_PREFIX_OPCODE:
2356 case LOCK_PREFIX_OPCODE:
2365 case ADDR_PREFIX_OPCODE:
2369 case DATA_PREFIX_OPCODE:
2373 if (i.prefix[q] != 0)
2381 i.prefix[q] |= prefix;
2384 as_bad (_("same type of prefix used twice"));
2390 update_code_flag (int value, int check)
2392 PRINTF_LIKE ((*as_error));
2394 flag_code = (enum flag_code) value;
2395 if (flag_code == CODE_64BIT)
2397 cpu_arch_flags.bitfield.cpu64 = 1;
2398 cpu_arch_flags.bitfield.cpuno64 = 0;
2402 cpu_arch_flags.bitfield.cpu64 = 0;
2403 cpu_arch_flags.bitfield.cpuno64 = 1;
2405 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2408 as_error = as_fatal;
2411 (*as_error) (_("64bit mode not supported on `%s'."),
2412 cpu_arch_name ? cpu_arch_name : default_arch);
2414 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2417 as_error = as_fatal;
2420 (*as_error) (_("32bit mode not supported on `%s'."),
2421 cpu_arch_name ? cpu_arch_name : default_arch);
2423 stackop_size = '\0';
2427 set_code_flag (int value)
2429 update_code_flag (value, 0);
2433 set_16bit_gcc_code_flag (int new_code_flag)
2435 flag_code = (enum flag_code) new_code_flag;
2436 if (flag_code != CODE_16BIT)
2438 cpu_arch_flags.bitfield.cpu64 = 0;
2439 cpu_arch_flags.bitfield.cpuno64 = 1;
2440 stackop_size = LONG_MNEM_SUFFIX;
2444 set_intel_syntax (int syntax_flag)
2446 /* Find out if register prefixing is specified. */
2447 int ask_naked_reg = 0;
2450 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2453 int e = get_symbol_name (&string);
2455 if (strcmp (string, "prefix") == 0)
2457 else if (strcmp (string, "noprefix") == 0)
2460 as_bad (_("bad argument to syntax directive."));
2461 (void) restore_line_pointer (e);
2463 demand_empty_rest_of_line ();
2465 intel_syntax = syntax_flag;
2467 if (ask_naked_reg == 0)
2468 allow_naked_reg = (intel_syntax
2469 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2471 allow_naked_reg = (ask_naked_reg < 0);
2473 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2475 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2476 identifier_chars['$'] = intel_syntax ? '$' : 0;
2477 register_prefix = allow_naked_reg ? "" : "%";
2481 set_intel_mnemonic (int mnemonic_flag)
2483 intel_mnemonic = mnemonic_flag;
2487 set_allow_index_reg (int flag)
2489 allow_index_reg = flag;
2493 set_check (int what)
2495 enum check_kind *kind;
2500 kind = &operand_check;
2511 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2514 int e = get_symbol_name (&string);
2516 if (strcmp (string, "none") == 0)
2518 else if (strcmp (string, "warning") == 0)
2519 *kind = check_warning;
2520 else if (strcmp (string, "error") == 0)
2521 *kind = check_error;
2523 as_bad (_("bad argument to %s_check directive."), str);
2524 (void) restore_line_pointer (e);
2527 as_bad (_("missing argument for %s_check directive"), str);
2529 demand_empty_rest_of_line ();
2533 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2534 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2537 static const char *arch;
2539 /* Intel LIOM is only supported on ELF. */
2545 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2546 use default_arch. */
2547 arch = cpu_arch_name;
2549 arch = default_arch;
2552 /* If we are targeting Intel MCU, we must enable it. */
2553 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2554 || new_flag.bitfield.cpuiamcu)
2557 /* If we are targeting Intel L1OM, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2559 || new_flag.bitfield.cpul1om)
2562 /* If we are targeting Intel K1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2564 || new_flag.bitfield.cpuk1om)
2567 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2572 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2576 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2579 int e = get_symbol_name (&string);
2581 i386_cpu_flags flags;
2583 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2585 if (strcmp (string, cpu_arch[j].name) == 0)
2587 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2591 cpu_arch_name = cpu_arch[j].name;
2592 cpu_sub_arch_name = NULL;
2593 cpu_arch_flags = cpu_arch[j].flags;
2594 if (flag_code == CODE_64BIT)
2596 cpu_arch_flags.bitfield.cpu64 = 1;
2597 cpu_arch_flags.bitfield.cpuno64 = 0;
2601 cpu_arch_flags.bitfield.cpu64 = 0;
2602 cpu_arch_flags.bitfield.cpuno64 = 1;
2604 cpu_arch_isa = cpu_arch[j].type;
2605 cpu_arch_isa_flags = cpu_arch[j].flags;
2606 if (!cpu_arch_tune_set)
2608 cpu_arch_tune = cpu_arch_isa;
2609 cpu_arch_tune_flags = cpu_arch_isa_flags;
2614 flags = cpu_flags_or (cpu_arch_flags,
2617 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2619 if (cpu_sub_arch_name)
2621 char *name = cpu_sub_arch_name;
2622 cpu_sub_arch_name = concat (name,
2624 (const char *) NULL);
2628 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2629 cpu_arch_flags = flags;
2630 cpu_arch_isa_flags = flags;
2632 (void) restore_line_pointer (e);
2633 demand_empty_rest_of_line ();
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2640 /* Disable an ISA extension. */
2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2648 if (cpu_sub_arch_name)
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2665 j = ARRAY_SIZE (cpu_arch);
2668 if (j >= ARRAY_SIZE (cpu_arch))
2669 as_bad (_("no such architecture: `%s'"), string);
2671 *input_line_pointer = e;
2674 as_bad (_("missing cpu architecture"));
2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2693 (void) restore_line_pointer (e);
2696 demand_empty_rest_of_line ();
2699 enum bfd_architecture
2702 if (cpu_arch_isa == PROCESSOR_L1OM)
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2724 return bfd_arch_i386;
2730 if (!strncmp (default_arch, "x86_64", 6))
2732 if (cpu_arch_isa == PROCESSOR_L1OM)
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2746 else if (default_arch[6] == '\0')
2747 return bfd_mach_x86_64;
2749 return bfd_mach_x64_32;
2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2761 return bfd_mach_i386_i386;
2764 as_fatal (_("unknown architecture"));
2770 const char *hash_err;
2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2775 /* Initialize op_hash hash table. */
2776 op_hash = hash_new ();
2779 const insn_template *optab;
2780 templates *core_optab;
2782 /* Setup for loop. */
2784 core_optab = XNEW (templates);
2785 core_optab->start = optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2793 /* different name --> ship out current template list;
2794 add to hash table; & begin anew. */
2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2798 (void *) core_optab);
2801 as_fatal (_("can't hash %s: %s"),
2805 if (optab->name == NULL)
2807 core_optab = XNEW (templates);
2808 core_optab->start = optab;
2813 /* Initialize reg_hash hash table. */
2814 reg_hash = hash_new ();
2816 const reg_entry *regtab;
2817 unsigned int regtab_size = i386_regtab_size;
2819 for (regtab = i386_regtab; regtab_size--; regtab++)
2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2823 as_fatal (_("can't hash %s: %s"),
2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2834 for (c = 0; c < 256; c++)
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2843 else if (ISLOWER (c))
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2849 else if (ISUPPER (c))
2851 mnemonic_chars[c] = TOLOWER (c);
2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2855 else if (c == '{' || c == '}')
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2861 if (ISALPHA (c) || ISDIGIT (c))
2862 identifier_chars[c] = c;
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2871 identifier_chars['@'] = '@';
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
2877 digit_chars['-'] = '-';
2878 mnemonic_chars['_'] = '_';
2879 mnemonic_chars['-'] = '-';
2880 mnemonic_chars['.'] = '.';
2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2888 if (flag_code == CODE_64BIT)
2890 #if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2894 x86_dwarf2_return_column = 16;
2896 x86_cie_data_alignment = -8;
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2906 i386_print_statistics (FILE *file)
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2914 /* Debugging routines for md_assemble. */
2915 static void pte (insn_template *);
2916 static void pt (i386_operand_type);
2917 static void pe (expressionS *);
2918 static void ps (symbolS *);
2921 pi (char *line, i386_insn *x)
2925 fprintf (stdout, "%s: template ", line);
2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2932 x->rm.mode, x->rm.reg, x->rm.regmem);
2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
2940 for (j = 0; j < x->operands; j++)
2942 fprintf (stdout, " #%d: ", j + 1);
2944 fprintf (stdout, "\n");
2945 if (x->types[j].bitfield.reg
2946 || x->types[j].bitfield.regmmx
2947 || x->types[j].bitfield.regsimd
2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
2962 pte (insn_template *t)
2965 fprintf (stdout, " %d operands ", t->operands);
2966 fprintf (stdout, "opcode %x ", t->base_opcode);
2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
2969 if (t->opcode_modifier.d)
2970 fprintf (stdout, "D");
2971 if (t->opcode_modifier.w)
2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
2974 for (j = 0; j < t->operands; j++)
2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
2978 fprintf (stdout, "\n");
2985 fprintf (stdout, " operation %d\n", e->X_op);
2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
2988 if (e->X_add_symbol)
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
3005 fprintf (stdout, "%s type %s%s",
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3011 static struct type_name
3013 i386_operand_type mask;
3016 const type_names[] =
3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
3048 { OPERAND_TYPE_REGYMM, "rYMM" },
3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
3051 { OPERAND_TYPE_ESSEG, "es" },
3055 pt (i386_operand_type t)
3058 i386_operand_type a;
3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3062 a = operand_type_and (t, type_names[j].mask);
3063 if (!operand_type_all_zero (&a))
3064 fprintf (stdout, "%s, ", type_names[j].name);
3069 #endif /* DEBUG386 */
3071 static bfd_reloc_code_real_type
3072 reloc (unsigned int size,
3075 bfd_reloc_code_real_type other)
3077 if (other != NO_RELOC)
3079 reloc_howto_type *rel;
3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3110 if (other == BFD_RELOC_SIZE32)
3113 other = BFD_RELOC_SIZE64;
3116 as_bad (_("there are no pc-relative size relocations"));
3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3128 as_bad (_("unknown relocation (%u)"), other);
3129 else if (size != bfd_get_reloc_size (rel))
3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3131 bfd_get_reloc_size (rel),
3133 else if (pcrel && !rel->pc_relative)
3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3137 || (rel->complain_on_overflow == complain_overflow_unsigned
3139 as_bad (_("relocated field and relocation type differ in signedness"));
3148 as_bad (_("there are no unsigned pc-relative relocations"));
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
3153 case 4: return BFD_RELOC_32_PCREL;
3154 case 8: return BFD_RELOC_64_PCREL;
3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3163 case 4: return BFD_RELOC_X86_64_32S;
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
3180 /* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3186 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3246 intel_float_operand (const char *mnemonic)
3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3255 switch (mnemonic[1])
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3261 return 2 /* integer op */;
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3279 switch (mnemonic[3])
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3298 /* Build the VEX prefix. */
3301 build_vex_prefix (const insn_template *t)
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3315 register_specifier = 0xf;
3317 /* Use 2-byte VEX prefix by swapping destination and source
3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
3321 && i.operands == i.reg_operands
3322 && i.tm.opcode_modifier.vexopcode == VEX0F
3323 && i.tm.opcode_modifier.load
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3337 gas_assert (i.rm.mode == 3);
3341 i.rm.regmem = i.rm.reg;
3344 /* Use the next insn. */
3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
3350 else if (i.tm.opcode_modifier.vex == VEX256)
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3372 case DATA_PREFIX_OPCODE:
3375 case REPE_PREFIX_OPCODE:
3378 case REPNE_PREFIX_OPCODE:
3385 /* Use 2-byte VEX prefix if possible. */
3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
3388 && i.tm.opcode_modifier.vexw != VEXW1
3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3391 /* 2-byte VEX prefix. */
3395 i.vex.bytes[0] = 0xc5;
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3406 /* 3-byte VEX prefix. */
3411 switch (i.tm.opcode_modifier.vexopcode)
3415 i.vex.bytes[0] = 0xc4;
3419 i.vex.bytes[0] = 0xc4;
3423 i.vex.bytes[0] = 0xc4;
3427 i.vex.bytes[0] = 0x8f;
3431 i.vex.bytes[0] = 0x8f;
3435 i.vex.bytes[0] = 0x8f;
3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3457 /* Build the EVEX prefix. */
3460 build_evex_prefix (void)
3462 unsigned int register_specifier;
3463 unsigned int implied_prefix;
3465 rex_byte vrex_used = 0;
3467 /* Check register specifier. */
3468 if (i.vex.register_specifier)
3470 gas_assert ((i.vrex & REX_X) == 0);
3472 register_specifier = i.vex.register_specifier->reg_num;
3473 if ((i.vex.register_specifier->reg_flags & RegRex))
3474 register_specifier += 8;
3475 /* The upper 16 registers are encoded in the fourth byte of the
3477 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3478 i.vex.bytes[3] = 0x8;
3479 register_specifier = ~register_specifier & 0xf;
3483 register_specifier = 0xf;
3485 /* Encode upper 16 vector index register in the fourth byte of
3487 if (!(i.vrex & REX_X))
3488 i.vex.bytes[3] = 0x8;
3493 switch ((i.tm.base_opcode >> 8) & 0xff)
3498 case DATA_PREFIX_OPCODE:
3501 case REPE_PREFIX_OPCODE:
3504 case REPNE_PREFIX_OPCODE:
3511 /* 4 byte EVEX prefix. */
3513 i.vex.bytes[0] = 0x62;
3516 switch (i.tm.opcode_modifier.vexopcode)
3532 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3534 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3536 /* The fifth bit of the second EVEX byte is 1's compliment of the
3537 REX_R bit in VREX. */
3538 if (!(i.vrex & REX_R))
3539 i.vex.bytes[1] |= 0x10;
3543 if ((i.reg_operands + i.imm_operands) == i.operands)
3545 /* When all operands are registers, the REX_X bit in REX is not
3546 used. We reuse it to encode the upper 16 registers, which is
3547 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3548 as 1's compliment. */
3549 if ((i.vrex & REX_B))
3552 i.vex.bytes[1] &= ~0x40;
3556 /* EVEX instructions shouldn't need the REX prefix. */
3557 i.vrex &= ~vrex_used;
3558 gas_assert (i.vrex == 0);
3560 /* Check the REX.W bit. */
3561 w = (i.rex & REX_W) ? 1 : 0;
3562 if (i.tm.opcode_modifier.vexw)
3564 if (i.tm.opcode_modifier.vexw == VEXW1)
3567 /* If w is not set it means we are dealing with WIG instruction. */
3570 if (evexwig == evexw1)
3574 /* Encode the U bit. */
3575 implied_prefix |= 0x4;
3577 /* The third byte of the EVEX prefix. */
3578 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3580 /* The fourth byte of the EVEX prefix. */
3581 /* The zeroing-masking bit. */
3582 if (i.mask && i.mask->zeroing)
3583 i.vex.bytes[3] |= 0x80;
3585 /* Don't always set the broadcast bit if there is no RC. */
3588 /* Encode the vector length. */
3589 unsigned int vec_length;
3591 switch (i.tm.opcode_modifier.evex)
3593 case EVEXLIG: /* LL' is ignored */
3594 vec_length = evexlig << 5;
3597 vec_length = 0 << 5;
3600 vec_length = 1 << 5;
3603 vec_length = 2 << 5;
3609 i.vex.bytes[3] |= vec_length;
3610 /* Encode the broadcast bit. */
3612 i.vex.bytes[3] |= 0x10;
3616 if (i.rounding->type != saeonly)
3617 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3619 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3622 if (i.mask && i.mask->mask)
3623 i.vex.bytes[3] |= i.mask->mask->reg_num;
3627 process_immext (void)
3631 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3634 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3635 with an opcode suffix which is coded in the same place as an
3636 8-bit immediate field would be.
3637 Here we check those operands and remove them afterwards. */
3640 for (x = 0; x < i.operands; x++)
3641 if (register_number (i.op[x].regs) != x)
3642 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3643 register_prefix, i.op[x].regs->reg_name, x + 1,
3649 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3651 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3652 suffix which is coded in the same place as an 8-bit immediate
3654 Here we check those operands and remove them afterwards. */
3657 if (i.operands != 3)
3660 for (x = 0; x < 2; x++)
3661 if (register_number (i.op[x].regs) != x)
3662 goto bad_register_operand;
3664 /* Check for third operand for mwaitx/monitorx insn. */
3665 if (register_number (i.op[x].regs)
3666 != (x + (i.tm.extension_opcode == 0xfb)))
3668 bad_register_operand:
3669 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3670 register_prefix, i.op[x].regs->reg_name, x+1,
3677 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3678 which is coded in the same place as an 8-bit immediate field
3679 would be. Here we fake an 8-bit immediate operand from the
3680 opcode suffix stored in tm.extension_opcode.
3682 AVX instructions also use this encoding, for some of
3683 3 argument instructions. */
3685 gas_assert (i.imm_operands <= 1
3687 || ((i.tm.opcode_modifier.vex
3688 || i.tm.opcode_modifier.evex)
3689 && i.operands <= 4)));
3691 exp = &im_expressions[i.imm_operands++];
3692 i.op[i.operands].imms = exp;
3693 i.types[i.operands] = imm8;
3695 exp->X_op = O_constant;
3696 exp->X_add_number = i.tm.extension_opcode;
3697 i.tm.extension_opcode = None;
3704 switch (i.tm.opcode_modifier.hleprefixok)
3709 as_bad (_("invalid instruction `%s' after `%s'"),
3710 i.tm.name, i.hle_prefix);
3713 if (i.prefix[LOCK_PREFIX])
3715 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3719 case HLEPrefixRelease:
3720 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3722 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3726 if (i.mem_operands == 0
3727 || !operand_type_check (i.types[i.operands - 1], anymem))
3729 as_bad (_("memory destination needed for instruction `%s'"
3730 " after `xrelease'"), i.tm.name);
3737 /* Try the shortest encoding by shortening operand size. */
3740 optimize_encoding (void)
3744 if (optimize_for_space
3745 && i.reg_operands == 1
3746 && i.imm_operands == 1
3747 && !i.types[1].bitfield.byte
3748 && i.op[0].imms->X_op == O_constant
3749 && fits_in_imm7 (i.op[0].imms->X_add_number)
3750 && ((i.tm.base_opcode == 0xa8
3751 && i.tm.extension_opcode == None)
3752 || (i.tm.base_opcode == 0xf6
3753 && i.tm.extension_opcode == 0x0)))
3756 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3758 unsigned int base_regnum = i.op[1].regs->reg_num;
3759 if (flag_code == CODE_64BIT || base_regnum < 4)
3761 i.types[1].bitfield.byte = 1;
3762 /* Ignore the suffix. */
3764 if (base_regnum >= 4
3765 && !(i.op[1].regs->reg_flags & RegRex))
3767 /* Handle SP, BP, SI and DI registers. */
3768 if (i.types[1].bitfield.word)
3770 else if (i.types[1].bitfield.dword)
3778 else if (flag_code == CODE_64BIT
3779 && ((i.reg_operands == 1
3780 && i.imm_operands == 1
3781 && i.op[0].imms->X_op == O_constant
3782 && ((i.tm.base_opcode == 0xb0
3783 && i.tm.extension_opcode == None
3784 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3785 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3786 && (((i.tm.base_opcode == 0x24
3787 || i.tm.base_opcode == 0xa8)
3788 && i.tm.extension_opcode == None)
3789 || (i.tm.base_opcode == 0x80
3790 && i.tm.extension_opcode == 0x4)
3791 || ((i.tm.base_opcode == 0xf6
3792 || i.tm.base_opcode == 0xc6)
3793 && i.tm.extension_opcode == 0x0)))))
3794 || (i.reg_operands == 2
3795 && i.op[0].regs == i.op[1].regs
3796 && ((i.tm.base_opcode == 0x30
3797 || i.tm.base_opcode == 0x28)
3798 && i.tm.extension_opcode == None)))
3799 && i.types[1].bitfield.qword)
3802 andq $imm31, %r64 -> andl $imm31, %r32
3803 testq $imm31, %r64 -> testl $imm31, %r32
3804 xorq %r64, %r64 -> xorl %r32, %r32
3805 subq %r64, %r64 -> subl %r32, %r32
3806 movq $imm31, %r64 -> movl $imm31, %r32
3807 movq $imm32, %r64 -> movl $imm32, %r32
3809 i.tm.opcode_modifier.norex64 = 1;
3810 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3813 movq $imm31, %r64 -> movl $imm31, %r32
3814 movq $imm32, %r64 -> movl $imm32, %r32
3816 i.tm.operand_types[0].bitfield.imm32 = 1;
3817 i.tm.operand_types[0].bitfield.imm32s = 0;
3818 i.tm.operand_types[0].bitfield.imm64 = 0;
3819 i.types[0].bitfield.imm32 = 1;
3820 i.types[0].bitfield.imm32s = 0;
3821 i.types[0].bitfield.imm64 = 0;
3822 i.types[1].bitfield.dword = 1;
3823 i.types[1].bitfield.qword = 0;
3824 if (i.tm.base_opcode == 0xc6)
3827 movq $imm31, %r64 -> movl $imm31, %r32
3829 i.tm.base_opcode = 0xb0;
3830 i.tm.extension_opcode = None;
3831 i.tm.opcode_modifier.shortform = 1;
3832 i.tm.opcode_modifier.modrm = 0;
3836 else if (optimize > 1
3837 && i.reg_operands == 3
3838 && i.op[0].regs == i.op[1].regs
3839 && !i.types[2].bitfield.xmmword
3840 && (i.tm.opcode_modifier.vex
3843 && i.tm.opcode_modifier.evex
3844 && cpu_arch_flags.bitfield.cpuavx512vl))
3845 && ((i.tm.base_opcode == 0x55
3846 || i.tm.base_opcode == 0x6655
3847 || i.tm.base_opcode == 0x66df
3848 || i.tm.base_opcode == 0x57
3849 || i.tm.base_opcode == 0x6657
3850 || i.tm.base_opcode == 0x66ef
3851 || i.tm.base_opcode == 0x66f8
3852 || i.tm.base_opcode == 0x66f9
3853 || i.tm.base_opcode == 0x66fa
3854 || i.tm.base_opcode == 0x66fb)
3855 && i.tm.extension_opcode == None))
3858 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3860 EVEX VOP %zmmM, %zmmM, %zmmN
3861 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3862 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3863 EVEX VOP %ymmM, %ymmM, %ymmN
3864 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3865 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3866 VEX VOP %ymmM, %ymmM, %ymmN
3867 -> VEX VOP %xmmM, %xmmM, %xmmN
3868 VOP, one of vpandn and vpxor:
3869 VEX VOP %ymmM, %ymmM, %ymmN
3870 -> VEX VOP %xmmM, %xmmM, %xmmN
3871 VOP, one of vpandnd and vpandnq:
3872 EVEX VOP %zmmM, %zmmM, %zmmN
3873 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3875 EVEX VOP %ymmM, %ymmM, %ymmN
3876 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3877 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3878 VOP, one of vpxord and vpxorq:
3879 EVEX VOP %zmmM, %zmmM, %zmmN
3880 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 EVEX VOP %ymmM, %ymmM, %ymmN
3883 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3884 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3886 if (i.tm.opcode_modifier.evex)
3888 /* If only lower 16 vector registers are used, we can use
3890 for (j = 0; j < 3; j++)
3891 if (register_number (i.op[j].regs) > 15)
3895 i.tm.opcode_modifier.evex = EVEX128;
3898 i.tm.opcode_modifier.vex = VEX128;
3899 i.tm.opcode_modifier.vexw = VEXW0;
3900 i.tm.opcode_modifier.evex = 0;
3904 i.tm.opcode_modifier.vex = VEX128;
3906 if (i.tm.opcode_modifier.vex)
3907 for (j = 0; j < 3; j++)
3909 i.types[j].bitfield.xmmword = 1;
3910 i.types[j].bitfield.ymmword = 0;
3915 /* This is the guts of the machine-dependent assembler. LINE points to a
3916 machine dependent instruction. This function is supposed to emit
3917 the frags/bytes it assembles to. */
3920 md_assemble (char *line)
3923 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3924 const insn_template *t;
3926 /* Initialize globals. */
3927 memset (&i, '\0', sizeof (i));
3928 for (j = 0; j < MAX_OPERANDS; j++)
3929 i.reloc[j] = NO_RELOC;
3930 memset (disp_expressions, '\0', sizeof (disp_expressions));
3931 memset (im_expressions, '\0', sizeof (im_expressions));
3932 save_stack_p = save_stack;
3934 /* First parse an instruction mnemonic & call i386_operand for the operands.
3935 We assume that the scrubber has arranged it so that line[0] is the valid
3936 start of a (possibly prefixed) mnemonic. */
3938 line = parse_insn (line, mnemonic);
3941 mnem_suffix = i.suffix;
3943 line = parse_operands (line, mnemonic);
3945 xfree (i.memop1_string);
3946 i.memop1_string = NULL;
3950 /* Now we've parsed the mnemonic into a set of templates, and have the
3951 operands at hand. */
3953 /* All intel opcodes have reversed operands except for "bound" and
3954 "enter". We also don't reverse intersegment "jmp" and "call"
3955 instructions with 2 immediate operands so that the immediate segment
3956 precedes the offset, as it does when in AT&T mode. */
3959 && (strcmp (mnemonic, "bound") != 0)
3960 && (strcmp (mnemonic, "invlpga") != 0)
3961 && !(operand_type_check (i.types[0], imm)
3962 && operand_type_check (i.types[1], imm)))
3965 /* The order of the immediates should be reversed
3966 for 2 immediates extrq and insertq instructions */
3967 if (i.imm_operands == 2
3968 && (strcmp (mnemonic, "extrq") == 0
3969 || strcmp (mnemonic, "insertq") == 0))
3970 swap_2_operands (0, 1);
3975 /* Don't optimize displacement for movabs since it only takes 64bit
3978 && i.disp_encoding != disp_encoding_32bit
3979 && (flag_code != CODE_64BIT
3980 || strcmp (mnemonic, "movabs") != 0))
3983 /* Next, we find a template that matches the given insn,
3984 making sure the overlap of the given operands types is consistent
3985 with the template operand types. */
3987 if (!(t = match_template (mnem_suffix)))
3990 if (sse_check != check_none
3991 && !i.tm.opcode_modifier.noavx
3992 && !i.tm.cpu_flags.bitfield.cpuavx
3993 && (i.tm.cpu_flags.bitfield.cpusse
3994 || i.tm.cpu_flags.bitfield.cpusse2
3995 || i.tm.cpu_flags.bitfield.cpusse3
3996 || i.tm.cpu_flags.bitfield.cpussse3
3997 || i.tm.cpu_flags.bitfield.cpusse4_1
3998 || i.tm.cpu_flags.bitfield.cpusse4_2
3999 || i.tm.cpu_flags.bitfield.cpupclmul
4000 || i.tm.cpu_flags.bitfield.cpuaes
4001 || i.tm.cpu_flags.bitfield.cpugfni))
4003 (sse_check == check_warning
4005 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4008 /* Zap movzx and movsx suffix. The suffix has been set from
4009 "word ptr" or "byte ptr" on the source operand in Intel syntax
4010 or extracted from mnemonic in AT&T syntax. But we'll use
4011 the destination register to choose the suffix for encoding. */
4012 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4014 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4015 there is no suffix, the default will be byte extension. */
4016 if (i.reg_operands != 2
4019 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4024 if (i.tm.opcode_modifier.fwait)
4025 if (!add_prefix (FWAIT_OPCODE))
4028 /* Check if REP prefix is OK. */
4029 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4031 as_bad (_("invalid instruction `%s' after `%s'"),
4032 i.tm.name, i.rep_prefix);
4036 /* Check for lock without a lockable instruction. Destination operand
4037 must be memory unless it is xchg (0x86). */
4038 if (i.prefix[LOCK_PREFIX]
4039 && (!i.tm.opcode_modifier.islockable
4040 || i.mem_operands == 0
4041 || (i.tm.base_opcode != 0x86
4042 && !operand_type_check (i.types[i.operands - 1], anymem))))
4044 as_bad (_("expecting lockable instruction after `lock'"));
4048 /* Check if HLE prefix is OK. */
4049 if (i.hle_prefix && !check_hle ())
4052 /* Check BND prefix. */
4053 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4054 as_bad (_("expecting valid branch instruction after `bnd'"));
4056 /* Check NOTRACK prefix. */
4057 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4058 as_bad (_("expecting indirect branch instruction after `notrack'"));
4060 if (i.tm.cpu_flags.bitfield.cpumpx)
4062 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4063 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4064 else if (flag_code != CODE_16BIT
4065 ? i.prefix[ADDR_PREFIX]
4066 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4067 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4070 /* Insert BND prefix. */
4072 && i.tm.opcode_modifier.bndprefixok
4073 && !i.prefix[BND_PREFIX])
4074 add_prefix (BND_PREFIX_OPCODE);
4076 /* Check string instruction segment overrides. */
4077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4079 if (!check_string ())
4081 i.disp_operands = 0;
4084 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4085 optimize_encoding ();
4087 if (!process_suffix ())
4090 /* Update operand types. */
4091 for (j = 0; j < i.operands; j++)
4092 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4094 /* Make still unresolved immediate matches conform to size of immediate
4095 given in i.suffix. */
4096 if (!finalize_imm ())
4099 if (i.types[0].bitfield.imm1)
4100 i.imm_operands = 0; /* kludge for shift insns. */
4102 /* We only need to check those implicit registers for instructions
4103 with 3 operands or less. */
4104 if (i.operands <= 3)
4105 for (j = 0; j < i.operands; j++)
4106 if (i.types[j].bitfield.inoutportreg
4107 || i.types[j].bitfield.shiftcount
4108 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4111 /* ImmExt should be processed after SSE2AVX. */
4112 if (!i.tm.opcode_modifier.sse2avx
4113 && i.tm.opcode_modifier.immext)
4116 /* For insns with operands there are more diddles to do to the opcode. */
4119 if (!process_operands ())
4122 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4124 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4125 as_warn (_("translating to `%sp'"), i.tm.name);
4128 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4130 if (flag_code == CODE_16BIT)
4132 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4137 if (i.tm.opcode_modifier.vex)
4138 build_vex_prefix (t);
4140 build_evex_prefix ();
4143 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4144 instructions may define INT_OPCODE as well, so avoid this corner
4145 case for those instructions that use MODRM. */
4146 if (i.tm.base_opcode == INT_OPCODE
4147 && !i.tm.opcode_modifier.modrm
4148 && i.op[0].imms->X_add_number == 3)
4150 i.tm.base_opcode = INT3_OPCODE;
4154 if ((i.tm.opcode_modifier.jump
4155 || i.tm.opcode_modifier.jumpbyte
4156 || i.tm.opcode_modifier.jumpdword)
4157 && i.op[0].disps->X_op == O_constant)
4159 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4160 the absolute address given by the constant. Since ix86 jumps and
4161 calls are pc relative, we need to generate a reloc. */
4162 i.op[0].disps->X_add_symbol = &abs_symbol;
4163 i.op[0].disps->X_op = O_symbol;
4166 if (i.tm.opcode_modifier.rex64)
4169 /* For 8 bit registers we need an empty rex prefix. Also if the
4170 instruction already has a prefix, we need to convert old
4171 registers to new ones. */
4173 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4174 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4175 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4176 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4177 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4178 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4183 i.rex |= REX_OPCODE;
4184 for (x = 0; x < 2; x++)
4186 /* Look for 8 bit operand that uses old registers. */
4187 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4188 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4190 /* In case it is "hi" register, give up. */
4191 if (i.op[x].regs->reg_num > 3)
4192 as_bad (_("can't encode register '%s%s' in an "
4193 "instruction requiring REX prefix."),
4194 register_prefix, i.op[x].regs->reg_name);
4196 /* Otherwise it is equivalent to the extended register.
4197 Since the encoding doesn't change this is merely
4198 cosmetic cleanup for debug output. */
4200 i.op[x].regs = i.op[x].regs + 8;
4205 if (i.rex == 0 && i.rex_encoding)
4207 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4208 that uses legacy register. If it is "hi" register, don't add
4209 the REX_OPCODE byte. */
4211 for (x = 0; x < 2; x++)
4212 if (i.types[x].bitfield.reg
4213 && i.types[x].bitfield.byte
4214 && (i.op[x].regs->reg_flags & RegRex64) == 0
4215 && i.op[x].regs->reg_num > 3)
4217 i.rex_encoding = FALSE;
4226 add_prefix (REX_OPCODE | i.rex);
4228 /* We are ready to output the insn. */
4233 parse_insn (char *line, char *mnemonic)
4236 char *token_start = l;
4239 const insn_template *t;
4245 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4250 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4252 as_bad (_("no such instruction: `%s'"), token_start);
4257 if (!is_space_char (*l)
4258 && *l != END_OF_INSN
4260 || (*l != PREFIX_SEPARATOR
4263 as_bad (_("invalid character %s in mnemonic"),
4264 output_invalid (*l));
4267 if (token_start == l)
4269 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4270 as_bad (_("expecting prefix; got nothing"));
4272 as_bad (_("expecting mnemonic; got nothing"));
4276 /* Look up instruction (or prefix) via hash table. */
4277 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4279 if (*l != END_OF_INSN
4280 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4281 && current_templates
4282 && current_templates->start->opcode_modifier.isprefix)
4284 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4286 as_bad ((flag_code != CODE_64BIT
4287 ? _("`%s' is only supported in 64-bit mode")
4288 : _("`%s' is not supported in 64-bit mode")),
4289 current_templates->start->name);
4292 /* If we are in 16-bit mode, do not allow addr16 or data16.
4293 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4294 if ((current_templates->start->opcode_modifier.size16
4295 || current_templates->start->opcode_modifier.size32)
4296 && flag_code != CODE_64BIT
4297 && (current_templates->start->opcode_modifier.size32
4298 ^ (flag_code == CODE_16BIT)))
4300 as_bad (_("redundant %s prefix"),
4301 current_templates->start->name);
4304 if (current_templates->start->opcode_length == 0)
4306 /* Handle pseudo prefixes. */
4307 switch (current_templates->start->base_opcode)
4311 i.disp_encoding = disp_encoding_8bit;
4315 i.disp_encoding = disp_encoding_32bit;
4319 i.dir_encoding = dir_encoding_load;
4323 i.dir_encoding = dir_encoding_store;
4327 i.vec_encoding = vex_encoding_vex2;
4331 i.vec_encoding = vex_encoding_vex3;
4335 i.vec_encoding = vex_encoding_evex;
4339 i.rex_encoding = TRUE;
4343 i.no_optimize = TRUE;
4351 /* Add prefix, checking for repeated prefixes. */
4352 switch (add_prefix (current_templates->start->base_opcode))
4357 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4358 i.notrack_prefix = current_templates->start->name;
4361 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4362 i.hle_prefix = current_templates->start->name;
4363 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4364 i.bnd_prefix = current_templates->start->name;
4366 i.rep_prefix = current_templates->start->name;
4372 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4379 if (!current_templates)
4381 /* Check if we should swap operand or force 32bit displacement in
4383 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4384 i.dir_encoding = dir_encoding_store;
4385 else if (mnem_p - 3 == dot_p
4388 i.disp_encoding = disp_encoding_8bit;
4389 else if (mnem_p - 4 == dot_p
4393 i.disp_encoding = disp_encoding_32bit;
4398 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4401 if (!current_templates)
4404 /* See if we can get a match by trimming off a suffix. */
4407 case WORD_MNEM_SUFFIX:
4408 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4409 i.suffix = SHORT_MNEM_SUFFIX;
4412 case BYTE_MNEM_SUFFIX:
4413 case QWORD_MNEM_SUFFIX:
4414 i.suffix = mnem_p[-1];
4416 current_templates = (const templates *) hash_find (op_hash,
4419 case SHORT_MNEM_SUFFIX:
4420 case LONG_MNEM_SUFFIX:
4423 i.suffix = mnem_p[-1];
4425 current_templates = (const templates *) hash_find (op_hash,
4434 if (intel_float_operand (mnemonic) == 1)
4435 i.suffix = SHORT_MNEM_SUFFIX;
4437 i.suffix = LONG_MNEM_SUFFIX;
4439 current_templates = (const templates *) hash_find (op_hash,
4444 if (!current_templates)
4446 as_bad (_("no such instruction: `%s'"), token_start);
4451 if (current_templates->start->opcode_modifier.jump
4452 || current_templates->start->opcode_modifier.jumpbyte)
4454 /* Check for a branch hint. We allow ",pt" and ",pn" for
4455 predict taken and predict not taken respectively.
4456 I'm not sure that branch hints actually do anything on loop
4457 and jcxz insns (JumpByte) for current Pentium4 chips. They
4458 may work in the future and it doesn't hurt to accept them
4460 if (l[0] == ',' && l[1] == 'p')
4464 if (!add_prefix (DS_PREFIX_OPCODE))
4468 else if (l[2] == 'n')
4470 if (!add_prefix (CS_PREFIX_OPCODE))
4476 /* Any other comma loses. */
4479 as_bad (_("invalid character %s in mnemonic"),
4480 output_invalid (*l));
4484 /* Check if instruction is supported on specified architecture. */
4486 for (t = current_templates->start; t < current_templates->end; ++t)
4488 supported |= cpu_flags_match (t);
4489 if (supported == CPU_FLAGS_PERFECT_MATCH)
4491 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4492 as_warn (_("use .code16 to ensure correct addressing mode"));
4498 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4499 as_bad (flag_code == CODE_64BIT
4500 ? _("`%s' is not supported in 64-bit mode")
4501 : _("`%s' is only supported in 64-bit mode"),
4502 current_templates->start->name);
4504 as_bad (_("`%s' is not supported on `%s%s'"),
4505 current_templates->start->name,
4506 cpu_arch_name ? cpu_arch_name : default_arch,
4507 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4513 parse_operands (char *l, const char *mnemonic)
4517 /* 1 if operand is pending after ','. */
4518 unsigned int expecting_operand = 0;
4520 /* Non-zero if operand parens not balanced. */
4521 unsigned int paren_not_balanced;
4523 while (*l != END_OF_INSN)
4525 /* Skip optional white space before operand. */
4526 if (is_space_char (*l))
4528 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4530 as_bad (_("invalid character %s before operand %d"),
4531 output_invalid (*l),
4535 token_start = l; /* After white space. */
4536 paren_not_balanced = 0;
4537 while (paren_not_balanced || *l != ',')
4539 if (*l == END_OF_INSN)
4541 if (paren_not_balanced)
4544 as_bad (_("unbalanced parenthesis in operand %d."),
4547 as_bad (_("unbalanced brackets in operand %d."),
4552 break; /* we are done */
4554 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4556 as_bad (_("invalid character %s in operand %d"),
4557 output_invalid (*l),
4564 ++paren_not_balanced;
4566 --paren_not_balanced;
4571 ++paren_not_balanced;
4573 --paren_not_balanced;
4577 if (l != token_start)
4578 { /* Yes, we've read in another operand. */
4579 unsigned int operand_ok;
4580 this_operand = i.operands++;
4581 if (i.operands > MAX_OPERANDS)
4583 as_bad (_("spurious operands; (%d operands/instruction max)"),
4587 i.types[this_operand].bitfield.unspecified = 1;
4588 /* Now parse operand adding info to 'i' as we go along. */
4589 END_STRING_AND_SAVE (l);
4593 i386_intel_operand (token_start,
4594 intel_float_operand (mnemonic));
4596 operand_ok = i386_att_operand (token_start);
4598 RESTORE_END_STRING (l);
4604 if (expecting_operand)
4606 expecting_operand_after_comma:
4607 as_bad (_("expecting operand after ','; got nothing"));
4612 as_bad (_("expecting operand before ','; got nothing"));
4617 /* Now *l must be either ',' or END_OF_INSN. */
4620 if (*++l == END_OF_INSN)
4622 /* Just skip it, if it's \n complain. */
4623 goto expecting_operand_after_comma;
4625 expecting_operand = 1;
4632 swap_2_operands (int xchg1, int xchg2)
4634 union i386_op temp_op;
4635 i386_operand_type temp_type;
4636 enum bfd_reloc_code_real temp_reloc;
4638 temp_type = i.types[xchg2];
4639 i.types[xchg2] = i.types[xchg1];
4640 i.types[xchg1] = temp_type;
4641 temp_op = i.op[xchg2];
4642 i.op[xchg2] = i.op[xchg1];
4643 i.op[xchg1] = temp_op;
4644 temp_reloc = i.reloc[xchg2];
4645 i.reloc[xchg2] = i.reloc[xchg1];
4646 i.reloc[xchg1] = temp_reloc;
4650 if (i.mask->operand == xchg1)
4651 i.mask->operand = xchg2;
4652 else if (i.mask->operand == xchg2)
4653 i.mask->operand = xchg1;
4657 if (i.broadcast->operand == xchg1)
4658 i.broadcast->operand = xchg2;
4659 else if (i.broadcast->operand == xchg2)
4660 i.broadcast->operand = xchg1;
4664 if (i.rounding->operand == xchg1)
4665 i.rounding->operand = xchg2;
4666 else if (i.rounding->operand == xchg2)
4667 i.rounding->operand = xchg1;
4672 swap_operands (void)
4678 swap_2_operands (1, i.operands - 2);
4682 swap_2_operands (0, i.operands - 1);
4688 if (i.mem_operands == 2)
4690 const seg_entry *temp_seg;
4691 temp_seg = i.seg[0];
4692 i.seg[0] = i.seg[1];
4693 i.seg[1] = temp_seg;
4697 /* Try to ensure constant immediates are represented in the smallest
4702 char guess_suffix = 0;
4706 guess_suffix = i.suffix;
4707 else if (i.reg_operands)
4709 /* Figure out a suffix from the last register operand specified.
4710 We can't do this properly yet, ie. excluding InOutPortReg,
4711 but the following works for instructions with immediates.
4712 In any case, we can't set i.suffix yet. */
4713 for (op = i.operands; --op >= 0;)
4714 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4716 guess_suffix = BYTE_MNEM_SUFFIX;
4719 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4721 guess_suffix = WORD_MNEM_SUFFIX;
4724 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4726 guess_suffix = LONG_MNEM_SUFFIX;
4729 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4731 guess_suffix = QWORD_MNEM_SUFFIX;
4735 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4736 guess_suffix = WORD_MNEM_SUFFIX;
4738 for (op = i.operands; --op >= 0;)
4739 if (operand_type_check (i.types[op], imm))
4741 switch (i.op[op].imms->X_op)
4744 /* If a suffix is given, this operand may be shortened. */
4745 switch (guess_suffix)
4747 case LONG_MNEM_SUFFIX:
4748 i.types[op].bitfield.imm32 = 1;
4749 i.types[op].bitfield.imm64 = 1;
4751 case WORD_MNEM_SUFFIX:
4752 i.types[op].bitfield.imm16 = 1;
4753 i.types[op].bitfield.imm32 = 1;
4754 i.types[op].bitfield.imm32s = 1;
4755 i.types[op].bitfield.imm64 = 1;
4757 case BYTE_MNEM_SUFFIX:
4758 i.types[op].bitfield.imm8 = 1;
4759 i.types[op].bitfield.imm8s = 1;
4760 i.types[op].bitfield.imm16 = 1;
4761 i.types[op].bitfield.imm32 = 1;
4762 i.types[op].bitfield.imm32s = 1;
4763 i.types[op].bitfield.imm64 = 1;
4767 /* If this operand is at most 16 bits, convert it
4768 to a signed 16 bit number before trying to see
4769 whether it will fit in an even smaller size.
4770 This allows a 16-bit operand such as $0xffe0 to
4771 be recognised as within Imm8S range. */
4772 if ((i.types[op].bitfield.imm16)
4773 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4775 i.op[op].imms->X_add_number =
4776 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4779 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4780 if ((i.types[op].bitfield.imm32)
4781 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4784 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4785 ^ ((offsetT) 1 << 31))
4786 - ((offsetT) 1 << 31));
4790 = operand_type_or (i.types[op],
4791 smallest_imm_type (i.op[op].imms->X_add_number));
4793 /* We must avoid matching of Imm32 templates when 64bit
4794 only immediate is available. */
4795 if (guess_suffix == QWORD_MNEM_SUFFIX)
4796 i.types[op].bitfield.imm32 = 0;
4803 /* Symbols and expressions. */
4805 /* Convert symbolic operand to proper sizes for matching, but don't
4806 prevent matching a set of insns that only supports sizes other
4807 than those matching the insn suffix. */
4809 i386_operand_type mask, allowed;
4810 const insn_template *t;
4812 operand_type_set (&mask, 0);
4813 operand_type_set (&allowed, 0);
4815 for (t = current_templates->start;
4816 t < current_templates->end;
4818 allowed = operand_type_or (allowed,
4819 t->operand_types[op]);
4820 switch (guess_suffix)
4822 case QWORD_MNEM_SUFFIX:
4823 mask.bitfield.imm64 = 1;
4824 mask.bitfield.imm32s = 1;
4826 case LONG_MNEM_SUFFIX:
4827 mask.bitfield.imm32 = 1;
4829 case WORD_MNEM_SUFFIX:
4830 mask.bitfield.imm16 = 1;
4832 case BYTE_MNEM_SUFFIX:
4833 mask.bitfield.imm8 = 1;
4838 allowed = operand_type_and (mask, allowed);
4839 if (!operand_type_all_zero (&allowed))
4840 i.types[op] = operand_type_and (i.types[op], mask);
4847 /* Try to use the smallest displacement type too. */
4849 optimize_disp (void)
4853 for (op = i.operands; --op >= 0;)
4854 if (operand_type_check (i.types[op], disp))
4856 if (i.op[op].disps->X_op == O_constant)
4858 offsetT op_disp = i.op[op].disps->X_add_number;
4860 if (i.types[op].bitfield.disp16
4861 && (op_disp & ~(offsetT) 0xffff) == 0)
4863 /* If this operand is at most 16 bits, convert
4864 to a signed 16 bit number and don't use 64bit
4866 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4867 i.types[op].bitfield.disp64 = 0;
4870 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4871 if (i.types[op].bitfield.disp32
4872 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4874 /* If this operand is at most 32 bits, convert
4875 to a signed 32 bit number and don't use 64bit
4877 op_disp &= (((offsetT) 2 << 31) - 1);
4878 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4879 i.types[op].bitfield.disp64 = 0;
4882 if (!op_disp && i.types[op].bitfield.baseindex)
4884 i.types[op].bitfield.disp8 = 0;
4885 i.types[op].bitfield.disp16 = 0;
4886 i.types[op].bitfield.disp32 = 0;
4887 i.types[op].bitfield.disp32s = 0;
4888 i.types[op].bitfield.disp64 = 0;
4892 else if (flag_code == CODE_64BIT)
4894 if (fits_in_signed_long (op_disp))
4896 i.types[op].bitfield.disp64 = 0;
4897 i.types[op].bitfield.disp32s = 1;
4899 if (i.prefix[ADDR_PREFIX]
4900 && fits_in_unsigned_long (op_disp))
4901 i.types[op].bitfield.disp32 = 1;
4903 if ((i.types[op].bitfield.disp32
4904 || i.types[op].bitfield.disp32s
4905 || i.types[op].bitfield.disp16)
4906 && fits_in_disp8 (op_disp))
4907 i.types[op].bitfield.disp8 = 1;
4909 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4910 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4912 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4913 i.op[op].disps, 0, i.reloc[op]);
4914 i.types[op].bitfield.disp8 = 0;
4915 i.types[op].bitfield.disp16 = 0;
4916 i.types[op].bitfield.disp32 = 0;
4917 i.types[op].bitfield.disp32s = 0;
4918 i.types[op].bitfield.disp64 = 0;
4921 /* We only support 64bit displacement on constants. */
4922 i.types[op].bitfield.disp64 = 0;
4926 /* Check if operands are valid for the instruction. */
4929 check_VecOperands (const insn_template *t)
4933 /* Without VSIB byte, we can't have a vector register for index. */
4934 if (!t->opcode_modifier.vecsib
4936 && (i.index_reg->reg_type.bitfield.xmmword
4937 || i.index_reg->reg_type.bitfield.ymmword
4938 || i.index_reg->reg_type.bitfield.zmmword))
4940 i.error = unsupported_vector_index_register;
4944 /* Check if default mask is allowed. */
4945 if (t->opcode_modifier.nodefmask
4946 && (!i.mask || i.mask->mask->reg_num == 0))
4948 i.error = no_default_mask;
4952 /* For VSIB byte, we need a vector register for index, and all vector
4953 registers must be distinct. */
4954 if (t->opcode_modifier.vecsib)
4957 || !((t->opcode_modifier.vecsib == VecSIB128
4958 && i.index_reg->reg_type.bitfield.xmmword)
4959 || (t->opcode_modifier.vecsib == VecSIB256
4960 && i.index_reg->reg_type.bitfield.ymmword)
4961 || (t->opcode_modifier.vecsib == VecSIB512
4962 && i.index_reg->reg_type.bitfield.zmmword)))
4964 i.error = invalid_vsib_address;
4968 gas_assert (i.reg_operands == 2 || i.mask);
4969 if (i.reg_operands == 2 && !i.mask)
4971 gas_assert (i.types[0].bitfield.regsimd);
4972 gas_assert (i.types[0].bitfield.xmmword
4973 || i.types[0].bitfield.ymmword);
4974 gas_assert (i.types[2].bitfield.regsimd);
4975 gas_assert (i.types[2].bitfield.xmmword
4976 || i.types[2].bitfield.ymmword);
4977 if (operand_check == check_none)
4979 if (register_number (i.op[0].regs)
4980 != register_number (i.index_reg)
4981 && register_number (i.op[2].regs)
4982 != register_number (i.index_reg)
4983 && register_number (i.op[0].regs)
4984 != register_number (i.op[2].regs))
4986 if (operand_check == check_error)
4988 i.error = invalid_vector_register_set;
4991 as_warn (_("mask, index, and destination registers should be distinct"));
4993 else if (i.reg_operands == 1 && i.mask)
4995 if (i.types[1].bitfield.regsimd
4996 && (i.types[1].bitfield.xmmword
4997 || i.types[1].bitfield.ymmword
4998 || i.types[1].bitfield.zmmword)
4999 && (register_number (i.op[1].regs)
5000 == register_number (i.index_reg)))
5002 if (operand_check == check_error)
5004 i.error = invalid_vector_register_set;
5007 if (operand_check != check_none)
5008 as_warn (_("index and destination registers should be distinct"));
5013 /* Check if broadcast is supported by the instruction and is applied
5014 to the memory operand. */
5017 int broadcasted_opnd_size;
5019 /* Check if specified broadcast is supported in this instruction,
5020 and it's applied to memory operand of DWORD or QWORD type,
5021 depending on VecESize. */
5022 if (i.broadcast->type != t->opcode_modifier.broadcast
5023 || !i.types[i.broadcast->operand].bitfield.mem
5024 || (t->opcode_modifier.vecesize == 0
5025 && !i.types[i.broadcast->operand].bitfield.dword
5026 && !i.types[i.broadcast->operand].bitfield.unspecified)
5027 || (t->opcode_modifier.vecesize == 1
5028 && !i.types[i.broadcast->operand].bitfield.qword
5029 && !i.types[i.broadcast->operand].bitfield.unspecified))
5032 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5033 if (i.broadcast->type == BROADCAST_1TO16)
5034 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5035 else if (i.broadcast->type == BROADCAST_1TO8)
5036 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5037 else if (i.broadcast->type == BROADCAST_1TO4)
5038 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5039 else if (i.broadcast->type == BROADCAST_1TO2)
5040 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5044 if ((broadcasted_opnd_size == 256
5045 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5046 || (broadcasted_opnd_size == 512
5047 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5050 i.error = unsupported_broadcast;
5054 /* If broadcast is supported in this instruction, we need to check if
5055 operand of one-element size isn't specified without broadcast. */
5056 else if (t->opcode_modifier.broadcast && i.mem_operands)
5058 /* Find memory operand. */
5059 for (op = 0; op < i.operands; op++)
5060 if (operand_type_check (i.types[op], anymem))
5062 gas_assert (op < i.operands);
5063 /* Check size of the memory operand. */
5064 if ((t->opcode_modifier.vecesize == 0
5065 && i.types[op].bitfield.dword)
5066 || (t->opcode_modifier.vecesize == 1
5067 && i.types[op].bitfield.qword))
5069 i.error = broadcast_needed;
5074 /* Check if requested masking is supported. */
5076 && (!t->opcode_modifier.masking
5078 && t->opcode_modifier.masking == MERGING_MASKING)))
5080 i.error = unsupported_masking;
5084 /* Check if masking is applied to dest operand. */
5085 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5087 i.error = mask_not_on_destination;
5094 if ((i.rounding->type != saeonly
5095 && !t->opcode_modifier.staticrounding)
5096 || (i.rounding->type == saeonly
5097 && (t->opcode_modifier.staticrounding
5098 || !t->opcode_modifier.sae)))
5100 i.error = unsupported_rc_sae;
5103 /* If the instruction has several immediate operands and one of
5104 them is rounding, the rounding operand should be the last
5105 immediate operand. */
5106 if (i.imm_operands > 1
5107 && i.rounding->operand != (int) (i.imm_operands - 1))
5109 i.error = rc_sae_operand_not_last_imm;
5114 /* Check vector Disp8 operand. */
5115 if (t->opcode_modifier.disp8memshift
5116 && i.disp_encoding != disp_encoding_32bit)
5119 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5121 i.memshift = t->opcode_modifier.disp8memshift;
5123 for (op = 0; op < i.operands; op++)
5124 if (operand_type_check (i.types[op], disp)
5125 && i.op[op].disps->X_op == O_constant)
5127 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5129 i.types[op].bitfield.disp8 = 1;
5132 i.types[op].bitfield.disp8 = 0;
5141 /* Check if operands are valid for the instruction. Update VEX
5145 VEX_check_operands (const insn_template *t)
5147 if (i.vec_encoding == vex_encoding_evex)
5149 /* This instruction must be encoded with EVEX prefix. */
5150 if (!t->opcode_modifier.evex)
5152 i.error = unsupported;
5158 if (!t->opcode_modifier.vex)
5160 /* This instruction template doesn't have VEX prefix. */
5161 if (i.vec_encoding != vex_encoding_default)
5163 i.error = unsupported;
5169 /* Only check VEX_Imm4, which must be the first operand. */
5170 if (t->operand_types[0].bitfield.vec_imm4)
5172 if (i.op[0].imms->X_op != O_constant
5173 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5179 /* Turn off Imm8 so that update_imm won't complain. */
5180 i.types[0] = vec_imm4;
5186 static const insn_template *
5187 match_template (char mnem_suffix)
5189 /* Points to template once we've found it. */
5190 const insn_template *t;
5191 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5192 i386_operand_type overlap4;
5193 unsigned int found_reverse_match;
5194 i386_opcode_modifier suffix_check, mnemsuf_check;
5195 i386_operand_type operand_types [MAX_OPERANDS];
5196 int addr_prefix_disp;
5198 unsigned int found_cpu_match;
5199 unsigned int check_register;
5200 enum i386_error specific_error = 0;
5202 #if MAX_OPERANDS != 5
5203 # error "MAX_OPERANDS must be 5."
5206 found_reverse_match = 0;
5207 addr_prefix_disp = -1;
5209 memset (&suffix_check, 0, sizeof (suffix_check));
5210 if (i.suffix == BYTE_MNEM_SUFFIX)
5211 suffix_check.no_bsuf = 1;
5212 else if (i.suffix == WORD_MNEM_SUFFIX)
5213 suffix_check.no_wsuf = 1;
5214 else if (i.suffix == SHORT_MNEM_SUFFIX)
5215 suffix_check.no_ssuf = 1;
5216 else if (i.suffix == LONG_MNEM_SUFFIX)
5217 suffix_check.no_lsuf = 1;
5218 else if (i.suffix == QWORD_MNEM_SUFFIX)
5219 suffix_check.no_qsuf = 1;
5220 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5221 suffix_check.no_ldsuf = 1;
5223 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5226 switch (mnem_suffix)
5228 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5229 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5230 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5231 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5232 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5236 /* Must have right number of operands. */
5237 i.error = number_of_operands_mismatch;
5239 for (t = current_templates->start; t < current_templates->end; t++)
5241 addr_prefix_disp = -1;
5243 if (i.operands != t->operands)
5246 /* Check processor support. */
5247 i.error = unsupported;
5248 found_cpu_match = (cpu_flags_match (t)
5249 == CPU_FLAGS_PERFECT_MATCH);
5250 if (!found_cpu_match)
5253 /* Check old gcc support. */
5254 i.error = old_gcc_only;
5255 if (!old_gcc && t->opcode_modifier.oldgcc)
5258 /* Check AT&T mnemonic. */
5259 i.error = unsupported_with_intel_mnemonic;
5260 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5263 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5264 i.error = unsupported_syntax;
5265 if ((intel_syntax && t->opcode_modifier.attsyntax)
5266 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5267 || (intel64 && t->opcode_modifier.amd64)
5268 || (!intel64 && t->opcode_modifier.intel64))
5271 /* Check the suffix, except for some instructions in intel mode. */
5272 i.error = invalid_instruction_suffix;
5273 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5274 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5275 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5276 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5277 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5278 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5279 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5281 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5282 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5283 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5284 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5285 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5286 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5287 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5290 if (!operand_size_match (t))
5293 for (j = 0; j < MAX_OPERANDS; j++)
5294 operand_types[j] = t->operand_types[j];
5296 /* In general, don't allow 64-bit operands in 32-bit mode. */
5297 if (i.suffix == QWORD_MNEM_SUFFIX
5298 && flag_code != CODE_64BIT
5300 ? (!t->opcode_modifier.ignoresize
5301 && !intel_float_operand (t->name))
5302 : intel_float_operand (t->name) != 2)
5303 && ((!operand_types[0].bitfield.regmmx
5304 && !operand_types[0].bitfield.regsimd)
5305 || (!operand_types[t->operands > 1].bitfield.regmmx
5306 && !operand_types[t->operands > 1].bitfield.regsimd))
5307 && (t->base_opcode != 0x0fc7
5308 || t->extension_opcode != 1 /* cmpxchg8b */))
5311 /* In general, don't allow 32-bit operands on pre-386. */
5312 else if (i.suffix == LONG_MNEM_SUFFIX
5313 && !cpu_arch_flags.bitfield.cpui386
5315 ? (!t->opcode_modifier.ignoresize
5316 && !intel_float_operand (t->name))
5317 : intel_float_operand (t->name) != 2)
5318 && ((!operand_types[0].bitfield.regmmx
5319 && !operand_types[0].bitfield.regsimd)
5320 || (!operand_types[t->operands > 1].bitfield.regmmx
5321 && !operand_types[t->operands > 1].bitfield.regsimd)))
5324 /* Do not verify operands when there are none. */
5328 /* We've found a match; break out of loop. */
5332 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5333 into Disp32/Disp16/Disp32 operand. */
5334 if (i.prefix[ADDR_PREFIX] != 0)
5336 /* There should be only one Disp operand. */
5340 for (j = 0; j < MAX_OPERANDS; j++)
5342 if (operand_types[j].bitfield.disp16)
5344 addr_prefix_disp = j;
5345 operand_types[j].bitfield.disp32 = 1;
5346 operand_types[j].bitfield.disp16 = 0;
5352 for (j = 0; j < MAX_OPERANDS; j++)
5354 if (operand_types[j].bitfield.disp32)
5356 addr_prefix_disp = j;
5357 operand_types[j].bitfield.disp32 = 0;
5358 operand_types[j].bitfield.disp16 = 1;
5364 for (j = 0; j < MAX_OPERANDS; j++)
5366 if (operand_types[j].bitfield.disp64)
5368 addr_prefix_disp = j;
5369 operand_types[j].bitfield.disp64 = 0;
5370 operand_types[j].bitfield.disp32 = 1;
5378 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5379 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5382 /* We check register size if needed. */
5383 check_register = t->opcode_modifier.checkregsize;
5384 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5385 switch (t->operands)
5388 if (!operand_type_match (overlap0, i.types[0]))
5392 /* xchg %eax, %eax is a special case. It is an alias for nop
5393 only in 32bit mode and we can use opcode 0x90. In 64bit
5394 mode, we can't use 0x90 for xchg %eax, %eax since it should
5395 zero-extend %eax to %rax. */
5396 if (flag_code == CODE_64BIT
5397 && t->base_opcode == 0x90
5398 && operand_type_equal (&i.types [0], &acc32)
5399 && operand_type_equal (&i.types [1], &acc32))
5401 /* If we want store form, we reverse direction of operands. */
5402 if (i.dir_encoding == dir_encoding_store
5403 && t->opcode_modifier.d)
5408 /* If we want store form, we skip the current load. */
5409 if (i.dir_encoding == dir_encoding_store
5410 && i.mem_operands == 0
5411 && t->opcode_modifier.load)
5416 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5417 if (!operand_type_match (overlap0, i.types[0])
5418 || !operand_type_match (overlap1, i.types[1])
5420 && !operand_type_register_match (i.types[0],
5425 /* Check if other direction is valid ... */
5426 if (!t->opcode_modifier.d)
5430 /* Try reversing direction of operands. */
5431 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5432 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5433 if (!operand_type_match (overlap0, i.types[0])
5434 || !operand_type_match (overlap1, i.types[1])
5436 && !operand_type_register_match (i.types[0],
5441 /* Does not match either direction. */
5444 /* found_reverse_match holds which of D or FloatR
5446 if (!t->opcode_modifier.d)
5447 found_reverse_match = 0;
5448 else if (operand_types[0].bitfield.tbyte)
5449 found_reverse_match = Opcode_FloatD;
5451 found_reverse_match = Opcode_D;
5452 if (t->opcode_modifier.floatr)
5453 found_reverse_match |= Opcode_FloatR;
5457 /* Found a forward 2 operand match here. */
5458 switch (t->operands)
5461 overlap4 = operand_type_and (i.types[4],
5465 overlap3 = operand_type_and (i.types[3],
5469 overlap2 = operand_type_and (i.types[2],
5474 switch (t->operands)
5477 if (!operand_type_match (overlap4, i.types[4])
5478 || !operand_type_register_match (i.types[3],
5485 if (!operand_type_match (overlap3, i.types[3])
5487 && !operand_type_register_match (i.types[2],
5494 /* Here we make use of the fact that there are no
5495 reverse match 3 operand instructions. */
5496 if (!operand_type_match (overlap2, i.types[2])
5498 && (!operand_type_register_match (i.types[0],
5502 || !operand_type_register_match (i.types[1],
5505 operand_types[2]))))
5510 /* Found either forward/reverse 2, 3 or 4 operand match here:
5511 slip through to break. */
5513 if (!found_cpu_match)
5515 found_reverse_match = 0;
5519 /* Check if vector and VEX operands are valid. */
5520 if (check_VecOperands (t) || VEX_check_operands (t))
5522 specific_error = i.error;
5526 /* We've found a match; break out of loop. */
5530 if (t == current_templates->end)
5532 /* We found no match. */
5533 const char *err_msg;
5534 switch (specific_error ? specific_error : i.error)
5538 case operand_size_mismatch:
5539 err_msg = _("operand size mismatch");
5541 case operand_type_mismatch:
5542 err_msg = _("operand type mismatch");
5544 case register_type_mismatch:
5545 err_msg = _("register type mismatch");
5547 case number_of_operands_mismatch:
5548 err_msg = _("number of operands mismatch");
5550 case invalid_instruction_suffix:
5551 err_msg = _("invalid instruction suffix");
5554 err_msg = _("constant doesn't fit in 4 bits");
5557 err_msg = _("only supported with old gcc");
5559 case unsupported_with_intel_mnemonic:
5560 err_msg = _("unsupported with Intel mnemonic");
5562 case unsupported_syntax:
5563 err_msg = _("unsupported syntax");
5566 as_bad (_("unsupported instruction `%s'"),
5567 current_templates->start->name);
5569 case invalid_vsib_address:
5570 err_msg = _("invalid VSIB address");
5572 case invalid_vector_register_set:
5573 err_msg = _("mask, index, and destination registers must be distinct");
5575 case unsupported_vector_index_register:
5576 err_msg = _("unsupported vector index register");
5578 case unsupported_broadcast:
5579 err_msg = _("unsupported broadcast");
5581 case broadcast_not_on_src_operand:
5582 err_msg = _("broadcast not on source memory operand");
5584 case broadcast_needed:
5585 err_msg = _("broadcast is needed for operand of such type");
5587 case unsupported_masking:
5588 err_msg = _("unsupported masking");
5590 case mask_not_on_destination:
5591 err_msg = _("mask not on destination operand");
5593 case no_default_mask:
5594 err_msg = _("default mask isn't allowed");
5596 case unsupported_rc_sae:
5597 err_msg = _("unsupported static rounding/sae");
5599 case rc_sae_operand_not_last_imm:
5601 err_msg = _("RC/SAE operand must precede immediate operands");
5603 err_msg = _("RC/SAE operand must follow immediate operands");
5605 case invalid_register_operand:
5606 err_msg = _("invalid register operand");
5609 as_bad (_("%s for `%s'"), err_msg,
5610 current_templates->start->name);
5614 if (!quiet_warnings)
5617 && (i.types[0].bitfield.jumpabsolute
5618 != operand_types[0].bitfield.jumpabsolute))
5620 as_warn (_("indirect %s without `*'"), t->name);
5623 if (t->opcode_modifier.isprefix
5624 && t->opcode_modifier.ignoresize)
5626 /* Warn them that a data or address size prefix doesn't
5627 affect assembly of the next line of code. */
5628 as_warn (_("stand-alone `%s' prefix"), t->name);
5632 /* Copy the template we found. */
5635 if (addr_prefix_disp != -1)
5636 i.tm.operand_types[addr_prefix_disp]
5637 = operand_types[addr_prefix_disp];
5639 if (found_reverse_match)
5641 /* If we found a reverse match we must alter the opcode
5642 direction bit. found_reverse_match holds bits to change
5643 (different for int & float insns). */
5645 i.tm.base_opcode ^= found_reverse_match;
5647 i.tm.operand_types[0] = operand_types[1];
5648 i.tm.operand_types[1] = operand_types[0];
5657 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5658 if (i.tm.operand_types[mem_op].bitfield.esseg)
5660 if (i.seg[0] != NULL && i.seg[0] != &es)
5662 as_bad (_("`%s' operand %d must use `%ses' segment"),
5668 /* There's only ever one segment override allowed per instruction.
5669 This instruction possibly has a legal segment override on the
5670 second operand, so copy the segment to where non-string
5671 instructions store it, allowing common code. */
5672 i.seg[0] = i.seg[1];
5674 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5676 if (i.seg[1] != NULL && i.seg[1] != &es)
5678 as_bad (_("`%s' operand %d must use `%ses' segment"),
5689 process_suffix (void)
5691 /* If matched instruction specifies an explicit instruction mnemonic
5693 if (i.tm.opcode_modifier.size16)
5694 i.suffix = WORD_MNEM_SUFFIX;
5695 else if (i.tm.opcode_modifier.size32)
5696 i.suffix = LONG_MNEM_SUFFIX;
5697 else if (i.tm.opcode_modifier.size64)
5698 i.suffix = QWORD_MNEM_SUFFIX;
5699 else if (i.reg_operands)
5701 /* If there's no instruction mnemonic suffix we try to invent one
5702 based on register operands. */
5705 /* We take i.suffix from the last register operand specified,
5706 Destination register type is more significant than source
5707 register type. crc32 in SSE4.2 prefers source register
5709 if (i.tm.base_opcode == 0xf20f38f1)
5711 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5712 i.suffix = WORD_MNEM_SUFFIX;
5713 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5714 i.suffix = LONG_MNEM_SUFFIX;
5715 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5716 i.suffix = QWORD_MNEM_SUFFIX;
5718 else if (i.tm.base_opcode == 0xf20f38f0)
5720 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5721 i.suffix = BYTE_MNEM_SUFFIX;
5728 if (i.tm.base_opcode == 0xf20f38f1
5729 || i.tm.base_opcode == 0xf20f38f0)
5731 /* We have to know the operand size for crc32. */
5732 as_bad (_("ambiguous memory operand size for `%s`"),
5737 for (op = i.operands; --op >= 0;)
5738 if (!i.tm.operand_types[op].bitfield.inoutportreg
5739 && !i.tm.operand_types[op].bitfield.shiftcount)
5741 if (!i.types[op].bitfield.reg)
5743 if (i.types[op].bitfield.byte)
5744 i.suffix = BYTE_MNEM_SUFFIX;
5745 else if (i.types[op].bitfield.word)
5746 i.suffix = WORD_MNEM_SUFFIX;
5747 else if (i.types[op].bitfield.dword)
5748 i.suffix = LONG_MNEM_SUFFIX;
5749 else if (i.types[op].bitfield.qword)
5750 i.suffix = QWORD_MNEM_SUFFIX;
5757 else if (i.suffix == BYTE_MNEM_SUFFIX)
5760 && i.tm.opcode_modifier.ignoresize
5761 && i.tm.opcode_modifier.no_bsuf)
5763 else if (!check_byte_reg ())
5766 else if (i.suffix == LONG_MNEM_SUFFIX)
5769 && i.tm.opcode_modifier.ignoresize
5770 && i.tm.opcode_modifier.no_lsuf)
5772 else if (!check_long_reg ())
5775 else if (i.suffix == QWORD_MNEM_SUFFIX)
5778 && i.tm.opcode_modifier.ignoresize
5779 && i.tm.opcode_modifier.no_qsuf)
5781 else if (!check_qword_reg ())
5784 else if (i.suffix == WORD_MNEM_SUFFIX)
5787 && i.tm.opcode_modifier.ignoresize
5788 && i.tm.opcode_modifier.no_wsuf)
5790 else if (!check_word_reg ())
5793 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5794 || i.suffix == YMMWORD_MNEM_SUFFIX
5795 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5797 /* Skip if the instruction has x/y/z suffix. match_template
5798 should check if it is a valid suffix. */
5800 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5801 /* Do nothing if the instruction is going to ignore the prefix. */
5806 else if (i.tm.opcode_modifier.defaultsize
5808 /* exclude fldenv/frstor/fsave/fstenv */
5809 && i.tm.opcode_modifier.no_ssuf)
5811 i.suffix = stackop_size;
5813 else if (intel_syntax
5815 && (i.tm.operand_types[0].bitfield.jumpabsolute
5816 || i.tm.opcode_modifier.jumpbyte
5817 || i.tm.opcode_modifier.jumpintersegment
5818 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5819 && i.tm.extension_opcode <= 3)))
5824 if (!i.tm.opcode_modifier.no_qsuf)
5826 i.suffix = QWORD_MNEM_SUFFIX;
5831 if (!i.tm.opcode_modifier.no_lsuf)
5832 i.suffix = LONG_MNEM_SUFFIX;
5835 if (!i.tm.opcode_modifier.no_wsuf)
5836 i.suffix = WORD_MNEM_SUFFIX;
5845 if (i.tm.opcode_modifier.w)
5847 as_bad (_("no instruction mnemonic suffix given and "
5848 "no register operands; can't size instruction"));
5854 unsigned int suffixes;
5856 suffixes = !i.tm.opcode_modifier.no_bsuf;
5857 if (!i.tm.opcode_modifier.no_wsuf)
5859 if (!i.tm.opcode_modifier.no_lsuf)
5861 if (!i.tm.opcode_modifier.no_ldsuf)
5863 if (!i.tm.opcode_modifier.no_ssuf)
5865 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5868 /* There are more than suffix matches. */
5869 if (i.tm.opcode_modifier.w
5870 || ((suffixes & (suffixes - 1))
5871 && !i.tm.opcode_modifier.defaultsize
5872 && !i.tm.opcode_modifier.ignoresize))
5874 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5880 /* Change the opcode based on the operand size given by i.suffix;
5881 We don't need to change things for byte insns. */
5884 && i.suffix != BYTE_MNEM_SUFFIX
5885 && i.suffix != XMMWORD_MNEM_SUFFIX
5886 && i.suffix != YMMWORD_MNEM_SUFFIX
5887 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5889 /* It's not a byte, select word/dword operation. */
5890 if (i.tm.opcode_modifier.w)
5892 if (i.tm.opcode_modifier.shortform)
5893 i.tm.base_opcode |= 8;
5895 i.tm.base_opcode |= 1;
5898 /* Now select between word & dword operations via the operand
5899 size prefix, except for instructions that will ignore this
5901 if (i.tm.opcode_modifier.addrprefixop0)
5903 /* The address size override prefix changes the size of the
5905 if ((flag_code == CODE_32BIT
5906 && i.op->regs[0].reg_type.bitfield.word)
5907 || (flag_code != CODE_32BIT
5908 && i.op->regs[0].reg_type.bitfield.dword))
5909 if (!add_prefix (ADDR_PREFIX_OPCODE))
5912 else if (i.suffix != QWORD_MNEM_SUFFIX
5913 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5914 && !i.tm.opcode_modifier.ignoresize
5915 && !i.tm.opcode_modifier.floatmf
5916 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5917 || (flag_code == CODE_64BIT
5918 && i.tm.opcode_modifier.jumpbyte)))
5920 unsigned int prefix = DATA_PREFIX_OPCODE;
5922 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5923 prefix = ADDR_PREFIX_OPCODE;
5925 if (!add_prefix (prefix))
5929 /* Set mode64 for an operand. */
5930 if (i.suffix == QWORD_MNEM_SUFFIX
5931 && flag_code == CODE_64BIT
5932 && !i.tm.opcode_modifier.norex64)
5934 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5935 need rex64. cmpxchg8b is also a special case. */
5936 if (! (i.operands == 2
5937 && i.tm.base_opcode == 0x90
5938 && i.tm.extension_opcode == None
5939 && operand_type_equal (&i.types [0], &acc64)
5940 && operand_type_equal (&i.types [1], &acc64))
5941 && ! (i.operands == 1
5942 && i.tm.base_opcode == 0xfc7
5943 && i.tm.extension_opcode == 1
5944 && !operand_type_check (i.types [0], reg)
5945 && operand_type_check (i.types [0], anymem)))
5949 /* Size floating point instruction. */
5950 if (i.suffix == LONG_MNEM_SUFFIX)
5951 if (i.tm.opcode_modifier.floatmf)
5952 i.tm.base_opcode ^= 4;
5959 check_byte_reg (void)
5963 for (op = i.operands; --op >= 0;)
5965 /* Skip non-register operands. */
5966 if (!i.types[op].bitfield.reg)
5969 /* If this is an eight bit register, it's OK. If it's the 16 or
5970 32 bit version of an eight bit register, we will just use the
5971 low portion, and that's OK too. */
5972 if (i.types[op].bitfield.byte)
5975 /* I/O port address operands are OK too. */
5976 if (i.tm.operand_types[op].bitfield.inoutportreg)
5979 /* crc32 doesn't generate this warning. */
5980 if (i.tm.base_opcode == 0xf20f38f0)
5983 if ((i.types[op].bitfield.word
5984 || i.types[op].bitfield.dword
5985 || i.types[op].bitfield.qword)
5986 && i.op[op].regs->reg_num < 4
5987 /* Prohibit these changes in 64bit mode, since the lowering
5988 would be more complicated. */
5989 && flag_code != CODE_64BIT)
5991 #if REGISTER_WARNINGS
5992 if (!quiet_warnings)
5993 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5995 (i.op[op].regs + (i.types[op].bitfield.word
5996 ? REGNAM_AL - REGNAM_AX
5997 : REGNAM_AL - REGNAM_EAX))->reg_name,
5999 i.op[op].regs->reg_name,
6004 /* Any other register is bad. */
6005 if (i.types[op].bitfield.reg
6006 || i.types[op].bitfield.regmmx
6007 || i.types[op].bitfield.regsimd
6008 || i.types[op].bitfield.sreg2
6009 || i.types[op].bitfield.sreg3
6010 || i.types[op].bitfield.control
6011 || i.types[op].bitfield.debug
6012 || i.types[op].bitfield.test)
6014 as_bad (_("`%s%s' not allowed with `%s%c'"),
6016 i.op[op].regs->reg_name,
6026 check_long_reg (void)
6030 for (op = i.operands; --op >= 0;)
6031 /* Skip non-register operands. */
6032 if (!i.types[op].bitfield.reg)
6034 /* Reject eight bit registers, except where the template requires
6035 them. (eg. movzb) */
6036 else if (i.types[op].bitfield.byte
6037 && (i.tm.operand_types[op].bitfield.reg
6038 || i.tm.operand_types[op].bitfield.acc)
6039 && (i.tm.operand_types[op].bitfield.word
6040 || i.tm.operand_types[op].bitfield.dword))
6042 as_bad (_("`%s%s' not allowed with `%s%c'"),
6044 i.op[op].regs->reg_name,
6049 /* Warn if the e prefix on a general reg is missing. */
6050 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6051 && i.types[op].bitfield.word
6052 && (i.tm.operand_types[op].bitfield.reg
6053 || i.tm.operand_types[op].bitfield.acc)
6054 && i.tm.operand_types[op].bitfield.dword)
6056 /* Prohibit these changes in the 64bit mode, since the
6057 lowering is more complicated. */
6058 if (flag_code == CODE_64BIT)
6060 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6061 register_prefix, i.op[op].regs->reg_name,
6065 #if REGISTER_WARNINGS
6066 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6068 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6069 register_prefix, i.op[op].regs->reg_name, i.suffix);
6072 /* Warn if the r prefix on a general reg is present. */
6073 else if (i.types[op].bitfield.qword
6074 && (i.tm.operand_types[op].bitfield.reg
6075 || i.tm.operand_types[op].bitfield.acc)
6076 && i.tm.operand_types[op].bitfield.dword)
6079 && i.tm.opcode_modifier.toqword
6080 && !i.types[0].bitfield.regsimd)
6082 /* Convert to QWORD. We want REX byte. */
6083 i.suffix = QWORD_MNEM_SUFFIX;
6087 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6088 register_prefix, i.op[op].regs->reg_name,
6097 check_qword_reg (void)
6101 for (op = i.operands; --op >= 0; )
6102 /* Skip non-register operands. */
6103 if (!i.types[op].bitfield.reg)
6105 /* Reject eight bit registers, except where the template requires
6106 them. (eg. movzb) */
6107 else if (i.types[op].bitfield.byte
6108 && (i.tm.operand_types[op].bitfield.reg
6109 || i.tm.operand_types[op].bitfield.acc)
6110 && (i.tm.operand_types[op].bitfield.word
6111 || i.tm.operand_types[op].bitfield.dword))
6113 as_bad (_("`%s%s' not allowed with `%s%c'"),
6115 i.op[op].regs->reg_name,
6120 /* Warn if the r prefix on a general reg is missing. */
6121 else if ((i.types[op].bitfield.word
6122 || i.types[op].bitfield.dword)
6123 && (i.tm.operand_types[op].bitfield.reg
6124 || i.tm.operand_types[op].bitfield.acc)
6125 && i.tm.operand_types[op].bitfield.qword)
6127 /* Prohibit these changes in the 64bit mode, since the
6128 lowering is more complicated. */
6130 && i.tm.opcode_modifier.todword
6131 && !i.types[0].bitfield.regsimd)
6133 /* Convert to DWORD. We don't want REX byte. */
6134 i.suffix = LONG_MNEM_SUFFIX;
6138 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6139 register_prefix, i.op[op].regs->reg_name,
6148 check_word_reg (void)
6151 for (op = i.operands; --op >= 0;)
6152 /* Skip non-register operands. */
6153 if (!i.types[op].bitfield.reg)
6155 /* Reject eight bit registers, except where the template requires
6156 them. (eg. movzb) */
6157 else if (i.types[op].bitfield.byte
6158 && (i.tm.operand_types[op].bitfield.reg
6159 || i.tm.operand_types[op].bitfield.acc)
6160 && (i.tm.operand_types[op].bitfield.word
6161 || i.tm.operand_types[op].bitfield.dword))
6163 as_bad (_("`%s%s' not allowed with `%s%c'"),
6165 i.op[op].regs->reg_name,
6170 /* Warn if the e or r prefix on a general reg is present. */
6171 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6172 && (i.types[op].bitfield.dword
6173 || i.types[op].bitfield.qword)
6174 && (i.tm.operand_types[op].bitfield.reg
6175 || i.tm.operand_types[op].bitfield.acc)
6176 && i.tm.operand_types[op].bitfield.word)
6178 /* Prohibit these changes in the 64bit mode, since the
6179 lowering is more complicated. */
6180 if (flag_code == CODE_64BIT)
6182 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6183 register_prefix, i.op[op].regs->reg_name,
6187 #if REGISTER_WARNINGS
6188 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6190 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6191 register_prefix, i.op[op].regs->reg_name, i.suffix);
6198 update_imm (unsigned int j)
6200 i386_operand_type overlap = i.types[j];
6201 if ((overlap.bitfield.imm8
6202 || overlap.bitfield.imm8s
6203 || overlap.bitfield.imm16
6204 || overlap.bitfield.imm32
6205 || overlap.bitfield.imm32s
6206 || overlap.bitfield.imm64)
6207 && !operand_type_equal (&overlap, &imm8)
6208 && !operand_type_equal (&overlap, &imm8s)
6209 && !operand_type_equal (&overlap, &imm16)
6210 && !operand_type_equal (&overlap, &imm32)
6211 && !operand_type_equal (&overlap, &imm32s)
6212 && !operand_type_equal (&overlap, &imm64))
6216 i386_operand_type temp;
6218 operand_type_set (&temp, 0);
6219 if (i.suffix == BYTE_MNEM_SUFFIX)
6221 temp.bitfield.imm8 = overlap.bitfield.imm8;
6222 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6224 else if (i.suffix == WORD_MNEM_SUFFIX)
6225 temp.bitfield.imm16 = overlap.bitfield.imm16;
6226 else if (i.suffix == QWORD_MNEM_SUFFIX)
6228 temp.bitfield.imm64 = overlap.bitfield.imm64;
6229 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6232 temp.bitfield.imm32 = overlap.bitfield.imm32;
6235 else if (operand_type_equal (&overlap, &imm16_32_32s)
6236 || operand_type_equal (&overlap, &imm16_32)
6237 || operand_type_equal (&overlap, &imm16_32s))
6239 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6244 if (!operand_type_equal (&overlap, &imm8)
6245 && !operand_type_equal (&overlap, &imm8s)
6246 && !operand_type_equal (&overlap, &imm16)
6247 && !operand_type_equal (&overlap, &imm32)
6248 && !operand_type_equal (&overlap, &imm32s)
6249 && !operand_type_equal (&overlap, &imm64))
6251 as_bad (_("no instruction mnemonic suffix given; "
6252 "can't determine immediate size"));
6256 i.types[j] = overlap;
6266 /* Update the first 2 immediate operands. */
6267 n = i.operands > 2 ? 2 : i.operands;
6270 for (j = 0; j < n; j++)
6271 if (update_imm (j) == 0)
6274 /* The 3rd operand can't be immediate operand. */
6275 gas_assert (operand_type_check (i.types[2], imm) == 0);
6282 process_operands (void)
6284 /* Default segment register this instruction will use for memory
6285 accesses. 0 means unknown. This is only for optimizing out
6286 unnecessary segment overrides. */
6287 const seg_entry *default_seg = 0;
6289 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6291 unsigned int dupl = i.operands;
6292 unsigned int dest = dupl - 1;
6295 /* The destination must be an xmm register. */
6296 gas_assert (i.reg_operands
6297 && MAX_OPERANDS > dupl
6298 && operand_type_equal (&i.types[dest], ®xmm));
6300 if (i.tm.operand_types[0].bitfield.acc
6301 && i.tm.operand_types[0].bitfield.xmmword)
6303 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6305 /* Keep xmm0 for instructions with VEX prefix and 3
6307 i.tm.operand_types[0].bitfield.acc = 0;
6308 i.tm.operand_types[0].bitfield.regsimd = 1;
6313 /* We remove the first xmm0 and keep the number of
6314 operands unchanged, which in fact duplicates the
6316 for (j = 1; j < i.operands; j++)
6318 i.op[j - 1] = i.op[j];
6319 i.types[j - 1] = i.types[j];
6320 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6324 else if (i.tm.opcode_modifier.implicit1stxmm0)
6326 gas_assert ((MAX_OPERANDS - 1) > dupl
6327 && (i.tm.opcode_modifier.vexsources
6330 /* Add the implicit xmm0 for instructions with VEX prefix
6332 for (j = i.operands; j > 0; j--)
6334 i.op[j] = i.op[j - 1];
6335 i.types[j] = i.types[j - 1];
6336 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6339 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6340 i.types[0] = regxmm;
6341 i.tm.operand_types[0] = regxmm;
6344 i.reg_operands += 2;
6349 i.op[dupl] = i.op[dest];
6350 i.types[dupl] = i.types[dest];
6351 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6360 i.op[dupl] = i.op[dest];
6361 i.types[dupl] = i.types[dest];
6362 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6365 if (i.tm.opcode_modifier.immext)
6368 else if (i.tm.operand_types[0].bitfield.acc
6369 && i.tm.operand_types[0].bitfield.xmmword)
6373 for (j = 1; j < i.operands; j++)
6375 i.op[j - 1] = i.op[j];
6376 i.types[j - 1] = i.types[j];
6378 /* We need to adjust fields in i.tm since they are used by
6379 build_modrm_byte. */
6380 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6387 else if (i.tm.opcode_modifier.implicitquadgroup)
6389 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6391 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6392 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6393 regnum = register_number (i.op[1].regs);
6394 first_reg_in_group = regnum & ~3;
6395 last_reg_in_group = first_reg_in_group + 3;
6396 if (regnum != first_reg_in_group)
6397 as_warn (_("source register `%s%s' implicitly denotes"
6398 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6399 register_prefix, i.op[1].regs->reg_name,
6400 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6401 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6404 else if (i.tm.opcode_modifier.regkludge)
6406 /* The imul $imm, %reg instruction is converted into
6407 imul $imm, %reg, %reg, and the clr %reg instruction
6408 is converted into xor %reg, %reg. */
6410 unsigned int first_reg_op;
6412 if (operand_type_check (i.types[0], reg))
6416 /* Pretend we saw the extra register operand. */
6417 gas_assert (i.reg_operands == 1
6418 && i.op[first_reg_op + 1].regs == 0);
6419 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6420 i.types[first_reg_op + 1] = i.types[first_reg_op];
6425 if (i.tm.opcode_modifier.shortform)
6427 if (i.types[0].bitfield.sreg2
6428 || i.types[0].bitfield.sreg3)
6430 if (i.tm.base_opcode == POP_SEG_SHORT
6431 && i.op[0].regs->reg_num == 1)
6433 as_bad (_("you can't `pop %scs'"), register_prefix);
6436 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6437 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6442 /* The register or float register operand is in operand
6446 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6447 || operand_type_check (i.types[0], reg))
6451 /* Register goes in low 3 bits of opcode. */
6452 i.tm.base_opcode |= i.op[op].regs->reg_num;
6453 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6455 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6457 /* Warn about some common errors, but press on regardless.
6458 The first case can be generated by gcc (<= 2.8.1). */
6459 if (i.operands == 2)
6461 /* Reversed arguments on faddp, fsubp, etc. */
6462 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6463 register_prefix, i.op[!intel_syntax].regs->reg_name,
6464 register_prefix, i.op[intel_syntax].regs->reg_name);
6468 /* Extraneous `l' suffix on fp insn. */
6469 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6470 register_prefix, i.op[0].regs->reg_name);
6475 else if (i.tm.opcode_modifier.modrm)
6477 /* The opcode is completed (modulo i.tm.extension_opcode which
6478 must be put into the modrm byte). Now, we make the modrm and
6479 index base bytes based on all the info we've collected. */
6481 default_seg = build_modrm_byte ();
6483 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6487 else if (i.tm.opcode_modifier.isstring)
6489 /* For the string instructions that allow a segment override
6490 on one of their operands, the default segment is ds. */
6494 if (i.tm.base_opcode == 0x8d /* lea */
6497 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6499 /* If a segment was explicitly specified, and the specified segment
6500 is not the default, use an opcode prefix to select it. If we
6501 never figured out what the default segment is, then default_seg
6502 will be zero at this point, and the specified segment prefix will
6504 if ((i.seg[0]) && (i.seg[0] != default_seg))
6506 if (!add_prefix (i.seg[0]->seg_prefix))
6512 static const seg_entry *
6513 build_modrm_byte (void)
6515 const seg_entry *default_seg = 0;
6516 unsigned int source, dest;
6519 /* The first operand of instructions with VEX prefix and 3 sources
6520 must be VEX_Imm4. */
6521 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6524 unsigned int nds, reg_slot;
6527 if (i.tm.opcode_modifier.veximmext
6528 && i.tm.opcode_modifier.immext)
6530 dest = i.operands - 2;
6531 gas_assert (dest == 3);
6534 dest = i.operands - 1;
6537 /* There are 2 kinds of instructions:
6538 1. 5 operands: 4 register operands or 3 register operands
6539 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6540 VexW0 or VexW1. The destination must be either XMM, YMM or
6542 2. 4 operands: 4 register operands or 3 register operands
6543 plus 1 memory operand, VexXDS, and VexImmExt */
6544 gas_assert ((i.reg_operands == 4
6545 || (i.reg_operands == 3 && i.mem_operands == 1))
6546 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6547 && (i.tm.opcode_modifier.veximmext
6548 || (i.imm_operands == 1
6549 && i.types[0].bitfield.vec_imm4
6550 && (i.tm.opcode_modifier.vexw == VEXW0
6551 || i.tm.opcode_modifier.vexw == VEXW1)
6552 && i.tm.operand_types[dest].bitfield.regsimd)));
6554 if (i.imm_operands == 0)
6556 /* When there is no immediate operand, generate an 8bit
6557 immediate operand to encode the first operand. */
6558 exp = &im_expressions[i.imm_operands++];
6559 i.op[i.operands].imms = exp;
6560 i.types[i.operands] = imm8;
6562 /* If VexW1 is set, the first operand is the source and
6563 the second operand is encoded in the immediate operand. */
6564 if (i.tm.opcode_modifier.vexw == VEXW1)
6575 /* FMA swaps REG and NDS. */
6576 if (i.tm.cpu_flags.bitfield.cpufma)
6584 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6585 exp->X_op = O_constant;
6586 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6587 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6591 unsigned int imm_slot;
6593 if (i.tm.opcode_modifier.vexw == VEXW0)
6595 /* If VexW0 is set, the third operand is the source and
6596 the second operand is encoded in the immediate
6603 /* VexW1 is set, the second operand is the source and
6604 the third operand is encoded in the immediate
6610 if (i.tm.opcode_modifier.immext)
6612 /* When ImmExt is set, the immediate byte is the last
6614 imm_slot = i.operands - 1;
6622 /* Turn on Imm8 so that output_imm will generate it. */
6623 i.types[imm_slot].bitfield.imm8 = 1;
6626 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6627 i.op[imm_slot].imms->X_add_number
6628 |= register_number (i.op[reg_slot].regs) << 4;
6629 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6632 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6633 i.vex.register_specifier = i.op[nds].regs;
6638 /* i.reg_operands MUST be the number of real register operands;
6639 implicit registers do not count. If there are 3 register
6640 operands, it must be a instruction with VexNDS. For a
6641 instruction with VexNDD, the destination register is encoded
6642 in VEX prefix. If there are 4 register operands, it must be
6643 a instruction with VEX prefix and 3 sources. */
6644 if (i.mem_operands == 0
6645 && ((i.reg_operands == 2
6646 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6647 || (i.reg_operands == 3
6648 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6649 || (i.reg_operands == 4 && vex_3_sources)))
6657 /* When there are 3 operands, one of them may be immediate,
6658 which may be the first or the last operand. Otherwise,
6659 the first operand must be shift count register (cl) or it
6660 is an instruction with VexNDS. */
6661 gas_assert (i.imm_operands == 1
6662 || (i.imm_operands == 0
6663 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6664 || i.types[0].bitfield.shiftcount)));
6665 if (operand_type_check (i.types[0], imm)
6666 || i.types[0].bitfield.shiftcount)
6672 /* When there are 4 operands, the first two must be 8bit
6673 immediate operands. The source operand will be the 3rd
6676 For instructions with VexNDS, if the first operand
6677 an imm8, the source operand is the 2nd one. If the last
6678 operand is imm8, the source operand is the first one. */
6679 gas_assert ((i.imm_operands == 2
6680 && i.types[0].bitfield.imm8
6681 && i.types[1].bitfield.imm8)
6682 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6683 && i.imm_operands == 1
6684 && (i.types[0].bitfield.imm8
6685 || i.types[i.operands - 1].bitfield.imm8
6687 if (i.imm_operands == 2)
6691 if (i.types[0].bitfield.imm8)
6698 if (i.tm.opcode_modifier.evex)
6700 /* For EVEX instructions, when there are 5 operands, the
6701 first one must be immediate operand. If the second one
6702 is immediate operand, the source operand is the 3th
6703 one. If the last one is immediate operand, the source
6704 operand is the 2nd one. */
6705 gas_assert (i.imm_operands == 2
6706 && i.tm.opcode_modifier.sae
6707 && operand_type_check (i.types[0], imm));
6708 if (operand_type_check (i.types[1], imm))
6710 else if (operand_type_check (i.types[4], imm))
6724 /* RC/SAE operand could be between DEST and SRC. That happens
6725 when one operand is GPR and the other one is XMM/YMM/ZMM
6727 if (i.rounding && i.rounding->operand == (int) dest)
6730 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6732 /* For instructions with VexNDS, the register-only source
6733 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6734 register. It is encoded in VEX prefix. We need to
6735 clear RegMem bit before calling operand_type_equal. */
6737 i386_operand_type op;
6740 /* Check register-only source operand when two source
6741 operands are swapped. */
6742 if (!i.tm.operand_types[source].bitfield.baseindex
6743 && i.tm.operand_types[dest].bitfield.baseindex)
6751 op = i.tm.operand_types[vvvv];
6752 op.bitfield.regmem = 0;
6753 if ((dest + 1) >= i.operands
6754 || ((!op.bitfield.reg
6755 || (!op.bitfield.dword && !op.bitfield.qword))
6756 && !op.bitfield.regsimd
6757 && !operand_type_equal (&op, ®mask)))
6759 i.vex.register_specifier = i.op[vvvv].regs;
6765 /* One of the register operands will be encoded in the i.tm.reg
6766 field, the other in the combined i.tm.mode and i.tm.regmem
6767 fields. If no form of this instruction supports a memory
6768 destination operand, then we assume the source operand may
6769 sometimes be a memory operand and so we need to store the
6770 destination in the i.rm.reg field. */
6771 if (!i.tm.operand_types[dest].bitfield.regmem
6772 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6774 i.rm.reg = i.op[dest].regs->reg_num;
6775 i.rm.regmem = i.op[source].regs->reg_num;
6776 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6778 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6780 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6782 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6787 i.rm.reg = i.op[source].regs->reg_num;
6788 i.rm.regmem = i.op[dest].regs->reg_num;
6789 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6791 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6793 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6795 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6798 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6800 if (!i.types[0].bitfield.control
6801 && !i.types[1].bitfield.control)
6803 i.rex &= ~(REX_R | REX_B);
6804 add_prefix (LOCK_PREFIX_OPCODE);
6808 { /* If it's not 2 reg operands... */
6813 unsigned int fake_zero_displacement = 0;
6816 for (op = 0; op < i.operands; op++)
6817 if (operand_type_check (i.types[op], anymem))
6819 gas_assert (op < i.operands);
6821 if (i.tm.opcode_modifier.vecsib)
6823 if (i.index_reg->reg_num == RegEiz
6824 || i.index_reg->reg_num == RegRiz)
6827 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6830 i.sib.base = NO_BASE_REGISTER;
6831 i.sib.scale = i.log2_scale_factor;
6832 i.types[op].bitfield.disp8 = 0;
6833 i.types[op].bitfield.disp16 = 0;
6834 i.types[op].bitfield.disp64 = 0;
6835 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6837 /* Must be 32 bit */
6838 i.types[op].bitfield.disp32 = 1;
6839 i.types[op].bitfield.disp32s = 0;
6843 i.types[op].bitfield.disp32 = 0;
6844 i.types[op].bitfield.disp32s = 1;
6847 i.sib.index = i.index_reg->reg_num;
6848 if ((i.index_reg->reg_flags & RegRex) != 0)
6850 if ((i.index_reg->reg_flags & RegVRex) != 0)
6856 if (i.base_reg == 0)
6859 if (!i.disp_operands)
6860 fake_zero_displacement = 1;
6861 if (i.index_reg == 0)
6863 i386_operand_type newdisp;
6865 gas_assert (!i.tm.opcode_modifier.vecsib);
6866 /* Operand is just <disp> */
6867 if (flag_code == CODE_64BIT)
6869 /* 64bit mode overwrites the 32bit absolute
6870 addressing by RIP relative addressing and
6871 absolute addressing is encoded by one of the
6872 redundant SIB forms. */
6873 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6874 i.sib.base = NO_BASE_REGISTER;
6875 i.sib.index = NO_INDEX_REGISTER;
6876 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6878 else if ((flag_code == CODE_16BIT)
6879 ^ (i.prefix[ADDR_PREFIX] != 0))
6881 i.rm.regmem = NO_BASE_REGISTER_16;
6886 i.rm.regmem = NO_BASE_REGISTER;
6889 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6890 i.types[op] = operand_type_or (i.types[op], newdisp);
6892 else if (!i.tm.opcode_modifier.vecsib)
6894 /* !i.base_reg && i.index_reg */
6895 if (i.index_reg->reg_num == RegEiz
6896 || i.index_reg->reg_num == RegRiz)
6897 i.sib.index = NO_INDEX_REGISTER;
6899 i.sib.index = i.index_reg->reg_num;
6900 i.sib.base = NO_BASE_REGISTER;
6901 i.sib.scale = i.log2_scale_factor;
6902 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6903 i.types[op].bitfield.disp8 = 0;
6904 i.types[op].bitfield.disp16 = 0;
6905 i.types[op].bitfield.disp64 = 0;
6906 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6908 /* Must be 32 bit */
6909 i.types[op].bitfield.disp32 = 1;
6910 i.types[op].bitfield.disp32s = 0;
6914 i.types[op].bitfield.disp32 = 0;
6915 i.types[op].bitfield.disp32s = 1;
6917 if ((i.index_reg->reg_flags & RegRex) != 0)
6921 /* RIP addressing for 64bit mode. */
6922 else if (i.base_reg->reg_num == RegRip ||
6923 i.base_reg->reg_num == RegEip)
6925 gas_assert (!i.tm.opcode_modifier.vecsib);
6926 i.rm.regmem = NO_BASE_REGISTER;
6927 i.types[op].bitfield.disp8 = 0;
6928 i.types[op].bitfield.disp16 = 0;
6929 i.types[op].bitfield.disp32 = 0;
6930 i.types[op].bitfield.disp32s = 1;
6931 i.types[op].bitfield.disp64 = 0;
6932 i.flags[op] |= Operand_PCrel;
6933 if (! i.disp_operands)
6934 fake_zero_displacement = 1;
6936 else if (i.base_reg->reg_type.bitfield.word)
6938 gas_assert (!i.tm.opcode_modifier.vecsib);
6939 switch (i.base_reg->reg_num)
6942 if (i.index_reg == 0)
6944 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6945 i.rm.regmem = i.index_reg->reg_num - 6;
6949 if (i.index_reg == 0)
6952 if (operand_type_check (i.types[op], disp) == 0)
6954 /* fake (%bp) into 0(%bp) */
6955 i.types[op].bitfield.disp8 = 1;
6956 fake_zero_displacement = 1;
6959 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6960 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6962 default: /* (%si) -> 4 or (%di) -> 5 */
6963 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6965 i.rm.mode = mode_from_disp_size (i.types[op]);
6967 else /* i.base_reg and 32/64 bit mode */
6969 if (flag_code == CODE_64BIT
6970 && operand_type_check (i.types[op], disp))
6972 i.types[op].bitfield.disp16 = 0;
6973 i.types[op].bitfield.disp64 = 0;
6974 if (i.prefix[ADDR_PREFIX] == 0)
6976 i.types[op].bitfield.disp32 = 0;
6977 i.types[op].bitfield.disp32s = 1;
6981 i.types[op].bitfield.disp32 = 1;
6982 i.types[op].bitfield.disp32s = 0;
6986 if (!i.tm.opcode_modifier.vecsib)
6987 i.rm.regmem = i.base_reg->reg_num;
6988 if ((i.base_reg->reg_flags & RegRex) != 0)
6990 i.sib.base = i.base_reg->reg_num;
6991 /* x86-64 ignores REX prefix bit here to avoid decoder
6993 if (!(i.base_reg->reg_flags & RegRex)
6994 && (i.base_reg->reg_num == EBP_REG_NUM
6995 || i.base_reg->reg_num == ESP_REG_NUM))
6997 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6999 fake_zero_displacement = 1;
7000 i.types[op].bitfield.disp8 = 1;
7002 i.sib.scale = i.log2_scale_factor;
7003 if (i.index_reg == 0)
7005 gas_assert (!i.tm.opcode_modifier.vecsib);
7006 /* <disp>(%esp) becomes two byte modrm with no index
7007 register. We've already stored the code for esp
7008 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7009 Any base register besides %esp will not use the
7010 extra modrm byte. */
7011 i.sib.index = NO_INDEX_REGISTER;
7013 else if (!i.tm.opcode_modifier.vecsib)
7015 if (i.index_reg->reg_num == RegEiz
7016 || i.index_reg->reg_num == RegRiz)
7017 i.sib.index = NO_INDEX_REGISTER;
7019 i.sib.index = i.index_reg->reg_num;
7020 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7021 if ((i.index_reg->reg_flags & RegRex) != 0)
7026 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7027 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7031 if (!fake_zero_displacement
7035 fake_zero_displacement = 1;
7036 if (i.disp_encoding == disp_encoding_8bit)
7037 i.types[op].bitfield.disp8 = 1;
7039 i.types[op].bitfield.disp32 = 1;
7041 i.rm.mode = mode_from_disp_size (i.types[op]);
7045 if (fake_zero_displacement)
7047 /* Fakes a zero displacement assuming that i.types[op]
7048 holds the correct displacement size. */
7051 gas_assert (i.op[op].disps == 0);
7052 exp = &disp_expressions[i.disp_operands++];
7053 i.op[op].disps = exp;
7054 exp->X_op = O_constant;
7055 exp->X_add_number = 0;
7056 exp->X_add_symbol = (symbolS *) 0;
7057 exp->X_op_symbol = (symbolS *) 0;
7065 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7067 if (operand_type_check (i.types[0], imm))
7068 i.vex.register_specifier = NULL;
7071 /* VEX.vvvv encodes one of the sources when the first
7072 operand is not an immediate. */
7073 if (i.tm.opcode_modifier.vexw == VEXW0)
7074 i.vex.register_specifier = i.op[0].regs;
7076 i.vex.register_specifier = i.op[1].regs;
7079 /* Destination is a XMM register encoded in the ModRM.reg
7081 i.rm.reg = i.op[2].regs->reg_num;
7082 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7085 /* ModRM.rm and VEX.B encodes the other source. */
7086 if (!i.mem_operands)
7090 if (i.tm.opcode_modifier.vexw == VEXW0)
7091 i.rm.regmem = i.op[1].regs->reg_num;
7093 i.rm.regmem = i.op[0].regs->reg_num;
7095 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7099 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7101 i.vex.register_specifier = i.op[2].regs;
7102 if (!i.mem_operands)
7105 i.rm.regmem = i.op[1].regs->reg_num;
7106 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7110 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7111 (if any) based on i.tm.extension_opcode. Again, we must be
7112 careful to make sure that segment/control/debug/test/MMX
7113 registers are coded into the i.rm.reg field. */
7114 else if (i.reg_operands)
7117 unsigned int vex_reg = ~0;
7119 for (op = 0; op < i.operands; op++)
7120 if (i.types[op].bitfield.reg
7121 || i.types[op].bitfield.regmmx
7122 || i.types[op].bitfield.regsimd
7123 || i.types[op].bitfield.regbnd
7124 || i.types[op].bitfield.regmask
7125 || i.types[op].bitfield.sreg2
7126 || i.types[op].bitfield.sreg3
7127 || i.types[op].bitfield.control
7128 || i.types[op].bitfield.debug
7129 || i.types[op].bitfield.test)
7134 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7136 /* For instructions with VexNDS, the register-only
7137 source operand is encoded in VEX prefix. */
7138 gas_assert (mem != (unsigned int) ~0);
7143 gas_assert (op < i.operands);
7147 /* Check register-only source operand when two source
7148 operands are swapped. */
7149 if (!i.tm.operand_types[op].bitfield.baseindex
7150 && i.tm.operand_types[op + 1].bitfield.baseindex)
7154 gas_assert (mem == (vex_reg + 1)
7155 && op < i.operands);
7160 gas_assert (vex_reg < i.operands);
7164 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7166 /* For instructions with VexNDD, the register destination
7167 is encoded in VEX prefix. */
7168 if (i.mem_operands == 0)
7170 /* There is no memory operand. */
7171 gas_assert ((op + 2) == i.operands);
7176 /* There are only 2 operands. */
7177 gas_assert (op < 2 && i.operands == 2);
7182 gas_assert (op < i.operands);
7184 if (vex_reg != (unsigned int) ~0)
7186 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7188 if ((!type->bitfield.reg
7189 || (!type->bitfield.dword && !type->bitfield.qword))
7190 && !type->bitfield.regsimd
7191 && !operand_type_equal (type, ®mask))
7194 i.vex.register_specifier = i.op[vex_reg].regs;
7197 /* Don't set OP operand twice. */
7200 /* If there is an extension opcode to put here, the
7201 register number must be put into the regmem field. */
7202 if (i.tm.extension_opcode != None)
7204 i.rm.regmem = i.op[op].regs->reg_num;
7205 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7207 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7212 i.rm.reg = i.op[op].regs->reg_num;
7213 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7215 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7220 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7221 must set it to 3 to indicate this is a register operand
7222 in the regmem field. */
7223 if (!i.mem_operands)
7227 /* Fill in i.rm.reg field with extension opcode (if any). */
7228 if (i.tm.extension_opcode != None)
7229 i.rm.reg = i.tm.extension_opcode;
7235 output_branch (void)
7241 relax_substateT subtype;
7245 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7246 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7249 if (i.prefix[DATA_PREFIX] != 0)
7255 /* Pentium4 branch hints. */
7256 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7257 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7262 if (i.prefix[REX_PREFIX] != 0)
7268 /* BND prefixed jump. */
7269 if (i.prefix[BND_PREFIX] != 0)
7271 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7275 if (i.prefixes != 0 && !intel_syntax)
7276 as_warn (_("skipping prefixes on this instruction"));
7278 /* It's always a symbol; End frag & setup for relax.
7279 Make sure there is enough room in this frag for the largest
7280 instruction we may generate in md_convert_frag. This is 2
7281 bytes for the opcode and room for the prefix and largest
7283 frag_grow (prefix + 2 + 4);
7284 /* Prefix and 1 opcode byte go in fr_fix. */
7285 p = frag_more (prefix + 1);
7286 if (i.prefix[DATA_PREFIX] != 0)
7287 *p++ = DATA_PREFIX_OPCODE;
7288 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7289 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7290 *p++ = i.prefix[SEG_PREFIX];
7291 if (i.prefix[REX_PREFIX] != 0)
7292 *p++ = i.prefix[REX_PREFIX];
7293 *p = i.tm.base_opcode;
7295 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7296 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7297 else if (cpu_arch_flags.bitfield.cpui386)
7298 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7300 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7303 sym = i.op[0].disps->X_add_symbol;
7304 off = i.op[0].disps->X_add_number;
7306 if (i.op[0].disps->X_op != O_constant
7307 && i.op[0].disps->X_op != O_symbol)
7309 /* Handle complex expressions. */
7310 sym = make_expr_symbol (i.op[0].disps);
7314 /* 1 possible extra opcode + 4 byte displacement go in var part.
7315 Pass reloc in fr_var. */
7316 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7320 /* Return TRUE iff PLT32 relocation should be used for branching to
7324 need_plt32_p (symbolS *s)
7326 /* PLT32 relocation is ELF only. */
7330 /* Since there is no need to prepare for PLT branch on x86-64, we
7331 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7332 be used as a marker for 32-bit PC-relative branches. */
7336 /* Weak or undefined symbol need PLT32 relocation. */
7337 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7340 /* Non-global symbol doesn't need PLT32 relocation. */
7341 if (! S_IS_EXTERNAL (s))
7344 /* Other global symbols need PLT32 relocation. NB: Symbol with
7345 non-default visibilities are treated as normal global symbol
7346 so that PLT32 relocation can be used as a marker for 32-bit
7347 PC-relative branches. It is useful for linker relaxation. */
7358 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7360 if (i.tm.opcode_modifier.jumpbyte)
7362 /* This is a loop or jecxz type instruction. */
7364 if (i.prefix[ADDR_PREFIX] != 0)
7366 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7369 /* Pentium4 branch hints. */
7370 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7371 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7373 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7382 if (flag_code == CODE_16BIT)
7385 if (i.prefix[DATA_PREFIX] != 0)
7387 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7397 if (i.prefix[REX_PREFIX] != 0)
7399 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7403 /* BND prefixed jump. */
7404 if (i.prefix[BND_PREFIX] != 0)
7406 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7410 if (i.prefixes != 0 && !intel_syntax)
7411 as_warn (_("skipping prefixes on this instruction"));
7413 p = frag_more (i.tm.opcode_length + size);
7414 switch (i.tm.opcode_length)
7417 *p++ = i.tm.base_opcode >> 8;
7420 *p++ = i.tm.base_opcode;
7426 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7428 && jump_reloc == NO_RELOC
7429 && need_plt32_p (i.op[0].disps->X_add_symbol))
7430 jump_reloc = BFD_RELOC_X86_64_PLT32;
7433 jump_reloc = reloc (size, 1, 1, jump_reloc);
7435 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7436 i.op[0].disps, 1, jump_reloc);
7438 /* All jumps handled here are signed, but don't use a signed limit
7439 check for 32 and 16 bit jumps as we want to allow wrap around at
7440 4G and 64k respectively. */
7442 fixP->fx_signed = 1;
7446 output_interseg_jump (void)
7454 if (flag_code == CODE_16BIT)
7458 if (i.prefix[DATA_PREFIX] != 0)
7464 if (i.prefix[REX_PREFIX] != 0)
7474 if (i.prefixes != 0 && !intel_syntax)
7475 as_warn (_("skipping prefixes on this instruction"));
7477 /* 1 opcode; 2 segment; offset */
7478 p = frag_more (prefix + 1 + 2 + size);
7480 if (i.prefix[DATA_PREFIX] != 0)
7481 *p++ = DATA_PREFIX_OPCODE;
7483 if (i.prefix[REX_PREFIX] != 0)
7484 *p++ = i.prefix[REX_PREFIX];
7486 *p++ = i.tm.base_opcode;
7487 if (i.op[1].imms->X_op == O_constant)
7489 offsetT n = i.op[1].imms->X_add_number;
7492 && !fits_in_unsigned_word (n)
7493 && !fits_in_signed_word (n))
7495 as_bad (_("16-bit jump out of range"));
7498 md_number_to_chars (p, n, size);
7501 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7502 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7503 if (i.op[0].imms->X_op != O_constant)
7504 as_bad (_("can't handle non absolute segment in `%s'"),
7506 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7512 fragS *insn_start_frag;
7513 offsetT insn_start_off;
7515 /* Tie dwarf2 debug info to the address at the start of the insn.
7516 We can't do this after the insn has been output as the current
7517 frag may have been closed off. eg. by frag_var. */
7518 dwarf2_emit_insn (0);
7520 insn_start_frag = frag_now;
7521 insn_start_off = frag_now_fix ();
7524 if (i.tm.opcode_modifier.jump)
7526 else if (i.tm.opcode_modifier.jumpbyte
7527 || i.tm.opcode_modifier.jumpdword)
7529 else if (i.tm.opcode_modifier.jumpintersegment)
7530 output_interseg_jump ();
7533 /* Output normal instructions here. */
7537 unsigned int prefix;
7540 && i.tm.base_opcode == 0xfae
7542 && i.imm_operands == 1
7543 && (i.op[0].imms->X_add_number == 0xe8
7544 || i.op[0].imms->X_add_number == 0xf0
7545 || i.op[0].imms->X_add_number == 0xf8))
7547 /* Encode lfence, mfence, and sfence as
7548 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7549 offsetT val = 0x240483f0ULL;
7551 md_number_to_chars (p, val, 5);
7555 /* Some processors fail on LOCK prefix. This options makes
7556 assembler ignore LOCK prefix and serves as a workaround. */
7557 if (omit_lock_prefix)
7559 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7561 i.prefix[LOCK_PREFIX] = 0;
7564 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7565 don't need the explicit prefix. */
7566 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7568 switch (i.tm.opcode_length)
7571 if (i.tm.base_opcode & 0xff000000)
7573 prefix = (i.tm.base_opcode >> 24) & 0xff;
7578 if ((i.tm.base_opcode & 0xff0000) != 0)
7580 prefix = (i.tm.base_opcode >> 16) & 0xff;
7581 if (i.tm.cpu_flags.bitfield.cpupadlock)
7584 if (prefix != REPE_PREFIX_OPCODE
7585 || (i.prefix[REP_PREFIX]
7586 != REPE_PREFIX_OPCODE))
7587 add_prefix (prefix);
7590 add_prefix (prefix);
7596 /* Check for pseudo prefixes. */
7597 as_bad_where (insn_start_frag->fr_file,
7598 insn_start_frag->fr_line,
7599 _("pseudo prefix without instruction"));
7605 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7606 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7607 R_X86_64_GOTTPOFF relocation so that linker can safely
7608 perform IE->LE optimization. */
7609 if (x86_elf_abi == X86_64_X32_ABI
7611 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7612 && i.prefix[REX_PREFIX] == 0)
7613 add_prefix (REX_OPCODE);
7616 /* The prefix bytes. */
7617 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7619 FRAG_APPEND_1_CHAR (*q);
7623 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7628 /* REX byte is encoded in VEX prefix. */
7632 FRAG_APPEND_1_CHAR (*q);
7635 /* There should be no other prefixes for instructions
7640 /* For EVEX instructions i.vrex should become 0 after
7641 build_evex_prefix. For VEX instructions upper 16 registers
7642 aren't available, so VREX should be 0. */
7645 /* Now the VEX prefix. */
7646 p = frag_more (i.vex.length);
7647 for (j = 0; j < i.vex.length; j++)
7648 p[j] = i.vex.bytes[j];
7651 /* Now the opcode; be careful about word order here! */
7652 if (i.tm.opcode_length == 1)
7654 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7658 switch (i.tm.opcode_length)
7662 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7663 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7667 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7677 /* Put out high byte first: can't use md_number_to_chars! */
7678 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7679 *p = i.tm.base_opcode & 0xff;
7682 /* Now the modrm byte and sib byte (if present). */
7683 if (i.tm.opcode_modifier.modrm)
7685 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7688 /* If i.rm.regmem == ESP (4)
7689 && i.rm.mode != (Register mode)
7691 ==> need second modrm byte. */
7692 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7694 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7695 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7697 | i.sib.scale << 6));
7700 if (i.disp_operands)
7701 output_disp (insn_start_frag, insn_start_off);
7704 output_imm (insn_start_frag, insn_start_off);
7710 pi ("" /*line*/, &i);
7712 #endif /* DEBUG386 */
7715 /* Return the size of the displacement operand N. */
7718 disp_size (unsigned int n)
7722 if (i.types[n].bitfield.disp64)
7724 else if (i.types[n].bitfield.disp8)
7726 else if (i.types[n].bitfield.disp16)
7731 /* Return the size of the immediate operand N. */
7734 imm_size (unsigned int n)
7737 if (i.types[n].bitfield.imm64)
7739 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7741 else if (i.types[n].bitfield.imm16)
7747 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7752 for (n = 0; n < i.operands; n++)
7754 if (operand_type_check (i.types[n], disp))
7756 if (i.op[n].disps->X_op == O_constant)
7758 int size = disp_size (n);
7759 offsetT val = i.op[n].disps->X_add_number;
7761 val = offset_in_range (val >> i.memshift, size);
7762 p = frag_more (size);
7763 md_number_to_chars (p, val, size);
7767 enum bfd_reloc_code_real reloc_type;
7768 int size = disp_size (n);
7769 int sign = i.types[n].bitfield.disp32s;
7770 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7773 /* We can't have 8 bit displacement here. */
7774 gas_assert (!i.types[n].bitfield.disp8);
7776 /* The PC relative address is computed relative
7777 to the instruction boundary, so in case immediate
7778 fields follows, we need to adjust the value. */
7779 if (pcrel && i.imm_operands)
7784 for (n1 = 0; n1 < i.operands; n1++)
7785 if (operand_type_check (i.types[n1], imm))
7787 /* Only one immediate is allowed for PC
7788 relative address. */
7789 gas_assert (sz == 0);
7791 i.op[n].disps->X_add_number -= sz;
7793 /* We should find the immediate. */
7794 gas_assert (sz != 0);
7797 p = frag_more (size);
7798 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7800 && GOT_symbol == i.op[n].disps->X_add_symbol
7801 && (((reloc_type == BFD_RELOC_32
7802 || reloc_type == BFD_RELOC_X86_64_32S
7803 || (reloc_type == BFD_RELOC_64
7805 && (i.op[n].disps->X_op == O_symbol
7806 || (i.op[n].disps->X_op == O_add
7807 && ((symbol_get_value_expression
7808 (i.op[n].disps->X_op_symbol)->X_op)
7810 || reloc_type == BFD_RELOC_32_PCREL))
7814 if (insn_start_frag == frag_now)
7815 add = (p - frag_now->fr_literal) - insn_start_off;
7820 add = insn_start_frag->fr_fix - insn_start_off;
7821 for (fr = insn_start_frag->fr_next;
7822 fr && fr != frag_now; fr = fr->fr_next)
7824 add += p - frag_now->fr_literal;
7829 reloc_type = BFD_RELOC_386_GOTPC;
7830 i.op[n].imms->X_add_number += add;
7832 else if (reloc_type == BFD_RELOC_64)
7833 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7835 /* Don't do the adjustment for x86-64, as there
7836 the pcrel addressing is relative to the _next_
7837 insn, and that is taken care of in other code. */
7838 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7840 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7841 size, i.op[n].disps, pcrel,
7843 /* Check for "call/jmp *mem", "mov mem, %reg",
7844 "test %reg, mem" and "binop mem, %reg" where binop
7845 is one of adc, add, and, cmp, or, sbb, sub, xor
7846 instructions. Always generate R_386_GOT32X for
7847 "sym*GOT" operand in 32-bit mode. */
7848 if ((generate_relax_relocations
7851 && i.rm.regmem == 5))
7853 || (i.rm.mode == 0 && i.rm.regmem == 5))
7854 && ((i.operands == 1
7855 && i.tm.base_opcode == 0xff
7856 && (i.rm.reg == 2 || i.rm.reg == 4))
7858 && (i.tm.base_opcode == 0x8b
7859 || i.tm.base_opcode == 0x85
7860 || (i.tm.base_opcode & 0xc7) == 0x03))))
7864 fixP->fx_tcbit = i.rex != 0;
7866 && (i.base_reg->reg_num == RegRip
7867 || i.base_reg->reg_num == RegEip))
7868 fixP->fx_tcbit2 = 1;
7871 fixP->fx_tcbit2 = 1;
7879 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7884 for (n = 0; n < i.operands; n++)
7886 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7887 if (i.rounding && (int) n == i.rounding->operand)
7890 if (operand_type_check (i.types[n], imm))
7892 if (i.op[n].imms->X_op == O_constant)
7894 int size = imm_size (n);
7897 val = offset_in_range (i.op[n].imms->X_add_number,
7899 p = frag_more (size);
7900 md_number_to_chars (p, val, size);
7904 /* Not absolute_section.
7905 Need a 32-bit fixup (don't support 8bit
7906 non-absolute imms). Try to support other
7908 enum bfd_reloc_code_real reloc_type;
7909 int size = imm_size (n);
7912 if (i.types[n].bitfield.imm32s
7913 && (i.suffix == QWORD_MNEM_SUFFIX
7914 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7919 p = frag_more (size);
7920 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7922 /* This is tough to explain. We end up with this one if we
7923 * have operands that look like
7924 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7925 * obtain the absolute address of the GOT, and it is strongly
7926 * preferable from a performance point of view to avoid using
7927 * a runtime relocation for this. The actual sequence of
7928 * instructions often look something like:
7933 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7935 * The call and pop essentially return the absolute address
7936 * of the label .L66 and store it in %ebx. The linker itself
7937 * will ultimately change the first operand of the addl so
7938 * that %ebx points to the GOT, but to keep things simple, the
7939 * .o file must have this operand set so that it generates not
7940 * the absolute address of .L66, but the absolute address of
7941 * itself. This allows the linker itself simply treat a GOTPC
7942 * relocation as asking for a pcrel offset to the GOT to be
7943 * added in, and the addend of the relocation is stored in the
7944 * operand field for the instruction itself.
7946 * Our job here is to fix the operand so that it would add
7947 * the correct offset so that %ebx would point to itself. The
7948 * thing that is tricky is that .-.L66 will point to the
7949 * beginning of the instruction, so we need to further modify
7950 * the operand so that it will point to itself. There are
7951 * other cases where you have something like:
7953 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7955 * and here no correction would be required. Internally in
7956 * the assembler we treat operands of this form as not being
7957 * pcrel since the '.' is explicitly mentioned, and I wonder
7958 * whether it would simplify matters to do it this way. Who
7959 * knows. In earlier versions of the PIC patches, the
7960 * pcrel_adjust field was used to store the correction, but
7961 * since the expression is not pcrel, I felt it would be
7962 * confusing to do it this way. */
7964 if ((reloc_type == BFD_RELOC_32
7965 || reloc_type == BFD_RELOC_X86_64_32S
7966 || reloc_type == BFD_RELOC_64)
7968 && GOT_symbol == i.op[n].imms->X_add_symbol
7969 && (i.op[n].imms->X_op == O_symbol
7970 || (i.op[n].imms->X_op == O_add
7971 && ((symbol_get_value_expression
7972 (i.op[n].imms->X_op_symbol)->X_op)
7977 if (insn_start_frag == frag_now)
7978 add = (p - frag_now->fr_literal) - insn_start_off;
7983 add = insn_start_frag->fr_fix - insn_start_off;
7984 for (fr = insn_start_frag->fr_next;
7985 fr && fr != frag_now; fr = fr->fr_next)
7987 add += p - frag_now->fr_literal;
7991 reloc_type = BFD_RELOC_386_GOTPC;
7993 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7995 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7996 i.op[n].imms->X_add_number += add;
7998 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7999 i.op[n].imms, 0, reloc_type);
8005 /* x86_cons_fix_new is called via the expression parsing code when a
8006 reloc is needed. We use this hook to get the correct .got reloc. */
8007 static int cons_sign = -1;
8010 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8011 expressionS *exp, bfd_reloc_code_real_type r)
8013 r = reloc (len, 0, cons_sign, r);
8016 if (exp->X_op == O_secrel)
8018 exp->X_op = O_symbol;
8019 r = BFD_RELOC_32_SECREL;
8023 fix_new_exp (frag, off, len, exp, 0, r);
8026 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8027 purpose of the `.dc.a' internal pseudo-op. */
8030 x86_address_bytes (void)
8032 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8034 return stdoutput->arch_info->bits_per_address / 8;
8037 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8039 # define lex_got(reloc, adjust, types) NULL
8041 /* Parse operands of the form
8042 <symbol>@GOTOFF+<nnn>
8043 and similar .plt or .got references.
8045 If we find one, set up the correct relocation in RELOC and copy the
8046 input string, minus the `@GOTOFF' into a malloc'd buffer for
8047 parsing by the calling routine. Return this buffer, and if ADJUST
8048 is non-null set it to the length of the string we removed from the
8049 input line. Otherwise return NULL. */
8051 lex_got (enum bfd_reloc_code_real *rel,
8053 i386_operand_type *types)
8055 /* Some of the relocations depend on the size of what field is to
8056 be relocated. But in our callers i386_immediate and i386_displacement
8057 we don't yet know the operand size (this will be set by insn
8058 matching). Hence we record the word32 relocation here,
8059 and adjust the reloc according to the real size in reloc(). */
8060 static const struct {
8063 const enum bfd_reloc_code_real rel[2];
8064 const i386_operand_type types64;
8066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8067 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8069 OPERAND_TYPE_IMM32_64 },
8071 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8072 BFD_RELOC_X86_64_PLTOFF64 },
8073 OPERAND_TYPE_IMM64 },
8074 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8075 BFD_RELOC_X86_64_PLT32 },
8076 OPERAND_TYPE_IMM32_32S_DISP32 },
8077 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8078 BFD_RELOC_X86_64_GOTPLT64 },
8079 OPERAND_TYPE_IMM64_DISP64 },
8080 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8081 BFD_RELOC_X86_64_GOTOFF64 },
8082 OPERAND_TYPE_IMM64_DISP64 },
8083 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8084 BFD_RELOC_X86_64_GOTPCREL },
8085 OPERAND_TYPE_IMM32_32S_DISP32 },
8086 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8087 BFD_RELOC_X86_64_TLSGD },
8088 OPERAND_TYPE_IMM32_32S_DISP32 },
8089 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8090 _dummy_first_bfd_reloc_code_real },
8091 OPERAND_TYPE_NONE },
8092 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8093 BFD_RELOC_X86_64_TLSLD },
8094 OPERAND_TYPE_IMM32_32S_DISP32 },
8095 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8096 BFD_RELOC_X86_64_GOTTPOFF },
8097 OPERAND_TYPE_IMM32_32S_DISP32 },
8098 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8099 BFD_RELOC_X86_64_TPOFF32 },
8100 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8101 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8102 _dummy_first_bfd_reloc_code_real },
8103 OPERAND_TYPE_NONE },
8104 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8105 BFD_RELOC_X86_64_DTPOFF32 },
8106 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8107 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8108 _dummy_first_bfd_reloc_code_real },
8109 OPERAND_TYPE_NONE },
8110 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8111 _dummy_first_bfd_reloc_code_real },
8112 OPERAND_TYPE_NONE },
8113 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8114 BFD_RELOC_X86_64_GOT32 },
8115 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8116 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8117 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8118 OPERAND_TYPE_IMM32_32S_DISP32 },
8119 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8120 BFD_RELOC_X86_64_TLSDESC_CALL },
8121 OPERAND_TYPE_IMM32_32S_DISP32 },
8126 #if defined (OBJ_MAYBE_ELF)
8131 for (cp = input_line_pointer; *cp != '@'; cp++)
8132 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8135 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8137 int len = gotrel[j].len;
8138 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8140 if (gotrel[j].rel[object_64bit] != 0)
8143 char *tmpbuf, *past_reloc;
8145 *rel = gotrel[j].rel[object_64bit];
8149 if (flag_code != CODE_64BIT)
8151 types->bitfield.imm32 = 1;
8152 types->bitfield.disp32 = 1;
8155 *types = gotrel[j].types64;
8158 if (j != 0 && GOT_symbol == NULL)
8159 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8161 /* The length of the first part of our input line. */
8162 first = cp - input_line_pointer;
8164 /* The second part goes from after the reloc token until
8165 (and including) an end_of_line char or comma. */
8166 past_reloc = cp + 1 + len;
8168 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8170 second = cp + 1 - past_reloc;
8172 /* Allocate and copy string. The trailing NUL shouldn't
8173 be necessary, but be safe. */
8174 tmpbuf = XNEWVEC (char, first + second + 2);
8175 memcpy (tmpbuf, input_line_pointer, first);
8176 if (second != 0 && *past_reloc != ' ')
8177 /* Replace the relocation token with ' ', so that
8178 errors like foo@GOTOFF1 will be detected. */
8179 tmpbuf[first++] = ' ';
8181 /* Increment length by 1 if the relocation token is
8186 memcpy (tmpbuf + first, past_reloc, second);
8187 tmpbuf[first + second] = '\0';
8191 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8192 gotrel[j].str, 1 << (5 + object_64bit));
8197 /* Might be a symbol version string. Don't as_bad here. */
8206 /* Parse operands of the form
8207 <symbol>@SECREL32+<nnn>
8209 If we find one, set up the correct relocation in RELOC and copy the
8210 input string, minus the `@SECREL32' into a malloc'd buffer for
8211 parsing by the calling routine. Return this buffer, and if ADJUST
8212 is non-null set it to the length of the string we removed from the
8213 input line. Otherwise return NULL.
8215 This function is copied from the ELF version above adjusted for PE targets. */
8218 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8219 int *adjust ATTRIBUTE_UNUSED,
8220 i386_operand_type *types)
8226 const enum bfd_reloc_code_real rel[2];
8227 const i386_operand_type types64;
8231 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8232 BFD_RELOC_32_SECREL },
8233 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8239 for (cp = input_line_pointer; *cp != '@'; cp++)
8240 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8243 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8245 int len = gotrel[j].len;
8247 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8249 if (gotrel[j].rel[object_64bit] != 0)
8252 char *tmpbuf, *past_reloc;
8254 *rel = gotrel[j].rel[object_64bit];
8260 if (flag_code != CODE_64BIT)
8262 types->bitfield.imm32 = 1;
8263 types->bitfield.disp32 = 1;
8266 *types = gotrel[j].types64;
8269 /* The length of the first part of our input line. */
8270 first = cp - input_line_pointer;
8272 /* The second part goes from after the reloc token until
8273 (and including) an end_of_line char or comma. */
8274 past_reloc = cp + 1 + len;
8276 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8278 second = cp + 1 - past_reloc;
8280 /* Allocate and copy string. The trailing NUL shouldn't
8281 be necessary, but be safe. */
8282 tmpbuf = XNEWVEC (char, first + second + 2);
8283 memcpy (tmpbuf, input_line_pointer, first);
8284 if (second != 0 && *past_reloc != ' ')
8285 /* Replace the relocation token with ' ', so that
8286 errors like foo@SECLREL321 will be detected. */
8287 tmpbuf[first++] = ' ';
8288 memcpy (tmpbuf + first, past_reloc, second);
8289 tmpbuf[first + second] = '\0';
8293 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8294 gotrel[j].str, 1 << (5 + object_64bit));
8299 /* Might be a symbol version string. Don't as_bad here. */
8305 bfd_reloc_code_real_type
8306 x86_cons (expressionS *exp, int size)
8308 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8310 intel_syntax = -intel_syntax;
8313 if (size == 4 || (object_64bit && size == 8))
8315 /* Handle @GOTOFF and the like in an expression. */
8317 char *gotfree_input_line;
8320 save = input_line_pointer;
8321 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8322 if (gotfree_input_line)
8323 input_line_pointer = gotfree_input_line;
8327 if (gotfree_input_line)
8329 /* expression () has merrily parsed up to the end of line,
8330 or a comma - in the wrong buffer. Transfer how far
8331 input_line_pointer has moved to the right buffer. */
8332 input_line_pointer = (save
8333 + (input_line_pointer - gotfree_input_line)
8335 free (gotfree_input_line);
8336 if (exp->X_op == O_constant
8337 || exp->X_op == O_absent
8338 || exp->X_op == O_illegal
8339 || exp->X_op == O_register
8340 || exp->X_op == O_big)
8342 char c = *input_line_pointer;
8343 *input_line_pointer = 0;
8344 as_bad (_("missing or invalid expression `%s'"), save);
8345 *input_line_pointer = c;
8352 intel_syntax = -intel_syntax;
8355 i386_intel_simplify (exp);
8361 signed_cons (int size)
8363 if (flag_code == CODE_64BIT)
8371 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8378 if (exp.X_op == O_symbol)
8379 exp.X_op = O_secrel;
8381 emit_expr (&exp, 4);
8383 while (*input_line_pointer++ == ',');
8385 input_line_pointer--;
8386 demand_empty_rest_of_line ();
8390 /* Handle Vector operations. */
8393 check_VecOperations (char *op_string, char *op_end)
8395 const reg_entry *mask;
8400 && (op_end == NULL || op_string < op_end))
8403 if (*op_string == '{')
8407 /* Check broadcasts. */
8408 if (strncmp (op_string, "1to", 3) == 0)
8413 goto duplicated_vec_op;
8416 if (*op_string == '8')
8417 bcst_type = BROADCAST_1TO8;
8418 else if (*op_string == '4')
8419 bcst_type = BROADCAST_1TO4;
8420 else if (*op_string == '2')
8421 bcst_type = BROADCAST_1TO2;
8422 else if (*op_string == '1'
8423 && *(op_string+1) == '6')
8425 bcst_type = BROADCAST_1TO16;
8430 as_bad (_("Unsupported broadcast: `%s'"), saved);
8435 broadcast_op.type = bcst_type;
8436 broadcast_op.operand = this_operand;
8437 i.broadcast = &broadcast_op;
8439 /* Check masking operation. */
8440 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8442 /* k0 can't be used for write mask. */
8443 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8445 as_bad (_("`%s%s' can't be used for write mask"),
8446 register_prefix, mask->reg_name);
8452 mask_op.mask = mask;
8453 mask_op.zeroing = 0;
8454 mask_op.operand = this_operand;
8460 goto duplicated_vec_op;
8462 i.mask->mask = mask;
8464 /* Only "{z}" is allowed here. No need to check
8465 zeroing mask explicitly. */
8466 if (i.mask->operand != this_operand)
8468 as_bad (_("invalid write mask `%s'"), saved);
8475 /* Check zeroing-flag for masking operation. */
8476 else if (*op_string == 'z')
8480 mask_op.mask = NULL;
8481 mask_op.zeroing = 1;
8482 mask_op.operand = this_operand;
8487 if (i.mask->zeroing)
8490 as_bad (_("duplicated `%s'"), saved);
8494 i.mask->zeroing = 1;
8496 /* Only "{%k}" is allowed here. No need to check mask
8497 register explicitly. */
8498 if (i.mask->operand != this_operand)
8500 as_bad (_("invalid zeroing-masking `%s'"),
8509 goto unknown_vec_op;
8511 if (*op_string != '}')
8513 as_bad (_("missing `}' in `%s'"), saved);
8520 /* We don't know this one. */
8521 as_bad (_("unknown vector operation: `%s'"), saved);
8525 if (i.mask && i.mask->zeroing && !i.mask->mask)
8527 as_bad (_("zeroing-masking only allowed with write mask"));
8535 i386_immediate (char *imm_start)
8537 char *save_input_line_pointer;
8538 char *gotfree_input_line;
8541 i386_operand_type types;
8543 operand_type_set (&types, ~0);
8545 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8547 as_bad (_("at most %d immediate operands are allowed"),
8548 MAX_IMMEDIATE_OPERANDS);
8552 exp = &im_expressions[i.imm_operands++];
8553 i.op[this_operand].imms = exp;
8555 if (is_space_char (*imm_start))
8558 save_input_line_pointer = input_line_pointer;
8559 input_line_pointer = imm_start;
8561 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8562 if (gotfree_input_line)
8563 input_line_pointer = gotfree_input_line;
8565 exp_seg = expression (exp);
8569 /* Handle vector operations. */
8570 if (*input_line_pointer == '{')
8572 input_line_pointer = check_VecOperations (input_line_pointer,
8574 if (input_line_pointer == NULL)
8578 if (*input_line_pointer)
8579 as_bad (_("junk `%s' after expression"), input_line_pointer);
8581 input_line_pointer = save_input_line_pointer;
8582 if (gotfree_input_line)
8584 free (gotfree_input_line);
8586 if (exp->X_op == O_constant || exp->X_op == O_register)
8587 exp->X_op = O_illegal;
8590 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8594 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8595 i386_operand_type types, const char *imm_start)
8597 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8600 as_bad (_("missing or invalid immediate expression `%s'"),
8604 else if (exp->X_op == O_constant)
8606 /* Size it properly later. */
8607 i.types[this_operand].bitfield.imm64 = 1;
8608 /* If not 64bit, sign extend val. */
8609 if (flag_code != CODE_64BIT
8610 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8612 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8614 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8615 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8616 && exp_seg != absolute_section
8617 && exp_seg != text_section
8618 && exp_seg != data_section
8619 && exp_seg != bss_section
8620 && exp_seg != undefined_section
8621 && !bfd_is_com_section (exp_seg))
8623 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8627 else if (!intel_syntax && exp_seg == reg_section)
8630 as_bad (_("illegal immediate register operand %s"), imm_start);
8635 /* This is an address. The size of the address will be
8636 determined later, depending on destination register,
8637 suffix, or the default for the section. */
8638 i.types[this_operand].bitfield.imm8 = 1;
8639 i.types[this_operand].bitfield.imm16 = 1;
8640 i.types[this_operand].bitfield.imm32 = 1;
8641 i.types[this_operand].bitfield.imm32s = 1;
8642 i.types[this_operand].bitfield.imm64 = 1;
8643 i.types[this_operand] = operand_type_and (i.types[this_operand],
8651 i386_scale (char *scale)
8654 char *save = input_line_pointer;
8656 input_line_pointer = scale;
8657 val = get_absolute_expression ();
8662 i.log2_scale_factor = 0;
8665 i.log2_scale_factor = 1;
8668 i.log2_scale_factor = 2;
8671 i.log2_scale_factor = 3;
8675 char sep = *input_line_pointer;
8677 *input_line_pointer = '\0';
8678 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8680 *input_line_pointer = sep;
8681 input_line_pointer = save;
8685 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8687 as_warn (_("scale factor of %d without an index register"),
8688 1 << i.log2_scale_factor);
8689 i.log2_scale_factor = 0;
8691 scale = input_line_pointer;
8692 input_line_pointer = save;
8697 i386_displacement (char *disp_start, char *disp_end)
8701 char *save_input_line_pointer;
8702 char *gotfree_input_line;
8704 i386_operand_type bigdisp, types = anydisp;
8707 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8709 as_bad (_("at most %d displacement operands are allowed"),
8710 MAX_MEMORY_OPERANDS);
8714 operand_type_set (&bigdisp, 0);
8715 if ((i.types[this_operand].bitfield.jumpabsolute)
8716 || (!current_templates->start->opcode_modifier.jump
8717 && !current_templates->start->opcode_modifier.jumpdword))
8719 bigdisp.bitfield.disp32 = 1;
8720 override = (i.prefix[ADDR_PREFIX] != 0);
8721 if (flag_code == CODE_64BIT)
8725 bigdisp.bitfield.disp32s = 1;
8726 bigdisp.bitfield.disp64 = 1;
8729 else if ((flag_code == CODE_16BIT) ^ override)
8731 bigdisp.bitfield.disp32 = 0;
8732 bigdisp.bitfield.disp16 = 1;
8737 /* For PC-relative branches, the width of the displacement
8738 is dependent upon data size, not address size. */
8739 override = (i.prefix[DATA_PREFIX] != 0);
8740 if (flag_code == CODE_64BIT)
8742 if (override || i.suffix == WORD_MNEM_SUFFIX)
8743 bigdisp.bitfield.disp16 = 1;
8746 bigdisp.bitfield.disp32 = 1;
8747 bigdisp.bitfield.disp32s = 1;
8753 override = (i.suffix == (flag_code != CODE_16BIT
8755 : LONG_MNEM_SUFFIX));
8756 bigdisp.bitfield.disp32 = 1;
8757 if ((flag_code == CODE_16BIT) ^ override)
8759 bigdisp.bitfield.disp32 = 0;
8760 bigdisp.bitfield.disp16 = 1;
8764 i.types[this_operand] = operand_type_or (i.types[this_operand],
8767 exp = &disp_expressions[i.disp_operands];
8768 i.op[this_operand].disps = exp;
8770 save_input_line_pointer = input_line_pointer;
8771 input_line_pointer = disp_start;
8772 END_STRING_AND_SAVE (disp_end);
8774 #ifndef GCC_ASM_O_HACK
8775 #define GCC_ASM_O_HACK 0
8778 END_STRING_AND_SAVE (disp_end + 1);
8779 if (i.types[this_operand].bitfield.baseIndex
8780 && displacement_string_end[-1] == '+')
8782 /* This hack is to avoid a warning when using the "o"
8783 constraint within gcc asm statements.
8786 #define _set_tssldt_desc(n,addr,limit,type) \
8787 __asm__ __volatile__ ( \
8789 "movw %w1,2+%0\n\t" \
8791 "movb %b1,4+%0\n\t" \
8792 "movb %4,5+%0\n\t" \
8793 "movb $0,6+%0\n\t" \
8794 "movb %h1,7+%0\n\t" \
8796 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8798 This works great except that the output assembler ends
8799 up looking a bit weird if it turns out that there is
8800 no offset. You end up producing code that looks like:
8813 So here we provide the missing zero. */
8815 *displacement_string_end = '0';
8818 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8819 if (gotfree_input_line)
8820 input_line_pointer = gotfree_input_line;
8822 exp_seg = expression (exp);
8825 if (*input_line_pointer)
8826 as_bad (_("junk `%s' after expression"), input_line_pointer);
8828 RESTORE_END_STRING (disp_end + 1);
8830 input_line_pointer = save_input_line_pointer;
8831 if (gotfree_input_line)
8833 free (gotfree_input_line);
8835 if (exp->X_op == O_constant || exp->X_op == O_register)
8836 exp->X_op = O_illegal;
8839 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8841 RESTORE_END_STRING (disp_end);
8847 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8848 i386_operand_type types, const char *disp_start)
8850 i386_operand_type bigdisp;
8853 /* We do this to make sure that the section symbol is in
8854 the symbol table. We will ultimately change the relocation
8855 to be relative to the beginning of the section. */
8856 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8857 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8858 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8860 if (exp->X_op != O_symbol)
8863 if (S_IS_LOCAL (exp->X_add_symbol)
8864 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8865 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8866 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8867 exp->X_op = O_subtract;
8868 exp->X_op_symbol = GOT_symbol;
8869 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8870 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8871 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8872 i.reloc[this_operand] = BFD_RELOC_64;
8874 i.reloc[this_operand] = BFD_RELOC_32;
8877 else if (exp->X_op == O_absent
8878 || exp->X_op == O_illegal
8879 || exp->X_op == O_big)
8882 as_bad (_("missing or invalid displacement expression `%s'"),
8887 else if (flag_code == CODE_64BIT
8888 && !i.prefix[ADDR_PREFIX]
8889 && exp->X_op == O_constant)
8891 /* Since displacement is signed extended to 64bit, don't allow
8892 disp32 and turn off disp32s if they are out of range. */
8893 i.types[this_operand].bitfield.disp32 = 0;
8894 if (!fits_in_signed_long (exp->X_add_number))
8896 i.types[this_operand].bitfield.disp32s = 0;
8897 if (i.types[this_operand].bitfield.baseindex)
8899 as_bad (_("0x%lx out range of signed 32bit displacement"),
8900 (long) exp->X_add_number);
8906 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8907 else if (exp->X_op != O_constant
8908 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8909 && exp_seg != absolute_section
8910 && exp_seg != text_section
8911 && exp_seg != data_section
8912 && exp_seg != bss_section
8913 && exp_seg != undefined_section
8914 && !bfd_is_com_section (exp_seg))
8916 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8921 /* Check if this is a displacement only operand. */
8922 bigdisp = i.types[this_operand];
8923 bigdisp.bitfield.disp8 = 0;
8924 bigdisp.bitfield.disp16 = 0;
8925 bigdisp.bitfield.disp32 = 0;
8926 bigdisp.bitfield.disp32s = 0;
8927 bigdisp.bitfield.disp64 = 0;
8928 if (operand_type_all_zero (&bigdisp))
8929 i.types[this_operand] = operand_type_and (i.types[this_operand],
8935 /* Return the active addressing mode, taking address override and
8936 registers forming the address into consideration. Update the
8937 address override prefix if necessary. */
8939 static enum flag_code
8940 i386_addressing_mode (void)
8942 enum flag_code addr_mode;
8944 if (i.prefix[ADDR_PREFIX])
8945 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8948 addr_mode = flag_code;
8950 #if INFER_ADDR_PREFIX
8951 if (i.mem_operands == 0)
8953 /* Infer address prefix from the first memory operand. */
8954 const reg_entry *addr_reg = i.base_reg;
8956 if (addr_reg == NULL)
8957 addr_reg = i.index_reg;
8961 if (addr_reg->reg_num == RegEip
8962 || addr_reg->reg_num == RegEiz
8963 || addr_reg->reg_type.bitfield.dword)
8964 addr_mode = CODE_32BIT;
8965 else if (flag_code != CODE_64BIT
8966 && addr_reg->reg_type.bitfield.word)
8967 addr_mode = CODE_16BIT;
8969 if (addr_mode != flag_code)
8971 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8973 /* Change the size of any displacement too. At most one
8974 of Disp16 or Disp32 is set.
8975 FIXME. There doesn't seem to be any real need for
8976 separate Disp16 and Disp32 flags. The same goes for
8977 Imm16 and Imm32. Removing them would probably clean
8978 up the code quite a lot. */
8979 if (flag_code != CODE_64BIT
8980 && (i.types[this_operand].bitfield.disp16
8981 || i.types[this_operand].bitfield.disp32))
8982 i.types[this_operand]
8983 = operand_type_xor (i.types[this_operand], disp16_32);
8993 /* Make sure the memory operand we've been dealt is valid.
8994 Return 1 on success, 0 on a failure. */
8997 i386_index_check (const char *operand_string)
8999 const char *kind = "base/index";
9000 enum flag_code addr_mode = i386_addressing_mode ();
9002 if (current_templates->start->opcode_modifier.isstring
9003 && !current_templates->start->opcode_modifier.immext
9004 && (current_templates->end[-1].opcode_modifier.isstring
9007 /* Memory operands of string insns are special in that they only allow
9008 a single register (rDI, rSI, or rBX) as their memory address. */
9009 const reg_entry *expected_reg;
9010 static const char *di_si[][2] =
9016 static const char *bx[] = { "ebx", "bx", "rbx" };
9018 kind = "string address";
9020 if (current_templates->start->opcode_modifier.repprefixok)
9022 i386_operand_type type = current_templates->end[-1].operand_types[0];
9024 if (!type.bitfield.baseindex
9025 || ((!i.mem_operands != !intel_syntax)
9026 && current_templates->end[-1].operand_types[1]
9027 .bitfield.baseindex))
9028 type = current_templates->end[-1].operand_types[1];
9029 expected_reg = hash_find (reg_hash,
9030 di_si[addr_mode][type.bitfield.esseg]);
9034 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9036 if (i.base_reg != expected_reg
9038 || operand_type_check (i.types[this_operand], disp))
9040 /* The second memory operand must have the same size as
9044 && !((addr_mode == CODE_64BIT
9045 && i.base_reg->reg_type.bitfield.qword)
9046 || (addr_mode == CODE_32BIT
9047 ? i.base_reg->reg_type.bitfield.dword
9048 : i.base_reg->reg_type.bitfield.word)))
9051 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9053 intel_syntax ? '[' : '(',
9055 expected_reg->reg_name,
9056 intel_syntax ? ']' : ')');
9063 as_bad (_("`%s' is not a valid %s expression"),
9064 operand_string, kind);
9069 if (addr_mode != CODE_16BIT)
9071 /* 32-bit/64-bit checks. */
9073 && (addr_mode == CODE_64BIT
9074 ? !i.base_reg->reg_type.bitfield.qword
9075 : !i.base_reg->reg_type.bitfield.dword)
9077 || (i.base_reg->reg_num
9078 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9080 && !i.index_reg->reg_type.bitfield.xmmword
9081 && !i.index_reg->reg_type.bitfield.ymmword
9082 && !i.index_reg->reg_type.bitfield.zmmword
9083 && ((addr_mode == CODE_64BIT
9084 ? !(i.index_reg->reg_type.bitfield.qword
9085 || i.index_reg->reg_num == RegRiz)
9086 : !(i.index_reg->reg_type.bitfield.dword
9087 || i.index_reg->reg_num == RegEiz))
9088 || !i.index_reg->reg_type.bitfield.baseindex)))
9091 /* bndmk, bndldx, and bndstx have special restrictions. */
9092 if (current_templates->start->base_opcode == 0xf30f1b
9093 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9095 /* They cannot use RIP-relative addressing. */
9096 if (i.base_reg && i.base_reg->reg_num == RegRip)
9098 as_bad (_("`%s' cannot be used here"), operand_string);
9102 /* bndldx and bndstx ignore their scale factor. */
9103 if (current_templates->start->base_opcode != 0xf30f1b
9104 && i.log2_scale_factor)
9105 as_warn (_("register scaling is being ignored here"));
9110 /* 16-bit checks. */
9112 && (!i.base_reg->reg_type.bitfield.word
9113 || !i.base_reg->reg_type.bitfield.baseindex))
9115 && (!i.index_reg->reg_type.bitfield.word
9116 || !i.index_reg->reg_type.bitfield.baseindex
9118 && i.base_reg->reg_num < 6
9119 && i.index_reg->reg_num >= 6
9120 && i.log2_scale_factor == 0))))
9127 /* Handle vector immediates. */
9130 RC_SAE_immediate (const char *imm_start)
9132 unsigned int match_found, j;
9133 const char *pstr = imm_start;
9141 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9143 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9147 rc_op.type = RC_NamesTable[j].type;
9148 rc_op.operand = this_operand;
9149 i.rounding = &rc_op;
9153 as_bad (_("duplicated `%s'"), imm_start);
9156 pstr += RC_NamesTable[j].len;
9166 as_bad (_("Missing '}': '%s'"), imm_start);
9169 /* RC/SAE immediate string should contain nothing more. */;
9172 as_bad (_("Junk after '}': '%s'"), imm_start);
9176 exp = &im_expressions[i.imm_operands++];
9177 i.op[this_operand].imms = exp;
9179 exp->X_op = O_constant;
9180 exp->X_add_number = 0;
9181 exp->X_add_symbol = (symbolS *) 0;
9182 exp->X_op_symbol = (symbolS *) 0;
9184 i.types[this_operand].bitfield.imm8 = 1;
9188 /* Only string instructions can have a second memory operand, so
9189 reduce current_templates to just those if it contains any. */
9191 maybe_adjust_templates (void)
9193 const insn_template *t;
9195 gas_assert (i.mem_operands == 1);
9197 for (t = current_templates->start; t < current_templates->end; ++t)
9198 if (t->opcode_modifier.isstring)
9201 if (t < current_templates->end)
9203 static templates aux_templates;
9204 bfd_boolean recheck;
9206 aux_templates.start = t;
9207 for (; t < current_templates->end; ++t)
9208 if (!t->opcode_modifier.isstring)
9210 aux_templates.end = t;
9212 /* Determine whether to re-check the first memory operand. */
9213 recheck = (aux_templates.start != current_templates->start
9214 || t != current_templates->end);
9216 current_templates = &aux_templates;
9221 if (i.memop1_string != NULL
9222 && i386_index_check (i.memop1_string) == 0)
9231 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9235 i386_att_operand (char *operand_string)
9239 char *op_string = operand_string;
9241 if (is_space_char (*op_string))
9244 /* We check for an absolute prefix (differentiating,
9245 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9246 if (*op_string == ABSOLUTE_PREFIX)
9249 if (is_space_char (*op_string))
9251 i.types[this_operand].bitfield.jumpabsolute = 1;
9254 /* Check if operand is a register. */
9255 if ((r = parse_register (op_string, &end_op)) != NULL)
9257 i386_operand_type temp;
9259 /* Check for a segment override by searching for ':' after a
9260 segment register. */
9262 if (is_space_char (*op_string))
9264 if (*op_string == ':'
9265 && (r->reg_type.bitfield.sreg2
9266 || r->reg_type.bitfield.sreg3))
9271 i.seg[i.mem_operands] = &es;
9274 i.seg[i.mem_operands] = &cs;
9277 i.seg[i.mem_operands] = &ss;
9280 i.seg[i.mem_operands] = &ds;
9283 i.seg[i.mem_operands] = &fs;
9286 i.seg[i.mem_operands] = &gs;
9290 /* Skip the ':' and whitespace. */
9292 if (is_space_char (*op_string))
9295 if (!is_digit_char (*op_string)
9296 && !is_identifier_char (*op_string)
9297 && *op_string != '('
9298 && *op_string != ABSOLUTE_PREFIX)
9300 as_bad (_("bad memory operand `%s'"), op_string);
9303 /* Handle case of %es:*foo. */
9304 if (*op_string == ABSOLUTE_PREFIX)
9307 if (is_space_char (*op_string))
9309 i.types[this_operand].bitfield.jumpabsolute = 1;
9311 goto do_memory_reference;
9314 /* Handle vector operations. */
9315 if (*op_string == '{')
9317 op_string = check_VecOperations (op_string, NULL);
9318 if (op_string == NULL)
9324 as_bad (_("junk `%s' after register"), op_string);
9328 temp.bitfield.baseindex = 0;
9329 i.types[this_operand] = operand_type_or (i.types[this_operand],
9331 i.types[this_operand].bitfield.unspecified = 0;
9332 i.op[this_operand].regs = r;
9335 else if (*op_string == REGISTER_PREFIX)
9337 as_bad (_("bad register name `%s'"), op_string);
9340 else if (*op_string == IMMEDIATE_PREFIX)
9343 if (i.types[this_operand].bitfield.jumpabsolute)
9345 as_bad (_("immediate operand illegal with absolute jump"));
9348 if (!i386_immediate (op_string))
9351 else if (RC_SAE_immediate (operand_string))
9353 /* If it is a RC or SAE immediate, do nothing. */
9356 else if (is_digit_char (*op_string)
9357 || is_identifier_char (*op_string)
9358 || *op_string == '"'
9359 || *op_string == '(')
9361 /* This is a memory reference of some sort. */
9364 /* Start and end of displacement string expression (if found). */
9365 char *displacement_string_start;
9366 char *displacement_string_end;
9369 do_memory_reference:
9370 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9372 if ((i.mem_operands == 1
9373 && !current_templates->start->opcode_modifier.isstring)
9374 || i.mem_operands == 2)
9376 as_bad (_("too many memory references for `%s'"),
9377 current_templates->start->name);
9381 /* Check for base index form. We detect the base index form by
9382 looking for an ')' at the end of the operand, searching
9383 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9385 base_string = op_string + strlen (op_string);
9387 /* Handle vector operations. */
9388 vop_start = strchr (op_string, '{');
9389 if (vop_start && vop_start < base_string)
9391 if (check_VecOperations (vop_start, base_string) == NULL)
9393 base_string = vop_start;
9397 if (is_space_char (*base_string))
9400 /* If we only have a displacement, set-up for it to be parsed later. */
9401 displacement_string_start = op_string;
9402 displacement_string_end = base_string + 1;
9404 if (*base_string == ')')
9407 unsigned int parens_balanced = 1;
9408 /* We've already checked that the number of left & right ()'s are
9409 equal, so this loop will not be infinite. */
9413 if (*base_string == ')')
9415 if (*base_string == '(')
9418 while (parens_balanced);
9420 temp_string = base_string;
9422 /* Skip past '(' and whitespace. */
9424 if (is_space_char (*base_string))
9427 if (*base_string == ','
9428 || ((i.base_reg = parse_register (base_string, &end_op))
9431 displacement_string_end = temp_string;
9433 i.types[this_operand].bitfield.baseindex = 1;
9437 base_string = end_op;
9438 if (is_space_char (*base_string))
9442 /* There may be an index reg or scale factor here. */
9443 if (*base_string == ',')
9446 if (is_space_char (*base_string))
9449 if ((i.index_reg = parse_register (base_string, &end_op))
9452 base_string = end_op;
9453 if (is_space_char (*base_string))
9455 if (*base_string == ',')
9458 if (is_space_char (*base_string))
9461 else if (*base_string != ')')
9463 as_bad (_("expecting `,' or `)' "
9464 "after index register in `%s'"),
9469 else if (*base_string == REGISTER_PREFIX)
9471 end_op = strchr (base_string, ',');
9474 as_bad (_("bad register name `%s'"), base_string);
9478 /* Check for scale factor. */
9479 if (*base_string != ')')
9481 char *end_scale = i386_scale (base_string);
9486 base_string = end_scale;
9487 if (is_space_char (*base_string))
9489 if (*base_string != ')')
9491 as_bad (_("expecting `)' "
9492 "after scale factor in `%s'"),
9497 else if (!i.index_reg)
9499 as_bad (_("expecting index register or scale factor "
9500 "after `,'; got '%c'"),
9505 else if (*base_string != ')')
9507 as_bad (_("expecting `,' or `)' "
9508 "after base register in `%s'"),
9513 else if (*base_string == REGISTER_PREFIX)
9515 end_op = strchr (base_string, ',');
9518 as_bad (_("bad register name `%s'"), base_string);
9523 /* If there's an expression beginning the operand, parse it,
9524 assuming displacement_string_start and
9525 displacement_string_end are meaningful. */
9526 if (displacement_string_start != displacement_string_end)
9528 if (!i386_displacement (displacement_string_start,
9529 displacement_string_end))
9533 /* Special case for (%dx) while doing input/output op. */
9535 && operand_type_equal (&i.base_reg->reg_type,
9536 ®16_inoutportreg)
9538 && i.log2_scale_factor == 0
9539 && i.seg[i.mem_operands] == 0
9540 && !operand_type_check (i.types[this_operand], disp))
9542 i.types[this_operand] = inoutportreg;
9546 if (i386_index_check (operand_string) == 0)
9548 i.types[this_operand].bitfield.mem = 1;
9549 if (i.mem_operands == 0)
9550 i.memop1_string = xstrdup (operand_string);
9555 /* It's not a memory operand; argh! */
9556 as_bad (_("invalid char %s beginning operand %d `%s'"),
9557 output_invalid (*op_string),
9562 return 1; /* Normal return. */
9565 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9566 that an rs_machine_dependent frag may reach. */
9569 i386_frag_max_var (fragS *frag)
9571 /* The only relaxable frags are for jumps.
9572 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9573 gas_assert (frag->fr_type == rs_machine_dependent);
9574 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9579 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9581 /* STT_GNU_IFUNC symbol must go through PLT. */
9582 if ((symbol_get_bfdsym (fr_symbol)->flags
9583 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9586 if (!S_IS_EXTERNAL (fr_symbol))
9587 /* Symbol may be weak or local. */
9588 return !S_IS_WEAK (fr_symbol);
9590 /* Global symbols with non-default visibility can't be preempted. */
9591 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9594 if (fr_var != NO_RELOC)
9595 switch ((enum bfd_reloc_code_real) fr_var)
9597 case BFD_RELOC_386_PLT32:
9598 case BFD_RELOC_X86_64_PLT32:
9599 /* Symbol with PLT relocation may be preempted. */
9605 /* Global symbols with default visibility in a shared library may be
9606 preempted by another definition. */
9611 /* md_estimate_size_before_relax()
9613 Called just before relax() for rs_machine_dependent frags. The x86
9614 assembler uses these frags to handle variable size jump
9617 Any symbol that is now undefined will not become defined.
9618 Return the correct fr_subtype in the frag.
9619 Return the initial "guess for variable size of frag" to caller.
9620 The guess is actually the growth beyond the fixed part. Whatever
9621 we do to grow the fixed or variable part contributes to our
9625 md_estimate_size_before_relax (fragS *fragP, segT segment)
9627 /* We've already got fragP->fr_subtype right; all we have to do is
9628 check for un-relaxable symbols. On an ELF system, we can't relax
9629 an externally visible symbol, because it may be overridden by a
9631 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9632 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9634 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9637 #if defined (OBJ_COFF) && defined (TE_PE)
9638 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9639 && S_IS_WEAK (fragP->fr_symbol))
9643 /* Symbol is undefined in this segment, or we need to keep a
9644 reloc so that weak symbols can be overridden. */
9645 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9646 enum bfd_reloc_code_real reloc_type;
9647 unsigned char *opcode;
9650 if (fragP->fr_var != NO_RELOC)
9651 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9653 reloc_type = BFD_RELOC_16_PCREL;
9654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9655 else if (need_plt32_p (fragP->fr_symbol))
9656 reloc_type = BFD_RELOC_X86_64_PLT32;
9659 reloc_type = BFD_RELOC_32_PCREL;
9661 old_fr_fix = fragP->fr_fix;
9662 opcode = (unsigned char *) fragP->fr_opcode;
9664 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9667 /* Make jmp (0xeb) a (d)word displacement jump. */
9669 fragP->fr_fix += size;
9670 fix_new (fragP, old_fr_fix, size,
9672 fragP->fr_offset, 1,
9678 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9680 /* Negate the condition, and branch past an
9681 unconditional jump. */
9684 /* Insert an unconditional jump. */
9686 /* We added two extra opcode bytes, and have a two byte
9688 fragP->fr_fix += 2 + 2;
9689 fix_new (fragP, old_fr_fix + 2, 2,
9691 fragP->fr_offset, 1,
9698 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9703 fixP = fix_new (fragP, old_fr_fix, 1,
9705 fragP->fr_offset, 1,
9707 fixP->fx_signed = 1;
9711 /* This changes the byte-displacement jump 0x7N
9712 to the (d)word-displacement jump 0x0f,0x8N. */
9713 opcode[1] = opcode[0] + 0x10;
9714 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9715 /* We've added an opcode byte. */
9716 fragP->fr_fix += 1 + size;
9717 fix_new (fragP, old_fr_fix + 1, size,
9719 fragP->fr_offset, 1,
9724 BAD_CASE (fragP->fr_subtype);
9728 return fragP->fr_fix - old_fr_fix;
9731 /* Guess size depending on current relax state. Initially the relax
9732 state will correspond to a short jump and we return 1, because
9733 the variable part of the frag (the branch offset) is one byte
9734 long. However, we can relax a section more than once and in that
9735 case we must either set fr_subtype back to the unrelaxed state,
9736 or return the value for the appropriate branch. */
9737 return md_relax_table[fragP->fr_subtype].rlx_length;
9740 /* Called after relax() is finished.
9742 In: Address of frag.
9743 fr_type == rs_machine_dependent.
9744 fr_subtype is what the address relaxed to.
9746 Out: Any fixSs and constants are set up.
9747 Caller will turn frag into a ".space 0". */
9750 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9753 unsigned char *opcode;
9754 unsigned char *where_to_put_displacement = NULL;
9755 offsetT target_address;
9756 offsetT opcode_address;
9757 unsigned int extension = 0;
9758 offsetT displacement_from_opcode_start;
9760 opcode = (unsigned char *) fragP->fr_opcode;
9762 /* Address we want to reach in file space. */
9763 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9765 /* Address opcode resides at in file space. */
9766 opcode_address = fragP->fr_address + fragP->fr_fix;
9768 /* Displacement from opcode start to fill into instruction. */
9769 displacement_from_opcode_start = target_address - opcode_address;
9771 if ((fragP->fr_subtype & BIG) == 0)
9773 /* Don't have to change opcode. */
9774 extension = 1; /* 1 opcode + 1 displacement */
9775 where_to_put_displacement = &opcode[1];
9779 if (no_cond_jump_promotion
9780 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9781 as_warn_where (fragP->fr_file, fragP->fr_line,
9782 _("long jump required"));
9784 switch (fragP->fr_subtype)
9786 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9787 extension = 4; /* 1 opcode + 4 displacement */
9789 where_to_put_displacement = &opcode[1];
9792 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9793 extension = 2; /* 1 opcode + 2 displacement */
9795 where_to_put_displacement = &opcode[1];
9798 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9799 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9800 extension = 5; /* 2 opcode + 4 displacement */
9801 opcode[1] = opcode[0] + 0x10;
9802 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9803 where_to_put_displacement = &opcode[2];
9806 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9807 extension = 3; /* 2 opcode + 2 displacement */
9808 opcode[1] = opcode[0] + 0x10;
9809 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9810 where_to_put_displacement = &opcode[2];
9813 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9818 where_to_put_displacement = &opcode[3];
9822 BAD_CASE (fragP->fr_subtype);
9827 /* If size if less then four we are sure that the operand fits,
9828 but if it's 4, then it could be that the displacement is larger
9830 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9832 && ((addressT) (displacement_from_opcode_start - extension
9833 + ((addressT) 1 << 31))
9834 > (((addressT) 2 << 31) - 1)))
9836 as_bad_where (fragP->fr_file, fragP->fr_line,
9837 _("jump target out of range"));
9838 /* Make us emit 0. */
9839 displacement_from_opcode_start = extension;
9841 /* Now put displacement after opcode. */
9842 md_number_to_chars ((char *) where_to_put_displacement,
9843 (valueT) (displacement_from_opcode_start - extension),
9844 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9845 fragP->fr_fix += extension;
9848 /* Apply a fixup (fixP) to segment data, once it has been determined
9849 by our caller that we have all the info we need to fix it up.
9851 Parameter valP is the pointer to the value of the bits.
9853 On the 386, immediates, displacements, and data pointers are all in
9854 the same (little-endian) format, so we don't need to care about which
9858 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9860 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9861 valueT value = *valP;
9863 #if !defined (TE_Mach)
9866 switch (fixP->fx_r_type)
9872 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9875 case BFD_RELOC_X86_64_32S:
9876 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9879 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9882 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9887 if (fixP->fx_addsy != NULL
9888 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9889 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9890 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9891 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9892 && !use_rela_relocations)
9894 /* This is a hack. There should be a better way to handle this.
9895 This covers for the fact that bfd_install_relocation will
9896 subtract the current location (for partial_inplace, PC relative
9897 relocations); see more below. */
9901 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9904 value += fixP->fx_where + fixP->fx_frag->fr_address;
9906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9909 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9912 || (symbol_section_p (fixP->fx_addsy)
9913 && sym_seg != absolute_section))
9914 && !generic_force_reloc (fixP))
9916 /* Yes, we add the values in twice. This is because
9917 bfd_install_relocation subtracts them out again. I think
9918 bfd_install_relocation is broken, but I don't dare change
9920 value += fixP->fx_where + fixP->fx_frag->fr_address;
9924 #if defined (OBJ_COFF) && defined (TE_PE)
9925 /* For some reason, the PE format does not store a
9926 section address offset for a PC relative symbol. */
9927 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9928 || S_IS_WEAK (fixP->fx_addsy))
9929 value += md_pcrel_from (fixP);
9932 #if defined (OBJ_COFF) && defined (TE_PE)
9933 if (fixP->fx_addsy != NULL
9934 && S_IS_WEAK (fixP->fx_addsy)
9935 /* PR 16858: Do not modify weak function references. */
9936 && ! fixP->fx_pcrel)
9938 #if !defined (TE_PEP)
9939 /* For x86 PE weak function symbols are neither PC-relative
9940 nor do they set S_IS_FUNCTION. So the only reliable way
9941 to detect them is to check the flags of their containing
9943 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9944 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9948 value -= S_GET_VALUE (fixP->fx_addsy);
9952 /* Fix a few things - the dynamic linker expects certain values here,
9953 and we must not disappoint it. */
9954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9955 if (IS_ELF && fixP->fx_addsy)
9956 switch (fixP->fx_r_type)
9958 case BFD_RELOC_386_PLT32:
9959 case BFD_RELOC_X86_64_PLT32:
9960 /* Make the jump instruction point to the address of the operand. At
9961 runtime we merely add the offset to the actual PLT entry. */
9965 case BFD_RELOC_386_TLS_GD:
9966 case BFD_RELOC_386_TLS_LDM:
9967 case BFD_RELOC_386_TLS_IE_32:
9968 case BFD_RELOC_386_TLS_IE:
9969 case BFD_RELOC_386_TLS_GOTIE:
9970 case BFD_RELOC_386_TLS_GOTDESC:
9971 case BFD_RELOC_X86_64_TLSGD:
9972 case BFD_RELOC_X86_64_TLSLD:
9973 case BFD_RELOC_X86_64_GOTTPOFF:
9974 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9975 value = 0; /* Fully resolved at runtime. No addend. */
9977 case BFD_RELOC_386_TLS_LE:
9978 case BFD_RELOC_386_TLS_LDO_32:
9979 case BFD_RELOC_386_TLS_LE_32:
9980 case BFD_RELOC_X86_64_DTPOFF32:
9981 case BFD_RELOC_X86_64_DTPOFF64:
9982 case BFD_RELOC_X86_64_TPOFF32:
9983 case BFD_RELOC_X86_64_TPOFF64:
9984 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9987 case BFD_RELOC_386_TLS_DESC_CALL:
9988 case BFD_RELOC_X86_64_TLSDESC_CALL:
9989 value = 0; /* Fully resolved at runtime. No addend. */
9990 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9994 case BFD_RELOC_VTABLE_INHERIT:
9995 case BFD_RELOC_VTABLE_ENTRY:
10002 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10004 #endif /* !defined (TE_Mach) */
10006 /* Are we finished with this relocation now? */
10007 if (fixP->fx_addsy == NULL)
10009 #if defined (OBJ_COFF) && defined (TE_PE)
10010 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10013 /* Remember value for tc_gen_reloc. */
10014 fixP->fx_addnumber = value;
10015 /* Clear out the frag for now. */
10019 else if (use_rela_relocations)
10021 fixP->fx_no_overflow = 1;
10022 /* Remember value for tc_gen_reloc. */
10023 fixP->fx_addnumber = value;
10027 md_number_to_chars (p, value, fixP->fx_size);
10031 md_atof (int type, char *litP, int *sizeP)
10033 /* This outputs the LITTLENUMs in REVERSE order;
10034 in accord with the bigendian 386. */
10035 return ieee_md_atof (type, litP, sizeP, FALSE);
10038 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10041 output_invalid (int c)
10044 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10047 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10048 "(0x%x)", (unsigned char) c);
10049 return output_invalid_buf;
10052 /* REG_STRING starts *before* REGISTER_PREFIX. */
10054 static const reg_entry *
10055 parse_real_register (char *reg_string, char **end_op)
10057 char *s = reg_string;
10059 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10060 const reg_entry *r;
10062 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10063 if (*s == REGISTER_PREFIX)
10066 if (is_space_char (*s))
10069 p = reg_name_given;
10070 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10072 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10073 return (const reg_entry *) NULL;
10077 /* For naked regs, make sure that we are not dealing with an identifier.
10078 This prevents confusing an identifier like `eax_var' with register
10080 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10081 return (const reg_entry *) NULL;
10085 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10087 /* Handle floating point regs, allowing spaces in the (i) part. */
10088 if (r == i386_regtab /* %st is first entry of table */)
10090 if (is_space_char (*s))
10095 if (is_space_char (*s))
10097 if (*s >= '0' && *s <= '7')
10099 int fpr = *s - '0';
10101 if (is_space_char (*s))
10106 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10111 /* We have "%st(" then garbage. */
10112 return (const reg_entry *) NULL;
10116 if (r == NULL || allow_pseudo_reg)
10119 if (operand_type_all_zero (&r->reg_type))
10120 return (const reg_entry *) NULL;
10122 if ((r->reg_type.bitfield.dword
10123 || r->reg_type.bitfield.sreg3
10124 || r->reg_type.bitfield.control
10125 || r->reg_type.bitfield.debug
10126 || r->reg_type.bitfield.test)
10127 && !cpu_arch_flags.bitfield.cpui386)
10128 return (const reg_entry *) NULL;
10130 if (r->reg_type.bitfield.tbyte
10131 && !cpu_arch_flags.bitfield.cpu8087
10132 && !cpu_arch_flags.bitfield.cpu287
10133 && !cpu_arch_flags.bitfield.cpu387)
10134 return (const reg_entry *) NULL;
10136 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10137 return (const reg_entry *) NULL;
10139 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10140 return (const reg_entry *) NULL;
10142 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10143 return (const reg_entry *) NULL;
10145 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10146 return (const reg_entry *) NULL;
10148 if (r->reg_type.bitfield.regmask
10149 && !cpu_arch_flags.bitfield.cpuregmask)
10150 return (const reg_entry *) NULL;
10152 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10153 if (!allow_index_reg
10154 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10155 return (const reg_entry *) NULL;
10157 /* Upper 16 vector register is only available with VREX in 64bit
10159 if ((r->reg_flags & RegVRex))
10161 if (i.vec_encoding == vex_encoding_default)
10162 i.vec_encoding = vex_encoding_evex;
10164 if (!cpu_arch_flags.bitfield.cpuvrex
10165 || i.vec_encoding != vex_encoding_evex
10166 || flag_code != CODE_64BIT)
10167 return (const reg_entry *) NULL;
10170 if (((r->reg_flags & (RegRex64 | RegRex))
10171 || r->reg_type.bitfield.qword)
10172 && (!cpu_arch_flags.bitfield.cpulm
10173 || !operand_type_equal (&r->reg_type, &control))
10174 && flag_code != CODE_64BIT)
10175 return (const reg_entry *) NULL;
10177 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10178 return (const reg_entry *) NULL;
10183 /* REG_STRING starts *before* REGISTER_PREFIX. */
10185 static const reg_entry *
10186 parse_register (char *reg_string, char **end_op)
10188 const reg_entry *r;
10190 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10191 r = parse_real_register (reg_string, end_op);
10196 char *save = input_line_pointer;
10200 input_line_pointer = reg_string;
10201 c = get_symbol_name (®_string);
10202 symbolP = symbol_find (reg_string);
10203 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10205 const expressionS *e = symbol_get_value_expression (symbolP);
10207 know (e->X_op == O_register);
10208 know (e->X_add_number >= 0
10209 && (valueT) e->X_add_number < i386_regtab_size);
10210 r = i386_regtab + e->X_add_number;
10211 if ((r->reg_flags & RegVRex))
10212 i.vec_encoding = vex_encoding_evex;
10213 *end_op = input_line_pointer;
10215 *input_line_pointer = c;
10216 input_line_pointer = save;
10222 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10224 const reg_entry *r;
10225 char *end = input_line_pointer;
10228 r = parse_register (name, &input_line_pointer);
10229 if (r && end <= input_line_pointer)
10231 *nextcharP = *input_line_pointer;
10232 *input_line_pointer = 0;
10233 e->X_op = O_register;
10234 e->X_add_number = r - i386_regtab;
10237 input_line_pointer = end;
10239 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10243 md_operand (expressionS *e)
10246 const reg_entry *r;
10248 switch (*input_line_pointer)
10250 case REGISTER_PREFIX:
10251 r = parse_real_register (input_line_pointer, &end);
10254 e->X_op = O_register;
10255 e->X_add_number = r - i386_regtab;
10256 input_line_pointer = end;
10261 gas_assert (intel_syntax);
10262 end = input_line_pointer++;
10264 if (*input_line_pointer == ']')
10266 ++input_line_pointer;
10267 e->X_op_symbol = make_expr_symbol (e);
10268 e->X_add_symbol = NULL;
10269 e->X_add_number = 0;
10274 e->X_op = O_absent;
10275 input_line_pointer = end;
10282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10283 const char *md_shortopts = "kVQ:sqnO::";
10285 const char *md_shortopts = "qnO::";
10288 #define OPTION_32 (OPTION_MD_BASE + 0)
10289 #define OPTION_64 (OPTION_MD_BASE + 1)
10290 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10291 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10292 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10293 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10294 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10295 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10296 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10297 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10298 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10299 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10300 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10301 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10302 #define OPTION_X32 (OPTION_MD_BASE + 14)
10303 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10304 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10305 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10306 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10307 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10308 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10309 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10310 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10311 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10312 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10313 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10315 struct option md_longopts[] =
10317 {"32", no_argument, NULL, OPTION_32},
10318 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10319 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10320 {"64", no_argument, NULL, OPTION_64},
10322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10323 {"x32", no_argument, NULL, OPTION_X32},
10324 {"mshared", no_argument, NULL, OPTION_MSHARED},
10326 {"divide", no_argument, NULL, OPTION_DIVIDE},
10327 {"march", required_argument, NULL, OPTION_MARCH},
10328 {"mtune", required_argument, NULL, OPTION_MTUNE},
10329 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10330 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10331 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10332 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10333 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10334 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10335 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10336 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10337 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10338 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10339 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10340 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10341 # if defined (TE_PE) || defined (TE_PEP)
10342 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10344 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10345 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10346 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10347 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10348 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10349 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10350 {NULL, no_argument, NULL, 0}
10352 size_t md_longopts_size = sizeof (md_longopts);
10355 md_parse_option (int c, const char *arg)
10358 char *arch, *next, *saved;
10363 optimize_align_code = 0;
10367 quiet_warnings = 1;
10370 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10371 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10372 should be emitted or not. FIXME: Not implemented. */
10376 /* -V: SVR4 argument to print version ID. */
10378 print_version_id ();
10381 /* -k: Ignore for FreeBSD compatibility. */
10386 /* -s: On i386 Solaris, this tells the native assembler to use
10387 .stab instead of .stab.excl. We always use .stab anyhow. */
10390 case OPTION_MSHARED:
10394 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10395 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10398 const char **list, **l;
10400 list = bfd_target_list ();
10401 for (l = list; *l != NULL; l++)
10402 if (CONST_STRNEQ (*l, "elf64-x86-64")
10403 || strcmp (*l, "coff-x86-64") == 0
10404 || strcmp (*l, "pe-x86-64") == 0
10405 || strcmp (*l, "pei-x86-64") == 0
10406 || strcmp (*l, "mach-o-x86-64") == 0)
10408 default_arch = "x86_64";
10412 as_fatal (_("no compiled in support for x86_64"));
10418 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10422 const char **list, **l;
10424 list = bfd_target_list ();
10425 for (l = list; *l != NULL; l++)
10426 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10428 default_arch = "x86_64:32";
10432 as_fatal (_("no compiled in support for 32bit x86_64"));
10436 as_fatal (_("32bit x86_64 is only supported for ELF"));
10441 default_arch = "i386";
10444 case OPTION_DIVIDE:
10445 #ifdef SVR4_COMMENT_CHARS
10450 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10452 for (s = i386_comment_chars; *s != '\0'; s++)
10456 i386_comment_chars = n;
10462 saved = xstrdup (arg);
10464 /* Allow -march=+nosse. */
10470 as_fatal (_("invalid -march= option: `%s'"), arg);
10471 next = strchr (arch, '+');
10474 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10476 if (strcmp (arch, cpu_arch [j].name) == 0)
10479 if (! cpu_arch[j].flags.bitfield.cpui386)
10482 cpu_arch_name = cpu_arch[j].name;
10483 cpu_sub_arch_name = NULL;
10484 cpu_arch_flags = cpu_arch[j].flags;
10485 cpu_arch_isa = cpu_arch[j].type;
10486 cpu_arch_isa_flags = cpu_arch[j].flags;
10487 if (!cpu_arch_tune_set)
10489 cpu_arch_tune = cpu_arch_isa;
10490 cpu_arch_tune_flags = cpu_arch_isa_flags;
10494 else if (*cpu_arch [j].name == '.'
10495 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10497 /* ISA extension. */
10498 i386_cpu_flags flags;
10500 flags = cpu_flags_or (cpu_arch_flags,
10501 cpu_arch[j].flags);
10503 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10505 if (cpu_sub_arch_name)
10507 char *name = cpu_sub_arch_name;
10508 cpu_sub_arch_name = concat (name,
10510 (const char *) NULL);
10514 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10515 cpu_arch_flags = flags;
10516 cpu_arch_isa_flags = flags;
10522 if (j >= ARRAY_SIZE (cpu_arch))
10524 /* Disable an ISA extension. */
10525 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10526 if (strcmp (arch, cpu_noarch [j].name) == 0)
10528 i386_cpu_flags flags;
10530 flags = cpu_flags_and_not (cpu_arch_flags,
10531 cpu_noarch[j].flags);
10532 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10534 if (cpu_sub_arch_name)
10536 char *name = cpu_sub_arch_name;
10537 cpu_sub_arch_name = concat (arch,
10538 (const char *) NULL);
10542 cpu_sub_arch_name = xstrdup (arch);
10543 cpu_arch_flags = flags;
10544 cpu_arch_isa_flags = flags;
10549 if (j >= ARRAY_SIZE (cpu_noarch))
10550 j = ARRAY_SIZE (cpu_arch);
10553 if (j >= ARRAY_SIZE (cpu_arch))
10554 as_fatal (_("invalid -march= option: `%s'"), arg);
10558 while (next != NULL);
10564 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10565 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10567 if (strcmp (arg, cpu_arch [j].name) == 0)
10569 cpu_arch_tune_set = 1;
10570 cpu_arch_tune = cpu_arch [j].type;
10571 cpu_arch_tune_flags = cpu_arch[j].flags;
10575 if (j >= ARRAY_SIZE (cpu_arch))
10576 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10579 case OPTION_MMNEMONIC:
10580 if (strcasecmp (arg, "att") == 0)
10581 intel_mnemonic = 0;
10582 else if (strcasecmp (arg, "intel") == 0)
10583 intel_mnemonic = 1;
10585 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10588 case OPTION_MSYNTAX:
10589 if (strcasecmp (arg, "att") == 0)
10591 else if (strcasecmp (arg, "intel") == 0)
10594 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10597 case OPTION_MINDEX_REG:
10598 allow_index_reg = 1;
10601 case OPTION_MNAKED_REG:
10602 allow_naked_reg = 1;
10605 case OPTION_MOLD_GCC:
10609 case OPTION_MSSE2AVX:
10613 case OPTION_MSSE_CHECK:
10614 if (strcasecmp (arg, "error") == 0)
10615 sse_check = check_error;
10616 else if (strcasecmp (arg, "warning") == 0)
10617 sse_check = check_warning;
10618 else if (strcasecmp (arg, "none") == 0)
10619 sse_check = check_none;
10621 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10624 case OPTION_MOPERAND_CHECK:
10625 if (strcasecmp (arg, "error") == 0)
10626 operand_check = check_error;
10627 else if (strcasecmp (arg, "warning") == 0)
10628 operand_check = check_warning;
10629 else if (strcasecmp (arg, "none") == 0)
10630 operand_check = check_none;
10632 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10635 case OPTION_MAVXSCALAR:
10636 if (strcasecmp (arg, "128") == 0)
10637 avxscalar = vex128;
10638 else if (strcasecmp (arg, "256") == 0)
10639 avxscalar = vex256;
10641 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10644 case OPTION_MADD_BND_PREFIX:
10645 add_bnd_prefix = 1;
10648 case OPTION_MEVEXLIG:
10649 if (strcmp (arg, "128") == 0)
10650 evexlig = evexl128;
10651 else if (strcmp (arg, "256") == 0)
10652 evexlig = evexl256;
10653 else if (strcmp (arg, "512") == 0)
10654 evexlig = evexl512;
10656 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10659 case OPTION_MEVEXRCIG:
10660 if (strcmp (arg, "rne") == 0)
10662 else if (strcmp (arg, "rd") == 0)
10664 else if (strcmp (arg, "ru") == 0)
10666 else if (strcmp (arg, "rz") == 0)
10669 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10672 case OPTION_MEVEXWIG:
10673 if (strcmp (arg, "0") == 0)
10675 else if (strcmp (arg, "1") == 0)
10678 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10681 # if defined (TE_PE) || defined (TE_PEP)
10682 case OPTION_MBIG_OBJ:
10687 case OPTION_MOMIT_LOCK_PREFIX:
10688 if (strcasecmp (arg, "yes") == 0)
10689 omit_lock_prefix = 1;
10690 else if (strcasecmp (arg, "no") == 0)
10691 omit_lock_prefix = 0;
10693 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10696 case OPTION_MFENCE_AS_LOCK_ADD:
10697 if (strcasecmp (arg, "yes") == 0)
10699 else if (strcasecmp (arg, "no") == 0)
10702 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10705 case OPTION_MRELAX_RELOCATIONS:
10706 if (strcasecmp (arg, "yes") == 0)
10707 generate_relax_relocations = 1;
10708 else if (strcasecmp (arg, "no") == 0)
10709 generate_relax_relocations = 0;
10711 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10714 case OPTION_MAMD64:
10718 case OPTION_MINTEL64:
10726 /* Turn off -Os. */
10727 optimize_for_space = 0;
10729 else if (*arg == 's')
10731 optimize_for_space = 1;
10732 /* Turn on all encoding optimizations. */
10737 optimize = atoi (arg);
10738 /* Turn off -Os. */
10739 optimize_for_space = 0;
10749 #define MESSAGE_TEMPLATE \
10753 output_message (FILE *stream, char *p, char *message, char *start,
10754 int *left_p, const char *name, int len)
10756 int size = sizeof (MESSAGE_TEMPLATE);
10757 int left = *left_p;
10759 /* Reserve 2 spaces for ", " or ",\0" */
10762 /* Check if there is any room. */
10770 p = mempcpy (p, name, len);
10774 /* Output the current message now and start a new one. */
10777 fprintf (stream, "%s\n", message);
10779 left = size - (start - message) - len - 2;
10781 gas_assert (left >= 0);
10783 p = mempcpy (p, name, len);
10791 show_arch (FILE *stream, int ext, int check)
10793 static char message[] = MESSAGE_TEMPLATE;
10794 char *start = message + 27;
10796 int size = sizeof (MESSAGE_TEMPLATE);
10803 left = size - (start - message);
10804 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10806 /* Should it be skipped? */
10807 if (cpu_arch [j].skip)
10810 name = cpu_arch [j].name;
10811 len = cpu_arch [j].len;
10814 /* It is an extension. Skip if we aren't asked to show it. */
10825 /* It is an processor. Skip if we show only extension. */
10828 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10830 /* It is an impossible processor - skip. */
10834 p = output_message (stream, p, message, start, &left, name, len);
10837 /* Display disabled extensions. */
10839 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10841 name = cpu_noarch [j].name;
10842 len = cpu_noarch [j].len;
10843 p = output_message (stream, p, message, start, &left, name,
10848 fprintf (stream, "%s\n", message);
10852 md_show_usage (FILE *stream)
10854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10855 fprintf (stream, _("\
10857 -V print assembler version number\n\
10860 fprintf (stream, _("\
10861 -n Do not optimize code alignment\n\
10862 -q quieten some warnings\n"));
10863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10864 fprintf (stream, _("\
10867 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10868 || defined (TE_PE) || defined (TE_PEP))
10869 fprintf (stream, _("\
10870 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10872 #ifdef SVR4_COMMENT_CHARS
10873 fprintf (stream, _("\
10874 --divide do not treat `/' as a comment character\n"));
10876 fprintf (stream, _("\
10877 --divide ignored\n"));
10879 fprintf (stream, _("\
10880 -march=CPU[,+EXTENSION...]\n\
10881 generate code for CPU and EXTENSION, CPU is one of:\n"));
10882 show_arch (stream, 0, 1);
10883 fprintf (stream, _("\
10884 EXTENSION is combination of:\n"));
10885 show_arch (stream, 1, 0);
10886 fprintf (stream, _("\
10887 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10888 show_arch (stream, 0, 0);
10889 fprintf (stream, _("\
10890 -msse2avx encode SSE instructions with VEX prefix\n"));
10891 fprintf (stream, _("\
10892 -msse-check=[none|error|warning]\n\
10893 check SSE instructions\n"));
10894 fprintf (stream, _("\
10895 -moperand-check=[none|error|warning]\n\
10896 check operand combinations for validity\n"));
10897 fprintf (stream, _("\
10898 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10900 fprintf (stream, _("\
10901 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10903 fprintf (stream, _("\
10904 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10905 for EVEX.W bit ignored instructions\n"));
10906 fprintf (stream, _("\
10907 -mevexrcig=[rne|rd|ru|rz]\n\
10908 encode EVEX instructions with specific EVEX.RC value\n\
10909 for SAE-only ignored instructions\n"));
10910 fprintf (stream, _("\
10911 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10912 fprintf (stream, _("\
10913 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10914 fprintf (stream, _("\
10915 -mindex-reg support pseudo index registers\n"));
10916 fprintf (stream, _("\
10917 -mnaked-reg don't require `%%' prefix for registers\n"));
10918 fprintf (stream, _("\
10919 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10920 fprintf (stream, _("\
10921 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10922 fprintf (stream, _("\
10923 -mshared disable branch optimization for shared code\n"));
10924 # if defined (TE_PE) || defined (TE_PEP)
10925 fprintf (stream, _("\
10926 -mbig-obj generate big object files\n"));
10928 fprintf (stream, _("\
10929 -momit-lock-prefix=[no|yes]\n\
10930 strip all lock prefixes\n"));
10931 fprintf (stream, _("\
10932 -mfence-as-lock-add=[no|yes]\n\
10933 encode lfence, mfence and sfence as\n\
10934 lock addl $0x0, (%%{re}sp)\n"));
10935 fprintf (stream, _("\
10936 -mrelax-relocations=[no|yes]\n\
10937 generate relax relocations\n"));
10938 fprintf (stream, _("\
10939 -mamd64 accept only AMD64 ISA\n"));
10940 fprintf (stream, _("\
10941 -mintel64 accept only Intel64 ISA\n"));
10944 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10945 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10946 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10948 /* Pick the target format to use. */
10951 i386_target_format (void)
10953 if (!strncmp (default_arch, "x86_64", 6))
10955 update_code_flag (CODE_64BIT, 1);
10956 if (default_arch[6] == '\0')
10957 x86_elf_abi = X86_64_ABI;
10959 x86_elf_abi = X86_64_X32_ABI;
10961 else if (!strcmp (default_arch, "i386"))
10962 update_code_flag (CODE_32BIT, 1);
10963 else if (!strcmp (default_arch, "iamcu"))
10965 update_code_flag (CODE_32BIT, 1);
10966 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10968 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10969 cpu_arch_name = "iamcu";
10970 cpu_sub_arch_name = NULL;
10971 cpu_arch_flags = iamcu_flags;
10972 cpu_arch_isa = PROCESSOR_IAMCU;
10973 cpu_arch_isa_flags = iamcu_flags;
10974 if (!cpu_arch_tune_set)
10976 cpu_arch_tune = cpu_arch_isa;
10977 cpu_arch_tune_flags = cpu_arch_isa_flags;
10980 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10981 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10985 as_fatal (_("unknown architecture"));
10987 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10988 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10989 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10990 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10992 switch (OUTPUT_FLAVOR)
10994 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10995 case bfd_target_aout_flavour:
10996 return AOUT_TARGET_FORMAT;
10998 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10999 # if defined (TE_PE) || defined (TE_PEP)
11000 case bfd_target_coff_flavour:
11001 if (flag_code == CODE_64BIT)
11002 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11005 # elif defined (TE_GO32)
11006 case bfd_target_coff_flavour:
11007 return "coff-go32";
11009 case bfd_target_coff_flavour:
11010 return "coff-i386";
11013 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11014 case bfd_target_elf_flavour:
11016 const char *format;
11018 switch (x86_elf_abi)
11021 format = ELF_TARGET_FORMAT;
11024 use_rela_relocations = 1;
11026 format = ELF_TARGET_FORMAT64;
11028 case X86_64_X32_ABI:
11029 use_rela_relocations = 1;
11031 disallow_64bit_reloc = 1;
11032 format = ELF_TARGET_FORMAT32;
11035 if (cpu_arch_isa == PROCESSOR_L1OM)
11037 if (x86_elf_abi != X86_64_ABI)
11038 as_fatal (_("Intel L1OM is 64bit only"));
11039 return ELF_TARGET_L1OM_FORMAT;
11041 else if (cpu_arch_isa == PROCESSOR_K1OM)
11043 if (x86_elf_abi != X86_64_ABI)
11044 as_fatal (_("Intel K1OM is 64bit only"));
11045 return ELF_TARGET_K1OM_FORMAT;
11047 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11049 if (x86_elf_abi != I386_ABI)
11050 as_fatal (_("Intel MCU is 32bit only"));
11051 return ELF_TARGET_IAMCU_FORMAT;
11057 #if defined (OBJ_MACH_O)
11058 case bfd_target_mach_o_flavour:
11059 if (flag_code == CODE_64BIT)
11061 use_rela_relocations = 1;
11063 return "mach-o-x86-64";
11066 return "mach-o-i386";
11074 #endif /* OBJ_MAYBE_ more than one */
11077 md_undefined_symbol (char *name)
11079 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11080 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11081 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11082 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11086 if (symbol_find (name))
11087 as_bad (_("GOT already in symbol table"));
11088 GOT_symbol = symbol_new (name, undefined_section,
11089 (valueT) 0, &zero_address_frag);
11096 /* Round up a section size to the appropriate boundary. */
11099 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11101 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11102 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11104 /* For a.out, force the section size to be aligned. If we don't do
11105 this, BFD will align it for us, but it will not write out the
11106 final bytes of the section. This may be a bug in BFD, but it is
11107 easier to fix it here since that is how the other a.out targets
11111 align = bfd_get_section_alignment (stdoutput, segment);
11112 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11119 /* On the i386, PC-relative offsets are relative to the start of the
11120 next instruction. That is, the address of the offset, plus its
11121 size, since the offset is always the last part of the insn. */
11124 md_pcrel_from (fixS *fixP)
11126 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11132 s_bss (int ignore ATTRIBUTE_UNUSED)
11136 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11138 obj_elf_section_change_hook ();
11140 temp = get_absolute_expression ();
11141 subseg_set (bss_section, (subsegT) temp);
11142 demand_empty_rest_of_line ();
11148 i386_validate_fix (fixS *fixp)
11150 if (fixp->fx_subsy)
11152 if (fixp->fx_subsy == GOT_symbol)
11154 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11159 if (fixp->fx_tcbit2)
11160 fixp->fx_r_type = (fixp->fx_tcbit
11161 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11162 : BFD_RELOC_X86_64_GOTPCRELX);
11165 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11170 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11172 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11174 fixp->fx_subsy = 0;
11177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11178 else if (!object_64bit)
11180 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11181 && fixp->fx_tcbit2)
11182 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11188 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11191 bfd_reloc_code_real_type code;
11193 switch (fixp->fx_r_type)
11195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11196 case BFD_RELOC_SIZE32:
11197 case BFD_RELOC_SIZE64:
11198 if (S_IS_DEFINED (fixp->fx_addsy)
11199 && !S_IS_EXTERNAL (fixp->fx_addsy))
11201 /* Resolve size relocation against local symbol to size of
11202 the symbol plus addend. */
11203 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11204 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11205 && !fits_in_unsigned_long (value))
11206 as_bad_where (fixp->fx_file, fixp->fx_line,
11207 _("symbol size computation overflow"));
11208 fixp->fx_addsy = NULL;
11209 fixp->fx_subsy = NULL;
11210 md_apply_fix (fixp, (valueT *) &value, NULL);
11214 /* Fall through. */
11216 case BFD_RELOC_X86_64_PLT32:
11217 case BFD_RELOC_X86_64_GOT32:
11218 case BFD_RELOC_X86_64_GOTPCREL:
11219 case BFD_RELOC_X86_64_GOTPCRELX:
11220 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11221 case BFD_RELOC_386_PLT32:
11222 case BFD_RELOC_386_GOT32:
11223 case BFD_RELOC_386_GOT32X:
11224 case BFD_RELOC_386_GOTOFF:
11225 case BFD_RELOC_386_GOTPC:
11226 case BFD_RELOC_386_TLS_GD:
11227 case BFD_RELOC_386_TLS_LDM:
11228 case BFD_RELOC_386_TLS_LDO_32:
11229 case BFD_RELOC_386_TLS_IE_32:
11230 case BFD_RELOC_386_TLS_IE:
11231 case BFD_RELOC_386_TLS_GOTIE:
11232 case BFD_RELOC_386_TLS_LE_32:
11233 case BFD_RELOC_386_TLS_LE:
11234 case BFD_RELOC_386_TLS_GOTDESC:
11235 case BFD_RELOC_386_TLS_DESC_CALL:
11236 case BFD_RELOC_X86_64_TLSGD:
11237 case BFD_RELOC_X86_64_TLSLD:
11238 case BFD_RELOC_X86_64_DTPOFF32:
11239 case BFD_RELOC_X86_64_DTPOFF64:
11240 case BFD_RELOC_X86_64_GOTTPOFF:
11241 case BFD_RELOC_X86_64_TPOFF32:
11242 case BFD_RELOC_X86_64_TPOFF64:
11243 case BFD_RELOC_X86_64_GOTOFF64:
11244 case BFD_RELOC_X86_64_GOTPC32:
11245 case BFD_RELOC_X86_64_GOT64:
11246 case BFD_RELOC_X86_64_GOTPCREL64:
11247 case BFD_RELOC_X86_64_GOTPC64:
11248 case BFD_RELOC_X86_64_GOTPLT64:
11249 case BFD_RELOC_X86_64_PLTOFF64:
11250 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11251 case BFD_RELOC_X86_64_TLSDESC_CALL:
11252 case BFD_RELOC_RVA:
11253 case BFD_RELOC_VTABLE_ENTRY:
11254 case BFD_RELOC_VTABLE_INHERIT:
11256 case BFD_RELOC_32_SECREL:
11258 code = fixp->fx_r_type;
11260 case BFD_RELOC_X86_64_32S:
11261 if (!fixp->fx_pcrel)
11263 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11264 code = fixp->fx_r_type;
11267 /* Fall through. */
11269 if (fixp->fx_pcrel)
11271 switch (fixp->fx_size)
11274 as_bad_where (fixp->fx_file, fixp->fx_line,
11275 _("can not do %d byte pc-relative relocation"),
11277 code = BFD_RELOC_32_PCREL;
11279 case 1: code = BFD_RELOC_8_PCREL; break;
11280 case 2: code = BFD_RELOC_16_PCREL; break;
11281 case 4: code = BFD_RELOC_32_PCREL; break;
11283 case 8: code = BFD_RELOC_64_PCREL; break;
11289 switch (fixp->fx_size)
11292 as_bad_where (fixp->fx_file, fixp->fx_line,
11293 _("can not do %d byte relocation"),
11295 code = BFD_RELOC_32;
11297 case 1: code = BFD_RELOC_8; break;
11298 case 2: code = BFD_RELOC_16; break;
11299 case 4: code = BFD_RELOC_32; break;
11301 case 8: code = BFD_RELOC_64; break;
11308 if ((code == BFD_RELOC_32
11309 || code == BFD_RELOC_32_PCREL
11310 || code == BFD_RELOC_X86_64_32S)
11312 && fixp->fx_addsy == GOT_symbol)
11315 code = BFD_RELOC_386_GOTPC;
11317 code = BFD_RELOC_X86_64_GOTPC32;
11319 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11321 && fixp->fx_addsy == GOT_symbol)
11323 code = BFD_RELOC_X86_64_GOTPC64;
11326 rel = XNEW (arelent);
11327 rel->sym_ptr_ptr = XNEW (asymbol *);
11328 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11330 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11332 if (!use_rela_relocations)
11334 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11335 vtable entry to be used in the relocation's section offset. */
11336 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11337 rel->address = fixp->fx_offset;
11338 #if defined (OBJ_COFF) && defined (TE_PE)
11339 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11340 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11345 /* Use the rela in 64bit mode. */
11348 if (disallow_64bit_reloc)
11351 case BFD_RELOC_X86_64_DTPOFF64:
11352 case BFD_RELOC_X86_64_TPOFF64:
11353 case BFD_RELOC_64_PCREL:
11354 case BFD_RELOC_X86_64_GOTOFF64:
11355 case BFD_RELOC_X86_64_GOT64:
11356 case BFD_RELOC_X86_64_GOTPCREL64:
11357 case BFD_RELOC_X86_64_GOTPC64:
11358 case BFD_RELOC_X86_64_GOTPLT64:
11359 case BFD_RELOC_X86_64_PLTOFF64:
11360 as_bad_where (fixp->fx_file, fixp->fx_line,
11361 _("cannot represent relocation type %s in x32 mode"),
11362 bfd_get_reloc_code_name (code));
11368 if (!fixp->fx_pcrel)
11369 rel->addend = fixp->fx_offset;
11373 case BFD_RELOC_X86_64_PLT32:
11374 case BFD_RELOC_X86_64_GOT32:
11375 case BFD_RELOC_X86_64_GOTPCREL:
11376 case BFD_RELOC_X86_64_GOTPCRELX:
11377 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11378 case BFD_RELOC_X86_64_TLSGD:
11379 case BFD_RELOC_X86_64_TLSLD:
11380 case BFD_RELOC_X86_64_GOTTPOFF:
11381 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11382 case BFD_RELOC_X86_64_TLSDESC_CALL:
11383 rel->addend = fixp->fx_offset - fixp->fx_size;
11386 rel->addend = (section->vma
11388 + fixp->fx_addnumber
11389 + md_pcrel_from (fixp));
11394 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11395 if (rel->howto == NULL)
11397 as_bad_where (fixp->fx_file, fixp->fx_line,
11398 _("cannot represent relocation type %s"),
11399 bfd_get_reloc_code_name (code));
11400 /* Set howto to a garbage value so that we can keep going. */
11401 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11402 gas_assert (rel->howto != NULL);
11408 #include "tc-i386-intel.c"
11411 tc_x86_parse_to_dw2regnum (expressionS *exp)
11413 int saved_naked_reg;
11414 char saved_register_dot;
11416 saved_naked_reg = allow_naked_reg;
11417 allow_naked_reg = 1;
11418 saved_register_dot = register_chars['.'];
11419 register_chars['.'] = '.';
11420 allow_pseudo_reg = 1;
11421 expression_and_evaluate (exp);
11422 allow_pseudo_reg = 0;
11423 register_chars['.'] = saved_register_dot;
11424 allow_naked_reg = saved_naked_reg;
11426 if (exp->X_op == O_register && exp->X_add_number >= 0)
11428 if ((addressT) exp->X_add_number < i386_regtab_size)
11430 exp->X_op = O_constant;
11431 exp->X_add_number = i386_regtab[exp->X_add_number]
11432 .dw2_regnum[flag_code >> 1];
11435 exp->X_op = O_illegal;
11440 tc_x86_frame_initial_instructions (void)
11442 static unsigned int sp_regno[2];
11444 if (!sp_regno[flag_code >> 1])
11446 char *saved_input = input_line_pointer;
11447 char sp[][4] = {"esp", "rsp"};
11450 input_line_pointer = sp[flag_code >> 1];
11451 tc_x86_parse_to_dw2regnum (&exp);
11452 gas_assert (exp.X_op == O_constant);
11453 sp_regno[flag_code >> 1] = exp.X_add_number;
11454 input_line_pointer = saved_input;
11457 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11458 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11462 x86_dwarf2_addr_size (void)
11464 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11465 if (x86_elf_abi == X86_64_X32_ABI)
11468 return bfd_arch_bits_per_address (stdoutput) / 8;
11472 i386_elf_section_type (const char *str, size_t len)
11474 if (flag_code == CODE_64BIT
11475 && len == sizeof ("unwind") - 1
11476 && strncmp (str, "unwind", 6) == 0)
11477 return SHT_X86_64_UNWIND;
11484 i386_solaris_fix_up_eh_frame (segT sec)
11486 if (flag_code == CODE_64BIT)
11487 elf_section_type (sec) = SHT_X86_64_UNWIND;
11493 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11497 exp.X_op = O_secrel;
11498 exp.X_add_symbol = symbol;
11499 exp.X_add_number = 0;
11500 emit_expr (&exp, size);
11504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11505 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11508 x86_64_section_letter (int letter, const char **ptr_msg)
11510 if (flag_code == CODE_64BIT)
11513 return SHF_X86_64_LARGE;
11515 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11518 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11523 x86_64_section_word (char *str, size_t len)
11525 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11526 return SHF_X86_64_LARGE;
11532 handle_large_common (int small ATTRIBUTE_UNUSED)
11534 if (flag_code != CODE_64BIT)
11536 s_comm_internal (0, elf_common_parse);
11537 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11541 static segT lbss_section;
11542 asection *saved_com_section_ptr = elf_com_section_ptr;
11543 asection *saved_bss_section = bss_section;
11545 if (lbss_section == NULL)
11547 flagword applicable;
11548 segT seg = now_seg;
11549 subsegT subseg = now_subseg;
11551 /* The .lbss section is for local .largecomm symbols. */
11552 lbss_section = subseg_new (".lbss", 0);
11553 applicable = bfd_applicable_section_flags (stdoutput);
11554 bfd_set_section_flags (stdoutput, lbss_section,
11555 applicable & SEC_ALLOC);
11556 seg_info (lbss_section)->bss = 1;
11558 subseg_set (seg, subseg);
11561 elf_com_section_ptr = &_bfd_elf_large_com_section;
11562 bss_section = lbss_section;
11564 s_comm_internal (0, elf_common_parse);
11566 elf_com_section_ptr = saved_com_section_ptr;
11567 bss_section = saved_bss_section;
11570 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */