1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry *parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static void process_drex (void);
93 static int process_operands (void);
94 static const seg_entry *build_modrm_byte (void);
95 static void output_insn (void);
96 static void output_imm (fragS *, offsetT);
97 static void output_disp (fragS *, offsetT);
99 static void s_bss (int);
101 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
102 static void handle_large_common (int small ATTRIBUTE_UNUSED);
105 static const char *default_arch = DEFAULT_ARCH;
107 /* 'md_assemble ()' gathers together information and puts it into a
114 const reg_entry *regs;
119 /* TM holds the template for the insn were currently assembling. */
122 /* SUFFIX holds the instruction mnemonic suffix if given.
123 (e.g. 'l' for 'movl') */
126 /* OPERANDS gives the number of given operands. */
127 unsigned int operands;
129 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
130 of given register, displacement, memory operands and immediate
132 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
134 /* TYPES [i] is the type (see above #defines) which tells us how to
135 use OP[i] for the corresponding operand. */
136 i386_operand_type types[MAX_OPERANDS];
138 /* Displacement expression, immediate expression, or register for each
140 union i386_op op[MAX_OPERANDS];
142 /* Flags for operands. */
143 unsigned int flags[MAX_OPERANDS];
144 #define Operand_PCrel 1
146 /* Relocation type for operand */
147 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
149 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
150 the base index byte below. */
151 const reg_entry *base_reg;
152 const reg_entry *index_reg;
153 unsigned int log2_scale_factor;
155 /* SEG gives the seg_entries of this insn. They are zero unless
156 explicit segment overrides are given. */
157 const seg_entry *seg[2];
159 /* PREFIX holds all the given prefix opcodes (usually null).
160 PREFIXES is the number of prefix opcodes. */
161 unsigned int prefixes;
162 unsigned char prefix[MAX_PREFIXES];
164 /* RM and SIB are the modrm byte and the sib byte where the
165 addressing modes of this insn are encoded. DREX is the byte
166 added by the SSE5 instructions. */
174 typedef struct _i386_insn i386_insn;
176 /* List of chars besides those in app.c:symbol_chars that can start an
177 operand. Used to prevent the scrubber eating vital white-space. */
178 const char extra_symbol_chars[] = "*%-(["
187 #if (defined (TE_I386AIX) \
188 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
189 && !defined (TE_GNU) \
190 && !defined (TE_LINUX) \
191 && !defined (TE_NETWARE) \
192 && !defined (TE_FreeBSD) \
193 && !defined (TE_NetBSD)))
194 /* This array holds the chars that always start a comment. If the
195 pre-processor is disabled, these aren't very useful. The option
196 --divide will remove '/' from this list. */
197 const char *i386_comment_chars = "#/";
198 #define SVR4_COMMENT_CHARS 1
199 #define PREFIX_SEPARATOR '\\'
202 const char *i386_comment_chars = "#";
203 #define PREFIX_SEPARATOR '/'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars[] = "#/";
216 const char line_separator_chars[] = ";";
218 /* Chars that can be used to separate mant from exp in floating point
220 const char EXP_CHARS[] = "eE";
222 /* Chars that mean this number is a floating point constant
225 const char FLT_CHARS[] = "fFdDxX";
227 /* Tables for lexical analysis. */
228 static char mnemonic_chars[256];
229 static char register_chars[256];
230 static char operand_chars[256];
231 static char identifier_chars[256];
232 static char digit_chars[256];
234 /* Lexical macros. */
235 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
236 #define is_operand_char(x) (operand_chars[(unsigned char) x])
237 #define is_register_char(x) (register_chars[(unsigned char) x])
238 #define is_space_char(x) ((x) == ' ')
239 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
240 #define is_digit_char(x) (digit_chars[(unsigned char) x])
242 /* All non-digit non-letter characters that may occur in an operand. */
243 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
245 /* md_assemble() always leaves the strings it's passed unaltered. To
246 effect this we maintain a stack of saved characters that we've smashed
247 with '\0's (indicating end of strings for various sub-fields of the
248 assembler instruction). */
249 static char save_stack[32];
250 static char *save_stack_p;
251 #define END_STRING_AND_SAVE(s) \
252 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
253 #define RESTORE_END_STRING(s) \
254 do { *(s) = *--save_stack_p; } while (0)
256 /* The instruction we're assembling. */
259 /* Possible templates for current insn. */
260 static const templates *current_templates;
262 /* Per instruction expressionS buffers: max displacements & immediates. */
263 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
264 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
266 /* Current operand we are working on. */
267 static int this_operand;
269 /* We support four different modes. FLAG_CODE variable is used to distinguish
276 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
278 static enum flag_code flag_code;
279 static unsigned int object_64bit;
280 static int use_rela_relocations = 0;
282 /* The names used to print error messages. */
283 static const char *flag_code_names[] =
290 /* 1 for intel syntax,
292 static int intel_syntax = 0;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg = 0;
297 /* Register prefix used for error message. */
298 static const char *register_prefix = "%";
300 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303 static char stackop_size = '\0';
305 /* Non-zero to optimize code alignment. */
306 int optimize_align_code = 1;
308 /* Non-zero to quieten some warnings. */
309 static int quiet_warnings = 0;
312 static const char *cpu_arch_name = NULL;
313 static const char *cpu_sub_arch_name = NULL;
315 /* CPU feature flags. */
316 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
318 /* Bitwise NOT of cpu_arch_flags. */
319 static i386_cpu_flags cpu_arch_flags_not;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set = 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion = 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS *GOT_symbol;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch[] =
430 {"generic32", PROCESSOR_GENERIC32,
431 CPU_GENERIC32_FLAGS },
432 {"generic64", PROCESSOR_GENERIC64,
433 CPU_GENERIC64_FLAGS },
434 {"i8086", PROCESSOR_UNKNOWN,
436 {"i186", PROCESSOR_UNKNOWN,
438 {"i286", PROCESSOR_UNKNOWN,
440 {"i386", PROCESSOR_I386,
442 {"i486", PROCESSOR_I486,
444 {"i586", PROCESSOR_PENTIUM,
446 {"i686", PROCESSOR_PENTIUMPRO,
448 {"pentium", PROCESSOR_PENTIUM,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
456 {"pentium4", PROCESSOR_PENTIUM4,
458 {"prescott", PROCESSOR_NOCONA,
460 {"nocona", PROCESSOR_NOCONA,
462 {"yonah", PROCESSOR_CORE,
464 {"core", PROCESSOR_CORE,
466 {"merom", PROCESSOR_CORE2,
468 {"core2", PROCESSOR_CORE2,
472 {"k6_2", PROCESSOR_K6,
474 {"athlon", PROCESSOR_ATHLON,
476 {"sledgehammer", PROCESSOR_K8,
478 {"opteron", PROCESSOR_K8,
482 {"amdfam10", PROCESSOR_AMDFAM10,
483 CPU_AMDFAM10_FLAGS },
484 {".mmx", PROCESSOR_UNKNOWN,
486 {".sse", PROCESSOR_UNKNOWN,
488 {".sse2", PROCESSOR_UNKNOWN,
490 {".sse3", PROCESSOR_UNKNOWN,
492 {".ssse3", PROCESSOR_UNKNOWN,
494 {".sse4.1", PROCESSOR_UNKNOWN,
496 {".sse4.2", PROCESSOR_UNKNOWN,
498 {".sse4", PROCESSOR_UNKNOWN,
500 {".3dnow", PROCESSOR_UNKNOWN,
502 {".3dnowa", PROCESSOR_UNKNOWN,
504 {".padlock", PROCESSOR_UNKNOWN,
506 {".pacifica", PROCESSOR_UNKNOWN,
508 {".svme", PROCESSOR_UNKNOWN,
510 {".sse4a", PROCESSOR_UNKNOWN,
512 {".abm", PROCESSOR_UNKNOWN,
514 {".sse5", PROCESSOR_UNKNOWN,
518 const pseudo_typeS md_pseudo_table[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
523 {"align", s_align_ptwo, 0},
525 {"arch", set_cpu_arch, 0},
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
533 {"slong", signed_cons, 4},
534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
550 {"secrel32", pe_directive_secrel, 0},
555 /* For interface with expression (). */
556 extern char *input_line_pointer;
558 /* Hash table for instruction mnemonic lookup. */
559 static struct hash_control *op_hash;
561 /* Hash table for register lookup. */
562 static struct hash_control *reg_hash;
565 i386_align_code (fragS *fragP, int count)
567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
570 static const char f32_1[] =
572 static const char f32_2[] =
573 {0x66,0x90}; /* xchg %ax,%ax */
574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f16_3[] =
607 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
608 static const char f16_4[] =
609 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_5[] =
612 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_6[] =
614 {0x89,0xf6, /* mov %si,%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_7[] =
617 {0x8d,0x74,0x00, /* lea 0(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_8[] =
620 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
622 static const char jump_31[] =
623 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
625 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
626 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
627 static const char *const f32_patt[] = {
628 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
629 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
631 static const char *const f16_patt[] = {
632 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
635 static const char alt_3[] =
637 /* nopl 0(%[re]ax) */
638 static const char alt_4[] =
639 {0x0f,0x1f,0x40,0x00};
640 /* nopl 0(%[re]ax,%[re]ax,1) */
641 static const char alt_5[] =
642 {0x0f,0x1f,0x44,0x00,0x00};
643 /* nopw 0(%[re]ax,%[re]ax,1) */
644 static const char alt_6[] =
645 {0x66,0x0f,0x1f,0x44,0x00,0x00};
646 /* nopl 0L(%[re]ax) */
647 static const char alt_7[] =
648 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
649 /* nopl 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_8[] =
651 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw 0L(%[re]ax,%[re]ax,1) */
653 static const char alt_9[] =
654 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_10[] =
657 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_long_11[] =
662 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 nopw %cs:0L(%[re]ax,%[re]ax,1) */
666 static const char alt_long_12[] =
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_13[] =
678 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 nopw %cs:0L(%[re]ax,%[re]ax,1) */
684 static const char alt_long_14[] =
689 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 nopw %cs:0L(%[re]ax,%[re]ax,1) */
696 static const char alt_long_15[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* nopl 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_11[] =
706 {0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_12[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
715 static const char alt_short_13[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 static const char alt_short_14[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 nopl 0L(%[re]ax,%[re]ax,1) */
725 static const char alt_short_15[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
728 static const char *const alt_short_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
731 alt_short_14, alt_short_15
733 static const char *const alt_long_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
736 alt_long_14, alt_long_15
739 /* Only align for at least a positive non-zero boundary. */
740 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
743 /* We need to decide which NOP sequence to use for 32bit and
744 64bit. When -mtune= is used:
746 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
747 PROCESSOR_GENERIC32, f32_patt will be used.
748 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
750 alt_long_patt will be used.
751 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
752 PROCESSOR_AMDFAM10, alt_short_patt will be used.
754 When -mtune= isn't used, alt_long_patt will be used if
755 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
758 When -march= or .arch is used, we can't use anything beyond
759 cpu_arch_isa_flags. */
761 if (flag_code == CODE_16BIT)
765 memcpy (fragP->fr_literal + fragP->fr_fix,
767 /* Adjust jump offset. */
768 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 memcpy (fragP->fr_literal + fragP->fr_fix,
772 f16_patt[count - 1], count);
776 const char *const *patt = NULL;
778 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
780 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
781 switch (cpu_arch_tune)
783 case PROCESSOR_UNKNOWN:
784 /* We use cpu_arch_isa_flags to check if we SHOULD
785 optimize for Cpu686. */
786 if (cpu_arch_isa_flags.bitfield.cpui686)
787 patt = alt_long_patt;
791 case PROCESSOR_PENTIUMPRO:
792 case PROCESSOR_PENTIUM4:
793 case PROCESSOR_NOCONA:
795 case PROCESSOR_CORE2:
796 case PROCESSOR_GENERIC64:
797 patt = alt_long_patt;
800 case PROCESSOR_ATHLON:
802 case PROCESSOR_AMDFAM10:
803 patt = alt_short_patt;
807 case PROCESSOR_PENTIUM:
808 case PROCESSOR_GENERIC32:
815 switch (cpu_arch_tune)
817 case PROCESSOR_UNKNOWN:
818 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
819 PROCESSOR_UNKNOWN. */
825 case PROCESSOR_PENTIUM:
827 case PROCESSOR_ATHLON:
829 case PROCESSOR_AMDFAM10:
830 case PROCESSOR_GENERIC32:
831 /* We use cpu_arch_isa_flags to check if we CAN optimize
833 if (cpu_arch_isa_flags.bitfield.cpui686)
834 patt = alt_short_patt;
838 case PROCESSOR_PENTIUMPRO:
839 case PROCESSOR_PENTIUM4:
840 case PROCESSOR_NOCONA:
842 case PROCESSOR_CORE2:
843 if (cpu_arch_isa_flags.bitfield.cpui686)
844 patt = alt_long_patt;
848 case PROCESSOR_GENERIC64:
849 patt = alt_long_patt;
854 if (patt == f32_patt)
856 /* If the padding is less than 15 bytes, we use the normal
857 ones. Otherwise, we use a jump instruction and adjust
860 memcpy (fragP->fr_literal + fragP->fr_fix,
861 patt[count - 1], count);
864 memcpy (fragP->fr_literal + fragP->fr_fix,
866 /* Adjust jump offset. */
867 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 /* Maximum length of an instruction is 15 byte. If the
873 padding is greater than 15 bytes and we don't use jump,
874 we have to break it into smaller pieces. */
879 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 memcpy (fragP->fr_literal + fragP->fr_fix,
885 patt [padding - 1], padding);
888 fragP->fr_var = count;
892 uints_all_zero (const unsigned int *x, unsigned int size)
910 uints_set (unsigned int *x, unsigned int v, unsigned int size)
927 uints_equal (const unsigned int *x, const unsigned int *y,
939 return x[0] == y [0];
946 #define UINTS_ALL_ZERO(x) \
947 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
948 #define UINTS_SET(x, v) \
949 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
950 #define UINTS_CLEAR(x) \
951 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
952 #define UINTS_EQUAL(x, y) \
953 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
956 cpu_flags_check_cpu64 (i386_cpu_flags f)
958 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
959 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
962 static INLINE i386_cpu_flags
963 cpu_flags_not (i386_cpu_flags x)
965 switch (ARRAY_SIZE (x.array))
968 x.array [2] = ~x.array [2];
970 x.array [1] = ~x.array [1];
972 x.array [0] = ~x.array [0];
979 x.bitfield.unused = 0;
985 static INLINE i386_cpu_flags
986 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
988 switch (ARRAY_SIZE (x.array))
991 x.array [2] &= y.array [2];
993 x.array [1] &= y.array [1];
995 x.array [0] &= y.array [0];
1003 static INLINE i386_cpu_flags
1004 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1006 switch (ARRAY_SIZE (x.array))
1009 x.array [2] |= y.array [2];
1011 x.array [1] |= y.array [1];
1013 x.array [0] |= y.array [0];
1022 cpu_flags_match (i386_cpu_flags x)
1024 i386_cpu_flags not = cpu_arch_flags_not;
1026 not.bitfield.cpu64 = 1;
1027 not.bitfield.cpuno64 = 1;
1029 x.bitfield.cpu64 = 0;
1030 x.bitfield.cpuno64 = 0;
1032 not = cpu_flags_and (x, not);
1033 return UINTS_ALL_ZERO (not);
1036 static INLINE i386_operand_type
1037 operand_type_and (i386_operand_type x, i386_operand_type y)
1039 switch (ARRAY_SIZE (x.array))
1042 x.array [2] &= y.array [2];
1044 x.array [1] &= y.array [1];
1046 x.array [0] &= y.array [0];
1054 static INLINE i386_operand_type
1055 operand_type_or (i386_operand_type x, i386_operand_type y)
1057 switch (ARRAY_SIZE (x.array))
1060 x.array [2] |= y.array [2];
1062 x.array [1] |= y.array [1];
1064 x.array [0] |= y.array [0];
1072 static INLINE i386_operand_type
1073 operand_type_xor (i386_operand_type x, i386_operand_type y)
1075 switch (ARRAY_SIZE (x.array))
1078 x.array [2] ^= y.array [2];
1080 x.array [1] ^= y.array [1];
1082 x.array [0] ^= y.array [0];
1090 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1091 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1092 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1093 static const i386_operand_type reg16_inoutportreg
1094 = OPERAND_TYPE_REG16_INOUTPORTREG;
1095 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1096 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1097 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1098 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1099 static const i386_operand_type anydisp
1100 = OPERAND_TYPE_ANYDISP;
1101 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1102 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1103 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1104 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1105 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1106 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1107 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1108 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1109 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1110 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1121 operand_type_check (i386_operand_type t, enum operand_type c)
1126 return (t.bitfield.reg8
1129 || t.bitfield.reg64);
1132 return (t.bitfield.imm8
1136 || t.bitfield.imm32s
1137 || t.bitfield.imm64);
1140 return (t.bitfield.disp8
1141 || t.bitfield.disp16
1142 || t.bitfield.disp32
1143 || t.bitfield.disp32s
1144 || t.bitfield.disp64);
1147 return (t.bitfield.disp8
1148 || t.bitfield.disp16
1149 || t.bitfield.disp32
1150 || t.bitfield.disp32s
1151 || t.bitfield.disp64
1152 || t.bitfield.baseindex);
1160 operand_type_match (i386_operand_type overlap,
1161 i386_operand_type given)
1163 i386_operand_type temp = overlap;
1165 temp.bitfield.jumpabsolute = 0;
1166 if (UINTS_ALL_ZERO (temp))
1169 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1170 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1173 /* If given types r0 and r1 are registers they must be of the same type
1174 unless the expected operand type register overlap is null.
1175 Note that Acc in a template matches every size of reg. */
1178 operand_type_register_match (i386_operand_type m0,
1179 i386_operand_type g0,
1180 i386_operand_type t0,
1181 i386_operand_type m1,
1182 i386_operand_type g1,
1183 i386_operand_type t1)
1185 if (!operand_type_check (g0, reg))
1188 if (!operand_type_check (g1, reg))
1191 if (g0.bitfield.reg8 == g1.bitfield.reg8
1192 && g0.bitfield.reg16 == g1.bitfield.reg16
1193 && g0.bitfield.reg32 == g1.bitfield.reg32
1194 && g0.bitfield.reg64 == g1.bitfield.reg64)
1197 if (m0.bitfield.acc)
1199 t0.bitfield.reg8 = 1;
1200 t0.bitfield.reg16 = 1;
1201 t0.bitfield.reg32 = 1;
1202 t0.bitfield.reg64 = 1;
1205 if (m1.bitfield.acc)
1207 t1.bitfield.reg8 = 1;
1208 t1.bitfield.reg16 = 1;
1209 t1.bitfield.reg32 = 1;
1210 t1.bitfield.reg64 = 1;
1213 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1214 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1215 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1216 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1219 static INLINE unsigned int
1220 mode_from_disp_size (i386_operand_type t)
1222 if (t.bitfield.disp8)
1224 else if (t.bitfield.disp16
1225 || t.bitfield.disp32
1226 || t.bitfield.disp32s)
1233 fits_in_signed_byte (offsetT num)
1235 return (num >= -128) && (num <= 127);
1239 fits_in_unsigned_byte (offsetT num)
1241 return (num & 0xff) == num;
1245 fits_in_unsigned_word (offsetT num)
1247 return (num & 0xffff) == num;
1251 fits_in_signed_word (offsetT num)
1253 return (-32768 <= num) && (num <= 32767);
1257 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1262 return (!(((offsetT) -1 << 31) & num)
1263 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1265 } /* fits_in_signed_long() */
1268 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1273 return (num & (((offsetT) 2 << 31) - 1)) == num;
1275 } /* fits_in_unsigned_long() */
1277 static i386_operand_type
1278 smallest_imm_type (offsetT num)
1280 i386_operand_type t;
1283 t.bitfield.imm64 = 1;
1285 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1287 /* This code is disabled on the 486 because all the Imm1 forms
1288 in the opcode table are slower on the i486. They're the
1289 versions with the implicitly specified single-position
1290 displacement, which has another syntax if you really want to
1292 t.bitfield.imm1 = 1;
1293 t.bitfield.imm8 = 1;
1294 t.bitfield.imm8s = 1;
1295 t.bitfield.imm16 = 1;
1296 t.bitfield.imm32 = 1;
1297 t.bitfield.imm32s = 1;
1299 else if (fits_in_signed_byte (num))
1301 t.bitfield.imm8 = 1;
1302 t.bitfield.imm8s = 1;
1303 t.bitfield.imm16 = 1;
1304 t.bitfield.imm32 = 1;
1305 t.bitfield.imm32s = 1;
1307 else if (fits_in_unsigned_byte (num))
1309 t.bitfield.imm8 = 1;
1310 t.bitfield.imm16 = 1;
1311 t.bitfield.imm32 = 1;
1312 t.bitfield.imm32s = 1;
1314 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1316 t.bitfield.imm16 = 1;
1317 t.bitfield.imm32 = 1;
1318 t.bitfield.imm32s = 1;
1320 else if (fits_in_signed_long (num))
1322 t.bitfield.imm32 = 1;
1323 t.bitfield.imm32s = 1;
1325 else if (fits_in_unsigned_long (num))
1326 t.bitfield.imm32 = 1;
1332 offset_in_range (offsetT val, int size)
1338 case 1: mask = ((addressT) 1 << 8) - 1; break;
1339 case 2: mask = ((addressT) 1 << 16) - 1; break;
1340 case 4: mask = ((addressT) 2 << 31) - 1; break;
1342 case 8: mask = ((addressT) 2 << 63) - 1; break;
1347 /* If BFD64, sign extend val. */
1348 if (!use_rela_relocations)
1349 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1350 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1352 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1354 char buf1[40], buf2[40];
1356 sprint_value (buf1, val);
1357 sprint_value (buf2, val & mask);
1358 as_warn (_("%s shortened to %s"), buf1, buf2);
1363 /* Returns 0 if attempting to add a prefix where one from the same
1364 class already exists, 1 if non rep/repne added, 2 if rep/repne
1367 add_prefix (unsigned int prefix)
1372 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1373 && flag_code == CODE_64BIT)
1375 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1376 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1377 && (prefix & (REX_R | REX_X | REX_B))))
1388 case CS_PREFIX_OPCODE:
1389 case DS_PREFIX_OPCODE:
1390 case ES_PREFIX_OPCODE:
1391 case FS_PREFIX_OPCODE:
1392 case GS_PREFIX_OPCODE:
1393 case SS_PREFIX_OPCODE:
1397 case REPNE_PREFIX_OPCODE:
1398 case REPE_PREFIX_OPCODE:
1401 case LOCK_PREFIX_OPCODE:
1409 case ADDR_PREFIX_OPCODE:
1413 case DATA_PREFIX_OPCODE:
1417 if (i.prefix[q] != 0)
1425 i.prefix[q] |= prefix;
1428 as_bad (_("same type of prefix used twice"));
1434 set_code_flag (int value)
1437 if (flag_code == CODE_64BIT)
1439 cpu_arch_flags.bitfield.cpu64 = 1;
1440 cpu_arch_flags.bitfield.cpuno64 = 0;
1441 cpu_arch_flags_not.bitfield.cpu64 = 0;
1442 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1446 cpu_arch_flags.bitfield.cpu64 = 0;
1447 cpu_arch_flags.bitfield.cpuno64 = 1;
1448 cpu_arch_flags_not.bitfield.cpu64 = 1;
1449 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1451 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1453 as_bad (_("64bit mode not supported on this CPU."));
1455 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1457 as_bad (_("32bit mode not supported on this CPU."));
1459 stackop_size = '\0';
1463 set_16bit_gcc_code_flag (int new_code_flag)
1465 flag_code = new_code_flag;
1466 if (flag_code != CODE_16BIT)
1468 cpu_arch_flags.bitfield.cpu64 = 0;
1469 cpu_arch_flags.bitfield.cpuno64 = 1;
1470 cpu_arch_flags_not.bitfield.cpu64 = 1;
1471 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1472 stackop_size = LONG_MNEM_SUFFIX;
1476 set_intel_syntax (int syntax_flag)
1478 /* Find out if register prefixing is specified. */
1479 int ask_naked_reg = 0;
1482 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1484 char *string = input_line_pointer;
1485 int e = get_symbol_end ();
1487 if (strcmp (string, "prefix") == 0)
1489 else if (strcmp (string, "noprefix") == 0)
1492 as_bad (_("bad argument to syntax directive."));
1493 *input_line_pointer = e;
1495 demand_empty_rest_of_line ();
1497 intel_syntax = syntax_flag;
1499 if (ask_naked_reg == 0)
1500 allow_naked_reg = (intel_syntax
1501 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1503 allow_naked_reg = (ask_naked_reg < 0);
1505 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1506 identifier_chars['$'] = intel_syntax ? '$' : 0;
1507 register_prefix = allow_naked_reg ? "" : "%";
1511 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1515 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1517 char *string = input_line_pointer;
1518 int e = get_symbol_end ();
1520 i386_cpu_flags flags;
1522 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1524 if (strcmp (string, cpu_arch[i].name) == 0)
1528 cpu_arch_name = cpu_arch[i].name;
1529 cpu_sub_arch_name = NULL;
1530 cpu_arch_flags = cpu_arch[i].flags;
1531 if (flag_code == CODE_64BIT)
1533 cpu_arch_flags.bitfield.cpu64 = 1;
1534 cpu_arch_flags.bitfield.cpuno64 = 0;
1538 cpu_arch_flags.bitfield.cpu64 = 0;
1539 cpu_arch_flags.bitfield.cpuno64 = 1;
1541 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1542 cpu_arch_isa = cpu_arch[i].type;
1543 cpu_arch_isa_flags = cpu_arch[i].flags;
1544 if (!cpu_arch_tune_set)
1546 cpu_arch_tune = cpu_arch_isa;
1547 cpu_arch_tune_flags = cpu_arch_isa_flags;
1552 flags = cpu_flags_or (cpu_arch_flags,
1554 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1556 cpu_sub_arch_name = cpu_arch[i].name;
1557 cpu_arch_flags = flags;
1558 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1560 *input_line_pointer = e;
1561 demand_empty_rest_of_line ();
1565 if (i >= ARRAY_SIZE (cpu_arch))
1566 as_bad (_("no such architecture: `%s'"), string);
1568 *input_line_pointer = e;
1571 as_bad (_("missing cpu architecture"));
1573 no_cond_jump_promotion = 0;
1574 if (*input_line_pointer == ','
1575 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1577 char *string = ++input_line_pointer;
1578 int e = get_symbol_end ();
1580 if (strcmp (string, "nojumps") == 0)
1581 no_cond_jump_promotion = 1;
1582 else if (strcmp (string, "jumps") == 0)
1585 as_bad (_("no such architecture modifier: `%s'"), string);
1587 *input_line_pointer = e;
1590 demand_empty_rest_of_line ();
1596 if (!strcmp (default_arch, "x86_64"))
1597 return bfd_mach_x86_64;
1598 else if (!strcmp (default_arch, "i386"))
1599 return bfd_mach_i386_i386;
1601 as_fatal (_("Unknown architecture"));
1607 const char *hash_err;
1609 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1611 /* Initialize op_hash hash table. */
1612 op_hash = hash_new ();
1615 const template *optab;
1616 templates *core_optab;
1618 /* Setup for loop. */
1620 core_optab = (templates *) xmalloc (sizeof (templates));
1621 core_optab->start = optab;
1626 if (optab->name == NULL
1627 || strcmp (optab->name, (optab - 1)->name) != 0)
1629 /* different name --> ship out current template list;
1630 add to hash table; & begin anew. */
1631 core_optab->end = optab;
1632 hash_err = hash_insert (op_hash,
1637 as_fatal (_("Internal Error: Can't hash %s: %s"),
1641 if (optab->name == NULL)
1643 core_optab = (templates *) xmalloc (sizeof (templates));
1644 core_optab->start = optab;
1649 /* Initialize reg_hash hash table. */
1650 reg_hash = hash_new ();
1652 const reg_entry *regtab;
1653 unsigned int regtab_size = i386_regtab_size;
1655 for (regtab = i386_regtab; regtab_size--; regtab++)
1657 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1659 as_fatal (_("Internal Error: Can't hash %s: %s"),
1665 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1670 for (c = 0; c < 256; c++)
1675 mnemonic_chars[c] = c;
1676 register_chars[c] = c;
1677 operand_chars[c] = c;
1679 else if (ISLOWER (c))
1681 mnemonic_chars[c] = c;
1682 register_chars[c] = c;
1683 operand_chars[c] = c;
1685 else if (ISUPPER (c))
1687 mnemonic_chars[c] = TOLOWER (c);
1688 register_chars[c] = mnemonic_chars[c];
1689 operand_chars[c] = c;
1692 if (ISALPHA (c) || ISDIGIT (c))
1693 identifier_chars[c] = c;
1696 identifier_chars[c] = c;
1697 operand_chars[c] = c;
1702 identifier_chars['@'] = '@';
1705 identifier_chars['?'] = '?';
1706 operand_chars['?'] = '?';
1708 digit_chars['-'] = '-';
1709 mnemonic_chars['-'] = '-';
1710 mnemonic_chars['.'] = '.';
1711 identifier_chars['_'] = '_';
1712 identifier_chars['.'] = '.';
1714 for (p = operand_special_chars; *p != '\0'; p++)
1715 operand_chars[(unsigned char) *p] = *p;
1718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1721 record_alignment (text_section, 2);
1722 record_alignment (data_section, 2);
1723 record_alignment (bss_section, 2);
1727 if (flag_code == CODE_64BIT)
1729 x86_dwarf2_return_column = 16;
1730 x86_cie_data_alignment = -8;
1734 x86_dwarf2_return_column = 8;
1735 x86_cie_data_alignment = -4;
1740 i386_print_statistics (FILE *file)
1742 hash_print_statistics (file, "i386 opcode", op_hash);
1743 hash_print_statistics (file, "i386 register", reg_hash);
1748 /* Debugging routines for md_assemble. */
1749 static void pte (template *);
1750 static void pt (i386_operand_type);
1751 static void pe (expressionS *);
1752 static void ps (symbolS *);
1755 pi (char *line, i386_insn *x)
1759 fprintf (stdout, "%s: template ", line);
1761 fprintf (stdout, " address: base %s index %s scale %x\n",
1762 x->base_reg ? x->base_reg->reg_name : "none",
1763 x->index_reg ? x->index_reg->reg_name : "none",
1764 x->log2_scale_factor);
1765 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1766 x->rm.mode, x->rm.reg, x->rm.regmem);
1767 fprintf (stdout, " sib: base %x index %x scale %x\n",
1768 x->sib.base, x->sib.index, x->sib.scale);
1769 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1770 (x->rex & REX_W) != 0,
1771 (x->rex & REX_R) != 0,
1772 (x->rex & REX_X) != 0,
1773 (x->rex & REX_B) != 0);
1774 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1775 x->drex.reg, x->drex.rex);
1776 for (i = 0; i < x->operands; i++)
1778 fprintf (stdout, " #%d: ", i + 1);
1780 fprintf (stdout, "\n");
1781 if (x->types[i].bitfield.reg8
1782 || x->types[i].bitfield.reg16
1783 || x->types[i].bitfield.reg32
1784 || x->types[i].bitfield.reg64
1785 || x->types[i].bitfield.regmmx
1786 || x->types[i].bitfield.regxmm
1787 || x->types[i].bitfield.sreg2
1788 || x->types[i].bitfield.sreg3
1789 || x->types[i].bitfield.control
1790 || x->types[i].bitfield.debug
1791 || x->types[i].bitfield.test)
1792 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1793 if (operand_type_check (x->types[i], imm))
1795 if (operand_type_check (x->types[i], disp))
1796 pe (x->op[i].disps);
1804 fprintf (stdout, " %d operands ", t->operands);
1805 fprintf (stdout, "opcode %x ", t->base_opcode);
1806 if (t->extension_opcode != None)
1807 fprintf (stdout, "ext %x ", t->extension_opcode);
1808 if (t->opcode_modifier.d)
1809 fprintf (stdout, "D");
1810 if (t->opcode_modifier.w)
1811 fprintf (stdout, "W");
1812 fprintf (stdout, "\n");
1813 for (i = 0; i < t->operands; i++)
1815 fprintf (stdout, " #%d type ", i + 1);
1816 pt (t->operand_types[i]);
1817 fprintf (stdout, "\n");
1824 fprintf (stdout, " operation %d\n", e->X_op);
1825 fprintf (stdout, " add_number %ld (%lx)\n",
1826 (long) e->X_add_number, (long) e->X_add_number);
1827 if (e->X_add_symbol)
1829 fprintf (stdout, " add_symbol ");
1830 ps (e->X_add_symbol);
1831 fprintf (stdout, "\n");
1835 fprintf (stdout, " op_symbol ");
1836 ps (e->X_op_symbol);
1837 fprintf (stdout, "\n");
1844 fprintf (stdout, "%s type %s%s",
1846 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1847 segment_name (S_GET_SEGMENT (s)));
1850 static struct type_name
1852 i386_operand_type mask;
1855 const type_names[] =
1857 { OPERAND_TYPE_REG8, "r8" },
1858 { OPERAND_TYPE_REG16, "r16" },
1859 { OPERAND_TYPE_REG32, "r32" },
1860 { OPERAND_TYPE_REG64, "r64" },
1861 { OPERAND_TYPE_IMM8, "i8" },
1862 { OPERAND_TYPE_IMM8, "i8s" },
1863 { OPERAND_TYPE_IMM16, "i16" },
1864 { OPERAND_TYPE_IMM32, "i32" },
1865 { OPERAND_TYPE_IMM32S, "i32s" },
1866 { OPERAND_TYPE_IMM64, "i64" },
1867 { OPERAND_TYPE_IMM1, "i1" },
1868 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1869 { OPERAND_TYPE_DISP8, "d8" },
1870 { OPERAND_TYPE_DISP16, "d16" },
1871 { OPERAND_TYPE_DISP32, "d32" },
1872 { OPERAND_TYPE_DISP32S, "d32s" },
1873 { OPERAND_TYPE_DISP64, "d64" },
1874 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1875 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1876 { OPERAND_TYPE_CONTROL, "control reg" },
1877 { OPERAND_TYPE_TEST, "test reg" },
1878 { OPERAND_TYPE_DEBUG, "debug reg" },
1879 { OPERAND_TYPE_FLOATREG, "FReg" },
1880 { OPERAND_TYPE_FLOATACC, "FAcc" },
1881 { OPERAND_TYPE_SREG2, "SReg2" },
1882 { OPERAND_TYPE_SREG3, "SReg3" },
1883 { OPERAND_TYPE_ACC, "Acc" },
1884 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1885 { OPERAND_TYPE_REGMMX, "rMMX" },
1886 { OPERAND_TYPE_REGXMM, "rXMM" },
1887 { OPERAND_TYPE_ESSEG, "es" },
1891 pt (i386_operand_type t)
1894 i386_operand_type a;
1896 for (j = 0; j < ARRAY_SIZE (type_names); j++)
1898 a = operand_type_and (t, type_names[j].mask);
1899 if (!UINTS_ALL_ZERO (a))
1900 fprintf (stdout, "%s, ", type_names[j].name);
1905 #endif /* DEBUG386 */
1907 static bfd_reloc_code_real_type
1908 reloc (unsigned int size,
1911 bfd_reloc_code_real_type other)
1913 if (other != NO_RELOC)
1915 reloc_howto_type *reloc;
1920 case BFD_RELOC_X86_64_GOT32:
1921 return BFD_RELOC_X86_64_GOT64;
1923 case BFD_RELOC_X86_64_PLTOFF64:
1924 return BFD_RELOC_X86_64_PLTOFF64;
1926 case BFD_RELOC_X86_64_GOTPC32:
1927 other = BFD_RELOC_X86_64_GOTPC64;
1929 case BFD_RELOC_X86_64_GOTPCREL:
1930 other = BFD_RELOC_X86_64_GOTPCREL64;
1932 case BFD_RELOC_X86_64_TPOFF32:
1933 other = BFD_RELOC_X86_64_TPOFF64;
1935 case BFD_RELOC_X86_64_DTPOFF32:
1936 other = BFD_RELOC_X86_64_DTPOFF64;
1942 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1943 if (size == 4 && flag_code != CODE_64BIT)
1946 reloc = bfd_reloc_type_lookup (stdoutput, other);
1948 as_bad (_("unknown relocation (%u)"), other);
1949 else if (size != bfd_get_reloc_size (reloc))
1950 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1951 bfd_get_reloc_size (reloc),
1953 else if (pcrel && !reloc->pc_relative)
1954 as_bad (_("non-pc-relative relocation for pc-relative field"));
1955 else if ((reloc->complain_on_overflow == complain_overflow_signed
1957 || (reloc->complain_on_overflow == complain_overflow_unsigned
1959 as_bad (_("relocated field and relocation type differ in signedness"));
1968 as_bad (_("there are no unsigned pc-relative relocations"));
1971 case 1: return BFD_RELOC_8_PCREL;
1972 case 2: return BFD_RELOC_16_PCREL;
1973 case 4: return BFD_RELOC_32_PCREL;
1974 case 8: return BFD_RELOC_64_PCREL;
1976 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1983 case 4: return BFD_RELOC_X86_64_32S;
1988 case 1: return BFD_RELOC_8;
1989 case 2: return BFD_RELOC_16;
1990 case 4: return BFD_RELOC_32;
1991 case 8: return BFD_RELOC_64;
1993 as_bad (_("cannot do %s %u byte relocation"),
1994 sign > 0 ? "signed" : "unsigned", size);
1998 return BFD_RELOC_NONE;
2001 /* Here we decide which fixups can be adjusted to make them relative to
2002 the beginning of the section instead of the symbol. Basically we need
2003 to make sure that the dynamic relocations are done correctly, so in
2004 some cases we force the original symbol to be used. */
2007 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2013 /* Don't adjust pc-relative references to merge sections in 64-bit
2015 if (use_rela_relocations
2016 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2020 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2021 and changed later by validate_fix. */
2022 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2023 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2026 /* adjust_reloc_syms doesn't know about the GOT. */
2027 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2028 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2029 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2040 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2049 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2053 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2054 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2061 intel_float_operand (const char *mnemonic)
2063 /* Note that the value returned is meaningful only for opcodes with (memory)
2064 operands, hence the code here is free to improperly handle opcodes that
2065 have no operands (for better performance and smaller code). */
2067 if (mnemonic[0] != 'f')
2068 return 0; /* non-math */
2070 switch (mnemonic[1])
2072 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2073 the fs segment override prefix not currently handled because no
2074 call path can make opcodes without operands get here */
2076 return 2 /* integer op */;
2078 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2079 return 3; /* fldcw/fldenv */
2082 if (mnemonic[2] != 'o' /* fnop */)
2083 return 3; /* non-waiting control op */
2086 if (mnemonic[2] == 's')
2087 return 3; /* frstor/frstpm */
2090 if (mnemonic[2] == 'a')
2091 return 3; /* fsave */
2092 if (mnemonic[2] == 't')
2094 switch (mnemonic[3])
2096 case 'c': /* fstcw */
2097 case 'd': /* fstdw */
2098 case 'e': /* fstenv */
2099 case 's': /* fsts[gw] */
2105 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2106 return 0; /* fxsave/fxrstor are not really math ops */
2113 /* This is the guts of the machine-dependent assembler. LINE points to a
2114 machine dependent instruction. This function is supposed to emit
2115 the frags/bytes it assembles to. */
2122 char mnemonic[MAX_MNEM_SIZE];
2124 /* Initialize globals. */
2125 memset (&i, '\0', sizeof (i));
2126 for (j = 0; j < MAX_OPERANDS; j++)
2127 i.reloc[j] = NO_RELOC;
2128 memset (disp_expressions, '\0', sizeof (disp_expressions));
2129 memset (im_expressions, '\0', sizeof (im_expressions));
2130 save_stack_p = save_stack;
2132 /* First parse an instruction mnemonic & call i386_operand for the operands.
2133 We assume that the scrubber has arranged it so that line[0] is the valid
2134 start of a (possibly prefixed) mnemonic. */
2136 line = parse_insn (line, mnemonic);
2140 line = parse_operands (line, mnemonic);
2144 /* Now we've parsed the mnemonic into a set of templates, and have the
2145 operands at hand. */
2147 /* All intel opcodes have reversed operands except for "bound" and
2148 "enter". We also don't reverse intersegment "jmp" and "call"
2149 instructions with 2 immediate operands so that the immediate segment
2150 precedes the offset, as it does when in AT&T mode. */
2153 && (strcmp (mnemonic, "bound") != 0)
2154 && (strcmp (mnemonic, "invlpga") != 0)
2155 && !(operand_type_check (i.types[0], imm)
2156 && operand_type_check (i.types[1], imm)))
2159 /* The order of the immediates should be reversed
2160 for 2 immediates extrq and insertq instructions */
2161 if (i.imm_operands == 2
2162 && (strcmp (mnemonic, "extrq") == 0
2163 || strcmp (mnemonic, "insertq") == 0))
2164 swap_2_operands (0, 1);
2169 /* Don't optimize displacement for movabs since it only takes 64bit
2172 && (flag_code != CODE_64BIT
2173 || strcmp (mnemonic, "movabs") != 0))
2176 /* Next, we find a template that matches the given insn,
2177 making sure the overlap of the given operands types is consistent
2178 with the template operand types. */
2180 if (!match_template ())
2185 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2187 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
2188 i.tm.base_opcode ^= Opcode_FloatR;
2190 /* Zap movzx and movsx suffix. The suffix may have been set from
2191 "word ptr" or "byte ptr" on the source operand, but we'll use
2192 the suffix later to choose the destination register. */
2193 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2195 if (i.reg_operands < 2
2197 && (!i.tm.opcode_modifier.no_bsuf
2198 || !i.tm.opcode_modifier.no_wsuf
2199 || !i.tm.opcode_modifier.no_lsuf
2200 || !i.tm.opcode_modifier.no_ssuf
2201 || !i.tm.opcode_modifier.no_xsuf
2202 || !i.tm.opcode_modifier.no_qsuf))
2203 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2209 if (i.tm.opcode_modifier.fwait)
2210 if (!add_prefix (FWAIT_OPCODE))
2213 /* Check string instruction segment overrides. */
2214 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2216 if (!check_string ())
2220 if (!process_suffix ())
2223 /* Make still unresolved immediate matches conform to size of immediate
2224 given in i.suffix. */
2225 if (!finalize_imm ())
2228 if (i.types[0].bitfield.imm1)
2229 i.imm_operands = 0; /* kludge for shift insns. */
2231 for (j = 0; j < 3; j++)
2232 if (i.types[j].bitfield.inoutportreg
2233 || i.types[j].bitfield.shiftcount
2234 || i.types[j].bitfield.acc
2235 || i.types[j].bitfield.floatacc)
2238 if (i.tm.opcode_modifier.immext)
2242 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2244 /* Streaming SIMD extensions 3 Instructions have the fixed
2245 operands with an opcode suffix which is coded in the same
2246 place as an 8-bit immediate field would be. Here we check
2247 those operands and remove them afterwards. */
2250 for (x = 0; x < i.operands; x++)
2251 if (i.op[x].regs->reg_num != x)
2252 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2254 i.op[x].regs->reg_name,
2260 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2261 opcode suffix which is coded in the same place as an 8-bit
2262 immediate field would be. Here we fake an 8-bit immediate
2263 operand from the opcode suffix stored in tm.extension_opcode.
2264 SSE5 also uses this encoding, for some of its 3 argument
2267 assert (i.imm_operands == 0
2269 || (i.tm.cpu_flags.bitfield.cpusse5
2270 && i.operands <= 3)));
2272 exp = &im_expressions[i.imm_operands++];
2273 i.op[i.operands].imms = exp;
2274 UINTS_CLEAR (i.types[i.operands]);
2275 i.types[i.operands].bitfield.imm8 = 1;
2277 exp->X_op = O_constant;
2278 exp->X_add_number = i.tm.extension_opcode;
2279 i.tm.extension_opcode = None;
2282 /* For insns with operands there are more diddles to do to the opcode. */
2285 if (!process_operands ())
2288 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2290 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2291 as_warn (_("translating to `%sp'"), i.tm.name);
2294 /* Handle conversion of 'int $3' --> special int3 insn. */
2295 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2297 i.tm.base_opcode = INT3_OPCODE;
2301 if ((i.tm.opcode_modifier.jump
2302 || i.tm.opcode_modifier.jumpbyte
2303 || i.tm.opcode_modifier.jumpdword)
2304 && i.op[0].disps->X_op == O_constant)
2306 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2307 the absolute address given by the constant. Since ix86 jumps and
2308 calls are pc relative, we need to generate a reloc. */
2309 i.op[0].disps->X_add_symbol = &abs_symbol;
2310 i.op[0].disps->X_op = O_symbol;
2313 if (i.tm.opcode_modifier.rex64)
2316 /* For 8 bit registers we need an empty rex prefix. Also if the
2317 instruction already has a prefix, we need to convert old
2318 registers to new ones. */
2320 if ((i.types[0].bitfield.reg8
2321 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2322 || (i.types[1].bitfield.reg8
2323 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2324 || ((i.types[0].bitfield.reg8
2325 || i.types[1].bitfield.reg8)
2330 i.rex |= REX_OPCODE;
2331 for (x = 0; x < 2; x++)
2333 /* Look for 8 bit operand that uses old registers. */
2334 if (i.types[x].bitfield.reg8
2335 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2337 /* In case it is "hi" register, give up. */
2338 if (i.op[x].regs->reg_num > 3)
2339 as_bad (_("can't encode register '%s%s' in an "
2340 "instruction requiring REX prefix."),
2341 register_prefix, i.op[x].regs->reg_name);
2343 /* Otherwise it is equivalent to the extended register.
2344 Since the encoding doesn't change this is merely
2345 cosmetic cleanup for debug output. */
2347 i.op[x].regs = i.op[x].regs + 8;
2352 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2354 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2359 else if (i.rex != 0)
2360 add_prefix (REX_OPCODE | i.rex);
2362 /* We are ready to output the insn. */
2367 parse_insn (char *line, char *mnemonic)
2370 char *token_start = l;
2375 /* Non-zero if we found a prefix only acceptable with string insns. */
2376 const char *expecting_string_instruction = NULL;
2381 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2384 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2386 as_bad (_("no such instruction: `%s'"), token_start);
2391 if (!is_space_char (*l)
2392 && *l != END_OF_INSN
2394 || (*l != PREFIX_SEPARATOR
2397 as_bad (_("invalid character %s in mnemonic"),
2398 output_invalid (*l));
2401 if (token_start == l)
2403 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2404 as_bad (_("expecting prefix; got nothing"));
2406 as_bad (_("expecting mnemonic; got nothing"));
2410 /* Look up instruction (or prefix) via hash table. */
2411 current_templates = hash_find (op_hash, mnemonic);
2413 if (*l != END_OF_INSN
2414 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2415 && current_templates
2416 && current_templates->start->opcode_modifier.isprefix)
2418 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2420 as_bad ((flag_code != CODE_64BIT
2421 ? _("`%s' is only supported in 64-bit mode")
2422 : _("`%s' is not supported in 64-bit mode")),
2423 current_templates->start->name);
2426 /* If we are in 16-bit mode, do not allow addr16 or data16.
2427 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2428 if ((current_templates->start->opcode_modifier.size16
2429 || current_templates->start->opcode_modifier.size32)
2430 && flag_code != CODE_64BIT
2431 && (current_templates->start->opcode_modifier.size32
2432 ^ (flag_code == CODE_16BIT)))
2434 as_bad (_("redundant %s prefix"),
2435 current_templates->start->name);
2438 /* Add prefix, checking for repeated prefixes. */
2439 switch (add_prefix (current_templates->start->base_opcode))
2444 expecting_string_instruction = current_templates->start->name;
2447 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2454 if (!current_templates)
2456 /* See if we can get a match by trimming off a suffix. */
2459 case WORD_MNEM_SUFFIX:
2460 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2461 i.suffix = SHORT_MNEM_SUFFIX;
2463 case BYTE_MNEM_SUFFIX:
2464 case QWORD_MNEM_SUFFIX:
2465 i.suffix = mnem_p[-1];
2467 current_templates = hash_find (op_hash, mnemonic);
2469 case SHORT_MNEM_SUFFIX:
2470 case LONG_MNEM_SUFFIX:
2473 i.suffix = mnem_p[-1];
2475 current_templates = hash_find (op_hash, mnemonic);
2483 if (intel_float_operand (mnemonic) == 1)
2484 i.suffix = SHORT_MNEM_SUFFIX;
2486 i.suffix = LONG_MNEM_SUFFIX;
2488 current_templates = hash_find (op_hash, mnemonic);
2492 if (!current_templates)
2494 as_bad (_("no such instruction: `%s'"), token_start);
2499 if (current_templates->start->opcode_modifier.jump
2500 || current_templates->start->opcode_modifier.jumpbyte)
2502 /* Check for a branch hint. We allow ",pt" and ",pn" for
2503 predict taken and predict not taken respectively.
2504 I'm not sure that branch hints actually do anything on loop
2505 and jcxz insns (JumpByte) for current Pentium4 chips. They
2506 may work in the future and it doesn't hurt to accept them
2508 if (l[0] == ',' && l[1] == 'p')
2512 if (!add_prefix (DS_PREFIX_OPCODE))
2516 else if (l[2] == 'n')
2518 if (!add_prefix (CS_PREFIX_OPCODE))
2524 /* Any other comma loses. */
2527 as_bad (_("invalid character %s in mnemonic"),
2528 output_invalid (*l));
2532 /* Check if instruction is supported on specified architecture. */
2534 for (t = current_templates->start; t < current_templates->end; ++t)
2536 if (cpu_flags_match (t->cpu_flags))
2538 if (cpu_flags_check_cpu64 (t->cpu_flags))
2541 if (!(supported & 2))
2543 as_bad (flag_code == CODE_64BIT
2544 ? _("`%s' is not supported in 64-bit mode")
2545 : _("`%s' is only supported in 64-bit mode"),
2546 current_templates->start->name);
2549 if (!(supported & 1))
2551 as_warn (_("`%s' is not supported on `%s%s'"),
2552 current_templates->start->name,
2554 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2556 else if (!cpu_arch_flags.bitfield.cpui386
2557 && (flag_code != CODE_16BIT))
2559 as_warn (_("use .code16 to ensure correct addressing mode"));
2562 /* Check for rep/repne without a string instruction. */
2563 if (expecting_string_instruction)
2565 static templates override;
2567 for (t = current_templates->start; t < current_templates->end; ++t)
2568 if (t->opcode_modifier.isstring)
2570 if (t >= current_templates->end)
2572 as_bad (_("expecting string instruction after `%s'"),
2573 expecting_string_instruction);
2576 for (override.start = t; t < current_templates->end; ++t)
2577 if (!t->opcode_modifier.isstring)
2580 current_templates = &override;
2587 parse_operands (char *l, const char *mnemonic)
2591 /* 1 if operand is pending after ','. */
2592 unsigned int expecting_operand = 0;
2594 /* Non-zero if operand parens not balanced. */
2595 unsigned int paren_not_balanced;
2597 while (*l != END_OF_INSN)
2599 /* Skip optional white space before operand. */
2600 if (is_space_char (*l))
2602 if (!is_operand_char (*l) && *l != END_OF_INSN)
2604 as_bad (_("invalid character %s before operand %d"),
2605 output_invalid (*l),
2609 token_start = l; /* after white space */
2610 paren_not_balanced = 0;
2611 while (paren_not_balanced || *l != ',')
2613 if (*l == END_OF_INSN)
2615 if (paren_not_balanced)
2618 as_bad (_("unbalanced parenthesis in operand %d."),
2621 as_bad (_("unbalanced brackets in operand %d."),
2626 break; /* we are done */
2628 else if (!is_operand_char (*l) && !is_space_char (*l))
2630 as_bad (_("invalid character %s in operand %d"),
2631 output_invalid (*l),
2638 ++paren_not_balanced;
2640 --paren_not_balanced;
2645 ++paren_not_balanced;
2647 --paren_not_balanced;
2651 if (l != token_start)
2652 { /* Yes, we've read in another operand. */
2653 unsigned int operand_ok;
2654 this_operand = i.operands++;
2655 if (i.operands > MAX_OPERANDS)
2657 as_bad (_("spurious operands; (%d operands/instruction max)"),
2661 /* Now parse operand adding info to 'i' as we go along. */
2662 END_STRING_AND_SAVE (l);
2666 i386_intel_operand (token_start,
2667 intel_float_operand (mnemonic));
2669 operand_ok = i386_operand (token_start);
2671 RESTORE_END_STRING (l);
2677 if (expecting_operand)
2679 expecting_operand_after_comma:
2680 as_bad (_("expecting operand after ','; got nothing"));
2685 as_bad (_("expecting operand before ','; got nothing"));
2690 /* Now *l must be either ',' or END_OF_INSN. */
2693 if (*++l == END_OF_INSN)
2695 /* Just skip it, if it's \n complain. */
2696 goto expecting_operand_after_comma;
2698 expecting_operand = 1;
2705 swap_2_operands (int xchg1, int xchg2)
2707 union i386_op temp_op;
2708 i386_operand_type temp_type;
2709 enum bfd_reloc_code_real temp_reloc;
2711 temp_type = i.types[xchg2];
2712 i.types[xchg2] = i.types[xchg1];
2713 i.types[xchg1] = temp_type;
2714 temp_op = i.op[xchg2];
2715 i.op[xchg2] = i.op[xchg1];
2716 i.op[xchg1] = temp_op;
2717 temp_reloc = i.reloc[xchg2];
2718 i.reloc[xchg2] = i.reloc[xchg1];
2719 i.reloc[xchg1] = temp_reloc;
2723 swap_operands (void)
2728 swap_2_operands (1, i.operands - 2);
2731 swap_2_operands (0, i.operands - 1);
2737 if (i.mem_operands == 2)
2739 const seg_entry *temp_seg;
2740 temp_seg = i.seg[0];
2741 i.seg[0] = i.seg[1];
2742 i.seg[1] = temp_seg;
2746 /* Try to ensure constant immediates are represented in the smallest
2751 char guess_suffix = 0;
2755 guess_suffix = i.suffix;
2756 else if (i.reg_operands)
2758 /* Figure out a suffix from the last register operand specified.
2759 We can't do this properly yet, ie. excluding InOutPortReg,
2760 but the following works for instructions with immediates.
2761 In any case, we can't set i.suffix yet. */
2762 for (op = i.operands; --op >= 0;)
2763 if (i.types[op].bitfield.reg8)
2765 guess_suffix = BYTE_MNEM_SUFFIX;
2768 else if (i.types[op].bitfield.reg16)
2770 guess_suffix = WORD_MNEM_SUFFIX;
2773 else if (i.types[op].bitfield.reg32)
2775 guess_suffix = LONG_MNEM_SUFFIX;
2778 else if (i.types[op].bitfield.reg64)
2780 guess_suffix = QWORD_MNEM_SUFFIX;
2784 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2785 guess_suffix = WORD_MNEM_SUFFIX;
2787 for (op = i.operands; --op >= 0;)
2788 if (operand_type_check (i.types[op], imm))
2790 switch (i.op[op].imms->X_op)
2793 /* If a suffix is given, this operand may be shortened. */
2794 switch (guess_suffix)
2796 case LONG_MNEM_SUFFIX:
2797 i.types[op].bitfield.imm32 = 1;
2798 i.types[op].bitfield.imm64 = 1;
2800 case WORD_MNEM_SUFFIX:
2801 i.types[op].bitfield.imm16 = 1;
2802 i.types[op].bitfield.imm32 = 1;
2803 i.types[op].bitfield.imm32s = 1;
2804 i.types[op].bitfield.imm64 = 1;
2806 case BYTE_MNEM_SUFFIX:
2807 i.types[op].bitfield.imm8 = 1;
2808 i.types[op].bitfield.imm8s = 1;
2809 i.types[op].bitfield.imm16 = 1;
2810 i.types[op].bitfield.imm32 = 1;
2811 i.types[op].bitfield.imm32s = 1;
2812 i.types[op].bitfield.imm64 = 1;
2816 /* If this operand is at most 16 bits, convert it
2817 to a signed 16 bit number before trying to see
2818 whether it will fit in an even smaller size.
2819 This allows a 16-bit operand such as $0xffe0 to
2820 be recognised as within Imm8S range. */
2821 if ((i.types[op].bitfield.imm16)
2822 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2824 i.op[op].imms->X_add_number =
2825 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2827 if ((i.types[op].bitfield.imm32)
2828 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2831 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2832 ^ ((offsetT) 1 << 31))
2833 - ((offsetT) 1 << 31));
2836 = operand_type_or (i.types[op],
2837 smallest_imm_type (i.op[op].imms->X_add_number));
2839 /* We must avoid matching of Imm32 templates when 64bit
2840 only immediate is available. */
2841 if (guess_suffix == QWORD_MNEM_SUFFIX)
2842 i.types[op].bitfield.imm32 = 0;
2849 /* Symbols and expressions. */
2851 /* Convert symbolic operand to proper sizes for matching, but don't
2852 prevent matching a set of insns that only supports sizes other
2853 than those matching the insn suffix. */
2855 i386_operand_type mask, allowed;
2859 UINTS_CLEAR (allowed);
2861 for (t = current_templates->start;
2862 t < current_templates->end;
2864 allowed = operand_type_or (allowed,
2865 t->operand_types[op]);
2866 switch (guess_suffix)
2868 case QWORD_MNEM_SUFFIX:
2869 mask.bitfield.imm64 = 1;
2870 mask.bitfield.imm32s = 1;
2872 case LONG_MNEM_SUFFIX:
2873 mask.bitfield.imm32 = 1;
2875 case WORD_MNEM_SUFFIX:
2876 mask.bitfield.imm16 = 1;
2878 case BYTE_MNEM_SUFFIX:
2879 mask.bitfield.imm8 = 1;
2884 allowed = operand_type_and (mask, allowed);
2885 if (!UINTS_ALL_ZERO (allowed))
2886 i.types[op] = operand_type_and (i.types[op], mask);
2893 /* Try to use the smallest displacement type too. */
2895 optimize_disp (void)
2899 for (op = i.operands; --op >= 0;)
2900 if (operand_type_check (i.types[op], disp))
2902 if (i.op[op].disps->X_op == O_constant)
2904 offsetT disp = i.op[op].disps->X_add_number;
2906 if (i.types[op].bitfield.disp16
2907 && (disp & ~(offsetT) 0xffff) == 0)
2909 /* If this operand is at most 16 bits, convert
2910 to a signed 16 bit number and don't use 64bit
2912 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2913 i.types[op].bitfield.disp64 = 0;
2915 if (i.types[op].bitfield.disp32
2916 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2918 /* If this operand is at most 32 bits, convert
2919 to a signed 32 bit number and don't use 64bit
2921 disp &= (((offsetT) 2 << 31) - 1);
2922 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2923 i.types[op].bitfield.disp64 = 0;
2925 if (!disp && i.types[op].bitfield.baseindex)
2927 i.types[op].bitfield.disp8 = 0;
2928 i.types[op].bitfield.disp16 = 0;
2929 i.types[op].bitfield.disp32 = 0;
2930 i.types[op].bitfield.disp32s = 0;
2931 i.types[op].bitfield.disp64 = 0;
2935 else if (flag_code == CODE_64BIT)
2937 if (fits_in_signed_long (disp))
2939 i.types[op].bitfield.disp64 = 0;
2940 i.types[op].bitfield.disp32s = 1;
2942 if (fits_in_unsigned_long (disp))
2943 i.types[op].bitfield.disp32 = 1;
2945 if ((i.types[op].bitfield.disp32
2946 || i.types[op].bitfield.disp32s
2947 || i.types[op].bitfield.disp16)
2948 && fits_in_signed_byte (disp))
2949 i.types[op].bitfield.disp8 = 1;
2951 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2952 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2954 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2955 i.op[op].disps, 0, i.reloc[op]);
2956 i.types[op].bitfield.disp8 = 0;
2957 i.types[op].bitfield.disp16 = 0;
2958 i.types[op].bitfield.disp32 = 0;
2959 i.types[op].bitfield.disp32s = 0;
2960 i.types[op].bitfield.disp64 = 0;
2963 /* We only support 64bit displacement on constants. */
2964 i.types[op].bitfield.disp64 = 0;
2969 match_template (void)
2971 /* Points to template once we've found it. */
2973 i386_operand_type overlap0, overlap1, overlap2, overlap3;
2974 unsigned int found_reverse_match;
2975 i386_opcode_modifier suffix_check;
2976 i386_operand_type operand_types [MAX_OPERANDS];
2977 int addr_prefix_disp;
2979 i386_cpu_flags overlap;
2981 #if MAX_OPERANDS != 4
2982 # error "MAX_OPERANDS must be 4."
2985 found_reverse_match = 0;
2986 addr_prefix_disp = -1;
2988 memset (&suffix_check, 0, sizeof (suffix_check));
2989 if (i.suffix == BYTE_MNEM_SUFFIX)
2990 suffix_check.no_bsuf = 1;
2991 else if (i.suffix == WORD_MNEM_SUFFIX)
2992 suffix_check.no_wsuf = 1;
2993 else if (i.suffix == SHORT_MNEM_SUFFIX)
2994 suffix_check.no_ssuf = 1;
2995 else if (i.suffix == LONG_MNEM_SUFFIX)
2996 suffix_check.no_lsuf = 1;
2997 else if (i.suffix == QWORD_MNEM_SUFFIX)
2998 suffix_check.no_qsuf = 1;
2999 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3000 suffix_check.no_xsuf = 1;
3002 for (t = current_templates->start; t < current_templates->end; t++)
3004 addr_prefix_disp = -1;
3006 /* Must have right number of operands. */
3007 if (i.operands != t->operands)
3010 /* Check the suffix, except for some instructions in intel mode. */
3011 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3012 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3013 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3014 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3015 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3016 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3017 && !(intel_syntax && t->opcode_modifier.ignoresize))
3020 for (j = 0; j < MAX_OPERANDS; j++)
3021 operand_types [j] = t->operand_types [j];
3023 /* In general, don't allow 64-bit operands in 32-bit mode. */
3024 if (i.suffix == QWORD_MNEM_SUFFIX
3025 && flag_code != CODE_64BIT
3027 ? (!t->opcode_modifier.ignoresize
3028 && !intel_float_operand (t->name))
3029 : intel_float_operand (t->name) != 2)
3030 && ((!operand_types[0].bitfield.regmmx
3031 && !operand_types[0].bitfield.regxmm)
3032 || (!operand_types[t->operands > 1].bitfield.regmmx
3033 && !!operand_types[t->operands > 1].bitfield.regxmm))
3034 && (t->base_opcode != 0x0fc7
3035 || t->extension_opcode != 1 /* cmpxchg8b */))
3038 /* Do not verify operands when there are none. */
3041 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3044 if (!UINTS_ALL_ZERO (overlap))
3046 /* We've found a match; break out of loop. */
3051 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3052 into Disp32/Disp16/Disp32 operand. */
3053 if (i.prefix[ADDR_PREFIX] != 0)
3055 /* There should be only one Disp operand. */
3059 for (j = 0; j < MAX_OPERANDS; j++)
3061 if (operand_types[j].bitfield.disp16)
3063 addr_prefix_disp = j;
3064 operand_types[j].bitfield.disp32 = 1;
3065 operand_types[j].bitfield.disp16 = 0;
3071 for (j = 0; j < MAX_OPERANDS; j++)
3073 if (operand_types[j].bitfield.disp32)
3075 addr_prefix_disp = j;
3076 operand_types[j].bitfield.disp32 = 0;
3077 operand_types[j].bitfield.disp16 = 1;
3083 for (j = 0; j < MAX_OPERANDS; j++)
3085 if (operand_types[j].bitfield.disp64)
3087 addr_prefix_disp = j;
3088 operand_types[j].bitfield.disp64 = 0;
3089 operand_types[j].bitfield.disp32 = 1;
3097 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3098 switch (t->operands)
3101 if (!operand_type_match (overlap0, i.types[0]))
3105 /* xchg %eax, %eax is a special case. It is an aliase for nop
3106 only in 32bit mode and we can use opcode 0x90. In 64bit
3107 mode, we can't use 0x90 for xchg %eax, %eax since it should
3108 zero-extend %eax to %rax. */
3109 if (flag_code == CODE_64BIT
3110 && t->base_opcode == 0x90
3111 && UINTS_EQUAL (i.types [0], acc32)
3112 && UINTS_EQUAL (i.types [1], acc32))
3116 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3117 if (!operand_type_match (overlap0, i.types[0])
3118 || !operand_type_match (overlap1, i.types[1])
3119 /* monitor in SSE3 is a very special case. The first
3120 register and the second register may have different
3121 sizes. The same applies to crc32 in SSE4.2. It is
3122 also true for invlpga, vmload, vmrun and vmsave in
3124 || !((t->base_opcode == 0x0f01
3125 && (t->extension_opcode == 0xc8
3126 || t->extension_opcode == 0xd8
3127 || t->extension_opcode == 0xda
3128 || t->extension_opcode == 0xdb
3129 || t->extension_opcode == 0xdf))
3130 || t->base_opcode == 0xf20f38f1
3131 || operand_type_register_match (overlap0, i.types[0],
3133 overlap1, i.types[1],
3136 /* Check if other direction is valid ... */
3137 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3140 /* Try reversing direction of operands. */
3141 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3142 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3143 if (!operand_type_match (overlap0, i.types[0])
3144 || !operand_type_match (overlap1, i.types[1])
3145 || !operand_type_register_match (overlap0, i.types[0],
3147 overlap1, i.types[1],
3150 /* Does not match either direction. */
3153 /* found_reverse_match holds which of D or FloatDR
3155 if (t->opcode_modifier.d)
3156 found_reverse_match = Opcode_D;
3157 else if (t->opcode_modifier.floatd)
3158 found_reverse_match = Opcode_FloatD;
3160 found_reverse_match = 0;
3161 if (t->opcode_modifier.floatr)
3162 found_reverse_match |= Opcode_FloatR;
3166 /* Found a forward 2 operand match here. */
3167 switch (t->operands)
3170 overlap3 = operand_type_and (i.types[3],
3173 overlap2 = operand_type_and (i.types[2],
3178 switch (t->operands)
3181 if (!operand_type_match (overlap3, i.types[3])
3182 || !operand_type_register_match (overlap2,
3190 /* Here we make use of the fact that there are no
3191 reverse match 3 operand instructions, and all 3
3192 operand instructions only need to be checked for
3193 register consistency between operands 2 and 3. */
3194 if (!operand_type_match (overlap2, i.types[2])
3195 || !operand_type_register_match (overlap1,
3205 /* Found either forward/reverse 2, 3 or 4 operand match here:
3206 slip through to break. */
3208 if (!UINTS_ALL_ZERO (overlap))
3210 found_reverse_match = 0;
3213 /* We've found a match; break out of loop. */
3217 if (t == current_templates->end)
3219 /* We found no match. */
3220 as_bad (_("suffix or operands invalid for `%s'"),
3221 current_templates->start->name);
3225 if (!quiet_warnings)
3228 && (i.types[0].bitfield.jumpabsolute
3229 != operand_types[0].bitfield.jumpabsolute))
3231 as_warn (_("indirect %s without `*'"), t->name);
3234 if (t->opcode_modifier.isprefix
3235 && t->opcode_modifier.ignoresize)
3237 /* Warn them that a data or address size prefix doesn't
3238 affect assembly of the next line of code. */
3239 as_warn (_("stand-alone `%s' prefix"), t->name);
3243 /* Copy the template we found. */
3246 if (addr_prefix_disp != -1)
3247 i.tm.operand_types[addr_prefix_disp]
3248 = operand_types[addr_prefix_disp];
3250 if (found_reverse_match)
3252 /* If we found a reverse match we must alter the opcode
3253 direction bit. found_reverse_match holds bits to change
3254 (different for int & float insns). */
3256 i.tm.base_opcode ^= found_reverse_match;
3258 i.tm.operand_types[0] = operand_types[1];
3259 i.tm.operand_types[1] = operand_types[0];
3268 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3269 if (i.tm.operand_types[mem_op].bitfield.esseg)
3271 if (i.seg[0] != NULL && i.seg[0] != &es)
3273 as_bad (_("`%s' operand %d must use `%%es' segment"),
3278 /* There's only ever one segment override allowed per instruction.
3279 This instruction possibly has a legal segment override on the
3280 second operand, so copy the segment to where non-string
3281 instructions store it, allowing common code. */
3282 i.seg[0] = i.seg[1];
3284 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3286 if (i.seg[1] != NULL && i.seg[1] != &es)
3288 as_bad (_("`%s' operand %d must use `%%es' segment"),
3298 process_suffix (void)
3300 /* If matched instruction specifies an explicit instruction mnemonic
3302 if (i.tm.opcode_modifier.size16)
3303 i.suffix = WORD_MNEM_SUFFIX;
3304 else if (i.tm.opcode_modifier.size32)
3305 i.suffix = LONG_MNEM_SUFFIX;
3306 else if (i.tm.opcode_modifier.size64)
3307 i.suffix = QWORD_MNEM_SUFFIX;
3308 else if (i.reg_operands)
3310 /* If there's no instruction mnemonic suffix we try to invent one
3311 based on register operands. */
3314 /* We take i.suffix from the last register operand specified,
3315 Destination register type is more significant than source
3316 register type. crc32 in SSE4.2 prefers source register
3318 if (i.tm.base_opcode == 0xf20f38f1)
3320 if (i.types[0].bitfield.reg16)
3321 i.suffix = WORD_MNEM_SUFFIX;
3322 else if (i.types[0].bitfield.reg32)
3323 i.suffix = LONG_MNEM_SUFFIX;
3324 else if (i.types[0].bitfield.reg64)
3325 i.suffix = QWORD_MNEM_SUFFIX;
3327 else if (i.tm.base_opcode == 0xf20f38f0)
3329 if (i.types[0].bitfield.reg8)
3330 i.suffix = BYTE_MNEM_SUFFIX;
3337 if (i.tm.base_opcode == 0xf20f38f1
3338 || i.tm.base_opcode == 0xf20f38f0)
3340 /* We have to know the operand size for crc32. */
3341 as_bad (_("ambiguous memory operand size for `%s`"),
3346 for (op = i.operands; --op >= 0;)
3347 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3349 if (i.types[op].bitfield.reg8)
3351 i.suffix = BYTE_MNEM_SUFFIX;
3354 else if (i.types[op].bitfield.reg16)
3356 i.suffix = WORD_MNEM_SUFFIX;
3359 else if (i.types[op].bitfield.reg32)
3361 i.suffix = LONG_MNEM_SUFFIX;
3364 else if (i.types[op].bitfield.reg64)
3366 i.suffix = QWORD_MNEM_SUFFIX;
3372 else if (i.suffix == BYTE_MNEM_SUFFIX)
3374 if (!check_byte_reg ())
3377 else if (i.suffix == LONG_MNEM_SUFFIX)
3379 if (!check_long_reg ())
3382 else if (i.suffix == QWORD_MNEM_SUFFIX)
3384 if (!check_qword_reg ())
3387 else if (i.suffix == WORD_MNEM_SUFFIX)
3389 if (!check_word_reg ())
3392 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3393 /* Do nothing if the instruction is going to ignore the prefix. */
3398 else if (i.tm.opcode_modifier.defaultsize
3400 /* exclude fldenv/frstor/fsave/fstenv */
3401 && i.tm.opcode_modifier.no_ssuf)
3403 i.suffix = stackop_size;
3405 else if (intel_syntax
3407 && (i.tm.operand_types[0].bitfield.jumpabsolute
3408 || i.tm.opcode_modifier.jumpbyte
3409 || i.tm.opcode_modifier.jumpintersegment
3410 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3411 && i.tm.extension_opcode <= 3)))
3416 if (!i.tm.opcode_modifier.no_qsuf)
3418 i.suffix = QWORD_MNEM_SUFFIX;
3422 if (!i.tm.opcode_modifier.no_lsuf)
3423 i.suffix = LONG_MNEM_SUFFIX;
3426 if (!i.tm.opcode_modifier.no_wsuf)
3427 i.suffix = WORD_MNEM_SUFFIX;
3436 if (i.tm.opcode_modifier.w)
3438 as_bad (_("no instruction mnemonic suffix given and "
3439 "no register operands; can't size instruction"));
3445 unsigned int suffixes;
3447 suffixes = !i.tm.opcode_modifier.no_bsuf;
3448 if (!i.tm.opcode_modifier.no_wsuf)
3450 if (!i.tm.opcode_modifier.no_lsuf)
3452 if (!i.tm.opcode_modifier.no_lsuf)
3454 if (!i.tm.opcode_modifier.no_ssuf)
3456 if (!i.tm.opcode_modifier.no_qsuf)
3459 /* There are more than suffix matches. */
3460 if (i.tm.opcode_modifier.w
3461 || ((suffixes & (suffixes - 1))
3462 && !i.tm.opcode_modifier.defaultsize
3463 && !i.tm.opcode_modifier.ignoresize))
3465 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3471 /* Change the opcode based on the operand size given by i.suffix;
3472 We don't need to change things for byte insns. */
3474 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3476 /* It's not a byte, select word/dword operation. */
3477 if (i.tm.opcode_modifier.w)
3479 if (i.tm.opcode_modifier.shortform)
3480 i.tm.base_opcode |= 8;
3482 i.tm.base_opcode |= 1;
3485 /* Now select between word & dword operations via the operand
3486 size prefix, except for instructions that will ignore this
3488 if (i.tm.base_opcode == 0x0f01
3489 && (i.tm.extension_opcode == 0xc8
3490 || i.tm.extension_opcode == 0xd8
3491 || i.tm.extension_opcode == 0xda
3492 || i.tm.extension_opcode == 0xdb
3493 || i.tm.extension_opcode == 0xdf))
3495 /* monitor in SSE3 is a very special case. The default size
3496 of AX is the size of mode. The address size override
3497 prefix will change the size of AX. It is also true for
3498 invlpga, vmload, vmrun and vmsave in SVME. */
3499 if ((flag_code == CODE_32BIT
3500 && i.op->regs[0].reg_type.bitfield.reg16)
3501 || (flag_code != CODE_32BIT
3502 && i.op->regs[0].reg_type.bitfield.reg32))
3503 if (!add_prefix (ADDR_PREFIX_OPCODE))
3506 else if (i.suffix != QWORD_MNEM_SUFFIX
3507 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3508 && !i.tm.opcode_modifier.ignoresize
3509 && !i.tm.opcode_modifier.floatmf
3510 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3511 || (flag_code == CODE_64BIT
3512 && i.tm.opcode_modifier.jumpbyte)))
3514 unsigned int prefix = DATA_PREFIX_OPCODE;
3516 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3517 prefix = ADDR_PREFIX_OPCODE;
3519 if (!add_prefix (prefix))
3523 /* Set mode64 for an operand. */
3524 if (i.suffix == QWORD_MNEM_SUFFIX
3525 && flag_code == CODE_64BIT
3526 && !i.tm.opcode_modifier.norex64)
3528 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3529 need rex64. cmpxchg8b is also a special case. */
3530 if (! (i.operands == 2
3531 && i.tm.base_opcode == 0x90
3532 && i.tm.extension_opcode == None
3533 && UINTS_EQUAL (i.types [0], acc64)
3534 && UINTS_EQUAL (i.types [1], acc64))
3535 && ! (i.operands == 1
3536 && i.tm.base_opcode == 0xfc7
3537 && i.tm.extension_opcode == 1
3538 && !operand_type_check (i.types [0], reg)
3539 && operand_type_check (i.types [0], anymem)))
3543 /* Size floating point instruction. */
3544 if (i.suffix == LONG_MNEM_SUFFIX)
3545 if (i.tm.opcode_modifier.floatmf)
3546 i.tm.base_opcode ^= 4;
3553 check_byte_reg (void)
3557 for (op = i.operands; --op >= 0;)
3559 /* If this is an eight bit register, it's OK. If it's the 16 or
3560 32 bit version of an eight bit register, we will just use the
3561 low portion, and that's OK too. */
3562 if (i.types[op].bitfield.reg8)
3565 /* movzx, movsx, pextrb and pinsrb should not generate this
3568 && (i.tm.base_opcode == 0xfb7
3569 || i.tm.base_opcode == 0xfb6
3570 || i.tm.base_opcode == 0x63
3571 || i.tm.base_opcode == 0xfbe
3572 || i.tm.base_opcode == 0xfbf
3573 || i.tm.base_opcode == 0x660f3a14
3574 || i.tm.base_opcode == 0x660f3a20))
3577 /* crc32 doesn't generate this warning. */
3578 if (i.tm.base_opcode == 0xf20f38f0)
3581 if ((i.types[op].bitfield.reg16
3582 || i.types[op].bitfield.reg32
3583 || i.types[op].bitfield.reg64)
3584 && i.op[op].regs->reg_num < 4)
3586 /* Prohibit these changes in the 64bit mode, since the
3587 lowering is more complicated. */
3588 if (flag_code == CODE_64BIT
3589 && !i.tm.operand_types[op].bitfield.inoutportreg)
3591 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3592 register_prefix, i.op[op].regs->reg_name,
3596 #if REGISTER_WARNINGS
3598 && !i.tm.operand_types[op].bitfield.inoutportreg)
3599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3601 (i.op[op].regs + (i.types[op].bitfield.reg16
3602 ? REGNAM_AL - REGNAM_AX
3603 : REGNAM_AL - REGNAM_EAX))->reg_name,
3605 i.op[op].regs->reg_name,
3610 /* Any other register is bad. */
3611 if (i.types[op].bitfield.reg16
3612 || i.types[op].bitfield.reg32
3613 || i.types[op].bitfield.reg64
3614 || i.types[op].bitfield.regmmx
3615 || i.types[op].bitfield.regxmm
3616 || i.types[op].bitfield.sreg2
3617 || i.types[op].bitfield.sreg3
3618 || i.types[op].bitfield.control
3619 || i.types[op].bitfield.debug
3620 || i.types[op].bitfield.test
3621 || i.types[op].bitfield.floatreg
3622 || i.types[op].bitfield.floatacc)
3624 as_bad (_("`%s%s' not allowed with `%s%c'"),
3626 i.op[op].regs->reg_name,
3636 check_long_reg (void)
3640 for (op = i.operands; --op >= 0;)
3641 /* Reject eight bit registers, except where the template requires
3642 them. (eg. movzb) */
3643 if (i.types[op].bitfield.reg8
3644 && (i.tm.operand_types[op].bitfield.reg16
3645 || i.tm.operand_types[op].bitfield.reg32
3646 || i.tm.operand_types[op].bitfield.acc))
3648 as_bad (_("`%s%s' not allowed with `%s%c'"),
3650 i.op[op].regs->reg_name,
3655 /* Warn if the e prefix on a general reg is missing. */
3656 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3657 && i.types[op].bitfield.reg16
3658 && (i.tm.operand_types[op].bitfield.reg32
3659 || i.tm.operand_types[op].bitfield.acc))
3661 /* Prohibit these changes in the 64bit mode, since the
3662 lowering is more complicated. */
3663 if (flag_code == CODE_64BIT)
3665 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3666 register_prefix, i.op[op].regs->reg_name,
3670 #if REGISTER_WARNINGS
3672 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3674 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3676 i.op[op].regs->reg_name,
3680 /* Warn if the r prefix on a general reg is missing. */
3681 else if (i.types[op].bitfield.reg64
3682 && (i.tm.operand_types[op].bitfield.reg32
3683 || i.tm.operand_types[op].bitfield.acc))
3686 && i.tm.base_opcode == 0xf30f2d
3687 && !i.types[0].bitfield.regxmm)
3689 /* cvtss2si converts DWORD memory to Reg64. We want
3691 i.suffix = QWORD_MNEM_SUFFIX;
3695 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3696 register_prefix, i.op[op].regs->reg_name,
3705 check_qword_reg (void)
3709 for (op = i.operands; --op >= 0; )
3710 /* Reject eight bit registers, except where the template requires
3711 them. (eg. movzb) */
3712 if (i.types[op].bitfield.reg8
3713 && (i.tm.operand_types[op].bitfield.reg16
3714 || i.tm.operand_types[op].bitfield.reg32
3715 || i.tm.operand_types[op].bitfield.acc))
3717 as_bad (_("`%s%s' not allowed with `%s%c'"),
3719 i.op[op].regs->reg_name,
3724 /* Warn if the e prefix on a general reg is missing. */
3725 else if ((i.types[op].bitfield.reg16
3726 || i.types[op].bitfield.reg32)
3727 && (i.tm.operand_types[op].bitfield.reg32
3728 || i.tm.operand_types[op].bitfield.acc))
3730 /* Prohibit these changes in the 64bit mode, since the
3731 lowering is more complicated. */
3733 && i.tm.base_opcode == 0xf20f2d
3734 && !i.types[0].bitfield.regxmm)
3736 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3738 i.suffix = LONG_MNEM_SUFFIX;
3742 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3743 register_prefix, i.op[op].regs->reg_name,
3752 check_word_reg (void)
3755 for (op = i.operands; --op >= 0;)
3756 /* Reject eight bit registers, except where the template requires
3757 them. (eg. movzb) */
3758 if (i.types[op].bitfield.reg8
3759 && (i.tm.operand_types[op].bitfield.reg16
3760 || i.tm.operand_types[op].bitfield.reg32
3761 || i.tm.operand_types[op].bitfield.acc))
3763 as_bad (_("`%s%s' not allowed with `%s%c'"),
3765 i.op[op].regs->reg_name,
3770 /* Warn if the e prefix on a general reg is present. */
3771 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3772 && i.types[op].bitfield.reg32
3773 && (i.tm.operand_types[op].bitfield.reg16
3774 || i.tm.operand_types[op].bitfield.acc))
3776 /* Prohibit these changes in the 64bit mode, since the
3777 lowering is more complicated. */
3778 if (flag_code == CODE_64BIT)
3780 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3781 register_prefix, i.op[op].regs->reg_name,
3786 #if REGISTER_WARNINGS
3787 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3789 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3791 i.op[op].regs->reg_name,
3799 update_imm (unsigned int j)
3801 i386_operand_type overlap;
3803 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
3804 if ((overlap.bitfield.imm8
3805 || overlap.bitfield.imm8s
3806 || overlap.bitfield.imm16
3807 || overlap.bitfield.imm32
3808 || overlap.bitfield.imm32s
3809 || overlap.bitfield.imm64)
3810 && !UINTS_EQUAL (overlap, imm8)
3811 && !UINTS_EQUAL (overlap, imm8s)
3812 && !UINTS_EQUAL (overlap, imm16)
3813 && !UINTS_EQUAL (overlap, imm32)
3814 && !UINTS_EQUAL (overlap, imm32s)
3815 && !UINTS_EQUAL (overlap, imm64))
3819 i386_operand_type temp;
3822 if (i.suffix == BYTE_MNEM_SUFFIX)
3824 temp.bitfield.imm8 = overlap.bitfield.imm8;
3825 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3827 else if (i.suffix == WORD_MNEM_SUFFIX)
3828 temp.bitfield.imm16 = overlap.bitfield.imm16;
3829 else if (i.suffix == QWORD_MNEM_SUFFIX)
3831 temp.bitfield.imm64 = overlap.bitfield.imm64;
3832 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3835 temp.bitfield.imm32 = overlap.bitfield.imm32;
3838 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3839 || UINTS_EQUAL (overlap, imm16_32)
3840 || UINTS_EQUAL (overlap, imm16_32s))
3842 UINTS_CLEAR (overlap);
3843 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3844 overlap.bitfield.imm16 = 1;
3846 overlap.bitfield.imm32s = 1;
3848 if (!UINTS_EQUAL (overlap, imm8)
3849 && !UINTS_EQUAL (overlap, imm8s)
3850 && !UINTS_EQUAL (overlap, imm16)
3851 && !UINTS_EQUAL (overlap, imm32)
3852 && !UINTS_EQUAL (overlap, imm32s)
3853 && !UINTS_EQUAL (overlap, imm64))
3855 as_bad (_("no instruction mnemonic suffix given; "
3856 "can't determine immediate size"));
3860 i.types[j] = overlap;
3870 for (j = 0; j < 2; j++)
3871 if (update_imm (j) == 0)
3874 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
3875 assert (operand_type_check (i.types[2], imm) == 0);
3883 i.drex.modrm_reg = None;
3884 i.drex.modrm_regmem = None;
3886 /* SSE5 4 operand instructions must have the destination the same as
3887 one of the inputs. Figure out the destination register and cache
3888 it away in the drex field, and remember which fields to use for
3890 if (i.tm.opcode_modifier.drex
3891 && i.tm.opcode_modifier.drexv
3894 i.tm.extension_opcode = None;
3896 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3897 if (i.types[0].bitfield.regxmm != 0
3898 && i.types[1].bitfield.regxmm != 0
3899 && i.types[2].bitfield.regxmm != 0
3900 && i.types[3].bitfield.regxmm != 0
3901 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3902 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3904 /* Clear the arguments that are stored in drex. */
3905 UINTS_CLEAR (i.types[0]);
3906 UINTS_CLEAR (i.types[3]);
3907 i.reg_operands -= 2;
3909 /* There are two different ways to encode a 4 operand
3910 instruction with all registers that uses OC1 set to
3911 0 or 1. Favor setting OC1 to 0 since this mimics the
3912 actions of other SSE5 assemblers. Use modrm encoding 2
3913 for register/register. Include the high order bit that
3914 is normally stored in the REX byte in the register
3916 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3917 i.drex.modrm_reg = 2;
3918 i.drex.modrm_regmem = 1;
3919 i.drex.reg = (i.op[3].regs->reg_num
3920 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3923 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3924 else if (i.types[0].bitfield.regxmm != 0
3925 && i.types[1].bitfield.regxmm != 0
3926 && (i.types[2].bitfield.regxmm
3927 || operand_type_check (i.types[2], anymem))
3928 && i.types[3].bitfield.regxmm != 0
3929 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3930 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3932 /* clear the arguments that are stored in drex */
3933 UINTS_CLEAR (i.types[0]);
3934 UINTS_CLEAR (i.types[3]);
3935 i.reg_operands -= 2;
3937 /* Specify the modrm encoding for memory addressing. Include
3938 the high order bit that is normally stored in the REX byte
3939 in the register field. */
3940 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3941 i.drex.modrm_reg = 1;
3942 i.drex.modrm_regmem = 2;
3943 i.drex.reg = (i.op[3].regs->reg_num
3944 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3947 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3948 else if (i.types[0].bitfield.regxmm != 0
3949 && operand_type_check (i.types[1], anymem) != 0
3950 && i.types[2].bitfield.regxmm != 0
3951 && i.types[3].bitfield.regxmm != 0
3952 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3953 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3955 /* Clear the arguments that are stored in drex. */
3956 UINTS_CLEAR (i.types[0]);
3957 UINTS_CLEAR (i.types[3]);
3958 i.reg_operands -= 2;
3960 /* Specify the modrm encoding for memory addressing. Include
3961 the high order bit that is normally stored in the REX byte
3962 in the register field. */
3963 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3964 i.drex.modrm_reg = 2;
3965 i.drex.modrm_regmem = 1;
3966 i.drex.reg = (i.op[3].regs->reg_num
3967 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3970 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3971 else if (i.types[0].bitfield.regxmm != 0
3972 && i.types[1].bitfield.regxmm != 0
3973 && i.types[2].bitfield.regxmm != 0
3974 && i.types[3].bitfield.regxmm != 0
3975 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3976 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3978 /* clear the arguments that are stored in drex */
3979 UINTS_CLEAR (i.types[2]);
3980 UINTS_CLEAR (i.types[3]);
3981 i.reg_operands -= 2;
3983 /* There are two different ways to encode a 4 operand
3984 instruction with all registers that uses OC1 set to
3985 0 or 1. Favor setting OC1 to 0 since this mimics the
3986 actions of other SSE5 assemblers. Use modrm encoding
3987 2 for register/register. Include the high order bit that
3988 is normally stored in the REX byte in the register
3990 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3991 i.drex.modrm_reg = 1;
3992 i.drex.modrm_regmem = 0;
3994 /* Remember the register, including the upper bits */
3995 i.drex.reg = (i.op[3].regs->reg_num
3996 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3999 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4000 else if (i.types[0].bitfield.regxmm != 0
4001 && (i.types[1].bitfield.regxmm
4002 || operand_type_check (i.types[1], anymem))
4003 && i.types[2].bitfield.regxmm != 0
4004 && i.types[3].bitfield.regxmm != 0
4005 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4006 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4008 /* Clear the arguments that are stored in drex. */
4009 UINTS_CLEAR (i.types[2]);
4010 UINTS_CLEAR (i.types[3]);
4011 i.reg_operands -= 2;
4013 /* Specify the modrm encoding and remember the register
4014 including the bits normally stored in the REX byte. */
4015 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4016 i.drex.modrm_reg = 0;
4017 i.drex.modrm_regmem = 1;
4018 i.drex.reg = (i.op[3].regs->reg_num
4019 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4022 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4023 else if (operand_type_check (i.types[0], anymem) != 0
4024 && i.types[1].bitfield.regxmm != 0
4025 && i.types[2].bitfield.regxmm != 0
4026 && i.types[3].bitfield.regxmm != 0
4027 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4028 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4030 /* clear the arguments that are stored in drex */
4031 UINTS_CLEAR (i.types[2]);
4032 UINTS_CLEAR (i.types[3]);
4033 i.reg_operands -= 2;
4035 /* Specify the modrm encoding and remember the register
4036 including the bits normally stored in the REX byte. */
4037 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4038 i.drex.modrm_reg = 1;
4039 i.drex.modrm_regmem = 0;
4040 i.drex.reg = (i.op[3].regs->reg_num
4041 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4045 as_bad (_("Incorrect operands for the '%s' instruction"),
4049 /* SSE5 instructions with the DREX byte where the only memory operand
4050 is in the 2nd argument, and the first and last xmm register must
4051 match, and is encoded in the DREX byte. */
4052 else if (i.tm.opcode_modifier.drex
4053 && !i.tm.opcode_modifier.drexv
4056 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4057 if (i.types[0].bitfield.regxmm != 0
4058 && (i.types[1].bitfield.regxmm
4059 || operand_type_check(i.types[1], anymem))
4060 && i.types[2].bitfield.regxmm != 0
4061 && i.types[3].bitfield.regxmm != 0
4062 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4063 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4065 /* clear the arguments that are stored in drex */
4066 UINTS_CLEAR (i.types[0]);
4067 UINTS_CLEAR (i.types[3]);
4068 i.reg_operands -= 2;
4070 /* Specify the modrm encoding and remember the register
4071 including the high bit normally stored in the REX
4073 i.drex.modrm_reg = 2;
4074 i.drex.modrm_regmem = 1;
4075 i.drex.reg = (i.op[3].regs->reg_num
4076 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4080 as_bad (_("Incorrect operands for the '%s' instruction"),
4084 /* SSE5 3 operand instructions that the result is a register, being
4085 either operand can be a memory operand, using OC0 to note which
4086 one is the memory. */
4087 else if (i.tm.opcode_modifier.drex
4088 && i.tm.opcode_modifier.drexv
4091 i.tm.extension_opcode = None;
4093 /* Case 1: 3 operand insn, src1 = register. */
4094 if (i.types[0].bitfield.regxmm != 0
4095 && i.types[1].bitfield.regxmm != 0
4096 && i.types[2].bitfield.regxmm != 0)
4098 /* Clear the arguments that are stored in drex. */
4099 UINTS_CLEAR (i.types[2]);
4102 /* Specify the modrm encoding and remember the register
4103 including the high bit normally stored in the REX byte. */
4104 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4105 i.drex.modrm_reg = 1;
4106 i.drex.modrm_regmem = 0;
4107 i.drex.reg = (i.op[2].regs->reg_num
4108 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4111 /* Case 2: 3 operand insn, src1 = memory. */
4112 else if (operand_type_check (i.types[0], anymem) != 0
4113 && i.types[1].bitfield.regxmm != 0
4114 && i.types[2].bitfield.regxmm != 0)
4116 /* Clear the arguments that are stored in drex. */
4117 UINTS_CLEAR (i.types[2]);
4120 /* Specify the modrm encoding and remember the register
4121 including the high bit normally stored in the REX
4123 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4124 i.drex.modrm_reg = 1;
4125 i.drex.modrm_regmem = 0;
4126 i.drex.reg = (i.op[2].regs->reg_num
4127 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4130 /* Case 3: 3 operand insn, src2 = memory. */
4131 else if (i.types[0].bitfield.regxmm != 0
4132 && operand_type_check (i.types[1], anymem) != 0
4133 && i.types[2].bitfield.regxmm != 0)
4135 /* Clear the arguments that are stored in drex. */
4136 UINTS_CLEAR (i.types[2]);
4139 /* Specify the modrm encoding and remember the register
4140 including the high bit normally stored in the REX byte. */
4141 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4142 i.drex.modrm_reg = 0;
4143 i.drex.modrm_regmem = 1;
4144 i.drex.reg = (i.op[2].regs->reg_num
4145 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4149 as_bad (_("Incorrect operands for the '%s' instruction"),
4153 /* SSE5 4 operand instructions that are the comparison instructions
4154 where the first operand is the immediate value of the comparison
4156 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4158 /* Case 1: 4 operand insn, src1 = reg/memory. */
4159 if (operand_type_check (i.types[0], imm) != 0
4160 && (i.types[1].bitfield.regxmm
4161 || operand_type_check (i.types[1], anymem))
4162 && i.types[2].bitfield.regxmm != 0
4163 && i.types[3].bitfield.regxmm != 0)
4165 /* clear the arguments that are stored in drex */
4166 UINTS_CLEAR (i.types[3]);
4169 /* Specify the modrm encoding and remember the register
4170 including the high bit normally stored in the REX byte. */
4171 i.drex.modrm_reg = 2;
4172 i.drex.modrm_regmem = 1;
4173 i.drex.reg = (i.op[3].regs->reg_num
4174 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4177 /* Case 2: 3 operand insn with ImmExt that places the
4178 opcode_extension as an immediate argument. This is used for
4179 all of the varients of comparison that supplies the appropriate
4180 value as part of the instruction. */
4181 else if ((i.types[0].bitfield.regxmm
4182 || operand_type_check (i.types[0], anymem))
4183 && i.types[1].bitfield.regxmm != 0
4184 && i.types[2].bitfield.regxmm != 0
4185 && operand_type_check (i.types[3], imm) != 0)
4187 /* clear the arguments that are stored in drex */
4188 UINTS_CLEAR (i.types[2]);
4191 /* Specify the modrm encoding and remember the register
4192 including the high bit normally stored in the REX byte. */
4193 i.drex.modrm_reg = 1;
4194 i.drex.modrm_regmem = 0;
4195 i.drex.reg = (i.op[2].regs->reg_num
4196 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4200 as_bad (_("Incorrect operands for the '%s' instruction"),
4204 else if (i.tm.opcode_modifier.drex
4205 || i.tm.opcode_modifier.drexv
4206 || i.tm.opcode_modifier.drexc)
4207 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4211 process_operands (void)
4213 /* Default segment register this instruction will use for memory
4214 accesses. 0 means unknown. This is only for optimizing out
4215 unnecessary segment overrides. */
4216 const seg_entry *default_seg = 0;
4218 /* Handle all of the DREX munging that SSE5 needs. */
4219 if (i.tm.opcode_modifier.drex
4220 || i.tm.opcode_modifier.drexv
4221 || i.tm.opcode_modifier.drexc)
4224 /* The imul $imm, %reg instruction is converted into
4225 imul $imm, %reg, %reg, and the clr %reg instruction
4226 is converted into xor %reg, %reg. */
4227 if (i.tm.opcode_modifier.regkludge)
4229 if (i.tm.cpu_flags.bitfield.cpusse4_1)
4231 /* The first operand in instruction blendvpd, blendvps and
4232 pblendvb in SSE4.1 is implicit and must be xmm0. */
4233 assert (i.operands == 3
4234 && i.reg_operands >= 2
4235 && UINTS_EQUAL (i.types[0], regxmm));
4236 if (i.op[0].regs->reg_num != 0)
4239 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4240 i.tm.name, register_prefix);
4242 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4243 i.tm.name, register_prefix);
4248 i.types[0] = i.types[1];
4249 i.types[1] = i.types[2];
4253 /* We need to adjust fields in i.tm since they are used by
4254 build_modrm_byte. */
4255 i.tm.operand_types [0] = i.tm.operand_types [1];
4256 i.tm.operand_types [1] = i.tm.operand_types [2];
4261 unsigned int first_reg_op;
4263 if (operand_type_check (i.types[0], reg))
4267 /* Pretend we saw the extra register operand. */
4268 assert (i.reg_operands == 1
4269 && i.op[first_reg_op + 1].regs == 0);
4270 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4271 i.types[first_reg_op + 1] = i.types[first_reg_op];
4277 if (i.tm.opcode_modifier.shortform)
4279 if (i.types[0].bitfield.sreg2
4280 || i.types[0].bitfield.sreg3)
4282 if (i.tm.base_opcode == POP_SEG_SHORT
4283 && i.op[0].regs->reg_num == 1)
4285 as_bad (_("you can't `pop %%cs'"));
4288 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4289 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4294 /* The register or float register operand is in operand
4298 if (i.types[0].bitfield.floatreg
4299 || operand_type_check (i.types[0], reg))
4303 /* Register goes in low 3 bits of opcode. */
4304 i.tm.base_opcode |= i.op[op].regs->reg_num;
4305 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4307 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4309 /* Warn about some common errors, but press on regardless.
4310 The first case can be generated by gcc (<= 2.8.1). */
4311 if (i.operands == 2)
4313 /* Reversed arguments on faddp, fsubp, etc. */
4314 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4315 register_prefix, i.op[1].regs->reg_name,
4316 register_prefix, i.op[0].regs->reg_name);
4320 /* Extraneous `l' suffix on fp insn. */
4321 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4322 register_prefix, i.op[0].regs->reg_name);
4327 else if (i.tm.opcode_modifier.modrm)
4329 /* The opcode is completed (modulo i.tm.extension_opcode which
4330 must be put into the modrm byte). Now, we make the modrm and
4331 index base bytes based on all the info we've collected. */
4333 default_seg = build_modrm_byte ();
4335 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4339 else if (i.tm.opcode_modifier.isstring)
4341 /* For the string instructions that allow a segment override
4342 on one of their operands, the default segment is ds. */
4346 if (i.tm.base_opcode == 0x8d /* lea */
4349 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4351 /* If a segment was explicitly specified, and the specified segment
4352 is not the default, use an opcode prefix to select it. If we
4353 never figured out what the default segment is, then default_seg
4354 will be zero at this point, and the specified segment prefix will
4356 if ((i.seg[0]) && (i.seg[0] != default_seg))
4358 if (!add_prefix (i.seg[0]->seg_prefix))
4364 static const seg_entry *
4365 build_modrm_byte (void)
4367 const seg_entry *default_seg = 0;
4369 /* SSE5 4 operand instructions are encoded in such a way that one of
4370 the inputs must match the destination register. Process_drex hides
4371 the 3rd argument in the drex field, so that by the time we get
4372 here, it looks to GAS as if this is a 2 operand instruction. */
4373 if ((i.tm.opcode_modifier.drex
4374 || i.tm.opcode_modifier.drexv
4375 || i.tm.opcode_modifier.drexc)
4376 && i.reg_operands == 2)
4378 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4379 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4381 i.rm.reg = reg->reg_num;
4382 i.rm.regmem = regmem->reg_num;
4384 if ((reg->reg_flags & RegRex) != 0)
4386 if ((regmem->reg_flags & RegRex) != 0)
4390 /* i.reg_operands MUST be the number of real register operands;
4391 implicit registers do not count. */
4392 else if (i.reg_operands == 2)
4394 unsigned int source, dest;
4402 /* When there are 3 operands, one of them may be immediate,
4403 which may be the first or the last operand. Otherwise,
4404 the first operand must be shift count register (cl). */
4405 assert (i.imm_operands == 1
4406 || (i.imm_operands == 0
4407 && i.types[0].bitfield.shiftcount));
4408 if (operand_type_check (i.types[0], imm)
4409 || i.types[0].bitfield.shiftcount)
4415 /* When there are 4 operands, the first two must be immediate
4416 operands. The source operand will be the 3rd one. */
4417 assert (i.imm_operands == 2
4418 && operand_type_check (i.types[0], imm)
4419 && operand_type_check (i.types[1], imm));
4429 /* One of the register operands will be encoded in the i.tm.reg
4430 field, the other in the combined i.tm.mode and i.tm.regmem
4431 fields. If no form of this instruction supports a memory
4432 destination operand, then we assume the source operand may
4433 sometimes be a memory operand and so we need to store the
4434 destination in the i.rm.reg field. */
4435 if (!i.tm.operand_types[dest].bitfield.regmem
4436 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4438 i.rm.reg = i.op[dest].regs->reg_num;
4439 i.rm.regmem = i.op[source].regs->reg_num;
4440 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4442 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4447 i.rm.reg = i.op[source].regs->reg_num;
4448 i.rm.regmem = i.op[dest].regs->reg_num;
4449 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4451 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4454 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4456 if (!i.types[0].bitfield.control
4457 && !i.types[1].bitfield.control)
4459 i.rex &= ~(REX_R | REX_B);
4460 add_prefix (LOCK_PREFIX_OPCODE);
4464 { /* If it's not 2 reg operands... */
4467 unsigned int fake_zero_displacement = 0;
4470 /* This has been precalculated for SSE5 instructions
4471 that have a DREX field earlier in process_drex. */
4472 if (i.tm.opcode_modifier.drex
4473 || i.tm.opcode_modifier.drexv
4474 || i.tm.opcode_modifier.drexc)
4475 op = i.drex.modrm_regmem;
4478 for (op = 0; op < i.operands; op++)
4479 if (operand_type_check (i.types[op], anymem))
4481 assert (op < i.operands);
4486 if (i.base_reg == 0)
4489 if (!i.disp_operands)
4490 fake_zero_displacement = 1;
4491 if (i.index_reg == 0)
4493 /* Operand is just <disp> */
4494 if (flag_code == CODE_64BIT)
4496 /* 64bit mode overwrites the 32bit absolute
4497 addressing by RIP relative addressing and
4498 absolute addressing is encoded by one of the
4499 redundant SIB forms. */
4500 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4501 i.sib.base = NO_BASE_REGISTER;
4502 i.sib.index = NO_INDEX_REGISTER;
4503 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4504 ? disp32s : disp32);
4506 else if ((flag_code == CODE_16BIT)
4507 ^ (i.prefix[ADDR_PREFIX] != 0))
4509 i.rm.regmem = NO_BASE_REGISTER_16;
4510 i.types[op] = disp16;
4514 i.rm.regmem = NO_BASE_REGISTER;
4515 i.types[op] = disp32;
4518 else /* !i.base_reg && i.index_reg */
4520 i.sib.index = i.index_reg->reg_num;
4521 i.sib.base = NO_BASE_REGISTER;
4522 i.sib.scale = i.log2_scale_factor;
4523 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4524 i.types[op].bitfield.disp8 = 0;
4525 i.types[op].bitfield.disp16 = 0;
4526 i.types[op].bitfield.disp64 = 0;
4527 if (flag_code != CODE_64BIT)
4529 /* Must be 32 bit */
4530 i.types[op].bitfield.disp32 = 1;
4531 i.types[op].bitfield.disp32s = 0;
4535 i.types[op].bitfield.disp32 = 0;
4536 i.types[op].bitfield.disp32s = 1;
4538 if ((i.index_reg->reg_flags & RegRex) != 0)
4542 /* RIP addressing for 64bit mode. */
4543 else if (i.base_reg->reg_num == RegRip)
4545 i.rm.regmem = NO_BASE_REGISTER;
4546 i.types[op].bitfield.disp8 = 0;
4547 i.types[op].bitfield.disp16 = 0;
4548 i.types[op].bitfield.disp32 = 0;
4549 i.types[op].bitfield.disp32s = 1;
4550 i.types[op].bitfield.disp64 = 0;
4551 i.flags[op] |= Operand_PCrel;
4552 if (! i.disp_operands)
4553 fake_zero_displacement = 1;
4555 else if (i.base_reg->reg_type.bitfield.reg16)
4557 switch (i.base_reg->reg_num)
4560 if (i.index_reg == 0)
4562 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4563 i.rm.regmem = i.index_reg->reg_num - 6;
4567 if (i.index_reg == 0)
4570 if (operand_type_check (i.types[op], disp) == 0)
4572 /* fake (%bp) into 0(%bp) */
4573 i.types[op].bitfield.disp8 = 1;
4574 fake_zero_displacement = 1;
4577 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4578 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4580 default: /* (%si) -> 4 or (%di) -> 5 */
4581 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4583 i.rm.mode = mode_from_disp_size (i.types[op]);
4585 else /* i.base_reg and 32/64 bit mode */
4587 if (flag_code == CODE_64BIT
4588 && operand_type_check (i.types[op], disp))
4590 i386_operand_type temp;
4592 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4594 if (i.prefix[ADDR_PREFIX] == 0)
4595 i.types[op].bitfield.disp32s = 1;
4597 i.types[op].bitfield.disp32 = 1;
4600 i.rm.regmem = i.base_reg->reg_num;
4601 if ((i.base_reg->reg_flags & RegRex) != 0)
4603 i.sib.base = i.base_reg->reg_num;
4604 /* x86-64 ignores REX prefix bit here to avoid decoder
4606 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4609 if (i.disp_operands == 0)
4611 fake_zero_displacement = 1;
4612 i.types[op].bitfield.disp8 = 1;
4615 else if (i.base_reg->reg_num == ESP_REG_NUM)
4619 i.sib.scale = i.log2_scale_factor;
4620 if (i.index_reg == 0)
4622 /* <disp>(%esp) becomes two byte modrm with no index
4623 register. We've already stored the code for esp
4624 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4625 Any base register besides %esp will not use the
4626 extra modrm byte. */
4627 i.sib.index = NO_INDEX_REGISTER;
4628 #if !SCALE1_WHEN_NO_INDEX
4629 /* Another case where we force the second modrm
4631 if (i.log2_scale_factor)
4632 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4637 i.sib.index = i.index_reg->reg_num;
4638 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4639 if ((i.index_reg->reg_flags & RegRex) != 0)
4644 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4645 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4648 i.rm.mode = mode_from_disp_size (i.types[op]);
4651 if (fake_zero_displacement)
4653 /* Fakes a zero displacement assuming that i.types[op]
4654 holds the correct displacement size. */
4657 assert (i.op[op].disps == 0);
4658 exp = &disp_expressions[i.disp_operands++];
4659 i.op[op].disps = exp;
4660 exp->X_op = O_constant;
4661 exp->X_add_number = 0;
4662 exp->X_add_symbol = (symbolS *) 0;
4663 exp->X_op_symbol = (symbolS *) 0;
4667 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4668 (if any) based on i.tm.extension_opcode. Again, we must be
4669 careful to make sure that segment/control/debug/test/MMX
4670 registers are coded into the i.rm.reg field. */
4675 /* This has been precalculated for SSE5 instructions
4676 that have a DREX field earlier in process_drex. */
4677 if (i.tm.opcode_modifier.drex
4678 || i.tm.opcode_modifier.drexv
4679 || i.tm.opcode_modifier.drexc)
4681 op = i.drex.modrm_reg;
4682 i.rm.reg = i.op[op].regs->reg_num;
4683 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4688 for (op = 0; op < i.operands; op++)
4689 if (i.types[op].bitfield.reg8
4690 || i.types[op].bitfield.reg16
4691 || i.types[op].bitfield.reg32
4692 || i.types[op].bitfield.reg64
4693 || i.types[op].bitfield.regmmx
4694 || i.types[op].bitfield.regxmm
4695 || i.types[op].bitfield.sreg2
4696 || i.types[op].bitfield.sreg3
4697 || i.types[op].bitfield.control
4698 || i.types[op].bitfield.debug
4699 || i.types[op].bitfield.test)
4702 assert (op < i.operands);
4704 /* If there is an extension opcode to put here, the
4705 register number must be put into the regmem field. */
4706 if (i.tm.extension_opcode != None)
4708 i.rm.regmem = i.op[op].regs->reg_num;
4709 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4714 i.rm.reg = i.op[op].regs->reg_num;
4715 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4720 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4721 must set it to 3 to indicate this is a register operand
4722 in the regmem field. */
4723 if (!i.mem_operands)
4727 /* Fill in i.rm.reg field with extension opcode (if any). */
4728 if (i.tm.extension_opcode != None
4729 && !(i.tm.opcode_modifier.drex
4730 || i.tm.opcode_modifier.drexv
4731 || i.tm.opcode_modifier.drexc))
4732 i.rm.reg = i.tm.extension_opcode;
4738 output_branch (void)
4743 relax_substateT subtype;
4748 if (flag_code == CODE_16BIT)
4752 if (i.prefix[DATA_PREFIX] != 0)
4758 /* Pentium4 branch hints. */
4759 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4760 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4765 if (i.prefix[REX_PREFIX] != 0)
4771 if (i.prefixes != 0 && !intel_syntax)
4772 as_warn (_("skipping prefixes on this instruction"));
4774 /* It's always a symbol; End frag & setup for relax.
4775 Make sure there is enough room in this frag for the largest
4776 instruction we may generate in md_convert_frag. This is 2
4777 bytes for the opcode and room for the prefix and largest
4779 frag_grow (prefix + 2 + 4);
4780 /* Prefix and 1 opcode byte go in fr_fix. */
4781 p = frag_more (prefix + 1);
4782 if (i.prefix[DATA_PREFIX] != 0)
4783 *p++ = DATA_PREFIX_OPCODE;
4784 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4785 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4786 *p++ = i.prefix[SEG_PREFIX];
4787 if (i.prefix[REX_PREFIX] != 0)
4788 *p++ = i.prefix[REX_PREFIX];
4789 *p = i.tm.base_opcode;
4791 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4792 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
4793 else if (cpu_arch_flags.bitfield.cpui386)
4794 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4796 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4799 sym = i.op[0].disps->X_add_symbol;
4800 off = i.op[0].disps->X_add_number;
4802 if (i.op[0].disps->X_op != O_constant
4803 && i.op[0].disps->X_op != O_symbol)
4805 /* Handle complex expressions. */
4806 sym = make_expr_symbol (i.op[0].disps);
4810 /* 1 possible extra opcode + 4 byte displacement go in var part.
4811 Pass reloc in fr_var. */
4812 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4822 if (i.tm.opcode_modifier.jumpbyte)
4824 /* This is a loop or jecxz type instruction. */
4826 if (i.prefix[ADDR_PREFIX] != 0)
4828 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4831 /* Pentium4 branch hints. */
4832 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4833 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4835 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4844 if (flag_code == CODE_16BIT)
4847 if (i.prefix[DATA_PREFIX] != 0)
4849 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4859 if (i.prefix[REX_PREFIX] != 0)
4861 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4865 if (i.prefixes != 0 && !intel_syntax)
4866 as_warn (_("skipping prefixes on this instruction"));
4868 p = frag_more (1 + size);
4869 *p++ = i.tm.base_opcode;
4871 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4872 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4874 /* All jumps handled here are signed, but don't use a signed limit
4875 check for 32 and 16 bit jumps as we want to allow wrap around at
4876 4G and 64k respectively. */
4878 fixP->fx_signed = 1;
4882 output_interseg_jump (void)
4890 if (flag_code == CODE_16BIT)
4894 if (i.prefix[DATA_PREFIX] != 0)
4900 if (i.prefix[REX_PREFIX] != 0)
4910 if (i.prefixes != 0 && !intel_syntax)
4911 as_warn (_("skipping prefixes on this instruction"));
4913 /* 1 opcode; 2 segment; offset */
4914 p = frag_more (prefix + 1 + 2 + size);
4916 if (i.prefix[DATA_PREFIX] != 0)
4917 *p++ = DATA_PREFIX_OPCODE;
4919 if (i.prefix[REX_PREFIX] != 0)
4920 *p++ = i.prefix[REX_PREFIX];
4922 *p++ = i.tm.base_opcode;
4923 if (i.op[1].imms->X_op == O_constant)
4925 offsetT n = i.op[1].imms->X_add_number;
4928 && !fits_in_unsigned_word (n)
4929 && !fits_in_signed_word (n))
4931 as_bad (_("16-bit jump out of range"));
4934 md_number_to_chars (p, n, size);
4937 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4938 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4939 if (i.op[0].imms->X_op != O_constant)
4940 as_bad (_("can't handle non absolute segment in `%s'"),
4942 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4948 fragS *insn_start_frag;
4949 offsetT insn_start_off;
4951 /* Tie dwarf2 debug info to the address at the start of the insn.
4952 We can't do this after the insn has been output as the current
4953 frag may have been closed off. eg. by frag_var. */
4954 dwarf2_emit_insn (0);
4956 insn_start_frag = frag_now;
4957 insn_start_off = frag_now_fix ();
4960 if (i.tm.opcode_modifier.jump)
4962 else if (i.tm.opcode_modifier.jumpbyte
4963 || i.tm.opcode_modifier.jumpdword)
4965 else if (i.tm.opcode_modifier.jumpintersegment)
4966 output_interseg_jump ();
4969 /* Output normal instructions here. */
4972 unsigned int prefix;
4975 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4976 SSE4 and SSE5 instructions have 3 bytes. We may use one
4977 more higher byte to specify a prefix the instruction
4978 requires. Exclude instructions which are in both SSE4.2
4980 opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
4981 || i.tm.cpu_flags.bitfield.cpusse5
4982 || i.tm.cpu_flags.bitfield.cpusse4_1
4983 || (i.tm.cpu_flags.bitfield.cpusse4_2
4984 && !i.tm.cpu_flags.bitfield.cpuabm));
4987 if (i.tm.base_opcode & 0xff000000)
4989 prefix = (i.tm.base_opcode >> 24) & 0xff;
4993 else if ((i.tm.base_opcode & 0xff0000) != 0)
4995 prefix = (i.tm.base_opcode >> 16) & 0xff;
4996 if (i.tm.cpu_flags.bitfield.cpupadlock)
4999 if (prefix != REPE_PREFIX_OPCODE
5000 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5001 add_prefix (prefix);
5004 add_prefix (prefix);
5007 /* The prefix bytes. */
5009 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5015 md_number_to_chars (p, (valueT) *q, 1);
5019 /* Now the opcode; be careful about word order here! */
5020 if (fits_in_unsigned_byte (i.tm.base_opcode))
5022 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5029 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5034 /* Put out high byte first: can't use md_number_to_chars! */
5035 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5036 *p = i.tm.base_opcode & 0xff;
5038 /* On SSE5, encode the OC1 bit in the DREX field if this
5039 encoding has multiple formats. */
5040 if (i.tm.opcode_modifier.drex
5041 && i.tm.opcode_modifier.drexv
5042 && DREX_OC1 (i.tm.extension_opcode))
5043 *p |= DREX_OC1_MASK;
5046 /* Now the modrm byte and sib byte (if present). */
5047 if (i.tm.opcode_modifier.modrm)
5050 md_number_to_chars (p,
5051 (valueT) (i.rm.regmem << 0
5055 /* If i.rm.regmem == ESP (4)
5056 && i.rm.mode != (Register mode)
5058 ==> need second modrm byte. */
5059 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5061 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5064 md_number_to_chars (p,
5065 (valueT) (i.sib.base << 0
5067 | i.sib.scale << 6),
5072 /* Write the DREX byte if needed. */
5073 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5076 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5078 /* Encode the OC0 bit if this encoding has multiple
5080 if ((i.tm.opcode_modifier.drex
5081 || i.tm.opcode_modifier.drexv)
5082 && DREX_OC0 (i.tm.extension_opcode))
5083 *p |= DREX_OC0_MASK;
5086 if (i.disp_operands)
5087 output_disp (insn_start_frag, insn_start_off);
5090 output_imm (insn_start_frag, insn_start_off);
5096 pi ("" /*line*/, &i);
5098 #endif /* DEBUG386 */
5101 /* Return the size of the displacement operand N. */
5104 disp_size (unsigned int n)
5107 if (i.types[n].bitfield.disp64)
5109 else if (i.types[n].bitfield.disp8)
5111 else if (i.types[n].bitfield.disp16)
5116 /* Return the size of the immediate operand N. */
5119 imm_size (unsigned int n)
5122 if (i.types[n].bitfield.imm64)
5124 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5126 else if (i.types[n].bitfield.imm16)
5132 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5137 for (n = 0; n < i.operands; n++)
5139 if (operand_type_check (i.types[n], disp))
5141 if (i.op[n].disps->X_op == O_constant)
5143 int size = disp_size (n);
5146 val = offset_in_range (i.op[n].disps->X_add_number,
5148 p = frag_more (size);
5149 md_number_to_chars (p, val, size);
5153 enum bfd_reloc_code_real reloc_type;
5154 int size = disp_size (n);
5155 int sign = i.types[n].bitfield.disp32s;
5156 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5158 /* We can't have 8 bit displacement here. */
5159 assert (!i.types[n].bitfield.disp8);
5161 /* The PC relative address is computed relative
5162 to the instruction boundary, so in case immediate
5163 fields follows, we need to adjust the value. */
5164 if (pcrel && i.imm_operands)
5169 for (n1 = 0; n1 < i.operands; n1++)
5170 if (operand_type_check (i.types[n1], imm))
5172 /* Only one immediate is allowed for PC
5173 relative address. */
5176 i.op[n].disps->X_add_number -= sz;
5178 /* We should find the immediate. */
5182 p = frag_more (size);
5183 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5185 && GOT_symbol == i.op[n].disps->X_add_symbol
5186 && (((reloc_type == BFD_RELOC_32
5187 || reloc_type == BFD_RELOC_X86_64_32S
5188 || (reloc_type == BFD_RELOC_64
5190 && (i.op[n].disps->X_op == O_symbol
5191 || (i.op[n].disps->X_op == O_add
5192 && ((symbol_get_value_expression
5193 (i.op[n].disps->X_op_symbol)->X_op)
5195 || reloc_type == BFD_RELOC_32_PCREL))
5199 if (insn_start_frag == frag_now)
5200 add = (p - frag_now->fr_literal) - insn_start_off;
5205 add = insn_start_frag->fr_fix - insn_start_off;
5206 for (fr = insn_start_frag->fr_next;
5207 fr && fr != frag_now; fr = fr->fr_next)
5209 add += p - frag_now->fr_literal;
5214 reloc_type = BFD_RELOC_386_GOTPC;
5215 i.op[n].imms->X_add_number += add;
5217 else if (reloc_type == BFD_RELOC_64)
5218 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5220 /* Don't do the adjustment for x86-64, as there
5221 the pcrel addressing is relative to the _next_
5222 insn, and that is taken care of in other code. */
5223 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5225 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5226 i.op[n].disps, pcrel, reloc_type);
5233 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5238 for (n = 0; n < i.operands; n++)
5240 if (operand_type_check (i.types[n], imm))
5242 if (i.op[n].imms->X_op == O_constant)
5244 int size = imm_size (n);
5247 val = offset_in_range (i.op[n].imms->X_add_number,
5249 p = frag_more (size);
5250 md_number_to_chars (p, val, size);
5254 /* Not absolute_section.
5255 Need a 32-bit fixup (don't support 8bit
5256 non-absolute imms). Try to support other
5258 enum bfd_reloc_code_real reloc_type;
5259 int size = imm_size (n);
5262 if (i.types[n].bitfield.imm32s
5263 && (i.suffix == QWORD_MNEM_SUFFIX
5264 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5269 p = frag_more (size);
5270 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5272 /* This is tough to explain. We end up with this one if we
5273 * have operands that look like
5274 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5275 * obtain the absolute address of the GOT, and it is strongly
5276 * preferable from a performance point of view to avoid using
5277 * a runtime relocation for this. The actual sequence of
5278 * instructions often look something like:
5283 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5285 * The call and pop essentially return the absolute address
5286 * of the label .L66 and store it in %ebx. The linker itself
5287 * will ultimately change the first operand of the addl so
5288 * that %ebx points to the GOT, but to keep things simple, the
5289 * .o file must have this operand set so that it generates not
5290 * the absolute address of .L66, but the absolute address of
5291 * itself. This allows the linker itself simply treat a GOTPC
5292 * relocation as asking for a pcrel offset to the GOT to be
5293 * added in, and the addend of the relocation is stored in the
5294 * operand field for the instruction itself.
5296 * Our job here is to fix the operand so that it would add
5297 * the correct offset so that %ebx would point to itself. The
5298 * thing that is tricky is that .-.L66 will point to the
5299 * beginning of the instruction, so we need to further modify
5300 * the operand so that it will point to itself. There are
5301 * other cases where you have something like:
5303 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5305 * and here no correction would be required. Internally in
5306 * the assembler we treat operands of this form as not being
5307 * pcrel since the '.' is explicitly mentioned, and I wonder
5308 * whether it would simplify matters to do it this way. Who
5309 * knows. In earlier versions of the PIC patches, the
5310 * pcrel_adjust field was used to store the correction, but
5311 * since the expression is not pcrel, I felt it would be
5312 * confusing to do it this way. */
5314 if ((reloc_type == BFD_RELOC_32
5315 || reloc_type == BFD_RELOC_X86_64_32S
5316 || reloc_type == BFD_RELOC_64)
5318 && GOT_symbol == i.op[n].imms->X_add_symbol
5319 && (i.op[n].imms->X_op == O_symbol
5320 || (i.op[n].imms->X_op == O_add
5321 && ((symbol_get_value_expression
5322 (i.op[n].imms->X_op_symbol)->X_op)
5327 if (insn_start_frag == frag_now)
5328 add = (p - frag_now->fr_literal) - insn_start_off;
5333 add = insn_start_frag->fr_fix - insn_start_off;
5334 for (fr = insn_start_frag->fr_next;
5335 fr && fr != frag_now; fr = fr->fr_next)
5337 add += p - frag_now->fr_literal;
5341 reloc_type = BFD_RELOC_386_GOTPC;
5343 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5345 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5346 i.op[n].imms->X_add_number += add;
5348 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5349 i.op[n].imms, 0, reloc_type);
5355 /* x86_cons_fix_new is called via the expression parsing code when a
5356 reloc is needed. We use this hook to get the correct .got reloc. */
5357 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5358 static int cons_sign = -1;
5361 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5364 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5366 got_reloc = NO_RELOC;
5369 if (exp->X_op == O_secrel)
5371 exp->X_op = O_symbol;
5372 r = BFD_RELOC_32_SECREL;
5376 fix_new_exp (frag, off, len, exp, 0, r);
5379 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5380 # define lex_got(reloc, adjust, types) NULL
5382 /* Parse operands of the form
5383 <symbol>@GOTOFF+<nnn>
5384 and similar .plt or .got references.
5386 If we find one, set up the correct relocation in RELOC and copy the
5387 input string, minus the `@GOTOFF' into a malloc'd buffer for
5388 parsing by the calling routine. Return this buffer, and if ADJUST
5389 is non-null set it to the length of the string we removed from the
5390 input line. Otherwise return NULL. */
5392 lex_got (enum bfd_reloc_code_real *reloc,
5394 i386_operand_type *types)
5396 /* Some of the relocations depend on the size of what field is to
5397 be relocated. But in our callers i386_immediate and i386_displacement
5398 we don't yet know the operand size (this will be set by insn
5399 matching). Hence we record the word32 relocation here,
5400 and adjust the reloc according to the real size in reloc(). */
5401 static const struct {
5403 const enum bfd_reloc_code_real rel[2];
5404 const i386_operand_type types64;
5407 BFD_RELOC_X86_64_PLTOFF64 },
5408 OPERAND_TYPE_IMM64 },
5409 { "PLT", { BFD_RELOC_386_PLT32,
5410 BFD_RELOC_X86_64_PLT32 },
5411 OPERAND_TYPE_IMM32_32S_DISP32 },
5413 BFD_RELOC_X86_64_GOTPLT64 },
5414 OPERAND_TYPE_IMM64_DISP64 },
5415 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5416 BFD_RELOC_X86_64_GOTOFF64 },
5417 OPERAND_TYPE_IMM64_DISP64 },
5419 BFD_RELOC_X86_64_GOTPCREL },
5420 OPERAND_TYPE_IMM32_32S_DISP32 },
5421 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5422 BFD_RELOC_X86_64_TLSGD },
5423 OPERAND_TYPE_IMM32_32S_DISP32 },
5424 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5426 OPERAND_TYPE_NONE },
5428 BFD_RELOC_X86_64_TLSLD },
5429 OPERAND_TYPE_IMM32_32S_DISP32 },
5430 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5431 BFD_RELOC_X86_64_GOTTPOFF },
5432 OPERAND_TYPE_IMM32_32S_DISP32 },
5433 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5434 BFD_RELOC_X86_64_TPOFF32 },
5435 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5436 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5438 OPERAND_TYPE_NONE },
5439 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5440 BFD_RELOC_X86_64_DTPOFF32 },
5442 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5443 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5445 OPERAND_TYPE_NONE },
5446 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5448 OPERAND_TYPE_NONE },
5449 { "GOT", { BFD_RELOC_386_GOT32,
5450 BFD_RELOC_X86_64_GOT32 },
5451 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5452 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5453 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5454 OPERAND_TYPE_IMM32_32S_DISP32 },
5455 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5456 BFD_RELOC_X86_64_TLSDESC_CALL },
5457 OPERAND_TYPE_IMM32_32S_DISP32 },
5465 for (cp = input_line_pointer; *cp != '@'; cp++)
5466 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5469 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5473 len = strlen (gotrel[j].str);
5474 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5476 if (gotrel[j].rel[object_64bit] != 0)
5479 char *tmpbuf, *past_reloc;
5481 *reloc = gotrel[j].rel[object_64bit];
5487 if (flag_code != CODE_64BIT)
5489 types->bitfield.imm32 = 1;
5490 types->bitfield.disp32 = 1;
5493 *types = gotrel[j].types64;
5496 if (GOT_symbol == NULL)
5497 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5499 /* The length of the first part of our input line. */
5500 first = cp - input_line_pointer;
5502 /* The second part goes from after the reloc token until
5503 (and including) an end_of_line char or comma. */
5504 past_reloc = cp + 1 + len;
5506 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5508 second = cp + 1 - past_reloc;
5510 /* Allocate and copy string. The trailing NUL shouldn't
5511 be necessary, but be safe. */
5512 tmpbuf = xmalloc (first + second + 2);
5513 memcpy (tmpbuf, input_line_pointer, first);
5514 if (second != 0 && *past_reloc != ' ')
5515 /* Replace the relocation token with ' ', so that
5516 errors like foo@GOTOFF1 will be detected. */
5517 tmpbuf[first++] = ' ';
5518 memcpy (tmpbuf + first, past_reloc, second);
5519 tmpbuf[first + second] = '\0';
5523 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5524 gotrel[j].str, 1 << (5 + object_64bit));
5529 /* Might be a symbol version string. Don't as_bad here. */
5534 x86_cons (expressionS *exp, int size)
5536 if (size == 4 || (object_64bit && size == 8))
5538 /* Handle @GOTOFF and the like in an expression. */
5540 char *gotfree_input_line;
5543 save = input_line_pointer;
5544 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5545 if (gotfree_input_line)
5546 input_line_pointer = gotfree_input_line;
5550 if (gotfree_input_line)
5552 /* expression () has merrily parsed up to the end of line,
5553 or a comma - in the wrong buffer. Transfer how far
5554 input_line_pointer has moved to the right buffer. */
5555 input_line_pointer = (save
5556 + (input_line_pointer - gotfree_input_line)
5558 free (gotfree_input_line);
5559 if (exp->X_op == O_constant
5560 || exp->X_op == O_absent
5561 || exp->X_op == O_illegal
5562 || exp->X_op == O_register
5563 || exp->X_op == O_big)
5565 char c = *input_line_pointer;
5566 *input_line_pointer = 0;
5567 as_bad (_("missing or invalid expression `%s'"), save);
5568 *input_line_pointer = c;
5577 static void signed_cons (int size)
5579 if (flag_code == CODE_64BIT)
5587 pe_directive_secrel (dummy)
5588 int dummy ATTRIBUTE_UNUSED;
5595 if (exp.X_op == O_symbol)
5596 exp.X_op = O_secrel;
5598 emit_expr (&exp, 4);
5600 while (*input_line_pointer++ == ',');
5602 input_line_pointer--;
5603 demand_empty_rest_of_line ();
5608 i386_immediate (char *imm_start)
5610 char *save_input_line_pointer;
5611 char *gotfree_input_line;
5614 i386_operand_type types;
5616 UINTS_SET (types, ~0);
5618 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5620 as_bad (_("at most %d immediate operands are allowed"),
5621 MAX_IMMEDIATE_OPERANDS);
5625 exp = &im_expressions[i.imm_operands++];
5626 i.op[this_operand].imms = exp;
5628 if (is_space_char (*imm_start))
5631 save_input_line_pointer = input_line_pointer;
5632 input_line_pointer = imm_start;
5634 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5635 if (gotfree_input_line)
5636 input_line_pointer = gotfree_input_line;
5638 exp_seg = expression (exp);
5641 if (*input_line_pointer)
5642 as_bad (_("junk `%s' after expression"), input_line_pointer);
5644 input_line_pointer = save_input_line_pointer;
5645 if (gotfree_input_line)
5646 free (gotfree_input_line);
5648 if (exp->X_op == O_absent
5649 || exp->X_op == O_illegal
5650 || exp->X_op == O_big
5651 || (gotfree_input_line
5652 && (exp->X_op == O_constant
5653 || exp->X_op == O_register)))
5655 as_bad (_("missing or invalid immediate expression `%s'"),
5659 else if (exp->X_op == O_constant)
5661 /* Size it properly later. */
5662 i.types[this_operand].bitfield.imm64 = 1;
5663 /* If BFD64, sign extend val. */
5664 if (!use_rela_relocations
5665 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5667 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5669 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5670 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5671 && exp_seg != absolute_section
5672 && exp_seg != text_section
5673 && exp_seg != data_section
5674 && exp_seg != bss_section
5675 && exp_seg != undefined_section
5676 && !bfd_is_com_section (exp_seg))
5678 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5682 else if (!intel_syntax && exp->X_op == O_register)
5684 as_bad (_("illegal immediate register operand %s"), imm_start);
5689 /* This is an address. The size of the address will be
5690 determined later, depending on destination register,
5691 suffix, or the default for the section. */
5692 i.types[this_operand].bitfield.imm8 = 1;
5693 i.types[this_operand].bitfield.imm16 = 1;
5694 i.types[this_operand].bitfield.imm32 = 1;
5695 i.types[this_operand].bitfield.imm32s = 1;
5696 i.types[this_operand].bitfield.imm64 = 1;
5697 i.types[this_operand] = operand_type_and (i.types[this_operand],
5705 i386_scale (char *scale)
5708 char *save = input_line_pointer;
5710 input_line_pointer = scale;
5711 val = get_absolute_expression ();
5716 i.log2_scale_factor = 0;
5719 i.log2_scale_factor = 1;
5722 i.log2_scale_factor = 2;
5725 i.log2_scale_factor = 3;
5729 char sep = *input_line_pointer;
5731 *input_line_pointer = '\0';
5732 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5734 *input_line_pointer = sep;
5735 input_line_pointer = save;
5739 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5741 as_warn (_("scale factor of %d without an index register"),
5742 1 << i.log2_scale_factor);
5743 #if SCALE1_WHEN_NO_INDEX
5744 i.log2_scale_factor = 0;
5747 scale = input_line_pointer;
5748 input_line_pointer = save;
5753 i386_displacement (char *disp_start, char *disp_end)
5757 char *save_input_line_pointer;
5758 char *gotfree_input_line;
5760 i386_operand_type bigdisp, types = anydisp;
5763 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5765 as_bad (_("at most %d displacement operands are allowed"),
5766 MAX_MEMORY_OPERANDS);
5770 UINTS_CLEAR (bigdisp);
5771 if ((i.types[this_operand].bitfield.jumpabsolute)
5772 || (!current_templates->start->opcode_modifier.jump
5773 && !current_templates->start->opcode_modifier.jumpdword))
5775 bigdisp.bitfield.disp32 = 1;
5776 override = (i.prefix[ADDR_PREFIX] != 0);
5777 if (flag_code == CODE_64BIT)
5781 bigdisp.bitfield.disp32s = 1;
5782 bigdisp.bitfield.disp64 = 1;
5785 else if ((flag_code == CODE_16BIT) ^ override)
5787 bigdisp.bitfield.disp32 = 0;
5788 bigdisp.bitfield.disp16 = 1;
5793 /* For PC-relative branches, the width of the displacement
5794 is dependent upon data size, not address size. */
5795 override = (i.prefix[DATA_PREFIX] != 0);
5796 if (flag_code == CODE_64BIT)
5798 if (override || i.suffix == WORD_MNEM_SUFFIX)
5799 bigdisp.bitfield.disp16 = 1;
5802 bigdisp.bitfield.disp32 = 1;
5803 bigdisp.bitfield.disp32s = 1;
5809 override = (i.suffix == (flag_code != CODE_16BIT
5811 : LONG_MNEM_SUFFIX));
5812 bigdisp.bitfield.disp32 = 1;
5813 if ((flag_code == CODE_16BIT) ^ override)
5815 bigdisp.bitfield.disp32 = 0;
5816 bigdisp.bitfield.disp16 = 1;
5820 i.types[this_operand] = operand_type_or (i.types[this_operand],
5823 exp = &disp_expressions[i.disp_operands];
5824 i.op[this_operand].disps = exp;
5826 save_input_line_pointer = input_line_pointer;
5827 input_line_pointer = disp_start;
5828 END_STRING_AND_SAVE (disp_end);
5830 #ifndef GCC_ASM_O_HACK
5831 #define GCC_ASM_O_HACK 0
5834 END_STRING_AND_SAVE (disp_end + 1);
5835 if (i.types[this_operand].bitfield.baseIndex
5836 && displacement_string_end[-1] == '+')
5838 /* This hack is to avoid a warning when using the "o"
5839 constraint within gcc asm statements.
5842 #define _set_tssldt_desc(n,addr,limit,type) \
5843 __asm__ __volatile__ ( \
5845 "movw %w1,2+%0\n\t" \
5847 "movb %b1,4+%0\n\t" \
5848 "movb %4,5+%0\n\t" \
5849 "movb $0,6+%0\n\t" \
5850 "movb %h1,7+%0\n\t" \
5852 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5854 This works great except that the output assembler ends
5855 up looking a bit weird if it turns out that there is
5856 no offset. You end up producing code that looks like:
5869 So here we provide the missing zero. */
5871 *displacement_string_end = '0';
5874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5875 if (gotfree_input_line)
5876 input_line_pointer = gotfree_input_line;
5878 exp_seg = expression (exp);
5881 if (*input_line_pointer)
5882 as_bad (_("junk `%s' after expression"), input_line_pointer);
5884 RESTORE_END_STRING (disp_end + 1);
5886 input_line_pointer = save_input_line_pointer;
5887 if (gotfree_input_line)
5888 free (gotfree_input_line);
5891 /* We do this to make sure that the section symbol is in
5892 the symbol table. We will ultimately change the relocation
5893 to be relative to the beginning of the section. */
5894 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
5895 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5898 if (exp->X_op != O_symbol)
5901 if (S_IS_LOCAL (exp->X_add_symbol)
5902 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5903 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
5904 exp->X_op = O_subtract;
5905 exp->X_op_symbol = GOT_symbol;
5906 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
5907 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
5908 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5909 i.reloc[this_operand] = BFD_RELOC_64;
5911 i.reloc[this_operand] = BFD_RELOC_32;
5914 else if (exp->X_op == O_absent
5915 || exp->X_op == O_illegal
5916 || exp->X_op == O_big
5917 || (gotfree_input_line
5918 && (exp->X_op == O_constant
5919 || exp->X_op == O_register)))
5922 as_bad (_("missing or invalid displacement expression `%s'"),
5927 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5928 else if (exp->X_op != O_constant
5929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5930 && exp_seg != absolute_section
5931 && exp_seg != text_section
5932 && exp_seg != data_section
5933 && exp_seg != bss_section
5934 && exp_seg != undefined_section
5935 && !bfd_is_com_section (exp_seg))
5937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5942 RESTORE_END_STRING (disp_end);
5944 /* Check if this is a displacement only operand. */
5945 bigdisp = i.types[this_operand];
5946 bigdisp.bitfield.disp8 = 0;
5947 bigdisp.bitfield.disp16 = 0;
5948 bigdisp.bitfield.disp32 = 0;
5949 bigdisp.bitfield.disp32s = 0;
5950 bigdisp.bitfield.disp64 = 0;
5951 if (UINTS_ALL_ZERO (bigdisp))
5952 i.types[this_operand] = operand_type_and (i.types[this_operand],
5958 /* Make sure the memory operand we've been dealt is valid.
5959 Return 1 on success, 0 on a failure. */
5962 i386_index_check (const char *operand_string)
5965 #if INFER_ADDR_PREFIX
5971 if (flag_code == CODE_64BIT)
5974 && ((i.prefix[ADDR_PREFIX] == 0
5975 && !i.base_reg->reg_type.bitfield.reg64)
5976 || (i.prefix[ADDR_PREFIX]
5977 && !i.base_reg->reg_type.bitfield.reg32))
5979 || i.base_reg->reg_num != RegRip))
5981 && (!i.index_reg->reg_type.bitfield.baseindex
5982 || (i.prefix[ADDR_PREFIX] == 0
5983 && !i.index_reg->reg_type.bitfield.reg64)
5984 || (i.prefix[ADDR_PREFIX]
5985 && !i.index_reg->reg_type.bitfield.reg32))))
5990 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5994 && (!i.base_reg->reg_type.bitfield.reg16
5995 || !i.base_reg->reg_type.bitfield.baseindex))
5997 && (!i.index_reg->reg_type.bitfield.reg16
5998 || !i.index_reg->reg_type.bitfield.baseindex
6000 && i.base_reg->reg_num < 6
6001 && i.index_reg->reg_num >= 6
6002 && i.log2_scale_factor == 0))))
6009 && !i.base_reg->reg_type.bitfield.reg32)
6011 && (!i.index_reg->reg_type.bitfield.reg32
6012 || !i.index_reg->reg_type.bitfield.baseindex)))
6018 #if INFER_ADDR_PREFIX
6019 if (i.prefix[ADDR_PREFIX] == 0)
6021 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6023 /* Change the size of any displacement too. At most one of
6024 Disp16 or Disp32 is set.
6025 FIXME. There doesn't seem to be any real need for separate
6026 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6027 Removing them would probably clean up the code quite a lot. */
6028 if (flag_code != CODE_64BIT
6029 && (i.types[this_operand].bitfield.disp16
6030 || i.types[this_operand].bitfield.disp32))
6031 i.types[this_operand]
6032 = operand_type_xor (i.types[this_operand], disp16_32);
6037 as_bad (_("`%s' is not a valid base/index expression"),
6041 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6043 flag_code_names[flag_code]);
6048 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6052 i386_operand (char *operand_string)
6056 char *op_string = operand_string;
6058 if (is_space_char (*op_string))
6061 /* We check for an absolute prefix (differentiating,
6062 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6063 if (*op_string == ABSOLUTE_PREFIX)
6066 if (is_space_char (*op_string))
6068 i.types[this_operand].bitfield.jumpabsolute = 1;
6071 /* Check if operand is a register. */
6072 if ((r = parse_register (op_string, &end_op)) != NULL)
6074 i386_operand_type temp;
6076 /* Check for a segment override by searching for ':' after a
6077 segment register. */
6079 if (is_space_char (*op_string))
6081 if (*op_string == ':'
6082 && (r->reg_type.bitfield.sreg2
6083 || r->reg_type.bitfield.sreg3))
6088 i.seg[i.mem_operands] = &es;
6091 i.seg[i.mem_operands] = &cs;
6094 i.seg[i.mem_operands] = &ss;
6097 i.seg[i.mem_operands] = &ds;
6100 i.seg[i.mem_operands] = &fs;
6103 i.seg[i.mem_operands] = &gs;
6107 /* Skip the ':' and whitespace. */
6109 if (is_space_char (*op_string))
6112 if (!is_digit_char (*op_string)
6113 && !is_identifier_char (*op_string)
6114 && *op_string != '('
6115 && *op_string != ABSOLUTE_PREFIX)
6117 as_bad (_("bad memory operand `%s'"), op_string);
6120 /* Handle case of %es:*foo. */
6121 if (*op_string == ABSOLUTE_PREFIX)
6124 if (is_space_char (*op_string))
6126 i.types[this_operand].bitfield.jumpabsolute = 1;
6128 goto do_memory_reference;
6132 as_bad (_("junk `%s' after register"), op_string);
6136 temp.bitfield.baseindex = 0;
6137 i.types[this_operand] = operand_type_or (i.types[this_operand],
6139 i.op[this_operand].regs = r;
6142 else if (*op_string == REGISTER_PREFIX)
6144 as_bad (_("bad register name `%s'"), op_string);
6147 else if (*op_string == IMMEDIATE_PREFIX)
6150 if (i.types[this_operand].bitfield.jumpabsolute)
6152 as_bad (_("immediate operand illegal with absolute jump"));
6155 if (!i386_immediate (op_string))
6158 else if (is_digit_char (*op_string)
6159 || is_identifier_char (*op_string)
6160 || *op_string == '(')
6162 /* This is a memory reference of some sort. */
6165 /* Start and end of displacement string expression (if found). */
6166 char *displacement_string_start;
6167 char *displacement_string_end;
6169 do_memory_reference:
6170 if ((i.mem_operands == 1
6171 && !current_templates->start->opcode_modifier.isstring)
6172 || i.mem_operands == 2)
6174 as_bad (_("too many memory references for `%s'"),
6175 current_templates->start->name);
6179 /* Check for base index form. We detect the base index form by
6180 looking for an ')' at the end of the operand, searching
6181 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6183 base_string = op_string + strlen (op_string);
6186 if (is_space_char (*base_string))
6189 /* If we only have a displacement, set-up for it to be parsed later. */
6190 displacement_string_start = op_string;
6191 displacement_string_end = base_string + 1;
6193 if (*base_string == ')')
6196 unsigned int parens_balanced = 1;
6197 /* We've already checked that the number of left & right ()'s are
6198 equal, so this loop will not be infinite. */
6202 if (*base_string == ')')
6204 if (*base_string == '(')
6207 while (parens_balanced);
6209 temp_string = base_string;
6211 /* Skip past '(' and whitespace. */
6213 if (is_space_char (*base_string))
6216 if (*base_string == ','
6217 || ((i.base_reg = parse_register (base_string, &end_op))
6220 displacement_string_end = temp_string;
6222 i.types[this_operand].bitfield.baseindex = 1;
6226 base_string = end_op;
6227 if (is_space_char (*base_string))
6231 /* There may be an index reg or scale factor here. */
6232 if (*base_string == ',')
6235 if (is_space_char (*base_string))
6238 if ((i.index_reg = parse_register (base_string, &end_op))
6241 base_string = end_op;
6242 if (is_space_char (*base_string))
6244 if (*base_string == ',')
6247 if (is_space_char (*base_string))
6250 else if (*base_string != ')')
6252 as_bad (_("expecting `,' or `)' "
6253 "after index register in `%s'"),
6258 else if (*base_string == REGISTER_PREFIX)
6260 as_bad (_("bad register name `%s'"), base_string);
6264 /* Check for scale factor. */
6265 if (*base_string != ')')
6267 char *end_scale = i386_scale (base_string);
6272 base_string = end_scale;
6273 if (is_space_char (*base_string))
6275 if (*base_string != ')')
6277 as_bad (_("expecting `)' "
6278 "after scale factor in `%s'"),
6283 else if (!i.index_reg)
6285 as_bad (_("expecting index register or scale factor "
6286 "after `,'; got '%c'"),
6291 else if (*base_string != ')')
6293 as_bad (_("expecting `,' or `)' "
6294 "after base register in `%s'"),
6299 else if (*base_string == REGISTER_PREFIX)
6301 as_bad (_("bad register name `%s'"), base_string);
6306 /* If there's an expression beginning the operand, parse it,
6307 assuming displacement_string_start and
6308 displacement_string_end are meaningful. */
6309 if (displacement_string_start != displacement_string_end)
6311 if (!i386_displacement (displacement_string_start,
6312 displacement_string_end))
6316 /* Special case for (%dx) while doing input/output op. */
6318 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6320 && i.log2_scale_factor == 0
6321 && i.seg[i.mem_operands] == 0
6322 && !operand_type_check (i.types[this_operand], disp))
6324 UINTS_CLEAR (i.types[this_operand]);
6325 i.types[this_operand].bitfield.inoutportreg = 1;
6329 if (i386_index_check (operand_string) == 0)
6335 /* It's not a memory operand; argh! */
6336 as_bad (_("invalid char %s beginning operand %d `%s'"),
6337 output_invalid (*op_string),
6342 return 1; /* Normal return. */
6345 /* md_estimate_size_before_relax()
6347 Called just before relax() for rs_machine_dependent frags. The x86
6348 assembler uses these frags to handle variable size jump
6351 Any symbol that is now undefined will not become defined.
6352 Return the correct fr_subtype in the frag.
6353 Return the initial "guess for variable size of frag" to caller.
6354 The guess is actually the growth beyond the fixed part. Whatever
6355 we do to grow the fixed or variable part contributes to our
6359 md_estimate_size_before_relax (fragP, segment)
6363 /* We've already got fragP->fr_subtype right; all we have to do is
6364 check for un-relaxable symbols. On an ELF system, we can't relax
6365 an externally visible symbol, because it may be overridden by a
6367 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6370 && (S_IS_EXTERNAL (fragP->fr_symbol)
6371 || S_IS_WEAK (fragP->fr_symbol)))
6375 /* Symbol is undefined in this segment, or we need to keep a
6376 reloc so that weak symbols can be overridden. */
6377 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6378 enum bfd_reloc_code_real reloc_type;
6379 unsigned char *opcode;
6382 if (fragP->fr_var != NO_RELOC)
6383 reloc_type = fragP->fr_var;
6385 reloc_type = BFD_RELOC_16_PCREL;
6387 reloc_type = BFD_RELOC_32_PCREL;
6389 old_fr_fix = fragP->fr_fix;
6390 opcode = (unsigned char *) fragP->fr_opcode;
6392 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6395 /* Make jmp (0xeb) a (d)word displacement jump. */
6397 fragP->fr_fix += size;
6398 fix_new (fragP, old_fr_fix, size,
6400 fragP->fr_offset, 1,
6406 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6408 /* Negate the condition, and branch past an
6409 unconditional jump. */
6412 /* Insert an unconditional jump. */
6414 /* We added two extra opcode bytes, and have a two byte
6416 fragP->fr_fix += 2 + 2;
6417 fix_new (fragP, old_fr_fix + 2, 2,
6419 fragP->fr_offset, 1,
6426 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6431 fixP = fix_new (fragP, old_fr_fix, 1,
6433 fragP->fr_offset, 1,
6435 fixP->fx_signed = 1;
6439 /* This changes the byte-displacement jump 0x7N
6440 to the (d)word-displacement jump 0x0f,0x8N. */
6441 opcode[1] = opcode[0] + 0x10;
6442 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6443 /* We've added an opcode byte. */
6444 fragP->fr_fix += 1 + size;
6445 fix_new (fragP, old_fr_fix + 1, size,
6447 fragP->fr_offset, 1,
6452 BAD_CASE (fragP->fr_subtype);
6456 return fragP->fr_fix - old_fr_fix;
6459 /* Guess size depending on current relax state. Initially the relax
6460 state will correspond to a short jump and we return 1, because
6461 the variable part of the frag (the branch offset) is one byte
6462 long. However, we can relax a section more than once and in that
6463 case we must either set fr_subtype back to the unrelaxed state,
6464 or return the value for the appropriate branch. */
6465 return md_relax_table[fragP->fr_subtype].rlx_length;
6468 /* Called after relax() is finished.
6470 In: Address of frag.
6471 fr_type == rs_machine_dependent.
6472 fr_subtype is what the address relaxed to.
6474 Out: Any fixSs and constants are set up.
6475 Caller will turn frag into a ".space 0". */
6478 md_convert_frag (abfd, sec, fragP)
6479 bfd *abfd ATTRIBUTE_UNUSED;
6480 segT sec ATTRIBUTE_UNUSED;
6483 unsigned char *opcode;
6484 unsigned char *where_to_put_displacement = NULL;
6485 offsetT target_address;
6486 offsetT opcode_address;
6487 unsigned int extension = 0;
6488 offsetT displacement_from_opcode_start;
6490 opcode = (unsigned char *) fragP->fr_opcode;
6492 /* Address we want to reach in file space. */
6493 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6495 /* Address opcode resides at in file space. */
6496 opcode_address = fragP->fr_address + fragP->fr_fix;
6498 /* Displacement from opcode start to fill into instruction. */
6499 displacement_from_opcode_start = target_address - opcode_address;
6501 if ((fragP->fr_subtype & BIG) == 0)
6503 /* Don't have to change opcode. */
6504 extension = 1; /* 1 opcode + 1 displacement */
6505 where_to_put_displacement = &opcode[1];
6509 if (no_cond_jump_promotion
6510 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6511 as_warn_where (fragP->fr_file, fragP->fr_line,
6512 _("long jump required"));
6514 switch (fragP->fr_subtype)
6516 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6517 extension = 4; /* 1 opcode + 4 displacement */
6519 where_to_put_displacement = &opcode[1];
6522 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6523 extension = 2; /* 1 opcode + 2 displacement */
6525 where_to_put_displacement = &opcode[1];
6528 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6529 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6530 extension = 5; /* 2 opcode + 4 displacement */
6531 opcode[1] = opcode[0] + 0x10;
6532 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6533 where_to_put_displacement = &opcode[2];
6536 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6537 extension = 3; /* 2 opcode + 2 displacement */
6538 opcode[1] = opcode[0] + 0x10;
6539 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6540 where_to_put_displacement = &opcode[2];
6543 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6548 where_to_put_displacement = &opcode[3];
6552 BAD_CASE (fragP->fr_subtype);
6557 /* If size if less then four we are sure that the operand fits,
6558 but if it's 4, then it could be that the displacement is larger
6560 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6562 && ((addressT) (displacement_from_opcode_start - extension
6563 + ((addressT) 1 << 31))
6564 > (((addressT) 2 << 31) - 1)))
6566 as_bad_where (fragP->fr_file, fragP->fr_line,
6567 _("jump target out of range"));
6568 /* Make us emit 0. */
6569 displacement_from_opcode_start = extension;
6571 /* Now put displacement after opcode. */
6572 md_number_to_chars ((char *) where_to_put_displacement,
6573 (valueT) (displacement_from_opcode_start - extension),
6574 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6575 fragP->fr_fix += extension;
6578 /* Size of byte displacement jmp. */
6579 int md_short_jump_size = 2;
6581 /* Size of dword displacement jmp. */
6582 int md_long_jump_size = 5;
6585 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6587 addressT from_addr, to_addr;
6588 fragS *frag ATTRIBUTE_UNUSED;
6589 symbolS *to_symbol ATTRIBUTE_UNUSED;
6593 offset = to_addr - (from_addr + 2);
6594 /* Opcode for byte-disp jump. */
6595 md_number_to_chars (ptr, (valueT) 0xeb, 1);
6596 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6600 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6602 addressT from_addr, to_addr;
6603 fragS *frag ATTRIBUTE_UNUSED;
6604 symbolS *to_symbol ATTRIBUTE_UNUSED;
6608 offset = to_addr - (from_addr + 5);
6609 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6610 md_number_to_chars (ptr + 1, (valueT) offset, 4);
6613 /* Apply a fixup (fixS) to segment data, once it has been determined
6614 by our caller that we have all the info we need to fix it up.
6616 On the 386, immediates, displacements, and data pointers are all in
6617 the same (little-endian) format, so we don't need to care about which
6621 md_apply_fix (fixP, valP, seg)
6622 /* The fix we're to put in. */
6624 /* Pointer to the value of the bits. */
6626 /* Segment fix is from. */
6627 segT seg ATTRIBUTE_UNUSED;
6629 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6630 valueT value = *valP;
6632 #if !defined (TE_Mach)
6635 switch (fixP->fx_r_type)
6641 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6644 case BFD_RELOC_X86_64_32S:
6645 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6648 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6651 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6656 if (fixP->fx_addsy != NULL
6657 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6658 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6659 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6660 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6661 && !use_rela_relocations)
6663 /* This is a hack. There should be a better way to handle this.
6664 This covers for the fact that bfd_install_relocation will
6665 subtract the current location (for partial_inplace, PC relative
6666 relocations); see more below. */
6670 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6673 value += fixP->fx_where + fixP->fx_frag->fr_address;
6675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6678 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6681 || (symbol_section_p (fixP->fx_addsy)
6682 && sym_seg != absolute_section))
6683 && !generic_force_reloc (fixP))
6685 /* Yes, we add the values in twice. This is because
6686 bfd_install_relocation subtracts them out again. I think
6687 bfd_install_relocation is broken, but I don't dare change
6689 value += fixP->fx_where + fixP->fx_frag->fr_address;
6693 #if defined (OBJ_COFF) && defined (TE_PE)
6694 /* For some reason, the PE format does not store a
6695 section address offset for a PC relative symbol. */
6696 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6697 || S_IS_WEAK (fixP->fx_addsy))
6698 value += md_pcrel_from (fixP);
6702 /* Fix a few things - the dynamic linker expects certain values here,
6703 and we must not disappoint it. */
6704 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6705 if (IS_ELF && fixP->fx_addsy)
6706 switch (fixP->fx_r_type)
6708 case BFD_RELOC_386_PLT32:
6709 case BFD_RELOC_X86_64_PLT32:
6710 /* Make the jump instruction point to the address of the operand. At
6711 runtime we merely add the offset to the actual PLT entry. */
6715 case BFD_RELOC_386_TLS_GD:
6716 case BFD_RELOC_386_TLS_LDM:
6717 case BFD_RELOC_386_TLS_IE_32:
6718 case BFD_RELOC_386_TLS_IE:
6719 case BFD_RELOC_386_TLS_GOTIE:
6720 case BFD_RELOC_386_TLS_GOTDESC:
6721 case BFD_RELOC_X86_64_TLSGD:
6722 case BFD_RELOC_X86_64_TLSLD:
6723 case BFD_RELOC_X86_64_GOTTPOFF:
6724 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6725 value = 0; /* Fully resolved at runtime. No addend. */
6727 case BFD_RELOC_386_TLS_LE:
6728 case BFD_RELOC_386_TLS_LDO_32:
6729 case BFD_RELOC_386_TLS_LE_32:
6730 case BFD_RELOC_X86_64_DTPOFF32:
6731 case BFD_RELOC_X86_64_DTPOFF64:
6732 case BFD_RELOC_X86_64_TPOFF32:
6733 case BFD_RELOC_X86_64_TPOFF64:
6734 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6737 case BFD_RELOC_386_TLS_DESC_CALL:
6738 case BFD_RELOC_X86_64_TLSDESC_CALL:
6739 value = 0; /* Fully resolved at runtime. No addend. */
6740 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6744 case BFD_RELOC_386_GOT32:
6745 case BFD_RELOC_X86_64_GOT32:
6746 value = 0; /* Fully resolved at runtime. No addend. */
6749 case BFD_RELOC_VTABLE_INHERIT:
6750 case BFD_RELOC_VTABLE_ENTRY:
6757 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6759 #endif /* !defined (TE_Mach) */
6761 /* Are we finished with this relocation now? */
6762 if (fixP->fx_addsy == NULL)
6764 else if (use_rela_relocations)
6766 fixP->fx_no_overflow = 1;
6767 /* Remember value for tc_gen_reloc. */
6768 fixP->fx_addnumber = value;
6772 md_number_to_chars (p, value, fixP->fx_size);
6775 #define MAX_LITTLENUMS 6
6777 /* Turn the string pointed to by litP into a floating point constant
6778 of type TYPE, and emit the appropriate bytes. The number of
6779 LITTLENUMS emitted is stored in *SIZEP. An error message is
6780 returned, or NULL on OK. */
6783 md_atof (type, litP, sizeP)
6789 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6790 LITTLENUM_TYPE *wordP;
6812 return _("Bad call to md_atof ()");
6814 t = atof_ieee (input_line_pointer, type, words);
6816 input_line_pointer = t;
6818 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6819 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6820 the bigendian 386. */
6821 for (wordP = words + prec - 1; prec--;)
6823 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6824 litP += sizeof (LITTLENUM_TYPE);
6829 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6832 output_invalid (int c)
6835 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6838 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6839 "(0x%x)", (unsigned char) c);
6840 return output_invalid_buf;
6843 /* REG_STRING starts *before* REGISTER_PREFIX. */
6845 static const reg_entry *
6846 parse_real_register (char *reg_string, char **end_op)
6848 char *s = reg_string;
6850 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6853 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6854 if (*s == REGISTER_PREFIX)
6857 if (is_space_char (*s))
6861 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
6863 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
6864 return (const reg_entry *) NULL;
6868 /* For naked regs, make sure that we are not dealing with an identifier.
6869 This prevents confusing an identifier like `eax_var' with register
6871 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6872 return (const reg_entry *) NULL;
6876 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6878 /* Handle floating point regs, allowing spaces in the (i) part. */
6879 if (r == i386_regtab /* %st is first entry of table */)
6881 if (is_space_char (*s))
6886 if (is_space_char (*s))
6888 if (*s >= '0' && *s <= '7')
6892 if (is_space_char (*s))
6897 r = hash_find (reg_hash, "st(0)");
6902 /* We have "%st(" then garbage. */
6903 return (const reg_entry *) NULL;
6908 && ((r->reg_flags & (RegRex64 | RegRex))
6909 || r->reg_type.bitfield.reg64)
6910 && (!cpu_arch_flags.bitfield.cpulm
6911 || !UINTS_EQUAL (r->reg_type, control))
6912 && flag_code != CODE_64BIT)
6913 return (const reg_entry *) NULL;
6918 /* REG_STRING starts *before* REGISTER_PREFIX. */
6920 static const reg_entry *
6921 parse_register (char *reg_string, char **end_op)
6925 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6926 r = parse_real_register (reg_string, end_op);
6931 char *save = input_line_pointer;
6935 input_line_pointer = reg_string;
6936 c = get_symbol_end ();
6937 symbolP = symbol_find (reg_string);
6938 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6940 const expressionS *e = symbol_get_value_expression (symbolP);
6942 know (e->X_op == O_register);
6943 know (e->X_add_number >= 0
6944 && (valueT) e->X_add_number < i386_regtab_size);
6945 r = i386_regtab + e->X_add_number;
6946 *end_op = input_line_pointer;
6948 *input_line_pointer = c;
6949 input_line_pointer = save;
6955 i386_parse_name (char *name, expressionS *e, char *nextcharP)
6958 char *end = input_line_pointer;
6961 r = parse_register (name, &input_line_pointer);
6962 if (r && end <= input_line_pointer)
6964 *nextcharP = *input_line_pointer;
6965 *input_line_pointer = 0;
6966 e->X_op = O_register;
6967 e->X_add_number = r - i386_regtab;
6970 input_line_pointer = end;
6976 md_operand (expressionS *e)
6978 if (*input_line_pointer == REGISTER_PREFIX)
6981 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6985 e->X_op = O_register;
6986 e->X_add_number = r - i386_regtab;
6987 input_line_pointer = end;
6993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6994 const char *md_shortopts = "kVQ:sqn";
6996 const char *md_shortopts = "qn";
6999 #define OPTION_32 (OPTION_MD_BASE + 0)
7000 #define OPTION_64 (OPTION_MD_BASE + 1)
7001 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7002 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7003 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7005 struct option md_longopts[] =
7007 {"32", no_argument, NULL, OPTION_32},
7008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7009 {"64", no_argument, NULL, OPTION_64},
7011 {"divide", no_argument, NULL, OPTION_DIVIDE},
7012 {"march", required_argument, NULL, OPTION_MARCH},
7013 {"mtune", required_argument, NULL, OPTION_MTUNE},
7014 {NULL, no_argument, NULL, 0}
7016 size_t md_longopts_size = sizeof (md_longopts);
7019 md_parse_option (int c, char *arg)
7026 optimize_align_code = 0;
7033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7034 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7035 should be emitted or not. FIXME: Not implemented. */
7039 /* -V: SVR4 argument to print version ID. */
7041 print_version_id ();
7044 /* -k: Ignore for FreeBSD compatibility. */
7049 /* -s: On i386 Solaris, this tells the native assembler to use
7050 .stab instead of .stab.excl. We always use .stab anyhow. */
7053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7056 const char **list, **l;
7058 list = bfd_target_list ();
7059 for (l = list; *l != NULL; l++)
7060 if (CONST_STRNEQ (*l, "elf64-x86-64")
7061 || strcmp (*l, "coff-x86-64") == 0
7062 || strcmp (*l, "pe-x86-64") == 0
7063 || strcmp (*l, "pei-x86-64") == 0)
7065 default_arch = "x86_64";
7069 as_fatal (_("No compiled in support for x86_64"));
7076 default_arch = "i386";
7080 #ifdef SVR4_COMMENT_CHARS
7085 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7087 for (s = i386_comment_chars; *s != '\0'; s++)
7091 i386_comment_chars = n;
7098 as_fatal (_("Invalid -march= option: `%s'"), arg);
7099 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7101 if (strcmp (arg, cpu_arch [i].name) == 0)
7103 cpu_arch_isa = cpu_arch[i].type;
7104 cpu_arch_isa_flags = cpu_arch[i].flags;
7105 if (!cpu_arch_tune_set)
7107 cpu_arch_tune = cpu_arch_isa;
7108 cpu_arch_tune_flags = cpu_arch_isa_flags;
7113 if (i >= ARRAY_SIZE (cpu_arch))
7114 as_fatal (_("Invalid -march= option: `%s'"), arg);
7119 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7120 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7122 if (strcmp (arg, cpu_arch [i].name) == 0)
7124 cpu_arch_tune_set = 1;
7125 cpu_arch_tune = cpu_arch [i].type;
7126 cpu_arch_tune_flags = cpu_arch[i].flags;
7130 if (i >= ARRAY_SIZE (cpu_arch))
7131 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7141 md_show_usage (stream)
7144 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7145 fprintf (stream, _("\
7147 -V print assembler version number\n\
7150 fprintf (stream, _("\
7151 -n Do not optimize code alignment\n\
7152 -q quieten some warnings\n"));
7153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7154 fprintf (stream, _("\
7157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7158 fprintf (stream, _("\
7159 --32/--64 generate 32bit/64bit code\n"));
7161 #ifdef SVR4_COMMENT_CHARS
7162 fprintf (stream, _("\
7163 --divide do not treat `/' as a comment character\n"));
7165 fprintf (stream, _("\
7166 --divide ignored\n"));
7168 fprintf (stream, _("\
7169 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7170 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7171 core, core2, k6, athlon, k8, generic32, generic64\n"));
7175 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7176 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7178 /* Pick the target format to use. */
7181 i386_target_format (void)
7183 if (!strcmp (default_arch, "x86_64"))
7185 set_code_flag (CODE_64BIT);
7186 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7188 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7189 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7190 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7191 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7192 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7193 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7194 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7195 cpu_arch_isa_flags.bitfield.cpummx= 1;
7196 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7197 cpu_arch_isa_flags.bitfield.cpusse = 1;
7198 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7200 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7202 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7203 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7204 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7205 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7207 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7208 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7209 cpu_arch_tune_flags.bitfield.cpummx= 1;
7210 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7211 cpu_arch_tune_flags.bitfield.cpusse = 1;
7212 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7215 else if (!strcmp (default_arch, "i386"))
7217 set_code_flag (CODE_32BIT);
7218 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7220 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7221 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7222 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7224 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7226 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7227 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7228 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7232 as_fatal (_("Unknown architecture"));
7233 switch (OUTPUT_FLAVOR)
7236 case bfd_target_coff_flavour:
7237 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7240 #ifdef OBJ_MAYBE_AOUT
7241 case bfd_target_aout_flavour:
7242 return AOUT_TARGET_FORMAT;
7244 #ifdef OBJ_MAYBE_COFF
7245 case bfd_target_coff_flavour:
7248 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7249 case bfd_target_elf_flavour:
7251 if (flag_code == CODE_64BIT)
7254 use_rela_relocations = 1;
7256 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7265 #endif /* OBJ_MAYBE_ more than one */
7267 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7269 i386_elf_emit_arch_note (void)
7271 if (IS_ELF && cpu_arch_name != NULL)
7274 asection *seg = now_seg;
7275 subsegT subseg = now_subseg;
7276 Elf_Internal_Note i_note;
7277 Elf_External_Note e_note;
7278 asection *note_secp;
7281 /* Create the .note section. */
7282 note_secp = subseg_new (".note", 0);
7283 bfd_set_section_flags (stdoutput,
7285 SEC_HAS_CONTENTS | SEC_READONLY);
7287 /* Process the arch string. */
7288 len = strlen (cpu_arch_name);
7290 i_note.namesz = len + 1;
7292 i_note.type = NT_ARCH;
7293 p = frag_more (sizeof (e_note.namesz));
7294 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7295 p = frag_more (sizeof (e_note.descsz));
7296 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7297 p = frag_more (sizeof (e_note.type));
7298 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7299 p = frag_more (len + 1);
7300 strcpy (p, cpu_arch_name);
7302 frag_align (2, 0, 0);
7304 subseg_set (seg, subseg);
7310 md_undefined_symbol (name)
7313 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7314 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7315 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7316 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7320 if (symbol_find (name))
7321 as_bad (_("GOT already in symbol table"));
7322 GOT_symbol = symbol_new (name, undefined_section,
7323 (valueT) 0, &zero_address_frag);
7330 /* Round up a section size to the appropriate boundary. */
7333 md_section_align (segment, size)
7334 segT segment ATTRIBUTE_UNUSED;
7337 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7338 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7340 /* For a.out, force the section size to be aligned. If we don't do
7341 this, BFD will align it for us, but it will not write out the
7342 final bytes of the section. This may be a bug in BFD, but it is
7343 easier to fix it here since that is how the other a.out targets
7347 align = bfd_get_section_alignment (stdoutput, segment);
7348 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7355 /* On the i386, PC-relative offsets are relative to the start of the
7356 next instruction. That is, the address of the offset, plus its
7357 size, since the offset is always the last part of the insn. */
7360 md_pcrel_from (fixS *fixP)
7362 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7368 s_bss (int ignore ATTRIBUTE_UNUSED)
7372 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7374 obj_elf_section_change_hook ();
7376 temp = get_absolute_expression ();
7377 subseg_set (bss_section, (subsegT) temp);
7378 demand_empty_rest_of_line ();
7384 i386_validate_fix (fixS *fixp)
7386 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7388 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7392 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7397 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7399 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7406 tc_gen_reloc (section, fixp)
7407 asection *section ATTRIBUTE_UNUSED;
7411 bfd_reloc_code_real_type code;
7413 switch (fixp->fx_r_type)
7415 case BFD_RELOC_X86_64_PLT32:
7416 case BFD_RELOC_X86_64_GOT32:
7417 case BFD_RELOC_X86_64_GOTPCREL:
7418 case BFD_RELOC_386_PLT32:
7419 case BFD_RELOC_386_GOT32:
7420 case BFD_RELOC_386_GOTOFF:
7421 case BFD_RELOC_386_GOTPC:
7422 case BFD_RELOC_386_TLS_GD:
7423 case BFD_RELOC_386_TLS_LDM:
7424 case BFD_RELOC_386_TLS_LDO_32:
7425 case BFD_RELOC_386_TLS_IE_32:
7426 case BFD_RELOC_386_TLS_IE:
7427 case BFD_RELOC_386_TLS_GOTIE:
7428 case BFD_RELOC_386_TLS_LE_32:
7429 case BFD_RELOC_386_TLS_LE:
7430 case BFD_RELOC_386_TLS_GOTDESC:
7431 case BFD_RELOC_386_TLS_DESC_CALL:
7432 case BFD_RELOC_X86_64_TLSGD:
7433 case BFD_RELOC_X86_64_TLSLD:
7434 case BFD_RELOC_X86_64_DTPOFF32:
7435 case BFD_RELOC_X86_64_DTPOFF64:
7436 case BFD_RELOC_X86_64_GOTTPOFF:
7437 case BFD_RELOC_X86_64_TPOFF32:
7438 case BFD_RELOC_X86_64_TPOFF64:
7439 case BFD_RELOC_X86_64_GOTOFF64:
7440 case BFD_RELOC_X86_64_GOTPC32:
7441 case BFD_RELOC_X86_64_GOT64:
7442 case BFD_RELOC_X86_64_GOTPCREL64:
7443 case BFD_RELOC_X86_64_GOTPC64:
7444 case BFD_RELOC_X86_64_GOTPLT64:
7445 case BFD_RELOC_X86_64_PLTOFF64:
7446 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7447 case BFD_RELOC_X86_64_TLSDESC_CALL:
7449 case BFD_RELOC_VTABLE_ENTRY:
7450 case BFD_RELOC_VTABLE_INHERIT:
7452 case BFD_RELOC_32_SECREL:
7454 code = fixp->fx_r_type;
7456 case BFD_RELOC_X86_64_32S:
7457 if (!fixp->fx_pcrel)
7459 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7460 code = fixp->fx_r_type;
7466 switch (fixp->fx_size)
7469 as_bad_where (fixp->fx_file, fixp->fx_line,
7470 _("can not do %d byte pc-relative relocation"),
7472 code = BFD_RELOC_32_PCREL;
7474 case 1: code = BFD_RELOC_8_PCREL; break;
7475 case 2: code = BFD_RELOC_16_PCREL; break;
7476 case 4: code = BFD_RELOC_32_PCREL; break;
7478 case 8: code = BFD_RELOC_64_PCREL; break;
7484 switch (fixp->fx_size)
7487 as_bad_where (fixp->fx_file, fixp->fx_line,
7488 _("can not do %d byte relocation"),
7490 code = BFD_RELOC_32;
7492 case 1: code = BFD_RELOC_8; break;
7493 case 2: code = BFD_RELOC_16; break;
7494 case 4: code = BFD_RELOC_32; break;
7496 case 8: code = BFD_RELOC_64; break;
7503 if ((code == BFD_RELOC_32
7504 || code == BFD_RELOC_32_PCREL
7505 || code == BFD_RELOC_X86_64_32S)
7507 && fixp->fx_addsy == GOT_symbol)
7510 code = BFD_RELOC_386_GOTPC;
7512 code = BFD_RELOC_X86_64_GOTPC32;
7514 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7516 && fixp->fx_addsy == GOT_symbol)
7518 code = BFD_RELOC_X86_64_GOTPC64;
7521 rel = (arelent *) xmalloc (sizeof (arelent));
7522 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7523 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7525 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7527 if (!use_rela_relocations)
7529 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7530 vtable entry to be used in the relocation's section offset. */
7531 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7532 rel->address = fixp->fx_offset;
7536 /* Use the rela in 64bit mode. */
7539 if (!fixp->fx_pcrel)
7540 rel->addend = fixp->fx_offset;
7544 case BFD_RELOC_X86_64_PLT32:
7545 case BFD_RELOC_X86_64_GOT32:
7546 case BFD_RELOC_X86_64_GOTPCREL:
7547 case BFD_RELOC_X86_64_TLSGD:
7548 case BFD_RELOC_X86_64_TLSLD:
7549 case BFD_RELOC_X86_64_GOTTPOFF:
7550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7551 case BFD_RELOC_X86_64_TLSDESC_CALL:
7552 rel->addend = fixp->fx_offset - fixp->fx_size;
7555 rel->addend = (section->vma
7557 + fixp->fx_addnumber
7558 + md_pcrel_from (fixp));
7563 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7564 if (rel->howto == NULL)
7566 as_bad_where (fixp->fx_file, fixp->fx_line,
7567 _("cannot represent relocation type %s"),
7568 bfd_get_reloc_code_name (code));
7569 /* Set howto to a garbage value so that we can keep going. */
7570 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7571 assert (rel->howto != NULL);
7578 /* Parse operands using Intel syntax. This implements a recursive descent
7579 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7582 FIXME: We do not recognize the full operand grammar defined in the MASM
7583 documentation. In particular, all the structure/union and
7584 high-level macro operands are missing.
7586 Uppercase words are terminals, lower case words are non-terminals.
7587 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7588 bars '|' denote choices. Most grammar productions are implemented in
7589 functions called 'intel_<production>'.
7591 Initial production is 'expr'.
7597 binOp & | AND | \| | OR | ^ | XOR
7599 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7601 constant digits [[ radixOverride ]]
7603 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7641 => expr expr cmpOp e04
7644 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7645 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7647 hexdigit a | b | c | d | e | f
7648 | A | B | C | D | E | F
7654 mulOp * | / | % | MOD | << | SHL | >> | SHR
7658 register specialRegister
7662 segmentRegister CS | DS | ES | FS | GS | SS
7664 specialRegister CR0 | CR2 | CR3 | CR4
7665 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7666 | TR3 | TR4 | TR5 | TR6 | TR7
7668 We simplify the grammar in obvious places (e.g., register parsing is
7669 done by calling parse_register) and eliminate immediate left recursion
7670 to implement a recursive-descent parser.
7674 expr' cmpOp e04 expr'
7725 /* Parsing structure for the intel syntax parser. Used to implement the
7726 semantic actions for the operand grammar. */
7727 struct intel_parser_s
7729 char *op_string; /* The string being parsed. */
7730 int got_a_float; /* Whether the operand is a float. */
7731 int op_modifier; /* Operand modifier. */
7732 int is_mem; /* 1 if operand is memory reference. */
7733 int in_offset; /* >=1 if parsing operand of offset. */
7734 int in_bracket; /* >=1 if parsing operand in brackets. */
7735 const reg_entry *reg; /* Last register reference found. */
7736 char *disp; /* Displacement string being built. */
7737 char *next_operand; /* Resume point when splitting operands. */
7740 static struct intel_parser_s intel_parser;
7742 /* Token structure for parsing intel syntax. */
7745 int code; /* Token code. */
7746 const reg_entry *reg; /* Register entry for register tokens. */
7747 char *str; /* String representation. */
7750 static struct intel_token cur_token, prev_token;
7752 /* Token codes for the intel parser. Since T_SHORT is already used
7753 by COFF, undefine it first to prevent a warning. */
7772 /* Prototypes for intel parser functions. */
7773 static int intel_match_token (int);
7774 static void intel_putback_token (void);
7775 static void intel_get_token (void);
7776 static int intel_expr (void);
7777 static int intel_e04 (void);
7778 static int intel_e05 (void);
7779 static int intel_e06 (void);
7780 static int intel_e09 (void);
7781 static int intel_e10 (void);
7782 static int intel_e11 (void);
7785 i386_intel_operand (char *operand_string, int got_a_float)
7790 p = intel_parser.op_string = xstrdup (operand_string);
7791 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7795 /* Initialize token holders. */
7796 cur_token.code = prev_token.code = T_NIL;
7797 cur_token.reg = prev_token.reg = NULL;
7798 cur_token.str = prev_token.str = NULL;
7800 /* Initialize parser structure. */
7801 intel_parser.got_a_float = got_a_float;
7802 intel_parser.op_modifier = 0;
7803 intel_parser.is_mem = 0;
7804 intel_parser.in_offset = 0;
7805 intel_parser.in_bracket = 0;
7806 intel_parser.reg = NULL;
7807 intel_parser.disp[0] = '\0';
7808 intel_parser.next_operand = NULL;
7810 /* Read the first token and start the parser. */
7812 ret = intel_expr ();
7817 if (cur_token.code != T_NIL)
7819 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7820 current_templates->start->name, cur_token.str);
7823 /* If we found a memory reference, hand it over to i386_displacement
7824 to fill in the rest of the operand fields. */
7825 else if (intel_parser.is_mem)
7827 if ((i.mem_operands == 1
7828 && !current_templates->start->opcode_modifier.isstring)
7829 || i.mem_operands == 2)
7831 as_bad (_("too many memory references for '%s'"),
7832 current_templates->start->name);
7837 char *s = intel_parser.disp;
7840 if (!quiet_warnings && intel_parser.is_mem < 0)
7841 /* See the comments in intel_bracket_expr. */
7842 as_warn (_("Treating `%s' as memory reference"), operand_string);
7844 /* Add the displacement expression. */
7846 ret = i386_displacement (s, s + strlen (s));
7849 /* Swap base and index in 16-bit memory operands like
7850 [si+bx]. Since i386_index_check is also used in AT&T
7851 mode we have to do that here. */
7854 && i.base_reg->reg_type.bitfield.reg16
7855 && i.index_reg->reg_type.bitfield.reg16
7856 && i.base_reg->reg_num >= 6
7857 && i.index_reg->reg_num < 6)
7859 const reg_entry *base = i.index_reg;
7861 i.index_reg = i.base_reg;
7864 ret = i386_index_check (operand_string);
7869 /* Constant and OFFSET expressions are handled by i386_immediate. */
7870 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
7871 || intel_parser.reg == NULL)
7872 ret = i386_immediate (intel_parser.disp);
7874 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
7876 if (!ret || !intel_parser.next_operand)
7878 intel_parser.op_string = intel_parser.next_operand;
7879 this_operand = i.operands++;
7883 free (intel_parser.disp);
7888 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7892 expr' cmpOp e04 expr'
7897 /* XXX Implement the comparison operators. */
7898 return intel_e04 ();
7915 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7916 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
7918 if (cur_token.code == '+')
7920 else if (cur_token.code == '-')
7921 nregs = NUM_ADDRESS_REGS;
7925 strcat (intel_parser.disp, cur_token.str);
7926 intel_match_token (cur_token.code);
7937 int nregs = ~NUM_ADDRESS_REGS;
7944 if (cur_token.code == '&'
7945 || cur_token.code == '|'
7946 || cur_token.code == '^')
7950 str[0] = cur_token.code;
7952 strcat (intel_parser.disp, str);
7957 intel_match_token (cur_token.code);
7962 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7963 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7974 int nregs = ~NUM_ADDRESS_REGS;
7981 if (cur_token.code == '*'
7982 || cur_token.code == '/'
7983 || cur_token.code == '%')
7987 str[0] = cur_token.code;
7989 strcat (intel_parser.disp, str);
7991 else if (cur_token.code == T_SHL)
7992 strcat (intel_parser.disp, "<<");
7993 else if (cur_token.code == T_SHR)
7994 strcat (intel_parser.disp, ">>");
7998 intel_match_token (cur_token.code);
8003 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8004 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8022 int nregs = ~NUM_ADDRESS_REGS;
8027 /* Don't consume constants here. */
8028 if (cur_token.code == '+' || cur_token.code == '-')
8030 /* Need to look one token ahead - if the next token
8031 is a constant, the current token is its sign. */
8034 intel_match_token (cur_token.code);
8035 next_code = cur_token.code;
8036 intel_putback_token ();
8037 if (next_code == T_CONST)
8041 /* e09 OFFSET e09 */
8042 if (cur_token.code == T_OFFSET)
8045 ++intel_parser.in_offset;
8049 else if (cur_token.code == T_SHORT)
8050 intel_parser.op_modifier |= 1 << T_SHORT;
8053 else if (cur_token.code == '+')
8054 strcat (intel_parser.disp, "+");
8059 else if (cur_token.code == '-' || cur_token.code == '~')
8065 str[0] = cur_token.code;
8067 strcat (intel_parser.disp, str);
8074 intel_match_token (cur_token.code);
8082 /* e09' PTR e10 e09' */
8083 if (cur_token.code == T_PTR)
8087 if (prev_token.code == T_BYTE)
8088 suffix = BYTE_MNEM_SUFFIX;
8090 else if (prev_token.code == T_WORD)
8092 if (current_templates->start->name[0] == 'l'
8093 && current_templates->start->name[2] == 's'
8094 && current_templates->start->name[3] == 0)
8095 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8096 else if (intel_parser.got_a_float == 2) /* "fi..." */
8097 suffix = SHORT_MNEM_SUFFIX;
8099 suffix = WORD_MNEM_SUFFIX;
8102 else if (prev_token.code == T_DWORD)
8104 if (current_templates->start->name[0] == 'l'
8105 && current_templates->start->name[2] == 's'
8106 && current_templates->start->name[3] == 0)
8107 suffix = WORD_MNEM_SUFFIX;
8108 else if (flag_code == CODE_16BIT
8109 && (current_templates->start->opcode_modifier.jump
8110 || current_templates->start->opcode_modifier.jumpdword))
8111 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8112 else if (intel_parser.got_a_float == 1) /* "f..." */
8113 suffix = SHORT_MNEM_SUFFIX;
8115 suffix = LONG_MNEM_SUFFIX;
8118 else if (prev_token.code == T_FWORD)
8120 if (current_templates->start->name[0] == 'l'
8121 && current_templates->start->name[2] == 's'
8122 && current_templates->start->name[3] == 0)
8123 suffix = LONG_MNEM_SUFFIX;
8124 else if (!intel_parser.got_a_float)
8126 if (flag_code == CODE_16BIT)
8127 add_prefix (DATA_PREFIX_OPCODE);
8128 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8131 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8134 else if (prev_token.code == T_QWORD)
8136 if (intel_parser.got_a_float == 1) /* "f..." */
8137 suffix = LONG_MNEM_SUFFIX;
8139 suffix = QWORD_MNEM_SUFFIX;
8142 else if (prev_token.code == T_TBYTE)
8144 if (intel_parser.got_a_float == 1)
8145 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8147 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8150 else if (prev_token.code == T_XMMWORD)
8152 /* XXX ignored for now, but accepted since gcc uses it */
8158 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8162 /* Operands for jump/call using 'ptr' notation denote absolute
8164 if (current_templates->start->opcode_modifier.jump
8165 || current_templates->start->opcode_modifier.jumpdword)
8166 i.types[this_operand].bitfield.jumpabsolute = 1;
8168 if (current_templates->start->base_opcode == 0x8d /* lea */)
8172 else if (i.suffix != suffix)
8174 as_bad (_("Conflicting operand modifiers"));
8180 /* e09' : e10 e09' */
8181 else if (cur_token.code == ':')
8183 if (prev_token.code != T_REG)
8185 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8186 segment/group identifier (which we don't have), using comma
8187 as the operand separator there is even less consistent, since
8188 there all branches only have a single operand. */
8189 if (this_operand != 0
8190 || intel_parser.in_offset
8191 || intel_parser.in_bracket
8192 || (!current_templates->start->opcode_modifier.jump
8193 && !current_templates->start->opcode_modifier.jumpdword
8194 && !current_templates->start->opcode_modifier.jumpintersegment
8195 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8196 return intel_match_token (T_NIL);
8197 /* Remember the start of the 2nd operand and terminate 1st
8199 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8200 another expression), but it gets at least the simplest case
8201 (a plain number or symbol on the left side) right. */
8202 intel_parser.next_operand = intel_parser.op_string;
8203 *--intel_parser.op_string = '\0';
8204 return intel_match_token (':');
8212 intel_match_token (cur_token.code);
8218 --intel_parser.in_offset;
8221 if (NUM_ADDRESS_REGS > nregs)
8223 as_bad (_("Invalid operand to `OFFSET'"));
8226 intel_parser.op_modifier |= 1 << T_OFFSET;
8229 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8230 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8235 intel_bracket_expr (void)
8237 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8238 const char *start = intel_parser.op_string;
8241 if (i.op[this_operand].regs)
8242 return intel_match_token (T_NIL);
8244 intel_match_token ('[');
8246 /* Mark as a memory operand only if it's not already known to be an
8247 offset expression. If it's an offset expression, we need to keep
8249 if (!intel_parser.in_offset)
8251 ++intel_parser.in_bracket;
8253 /* Operands for jump/call inside brackets denote absolute addresses. */
8254 if (current_templates->start->opcode_modifier.jump
8255 || current_templates->start->opcode_modifier.jumpdword)
8256 i.types[this_operand].bitfield.jumpabsolute = 1;
8258 /* Unfortunately gas always diverged from MASM in a respect that can't
8259 be easily fixed without risking to break code sequences likely to be
8260 encountered (the testsuite even check for this): MASM doesn't consider
8261 an expression inside brackets unconditionally as a memory reference.
8262 When that is e.g. a constant, an offset expression, or the sum of the
8263 two, this is still taken as a constant load. gas, however, always
8264 treated these as memory references. As a compromise, we'll try to make
8265 offset expressions inside brackets work the MASM way (since that's
8266 less likely to be found in real world code), but make constants alone
8267 continue to work the traditional gas way. In either case, issue a
8269 intel_parser.op_modifier &= ~was_offset;
8272 strcat (intel_parser.disp, "[");
8274 /* Add a '+' to the displacement string if necessary. */
8275 if (*intel_parser.disp != '\0'
8276 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8277 strcat (intel_parser.disp, "+");
8280 && (len = intel_parser.op_string - start - 1,
8281 intel_match_token (']')))
8283 /* Preserve brackets when the operand is an offset expression. */
8284 if (intel_parser.in_offset)
8285 strcat (intel_parser.disp, "]");
8288 --intel_parser.in_bracket;
8289 if (i.base_reg || i.index_reg)
8290 intel_parser.is_mem = 1;
8291 if (!intel_parser.is_mem)
8293 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8294 /* Defer the warning until all of the operand was parsed. */
8295 intel_parser.is_mem = -1;
8296 else if (!quiet_warnings)
8297 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8298 len, start, len, start);
8301 intel_parser.op_modifier |= was_offset;
8318 while (cur_token.code == '[')
8320 if (!intel_bracket_expr ())
8345 switch (cur_token.code)
8349 intel_match_token ('(');
8350 strcat (intel_parser.disp, "(");
8352 if (intel_expr () && intel_match_token (')'))
8354 strcat (intel_parser.disp, ")");
8361 return intel_bracket_expr ();
8366 strcat (intel_parser.disp, cur_token.str);
8367 intel_match_token (cur_token.code);
8369 /* Mark as a memory operand only if it's not already known to be an
8370 offset expression. */
8371 if (!intel_parser.in_offset)
8372 intel_parser.is_mem = 1;
8379 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8381 intel_match_token (T_REG);
8383 /* Check for segment change. */
8384 if (cur_token.code == ':')
8386 if (!reg->reg_type.bitfield.sreg2
8387 && !reg->reg_type.bitfield.sreg3)
8389 as_bad (_("`%s' is not a valid segment register"),
8393 else if (i.seg[i.mem_operands])
8394 as_warn (_("Extra segment override ignored"));
8397 if (!intel_parser.in_offset)
8398 intel_parser.is_mem = 1;
8399 switch (reg->reg_num)
8402 i.seg[i.mem_operands] = &es;
8405 i.seg[i.mem_operands] = &cs;
8408 i.seg[i.mem_operands] = &ss;
8411 i.seg[i.mem_operands] = &ds;
8414 i.seg[i.mem_operands] = &fs;
8417 i.seg[i.mem_operands] = &gs;
8423 /* Not a segment register. Check for register scaling. */
8424 else if (cur_token.code == '*')
8426 if (!intel_parser.in_bracket)
8428 as_bad (_("Register scaling only allowed in memory operands"));
8432 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8433 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8434 else if (i.index_reg)
8435 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8437 /* What follows must be a valid scale. */
8438 intel_match_token ('*');
8440 i.types[this_operand].bitfield.baseindex = 1;
8442 /* Set the scale after setting the register (otherwise,
8443 i386_scale will complain) */
8444 if (cur_token.code == '+' || cur_token.code == '-')
8446 char *str, sign = cur_token.code;
8447 intel_match_token (cur_token.code);
8448 if (cur_token.code != T_CONST)
8450 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8454 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8455 strcpy (str + 1, cur_token.str);
8457 if (!i386_scale (str))
8461 else if (!i386_scale (cur_token.str))
8463 intel_match_token (cur_token.code);
8466 /* No scaling. If this is a memory operand, the register is either a
8467 base register (first occurrence) or an index register (second
8469 else if (intel_parser.in_bracket)
8474 else if (!i.index_reg)
8478 as_bad (_("Too many register references in memory operand"));
8482 i.types[this_operand].bitfield.baseindex = 1;
8485 /* It's neither base nor index. */
8486 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8488 i386_operand_type temp = reg->reg_type;
8489 temp.bitfield.baseindex = 0;
8490 i.types[this_operand] = operand_type_or (i.types[this_operand],
8492 i.op[this_operand].regs = reg;
8497 as_bad (_("Invalid use of register"));
8501 /* Since registers are not part of the displacement string (except
8502 when we're parsing offset operands), we may need to remove any
8503 preceding '+' from the displacement string. */
8504 if (*intel_parser.disp != '\0'
8505 && !intel_parser.in_offset)
8507 char *s = intel_parser.disp;
8508 s += strlen (s) - 1;
8531 intel_match_token (cur_token.code);
8533 if (cur_token.code == T_PTR)
8536 /* It must have been an identifier. */
8537 intel_putback_token ();
8538 cur_token.code = T_ID;
8544 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8548 /* The identifier represents a memory reference only if it's not
8549 preceded by an offset modifier and if it's not an equate. */
8550 symbolP = symbol_find(cur_token.str);
8551 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8552 intel_parser.is_mem = 1;
8560 char *save_str, sign = 0;
8562 /* Allow constants that start with `+' or `-'. */
8563 if (cur_token.code == '-' || cur_token.code == '+')
8565 sign = cur_token.code;
8566 intel_match_token (cur_token.code);
8567 if (cur_token.code != T_CONST)
8569 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8575 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8576 strcpy (save_str + !!sign, cur_token.str);
8580 /* Get the next token to check for register scaling. */
8581 intel_match_token (cur_token.code);
8583 /* Check if this constant is a scaling factor for an
8585 if (cur_token.code == '*')
8587 if (intel_match_token ('*') && cur_token.code == T_REG)
8589 const reg_entry *reg = cur_token.reg;
8591 if (!intel_parser.in_bracket)
8593 as_bad (_("Register scaling only allowed "
8594 "in memory operands"));
8598 /* Disallow things like [1*si].
8599 sp and esp are invalid as index. */
8600 if (reg->reg_type.bitfield.reg16)
8601 reg = i386_regtab + REGNAM_AX + 4;
8602 else if (i.index_reg)
8603 reg = i386_regtab + REGNAM_EAX + 4;
8605 /* The constant is followed by `* reg', so it must be
8608 i.types[this_operand].bitfield.baseindex = 1;
8610 /* Set the scale after setting the register (otherwise,
8611 i386_scale will complain) */
8612 if (!i386_scale (save_str))
8614 intel_match_token (T_REG);
8616 /* Since registers are not part of the displacement
8617 string, we may need to remove any preceding '+' from
8618 the displacement string. */
8619 if (*intel_parser.disp != '\0')
8621 char *s = intel_parser.disp;
8622 s += strlen (s) - 1;
8632 /* The constant was not used for register scaling. Since we have
8633 already consumed the token following `*' we now need to put it
8634 back in the stream. */
8635 intel_putback_token ();
8638 /* Add the constant to the displacement string. */
8639 strcat (intel_parser.disp, save_str);
8646 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8650 /* Match the given token against cur_token. If they match, read the next
8651 token from the operand string. */
8653 intel_match_token (int code)
8655 if (cur_token.code == code)
8662 as_bad (_("Unexpected token `%s'"), cur_token.str);
8667 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8669 intel_get_token (void)
8672 const reg_entry *reg;
8673 struct intel_token new_token;
8675 new_token.code = T_NIL;
8676 new_token.reg = NULL;
8677 new_token.str = NULL;
8679 /* Free the memory allocated to the previous token and move
8680 cur_token to prev_token. */
8682 free (prev_token.str);
8684 prev_token = cur_token;
8686 /* Skip whitespace. */
8687 while (is_space_char (*intel_parser.op_string))
8688 intel_parser.op_string++;
8690 /* Return an empty token if we find nothing else on the line. */
8691 if (*intel_parser.op_string == '\0')
8693 cur_token = new_token;
8697 /* The new token cannot be larger than the remainder of the operand
8699 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8700 new_token.str[0] = '\0';
8702 if (strchr ("0123456789", *intel_parser.op_string))
8704 char *p = new_token.str;
8705 char *q = intel_parser.op_string;
8706 new_token.code = T_CONST;
8708 /* Allow any kind of identifier char to encompass floating point and
8709 hexadecimal numbers. */
8710 while (is_identifier_char (*q))
8714 /* Recognize special symbol names [0-9][bf]. */
8715 if (strlen (intel_parser.op_string) == 2
8716 && (intel_parser.op_string[1] == 'b'
8717 || intel_parser.op_string[1] == 'f'))
8718 new_token.code = T_ID;
8721 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8723 size_t len = end_op - intel_parser.op_string;
8725 new_token.code = T_REG;
8726 new_token.reg = reg;
8728 memcpy (new_token.str, intel_parser.op_string, len);
8729 new_token.str[len] = '\0';
8732 else if (is_identifier_char (*intel_parser.op_string))
8734 char *p = new_token.str;
8735 char *q = intel_parser.op_string;
8737 /* A '.' or '$' followed by an identifier char is an identifier.
8738 Otherwise, it's operator '.' followed by an expression. */
8739 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8741 new_token.code = '.';
8742 new_token.str[0] = '.';
8743 new_token.str[1] = '\0';
8747 while (is_identifier_char (*q) || *q == '@')
8751 if (strcasecmp (new_token.str, "NOT") == 0)
8752 new_token.code = '~';
8754 else if (strcasecmp (new_token.str, "MOD") == 0)
8755 new_token.code = '%';
8757 else if (strcasecmp (new_token.str, "AND") == 0)
8758 new_token.code = '&';
8760 else if (strcasecmp (new_token.str, "OR") == 0)
8761 new_token.code = '|';
8763 else if (strcasecmp (new_token.str, "XOR") == 0)
8764 new_token.code = '^';
8766 else if (strcasecmp (new_token.str, "SHL") == 0)
8767 new_token.code = T_SHL;
8769 else if (strcasecmp (new_token.str, "SHR") == 0)
8770 new_token.code = T_SHR;
8772 else if (strcasecmp (new_token.str, "BYTE") == 0)
8773 new_token.code = T_BYTE;
8775 else if (strcasecmp (new_token.str, "WORD") == 0)
8776 new_token.code = T_WORD;
8778 else if (strcasecmp (new_token.str, "DWORD") == 0)
8779 new_token.code = T_DWORD;
8781 else if (strcasecmp (new_token.str, "FWORD") == 0)
8782 new_token.code = T_FWORD;
8784 else if (strcasecmp (new_token.str, "QWORD") == 0)
8785 new_token.code = T_QWORD;
8787 else if (strcasecmp (new_token.str, "TBYTE") == 0
8788 /* XXX remove (gcc still uses it) */
8789 || strcasecmp (new_token.str, "XWORD") == 0)
8790 new_token.code = T_TBYTE;
8792 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8793 || strcasecmp (new_token.str, "OWORD") == 0)
8794 new_token.code = T_XMMWORD;
8796 else if (strcasecmp (new_token.str, "PTR") == 0)
8797 new_token.code = T_PTR;
8799 else if (strcasecmp (new_token.str, "SHORT") == 0)
8800 new_token.code = T_SHORT;
8802 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8804 new_token.code = T_OFFSET;
8806 /* ??? This is not mentioned in the MASM grammar but gcc
8807 makes use of it with -mintel-syntax. OFFSET may be
8808 followed by FLAT: */
8809 if (strncasecmp (q, " FLAT:", 6) == 0)
8810 strcat (new_token.str, " FLAT:");
8813 /* ??? This is not mentioned in the MASM grammar. */
8814 else if (strcasecmp (new_token.str, "FLAT") == 0)
8816 new_token.code = T_OFFSET;
8818 strcat (new_token.str, ":");
8820 as_bad (_("`:' expected"));
8824 new_token.code = T_ID;
8828 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8830 new_token.code = *intel_parser.op_string;
8831 new_token.str[0] = *intel_parser.op_string;
8832 new_token.str[1] = '\0';
8835 else if (strchr ("<>", *intel_parser.op_string)
8836 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8838 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8839 new_token.str[0] = *intel_parser.op_string;
8840 new_token.str[1] = *intel_parser.op_string;
8841 new_token.str[2] = '\0';
8845 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
8847 intel_parser.op_string += strlen (new_token.str);
8848 cur_token = new_token;
8851 /* Put cur_token back into the token stream and make cur_token point to
8854 intel_putback_token (void)
8856 if (cur_token.code != T_NIL)
8858 intel_parser.op_string -= strlen (cur_token.str);
8859 free (cur_token.str);
8861 cur_token = prev_token;
8863 /* Forget prev_token. */
8864 prev_token.code = T_NIL;
8865 prev_token.reg = NULL;
8866 prev_token.str = NULL;
8870 tc_x86_regname_to_dw2regnum (char *regname)
8872 unsigned int regnum;
8873 unsigned int regnames_count;
8874 static const char *const regnames_32[] =
8876 "eax", "ecx", "edx", "ebx",
8877 "esp", "ebp", "esi", "edi",
8878 "eip", "eflags", NULL,
8879 "st0", "st1", "st2", "st3",
8880 "st4", "st5", "st6", "st7",
8882 "xmm0", "xmm1", "xmm2", "xmm3",
8883 "xmm4", "xmm5", "xmm6", "xmm7",
8884 "mm0", "mm1", "mm2", "mm3",
8885 "mm4", "mm5", "mm6", "mm7",
8886 "fcw", "fsw", "mxcsr",
8887 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8890 static const char *const regnames_64[] =
8892 "rax", "rdx", "rcx", "rbx",
8893 "rsi", "rdi", "rbp", "rsp",
8894 "r8", "r9", "r10", "r11",
8895 "r12", "r13", "r14", "r15",
8897 "xmm0", "xmm1", "xmm2", "xmm3",
8898 "xmm4", "xmm5", "xmm6", "xmm7",
8899 "xmm8", "xmm9", "xmm10", "xmm11",
8900 "xmm12", "xmm13", "xmm14", "xmm15",
8901 "st0", "st1", "st2", "st3",
8902 "st4", "st5", "st6", "st7",
8903 "mm0", "mm1", "mm2", "mm3",
8904 "mm4", "mm5", "mm6", "mm7",
8906 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8907 "fs.base", "gs.base", NULL, NULL,
8909 "mxcsr", "fcw", "fsw"
8911 const char *const *regnames;
8913 if (flag_code == CODE_64BIT)
8915 regnames = regnames_64;
8916 regnames_count = ARRAY_SIZE (regnames_64);
8920 regnames = regnames_32;
8921 regnames_count = ARRAY_SIZE (regnames_32);
8924 for (regnum = 0; regnum < regnames_count; regnum++)
8925 if (regnames[regnum] != NULL
8926 && strcmp (regname, regnames[regnum]) == 0)
8933 tc_x86_frame_initial_instructions (void)
8935 static unsigned int sp_regno;
8938 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8941 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8942 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8946 i386_elf_section_type (const char *str, size_t len)
8948 if (flag_code == CODE_64BIT
8949 && len == sizeof ("unwind") - 1
8950 && strncmp (str, "unwind", 6) == 0)
8951 return SHT_X86_64_UNWIND;
8958 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8962 expr.X_op = O_secrel;
8963 expr.X_add_symbol = symbol;
8964 expr.X_add_number = 0;
8965 emit_expr (&expr, size);
8969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8970 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8973 x86_64_section_letter (int letter, char **ptr_msg)
8975 if (flag_code == CODE_64BIT)
8978 return SHF_X86_64_LARGE;
8980 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8983 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8988 x86_64_section_word (char *str, size_t len)
8990 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8991 return SHF_X86_64_LARGE;
8997 handle_large_common (int small ATTRIBUTE_UNUSED)
8999 if (flag_code != CODE_64BIT)
9001 s_comm_internal (0, elf_common_parse);
9002 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9006 static segT lbss_section;
9007 asection *saved_com_section_ptr = elf_com_section_ptr;
9008 asection *saved_bss_section = bss_section;
9010 if (lbss_section == NULL)
9012 flagword applicable;
9014 subsegT subseg = now_subseg;
9016 /* The .lbss section is for local .largecomm symbols. */
9017 lbss_section = subseg_new (".lbss", 0);
9018 applicable = bfd_applicable_section_flags (stdoutput);
9019 bfd_set_section_flags (stdoutput, lbss_section,
9020 applicable & SEC_ALLOC);
9021 seg_info (lbss_section)->bss = 1;
9023 subseg_set (seg, subseg);
9026 elf_com_section_ptr = &_bfd_elf_large_com_section;
9027 bss_section = lbss_section;
9029 s_comm_internal (0, elf_common_parse);
9031 elf_com_section_ptr = saved_com_section_ptr;
9032 bss_section = saved_bss_section;
9035 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */