1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if pseudo registers are permitted. */
417 static int allow_pseudo_reg = 0;
419 /* 1 if register prefix % not required. */
420 static int allow_naked_reg = 0;
422 /* 1 if pseudo index register, eiz/riz, is allowed . */
423 static int allow_index_reg = 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix = "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size = '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code = 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings = 0;
440 static const char *cpu_arch_name = NULL;
441 static char *cpu_sub_arch_name = NULL;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set = 0;
449 /* Cpu we are generating instructions for. */
450 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags;
455 /* CPU instruction set architecture used. */
456 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
458 /* CPU feature flags of instruction set architecture used. */
459 static i386_cpu_flags cpu_arch_isa_flags;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion = 0;
465 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
466 static symbolS *GOT_symbol;
468 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
469 unsigned int x86_dwarf2_return_column;
471 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472 int x86_cie_data_alignment;
474 /* Interface to relax_segment.
475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
480 #define UNCOND_JUMP 0
482 #define COND_JUMP86 2
487 #define SMALL16 (SMALL | CODE16)
489 #define BIG16 (BIG | CODE16)
493 #define INLINE __inline__
499 #define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501 #define TYPE_FROM_RELAX_STATE(s) \
503 #define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
506 /* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
514 const relax_typeS md_relax_table[] =
517 1) most positive reach of this state,
518 2) most negative reach of this state,
519 3) how many bytes this mode will have in the variable part of the frag
520 4) which index into the table to try if we can't fit into this one. */
522 /* UNCOND_JUMP states. */
523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
538 /* word conditionals add 3 bytes to frag:
539 1 extra opcode byte, 2 displacement bytes. */
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
553 static const arch_entry cpu_arch[] =
555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
561 { "i186", PROCESSOR_UNKNOWN,
563 { "i286", PROCESSOR_UNKNOWN,
565 { "i386", PROCESSOR_I386,
567 { "i486", PROCESSOR_I486,
569 { "i586", PROCESSOR_PENTIUM,
571 { "i686", PROCESSOR_PENTIUMPRO,
573 { "pentium", PROCESSOR_PENTIUM,
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
581 { "pentium4", PROCESSOR_PENTIUM4,
583 { "prescott", PROCESSOR_NOCONA,
585 { "nocona", PROCESSOR_NOCONA,
587 { "yonah", PROCESSOR_CORE,
589 { "core", PROCESSOR_CORE,
591 { "merom", PROCESSOR_CORE2,
593 { "core2", PROCESSOR_CORE2,
595 { "k6", PROCESSOR_K6,
597 { "k6_2", PROCESSOR_K6,
599 { "athlon", PROCESSOR_ATHLON,
601 { "sledgehammer", PROCESSOR_K8,
603 { "opteron", PROCESSOR_K8,
605 { "k8", PROCESSOR_K8,
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
611 { ".sse", PROCESSOR_UNKNOWN,
613 { ".sse2", PROCESSOR_UNKNOWN,
615 { ".sse3", PROCESSOR_UNKNOWN,
617 { ".ssse3", PROCESSOR_UNKNOWN,
619 { ".sse4.1", PROCESSOR_UNKNOWN,
621 { ".sse4.2", PROCESSOR_UNKNOWN,
623 { ".sse4", PROCESSOR_UNKNOWN,
625 { ".vmx", PROCESSOR_UNKNOWN,
627 { ".smx", PROCESSOR_UNKNOWN,
629 { ".xsave", PROCESSOR_UNKNOWN,
631 { ".3dnow", PROCESSOR_UNKNOWN,
633 { ".3dnowa", PROCESSOR_UNKNOWN,
635 { ".padlock", PROCESSOR_UNKNOWN,
637 { ".pacifica", PROCESSOR_UNKNOWN,
639 { ".svme", PROCESSOR_UNKNOWN,
641 { ".sse4a", PROCESSOR_UNKNOWN,
643 { ".abm", PROCESSOR_UNKNOWN,
645 { ".sse5", PROCESSOR_UNKNOWN,
649 const pseudo_typeS md_pseudo_table[] =
651 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
654 {"align", s_align_ptwo, 0},
656 {"arch", set_cpu_arch, 0},
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
664 {"slong", signed_cons, 4},
665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
685 {"secrel32", pe_directive_secrel, 0},
690 /* For interface with expression (). */
691 extern char *input_line_pointer;
693 /* Hash table for instruction mnemonic lookup. */
694 static struct hash_control *op_hash;
696 /* Hash table for register lookup. */
697 static struct hash_control *reg_hash;
700 i386_align_code (fragS *fragP, int count)
702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
705 static const char f32_1[] =
707 static const char f32_2[] =
708 {0x66,0x90}; /* xchg %ax,%ax */
709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
766 static const char *const f16_patt[] = {
767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
770 static const char alt_3[] =
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
896 if (flag_code == CODE_16BIT)
900 memcpy (fragP->fr_literal + fragP->fr_fix,
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
911 const char *const *patt = NULL;
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
921 if (cpu_arch_isa_flags.bitfield.cpui686)
922 patt = alt_long_patt;
926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
935 case PROCESSOR_ATHLON:
937 case PROCESSOR_AMDFAM10:
938 patt = alt_short_patt;
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
950 switch (cpu_arch_tune)
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
960 case PROCESSOR_PENTIUM:
962 case PROCESSOR_ATHLON:
964 case PROCESSOR_AMDFAM10:
965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
968 if (cpu_arch_isa_flags.bitfield.cpui686)
969 patt = alt_short_patt;
973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
977 case PROCESSOR_CORE2:
978 if (cpu_arch_isa_flags.bitfield.cpui686)
979 patt = alt_long_patt;
983 case PROCESSOR_GENERIC64:
984 patt = alt_long_patt;
989 if (patt == f32_patt)
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1023 fragP->fr_var = count;
1027 operand_type_all_zero (const union i386_operand_type *x)
1029 switch (ARRAY_SIZE(x->array))
1038 return !x->array[0];
1045 operand_type_set (union i386_operand_type *x, unsigned int v)
1047 switch (ARRAY_SIZE(x->array))
1062 operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
1065 switch (ARRAY_SIZE(x->array))
1068 if (x->array[2] != y->array[2])
1071 if (x->array[1] != y->array[1])
1074 return x->array[0] == y->array[0];
1082 cpu_flags_all_zero (const union i386_cpu_flags *x)
1084 switch (ARRAY_SIZE(x->array))
1093 return !x->array[0];
1100 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1102 switch (ARRAY_SIZE(x->array))
1117 cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1120 switch (ARRAY_SIZE(x->array))
1123 if (x->array[2] != y->array[2])
1126 if (x->array[1] != y->array[1])
1129 return x->array[0] == y->array[0];
1137 cpu_flags_check_cpu64 (i386_cpu_flags f)
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1143 static INLINE i386_cpu_flags
1144 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1146 switch (ARRAY_SIZE (x.array))
1149 x.array [2] &= y.array [2];
1151 x.array [1] &= y.array [1];
1153 x.array [0] &= y.array [0];
1161 static INLINE i386_cpu_flags
1162 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1164 switch (ARRAY_SIZE (x.array))
1167 x.array [2] |= y.array [2];
1169 x.array [1] |= y.array [1];
1171 x.array [0] |= y.array [0];
1179 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1183 cpu_flags_match (i386_cpu_flags x)
1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1190 if (cpu_flags_all_zero (&x))
1194 i386_cpu_flags cpu = cpu_arch_flags;
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
1204 static INLINE i386_operand_type
1205 operand_type_and (i386_operand_type x, i386_operand_type y)
1207 switch (ARRAY_SIZE (x.array))
1210 x.array [2] &= y.array [2];
1212 x.array [1] &= y.array [1];
1214 x.array [0] &= y.array [0];
1222 static INLINE i386_operand_type
1223 operand_type_or (i386_operand_type x, i386_operand_type y)
1225 switch (ARRAY_SIZE (x.array))
1228 x.array [2] |= y.array [2];
1230 x.array [1] |= y.array [1];
1232 x.array [0] |= y.array [0];
1240 static INLINE i386_operand_type
1241 operand_type_xor (i386_operand_type x, i386_operand_type y)
1243 switch (ARRAY_SIZE (x.array))
1246 x.array [2] ^= y.array [2];
1248 x.array [1] ^= y.array [1];
1250 x.array [0] ^= y.array [0];
1258 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1261 static const i386_operand_type inoutportreg
1262 = OPERAND_TYPE_INOUTPORTREG;
1263 static const i386_operand_type reg16_inoutportreg
1264 = OPERAND_TYPE_REG16_INOUTPORTREG;
1265 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1266 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1267 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1268 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1269 static const i386_operand_type anydisp
1270 = OPERAND_TYPE_ANYDISP;
1271 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1272 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1273 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1274 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1275 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1276 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1277 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1278 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1279 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1280 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1291 operand_type_check (i386_operand_type t, enum operand_type c)
1296 return (t.bitfield.reg8
1299 || t.bitfield.reg64);
1302 return (t.bitfield.imm8
1306 || t.bitfield.imm32s
1307 || t.bitfield.imm64);
1310 return (t.bitfield.disp8
1311 || t.bitfield.disp16
1312 || t.bitfield.disp32
1313 || t.bitfield.disp32s
1314 || t.bitfield.disp64);
1317 return (t.bitfield.disp8
1318 || t.bitfield.disp16
1319 || t.bitfield.disp32
1320 || t.bitfield.disp32s
1321 || t.bitfield.disp64
1322 || t.bitfield.baseindex);
1329 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1330 operand J for instruction template T. */
1333 match_reg_size (const template *t, unsigned int j)
1335 return !((i.types[j].bitfield.byte
1336 && !t->operand_types[j].bitfield.byte)
1337 || (i.types[j].bitfield.word
1338 && !t->operand_types[j].bitfield.word)
1339 || (i.types[j].bitfield.dword
1340 && !t->operand_types[j].bitfield.dword)
1341 || (i.types[j].bitfield.qword
1342 && !t->operand_types[j].bitfield.qword));
1345 /* Return 1 if there is no conflict in any size on operand J for
1346 instruction template T. */
1349 match_mem_size (const template *t, unsigned int j)
1351 return (match_reg_size (t, j)
1352 && !((i.types[j].bitfield.unspecified
1353 && !t->operand_types[j].bitfield.unspecified)
1354 || (i.types[j].bitfield.fword
1355 && !t->operand_types[j].bitfield.fword)
1356 || (i.types[j].bitfield.tbyte
1357 && !t->operand_types[j].bitfield.tbyte)
1358 || (i.types[j].bitfield.xmmword
1359 && !t->operand_types[j].bitfield.xmmword)));
1362 /* Return 1 if there is no size conflict on any operands for
1363 instruction template T. */
1366 operand_size_match (const template *t)
1371 /* Don't check jump instructions. */
1372 if (t->opcode_modifier.jump
1373 || t->opcode_modifier.jumpbyte
1374 || t->opcode_modifier.jumpdword
1375 || t->opcode_modifier.jumpintersegment)
1378 /* Check memory and accumulator operand size. */
1379 for (j = 0; j < i.operands; j++)
1381 if (t->operand_types[j].bitfield.anysize)
1384 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1390 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1398 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1401 /* Check reverse. */
1402 assert (i.operands == 2);
1405 for (j = 0; j < 2; j++)
1407 if (t->operand_types[j].bitfield.acc
1408 && !match_reg_size (t, j ? 0 : 1))
1414 if (i.types[j].bitfield.mem
1415 && !match_mem_size (t, j ? 0 : 1))
1426 operand_type_match (i386_operand_type overlap,
1427 i386_operand_type given)
1429 i386_operand_type temp = overlap;
1431 temp.bitfield.jumpabsolute = 0;
1432 temp.bitfield.unspecified = 0;
1433 temp.bitfield.byte = 0;
1434 temp.bitfield.word = 0;
1435 temp.bitfield.dword = 0;
1436 temp.bitfield.fword = 0;
1437 temp.bitfield.qword = 0;
1438 temp.bitfield.tbyte = 0;
1439 temp.bitfield.xmmword = 0;
1440 if (operand_type_all_zero (&temp))
1443 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1444 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1447 /* If given types g0 and g1 are registers they must be of the same type
1448 unless the expected operand type register overlap is null.
1449 Note that Acc in a template matches every size of reg. */
1452 operand_type_register_match (i386_operand_type m0,
1453 i386_operand_type g0,
1454 i386_operand_type t0,
1455 i386_operand_type m1,
1456 i386_operand_type g1,
1457 i386_operand_type t1)
1459 if (!operand_type_check (g0, reg))
1462 if (!operand_type_check (g1, reg))
1465 if (g0.bitfield.reg8 == g1.bitfield.reg8
1466 && g0.bitfield.reg16 == g1.bitfield.reg16
1467 && g0.bitfield.reg32 == g1.bitfield.reg32
1468 && g0.bitfield.reg64 == g1.bitfield.reg64)
1471 if (m0.bitfield.acc)
1473 t0.bitfield.reg8 = 1;
1474 t0.bitfield.reg16 = 1;
1475 t0.bitfield.reg32 = 1;
1476 t0.bitfield.reg64 = 1;
1479 if (m1.bitfield.acc)
1481 t1.bitfield.reg8 = 1;
1482 t1.bitfield.reg16 = 1;
1483 t1.bitfield.reg32 = 1;
1484 t1.bitfield.reg64 = 1;
1487 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1488 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1489 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1490 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1493 static INLINE unsigned int
1494 mode_from_disp_size (i386_operand_type t)
1496 if (t.bitfield.disp8)
1498 else if (t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s)
1507 fits_in_signed_byte (offsetT num)
1509 return (num >= -128) && (num <= 127);
1513 fits_in_unsigned_byte (offsetT num)
1515 return (num & 0xff) == num;
1519 fits_in_unsigned_word (offsetT num)
1521 return (num & 0xffff) == num;
1525 fits_in_signed_word (offsetT num)
1527 return (-32768 <= num) && (num <= 32767);
1531 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1536 return (!(((offsetT) -1 << 31) & num)
1537 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1539 } /* fits_in_signed_long() */
1542 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1547 return (num & (((offsetT) 2 << 31) - 1)) == num;
1549 } /* fits_in_unsigned_long() */
1551 static i386_operand_type
1552 smallest_imm_type (offsetT num)
1554 i386_operand_type t;
1556 operand_type_set (&t, 0);
1557 t.bitfield.imm64 = 1;
1559 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1561 /* This code is disabled on the 486 because all the Imm1 forms
1562 in the opcode table are slower on the i486. They're the
1563 versions with the implicitly specified single-position
1564 displacement, which has another syntax if you really want to
1566 t.bitfield.imm1 = 1;
1567 t.bitfield.imm8 = 1;
1568 t.bitfield.imm8s = 1;
1569 t.bitfield.imm16 = 1;
1570 t.bitfield.imm32 = 1;
1571 t.bitfield.imm32s = 1;
1573 else if (fits_in_signed_byte (num))
1575 t.bitfield.imm8 = 1;
1576 t.bitfield.imm8s = 1;
1577 t.bitfield.imm16 = 1;
1578 t.bitfield.imm32 = 1;
1579 t.bitfield.imm32s = 1;
1581 else if (fits_in_unsigned_byte (num))
1583 t.bitfield.imm8 = 1;
1584 t.bitfield.imm16 = 1;
1585 t.bitfield.imm32 = 1;
1586 t.bitfield.imm32s = 1;
1588 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1590 t.bitfield.imm16 = 1;
1591 t.bitfield.imm32 = 1;
1592 t.bitfield.imm32s = 1;
1594 else if (fits_in_signed_long (num))
1596 t.bitfield.imm32 = 1;
1597 t.bitfield.imm32s = 1;
1599 else if (fits_in_unsigned_long (num))
1600 t.bitfield.imm32 = 1;
1606 offset_in_range (offsetT val, int size)
1612 case 1: mask = ((addressT) 1 << 8) - 1; break;
1613 case 2: mask = ((addressT) 1 << 16) - 1; break;
1614 case 4: mask = ((addressT) 2 << 31) - 1; break;
1616 case 8: mask = ((addressT) 2 << 63) - 1; break;
1621 /* If BFD64, sign extend val. */
1622 if (!use_rela_relocations)
1623 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1624 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1626 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1628 char buf1[40], buf2[40];
1630 sprint_value (buf1, val);
1631 sprint_value (buf2, val & mask);
1632 as_warn (_("%s shortened to %s"), buf1, buf2);
1637 /* Returns 0 if attempting to add a prefix where one from the same
1638 class already exists, 1 if non rep/repne added, 2 if rep/repne
1641 add_prefix (unsigned int prefix)
1646 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1647 && flag_code == CODE_64BIT)
1649 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1650 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1651 && (prefix & (REX_R | REX_X | REX_B))))
1662 case CS_PREFIX_OPCODE:
1663 case DS_PREFIX_OPCODE:
1664 case ES_PREFIX_OPCODE:
1665 case FS_PREFIX_OPCODE:
1666 case GS_PREFIX_OPCODE:
1667 case SS_PREFIX_OPCODE:
1671 case REPNE_PREFIX_OPCODE:
1672 case REPE_PREFIX_OPCODE:
1675 case LOCK_PREFIX_OPCODE:
1683 case ADDR_PREFIX_OPCODE:
1687 case DATA_PREFIX_OPCODE:
1691 if (i.prefix[q] != 0)
1699 i.prefix[q] |= prefix;
1702 as_bad (_("same type of prefix used twice"));
1708 set_code_flag (int value)
1711 if (flag_code == CODE_64BIT)
1713 cpu_arch_flags.bitfield.cpu64 = 1;
1714 cpu_arch_flags.bitfield.cpuno64 = 0;
1718 cpu_arch_flags.bitfield.cpu64 = 0;
1719 cpu_arch_flags.bitfield.cpuno64 = 1;
1721 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1723 as_bad (_("64bit mode not supported on this CPU."));
1725 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1727 as_bad (_("32bit mode not supported on this CPU."));
1729 stackop_size = '\0';
1733 set_16bit_gcc_code_flag (int new_code_flag)
1735 flag_code = new_code_flag;
1736 if (flag_code != CODE_16BIT)
1738 cpu_arch_flags.bitfield.cpu64 = 0;
1739 cpu_arch_flags.bitfield.cpuno64 = 1;
1740 stackop_size = LONG_MNEM_SUFFIX;
1744 set_intel_syntax (int syntax_flag)
1746 /* Find out if register prefixing is specified. */
1747 int ask_naked_reg = 0;
1750 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1752 char *string = input_line_pointer;
1753 int e = get_symbol_end ();
1755 if (strcmp (string, "prefix") == 0)
1757 else if (strcmp (string, "noprefix") == 0)
1760 as_bad (_("bad argument to syntax directive."));
1761 *input_line_pointer = e;
1763 demand_empty_rest_of_line ();
1765 intel_syntax = syntax_flag;
1767 if (ask_naked_reg == 0)
1768 allow_naked_reg = (intel_syntax
1769 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1771 allow_naked_reg = (ask_naked_reg < 0);
1773 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1774 identifier_chars['$'] = intel_syntax ? '$' : 0;
1775 register_prefix = allow_naked_reg ? "" : "%";
1779 set_intel_mnemonic (int mnemonic_flag)
1781 intel_mnemonic = mnemonic_flag;
1785 set_allow_index_reg (int flag)
1787 allow_index_reg = flag;
1791 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1797 char *string = input_line_pointer;
1798 int e = get_symbol_end ();
1800 i386_cpu_flags flags;
1802 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1804 if (strcmp (string, cpu_arch[i].name) == 0)
1808 cpu_arch_name = cpu_arch[i].name;
1809 cpu_sub_arch_name = NULL;
1810 cpu_arch_flags = cpu_arch[i].flags;
1811 if (flag_code == CODE_64BIT)
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1821 cpu_arch_isa = cpu_arch[i].type;
1822 cpu_arch_isa_flags = cpu_arch[i].flags;
1823 if (!cpu_arch_tune_set)
1825 cpu_arch_tune = cpu_arch_isa;
1826 cpu_arch_tune_flags = cpu_arch_isa_flags;
1831 flags = cpu_flags_or (cpu_arch_flags,
1833 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1835 if (cpu_sub_arch_name)
1837 char *name = cpu_sub_arch_name;
1838 cpu_sub_arch_name = concat (name,
1840 (const char *) NULL);
1844 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1845 cpu_arch_flags = flags;
1847 *input_line_pointer = e;
1848 demand_empty_rest_of_line ();
1852 if (i >= ARRAY_SIZE (cpu_arch))
1853 as_bad (_("no such architecture: `%s'"), string);
1855 *input_line_pointer = e;
1858 as_bad (_("missing cpu architecture"));
1860 no_cond_jump_promotion = 0;
1861 if (*input_line_pointer == ','
1862 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1864 char *string = ++input_line_pointer;
1865 int e = get_symbol_end ();
1867 if (strcmp (string, "nojumps") == 0)
1868 no_cond_jump_promotion = 1;
1869 else if (strcmp (string, "jumps") == 0)
1872 as_bad (_("no such architecture modifier: `%s'"), string);
1874 *input_line_pointer = e;
1877 demand_empty_rest_of_line ();
1883 if (!strcmp (default_arch, "x86_64"))
1884 return bfd_mach_x86_64;
1885 else if (!strcmp (default_arch, "i386"))
1886 return bfd_mach_i386_i386;
1888 as_fatal (_("Unknown architecture"));
1894 const char *hash_err;
1896 /* Initialize op_hash hash table. */
1897 op_hash = hash_new ();
1900 const template *optab;
1901 templates *core_optab;
1903 /* Setup for loop. */
1905 core_optab = (templates *) xmalloc (sizeof (templates));
1906 core_optab->start = optab;
1911 if (optab->name == NULL
1912 || strcmp (optab->name, (optab - 1)->name) != 0)
1914 /* different name --> ship out current template list;
1915 add to hash table; & begin anew. */
1916 core_optab->end = optab;
1917 hash_err = hash_insert (op_hash,
1922 as_fatal (_("Internal Error: Can't hash %s: %s"),
1926 if (optab->name == NULL)
1928 core_optab = (templates *) xmalloc (sizeof (templates));
1929 core_optab->start = optab;
1934 /* Initialize reg_hash hash table. */
1935 reg_hash = hash_new ();
1937 const reg_entry *regtab;
1938 unsigned int regtab_size = i386_regtab_size;
1940 for (regtab = i386_regtab; regtab_size--; regtab++)
1942 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1944 as_fatal (_("Internal Error: Can't hash %s: %s"),
1950 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1955 for (c = 0; c < 256; c++)
1960 mnemonic_chars[c] = c;
1961 register_chars[c] = c;
1962 operand_chars[c] = c;
1964 else if (ISLOWER (c))
1966 mnemonic_chars[c] = c;
1967 register_chars[c] = c;
1968 operand_chars[c] = c;
1970 else if (ISUPPER (c))
1972 mnemonic_chars[c] = TOLOWER (c);
1973 register_chars[c] = mnemonic_chars[c];
1974 operand_chars[c] = c;
1977 if (ISALPHA (c) || ISDIGIT (c))
1978 identifier_chars[c] = c;
1981 identifier_chars[c] = c;
1982 operand_chars[c] = c;
1987 identifier_chars['@'] = '@';
1990 identifier_chars['?'] = '?';
1991 operand_chars['?'] = '?';
1993 digit_chars['-'] = '-';
1994 mnemonic_chars['-'] = '-';
1995 mnemonic_chars['.'] = '.';
1996 identifier_chars['_'] = '_';
1997 identifier_chars['.'] = '.';
1999 for (p = operand_special_chars; *p != '\0'; p++)
2000 operand_chars[(unsigned char) *p] = *p;
2003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2006 record_alignment (text_section, 2);
2007 record_alignment (data_section, 2);
2008 record_alignment (bss_section, 2);
2012 if (flag_code == CODE_64BIT)
2014 x86_dwarf2_return_column = 16;
2015 x86_cie_data_alignment = -8;
2019 x86_dwarf2_return_column = 8;
2020 x86_cie_data_alignment = -4;
2025 i386_print_statistics (FILE *file)
2027 hash_print_statistics (file, "i386 opcode", op_hash);
2028 hash_print_statistics (file, "i386 register", reg_hash);
2033 /* Debugging routines for md_assemble. */
2034 static void pte (template *);
2035 static void pt (i386_operand_type);
2036 static void pe (expressionS *);
2037 static void ps (symbolS *);
2040 pi (char *line, i386_insn *x)
2044 fprintf (stdout, "%s: template ", line);
2046 fprintf (stdout, " address: base %s index %s scale %x\n",
2047 x->base_reg ? x->base_reg->reg_name : "none",
2048 x->index_reg ? x->index_reg->reg_name : "none",
2049 x->log2_scale_factor);
2050 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2051 x->rm.mode, x->rm.reg, x->rm.regmem);
2052 fprintf (stdout, " sib: base %x index %x scale %x\n",
2053 x->sib.base, x->sib.index, x->sib.scale);
2054 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2055 (x->rex & REX_W) != 0,
2056 (x->rex & REX_R) != 0,
2057 (x->rex & REX_X) != 0,
2058 (x->rex & REX_B) != 0);
2059 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2060 x->drex.reg, x->drex.rex);
2061 for (i = 0; i < x->operands; i++)
2063 fprintf (stdout, " #%d: ", i + 1);
2065 fprintf (stdout, "\n");
2066 if (x->types[i].bitfield.reg8
2067 || x->types[i].bitfield.reg16
2068 || x->types[i].bitfield.reg32
2069 || x->types[i].bitfield.reg64
2070 || x->types[i].bitfield.regmmx
2071 || x->types[i].bitfield.regxmm
2072 || x->types[i].bitfield.sreg2
2073 || x->types[i].bitfield.sreg3
2074 || x->types[i].bitfield.control
2075 || x->types[i].bitfield.debug
2076 || x->types[i].bitfield.test)
2077 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2078 if (operand_type_check (x->types[i], imm))
2080 if (operand_type_check (x->types[i], disp))
2081 pe (x->op[i].disps);
2089 fprintf (stdout, " %d operands ", t->operands);
2090 fprintf (stdout, "opcode %x ", t->base_opcode);
2091 if (t->extension_opcode != None)
2092 fprintf (stdout, "ext %x ", t->extension_opcode);
2093 if (t->opcode_modifier.d)
2094 fprintf (stdout, "D");
2095 if (t->opcode_modifier.w)
2096 fprintf (stdout, "W");
2097 fprintf (stdout, "\n");
2098 for (i = 0; i < t->operands; i++)
2100 fprintf (stdout, " #%d type ", i + 1);
2101 pt (t->operand_types[i]);
2102 fprintf (stdout, "\n");
2109 fprintf (stdout, " operation %d\n", e->X_op);
2110 fprintf (stdout, " add_number %ld (%lx)\n",
2111 (long) e->X_add_number, (long) e->X_add_number);
2112 if (e->X_add_symbol)
2114 fprintf (stdout, " add_symbol ");
2115 ps (e->X_add_symbol);
2116 fprintf (stdout, "\n");
2120 fprintf (stdout, " op_symbol ");
2121 ps (e->X_op_symbol);
2122 fprintf (stdout, "\n");
2129 fprintf (stdout, "%s type %s%s",
2131 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2132 segment_name (S_GET_SEGMENT (s)));
2135 static struct type_name
2137 i386_operand_type mask;
2140 const type_names[] =
2142 { OPERAND_TYPE_REG8, "r8" },
2143 { OPERAND_TYPE_REG16, "r16" },
2144 { OPERAND_TYPE_REG32, "r32" },
2145 { OPERAND_TYPE_REG64, "r64" },
2146 { OPERAND_TYPE_IMM8, "i8" },
2147 { OPERAND_TYPE_IMM8, "i8s" },
2148 { OPERAND_TYPE_IMM16, "i16" },
2149 { OPERAND_TYPE_IMM32, "i32" },
2150 { OPERAND_TYPE_IMM32S, "i32s" },
2151 { OPERAND_TYPE_IMM64, "i64" },
2152 { OPERAND_TYPE_IMM1, "i1" },
2153 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2154 { OPERAND_TYPE_DISP8, "d8" },
2155 { OPERAND_TYPE_DISP16, "d16" },
2156 { OPERAND_TYPE_DISP32, "d32" },
2157 { OPERAND_TYPE_DISP32S, "d32s" },
2158 { OPERAND_TYPE_DISP64, "d64" },
2159 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2160 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2161 { OPERAND_TYPE_CONTROL, "control reg" },
2162 { OPERAND_TYPE_TEST, "test reg" },
2163 { OPERAND_TYPE_DEBUG, "debug reg" },
2164 { OPERAND_TYPE_FLOATREG, "FReg" },
2165 { OPERAND_TYPE_FLOATACC, "FAcc" },
2166 { OPERAND_TYPE_SREG2, "SReg2" },
2167 { OPERAND_TYPE_SREG3, "SReg3" },
2168 { OPERAND_TYPE_ACC, "Acc" },
2169 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2170 { OPERAND_TYPE_REGMMX, "rMMX" },
2171 { OPERAND_TYPE_REGXMM, "rXMM" },
2172 { OPERAND_TYPE_ESSEG, "es" },
2176 pt (i386_operand_type t)
2179 i386_operand_type a;
2181 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2183 a = operand_type_and (t, type_names[j].mask);
2184 if (!UINTS_ALL_ZERO (a))
2185 fprintf (stdout, "%s, ", type_names[j].name);
2190 #endif /* DEBUG386 */
2192 static bfd_reloc_code_real_type
2193 reloc (unsigned int size,
2196 bfd_reloc_code_real_type other)
2198 if (other != NO_RELOC)
2200 reloc_howto_type *reloc;
2205 case BFD_RELOC_X86_64_GOT32:
2206 return BFD_RELOC_X86_64_GOT64;
2208 case BFD_RELOC_X86_64_PLTOFF64:
2209 return BFD_RELOC_X86_64_PLTOFF64;
2211 case BFD_RELOC_X86_64_GOTPC32:
2212 other = BFD_RELOC_X86_64_GOTPC64;
2214 case BFD_RELOC_X86_64_GOTPCREL:
2215 other = BFD_RELOC_X86_64_GOTPCREL64;
2217 case BFD_RELOC_X86_64_TPOFF32:
2218 other = BFD_RELOC_X86_64_TPOFF64;
2220 case BFD_RELOC_X86_64_DTPOFF32:
2221 other = BFD_RELOC_X86_64_DTPOFF64;
2227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2228 if (size == 4 && flag_code != CODE_64BIT)
2231 reloc = bfd_reloc_type_lookup (stdoutput, other);
2233 as_bad (_("unknown relocation (%u)"), other);
2234 else if (size != bfd_get_reloc_size (reloc))
2235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2236 bfd_get_reloc_size (reloc),
2238 else if (pcrel && !reloc->pc_relative)
2239 as_bad (_("non-pc-relative relocation for pc-relative field"));
2240 else if ((reloc->complain_on_overflow == complain_overflow_signed
2242 || (reloc->complain_on_overflow == complain_overflow_unsigned
2244 as_bad (_("relocated field and relocation type differ in signedness"));
2253 as_bad (_("there are no unsigned pc-relative relocations"));
2256 case 1: return BFD_RELOC_8_PCREL;
2257 case 2: return BFD_RELOC_16_PCREL;
2258 case 4: return BFD_RELOC_32_PCREL;
2259 case 8: return BFD_RELOC_64_PCREL;
2261 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2268 case 4: return BFD_RELOC_X86_64_32S;
2273 case 1: return BFD_RELOC_8;
2274 case 2: return BFD_RELOC_16;
2275 case 4: return BFD_RELOC_32;
2276 case 8: return BFD_RELOC_64;
2278 as_bad (_("cannot do %s %u byte relocation"),
2279 sign > 0 ? "signed" : "unsigned", size);
2283 return BFD_RELOC_NONE;
2286 /* Here we decide which fixups can be adjusted to make them relative to
2287 the beginning of the section instead of the symbol. Basically we need
2288 to make sure that the dynamic relocations are done correctly, so in
2289 some cases we force the original symbol to be used. */
2292 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2298 /* Don't adjust pc-relative references to merge sections in 64-bit
2300 if (use_rela_relocations
2301 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2305 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2306 and changed later by validate_fix. */
2307 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2308 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2311 /* adjust_reloc_syms doesn't know about the GOT. */
2312 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2313 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2314 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2324 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2325 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2328 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2338 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2339 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2346 intel_float_operand (const char *mnemonic)
2348 /* Note that the value returned is meaningful only for opcodes with (memory)
2349 operands, hence the code here is free to improperly handle opcodes that
2350 have no operands (for better performance and smaller code). */
2352 if (mnemonic[0] != 'f')
2353 return 0; /* non-math */
2355 switch (mnemonic[1])
2357 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2358 the fs segment override prefix not currently handled because no
2359 call path can make opcodes without operands get here */
2361 return 2 /* integer op */;
2363 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2364 return 3; /* fldcw/fldenv */
2367 if (mnemonic[2] != 'o' /* fnop */)
2368 return 3; /* non-waiting control op */
2371 if (mnemonic[2] == 's')
2372 return 3; /* frstor/frstpm */
2375 if (mnemonic[2] == 'a')
2376 return 3; /* fsave */
2377 if (mnemonic[2] == 't')
2379 switch (mnemonic[3])
2381 case 'c': /* fstcw */
2382 case 'd': /* fstdw */
2383 case 'e': /* fstenv */
2384 case 's': /* fsts[gw] */
2390 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2391 return 0; /* fxsave/fxrstor are not really math ops */
2399 process_immext (void)
2403 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2405 /* SSE3 Instructions have the fixed operands with an opcode
2406 suffix which is coded in the same place as an 8-bit immediate
2407 field would be. Here we check those operands and remove them
2411 for (x = 0; x < i.operands; x++)
2412 if (i.op[x].regs->reg_num != x)
2413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2414 register_prefix, i.op[x].regs->reg_name, x + 1,
2420 /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
2421 which is coded in the same place as an 8-bit immediate field
2422 would be. Here we fake an 8-bit immediate operand from the
2423 opcode suffix stored in tm.extension_opcode.
2425 SSE5 also uses this encoding, for some of its 3 argument
2428 assert (i.imm_operands == 0
2430 || (i.tm.cpu_flags.bitfield.cpusse5
2431 && i.operands <= 3)));
2433 exp = &im_expressions[i.imm_operands++];
2434 i.op[i.operands].imms = exp;
2435 i.types[i.operands] = imm8;
2437 exp->X_op = O_constant;
2438 exp->X_add_number = i.tm.extension_opcode;
2439 i.tm.extension_opcode = None;
2442 /* This is the guts of the machine-dependent assembler. LINE points to a
2443 machine dependent instruction. This function is supposed to emit
2444 the frags/bytes it assembles to. */
2447 md_assemble (char *line)
2450 char mnemonic[MAX_MNEM_SIZE];
2452 /* Initialize globals. */
2453 memset (&i, '\0', sizeof (i));
2454 for (j = 0; j < MAX_OPERANDS; j++)
2455 i.reloc[j] = NO_RELOC;
2456 memset (disp_expressions, '\0', sizeof (disp_expressions));
2457 memset (im_expressions, '\0', sizeof (im_expressions));
2458 save_stack_p = save_stack;
2460 /* First parse an instruction mnemonic & call i386_operand for the operands.
2461 We assume that the scrubber has arranged it so that line[0] is the valid
2462 start of a (possibly prefixed) mnemonic. */
2464 line = parse_insn (line, mnemonic);
2468 line = parse_operands (line, mnemonic);
2472 /* Now we've parsed the mnemonic into a set of templates, and have the
2473 operands at hand. */
2475 /* All intel opcodes have reversed operands except for "bound" and
2476 "enter". We also don't reverse intersegment "jmp" and "call"
2477 instructions with 2 immediate operands so that the immediate segment
2478 precedes the offset, as it does when in AT&T mode. */
2481 && (strcmp (mnemonic, "bound") != 0)
2482 && (strcmp (mnemonic, "invlpga") != 0)
2483 && !(operand_type_check (i.types[0], imm)
2484 && operand_type_check (i.types[1], imm)))
2487 /* The order of the immediates should be reversed
2488 for 2 immediates extrq and insertq instructions */
2489 if (i.imm_operands == 2
2490 && (strcmp (mnemonic, "extrq") == 0
2491 || strcmp (mnemonic, "insertq") == 0))
2492 swap_2_operands (0, 1);
2497 /* Don't optimize displacement for movabs since it only takes 64bit
2500 && (flag_code != CODE_64BIT
2501 || strcmp (mnemonic, "movabs") != 0))
2504 /* Next, we find a template that matches the given insn,
2505 making sure the overlap of the given operands types is consistent
2506 with the template operand types. */
2508 if (!match_template ())
2511 /* Zap movzx and movsx suffix. The suffix has been set from
2512 "word ptr" or "byte ptr" on the source operand in Intel syntax
2513 or extracted from mnemonic in AT&T syntax. But we'll use
2514 the destination register to choose the suffix for encoding. */
2515 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2517 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2518 there is no suffix, the default will be byte extension. */
2519 if (i.reg_operands != 2
2522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2527 if (i.tm.opcode_modifier.fwait)
2528 if (!add_prefix (FWAIT_OPCODE))
2531 /* Check string instruction segment overrides. */
2532 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2534 if (!check_string ())
2538 if (!process_suffix ())
2541 /* Make still unresolved immediate matches conform to size of immediate
2542 given in i.suffix. */
2543 if (!finalize_imm ())
2546 if (i.types[0].bitfield.imm1)
2547 i.imm_operands = 0; /* kludge for shift insns. */
2549 for (j = 0; j < 3; j++)
2550 if (i.types[j].bitfield.inoutportreg
2551 || i.types[j].bitfield.shiftcount
2552 || i.types[j].bitfield.acc
2553 || i.types[j].bitfield.floatacc)
2556 if (i.tm.opcode_modifier.immext)
2559 /* For insns with operands there are more diddles to do to the opcode. */
2562 if (!process_operands ())
2565 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2567 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2568 as_warn (_("translating to `%sp'"), i.tm.name);
2571 /* Handle conversion of 'int $3' --> special int3 insn. */
2572 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2574 i.tm.base_opcode = INT3_OPCODE;
2578 if ((i.tm.opcode_modifier.jump
2579 || i.tm.opcode_modifier.jumpbyte
2580 || i.tm.opcode_modifier.jumpdword)
2581 && i.op[0].disps->X_op == O_constant)
2583 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2584 the absolute address given by the constant. Since ix86 jumps and
2585 calls are pc relative, we need to generate a reloc. */
2586 i.op[0].disps->X_add_symbol = &abs_symbol;
2587 i.op[0].disps->X_op = O_symbol;
2590 if (i.tm.opcode_modifier.rex64)
2593 /* For 8 bit registers we need an empty rex prefix. Also if the
2594 instruction already has a prefix, we need to convert old
2595 registers to new ones. */
2597 if ((i.types[0].bitfield.reg8
2598 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2599 || (i.types[1].bitfield.reg8
2600 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2601 || ((i.types[0].bitfield.reg8
2602 || i.types[1].bitfield.reg8)
2607 i.rex |= REX_OPCODE;
2608 for (x = 0; x < 2; x++)
2610 /* Look for 8 bit operand that uses old registers. */
2611 if (i.types[x].bitfield.reg8
2612 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2614 /* In case it is "hi" register, give up. */
2615 if (i.op[x].regs->reg_num > 3)
2616 as_bad (_("can't encode register '%s%s' in an "
2617 "instruction requiring REX prefix."),
2618 register_prefix, i.op[x].regs->reg_name);
2620 /* Otherwise it is equivalent to the extended register.
2621 Since the encoding doesn't change this is merely
2622 cosmetic cleanup for debug output. */
2624 i.op[x].regs = i.op[x].regs + 8;
2629 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2631 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2636 else if (i.rex != 0)
2637 add_prefix (REX_OPCODE | i.rex);
2639 /* We are ready to output the insn. */
2644 parse_insn (char *line, char *mnemonic)
2647 char *token_start = l;
2652 /* Non-zero if we found a prefix only acceptable with string insns. */
2653 const char *expecting_string_instruction = NULL;
2658 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2661 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2663 as_bad (_("no such instruction: `%s'"), token_start);
2668 if (!is_space_char (*l)
2669 && *l != END_OF_INSN
2671 || (*l != PREFIX_SEPARATOR
2674 as_bad (_("invalid character %s in mnemonic"),
2675 output_invalid (*l));
2678 if (token_start == l)
2680 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2681 as_bad (_("expecting prefix; got nothing"));
2683 as_bad (_("expecting mnemonic; got nothing"));
2687 /* Look up instruction (or prefix) via hash table. */
2688 current_templates = hash_find (op_hash, mnemonic);
2690 if (*l != END_OF_INSN
2691 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2692 && current_templates
2693 && current_templates->start->opcode_modifier.isprefix)
2695 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2697 as_bad ((flag_code != CODE_64BIT
2698 ? _("`%s' is only supported in 64-bit mode")
2699 : _("`%s' is not supported in 64-bit mode")),
2700 current_templates->start->name);
2703 /* If we are in 16-bit mode, do not allow addr16 or data16.
2704 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2705 if ((current_templates->start->opcode_modifier.size16
2706 || current_templates->start->opcode_modifier.size32)
2707 && flag_code != CODE_64BIT
2708 && (current_templates->start->opcode_modifier.size32
2709 ^ (flag_code == CODE_16BIT)))
2711 as_bad (_("redundant %s prefix"),
2712 current_templates->start->name);
2715 /* Add prefix, checking for repeated prefixes. */
2716 switch (add_prefix (current_templates->start->base_opcode))
2721 expecting_string_instruction = current_templates->start->name;
2724 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2731 if (!current_templates)
2733 /* See if we can get a match by trimming off a suffix. */
2736 case WORD_MNEM_SUFFIX:
2737 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2738 i.suffix = SHORT_MNEM_SUFFIX;
2740 case BYTE_MNEM_SUFFIX:
2741 case QWORD_MNEM_SUFFIX:
2742 i.suffix = mnem_p[-1];
2744 current_templates = hash_find (op_hash, mnemonic);
2746 case SHORT_MNEM_SUFFIX:
2747 case LONG_MNEM_SUFFIX:
2750 i.suffix = mnem_p[-1];
2752 current_templates = hash_find (op_hash, mnemonic);
2760 if (intel_float_operand (mnemonic) == 1)
2761 i.suffix = SHORT_MNEM_SUFFIX;
2763 i.suffix = LONG_MNEM_SUFFIX;
2765 current_templates = hash_find (op_hash, mnemonic);
2769 if (!current_templates)
2771 as_bad (_("no such instruction: `%s'"), token_start);
2776 if (current_templates->start->opcode_modifier.jump
2777 || current_templates->start->opcode_modifier.jumpbyte)
2779 /* Check for a branch hint. We allow ",pt" and ",pn" for
2780 predict taken and predict not taken respectively.
2781 I'm not sure that branch hints actually do anything on loop
2782 and jcxz insns (JumpByte) for current Pentium4 chips. They
2783 may work in the future and it doesn't hurt to accept them
2785 if (l[0] == ',' && l[1] == 'p')
2789 if (!add_prefix (DS_PREFIX_OPCODE))
2793 else if (l[2] == 'n')
2795 if (!add_prefix (CS_PREFIX_OPCODE))
2801 /* Any other comma loses. */
2804 as_bad (_("invalid character %s in mnemonic"),
2805 output_invalid (*l));
2809 /* Check if instruction is supported on specified architecture. */
2811 for (t = current_templates->start; t < current_templates->end; ++t)
2813 supported |= cpu_flags_match (t->cpu_flags);
2818 if (!(supported & 2))
2820 as_bad (flag_code == CODE_64BIT
2821 ? _("`%s' is not supported in 64-bit mode")
2822 : _("`%s' is only supported in 64-bit mode"),
2823 current_templates->start->name);
2826 if (!(supported & 1))
2828 as_bad (_("`%s' is not supported on `%s%s'"),
2829 current_templates->start->name, cpu_arch_name,
2830 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2835 if (!cpu_arch_flags.bitfield.cpui386
2836 && (flag_code != CODE_16BIT))
2838 as_warn (_("use .code16 to ensure correct addressing mode"));
2841 /* Check for rep/repne without a string instruction. */
2842 if (expecting_string_instruction)
2844 static templates override;
2846 for (t = current_templates->start; t < current_templates->end; ++t)
2847 if (t->opcode_modifier.isstring)
2849 if (t >= current_templates->end)
2851 as_bad (_("expecting string instruction after `%s'"),
2852 expecting_string_instruction);
2855 for (override.start = t; t < current_templates->end; ++t)
2856 if (!t->opcode_modifier.isstring)
2859 current_templates = &override;
2866 parse_operands (char *l, const char *mnemonic)
2870 /* 1 if operand is pending after ','. */
2871 unsigned int expecting_operand = 0;
2873 /* Non-zero if operand parens not balanced. */
2874 unsigned int paren_not_balanced;
2876 while (*l != END_OF_INSN)
2878 /* Skip optional white space before operand. */
2879 if (is_space_char (*l))
2881 if (!is_operand_char (*l) && *l != END_OF_INSN)
2883 as_bad (_("invalid character %s before operand %d"),
2884 output_invalid (*l),
2888 token_start = l; /* after white space */
2889 paren_not_balanced = 0;
2890 while (paren_not_balanced || *l != ',')
2892 if (*l == END_OF_INSN)
2894 if (paren_not_balanced)
2897 as_bad (_("unbalanced parenthesis in operand %d."),
2900 as_bad (_("unbalanced brackets in operand %d."),
2905 break; /* we are done */
2907 else if (!is_operand_char (*l) && !is_space_char (*l))
2909 as_bad (_("invalid character %s in operand %d"),
2910 output_invalid (*l),
2917 ++paren_not_balanced;
2919 --paren_not_balanced;
2924 ++paren_not_balanced;
2926 --paren_not_balanced;
2930 if (l != token_start)
2931 { /* Yes, we've read in another operand. */
2932 unsigned int operand_ok;
2933 this_operand = i.operands++;
2934 i.types[this_operand].bitfield.unspecified = 1;
2935 if (i.operands > MAX_OPERANDS)
2937 as_bad (_("spurious operands; (%d operands/instruction max)"),
2941 /* Now parse operand adding info to 'i' as we go along. */
2942 END_STRING_AND_SAVE (l);
2946 i386_intel_operand (token_start,
2947 intel_float_operand (mnemonic));
2949 operand_ok = i386_att_operand (token_start);
2951 RESTORE_END_STRING (l);
2957 if (expecting_operand)
2959 expecting_operand_after_comma:
2960 as_bad (_("expecting operand after ','; got nothing"));
2965 as_bad (_("expecting operand before ','; got nothing"));
2970 /* Now *l must be either ',' or END_OF_INSN. */
2973 if (*++l == END_OF_INSN)
2975 /* Just skip it, if it's \n complain. */
2976 goto expecting_operand_after_comma;
2978 expecting_operand = 1;
2985 swap_2_operands (int xchg1, int xchg2)
2987 union i386_op temp_op;
2988 i386_operand_type temp_type;
2989 enum bfd_reloc_code_real temp_reloc;
2991 temp_type = i.types[xchg2];
2992 i.types[xchg2] = i.types[xchg1];
2993 i.types[xchg1] = temp_type;
2994 temp_op = i.op[xchg2];
2995 i.op[xchg2] = i.op[xchg1];
2996 i.op[xchg1] = temp_op;
2997 temp_reloc = i.reloc[xchg2];
2998 i.reloc[xchg2] = i.reloc[xchg1];
2999 i.reloc[xchg1] = temp_reloc;
3003 swap_operands (void)
3008 swap_2_operands (1, i.operands - 2);
3011 swap_2_operands (0, i.operands - 1);
3017 if (i.mem_operands == 2)
3019 const seg_entry *temp_seg;
3020 temp_seg = i.seg[0];
3021 i.seg[0] = i.seg[1];
3022 i.seg[1] = temp_seg;
3026 /* Try to ensure constant immediates are represented in the smallest
3031 char guess_suffix = 0;
3035 guess_suffix = i.suffix;
3036 else if (i.reg_operands)
3038 /* Figure out a suffix from the last register operand specified.
3039 We can't do this properly yet, ie. excluding InOutPortReg,
3040 but the following works for instructions with immediates.
3041 In any case, we can't set i.suffix yet. */
3042 for (op = i.operands; --op >= 0;)
3043 if (i.types[op].bitfield.reg8)
3045 guess_suffix = BYTE_MNEM_SUFFIX;
3048 else if (i.types[op].bitfield.reg16)
3050 guess_suffix = WORD_MNEM_SUFFIX;
3053 else if (i.types[op].bitfield.reg32)
3055 guess_suffix = LONG_MNEM_SUFFIX;
3058 else if (i.types[op].bitfield.reg64)
3060 guess_suffix = QWORD_MNEM_SUFFIX;
3064 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3065 guess_suffix = WORD_MNEM_SUFFIX;
3067 for (op = i.operands; --op >= 0;)
3068 if (operand_type_check (i.types[op], imm))
3070 switch (i.op[op].imms->X_op)
3073 /* If a suffix is given, this operand may be shortened. */
3074 switch (guess_suffix)
3076 case LONG_MNEM_SUFFIX:
3077 i.types[op].bitfield.imm32 = 1;
3078 i.types[op].bitfield.imm64 = 1;
3080 case WORD_MNEM_SUFFIX:
3081 i.types[op].bitfield.imm16 = 1;
3082 i.types[op].bitfield.imm32 = 1;
3083 i.types[op].bitfield.imm32s = 1;
3084 i.types[op].bitfield.imm64 = 1;
3086 case BYTE_MNEM_SUFFIX:
3087 i.types[op].bitfield.imm8 = 1;
3088 i.types[op].bitfield.imm8s = 1;
3089 i.types[op].bitfield.imm16 = 1;
3090 i.types[op].bitfield.imm32 = 1;
3091 i.types[op].bitfield.imm32s = 1;
3092 i.types[op].bitfield.imm64 = 1;
3096 /* If this operand is at most 16 bits, convert it
3097 to a signed 16 bit number before trying to see
3098 whether it will fit in an even smaller size.
3099 This allows a 16-bit operand such as $0xffe0 to
3100 be recognised as within Imm8S range. */
3101 if ((i.types[op].bitfield.imm16)
3102 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3104 i.op[op].imms->X_add_number =
3105 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3107 if ((i.types[op].bitfield.imm32)
3108 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3111 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3112 ^ ((offsetT) 1 << 31))
3113 - ((offsetT) 1 << 31));
3116 = operand_type_or (i.types[op],
3117 smallest_imm_type (i.op[op].imms->X_add_number));
3119 /* We must avoid matching of Imm32 templates when 64bit
3120 only immediate is available. */
3121 if (guess_suffix == QWORD_MNEM_SUFFIX)
3122 i.types[op].bitfield.imm32 = 0;
3129 /* Symbols and expressions. */
3131 /* Convert symbolic operand to proper sizes for matching, but don't
3132 prevent matching a set of insns that only supports sizes other
3133 than those matching the insn suffix. */
3135 i386_operand_type mask, allowed;
3138 operand_type_set (&mask, 0);
3139 operand_type_set (&allowed, 0);
3141 for (t = current_templates->start;
3142 t < current_templates->end;
3144 allowed = operand_type_or (allowed,
3145 t->operand_types[op]);
3146 switch (guess_suffix)
3148 case QWORD_MNEM_SUFFIX:
3149 mask.bitfield.imm64 = 1;
3150 mask.bitfield.imm32s = 1;
3152 case LONG_MNEM_SUFFIX:
3153 mask.bitfield.imm32 = 1;
3155 case WORD_MNEM_SUFFIX:
3156 mask.bitfield.imm16 = 1;
3158 case BYTE_MNEM_SUFFIX:
3159 mask.bitfield.imm8 = 1;
3164 allowed = operand_type_and (mask, allowed);
3165 if (!operand_type_all_zero (&allowed))
3166 i.types[op] = operand_type_and (i.types[op], mask);
3173 /* Try to use the smallest displacement type too. */
3175 optimize_disp (void)
3179 for (op = i.operands; --op >= 0;)
3180 if (operand_type_check (i.types[op], disp))
3182 if (i.op[op].disps->X_op == O_constant)
3184 offsetT disp = i.op[op].disps->X_add_number;
3186 if (i.types[op].bitfield.disp16
3187 && (disp & ~(offsetT) 0xffff) == 0)
3189 /* If this operand is at most 16 bits, convert
3190 to a signed 16 bit number and don't use 64bit
3192 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3193 i.types[op].bitfield.disp64 = 0;
3195 if (i.types[op].bitfield.disp32
3196 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3198 /* If this operand is at most 32 bits, convert
3199 to a signed 32 bit number and don't use 64bit
3201 disp &= (((offsetT) 2 << 31) - 1);
3202 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3203 i.types[op].bitfield.disp64 = 0;
3205 if (!disp && i.types[op].bitfield.baseindex)
3207 i.types[op].bitfield.disp8 = 0;
3208 i.types[op].bitfield.disp16 = 0;
3209 i.types[op].bitfield.disp32 = 0;
3210 i.types[op].bitfield.disp32s = 0;
3211 i.types[op].bitfield.disp64 = 0;
3215 else if (flag_code == CODE_64BIT)
3217 if (fits_in_signed_long (disp))
3219 i.types[op].bitfield.disp64 = 0;
3220 i.types[op].bitfield.disp32s = 1;
3222 if (fits_in_unsigned_long (disp))
3223 i.types[op].bitfield.disp32 = 1;
3225 if ((i.types[op].bitfield.disp32
3226 || i.types[op].bitfield.disp32s
3227 || i.types[op].bitfield.disp16)
3228 && fits_in_signed_byte (disp))
3229 i.types[op].bitfield.disp8 = 1;
3231 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3232 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3234 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3235 i.op[op].disps, 0, i.reloc[op]);
3236 i.types[op].bitfield.disp8 = 0;
3237 i.types[op].bitfield.disp16 = 0;
3238 i.types[op].bitfield.disp32 = 0;
3239 i.types[op].bitfield.disp32s = 0;
3240 i.types[op].bitfield.disp64 = 0;
3243 /* We only support 64bit displacement on constants. */
3244 i.types[op].bitfield.disp64 = 0;
3249 match_template (void)
3251 /* Points to template once we've found it. */
3253 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3254 unsigned int found_reverse_match;
3255 i386_opcode_modifier suffix_check;
3256 i386_operand_type operand_types [MAX_OPERANDS];
3257 int addr_prefix_disp;
3259 unsigned int found_cpu_match;
3260 unsigned int check_register;
3262 #if MAX_OPERANDS != 4
3263 # error "MAX_OPERANDS must be 4."
3266 found_reverse_match = 0;
3267 addr_prefix_disp = -1;
3269 memset (&suffix_check, 0, sizeof (suffix_check));
3270 if (i.suffix == BYTE_MNEM_SUFFIX)
3271 suffix_check.no_bsuf = 1;
3272 else if (i.suffix == WORD_MNEM_SUFFIX)
3273 suffix_check.no_wsuf = 1;
3274 else if (i.suffix == SHORT_MNEM_SUFFIX)
3275 suffix_check.no_ssuf = 1;
3276 else if (i.suffix == LONG_MNEM_SUFFIX)
3277 suffix_check.no_lsuf = 1;
3278 else if (i.suffix == QWORD_MNEM_SUFFIX)
3279 suffix_check.no_qsuf = 1;
3280 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3281 suffix_check.no_ldsuf = 1;
3283 for (t = current_templates->start; t < current_templates->end; t++)
3285 addr_prefix_disp = -1;
3287 /* Must have right number of operands. */
3288 if (i.operands != t->operands)
3291 /* Check processor support. */
3292 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3293 if (!found_cpu_match)
3296 /* Check old gcc support. */
3297 if (!old_gcc && t->opcode_modifier.oldgcc)
3300 /* Check AT&T mnemonic. */
3301 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3304 /* Check AT&T syntax Intel syntax. */
3305 if ((intel_syntax && t->opcode_modifier.attsyntax)
3306 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3309 /* Check the suffix, except for some instructions in intel mode. */
3310 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3311 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3312 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3313 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3314 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3315 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3316 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3319 if (!operand_size_match (t))
3322 for (j = 0; j < MAX_OPERANDS; j++)
3323 operand_types[j] = t->operand_types[j];
3325 /* In general, don't allow 64-bit operands in 32-bit mode. */
3326 if (i.suffix == QWORD_MNEM_SUFFIX
3327 && flag_code != CODE_64BIT
3329 ? (!t->opcode_modifier.ignoresize
3330 && !intel_float_operand (t->name))
3331 : intel_float_operand (t->name) != 2)
3332 && ((!operand_types[0].bitfield.regmmx
3333 && !operand_types[0].bitfield.regxmm)
3334 || (!operand_types[t->operands > 1].bitfield.regmmx
3335 && !!operand_types[t->operands > 1].bitfield.regxmm))
3336 && (t->base_opcode != 0x0fc7
3337 || t->extension_opcode != 1 /* cmpxchg8b */))
3340 /* Do not verify operands when there are none. */
3344 /* We've found a match; break out of loop. */
3348 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3349 into Disp32/Disp16/Disp32 operand. */
3350 if (i.prefix[ADDR_PREFIX] != 0)
3352 /* There should be only one Disp operand. */
3356 for (j = 0; j < MAX_OPERANDS; j++)
3358 if (operand_types[j].bitfield.disp16)
3360 addr_prefix_disp = j;
3361 operand_types[j].bitfield.disp32 = 1;
3362 operand_types[j].bitfield.disp16 = 0;
3368 for (j = 0; j < MAX_OPERANDS; j++)
3370 if (operand_types[j].bitfield.disp32)
3372 addr_prefix_disp = j;
3373 operand_types[j].bitfield.disp32 = 0;
3374 operand_types[j].bitfield.disp16 = 1;
3380 for (j = 0; j < MAX_OPERANDS; j++)
3382 if (operand_types[j].bitfield.disp64)
3384 addr_prefix_disp = j;
3385 operand_types[j].bitfield.disp64 = 0;
3386 operand_types[j].bitfield.disp32 = 1;
3394 /* We check register size only if size of operands can be
3395 encoded the canonical way. */
3396 check_register = t->opcode_modifier.w;
3397 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3398 switch (t->operands)
3401 if (!operand_type_match (overlap0, i.types[0]))
3405 /* xchg %eax, %eax is a special case. It is an aliase for nop
3406 only in 32bit mode and we can use opcode 0x90. In 64bit
3407 mode, we can't use 0x90 for xchg %eax, %eax since it should
3408 zero-extend %eax to %rax. */
3409 if (flag_code == CODE_64BIT
3410 && t->base_opcode == 0x90
3411 && operand_type_equal (&i.types [0], &acc32)
3412 && operand_type_equal (&i.types [1], &acc32))
3416 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3417 if (!operand_type_match (overlap0, i.types[0])
3418 || !operand_type_match (overlap1, i.types[1])
3420 && !operand_type_register_match (overlap0, i.types[0],
3422 overlap1, i.types[1],
3425 /* Check if other direction is valid ... */
3426 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3429 /* Try reversing direction of operands. */
3430 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3431 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3432 if (!operand_type_match (overlap0, i.types[0])
3433 || !operand_type_match (overlap1, i.types[1])
3435 && !operand_type_register_match (overlap0,
3442 /* Does not match either direction. */
3445 /* found_reverse_match holds which of D or FloatDR
3447 if (t->opcode_modifier.d)
3448 found_reverse_match = Opcode_D;
3449 else if (t->opcode_modifier.floatd)
3450 found_reverse_match = Opcode_FloatD;
3452 found_reverse_match = 0;
3453 if (t->opcode_modifier.floatr)
3454 found_reverse_match |= Opcode_FloatR;
3458 /* Found a forward 2 operand match here. */
3459 switch (t->operands)
3462 overlap3 = operand_type_and (i.types[3],
3465 overlap2 = operand_type_and (i.types[2],
3470 switch (t->operands)
3473 if (!operand_type_match (overlap3, i.types[3])
3475 && !operand_type_register_match (overlap2,
3483 /* Here we make use of the fact that there are no
3484 reverse match 3 operand instructions, and all 3
3485 operand instructions only need to be checked for
3486 register consistency between operands 2 and 3. */
3487 if (!operand_type_match (overlap2, i.types[2])
3489 && !operand_type_register_match (overlap1,
3499 /* Found either forward/reverse 2, 3 or 4 operand match here:
3500 slip through to break. */
3502 if (!found_cpu_match)
3504 found_reverse_match = 0;
3507 /* We've found a match; break out of loop. */
3511 if (t == current_templates->end)
3513 /* We found no match. */
3514 as_bad (_("suffix or operands invalid for `%s'"),
3515 current_templates->start->name);
3519 if (!quiet_warnings)
3522 && (i.types[0].bitfield.jumpabsolute
3523 != operand_types[0].bitfield.jumpabsolute))
3525 as_warn (_("indirect %s without `*'"), t->name);
3528 if (t->opcode_modifier.isprefix
3529 && t->opcode_modifier.ignoresize)
3531 /* Warn them that a data or address size prefix doesn't
3532 affect assembly of the next line of code. */
3533 as_warn (_("stand-alone `%s' prefix"), t->name);
3537 /* Copy the template we found. */
3540 if (addr_prefix_disp != -1)
3541 i.tm.operand_types[addr_prefix_disp]
3542 = operand_types[addr_prefix_disp];
3544 if (found_reverse_match)
3546 /* If we found a reverse match we must alter the opcode
3547 direction bit. found_reverse_match holds bits to change
3548 (different for int & float insns). */
3550 i.tm.base_opcode ^= found_reverse_match;
3552 i.tm.operand_types[0] = operand_types[1];
3553 i.tm.operand_types[1] = operand_types[0];
3562 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3563 if (i.tm.operand_types[mem_op].bitfield.esseg)
3565 if (i.seg[0] != NULL && i.seg[0] != &es)
3567 as_bad (_("`%s' operand %d must use `%%es' segment"),
3572 /* There's only ever one segment override allowed per instruction.
3573 This instruction possibly has a legal segment override on the
3574 second operand, so copy the segment to where non-string
3575 instructions store it, allowing common code. */
3576 i.seg[0] = i.seg[1];
3578 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3580 if (i.seg[1] != NULL && i.seg[1] != &es)
3582 as_bad (_("`%s' operand %d must use `%%es' segment"),
3592 process_suffix (void)
3594 /* If matched instruction specifies an explicit instruction mnemonic
3596 if (i.tm.opcode_modifier.size16)
3597 i.suffix = WORD_MNEM_SUFFIX;
3598 else if (i.tm.opcode_modifier.size32)
3599 i.suffix = LONG_MNEM_SUFFIX;
3600 else if (i.tm.opcode_modifier.size64)
3601 i.suffix = QWORD_MNEM_SUFFIX;
3602 else if (i.reg_operands)
3604 /* If there's no instruction mnemonic suffix we try to invent one
3605 based on register operands. */
3608 /* We take i.suffix from the last register operand specified,
3609 Destination register type is more significant than source
3610 register type. crc32 in SSE4.2 prefers source register
3612 if (i.tm.base_opcode == 0xf20f38f1)
3614 if (i.types[0].bitfield.reg16)
3615 i.suffix = WORD_MNEM_SUFFIX;
3616 else if (i.types[0].bitfield.reg32)
3617 i.suffix = LONG_MNEM_SUFFIX;
3618 else if (i.types[0].bitfield.reg64)
3619 i.suffix = QWORD_MNEM_SUFFIX;
3621 else if (i.tm.base_opcode == 0xf20f38f0)
3623 if (i.types[0].bitfield.reg8)
3624 i.suffix = BYTE_MNEM_SUFFIX;
3631 if (i.tm.base_opcode == 0xf20f38f1
3632 || i.tm.base_opcode == 0xf20f38f0)
3634 /* We have to know the operand size for crc32. */
3635 as_bad (_("ambiguous memory operand size for `%s`"),
3640 for (op = i.operands; --op >= 0;)
3641 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3643 if (i.types[op].bitfield.reg8)
3645 i.suffix = BYTE_MNEM_SUFFIX;
3648 else if (i.types[op].bitfield.reg16)
3650 i.suffix = WORD_MNEM_SUFFIX;
3653 else if (i.types[op].bitfield.reg32)
3655 i.suffix = LONG_MNEM_SUFFIX;
3658 else if (i.types[op].bitfield.reg64)
3660 i.suffix = QWORD_MNEM_SUFFIX;
3666 else if (i.suffix == BYTE_MNEM_SUFFIX)
3668 if (!check_byte_reg ())
3671 else if (i.suffix == LONG_MNEM_SUFFIX)
3673 if (!check_long_reg ())
3676 else if (i.suffix == QWORD_MNEM_SUFFIX)
3679 && i.tm.opcode_modifier.ignoresize
3680 && i.tm.opcode_modifier.no_qsuf)
3682 else if (!check_qword_reg ())
3685 else if (i.suffix == WORD_MNEM_SUFFIX)
3687 if (!check_word_reg ())
3690 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3692 /* Skip if the instruction has x suffix. match_template
3693 should check if it is a valid suffix. */
3695 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3696 /* Do nothing if the instruction is going to ignore the prefix. */
3701 else if (i.tm.opcode_modifier.defaultsize
3703 /* exclude fldenv/frstor/fsave/fstenv */
3704 && i.tm.opcode_modifier.no_ssuf)
3706 i.suffix = stackop_size;
3708 else if (intel_syntax
3710 && (i.tm.operand_types[0].bitfield.jumpabsolute
3711 || i.tm.opcode_modifier.jumpbyte
3712 || i.tm.opcode_modifier.jumpintersegment
3713 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3714 && i.tm.extension_opcode <= 3)))
3719 if (!i.tm.opcode_modifier.no_qsuf)
3721 i.suffix = QWORD_MNEM_SUFFIX;
3725 if (!i.tm.opcode_modifier.no_lsuf)
3726 i.suffix = LONG_MNEM_SUFFIX;
3729 if (!i.tm.opcode_modifier.no_wsuf)
3730 i.suffix = WORD_MNEM_SUFFIX;
3739 if (i.tm.opcode_modifier.w)
3741 as_bad (_("no instruction mnemonic suffix given and "
3742 "no register operands; can't size instruction"));
3748 unsigned int suffixes;
3750 suffixes = !i.tm.opcode_modifier.no_bsuf;
3751 if (!i.tm.opcode_modifier.no_wsuf)
3753 if (!i.tm.opcode_modifier.no_lsuf)
3755 if (!i.tm.opcode_modifier.no_ldsuf)
3757 if (!i.tm.opcode_modifier.no_ssuf)
3759 if (!i.tm.opcode_modifier.no_qsuf)
3762 /* There are more than suffix matches. */
3763 if (i.tm.opcode_modifier.w
3764 || ((suffixes & (suffixes - 1))
3765 && !i.tm.opcode_modifier.defaultsize
3766 && !i.tm.opcode_modifier.ignoresize))
3768 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3774 /* Change the opcode based on the operand size given by i.suffix;
3775 We don't need to change things for byte insns. */
3778 && i.suffix != BYTE_MNEM_SUFFIX
3779 && i.suffix != XMMWORD_MNEM_SUFFIX)
3781 /* It's not a byte, select word/dword operation. */
3782 if (i.tm.opcode_modifier.w)
3784 if (i.tm.opcode_modifier.shortform)
3785 i.tm.base_opcode |= 8;
3787 i.tm.base_opcode |= 1;
3790 /* Now select between word & dword operations via the operand
3791 size prefix, except for instructions that will ignore this
3793 if (i.tm.opcode_modifier.addrprefixop0)
3795 /* The address size override prefix changes the size of the
3797 if ((flag_code == CODE_32BIT
3798 && i.op->regs[0].reg_type.bitfield.reg16)
3799 || (flag_code != CODE_32BIT
3800 && i.op->regs[0].reg_type.bitfield.reg32))
3801 if (!add_prefix (ADDR_PREFIX_OPCODE))
3804 else if (i.suffix != QWORD_MNEM_SUFFIX
3805 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3806 && !i.tm.opcode_modifier.ignoresize
3807 && !i.tm.opcode_modifier.floatmf
3808 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3809 || (flag_code == CODE_64BIT
3810 && i.tm.opcode_modifier.jumpbyte)))
3812 unsigned int prefix = DATA_PREFIX_OPCODE;
3814 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3815 prefix = ADDR_PREFIX_OPCODE;
3817 if (!add_prefix (prefix))
3821 /* Set mode64 for an operand. */
3822 if (i.suffix == QWORD_MNEM_SUFFIX
3823 && flag_code == CODE_64BIT
3824 && !i.tm.opcode_modifier.norex64)
3826 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3827 need rex64. cmpxchg8b is also a special case. */
3828 if (! (i.operands == 2
3829 && i.tm.base_opcode == 0x90
3830 && i.tm.extension_opcode == None
3831 && operand_type_equal (&i.types [0], &acc64)
3832 && operand_type_equal (&i.types [1], &acc64))
3833 && ! (i.operands == 1
3834 && i.tm.base_opcode == 0xfc7
3835 && i.tm.extension_opcode == 1
3836 && !operand_type_check (i.types [0], reg)
3837 && operand_type_check (i.types [0], anymem)))
3841 /* Size floating point instruction. */
3842 if (i.suffix == LONG_MNEM_SUFFIX)
3843 if (i.tm.opcode_modifier.floatmf)
3844 i.tm.base_opcode ^= 4;
3851 check_byte_reg (void)
3855 for (op = i.operands; --op >= 0;)
3857 /* If this is an eight bit register, it's OK. If it's the 16 or
3858 32 bit version of an eight bit register, we will just use the
3859 low portion, and that's OK too. */
3860 if (i.types[op].bitfield.reg8)
3863 /* Don't generate this warning if not needed. */
3864 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3867 /* crc32 doesn't generate this warning. */
3868 if (i.tm.base_opcode == 0xf20f38f0)
3871 if ((i.types[op].bitfield.reg16
3872 || i.types[op].bitfield.reg32
3873 || i.types[op].bitfield.reg64)
3874 && i.op[op].regs->reg_num < 4)
3876 /* Prohibit these changes in the 64bit mode, since the
3877 lowering is more complicated. */
3878 if (flag_code == CODE_64BIT
3879 && !i.tm.operand_types[op].bitfield.inoutportreg)
3881 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3882 register_prefix, i.op[op].regs->reg_name,
3886 #if REGISTER_WARNINGS
3888 && !i.tm.operand_types[op].bitfield.inoutportreg)
3889 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3891 (i.op[op].regs + (i.types[op].bitfield.reg16
3892 ? REGNAM_AL - REGNAM_AX
3893 : REGNAM_AL - REGNAM_EAX))->reg_name,
3895 i.op[op].regs->reg_name,
3900 /* Any other register is bad. */
3901 if (i.types[op].bitfield.reg16
3902 || i.types[op].bitfield.reg32
3903 || i.types[op].bitfield.reg64
3904 || i.types[op].bitfield.regmmx
3905 || i.types[op].bitfield.regxmm
3906 || i.types[op].bitfield.sreg2
3907 || i.types[op].bitfield.sreg3
3908 || i.types[op].bitfield.control
3909 || i.types[op].bitfield.debug
3910 || i.types[op].bitfield.test
3911 || i.types[op].bitfield.floatreg
3912 || i.types[op].bitfield.floatacc)
3914 as_bad (_("`%s%s' not allowed with `%s%c'"),
3916 i.op[op].regs->reg_name,
3926 check_long_reg (void)
3930 for (op = i.operands; --op >= 0;)
3931 /* Reject eight bit registers, except where the template requires
3932 them. (eg. movzb) */
3933 if (i.types[op].bitfield.reg8
3934 && (i.tm.operand_types[op].bitfield.reg16
3935 || i.tm.operand_types[op].bitfield.reg32
3936 || i.tm.operand_types[op].bitfield.acc))
3938 as_bad (_("`%s%s' not allowed with `%s%c'"),
3940 i.op[op].regs->reg_name,
3945 /* Warn if the e prefix on a general reg is missing. */
3946 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3947 && i.types[op].bitfield.reg16
3948 && (i.tm.operand_types[op].bitfield.reg32
3949 || i.tm.operand_types[op].bitfield.acc))
3951 /* Prohibit these changes in the 64bit mode, since the
3952 lowering is more complicated. */
3953 if (flag_code == CODE_64BIT)
3955 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3956 register_prefix, i.op[op].regs->reg_name,
3960 #if REGISTER_WARNINGS
3962 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3964 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3966 i.op[op].regs->reg_name,
3970 /* Warn if the r prefix on a general reg is missing. */
3971 else if (i.types[op].bitfield.reg64
3972 && (i.tm.operand_types[op].bitfield.reg32
3973 || i.tm.operand_types[op].bitfield.acc))
3976 && i.tm.opcode_modifier.toqword
3977 && !i.types[0].bitfield.regxmm)
3979 /* Convert to QWORD. We want REX byte. */
3980 i.suffix = QWORD_MNEM_SUFFIX;
3984 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3985 register_prefix, i.op[op].regs->reg_name,
3994 check_qword_reg (void)
3998 for (op = i.operands; --op >= 0; )
3999 /* Reject eight bit registers, except where the template requires
4000 them. (eg. movzb) */
4001 if (i.types[op].bitfield.reg8
4002 && (i.tm.operand_types[op].bitfield.reg16
4003 || i.tm.operand_types[op].bitfield.reg32
4004 || i.tm.operand_types[op].bitfield.acc))
4006 as_bad (_("`%s%s' not allowed with `%s%c'"),
4008 i.op[op].regs->reg_name,
4013 /* Warn if the e prefix on a general reg is missing. */
4014 else if ((i.types[op].bitfield.reg16
4015 || i.types[op].bitfield.reg32)
4016 && (i.tm.operand_types[op].bitfield.reg32
4017 || i.tm.operand_types[op].bitfield.acc))
4019 /* Prohibit these changes in the 64bit mode, since the
4020 lowering is more complicated. */
4022 && i.tm.opcode_modifier.todword
4023 && !i.types[0].bitfield.regxmm)
4025 /* Convert to DWORD. We don't want REX byte. */
4026 i.suffix = LONG_MNEM_SUFFIX;
4030 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4031 register_prefix, i.op[op].regs->reg_name,
4040 check_word_reg (void)
4043 for (op = i.operands; --op >= 0;)
4044 /* Reject eight bit registers, except where the template requires
4045 them. (eg. movzb) */
4046 if (i.types[op].bitfield.reg8
4047 && (i.tm.operand_types[op].bitfield.reg16
4048 || i.tm.operand_types[op].bitfield.reg32
4049 || i.tm.operand_types[op].bitfield.acc))
4051 as_bad (_("`%s%s' not allowed with `%s%c'"),
4053 i.op[op].regs->reg_name,
4058 /* Warn if the e prefix on a general reg is present. */
4059 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4060 && i.types[op].bitfield.reg32
4061 && (i.tm.operand_types[op].bitfield.reg16
4062 || i.tm.operand_types[op].bitfield.acc))
4064 /* Prohibit these changes in the 64bit mode, since the
4065 lowering is more complicated. */
4066 if (flag_code == CODE_64BIT)
4068 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4069 register_prefix, i.op[op].regs->reg_name,
4074 #if REGISTER_WARNINGS
4075 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4077 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4079 i.op[op].regs->reg_name,
4087 update_imm (unsigned int j)
4089 i386_operand_type overlap;
4091 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4092 if ((overlap.bitfield.imm8
4093 || overlap.bitfield.imm8s
4094 || overlap.bitfield.imm16
4095 || overlap.bitfield.imm32
4096 || overlap.bitfield.imm32s
4097 || overlap.bitfield.imm64)
4098 && !operand_type_equal (&overlap, &imm8)
4099 && !operand_type_equal (&overlap, &imm8s)
4100 && !operand_type_equal (&overlap, &imm16)
4101 && !operand_type_equal (&overlap, &imm32)
4102 && !operand_type_equal (&overlap, &imm32s)
4103 && !operand_type_equal (&overlap, &imm64))
4107 i386_operand_type temp;
4109 operand_type_set (&temp, 0);
4110 if (i.suffix == BYTE_MNEM_SUFFIX)
4112 temp.bitfield.imm8 = overlap.bitfield.imm8;
4113 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4115 else if (i.suffix == WORD_MNEM_SUFFIX)
4116 temp.bitfield.imm16 = overlap.bitfield.imm16;
4117 else if (i.suffix == QWORD_MNEM_SUFFIX)
4119 temp.bitfield.imm64 = overlap.bitfield.imm64;
4120 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4123 temp.bitfield.imm32 = overlap.bitfield.imm32;
4126 else if (operand_type_equal (&overlap, &imm16_32_32s)
4127 || operand_type_equal (&overlap, &imm16_32)
4128 || operand_type_equal (&overlap, &imm16_32s))
4130 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4135 if (!operand_type_equal (&overlap, &imm8)
4136 && !operand_type_equal (&overlap, &imm8s)
4137 && !operand_type_equal (&overlap, &imm16)
4138 && !operand_type_equal (&overlap, &imm32)
4139 && !operand_type_equal (&overlap, &imm32s)
4140 && !operand_type_equal (&overlap, &imm64))
4142 as_bad (_("no instruction mnemonic suffix given; "
4143 "can't determine immediate size"));
4147 i.types[j] = overlap;
4157 for (j = 0; j < 2; j++)
4158 if (update_imm (j) == 0)
4161 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4162 assert (operand_type_check (i.types[2], imm) == 0);
4170 i.drex.modrm_reg = 0;
4171 i.drex.modrm_regmem = 0;
4173 /* SSE5 4 operand instructions must have the destination the same as
4174 one of the inputs. Figure out the destination register and cache
4175 it away in the drex field, and remember which fields to use for
4177 if (i.tm.opcode_modifier.drex
4178 && i.tm.opcode_modifier.drexv
4181 i.tm.extension_opcode = None;
4183 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4184 if (i.types[0].bitfield.regxmm != 0
4185 && i.types[1].bitfield.regxmm != 0
4186 && i.types[2].bitfield.regxmm != 0
4187 && i.types[3].bitfield.regxmm != 0
4188 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4189 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4191 /* Clear the arguments that are stored in drex. */
4192 operand_type_set (&i.types[0], 0);
4193 operand_type_set (&i.types[3], 0);
4194 i.reg_operands -= 2;
4196 /* There are two different ways to encode a 4 operand
4197 instruction with all registers that uses OC1 set to
4198 0 or 1. Favor setting OC1 to 0 since this mimics the
4199 actions of other SSE5 assemblers. Use modrm encoding 2
4200 for register/register. Include the high order bit that
4201 is normally stored in the REX byte in the register
4203 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4204 i.drex.modrm_reg = 2;
4205 i.drex.modrm_regmem = 1;
4206 i.drex.reg = (i.op[3].regs->reg_num
4207 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4210 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4211 else if (i.types[0].bitfield.regxmm != 0
4212 && i.types[1].bitfield.regxmm != 0
4213 && (i.types[2].bitfield.regxmm
4214 || operand_type_check (i.types[2], anymem))
4215 && i.types[3].bitfield.regxmm != 0
4216 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4217 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4219 /* clear the arguments that are stored in drex */
4220 operand_type_set (&i.types[0], 0);
4221 operand_type_set (&i.types[3], 0);
4222 i.reg_operands -= 2;
4224 /* Specify the modrm encoding for memory addressing. Include
4225 the high order bit that is normally stored in the REX byte
4226 in the register field. */
4227 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4228 i.drex.modrm_reg = 1;
4229 i.drex.modrm_regmem = 2;
4230 i.drex.reg = (i.op[3].regs->reg_num
4231 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4234 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4235 else if (i.types[0].bitfield.regxmm != 0
4236 && operand_type_check (i.types[1], anymem) != 0
4237 && i.types[2].bitfield.regxmm != 0
4238 && i.types[3].bitfield.regxmm != 0
4239 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4240 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4242 /* Clear the arguments that are stored in drex. */
4243 operand_type_set (&i.types[0], 0);
4244 operand_type_set (&i.types[3], 0);
4245 i.reg_operands -= 2;
4247 /* Specify the modrm encoding for memory addressing. Include
4248 the high order bit that is normally stored in the REX byte
4249 in the register field. */
4250 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4251 i.drex.modrm_reg = 2;
4252 i.drex.modrm_regmem = 1;
4253 i.drex.reg = (i.op[3].regs->reg_num
4254 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4257 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4258 else if (i.types[0].bitfield.regxmm != 0
4259 && i.types[1].bitfield.regxmm != 0
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0
4262 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4263 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4265 /* clear the arguments that are stored in drex */
4266 operand_type_set (&i.types[2], 0);
4267 operand_type_set (&i.types[3], 0);
4268 i.reg_operands -= 2;
4270 /* There are two different ways to encode a 4 operand
4271 instruction with all registers that uses OC1 set to
4272 0 or 1. Favor setting OC1 to 0 since this mimics the
4273 actions of other SSE5 assemblers. Use modrm encoding
4274 2 for register/register. Include the high order bit that
4275 is normally stored in the REX byte in the register
4277 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4278 i.drex.modrm_reg = 1;
4279 i.drex.modrm_regmem = 0;
4281 /* Remember the register, including the upper bits */
4282 i.drex.reg = (i.op[3].regs->reg_num
4283 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4286 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4287 else if (i.types[0].bitfield.regxmm != 0
4288 && (i.types[1].bitfield.regxmm
4289 || operand_type_check (i.types[1], anymem))
4290 && i.types[2].bitfield.regxmm != 0
4291 && i.types[3].bitfield.regxmm != 0
4292 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4293 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4295 /* Clear the arguments that are stored in drex. */
4296 operand_type_set (&i.types[2], 0);
4297 operand_type_set (&i.types[3], 0);
4298 i.reg_operands -= 2;
4300 /* Specify the modrm encoding and remember the register
4301 including the bits normally stored in the REX byte. */
4302 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4303 i.drex.modrm_reg = 0;
4304 i.drex.modrm_regmem = 1;
4305 i.drex.reg = (i.op[3].regs->reg_num
4306 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4309 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4310 else if (operand_type_check (i.types[0], anymem) != 0
4311 && i.types[1].bitfield.regxmm != 0
4312 && i.types[2].bitfield.regxmm != 0
4313 && i.types[3].bitfield.regxmm != 0
4314 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4315 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4317 /* clear the arguments that are stored in drex */
4318 operand_type_set (&i.types[2], 0);
4319 operand_type_set (&i.types[3], 0);
4320 i.reg_operands -= 2;
4322 /* Specify the modrm encoding and remember the register
4323 including the bits normally stored in the REX byte. */
4324 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4325 i.drex.modrm_reg = 1;
4326 i.drex.modrm_regmem = 0;
4327 i.drex.reg = (i.op[3].regs->reg_num
4328 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4332 as_bad (_("Incorrect operands for the '%s' instruction"),
4336 /* SSE5 instructions with the DREX byte where the only memory operand
4337 is in the 2nd argument, and the first and last xmm register must
4338 match, and is encoded in the DREX byte. */
4339 else if (i.tm.opcode_modifier.drex
4340 && !i.tm.opcode_modifier.drexv
4343 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4344 if (i.types[0].bitfield.regxmm != 0
4345 && (i.types[1].bitfield.regxmm
4346 || operand_type_check(i.types[1], anymem))
4347 && i.types[2].bitfield.regxmm != 0
4348 && i.types[3].bitfield.regxmm != 0
4349 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4350 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4352 /* clear the arguments that are stored in drex */
4353 operand_type_set (&i.types[0], 0);
4354 operand_type_set (&i.types[3], 0);
4355 i.reg_operands -= 2;
4357 /* Specify the modrm encoding and remember the register
4358 including the high bit normally stored in the REX
4360 i.drex.modrm_reg = 2;
4361 i.drex.modrm_regmem = 1;
4362 i.drex.reg = (i.op[3].regs->reg_num
4363 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4367 as_bad (_("Incorrect operands for the '%s' instruction"),
4371 /* SSE5 3 operand instructions that the result is a register, being
4372 either operand can be a memory operand, using OC0 to note which
4373 one is the memory. */
4374 else if (i.tm.opcode_modifier.drex
4375 && i.tm.opcode_modifier.drexv
4378 i.tm.extension_opcode = None;
4380 /* Case 1: 3 operand insn, src1 = register. */
4381 if (i.types[0].bitfield.regxmm != 0
4382 && i.types[1].bitfield.regxmm != 0
4383 && i.types[2].bitfield.regxmm != 0)
4385 /* Clear the arguments that are stored in drex. */
4386 operand_type_set (&i.types[2], 0);
4389 /* Specify the modrm encoding and remember the register
4390 including the high bit normally stored in the REX byte. */
4391 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4392 i.drex.modrm_reg = 1;
4393 i.drex.modrm_regmem = 0;
4394 i.drex.reg = (i.op[2].regs->reg_num
4395 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4398 /* Case 2: 3 operand insn, src1 = memory. */
4399 else if (operand_type_check (i.types[0], anymem) != 0
4400 && i.types[1].bitfield.regxmm != 0
4401 && i.types[2].bitfield.regxmm != 0)
4403 /* Clear the arguments that are stored in drex. */
4404 operand_type_set (&i.types[2], 0);
4407 /* Specify the modrm encoding and remember the register
4408 including the high bit normally stored in the REX
4410 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4411 i.drex.modrm_reg = 1;
4412 i.drex.modrm_regmem = 0;
4413 i.drex.reg = (i.op[2].regs->reg_num
4414 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4417 /* Case 3: 3 operand insn, src2 = memory. */
4418 else if (i.types[0].bitfield.regxmm != 0
4419 && operand_type_check (i.types[1], anymem) != 0
4420 && i.types[2].bitfield.regxmm != 0)
4422 /* Clear the arguments that are stored in drex. */
4423 operand_type_set (&i.types[2], 0);
4426 /* Specify the modrm encoding and remember the register
4427 including the high bit normally stored in the REX byte. */
4428 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4429 i.drex.modrm_reg = 0;
4430 i.drex.modrm_regmem = 1;
4431 i.drex.reg = (i.op[2].regs->reg_num
4432 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4436 as_bad (_("Incorrect operands for the '%s' instruction"),
4440 /* SSE5 4 operand instructions that are the comparison instructions
4441 where the first operand is the immediate value of the comparison
4443 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4445 /* Case 1: 4 operand insn, src1 = reg/memory. */
4446 if (operand_type_check (i.types[0], imm) != 0
4447 && (i.types[1].bitfield.regxmm
4448 || operand_type_check (i.types[1], anymem))
4449 && i.types[2].bitfield.regxmm != 0
4450 && i.types[3].bitfield.regxmm != 0)
4452 /* clear the arguments that are stored in drex */
4453 operand_type_set (&i.types[3], 0);
4456 /* Specify the modrm encoding and remember the register
4457 including the high bit normally stored in the REX byte. */
4458 i.drex.modrm_reg = 2;
4459 i.drex.modrm_regmem = 1;
4460 i.drex.reg = (i.op[3].regs->reg_num
4461 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4464 /* Case 2: 3 operand insn with ImmExt that places the
4465 opcode_extension as an immediate argument. This is used for
4466 all of the varients of comparison that supplies the appropriate
4467 value as part of the instruction. */
4468 else if ((i.types[0].bitfield.regxmm
4469 || operand_type_check (i.types[0], anymem))
4470 && i.types[1].bitfield.regxmm != 0
4471 && i.types[2].bitfield.regxmm != 0
4472 && operand_type_check (i.types[3], imm) != 0)
4474 /* clear the arguments that are stored in drex */
4475 operand_type_set (&i.types[2], 0);
4478 /* Specify the modrm encoding and remember the register
4479 including the high bit normally stored in the REX byte. */
4480 i.drex.modrm_reg = 1;
4481 i.drex.modrm_regmem = 0;
4482 i.drex.reg = (i.op[2].regs->reg_num
4483 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4487 as_bad (_("Incorrect operands for the '%s' instruction"),
4491 else if (i.tm.opcode_modifier.drex
4492 || i.tm.opcode_modifier.drexv
4493 || i.tm.opcode_modifier.drexc)
4494 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4498 process_operands (void)
4500 /* Default segment register this instruction will use for memory
4501 accesses. 0 means unknown. This is only for optimizing out
4502 unnecessary segment overrides. */
4503 const seg_entry *default_seg = 0;
4505 /* Handle all of the DREX munging that SSE5 needs. */
4506 if (i.tm.opcode_modifier.drex
4507 || i.tm.opcode_modifier.drexv
4508 || i.tm.opcode_modifier.drexc)
4511 if (i.tm.opcode_modifier.firstxmm0)
4515 /* The first operand is implicit and must be xmm0. */
4516 assert (i.reg_operands
4517 && operand_type_equal (&i.types[0], ®xmm));
4518 if (i.op[0].regs->reg_num != 0)
4521 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4522 i.tm.name, register_prefix);
4524 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4525 i.tm.name, register_prefix);
4529 for (j = 1; j < i.operands; j++)
4531 i.op[j - 1] = i.op[j];
4532 i.types[j - 1] = i.types[j];
4534 /* We need to adjust fields in i.tm since they are used by
4535 build_modrm_byte. */
4536 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4543 else if (i.tm.opcode_modifier.regkludge)
4545 /* The imul $imm, %reg instruction is converted into
4546 imul $imm, %reg, %reg, and the clr %reg instruction
4547 is converted into xor %reg, %reg. */
4549 unsigned int first_reg_op;
4551 if (operand_type_check (i.types[0], reg))
4555 /* Pretend we saw the extra register operand. */
4556 assert (i.reg_operands == 1
4557 && i.op[first_reg_op + 1].regs == 0);
4558 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4559 i.types[first_reg_op + 1] = i.types[first_reg_op];
4564 if (i.tm.opcode_modifier.shortform)
4566 if (i.types[0].bitfield.sreg2
4567 || i.types[0].bitfield.sreg3)
4569 if (i.tm.base_opcode == POP_SEG_SHORT
4570 && i.op[0].regs->reg_num == 1)
4572 as_bad (_("you can't `pop %%cs'"));
4575 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4576 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4581 /* The register or float register operand is in operand
4585 if (i.types[0].bitfield.floatreg
4586 || operand_type_check (i.types[0], reg))
4590 /* Register goes in low 3 bits of opcode. */
4591 i.tm.base_opcode |= i.op[op].regs->reg_num;
4592 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4594 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4596 /* Warn about some common errors, but press on regardless.
4597 The first case can be generated by gcc (<= 2.8.1). */
4598 if (i.operands == 2)
4600 /* Reversed arguments on faddp, fsubp, etc. */
4601 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4602 register_prefix, i.op[1].regs->reg_name,
4603 register_prefix, i.op[0].regs->reg_name);
4607 /* Extraneous `l' suffix on fp insn. */
4608 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4609 register_prefix, i.op[0].regs->reg_name);
4614 else if (i.tm.opcode_modifier.modrm)
4616 /* The opcode is completed (modulo i.tm.extension_opcode which
4617 must be put into the modrm byte). Now, we make the modrm and
4618 index base bytes based on all the info we've collected. */
4620 default_seg = build_modrm_byte ();
4622 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4626 else if (i.tm.opcode_modifier.isstring)
4628 /* For the string instructions that allow a segment override
4629 on one of their operands, the default segment is ds. */
4633 if (i.tm.base_opcode == 0x8d /* lea */
4636 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4638 /* If a segment was explicitly specified, and the specified segment
4639 is not the default, use an opcode prefix to select it. If we
4640 never figured out what the default segment is, then default_seg
4641 will be zero at this point, and the specified segment prefix will
4643 if ((i.seg[0]) && (i.seg[0] != default_seg))
4645 if (!add_prefix (i.seg[0]->seg_prefix))
4651 static const seg_entry *
4652 build_modrm_byte (void)
4654 const seg_entry *default_seg = 0;
4656 /* SSE5 4 operand instructions are encoded in such a way that one of
4657 the inputs must match the destination register. Process_drex hides
4658 the 3rd argument in the drex field, so that by the time we get
4659 here, it looks to GAS as if this is a 2 operand instruction. */
4660 if ((i.tm.opcode_modifier.drex
4661 || i.tm.opcode_modifier.drexv
4662 || i.tm.opcode_modifier.drexc)
4663 && i.reg_operands == 2)
4665 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4666 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4668 i.rm.reg = reg->reg_num;
4669 i.rm.regmem = regmem->reg_num;
4671 if ((reg->reg_flags & RegRex) != 0)
4673 if ((regmem->reg_flags & RegRex) != 0)
4677 /* i.reg_operands MUST be the number of real register operands;
4678 implicit registers do not count. */
4679 else if (i.reg_operands == 2)
4681 unsigned int source, dest;
4689 /* When there are 3 operands, one of them may be immediate,
4690 which may be the first or the last operand. Otherwise,
4691 the first operand must be shift count register (cl). */
4692 assert (i.imm_operands == 1
4693 || (i.imm_operands == 0
4694 && i.types[0].bitfield.shiftcount));
4695 if (operand_type_check (i.types[0], imm)
4696 || i.types[0].bitfield.shiftcount)
4702 /* When there are 4 operands, the first two must be 8bit
4703 immediate operands. The source operand will be the 3rd
4705 assert (i.imm_operands == 2
4706 && i.types[0].bitfield.imm8
4707 && i.types[1].bitfield.imm8);
4717 /* One of the register operands will be encoded in the i.tm.reg
4718 field, the other in the combined i.tm.mode and i.tm.regmem
4719 fields. If no form of this instruction supports a memory
4720 destination operand, then we assume the source operand may
4721 sometimes be a memory operand and so we need to store the
4722 destination in the i.rm.reg field. */
4723 if (!i.tm.operand_types[dest].bitfield.regmem
4724 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4726 i.rm.reg = i.op[dest].regs->reg_num;
4727 i.rm.regmem = i.op[source].regs->reg_num;
4728 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4730 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4735 i.rm.reg = i.op[source].regs->reg_num;
4736 i.rm.regmem = i.op[dest].regs->reg_num;
4737 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4739 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4742 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4744 if (!i.types[0].bitfield.control
4745 && !i.types[1].bitfield.control)
4747 i.rex &= ~(REX_R | REX_B);
4748 add_prefix (LOCK_PREFIX_OPCODE);
4752 { /* If it's not 2 reg operands... */
4755 unsigned int fake_zero_displacement = 0;
4758 /* This has been precalculated for SSE5 instructions
4759 that have a DREX field earlier in process_drex. */
4760 if (i.tm.opcode_modifier.drex
4761 || i.tm.opcode_modifier.drexv
4762 || i.tm.opcode_modifier.drexc)
4763 op = i.drex.modrm_regmem;
4766 for (op = 0; op < i.operands; op++)
4767 if (operand_type_check (i.types[op], anymem))
4769 assert (op < i.operands);
4774 if (i.base_reg == 0)
4777 if (!i.disp_operands)
4778 fake_zero_displacement = 1;
4779 if (i.index_reg == 0)
4781 /* Operand is just <disp> */
4782 if (flag_code == CODE_64BIT)
4784 /* 64bit mode overwrites the 32bit absolute
4785 addressing by RIP relative addressing and
4786 absolute addressing is encoded by one of the
4787 redundant SIB forms. */
4788 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4789 i.sib.base = NO_BASE_REGISTER;
4790 i.sib.index = NO_INDEX_REGISTER;
4791 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4792 ? disp32s : disp32);
4794 else if ((flag_code == CODE_16BIT)
4795 ^ (i.prefix[ADDR_PREFIX] != 0))
4797 i.rm.regmem = NO_BASE_REGISTER_16;
4798 i.types[op] = disp16;
4802 i.rm.regmem = NO_BASE_REGISTER;
4803 i.types[op] = disp32;
4806 else /* !i.base_reg && i.index_reg */
4808 if (i.index_reg->reg_num == RegEiz
4809 || i.index_reg->reg_num == RegRiz)
4810 i.sib.index = NO_INDEX_REGISTER;
4812 i.sib.index = i.index_reg->reg_num;
4813 i.sib.base = NO_BASE_REGISTER;
4814 i.sib.scale = i.log2_scale_factor;
4815 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4816 i.types[op].bitfield.disp8 = 0;
4817 i.types[op].bitfield.disp16 = 0;
4818 i.types[op].bitfield.disp64 = 0;
4819 if (flag_code != CODE_64BIT)
4821 /* Must be 32 bit */
4822 i.types[op].bitfield.disp32 = 1;
4823 i.types[op].bitfield.disp32s = 0;
4827 i.types[op].bitfield.disp32 = 0;
4828 i.types[op].bitfield.disp32s = 1;
4830 if ((i.index_reg->reg_flags & RegRex) != 0)
4834 /* RIP addressing for 64bit mode. */
4835 else if (i.base_reg->reg_num == RegRip ||
4836 i.base_reg->reg_num == RegEip)
4838 i.rm.regmem = NO_BASE_REGISTER;
4839 i.types[op].bitfield.disp8 = 0;
4840 i.types[op].bitfield.disp16 = 0;
4841 i.types[op].bitfield.disp32 = 0;
4842 i.types[op].bitfield.disp32s = 1;
4843 i.types[op].bitfield.disp64 = 0;
4844 i.flags[op] |= Operand_PCrel;
4845 if (! i.disp_operands)
4846 fake_zero_displacement = 1;
4848 else if (i.base_reg->reg_type.bitfield.reg16)
4850 switch (i.base_reg->reg_num)
4853 if (i.index_reg == 0)
4855 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4856 i.rm.regmem = i.index_reg->reg_num - 6;
4860 if (i.index_reg == 0)
4863 if (operand_type_check (i.types[op], disp) == 0)
4865 /* fake (%bp) into 0(%bp) */
4866 i.types[op].bitfield.disp8 = 1;
4867 fake_zero_displacement = 1;
4870 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4871 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4873 default: /* (%si) -> 4 or (%di) -> 5 */
4874 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4876 i.rm.mode = mode_from_disp_size (i.types[op]);
4878 else /* i.base_reg and 32/64 bit mode */
4880 if (flag_code == CODE_64BIT
4881 && operand_type_check (i.types[op], disp))
4883 i386_operand_type temp;
4884 operand_type_set (&temp, 0);
4885 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4887 if (i.prefix[ADDR_PREFIX] == 0)
4888 i.types[op].bitfield.disp32s = 1;
4890 i.types[op].bitfield.disp32 = 1;
4893 i.rm.regmem = i.base_reg->reg_num;
4894 if ((i.base_reg->reg_flags & RegRex) != 0)
4896 i.sib.base = i.base_reg->reg_num;
4897 /* x86-64 ignores REX prefix bit here to avoid decoder
4899 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4902 if (i.disp_operands == 0)
4904 fake_zero_displacement = 1;
4905 i.types[op].bitfield.disp8 = 1;
4908 else if (i.base_reg->reg_num == ESP_REG_NUM)
4912 i.sib.scale = i.log2_scale_factor;
4913 if (i.index_reg == 0)
4915 /* <disp>(%esp) becomes two byte modrm with no index
4916 register. We've already stored the code for esp
4917 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4918 Any base register besides %esp will not use the
4919 extra modrm byte. */
4920 i.sib.index = NO_INDEX_REGISTER;
4924 if (i.index_reg->reg_num == RegEiz
4925 || i.index_reg->reg_num == RegRiz)
4926 i.sib.index = NO_INDEX_REGISTER;
4928 i.sib.index = i.index_reg->reg_num;
4929 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4930 if ((i.index_reg->reg_flags & RegRex) != 0)
4935 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4936 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4939 i.rm.mode = mode_from_disp_size (i.types[op]);
4942 if (fake_zero_displacement)
4944 /* Fakes a zero displacement assuming that i.types[op]
4945 holds the correct displacement size. */
4948 assert (i.op[op].disps == 0);
4949 exp = &disp_expressions[i.disp_operands++];
4950 i.op[op].disps = exp;
4951 exp->X_op = O_constant;
4952 exp->X_add_number = 0;
4953 exp->X_add_symbol = (symbolS *) 0;
4954 exp->X_op_symbol = (symbolS *) 0;
4958 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4959 (if any) based on i.tm.extension_opcode. Again, we must be
4960 careful to make sure that segment/control/debug/test/MMX
4961 registers are coded into the i.rm.reg field. */
4966 /* This has been precalculated for SSE5 instructions
4967 that have a DREX field earlier in process_drex. */
4968 if (i.tm.opcode_modifier.drex
4969 || i.tm.opcode_modifier.drexv
4970 || i.tm.opcode_modifier.drexc)
4972 op = i.drex.modrm_reg;
4973 i.rm.reg = i.op[op].regs->reg_num;
4974 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4979 for (op = 0; op < i.operands; op++)
4980 if (i.types[op].bitfield.reg8
4981 || i.types[op].bitfield.reg16
4982 || i.types[op].bitfield.reg32
4983 || i.types[op].bitfield.reg64
4984 || i.types[op].bitfield.regmmx
4985 || i.types[op].bitfield.regxmm
4986 || i.types[op].bitfield.sreg2
4987 || i.types[op].bitfield.sreg3
4988 || i.types[op].bitfield.control
4989 || i.types[op].bitfield.debug
4990 || i.types[op].bitfield.test)
4993 assert (op < i.operands);
4995 /* If there is an extension opcode to put here, the
4996 register number must be put into the regmem field. */
4997 if (i.tm.extension_opcode != None)
4999 i.rm.regmem = i.op[op].regs->reg_num;
5000 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5005 i.rm.reg = i.op[op].regs->reg_num;
5006 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5011 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5012 must set it to 3 to indicate this is a register operand
5013 in the regmem field. */
5014 if (!i.mem_operands)
5018 /* Fill in i.rm.reg field with extension opcode (if any). */
5019 if (i.tm.extension_opcode != None
5020 && !(i.tm.opcode_modifier.drex
5021 || i.tm.opcode_modifier.drexv
5022 || i.tm.opcode_modifier.drexc))
5023 i.rm.reg = i.tm.extension_opcode;
5029 output_branch (void)
5034 relax_substateT subtype;
5039 if (flag_code == CODE_16BIT)
5043 if (i.prefix[DATA_PREFIX] != 0)
5049 /* Pentium4 branch hints. */
5050 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5051 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5056 if (i.prefix[REX_PREFIX] != 0)
5062 if (i.prefixes != 0 && !intel_syntax)
5063 as_warn (_("skipping prefixes on this instruction"));
5065 /* It's always a symbol; End frag & setup for relax.
5066 Make sure there is enough room in this frag for the largest
5067 instruction we may generate in md_convert_frag. This is 2
5068 bytes for the opcode and room for the prefix and largest
5070 frag_grow (prefix + 2 + 4);
5071 /* Prefix and 1 opcode byte go in fr_fix. */
5072 p = frag_more (prefix + 1);
5073 if (i.prefix[DATA_PREFIX] != 0)
5074 *p++ = DATA_PREFIX_OPCODE;
5075 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5076 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5077 *p++ = i.prefix[SEG_PREFIX];
5078 if (i.prefix[REX_PREFIX] != 0)
5079 *p++ = i.prefix[REX_PREFIX];
5080 *p = i.tm.base_opcode;
5082 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5083 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5084 else if (cpu_arch_flags.bitfield.cpui386)
5085 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5087 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5090 sym = i.op[0].disps->X_add_symbol;
5091 off = i.op[0].disps->X_add_number;
5093 if (i.op[0].disps->X_op != O_constant
5094 && i.op[0].disps->X_op != O_symbol)
5096 /* Handle complex expressions. */
5097 sym = make_expr_symbol (i.op[0].disps);
5101 /* 1 possible extra opcode + 4 byte displacement go in var part.
5102 Pass reloc in fr_var. */
5103 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5113 if (i.tm.opcode_modifier.jumpbyte)
5115 /* This is a loop or jecxz type instruction. */
5117 if (i.prefix[ADDR_PREFIX] != 0)
5119 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5122 /* Pentium4 branch hints. */
5123 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5124 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5126 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5135 if (flag_code == CODE_16BIT)
5138 if (i.prefix[DATA_PREFIX] != 0)
5140 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5150 if (i.prefix[REX_PREFIX] != 0)
5152 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5156 if (i.prefixes != 0 && !intel_syntax)
5157 as_warn (_("skipping prefixes on this instruction"));
5159 p = frag_more (1 + size);
5160 *p++ = i.tm.base_opcode;
5162 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5163 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5165 /* All jumps handled here are signed, but don't use a signed limit
5166 check for 32 and 16 bit jumps as we want to allow wrap around at
5167 4G and 64k respectively. */
5169 fixP->fx_signed = 1;
5173 output_interseg_jump (void)
5181 if (flag_code == CODE_16BIT)
5185 if (i.prefix[DATA_PREFIX] != 0)
5191 if (i.prefix[REX_PREFIX] != 0)
5201 if (i.prefixes != 0 && !intel_syntax)
5202 as_warn (_("skipping prefixes on this instruction"));
5204 /* 1 opcode; 2 segment; offset */
5205 p = frag_more (prefix + 1 + 2 + size);
5207 if (i.prefix[DATA_PREFIX] != 0)
5208 *p++ = DATA_PREFIX_OPCODE;
5210 if (i.prefix[REX_PREFIX] != 0)
5211 *p++ = i.prefix[REX_PREFIX];
5213 *p++ = i.tm.base_opcode;
5214 if (i.op[1].imms->X_op == O_constant)
5216 offsetT n = i.op[1].imms->X_add_number;
5219 && !fits_in_unsigned_word (n)
5220 && !fits_in_signed_word (n))
5222 as_bad (_("16-bit jump out of range"));
5225 md_number_to_chars (p, n, size);
5228 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5229 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5230 if (i.op[0].imms->X_op != O_constant)
5231 as_bad (_("can't handle non absolute segment in `%s'"),
5233 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5239 fragS *insn_start_frag;
5240 offsetT insn_start_off;
5242 /* Tie dwarf2 debug info to the address at the start of the insn.
5243 We can't do this after the insn has been output as the current
5244 frag may have been closed off. eg. by frag_var. */
5245 dwarf2_emit_insn (0);
5247 insn_start_frag = frag_now;
5248 insn_start_off = frag_now_fix ();
5251 if (i.tm.opcode_modifier.jump)
5253 else if (i.tm.opcode_modifier.jumpbyte
5254 || i.tm.opcode_modifier.jumpdword)
5256 else if (i.tm.opcode_modifier.jumpintersegment)
5257 output_interseg_jump ();
5260 /* Output normal instructions here. */
5264 unsigned int prefix;
5266 switch (i.tm.opcode_length)
5269 if (i.tm.base_opcode & 0xff000000)
5271 prefix = (i.tm.base_opcode >> 24) & 0xff;
5276 if ((i.tm.base_opcode & 0xff0000) != 0)
5278 prefix = (i.tm.base_opcode >> 16) & 0xff;
5279 if (i.tm.cpu_flags.bitfield.cpupadlock)
5282 if (prefix != REPE_PREFIX_OPCODE
5283 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5284 add_prefix (prefix);
5287 add_prefix (prefix);
5296 /* The prefix bytes. */
5297 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5299 FRAG_APPEND_1_CHAR (*q);
5301 /* Now the opcode; be careful about word order here! */
5302 if (i.tm.opcode_length == 1)
5304 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5308 switch (i.tm.opcode_length)
5312 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5322 /* Put out high byte first: can't use md_number_to_chars! */
5323 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5324 *p = i.tm.base_opcode & 0xff;
5326 /* On SSE5, encode the OC1 bit in the DREX field if this
5327 encoding has multiple formats. */
5328 if (i.tm.opcode_modifier.drex
5329 && i.tm.opcode_modifier.drexv
5330 && DREX_OC1 (i.tm.extension_opcode))
5331 *p |= DREX_OC1_MASK;
5334 /* Now the modrm byte and sib byte (if present). */
5335 if (i.tm.opcode_modifier.modrm)
5337 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5340 /* If i.rm.regmem == ESP (4)
5341 && i.rm.mode != (Register mode)
5343 ==> need second modrm byte. */
5344 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5346 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5347 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5349 | i.sib.scale << 6));
5352 /* Write the DREX byte if needed. */
5353 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5356 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5358 /* Encode the OC0 bit if this encoding has multiple
5360 if ((i.tm.opcode_modifier.drex
5361 || i.tm.opcode_modifier.drexv)
5362 && DREX_OC0 (i.tm.extension_opcode))
5363 *p |= DREX_OC0_MASK;
5366 if (i.disp_operands)
5367 output_disp (insn_start_frag, insn_start_off);
5370 output_imm (insn_start_frag, insn_start_off);
5376 pi ("" /*line*/, &i);
5378 #endif /* DEBUG386 */
5381 /* Return the size of the displacement operand N. */
5384 disp_size (unsigned int n)
5387 if (i.types[n].bitfield.disp64)
5389 else if (i.types[n].bitfield.disp8)
5391 else if (i.types[n].bitfield.disp16)
5396 /* Return the size of the immediate operand N. */
5399 imm_size (unsigned int n)
5402 if (i.types[n].bitfield.imm64)
5404 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5406 else if (i.types[n].bitfield.imm16)
5412 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5417 for (n = 0; n < i.operands; n++)
5419 if (operand_type_check (i.types[n], disp))
5421 if (i.op[n].disps->X_op == O_constant)
5423 int size = disp_size (n);
5426 val = offset_in_range (i.op[n].disps->X_add_number,
5428 p = frag_more (size);
5429 md_number_to_chars (p, val, size);
5433 enum bfd_reloc_code_real reloc_type;
5434 int size = disp_size (n);
5435 int sign = i.types[n].bitfield.disp32s;
5436 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5438 /* We can't have 8 bit displacement here. */
5439 assert (!i.types[n].bitfield.disp8);
5441 /* The PC relative address is computed relative
5442 to the instruction boundary, so in case immediate
5443 fields follows, we need to adjust the value. */
5444 if (pcrel && i.imm_operands)
5449 for (n1 = 0; n1 < i.operands; n1++)
5450 if (operand_type_check (i.types[n1], imm))
5452 /* Only one immediate is allowed for PC
5453 relative address. */
5456 i.op[n].disps->X_add_number -= sz;
5458 /* We should find the immediate. */
5462 p = frag_more (size);
5463 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5465 && GOT_symbol == i.op[n].disps->X_add_symbol
5466 && (((reloc_type == BFD_RELOC_32
5467 || reloc_type == BFD_RELOC_X86_64_32S
5468 || (reloc_type == BFD_RELOC_64
5470 && (i.op[n].disps->X_op == O_symbol
5471 || (i.op[n].disps->X_op == O_add
5472 && ((symbol_get_value_expression
5473 (i.op[n].disps->X_op_symbol)->X_op)
5475 || reloc_type == BFD_RELOC_32_PCREL))
5479 if (insn_start_frag == frag_now)
5480 add = (p - frag_now->fr_literal) - insn_start_off;
5485 add = insn_start_frag->fr_fix - insn_start_off;
5486 for (fr = insn_start_frag->fr_next;
5487 fr && fr != frag_now; fr = fr->fr_next)
5489 add += p - frag_now->fr_literal;
5494 reloc_type = BFD_RELOC_386_GOTPC;
5495 i.op[n].imms->X_add_number += add;
5497 else if (reloc_type == BFD_RELOC_64)
5498 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5500 /* Don't do the adjustment for x86-64, as there
5501 the pcrel addressing is relative to the _next_
5502 insn, and that is taken care of in other code. */
5503 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5505 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5506 i.op[n].disps, pcrel, reloc_type);
5513 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5518 for (n = 0; n < i.operands; n++)
5520 if (operand_type_check (i.types[n], imm))
5522 if (i.op[n].imms->X_op == O_constant)
5524 int size = imm_size (n);
5527 val = offset_in_range (i.op[n].imms->X_add_number,
5529 p = frag_more (size);
5530 md_number_to_chars (p, val, size);
5534 /* Not absolute_section.
5535 Need a 32-bit fixup (don't support 8bit
5536 non-absolute imms). Try to support other
5538 enum bfd_reloc_code_real reloc_type;
5539 int size = imm_size (n);
5542 if (i.types[n].bitfield.imm32s
5543 && (i.suffix == QWORD_MNEM_SUFFIX
5544 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5549 p = frag_more (size);
5550 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5552 /* This is tough to explain. We end up with this one if we
5553 * have operands that look like
5554 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5555 * obtain the absolute address of the GOT, and it is strongly
5556 * preferable from a performance point of view to avoid using
5557 * a runtime relocation for this. The actual sequence of
5558 * instructions often look something like:
5563 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5565 * The call and pop essentially return the absolute address
5566 * of the label .L66 and store it in %ebx. The linker itself
5567 * will ultimately change the first operand of the addl so
5568 * that %ebx points to the GOT, but to keep things simple, the
5569 * .o file must have this operand set so that it generates not
5570 * the absolute address of .L66, but the absolute address of
5571 * itself. This allows the linker itself simply treat a GOTPC
5572 * relocation as asking for a pcrel offset to the GOT to be
5573 * added in, and the addend of the relocation is stored in the
5574 * operand field for the instruction itself.
5576 * Our job here is to fix the operand so that it would add
5577 * the correct offset so that %ebx would point to itself. The
5578 * thing that is tricky is that .-.L66 will point to the
5579 * beginning of the instruction, so we need to further modify
5580 * the operand so that it will point to itself. There are
5581 * other cases where you have something like:
5583 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5585 * and here no correction would be required. Internally in
5586 * the assembler we treat operands of this form as not being
5587 * pcrel since the '.' is explicitly mentioned, and I wonder
5588 * whether it would simplify matters to do it this way. Who
5589 * knows. In earlier versions of the PIC patches, the
5590 * pcrel_adjust field was used to store the correction, but
5591 * since the expression is not pcrel, I felt it would be
5592 * confusing to do it this way. */
5594 if ((reloc_type == BFD_RELOC_32
5595 || reloc_type == BFD_RELOC_X86_64_32S
5596 || reloc_type == BFD_RELOC_64)
5598 && GOT_symbol == i.op[n].imms->X_add_symbol
5599 && (i.op[n].imms->X_op == O_symbol
5600 || (i.op[n].imms->X_op == O_add
5601 && ((symbol_get_value_expression
5602 (i.op[n].imms->X_op_symbol)->X_op)
5607 if (insn_start_frag == frag_now)
5608 add = (p - frag_now->fr_literal) - insn_start_off;
5613 add = insn_start_frag->fr_fix - insn_start_off;
5614 for (fr = insn_start_frag->fr_next;
5615 fr && fr != frag_now; fr = fr->fr_next)
5617 add += p - frag_now->fr_literal;
5621 reloc_type = BFD_RELOC_386_GOTPC;
5623 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5625 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5626 i.op[n].imms->X_add_number += add;
5628 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5629 i.op[n].imms, 0, reloc_type);
5635 /* x86_cons_fix_new is called via the expression parsing code when a
5636 reloc is needed. We use this hook to get the correct .got reloc. */
5637 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5638 static int cons_sign = -1;
5641 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5644 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5646 got_reloc = NO_RELOC;
5649 if (exp->X_op == O_secrel)
5651 exp->X_op = O_symbol;
5652 r = BFD_RELOC_32_SECREL;
5656 fix_new_exp (frag, off, len, exp, 0, r);
5659 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5660 # define lex_got(reloc, adjust, types) NULL
5662 /* Parse operands of the form
5663 <symbol>@GOTOFF+<nnn>
5664 and similar .plt or .got references.
5666 If we find one, set up the correct relocation in RELOC and copy the
5667 input string, minus the `@GOTOFF' into a malloc'd buffer for
5668 parsing by the calling routine. Return this buffer, and if ADJUST
5669 is non-null set it to the length of the string we removed from the
5670 input line. Otherwise return NULL. */
5672 lex_got (enum bfd_reloc_code_real *reloc,
5674 i386_operand_type *types)
5676 /* Some of the relocations depend on the size of what field is to
5677 be relocated. But in our callers i386_immediate and i386_displacement
5678 we don't yet know the operand size (this will be set by insn
5679 matching). Hence we record the word32 relocation here,
5680 and adjust the reloc according to the real size in reloc(). */
5681 static const struct {
5683 const enum bfd_reloc_code_real rel[2];
5684 const i386_operand_type types64;
5687 BFD_RELOC_X86_64_PLTOFF64 },
5688 OPERAND_TYPE_IMM64 },
5689 { "PLT", { BFD_RELOC_386_PLT32,
5690 BFD_RELOC_X86_64_PLT32 },
5691 OPERAND_TYPE_IMM32_32S_DISP32 },
5693 BFD_RELOC_X86_64_GOTPLT64 },
5694 OPERAND_TYPE_IMM64_DISP64 },
5695 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5696 BFD_RELOC_X86_64_GOTOFF64 },
5697 OPERAND_TYPE_IMM64_DISP64 },
5699 BFD_RELOC_X86_64_GOTPCREL },
5700 OPERAND_TYPE_IMM32_32S_DISP32 },
5701 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5702 BFD_RELOC_X86_64_TLSGD },
5703 OPERAND_TYPE_IMM32_32S_DISP32 },
5704 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5706 OPERAND_TYPE_NONE },
5708 BFD_RELOC_X86_64_TLSLD },
5709 OPERAND_TYPE_IMM32_32S_DISP32 },
5710 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5711 BFD_RELOC_X86_64_GOTTPOFF },
5712 OPERAND_TYPE_IMM32_32S_DISP32 },
5713 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5714 BFD_RELOC_X86_64_TPOFF32 },
5715 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5716 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5718 OPERAND_TYPE_NONE },
5719 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5720 BFD_RELOC_X86_64_DTPOFF32 },
5722 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5723 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5725 OPERAND_TYPE_NONE },
5726 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5728 OPERAND_TYPE_NONE },
5729 { "GOT", { BFD_RELOC_386_GOT32,
5730 BFD_RELOC_X86_64_GOT32 },
5731 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5732 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5733 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5734 OPERAND_TYPE_IMM32_32S_DISP32 },
5735 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5736 BFD_RELOC_X86_64_TLSDESC_CALL },
5737 OPERAND_TYPE_IMM32_32S_DISP32 },
5745 for (cp = input_line_pointer; *cp != '@'; cp++)
5746 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5749 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5753 len = strlen (gotrel[j].str);
5754 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5756 if (gotrel[j].rel[object_64bit] != 0)
5759 char *tmpbuf, *past_reloc;
5761 *reloc = gotrel[j].rel[object_64bit];
5767 if (flag_code != CODE_64BIT)
5769 types->bitfield.imm32 = 1;
5770 types->bitfield.disp32 = 1;
5773 *types = gotrel[j].types64;
5776 if (GOT_symbol == NULL)
5777 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5779 /* The length of the first part of our input line. */
5780 first = cp - input_line_pointer;
5782 /* The second part goes from after the reloc token until
5783 (and including) an end_of_line char or comma. */
5784 past_reloc = cp + 1 + len;
5786 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5788 second = cp + 1 - past_reloc;
5790 /* Allocate and copy string. The trailing NUL shouldn't
5791 be necessary, but be safe. */
5792 tmpbuf = xmalloc (first + second + 2);
5793 memcpy (tmpbuf, input_line_pointer, first);
5794 if (second != 0 && *past_reloc != ' ')
5795 /* Replace the relocation token with ' ', so that
5796 errors like foo@GOTOFF1 will be detected. */
5797 tmpbuf[first++] = ' ';
5798 memcpy (tmpbuf + first, past_reloc, second);
5799 tmpbuf[first + second] = '\0';
5803 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5804 gotrel[j].str, 1 << (5 + object_64bit));
5809 /* Might be a symbol version string. Don't as_bad here. */
5814 x86_cons (expressionS *exp, int size)
5816 if (size == 4 || (object_64bit && size == 8))
5818 /* Handle @GOTOFF and the like in an expression. */
5820 char *gotfree_input_line;
5823 save = input_line_pointer;
5824 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5825 if (gotfree_input_line)
5826 input_line_pointer = gotfree_input_line;
5830 if (gotfree_input_line)
5832 /* expression () has merrily parsed up to the end of line,
5833 or a comma - in the wrong buffer. Transfer how far
5834 input_line_pointer has moved to the right buffer. */
5835 input_line_pointer = (save
5836 + (input_line_pointer - gotfree_input_line)
5838 free (gotfree_input_line);
5839 if (exp->X_op == O_constant
5840 || exp->X_op == O_absent
5841 || exp->X_op == O_illegal
5842 || exp->X_op == O_register
5843 || exp->X_op == O_big)
5845 char c = *input_line_pointer;
5846 *input_line_pointer = 0;
5847 as_bad (_("missing or invalid expression `%s'"), save);
5848 *input_line_pointer = c;
5857 static void signed_cons (int size)
5859 if (flag_code == CODE_64BIT)
5867 pe_directive_secrel (dummy)
5868 int dummy ATTRIBUTE_UNUSED;
5875 if (exp.X_op == O_symbol)
5876 exp.X_op = O_secrel;
5878 emit_expr (&exp, 4);
5880 while (*input_line_pointer++ == ',');
5882 input_line_pointer--;
5883 demand_empty_rest_of_line ();
5888 i386_immediate (char *imm_start)
5890 char *save_input_line_pointer;
5891 char *gotfree_input_line;
5894 i386_operand_type types;
5896 operand_type_set (&types, ~0);
5898 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5900 as_bad (_("at most %d immediate operands are allowed"),
5901 MAX_IMMEDIATE_OPERANDS);
5905 exp = &im_expressions[i.imm_operands++];
5906 i.op[this_operand].imms = exp;
5908 if (is_space_char (*imm_start))
5911 save_input_line_pointer = input_line_pointer;
5912 input_line_pointer = imm_start;
5914 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5915 if (gotfree_input_line)
5916 input_line_pointer = gotfree_input_line;
5918 exp_seg = expression (exp);
5921 if (*input_line_pointer)
5922 as_bad (_("junk `%s' after expression"), input_line_pointer);
5924 input_line_pointer = save_input_line_pointer;
5925 if (gotfree_input_line)
5926 free (gotfree_input_line);
5928 if (exp->X_op == O_absent
5929 || exp->X_op == O_illegal
5930 || exp->X_op == O_big
5931 || (gotfree_input_line
5932 && (exp->X_op == O_constant
5933 || exp->X_op == O_register)))
5935 as_bad (_("missing or invalid immediate expression `%s'"),
5939 else if (exp->X_op == O_constant)
5941 /* Size it properly later. */
5942 i.types[this_operand].bitfield.imm64 = 1;
5943 /* If BFD64, sign extend val. */
5944 if (!use_rela_relocations
5945 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5947 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5949 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5950 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5951 && exp_seg != absolute_section
5952 && exp_seg != text_section
5953 && exp_seg != data_section
5954 && exp_seg != bss_section
5955 && exp_seg != undefined_section
5956 && !bfd_is_com_section (exp_seg))
5958 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5962 else if (!intel_syntax && exp->X_op == O_register)
5964 as_bad (_("illegal immediate register operand %s"), imm_start);
5969 /* This is an address. The size of the address will be
5970 determined later, depending on destination register,
5971 suffix, or the default for the section. */
5972 i.types[this_operand].bitfield.imm8 = 1;
5973 i.types[this_operand].bitfield.imm16 = 1;
5974 i.types[this_operand].bitfield.imm32 = 1;
5975 i.types[this_operand].bitfield.imm32s = 1;
5976 i.types[this_operand].bitfield.imm64 = 1;
5977 i.types[this_operand] = operand_type_and (i.types[this_operand],
5985 i386_scale (char *scale)
5988 char *save = input_line_pointer;
5990 input_line_pointer = scale;
5991 val = get_absolute_expression ();
5996 i.log2_scale_factor = 0;
5999 i.log2_scale_factor = 1;
6002 i.log2_scale_factor = 2;
6005 i.log2_scale_factor = 3;
6009 char sep = *input_line_pointer;
6011 *input_line_pointer = '\0';
6012 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6014 *input_line_pointer = sep;
6015 input_line_pointer = save;
6019 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6021 as_warn (_("scale factor of %d without an index register"),
6022 1 << i.log2_scale_factor);
6023 i.log2_scale_factor = 0;
6025 scale = input_line_pointer;
6026 input_line_pointer = save;
6031 i386_displacement (char *disp_start, char *disp_end)
6035 char *save_input_line_pointer;
6036 char *gotfree_input_line;
6038 i386_operand_type bigdisp, types = anydisp;
6041 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6043 as_bad (_("at most %d displacement operands are allowed"),
6044 MAX_MEMORY_OPERANDS);
6048 operand_type_set (&bigdisp, 0);
6049 if ((i.types[this_operand].bitfield.jumpabsolute)
6050 || (!current_templates->start->opcode_modifier.jump
6051 && !current_templates->start->opcode_modifier.jumpdword))
6053 bigdisp.bitfield.disp32 = 1;
6054 override = (i.prefix[ADDR_PREFIX] != 0);
6055 if (flag_code == CODE_64BIT)
6059 bigdisp.bitfield.disp32s = 1;
6060 bigdisp.bitfield.disp64 = 1;
6063 else if ((flag_code == CODE_16BIT) ^ override)
6065 bigdisp.bitfield.disp32 = 0;
6066 bigdisp.bitfield.disp16 = 1;
6071 /* For PC-relative branches, the width of the displacement
6072 is dependent upon data size, not address size. */
6073 override = (i.prefix[DATA_PREFIX] != 0);
6074 if (flag_code == CODE_64BIT)
6076 if (override || i.suffix == WORD_MNEM_SUFFIX)
6077 bigdisp.bitfield.disp16 = 1;
6080 bigdisp.bitfield.disp32 = 1;
6081 bigdisp.bitfield.disp32s = 1;
6087 override = (i.suffix == (flag_code != CODE_16BIT
6089 : LONG_MNEM_SUFFIX));
6090 bigdisp.bitfield.disp32 = 1;
6091 if ((flag_code == CODE_16BIT) ^ override)
6093 bigdisp.bitfield.disp32 = 0;
6094 bigdisp.bitfield.disp16 = 1;
6098 i.types[this_operand] = operand_type_or (i.types[this_operand],
6101 exp = &disp_expressions[i.disp_operands];
6102 i.op[this_operand].disps = exp;
6104 save_input_line_pointer = input_line_pointer;
6105 input_line_pointer = disp_start;
6106 END_STRING_AND_SAVE (disp_end);
6108 #ifndef GCC_ASM_O_HACK
6109 #define GCC_ASM_O_HACK 0
6112 END_STRING_AND_SAVE (disp_end + 1);
6113 if (i.types[this_operand].bitfield.baseIndex
6114 && displacement_string_end[-1] == '+')
6116 /* This hack is to avoid a warning when using the "o"
6117 constraint within gcc asm statements.
6120 #define _set_tssldt_desc(n,addr,limit,type) \
6121 __asm__ __volatile__ ( \
6123 "movw %w1,2+%0\n\t" \
6125 "movb %b1,4+%0\n\t" \
6126 "movb %4,5+%0\n\t" \
6127 "movb $0,6+%0\n\t" \
6128 "movb %h1,7+%0\n\t" \
6130 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6132 This works great except that the output assembler ends
6133 up looking a bit weird if it turns out that there is
6134 no offset. You end up producing code that looks like:
6147 So here we provide the missing zero. */
6149 *displacement_string_end = '0';
6152 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6153 if (gotfree_input_line)
6154 input_line_pointer = gotfree_input_line;
6156 exp_seg = expression (exp);
6159 if (*input_line_pointer)
6160 as_bad (_("junk `%s' after expression"), input_line_pointer);
6162 RESTORE_END_STRING (disp_end + 1);
6164 input_line_pointer = save_input_line_pointer;
6165 if (gotfree_input_line)
6166 free (gotfree_input_line);
6169 /* We do this to make sure that the section symbol is in
6170 the symbol table. We will ultimately change the relocation
6171 to be relative to the beginning of the section. */
6172 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6173 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6174 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6176 if (exp->X_op != O_symbol)
6179 if (S_IS_LOCAL (exp->X_add_symbol)
6180 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6181 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6182 exp->X_op = O_subtract;
6183 exp->X_op_symbol = GOT_symbol;
6184 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6185 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6186 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6187 i.reloc[this_operand] = BFD_RELOC_64;
6189 i.reloc[this_operand] = BFD_RELOC_32;
6192 else if (exp->X_op == O_absent
6193 || exp->X_op == O_illegal
6194 || exp->X_op == O_big
6195 || (gotfree_input_line
6196 && (exp->X_op == O_constant
6197 || exp->X_op == O_register)))
6200 as_bad (_("missing or invalid displacement expression `%s'"),
6205 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6206 else if (exp->X_op != O_constant
6207 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6208 && exp_seg != absolute_section
6209 && exp_seg != text_section
6210 && exp_seg != data_section
6211 && exp_seg != bss_section
6212 && exp_seg != undefined_section
6213 && !bfd_is_com_section (exp_seg))
6215 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6220 RESTORE_END_STRING (disp_end);
6222 /* Check if this is a displacement only operand. */
6223 bigdisp = i.types[this_operand];
6224 bigdisp.bitfield.disp8 = 0;
6225 bigdisp.bitfield.disp16 = 0;
6226 bigdisp.bitfield.disp32 = 0;
6227 bigdisp.bitfield.disp32s = 0;
6228 bigdisp.bitfield.disp64 = 0;
6229 if (operand_type_all_zero (&bigdisp))
6230 i.types[this_operand] = operand_type_and (i.types[this_operand],
6236 /* Make sure the memory operand we've been dealt is valid.
6237 Return 1 on success, 0 on a failure. */
6240 i386_index_check (const char *operand_string)
6243 #if INFER_ADDR_PREFIX
6249 if (flag_code == CODE_64BIT)
6252 && ((i.prefix[ADDR_PREFIX] == 0
6253 && !i.base_reg->reg_type.bitfield.reg64)
6254 || (i.prefix[ADDR_PREFIX]
6255 && !i.base_reg->reg_type.bitfield.reg32))
6257 || i.base_reg->reg_num !=
6258 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6260 && (!i.index_reg->reg_type.bitfield.baseindex
6261 || (i.prefix[ADDR_PREFIX] == 0
6262 && i.index_reg->reg_num != RegRiz
6263 && !i.index_reg->reg_type.bitfield.reg64
6265 || (i.prefix[ADDR_PREFIX]
6266 && i.index_reg->reg_num != RegEiz
6267 && !i.index_reg->reg_type.bitfield.reg32))))
6272 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6276 && (!i.base_reg->reg_type.bitfield.reg16
6277 || !i.base_reg->reg_type.bitfield.baseindex))
6279 && (!i.index_reg->reg_type.bitfield.reg16
6280 || !i.index_reg->reg_type.bitfield.baseindex
6282 && i.base_reg->reg_num < 6
6283 && i.index_reg->reg_num >= 6
6284 && i.log2_scale_factor == 0))))
6291 && !i.base_reg->reg_type.bitfield.reg32)
6293 && ((!i.index_reg->reg_type.bitfield.reg32
6294 && i.index_reg->reg_num != RegEiz)
6295 || !i.index_reg->reg_type.bitfield.baseindex)))
6301 #if INFER_ADDR_PREFIX
6302 if (i.prefix[ADDR_PREFIX] == 0)
6304 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6306 /* Change the size of any displacement too. At most one of
6307 Disp16 or Disp32 is set.
6308 FIXME. There doesn't seem to be any real need for separate
6309 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6310 Removing them would probably clean up the code quite a lot. */
6311 if (flag_code != CODE_64BIT
6312 && (i.types[this_operand].bitfield.disp16
6313 || i.types[this_operand].bitfield.disp32))
6314 i.types[this_operand]
6315 = operand_type_xor (i.types[this_operand], disp16_32);
6320 as_bad (_("`%s' is not a valid base/index expression"),
6324 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6326 flag_code_names[flag_code]);
6331 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6335 i386_att_operand (char *operand_string)
6339 char *op_string = operand_string;
6341 if (is_space_char (*op_string))
6344 /* We check for an absolute prefix (differentiating,
6345 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6346 if (*op_string == ABSOLUTE_PREFIX)
6349 if (is_space_char (*op_string))
6351 i.types[this_operand].bitfield.jumpabsolute = 1;
6354 /* Check if operand is a register. */
6355 if ((r = parse_register (op_string, &end_op)) != NULL)
6357 i386_operand_type temp;
6359 /* Check for a segment override by searching for ':' after a
6360 segment register. */
6362 if (is_space_char (*op_string))
6364 if (*op_string == ':'
6365 && (r->reg_type.bitfield.sreg2
6366 || r->reg_type.bitfield.sreg3))
6371 i.seg[i.mem_operands] = &es;
6374 i.seg[i.mem_operands] = &cs;
6377 i.seg[i.mem_operands] = &ss;
6380 i.seg[i.mem_operands] = &ds;
6383 i.seg[i.mem_operands] = &fs;
6386 i.seg[i.mem_operands] = &gs;
6390 /* Skip the ':' and whitespace. */
6392 if (is_space_char (*op_string))
6395 if (!is_digit_char (*op_string)
6396 && !is_identifier_char (*op_string)
6397 && *op_string != '('
6398 && *op_string != ABSOLUTE_PREFIX)
6400 as_bad (_("bad memory operand `%s'"), op_string);
6403 /* Handle case of %es:*foo. */
6404 if (*op_string == ABSOLUTE_PREFIX)
6407 if (is_space_char (*op_string))
6409 i.types[this_operand].bitfield.jumpabsolute = 1;
6411 goto do_memory_reference;
6415 as_bad (_("junk `%s' after register"), op_string);
6419 temp.bitfield.baseindex = 0;
6420 i.types[this_operand] = operand_type_or (i.types[this_operand],
6422 i.types[this_operand].bitfield.unspecified = 0;
6423 i.op[this_operand].regs = r;
6426 else if (*op_string == REGISTER_PREFIX)
6428 as_bad (_("bad register name `%s'"), op_string);
6431 else if (*op_string == IMMEDIATE_PREFIX)
6434 if (i.types[this_operand].bitfield.jumpabsolute)
6436 as_bad (_("immediate operand illegal with absolute jump"));
6439 if (!i386_immediate (op_string))
6442 else if (is_digit_char (*op_string)
6443 || is_identifier_char (*op_string)
6444 || *op_string == '(')
6446 /* This is a memory reference of some sort. */
6449 /* Start and end of displacement string expression (if found). */
6450 char *displacement_string_start;
6451 char *displacement_string_end;
6453 do_memory_reference:
6454 if ((i.mem_operands == 1
6455 && !current_templates->start->opcode_modifier.isstring)
6456 || i.mem_operands == 2)
6458 as_bad (_("too many memory references for `%s'"),
6459 current_templates->start->name);
6463 /* Check for base index form. We detect the base index form by
6464 looking for an ')' at the end of the operand, searching
6465 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6467 base_string = op_string + strlen (op_string);
6470 if (is_space_char (*base_string))
6473 /* If we only have a displacement, set-up for it to be parsed later. */
6474 displacement_string_start = op_string;
6475 displacement_string_end = base_string + 1;
6477 if (*base_string == ')')
6480 unsigned int parens_balanced = 1;
6481 /* We've already checked that the number of left & right ()'s are
6482 equal, so this loop will not be infinite. */
6486 if (*base_string == ')')
6488 if (*base_string == '(')
6491 while (parens_balanced);
6493 temp_string = base_string;
6495 /* Skip past '(' and whitespace. */
6497 if (is_space_char (*base_string))
6500 if (*base_string == ','
6501 || ((i.base_reg = parse_register (base_string, &end_op))
6504 displacement_string_end = temp_string;
6506 i.types[this_operand].bitfield.baseindex = 1;
6510 base_string = end_op;
6511 if (is_space_char (*base_string))
6515 /* There may be an index reg or scale factor here. */
6516 if (*base_string == ',')
6519 if (is_space_char (*base_string))
6522 if ((i.index_reg = parse_register (base_string, &end_op))
6525 base_string = end_op;
6526 if (is_space_char (*base_string))
6528 if (*base_string == ',')
6531 if (is_space_char (*base_string))
6534 else if (*base_string != ')')
6536 as_bad (_("expecting `,' or `)' "
6537 "after index register in `%s'"),
6542 else if (*base_string == REGISTER_PREFIX)
6544 as_bad (_("bad register name `%s'"), base_string);
6548 /* Check for scale factor. */
6549 if (*base_string != ')')
6551 char *end_scale = i386_scale (base_string);
6556 base_string = end_scale;
6557 if (is_space_char (*base_string))
6559 if (*base_string != ')')
6561 as_bad (_("expecting `)' "
6562 "after scale factor in `%s'"),
6567 else if (!i.index_reg)
6569 as_bad (_("expecting index register or scale factor "
6570 "after `,'; got '%c'"),
6575 else if (*base_string != ')')
6577 as_bad (_("expecting `,' or `)' "
6578 "after base register in `%s'"),
6583 else if (*base_string == REGISTER_PREFIX)
6585 as_bad (_("bad register name `%s'"), base_string);
6590 /* If there's an expression beginning the operand, parse it,
6591 assuming displacement_string_start and
6592 displacement_string_end are meaningful. */
6593 if (displacement_string_start != displacement_string_end)
6595 if (!i386_displacement (displacement_string_start,
6596 displacement_string_end))
6600 /* Special case for (%dx) while doing input/output op. */
6602 && operand_type_equal (&i.base_reg->reg_type,
6603 ®16_inoutportreg)
6605 && i.log2_scale_factor == 0
6606 && i.seg[i.mem_operands] == 0
6607 && !operand_type_check (i.types[this_operand], disp))
6609 i.types[this_operand] = inoutportreg;
6613 if (i386_index_check (operand_string) == 0)
6615 i.types[this_operand].bitfield.mem = 1;
6620 /* It's not a memory operand; argh! */
6621 as_bad (_("invalid char %s beginning operand %d `%s'"),
6622 output_invalid (*op_string),
6627 return 1; /* Normal return. */
6630 /* md_estimate_size_before_relax()
6632 Called just before relax() for rs_machine_dependent frags. The x86
6633 assembler uses these frags to handle variable size jump
6636 Any symbol that is now undefined will not become defined.
6637 Return the correct fr_subtype in the frag.
6638 Return the initial "guess for variable size of frag" to caller.
6639 The guess is actually the growth beyond the fixed part. Whatever
6640 we do to grow the fixed or variable part contributes to our
6644 md_estimate_size_before_relax (fragP, segment)
6648 /* We've already got fragP->fr_subtype right; all we have to do is
6649 check for un-relaxable symbols. On an ELF system, we can't relax
6650 an externally visible symbol, because it may be overridden by a
6652 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6655 && (S_IS_EXTERNAL (fragP->fr_symbol)
6656 || S_IS_WEAK (fragP->fr_symbol)))
6660 /* Symbol is undefined in this segment, or we need to keep a
6661 reloc so that weak symbols can be overridden. */
6662 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6663 enum bfd_reloc_code_real reloc_type;
6664 unsigned char *opcode;
6667 if (fragP->fr_var != NO_RELOC)
6668 reloc_type = fragP->fr_var;
6670 reloc_type = BFD_RELOC_16_PCREL;
6672 reloc_type = BFD_RELOC_32_PCREL;
6674 old_fr_fix = fragP->fr_fix;
6675 opcode = (unsigned char *) fragP->fr_opcode;
6677 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6680 /* Make jmp (0xeb) a (d)word displacement jump. */
6682 fragP->fr_fix += size;
6683 fix_new (fragP, old_fr_fix, size,
6685 fragP->fr_offset, 1,
6691 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6693 /* Negate the condition, and branch past an
6694 unconditional jump. */
6697 /* Insert an unconditional jump. */
6699 /* We added two extra opcode bytes, and have a two byte
6701 fragP->fr_fix += 2 + 2;
6702 fix_new (fragP, old_fr_fix + 2, 2,
6704 fragP->fr_offset, 1,
6711 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6716 fixP = fix_new (fragP, old_fr_fix, 1,
6718 fragP->fr_offset, 1,
6720 fixP->fx_signed = 1;
6724 /* This changes the byte-displacement jump 0x7N
6725 to the (d)word-displacement jump 0x0f,0x8N. */
6726 opcode[1] = opcode[0] + 0x10;
6727 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6728 /* We've added an opcode byte. */
6729 fragP->fr_fix += 1 + size;
6730 fix_new (fragP, old_fr_fix + 1, size,
6732 fragP->fr_offset, 1,
6737 BAD_CASE (fragP->fr_subtype);
6741 return fragP->fr_fix - old_fr_fix;
6744 /* Guess size depending on current relax state. Initially the relax
6745 state will correspond to a short jump and we return 1, because
6746 the variable part of the frag (the branch offset) is one byte
6747 long. However, we can relax a section more than once and in that
6748 case we must either set fr_subtype back to the unrelaxed state,
6749 or return the value for the appropriate branch. */
6750 return md_relax_table[fragP->fr_subtype].rlx_length;
6753 /* Called after relax() is finished.
6755 In: Address of frag.
6756 fr_type == rs_machine_dependent.
6757 fr_subtype is what the address relaxed to.
6759 Out: Any fixSs and constants are set up.
6760 Caller will turn frag into a ".space 0". */
6763 md_convert_frag (abfd, sec, fragP)
6764 bfd *abfd ATTRIBUTE_UNUSED;
6765 segT sec ATTRIBUTE_UNUSED;
6768 unsigned char *opcode;
6769 unsigned char *where_to_put_displacement = NULL;
6770 offsetT target_address;
6771 offsetT opcode_address;
6772 unsigned int extension = 0;
6773 offsetT displacement_from_opcode_start;
6775 opcode = (unsigned char *) fragP->fr_opcode;
6777 /* Address we want to reach in file space. */
6778 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6780 /* Address opcode resides at in file space. */
6781 opcode_address = fragP->fr_address + fragP->fr_fix;
6783 /* Displacement from opcode start to fill into instruction. */
6784 displacement_from_opcode_start = target_address - opcode_address;
6786 if ((fragP->fr_subtype & BIG) == 0)
6788 /* Don't have to change opcode. */
6789 extension = 1; /* 1 opcode + 1 displacement */
6790 where_to_put_displacement = &opcode[1];
6794 if (no_cond_jump_promotion
6795 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6796 as_warn_where (fragP->fr_file, fragP->fr_line,
6797 _("long jump required"));
6799 switch (fragP->fr_subtype)
6801 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6802 extension = 4; /* 1 opcode + 4 displacement */
6804 where_to_put_displacement = &opcode[1];
6807 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6808 extension = 2; /* 1 opcode + 2 displacement */
6810 where_to_put_displacement = &opcode[1];
6813 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6814 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6815 extension = 5; /* 2 opcode + 4 displacement */
6816 opcode[1] = opcode[0] + 0x10;
6817 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6818 where_to_put_displacement = &opcode[2];
6821 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6822 extension = 3; /* 2 opcode + 2 displacement */
6823 opcode[1] = opcode[0] + 0x10;
6824 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6825 where_to_put_displacement = &opcode[2];
6828 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6833 where_to_put_displacement = &opcode[3];
6837 BAD_CASE (fragP->fr_subtype);
6842 /* If size if less then four we are sure that the operand fits,
6843 but if it's 4, then it could be that the displacement is larger
6845 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6847 && ((addressT) (displacement_from_opcode_start - extension
6848 + ((addressT) 1 << 31))
6849 > (((addressT) 2 << 31) - 1)))
6851 as_bad_where (fragP->fr_file, fragP->fr_line,
6852 _("jump target out of range"));
6853 /* Make us emit 0. */
6854 displacement_from_opcode_start = extension;
6856 /* Now put displacement after opcode. */
6857 md_number_to_chars ((char *) where_to_put_displacement,
6858 (valueT) (displacement_from_opcode_start - extension),
6859 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6860 fragP->fr_fix += extension;
6863 /* Apply a fixup (fixS) to segment data, once it has been determined
6864 by our caller that we have all the info we need to fix it up.
6866 On the 386, immediates, displacements, and data pointers are all in
6867 the same (little-endian) format, so we don't need to care about which
6871 md_apply_fix (fixP, valP, seg)
6872 /* The fix we're to put in. */
6874 /* Pointer to the value of the bits. */
6876 /* Segment fix is from. */
6877 segT seg ATTRIBUTE_UNUSED;
6879 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6880 valueT value = *valP;
6882 #if !defined (TE_Mach)
6885 switch (fixP->fx_r_type)
6891 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6894 case BFD_RELOC_X86_64_32S:
6895 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6898 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6901 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6906 if (fixP->fx_addsy != NULL
6907 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6908 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6909 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6910 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6911 && !use_rela_relocations)
6913 /* This is a hack. There should be a better way to handle this.
6914 This covers for the fact that bfd_install_relocation will
6915 subtract the current location (for partial_inplace, PC relative
6916 relocations); see more below. */
6920 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6923 value += fixP->fx_where + fixP->fx_frag->fr_address;
6925 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6928 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6931 || (symbol_section_p (fixP->fx_addsy)
6932 && sym_seg != absolute_section))
6933 && !generic_force_reloc (fixP))
6935 /* Yes, we add the values in twice. This is because
6936 bfd_install_relocation subtracts them out again. I think
6937 bfd_install_relocation is broken, but I don't dare change
6939 value += fixP->fx_where + fixP->fx_frag->fr_address;
6943 #if defined (OBJ_COFF) && defined (TE_PE)
6944 /* For some reason, the PE format does not store a
6945 section address offset for a PC relative symbol. */
6946 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6947 || S_IS_WEAK (fixP->fx_addsy))
6948 value += md_pcrel_from (fixP);
6952 /* Fix a few things - the dynamic linker expects certain values here,
6953 and we must not disappoint it. */
6954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6955 if (IS_ELF && fixP->fx_addsy)
6956 switch (fixP->fx_r_type)
6958 case BFD_RELOC_386_PLT32:
6959 case BFD_RELOC_X86_64_PLT32:
6960 /* Make the jump instruction point to the address of the operand. At
6961 runtime we merely add the offset to the actual PLT entry. */
6965 case BFD_RELOC_386_TLS_GD:
6966 case BFD_RELOC_386_TLS_LDM:
6967 case BFD_RELOC_386_TLS_IE_32:
6968 case BFD_RELOC_386_TLS_IE:
6969 case BFD_RELOC_386_TLS_GOTIE:
6970 case BFD_RELOC_386_TLS_GOTDESC:
6971 case BFD_RELOC_X86_64_TLSGD:
6972 case BFD_RELOC_X86_64_TLSLD:
6973 case BFD_RELOC_X86_64_GOTTPOFF:
6974 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6975 value = 0; /* Fully resolved at runtime. No addend. */
6977 case BFD_RELOC_386_TLS_LE:
6978 case BFD_RELOC_386_TLS_LDO_32:
6979 case BFD_RELOC_386_TLS_LE_32:
6980 case BFD_RELOC_X86_64_DTPOFF32:
6981 case BFD_RELOC_X86_64_DTPOFF64:
6982 case BFD_RELOC_X86_64_TPOFF32:
6983 case BFD_RELOC_X86_64_TPOFF64:
6984 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6987 case BFD_RELOC_386_TLS_DESC_CALL:
6988 case BFD_RELOC_X86_64_TLSDESC_CALL:
6989 value = 0; /* Fully resolved at runtime. No addend. */
6990 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6994 case BFD_RELOC_386_GOT32:
6995 case BFD_RELOC_X86_64_GOT32:
6996 value = 0; /* Fully resolved at runtime. No addend. */
6999 case BFD_RELOC_VTABLE_INHERIT:
7000 case BFD_RELOC_VTABLE_ENTRY:
7007 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7009 #endif /* !defined (TE_Mach) */
7011 /* Are we finished with this relocation now? */
7012 if (fixP->fx_addsy == NULL)
7014 else if (use_rela_relocations)
7016 fixP->fx_no_overflow = 1;
7017 /* Remember value for tc_gen_reloc. */
7018 fixP->fx_addnumber = value;
7022 md_number_to_chars (p, value, fixP->fx_size);
7026 md_atof (int type, char *litP, int *sizeP)
7028 /* This outputs the LITTLENUMs in REVERSE order;
7029 in accord with the bigendian 386. */
7030 return ieee_md_atof (type, litP, sizeP, FALSE);
7033 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7036 output_invalid (int c)
7039 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7042 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7043 "(0x%x)", (unsigned char) c);
7044 return output_invalid_buf;
7047 /* REG_STRING starts *before* REGISTER_PREFIX. */
7049 static const reg_entry *
7050 parse_real_register (char *reg_string, char **end_op)
7052 char *s = reg_string;
7054 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7057 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7058 if (*s == REGISTER_PREFIX)
7061 if (is_space_char (*s))
7065 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7067 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7068 return (const reg_entry *) NULL;
7072 /* For naked regs, make sure that we are not dealing with an identifier.
7073 This prevents confusing an identifier like `eax_var' with register
7075 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7076 return (const reg_entry *) NULL;
7080 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7082 /* Handle floating point regs, allowing spaces in the (i) part. */
7083 if (r == i386_regtab /* %st is first entry of table */)
7085 if (is_space_char (*s))
7090 if (is_space_char (*s))
7092 if (*s >= '0' && *s <= '7')
7096 if (is_space_char (*s))
7101 r = hash_find (reg_hash, "st(0)");
7106 /* We have "%st(" then garbage. */
7107 return (const reg_entry *) NULL;
7111 if (r == NULL || allow_pseudo_reg)
7114 if (operand_type_all_zero (&r->reg_type))
7115 return (const reg_entry *) NULL;
7117 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7118 if (!allow_index_reg
7119 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7120 return (const reg_entry *) NULL;
7122 if (((r->reg_flags & (RegRex64 | RegRex))
7123 || r->reg_type.bitfield.reg64)
7124 && (!cpu_arch_flags.bitfield.cpulm
7125 || !operand_type_equal (&r->reg_type, &control))
7126 && flag_code != CODE_64BIT)
7127 return (const reg_entry *) NULL;
7129 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7130 return (const reg_entry *) NULL;
7135 /* REG_STRING starts *before* REGISTER_PREFIX. */
7137 static const reg_entry *
7138 parse_register (char *reg_string, char **end_op)
7142 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7143 r = parse_real_register (reg_string, end_op);
7148 char *save = input_line_pointer;
7152 input_line_pointer = reg_string;
7153 c = get_symbol_end ();
7154 symbolP = symbol_find (reg_string);
7155 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7157 const expressionS *e = symbol_get_value_expression (symbolP);
7159 know (e->X_op == O_register);
7160 know (e->X_add_number >= 0
7161 && (valueT) e->X_add_number < i386_regtab_size);
7162 r = i386_regtab + e->X_add_number;
7163 *end_op = input_line_pointer;
7165 *input_line_pointer = c;
7166 input_line_pointer = save;
7172 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7175 char *end = input_line_pointer;
7178 r = parse_register (name, &input_line_pointer);
7179 if (r && end <= input_line_pointer)
7181 *nextcharP = *input_line_pointer;
7182 *input_line_pointer = 0;
7183 e->X_op = O_register;
7184 e->X_add_number = r - i386_regtab;
7187 input_line_pointer = end;
7193 md_operand (expressionS *e)
7195 if (*input_line_pointer == REGISTER_PREFIX)
7198 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7202 e->X_op = O_register;
7203 e->X_add_number = r - i386_regtab;
7204 input_line_pointer = end;
7210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7211 const char *md_shortopts = "kVQ:sqn";
7213 const char *md_shortopts = "qn";
7216 #define OPTION_32 (OPTION_MD_BASE + 0)
7217 #define OPTION_64 (OPTION_MD_BASE + 1)
7218 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7219 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7220 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7221 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7222 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7223 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7224 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7225 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7227 struct option md_longopts[] =
7229 {"32", no_argument, NULL, OPTION_32},
7230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7231 {"64", no_argument, NULL, OPTION_64},
7233 {"divide", no_argument, NULL, OPTION_DIVIDE},
7234 {"march", required_argument, NULL, OPTION_MARCH},
7235 {"mtune", required_argument, NULL, OPTION_MTUNE},
7236 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7237 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7238 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7239 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7240 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7241 {NULL, no_argument, NULL, 0}
7243 size_t md_longopts_size = sizeof (md_longopts);
7246 md_parse_option (int c, char *arg)
7254 optimize_align_code = 0;
7261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7262 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7263 should be emitted or not. FIXME: Not implemented. */
7267 /* -V: SVR4 argument to print version ID. */
7269 print_version_id ();
7272 /* -k: Ignore for FreeBSD compatibility. */
7277 /* -s: On i386 Solaris, this tells the native assembler to use
7278 .stab instead of .stab.excl. We always use .stab anyhow. */
7281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7284 const char **list, **l;
7286 list = bfd_target_list ();
7287 for (l = list; *l != NULL; l++)
7288 if (CONST_STRNEQ (*l, "elf64-x86-64")
7289 || strcmp (*l, "coff-x86-64") == 0
7290 || strcmp (*l, "pe-x86-64") == 0
7291 || strcmp (*l, "pei-x86-64") == 0)
7293 default_arch = "x86_64";
7297 as_fatal (_("No compiled in support for x86_64"));
7304 default_arch = "i386";
7308 #ifdef SVR4_COMMENT_CHARS
7313 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7315 for (s = i386_comment_chars; *s != '\0'; s++)
7319 i386_comment_chars = n;
7325 arch = xstrdup (arg);
7329 as_fatal (_("Invalid -march= option: `%s'"), arg);
7330 next = strchr (arch, '+');
7333 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7335 if (strcmp (arch, cpu_arch [i].name) == 0)
7338 cpu_arch_name = cpu_arch[i].name;
7339 cpu_sub_arch_name = NULL;
7340 cpu_arch_flags = cpu_arch[i].flags;
7341 cpu_arch_isa = cpu_arch[i].type;
7342 cpu_arch_isa_flags = cpu_arch[i].flags;
7343 if (!cpu_arch_tune_set)
7345 cpu_arch_tune = cpu_arch_isa;
7346 cpu_arch_tune_flags = cpu_arch_isa_flags;
7350 else if (*cpu_arch [i].name == '.'
7351 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7353 /* ISA entension. */
7354 i386_cpu_flags flags;
7355 flags = cpu_flags_or (cpu_arch_flags,
7357 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7359 if (cpu_sub_arch_name)
7361 char *name = cpu_sub_arch_name;
7362 cpu_sub_arch_name = concat (name,
7364 (const char *) NULL);
7368 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7369 cpu_arch_flags = flags;
7375 if (i >= ARRAY_SIZE (cpu_arch))
7376 as_fatal (_("Invalid -march= option: `%s'"), arg);
7380 while (next != NULL );
7385 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7386 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7388 if (strcmp (arg, cpu_arch [i].name) == 0)
7390 cpu_arch_tune_set = 1;
7391 cpu_arch_tune = cpu_arch [i].type;
7392 cpu_arch_tune_flags = cpu_arch[i].flags;
7396 if (i >= ARRAY_SIZE (cpu_arch))
7397 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7400 case OPTION_MMNEMONIC:
7401 if (strcasecmp (arg, "att") == 0)
7403 else if (strcasecmp (arg, "intel") == 0)
7406 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7409 case OPTION_MSYNTAX:
7410 if (strcasecmp (arg, "att") == 0)
7412 else if (strcasecmp (arg, "intel") == 0)
7415 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7418 case OPTION_MINDEX_REG:
7419 allow_index_reg = 1;
7422 case OPTION_MNAKED_REG:
7423 allow_naked_reg = 1;
7426 case OPTION_MOLD_GCC:
7437 md_show_usage (stream)
7440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7441 fprintf (stream, _("\
7443 -V print assembler version number\n\
7446 fprintf (stream, _("\
7447 -n Do not optimize code alignment\n\
7448 -q quieten some warnings\n"));
7449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7450 fprintf (stream, _("\
7453 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7454 fprintf (stream, _("\
7455 --32/--64 generate 32bit/64bit code\n"));
7457 #ifdef SVR4_COMMENT_CHARS
7458 fprintf (stream, _("\
7459 --divide do not treat `/' as a comment character\n"));
7461 fprintf (stream, _("\
7462 --divide ignored\n"));
7464 fprintf (stream, _("\
7465 -march=CPU[,+EXTENSION...]\n\
7466 generate code for CPU and EXTENSION, CPU is one of:\n\
7467 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7468 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7469 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7470 generic32, generic64\n\
7471 EXTENSION is combination of:\n\
7472 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7473 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7475 fprintf (stream, _("\
7476 -mtune=CPU optimize for CPU, CPU is one of:\n\
7477 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7478 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7479 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7480 generic32, generic64\n"));
7481 fprintf (stream, _("\
7482 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7483 fprintf (stream, _("\
7484 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7485 fprintf (stream, _("\
7486 -mindex-reg support pseudo index registers\n"));
7487 fprintf (stream, _("\
7488 -mnaked-reg don't require `%%' prefix for registers\n"));
7489 fprintf (stream, _("\
7490 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7493 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7494 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7496 /* Pick the target format to use. */
7499 i386_target_format (void)
7501 if (!strcmp (default_arch, "x86_64"))
7503 set_code_flag (CODE_64BIT);
7504 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7506 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7507 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7508 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7509 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7510 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7511 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7512 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7513 cpu_arch_isa_flags.bitfield.cpummx= 1;
7514 cpu_arch_isa_flags.bitfield.cpusse = 1;
7515 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7517 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7519 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7520 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7521 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7522 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7523 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7524 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7525 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7526 cpu_arch_tune_flags.bitfield.cpummx= 1;
7527 cpu_arch_tune_flags.bitfield.cpusse = 1;
7528 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7531 else if (!strcmp (default_arch, "i386"))
7533 set_code_flag (CODE_32BIT);
7534 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7536 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7537 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7538 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7540 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7542 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7543 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7544 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7548 as_fatal (_("Unknown architecture"));
7549 switch (OUTPUT_FLAVOR)
7552 case bfd_target_coff_flavour:
7553 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7556 #ifdef OBJ_MAYBE_AOUT
7557 case bfd_target_aout_flavour:
7558 return AOUT_TARGET_FORMAT;
7560 #ifdef OBJ_MAYBE_COFF
7561 case bfd_target_coff_flavour:
7564 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7565 case bfd_target_elf_flavour:
7567 if (flag_code == CODE_64BIT)
7570 use_rela_relocations = 1;
7572 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7581 #endif /* OBJ_MAYBE_ more than one */
7583 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7585 i386_elf_emit_arch_note (void)
7587 if (IS_ELF && cpu_arch_name != NULL)
7590 asection *seg = now_seg;
7591 subsegT subseg = now_subseg;
7592 Elf_Internal_Note i_note;
7593 Elf_External_Note e_note;
7594 asection *note_secp;
7597 /* Create the .note section. */
7598 note_secp = subseg_new (".note", 0);
7599 bfd_set_section_flags (stdoutput,
7601 SEC_HAS_CONTENTS | SEC_READONLY);
7603 /* Process the arch string. */
7604 len = strlen (cpu_arch_name);
7606 i_note.namesz = len + 1;
7608 i_note.type = NT_ARCH;
7609 p = frag_more (sizeof (e_note.namesz));
7610 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7611 p = frag_more (sizeof (e_note.descsz));
7612 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7613 p = frag_more (sizeof (e_note.type));
7614 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7615 p = frag_more (len + 1);
7616 strcpy (p, cpu_arch_name);
7618 frag_align (2, 0, 0);
7620 subseg_set (seg, subseg);
7626 md_undefined_symbol (name)
7629 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7630 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7631 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7632 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7636 if (symbol_find (name))
7637 as_bad (_("GOT already in symbol table"));
7638 GOT_symbol = symbol_new (name, undefined_section,
7639 (valueT) 0, &zero_address_frag);
7646 /* Round up a section size to the appropriate boundary. */
7649 md_section_align (segment, size)
7650 segT segment ATTRIBUTE_UNUSED;
7653 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7654 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7656 /* For a.out, force the section size to be aligned. If we don't do
7657 this, BFD will align it for us, but it will not write out the
7658 final bytes of the section. This may be a bug in BFD, but it is
7659 easier to fix it here since that is how the other a.out targets
7663 align = bfd_get_section_alignment (stdoutput, segment);
7664 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7671 /* On the i386, PC-relative offsets are relative to the start of the
7672 next instruction. That is, the address of the offset, plus its
7673 size, since the offset is always the last part of the insn. */
7676 md_pcrel_from (fixS *fixP)
7678 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7684 s_bss (int ignore ATTRIBUTE_UNUSED)
7688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7690 obj_elf_section_change_hook ();
7692 temp = get_absolute_expression ();
7693 subseg_set (bss_section, (subsegT) temp);
7694 demand_empty_rest_of_line ();
7700 i386_validate_fix (fixS *fixp)
7702 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7704 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7708 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7713 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7715 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7722 tc_gen_reloc (section, fixp)
7723 asection *section ATTRIBUTE_UNUSED;
7727 bfd_reloc_code_real_type code;
7729 switch (fixp->fx_r_type)
7731 case BFD_RELOC_X86_64_PLT32:
7732 case BFD_RELOC_X86_64_GOT32:
7733 case BFD_RELOC_X86_64_GOTPCREL:
7734 case BFD_RELOC_386_PLT32:
7735 case BFD_RELOC_386_GOT32:
7736 case BFD_RELOC_386_GOTOFF:
7737 case BFD_RELOC_386_GOTPC:
7738 case BFD_RELOC_386_TLS_GD:
7739 case BFD_RELOC_386_TLS_LDM:
7740 case BFD_RELOC_386_TLS_LDO_32:
7741 case BFD_RELOC_386_TLS_IE_32:
7742 case BFD_RELOC_386_TLS_IE:
7743 case BFD_RELOC_386_TLS_GOTIE:
7744 case BFD_RELOC_386_TLS_LE_32:
7745 case BFD_RELOC_386_TLS_LE:
7746 case BFD_RELOC_386_TLS_GOTDESC:
7747 case BFD_RELOC_386_TLS_DESC_CALL:
7748 case BFD_RELOC_X86_64_TLSGD:
7749 case BFD_RELOC_X86_64_TLSLD:
7750 case BFD_RELOC_X86_64_DTPOFF32:
7751 case BFD_RELOC_X86_64_DTPOFF64:
7752 case BFD_RELOC_X86_64_GOTTPOFF:
7753 case BFD_RELOC_X86_64_TPOFF32:
7754 case BFD_RELOC_X86_64_TPOFF64:
7755 case BFD_RELOC_X86_64_GOTOFF64:
7756 case BFD_RELOC_X86_64_GOTPC32:
7757 case BFD_RELOC_X86_64_GOT64:
7758 case BFD_RELOC_X86_64_GOTPCREL64:
7759 case BFD_RELOC_X86_64_GOTPC64:
7760 case BFD_RELOC_X86_64_GOTPLT64:
7761 case BFD_RELOC_X86_64_PLTOFF64:
7762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7763 case BFD_RELOC_X86_64_TLSDESC_CALL:
7765 case BFD_RELOC_VTABLE_ENTRY:
7766 case BFD_RELOC_VTABLE_INHERIT:
7768 case BFD_RELOC_32_SECREL:
7770 code = fixp->fx_r_type;
7772 case BFD_RELOC_X86_64_32S:
7773 if (!fixp->fx_pcrel)
7775 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7776 code = fixp->fx_r_type;
7782 switch (fixp->fx_size)
7785 as_bad_where (fixp->fx_file, fixp->fx_line,
7786 _("can not do %d byte pc-relative relocation"),
7788 code = BFD_RELOC_32_PCREL;
7790 case 1: code = BFD_RELOC_8_PCREL; break;
7791 case 2: code = BFD_RELOC_16_PCREL; break;
7792 case 4: code = BFD_RELOC_32_PCREL; break;
7794 case 8: code = BFD_RELOC_64_PCREL; break;
7800 switch (fixp->fx_size)
7803 as_bad_where (fixp->fx_file, fixp->fx_line,
7804 _("can not do %d byte relocation"),
7806 code = BFD_RELOC_32;
7808 case 1: code = BFD_RELOC_8; break;
7809 case 2: code = BFD_RELOC_16; break;
7810 case 4: code = BFD_RELOC_32; break;
7812 case 8: code = BFD_RELOC_64; break;
7819 if ((code == BFD_RELOC_32
7820 || code == BFD_RELOC_32_PCREL
7821 || code == BFD_RELOC_X86_64_32S)
7823 && fixp->fx_addsy == GOT_symbol)
7826 code = BFD_RELOC_386_GOTPC;
7828 code = BFD_RELOC_X86_64_GOTPC32;
7830 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7832 && fixp->fx_addsy == GOT_symbol)
7834 code = BFD_RELOC_X86_64_GOTPC64;
7837 rel = (arelent *) xmalloc (sizeof (arelent));
7838 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7839 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7841 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7843 if (!use_rela_relocations)
7845 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7846 vtable entry to be used in the relocation's section offset. */
7847 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7848 rel->address = fixp->fx_offset;
7852 /* Use the rela in 64bit mode. */
7855 if (!fixp->fx_pcrel)
7856 rel->addend = fixp->fx_offset;
7860 case BFD_RELOC_X86_64_PLT32:
7861 case BFD_RELOC_X86_64_GOT32:
7862 case BFD_RELOC_X86_64_GOTPCREL:
7863 case BFD_RELOC_X86_64_TLSGD:
7864 case BFD_RELOC_X86_64_TLSLD:
7865 case BFD_RELOC_X86_64_GOTTPOFF:
7866 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7867 case BFD_RELOC_X86_64_TLSDESC_CALL:
7868 rel->addend = fixp->fx_offset - fixp->fx_size;
7871 rel->addend = (section->vma
7873 + fixp->fx_addnumber
7874 + md_pcrel_from (fixp));
7879 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7880 if (rel->howto == NULL)
7882 as_bad_where (fixp->fx_file, fixp->fx_line,
7883 _("cannot represent relocation type %s"),
7884 bfd_get_reloc_code_name (code));
7885 /* Set howto to a garbage value so that we can keep going. */
7886 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7887 assert (rel->howto != NULL);
7894 /* Parse operands using Intel syntax. This implements a recursive descent
7895 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7898 FIXME: We do not recognize the full operand grammar defined in the MASM
7899 documentation. In particular, all the structure/union and
7900 high-level macro operands are missing.
7902 Uppercase words are terminals, lower case words are non-terminals.
7903 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7904 bars '|' denote choices. Most grammar productions are implemented in
7905 functions called 'intel_<production>'.
7907 Initial production is 'expr'.
7913 binOp & | AND | \| | OR | ^ | XOR
7915 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7917 constant digits [[ radixOverride ]]
7919 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7957 => expr expr cmpOp e04
7960 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7961 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7963 hexdigit a | b | c | d | e | f
7964 | A | B | C | D | E | F
7970 mulOp * | / | % | MOD | << | SHL | >> | SHR
7974 register specialRegister
7978 segmentRegister CS | DS | ES | FS | GS | SS
7980 specialRegister CR0 | CR2 | CR3 | CR4
7981 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7982 | TR3 | TR4 | TR5 | TR6 | TR7
7984 We simplify the grammar in obvious places (e.g., register parsing is
7985 done by calling parse_register) and eliminate immediate left recursion
7986 to implement a recursive-descent parser.
7990 expr' cmpOp e04 expr'
8041 /* Parsing structure for the intel syntax parser. Used to implement the
8042 semantic actions for the operand grammar. */
8043 struct intel_parser_s
8045 char *op_string; /* The string being parsed. */
8046 int got_a_float; /* Whether the operand is a float. */
8047 int op_modifier; /* Operand modifier. */
8048 int is_mem; /* 1 if operand is memory reference. */
8049 int in_offset; /* >=1 if parsing operand of offset. */
8050 int in_bracket; /* >=1 if parsing operand in brackets. */
8051 const reg_entry *reg; /* Last register reference found. */
8052 char *disp; /* Displacement string being built. */
8053 char *next_operand; /* Resume point when splitting operands. */
8056 static struct intel_parser_s intel_parser;
8058 /* Token structure for parsing intel syntax. */
8061 int code; /* Token code. */
8062 const reg_entry *reg; /* Register entry for register tokens. */
8063 char *str; /* String representation. */
8066 static struct intel_token cur_token, prev_token;
8068 /* Token codes for the intel parser. Since T_SHORT is already used
8069 by COFF, undefine it first to prevent a warning. */
8088 /* Prototypes for intel parser functions. */
8089 static int intel_match_token (int);
8090 static void intel_putback_token (void);
8091 static void intel_get_token (void);
8092 static int intel_expr (void);
8093 static int intel_e04 (void);
8094 static int intel_e05 (void);
8095 static int intel_e06 (void);
8096 static int intel_e09 (void);
8097 static int intel_e10 (void);
8098 static int intel_e11 (void);
8101 i386_intel_operand (char *operand_string, int got_a_float)
8106 p = intel_parser.op_string = xstrdup (operand_string);
8107 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8111 /* Initialize token holders. */
8112 cur_token.code = prev_token.code = T_NIL;
8113 cur_token.reg = prev_token.reg = NULL;
8114 cur_token.str = prev_token.str = NULL;
8116 /* Initialize parser structure. */
8117 intel_parser.got_a_float = got_a_float;
8118 intel_parser.op_modifier = 0;
8119 intel_parser.is_mem = 0;
8120 intel_parser.in_offset = 0;
8121 intel_parser.in_bracket = 0;
8122 intel_parser.reg = NULL;
8123 intel_parser.disp[0] = '\0';
8124 intel_parser.next_operand = NULL;
8126 /* Read the first token and start the parser. */
8128 ret = intel_expr ();
8133 if (cur_token.code != T_NIL)
8135 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8136 current_templates->start->name, cur_token.str);
8139 /* If we found a memory reference, hand it over to i386_displacement
8140 to fill in the rest of the operand fields. */
8141 else if (intel_parser.is_mem)
8143 if ((i.mem_operands == 1
8144 && !current_templates->start->opcode_modifier.isstring)
8145 || i.mem_operands == 2)
8147 as_bad (_("too many memory references for '%s'"),
8148 current_templates->start->name);
8153 char *s = intel_parser.disp;
8154 i.types[this_operand].bitfield.mem = 1;
8157 if (!quiet_warnings && intel_parser.is_mem < 0)
8158 /* See the comments in intel_bracket_expr. */
8159 as_warn (_("Treating `%s' as memory reference"), operand_string);
8161 /* Add the displacement expression. */
8163 ret = i386_displacement (s, s + strlen (s));
8166 /* Swap base and index in 16-bit memory operands like
8167 [si+bx]. Since i386_index_check is also used in AT&T
8168 mode we have to do that here. */
8171 && i.base_reg->reg_type.bitfield.reg16
8172 && i.index_reg->reg_type.bitfield.reg16
8173 && i.base_reg->reg_num >= 6
8174 && i.index_reg->reg_num < 6)
8176 const reg_entry *base = i.index_reg;
8178 i.index_reg = i.base_reg;
8181 ret = i386_index_check (operand_string);
8186 /* Constant and OFFSET expressions are handled by i386_immediate. */
8187 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8188 || intel_parser.reg == NULL)
8190 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8192 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8193 as_warn (_("Segment override ignored"));
8194 i.seg[i.mem_operands] = NULL;
8196 ret = i386_immediate (intel_parser.disp);
8199 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8201 if (!ret || !intel_parser.next_operand)
8203 intel_parser.op_string = intel_parser.next_operand;
8204 this_operand = i.operands++;
8205 i.types[this_operand].bitfield.unspecified = 1;
8209 free (intel_parser.disp);
8214 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8218 expr' cmpOp e04 expr'
8223 /* XXX Implement the comparison operators. */
8224 return intel_e04 ();
8241 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8242 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8244 if (cur_token.code == '+')
8246 else if (cur_token.code == '-')
8247 nregs = NUM_ADDRESS_REGS;
8251 strcat (intel_parser.disp, cur_token.str);
8252 intel_match_token (cur_token.code);
8263 int nregs = ~NUM_ADDRESS_REGS;
8270 if (cur_token.code == '&'
8271 || cur_token.code == '|'
8272 || cur_token.code == '^')
8276 str[0] = cur_token.code;
8278 strcat (intel_parser.disp, str);
8283 intel_match_token (cur_token.code);
8288 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8289 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8300 int nregs = ~NUM_ADDRESS_REGS;
8307 if (cur_token.code == '*'
8308 || cur_token.code == '/'
8309 || cur_token.code == '%')
8313 str[0] = cur_token.code;
8315 strcat (intel_parser.disp, str);
8317 else if (cur_token.code == T_SHL)
8318 strcat (intel_parser.disp, "<<");
8319 else if (cur_token.code == T_SHR)
8320 strcat (intel_parser.disp, ">>");
8324 intel_match_token (cur_token.code);
8329 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8330 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8348 int nregs = ~NUM_ADDRESS_REGS;
8353 /* Don't consume constants here. */
8354 if (cur_token.code == '+' || cur_token.code == '-')
8356 /* Need to look one token ahead - if the next token
8357 is a constant, the current token is its sign. */
8360 intel_match_token (cur_token.code);
8361 next_code = cur_token.code;
8362 intel_putback_token ();
8363 if (next_code == T_CONST)
8367 /* e09 OFFSET e09 */
8368 if (cur_token.code == T_OFFSET)
8371 ++intel_parser.in_offset;
8375 else if (cur_token.code == T_SHORT)
8376 intel_parser.op_modifier |= 1 << T_SHORT;
8379 else if (cur_token.code == '+')
8380 strcat (intel_parser.disp, "+");
8385 else if (cur_token.code == '-' || cur_token.code == '~')
8391 str[0] = cur_token.code;
8393 strcat (intel_parser.disp, str);
8400 intel_match_token (cur_token.code);
8408 /* e09' PTR e10 e09' */
8409 if (cur_token.code == T_PTR)
8413 if (prev_token.code == T_BYTE)
8415 suffix = BYTE_MNEM_SUFFIX;
8416 i.types[this_operand].bitfield.byte = 1;
8419 else if (prev_token.code == T_WORD)
8421 if ((current_templates->start->name[0] == 'l'
8422 && current_templates->start->name[2] == 's'
8423 && current_templates->start->name[3] == 0)
8424 || current_templates->start->base_opcode == 0x62 /* bound */)
8425 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8426 else if (intel_parser.got_a_float == 2) /* "fi..." */
8427 suffix = SHORT_MNEM_SUFFIX;
8429 suffix = WORD_MNEM_SUFFIX;
8430 i.types[this_operand].bitfield.word = 1;
8433 else if (prev_token.code == T_DWORD)
8435 if ((current_templates->start->name[0] == 'l'
8436 && current_templates->start->name[2] == 's'
8437 && current_templates->start->name[3] == 0)
8438 || current_templates->start->base_opcode == 0x62 /* bound */)
8439 suffix = WORD_MNEM_SUFFIX;
8440 else if (flag_code == CODE_16BIT
8441 && (current_templates->start->opcode_modifier.jump
8442 || current_templates->start->opcode_modifier.jumpdword))
8443 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8444 else if (intel_parser.got_a_float == 1) /* "f..." */
8445 suffix = SHORT_MNEM_SUFFIX;
8447 suffix = LONG_MNEM_SUFFIX;
8448 i.types[this_operand].bitfield.dword = 1;
8451 else if (prev_token.code == T_FWORD)
8453 if (current_templates->start->name[0] == 'l'
8454 && current_templates->start->name[2] == 's'
8455 && current_templates->start->name[3] == 0)
8456 suffix = LONG_MNEM_SUFFIX;
8457 else if (!intel_parser.got_a_float)
8459 if (flag_code == CODE_16BIT)
8460 add_prefix (DATA_PREFIX_OPCODE);
8461 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8464 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8465 i.types[this_operand].bitfield.fword = 1;
8468 else if (prev_token.code == T_QWORD)
8470 if (current_templates->start->base_opcode == 0x62 /* bound */
8471 || intel_parser.got_a_float == 1) /* "f..." */
8472 suffix = LONG_MNEM_SUFFIX;
8474 suffix = QWORD_MNEM_SUFFIX;
8475 i.types[this_operand].bitfield.qword = 1;
8478 else if (prev_token.code == T_TBYTE)
8480 if (intel_parser.got_a_float == 1)
8481 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8483 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8486 else if (prev_token.code == T_XMMWORD)
8488 suffix = XMMWORD_MNEM_SUFFIX;
8489 i.types[this_operand].bitfield.xmmword = 1;
8494 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8498 i.types[this_operand].bitfield.unspecified = 0;
8500 /* Operands for jump/call using 'ptr' notation denote absolute
8502 if (current_templates->start->opcode_modifier.jump
8503 || current_templates->start->opcode_modifier.jumpdword)
8504 i.types[this_operand].bitfield.jumpabsolute = 1;
8506 if (current_templates->start->base_opcode == 0x8d /* lea */)
8510 else if (i.suffix != suffix)
8512 as_bad (_("Conflicting operand modifiers"));
8518 /* e09' : e10 e09' */
8519 else if (cur_token.code == ':')
8521 if (prev_token.code != T_REG)
8523 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8524 segment/group identifier (which we don't have), using comma
8525 as the operand separator there is even less consistent, since
8526 there all branches only have a single operand. */
8527 if (this_operand != 0
8528 || intel_parser.in_offset
8529 || intel_parser.in_bracket
8530 || (!current_templates->start->opcode_modifier.jump
8531 && !current_templates->start->opcode_modifier.jumpdword
8532 && !current_templates->start->opcode_modifier.jumpintersegment
8533 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8534 return intel_match_token (T_NIL);
8535 /* Remember the start of the 2nd operand and terminate 1st
8537 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8538 another expression), but it gets at least the simplest case
8539 (a plain number or symbol on the left side) right. */
8540 intel_parser.next_operand = intel_parser.op_string;
8541 *--intel_parser.op_string = '\0';
8542 return intel_match_token (':');
8550 intel_match_token (cur_token.code);
8556 --intel_parser.in_offset;
8559 if (NUM_ADDRESS_REGS > nregs)
8561 as_bad (_("Invalid operand to `OFFSET'"));
8564 intel_parser.op_modifier |= 1 << T_OFFSET;
8567 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8568 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8573 intel_bracket_expr (void)
8575 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8576 const char *start = intel_parser.op_string;
8579 if (i.op[this_operand].regs)
8580 return intel_match_token (T_NIL);
8582 intel_match_token ('[');
8584 /* Mark as a memory operand only if it's not already known to be an
8585 offset expression. If it's an offset expression, we need to keep
8587 if (!intel_parser.in_offset)
8589 ++intel_parser.in_bracket;
8591 /* Operands for jump/call inside brackets denote absolute addresses. */
8592 if (current_templates->start->opcode_modifier.jump
8593 || current_templates->start->opcode_modifier.jumpdword)
8594 i.types[this_operand].bitfield.jumpabsolute = 1;
8596 /* Unfortunately gas always diverged from MASM in a respect that can't
8597 be easily fixed without risking to break code sequences likely to be
8598 encountered (the testsuite even check for this): MASM doesn't consider
8599 an expression inside brackets unconditionally as a memory reference.
8600 When that is e.g. a constant, an offset expression, or the sum of the
8601 two, this is still taken as a constant load. gas, however, always
8602 treated these as memory references. As a compromise, we'll try to make
8603 offset expressions inside brackets work the MASM way (since that's
8604 less likely to be found in real world code), but make constants alone
8605 continue to work the traditional gas way. In either case, issue a
8607 intel_parser.op_modifier &= ~was_offset;
8610 strcat (intel_parser.disp, "[");
8612 /* Add a '+' to the displacement string if necessary. */
8613 if (*intel_parser.disp != '\0'
8614 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8615 strcat (intel_parser.disp, "+");
8618 && (len = intel_parser.op_string - start - 1,
8619 intel_match_token (']')))
8621 /* Preserve brackets when the operand is an offset expression. */
8622 if (intel_parser.in_offset)
8623 strcat (intel_parser.disp, "]");
8626 --intel_parser.in_bracket;
8627 if (i.base_reg || i.index_reg)
8628 intel_parser.is_mem = 1;
8629 if (!intel_parser.is_mem)
8631 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8632 /* Defer the warning until all of the operand was parsed. */
8633 intel_parser.is_mem = -1;
8634 else if (!quiet_warnings)
8635 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8636 len, start, len, start);
8639 intel_parser.op_modifier |= was_offset;
8656 while (cur_token.code == '[')
8658 if (!intel_bracket_expr ())
8683 switch (cur_token.code)
8687 intel_match_token ('(');
8688 strcat (intel_parser.disp, "(");
8690 if (intel_expr () && intel_match_token (')'))
8692 strcat (intel_parser.disp, ")");
8699 return intel_bracket_expr ();
8704 strcat (intel_parser.disp, cur_token.str);
8705 intel_match_token (cur_token.code);
8707 /* Mark as a memory operand only if it's not already known to be an
8708 offset expression. */
8709 if (!intel_parser.in_offset)
8710 intel_parser.is_mem = 1;
8717 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8719 intel_match_token (T_REG);
8721 /* Check for segment change. */
8722 if (cur_token.code == ':')
8724 if (!reg->reg_type.bitfield.sreg2
8725 && !reg->reg_type.bitfield.sreg3)
8727 as_bad (_("`%s' is not a valid segment register"),
8731 else if (i.mem_operands >= 2)
8732 as_warn (_("Segment override ignored"));
8733 else if (i.seg[i.mem_operands])
8734 as_warn (_("Extra segment override ignored"));
8737 if (!intel_parser.in_offset)
8738 intel_parser.is_mem = 1;
8739 switch (reg->reg_num)
8742 i.seg[i.mem_operands] = &es;
8745 i.seg[i.mem_operands] = &cs;
8748 i.seg[i.mem_operands] = &ss;
8751 i.seg[i.mem_operands] = &ds;
8754 i.seg[i.mem_operands] = &fs;
8757 i.seg[i.mem_operands] = &gs;
8763 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8765 as_bad (_("cannot use `FLAT' here"));
8769 /* Not a segment register. Check for register scaling. */
8770 else if (cur_token.code == '*')
8772 if (!intel_parser.in_bracket)
8774 as_bad (_("Register scaling only allowed in memory operands"));
8778 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8779 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8780 else if (i.index_reg)
8781 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8783 /* What follows must be a valid scale. */
8784 intel_match_token ('*');
8786 i.types[this_operand].bitfield.baseindex = 1;
8788 /* Set the scale after setting the register (otherwise,
8789 i386_scale will complain) */
8790 if (cur_token.code == '+' || cur_token.code == '-')
8792 char *str, sign = cur_token.code;
8793 intel_match_token (cur_token.code);
8794 if (cur_token.code != T_CONST)
8796 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8800 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8801 strcpy (str + 1, cur_token.str);
8803 if (!i386_scale (str))
8807 else if (!i386_scale (cur_token.str))
8809 intel_match_token (cur_token.code);
8812 /* No scaling. If this is a memory operand, the register is either a
8813 base register (first occurrence) or an index register (second
8815 else if (intel_parser.in_bracket)
8820 else if (!i.index_reg)
8824 as_bad (_("Too many register references in memory operand"));
8828 i.types[this_operand].bitfield.baseindex = 1;
8831 /* It's neither base nor index. */
8832 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8834 i386_operand_type temp = reg->reg_type;
8835 temp.bitfield.baseindex = 0;
8836 i.types[this_operand] = operand_type_or (i.types[this_operand],
8838 i.types[this_operand].bitfield.unspecified = 0;
8839 i.op[this_operand].regs = reg;
8844 as_bad (_("Invalid use of register"));
8848 /* Since registers are not part of the displacement string (except
8849 when we're parsing offset operands), we may need to remove any
8850 preceding '+' from the displacement string. */
8851 if (*intel_parser.disp != '\0'
8852 && !intel_parser.in_offset)
8854 char *s = intel_parser.disp;
8855 s += strlen (s) - 1;
8878 intel_match_token (cur_token.code);
8880 if (cur_token.code == T_PTR)
8883 /* It must have been an identifier. */
8884 intel_putback_token ();
8885 cur_token.code = T_ID;
8891 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8895 /* The identifier represents a memory reference only if it's not
8896 preceded by an offset modifier and if it's not an equate. */
8897 symbolP = symbol_find(cur_token.str);
8898 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8899 intel_parser.is_mem = 1;
8907 char *save_str, sign = 0;
8909 /* Allow constants that start with `+' or `-'. */
8910 if (cur_token.code == '-' || cur_token.code == '+')
8912 sign = cur_token.code;
8913 intel_match_token (cur_token.code);
8914 if (cur_token.code != T_CONST)
8916 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8922 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8923 strcpy (save_str + !!sign, cur_token.str);
8927 /* Get the next token to check for register scaling. */
8928 intel_match_token (cur_token.code);
8930 /* Check if this constant is a scaling factor for an
8932 if (cur_token.code == '*')
8934 if (intel_match_token ('*') && cur_token.code == T_REG)
8936 const reg_entry *reg = cur_token.reg;
8938 if (!intel_parser.in_bracket)
8940 as_bad (_("Register scaling only allowed "
8941 "in memory operands"));
8945 /* Disallow things like [1*si].
8946 sp and esp are invalid as index. */
8947 if (reg->reg_type.bitfield.reg16)
8948 reg = i386_regtab + REGNAM_AX + 4;
8949 else if (i.index_reg)
8950 reg = i386_regtab + REGNAM_EAX + 4;
8952 /* The constant is followed by `* reg', so it must be
8955 i.types[this_operand].bitfield.baseindex = 1;
8957 /* Set the scale after setting the register (otherwise,
8958 i386_scale will complain) */
8959 if (!i386_scale (save_str))
8961 intel_match_token (T_REG);
8963 /* Since registers are not part of the displacement
8964 string, we may need to remove any preceding '+' from
8965 the displacement string. */
8966 if (*intel_parser.disp != '\0')
8968 char *s = intel_parser.disp;
8969 s += strlen (s) - 1;
8979 /* The constant was not used for register scaling. Since we have
8980 already consumed the token following `*' we now need to put it
8981 back in the stream. */
8982 intel_putback_token ();
8985 /* Add the constant to the displacement string. */
8986 strcat (intel_parser.disp, save_str);
8993 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8997 /* Match the given token against cur_token. If they match, read the next
8998 token from the operand string. */
9000 intel_match_token (int code)
9002 if (cur_token.code == code)
9009 as_bad (_("Unexpected token `%s'"), cur_token.str);
9014 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9016 intel_get_token (void)
9019 const reg_entry *reg;
9020 struct intel_token new_token;
9022 new_token.code = T_NIL;
9023 new_token.reg = NULL;
9024 new_token.str = NULL;
9026 /* Free the memory allocated to the previous token and move
9027 cur_token to prev_token. */
9029 free (prev_token.str);
9031 prev_token = cur_token;
9033 /* Skip whitespace. */
9034 while (is_space_char (*intel_parser.op_string))
9035 intel_parser.op_string++;
9037 /* Return an empty token if we find nothing else on the line. */
9038 if (*intel_parser.op_string == '\0')
9040 cur_token = new_token;
9044 /* The new token cannot be larger than the remainder of the operand
9046 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
9047 new_token.str[0] = '\0';
9049 if (strchr ("0123456789", *intel_parser.op_string))
9051 char *p = new_token.str;
9052 char *q = intel_parser.op_string;
9053 new_token.code = T_CONST;
9055 /* Allow any kind of identifier char to encompass floating point and
9056 hexadecimal numbers. */
9057 while (is_identifier_char (*q))
9061 /* Recognize special symbol names [0-9][bf]. */
9062 if (strlen (intel_parser.op_string) == 2
9063 && (intel_parser.op_string[1] == 'b'
9064 || intel_parser.op_string[1] == 'f'))
9065 new_token.code = T_ID;
9068 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9070 size_t len = end_op - intel_parser.op_string;
9072 new_token.code = T_REG;
9073 new_token.reg = reg;
9075 memcpy (new_token.str, intel_parser.op_string, len);
9076 new_token.str[len] = '\0';
9079 else if (is_identifier_char (*intel_parser.op_string))
9081 char *p = new_token.str;
9082 char *q = intel_parser.op_string;
9084 /* A '.' or '$' followed by an identifier char is an identifier.
9085 Otherwise, it's operator '.' followed by an expression. */
9086 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9088 new_token.code = '.';
9089 new_token.str[0] = '.';
9090 new_token.str[1] = '\0';
9094 while (is_identifier_char (*q) || *q == '@')
9098 if (strcasecmp (new_token.str, "NOT") == 0)
9099 new_token.code = '~';
9101 else if (strcasecmp (new_token.str, "MOD") == 0)
9102 new_token.code = '%';
9104 else if (strcasecmp (new_token.str, "AND") == 0)
9105 new_token.code = '&';
9107 else if (strcasecmp (new_token.str, "OR") == 0)
9108 new_token.code = '|';
9110 else if (strcasecmp (new_token.str, "XOR") == 0)
9111 new_token.code = '^';
9113 else if (strcasecmp (new_token.str, "SHL") == 0)
9114 new_token.code = T_SHL;
9116 else if (strcasecmp (new_token.str, "SHR") == 0)
9117 new_token.code = T_SHR;
9119 else if (strcasecmp (new_token.str, "BYTE") == 0)
9120 new_token.code = T_BYTE;
9122 else if (strcasecmp (new_token.str, "WORD") == 0)
9123 new_token.code = T_WORD;
9125 else if (strcasecmp (new_token.str, "DWORD") == 0)
9126 new_token.code = T_DWORD;
9128 else if (strcasecmp (new_token.str, "FWORD") == 0)
9129 new_token.code = T_FWORD;
9131 else if (strcasecmp (new_token.str, "QWORD") == 0)
9132 new_token.code = T_QWORD;
9134 else if (strcasecmp (new_token.str, "TBYTE") == 0
9135 /* XXX remove (gcc still uses it) */
9136 || strcasecmp (new_token.str, "XWORD") == 0)
9137 new_token.code = T_TBYTE;
9139 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9140 || strcasecmp (new_token.str, "OWORD") == 0)
9141 new_token.code = T_XMMWORD;
9143 else if (strcasecmp (new_token.str, "PTR") == 0)
9144 new_token.code = T_PTR;
9146 else if (strcasecmp (new_token.str, "SHORT") == 0)
9147 new_token.code = T_SHORT;
9149 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9151 new_token.code = T_OFFSET;
9153 /* ??? This is not mentioned in the MASM grammar but gcc
9154 makes use of it with -mintel-syntax. OFFSET may be
9155 followed by FLAT: */
9156 if (strncasecmp (q, " FLAT:", 6) == 0)
9157 strcat (new_token.str, " FLAT:");
9161 new_token.code = T_ID;
9165 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9167 new_token.code = *intel_parser.op_string;
9168 new_token.str[0] = *intel_parser.op_string;
9169 new_token.str[1] = '\0';
9172 else if (strchr ("<>", *intel_parser.op_string)
9173 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9175 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9176 new_token.str[0] = *intel_parser.op_string;
9177 new_token.str[1] = *intel_parser.op_string;
9178 new_token.str[2] = '\0';
9182 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9184 intel_parser.op_string += strlen (new_token.str);
9185 cur_token = new_token;
9188 /* Put cur_token back into the token stream and make cur_token point to
9191 intel_putback_token (void)
9193 if (cur_token.code != T_NIL)
9195 intel_parser.op_string -= strlen (cur_token.str);
9196 free (cur_token.str);
9198 cur_token = prev_token;
9200 /* Forget prev_token. */
9201 prev_token.code = T_NIL;
9202 prev_token.reg = NULL;
9203 prev_token.str = NULL;
9207 tc_x86_parse_to_dw2regnum (expressionS *exp)
9209 int saved_naked_reg;
9210 char saved_register_dot;
9212 saved_naked_reg = allow_naked_reg;
9213 allow_naked_reg = 1;
9214 saved_register_dot = register_chars['.'];
9215 register_chars['.'] = '.';
9216 allow_pseudo_reg = 1;
9217 expression_and_evaluate (exp);
9218 allow_pseudo_reg = 0;
9219 register_chars['.'] = saved_register_dot;
9220 allow_naked_reg = saved_naked_reg;
9222 if (exp->X_op == O_register && exp->X_add_number >= 0)
9224 if ((addressT) exp->X_add_number < i386_regtab_size)
9226 exp->X_op = O_constant;
9227 exp->X_add_number = i386_regtab[exp->X_add_number]
9228 .dw2_regnum[flag_code >> 1];
9231 exp->X_op = O_illegal;
9236 tc_x86_frame_initial_instructions (void)
9238 static unsigned int sp_regno[2];
9240 if (!sp_regno[flag_code >> 1])
9242 char *saved_input = input_line_pointer;
9243 char sp[][4] = {"esp", "rsp"};
9246 input_line_pointer = sp[flag_code >> 1];
9247 tc_x86_parse_to_dw2regnum (&exp);
9248 assert (exp.X_op == O_constant);
9249 sp_regno[flag_code >> 1] = exp.X_add_number;
9250 input_line_pointer = saved_input;
9253 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9254 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9258 i386_elf_section_type (const char *str, size_t len)
9260 if (flag_code == CODE_64BIT
9261 && len == sizeof ("unwind") - 1
9262 && strncmp (str, "unwind", 6) == 0)
9263 return SHT_X86_64_UNWIND;
9270 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9274 expr.X_op = O_secrel;
9275 expr.X_add_symbol = symbol;
9276 expr.X_add_number = 0;
9277 emit_expr (&expr, size);
9281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9282 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9285 x86_64_section_letter (int letter, char **ptr_msg)
9287 if (flag_code == CODE_64BIT)
9290 return SHF_X86_64_LARGE;
9292 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9295 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9300 x86_64_section_word (char *str, size_t len)
9302 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9303 return SHF_X86_64_LARGE;
9309 handle_large_common (int small ATTRIBUTE_UNUSED)
9311 if (flag_code != CODE_64BIT)
9313 s_comm_internal (0, elf_common_parse);
9314 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9318 static segT lbss_section;
9319 asection *saved_com_section_ptr = elf_com_section_ptr;
9320 asection *saved_bss_section = bss_section;
9322 if (lbss_section == NULL)
9324 flagword applicable;
9326 subsegT subseg = now_subseg;
9328 /* The .lbss section is for local .largecomm symbols. */
9329 lbss_section = subseg_new (".lbss", 0);
9330 applicable = bfd_applicable_section_flags (stdoutput);
9331 bfd_set_section_flags (stdoutput, lbss_section,
9332 applicable & SEC_ALLOC);
9333 seg_info (lbss_section)->bss = 1;
9335 subseg_set (seg, subseg);
9338 elf_com_section_ptr = &_bfd_elf_large_com_section;
9339 bss_section = lbss_section;
9341 s_comm_internal (0, elf_common_parse);
9343 elf_com_section_ptr = saved_com_section_ptr;
9344 bss_section = saved_bss_section;
9347 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */