1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static char *output_invalid PARAMS ((int c));
84 static int i386_operand PARAMS ((char *operand_string));
85 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86 static const reg_entry *parse_register PARAMS ((char *reg_string,
88 static char *parse_insn PARAMS ((char *, char *));
89 static char *parse_operands PARAMS ((char *, const char *));
90 static void swap_operands PARAMS ((void));
91 static void optimize_imm PARAMS ((void));
92 static void optimize_disp PARAMS ((void));
93 static int match_template PARAMS ((void));
94 static int check_string PARAMS ((void));
95 static int process_suffix PARAMS ((void));
96 static int check_byte_reg PARAMS ((void));
97 static int check_long_reg PARAMS ((void));
98 static int check_qword_reg PARAMS ((void));
99 static int check_word_reg PARAMS ((void));
100 static int finalize_imm PARAMS ((void));
101 static int process_operands PARAMS ((void));
102 static const seg_entry *build_modrm_byte PARAMS ((void));
103 static void output_insn PARAMS ((void));
104 static void output_branch PARAMS ((void));
105 static void output_jump PARAMS ((void));
106 static void output_interseg_jump PARAMS ((void));
107 static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109 static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
112 static void s_bss PARAMS ((int));
115 static const char *default_arch = DEFAULT_ARCH;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry *regs;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types[MAX_OPERANDS];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op[MAX_OPERANDS];
152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry *seg[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars[] = "/#";
225 const char line_separator_chars[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars[256];
238 static char register_chars[256];
239 static char operand_chars[256];
240 static char identifier_chars[256];
241 static char digit_chars[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack[32];
259 static char *save_stack_p;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates *current_templates;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions[2], im_expressions[2];
274 /* Current operand we are working on. */
275 static int this_operand;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code;
287 static int use_rela_relocations = 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names[] =
297 /* 1 for intel syntax,
299 static int intel_syntax = 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg = 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size = '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code = 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings = 0;
316 static const char *cpu_arch_name = NULL;
317 static const char *cpu_sub_arch_name = NULL;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion = 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch[] = {
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
433 {".sse", CpuMMX|CpuMMX2|CpuSSE },
434 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
435 {".3dnow", CpuMMX|Cpu3dnow },
436 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
437 {".padlock", CpuPadLock },
441 const pseudo_typeS md_pseudo_table[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes, 0},
446 {"align", s_align_ptwo, 0},
448 {"arch", set_cpu_arch, 0},
452 {"ffloat", float_cons, 'f'},
453 {"dfloat", float_cons, 'd'},
454 {"tfloat", float_cons, 'x'},
456 {"noopt", s_ignore, 0},
457 {"optim", s_ignore, 0},
458 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
459 {"code16", set_code_flag, CODE_16BIT},
460 {"code32", set_code_flag, CODE_32BIT},
461 {"code64", set_code_flag, CODE_64BIT},
462 {"intel_syntax", set_intel_syntax, 1},
463 {"att_syntax", set_intel_syntax, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
465 {"loc", dwarf2_directive_loc, 0},
467 {"secrel32", pe_directive_secrel, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control *op_hash;
478 /* Hash table for register lookup. */
479 static struct hash_control *reg_hash;
482 i386_align_code (fragP, count)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1[] =
491 static const char f32_2[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt[] = {
545 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
546 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
548 static const char *const f16_patt[] = {
549 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
550 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
553 if (count <= 0 || count > 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code == CODE_64BIT)
561 int nnops = (count + 3) / 4;
562 int len = count / nnops;
563 int remains = count - nnops * len;
566 for (i = 0; i < remains; i++)
568 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
569 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
572 for (; i < nnops; i++)
574 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
575 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
580 if (flag_code == CODE_16BIT)
582 memcpy (fragP->fr_literal + fragP->fr_fix,
583 f16_patt[count - 1], count);
585 /* Adjust jump offset. */
586 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
589 memcpy (fragP->fr_literal + fragP->fr_fix,
590 f32_patt[count - 1], count);
591 fragP->fr_var = count;
594 static INLINE unsigned int
595 mode_from_disp_size (t)
598 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
602 fits_in_signed_byte (num)
605 return (num >= -128) && (num <= 127);
609 fits_in_unsigned_byte (num)
612 return (num & 0xff) == num;
616 fits_in_unsigned_word (num)
619 return (num & 0xffff) == num;
623 fits_in_signed_word (num)
626 return (-32768 <= num) && (num <= 32767);
629 fits_in_signed_long (num)
630 offsetT num ATTRIBUTE_UNUSED;
635 return (!(((offsetT) -1 << 31) & num)
636 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
646 return (num & (((offsetT) 2 << 31) - 1)) == num;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num)
654 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
664 return (fits_in_signed_byte (num)
665 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
666 : fits_in_unsigned_byte (num)
667 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
668 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
669 ? (Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_signed_long (num)
671 ? (Imm32 | Imm32S | Imm64)
672 : fits_in_unsigned_long (num)
678 offset_in_range (val, size)
686 case 1: mask = ((addressT) 1 << 8) - 1; break;
687 case 2: mask = ((addressT) 1 << 16) - 1; break;
688 case 4: mask = ((addressT) 2 << 31) - 1; break;
690 case 8: mask = ((addressT) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations)
697 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
698 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
700 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
702 char buf1[40], buf2[40];
704 sprint_value (buf1, val);
705 sprint_value (buf2, val & mask);
706 as_warn (_("%s shortened to %s"), buf1, buf2);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
722 && flag_code == CODE_64BIT)
730 case CS_PREFIX_OPCODE:
731 case DS_PREFIX_OPCODE:
732 case ES_PREFIX_OPCODE:
733 case FS_PREFIX_OPCODE:
734 case GS_PREFIX_OPCODE:
735 case SS_PREFIX_OPCODE:
739 case REPNE_PREFIX_OPCODE:
740 case REPE_PREFIX_OPCODE:
743 case LOCK_PREFIX_OPCODE:
751 case ADDR_PREFIX_OPCODE:
755 case DATA_PREFIX_OPCODE:
760 if (i.prefix[q] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i.prefix[q] = prefix;
772 set_code_flag (value)
776 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
777 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag)
793 flag_code = new_code_flag;
794 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
795 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
796 stackop_size = LONG_MNEM_SUFFIX;
800 set_intel_syntax (syntax_flag)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg = 0;
807 if (!is_end_of_line[(unsigned char) *input_line_pointer])
809 char *string = input_line_pointer;
810 int e = get_symbol_end ();
812 if (strcmp (string, "prefix") == 0)
814 else if (strcmp (string, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer = e;
820 demand_empty_rest_of_line ();
822 intel_syntax = syntax_flag;
824 if (ask_naked_reg == 0)
825 allow_naked_reg = (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
828 allow_naked_reg = (ask_naked_reg < 0);
830 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
831 identifier_chars['$'] = intel_syntax ? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED;
840 if (!is_end_of_line[(unsigned char) *input_line_pointer])
842 char *string = input_line_pointer;
843 int e = get_symbol_end ();
846 for (i = 0; cpu_arch[i].name; i++)
848 if (strcmp (string, cpu_arch[i].name) == 0)
852 cpu_arch_name = cpu_arch[i].name;
853 cpu_sub_arch_name = NULL;
854 cpu_arch_flags = (cpu_arch[i].flags
855 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
858 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
860 cpu_sub_arch_name = cpu_arch[i].name;
861 cpu_arch_flags |= cpu_arch[i].flags;
863 *input_line_pointer = e;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch[i].name)
869 as_bad (_("no such architecture: `%s'"), string);
871 *input_line_pointer = e;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion = 0;
877 if (*input_line_pointer == ','
878 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
880 char *string = ++input_line_pointer;
881 int e = get_symbol_end ();
883 if (strcmp (string, "nojumps") == 0)
884 no_cond_jump_promotion = 1;
885 else if (strcmp (string, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string);
890 *input_line_pointer = e;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch, "x86_64"))
900 return bfd_mach_x86_64;
901 else if (!strcmp (default_arch, "i386"))
902 return bfd_mach_i386_i386;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err;
912 /* Initialize op_hash hash table. */
913 op_hash = hash_new ();
916 const template *optab;
917 templates *core_optab;
919 /* Setup for loop. */
921 core_optab = (templates *) xmalloc (sizeof (templates));
922 core_optab->start = optab;
927 if (optab->name == NULL
928 || strcmp (optab->name, (optab - 1)->name) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab->end = optab;
933 hash_err = hash_insert (op_hash,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab->name == NULL)
944 core_optab = (templates *) xmalloc (sizeof (templates));
945 core_optab->start = optab;
950 /* Initialize reg_hash hash table. */
951 reg_hash = hash_new ();
953 const reg_entry *regtab;
955 for (regtab = i386_regtab;
956 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
959 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c = 0; c < 256; c++)
977 mnemonic_chars[c] = c;
978 register_chars[c] = c;
979 operand_chars[c] = c;
981 else if (ISLOWER (c))
983 mnemonic_chars[c] = c;
984 register_chars[c] = c;
985 operand_chars[c] = c;
987 else if (ISUPPER (c))
989 mnemonic_chars[c] = TOLOWER (c);
990 register_chars[c] = mnemonic_chars[c];
991 operand_chars[c] = c;
994 if (ISALPHA (c) || ISDIGIT (c))
995 identifier_chars[c] = c;
998 identifier_chars[c] = c;
999 operand_chars[c] = c;
1004 identifier_chars['@'] = '@';
1007 identifier_chars['?'] = '?';
1008 operand_chars['?'] = '?';
1010 digit_chars['-'] = '-';
1011 identifier_chars['_'] = '_';
1012 identifier_chars['.'] = '.';
1014 for (p = operand_special_chars; *p != '\0'; p++)
1015 operand_chars[(unsigned char) *p] = *p;
1018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1019 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1021 record_alignment (text_section, 2);
1022 record_alignment (data_section, 2);
1023 record_alignment (bss_section, 2);
1027 if (flag_code == CODE_64BIT)
1029 x86_dwarf2_return_column = 16;
1030 x86_cie_data_alignment = -8;
1034 x86_dwarf2_return_column = 8;
1035 x86_cie_data_alignment = -4;
1040 i386_print_statistics (file)
1043 hash_print_statistics (file, "i386 opcode", op_hash);
1044 hash_print_statistics (file, "i386 register", reg_hash);
1049 /* Debugging routines for md_assemble. */
1050 static void pi PARAMS ((char *, i386_insn *));
1051 static void pte PARAMS ((template *));
1052 static void pt PARAMS ((unsigned int));
1053 static void pe PARAMS ((expressionS *));
1054 static void ps PARAMS ((symbolS *));
1063 fprintf (stdout, "%s: template ", line);
1065 fprintf (stdout, " address: base %s index %s scale %x\n",
1066 x->base_reg ? x->base_reg->reg_name : "none",
1067 x->index_reg ? x->index_reg->reg_name : "none",
1068 x->log2_scale_factor);
1069 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1070 x->rm.mode, x->rm.reg, x->rm.regmem);
1071 fprintf (stdout, " sib: base %x index %x scale %x\n",
1072 x->sib.base, x->sib.index, x->sib.scale);
1073 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1074 (x->rex & REX_MODE64) != 0,
1075 (x->rex & REX_EXTX) != 0,
1076 (x->rex & REX_EXTY) != 0,
1077 (x->rex & REX_EXTZ) != 0);
1078 for (i = 0; i < x->operands; i++)
1080 fprintf (stdout, " #%d: ", i + 1);
1082 fprintf (stdout, "\n");
1084 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1085 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1086 if (x->types[i] & Imm)
1088 if (x->types[i] & Disp)
1089 pe (x->op[i].disps);
1098 fprintf (stdout, " %d operands ", t->operands);
1099 fprintf (stdout, "opcode %x ", t->base_opcode);
1100 if (t->extension_opcode != None)
1101 fprintf (stdout, "ext %x ", t->extension_opcode);
1102 if (t->opcode_modifier & D)
1103 fprintf (stdout, "D");
1104 if (t->opcode_modifier & W)
1105 fprintf (stdout, "W");
1106 fprintf (stdout, "\n");
1107 for (i = 0; i < t->operands; i++)
1109 fprintf (stdout, " #%d type ", i + 1);
1110 pt (t->operand_types[i]);
1111 fprintf (stdout, "\n");
1119 fprintf (stdout, " operation %d\n", e->X_op);
1120 fprintf (stdout, " add_number %ld (%lx)\n",
1121 (long) e->X_add_number, (long) e->X_add_number);
1122 if (e->X_add_symbol)
1124 fprintf (stdout, " add_symbol ");
1125 ps (e->X_add_symbol);
1126 fprintf (stdout, "\n");
1130 fprintf (stdout, " op_symbol ");
1131 ps (e->X_op_symbol);
1132 fprintf (stdout, "\n");
1140 fprintf (stdout, "%s type %s%s",
1142 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1143 segment_name (S_GET_SEGMENT (s)));
1152 static const type_names[] =
1165 { BaseIndex, "BaseIndex" },
1169 { Disp32S, "d32s" },
1171 { InOutPortReg, "InOutPortReg" },
1172 { ShiftCount, "ShiftCount" },
1173 { Control, "control reg" },
1174 { Test, "test reg" },
1175 { Debug, "debug reg" },
1176 { FloatReg, "FReg" },
1177 { FloatAcc, "FAcc" },
1181 { JumpAbsolute, "Jump Absolute" },
1192 const struct type_name *ty;
1194 for (ty = type_names; ty->mask; ty++)
1196 fprintf (stdout, "%s, ", ty->tname);
1200 #endif /* DEBUG386 */
1202 static bfd_reloc_code_real_type reloc
1203 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1205 static bfd_reloc_code_real_type
1206 reloc (size, pcrel, sign, other)
1210 bfd_reloc_code_real_type other;
1212 if (other != NO_RELOC)
1218 as_bad (_("There are no unsigned pc-relative relocations"));
1221 case 1: return BFD_RELOC_8_PCREL;
1222 case 2: return BFD_RELOC_16_PCREL;
1223 case 4: return BFD_RELOC_32_PCREL;
1225 as_bad (_("can not do %d byte pc-relative relocation"), size);
1232 case 4: return BFD_RELOC_X86_64_32S;
1237 case 1: return BFD_RELOC_8;
1238 case 2: return BFD_RELOC_16;
1239 case 4: return BFD_RELOC_32;
1240 case 8: return BFD_RELOC_64;
1242 as_bad (_("can not do %s %d byte relocation"),
1243 sign ? "signed" : "unsigned", size);
1247 return BFD_RELOC_NONE;
1250 /* Here we decide which fixups can be adjusted to make them relative to
1251 the beginning of the section instead of the symbol. Basically we need
1252 to make sure that the dynamic relocations are done correctly, so in
1253 some cases we force the original symbol to be used. */
1256 tc_i386_fix_adjustable (fixP)
1257 fixS *fixP ATTRIBUTE_UNUSED;
1259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1260 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1263 /* Don't adjust pc-relative references to merge sections in 64-bit
1265 if (use_rela_relocations
1266 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1270 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1271 and changed later by validate_fix. */
1272 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1273 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1276 /* adjust_reloc_syms doesn't know about the GOT. */
1277 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1278 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1279 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1280 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1281 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1282 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1283 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1284 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1285 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1288 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1289 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1290 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1291 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1292 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1293 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1296 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1297 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1303 static int intel_float_operand PARAMS ((const char *mnemonic));
1306 intel_float_operand (mnemonic)
1307 const char *mnemonic;
1309 /* Note that the value returned is meaningful only for opcodes with (memory)
1310 operands, hence the code here is free to improperly handle opcodes that
1311 have no operands (for better performance and smaller code). */
1313 if (mnemonic[0] != 'f')
1314 return 0; /* non-math */
1316 switch (mnemonic[1])
1318 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1319 the fs segment override prefix not currently handled because no
1320 call path can make opcodes without operands get here */
1322 return 2 /* integer op */;
1324 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1325 return 3; /* fldcw/fldenv */
1328 if (mnemonic[2] != 'o' /* fnop */)
1329 return 3; /* non-waiting control op */
1332 if (mnemonic[2] == 's')
1333 return 3; /* frstor/frstpm */
1336 if (mnemonic[2] == 'a')
1337 return 3; /* fsave */
1338 if (mnemonic[2] == 't')
1340 switch (mnemonic[3])
1342 case 'c': /* fstcw */
1343 case 'd': /* fstdw */
1344 case 'e': /* fstenv */
1345 case 's': /* fsts[gw] */
1351 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1352 return 0; /* fxsave/fxrstor are not really math ops */
1359 /* This is the guts of the machine-dependent assembler. LINE points to a
1360 machine dependent instruction. This function is supposed to emit
1361 the frags/bytes it assembles to. */
1368 char mnemonic[MAX_MNEM_SIZE];
1370 /* Initialize globals. */
1371 memset (&i, '\0', sizeof (i));
1372 for (j = 0; j < MAX_OPERANDS; j++)
1373 i.reloc[j] = NO_RELOC;
1374 memset (disp_expressions, '\0', sizeof (disp_expressions));
1375 memset (im_expressions, '\0', sizeof (im_expressions));
1376 save_stack_p = save_stack;
1378 /* First parse an instruction mnemonic & call i386_operand for the operands.
1379 We assume that the scrubber has arranged it so that line[0] is the valid
1380 start of a (possibly prefixed) mnemonic. */
1382 line = parse_insn (line, mnemonic);
1386 line = parse_operands (line, mnemonic);
1390 /* Now we've parsed the mnemonic into a set of templates, and have the
1391 operands at hand. */
1393 /* All intel opcodes have reversed operands except for "bound" and
1394 "enter". We also don't reverse intersegment "jmp" and "call"
1395 instructions with 2 immediate operands so that the immediate segment
1396 precedes the offset, as it does when in AT&T mode. "enter" and the
1397 intersegment "jmp" and "call" instructions are the only ones that
1398 have two immediate operands. */
1399 if (intel_syntax && i.operands > 1
1400 && (strcmp (mnemonic, "bound") != 0)
1401 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1407 if (i.disp_operands)
1410 /* Next, we find a template that matches the given insn,
1411 making sure the overlap of the given operands types is consistent
1412 with the template operand types. */
1414 if (!match_template ())
1419 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1421 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1422 i.tm.base_opcode ^= FloatR;
1424 /* Zap movzx and movsx suffix. The suffix may have been set from
1425 "word ptr" or "byte ptr" on the source operand, but we'll use
1426 the suffix later to choose the destination register. */
1427 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1429 if (i.reg_operands < 2
1431 && (~i.tm.opcode_modifier
1438 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1444 if (i.tm.opcode_modifier & FWait)
1445 if (!add_prefix (FWAIT_OPCODE))
1448 /* Check string instruction segment overrides. */
1449 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1451 if (!check_string ())
1455 if (!process_suffix ())
1458 /* Make still unresolved immediate matches conform to size of immediate
1459 given in i.suffix. */
1460 if (!finalize_imm ())
1463 if (i.types[0] & Imm1)
1464 i.imm_operands = 0; /* kludge for shift insns. */
1465 if (i.types[0] & ImplicitRegister)
1467 if (i.types[1] & ImplicitRegister)
1469 if (i.types[2] & ImplicitRegister)
1472 if (i.tm.opcode_modifier & ImmExt)
1476 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1478 /* These Intel Prescott New Instructions have the fixed
1479 operands with an opcode suffix which is coded in the same
1480 place as an 8-bit immediate field would be. Here we check
1481 those operands and remove them afterwards. */
1484 for (x = 0; x < i.operands; x++)
1485 if (i.op[x].regs->reg_num != x)
1486 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1487 i.op[x].regs->reg_name, x + 1, i.tm.name);
1491 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1492 opcode suffix which is coded in the same place as an 8-bit
1493 immediate field would be. Here we fake an 8-bit immediate
1494 operand from the opcode suffix stored in tm.extension_opcode. */
1496 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1498 exp = &im_expressions[i.imm_operands++];
1499 i.op[i.operands].imms = exp;
1500 i.types[i.operands++] = Imm8;
1501 exp->X_op = O_constant;
1502 exp->X_add_number = i.tm.extension_opcode;
1503 i.tm.extension_opcode = None;
1506 /* For insns with operands there are more diddles to do to the opcode. */
1509 if (!process_operands ())
1512 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1514 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1515 as_warn (_("translating to `%sp'"), i.tm.name);
1518 /* Handle conversion of 'int $3' --> special int3 insn. */
1519 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1521 i.tm.base_opcode = INT3_OPCODE;
1525 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1526 && i.op[0].disps->X_op == O_constant)
1528 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1529 the absolute address given by the constant. Since ix86 jumps and
1530 calls are pc relative, we need to generate a reloc. */
1531 i.op[0].disps->X_add_symbol = &abs_symbol;
1532 i.op[0].disps->X_op = O_symbol;
1535 if ((i.tm.opcode_modifier & Rex64) != 0)
1536 i.rex |= REX_MODE64;
1538 /* For 8 bit registers we need an empty rex prefix. Also if the
1539 instruction already has a prefix, we need to convert old
1540 registers to new ones. */
1542 if (((i.types[0] & Reg8) != 0
1543 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1544 || ((i.types[1] & Reg8) != 0
1545 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1546 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1551 i.rex |= REX_OPCODE;
1552 for (x = 0; x < 2; x++)
1554 /* Look for 8 bit operand that uses old registers. */
1555 if ((i.types[x] & Reg8) != 0
1556 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1558 /* In case it is "hi" register, give up. */
1559 if (i.op[x].regs->reg_num > 3)
1560 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1561 i.op[x].regs->reg_name);
1563 /* Otherwise it is equivalent to the extended register.
1564 Since the encoding doesn't change this is merely
1565 cosmetic cleanup for debug output. */
1567 i.op[x].regs = i.op[x].regs + 8;
1573 add_prefix (REX_OPCODE | i.rex);
1575 /* We are ready to output the insn. */
1580 parse_insn (line, mnemonic)
1585 char *token_start = l;
1590 /* Non-zero if we found a prefix only acceptable with string insns. */
1591 const char *expecting_string_instruction = NULL;
1596 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1599 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1601 as_bad (_("no such instruction: `%s'"), token_start);
1606 if (!is_space_char (*l)
1607 && *l != END_OF_INSN
1608 && *l != PREFIX_SEPARATOR
1611 as_bad (_("invalid character %s in mnemonic"),
1612 output_invalid (*l));
1615 if (token_start == l)
1617 if (*l == PREFIX_SEPARATOR)
1618 as_bad (_("expecting prefix; got nothing"));
1620 as_bad (_("expecting mnemonic; got nothing"));
1624 /* Look up instruction (or prefix) via hash table. */
1625 current_templates = hash_find (op_hash, mnemonic);
1627 if (*l != END_OF_INSN
1628 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1629 && current_templates
1630 && (current_templates->start->opcode_modifier & IsPrefix))
1632 /* If we are in 16-bit mode, do not allow addr16 or data16.
1633 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1634 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1635 && flag_code != CODE_64BIT
1636 && (((current_templates->start->opcode_modifier & Size32) != 0)
1637 ^ (flag_code == CODE_16BIT)))
1639 as_bad (_("redundant %s prefix"),
1640 current_templates->start->name);
1643 /* Add prefix, checking for repeated prefixes. */
1644 switch (add_prefix (current_templates->start->base_opcode))
1649 expecting_string_instruction = current_templates->start->name;
1652 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1659 if (!current_templates)
1661 /* See if we can get a match by trimming off a suffix. */
1664 case WORD_MNEM_SUFFIX:
1665 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1666 i.suffix = SHORT_MNEM_SUFFIX;
1668 case BYTE_MNEM_SUFFIX:
1669 case QWORD_MNEM_SUFFIX:
1670 i.suffix = mnem_p[-1];
1672 current_templates = hash_find (op_hash, mnemonic);
1674 case SHORT_MNEM_SUFFIX:
1675 case LONG_MNEM_SUFFIX:
1678 i.suffix = mnem_p[-1];
1680 current_templates = hash_find (op_hash, mnemonic);
1688 if (intel_float_operand (mnemonic) == 1)
1689 i.suffix = SHORT_MNEM_SUFFIX;
1691 i.suffix = LONG_MNEM_SUFFIX;
1693 current_templates = hash_find (op_hash, mnemonic);
1697 if (!current_templates)
1699 as_bad (_("no such instruction: `%s'"), token_start);
1704 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1706 /* Check for a branch hint. We allow ",pt" and ",pn" for
1707 predict taken and predict not taken respectively.
1708 I'm not sure that branch hints actually do anything on loop
1709 and jcxz insns (JumpByte) for current Pentium4 chips. They
1710 may work in the future and it doesn't hurt to accept them
1712 if (l[0] == ',' && l[1] == 'p')
1716 if (!add_prefix (DS_PREFIX_OPCODE))
1720 else if (l[2] == 'n')
1722 if (!add_prefix (CS_PREFIX_OPCODE))
1728 /* Any other comma loses. */
1731 as_bad (_("invalid character %s in mnemonic"),
1732 output_invalid (*l));
1736 /* Check if instruction is supported on specified architecture. */
1738 for (t = current_templates->start; t < current_templates->end; ++t)
1740 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1741 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1743 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1746 if (!(supported & 2))
1748 as_bad (flag_code == CODE_64BIT
1749 ? _("`%s' is not supported in 64-bit mode")
1750 : _("`%s' is only supported in 64-bit mode"),
1751 current_templates->start->name);
1754 if (!(supported & 1))
1756 as_warn (_("`%s' is not supported on `%s%s'"),
1757 current_templates->start->name,
1759 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1761 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1763 as_warn (_("use .code16 to ensure correct addressing mode"));
1766 /* Check for rep/repne without a string instruction. */
1767 if (expecting_string_instruction
1768 && !(current_templates->start->opcode_modifier & IsString))
1770 as_bad (_("expecting string instruction after `%s'"),
1771 expecting_string_instruction);
1779 parse_operands (l, mnemonic)
1781 const char *mnemonic;
1785 /* 1 if operand is pending after ','. */
1786 unsigned int expecting_operand = 0;
1788 /* Non-zero if operand parens not balanced. */
1789 unsigned int paren_not_balanced;
1791 while (*l != END_OF_INSN)
1793 /* Skip optional white space before operand. */
1794 if (is_space_char (*l))
1796 if (!is_operand_char (*l) && *l != END_OF_INSN)
1798 as_bad (_("invalid character %s before operand %d"),
1799 output_invalid (*l),
1803 token_start = l; /* after white space */
1804 paren_not_balanced = 0;
1805 while (paren_not_balanced || *l != ',')
1807 if (*l == END_OF_INSN)
1809 if (paren_not_balanced)
1812 as_bad (_("unbalanced parenthesis in operand %d."),
1815 as_bad (_("unbalanced brackets in operand %d."),
1820 break; /* we are done */
1822 else if (!is_operand_char (*l) && !is_space_char (*l))
1824 as_bad (_("invalid character %s in operand %d"),
1825 output_invalid (*l),
1832 ++paren_not_balanced;
1834 --paren_not_balanced;
1839 ++paren_not_balanced;
1841 --paren_not_balanced;
1845 if (l != token_start)
1846 { /* Yes, we've read in another operand. */
1847 unsigned int operand_ok;
1848 this_operand = i.operands++;
1849 if (i.operands > MAX_OPERANDS)
1851 as_bad (_("spurious operands; (%d operands/instruction max)"),
1855 /* Now parse operand adding info to 'i' as we go along. */
1856 END_STRING_AND_SAVE (l);
1860 i386_intel_operand (token_start,
1861 intel_float_operand (mnemonic));
1863 operand_ok = i386_operand (token_start);
1865 RESTORE_END_STRING (l);
1871 if (expecting_operand)
1873 expecting_operand_after_comma:
1874 as_bad (_("expecting operand after ','; got nothing"));
1879 as_bad (_("expecting operand before ','; got nothing"));
1884 /* Now *l must be either ',' or END_OF_INSN. */
1887 if (*++l == END_OF_INSN)
1889 /* Just skip it, if it's \n complain. */
1890 goto expecting_operand_after_comma;
1892 expecting_operand = 1;
1901 union i386_op temp_op;
1902 unsigned int temp_type;
1903 enum bfd_reloc_code_real temp_reloc;
1907 if (i.operands == 2)
1912 else if (i.operands == 3)
1917 temp_type = i.types[xchg2];
1918 i.types[xchg2] = i.types[xchg1];
1919 i.types[xchg1] = temp_type;
1920 temp_op = i.op[xchg2];
1921 i.op[xchg2] = i.op[xchg1];
1922 i.op[xchg1] = temp_op;
1923 temp_reloc = i.reloc[xchg2];
1924 i.reloc[xchg2] = i.reloc[xchg1];
1925 i.reloc[xchg1] = temp_reloc;
1927 if (i.mem_operands == 2)
1929 const seg_entry *temp_seg;
1930 temp_seg = i.seg[0];
1931 i.seg[0] = i.seg[1];
1932 i.seg[1] = temp_seg;
1936 /* Try to ensure constant immediates are represented in the smallest
1941 char guess_suffix = 0;
1945 guess_suffix = i.suffix;
1946 else if (i.reg_operands)
1948 /* Figure out a suffix from the last register operand specified.
1949 We can't do this properly yet, ie. excluding InOutPortReg,
1950 but the following works for instructions with immediates.
1951 In any case, we can't set i.suffix yet. */
1952 for (op = i.operands; --op >= 0;)
1953 if (i.types[op] & Reg)
1955 if (i.types[op] & Reg8)
1956 guess_suffix = BYTE_MNEM_SUFFIX;
1957 else if (i.types[op] & Reg16)
1958 guess_suffix = WORD_MNEM_SUFFIX;
1959 else if (i.types[op] & Reg32)
1960 guess_suffix = LONG_MNEM_SUFFIX;
1961 else if (i.types[op] & Reg64)
1962 guess_suffix = QWORD_MNEM_SUFFIX;
1966 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1967 guess_suffix = WORD_MNEM_SUFFIX;
1969 for (op = i.operands; --op >= 0;)
1970 if (i.types[op] & Imm)
1972 switch (i.op[op].imms->X_op)
1975 /* If a suffix is given, this operand may be shortened. */
1976 switch (guess_suffix)
1978 case LONG_MNEM_SUFFIX:
1979 i.types[op] |= Imm32 | Imm64;
1981 case WORD_MNEM_SUFFIX:
1982 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1984 case BYTE_MNEM_SUFFIX:
1985 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1989 /* If this operand is at most 16 bits, convert it
1990 to a signed 16 bit number before trying to see
1991 whether it will fit in an even smaller size.
1992 This allows a 16-bit operand such as $0xffe0 to
1993 be recognised as within Imm8S range. */
1994 if ((i.types[op] & Imm16)
1995 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1997 i.op[op].imms->X_add_number =
1998 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2000 if ((i.types[op] & Imm32)
2001 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2004 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2005 ^ ((offsetT) 1 << 31))
2006 - ((offsetT) 1 << 31));
2008 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2010 /* We must avoid matching of Imm32 templates when 64bit
2011 only immediate is available. */
2012 if (guess_suffix == QWORD_MNEM_SUFFIX)
2013 i.types[op] &= ~Imm32;
2020 /* Symbols and expressions. */
2022 /* Convert symbolic operand to proper sizes for matching. */
2023 switch (guess_suffix)
2025 case QWORD_MNEM_SUFFIX:
2026 i.types[op] = Imm64 | Imm32S;
2028 case LONG_MNEM_SUFFIX:
2029 i.types[op] = Imm32;
2031 case WORD_MNEM_SUFFIX:
2032 i.types[op] = Imm16;
2034 case BYTE_MNEM_SUFFIX:
2035 i.types[op] = Imm8 | Imm8S;
2043 /* Try to use the smallest displacement type too. */
2049 for (op = i.operands; --op >= 0;)
2050 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
2052 offsetT disp = i.op[op].disps->X_add_number;
2054 if (i.types[op] & Disp16)
2056 /* We know this operand is at most 16 bits, so
2057 convert to a signed 16 bit number before trying
2058 to see whether it will fit in an even smaller
2061 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2063 else if (i.types[op] & Disp32)
2065 /* We know this operand is at most 32 bits, so convert to a
2066 signed 32 bit number before trying to see whether it will
2067 fit in an even smaller size. */
2068 disp &= (((offsetT) 2 << 31) - 1);
2069 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2071 if (flag_code == CODE_64BIT)
2073 if (fits_in_signed_long (disp))
2074 i.types[op] |= Disp32S;
2075 if (fits_in_unsigned_long (disp))
2076 i.types[op] |= Disp32;
2078 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2079 && fits_in_signed_byte (disp))
2080 i.types[op] |= Disp8;
2087 /* Points to template once we've found it. */
2089 unsigned int overlap0, overlap1, overlap2;
2090 unsigned int found_reverse_match;
2093 #define MATCH(overlap, given, template) \
2094 ((overlap & ~JumpAbsolute) \
2095 && (((given) & (BaseIndex | JumpAbsolute)) \
2096 == ((overlap) & (BaseIndex | JumpAbsolute))))
2098 /* If given types r0 and r1 are registers they must be of the same type
2099 unless the expected operand type register overlap is null.
2100 Note that Acc in a template matches every size of reg. */
2101 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2102 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2103 || ((g0) & Reg) == ((g1) & Reg) \
2104 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2109 found_reverse_match = 0;
2110 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2112 : (i.suffix == WORD_MNEM_SUFFIX
2114 : (i.suffix == SHORT_MNEM_SUFFIX
2116 : (i.suffix == LONG_MNEM_SUFFIX
2118 : (i.suffix == QWORD_MNEM_SUFFIX
2120 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2121 ? No_xSuf : 0))))));
2123 t = current_templates->start;
2124 if (i.suffix == QWORD_MNEM_SUFFIX
2125 && flag_code != CODE_64BIT
2127 ? !(t->opcode_modifier & IgnoreSize)
2128 && !intel_float_operand (t->name)
2129 : intel_float_operand (t->name) != 2)
2130 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2131 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2132 && (t->base_opcode != 0x0fc7
2133 || t->extension_opcode != 1 /* cmpxchg8b */))
2134 t = current_templates->end;
2135 for (; t < current_templates->end; t++)
2137 /* Must have right number of operands. */
2138 if (i.operands != t->operands)
2141 /* Check the suffix, except for some instructions in intel mode. */
2142 if ((t->opcode_modifier & suffix_check)
2144 && (t->opcode_modifier & IgnoreSize)))
2147 /* Do not verify operands when there are none. */
2148 else if (!t->operands)
2150 if (t->cpu_flags & ~cpu_arch_flags)
2152 /* We've found a match; break out of loop. */
2156 overlap0 = i.types[0] & t->operand_types[0];
2157 switch (t->operands)
2160 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2165 overlap1 = i.types[1] & t->operand_types[1];
2166 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2167 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2168 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2169 t->operand_types[0],
2170 overlap1, i.types[1],
2171 t->operand_types[1]))
2173 /* Check if other direction is valid ... */
2174 if ((t->opcode_modifier & (D | FloatD)) == 0)
2177 /* Try reversing direction of operands. */
2178 overlap0 = i.types[0] & t->operand_types[1];
2179 overlap1 = i.types[1] & t->operand_types[0];
2180 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2181 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2182 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2183 t->operand_types[1],
2184 overlap1, i.types[1],
2185 t->operand_types[0]))
2187 /* Does not match either direction. */
2190 /* found_reverse_match holds which of D or FloatDR
2192 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2194 /* Found a forward 2 operand match here. */
2195 else if (t->operands == 3)
2197 /* Here we make use of the fact that there are no
2198 reverse match 3 operand instructions, and all 3
2199 operand instructions only need to be checked for
2200 register consistency between operands 2 and 3. */
2201 overlap2 = i.types[2] & t->operand_types[2];
2202 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2203 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2204 t->operand_types[1],
2205 overlap2, i.types[2],
2206 t->operand_types[2]))
2210 /* Found either forward/reverse 2 or 3 operand match here:
2211 slip through to break. */
2213 if (t->cpu_flags & ~cpu_arch_flags)
2215 found_reverse_match = 0;
2218 /* We've found a match; break out of loop. */
2222 if (t == current_templates->end)
2224 /* We found no match. */
2225 as_bad (_("suffix or operands invalid for `%s'"),
2226 current_templates->start->name);
2230 if (!quiet_warnings)
2233 && ((i.types[0] & JumpAbsolute)
2234 != (t->operand_types[0] & JumpAbsolute)))
2236 as_warn (_("indirect %s without `*'"), t->name);
2239 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2240 == (IsPrefix | IgnoreSize))
2242 /* Warn them that a data or address size prefix doesn't
2243 affect assembly of the next line of code. */
2244 as_warn (_("stand-alone `%s' prefix"), t->name);
2248 /* Copy the template we found. */
2250 if (found_reverse_match)
2252 /* If we found a reverse match we must alter the opcode
2253 direction bit. found_reverse_match holds bits to change
2254 (different for int & float insns). */
2256 i.tm.base_opcode ^= found_reverse_match;
2258 i.tm.operand_types[0] = t->operand_types[1];
2259 i.tm.operand_types[1] = t->operand_types[0];
2268 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2269 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2271 if (i.seg[0] != NULL && i.seg[0] != &es)
2273 as_bad (_("`%s' operand %d must use `%%es' segment"),
2278 /* There's only ever one segment override allowed per instruction.
2279 This instruction possibly has a legal segment override on the
2280 second operand, so copy the segment to where non-string
2281 instructions store it, allowing common code. */
2282 i.seg[0] = i.seg[1];
2284 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2286 if (i.seg[1] != NULL && i.seg[1] != &es)
2288 as_bad (_("`%s' operand %d must use `%%es' segment"),
2298 process_suffix (void)
2300 /* If matched instruction specifies an explicit instruction mnemonic
2302 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2304 if (i.tm.opcode_modifier & Size16)
2305 i.suffix = WORD_MNEM_SUFFIX;
2306 else if (i.tm.opcode_modifier & Size64)
2307 i.suffix = QWORD_MNEM_SUFFIX;
2309 i.suffix = LONG_MNEM_SUFFIX;
2311 else if (i.reg_operands)
2313 /* If there's no instruction mnemonic suffix we try to invent one
2314 based on register operands. */
2317 /* We take i.suffix from the last register operand specified,
2318 Destination register type is more significant than source
2322 for (op = i.operands; --op >= 0;)
2323 if ((i.types[op] & Reg)
2324 && !(i.tm.operand_types[op] & InOutPortReg))
2326 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2327 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2328 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2333 else if (i.suffix == BYTE_MNEM_SUFFIX)
2335 if (!check_byte_reg ())
2338 else if (i.suffix == LONG_MNEM_SUFFIX)
2340 if (!check_long_reg ())
2343 else if (i.suffix == QWORD_MNEM_SUFFIX)
2345 if (!check_qword_reg ())
2348 else if (i.suffix == WORD_MNEM_SUFFIX)
2350 if (!check_word_reg ())
2353 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2354 /* Do nothing if the instruction is going to ignore the prefix. */
2359 else if ((i.tm.opcode_modifier & DefaultSize)
2361 /* exclude fldenv/frstor/fsave/fstenv */
2362 && (i.tm.opcode_modifier & No_sSuf))
2364 i.suffix = stackop_size;
2366 else if (intel_syntax
2368 && ((i.tm.operand_types[0] & JumpAbsolute)
2369 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2370 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2371 && i.tm.extension_opcode <= 3)))
2376 if (!(i.tm.opcode_modifier & No_qSuf))
2378 i.suffix = QWORD_MNEM_SUFFIX;
2382 if (!(i.tm.opcode_modifier & No_lSuf))
2383 i.suffix = LONG_MNEM_SUFFIX;
2386 if (!(i.tm.opcode_modifier & No_wSuf))
2387 i.suffix = WORD_MNEM_SUFFIX;
2396 if (i.tm.opcode_modifier & W)
2398 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2404 unsigned int suffixes = ~i.tm.opcode_modifier
2412 if ((i.tm.opcode_modifier & W)
2413 || ((suffixes & (suffixes - 1))
2414 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2416 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2422 /* Change the opcode based on the operand size given by i.suffix;
2423 We don't need to change things for byte insns. */
2425 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2427 /* It's not a byte, select word/dword operation. */
2428 if (i.tm.opcode_modifier & W)
2430 if (i.tm.opcode_modifier & ShortForm)
2431 i.tm.base_opcode |= 8;
2433 i.tm.base_opcode |= 1;
2436 /* Now select between word & dword operations via the operand
2437 size prefix, except for instructions that will ignore this
2439 if (i.suffix != QWORD_MNEM_SUFFIX
2440 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2441 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2442 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2443 || (flag_code == CODE_64BIT
2444 && (i.tm.opcode_modifier & JumpByte))))
2446 unsigned int prefix = DATA_PREFIX_OPCODE;
2448 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2449 prefix = ADDR_PREFIX_OPCODE;
2451 if (!add_prefix (prefix))
2455 /* Set mode64 for an operand. */
2456 if (i.suffix == QWORD_MNEM_SUFFIX
2457 && flag_code == CODE_64BIT
2458 && (i.tm.opcode_modifier & NoRex64) == 0)
2459 i.rex |= REX_MODE64;
2461 /* Size floating point instruction. */
2462 if (i.suffix == LONG_MNEM_SUFFIX)
2463 if (i.tm.opcode_modifier & FloatMF)
2464 i.tm.base_opcode ^= 4;
2471 check_byte_reg (void)
2475 for (op = i.operands; --op >= 0;)
2477 /* If this is an eight bit register, it's OK. If it's the 16 or
2478 32 bit version of an eight bit register, we will just use the
2479 low portion, and that's OK too. */
2480 if (i.types[op] & Reg8)
2483 /* movzx and movsx should not generate this warning. */
2485 && (i.tm.base_opcode == 0xfb7
2486 || i.tm.base_opcode == 0xfb6
2487 || i.tm.base_opcode == 0x63
2488 || i.tm.base_opcode == 0xfbe
2489 || i.tm.base_opcode == 0xfbf))
2492 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2494 /* Prohibit these changes in the 64bit mode, since the
2495 lowering is more complicated. */
2496 if (flag_code == CODE_64BIT
2497 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2499 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2500 i.op[op].regs->reg_name,
2504 #if REGISTER_WARNINGS
2506 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2507 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2508 (i.op[op].regs + (i.types[op] & Reg16
2509 ? REGNAM_AL - REGNAM_AX
2510 : REGNAM_AL - REGNAM_EAX))->reg_name,
2511 i.op[op].regs->reg_name,
2516 /* Any other register is bad. */
2517 if (i.types[op] & (Reg | RegMMX | RegXMM
2519 | Control | Debug | Test
2520 | FloatReg | FloatAcc))
2522 as_bad (_("`%%%s' not allowed with `%s%c'"),
2523 i.op[op].regs->reg_name,
2537 for (op = i.operands; --op >= 0;)
2538 /* Reject eight bit registers, except where the template requires
2539 them. (eg. movzb) */
2540 if ((i.types[op] & Reg8) != 0
2541 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2543 as_bad (_("`%%%s' not allowed with `%s%c'"),
2544 i.op[op].regs->reg_name,
2549 /* Warn if the e prefix on a general reg is missing. */
2550 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2551 && (i.types[op] & Reg16) != 0
2552 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2554 /* Prohibit these changes in the 64bit mode, since the
2555 lowering is more complicated. */
2556 if (flag_code == CODE_64BIT)
2558 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2559 i.op[op].regs->reg_name,
2563 #if REGISTER_WARNINGS
2565 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2566 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2567 i.op[op].regs->reg_name,
2571 /* Warn if the r prefix on a general reg is missing. */
2572 else if ((i.types[op] & Reg64) != 0
2573 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2575 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2576 i.op[op].regs->reg_name,
2588 for (op = i.operands; --op >= 0; )
2589 /* Reject eight bit registers, except where the template requires
2590 them. (eg. movzb) */
2591 if ((i.types[op] & Reg8) != 0
2592 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2594 as_bad (_("`%%%s' not allowed with `%s%c'"),
2595 i.op[op].regs->reg_name,
2600 /* Warn if the e prefix on a general reg is missing. */
2601 else if (((i.types[op] & Reg16) != 0
2602 || (i.types[op] & Reg32) != 0)
2603 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2605 /* Prohibit these changes in the 64bit mode, since the
2606 lowering is more complicated. */
2607 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2608 i.op[op].regs->reg_name,
2619 for (op = i.operands; --op >= 0;)
2620 /* Reject eight bit registers, except where the template requires
2621 them. (eg. movzb) */
2622 if ((i.types[op] & Reg8) != 0
2623 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2625 as_bad (_("`%%%s' not allowed with `%s%c'"),
2626 i.op[op].regs->reg_name,
2631 /* Warn if the e prefix on a general reg is present. */
2632 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2633 && (i.types[op] & Reg32) != 0
2634 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2636 /* Prohibit these changes in the 64bit mode, since the
2637 lowering is more complicated. */
2638 if (flag_code == CODE_64BIT)
2640 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2641 i.op[op].regs->reg_name,
2646 #if REGISTER_WARNINGS
2647 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2648 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2649 i.op[op].regs->reg_name,
2659 unsigned int overlap0, overlap1, overlap2;
2661 overlap0 = i.types[0] & i.tm.operand_types[0];
2662 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2663 && overlap0 != Imm8 && overlap0 != Imm8S
2664 && overlap0 != Imm16 && overlap0 != Imm32S
2665 && overlap0 != Imm32 && overlap0 != Imm64)
2669 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2671 : (i.suffix == WORD_MNEM_SUFFIX
2673 : (i.suffix == QWORD_MNEM_SUFFIX
2677 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2678 || overlap0 == (Imm16 | Imm32)
2679 || overlap0 == (Imm16 | Imm32S))
2681 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2684 if (overlap0 != Imm8 && overlap0 != Imm8S
2685 && overlap0 != Imm16 && overlap0 != Imm32S
2686 && overlap0 != Imm32 && overlap0 != Imm64)
2688 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2692 i.types[0] = overlap0;
2694 overlap1 = i.types[1] & i.tm.operand_types[1];
2695 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2696 && overlap1 != Imm8 && overlap1 != Imm8S
2697 && overlap1 != Imm16 && overlap1 != Imm32S
2698 && overlap1 != Imm32 && overlap1 != Imm64)
2702 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2704 : (i.suffix == WORD_MNEM_SUFFIX
2706 : (i.suffix == QWORD_MNEM_SUFFIX
2710 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2711 || overlap1 == (Imm16 | Imm32)
2712 || overlap1 == (Imm16 | Imm32S))
2714 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2717 if (overlap1 != Imm8 && overlap1 != Imm8S
2718 && overlap1 != Imm16 && overlap1 != Imm32S
2719 && overlap1 != Imm32 && overlap1 != Imm64)
2721 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2725 i.types[1] = overlap1;
2727 overlap2 = i.types[2] & i.tm.operand_types[2];
2728 assert ((overlap2 & Imm) == 0);
2729 i.types[2] = overlap2;
2737 /* Default segment register this instruction will use for memory
2738 accesses. 0 means unknown. This is only for optimizing out
2739 unnecessary segment overrides. */
2740 const seg_entry *default_seg = 0;
2742 /* The imul $imm, %reg instruction is converted into
2743 imul $imm, %reg, %reg, and the clr %reg instruction
2744 is converted into xor %reg, %reg. */
2745 if (i.tm.opcode_modifier & regKludge)
2747 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2748 /* Pretend we saw the extra register operand. */
2749 assert (i.op[first_reg_op + 1].regs == 0);
2750 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2751 i.types[first_reg_op + 1] = i.types[first_reg_op];
2755 if (i.tm.opcode_modifier & ShortForm)
2757 /* The register or float register operand is in operand 0 or 1. */
2758 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2759 /* Register goes in low 3 bits of opcode. */
2760 i.tm.base_opcode |= i.op[op].regs->reg_num;
2761 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2763 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2765 /* Warn about some common errors, but press on regardless.
2766 The first case can be generated by gcc (<= 2.8.1). */
2767 if (i.operands == 2)
2769 /* Reversed arguments on faddp, fsubp, etc. */
2770 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2771 i.op[1].regs->reg_name,
2772 i.op[0].regs->reg_name);
2776 /* Extraneous `l' suffix on fp insn. */
2777 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2778 i.op[0].regs->reg_name);
2782 else if (i.tm.opcode_modifier & Modrm)
2784 /* The opcode is completed (modulo i.tm.extension_opcode which
2785 must be put into the modrm byte). Now, we make the modrm and
2786 index base bytes based on all the info we've collected. */
2788 default_seg = build_modrm_byte ();
2790 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2792 if (i.tm.base_opcode == POP_SEG_SHORT
2793 && i.op[0].regs->reg_num == 1)
2795 as_bad (_("you can't `pop %%cs'"));
2798 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2799 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2802 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2806 else if ((i.tm.opcode_modifier & IsString) != 0)
2808 /* For the string instructions that allow a segment override
2809 on one of their operands, the default segment is ds. */
2813 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2814 as_warn (_("segment override on `lea' is ineffectual"));
2816 /* If a segment was explicitly specified, and the specified segment
2817 is not the default, use an opcode prefix to select it. If we
2818 never figured out what the default segment is, then default_seg
2819 will be zero at this point, and the specified segment prefix will
2821 if ((i.seg[0]) && (i.seg[0] != default_seg))
2823 if (!add_prefix (i.seg[0]->seg_prefix))
2829 static const seg_entry *
2832 const seg_entry *default_seg = 0;
2834 /* i.reg_operands MUST be the number of real register operands;
2835 implicit registers do not count. */
2836 if (i.reg_operands == 2)
2838 unsigned int source, dest;
2839 source = ((i.types[0]
2840 & (Reg | RegMMX | RegXMM
2842 | Control | Debug | Test))
2847 /* One of the register operands will be encoded in the i.tm.reg
2848 field, the other in the combined i.tm.mode and i.tm.regmem
2849 fields. If no form of this instruction supports a memory
2850 destination operand, then we assume the source operand may
2851 sometimes be a memory operand and so we need to store the
2852 destination in the i.rm.reg field. */
2853 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2855 i.rm.reg = i.op[dest].regs->reg_num;
2856 i.rm.regmem = i.op[source].regs->reg_num;
2857 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2859 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2864 i.rm.reg = i.op[source].regs->reg_num;
2865 i.rm.regmem = i.op[dest].regs->reg_num;
2866 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2868 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2873 { /* If it's not 2 reg operands... */
2876 unsigned int fake_zero_displacement = 0;
2877 unsigned int op = ((i.types[0] & AnyMem)
2879 : (i.types[1] & AnyMem) ? 1 : 2);
2883 if (i.base_reg == 0)
2886 if (!i.disp_operands)
2887 fake_zero_displacement = 1;
2888 if (i.index_reg == 0)
2890 /* Operand is just <disp> */
2891 if (flag_code == CODE_64BIT)
2893 /* 64bit mode overwrites the 32bit absolute
2894 addressing by RIP relative addressing and
2895 absolute addressing is encoded by one of the
2896 redundant SIB forms. */
2897 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2898 i.sib.base = NO_BASE_REGISTER;
2899 i.sib.index = NO_INDEX_REGISTER;
2900 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2902 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2904 i.rm.regmem = NO_BASE_REGISTER_16;
2905 i.types[op] = Disp16;
2909 i.rm.regmem = NO_BASE_REGISTER;
2910 i.types[op] = Disp32;
2913 else /* !i.base_reg && i.index_reg */
2915 i.sib.index = i.index_reg->reg_num;
2916 i.sib.base = NO_BASE_REGISTER;
2917 i.sib.scale = i.log2_scale_factor;
2918 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2919 i.types[op] &= ~Disp;
2920 if (flag_code != CODE_64BIT)
2921 i.types[op] |= Disp32; /* Must be 32 bit */
2923 i.types[op] |= Disp32S;
2924 if ((i.index_reg->reg_flags & RegRex) != 0)
2928 /* RIP addressing for 64bit mode. */
2929 else if (i.base_reg->reg_type == BaseIndex)
2931 i.rm.regmem = NO_BASE_REGISTER;
2932 i.types[op] &= ~ Disp;
2933 i.types[op] |= Disp32S;
2934 i.flags[op] = Operand_PCrel;
2935 if (! i.disp_operands)
2936 fake_zero_displacement = 1;
2938 else if (i.base_reg->reg_type & Reg16)
2940 switch (i.base_reg->reg_num)
2943 if (i.index_reg == 0)
2945 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2946 i.rm.regmem = i.index_reg->reg_num - 6;
2950 if (i.index_reg == 0)
2953 if ((i.types[op] & Disp) == 0)
2955 /* fake (%bp) into 0(%bp) */
2956 i.types[op] |= Disp8;
2957 fake_zero_displacement = 1;
2960 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2961 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2963 default: /* (%si) -> 4 or (%di) -> 5 */
2964 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2966 i.rm.mode = mode_from_disp_size (i.types[op]);
2968 else /* i.base_reg and 32/64 bit mode */
2970 if (flag_code == CODE_64BIT
2971 && (i.types[op] & Disp))
2972 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
2974 i.rm.regmem = i.base_reg->reg_num;
2975 if ((i.base_reg->reg_flags & RegRex) != 0)
2977 i.sib.base = i.base_reg->reg_num;
2978 /* x86-64 ignores REX prefix bit here to avoid decoder
2980 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2983 if (i.disp_operands == 0)
2985 fake_zero_displacement = 1;
2986 i.types[op] |= Disp8;
2989 else if (i.base_reg->reg_num == ESP_REG_NUM)
2993 i.sib.scale = i.log2_scale_factor;
2994 if (i.index_reg == 0)
2996 /* <disp>(%esp) becomes two byte modrm with no index
2997 register. We've already stored the code for esp
2998 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2999 Any base register besides %esp will not use the
3000 extra modrm byte. */
3001 i.sib.index = NO_INDEX_REGISTER;
3002 #if !SCALE1_WHEN_NO_INDEX
3003 /* Another case where we force the second modrm byte. */
3004 if (i.log2_scale_factor)
3005 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3010 i.sib.index = i.index_reg->reg_num;
3011 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3012 if ((i.index_reg->reg_flags & RegRex) != 0)
3015 i.rm.mode = mode_from_disp_size (i.types[op]);
3018 if (fake_zero_displacement)
3020 /* Fakes a zero displacement assuming that i.types[op]
3021 holds the correct displacement size. */
3024 assert (i.op[op].disps == 0);
3025 exp = &disp_expressions[i.disp_operands++];
3026 i.op[op].disps = exp;
3027 exp->X_op = O_constant;
3028 exp->X_add_number = 0;
3029 exp->X_add_symbol = (symbolS *) 0;
3030 exp->X_op_symbol = (symbolS *) 0;
3034 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3035 (if any) based on i.tm.extension_opcode. Again, we must be
3036 careful to make sure that segment/control/debug/test/MMX
3037 registers are coded into the i.rm.reg field. */
3042 & (Reg | RegMMX | RegXMM
3044 | Control | Debug | Test))
3047 & (Reg | RegMMX | RegXMM
3049 | Control | Debug | Test))
3052 /* If there is an extension opcode to put here, the register
3053 number must be put into the regmem field. */
3054 if (i.tm.extension_opcode != None)
3056 i.rm.regmem = i.op[op].regs->reg_num;
3057 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3062 i.rm.reg = i.op[op].regs->reg_num;
3063 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3067 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3068 must set it to 3 to indicate this is a register operand
3069 in the regmem field. */
3070 if (!i.mem_operands)
3074 /* Fill in i.rm.reg field with extension opcode (if any). */
3075 if (i.tm.extension_opcode != None)
3076 i.rm.reg = i.tm.extension_opcode;
3087 relax_substateT subtype;
3092 if (flag_code == CODE_16BIT)
3096 if (i.prefix[DATA_PREFIX] != 0)
3102 /* Pentium4 branch hints. */
3103 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3104 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3109 if (i.prefix[REX_PREFIX] != 0)
3115 if (i.prefixes != 0 && !intel_syntax)
3116 as_warn (_("skipping prefixes on this instruction"));
3118 /* It's always a symbol; End frag & setup for relax.
3119 Make sure there is enough room in this frag for the largest
3120 instruction we may generate in md_convert_frag. This is 2
3121 bytes for the opcode and room for the prefix and largest
3123 frag_grow (prefix + 2 + 4);
3124 /* Prefix and 1 opcode byte go in fr_fix. */
3125 p = frag_more (prefix + 1);
3126 if (i.prefix[DATA_PREFIX] != 0)
3127 *p++ = DATA_PREFIX_OPCODE;
3128 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3129 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3130 *p++ = i.prefix[SEG_PREFIX];
3131 if (i.prefix[REX_PREFIX] != 0)
3132 *p++ = i.prefix[REX_PREFIX];
3133 *p = i.tm.base_opcode;
3135 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3136 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3137 else if ((cpu_arch_flags & Cpu386) != 0)
3138 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3140 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3143 sym = i.op[0].disps->X_add_symbol;
3144 off = i.op[0].disps->X_add_number;
3146 if (i.op[0].disps->X_op != O_constant
3147 && i.op[0].disps->X_op != O_symbol)
3149 /* Handle complex expressions. */
3150 sym = make_expr_symbol (i.op[0].disps);
3154 /* 1 possible extra opcode + 4 byte displacement go in var part.
3155 Pass reloc in fr_var. */
3156 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3166 if (i.tm.opcode_modifier & JumpByte)
3168 /* This is a loop or jecxz type instruction. */
3170 if (i.prefix[ADDR_PREFIX] != 0)
3172 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3175 /* Pentium4 branch hints. */
3176 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3177 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3179 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3188 if (flag_code == CODE_16BIT)
3191 if (i.prefix[DATA_PREFIX] != 0)
3193 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3203 if (i.prefix[REX_PREFIX] != 0)
3205 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3209 if (i.prefixes != 0 && !intel_syntax)
3210 as_warn (_("skipping prefixes on this instruction"));
3212 p = frag_more (1 + size);
3213 *p++ = i.tm.base_opcode;
3215 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3216 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3218 /* All jumps handled here are signed, but don't use a signed limit
3219 check for 32 and 16 bit jumps as we want to allow wrap around at
3220 4G and 64k respectively. */
3222 fixP->fx_signed = 1;
3226 output_interseg_jump ()
3234 if (flag_code == CODE_16BIT)
3238 if (i.prefix[DATA_PREFIX] != 0)
3244 if (i.prefix[REX_PREFIX] != 0)
3254 if (i.prefixes != 0 && !intel_syntax)
3255 as_warn (_("skipping prefixes on this instruction"));
3257 /* 1 opcode; 2 segment; offset */
3258 p = frag_more (prefix + 1 + 2 + size);
3260 if (i.prefix[DATA_PREFIX] != 0)
3261 *p++ = DATA_PREFIX_OPCODE;
3263 if (i.prefix[REX_PREFIX] != 0)
3264 *p++ = i.prefix[REX_PREFIX];
3266 *p++ = i.tm.base_opcode;
3267 if (i.op[1].imms->X_op == O_constant)
3269 offsetT n = i.op[1].imms->X_add_number;
3272 && !fits_in_unsigned_word (n)
3273 && !fits_in_signed_word (n))
3275 as_bad (_("16-bit jump out of range"));
3278 md_number_to_chars (p, n, size);
3281 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3282 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3283 if (i.op[0].imms->X_op != O_constant)
3284 as_bad (_("can't handle non absolute segment in `%s'"),
3286 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3292 fragS *insn_start_frag;
3293 offsetT insn_start_off;
3295 /* Tie dwarf2 debug info to the address at the start of the insn.
3296 We can't do this after the insn has been output as the current
3297 frag may have been closed off. eg. by frag_var. */
3298 dwarf2_emit_insn (0);
3300 insn_start_frag = frag_now;
3301 insn_start_off = frag_now_fix ();
3304 if (i.tm.opcode_modifier & Jump)
3306 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3308 else if (i.tm.opcode_modifier & JumpInterSegment)
3309 output_interseg_jump ();
3312 /* Output normal instructions here. */
3316 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3317 have 3 bytes. We may use one more higher byte to specify a prefix
3318 the instruction requires. */
3319 if ((i.tm.cpu_flags & CpuPadLock) != 0
3320 && (i.tm.base_opcode & 0xff000000) != 0)
3322 unsigned int prefix;
3323 prefix = (i.tm.base_opcode >> 24) & 0xff;
3325 if (prefix != REPE_PREFIX_OPCODE
3326 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3327 add_prefix (prefix);
3330 if ((i.tm.cpu_flags & CpuPadLock) == 0
3331 && (i.tm.base_opcode & 0xff0000) != 0)
3332 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3334 /* The prefix bytes. */
3336 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3342 md_number_to_chars (p, (valueT) *q, 1);
3346 /* Now the opcode; be careful about word order here! */
3347 if (fits_in_unsigned_byte (i.tm.base_opcode))
3349 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3353 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3356 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3361 /* Put out high byte first: can't use md_number_to_chars! */
3362 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3363 *p = i.tm.base_opcode & 0xff;
3366 /* Now the modrm byte and sib byte (if present). */
3367 if (i.tm.opcode_modifier & Modrm)
3370 md_number_to_chars (p,
3371 (valueT) (i.rm.regmem << 0
3375 /* If i.rm.regmem == ESP (4)
3376 && i.rm.mode != (Register mode)
3378 ==> need second modrm byte. */
3379 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3381 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3384 md_number_to_chars (p,
3385 (valueT) (i.sib.base << 0
3387 | i.sib.scale << 6),
3392 if (i.disp_operands)
3393 output_disp (insn_start_frag, insn_start_off);
3396 output_imm (insn_start_frag, insn_start_off);
3404 #endif /* DEBUG386 */
3408 output_disp (insn_start_frag, insn_start_off)
3409 fragS *insn_start_frag;
3410 offsetT insn_start_off;
3415 for (n = 0; n < i.operands; n++)
3417 if (i.types[n] & Disp)
3419 if (i.op[n].disps->X_op == O_constant)
3425 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3428 if (i.types[n] & Disp8)
3430 if (i.types[n] & Disp64)
3433 val = offset_in_range (i.op[n].disps->X_add_number,
3435 p = frag_more (size);
3436 md_number_to_chars (p, val, size);
3440 enum bfd_reloc_code_real reloc_type;
3443 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3445 /* The PC relative address is computed relative
3446 to the instruction boundary, so in case immediate
3447 fields follows, we need to adjust the value. */
3448 if (pcrel && i.imm_operands)
3453 for (n1 = 0; n1 < i.operands; n1++)
3454 if (i.types[n1] & Imm)
3456 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3459 if (i.types[n1] & (Imm8 | Imm8S))
3461 if (i.types[n1] & Imm64)
3466 /* We should find the immediate. */
3467 if (n1 == i.operands)
3469 i.op[n].disps->X_add_number -= imm_size;
3472 if (i.types[n] & Disp32S)
3475 if (i.types[n] & (Disp16 | Disp64))
3478 if (i.types[n] & Disp64)
3482 p = frag_more (size);
3483 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3484 if (reloc_type == BFD_RELOC_32
3486 && GOT_symbol == i.op[n].disps->X_add_symbol
3487 && (i.op[n].disps->X_op == O_symbol
3488 || (i.op[n].disps->X_op == O_add
3489 && ((symbol_get_value_expression
3490 (i.op[n].disps->X_op_symbol)->X_op)
3495 if (insn_start_frag == frag_now)
3496 add = (p - frag_now->fr_literal) - insn_start_off;
3501 add = insn_start_frag->fr_fix - insn_start_off;
3502 for (fr = insn_start_frag->fr_next;
3503 fr && fr != frag_now; fr = fr->fr_next)
3505 add += p - frag_now->fr_literal;
3508 /* We don't support dynamic linking on x86-64 yet. */
3509 if (flag_code == CODE_64BIT)
3511 reloc_type = BFD_RELOC_386_GOTPC;
3512 i.op[n].disps->X_add_number += add;
3514 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3515 i.op[n].disps, pcrel, reloc_type);
3522 output_imm (insn_start_frag, insn_start_off)
3523 fragS *insn_start_frag;
3524 offsetT insn_start_off;
3529 for (n = 0; n < i.operands; n++)
3531 if (i.types[n] & Imm)
3533 if (i.op[n].imms->X_op == O_constant)
3539 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3542 if (i.types[n] & (Imm8 | Imm8S))
3544 else if (i.types[n] & Imm64)
3547 val = offset_in_range (i.op[n].imms->X_add_number,
3549 p = frag_more (size);
3550 md_number_to_chars (p, val, size);
3554 /* Not absolute_section.
3555 Need a 32-bit fixup (don't support 8bit
3556 non-absolute imms). Try to support other
3558 enum bfd_reloc_code_real reloc_type;
3562 if ((i.types[n] & (Imm32S))
3563 && i.suffix == QWORD_MNEM_SUFFIX)
3565 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3568 if (i.types[n] & (Imm8 | Imm8S))
3570 if (i.types[n] & Imm64)
3574 p = frag_more (size);
3575 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3577 /* This is tough to explain. We end up with this one if we
3578 * have operands that look like
3579 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3580 * obtain the absolute address of the GOT, and it is strongly
3581 * preferable from a performance point of view to avoid using
3582 * a runtime relocation for this. The actual sequence of
3583 * instructions often look something like:
3588 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3590 * The call and pop essentially return the absolute address
3591 * of the label .L66 and store it in %ebx. The linker itself
3592 * will ultimately change the first operand of the addl so
3593 * that %ebx points to the GOT, but to keep things simple, the
3594 * .o file must have this operand set so that it generates not
3595 * the absolute address of .L66, but the absolute address of
3596 * itself. This allows the linker itself simply treat a GOTPC
3597 * relocation as asking for a pcrel offset to the GOT to be
3598 * added in, and the addend of the relocation is stored in the
3599 * operand field for the instruction itself.
3601 * Our job here is to fix the operand so that it would add
3602 * the correct offset so that %ebx would point to itself. The
3603 * thing that is tricky is that .-.L66 will point to the
3604 * beginning of the instruction, so we need to further modify
3605 * the operand so that it will point to itself. There are
3606 * other cases where you have something like:
3608 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3610 * and here no correction would be required. Internally in
3611 * the assembler we treat operands of this form as not being
3612 * pcrel since the '.' is explicitly mentioned, and I wonder
3613 * whether it would simplify matters to do it this way. Who
3614 * knows. In earlier versions of the PIC patches, the
3615 * pcrel_adjust field was used to store the correction, but
3616 * since the expression is not pcrel, I felt it would be
3617 * confusing to do it this way. */
3619 if (reloc_type == BFD_RELOC_32
3621 && GOT_symbol == i.op[n].imms->X_add_symbol
3622 && (i.op[n].imms->X_op == O_symbol
3623 || (i.op[n].imms->X_op == O_add
3624 && ((symbol_get_value_expression
3625 (i.op[n].imms->X_op_symbol)->X_op)
3630 if (insn_start_frag == frag_now)
3631 add = (p - frag_now->fr_literal) - insn_start_off;
3636 add = insn_start_frag->fr_fix - insn_start_off;
3637 for (fr = insn_start_frag->fr_next;
3638 fr && fr != frag_now; fr = fr->fr_next)
3640 add += p - frag_now->fr_literal;
3643 /* We don't support dynamic linking on x86-64 yet. */
3644 if (flag_code == CODE_64BIT)
3646 reloc_type = BFD_RELOC_386_GOTPC;
3647 i.op[n].imms->X_add_number += add;
3649 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3650 i.op[n].imms, 0, reloc_type);
3657 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
3659 /* Parse operands of the form
3660 <symbol>@GOTOFF+<nnn>
3661 and similar .plt or .got references.
3663 If we find one, set up the correct relocation in RELOC and copy the
3664 input string, minus the `@GOTOFF' into a malloc'd buffer for
3665 parsing by the calling routine. Return this buffer, and if ADJUST
3666 is non-null set it to the length of the string we removed from the
3667 input line. Otherwise return NULL. */
3669 lex_got (reloc, adjust)
3670 enum bfd_reloc_code_real *reloc;
3673 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3674 static const struct {
3676 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3678 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3679 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3680 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3681 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
3682 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3683 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3684 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3685 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
3686 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3687 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
3688 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3689 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
3690 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3695 for (cp = input_line_pointer; *cp != '@'; cp++)
3696 if (is_end_of_line[(unsigned char) *cp])
3699 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3703 len = strlen (gotrel[j].str);
3704 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3706 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3709 char *tmpbuf, *past_reloc;
3711 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3715 if (GOT_symbol == NULL)
3716 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3718 /* Replace the relocation token with ' ', so that
3719 errors like foo@GOTOFF1 will be detected. */
3721 /* The length of the first part of our input line. */
3722 first = cp - input_line_pointer;
3724 /* The second part goes from after the reloc token until
3725 (and including) an end_of_line char. Don't use strlen
3726 here as the end_of_line char may not be a NUL. */
3727 past_reloc = cp + 1 + len;
3728 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3730 second = cp - past_reloc;
3732 /* Allocate and copy string. The trailing NUL shouldn't
3733 be necessary, but be safe. */
3734 tmpbuf = xmalloc (first + second + 2);
3735 memcpy (tmpbuf, input_line_pointer, first);
3736 tmpbuf[first] = ' ';
3737 memcpy (tmpbuf + first + 1, past_reloc, second);
3738 tmpbuf[first + second + 1] = '\0';
3742 as_bad (_("@%s reloc is not supported in %s bit mode"),
3743 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3748 /* Might be a symbol version string. Don't as_bad here. */
3752 /* x86_cons_fix_new is called via the expression parsing code when a
3753 reloc is needed. We use this hook to get the correct .got reloc. */
3754 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3757 x86_cons_fix_new (frag, off, len, exp)
3763 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
3764 got_reloc = NO_RELOC;
3765 fix_new_exp (frag, off, len, exp, 0, r);
3769 x86_cons (exp, size)
3775 /* Handle @GOTOFF and the like in an expression. */
3777 char *gotfree_input_line;
3780 save = input_line_pointer;
3781 gotfree_input_line = lex_got (&got_reloc, &adjust);
3782 if (gotfree_input_line)
3783 input_line_pointer = gotfree_input_line;
3787 if (gotfree_input_line)
3789 /* expression () has merrily parsed up to the end of line,
3790 or a comma - in the wrong buffer. Transfer how far
3791 input_line_pointer has moved to the right buffer. */
3792 input_line_pointer = (save
3793 + (input_line_pointer - gotfree_input_line)
3795 free (gotfree_input_line);
3806 x86_pe_cons_fix_new (frag, off, len, exp)
3812 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3814 if (exp->X_op == O_secrel)
3816 exp->X_op = O_symbol;
3817 r = BFD_RELOC_32_SECREL;
3820 fix_new_exp (frag, off, len, exp, 0, r);
3824 pe_directive_secrel (dummy)
3825 int dummy ATTRIBUTE_UNUSED;
3832 if (exp.X_op == O_symbol)
3833 exp.X_op = O_secrel;
3835 emit_expr (&exp, 4);
3837 while (*input_line_pointer++ == ',');
3839 input_line_pointer--;
3840 demand_empty_rest_of_line ();
3845 static int i386_immediate PARAMS ((char *));
3848 i386_immediate (imm_start)
3851 char *save_input_line_pointer;
3853 char *gotfree_input_line;
3858 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3860 as_bad (_("only 1 or 2 immediate operands are allowed"));
3864 exp = &im_expressions[i.imm_operands++];
3865 i.op[this_operand].imms = exp;
3867 if (is_space_char (*imm_start))
3870 save_input_line_pointer = input_line_pointer;
3871 input_line_pointer = imm_start;
3874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3875 if (gotfree_input_line)
3876 input_line_pointer = gotfree_input_line;
3879 exp_seg = expression (exp);
3882 if (*input_line_pointer)
3883 as_bad (_("junk `%s' after expression"), input_line_pointer);
3885 input_line_pointer = save_input_line_pointer;
3887 if (gotfree_input_line)
3888 free (gotfree_input_line);
3891 if (exp->X_op == O_absent || exp->X_op == O_big)
3893 /* Missing or bad expr becomes absolute 0. */
3894 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3896 exp->X_op = O_constant;
3897 exp->X_add_number = 0;
3898 exp->X_add_symbol = (symbolS *) 0;
3899 exp->X_op_symbol = (symbolS *) 0;
3901 else if (exp->X_op == O_constant)
3903 /* Size it properly later. */
3904 i.types[this_operand] |= Imm64;
3905 /* If BFD64, sign extend val. */
3906 if (!use_rela_relocations)
3907 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3908 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3910 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3911 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3912 && exp_seg != absolute_section
3913 && exp_seg != text_section
3914 && exp_seg != data_section
3915 && exp_seg != bss_section
3916 && exp_seg != undefined_section
3917 && !bfd_is_com_section (exp_seg))
3919 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3925 /* This is an address. The size of the address will be
3926 determined later, depending on destination register,
3927 suffix, or the default for the section. */
3928 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3934 static char *i386_scale PARAMS ((char *));
3941 char *save = input_line_pointer;
3943 input_line_pointer = scale;
3944 val = get_absolute_expression ();
3949 i.log2_scale_factor = 0;
3952 i.log2_scale_factor = 1;
3955 i.log2_scale_factor = 2;
3958 i.log2_scale_factor = 3;
3961 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3963 input_line_pointer = save;
3966 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3968 as_warn (_("scale factor of %d without an index register"),
3969 1 << i.log2_scale_factor);
3970 #if SCALE1_WHEN_NO_INDEX
3971 i.log2_scale_factor = 0;
3974 scale = input_line_pointer;
3975 input_line_pointer = save;
3979 static int i386_displacement PARAMS ((char *, char *));
3982 i386_displacement (disp_start, disp_end)
3988 char *save_input_line_pointer;
3990 char *gotfree_input_line;
3992 int bigdisp = Disp32;
3994 if (flag_code == CODE_64BIT)
3996 if (i.prefix[ADDR_PREFIX] == 0)
3999 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4001 i.types[this_operand] |= bigdisp;
4003 exp = &disp_expressions[i.disp_operands];
4004 i.op[this_operand].disps = exp;
4006 save_input_line_pointer = input_line_pointer;
4007 input_line_pointer = disp_start;
4008 END_STRING_AND_SAVE (disp_end);
4010 #ifndef GCC_ASM_O_HACK
4011 #define GCC_ASM_O_HACK 0
4014 END_STRING_AND_SAVE (disp_end + 1);
4015 if ((i.types[this_operand] & BaseIndex) != 0
4016 && displacement_string_end[-1] == '+')
4018 /* This hack is to avoid a warning when using the "o"
4019 constraint within gcc asm statements.
4022 #define _set_tssldt_desc(n,addr,limit,type) \
4023 __asm__ __volatile__ ( \
4025 "movw %w1,2+%0\n\t" \
4027 "movb %b1,4+%0\n\t" \
4028 "movb %4,5+%0\n\t" \
4029 "movb $0,6+%0\n\t" \
4030 "movb %h1,7+%0\n\t" \
4032 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4034 This works great except that the output assembler ends
4035 up looking a bit weird if it turns out that there is
4036 no offset. You end up producing code that looks like:
4049 So here we provide the missing zero. */
4051 *displacement_string_end = '0';
4055 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4056 if (gotfree_input_line)
4057 input_line_pointer = gotfree_input_line;
4060 exp_seg = expression (exp);
4063 if (*input_line_pointer)
4064 as_bad (_("junk `%s' after expression"), input_line_pointer);
4066 RESTORE_END_STRING (disp_end + 1);
4068 RESTORE_END_STRING (disp_end);
4069 input_line_pointer = save_input_line_pointer;
4071 if (gotfree_input_line)
4072 free (gotfree_input_line);
4075 /* We do this to make sure that the section symbol is in
4076 the symbol table. We will ultimately change the relocation
4077 to be relative to the beginning of the section. */
4078 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4079 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4081 if (exp->X_op != O_symbol)
4083 as_bad (_("bad expression used with @%s"),
4084 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4090 if (S_IS_LOCAL (exp->X_add_symbol)
4091 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4092 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4093 exp->X_op = O_subtract;
4094 exp->X_op_symbol = GOT_symbol;
4095 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4096 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4098 i.reloc[this_operand] = BFD_RELOC_32;
4101 if (exp->X_op == O_absent || exp->X_op == O_big)
4103 /* Missing or bad expr becomes absolute 0. */
4104 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4106 exp->X_op = O_constant;
4107 exp->X_add_number = 0;
4108 exp->X_add_symbol = (symbolS *) 0;
4109 exp->X_op_symbol = (symbolS *) 0;
4112 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4113 if (exp->X_op != O_constant
4114 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4115 && exp_seg != absolute_section
4116 && exp_seg != text_section
4117 && exp_seg != data_section
4118 && exp_seg != bss_section
4119 && exp_seg != undefined_section
4120 && !bfd_is_com_section (exp_seg))
4122 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4126 else if (flag_code == CODE_64BIT)
4127 i.types[this_operand] |= Disp32S | Disp32;
4131 static int i386_index_check PARAMS ((const char *));
4133 /* Make sure the memory operand we've been dealt is valid.
4134 Return 1 on success, 0 on a failure. */
4137 i386_index_check (operand_string)
4138 const char *operand_string;
4141 #if INFER_ADDR_PREFIX
4147 if (flag_code == CODE_64BIT)
4149 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4152 && ((i.base_reg->reg_type & RegXX) == 0)
4153 && (i.base_reg->reg_type != BaseIndex
4156 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4157 != (RegXX | BaseIndex))))
4162 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4166 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4167 != (Reg16 | BaseIndex)))
4169 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4170 != (Reg16 | BaseIndex))
4172 && i.base_reg->reg_num < 6
4173 && i.index_reg->reg_num >= 6
4174 && i.log2_scale_factor == 0))))
4181 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4183 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4184 != (Reg32 | BaseIndex))))
4190 #if INFER_ADDR_PREFIX
4191 if (i.prefix[ADDR_PREFIX] == 0)
4193 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4195 /* Change the size of any displacement too. At most one of
4196 Disp16 or Disp32 is set.
4197 FIXME. There doesn't seem to be any real need for separate
4198 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4199 Removing them would probably clean up the code quite a lot. */
4200 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4201 i.types[this_operand] ^= (Disp16 | Disp32);
4206 as_bad (_("`%s' is not a valid base/index expression"),
4210 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4212 flag_code_names[flag_code]);
4217 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4221 i386_operand (operand_string)
4222 char *operand_string;
4226 char *op_string = operand_string;
4228 if (is_space_char (*op_string))
4231 /* We check for an absolute prefix (differentiating,
4232 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4233 if (*op_string == ABSOLUTE_PREFIX)
4236 if (is_space_char (*op_string))
4238 i.types[this_operand] |= JumpAbsolute;
4241 /* Check if operand is a register. */
4242 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4243 && (r = parse_register (op_string, &end_op)) != NULL)
4245 /* Check for a segment override by searching for ':' after a
4246 segment register. */
4248 if (is_space_char (*op_string))
4250 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4255 i.seg[i.mem_operands] = &es;
4258 i.seg[i.mem_operands] = &cs;
4261 i.seg[i.mem_operands] = &ss;
4264 i.seg[i.mem_operands] = &ds;
4267 i.seg[i.mem_operands] = &fs;
4270 i.seg[i.mem_operands] = &gs;
4274 /* Skip the ':' and whitespace. */
4276 if (is_space_char (*op_string))
4279 if (!is_digit_char (*op_string)
4280 && !is_identifier_char (*op_string)
4281 && *op_string != '('
4282 && *op_string != ABSOLUTE_PREFIX)
4284 as_bad (_("bad memory operand `%s'"), op_string);
4287 /* Handle case of %es:*foo. */
4288 if (*op_string == ABSOLUTE_PREFIX)
4291 if (is_space_char (*op_string))
4293 i.types[this_operand] |= JumpAbsolute;
4295 goto do_memory_reference;
4299 as_bad (_("junk `%s' after register"), op_string);
4302 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4303 i.op[this_operand].regs = r;
4306 else if (*op_string == REGISTER_PREFIX)
4308 as_bad (_("bad register name `%s'"), op_string);
4311 else if (*op_string == IMMEDIATE_PREFIX)
4314 if (i.types[this_operand] & JumpAbsolute)
4316 as_bad (_("immediate operand illegal with absolute jump"));
4319 if (!i386_immediate (op_string))
4322 else if (is_digit_char (*op_string)
4323 || is_identifier_char (*op_string)
4324 || *op_string == '(')
4326 /* This is a memory reference of some sort. */
4329 /* Start and end of displacement string expression (if found). */
4330 char *displacement_string_start;
4331 char *displacement_string_end;
4333 do_memory_reference:
4334 if ((i.mem_operands == 1
4335 && (current_templates->start->opcode_modifier & IsString) == 0)
4336 || i.mem_operands == 2)
4338 as_bad (_("too many memory references for `%s'"),
4339 current_templates->start->name);
4343 /* Check for base index form. We detect the base index form by
4344 looking for an ')' at the end of the operand, searching
4345 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4347 base_string = op_string + strlen (op_string);
4350 if (is_space_char (*base_string))
4353 /* If we only have a displacement, set-up for it to be parsed later. */
4354 displacement_string_start = op_string;
4355 displacement_string_end = base_string + 1;
4357 if (*base_string == ')')
4360 unsigned int parens_balanced = 1;
4361 /* We've already checked that the number of left & right ()'s are
4362 equal, so this loop will not be infinite. */
4366 if (*base_string == ')')
4368 if (*base_string == '(')
4371 while (parens_balanced);
4373 temp_string = base_string;
4375 /* Skip past '(' and whitespace. */
4377 if (is_space_char (*base_string))
4380 if (*base_string == ','
4381 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4382 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4384 displacement_string_end = temp_string;
4386 i.types[this_operand] |= BaseIndex;
4390 base_string = end_op;
4391 if (is_space_char (*base_string))
4395 /* There may be an index reg or scale factor here. */
4396 if (*base_string == ',')
4399 if (is_space_char (*base_string))
4402 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4403 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4405 base_string = end_op;
4406 if (is_space_char (*base_string))
4408 if (*base_string == ',')
4411 if (is_space_char (*base_string))
4414 else if (*base_string != ')')
4416 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4421 else if (*base_string == REGISTER_PREFIX)
4423 as_bad (_("bad register name `%s'"), base_string);
4427 /* Check for scale factor. */
4428 if (*base_string != ')')
4430 char *end_scale = i386_scale (base_string);
4435 base_string = end_scale;
4436 if (is_space_char (*base_string))
4438 if (*base_string != ')')
4440 as_bad (_("expecting `)' after scale factor in `%s'"),
4445 else if (!i.index_reg)
4447 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4452 else if (*base_string != ')')
4454 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4459 else if (*base_string == REGISTER_PREFIX)
4461 as_bad (_("bad register name `%s'"), base_string);
4466 /* If there's an expression beginning the operand, parse it,
4467 assuming displacement_string_start and
4468 displacement_string_end are meaningful. */
4469 if (displacement_string_start != displacement_string_end)
4471 if (!i386_displacement (displacement_string_start,
4472 displacement_string_end))
4476 /* Special case for (%dx) while doing input/output op. */
4478 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4480 && i.log2_scale_factor == 0
4481 && i.seg[i.mem_operands] == 0
4482 && (i.types[this_operand] & Disp) == 0)
4484 i.types[this_operand] = InOutPortReg;
4488 if (i386_index_check (operand_string) == 0)
4494 /* It's not a memory operand; argh! */
4495 as_bad (_("invalid char %s beginning operand %d `%s'"),
4496 output_invalid (*op_string),
4501 return 1; /* Normal return. */
4504 /* md_estimate_size_before_relax()
4506 Called just before relax() for rs_machine_dependent frags. The x86
4507 assembler uses these frags to handle variable size jump
4510 Any symbol that is now undefined will not become defined.
4511 Return the correct fr_subtype in the frag.
4512 Return the initial "guess for variable size of frag" to caller.
4513 The guess is actually the growth beyond the fixed part. Whatever
4514 we do to grow the fixed or variable part contributes to our
4518 md_estimate_size_before_relax (fragP, segment)
4522 /* We've already got fragP->fr_subtype right; all we have to do is
4523 check for un-relaxable symbols. On an ELF system, we can't relax
4524 an externally visible symbol, because it may be overridden by a
4526 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4528 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4529 && (S_IS_EXTERNAL (fragP->fr_symbol)
4530 || S_IS_WEAK (fragP->fr_symbol)))
4534 /* Symbol is undefined in this segment, or we need to keep a
4535 reloc so that weak symbols can be overridden. */
4536 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4537 enum bfd_reloc_code_real reloc_type;
4538 unsigned char *opcode;
4541 if (fragP->fr_var != NO_RELOC)
4542 reloc_type = fragP->fr_var;
4544 reloc_type = BFD_RELOC_16_PCREL;
4546 reloc_type = BFD_RELOC_32_PCREL;
4548 old_fr_fix = fragP->fr_fix;
4549 opcode = (unsigned char *) fragP->fr_opcode;
4551 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4554 /* Make jmp (0xeb) a (d)word displacement jump. */
4556 fragP->fr_fix += size;
4557 fix_new (fragP, old_fr_fix, size,
4559 fragP->fr_offset, 1,
4565 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4567 /* Negate the condition, and branch past an
4568 unconditional jump. */
4571 /* Insert an unconditional jump. */
4573 /* We added two extra opcode bytes, and have a two byte
4575 fragP->fr_fix += 2 + 2;
4576 fix_new (fragP, old_fr_fix + 2, 2,
4578 fragP->fr_offset, 1,
4585 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4590 fixP = fix_new (fragP, old_fr_fix, 1,
4592 fragP->fr_offset, 1,
4594 fixP->fx_signed = 1;
4598 /* This changes the byte-displacement jump 0x7N
4599 to the (d)word-displacement jump 0x0f,0x8N. */
4600 opcode[1] = opcode[0] + 0x10;
4601 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4602 /* We've added an opcode byte. */
4603 fragP->fr_fix += 1 + size;
4604 fix_new (fragP, old_fr_fix + 1, size,
4606 fragP->fr_offset, 1,
4611 BAD_CASE (fragP->fr_subtype);
4615 return fragP->fr_fix - old_fr_fix;
4618 /* Guess size depending on current relax state. Initially the relax
4619 state will correspond to a short jump and we return 1, because
4620 the variable part of the frag (the branch offset) is one byte
4621 long. However, we can relax a section more than once and in that
4622 case we must either set fr_subtype back to the unrelaxed state,
4623 or return the value for the appropriate branch. */
4624 return md_relax_table[fragP->fr_subtype].rlx_length;
4627 /* Called after relax() is finished.
4629 In: Address of frag.
4630 fr_type == rs_machine_dependent.
4631 fr_subtype is what the address relaxed to.
4633 Out: Any fixSs and constants are set up.
4634 Caller will turn frag into a ".space 0". */
4637 md_convert_frag (abfd, sec, fragP)
4638 bfd *abfd ATTRIBUTE_UNUSED;
4639 segT sec ATTRIBUTE_UNUSED;
4642 unsigned char *opcode;
4643 unsigned char *where_to_put_displacement = NULL;
4644 offsetT target_address;
4645 offsetT opcode_address;
4646 unsigned int extension = 0;
4647 offsetT displacement_from_opcode_start;
4649 opcode = (unsigned char *) fragP->fr_opcode;
4651 /* Address we want to reach in file space. */
4652 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4654 /* Address opcode resides at in file space. */
4655 opcode_address = fragP->fr_address + fragP->fr_fix;
4657 /* Displacement from opcode start to fill into instruction. */
4658 displacement_from_opcode_start = target_address - opcode_address;
4660 if ((fragP->fr_subtype & BIG) == 0)
4662 /* Don't have to change opcode. */
4663 extension = 1; /* 1 opcode + 1 displacement */
4664 where_to_put_displacement = &opcode[1];
4668 if (no_cond_jump_promotion
4669 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4670 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4672 switch (fragP->fr_subtype)
4674 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4675 extension = 4; /* 1 opcode + 4 displacement */
4677 where_to_put_displacement = &opcode[1];
4680 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4681 extension = 2; /* 1 opcode + 2 displacement */
4683 where_to_put_displacement = &opcode[1];
4686 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4687 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4688 extension = 5; /* 2 opcode + 4 displacement */
4689 opcode[1] = opcode[0] + 0x10;
4690 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4691 where_to_put_displacement = &opcode[2];
4694 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4695 extension = 3; /* 2 opcode + 2 displacement */
4696 opcode[1] = opcode[0] + 0x10;
4697 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4698 where_to_put_displacement = &opcode[2];
4701 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4706 where_to_put_displacement = &opcode[3];
4710 BAD_CASE (fragP->fr_subtype);
4715 /* Now put displacement after opcode. */
4716 md_number_to_chars ((char *) where_to_put_displacement,
4717 (valueT) (displacement_from_opcode_start - extension),
4718 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4719 fragP->fr_fix += extension;
4722 /* Size of byte displacement jmp. */
4723 int md_short_jump_size = 2;
4725 /* Size of dword displacement jmp. */
4726 int md_long_jump_size = 5;
4728 /* Size of relocation record. */
4729 const int md_reloc_size = 8;
4732 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4734 addressT from_addr, to_addr;
4735 fragS *frag ATTRIBUTE_UNUSED;
4736 symbolS *to_symbol ATTRIBUTE_UNUSED;
4740 offset = to_addr - (from_addr + 2);
4741 /* Opcode for byte-disp jump. */
4742 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4743 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4747 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4749 addressT from_addr, to_addr;
4750 fragS *frag ATTRIBUTE_UNUSED;
4751 symbolS *to_symbol ATTRIBUTE_UNUSED;
4755 offset = to_addr - (from_addr + 5);
4756 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4757 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4760 /* Apply a fixup (fixS) to segment data, once it has been determined
4761 by our caller that we have all the info we need to fix it up.
4763 On the 386, immediates, displacements, and data pointers are all in
4764 the same (little-endian) format, so we don't need to care about which
4768 md_apply_fix3 (fixP, valP, seg)
4769 /* The fix we're to put in. */
4771 /* Pointer to the value of the bits. */
4773 /* Segment fix is from. */
4774 segT seg ATTRIBUTE_UNUSED;
4776 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4777 valueT value = *valP;
4779 #if !defined (TE_Mach)
4782 switch (fixP->fx_r_type)
4788 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4791 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4794 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4799 if (fixP->fx_addsy != NULL
4800 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4801 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4802 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4803 && !use_rela_relocations)
4805 /* This is a hack. There should be a better way to handle this.
4806 This covers for the fact that bfd_install_relocation will
4807 subtract the current location (for partial_inplace, PC relative
4808 relocations); see more below. */
4810 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4812 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4815 value += fixP->fx_where + fixP->fx_frag->fr_address;
4817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4818 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4820 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
4823 || (symbol_section_p (fixP->fx_addsy)
4824 && sym_seg != absolute_section))
4825 && !generic_force_reloc (fixP))
4827 /* Yes, we add the values in twice. This is because
4828 bfd_install_relocation subtracts them out again. I think
4829 bfd_install_relocation is broken, but I don't dare change
4831 value += fixP->fx_where + fixP->fx_frag->fr_address;
4835 #if defined (OBJ_COFF) && defined (TE_PE)
4836 /* For some reason, the PE format does not store a
4837 section address offset for a PC relative symbol. */
4838 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4839 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4840 || S_IS_WEAK (fixP->fx_addsy)
4843 value += md_pcrel_from (fixP);
4847 /* Fix a few things - the dynamic linker expects certain values here,
4848 and we must not disappoint it. */
4849 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4850 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4852 switch (fixP->fx_r_type)
4854 case BFD_RELOC_386_PLT32:
4855 case BFD_RELOC_X86_64_PLT32:
4856 /* Make the jump instruction point to the address of the operand. At
4857 runtime we merely add the offset to the actual PLT entry. */
4861 case BFD_RELOC_386_TLS_GD:
4862 case BFD_RELOC_386_TLS_LDM:
4863 case BFD_RELOC_386_TLS_IE_32:
4864 case BFD_RELOC_386_TLS_IE:
4865 case BFD_RELOC_386_TLS_GOTIE:
4866 case BFD_RELOC_X86_64_TLSGD:
4867 case BFD_RELOC_X86_64_TLSLD:
4868 case BFD_RELOC_X86_64_GOTTPOFF:
4869 value = 0; /* Fully resolved at runtime. No addend. */
4871 case BFD_RELOC_386_TLS_LE:
4872 case BFD_RELOC_386_TLS_LDO_32:
4873 case BFD_RELOC_386_TLS_LE_32:
4874 case BFD_RELOC_X86_64_DTPOFF32:
4875 case BFD_RELOC_X86_64_TPOFF32:
4876 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4879 case BFD_RELOC_386_GOT32:
4880 case BFD_RELOC_X86_64_GOT32:
4881 value = 0; /* Fully resolved at runtime. No addend. */
4884 case BFD_RELOC_VTABLE_INHERIT:
4885 case BFD_RELOC_VTABLE_ENTRY:
4892 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4894 #endif /* !defined (TE_Mach) */
4896 /* Are we finished with this relocation now? */
4897 if (fixP->fx_addsy == NULL)
4899 else if (use_rela_relocations)
4901 fixP->fx_no_overflow = 1;
4902 /* Remember value for tc_gen_reloc. */
4903 fixP->fx_addnumber = value;
4907 md_number_to_chars (p, value, fixP->fx_size);
4910 #define MAX_LITTLENUMS 6
4912 /* Turn the string pointed to by litP into a floating point constant
4913 of type TYPE, and emit the appropriate bytes. The number of
4914 LITTLENUMS emitted is stored in *SIZEP. An error message is
4915 returned, or NULL on OK. */
4918 md_atof (type, litP, sizeP)
4924 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4925 LITTLENUM_TYPE *wordP;
4947 return _("Bad call to md_atof ()");
4949 t = atof_ieee (input_line_pointer, type, words);
4951 input_line_pointer = t;
4953 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4954 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4955 the bigendian 386. */
4956 for (wordP = words + prec - 1; prec--;)
4958 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4959 litP += sizeof (LITTLENUM_TYPE);
4964 char output_invalid_buf[8];
4971 sprintf (output_invalid_buf, "'%c'", c);
4973 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4974 return output_invalid_buf;
4977 /* REG_STRING starts *before* REGISTER_PREFIX. */
4979 static const reg_entry *
4980 parse_register (reg_string, end_op)
4984 char *s = reg_string;
4986 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4989 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4990 if (*s == REGISTER_PREFIX)
4993 if (is_space_char (*s))
4997 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4999 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5000 return (const reg_entry *) NULL;
5004 /* For naked regs, make sure that we are not dealing with an identifier.
5005 This prevents confusing an identifier like `eax_var' with register
5007 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5008 return (const reg_entry *) NULL;
5012 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5014 /* Handle floating point regs, allowing spaces in the (i) part. */
5015 if (r == i386_regtab /* %st is first entry of table */)
5017 if (is_space_char (*s))
5022 if (is_space_char (*s))
5024 if (*s >= '0' && *s <= '7')
5026 r = &i386_float_regtab[*s - '0'];
5028 if (is_space_char (*s))
5036 /* We have "%st(" then garbage. */
5037 return (const reg_entry *) NULL;
5042 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5043 && flag_code != CODE_64BIT)
5044 return (const reg_entry *) NULL;
5049 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5050 const char *md_shortopts = "kVQ:sqn";
5052 const char *md_shortopts = "qn";
5055 struct option md_longopts[] = {
5056 #define OPTION_32 (OPTION_MD_BASE + 0)
5057 {"32", no_argument, NULL, OPTION_32},
5058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5059 #define OPTION_64 (OPTION_MD_BASE + 1)
5060 {"64", no_argument, NULL, OPTION_64},
5062 {NULL, no_argument, NULL, 0}
5064 size_t md_longopts_size = sizeof (md_longopts);
5067 md_parse_option (c, arg)
5069 char *arg ATTRIBUTE_UNUSED;
5074 optimize_align_code = 0;
5081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5082 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5083 should be emitted or not. FIXME: Not implemented. */
5087 /* -V: SVR4 argument to print version ID. */
5089 print_version_id ();
5092 /* -k: Ignore for FreeBSD compatibility. */
5097 /* -s: On i386 Solaris, this tells the native assembler to use
5098 .stab instead of .stab.excl. We always use .stab anyhow. */
5103 const char **list, **l;
5105 list = bfd_target_list ();
5106 for (l = list; *l != NULL; l++)
5107 if (strcmp (*l, "elf64-x86-64") == 0)
5109 default_arch = "x86_64";
5113 as_fatal (_("No compiled in support for x86_64"));
5120 default_arch = "i386";
5130 md_show_usage (stream)
5133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5134 fprintf (stream, _("\
5136 -V print assembler version number\n\
5138 -n Do not optimize code alignment\n\
5139 -q quieten some warnings\n\
5142 fprintf (stream, _("\
5143 -n Do not optimize code alignment\n\
5144 -q quieten some warnings\n"));
5148 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5149 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5151 /* Pick the target format to use. */
5154 i386_target_format ()
5156 if (!strcmp (default_arch, "x86_64"))
5157 set_code_flag (CODE_64BIT);
5158 else if (!strcmp (default_arch, "i386"))
5159 set_code_flag (CODE_32BIT);
5161 as_fatal (_("Unknown architecture"));
5162 switch (OUTPUT_FLAVOR)
5164 #ifdef OBJ_MAYBE_AOUT
5165 case bfd_target_aout_flavour:
5166 return AOUT_TARGET_FORMAT;
5168 #ifdef OBJ_MAYBE_COFF
5169 case bfd_target_coff_flavour:
5172 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5173 case bfd_target_elf_flavour:
5175 if (flag_code == CODE_64BIT)
5176 use_rela_relocations = 1;
5177 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5186 #endif /* OBJ_MAYBE_ more than one */
5188 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5189 void i386_elf_emit_arch_note ()
5191 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5192 && cpu_arch_name != NULL)
5195 asection *seg = now_seg;
5196 subsegT subseg = now_subseg;
5197 Elf_Internal_Note i_note;
5198 Elf_External_Note e_note;
5199 asection *note_secp;
5202 /* Create the .note section. */
5203 note_secp = subseg_new (".note", 0);
5204 bfd_set_section_flags (stdoutput,
5206 SEC_HAS_CONTENTS | SEC_READONLY);
5208 /* Process the arch string. */
5209 len = strlen (cpu_arch_name);
5211 i_note.namesz = len + 1;
5213 i_note.type = NT_ARCH;
5214 p = frag_more (sizeof (e_note.namesz));
5215 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5216 p = frag_more (sizeof (e_note.descsz));
5217 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5218 p = frag_more (sizeof (e_note.type));
5219 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5220 p = frag_more (len + 1);
5221 strcpy (p, cpu_arch_name);
5223 frag_align (2, 0, 0);
5225 subseg_set (seg, subseg);
5231 md_undefined_symbol (name)
5234 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5235 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5236 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5237 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5241 if (symbol_find (name))
5242 as_bad (_("GOT already in symbol table"));
5243 GOT_symbol = symbol_new (name, undefined_section,
5244 (valueT) 0, &zero_address_frag);
5251 /* Round up a section size to the appropriate boundary. */
5254 md_section_align (segment, size)
5255 segT segment ATTRIBUTE_UNUSED;
5258 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5259 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5261 /* For a.out, force the section size to be aligned. If we don't do
5262 this, BFD will align it for us, but it will not write out the
5263 final bytes of the section. This may be a bug in BFD, but it is
5264 easier to fix it here since that is how the other a.out targets
5268 align = bfd_get_section_alignment (stdoutput, segment);
5269 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5276 /* On the i386, PC-relative offsets are relative to the start of the
5277 next instruction. That is, the address of the offset, plus its
5278 size, since the offset is always the last part of the insn. */
5281 md_pcrel_from (fixP)
5284 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5291 int ignore ATTRIBUTE_UNUSED;
5295 temp = get_absolute_expression ();
5296 subseg_set (bss_section, (subsegT) temp);
5297 demand_empty_rest_of_line ();
5303 i386_validate_fix (fixp)
5306 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5308 /* GOTOFF relocation are nonsense in 64bit mode. */
5309 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5311 if (flag_code != CODE_64BIT)
5313 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5317 if (flag_code == CODE_64BIT)
5319 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5326 tc_gen_reloc (section, fixp)
5327 asection *section ATTRIBUTE_UNUSED;
5331 bfd_reloc_code_real_type code;
5333 switch (fixp->fx_r_type)
5335 case BFD_RELOC_X86_64_PLT32:
5336 case BFD_RELOC_X86_64_GOT32:
5337 case BFD_RELOC_X86_64_GOTPCREL:
5338 case BFD_RELOC_386_PLT32:
5339 case BFD_RELOC_386_GOT32:
5340 case BFD_RELOC_386_GOTOFF:
5341 case BFD_RELOC_386_GOTPC:
5342 case BFD_RELOC_386_TLS_GD:
5343 case BFD_RELOC_386_TLS_LDM:
5344 case BFD_RELOC_386_TLS_LDO_32:
5345 case BFD_RELOC_386_TLS_IE_32:
5346 case BFD_RELOC_386_TLS_IE:
5347 case BFD_RELOC_386_TLS_GOTIE:
5348 case BFD_RELOC_386_TLS_LE_32:
5349 case BFD_RELOC_386_TLS_LE:
5350 case BFD_RELOC_X86_64_32S:
5351 case BFD_RELOC_X86_64_TLSGD:
5352 case BFD_RELOC_X86_64_TLSLD:
5353 case BFD_RELOC_X86_64_DTPOFF32:
5354 case BFD_RELOC_X86_64_GOTTPOFF:
5355 case BFD_RELOC_X86_64_TPOFF32:
5357 case BFD_RELOC_VTABLE_ENTRY:
5358 case BFD_RELOC_VTABLE_INHERIT:
5360 case BFD_RELOC_32_SECREL:
5362 code = fixp->fx_r_type;
5367 switch (fixp->fx_size)
5370 as_bad_where (fixp->fx_file, fixp->fx_line,
5371 _("can not do %d byte pc-relative relocation"),
5373 code = BFD_RELOC_32_PCREL;
5375 case 1: code = BFD_RELOC_8_PCREL; break;
5376 case 2: code = BFD_RELOC_16_PCREL; break;
5377 case 4: code = BFD_RELOC_32_PCREL; break;
5382 switch (fixp->fx_size)
5385 as_bad_where (fixp->fx_file, fixp->fx_line,
5386 _("can not do %d byte relocation"),
5388 code = BFD_RELOC_32;
5390 case 1: code = BFD_RELOC_8; break;
5391 case 2: code = BFD_RELOC_16; break;
5392 case 4: code = BFD_RELOC_32; break;
5394 case 8: code = BFD_RELOC_64; break;
5401 if (code == BFD_RELOC_32
5403 && fixp->fx_addsy == GOT_symbol)
5405 /* We don't support GOTPC on 64bit targets. */
5406 if (flag_code == CODE_64BIT)
5408 code = BFD_RELOC_386_GOTPC;
5411 rel = (arelent *) xmalloc (sizeof (arelent));
5412 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5413 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5415 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5417 if (!use_rela_relocations)
5419 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5420 vtable entry to be used in the relocation's section offset. */
5421 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5422 rel->address = fixp->fx_offset;
5426 /* Use the rela in 64bit mode. */
5429 if (!fixp->fx_pcrel)
5430 rel->addend = fixp->fx_offset;
5434 case BFD_RELOC_X86_64_PLT32:
5435 case BFD_RELOC_X86_64_GOT32:
5436 case BFD_RELOC_X86_64_GOTPCREL:
5437 case BFD_RELOC_X86_64_TLSGD:
5438 case BFD_RELOC_X86_64_TLSLD:
5439 case BFD_RELOC_X86_64_GOTTPOFF:
5440 rel->addend = fixp->fx_offset - fixp->fx_size;
5443 rel->addend = (section->vma
5445 + fixp->fx_addnumber
5446 + md_pcrel_from (fixp));
5451 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5452 if (rel->howto == NULL)
5454 as_bad_where (fixp->fx_file, fixp->fx_line,
5455 _("cannot represent relocation type %s"),
5456 bfd_get_reloc_code_name (code));
5457 /* Set howto to a garbage value so that we can keep going. */
5458 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5459 assert (rel->howto != NULL);
5466 /* Parse operands using Intel syntax. This implements a recursive descent
5467 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5470 FIXME: We do not recognize the full operand grammar defined in the MASM
5471 documentation. In particular, all the structure/union and
5472 high-level macro operands are missing.
5474 Uppercase words are terminals, lower case words are non-terminals.
5475 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5476 bars '|' denote choices. Most grammar productions are implemented in
5477 functions called 'intel_<production>'.
5479 Initial production is 'expr'.
5485 binOp & | AND | \| | OR | ^ | XOR
5487 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5489 constant digits [[ radixOverride ]]
5491 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5529 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5530 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5532 hexdigit a | b | c | d | e | f
5533 | A | B | C | D | E | F
5539 mulOp * | / | % | MOD | << | SHL | >> | SHR
5543 register specialRegister
5547 segmentRegister CS | DS | ES | FS | GS | SS
5549 specialRegister CR0 | CR2 | CR3 | CR4
5550 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5551 | TR3 | TR4 | TR5 | TR6 | TR7
5553 We simplify the grammar in obvious places (e.g., register parsing is
5554 done by calling parse_register) and eliminate immediate left recursion
5555 to implement a recursive-descent parser.
5605 /* Parsing structure for the intel syntax parser. Used to implement the
5606 semantic actions for the operand grammar. */
5607 struct intel_parser_s
5609 char *op_string; /* The string being parsed. */
5610 int got_a_float; /* Whether the operand is a float. */
5611 int op_modifier; /* Operand modifier. */
5612 int is_mem; /* 1 if operand is memory reference. */
5613 const reg_entry *reg; /* Last register reference found. */
5614 char *disp; /* Displacement string being built. */
5617 static struct intel_parser_s intel_parser;
5619 /* Token structure for parsing intel syntax. */
5622 int code; /* Token code. */
5623 const reg_entry *reg; /* Register entry for register tokens. */
5624 char *str; /* String representation. */
5627 static struct intel_token cur_token, prev_token;
5629 /* Token codes for the intel parser. Since T_SHORT is already used
5630 by COFF, undefine it first to prevent a warning. */
5649 /* Prototypes for intel parser functions. */
5650 static int intel_match_token PARAMS ((int code));
5651 static void intel_get_token PARAMS ((void));
5652 static void intel_putback_token PARAMS ((void));
5653 static int intel_expr PARAMS ((void));
5654 static int intel_e04 PARAMS ((void));
5655 static int intel_e04_1 PARAMS ((void));
5656 static int intel_e05 PARAMS ((void));
5657 static int intel_e05_1 PARAMS ((void));
5658 static int intel_e06 PARAMS ((void));
5659 static int intel_e06_1 PARAMS ((void));
5660 static int intel_e09 PARAMS ((void));
5661 static int intel_e09_1 PARAMS ((void));
5662 static int intel_e10 PARAMS ((void));
5663 static int intel_e10_1 PARAMS ((void));
5664 static int intel_e11 PARAMS ((void));
5667 i386_intel_operand (operand_string, got_a_float)
5668 char *operand_string;
5674 /* Initialize token holders. */
5675 cur_token.code = prev_token.code = T_NIL;
5676 cur_token.reg = prev_token.reg = NULL;
5677 cur_token.str = prev_token.str = NULL;
5679 /* Initialize parser structure. */
5680 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5683 strcpy (intel_parser.op_string, operand_string);
5684 intel_parser.got_a_float = got_a_float;
5685 intel_parser.op_modifier = -1;
5686 intel_parser.is_mem = 0;
5687 intel_parser.reg = NULL;
5688 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5689 if (intel_parser.disp == NULL)
5691 intel_parser.disp[0] = '\0';
5693 /* Read the first token and start the parser. */
5695 ret = intel_expr ();
5699 if (cur_token.code != T_NIL)
5701 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5702 current_templates->start->name, cur_token.str);
5705 /* If we found a memory reference, hand it over to i386_displacement
5706 to fill in the rest of the operand fields. */
5707 else if (intel_parser.is_mem)
5709 if ((i.mem_operands == 1
5710 && (current_templates->start->opcode_modifier & IsString) == 0)
5711 || i.mem_operands == 2)
5713 as_bad (_("too many memory references for '%s'"),
5714 current_templates->start->name);
5719 char *s = intel_parser.disp;
5722 /* Add the displacement expression. */
5724 ret = i386_displacement (s, s + strlen (s));
5726 ret = i386_index_check (operand_string);
5730 /* Constant and OFFSET expressions are handled by i386_immediate. */
5731 else if (intel_parser.op_modifier == T_OFFSET
5732 || intel_parser.reg == NULL)
5733 ret = i386_immediate (intel_parser.disp);
5737 free (intel_parser.disp);
5747 /* expr SHORT e04 */
5748 if (cur_token.code == T_SHORT)
5750 intel_parser.op_modifier = T_SHORT;
5751 intel_match_token (T_SHORT);
5753 return (intel_e04 ());
5758 return intel_e04 ();
5768 return (intel_e05 () && intel_e04_1 ());
5774 /* e04' addOp e05 e04' */
5775 if (cur_token.code == '+' || cur_token.code == '-')
5779 str[0] = cur_token.code;
5781 strcat (intel_parser.disp, str);
5782 intel_match_token (cur_token.code);
5784 return (intel_e05 () && intel_e04_1 ());
5799 return (intel_e06 () && intel_e05_1 ());
5805 /* e05' binOp e06 e05' */
5806 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5810 str[0] = cur_token.code;
5812 strcat (intel_parser.disp, str);
5813 intel_match_token (cur_token.code);
5815 return (intel_e06 () && intel_e05_1 ());
5830 return (intel_e09 () && intel_e06_1 ());
5836 /* e06' mulOp e09 e06' */
5837 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
5841 str[0] = cur_token.code;
5843 strcat (intel_parser.disp, str);
5844 intel_match_token (cur_token.code);
5846 return (intel_e09 () && intel_e06_1 ());
5848 else if (cur_token.code == T_SHL)
5850 strcat (intel_parser.disp, "<<");
5851 intel_match_token (cur_token.code);
5853 return (intel_e09 () && intel_e06_1 ());
5855 else if (cur_token.code == T_SHR)
5857 strcat (intel_parser.disp, ">>");
5858 intel_match_token (cur_token.code);
5860 return (intel_e09 () && intel_e06_1 ());
5868 /* e09 OFFSET e10 e09'
5881 /* e09 OFFSET e10 e09' */
5882 if (cur_token.code == T_OFFSET)
5884 intel_parser.is_mem = 0;
5885 intel_parser.op_modifier = T_OFFSET;
5886 intel_match_token (T_OFFSET);
5888 return (intel_e10 () && intel_e09_1 ());
5891 /* e09 NOT e10 e09' */
5892 else if (cur_token.code == '~')
5896 str[0] = cur_token.code;
5898 strcat (intel_parser.disp, str);
5899 intel_match_token (cur_token.code);
5901 return (intel_e10 () && intel_e09_1 ());
5906 return (intel_e10 () && intel_e09_1 ());
5912 /* e09' PTR e10 e09' */
5913 if (cur_token.code == T_PTR)
5917 if (prev_token.code == T_BYTE)
5918 suffix = BYTE_MNEM_SUFFIX;
5920 else if (prev_token.code == T_WORD)
5922 if (current_templates->start->name[0] == 'l'
5923 && current_templates->start->name[2] == 's'
5924 && current_templates->start->name[3] == 0)
5925 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
5926 else if (intel_parser.got_a_float == 2) /* "fi..." */
5927 suffix = SHORT_MNEM_SUFFIX;
5929 suffix = WORD_MNEM_SUFFIX;
5932 else if (prev_token.code == T_DWORD)
5934 if (current_templates->start->name[0] == 'l'
5935 && current_templates->start->name[2] == 's'
5936 && current_templates->start->name[3] == 0)
5937 suffix = WORD_MNEM_SUFFIX;
5938 else if (flag_code == CODE_16BIT
5939 && (current_templates->start->opcode_modifier
5940 & (Jump|JumpDword|JumpInterSegment)))
5941 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5942 else if (intel_parser.got_a_float == 1) /* "f..." */
5943 suffix = SHORT_MNEM_SUFFIX;
5945 suffix = LONG_MNEM_SUFFIX;
5948 else if (prev_token.code == T_FWORD)
5950 if (current_templates->start->name[0] == 'l'
5951 && current_templates->start->name[2] == 's'
5952 && current_templates->start->name[3] == 0)
5953 suffix = LONG_MNEM_SUFFIX;
5954 else if (!intel_parser.got_a_float)
5956 if (flag_code == CODE_16BIT)
5957 add_prefix (DATA_PREFIX_OPCODE);
5958 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5961 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
5964 else if (prev_token.code == T_QWORD)
5966 if (intel_parser.got_a_float == 1) /* "f..." */
5967 suffix = LONG_MNEM_SUFFIX;
5969 suffix = QWORD_MNEM_SUFFIX;
5972 else if (prev_token.code == T_TBYTE)
5974 if (intel_parser.got_a_float == 1)
5975 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5977 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
5980 else if (prev_token.code == T_XMMWORD)
5982 /* XXX ignored for now, but accepted since gcc uses it */
5988 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
5992 if (current_templates->start->base_opcode == 0x8d /* lea */)
5996 else if (i.suffix != suffix)
5998 as_bad (_("Conflicting operand modifiers"));
6002 intel_match_token (T_PTR);
6004 return (intel_e10 () && intel_e09_1 ());
6007 /* e09 : e10 e09' */
6008 else if (cur_token.code == ':')
6010 /* Mark as a memory operand only if it's not already known to be an
6011 offset expression. */
6012 if (intel_parser.op_modifier != T_OFFSET)
6013 intel_parser.is_mem = 1;
6015 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
6030 return (intel_e11 () && intel_e10_1 ());
6036 /* e10' [ expr ] e10' */
6037 if (cur_token.code == '[')
6039 intel_match_token ('[');
6041 /* Mark as a memory operand only if it's not already known to be an
6042 offset expression. If it's an offset expression, we need to keep
6044 if (intel_parser.op_modifier != T_OFFSET)
6045 intel_parser.is_mem = 1;
6047 strcat (intel_parser.disp, "[");
6049 /* Add a '+' to the displacement string if necessary. */
6050 if (*intel_parser.disp != '\0'
6051 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6052 strcat (intel_parser.disp, "+");
6054 if (intel_expr () && intel_match_token (']'))
6056 /* Preserve brackets when the operand is an offset expression. */
6057 if (intel_parser.op_modifier == T_OFFSET)
6058 strcat (intel_parser.disp, "]");
6060 return intel_e10_1 ();
6090 if (cur_token.code == '(')
6092 intel_match_token ('(');
6093 strcat (intel_parser.disp, "(");
6095 if (intel_expr () && intel_match_token (')'))
6097 strcat (intel_parser.disp, ")");
6105 else if (cur_token.code == '[')
6107 intel_match_token ('[');
6109 /* Mark as a memory operand only if it's not already known to be an
6110 offset expression. If it's an offset expression, we need to keep
6112 if (intel_parser.op_modifier != T_OFFSET)
6113 intel_parser.is_mem = 1;
6115 strcat (intel_parser.disp, "[");
6117 /* Operands for jump/call inside brackets denote absolute addresses. */
6118 if (current_templates->start->opcode_modifier
6119 & (Jump|JumpDword|JumpByte|JumpInterSegment))
6120 i.types[this_operand] |= JumpAbsolute;
6122 /* Add a '+' to the displacement string if necessary. */
6123 if (*intel_parser.disp != '\0'
6124 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6125 strcat (intel_parser.disp, "+");
6127 if (intel_expr () && intel_match_token (']'))
6129 /* Preserve brackets when the operand is an offset expression. */
6130 if (intel_parser.op_modifier == T_OFFSET)
6131 strcat (intel_parser.disp, "]");
6147 else if (cur_token.code == T_BYTE
6148 || cur_token.code == T_WORD
6149 || cur_token.code == T_DWORD
6150 || cur_token.code == T_FWORD
6151 || cur_token.code == T_QWORD
6152 || cur_token.code == T_TBYTE
6153 || cur_token.code == T_XMMWORD)
6155 intel_match_token (cur_token.code);
6157 if (cur_token.code != T_PTR)
6159 /* It must have been an identifier; add it to the displacement string. */
6160 strcat (intel_parser.disp, prev_token.str);
6162 /* The identifier represents a memory reference only if it's not
6163 preceded by an offset modifier and if it's not an equate. */
6164 if (intel_parser.op_modifier != T_OFFSET)
6168 symbolP = symbol_find(prev_token.str);
6169 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6170 intel_parser.is_mem = 1;
6179 else if (cur_token.code == '.')
6181 strcat (intel_parser.disp, cur_token.str);
6182 intel_match_token (cur_token.code);
6184 /* Mark as a memory operand only if it's not already known to be an
6185 offset expression. */
6186 if (intel_parser.op_modifier != T_OFFSET)
6187 intel_parser.is_mem = 1;
6193 else if (cur_token.code == T_REG)
6195 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6197 intel_match_token (T_REG);
6199 /* Check for segment change. */
6200 if (cur_token.code == ':')
6202 if (reg->reg_type & (SReg2 | SReg3))
6204 switch (reg->reg_num)
6207 i.seg[i.mem_operands] = &es;
6210 i.seg[i.mem_operands] = &cs;
6213 i.seg[i.mem_operands] = &ss;
6216 i.seg[i.mem_operands] = &ds;
6219 i.seg[i.mem_operands] = &fs;
6222 i.seg[i.mem_operands] = &gs;
6228 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6233 /* Not a segment register. Check for register scaling. */
6234 else if (cur_token.code == '*')
6236 if (!intel_parser.is_mem)
6238 as_bad (_("Register scaling only allowed in memory operands."));
6242 /* What follows must be a valid scale. */
6243 if (intel_match_token ('*')
6244 && strchr ("01248", *cur_token.str))
6247 i.types[this_operand] |= BaseIndex;
6249 /* Set the scale after setting the register (otherwise,
6250 i386_scale will complain) */
6251 i386_scale (cur_token.str);
6252 intel_match_token (T_CONST);
6256 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6262 /* No scaling. If this is a memory operand, the register is either a
6263 base register (first occurrence) or an index register (second
6265 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
6267 if (i.base_reg && i.index_reg)
6269 as_bad (_("Too many register references in memory operand."));
6273 if (i.base_reg == NULL)
6278 i.types[this_operand] |= BaseIndex;
6281 /* Offset modifier. Add the register to the displacement string to be
6282 parsed as an immediate expression after we're done. */
6283 else if (intel_parser.op_modifier == T_OFFSET)
6284 strcat (intel_parser.disp, reg->reg_name);
6286 /* It's neither base nor index nor offset. */
6289 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6290 i.op[this_operand].regs = reg;
6294 /* Since registers are not part of the displacement string (except
6295 when we're parsing offset operands), we may need to remove any
6296 preceding '+' from the displacement string. */
6297 if (*intel_parser.disp != '\0'
6298 && intel_parser.op_modifier != T_OFFSET)
6300 char *s = intel_parser.disp;
6301 s += strlen (s) - 1;
6310 else if (cur_token.code == T_ID)
6312 /* Add the identifier to the displacement string. */
6313 strcat (intel_parser.disp, cur_token.str);
6315 /* The identifier represents a memory reference only if it's not
6316 preceded by an offset modifier and if it's not an equate. */
6317 if (intel_parser.op_modifier != T_OFFSET)
6321 symbolP = symbol_find(cur_token.str);
6322 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6323 intel_parser.is_mem = 1;
6326 intel_match_token (T_ID);
6331 else if (cur_token.code == T_CONST
6332 || cur_token.code == '-'
6333 || cur_token.code == '+')
6337 /* Allow constants that start with `+' or `-'. */
6338 if (cur_token.code == '-' || cur_token.code == '+')
6340 strcat (intel_parser.disp, cur_token.str);
6341 intel_match_token (cur_token.code);
6342 if (cur_token.code != T_CONST)
6344 as_bad (_("Syntax error. Expecting a constant. Got `%s'."),
6350 save_str = (char *) malloc (strlen (cur_token.str) + 1);
6351 if (save_str == NULL)
6353 strcpy (save_str, cur_token.str);
6355 /* Get the next token to check for register scaling. */
6356 intel_match_token (cur_token.code);
6358 /* Check if this constant is a scaling factor for an index register. */
6359 if (cur_token.code == '*')
6361 if (intel_match_token ('*') && cur_token.code == T_REG)
6363 if (!intel_parser.is_mem)
6365 as_bad (_("Register scaling only allowed in memory operands."));
6369 /* The constant is followed by `* reg', so it must be
6371 if (strchr ("01248", *save_str))
6373 i.index_reg = cur_token.reg;
6374 i.types[this_operand] |= BaseIndex;
6376 /* Set the scale after setting the register (otherwise,
6377 i386_scale will complain) */
6378 i386_scale (save_str);
6379 intel_match_token (T_REG);
6381 /* Since registers are not part of the displacement
6382 string, we may need to remove any preceding '+' from
6383 the displacement string. */
6384 if (*intel_parser.disp != '\0')
6386 char *s = intel_parser.disp;
6387 s += strlen (s) - 1;
6400 /* The constant was not used for register scaling. Since we have
6401 already consumed the token following `*' we now need to put it
6402 back in the stream. */
6404 intel_putback_token ();
6407 /* Add the constant to the displacement string. */
6408 strcat (intel_parser.disp, save_str);
6414 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6418 /* Match the given token against cur_token. If they match, read the next
6419 token from the operand string. */
6421 intel_match_token (code)
6424 if (cur_token.code == code)
6431 as_bad (_("Unexpected token `%s'"), cur_token.str);
6436 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6441 const reg_entry *reg;
6442 struct intel_token new_token;
6444 new_token.code = T_NIL;
6445 new_token.reg = NULL;
6446 new_token.str = NULL;
6448 /* Free the memory allocated to the previous token and move
6449 cur_token to prev_token. */
6451 free (prev_token.str);
6453 prev_token = cur_token;
6455 /* Skip whitespace. */
6456 while (is_space_char (*intel_parser.op_string))
6457 intel_parser.op_string++;
6459 /* Return an empty token if we find nothing else on the line. */
6460 if (*intel_parser.op_string == '\0')
6462 cur_token = new_token;
6466 /* The new token cannot be larger than the remainder of the operand
6468 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6469 if (new_token.str == NULL)
6471 new_token.str[0] = '\0';
6473 if (strchr ("0123456789", *intel_parser.op_string))
6475 char *p = new_token.str;
6476 char *q = intel_parser.op_string;
6477 new_token.code = T_CONST;
6479 /* Allow any kind of identifier char to encompass floating point and
6480 hexadecimal numbers. */
6481 while (is_identifier_char (*q))
6485 /* Recognize special symbol names [0-9][bf]. */
6486 if (strlen (intel_parser.op_string) == 2
6487 && (intel_parser.op_string[1] == 'b'
6488 || intel_parser.op_string[1] == 'f'))
6489 new_token.code = T_ID;
6492 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6493 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6495 new_token.code = T_REG;
6496 new_token.reg = reg;
6498 if (*intel_parser.op_string == REGISTER_PREFIX)
6500 new_token.str[0] = REGISTER_PREFIX;
6501 new_token.str[1] = '\0';
6504 strcat (new_token.str, reg->reg_name);
6507 else if (is_identifier_char (*intel_parser.op_string))
6509 char *p = new_token.str;
6510 char *q = intel_parser.op_string;
6512 /* A '.' or '$' followed by an identifier char is an identifier.
6513 Otherwise, it's operator '.' followed by an expression. */
6514 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6516 new_token.code = '.';
6517 new_token.str[0] = '.';
6518 new_token.str[1] = '\0';
6522 while (is_identifier_char (*q) || *q == '@')
6526 if (strcasecmp (new_token.str, "NOT") == 0)
6527 new_token.code = '~';
6529 else if (strcasecmp (new_token.str, "MOD") == 0)
6530 new_token.code = '%';
6532 else if (strcasecmp (new_token.str, "AND") == 0)
6533 new_token.code = '&';
6535 else if (strcasecmp (new_token.str, "OR") == 0)
6536 new_token.code = '|';
6538 else if (strcasecmp (new_token.str, "XOR") == 0)
6539 new_token.code = '^';
6541 else if (strcasecmp (new_token.str, "SHL") == 0)
6542 new_token.code = T_SHL;
6544 else if (strcasecmp (new_token.str, "SHR") == 0)
6545 new_token.code = T_SHR;
6547 else if (strcasecmp (new_token.str, "BYTE") == 0)
6548 new_token.code = T_BYTE;
6550 else if (strcasecmp (new_token.str, "WORD") == 0)
6551 new_token.code = T_WORD;
6553 else if (strcasecmp (new_token.str, "DWORD") == 0)
6554 new_token.code = T_DWORD;
6556 else if (strcasecmp (new_token.str, "FWORD") == 0)
6557 new_token.code = T_FWORD;
6559 else if (strcasecmp (new_token.str, "QWORD") == 0)
6560 new_token.code = T_QWORD;
6562 else if (strcasecmp (new_token.str, "TBYTE") == 0
6563 /* XXX remove (gcc still uses it) */
6564 || strcasecmp (new_token.str, "XWORD") == 0)
6565 new_token.code = T_TBYTE;
6567 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6568 || strcasecmp (new_token.str, "OWORD") == 0)
6569 new_token.code = T_XMMWORD;
6571 else if (strcasecmp (new_token.str, "PTR") == 0)
6572 new_token.code = T_PTR;
6574 else if (strcasecmp (new_token.str, "SHORT") == 0)
6575 new_token.code = T_SHORT;
6577 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6579 new_token.code = T_OFFSET;
6581 /* ??? This is not mentioned in the MASM grammar but gcc
6582 makes use of it with -mintel-syntax. OFFSET may be
6583 followed by FLAT: */
6584 if (strncasecmp (q, " FLAT:", 6) == 0)
6585 strcat (new_token.str, " FLAT:");
6588 /* ??? This is not mentioned in the MASM grammar. */
6589 else if (strcasecmp (new_token.str, "FLAT") == 0)
6590 new_token.code = T_OFFSET;
6593 new_token.code = T_ID;
6597 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6599 new_token.code = *intel_parser.op_string;
6600 new_token.str[0] = *intel_parser.op_string;
6601 new_token.str[1] = '\0';
6604 else if (strchr ("<>", *intel_parser.op_string)
6605 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6607 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6608 new_token.str[0] = *intel_parser.op_string;
6609 new_token.str[1] = *intel_parser.op_string;
6610 new_token.str[2] = '\0';
6614 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
6616 intel_parser.op_string += strlen (new_token.str);
6617 cur_token = new_token;
6620 /* Put cur_token back into the token stream and make cur_token point to
6623 intel_putback_token ()
6625 intel_parser.op_string -= strlen (cur_token.str);
6626 free (cur_token.str);
6627 cur_token = prev_token;
6629 /* Forget prev_token. */
6630 prev_token.code = T_NIL;
6631 prev_token.reg = NULL;
6632 prev_token.str = NULL;
6636 tc_x86_regname_to_dw2regnum (const char *regname)
6638 unsigned int regnum;
6639 unsigned int regnames_count;
6640 char *regnames_32[] =
6642 "eax", "ecx", "edx", "ebx",
6643 "esp", "ebp", "esi", "edi",
6646 char *regnames_64[] =
6648 "rax", "rbx", "rcx", "rdx",
6649 "rdi", "rsi", "rbp", "rsp",
6650 "r8", "r9", "r10", "r11",
6651 "r12", "r13", "r14", "r15",
6656 if (flag_code == CODE_64BIT)
6658 regnames = regnames_64;
6659 regnames_count = ARRAY_SIZE (regnames_64);
6663 regnames = regnames_32;
6664 regnames_count = ARRAY_SIZE (regnames_32);
6667 for (regnum = 0; regnum < regnames_count; regnum++)
6668 if (strcmp (regname, regnames[regnum]) == 0)
6675 tc_x86_frame_initial_instructions (void)
6677 static unsigned int sp_regno;
6680 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6683 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6684 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
6688 i386_elf_section_type (const char *str, size_t len)
6690 if (flag_code == CODE_64BIT
6691 && len == sizeof ("unwind") - 1
6692 && strncmp (str, "unwind", 6) == 0)
6693 return SHT_X86_64_UNWIND;
6700 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6704 expr.X_op = O_secrel;
6705 expr.X_add_symbol = symbol;
6706 expr.X_add_number = 0;
6707 emit_expr (&expr, size);