1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
193 static const char *default_arch = DEFAULT_ARCH;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
234 /* Number of bytes to broadcast. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
268 unsupported_with_intel_mnemonic,
271 invalid_vsib_address,
272 invalid_vector_register_set,
273 unsupported_vector_index_register,
274 unsupported_broadcast,
277 mask_not_on_destination,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
286 /* TM holds the template for the insn were currently assembling. */
289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
293 /* OPERANDS gives the number of given operands. */
294 unsigned int operands;
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
299 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301 /* TYPES [i] is the type (see above #defines) which tells us how to
302 use OP[i] for the corresponding operand. */
303 i386_operand_type types[MAX_OPERANDS];
305 /* Displacement expression, immediate expression, or register for each
307 union i386_op op[MAX_OPERANDS];
309 /* Flags for operands. */
310 unsigned int flags[MAX_OPERANDS];
311 #define Operand_PCrel 1
313 /* Relocation type for operand */
314 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry *base_reg;
319 const reg_entry *index_reg;
320 unsigned int log2_scale_factor;
322 /* SEG gives the seg_entries of this insn. They are zero unless
323 explicit segment overrides are given. */
324 const seg_entry *seg[2];
326 /* Copied first memory operand string, for re-checking. */
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation *mask;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
354 /* Prefer load or store in encoding. */
357 dir_encoding_default = 0,
362 /* Prefer 8bit or 32bit displacement in encoding. */
365 disp_encoding_default = 0,
370 /* Prefer the REX byte in encoding. */
371 bfd_boolean rex_encoding;
373 /* Disable instruction size optimization. */
374 bfd_boolean no_optimize;
376 /* How to encode vector instructions. */
379 vex_encoding_default = 0,
386 const char *rep_prefix;
389 const char *hle_prefix;
391 /* Have BND prefix. */
392 const char *bnd_prefix;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix;
398 enum i386_error error;
401 typedef struct _i386_insn i386_insn;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable[] =
414 { rne, STRING_COMMA_LEN ("rn-sae") },
415 { rd, STRING_COMMA_LEN ("rd-sae") },
416 { ru, STRING_COMMA_LEN ("ru-sae") },
417 { rz, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars = "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars = "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars[] = "#/";
462 const char line_separator_chars[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars[256];
475 static char register_chars[256];
476 static char operand_chars[256];
477 static char identifier_chars[256];
478 static char digit_chars[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack[32];
496 static char *save_stack_p;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates *current_templates;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
510 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
512 /* Current operand we are working on. */
513 static int this_operand = -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code;
524 static unsigned int object_64bit;
525 static unsigned int disallow_64bit_reloc;
526 static int use_rela_relocations = 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi = I386_ABI;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj = 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared = 0;
553 /* 1 for intel syntax,
555 static int intel_syntax = 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic = !SYSV386_COMPAT;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix = 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592 static enum check_kind
598 sse_check, operand_check = check_warning;
601 1. Clear the REX_W bit with register operand if possible.
602 2. Above plus use 128bit vector instruction to clear the full vector
605 static int optimize = 0;
608 1. Clear the REX_W bit with register operand if possible.
609 2. Above plus use 128bit vector instruction to clear the full vector
611 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
614 static int optimize_for_space = 0;
616 /* Register prefix used for error message. */
617 static const char *register_prefix = "%";
619 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
620 leave, push, and pop instructions so that gcc has the same stack
621 frame as in 32 bit mode. */
622 static char stackop_size = '\0';
624 /* Non-zero to optimize code alignment. */
625 int optimize_align_code = 1;
627 /* Non-zero to quieten some warnings. */
628 static int quiet_warnings = 0;
631 static const char *cpu_arch_name = NULL;
632 static char *cpu_sub_arch_name = NULL;
634 /* CPU feature flags. */
635 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
637 /* If we have selected a cpu we are generating instructions for. */
638 static int cpu_arch_tune_set = 0;
640 /* Cpu we are generating instructions for. */
641 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
643 /* CPU feature flags of cpu we are generating instructions for. */
644 static i386_cpu_flags cpu_arch_tune_flags;
646 /* CPU instruction set architecture used. */
647 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
649 /* CPU feature flags of instruction set architecture used. */
650 i386_cpu_flags cpu_arch_isa_flags;
652 /* If set, conditional jumps are not automatically promoted to handle
653 larger than a byte offset. */
654 static unsigned int no_cond_jump_promotion = 0;
656 /* Encode SSE instructions with VEX prefix. */
657 static unsigned int sse2avx;
659 /* Encode scalar AVX instructions with specific vector length. */
666 /* Encode scalar EVEX LIG instructions with specific vector length. */
674 /* Encode EVEX WIG instructions with specific evex.w. */
681 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
682 static enum rc_type evexrcig = rne;
684 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
685 static symbolS *GOT_symbol;
687 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
688 unsigned int x86_dwarf2_return_column;
690 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
691 int x86_cie_data_alignment;
693 /* Interface to relax_segment.
694 There are 3 major relax states for 386 jump insns because the
695 different types of jumps add different sizes to frags when we're
696 figuring out what sort of jump to choose to reach a given label. */
699 #define UNCOND_JUMP 0
701 #define COND_JUMP86 2
706 #define SMALL16 (SMALL | CODE16)
708 #define BIG16 (BIG | CODE16)
712 #define INLINE __inline__
718 #define ENCODE_RELAX_STATE(type, size) \
719 ((relax_substateT) (((type) << 2) | (size)))
720 #define TYPE_FROM_RELAX_STATE(s) \
722 #define DISP_SIZE_FROM_RELAX_STATE(s) \
723 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
725 /* This table is used by relax_frag to promote short jumps to long
726 ones where necessary. SMALL (short) jumps may be promoted to BIG
727 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
728 don't allow a short jump in a 32 bit code segment to be promoted to
729 a 16 bit offset jump because it's slower (requires data size
730 prefix), and doesn't work, unless the destination is in the bottom
731 64k of the code segment (The top 16 bits of eip are zeroed). */
733 const relax_typeS md_relax_table[] =
736 1) most positive reach of this state,
737 2) most negative reach of this state,
738 3) how many bytes this mode will have in the variable part of the frag
739 4) which index into the table to try if we can't fit into this one. */
741 /* UNCOND_JUMP states. */
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
743 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
744 /* dword jmp adds 4 bytes to frag:
745 0 extra opcode bytes, 4 displacement bytes. */
747 /* word jmp adds 2 byte2 to frag:
748 0 extra opcode bytes, 2 displacement bytes. */
751 /* COND_JUMP states. */
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
753 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
754 /* dword conditionals adds 5 bytes to frag:
755 1 extra opcode byte, 4 displacement bytes. */
757 /* word conditionals add 3 bytes to frag:
758 1 extra opcode byte, 2 displacement bytes. */
761 /* COND_JUMP86 states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
764 /* dword conditionals adds 5 bytes to frag:
765 1 extra opcode byte, 4 displacement bytes. */
767 /* word conditionals add 4 bytes to frag:
768 1 displacement byte and a 3 byte long branch insn. */
772 static const arch_entry cpu_arch[] =
774 /* Do not replace the first two entries - i386_target_format()
775 relies on them being there in this order. */
776 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
777 CPU_GENERIC32_FLAGS, 0 },
778 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
779 CPU_GENERIC64_FLAGS, 0 },
780 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
782 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
784 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
786 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
788 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
790 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
792 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
794 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
796 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
797 CPU_PENTIUMPRO_FLAGS, 0 },
798 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
800 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
802 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
804 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
806 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
807 CPU_NOCONA_FLAGS, 0 },
808 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
810 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
812 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 1 },
814 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
815 CPU_CORE2_FLAGS, 0 },
816 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
817 CPU_COREI7_FLAGS, 0 },
818 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
820 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
822 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
823 CPU_IAMCU_FLAGS, 0 },
824 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
826 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
828 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
829 CPU_ATHLON_FLAGS, 0 },
830 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
832 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
834 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
836 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
837 CPU_AMDFAM10_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
839 CPU_BDVER1_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
841 CPU_BDVER2_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
843 CPU_BDVER3_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
845 CPU_BDVER4_FLAGS, 0 },
846 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
847 CPU_ZNVER1_FLAGS, 0 },
848 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
849 CPU_ZNVER2_FLAGS, 0 },
850 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
851 CPU_BTVER1_FLAGS, 0 },
852 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
853 CPU_BTVER2_FLAGS, 0 },
854 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
856 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
858 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
860 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
866 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
868 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
870 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
871 CPU_SSSE3_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_1_FLAGS, 0 },
874 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
875 CPU_SSE4_2_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_2_FLAGS, 0 },
878 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
882 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
883 CPU_AVX512F_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
885 CPU_AVX512CD_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
887 CPU_AVX512ER_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
889 CPU_AVX512PF_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
891 CPU_AVX512DQ_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
893 CPU_AVX512BW_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
895 CPU_AVX512VL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
899 CPU_VMFUNC_FLAGS, 0 },
900 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
903 CPU_XSAVE_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
905 CPU_XSAVEOPT_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
907 CPU_XSAVEC_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
909 CPU_XSAVES_FLAGS, 0 },
910 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
912 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
913 CPU_PCLMUL_FLAGS, 0 },
914 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
915 CPU_PCLMUL_FLAGS, 1 },
916 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
917 CPU_FSGSBASE_FLAGS, 0 },
918 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
919 CPU_RDRND_FLAGS, 0 },
920 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
933 CPU_MOVBE_FLAGS, 0 },
934 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
938 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
939 CPU_LZCNT_FLAGS, 0 },
940 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
942 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
944 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
945 CPU_INVPCID_FLAGS, 0 },
946 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
947 CPU_CLFLUSH_FLAGS, 0 },
948 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
950 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
951 CPU_SYSCALL_FLAGS, 0 },
952 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
953 CPU_RDTSCP_FLAGS, 0 },
954 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
955 CPU_3DNOW_FLAGS, 0 },
956 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
957 CPU_3DNOWA_FLAGS, 0 },
958 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
959 CPU_PADLOCK_FLAGS, 0 },
960 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
965 CPU_SSE4A_FLAGS, 0 },
966 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
975 CPU_RDSEED_FLAGS, 0 },
976 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
977 CPU_PRFCHW_FLAGS, 0 },
978 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
980 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
985 CPU_CLFLUSHOPT_FLAGS, 0 },
986 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
987 CPU_PREFETCHWT1_FLAGS, 0 },
988 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
992 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
993 CPU_AVX512IFMA_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
995 CPU_AVX512VBMI_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4FMAPS_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_4VNNIW_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VBMI2_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VNNI_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_BITALG_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1009 CPU_CLZERO_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1011 CPU_MWAITX_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1013 CPU_OSPKE_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1015 CPU_RDPID_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1017 CPU_PTWRITE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1020 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1021 CPU_SHSTK_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1023 CPU_GFNI_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1025 CPU_VAES_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1027 CPU_VPCLMULQDQ_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1029 CPU_WBNOINVD_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1031 CPU_PCONFIG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1033 CPU_WAITPKG_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1035 CPU_CLDEMOTE_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIRI_FLAGS, 0 },
1038 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1039 CPU_MOVDIR64B_FLAGS, 0 },
1042 static const noarch_entry cpu_noarch[] =
1044 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1045 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1046 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1047 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1048 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1049 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1050 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1052 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1054 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1055 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1056 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1057 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1069 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1070 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1071 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1072 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1073 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1074 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1075 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1076 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1080 /* Like s_lcomm_internal in gas/read.c but the alignment string
1081 is allowed to be optional. */
1084 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1091 && *input_line_pointer == ',')
1093 align = parse_align (needs_align - 1);
1095 if (align == (addressT) -1)
1110 bss_alloc (symbolP, size, align);
1115 pe_lcomm (int needs_align)
1117 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1121 const pseudo_typeS md_pseudo_table[] =
1123 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1124 {"align", s_align_bytes, 0},
1126 {"align", s_align_ptwo, 0},
1128 {"arch", set_cpu_arch, 0},
1132 {"lcomm", pe_lcomm, 1},
1134 {"ffloat", float_cons, 'f'},
1135 {"dfloat", float_cons, 'd'},
1136 {"tfloat", float_cons, 'x'},
1138 {"slong", signed_cons, 4},
1139 {"noopt", s_ignore, 0},
1140 {"optim", s_ignore, 0},
1141 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1142 {"code16", set_code_flag, CODE_16BIT},
1143 {"code32", set_code_flag, CODE_32BIT},
1145 {"code64", set_code_flag, CODE_64BIT},
1147 {"intel_syntax", set_intel_syntax, 1},
1148 {"att_syntax", set_intel_syntax, 0},
1149 {"intel_mnemonic", set_intel_mnemonic, 1},
1150 {"att_mnemonic", set_intel_mnemonic, 0},
1151 {"allow_index_reg", set_allow_index_reg, 1},
1152 {"disallow_index_reg", set_allow_index_reg, 0},
1153 {"sse_check", set_check, 0},
1154 {"operand_check", set_check, 1},
1155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1156 {"largecomm", handle_large_common, 0},
1158 {"file", dwarf2_directive_file, 0},
1159 {"loc", dwarf2_directive_loc, 0},
1160 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1163 {"secrel32", pe_directive_secrel, 0},
1168 /* For interface with expression (). */
1169 extern char *input_line_pointer;
1171 /* Hash table for instruction mnemonic lookup. */
1172 static struct hash_control *op_hash;
1174 /* Hash table for register lookup. */
1175 static struct hash_control *reg_hash;
1177 /* Various efficient no-op patterns for aligning code labels.
1178 Note: Don't try to assemble the instructions in the comments.
1179 0L and 0w are not legal. */
1180 static const unsigned char f32_1[] =
1182 static const unsigned char f32_2[] =
1183 {0x66,0x90}; /* xchg %ax,%ax */
1184 static const unsigned char f32_3[] =
1185 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1186 static const unsigned char f32_4[] =
1187 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1188 static const unsigned char f32_6[] =
1189 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1190 static const unsigned char f32_7[] =
1191 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1192 static const unsigned char f16_3[] =
1193 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1194 static const unsigned char f16_4[] =
1195 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1196 static const unsigned char jump_disp8[] =
1197 {0xeb}; /* jmp disp8 */
1198 static const unsigned char jump32_disp32[] =
1199 {0xe9}; /* jmp disp32 */
1200 static const unsigned char jump16_disp32[] =
1201 {0x66,0xe9}; /* jmp disp32 */
1202 /* 32-bit NOPs patterns. */
1203 static const unsigned char *const f32_patt[] = {
1204 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1206 /* 16-bit NOPs patterns. */
1207 static const unsigned char *const f16_patt[] = {
1208 f32_1, f32_2, f16_3, f16_4
1210 /* nopl (%[re]ax) */
1211 static const unsigned char alt_3[] =
1213 /* nopl 0(%[re]ax) */
1214 static const unsigned char alt_4[] =
1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_5[] =
1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_6[] =
1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
1223 static const unsigned char alt_7[] =
1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_8[] =
1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_9[] =
1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1232 static const unsigned char alt_10[] =
1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1234 /* data16 nopw %cs:0L(%eax,%eax,1) */
1235 static const unsigned char alt_11[] =
1236 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* 32-bit and 64-bit NOPs patterns. */
1238 static const unsigned char *const alt_patt[] = {
1239 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1240 alt_9, alt_10, alt_11
1243 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1244 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1247 i386_output_nops (char *where, const unsigned char *const *patt,
1248 int count, int max_single_nop_size)
1251 /* Place the longer NOP first. */
1254 const unsigned char *nops = patt[max_single_nop_size - 1];
1256 /* Use the smaller one if the requsted one isn't available. */
1259 max_single_nop_size--;
1260 nops = patt[max_single_nop_size - 1];
1263 last = count % max_single_nop_size;
1266 for (offset = 0; offset < count; offset += max_single_nop_size)
1267 memcpy (where + offset, nops, max_single_nop_size);
1271 nops = patt[last - 1];
1274 /* Use the smaller one plus one-byte NOP if the needed one
1277 nops = patt[last - 1];
1278 memcpy (where + offset, nops, last);
1279 where[offset + last] = *patt[0];
1282 memcpy (where + offset, nops, last);
1287 fits_in_imm7 (offsetT num)
1289 return (num & 0x7f) == num;
1293 fits_in_imm31 (offsetT num)
1295 return (num & 0x7fffffff) == num;
1298 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1299 single NOP instruction LIMIT. */
1302 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1304 const unsigned char *const *patt = NULL;
1305 int max_single_nop_size;
1306 /* Maximum number of NOPs before switching to jump over NOPs. */
1307 int max_number_of_nops;
1309 switch (fragP->fr_type)
1318 /* We need to decide which NOP sequence to use for 32bit and
1319 64bit. When -mtune= is used:
1321 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1322 PROCESSOR_GENERIC32, f32_patt will be used.
1323 2. For the rest, alt_patt will be used.
1325 When -mtune= isn't used, alt_patt will be used if
1326 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1329 When -march= or .arch is used, we can't use anything beyond
1330 cpu_arch_isa_flags. */
1332 if (flag_code == CODE_16BIT)
1335 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1336 /* Limit number of NOPs to 2 in 16-bit mode. */
1337 max_number_of_nops = 2;
1341 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1343 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1344 switch (cpu_arch_tune)
1346 case PROCESSOR_UNKNOWN:
1347 /* We use cpu_arch_isa_flags to check if we SHOULD
1348 optimize with nops. */
1349 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1354 case PROCESSOR_PENTIUM4:
1355 case PROCESSOR_NOCONA:
1356 case PROCESSOR_CORE:
1357 case PROCESSOR_CORE2:
1358 case PROCESSOR_COREI7:
1359 case PROCESSOR_L1OM:
1360 case PROCESSOR_K1OM:
1361 case PROCESSOR_GENERIC64:
1363 case PROCESSOR_ATHLON:
1365 case PROCESSOR_AMDFAM10:
1367 case PROCESSOR_ZNVER:
1371 case PROCESSOR_I386:
1372 case PROCESSOR_I486:
1373 case PROCESSOR_PENTIUM:
1374 case PROCESSOR_PENTIUMPRO:
1375 case PROCESSOR_IAMCU:
1376 case PROCESSOR_GENERIC32:
1383 switch (fragP->tc_frag_data.tune)
1385 case PROCESSOR_UNKNOWN:
1386 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1387 PROCESSOR_UNKNOWN. */
1391 case PROCESSOR_I386:
1392 case PROCESSOR_I486:
1393 case PROCESSOR_PENTIUM:
1394 case PROCESSOR_IAMCU:
1396 case PROCESSOR_ATHLON:
1398 case PROCESSOR_AMDFAM10:
1400 case PROCESSOR_ZNVER:
1402 case PROCESSOR_GENERIC32:
1403 /* We use cpu_arch_isa_flags to check if we CAN optimize
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 case PROCESSOR_PENTIUMPRO:
1411 case PROCESSOR_PENTIUM4:
1412 case PROCESSOR_NOCONA:
1413 case PROCESSOR_CORE:
1414 case PROCESSOR_CORE2:
1415 case PROCESSOR_COREI7:
1416 case PROCESSOR_L1OM:
1417 case PROCESSOR_K1OM:
1418 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1423 case PROCESSOR_GENERIC64:
1429 if (patt == f32_patt)
1431 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1432 /* Limit number of NOPs to 2 for older processors. */
1433 max_number_of_nops = 2;
1437 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1438 /* Limit number of NOPs to 7 for newer processors. */
1439 max_number_of_nops = 7;
1444 limit = max_single_nop_size;
1446 if (fragP->fr_type == rs_fill_nop)
1448 /* Output NOPs for .nop directive. */
1449 if (limit > max_single_nop_size)
1451 as_bad_where (fragP->fr_file, fragP->fr_line,
1452 _("invalid single nop size: %d "
1453 "(expect within [0, %d])"),
1454 limit, max_single_nop_size);
1459 fragP->fr_var = count;
1461 if ((count / max_single_nop_size) > max_number_of_nops)
1463 /* Generate jump over NOPs. */
1464 offsetT disp = count - 2;
1465 if (fits_in_imm7 (disp))
1467 /* Use "jmp disp8" if possible. */
1469 where[0] = jump_disp8[0];
1475 unsigned int size_of_jump;
1477 if (flag_code == CODE_16BIT)
1479 where[0] = jump16_disp32[0];
1480 where[1] = jump16_disp32[1];
1485 where[0] = jump32_disp32[0];
1489 count -= size_of_jump + 4;
1490 if (!fits_in_imm31 (count))
1492 as_bad_where (fragP->fr_file, fragP->fr_line,
1493 _("jump over nop padding out of range"));
1497 md_number_to_chars (where + size_of_jump, count, 4);
1498 where += size_of_jump + 4;
1502 /* Generate multiple NOPs. */
1503 i386_output_nops (where, patt, count, limit);
1507 operand_type_all_zero (const union i386_operand_type *x)
1509 switch (ARRAY_SIZE(x->array))
1520 return !x->array[0];
1527 operand_type_set (union i386_operand_type *x, unsigned int v)
1529 switch (ARRAY_SIZE(x->array))
1547 operand_type_equal (const union i386_operand_type *x,
1548 const union i386_operand_type *y)
1550 switch (ARRAY_SIZE(x->array))
1553 if (x->array[2] != y->array[2])
1557 if (x->array[1] != y->array[1])
1561 return x->array[0] == y->array[0];
1569 cpu_flags_all_zero (const union i386_cpu_flags *x)
1571 switch (ARRAY_SIZE(x->array))
1586 return !x->array[0];
1593 cpu_flags_equal (const union i386_cpu_flags *x,
1594 const union i386_cpu_flags *y)
1596 switch (ARRAY_SIZE(x->array))
1599 if (x->array[3] != y->array[3])
1603 if (x->array[2] != y->array[2])
1607 if (x->array[1] != y->array[1])
1611 return x->array[0] == y->array[0];
1619 cpu_flags_check_cpu64 (i386_cpu_flags f)
1621 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1622 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1625 static INLINE i386_cpu_flags
1626 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1628 switch (ARRAY_SIZE (x.array))
1631 x.array [3] &= y.array [3];
1634 x.array [2] &= y.array [2];
1637 x.array [1] &= y.array [1];
1640 x.array [0] &= y.array [0];
1648 static INLINE i386_cpu_flags
1649 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1651 switch (ARRAY_SIZE (x.array))
1654 x.array [3] |= y.array [3];
1657 x.array [2] |= y.array [2];
1660 x.array [1] |= y.array [1];
1663 x.array [0] |= y.array [0];
1671 static INLINE i386_cpu_flags
1672 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1674 switch (ARRAY_SIZE (x.array))
1677 x.array [3] &= ~y.array [3];
1680 x.array [2] &= ~y.array [2];
1683 x.array [1] &= ~y.array [1];
1686 x.array [0] &= ~y.array [0];
1694 #define CPU_FLAGS_ARCH_MATCH 0x1
1695 #define CPU_FLAGS_64BIT_MATCH 0x2
1697 #define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1700 /* Return CPU flags match bits. */
1703 cpu_flags_match (const insn_template *t)
1705 i386_cpu_flags x = t->cpu_flags;
1706 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1708 x.bitfield.cpu64 = 0;
1709 x.bitfield.cpuno64 = 0;
1711 if (cpu_flags_all_zero (&x))
1713 /* This instruction is available on all archs. */
1714 match |= CPU_FLAGS_ARCH_MATCH;
1718 /* This instruction is available only on some archs. */
1719 i386_cpu_flags cpu = cpu_arch_flags;
1721 /* AVX512VL is no standalone feature - match it and then strip it. */
1722 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1724 x.bitfield.cpuavx512vl = 0;
1726 cpu = cpu_flags_and (x, cpu);
1727 if (!cpu_flags_all_zero (&cpu))
1729 if (x.bitfield.cpuavx)
1731 /* We need to check a few extra flags with AVX. */
1732 if (cpu.bitfield.cpuavx
1733 && (!t->opcode_modifier.sse2avx || sse2avx)
1734 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1735 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1736 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1737 match |= CPU_FLAGS_ARCH_MATCH;
1739 else if (x.bitfield.cpuavx512f)
1741 /* We need to check a few extra flags with AVX512F. */
1742 if (cpu.bitfield.cpuavx512f
1743 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1744 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1745 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1746 match |= CPU_FLAGS_ARCH_MATCH;
1749 match |= CPU_FLAGS_ARCH_MATCH;
1755 static INLINE i386_operand_type
1756 operand_type_and (i386_operand_type x, i386_operand_type y)
1758 switch (ARRAY_SIZE (x.array))
1761 x.array [2] &= y.array [2];
1764 x.array [1] &= y.array [1];
1767 x.array [0] &= y.array [0];
1775 static INLINE i386_operand_type
1776 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1778 switch (ARRAY_SIZE (x.array))
1781 x.array [2] &= ~y.array [2];
1784 x.array [1] &= ~y.array [1];
1787 x.array [0] &= ~y.array [0];
1795 static INLINE i386_operand_type
1796 operand_type_or (i386_operand_type x, i386_operand_type y)
1798 switch (ARRAY_SIZE (x.array))
1801 x.array [2] |= y.array [2];
1804 x.array [1] |= y.array [1];
1807 x.array [0] |= y.array [0];
1815 static INLINE i386_operand_type
1816 operand_type_xor (i386_operand_type x, i386_operand_type y)
1818 switch (ARRAY_SIZE (x.array))
1821 x.array [2] ^= y.array [2];
1824 x.array [1] ^= y.array [1];
1827 x.array [0] ^= y.array [0];
1835 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1836 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1837 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1838 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1839 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1840 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1841 static const i386_operand_type anydisp
1842 = OPERAND_TYPE_ANYDISP;
1843 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1844 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1845 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1846 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1847 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1848 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1849 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1850 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1851 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1852 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1853 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1854 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1865 operand_type_check (i386_operand_type t, enum operand_type c)
1870 return t.bitfield.reg;
1873 return (t.bitfield.imm8
1877 || t.bitfield.imm32s
1878 || t.bitfield.imm64);
1881 return (t.bitfield.disp8
1882 || t.bitfield.disp16
1883 || t.bitfield.disp32
1884 || t.bitfield.disp32s
1885 || t.bitfield.disp64);
1888 return (t.bitfield.disp8
1889 || t.bitfield.disp16
1890 || t.bitfield.disp32
1891 || t.bitfield.disp32s
1892 || t.bitfield.disp64
1893 || t.bitfield.baseindex);
1902 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1903 between operand GIVEN and opeand WANTED for instruction template T. */
1906 match_operand_size (const insn_template *t, unsigned int wanted,
1909 return !((i.types[given].bitfield.byte
1910 && !t->operand_types[wanted].bitfield.byte)
1911 || (i.types[given].bitfield.word
1912 && !t->operand_types[wanted].bitfield.word)
1913 || (i.types[given].bitfield.dword
1914 && !t->operand_types[wanted].bitfield.dword)
1915 || (i.types[given].bitfield.qword
1916 && !t->operand_types[wanted].bitfield.qword)
1917 || (i.types[given].bitfield.tbyte
1918 && !t->operand_types[wanted].bitfield.tbyte));
1921 /* Return 1 if there is no conflict in SIMD register between operand
1922 GIVEN and opeand WANTED for instruction template T. */
1925 match_simd_size (const insn_template *t, unsigned int wanted,
1928 return !((i.types[given].bitfield.xmmword
1929 && !t->operand_types[wanted].bitfield.xmmword)
1930 || (i.types[given].bitfield.ymmword
1931 && !t->operand_types[wanted].bitfield.ymmword)
1932 || (i.types[given].bitfield.zmmword
1933 && !t->operand_types[wanted].bitfield.zmmword));
1936 /* Return 1 if there is no conflict in any size between operand GIVEN
1937 and opeand WANTED for instruction template T. */
1940 match_mem_size (const insn_template *t, unsigned int wanted,
1943 return (match_operand_size (t, wanted, given)
1944 && !((i.types[given].bitfield.unspecified
1946 && !t->operand_types[wanted].bitfield.unspecified)
1947 || (i.types[given].bitfield.fword
1948 && !t->operand_types[wanted].bitfield.fword)
1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1953 || ((t->operand_types[wanted].bitfield.regsimd
1954 && !t->opcode_modifier.broadcast
1955 && (t->operand_types[wanted].bitfield.byte
1956 || t->operand_types[wanted].bitfield.word
1957 || t->operand_types[wanted].bitfield.dword
1958 || t->operand_types[wanted].bitfield.qword))
1959 ? (i.types[given].bitfield.xmmword
1960 || i.types[given].bitfield.ymmword
1961 || i.types[given].bitfield.zmmword)
1962 : !match_simd_size(t, wanted, given))));
1965 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1966 operands for instruction template T, and it has MATCH_REVERSE set if there
1967 is no size conflict on any operands for the template with operands reversed
1968 (and the template allows for reversing in the first place). */
1970 #define MATCH_STRAIGHT 1
1971 #define MATCH_REVERSE 2
1973 static INLINE unsigned int
1974 operand_size_match (const insn_template *t)
1976 unsigned int j, match = MATCH_STRAIGHT;
1978 /* Don't check jump instructions. */
1979 if (t->opcode_modifier.jump
1980 || t->opcode_modifier.jumpbyte
1981 || t->opcode_modifier.jumpdword
1982 || t->opcode_modifier.jumpintersegment)
1985 /* Check memory and accumulator operand size. */
1986 for (j = 0; j < i.operands; j++)
1988 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1989 && t->operand_types[j].bitfield.anysize)
1992 if (t->operand_types[j].bitfield.reg
1993 && !match_operand_size (t, j, j))
1999 if (t->operand_types[j].bitfield.regsimd
2000 && !match_simd_size (t, j, j))
2006 if (t->operand_types[j].bitfield.acc
2007 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2013 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
2020 if (!t->opcode_modifier.d)
2024 i.error = operand_size_mismatch;
2028 /* Check reverse. */
2029 gas_assert (i.operands == 2);
2031 for (j = 0; j < 2; j++)
2033 if ((t->operand_types[j].bitfield.reg
2034 || t->operand_types[j].bitfield.acc)
2035 && !match_operand_size (t, j, !j))
2038 if (i.types[!j].bitfield.mem
2039 && !match_mem_size (t, j, !j))
2043 return match | MATCH_REVERSE;
2047 operand_type_match (i386_operand_type overlap,
2048 i386_operand_type given)
2050 i386_operand_type temp = overlap;
2052 temp.bitfield.jumpabsolute = 0;
2053 temp.bitfield.unspecified = 0;
2054 temp.bitfield.byte = 0;
2055 temp.bitfield.word = 0;
2056 temp.bitfield.dword = 0;
2057 temp.bitfield.fword = 0;
2058 temp.bitfield.qword = 0;
2059 temp.bitfield.tbyte = 0;
2060 temp.bitfield.xmmword = 0;
2061 temp.bitfield.ymmword = 0;
2062 temp.bitfield.zmmword = 0;
2063 if (operand_type_all_zero (&temp))
2066 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2067 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2071 i.error = operand_type_mismatch;
2075 /* If given types g0 and g1 are registers they must be of the same type
2076 unless the expected operand type register overlap is null.
2077 Memory operand size of certain SIMD instructions is also being checked
2081 operand_type_register_match (i386_operand_type g0,
2082 i386_operand_type t0,
2083 i386_operand_type g1,
2084 i386_operand_type t1)
2086 if (!g0.bitfield.reg
2087 && !g0.bitfield.regsimd
2088 && (!operand_type_check (g0, anymem)
2089 || g0.bitfield.unspecified
2090 || !t0.bitfield.regsimd))
2093 if (!g1.bitfield.reg
2094 && !g1.bitfield.regsimd
2095 && (!operand_type_check (g1, anymem)
2096 || g1.bitfield.unspecified
2097 || !t1.bitfield.regsimd))
2100 if (g0.bitfield.byte == g1.bitfield.byte
2101 && g0.bitfield.word == g1.bitfield.word
2102 && g0.bitfield.dword == g1.bitfield.dword
2103 && g0.bitfield.qword == g1.bitfield.qword
2104 && g0.bitfield.xmmword == g1.bitfield.xmmword
2105 && g0.bitfield.ymmword == g1.bitfield.ymmword
2106 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2109 if (!(t0.bitfield.byte & t1.bitfield.byte)
2110 && !(t0.bitfield.word & t1.bitfield.word)
2111 && !(t0.bitfield.dword & t1.bitfield.dword)
2112 && !(t0.bitfield.qword & t1.bitfield.qword)
2113 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2114 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2115 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2118 i.error = register_type_mismatch;
2123 static INLINE unsigned int
2124 register_number (const reg_entry *r)
2126 unsigned int nr = r->reg_num;
2128 if (r->reg_flags & RegRex)
2131 if (r->reg_flags & RegVRex)
2137 static INLINE unsigned int
2138 mode_from_disp_size (i386_operand_type t)
2140 if (t.bitfield.disp8)
2142 else if (t.bitfield.disp16
2143 || t.bitfield.disp32
2144 || t.bitfield.disp32s)
2151 fits_in_signed_byte (addressT num)
2153 return num + 0x80 <= 0xff;
2157 fits_in_unsigned_byte (addressT num)
2163 fits_in_unsigned_word (addressT num)
2165 return num <= 0xffff;
2169 fits_in_signed_word (addressT num)
2171 return num + 0x8000 <= 0xffff;
2175 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2180 return num + 0x80000000 <= 0xffffffff;
2182 } /* fits_in_signed_long() */
2185 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2190 return num <= 0xffffffff;
2192 } /* fits_in_unsigned_long() */
2195 fits_in_disp8 (offsetT num)
2197 int shift = i.memshift;
2203 mask = (1 << shift) - 1;
2205 /* Return 0 if NUM isn't properly aligned. */
2209 /* Check if NUM will fit in 8bit after shift. */
2210 return fits_in_signed_byte (num >> shift);
2214 fits_in_imm4 (offsetT num)
2216 return (num & 0xf) == num;
2219 static i386_operand_type
2220 smallest_imm_type (offsetT num)
2222 i386_operand_type t;
2224 operand_type_set (&t, 0);
2225 t.bitfield.imm64 = 1;
2227 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2229 /* This code is disabled on the 486 because all the Imm1 forms
2230 in the opcode table are slower on the i486. They're the
2231 versions with the implicitly specified single-position
2232 displacement, which has another syntax if you really want to
2234 t.bitfield.imm1 = 1;
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm8s = 1;
2237 t.bitfield.imm16 = 1;
2238 t.bitfield.imm32 = 1;
2239 t.bitfield.imm32s = 1;
2241 else if (fits_in_signed_byte (num))
2243 t.bitfield.imm8 = 1;
2244 t.bitfield.imm8s = 1;
2245 t.bitfield.imm16 = 1;
2246 t.bitfield.imm32 = 1;
2247 t.bitfield.imm32s = 1;
2249 else if (fits_in_unsigned_byte (num))
2251 t.bitfield.imm8 = 1;
2252 t.bitfield.imm16 = 1;
2253 t.bitfield.imm32 = 1;
2254 t.bitfield.imm32s = 1;
2256 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2258 t.bitfield.imm16 = 1;
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2262 else if (fits_in_signed_long (num))
2264 t.bitfield.imm32 = 1;
2265 t.bitfield.imm32s = 1;
2267 else if (fits_in_unsigned_long (num))
2268 t.bitfield.imm32 = 1;
2274 offset_in_range (offsetT val, int size)
2280 case 1: mask = ((addressT) 1 << 8) - 1; break;
2281 case 2: mask = ((addressT) 1 << 16) - 1; break;
2282 case 4: mask = ((addressT) 2 << 31) - 1; break;
2284 case 8: mask = ((addressT) 2 << 63) - 1; break;
2290 /* If BFD64, sign extend val for 32bit address mode. */
2291 if (flag_code != CODE_64BIT
2292 || i.prefix[ADDR_PREFIX])
2293 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2294 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2297 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2299 char buf1[40], buf2[40];
2301 sprint_value (buf1, val);
2302 sprint_value (buf2, val & mask);
2303 as_warn (_("%s shortened to %s"), buf1, buf2);
2318 a. PREFIX_EXIST if attempting to add a prefix where one from the
2319 same class already exists.
2320 b. PREFIX_LOCK if lock prefix is added.
2321 c. PREFIX_REP if rep/repne prefix is added.
2322 d. PREFIX_DS if ds prefix is added.
2323 e. PREFIX_OTHER if other prefix is added.
2326 static enum PREFIX_GROUP
2327 add_prefix (unsigned int prefix)
2329 enum PREFIX_GROUP ret = PREFIX_OTHER;
2332 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2333 && flag_code == CODE_64BIT)
2335 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2336 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2337 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2338 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2349 case DS_PREFIX_OPCODE:
2352 case CS_PREFIX_OPCODE:
2353 case ES_PREFIX_OPCODE:
2354 case FS_PREFIX_OPCODE:
2355 case GS_PREFIX_OPCODE:
2356 case SS_PREFIX_OPCODE:
2360 case REPNE_PREFIX_OPCODE:
2361 case REPE_PREFIX_OPCODE:
2366 case LOCK_PREFIX_OPCODE:
2375 case ADDR_PREFIX_OPCODE:
2379 case DATA_PREFIX_OPCODE:
2383 if (i.prefix[q] != 0)
2391 i.prefix[q] |= prefix;
2394 as_bad (_("same type of prefix used twice"));
2400 update_code_flag (int value, int check)
2402 PRINTF_LIKE ((*as_error));
2404 flag_code = (enum flag_code) value;
2405 if (flag_code == CODE_64BIT)
2407 cpu_arch_flags.bitfield.cpu64 = 1;
2408 cpu_arch_flags.bitfield.cpuno64 = 0;
2412 cpu_arch_flags.bitfield.cpu64 = 0;
2413 cpu_arch_flags.bitfield.cpuno64 = 1;
2415 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2418 as_error = as_fatal;
2421 (*as_error) (_("64bit mode not supported on `%s'."),
2422 cpu_arch_name ? cpu_arch_name : default_arch);
2424 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2427 as_error = as_fatal;
2430 (*as_error) (_("32bit mode not supported on `%s'."),
2431 cpu_arch_name ? cpu_arch_name : default_arch);
2433 stackop_size = '\0';
2437 set_code_flag (int value)
2439 update_code_flag (value, 0);
2443 set_16bit_gcc_code_flag (int new_code_flag)
2445 flag_code = (enum flag_code) new_code_flag;
2446 if (flag_code != CODE_16BIT)
2448 cpu_arch_flags.bitfield.cpu64 = 0;
2449 cpu_arch_flags.bitfield.cpuno64 = 1;
2450 stackop_size = LONG_MNEM_SUFFIX;
2454 set_intel_syntax (int syntax_flag)
2456 /* Find out if register prefixing is specified. */
2457 int ask_naked_reg = 0;
2460 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2463 int e = get_symbol_name (&string);
2465 if (strcmp (string, "prefix") == 0)
2467 else if (strcmp (string, "noprefix") == 0)
2470 as_bad (_("bad argument to syntax directive."));
2471 (void) restore_line_pointer (e);
2473 demand_empty_rest_of_line ();
2475 intel_syntax = syntax_flag;
2477 if (ask_naked_reg == 0)
2478 allow_naked_reg = (intel_syntax
2479 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2481 allow_naked_reg = (ask_naked_reg < 0);
2483 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2485 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2486 identifier_chars['$'] = intel_syntax ? '$' : 0;
2487 register_prefix = allow_naked_reg ? "" : "%";
2491 set_intel_mnemonic (int mnemonic_flag)
2493 intel_mnemonic = mnemonic_flag;
2497 set_allow_index_reg (int flag)
2499 allow_index_reg = flag;
2503 set_check (int what)
2505 enum check_kind *kind;
2510 kind = &operand_check;
2521 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2524 int e = get_symbol_name (&string);
2526 if (strcmp (string, "none") == 0)
2528 else if (strcmp (string, "warning") == 0)
2529 *kind = check_warning;
2530 else if (strcmp (string, "error") == 0)
2531 *kind = check_error;
2533 as_bad (_("bad argument to %s_check directive."), str);
2534 (void) restore_line_pointer (e);
2537 as_bad (_("missing argument for %s_check directive"), str);
2539 demand_empty_rest_of_line ();
2543 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2544 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2547 static const char *arch;
2549 /* Intel LIOM is only supported on ELF. */
2555 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2556 use default_arch. */
2557 arch = cpu_arch_name;
2559 arch = default_arch;
2562 /* If we are targeting Intel MCU, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2564 || new_flag.bitfield.cpuiamcu)
2567 /* If we are targeting Intel L1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2569 || new_flag.bitfield.cpul1om)
2572 /* If we are targeting Intel K1OM, we must enable it. */
2573 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2574 || new_flag.bitfield.cpuk1om)
2577 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2582 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2586 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2589 int e = get_symbol_name (&string);
2591 i386_cpu_flags flags;
2593 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2595 if (strcmp (string, cpu_arch[j].name) == 0)
2597 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2601 cpu_arch_name = cpu_arch[j].name;
2602 cpu_sub_arch_name = NULL;
2603 cpu_arch_flags = cpu_arch[j].flags;
2604 if (flag_code == CODE_64BIT)
2606 cpu_arch_flags.bitfield.cpu64 = 1;
2607 cpu_arch_flags.bitfield.cpuno64 = 0;
2611 cpu_arch_flags.bitfield.cpu64 = 0;
2612 cpu_arch_flags.bitfield.cpuno64 = 1;
2614 cpu_arch_isa = cpu_arch[j].type;
2615 cpu_arch_isa_flags = cpu_arch[j].flags;
2616 if (!cpu_arch_tune_set)
2618 cpu_arch_tune = cpu_arch_isa;
2619 cpu_arch_tune_flags = cpu_arch_isa_flags;
2624 flags = cpu_flags_or (cpu_arch_flags,
2627 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2629 if (cpu_sub_arch_name)
2631 char *name = cpu_sub_arch_name;
2632 cpu_sub_arch_name = concat (name,
2634 (const char *) NULL);
2638 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2639 cpu_arch_flags = flags;
2640 cpu_arch_isa_flags = flags;
2644 = cpu_flags_or (cpu_arch_isa_flags,
2646 (void) restore_line_pointer (e);
2647 demand_empty_rest_of_line ();
2652 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2654 /* Disable an ISA extension. */
2655 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2656 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2658 flags = cpu_flags_and_not (cpu_arch_flags,
2659 cpu_noarch[j].flags);
2660 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2662 if (cpu_sub_arch_name)
2664 char *name = cpu_sub_arch_name;
2665 cpu_sub_arch_name = concat (name, string,
2666 (const char *) NULL);
2670 cpu_sub_arch_name = xstrdup (string);
2671 cpu_arch_flags = flags;
2672 cpu_arch_isa_flags = flags;
2674 (void) restore_line_pointer (e);
2675 demand_empty_rest_of_line ();
2679 j = ARRAY_SIZE (cpu_arch);
2682 if (j >= ARRAY_SIZE (cpu_arch))
2683 as_bad (_("no such architecture: `%s'"), string);
2685 *input_line_pointer = e;
2688 as_bad (_("missing cpu architecture"));
2690 no_cond_jump_promotion = 0;
2691 if (*input_line_pointer == ','
2692 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2697 ++input_line_pointer;
2698 e = get_symbol_name (&string);
2700 if (strcmp (string, "nojumps") == 0)
2701 no_cond_jump_promotion = 1;
2702 else if (strcmp (string, "jumps") == 0)
2705 as_bad (_("no such architecture modifier: `%s'"), string);
2707 (void) restore_line_pointer (e);
2710 demand_empty_rest_of_line ();
2713 enum bfd_architecture
2716 if (cpu_arch_isa == PROCESSOR_L1OM)
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code != CODE_64BIT)
2720 as_fatal (_("Intel L1OM is 64bit ELF only"));
2721 return bfd_arch_l1om;
2723 else if (cpu_arch_isa == PROCESSOR_K1OM)
2725 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2726 || flag_code != CODE_64BIT)
2727 as_fatal (_("Intel K1OM is 64bit ELF only"));
2728 return bfd_arch_k1om;
2730 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2732 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2733 || flag_code == CODE_64BIT)
2734 as_fatal (_("Intel MCU is 32bit ELF only"));
2735 return bfd_arch_iamcu;
2738 return bfd_arch_i386;
2744 if (!strncmp (default_arch, "x86_64", 6))
2746 if (cpu_arch_isa == PROCESSOR_L1OM)
2748 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2749 || default_arch[6] != '\0')
2750 as_fatal (_("Intel L1OM is 64bit ELF only"));
2751 return bfd_mach_l1om;
2753 else if (cpu_arch_isa == PROCESSOR_K1OM)
2755 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2756 || default_arch[6] != '\0')
2757 as_fatal (_("Intel K1OM is 64bit ELF only"));
2758 return bfd_mach_k1om;
2760 else if (default_arch[6] == '\0')
2761 return bfd_mach_x86_64;
2763 return bfd_mach_x64_32;
2765 else if (!strcmp (default_arch, "i386")
2766 || !strcmp (default_arch, "iamcu"))
2768 if (cpu_arch_isa == PROCESSOR_IAMCU)
2770 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2771 as_fatal (_("Intel MCU is 32bit ELF only"));
2772 return bfd_mach_i386_iamcu;
2775 return bfd_mach_i386_i386;
2778 as_fatal (_("unknown architecture"));
2784 const char *hash_err;
2786 /* Support pseudo prefixes like {disp32}. */
2787 lex_type ['{'] = LEX_BEGIN_NAME;
2789 /* Initialize op_hash hash table. */
2790 op_hash = hash_new ();
2793 const insn_template *optab;
2794 templates *core_optab;
2796 /* Setup for loop. */
2798 core_optab = XNEW (templates);
2799 core_optab->start = optab;
2804 if (optab->name == NULL
2805 || strcmp (optab->name, (optab - 1)->name) != 0)
2807 /* different name --> ship out current template list;
2808 add to hash table; & begin anew. */
2809 core_optab->end = optab;
2810 hash_err = hash_insert (op_hash,
2812 (void *) core_optab);
2815 as_fatal (_("can't hash %s: %s"),
2819 if (optab->name == NULL)
2821 core_optab = XNEW (templates);
2822 core_optab->start = optab;
2827 /* Initialize reg_hash hash table. */
2828 reg_hash = hash_new ();
2830 const reg_entry *regtab;
2831 unsigned int regtab_size = i386_regtab_size;
2833 for (regtab = i386_regtab; regtab_size--; regtab++)
2835 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2837 as_fatal (_("can't hash %s: %s"),
2843 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2848 for (c = 0; c < 256; c++)
2853 mnemonic_chars[c] = c;
2854 register_chars[c] = c;
2855 operand_chars[c] = c;
2857 else if (ISLOWER (c))
2859 mnemonic_chars[c] = c;
2860 register_chars[c] = c;
2861 operand_chars[c] = c;
2863 else if (ISUPPER (c))
2865 mnemonic_chars[c] = TOLOWER (c);
2866 register_chars[c] = mnemonic_chars[c];
2867 operand_chars[c] = c;
2869 else if (c == '{' || c == '}')
2871 mnemonic_chars[c] = c;
2872 operand_chars[c] = c;
2875 if (ISALPHA (c) || ISDIGIT (c))
2876 identifier_chars[c] = c;
2879 identifier_chars[c] = c;
2880 operand_chars[c] = c;
2885 identifier_chars['@'] = '@';
2888 identifier_chars['?'] = '?';
2889 operand_chars['?'] = '?';
2891 digit_chars['-'] = '-';
2892 mnemonic_chars['_'] = '_';
2893 mnemonic_chars['-'] = '-';
2894 mnemonic_chars['.'] = '.';
2895 identifier_chars['_'] = '_';
2896 identifier_chars['.'] = '.';
2898 for (p = operand_special_chars; *p != '\0'; p++)
2899 operand_chars[(unsigned char) *p] = *p;
2902 if (flag_code == CODE_64BIT)
2904 #if defined (OBJ_COFF) && defined (TE_PE)
2905 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2908 x86_dwarf2_return_column = 16;
2910 x86_cie_data_alignment = -8;
2914 x86_dwarf2_return_column = 8;
2915 x86_cie_data_alignment = -4;
2920 i386_print_statistics (FILE *file)
2922 hash_print_statistics (file, "i386 opcode", op_hash);
2923 hash_print_statistics (file, "i386 register", reg_hash);
2928 /* Debugging routines for md_assemble. */
2929 static void pte (insn_template *);
2930 static void pt (i386_operand_type);
2931 static void pe (expressionS *);
2932 static void ps (symbolS *);
2935 pi (char *line, i386_insn *x)
2939 fprintf (stdout, "%s: template ", line);
2941 fprintf (stdout, " address: base %s index %s scale %x\n",
2942 x->base_reg ? x->base_reg->reg_name : "none",
2943 x->index_reg ? x->index_reg->reg_name : "none",
2944 x->log2_scale_factor);
2945 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2946 x->rm.mode, x->rm.reg, x->rm.regmem);
2947 fprintf (stdout, " sib: base %x index %x scale %x\n",
2948 x->sib.base, x->sib.index, x->sib.scale);
2949 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2950 (x->rex & REX_W) != 0,
2951 (x->rex & REX_R) != 0,
2952 (x->rex & REX_X) != 0,
2953 (x->rex & REX_B) != 0);
2954 for (j = 0; j < x->operands; j++)
2956 fprintf (stdout, " #%d: ", j + 1);
2958 fprintf (stdout, "\n");
2959 if (x->types[j].bitfield.reg
2960 || x->types[j].bitfield.regmmx
2961 || x->types[j].bitfield.regsimd
2962 || x->types[j].bitfield.sreg2
2963 || x->types[j].bitfield.sreg3
2964 || x->types[j].bitfield.control
2965 || x->types[j].bitfield.debug
2966 || x->types[j].bitfield.test)
2967 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2968 if (operand_type_check (x->types[j], imm))
2970 if (operand_type_check (x->types[j], disp))
2971 pe (x->op[j].disps);
2976 pte (insn_template *t)
2979 fprintf (stdout, " %d operands ", t->operands);
2980 fprintf (stdout, "opcode %x ", t->base_opcode);
2981 if (t->extension_opcode != None)
2982 fprintf (stdout, "ext %x ", t->extension_opcode);
2983 if (t->opcode_modifier.d)
2984 fprintf (stdout, "D");
2985 if (t->opcode_modifier.w)
2986 fprintf (stdout, "W");
2987 fprintf (stdout, "\n");
2988 for (j = 0; j < t->operands; j++)
2990 fprintf (stdout, " #%d type ", j + 1);
2991 pt (t->operand_types[j]);
2992 fprintf (stdout, "\n");
2999 fprintf (stdout, " operation %d\n", e->X_op);
3000 fprintf (stdout, " add_number %ld (%lx)\n",
3001 (long) e->X_add_number, (long) e->X_add_number);
3002 if (e->X_add_symbol)
3004 fprintf (stdout, " add_symbol ");
3005 ps (e->X_add_symbol);
3006 fprintf (stdout, "\n");
3010 fprintf (stdout, " op_symbol ");
3011 ps (e->X_op_symbol);
3012 fprintf (stdout, "\n");
3019 fprintf (stdout, "%s type %s%s",
3021 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3022 segment_name (S_GET_SEGMENT (s)));
3025 static struct type_name
3027 i386_operand_type mask;
3030 const type_names[] =
3032 { OPERAND_TYPE_REG8, "r8" },
3033 { OPERAND_TYPE_REG16, "r16" },
3034 { OPERAND_TYPE_REG32, "r32" },
3035 { OPERAND_TYPE_REG64, "r64" },
3036 { OPERAND_TYPE_IMM8, "i8" },
3037 { OPERAND_TYPE_IMM8, "i8s" },
3038 { OPERAND_TYPE_IMM16, "i16" },
3039 { OPERAND_TYPE_IMM32, "i32" },
3040 { OPERAND_TYPE_IMM32S, "i32s" },
3041 { OPERAND_TYPE_IMM64, "i64" },
3042 { OPERAND_TYPE_IMM1, "i1" },
3043 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3044 { OPERAND_TYPE_DISP8, "d8" },
3045 { OPERAND_TYPE_DISP16, "d16" },
3046 { OPERAND_TYPE_DISP32, "d32" },
3047 { OPERAND_TYPE_DISP32S, "d32s" },
3048 { OPERAND_TYPE_DISP64, "d64" },
3049 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3050 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3051 { OPERAND_TYPE_CONTROL, "control reg" },
3052 { OPERAND_TYPE_TEST, "test reg" },
3053 { OPERAND_TYPE_DEBUG, "debug reg" },
3054 { OPERAND_TYPE_FLOATREG, "FReg" },
3055 { OPERAND_TYPE_FLOATACC, "FAcc" },
3056 { OPERAND_TYPE_SREG2, "SReg2" },
3057 { OPERAND_TYPE_SREG3, "SReg3" },
3058 { OPERAND_TYPE_ACC, "Acc" },
3059 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3060 { OPERAND_TYPE_REGMMX, "rMMX" },
3061 { OPERAND_TYPE_REGXMM, "rXMM" },
3062 { OPERAND_TYPE_REGYMM, "rYMM" },
3063 { OPERAND_TYPE_REGZMM, "rZMM" },
3064 { OPERAND_TYPE_REGMASK, "Mask reg" },
3065 { OPERAND_TYPE_ESSEG, "es" },
3069 pt (i386_operand_type t)
3072 i386_operand_type a;
3074 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3076 a = operand_type_and (t, type_names[j].mask);
3077 if (!operand_type_all_zero (&a))
3078 fprintf (stdout, "%s, ", type_names[j].name);
3083 #endif /* DEBUG386 */
3085 static bfd_reloc_code_real_type
3086 reloc (unsigned int size,
3089 bfd_reloc_code_real_type other)
3091 if (other != NO_RELOC)
3093 reloc_howto_type *rel;
3098 case BFD_RELOC_X86_64_GOT32:
3099 return BFD_RELOC_X86_64_GOT64;
3101 case BFD_RELOC_X86_64_GOTPLT64:
3102 return BFD_RELOC_X86_64_GOTPLT64;
3104 case BFD_RELOC_X86_64_PLTOFF64:
3105 return BFD_RELOC_X86_64_PLTOFF64;
3107 case BFD_RELOC_X86_64_GOTPC32:
3108 other = BFD_RELOC_X86_64_GOTPC64;
3110 case BFD_RELOC_X86_64_GOTPCREL:
3111 other = BFD_RELOC_X86_64_GOTPCREL64;
3113 case BFD_RELOC_X86_64_TPOFF32:
3114 other = BFD_RELOC_X86_64_TPOFF64;
3116 case BFD_RELOC_X86_64_DTPOFF32:
3117 other = BFD_RELOC_X86_64_DTPOFF64;
3123 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3124 if (other == BFD_RELOC_SIZE32)
3127 other = BFD_RELOC_SIZE64;
3130 as_bad (_("there are no pc-relative size relocations"));
3136 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3137 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3140 rel = bfd_reloc_type_lookup (stdoutput, other);
3142 as_bad (_("unknown relocation (%u)"), other);
3143 else if (size != bfd_get_reloc_size (rel))
3144 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3145 bfd_get_reloc_size (rel),
3147 else if (pcrel && !rel->pc_relative)
3148 as_bad (_("non-pc-relative relocation for pc-relative field"));
3149 else if ((rel->complain_on_overflow == complain_overflow_signed
3151 || (rel->complain_on_overflow == complain_overflow_unsigned
3153 as_bad (_("relocated field and relocation type differ in signedness"));
3162 as_bad (_("there are no unsigned pc-relative relocations"));
3165 case 1: return BFD_RELOC_8_PCREL;
3166 case 2: return BFD_RELOC_16_PCREL;
3167 case 4: return BFD_RELOC_32_PCREL;
3168 case 8: return BFD_RELOC_64_PCREL;
3170 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3177 case 4: return BFD_RELOC_X86_64_32S;
3182 case 1: return BFD_RELOC_8;
3183 case 2: return BFD_RELOC_16;
3184 case 4: return BFD_RELOC_32;
3185 case 8: return BFD_RELOC_64;
3187 as_bad (_("cannot do %s %u byte relocation"),
3188 sign > 0 ? "signed" : "unsigned", size);
3194 /* Here we decide which fixups can be adjusted to make them relative to
3195 the beginning of the section instead of the symbol. Basically we need
3196 to make sure that the dynamic relocations are done correctly, so in
3197 some cases we force the original symbol to be used. */
3200 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3206 /* Don't adjust pc-relative references to merge sections in 64-bit
3208 if (use_rela_relocations
3209 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3213 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3214 and changed later by validate_fix. */
3215 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3216 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3219 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3220 for size relocations. */
3221 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3222 || fixP->fx_r_type == BFD_RELOC_SIZE64
3223 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3224 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3225 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3226 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3235 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3236 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3245 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3247 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3249 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3250 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3251 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3252 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3253 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3260 intel_float_operand (const char *mnemonic)
3262 /* Note that the value returned is meaningful only for opcodes with (memory)
3263 operands, hence the code here is free to improperly handle opcodes that
3264 have no operands (for better performance and smaller code). */
3266 if (mnemonic[0] != 'f')
3267 return 0; /* non-math */
3269 switch (mnemonic[1])
3271 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3272 the fs segment override prefix not currently handled because no
3273 call path can make opcodes without operands get here */
3275 return 2 /* integer op */;
3277 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3278 return 3; /* fldcw/fldenv */
3281 if (mnemonic[2] != 'o' /* fnop */)
3282 return 3; /* non-waiting control op */
3285 if (mnemonic[2] == 's')
3286 return 3; /* frstor/frstpm */
3289 if (mnemonic[2] == 'a')
3290 return 3; /* fsave */
3291 if (mnemonic[2] == 't')
3293 switch (mnemonic[3])
3295 case 'c': /* fstcw */
3296 case 'd': /* fstdw */
3297 case 'e': /* fstenv */
3298 case 's': /* fsts[gw] */
3304 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3305 return 0; /* fxsave/fxrstor are not really math ops */
3312 /* Build the VEX prefix. */
3315 build_vex_prefix (const insn_template *t)
3317 unsigned int register_specifier;
3318 unsigned int implied_prefix;
3319 unsigned int vector_length;
3321 /* Check register specifier. */
3322 if (i.vex.register_specifier)
3324 register_specifier =
3325 ~register_number (i.vex.register_specifier) & 0xf;
3326 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3329 register_specifier = 0xf;
3331 /* Use 2-byte VEX prefix by swapping destination and source
3333 if (i.vec_encoding != vex_encoding_vex3
3334 && i.dir_encoding == dir_encoding_default
3335 && i.operands == i.reg_operands
3336 && i.tm.opcode_modifier.vexopcode == VEX0F
3337 && i.tm.opcode_modifier.load
3340 unsigned int xchg = i.operands - 1;
3341 union i386_op temp_op;
3342 i386_operand_type temp_type;
3344 temp_type = i.types[xchg];
3345 i.types[xchg] = i.types[0];
3346 i.types[0] = temp_type;
3347 temp_op = i.op[xchg];
3348 i.op[xchg] = i.op[0];
3351 gas_assert (i.rm.mode == 3);
3355 i.rm.regmem = i.rm.reg;
3358 /* Use the next insn. */
3362 if (i.tm.opcode_modifier.vex == VEXScalar)
3363 vector_length = avxscalar;
3364 else if (i.tm.opcode_modifier.vex == VEX256)
3370 /* Determine vector length from the last multi-length vector
3373 for (op = t->operands; op--;)
3374 if (t->operand_types[op].bitfield.xmmword
3375 && t->operand_types[op].bitfield.ymmword
3376 && i.types[op].bitfield.ymmword)
3383 switch ((i.tm.base_opcode >> 8) & 0xff)
3388 case DATA_PREFIX_OPCODE:
3391 case REPE_PREFIX_OPCODE:
3394 case REPNE_PREFIX_OPCODE:
3401 /* Use 2-byte VEX prefix if possible. */
3402 if (i.vec_encoding != vex_encoding_vex3
3403 && i.tm.opcode_modifier.vexopcode == VEX0F
3404 && i.tm.opcode_modifier.vexw != VEXW1
3405 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3407 /* 2-byte VEX prefix. */
3411 i.vex.bytes[0] = 0xc5;
3413 /* Check the REX.R bit. */
3414 r = (i.rex & REX_R) ? 0 : 1;
3415 i.vex.bytes[1] = (r << 7
3416 | register_specifier << 3
3417 | vector_length << 2
3422 /* 3-byte VEX prefix. */
3427 switch (i.tm.opcode_modifier.vexopcode)
3431 i.vex.bytes[0] = 0xc4;
3435 i.vex.bytes[0] = 0xc4;
3439 i.vex.bytes[0] = 0xc4;
3443 i.vex.bytes[0] = 0x8f;
3447 i.vex.bytes[0] = 0x8f;
3451 i.vex.bytes[0] = 0x8f;
3457 /* The high 3 bits of the second VEX byte are 1's compliment
3458 of RXB bits from REX. */
3459 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3461 /* Check the REX.W bit. */
3462 w = (i.rex & REX_W) ? 1 : 0;
3463 if (i.tm.opcode_modifier.vexw == VEXW1)
3466 i.vex.bytes[2] = (w << 7
3467 | register_specifier << 3
3468 | vector_length << 2
3473 static INLINE bfd_boolean
3474 is_evex_encoding (const insn_template *t)
3476 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3477 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3478 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3481 static INLINE bfd_boolean
3482 is_any_vex_encoding (const insn_template *t)
3484 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3485 || is_evex_encoding (t);
3488 /* Build the EVEX prefix. */
3491 build_evex_prefix (void)
3493 unsigned int register_specifier;
3494 unsigned int implied_prefix;
3496 rex_byte vrex_used = 0;
3498 /* Check register specifier. */
3499 if (i.vex.register_specifier)
3501 gas_assert ((i.vrex & REX_X) == 0);
3503 register_specifier = i.vex.register_specifier->reg_num;
3504 if ((i.vex.register_specifier->reg_flags & RegRex))
3505 register_specifier += 8;
3506 /* The upper 16 registers are encoded in the fourth byte of the
3508 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3509 i.vex.bytes[3] = 0x8;
3510 register_specifier = ~register_specifier & 0xf;
3514 register_specifier = 0xf;
3516 /* Encode upper 16 vector index register in the fourth byte of
3518 if (!(i.vrex & REX_X))
3519 i.vex.bytes[3] = 0x8;
3524 switch ((i.tm.base_opcode >> 8) & 0xff)
3529 case DATA_PREFIX_OPCODE:
3532 case REPE_PREFIX_OPCODE:
3535 case REPNE_PREFIX_OPCODE:
3542 /* 4 byte EVEX prefix. */
3544 i.vex.bytes[0] = 0x62;
3547 switch (i.tm.opcode_modifier.vexopcode)
3563 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3565 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3567 /* The fifth bit of the second EVEX byte is 1's compliment of the
3568 REX_R bit in VREX. */
3569 if (!(i.vrex & REX_R))
3570 i.vex.bytes[1] |= 0x10;
3574 if ((i.reg_operands + i.imm_operands) == i.operands)
3576 /* When all operands are registers, the REX_X bit in REX is not
3577 used. We reuse it to encode the upper 16 registers, which is
3578 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3579 as 1's compliment. */
3580 if ((i.vrex & REX_B))
3583 i.vex.bytes[1] &= ~0x40;
3587 /* EVEX instructions shouldn't need the REX prefix. */
3588 i.vrex &= ~vrex_used;
3589 gas_assert (i.vrex == 0);
3591 /* Check the REX.W bit. */
3592 w = (i.rex & REX_W) ? 1 : 0;
3593 if (i.tm.opcode_modifier.vexw)
3595 if (i.tm.opcode_modifier.vexw == VEXW1)
3598 /* If w is not set it means we are dealing with WIG instruction. */
3601 if (evexwig == evexw1)
3605 /* Encode the U bit. */
3606 implied_prefix |= 0x4;
3608 /* The third byte of the EVEX prefix. */
3609 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3611 /* The fourth byte of the EVEX prefix. */
3612 /* The zeroing-masking bit. */
3613 if (i.mask && i.mask->zeroing)
3614 i.vex.bytes[3] |= 0x80;
3616 /* Don't always set the broadcast bit if there is no RC. */
3619 /* Encode the vector length. */
3620 unsigned int vec_length;
3622 if (!i.tm.opcode_modifier.evex
3623 || i.tm.opcode_modifier.evex == EVEXDYN)
3627 /* Determine vector length from the last multi-length vector
3630 for (op = i.operands; op--;)
3631 if (i.tm.operand_types[op].bitfield.xmmword
3632 + i.tm.operand_types[op].bitfield.ymmword
3633 + i.tm.operand_types[op].bitfield.zmmword > 1)
3635 if (i.types[op].bitfield.zmmword)
3637 i.tm.opcode_modifier.evex = EVEX512;
3640 else if (i.types[op].bitfield.ymmword)
3642 i.tm.opcode_modifier.evex = EVEX256;
3645 else if (i.types[op].bitfield.xmmword)
3647 i.tm.opcode_modifier.evex = EVEX128;
3650 else if (i.broadcast && (int) op == i.broadcast->operand)
3652 switch (i.broadcast->bytes)
3655 i.tm.opcode_modifier.evex = EVEX512;
3658 i.tm.opcode_modifier.evex = EVEX256;
3661 i.tm.opcode_modifier.evex = EVEX128;
3670 if (op >= MAX_OPERANDS)
3674 switch (i.tm.opcode_modifier.evex)
3676 case EVEXLIG: /* LL' is ignored */
3677 vec_length = evexlig << 5;
3680 vec_length = 0 << 5;
3683 vec_length = 1 << 5;
3686 vec_length = 2 << 5;
3692 i.vex.bytes[3] |= vec_length;
3693 /* Encode the broadcast bit. */
3695 i.vex.bytes[3] |= 0x10;
3699 if (i.rounding->type != saeonly)
3700 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3702 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3705 if (i.mask && i.mask->mask)
3706 i.vex.bytes[3] |= i.mask->mask->reg_num;
3710 process_immext (void)
3714 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3717 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3718 with an opcode suffix which is coded in the same place as an
3719 8-bit immediate field would be.
3720 Here we check those operands and remove them afterwards. */
3723 for (x = 0; x < i.operands; x++)
3724 if (register_number (i.op[x].regs) != x)
3725 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3726 register_prefix, i.op[x].regs->reg_name, x + 1,
3732 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3734 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3735 suffix which is coded in the same place as an 8-bit immediate
3737 Here we check those operands and remove them afterwards. */
3740 if (i.operands != 3)
3743 for (x = 0; x < 2; x++)
3744 if (register_number (i.op[x].regs) != x)
3745 goto bad_register_operand;
3747 /* Check for third operand for mwaitx/monitorx insn. */
3748 if (register_number (i.op[x].regs)
3749 != (x + (i.tm.extension_opcode == 0xfb)))
3751 bad_register_operand:
3752 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3753 register_prefix, i.op[x].regs->reg_name, x+1,
3760 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3761 which is coded in the same place as an 8-bit immediate field
3762 would be. Here we fake an 8-bit immediate operand from the
3763 opcode suffix stored in tm.extension_opcode.
3765 AVX instructions also use this encoding, for some of
3766 3 argument instructions. */
3768 gas_assert (i.imm_operands <= 1
3770 || (is_any_vex_encoding (&i.tm)
3771 && i.operands <= 4)));
3773 exp = &im_expressions[i.imm_operands++];
3774 i.op[i.operands].imms = exp;
3775 i.types[i.operands] = imm8;
3777 exp->X_op = O_constant;
3778 exp->X_add_number = i.tm.extension_opcode;
3779 i.tm.extension_opcode = None;
3786 switch (i.tm.opcode_modifier.hleprefixok)
3791 as_bad (_("invalid instruction `%s' after `%s'"),
3792 i.tm.name, i.hle_prefix);
3795 if (i.prefix[LOCK_PREFIX])
3797 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3801 case HLEPrefixRelease:
3802 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3804 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3808 if (i.mem_operands == 0
3809 || !operand_type_check (i.types[i.operands - 1], anymem))
3811 as_bad (_("memory destination needed for instruction `%s'"
3812 " after `xrelease'"), i.tm.name);
3819 /* Try the shortest encoding by shortening operand size. */
3822 optimize_encoding (void)
3826 if (optimize_for_space
3827 && i.reg_operands == 1
3828 && i.imm_operands == 1
3829 && !i.types[1].bitfield.byte
3830 && i.op[0].imms->X_op == O_constant
3831 && fits_in_imm7 (i.op[0].imms->X_add_number)
3832 && ((i.tm.base_opcode == 0xa8
3833 && i.tm.extension_opcode == None)
3834 || (i.tm.base_opcode == 0xf6
3835 && i.tm.extension_opcode == 0x0)))
3838 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3840 unsigned int base_regnum = i.op[1].regs->reg_num;
3841 if (flag_code == CODE_64BIT || base_regnum < 4)
3843 i.types[1].bitfield.byte = 1;
3844 /* Ignore the suffix. */
3846 if (base_regnum >= 4
3847 && !(i.op[1].regs->reg_flags & RegRex))
3849 /* Handle SP, BP, SI and DI registers. */
3850 if (i.types[1].bitfield.word)
3852 else if (i.types[1].bitfield.dword)
3860 else if (flag_code == CODE_64BIT
3861 && ((i.types[1].bitfield.qword
3862 && i.reg_operands == 1
3863 && i.imm_operands == 1
3864 && i.op[0].imms->X_op == O_constant
3865 && ((i.tm.base_opcode == 0xb0
3866 && i.tm.extension_opcode == None
3867 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3868 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3869 && (((i.tm.base_opcode == 0x24
3870 || i.tm.base_opcode == 0xa8)
3871 && i.tm.extension_opcode == None)
3872 || (i.tm.base_opcode == 0x80
3873 && i.tm.extension_opcode == 0x4)
3874 || ((i.tm.base_opcode == 0xf6
3875 || i.tm.base_opcode == 0xc6)
3876 && i.tm.extension_opcode == 0x0)))))
3877 || (i.types[0].bitfield.qword
3878 && ((i.reg_operands == 2
3879 && i.op[0].regs == i.op[1].regs
3880 && ((i.tm.base_opcode == 0x30
3881 || i.tm.base_opcode == 0x28)
3882 && i.tm.extension_opcode == None))
3883 || (i.reg_operands == 1
3885 && i.tm.base_opcode == 0x30
3886 && i.tm.extension_opcode == None)))))
3889 andq $imm31, %r64 -> andl $imm31, %r32
3890 testq $imm31, %r64 -> testl $imm31, %r32
3891 xorq %r64, %r64 -> xorl %r32, %r32
3892 subq %r64, %r64 -> subl %r32, %r32
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3896 i.tm.opcode_modifier.norex64 = 1;
3897 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3900 movq $imm31, %r64 -> movl $imm31, %r32
3901 movq $imm32, %r64 -> movl $imm32, %r32
3903 i.tm.operand_types[0].bitfield.imm32 = 1;
3904 i.tm.operand_types[0].bitfield.imm32s = 0;
3905 i.tm.operand_types[0].bitfield.imm64 = 0;
3906 i.types[0].bitfield.imm32 = 1;
3907 i.types[0].bitfield.imm32s = 0;
3908 i.types[0].bitfield.imm64 = 0;
3909 i.types[1].bitfield.dword = 1;
3910 i.types[1].bitfield.qword = 0;
3911 if (i.tm.base_opcode == 0xc6)
3914 movq $imm31, %r64 -> movl $imm31, %r32
3916 i.tm.base_opcode = 0xb0;
3917 i.tm.extension_opcode = None;
3918 i.tm.opcode_modifier.shortform = 1;
3919 i.tm.opcode_modifier.modrm = 0;
3923 else if (optimize > 1
3924 && i.reg_operands == 3
3925 && i.op[0].regs == i.op[1].regs
3926 && !i.types[2].bitfield.xmmword
3927 && (i.tm.opcode_modifier.vex
3928 || ((!i.mask || i.mask->zeroing)
3930 && is_evex_encoding (&i.tm)
3931 && (i.vec_encoding != vex_encoding_evex
3932 || i.tm.cpu_flags.bitfield.cpuavx512vl
3933 || (i.tm.operand_types[2].bitfield.zmmword
3934 && i.types[2].bitfield.ymmword)
3935 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3936 && ((i.tm.base_opcode == 0x55
3937 || i.tm.base_opcode == 0x6655
3938 || i.tm.base_opcode == 0x66df
3939 || i.tm.base_opcode == 0x57
3940 || i.tm.base_opcode == 0x6657
3941 || i.tm.base_opcode == 0x66ef
3942 || i.tm.base_opcode == 0x66f8
3943 || i.tm.base_opcode == 0x66f9
3944 || i.tm.base_opcode == 0x66fa
3945 || i.tm.base_opcode == 0x66fb
3946 || i.tm.base_opcode == 0x42
3947 || i.tm.base_opcode == 0x6642
3948 || i.tm.base_opcode == 0x47
3949 || i.tm.base_opcode == 0x6647)
3950 && i.tm.extension_opcode == None))
3953 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3955 EVEX VOP %zmmM, %zmmM, %zmmN
3956 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3957 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3958 EVEX VOP %ymmM, %ymmM, %ymmN
3959 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3960 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3961 VEX VOP %ymmM, %ymmM, %ymmN
3962 -> VEX VOP %xmmM, %xmmM, %xmmN
3963 VOP, one of vpandn and vpxor:
3964 VEX VOP %ymmM, %ymmM, %ymmN
3965 -> VEX VOP %xmmM, %xmmM, %xmmN
3966 VOP, one of vpandnd and vpandnq:
3967 EVEX VOP %zmmM, %zmmM, %zmmN
3968 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3969 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3970 EVEX VOP %ymmM, %ymmM, %ymmN
3971 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3972 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3973 VOP, one of vpxord and vpxorq:
3974 EVEX VOP %zmmM, %zmmM, %zmmN
3975 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3976 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3977 EVEX VOP %ymmM, %ymmM, %ymmN
3978 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3979 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3980 VOP, one of kxord and kxorq:
3981 VEX VOP %kM, %kM, %kN
3982 -> VEX kxorw %kM, %kM, %kN
3983 VOP, one of kandnd and kandnq:
3984 VEX VOP %kM, %kM, %kN
3985 -> VEX kandnw %kM, %kM, %kN
3987 if (is_evex_encoding (&i.tm))
3989 if (i.vec_encoding == vex_encoding_evex)
3990 i.tm.opcode_modifier.evex = EVEX128;
3993 i.tm.opcode_modifier.vex = VEX128;
3994 i.tm.opcode_modifier.vexw = VEXW0;
3995 i.tm.opcode_modifier.evex = 0;
3998 else if (i.tm.operand_types[0].bitfield.regmask)
4000 i.tm.base_opcode &= 0xff;
4001 i.tm.opcode_modifier.vexw = VEXW0;
4004 i.tm.opcode_modifier.vex = VEX128;
4006 if (i.tm.opcode_modifier.vex)
4007 for (j = 0; j < 3; j++)
4009 i.types[j].bitfield.xmmword = 1;
4010 i.types[j].bitfield.ymmword = 0;
4015 /* This is the guts of the machine-dependent assembler. LINE points to a
4016 machine dependent instruction. This function is supposed to emit
4017 the frags/bytes it assembles to. */
4020 md_assemble (char *line)
4023 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4024 const insn_template *t;
4026 /* Initialize globals. */
4027 memset (&i, '\0', sizeof (i));
4028 for (j = 0; j < MAX_OPERANDS; j++)
4029 i.reloc[j] = NO_RELOC;
4030 memset (disp_expressions, '\0', sizeof (disp_expressions));
4031 memset (im_expressions, '\0', sizeof (im_expressions));
4032 save_stack_p = save_stack;
4034 /* First parse an instruction mnemonic & call i386_operand for the operands.
4035 We assume that the scrubber has arranged it so that line[0] is the valid
4036 start of a (possibly prefixed) mnemonic. */
4038 line = parse_insn (line, mnemonic);
4041 mnem_suffix = i.suffix;
4043 line = parse_operands (line, mnemonic);
4045 xfree (i.memop1_string);
4046 i.memop1_string = NULL;
4050 /* Now we've parsed the mnemonic into a set of templates, and have the
4051 operands at hand. */
4053 /* All intel opcodes have reversed operands except for "bound" and
4054 "enter". We also don't reverse intersegment "jmp" and "call"
4055 instructions with 2 immediate operands so that the immediate segment
4056 precedes the offset, as it does when in AT&T mode. */
4059 && (strcmp (mnemonic, "bound") != 0)
4060 && (strcmp (mnemonic, "invlpga") != 0)
4061 && !(operand_type_check (i.types[0], imm)
4062 && operand_type_check (i.types[1], imm)))
4065 /* The order of the immediates should be reversed
4066 for 2 immediates extrq and insertq instructions */
4067 if (i.imm_operands == 2
4068 && (strcmp (mnemonic, "extrq") == 0
4069 || strcmp (mnemonic, "insertq") == 0))
4070 swap_2_operands (0, 1);
4075 /* Don't optimize displacement for movabs since it only takes 64bit
4078 && i.disp_encoding != disp_encoding_32bit
4079 && (flag_code != CODE_64BIT
4080 || strcmp (mnemonic, "movabs") != 0))
4083 /* Next, we find a template that matches the given insn,
4084 making sure the overlap of the given operands types is consistent
4085 with the template operand types. */
4087 if (!(t = match_template (mnem_suffix)))
4090 if (sse_check != check_none
4091 && !i.tm.opcode_modifier.noavx
4092 && !i.tm.cpu_flags.bitfield.cpuavx
4093 && (i.tm.cpu_flags.bitfield.cpusse
4094 || i.tm.cpu_flags.bitfield.cpusse2
4095 || i.tm.cpu_flags.bitfield.cpusse3
4096 || i.tm.cpu_flags.bitfield.cpussse3
4097 || i.tm.cpu_flags.bitfield.cpusse4_1
4098 || i.tm.cpu_flags.bitfield.cpusse4_2
4099 || i.tm.cpu_flags.bitfield.cpupclmul
4100 || i.tm.cpu_flags.bitfield.cpuaes
4101 || i.tm.cpu_flags.bitfield.cpugfni))
4103 (sse_check == check_warning
4105 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4108 /* Zap movzx and movsx suffix. The suffix has been set from
4109 "word ptr" or "byte ptr" on the source operand in Intel syntax
4110 or extracted from mnemonic in AT&T syntax. But we'll use
4111 the destination register to choose the suffix for encoding. */
4112 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4114 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4115 there is no suffix, the default will be byte extension. */
4116 if (i.reg_operands != 2
4119 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4124 if (i.tm.opcode_modifier.fwait)
4125 if (!add_prefix (FWAIT_OPCODE))
4128 /* Check if REP prefix is OK. */
4129 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4131 as_bad (_("invalid instruction `%s' after `%s'"),
4132 i.tm.name, i.rep_prefix);
4136 /* Check for lock without a lockable instruction. Destination operand
4137 must be memory unless it is xchg (0x86). */
4138 if (i.prefix[LOCK_PREFIX]
4139 && (!i.tm.opcode_modifier.islockable
4140 || i.mem_operands == 0
4141 || (i.tm.base_opcode != 0x86
4142 && !operand_type_check (i.types[i.operands - 1], anymem))))
4144 as_bad (_("expecting lockable instruction after `lock'"));
4148 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4149 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4151 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4155 /* Check if HLE prefix is OK. */
4156 if (i.hle_prefix && !check_hle ())
4159 /* Check BND prefix. */
4160 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4161 as_bad (_("expecting valid branch instruction after `bnd'"));
4163 /* Check NOTRACK prefix. */
4164 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4165 as_bad (_("expecting indirect branch instruction after `notrack'"));
4167 if (i.tm.cpu_flags.bitfield.cpumpx)
4169 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4170 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4171 else if (flag_code != CODE_16BIT
4172 ? i.prefix[ADDR_PREFIX]
4173 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4174 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4177 /* Insert BND prefix. */
4178 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4180 if (!i.prefix[BND_PREFIX])
4181 add_prefix (BND_PREFIX_OPCODE);
4182 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4184 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4185 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4189 /* Check string instruction segment overrides. */
4190 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4192 if (!check_string ())
4194 i.disp_operands = 0;
4197 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4198 optimize_encoding ();
4200 if (!process_suffix ())
4203 /* Update operand types. */
4204 for (j = 0; j < i.operands; j++)
4205 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4207 /* Make still unresolved immediate matches conform to size of immediate
4208 given in i.suffix. */
4209 if (!finalize_imm ())
4212 if (i.types[0].bitfield.imm1)
4213 i.imm_operands = 0; /* kludge for shift insns. */
4215 /* We only need to check those implicit registers for instructions
4216 with 3 operands or less. */
4217 if (i.operands <= 3)
4218 for (j = 0; j < i.operands; j++)
4219 if (i.types[j].bitfield.inoutportreg
4220 || i.types[j].bitfield.shiftcount
4221 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4224 /* ImmExt should be processed after SSE2AVX. */
4225 if (!i.tm.opcode_modifier.sse2avx
4226 && i.tm.opcode_modifier.immext)
4229 /* For insns with operands there are more diddles to do to the opcode. */
4232 if (!process_operands ())
4235 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4237 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4238 as_warn (_("translating to `%sp'"), i.tm.name);
4241 if (is_any_vex_encoding (&i.tm))
4243 if (flag_code == CODE_16BIT)
4245 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4250 if (i.tm.opcode_modifier.vex)
4251 build_vex_prefix (t);
4253 build_evex_prefix ();
4256 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4257 instructions may define INT_OPCODE as well, so avoid this corner
4258 case for those instructions that use MODRM. */
4259 if (i.tm.base_opcode == INT_OPCODE
4260 && !i.tm.opcode_modifier.modrm
4261 && i.op[0].imms->X_add_number == 3)
4263 i.tm.base_opcode = INT3_OPCODE;
4267 if ((i.tm.opcode_modifier.jump
4268 || i.tm.opcode_modifier.jumpbyte
4269 || i.tm.opcode_modifier.jumpdword)
4270 && i.op[0].disps->X_op == O_constant)
4272 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4273 the absolute address given by the constant. Since ix86 jumps and
4274 calls are pc relative, we need to generate a reloc. */
4275 i.op[0].disps->X_add_symbol = &abs_symbol;
4276 i.op[0].disps->X_op = O_symbol;
4279 if (i.tm.opcode_modifier.rex64)
4282 /* For 8 bit registers we need an empty rex prefix. Also if the
4283 instruction already has a prefix, we need to convert old
4284 registers to new ones. */
4286 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4287 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4288 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4289 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4290 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4291 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4296 i.rex |= REX_OPCODE;
4297 for (x = 0; x < 2; x++)
4299 /* Look for 8 bit operand that uses old registers. */
4300 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4301 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4303 /* In case it is "hi" register, give up. */
4304 if (i.op[x].regs->reg_num > 3)
4305 as_bad (_("can't encode register '%s%s' in an "
4306 "instruction requiring REX prefix."),
4307 register_prefix, i.op[x].regs->reg_name);
4309 /* Otherwise it is equivalent to the extended register.
4310 Since the encoding doesn't change this is merely
4311 cosmetic cleanup for debug output. */
4313 i.op[x].regs = i.op[x].regs + 8;
4318 if (i.rex == 0 && i.rex_encoding)
4320 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4321 that uses legacy register. If it is "hi" register, don't add
4322 the REX_OPCODE byte. */
4324 for (x = 0; x < 2; x++)
4325 if (i.types[x].bitfield.reg
4326 && i.types[x].bitfield.byte
4327 && (i.op[x].regs->reg_flags & RegRex64) == 0
4328 && i.op[x].regs->reg_num > 3)
4330 i.rex_encoding = FALSE;
4339 add_prefix (REX_OPCODE | i.rex);
4341 /* We are ready to output the insn. */
4346 parse_insn (char *line, char *mnemonic)
4349 char *token_start = l;
4352 const insn_template *t;
4358 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4363 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4365 as_bad (_("no such instruction: `%s'"), token_start);
4370 if (!is_space_char (*l)
4371 && *l != END_OF_INSN
4373 || (*l != PREFIX_SEPARATOR
4376 as_bad (_("invalid character %s in mnemonic"),
4377 output_invalid (*l));
4380 if (token_start == l)
4382 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4383 as_bad (_("expecting prefix; got nothing"));
4385 as_bad (_("expecting mnemonic; got nothing"));
4389 /* Look up instruction (or prefix) via hash table. */
4390 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4392 if (*l != END_OF_INSN
4393 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4394 && current_templates
4395 && current_templates->start->opcode_modifier.isprefix)
4397 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4399 as_bad ((flag_code != CODE_64BIT
4400 ? _("`%s' is only supported in 64-bit mode")
4401 : _("`%s' is not supported in 64-bit mode")),
4402 current_templates->start->name);
4405 /* If we are in 16-bit mode, do not allow addr16 or data16.
4406 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4407 if ((current_templates->start->opcode_modifier.size16
4408 || current_templates->start->opcode_modifier.size32)
4409 && flag_code != CODE_64BIT
4410 && (current_templates->start->opcode_modifier.size32
4411 ^ (flag_code == CODE_16BIT)))
4413 as_bad (_("redundant %s prefix"),
4414 current_templates->start->name);
4417 if (current_templates->start->opcode_length == 0)
4419 /* Handle pseudo prefixes. */
4420 switch (current_templates->start->base_opcode)
4424 i.disp_encoding = disp_encoding_8bit;
4428 i.disp_encoding = disp_encoding_32bit;
4432 i.dir_encoding = dir_encoding_load;
4436 i.dir_encoding = dir_encoding_store;
4440 i.vec_encoding = vex_encoding_vex2;
4444 i.vec_encoding = vex_encoding_vex3;
4448 i.vec_encoding = vex_encoding_evex;
4452 i.rex_encoding = TRUE;
4456 i.no_optimize = TRUE;
4464 /* Add prefix, checking for repeated prefixes. */
4465 switch (add_prefix (current_templates->start->base_opcode))
4470 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4471 i.notrack_prefix = current_templates->start->name;
4474 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4475 i.hle_prefix = current_templates->start->name;
4476 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4477 i.bnd_prefix = current_templates->start->name;
4479 i.rep_prefix = current_templates->start->name;
4485 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4492 if (!current_templates)
4494 /* Check if we should swap operand or force 32bit displacement in
4496 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4497 i.dir_encoding = dir_encoding_store;
4498 else if (mnem_p - 3 == dot_p
4501 i.disp_encoding = disp_encoding_8bit;
4502 else if (mnem_p - 4 == dot_p
4506 i.disp_encoding = disp_encoding_32bit;
4511 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4514 if (!current_templates)
4517 /* See if we can get a match by trimming off a suffix. */
4520 case WORD_MNEM_SUFFIX:
4521 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4522 i.suffix = SHORT_MNEM_SUFFIX;
4525 case BYTE_MNEM_SUFFIX:
4526 case QWORD_MNEM_SUFFIX:
4527 i.suffix = mnem_p[-1];
4529 current_templates = (const templates *) hash_find (op_hash,
4532 case SHORT_MNEM_SUFFIX:
4533 case LONG_MNEM_SUFFIX:
4536 i.suffix = mnem_p[-1];
4538 current_templates = (const templates *) hash_find (op_hash,
4547 if (intel_float_operand (mnemonic) == 1)
4548 i.suffix = SHORT_MNEM_SUFFIX;
4550 i.suffix = LONG_MNEM_SUFFIX;
4552 current_templates = (const templates *) hash_find (op_hash,
4557 if (!current_templates)
4559 as_bad (_("no such instruction: `%s'"), token_start);
4564 if (current_templates->start->opcode_modifier.jump
4565 || current_templates->start->opcode_modifier.jumpbyte)
4567 /* Check for a branch hint. We allow ",pt" and ",pn" for
4568 predict taken and predict not taken respectively.
4569 I'm not sure that branch hints actually do anything on loop
4570 and jcxz insns (JumpByte) for current Pentium4 chips. They
4571 may work in the future and it doesn't hurt to accept them
4573 if (l[0] == ',' && l[1] == 'p')
4577 if (!add_prefix (DS_PREFIX_OPCODE))
4581 else if (l[2] == 'n')
4583 if (!add_prefix (CS_PREFIX_OPCODE))
4589 /* Any other comma loses. */
4592 as_bad (_("invalid character %s in mnemonic"),
4593 output_invalid (*l));
4597 /* Check if instruction is supported on specified architecture. */
4599 for (t = current_templates->start; t < current_templates->end; ++t)
4601 supported |= cpu_flags_match (t);
4602 if (supported == CPU_FLAGS_PERFECT_MATCH)
4604 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4605 as_warn (_("use .code16 to ensure correct addressing mode"));
4611 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4612 as_bad (flag_code == CODE_64BIT
4613 ? _("`%s' is not supported in 64-bit mode")
4614 : _("`%s' is only supported in 64-bit mode"),
4615 current_templates->start->name);
4617 as_bad (_("`%s' is not supported on `%s%s'"),
4618 current_templates->start->name,
4619 cpu_arch_name ? cpu_arch_name : default_arch,
4620 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4626 parse_operands (char *l, const char *mnemonic)
4630 /* 1 if operand is pending after ','. */
4631 unsigned int expecting_operand = 0;
4633 /* Non-zero if operand parens not balanced. */
4634 unsigned int paren_not_balanced;
4636 while (*l != END_OF_INSN)
4638 /* Skip optional white space before operand. */
4639 if (is_space_char (*l))
4641 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4643 as_bad (_("invalid character %s before operand %d"),
4644 output_invalid (*l),
4648 token_start = l; /* After white space. */
4649 paren_not_balanced = 0;
4650 while (paren_not_balanced || *l != ',')
4652 if (*l == END_OF_INSN)
4654 if (paren_not_balanced)
4657 as_bad (_("unbalanced parenthesis in operand %d."),
4660 as_bad (_("unbalanced brackets in operand %d."),
4665 break; /* we are done */
4667 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4669 as_bad (_("invalid character %s in operand %d"),
4670 output_invalid (*l),
4677 ++paren_not_balanced;
4679 --paren_not_balanced;
4684 ++paren_not_balanced;
4686 --paren_not_balanced;
4690 if (l != token_start)
4691 { /* Yes, we've read in another operand. */
4692 unsigned int operand_ok;
4693 this_operand = i.operands++;
4694 if (i.operands > MAX_OPERANDS)
4696 as_bad (_("spurious operands; (%d operands/instruction max)"),
4700 i.types[this_operand].bitfield.unspecified = 1;
4701 /* Now parse operand adding info to 'i' as we go along. */
4702 END_STRING_AND_SAVE (l);
4704 if (i.mem_operands > 1)
4706 as_bad (_("too many memory references for `%s'"),
4713 i386_intel_operand (token_start,
4714 intel_float_operand (mnemonic));
4716 operand_ok = i386_att_operand (token_start);
4718 RESTORE_END_STRING (l);
4724 if (expecting_operand)
4726 expecting_operand_after_comma:
4727 as_bad (_("expecting operand after ','; got nothing"));
4732 as_bad (_("expecting operand before ','; got nothing"));
4737 /* Now *l must be either ',' or END_OF_INSN. */
4740 if (*++l == END_OF_INSN)
4742 /* Just skip it, if it's \n complain. */
4743 goto expecting_operand_after_comma;
4745 expecting_operand = 1;
4752 swap_2_operands (int xchg1, int xchg2)
4754 union i386_op temp_op;
4755 i386_operand_type temp_type;
4756 enum bfd_reloc_code_real temp_reloc;
4758 temp_type = i.types[xchg2];
4759 i.types[xchg2] = i.types[xchg1];
4760 i.types[xchg1] = temp_type;
4761 temp_op = i.op[xchg2];
4762 i.op[xchg2] = i.op[xchg1];
4763 i.op[xchg1] = temp_op;
4764 temp_reloc = i.reloc[xchg2];
4765 i.reloc[xchg2] = i.reloc[xchg1];
4766 i.reloc[xchg1] = temp_reloc;
4770 if (i.mask->operand == xchg1)
4771 i.mask->operand = xchg2;
4772 else if (i.mask->operand == xchg2)
4773 i.mask->operand = xchg1;
4777 if (i.broadcast->operand == xchg1)
4778 i.broadcast->operand = xchg2;
4779 else if (i.broadcast->operand == xchg2)
4780 i.broadcast->operand = xchg1;
4784 if (i.rounding->operand == xchg1)
4785 i.rounding->operand = xchg2;
4786 else if (i.rounding->operand == xchg2)
4787 i.rounding->operand = xchg1;
4792 swap_operands (void)
4798 swap_2_operands (1, i.operands - 2);
4802 swap_2_operands (0, i.operands - 1);
4808 if (i.mem_operands == 2)
4810 const seg_entry *temp_seg;
4811 temp_seg = i.seg[0];
4812 i.seg[0] = i.seg[1];
4813 i.seg[1] = temp_seg;
4817 /* Try to ensure constant immediates are represented in the smallest
4822 char guess_suffix = 0;
4826 guess_suffix = i.suffix;
4827 else if (i.reg_operands)
4829 /* Figure out a suffix from the last register operand specified.
4830 We can't do this properly yet, ie. excluding InOutPortReg,
4831 but the following works for instructions with immediates.
4832 In any case, we can't set i.suffix yet. */
4833 for (op = i.operands; --op >= 0;)
4834 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4836 guess_suffix = BYTE_MNEM_SUFFIX;
4839 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4841 guess_suffix = WORD_MNEM_SUFFIX;
4844 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4846 guess_suffix = LONG_MNEM_SUFFIX;
4849 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4851 guess_suffix = QWORD_MNEM_SUFFIX;
4855 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4856 guess_suffix = WORD_MNEM_SUFFIX;
4858 for (op = i.operands; --op >= 0;)
4859 if (operand_type_check (i.types[op], imm))
4861 switch (i.op[op].imms->X_op)
4864 /* If a suffix is given, this operand may be shortened. */
4865 switch (guess_suffix)
4867 case LONG_MNEM_SUFFIX:
4868 i.types[op].bitfield.imm32 = 1;
4869 i.types[op].bitfield.imm64 = 1;
4871 case WORD_MNEM_SUFFIX:
4872 i.types[op].bitfield.imm16 = 1;
4873 i.types[op].bitfield.imm32 = 1;
4874 i.types[op].bitfield.imm32s = 1;
4875 i.types[op].bitfield.imm64 = 1;
4877 case BYTE_MNEM_SUFFIX:
4878 i.types[op].bitfield.imm8 = 1;
4879 i.types[op].bitfield.imm8s = 1;
4880 i.types[op].bitfield.imm16 = 1;
4881 i.types[op].bitfield.imm32 = 1;
4882 i.types[op].bitfield.imm32s = 1;
4883 i.types[op].bitfield.imm64 = 1;
4887 /* If this operand is at most 16 bits, convert it
4888 to a signed 16 bit number before trying to see
4889 whether it will fit in an even smaller size.
4890 This allows a 16-bit operand such as $0xffe0 to
4891 be recognised as within Imm8S range. */
4892 if ((i.types[op].bitfield.imm16)
4893 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4895 i.op[op].imms->X_add_number =
4896 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4899 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4900 if ((i.types[op].bitfield.imm32)
4901 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4904 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4905 ^ ((offsetT) 1 << 31))
4906 - ((offsetT) 1 << 31));
4910 = operand_type_or (i.types[op],
4911 smallest_imm_type (i.op[op].imms->X_add_number));
4913 /* We must avoid matching of Imm32 templates when 64bit
4914 only immediate is available. */
4915 if (guess_suffix == QWORD_MNEM_SUFFIX)
4916 i.types[op].bitfield.imm32 = 0;
4923 /* Symbols and expressions. */
4925 /* Convert symbolic operand to proper sizes for matching, but don't
4926 prevent matching a set of insns that only supports sizes other
4927 than those matching the insn suffix. */
4929 i386_operand_type mask, allowed;
4930 const insn_template *t;
4932 operand_type_set (&mask, 0);
4933 operand_type_set (&allowed, 0);
4935 for (t = current_templates->start;
4936 t < current_templates->end;
4938 allowed = operand_type_or (allowed,
4939 t->operand_types[op]);
4940 switch (guess_suffix)
4942 case QWORD_MNEM_SUFFIX:
4943 mask.bitfield.imm64 = 1;
4944 mask.bitfield.imm32s = 1;
4946 case LONG_MNEM_SUFFIX:
4947 mask.bitfield.imm32 = 1;
4949 case WORD_MNEM_SUFFIX:
4950 mask.bitfield.imm16 = 1;
4952 case BYTE_MNEM_SUFFIX:
4953 mask.bitfield.imm8 = 1;
4958 allowed = operand_type_and (mask, allowed);
4959 if (!operand_type_all_zero (&allowed))
4960 i.types[op] = operand_type_and (i.types[op], mask);
4967 /* Try to use the smallest displacement type too. */
4969 optimize_disp (void)
4973 for (op = i.operands; --op >= 0;)
4974 if (operand_type_check (i.types[op], disp))
4976 if (i.op[op].disps->X_op == O_constant)
4978 offsetT op_disp = i.op[op].disps->X_add_number;
4980 if (i.types[op].bitfield.disp16
4981 && (op_disp & ~(offsetT) 0xffff) == 0)
4983 /* If this operand is at most 16 bits, convert
4984 to a signed 16 bit number and don't use 64bit
4986 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4987 i.types[op].bitfield.disp64 = 0;
4990 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4991 if (i.types[op].bitfield.disp32
4992 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4994 /* If this operand is at most 32 bits, convert
4995 to a signed 32 bit number and don't use 64bit
4997 op_disp &= (((offsetT) 2 << 31) - 1);
4998 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4999 i.types[op].bitfield.disp64 = 0;
5002 if (!op_disp && i.types[op].bitfield.baseindex)
5004 i.types[op].bitfield.disp8 = 0;
5005 i.types[op].bitfield.disp16 = 0;
5006 i.types[op].bitfield.disp32 = 0;
5007 i.types[op].bitfield.disp32s = 0;
5008 i.types[op].bitfield.disp64 = 0;
5012 else if (flag_code == CODE_64BIT)
5014 if (fits_in_signed_long (op_disp))
5016 i.types[op].bitfield.disp64 = 0;
5017 i.types[op].bitfield.disp32s = 1;
5019 if (i.prefix[ADDR_PREFIX]
5020 && fits_in_unsigned_long (op_disp))
5021 i.types[op].bitfield.disp32 = 1;
5023 if ((i.types[op].bitfield.disp32
5024 || i.types[op].bitfield.disp32s
5025 || i.types[op].bitfield.disp16)
5026 && fits_in_disp8 (op_disp))
5027 i.types[op].bitfield.disp8 = 1;
5029 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5030 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5032 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5033 i.op[op].disps, 0, i.reloc[op]);
5034 i.types[op].bitfield.disp8 = 0;
5035 i.types[op].bitfield.disp16 = 0;
5036 i.types[op].bitfield.disp32 = 0;
5037 i.types[op].bitfield.disp32s = 0;
5038 i.types[op].bitfield.disp64 = 0;
5041 /* We only support 64bit displacement on constants. */
5042 i.types[op].bitfield.disp64 = 0;
5046 /* Return 1 if there is a match in broadcast bytes between operand
5047 GIVEN and instruction template T. */
5050 match_broadcast_size (const insn_template *t, unsigned int given)
5052 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5053 && i.types[given].bitfield.byte)
5054 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5055 && i.types[given].bitfield.word)
5056 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5057 && i.types[given].bitfield.dword)
5058 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5059 && i.types[given].bitfield.qword));
5062 /* Check if operands are valid for the instruction. */
5065 check_VecOperands (const insn_template *t)
5069 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5071 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5072 any one operand are implicity requiring AVX512VL support if the actual
5073 operand size is YMMword or XMMword. Since this function runs after
5074 template matching, there's no need to check for YMMword/XMMword in
5076 cpu = cpu_flags_and (t->cpu_flags, avx512);
5077 if (!cpu_flags_all_zero (&cpu)
5078 && !t->cpu_flags.bitfield.cpuavx512vl
5079 && !cpu_arch_flags.bitfield.cpuavx512vl)
5081 for (op = 0; op < t->operands; ++op)
5083 if (t->operand_types[op].bitfield.zmmword
5084 && (i.types[op].bitfield.ymmword
5085 || i.types[op].bitfield.xmmword))
5087 i.error = unsupported;
5093 /* Without VSIB byte, we can't have a vector register for index. */
5094 if (!t->opcode_modifier.vecsib
5096 && (i.index_reg->reg_type.bitfield.xmmword
5097 || i.index_reg->reg_type.bitfield.ymmword
5098 || i.index_reg->reg_type.bitfield.zmmword))
5100 i.error = unsupported_vector_index_register;
5104 /* Check if default mask is allowed. */
5105 if (t->opcode_modifier.nodefmask
5106 && (!i.mask || i.mask->mask->reg_num == 0))
5108 i.error = no_default_mask;
5112 /* For VSIB byte, we need a vector register for index, and all vector
5113 registers must be distinct. */
5114 if (t->opcode_modifier.vecsib)
5117 || !((t->opcode_modifier.vecsib == VecSIB128
5118 && i.index_reg->reg_type.bitfield.xmmword)
5119 || (t->opcode_modifier.vecsib == VecSIB256
5120 && i.index_reg->reg_type.bitfield.ymmword)
5121 || (t->opcode_modifier.vecsib == VecSIB512
5122 && i.index_reg->reg_type.bitfield.zmmword)))
5124 i.error = invalid_vsib_address;
5128 gas_assert (i.reg_operands == 2 || i.mask);
5129 if (i.reg_operands == 2 && !i.mask)
5131 gas_assert (i.types[0].bitfield.regsimd);
5132 gas_assert (i.types[0].bitfield.xmmword
5133 || i.types[0].bitfield.ymmword);
5134 gas_assert (i.types[2].bitfield.regsimd);
5135 gas_assert (i.types[2].bitfield.xmmword
5136 || i.types[2].bitfield.ymmword);
5137 if (operand_check == check_none)
5139 if (register_number (i.op[0].regs)
5140 != register_number (i.index_reg)
5141 && register_number (i.op[2].regs)
5142 != register_number (i.index_reg)
5143 && register_number (i.op[0].regs)
5144 != register_number (i.op[2].regs))
5146 if (operand_check == check_error)
5148 i.error = invalid_vector_register_set;
5151 as_warn (_("mask, index, and destination registers should be distinct"));
5153 else if (i.reg_operands == 1 && i.mask)
5155 if (i.types[1].bitfield.regsimd
5156 && (i.types[1].bitfield.xmmword
5157 || i.types[1].bitfield.ymmword
5158 || i.types[1].bitfield.zmmword)
5159 && (register_number (i.op[1].regs)
5160 == register_number (i.index_reg)))
5162 if (operand_check == check_error)
5164 i.error = invalid_vector_register_set;
5167 if (operand_check != check_none)
5168 as_warn (_("index and destination registers should be distinct"));
5173 /* Check if broadcast is supported by the instruction and is applied
5174 to the memory operand. */
5177 i386_operand_type type, overlap;
5179 /* Check if specified broadcast is supported in this instruction,
5180 and its broadcast bytes match the memory operand. */
5181 op = i.broadcast->operand;
5182 if (!t->opcode_modifier.broadcast
5183 || !i.types[op].bitfield.mem
5184 || (!i.types[op].bitfield.unspecified
5185 && !match_broadcast_size (t, op)))
5188 i.error = unsupported_broadcast;
5192 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5193 * i.broadcast->type);
5194 operand_type_set (&type, 0);
5195 switch (i.broadcast->bytes)
5198 type.bitfield.word = 1;
5201 type.bitfield.dword = 1;
5204 type.bitfield.qword = 1;
5207 type.bitfield.xmmword = 1;
5210 type.bitfield.ymmword = 1;
5213 type.bitfield.zmmword = 1;
5219 overlap = operand_type_and (type, t->operand_types[op]);
5220 if (operand_type_all_zero (&overlap))
5223 if (t->opcode_modifier.checkregsize)
5227 type.bitfield.baseindex = 1;
5228 for (j = 0; j < i.operands; ++j)
5231 && !operand_type_register_match(i.types[j],
5232 t->operand_types[j],
5234 t->operand_types[op]))
5239 /* If broadcast is supported in this instruction, we need to check if
5240 operand of one-element size isn't specified without broadcast. */
5241 else if (t->opcode_modifier.broadcast && i.mem_operands)
5243 /* Find memory operand. */
5244 for (op = 0; op < i.operands; op++)
5245 if (operand_type_check (i.types[op], anymem))
5247 gas_assert (op < i.operands);
5248 /* Check size of the memory operand. */
5249 if (match_broadcast_size (t, op))
5251 i.error = broadcast_needed;
5256 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5258 /* Check if requested masking is supported. */
5261 switch (t->opcode_modifier.masking)
5265 case MERGING_MASKING:
5266 if (i.mask->zeroing)
5269 i.error = unsupported_masking;
5273 case DYNAMIC_MASKING:
5274 /* Memory destinations allow only merging masking. */
5275 if (i.mask->zeroing && i.mem_operands)
5277 /* Find memory operand. */
5278 for (op = 0; op < i.operands; op++)
5279 if (i.types[op].bitfield.mem)
5281 gas_assert (op < i.operands);
5282 if (op == i.operands - 1)
5284 i.error = unsupported_masking;
5294 /* Check if masking is applied to dest operand. */
5295 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5297 i.error = mask_not_on_destination;
5304 if ((i.rounding->type != saeonly
5305 && !t->opcode_modifier.staticrounding)
5306 || (i.rounding->type == saeonly
5307 && (t->opcode_modifier.staticrounding
5308 || !t->opcode_modifier.sae)))
5310 i.error = unsupported_rc_sae;
5313 /* If the instruction has several immediate operands and one of
5314 them is rounding, the rounding operand should be the last
5315 immediate operand. */
5316 if (i.imm_operands > 1
5317 && i.rounding->operand != (int) (i.imm_operands - 1))
5319 i.error = rc_sae_operand_not_last_imm;
5324 /* Check vector Disp8 operand. */
5325 if (t->opcode_modifier.disp8memshift
5326 && i.disp_encoding != disp_encoding_32bit)
5329 i.memshift = t->opcode_modifier.broadcast - 1;
5330 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5331 i.memshift = t->opcode_modifier.disp8memshift;
5334 const i386_operand_type *type = NULL;
5337 for (op = 0; op < i.operands; op++)
5338 if (operand_type_check (i.types[op], anymem))
5340 if (t->opcode_modifier.evex == EVEXLIG)
5341 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5342 else if (t->operand_types[op].bitfield.xmmword
5343 + t->operand_types[op].bitfield.ymmword
5344 + t->operand_types[op].bitfield.zmmword <= 1)
5345 type = &t->operand_types[op];
5346 else if (!i.types[op].bitfield.unspecified)
5347 type = &i.types[op];
5349 else if (i.types[op].bitfield.regsimd
5350 && t->opcode_modifier.evex != EVEXLIG)
5352 if (i.types[op].bitfield.zmmword)
5354 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5356 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5362 if (type->bitfield.zmmword)
5364 else if (type->bitfield.ymmword)
5366 else if (type->bitfield.xmmword)
5370 /* For the check in fits_in_disp8(). */
5371 if (i.memshift == 0)
5375 for (op = 0; op < i.operands; op++)
5376 if (operand_type_check (i.types[op], disp)
5377 && i.op[op].disps->X_op == O_constant)
5379 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5381 i.types[op].bitfield.disp8 = 1;
5384 i.types[op].bitfield.disp8 = 0;
5393 /* Check if operands are valid for the instruction. Update VEX
5397 VEX_check_operands (const insn_template *t)
5399 if (i.vec_encoding == vex_encoding_evex)
5401 /* This instruction must be encoded with EVEX prefix. */
5402 if (!is_evex_encoding (t))
5404 i.error = unsupported;
5410 if (!t->opcode_modifier.vex)
5412 /* This instruction template doesn't have VEX prefix. */
5413 if (i.vec_encoding != vex_encoding_default)
5415 i.error = unsupported;
5421 /* Only check VEX_Imm4, which must be the first operand. */
5422 if (t->operand_types[0].bitfield.vec_imm4)
5424 if (i.op[0].imms->X_op != O_constant
5425 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5431 /* Turn off Imm8 so that update_imm won't complain. */
5432 i.types[0] = vec_imm4;
5438 static const insn_template *
5439 match_template (char mnem_suffix)
5441 /* Points to template once we've found it. */
5442 const insn_template *t;
5443 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5444 i386_operand_type overlap4;
5445 unsigned int found_reverse_match;
5446 i386_opcode_modifier suffix_check, mnemsuf_check;
5447 i386_operand_type operand_types [MAX_OPERANDS];
5448 int addr_prefix_disp;
5450 unsigned int found_cpu_match, size_match;
5451 unsigned int check_register;
5452 enum i386_error specific_error = 0;
5454 #if MAX_OPERANDS != 5
5455 # error "MAX_OPERANDS must be 5."
5458 found_reverse_match = 0;
5459 addr_prefix_disp = -1;
5461 memset (&suffix_check, 0, sizeof (suffix_check));
5462 if (intel_syntax && i.broadcast)
5464 else if (i.suffix == BYTE_MNEM_SUFFIX)
5465 suffix_check.no_bsuf = 1;
5466 else if (i.suffix == WORD_MNEM_SUFFIX)
5467 suffix_check.no_wsuf = 1;
5468 else if (i.suffix == SHORT_MNEM_SUFFIX)
5469 suffix_check.no_ssuf = 1;
5470 else if (i.suffix == LONG_MNEM_SUFFIX)
5471 suffix_check.no_lsuf = 1;
5472 else if (i.suffix == QWORD_MNEM_SUFFIX)
5473 suffix_check.no_qsuf = 1;
5474 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5475 suffix_check.no_ldsuf = 1;
5477 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5480 switch (mnem_suffix)
5482 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5483 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5484 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5485 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5486 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5490 /* Must have right number of operands. */
5491 i.error = number_of_operands_mismatch;
5493 for (t = current_templates->start; t < current_templates->end; t++)
5495 addr_prefix_disp = -1;
5497 if (i.operands != t->operands)
5500 /* Check processor support. */
5501 i.error = unsupported;
5502 found_cpu_match = (cpu_flags_match (t)
5503 == CPU_FLAGS_PERFECT_MATCH);
5504 if (!found_cpu_match)
5507 /* Check AT&T mnemonic. */
5508 i.error = unsupported_with_intel_mnemonic;
5509 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5512 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5513 i.error = unsupported_syntax;
5514 if ((intel_syntax && t->opcode_modifier.attsyntax)
5515 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5516 || (intel64 && t->opcode_modifier.amd64)
5517 || (!intel64 && t->opcode_modifier.intel64))
5520 /* Check the suffix, except for some instructions in intel mode. */
5521 i.error = invalid_instruction_suffix;
5522 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5523 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5524 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5525 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5526 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5527 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5528 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5530 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5531 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5532 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5533 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5534 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5535 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5536 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5539 size_match = operand_size_match (t);
5543 for (j = 0; j < MAX_OPERANDS; j++)
5544 operand_types[j] = t->operand_types[j];
5546 /* In general, don't allow 64-bit operands in 32-bit mode. */
5547 if (i.suffix == QWORD_MNEM_SUFFIX
5548 && flag_code != CODE_64BIT
5550 ? (!t->opcode_modifier.ignoresize
5551 && !t->opcode_modifier.broadcast
5552 && !intel_float_operand (t->name))
5553 : intel_float_operand (t->name) != 2)
5554 && ((!operand_types[0].bitfield.regmmx
5555 && !operand_types[0].bitfield.regsimd)
5556 || (!operand_types[t->operands > 1].bitfield.regmmx
5557 && !operand_types[t->operands > 1].bitfield.regsimd))
5558 && (t->base_opcode != 0x0fc7
5559 || t->extension_opcode != 1 /* cmpxchg8b */))
5562 /* In general, don't allow 32-bit operands on pre-386. */
5563 else if (i.suffix == LONG_MNEM_SUFFIX
5564 && !cpu_arch_flags.bitfield.cpui386
5566 ? (!t->opcode_modifier.ignoresize
5567 && !intel_float_operand (t->name))
5568 : intel_float_operand (t->name) != 2)
5569 && ((!operand_types[0].bitfield.regmmx
5570 && !operand_types[0].bitfield.regsimd)
5571 || (!operand_types[t->operands > 1].bitfield.regmmx
5572 && !operand_types[t->operands > 1].bitfield.regsimd)))
5575 /* Do not verify operands when there are none. */
5579 /* We've found a match; break out of loop. */
5583 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5584 into Disp32/Disp16/Disp32 operand. */
5585 if (i.prefix[ADDR_PREFIX] != 0)
5587 /* There should be only one Disp operand. */
5591 for (j = 0; j < MAX_OPERANDS; j++)
5593 if (operand_types[j].bitfield.disp16)
5595 addr_prefix_disp = j;
5596 operand_types[j].bitfield.disp32 = 1;
5597 operand_types[j].bitfield.disp16 = 0;
5603 for (j = 0; j < MAX_OPERANDS; j++)
5605 if (operand_types[j].bitfield.disp32)
5607 addr_prefix_disp = j;
5608 operand_types[j].bitfield.disp32 = 0;
5609 operand_types[j].bitfield.disp16 = 1;
5615 for (j = 0; j < MAX_OPERANDS; j++)
5617 if (operand_types[j].bitfield.disp64)
5619 addr_prefix_disp = j;
5620 operand_types[j].bitfield.disp64 = 0;
5621 operand_types[j].bitfield.disp32 = 1;
5629 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5630 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5633 /* We check register size if needed. */
5634 if (t->opcode_modifier.checkregsize)
5636 check_register = (1 << t->operands) - 1;
5638 check_register &= ~(1 << i.broadcast->operand);
5643 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5644 switch (t->operands)
5647 if (!operand_type_match (overlap0, i.types[0]))
5651 /* xchg %eax, %eax is a special case. It is an alias for nop
5652 only in 32bit mode and we can use opcode 0x90. In 64bit
5653 mode, we can't use 0x90 for xchg %eax, %eax since it should
5654 zero-extend %eax to %rax. */
5655 if (flag_code == CODE_64BIT
5656 && t->base_opcode == 0x90
5657 && operand_type_equal (&i.types [0], &acc32)
5658 && operand_type_equal (&i.types [1], &acc32))
5660 /* xrelease mov %eax, <disp> is another special case. It must not
5661 match the accumulator-only encoding of mov. */
5662 if (flag_code != CODE_64BIT
5664 && t->base_opcode == 0xa0
5665 && i.types[0].bitfield.acc
5666 && operand_type_check (i.types[1], anymem))
5668 if (!(size_match & MATCH_STRAIGHT))
5670 /* If we want store form, we reverse direction of operands. */
5671 if (i.dir_encoding == dir_encoding_store
5672 && t->opcode_modifier.d)
5677 /* If we want store form, we skip the current load. */
5678 if (i.dir_encoding == dir_encoding_store
5679 && i.mem_operands == 0
5680 && t->opcode_modifier.load)
5685 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5686 if (!operand_type_match (overlap0, i.types[0])
5687 || !operand_type_match (overlap1, i.types[1])
5688 || ((check_register & 3) == 3
5689 && !operand_type_register_match (i.types[0],
5694 /* Check if other direction is valid ... */
5695 if (!t->opcode_modifier.d)
5699 if (!(size_match & MATCH_REVERSE))
5701 /* Try reversing direction of operands. */
5702 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5703 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5704 if (!operand_type_match (overlap0, i.types[0])
5705 || !operand_type_match (overlap1, i.types[1])
5707 && !operand_type_register_match (i.types[0],
5712 /* Does not match either direction. */
5715 /* found_reverse_match holds which of D or FloatR
5717 if (!t->opcode_modifier.d)
5718 found_reverse_match = 0;
5719 else if (operand_types[0].bitfield.tbyte)
5720 found_reverse_match = Opcode_FloatD;
5722 found_reverse_match = Opcode_D;
5723 if (t->opcode_modifier.floatr)
5724 found_reverse_match |= Opcode_FloatR;
5728 /* Found a forward 2 operand match here. */
5729 switch (t->operands)
5732 overlap4 = operand_type_and (i.types[4],
5736 overlap3 = operand_type_and (i.types[3],
5740 overlap2 = operand_type_and (i.types[2],
5745 switch (t->operands)
5748 if (!operand_type_match (overlap4, i.types[4])
5749 || !operand_type_register_match (i.types[3],
5756 if (!operand_type_match (overlap3, i.types[3])
5757 || ((check_register & 0xa) == 0xa
5758 && !operand_type_register_match (i.types[1],
5762 || ((check_register & 0xc) == 0xc
5763 && !operand_type_register_match (i.types[2],
5770 /* Here we make use of the fact that there are no
5771 reverse match 3 operand instructions. */
5772 if (!operand_type_match (overlap2, i.types[2])
5773 || ((check_register & 5) == 5
5774 && !operand_type_register_match (i.types[0],
5778 || ((check_register & 6) == 6
5779 && !operand_type_register_match (i.types[1],
5787 /* Found either forward/reverse 2, 3 or 4 operand match here:
5788 slip through to break. */
5790 if (!found_cpu_match)
5792 found_reverse_match = 0;
5796 /* Check if vector and VEX operands are valid. */
5797 if (check_VecOperands (t) || VEX_check_operands (t))
5799 specific_error = i.error;
5803 /* We've found a match; break out of loop. */
5807 if (t == current_templates->end)
5809 /* We found no match. */
5810 const char *err_msg;
5811 switch (specific_error ? specific_error : i.error)
5815 case operand_size_mismatch:
5816 err_msg = _("operand size mismatch");
5818 case operand_type_mismatch:
5819 err_msg = _("operand type mismatch");
5821 case register_type_mismatch:
5822 err_msg = _("register type mismatch");
5824 case number_of_operands_mismatch:
5825 err_msg = _("number of operands mismatch");
5827 case invalid_instruction_suffix:
5828 err_msg = _("invalid instruction suffix");
5831 err_msg = _("constant doesn't fit in 4 bits");
5833 case unsupported_with_intel_mnemonic:
5834 err_msg = _("unsupported with Intel mnemonic");
5836 case unsupported_syntax:
5837 err_msg = _("unsupported syntax");
5840 as_bad (_("unsupported instruction `%s'"),
5841 current_templates->start->name);
5843 case invalid_vsib_address:
5844 err_msg = _("invalid VSIB address");
5846 case invalid_vector_register_set:
5847 err_msg = _("mask, index, and destination registers must be distinct");
5849 case unsupported_vector_index_register:
5850 err_msg = _("unsupported vector index register");
5852 case unsupported_broadcast:
5853 err_msg = _("unsupported broadcast");
5855 case broadcast_needed:
5856 err_msg = _("broadcast is needed for operand of such type");
5858 case unsupported_masking:
5859 err_msg = _("unsupported masking");
5861 case mask_not_on_destination:
5862 err_msg = _("mask not on destination operand");
5864 case no_default_mask:
5865 err_msg = _("default mask isn't allowed");
5867 case unsupported_rc_sae:
5868 err_msg = _("unsupported static rounding/sae");
5870 case rc_sae_operand_not_last_imm:
5872 err_msg = _("RC/SAE operand must precede immediate operands");
5874 err_msg = _("RC/SAE operand must follow immediate operands");
5876 case invalid_register_operand:
5877 err_msg = _("invalid register operand");
5880 as_bad (_("%s for `%s'"), err_msg,
5881 current_templates->start->name);
5885 if (!quiet_warnings)
5888 && (i.types[0].bitfield.jumpabsolute
5889 != operand_types[0].bitfield.jumpabsolute))
5891 as_warn (_("indirect %s without `*'"), t->name);
5894 if (t->opcode_modifier.isprefix
5895 && t->opcode_modifier.ignoresize)
5897 /* Warn them that a data or address size prefix doesn't
5898 affect assembly of the next line of code. */
5899 as_warn (_("stand-alone `%s' prefix"), t->name);
5903 /* Copy the template we found. */
5906 if (addr_prefix_disp != -1)
5907 i.tm.operand_types[addr_prefix_disp]
5908 = operand_types[addr_prefix_disp];
5910 if (found_reverse_match)
5912 /* If we found a reverse match we must alter the opcode
5913 direction bit. found_reverse_match holds bits to change
5914 (different for int & float insns). */
5916 i.tm.base_opcode ^= found_reverse_match;
5918 i.tm.operand_types[0] = operand_types[1];
5919 i.tm.operand_types[1] = operand_types[0];
5928 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5929 if (i.tm.operand_types[mem_op].bitfield.esseg)
5931 if (i.seg[0] != NULL && i.seg[0] != &es)
5933 as_bad (_("`%s' operand %d must use `%ses' segment"),
5939 /* There's only ever one segment override allowed per instruction.
5940 This instruction possibly has a legal segment override on the
5941 second operand, so copy the segment to where non-string
5942 instructions store it, allowing common code. */
5943 i.seg[0] = i.seg[1];
5945 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5947 if (i.seg[1] != NULL && i.seg[1] != &es)
5949 as_bad (_("`%s' operand %d must use `%ses' segment"),
5960 process_suffix (void)
5962 /* If matched instruction specifies an explicit instruction mnemonic
5964 if (i.tm.opcode_modifier.size16)
5965 i.suffix = WORD_MNEM_SUFFIX;
5966 else if (i.tm.opcode_modifier.size32)
5967 i.suffix = LONG_MNEM_SUFFIX;
5968 else if (i.tm.opcode_modifier.size64)
5969 i.suffix = QWORD_MNEM_SUFFIX;
5970 else if (i.reg_operands)
5972 /* If there's no instruction mnemonic suffix we try to invent one
5973 based on register operands. */
5976 /* We take i.suffix from the last register operand specified,
5977 Destination register type is more significant than source
5978 register type. crc32 in SSE4.2 prefers source register
5980 if (i.tm.base_opcode == 0xf20f38f1)
5982 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5983 i.suffix = WORD_MNEM_SUFFIX;
5984 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5985 i.suffix = LONG_MNEM_SUFFIX;
5986 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5987 i.suffix = QWORD_MNEM_SUFFIX;
5989 else if (i.tm.base_opcode == 0xf20f38f0)
5991 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5992 i.suffix = BYTE_MNEM_SUFFIX;
5999 if (i.tm.base_opcode == 0xf20f38f1
6000 || i.tm.base_opcode == 0xf20f38f0)
6002 /* We have to know the operand size for crc32. */
6003 as_bad (_("ambiguous memory operand size for `%s`"),
6008 for (op = i.operands; --op >= 0;)
6009 if (!i.tm.operand_types[op].bitfield.inoutportreg
6010 && !i.tm.operand_types[op].bitfield.shiftcount)
6012 if (!i.types[op].bitfield.reg)
6014 if (i.types[op].bitfield.byte)
6015 i.suffix = BYTE_MNEM_SUFFIX;
6016 else if (i.types[op].bitfield.word)
6017 i.suffix = WORD_MNEM_SUFFIX;
6018 else if (i.types[op].bitfield.dword)
6019 i.suffix = LONG_MNEM_SUFFIX;
6020 else if (i.types[op].bitfield.qword)
6021 i.suffix = QWORD_MNEM_SUFFIX;
6028 else if (i.suffix == BYTE_MNEM_SUFFIX)
6031 && i.tm.opcode_modifier.ignoresize
6032 && i.tm.opcode_modifier.no_bsuf)
6034 else if (!check_byte_reg ())
6037 else if (i.suffix == LONG_MNEM_SUFFIX)
6040 && i.tm.opcode_modifier.ignoresize
6041 && i.tm.opcode_modifier.no_lsuf
6042 && !i.tm.opcode_modifier.todword
6043 && !i.tm.opcode_modifier.toqword)
6045 else if (!check_long_reg ())
6048 else if (i.suffix == QWORD_MNEM_SUFFIX)
6051 && i.tm.opcode_modifier.ignoresize
6052 && i.tm.opcode_modifier.no_qsuf
6053 && !i.tm.opcode_modifier.todword
6054 && !i.tm.opcode_modifier.toqword)
6056 else if (!check_qword_reg ())
6059 else if (i.suffix == WORD_MNEM_SUFFIX)
6062 && i.tm.opcode_modifier.ignoresize
6063 && i.tm.opcode_modifier.no_wsuf)
6065 else if (!check_word_reg ())
6068 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6069 /* Do nothing if the instruction is going to ignore the prefix. */
6074 else if (i.tm.opcode_modifier.defaultsize
6076 /* exclude fldenv/frstor/fsave/fstenv */
6077 && i.tm.opcode_modifier.no_ssuf)
6079 i.suffix = stackop_size;
6081 else if (intel_syntax
6083 && (i.tm.operand_types[0].bitfield.jumpabsolute
6084 || i.tm.opcode_modifier.jumpbyte
6085 || i.tm.opcode_modifier.jumpintersegment
6086 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6087 && i.tm.extension_opcode <= 3)))
6092 if (!i.tm.opcode_modifier.no_qsuf)
6094 i.suffix = QWORD_MNEM_SUFFIX;
6099 if (!i.tm.opcode_modifier.no_lsuf)
6100 i.suffix = LONG_MNEM_SUFFIX;
6103 if (!i.tm.opcode_modifier.no_wsuf)
6104 i.suffix = WORD_MNEM_SUFFIX;
6113 if (i.tm.opcode_modifier.w)
6115 as_bad (_("no instruction mnemonic suffix given and "
6116 "no register operands; can't size instruction"));
6122 unsigned int suffixes;
6124 suffixes = !i.tm.opcode_modifier.no_bsuf;
6125 if (!i.tm.opcode_modifier.no_wsuf)
6127 if (!i.tm.opcode_modifier.no_lsuf)
6129 if (!i.tm.opcode_modifier.no_ldsuf)
6131 if (!i.tm.opcode_modifier.no_ssuf)
6133 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6136 /* There are more than suffix matches. */
6137 if (i.tm.opcode_modifier.w
6138 || ((suffixes & (suffixes - 1))
6139 && !i.tm.opcode_modifier.defaultsize
6140 && !i.tm.opcode_modifier.ignoresize))
6142 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6148 /* Change the opcode based on the operand size given by i.suffix. */
6151 /* Size floating point instruction. */
6152 case LONG_MNEM_SUFFIX:
6153 if (i.tm.opcode_modifier.floatmf)
6155 i.tm.base_opcode ^= 4;
6159 case WORD_MNEM_SUFFIX:
6160 case QWORD_MNEM_SUFFIX:
6161 /* It's not a byte, select word/dword operation. */
6162 if (i.tm.opcode_modifier.w)
6164 if (i.tm.opcode_modifier.shortform)
6165 i.tm.base_opcode |= 8;
6167 i.tm.base_opcode |= 1;
6170 case SHORT_MNEM_SUFFIX:
6171 /* Now select between word & dword operations via the operand
6172 size prefix, except for instructions that will ignore this
6174 if (i.reg_operands > 0
6175 && i.types[0].bitfield.reg
6176 && i.tm.opcode_modifier.addrprefixopreg
6177 && (i.tm.opcode_modifier.immext
6178 || i.operands == 1))
6180 /* The address size override prefix changes the size of the
6182 if ((flag_code == CODE_32BIT
6183 && i.op[0].regs->reg_type.bitfield.word)
6184 || (flag_code != CODE_32BIT
6185 && i.op[0].regs->reg_type.bitfield.dword))
6186 if (!add_prefix (ADDR_PREFIX_OPCODE))
6189 else if (i.suffix != QWORD_MNEM_SUFFIX
6190 && !i.tm.opcode_modifier.ignoresize
6191 && !i.tm.opcode_modifier.floatmf
6192 && !i.tm.opcode_modifier.vex
6193 && !i.tm.opcode_modifier.vexopcode
6194 && !is_evex_encoding (&i.tm)
6195 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6196 || (flag_code == CODE_64BIT
6197 && i.tm.opcode_modifier.jumpbyte)))
6199 unsigned int prefix = DATA_PREFIX_OPCODE;
6201 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6202 prefix = ADDR_PREFIX_OPCODE;
6204 if (!add_prefix (prefix))
6208 /* Set mode64 for an operand. */
6209 if (i.suffix == QWORD_MNEM_SUFFIX
6210 && flag_code == CODE_64BIT
6211 && !i.tm.opcode_modifier.norex64
6212 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6214 && ! (i.operands == 2
6215 && i.tm.base_opcode == 0x90
6216 && i.tm.extension_opcode == None
6217 && operand_type_equal (&i.types [0], &acc64)
6218 && operand_type_equal (&i.types [1], &acc64)))
6224 if (i.reg_operands != 0
6226 && i.tm.opcode_modifier.addrprefixopreg
6227 && !i.tm.opcode_modifier.immext)
6229 /* Check invalid register operand when the address size override
6230 prefix changes the size of register operands. */
6232 enum { need_word, need_dword, need_qword } need;
6234 if (flag_code == CODE_32BIT)
6235 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6238 if (i.prefix[ADDR_PREFIX])
6241 need = flag_code == CODE_64BIT ? need_qword : need_word;
6244 for (op = 0; op < i.operands; op++)
6245 if (i.types[op].bitfield.reg
6246 && ((need == need_word
6247 && !i.op[op].regs->reg_type.bitfield.word)
6248 || (need == need_dword
6249 && !i.op[op].regs->reg_type.bitfield.dword)
6250 || (need == need_qword
6251 && !i.op[op].regs->reg_type.bitfield.qword)))
6253 as_bad (_("invalid register operand size for `%s'"),
6263 check_byte_reg (void)
6267 for (op = i.operands; --op >= 0;)
6269 /* Skip non-register operands. */
6270 if (!i.types[op].bitfield.reg)
6273 /* If this is an eight bit register, it's OK. If it's the 16 or
6274 32 bit version of an eight bit register, we will just use the
6275 low portion, and that's OK too. */
6276 if (i.types[op].bitfield.byte)
6279 /* I/O port address operands are OK too. */
6280 if (i.tm.operand_types[op].bitfield.inoutportreg)
6283 /* crc32 doesn't generate this warning. */
6284 if (i.tm.base_opcode == 0xf20f38f0)
6287 if ((i.types[op].bitfield.word
6288 || i.types[op].bitfield.dword
6289 || i.types[op].bitfield.qword)
6290 && i.op[op].regs->reg_num < 4
6291 /* Prohibit these changes in 64bit mode, since the lowering
6292 would be more complicated. */
6293 && flag_code != CODE_64BIT)
6295 #if REGISTER_WARNINGS
6296 if (!quiet_warnings)
6297 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6299 (i.op[op].regs + (i.types[op].bitfield.word
6300 ? REGNAM_AL - REGNAM_AX
6301 : REGNAM_AL - REGNAM_EAX))->reg_name,
6303 i.op[op].regs->reg_name,
6308 /* Any other register is bad. */
6309 if (i.types[op].bitfield.reg
6310 || i.types[op].bitfield.regmmx
6311 || i.types[op].bitfield.regsimd
6312 || i.types[op].bitfield.sreg2
6313 || i.types[op].bitfield.sreg3
6314 || i.types[op].bitfield.control
6315 || i.types[op].bitfield.debug
6316 || i.types[op].bitfield.test)
6318 as_bad (_("`%s%s' not allowed with `%s%c'"),
6320 i.op[op].regs->reg_name,
6330 check_long_reg (void)
6334 for (op = i.operands; --op >= 0;)
6335 /* Skip non-register operands. */
6336 if (!i.types[op].bitfield.reg)
6338 /* Reject eight bit registers, except where the template requires
6339 them. (eg. movzb) */
6340 else if (i.types[op].bitfield.byte
6341 && (i.tm.operand_types[op].bitfield.reg
6342 || i.tm.operand_types[op].bitfield.acc)
6343 && (i.tm.operand_types[op].bitfield.word
6344 || i.tm.operand_types[op].bitfield.dword))
6346 as_bad (_("`%s%s' not allowed with `%s%c'"),
6348 i.op[op].regs->reg_name,
6353 /* Warn if the e prefix on a general reg is missing. */
6354 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6355 && i.types[op].bitfield.word
6356 && (i.tm.operand_types[op].bitfield.reg
6357 || i.tm.operand_types[op].bitfield.acc)
6358 && i.tm.operand_types[op].bitfield.dword)
6360 /* Prohibit these changes in the 64bit mode, since the
6361 lowering is more complicated. */
6362 if (flag_code == CODE_64BIT)
6364 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6365 register_prefix, i.op[op].regs->reg_name,
6369 #if REGISTER_WARNINGS
6370 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6372 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6373 register_prefix, i.op[op].regs->reg_name, i.suffix);
6376 /* Warn if the r prefix on a general reg is present. */
6377 else if (i.types[op].bitfield.qword
6378 && (i.tm.operand_types[op].bitfield.reg
6379 || i.tm.operand_types[op].bitfield.acc)
6380 && i.tm.operand_types[op].bitfield.dword)
6383 && i.tm.opcode_modifier.toqword
6384 && !i.types[0].bitfield.regsimd)
6386 /* Convert to QWORD. We want REX byte. */
6387 i.suffix = QWORD_MNEM_SUFFIX;
6391 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6392 register_prefix, i.op[op].regs->reg_name,
6401 check_qword_reg (void)
6405 for (op = i.operands; --op >= 0; )
6406 /* Skip non-register operands. */
6407 if (!i.types[op].bitfield.reg)
6409 /* Reject eight bit registers, except where the template requires
6410 them. (eg. movzb) */
6411 else if (i.types[op].bitfield.byte
6412 && (i.tm.operand_types[op].bitfield.reg
6413 || i.tm.operand_types[op].bitfield.acc)
6414 && (i.tm.operand_types[op].bitfield.word
6415 || i.tm.operand_types[op].bitfield.dword))
6417 as_bad (_("`%s%s' not allowed with `%s%c'"),
6419 i.op[op].regs->reg_name,
6424 /* Warn if the r prefix on a general reg is missing. */
6425 else if ((i.types[op].bitfield.word
6426 || i.types[op].bitfield.dword)
6427 && (i.tm.operand_types[op].bitfield.reg
6428 || i.tm.operand_types[op].bitfield.acc)
6429 && i.tm.operand_types[op].bitfield.qword)
6431 /* Prohibit these changes in the 64bit mode, since the
6432 lowering is more complicated. */
6434 && i.tm.opcode_modifier.todword
6435 && !i.types[0].bitfield.regsimd)
6437 /* Convert to DWORD. We don't want REX byte. */
6438 i.suffix = LONG_MNEM_SUFFIX;
6442 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6443 register_prefix, i.op[op].regs->reg_name,
6452 check_word_reg (void)
6455 for (op = i.operands; --op >= 0;)
6456 /* Skip non-register operands. */
6457 if (!i.types[op].bitfield.reg)
6459 /* Reject eight bit registers, except where the template requires
6460 them. (eg. movzb) */
6461 else if (i.types[op].bitfield.byte
6462 && (i.tm.operand_types[op].bitfield.reg
6463 || i.tm.operand_types[op].bitfield.acc)
6464 && (i.tm.operand_types[op].bitfield.word
6465 || i.tm.operand_types[op].bitfield.dword))
6467 as_bad (_("`%s%s' not allowed with `%s%c'"),
6469 i.op[op].regs->reg_name,
6474 /* Warn if the e or r prefix on a general reg is present. */
6475 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6476 && (i.types[op].bitfield.dword
6477 || i.types[op].bitfield.qword)
6478 && (i.tm.operand_types[op].bitfield.reg
6479 || i.tm.operand_types[op].bitfield.acc)
6480 && i.tm.operand_types[op].bitfield.word)
6482 /* Prohibit these changes in the 64bit mode, since the
6483 lowering is more complicated. */
6484 if (flag_code == CODE_64BIT)
6486 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6487 register_prefix, i.op[op].regs->reg_name,
6491 #if REGISTER_WARNINGS
6492 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6494 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6495 register_prefix, i.op[op].regs->reg_name, i.suffix);
6502 update_imm (unsigned int j)
6504 i386_operand_type overlap = i.types[j];
6505 if ((overlap.bitfield.imm8
6506 || overlap.bitfield.imm8s
6507 || overlap.bitfield.imm16
6508 || overlap.bitfield.imm32
6509 || overlap.bitfield.imm32s
6510 || overlap.bitfield.imm64)
6511 && !operand_type_equal (&overlap, &imm8)
6512 && !operand_type_equal (&overlap, &imm8s)
6513 && !operand_type_equal (&overlap, &imm16)
6514 && !operand_type_equal (&overlap, &imm32)
6515 && !operand_type_equal (&overlap, &imm32s)
6516 && !operand_type_equal (&overlap, &imm64))
6520 i386_operand_type temp;
6522 operand_type_set (&temp, 0);
6523 if (i.suffix == BYTE_MNEM_SUFFIX)
6525 temp.bitfield.imm8 = overlap.bitfield.imm8;
6526 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6528 else if (i.suffix == WORD_MNEM_SUFFIX)
6529 temp.bitfield.imm16 = overlap.bitfield.imm16;
6530 else if (i.suffix == QWORD_MNEM_SUFFIX)
6532 temp.bitfield.imm64 = overlap.bitfield.imm64;
6533 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6536 temp.bitfield.imm32 = overlap.bitfield.imm32;
6539 else if (operand_type_equal (&overlap, &imm16_32_32s)
6540 || operand_type_equal (&overlap, &imm16_32)
6541 || operand_type_equal (&overlap, &imm16_32s))
6543 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6548 if (!operand_type_equal (&overlap, &imm8)
6549 && !operand_type_equal (&overlap, &imm8s)
6550 && !operand_type_equal (&overlap, &imm16)
6551 && !operand_type_equal (&overlap, &imm32)
6552 && !operand_type_equal (&overlap, &imm32s)
6553 && !operand_type_equal (&overlap, &imm64))
6555 as_bad (_("no instruction mnemonic suffix given; "
6556 "can't determine immediate size"));
6560 i.types[j] = overlap;
6570 /* Update the first 2 immediate operands. */
6571 n = i.operands > 2 ? 2 : i.operands;
6574 for (j = 0; j < n; j++)
6575 if (update_imm (j) == 0)
6578 /* The 3rd operand can't be immediate operand. */
6579 gas_assert (operand_type_check (i.types[2], imm) == 0);
6586 process_operands (void)
6588 /* Default segment register this instruction will use for memory
6589 accesses. 0 means unknown. This is only for optimizing out
6590 unnecessary segment overrides. */
6591 const seg_entry *default_seg = 0;
6593 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6595 unsigned int dupl = i.operands;
6596 unsigned int dest = dupl - 1;
6599 /* The destination must be an xmm register. */
6600 gas_assert (i.reg_operands
6601 && MAX_OPERANDS > dupl
6602 && operand_type_equal (&i.types[dest], ®xmm));
6604 if (i.tm.operand_types[0].bitfield.acc
6605 && i.tm.operand_types[0].bitfield.xmmword)
6607 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6609 /* Keep xmm0 for instructions with VEX prefix and 3
6611 i.tm.operand_types[0].bitfield.acc = 0;
6612 i.tm.operand_types[0].bitfield.regsimd = 1;
6617 /* We remove the first xmm0 and keep the number of
6618 operands unchanged, which in fact duplicates the
6620 for (j = 1; j < i.operands; j++)
6622 i.op[j - 1] = i.op[j];
6623 i.types[j - 1] = i.types[j];
6624 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6628 else if (i.tm.opcode_modifier.implicit1stxmm0)
6630 gas_assert ((MAX_OPERANDS - 1) > dupl
6631 && (i.tm.opcode_modifier.vexsources
6634 /* Add the implicit xmm0 for instructions with VEX prefix
6636 for (j = i.operands; j > 0; j--)
6638 i.op[j] = i.op[j - 1];
6639 i.types[j] = i.types[j - 1];
6640 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6643 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6644 i.types[0] = regxmm;
6645 i.tm.operand_types[0] = regxmm;
6648 i.reg_operands += 2;
6653 i.op[dupl] = i.op[dest];
6654 i.types[dupl] = i.types[dest];
6655 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6664 i.op[dupl] = i.op[dest];
6665 i.types[dupl] = i.types[dest];
6666 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6669 if (i.tm.opcode_modifier.immext)
6672 else if (i.tm.operand_types[0].bitfield.acc
6673 && i.tm.operand_types[0].bitfield.xmmword)
6677 for (j = 1; j < i.operands; j++)
6679 i.op[j - 1] = i.op[j];
6680 i.types[j - 1] = i.types[j];
6682 /* We need to adjust fields in i.tm since they are used by
6683 build_modrm_byte. */
6684 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6691 else if (i.tm.opcode_modifier.implicitquadgroup)
6693 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6695 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6696 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6697 regnum = register_number (i.op[1].regs);
6698 first_reg_in_group = regnum & ~3;
6699 last_reg_in_group = first_reg_in_group + 3;
6700 if (regnum != first_reg_in_group)
6701 as_warn (_("source register `%s%s' implicitly denotes"
6702 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6703 register_prefix, i.op[1].regs->reg_name,
6704 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6705 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6708 else if (i.tm.opcode_modifier.regkludge)
6710 /* The imul $imm, %reg instruction is converted into
6711 imul $imm, %reg, %reg, and the clr %reg instruction
6712 is converted into xor %reg, %reg. */
6714 unsigned int first_reg_op;
6716 if (operand_type_check (i.types[0], reg))
6720 /* Pretend we saw the extra register operand. */
6721 gas_assert (i.reg_operands == 1
6722 && i.op[first_reg_op + 1].regs == 0);
6723 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6724 i.types[first_reg_op + 1] = i.types[first_reg_op];
6729 if (i.tm.opcode_modifier.shortform)
6731 if (i.types[0].bitfield.sreg2
6732 || i.types[0].bitfield.sreg3)
6734 if (i.tm.base_opcode == POP_SEG_SHORT
6735 && i.op[0].regs->reg_num == 1)
6737 as_bad (_("you can't `pop %scs'"), register_prefix);
6740 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6741 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6746 /* The register or float register operand is in operand
6750 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6751 || operand_type_check (i.types[0], reg))
6755 /* Register goes in low 3 bits of opcode. */
6756 i.tm.base_opcode |= i.op[op].regs->reg_num;
6757 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6759 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6761 /* Warn about some common errors, but press on regardless.
6762 The first case can be generated by gcc (<= 2.8.1). */
6763 if (i.operands == 2)
6765 /* Reversed arguments on faddp, fsubp, etc. */
6766 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6767 register_prefix, i.op[!intel_syntax].regs->reg_name,
6768 register_prefix, i.op[intel_syntax].regs->reg_name);
6772 /* Extraneous `l' suffix on fp insn. */
6773 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6774 register_prefix, i.op[0].regs->reg_name);
6779 else if (i.tm.opcode_modifier.modrm)
6781 /* The opcode is completed (modulo i.tm.extension_opcode which
6782 must be put into the modrm byte). Now, we make the modrm and
6783 index base bytes based on all the info we've collected. */
6785 default_seg = build_modrm_byte ();
6787 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6791 else if (i.tm.opcode_modifier.isstring)
6793 /* For the string instructions that allow a segment override
6794 on one of their operands, the default segment is ds. */
6798 if (i.tm.base_opcode == 0x8d /* lea */
6801 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6803 /* If a segment was explicitly specified, and the specified segment
6804 is not the default, use an opcode prefix to select it. If we
6805 never figured out what the default segment is, then default_seg
6806 will be zero at this point, and the specified segment prefix will
6808 if ((i.seg[0]) && (i.seg[0] != default_seg))
6810 if (!add_prefix (i.seg[0]->seg_prefix))
6816 static const seg_entry *
6817 build_modrm_byte (void)
6819 const seg_entry *default_seg = 0;
6820 unsigned int source, dest;
6823 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6826 unsigned int nds, reg_slot;
6829 dest = i.operands - 1;
6832 /* There are 2 kinds of instructions:
6833 1. 5 operands: 4 register operands or 3 register operands
6834 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6835 VexW0 or VexW1. The destination must be either XMM, YMM or
6837 2. 4 operands: 4 register operands or 3 register operands
6838 plus 1 memory operand, with VexXDS. */
6839 gas_assert ((i.reg_operands == 4
6840 || (i.reg_operands == 3 && i.mem_operands == 1))
6841 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6842 && i.tm.opcode_modifier.vexw
6843 && i.tm.operand_types[dest].bitfield.regsimd);
6845 /* If VexW1 is set, the first non-immediate operand is the source and
6846 the second non-immediate one is encoded in the immediate operand. */
6847 if (i.tm.opcode_modifier.vexw == VEXW1)
6849 source = i.imm_operands;
6850 reg_slot = i.imm_operands + 1;
6854 source = i.imm_operands + 1;
6855 reg_slot = i.imm_operands;
6858 if (i.imm_operands == 0)
6860 /* When there is no immediate operand, generate an 8bit
6861 immediate operand to encode the first operand. */
6862 exp = &im_expressions[i.imm_operands++];
6863 i.op[i.operands].imms = exp;
6864 i.types[i.operands] = imm8;
6867 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6868 exp->X_op = O_constant;
6869 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6870 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6874 unsigned int imm_slot;
6876 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6878 if (i.tm.opcode_modifier.immext)
6880 /* When ImmExt is set, the immediate byte is the last
6882 imm_slot = i.operands - 1;
6890 /* Turn on Imm8 so that output_imm will generate it. */
6891 i.types[imm_slot].bitfield.imm8 = 1;
6894 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6895 i.op[imm_slot].imms->X_add_number
6896 |= register_number (i.op[reg_slot].regs) << 4;
6897 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6900 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6901 i.vex.register_specifier = i.op[nds].regs;
6906 /* i.reg_operands MUST be the number of real register operands;
6907 implicit registers do not count. If there are 3 register
6908 operands, it must be a instruction with VexNDS. For a
6909 instruction with VexNDD, the destination register is encoded
6910 in VEX prefix. If there are 4 register operands, it must be
6911 a instruction with VEX prefix and 3 sources. */
6912 if (i.mem_operands == 0
6913 && ((i.reg_operands == 2
6914 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6915 || (i.reg_operands == 3
6916 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6917 || (i.reg_operands == 4 && vex_3_sources)))
6925 /* When there are 3 operands, one of them may be immediate,
6926 which may be the first or the last operand. Otherwise,
6927 the first operand must be shift count register (cl) or it
6928 is an instruction with VexNDS. */
6929 gas_assert (i.imm_operands == 1
6930 || (i.imm_operands == 0
6931 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6932 || i.types[0].bitfield.shiftcount)));
6933 if (operand_type_check (i.types[0], imm)
6934 || i.types[0].bitfield.shiftcount)
6940 /* When there are 4 operands, the first two must be 8bit
6941 immediate operands. The source operand will be the 3rd
6944 For instructions with VexNDS, if the first operand
6945 an imm8, the source operand is the 2nd one. If the last
6946 operand is imm8, the source operand is the first one. */
6947 gas_assert ((i.imm_operands == 2
6948 && i.types[0].bitfield.imm8
6949 && i.types[1].bitfield.imm8)
6950 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6951 && i.imm_operands == 1
6952 && (i.types[0].bitfield.imm8
6953 || i.types[i.operands - 1].bitfield.imm8
6955 if (i.imm_operands == 2)
6959 if (i.types[0].bitfield.imm8)
6966 if (is_evex_encoding (&i.tm))
6968 /* For EVEX instructions, when there are 5 operands, the
6969 first one must be immediate operand. If the second one
6970 is immediate operand, the source operand is the 3th
6971 one. If the last one is immediate operand, the source
6972 operand is the 2nd one. */
6973 gas_assert (i.imm_operands == 2
6974 && i.tm.opcode_modifier.sae
6975 && operand_type_check (i.types[0], imm));
6976 if (operand_type_check (i.types[1], imm))
6978 else if (operand_type_check (i.types[4], imm))
6992 /* RC/SAE operand could be between DEST and SRC. That happens
6993 when one operand is GPR and the other one is XMM/YMM/ZMM
6995 if (i.rounding && i.rounding->operand == (int) dest)
6998 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7000 /* For instructions with VexNDS, the register-only source
7001 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7002 register. It is encoded in VEX prefix. We need to
7003 clear RegMem bit before calling operand_type_equal. */
7005 i386_operand_type op;
7008 /* Check register-only source operand when two source
7009 operands are swapped. */
7010 if (!i.tm.operand_types[source].bitfield.baseindex
7011 && i.tm.operand_types[dest].bitfield.baseindex)
7019 op = i.tm.operand_types[vvvv];
7020 op.bitfield.regmem = 0;
7021 if ((dest + 1) >= i.operands
7022 || ((!op.bitfield.reg
7023 || (!op.bitfield.dword && !op.bitfield.qword))
7024 && !op.bitfield.regsimd
7025 && !operand_type_equal (&op, ®mask)))
7027 i.vex.register_specifier = i.op[vvvv].regs;
7033 /* One of the register operands will be encoded in the i.tm.reg
7034 field, the other in the combined i.tm.mode and i.tm.regmem
7035 fields. If no form of this instruction supports a memory
7036 destination operand, then we assume the source operand may
7037 sometimes be a memory operand and so we need to store the
7038 destination in the i.rm.reg field. */
7039 if (!i.tm.operand_types[dest].bitfield.regmem
7040 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7042 i.rm.reg = i.op[dest].regs->reg_num;
7043 i.rm.regmem = i.op[source].regs->reg_num;
7044 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7046 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7048 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7050 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7055 i.rm.reg = i.op[source].regs->reg_num;
7056 i.rm.regmem = i.op[dest].regs->reg_num;
7057 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7059 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7061 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7063 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7066 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7068 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7071 add_prefix (LOCK_PREFIX_OPCODE);
7075 { /* If it's not 2 reg operands... */
7080 unsigned int fake_zero_displacement = 0;
7083 for (op = 0; op < i.operands; op++)
7084 if (operand_type_check (i.types[op], anymem))
7086 gas_assert (op < i.operands);
7088 if (i.tm.opcode_modifier.vecsib)
7090 if (i.index_reg->reg_num == RegEiz
7091 || i.index_reg->reg_num == RegRiz)
7094 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7097 i.sib.base = NO_BASE_REGISTER;
7098 i.sib.scale = i.log2_scale_factor;
7099 i.types[op].bitfield.disp8 = 0;
7100 i.types[op].bitfield.disp16 = 0;
7101 i.types[op].bitfield.disp64 = 0;
7102 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7104 /* Must be 32 bit */
7105 i.types[op].bitfield.disp32 = 1;
7106 i.types[op].bitfield.disp32s = 0;
7110 i.types[op].bitfield.disp32 = 0;
7111 i.types[op].bitfield.disp32s = 1;
7114 i.sib.index = i.index_reg->reg_num;
7115 if ((i.index_reg->reg_flags & RegRex) != 0)
7117 if ((i.index_reg->reg_flags & RegVRex) != 0)
7123 if (i.base_reg == 0)
7126 if (!i.disp_operands)
7127 fake_zero_displacement = 1;
7128 if (i.index_reg == 0)
7130 i386_operand_type newdisp;
7132 gas_assert (!i.tm.opcode_modifier.vecsib);
7133 /* Operand is just <disp> */
7134 if (flag_code == CODE_64BIT)
7136 /* 64bit mode overwrites the 32bit absolute
7137 addressing by RIP relative addressing and
7138 absolute addressing is encoded by one of the
7139 redundant SIB forms. */
7140 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7141 i.sib.base = NO_BASE_REGISTER;
7142 i.sib.index = NO_INDEX_REGISTER;
7143 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7145 else if ((flag_code == CODE_16BIT)
7146 ^ (i.prefix[ADDR_PREFIX] != 0))
7148 i.rm.regmem = NO_BASE_REGISTER_16;
7153 i.rm.regmem = NO_BASE_REGISTER;
7156 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7157 i.types[op] = operand_type_or (i.types[op], newdisp);
7159 else if (!i.tm.opcode_modifier.vecsib)
7161 /* !i.base_reg && i.index_reg */
7162 if (i.index_reg->reg_num == RegEiz
7163 || i.index_reg->reg_num == RegRiz)
7164 i.sib.index = NO_INDEX_REGISTER;
7166 i.sib.index = i.index_reg->reg_num;
7167 i.sib.base = NO_BASE_REGISTER;
7168 i.sib.scale = i.log2_scale_factor;
7169 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7170 i.types[op].bitfield.disp8 = 0;
7171 i.types[op].bitfield.disp16 = 0;
7172 i.types[op].bitfield.disp64 = 0;
7173 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7175 /* Must be 32 bit */
7176 i.types[op].bitfield.disp32 = 1;
7177 i.types[op].bitfield.disp32s = 0;
7181 i.types[op].bitfield.disp32 = 0;
7182 i.types[op].bitfield.disp32s = 1;
7184 if ((i.index_reg->reg_flags & RegRex) != 0)
7188 /* RIP addressing for 64bit mode. */
7189 else if (i.base_reg->reg_num == RegRip ||
7190 i.base_reg->reg_num == RegEip)
7192 gas_assert (!i.tm.opcode_modifier.vecsib);
7193 i.rm.regmem = NO_BASE_REGISTER;
7194 i.types[op].bitfield.disp8 = 0;
7195 i.types[op].bitfield.disp16 = 0;
7196 i.types[op].bitfield.disp32 = 0;
7197 i.types[op].bitfield.disp32s = 1;
7198 i.types[op].bitfield.disp64 = 0;
7199 i.flags[op] |= Operand_PCrel;
7200 if (! i.disp_operands)
7201 fake_zero_displacement = 1;
7203 else if (i.base_reg->reg_type.bitfield.word)
7205 gas_assert (!i.tm.opcode_modifier.vecsib);
7206 switch (i.base_reg->reg_num)
7209 if (i.index_reg == 0)
7211 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7212 i.rm.regmem = i.index_reg->reg_num - 6;
7216 if (i.index_reg == 0)
7219 if (operand_type_check (i.types[op], disp) == 0)
7221 /* fake (%bp) into 0(%bp) */
7222 i.types[op].bitfield.disp8 = 1;
7223 fake_zero_displacement = 1;
7226 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7227 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7229 default: /* (%si) -> 4 or (%di) -> 5 */
7230 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7232 i.rm.mode = mode_from_disp_size (i.types[op]);
7234 else /* i.base_reg and 32/64 bit mode */
7236 if (flag_code == CODE_64BIT
7237 && operand_type_check (i.types[op], disp))
7239 i.types[op].bitfield.disp16 = 0;
7240 i.types[op].bitfield.disp64 = 0;
7241 if (i.prefix[ADDR_PREFIX] == 0)
7243 i.types[op].bitfield.disp32 = 0;
7244 i.types[op].bitfield.disp32s = 1;
7248 i.types[op].bitfield.disp32 = 1;
7249 i.types[op].bitfield.disp32s = 0;
7253 if (!i.tm.opcode_modifier.vecsib)
7254 i.rm.regmem = i.base_reg->reg_num;
7255 if ((i.base_reg->reg_flags & RegRex) != 0)
7257 i.sib.base = i.base_reg->reg_num;
7258 /* x86-64 ignores REX prefix bit here to avoid decoder
7260 if (!(i.base_reg->reg_flags & RegRex)
7261 && (i.base_reg->reg_num == EBP_REG_NUM
7262 || i.base_reg->reg_num == ESP_REG_NUM))
7264 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7266 fake_zero_displacement = 1;
7267 i.types[op].bitfield.disp8 = 1;
7269 i.sib.scale = i.log2_scale_factor;
7270 if (i.index_reg == 0)
7272 gas_assert (!i.tm.opcode_modifier.vecsib);
7273 /* <disp>(%esp) becomes two byte modrm with no index
7274 register. We've already stored the code for esp
7275 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7276 Any base register besides %esp will not use the
7277 extra modrm byte. */
7278 i.sib.index = NO_INDEX_REGISTER;
7280 else if (!i.tm.opcode_modifier.vecsib)
7282 if (i.index_reg->reg_num == RegEiz
7283 || i.index_reg->reg_num == RegRiz)
7284 i.sib.index = NO_INDEX_REGISTER;
7286 i.sib.index = i.index_reg->reg_num;
7287 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7288 if ((i.index_reg->reg_flags & RegRex) != 0)
7293 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7294 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7298 if (!fake_zero_displacement
7302 fake_zero_displacement = 1;
7303 if (i.disp_encoding == disp_encoding_8bit)
7304 i.types[op].bitfield.disp8 = 1;
7306 i.types[op].bitfield.disp32 = 1;
7308 i.rm.mode = mode_from_disp_size (i.types[op]);
7312 if (fake_zero_displacement)
7314 /* Fakes a zero displacement assuming that i.types[op]
7315 holds the correct displacement size. */
7318 gas_assert (i.op[op].disps == 0);
7319 exp = &disp_expressions[i.disp_operands++];
7320 i.op[op].disps = exp;
7321 exp->X_op = O_constant;
7322 exp->X_add_number = 0;
7323 exp->X_add_symbol = (symbolS *) 0;
7324 exp->X_op_symbol = (symbolS *) 0;
7332 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7334 if (operand_type_check (i.types[0], imm))
7335 i.vex.register_specifier = NULL;
7338 /* VEX.vvvv encodes one of the sources when the first
7339 operand is not an immediate. */
7340 if (i.tm.opcode_modifier.vexw == VEXW0)
7341 i.vex.register_specifier = i.op[0].regs;
7343 i.vex.register_specifier = i.op[1].regs;
7346 /* Destination is a XMM register encoded in the ModRM.reg
7348 i.rm.reg = i.op[2].regs->reg_num;
7349 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7352 /* ModRM.rm and VEX.B encodes the other source. */
7353 if (!i.mem_operands)
7357 if (i.tm.opcode_modifier.vexw == VEXW0)
7358 i.rm.regmem = i.op[1].regs->reg_num;
7360 i.rm.regmem = i.op[0].regs->reg_num;
7362 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7366 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7368 i.vex.register_specifier = i.op[2].regs;
7369 if (!i.mem_operands)
7372 i.rm.regmem = i.op[1].regs->reg_num;
7373 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7377 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7378 (if any) based on i.tm.extension_opcode. Again, we must be
7379 careful to make sure that segment/control/debug/test/MMX
7380 registers are coded into the i.rm.reg field. */
7381 else if (i.reg_operands)
7384 unsigned int vex_reg = ~0;
7386 for (op = 0; op < i.operands; op++)
7387 if (i.types[op].bitfield.reg
7388 || i.types[op].bitfield.regmmx
7389 || i.types[op].bitfield.regsimd
7390 || i.types[op].bitfield.regbnd
7391 || i.types[op].bitfield.regmask
7392 || i.types[op].bitfield.sreg2
7393 || i.types[op].bitfield.sreg3
7394 || i.types[op].bitfield.control
7395 || i.types[op].bitfield.debug
7396 || i.types[op].bitfield.test)
7401 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7403 /* For instructions with VexNDS, the register-only
7404 source operand is encoded in VEX prefix. */
7405 gas_assert (mem != (unsigned int) ~0);
7410 gas_assert (op < i.operands);
7414 /* Check register-only source operand when two source
7415 operands are swapped. */
7416 if (!i.tm.operand_types[op].bitfield.baseindex
7417 && i.tm.operand_types[op + 1].bitfield.baseindex)
7421 gas_assert (mem == (vex_reg + 1)
7422 && op < i.operands);
7427 gas_assert (vex_reg < i.operands);
7431 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7433 /* For instructions with VexNDD, the register destination
7434 is encoded in VEX prefix. */
7435 if (i.mem_operands == 0)
7437 /* There is no memory operand. */
7438 gas_assert ((op + 2) == i.operands);
7443 /* There are only 2 non-immediate operands. */
7444 gas_assert (op < i.imm_operands + 2
7445 && i.operands == i.imm_operands + 2);
7446 vex_reg = i.imm_operands + 1;
7450 gas_assert (op < i.operands);
7452 if (vex_reg != (unsigned int) ~0)
7454 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7456 if ((!type->bitfield.reg
7457 || (!type->bitfield.dword && !type->bitfield.qword))
7458 && !type->bitfield.regsimd
7459 && !operand_type_equal (type, ®mask))
7462 i.vex.register_specifier = i.op[vex_reg].regs;
7465 /* Don't set OP operand twice. */
7468 /* If there is an extension opcode to put here, the
7469 register number must be put into the regmem field. */
7470 if (i.tm.extension_opcode != None)
7472 i.rm.regmem = i.op[op].regs->reg_num;
7473 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7475 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7480 i.rm.reg = i.op[op].regs->reg_num;
7481 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7483 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7488 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7489 must set it to 3 to indicate this is a register operand
7490 in the regmem field. */
7491 if (!i.mem_operands)
7495 /* Fill in i.rm.reg field with extension opcode (if any). */
7496 if (i.tm.extension_opcode != None)
7497 i.rm.reg = i.tm.extension_opcode;
7503 output_branch (void)
7509 relax_substateT subtype;
7513 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7514 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7517 if (i.prefix[DATA_PREFIX] != 0)
7523 /* Pentium4 branch hints. */
7524 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7525 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7530 if (i.prefix[REX_PREFIX] != 0)
7536 /* BND prefixed jump. */
7537 if (i.prefix[BND_PREFIX] != 0)
7539 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7543 if (i.prefixes != 0 && !intel_syntax)
7544 as_warn (_("skipping prefixes on this instruction"));
7546 /* It's always a symbol; End frag & setup for relax.
7547 Make sure there is enough room in this frag for the largest
7548 instruction we may generate in md_convert_frag. This is 2
7549 bytes for the opcode and room for the prefix and largest
7551 frag_grow (prefix + 2 + 4);
7552 /* Prefix and 1 opcode byte go in fr_fix. */
7553 p = frag_more (prefix + 1);
7554 if (i.prefix[DATA_PREFIX] != 0)
7555 *p++ = DATA_PREFIX_OPCODE;
7556 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7557 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7558 *p++ = i.prefix[SEG_PREFIX];
7559 if (i.prefix[REX_PREFIX] != 0)
7560 *p++ = i.prefix[REX_PREFIX];
7561 *p = i.tm.base_opcode;
7563 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7564 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7565 else if (cpu_arch_flags.bitfield.cpui386)
7566 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7568 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7571 sym = i.op[0].disps->X_add_symbol;
7572 off = i.op[0].disps->X_add_number;
7574 if (i.op[0].disps->X_op != O_constant
7575 && i.op[0].disps->X_op != O_symbol)
7577 /* Handle complex expressions. */
7578 sym = make_expr_symbol (i.op[0].disps);
7582 /* 1 possible extra opcode + 4 byte displacement go in var part.
7583 Pass reloc in fr_var. */
7584 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7588 /* Return TRUE iff PLT32 relocation should be used for branching to
7592 need_plt32_p (symbolS *s)
7594 /* PLT32 relocation is ELF only. */
7598 /* Since there is no need to prepare for PLT branch on x86-64, we
7599 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7600 be used as a marker for 32-bit PC-relative branches. */
7604 /* Weak or undefined symbol need PLT32 relocation. */
7605 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7608 /* Non-global symbol doesn't need PLT32 relocation. */
7609 if (! S_IS_EXTERNAL (s))
7612 /* Other global symbols need PLT32 relocation. NB: Symbol with
7613 non-default visibilities are treated as normal global symbol
7614 so that PLT32 relocation can be used as a marker for 32-bit
7615 PC-relative branches. It is useful for linker relaxation. */
7626 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7628 if (i.tm.opcode_modifier.jumpbyte)
7630 /* This is a loop or jecxz type instruction. */
7632 if (i.prefix[ADDR_PREFIX] != 0)
7634 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7637 /* Pentium4 branch hints. */
7638 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7639 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7641 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7650 if (flag_code == CODE_16BIT)
7653 if (i.prefix[DATA_PREFIX] != 0)
7655 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7665 if (i.prefix[REX_PREFIX] != 0)
7667 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7671 /* BND prefixed jump. */
7672 if (i.prefix[BND_PREFIX] != 0)
7674 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7678 if (i.prefixes != 0 && !intel_syntax)
7679 as_warn (_("skipping prefixes on this instruction"));
7681 p = frag_more (i.tm.opcode_length + size);
7682 switch (i.tm.opcode_length)
7685 *p++ = i.tm.base_opcode >> 8;
7688 *p++ = i.tm.base_opcode;
7694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7696 && jump_reloc == NO_RELOC
7697 && need_plt32_p (i.op[0].disps->X_add_symbol))
7698 jump_reloc = BFD_RELOC_X86_64_PLT32;
7701 jump_reloc = reloc (size, 1, 1, jump_reloc);
7703 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7704 i.op[0].disps, 1, jump_reloc);
7706 /* All jumps handled here are signed, but don't use a signed limit
7707 check for 32 and 16 bit jumps as we want to allow wrap around at
7708 4G and 64k respectively. */
7710 fixP->fx_signed = 1;
7714 output_interseg_jump (void)
7722 if (flag_code == CODE_16BIT)
7726 if (i.prefix[DATA_PREFIX] != 0)
7732 if (i.prefix[REX_PREFIX] != 0)
7742 if (i.prefixes != 0 && !intel_syntax)
7743 as_warn (_("skipping prefixes on this instruction"));
7745 /* 1 opcode; 2 segment; offset */
7746 p = frag_more (prefix + 1 + 2 + size);
7748 if (i.prefix[DATA_PREFIX] != 0)
7749 *p++ = DATA_PREFIX_OPCODE;
7751 if (i.prefix[REX_PREFIX] != 0)
7752 *p++ = i.prefix[REX_PREFIX];
7754 *p++ = i.tm.base_opcode;
7755 if (i.op[1].imms->X_op == O_constant)
7757 offsetT n = i.op[1].imms->X_add_number;
7760 && !fits_in_unsigned_word (n)
7761 && !fits_in_signed_word (n))
7763 as_bad (_("16-bit jump out of range"));
7766 md_number_to_chars (p, n, size);
7769 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7770 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7771 if (i.op[0].imms->X_op != O_constant)
7772 as_bad (_("can't handle non absolute segment in `%s'"),
7774 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7780 fragS *insn_start_frag;
7781 offsetT insn_start_off;
7783 /* Tie dwarf2 debug info to the address at the start of the insn.
7784 We can't do this after the insn has been output as the current
7785 frag may have been closed off. eg. by frag_var. */
7786 dwarf2_emit_insn (0);
7788 insn_start_frag = frag_now;
7789 insn_start_off = frag_now_fix ();
7792 if (i.tm.opcode_modifier.jump)
7794 else if (i.tm.opcode_modifier.jumpbyte
7795 || i.tm.opcode_modifier.jumpdword)
7797 else if (i.tm.opcode_modifier.jumpintersegment)
7798 output_interseg_jump ();
7801 /* Output normal instructions here. */
7805 unsigned int prefix;
7808 && i.tm.base_opcode == 0xfae
7810 && i.imm_operands == 1
7811 && (i.op[0].imms->X_add_number == 0xe8
7812 || i.op[0].imms->X_add_number == 0xf0
7813 || i.op[0].imms->X_add_number == 0xf8))
7815 /* Encode lfence, mfence, and sfence as
7816 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7817 offsetT val = 0x240483f0ULL;
7819 md_number_to_chars (p, val, 5);
7823 /* Some processors fail on LOCK prefix. This options makes
7824 assembler ignore LOCK prefix and serves as a workaround. */
7825 if (omit_lock_prefix)
7827 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7829 i.prefix[LOCK_PREFIX] = 0;
7832 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7833 don't need the explicit prefix. */
7834 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7836 switch (i.tm.opcode_length)
7839 if (i.tm.base_opcode & 0xff000000)
7841 prefix = (i.tm.base_opcode >> 24) & 0xff;
7842 add_prefix (prefix);
7846 if ((i.tm.base_opcode & 0xff0000) != 0)
7848 prefix = (i.tm.base_opcode >> 16) & 0xff;
7849 if (!i.tm.cpu_flags.bitfield.cpupadlock
7850 || prefix != REPE_PREFIX_OPCODE
7851 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
7852 add_prefix (prefix);
7858 /* Check for pseudo prefixes. */
7859 as_bad_where (insn_start_frag->fr_file,
7860 insn_start_frag->fr_line,
7861 _("pseudo prefix without instruction"));
7867 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7868 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7869 R_X86_64_GOTTPOFF relocation so that linker can safely
7870 perform IE->LE optimization. */
7871 if (x86_elf_abi == X86_64_X32_ABI
7873 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7874 && i.prefix[REX_PREFIX] == 0)
7875 add_prefix (REX_OPCODE);
7878 /* The prefix bytes. */
7879 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7881 FRAG_APPEND_1_CHAR (*q);
7885 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7890 /* REX byte is encoded in VEX prefix. */
7894 FRAG_APPEND_1_CHAR (*q);
7897 /* There should be no other prefixes for instructions
7902 /* For EVEX instructions i.vrex should become 0 after
7903 build_evex_prefix. For VEX instructions upper 16 registers
7904 aren't available, so VREX should be 0. */
7907 /* Now the VEX prefix. */
7908 p = frag_more (i.vex.length);
7909 for (j = 0; j < i.vex.length; j++)
7910 p[j] = i.vex.bytes[j];
7913 /* Now the opcode; be careful about word order here! */
7914 if (i.tm.opcode_length == 1)
7916 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7920 switch (i.tm.opcode_length)
7924 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7925 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7929 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7939 /* Put out high byte first: can't use md_number_to_chars! */
7940 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7941 *p = i.tm.base_opcode & 0xff;
7944 /* Now the modrm byte and sib byte (if present). */
7945 if (i.tm.opcode_modifier.modrm)
7947 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7950 /* If i.rm.regmem == ESP (4)
7951 && i.rm.mode != (Register mode)
7953 ==> need second modrm byte. */
7954 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7956 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7957 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7959 | i.sib.scale << 6));
7962 if (i.disp_operands)
7963 output_disp (insn_start_frag, insn_start_off);
7966 output_imm (insn_start_frag, insn_start_off);
7972 pi ("" /*line*/, &i);
7974 #endif /* DEBUG386 */
7977 /* Return the size of the displacement operand N. */
7980 disp_size (unsigned int n)
7984 if (i.types[n].bitfield.disp64)
7986 else if (i.types[n].bitfield.disp8)
7988 else if (i.types[n].bitfield.disp16)
7993 /* Return the size of the immediate operand N. */
7996 imm_size (unsigned int n)
7999 if (i.types[n].bitfield.imm64)
8001 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8003 else if (i.types[n].bitfield.imm16)
8009 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
8014 for (n = 0; n < i.operands; n++)
8016 if (operand_type_check (i.types[n], disp))
8018 if (i.op[n].disps->X_op == O_constant)
8020 int size = disp_size (n);
8021 offsetT val = i.op[n].disps->X_add_number;
8023 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8025 p = frag_more (size);
8026 md_number_to_chars (p, val, size);
8030 enum bfd_reloc_code_real reloc_type;
8031 int size = disp_size (n);
8032 int sign = i.types[n].bitfield.disp32s;
8033 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8036 /* We can't have 8 bit displacement here. */
8037 gas_assert (!i.types[n].bitfield.disp8);
8039 /* The PC relative address is computed relative
8040 to the instruction boundary, so in case immediate
8041 fields follows, we need to adjust the value. */
8042 if (pcrel && i.imm_operands)
8047 for (n1 = 0; n1 < i.operands; n1++)
8048 if (operand_type_check (i.types[n1], imm))
8050 /* Only one immediate is allowed for PC
8051 relative address. */
8052 gas_assert (sz == 0);
8054 i.op[n].disps->X_add_number -= sz;
8056 /* We should find the immediate. */
8057 gas_assert (sz != 0);
8060 p = frag_more (size);
8061 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8063 && GOT_symbol == i.op[n].disps->X_add_symbol
8064 && (((reloc_type == BFD_RELOC_32
8065 || reloc_type == BFD_RELOC_X86_64_32S
8066 || (reloc_type == BFD_RELOC_64
8068 && (i.op[n].disps->X_op == O_symbol
8069 || (i.op[n].disps->X_op == O_add
8070 && ((symbol_get_value_expression
8071 (i.op[n].disps->X_op_symbol)->X_op)
8073 || reloc_type == BFD_RELOC_32_PCREL))
8077 if (insn_start_frag == frag_now)
8078 add = (p - frag_now->fr_literal) - insn_start_off;
8083 add = insn_start_frag->fr_fix - insn_start_off;
8084 for (fr = insn_start_frag->fr_next;
8085 fr && fr != frag_now; fr = fr->fr_next)
8087 add += p - frag_now->fr_literal;
8092 reloc_type = BFD_RELOC_386_GOTPC;
8093 i.op[n].imms->X_add_number += add;
8095 else if (reloc_type == BFD_RELOC_64)
8096 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8098 /* Don't do the adjustment for x86-64, as there
8099 the pcrel addressing is relative to the _next_
8100 insn, and that is taken care of in other code. */
8101 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8103 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8104 size, i.op[n].disps, pcrel,
8106 /* Check for "call/jmp *mem", "mov mem, %reg",
8107 "test %reg, mem" and "binop mem, %reg" where binop
8108 is one of adc, add, and, cmp, or, sbb, sub, xor
8109 instructions. Always generate R_386_GOT32X for
8110 "sym*GOT" operand in 32-bit mode. */
8111 if ((generate_relax_relocations
8114 && i.rm.regmem == 5))
8116 || (i.rm.mode == 0 && i.rm.regmem == 5))
8117 && ((i.operands == 1
8118 && i.tm.base_opcode == 0xff
8119 && (i.rm.reg == 2 || i.rm.reg == 4))
8121 && (i.tm.base_opcode == 0x8b
8122 || i.tm.base_opcode == 0x85
8123 || (i.tm.base_opcode & 0xc7) == 0x03))))
8127 fixP->fx_tcbit = i.rex != 0;
8129 && (i.base_reg->reg_num == RegRip
8130 || i.base_reg->reg_num == RegEip))
8131 fixP->fx_tcbit2 = 1;
8134 fixP->fx_tcbit2 = 1;
8142 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8147 for (n = 0; n < i.operands; n++)
8149 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8150 if (i.rounding && (int) n == i.rounding->operand)
8153 if (operand_type_check (i.types[n], imm))
8155 if (i.op[n].imms->X_op == O_constant)
8157 int size = imm_size (n);
8160 val = offset_in_range (i.op[n].imms->X_add_number,
8162 p = frag_more (size);
8163 md_number_to_chars (p, val, size);
8167 /* Not absolute_section.
8168 Need a 32-bit fixup (don't support 8bit
8169 non-absolute imms). Try to support other
8171 enum bfd_reloc_code_real reloc_type;
8172 int size = imm_size (n);
8175 if (i.types[n].bitfield.imm32s
8176 && (i.suffix == QWORD_MNEM_SUFFIX
8177 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8182 p = frag_more (size);
8183 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8185 /* This is tough to explain. We end up with this one if we
8186 * have operands that look like
8187 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8188 * obtain the absolute address of the GOT, and it is strongly
8189 * preferable from a performance point of view to avoid using
8190 * a runtime relocation for this. The actual sequence of
8191 * instructions often look something like:
8196 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8198 * The call and pop essentially return the absolute address
8199 * of the label .L66 and store it in %ebx. The linker itself
8200 * will ultimately change the first operand of the addl so
8201 * that %ebx points to the GOT, but to keep things simple, the
8202 * .o file must have this operand set so that it generates not
8203 * the absolute address of .L66, but the absolute address of
8204 * itself. This allows the linker itself simply treat a GOTPC
8205 * relocation as asking for a pcrel offset to the GOT to be
8206 * added in, and the addend of the relocation is stored in the
8207 * operand field for the instruction itself.
8209 * Our job here is to fix the operand so that it would add
8210 * the correct offset so that %ebx would point to itself. The
8211 * thing that is tricky is that .-.L66 will point to the
8212 * beginning of the instruction, so we need to further modify
8213 * the operand so that it will point to itself. There are
8214 * other cases where you have something like:
8216 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8218 * and here no correction would be required. Internally in
8219 * the assembler we treat operands of this form as not being
8220 * pcrel since the '.' is explicitly mentioned, and I wonder
8221 * whether it would simplify matters to do it this way. Who
8222 * knows. In earlier versions of the PIC patches, the
8223 * pcrel_adjust field was used to store the correction, but
8224 * since the expression is not pcrel, I felt it would be
8225 * confusing to do it this way. */
8227 if ((reloc_type == BFD_RELOC_32
8228 || reloc_type == BFD_RELOC_X86_64_32S
8229 || reloc_type == BFD_RELOC_64)
8231 && GOT_symbol == i.op[n].imms->X_add_symbol
8232 && (i.op[n].imms->X_op == O_symbol
8233 || (i.op[n].imms->X_op == O_add
8234 && ((symbol_get_value_expression
8235 (i.op[n].imms->X_op_symbol)->X_op)
8240 if (insn_start_frag == frag_now)
8241 add = (p - frag_now->fr_literal) - insn_start_off;
8246 add = insn_start_frag->fr_fix - insn_start_off;
8247 for (fr = insn_start_frag->fr_next;
8248 fr && fr != frag_now; fr = fr->fr_next)
8250 add += p - frag_now->fr_literal;
8254 reloc_type = BFD_RELOC_386_GOTPC;
8256 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8258 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8259 i.op[n].imms->X_add_number += add;
8261 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8262 i.op[n].imms, 0, reloc_type);
8268 /* x86_cons_fix_new is called via the expression parsing code when a
8269 reloc is needed. We use this hook to get the correct .got reloc. */
8270 static int cons_sign = -1;
8273 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8274 expressionS *exp, bfd_reloc_code_real_type r)
8276 r = reloc (len, 0, cons_sign, r);
8279 if (exp->X_op == O_secrel)
8281 exp->X_op = O_symbol;
8282 r = BFD_RELOC_32_SECREL;
8286 fix_new_exp (frag, off, len, exp, 0, r);
8289 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8290 purpose of the `.dc.a' internal pseudo-op. */
8293 x86_address_bytes (void)
8295 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8297 return stdoutput->arch_info->bits_per_address / 8;
8300 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8302 # define lex_got(reloc, adjust, types) NULL
8304 /* Parse operands of the form
8305 <symbol>@GOTOFF+<nnn>
8306 and similar .plt or .got references.
8308 If we find one, set up the correct relocation in RELOC and copy the
8309 input string, minus the `@GOTOFF' into a malloc'd buffer for
8310 parsing by the calling routine. Return this buffer, and if ADJUST
8311 is non-null set it to the length of the string we removed from the
8312 input line. Otherwise return NULL. */
8314 lex_got (enum bfd_reloc_code_real *rel,
8316 i386_operand_type *types)
8318 /* Some of the relocations depend on the size of what field is to
8319 be relocated. But in our callers i386_immediate and i386_displacement
8320 we don't yet know the operand size (this will be set by insn
8321 matching). Hence we record the word32 relocation here,
8322 and adjust the reloc according to the real size in reloc(). */
8323 static const struct {
8326 const enum bfd_reloc_code_real rel[2];
8327 const i386_operand_type types64;
8329 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8330 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8332 OPERAND_TYPE_IMM32_64 },
8334 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8335 BFD_RELOC_X86_64_PLTOFF64 },
8336 OPERAND_TYPE_IMM64 },
8337 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8338 BFD_RELOC_X86_64_PLT32 },
8339 OPERAND_TYPE_IMM32_32S_DISP32 },
8340 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8341 BFD_RELOC_X86_64_GOTPLT64 },
8342 OPERAND_TYPE_IMM64_DISP64 },
8343 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8344 BFD_RELOC_X86_64_GOTOFF64 },
8345 OPERAND_TYPE_IMM64_DISP64 },
8346 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8347 BFD_RELOC_X86_64_GOTPCREL },
8348 OPERAND_TYPE_IMM32_32S_DISP32 },
8349 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8350 BFD_RELOC_X86_64_TLSGD },
8351 OPERAND_TYPE_IMM32_32S_DISP32 },
8352 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8353 _dummy_first_bfd_reloc_code_real },
8354 OPERAND_TYPE_NONE },
8355 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8356 BFD_RELOC_X86_64_TLSLD },
8357 OPERAND_TYPE_IMM32_32S_DISP32 },
8358 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8359 BFD_RELOC_X86_64_GOTTPOFF },
8360 OPERAND_TYPE_IMM32_32S_DISP32 },
8361 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8362 BFD_RELOC_X86_64_TPOFF32 },
8363 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8364 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8365 _dummy_first_bfd_reloc_code_real },
8366 OPERAND_TYPE_NONE },
8367 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8368 BFD_RELOC_X86_64_DTPOFF32 },
8369 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8370 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8371 _dummy_first_bfd_reloc_code_real },
8372 OPERAND_TYPE_NONE },
8373 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8374 _dummy_first_bfd_reloc_code_real },
8375 OPERAND_TYPE_NONE },
8376 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8377 BFD_RELOC_X86_64_GOT32 },
8378 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8379 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8380 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8381 OPERAND_TYPE_IMM32_32S_DISP32 },
8382 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8383 BFD_RELOC_X86_64_TLSDESC_CALL },
8384 OPERAND_TYPE_IMM32_32S_DISP32 },
8389 #if defined (OBJ_MAYBE_ELF)
8394 for (cp = input_line_pointer; *cp != '@'; cp++)
8395 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8398 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8400 int len = gotrel[j].len;
8401 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8403 if (gotrel[j].rel[object_64bit] != 0)
8406 char *tmpbuf, *past_reloc;
8408 *rel = gotrel[j].rel[object_64bit];
8412 if (flag_code != CODE_64BIT)
8414 types->bitfield.imm32 = 1;
8415 types->bitfield.disp32 = 1;
8418 *types = gotrel[j].types64;
8421 if (j != 0 && GOT_symbol == NULL)
8422 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8424 /* The length of the first part of our input line. */
8425 first = cp - input_line_pointer;
8427 /* The second part goes from after the reloc token until
8428 (and including) an end_of_line char or comma. */
8429 past_reloc = cp + 1 + len;
8431 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8433 second = cp + 1 - past_reloc;
8435 /* Allocate and copy string. The trailing NUL shouldn't
8436 be necessary, but be safe. */
8437 tmpbuf = XNEWVEC (char, first + second + 2);
8438 memcpy (tmpbuf, input_line_pointer, first);
8439 if (second != 0 && *past_reloc != ' ')
8440 /* Replace the relocation token with ' ', so that
8441 errors like foo@GOTOFF1 will be detected. */
8442 tmpbuf[first++] = ' ';
8444 /* Increment length by 1 if the relocation token is
8449 memcpy (tmpbuf + first, past_reloc, second);
8450 tmpbuf[first + second] = '\0';
8454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8455 gotrel[j].str, 1 << (5 + object_64bit));
8460 /* Might be a symbol version string. Don't as_bad here. */
8469 /* Parse operands of the form
8470 <symbol>@SECREL32+<nnn>
8472 If we find one, set up the correct relocation in RELOC and copy the
8473 input string, minus the `@SECREL32' into a malloc'd buffer for
8474 parsing by the calling routine. Return this buffer, and if ADJUST
8475 is non-null set it to the length of the string we removed from the
8476 input line. Otherwise return NULL.
8478 This function is copied from the ELF version above adjusted for PE targets. */
8481 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8482 int *adjust ATTRIBUTE_UNUSED,
8483 i386_operand_type *types)
8489 const enum bfd_reloc_code_real rel[2];
8490 const i386_operand_type types64;
8494 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8495 BFD_RELOC_32_SECREL },
8496 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8502 for (cp = input_line_pointer; *cp != '@'; cp++)
8503 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8506 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8508 int len = gotrel[j].len;
8510 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8512 if (gotrel[j].rel[object_64bit] != 0)
8515 char *tmpbuf, *past_reloc;
8517 *rel = gotrel[j].rel[object_64bit];
8523 if (flag_code != CODE_64BIT)
8525 types->bitfield.imm32 = 1;
8526 types->bitfield.disp32 = 1;
8529 *types = gotrel[j].types64;
8532 /* The length of the first part of our input line. */
8533 first = cp - input_line_pointer;
8535 /* The second part goes from after the reloc token until
8536 (and including) an end_of_line char or comma. */
8537 past_reloc = cp + 1 + len;
8539 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8541 second = cp + 1 - past_reloc;
8543 /* Allocate and copy string. The trailing NUL shouldn't
8544 be necessary, but be safe. */
8545 tmpbuf = XNEWVEC (char, first + second + 2);
8546 memcpy (tmpbuf, input_line_pointer, first);
8547 if (second != 0 && *past_reloc != ' ')
8548 /* Replace the relocation token with ' ', so that
8549 errors like foo@SECLREL321 will be detected. */
8550 tmpbuf[first++] = ' ';
8551 memcpy (tmpbuf + first, past_reloc, second);
8552 tmpbuf[first + second] = '\0';
8556 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8557 gotrel[j].str, 1 << (5 + object_64bit));
8562 /* Might be a symbol version string. Don't as_bad here. */
8568 bfd_reloc_code_real_type
8569 x86_cons (expressionS *exp, int size)
8571 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8573 intel_syntax = -intel_syntax;
8576 if (size == 4 || (object_64bit && size == 8))
8578 /* Handle @GOTOFF and the like in an expression. */
8580 char *gotfree_input_line;
8583 save = input_line_pointer;
8584 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8585 if (gotfree_input_line)
8586 input_line_pointer = gotfree_input_line;
8590 if (gotfree_input_line)
8592 /* expression () has merrily parsed up to the end of line,
8593 or a comma - in the wrong buffer. Transfer how far
8594 input_line_pointer has moved to the right buffer. */
8595 input_line_pointer = (save
8596 + (input_line_pointer - gotfree_input_line)
8598 free (gotfree_input_line);
8599 if (exp->X_op == O_constant
8600 || exp->X_op == O_absent
8601 || exp->X_op == O_illegal
8602 || exp->X_op == O_register
8603 || exp->X_op == O_big)
8605 char c = *input_line_pointer;
8606 *input_line_pointer = 0;
8607 as_bad (_("missing or invalid expression `%s'"), save);
8608 *input_line_pointer = c;
8615 intel_syntax = -intel_syntax;
8618 i386_intel_simplify (exp);
8624 signed_cons (int size)
8626 if (flag_code == CODE_64BIT)
8634 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8641 if (exp.X_op == O_symbol)
8642 exp.X_op = O_secrel;
8644 emit_expr (&exp, 4);
8646 while (*input_line_pointer++ == ',');
8648 input_line_pointer--;
8649 demand_empty_rest_of_line ();
8653 /* Handle Vector operations. */
8656 check_VecOperations (char *op_string, char *op_end)
8658 const reg_entry *mask;
8663 && (op_end == NULL || op_string < op_end))
8666 if (*op_string == '{')
8670 /* Check broadcasts. */
8671 if (strncmp (op_string, "1to", 3) == 0)
8676 goto duplicated_vec_op;
8679 if (*op_string == '8')
8681 else if (*op_string == '4')
8683 else if (*op_string == '2')
8685 else if (*op_string == '1'
8686 && *(op_string+1) == '6')
8693 as_bad (_("Unsupported broadcast: `%s'"), saved);
8698 broadcast_op.type = bcst_type;
8699 broadcast_op.operand = this_operand;
8700 broadcast_op.bytes = 0;
8701 i.broadcast = &broadcast_op;
8703 /* Check masking operation. */
8704 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8706 /* k0 can't be used for write mask. */
8707 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8709 as_bad (_("`%s%s' can't be used for write mask"),
8710 register_prefix, mask->reg_name);
8716 mask_op.mask = mask;
8717 mask_op.zeroing = 0;
8718 mask_op.operand = this_operand;
8724 goto duplicated_vec_op;
8726 i.mask->mask = mask;
8728 /* Only "{z}" is allowed here. No need to check
8729 zeroing mask explicitly. */
8730 if (i.mask->operand != this_operand)
8732 as_bad (_("invalid write mask `%s'"), saved);
8739 /* Check zeroing-flag for masking operation. */
8740 else if (*op_string == 'z')
8744 mask_op.mask = NULL;
8745 mask_op.zeroing = 1;
8746 mask_op.operand = this_operand;
8751 if (i.mask->zeroing)
8754 as_bad (_("duplicated `%s'"), saved);
8758 i.mask->zeroing = 1;
8760 /* Only "{%k}" is allowed here. No need to check mask
8761 register explicitly. */
8762 if (i.mask->operand != this_operand)
8764 as_bad (_("invalid zeroing-masking `%s'"),
8773 goto unknown_vec_op;
8775 if (*op_string != '}')
8777 as_bad (_("missing `}' in `%s'"), saved);
8782 /* Strip whitespace since the addition of pseudo prefixes
8783 changed how the scrubber treats '{'. */
8784 if (is_space_char (*op_string))
8790 /* We don't know this one. */
8791 as_bad (_("unknown vector operation: `%s'"), saved);
8795 if (i.mask && i.mask->zeroing && !i.mask->mask)
8797 as_bad (_("zeroing-masking only allowed with write mask"));
8805 i386_immediate (char *imm_start)
8807 char *save_input_line_pointer;
8808 char *gotfree_input_line;
8811 i386_operand_type types;
8813 operand_type_set (&types, ~0);
8815 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8817 as_bad (_("at most %d immediate operands are allowed"),
8818 MAX_IMMEDIATE_OPERANDS);
8822 exp = &im_expressions[i.imm_operands++];
8823 i.op[this_operand].imms = exp;
8825 if (is_space_char (*imm_start))
8828 save_input_line_pointer = input_line_pointer;
8829 input_line_pointer = imm_start;
8831 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8832 if (gotfree_input_line)
8833 input_line_pointer = gotfree_input_line;
8835 exp_seg = expression (exp);
8839 /* Handle vector operations. */
8840 if (*input_line_pointer == '{')
8842 input_line_pointer = check_VecOperations (input_line_pointer,
8844 if (input_line_pointer == NULL)
8848 if (*input_line_pointer)
8849 as_bad (_("junk `%s' after expression"), input_line_pointer);
8851 input_line_pointer = save_input_line_pointer;
8852 if (gotfree_input_line)
8854 free (gotfree_input_line);
8856 if (exp->X_op == O_constant || exp->X_op == O_register)
8857 exp->X_op = O_illegal;
8860 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8864 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8865 i386_operand_type types, const char *imm_start)
8867 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8870 as_bad (_("missing or invalid immediate expression `%s'"),
8874 else if (exp->X_op == O_constant)
8876 /* Size it properly later. */
8877 i.types[this_operand].bitfield.imm64 = 1;
8878 /* If not 64bit, sign extend val. */
8879 if (flag_code != CODE_64BIT
8880 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8882 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8884 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8885 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8886 && exp_seg != absolute_section
8887 && exp_seg != text_section
8888 && exp_seg != data_section
8889 && exp_seg != bss_section
8890 && exp_seg != undefined_section
8891 && !bfd_is_com_section (exp_seg))
8893 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8897 else if (!intel_syntax && exp_seg == reg_section)
8900 as_bad (_("illegal immediate register operand %s"), imm_start);
8905 /* This is an address. The size of the address will be
8906 determined later, depending on destination register,
8907 suffix, or the default for the section. */
8908 i.types[this_operand].bitfield.imm8 = 1;
8909 i.types[this_operand].bitfield.imm16 = 1;
8910 i.types[this_operand].bitfield.imm32 = 1;
8911 i.types[this_operand].bitfield.imm32s = 1;
8912 i.types[this_operand].bitfield.imm64 = 1;
8913 i.types[this_operand] = operand_type_and (i.types[this_operand],
8921 i386_scale (char *scale)
8924 char *save = input_line_pointer;
8926 input_line_pointer = scale;
8927 val = get_absolute_expression ();
8932 i.log2_scale_factor = 0;
8935 i.log2_scale_factor = 1;
8938 i.log2_scale_factor = 2;
8941 i.log2_scale_factor = 3;
8945 char sep = *input_line_pointer;
8947 *input_line_pointer = '\0';
8948 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8950 *input_line_pointer = sep;
8951 input_line_pointer = save;
8955 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8957 as_warn (_("scale factor of %d without an index register"),
8958 1 << i.log2_scale_factor);
8959 i.log2_scale_factor = 0;
8961 scale = input_line_pointer;
8962 input_line_pointer = save;
8967 i386_displacement (char *disp_start, char *disp_end)
8971 char *save_input_line_pointer;
8972 char *gotfree_input_line;
8974 i386_operand_type bigdisp, types = anydisp;
8977 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8979 as_bad (_("at most %d displacement operands are allowed"),
8980 MAX_MEMORY_OPERANDS);
8984 operand_type_set (&bigdisp, 0);
8985 if ((i.types[this_operand].bitfield.jumpabsolute)
8986 || (!current_templates->start->opcode_modifier.jump
8987 && !current_templates->start->opcode_modifier.jumpdword))
8989 bigdisp.bitfield.disp32 = 1;
8990 override = (i.prefix[ADDR_PREFIX] != 0);
8991 if (flag_code == CODE_64BIT)
8995 bigdisp.bitfield.disp32s = 1;
8996 bigdisp.bitfield.disp64 = 1;
8999 else if ((flag_code == CODE_16BIT) ^ override)
9001 bigdisp.bitfield.disp32 = 0;
9002 bigdisp.bitfield.disp16 = 1;
9007 /* For PC-relative branches, the width of the displacement
9008 is dependent upon data size, not address size. */
9009 override = (i.prefix[DATA_PREFIX] != 0);
9010 if (flag_code == CODE_64BIT)
9012 if (override || i.suffix == WORD_MNEM_SUFFIX)
9013 bigdisp.bitfield.disp16 = 1;
9016 bigdisp.bitfield.disp32 = 1;
9017 bigdisp.bitfield.disp32s = 1;
9023 override = (i.suffix == (flag_code != CODE_16BIT
9025 : LONG_MNEM_SUFFIX));
9026 bigdisp.bitfield.disp32 = 1;
9027 if ((flag_code == CODE_16BIT) ^ override)
9029 bigdisp.bitfield.disp32 = 0;
9030 bigdisp.bitfield.disp16 = 1;
9034 i.types[this_operand] = operand_type_or (i.types[this_operand],
9037 exp = &disp_expressions[i.disp_operands];
9038 i.op[this_operand].disps = exp;
9040 save_input_line_pointer = input_line_pointer;
9041 input_line_pointer = disp_start;
9042 END_STRING_AND_SAVE (disp_end);
9044 #ifndef GCC_ASM_O_HACK
9045 #define GCC_ASM_O_HACK 0
9048 END_STRING_AND_SAVE (disp_end + 1);
9049 if (i.types[this_operand].bitfield.baseIndex
9050 && displacement_string_end[-1] == '+')
9052 /* This hack is to avoid a warning when using the "o"
9053 constraint within gcc asm statements.
9056 #define _set_tssldt_desc(n,addr,limit,type) \
9057 __asm__ __volatile__ ( \
9059 "movw %w1,2+%0\n\t" \
9061 "movb %b1,4+%0\n\t" \
9062 "movb %4,5+%0\n\t" \
9063 "movb $0,6+%0\n\t" \
9064 "movb %h1,7+%0\n\t" \
9066 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9068 This works great except that the output assembler ends
9069 up looking a bit weird if it turns out that there is
9070 no offset. You end up producing code that looks like:
9083 So here we provide the missing zero. */
9085 *displacement_string_end = '0';
9088 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9089 if (gotfree_input_line)
9090 input_line_pointer = gotfree_input_line;
9092 exp_seg = expression (exp);
9095 if (*input_line_pointer)
9096 as_bad (_("junk `%s' after expression"), input_line_pointer);
9098 RESTORE_END_STRING (disp_end + 1);
9100 input_line_pointer = save_input_line_pointer;
9101 if (gotfree_input_line)
9103 free (gotfree_input_line);
9105 if (exp->X_op == O_constant || exp->X_op == O_register)
9106 exp->X_op = O_illegal;
9109 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9111 RESTORE_END_STRING (disp_end);
9117 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9118 i386_operand_type types, const char *disp_start)
9120 i386_operand_type bigdisp;
9123 /* We do this to make sure that the section symbol is in
9124 the symbol table. We will ultimately change the relocation
9125 to be relative to the beginning of the section. */
9126 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9127 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9128 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9130 if (exp->X_op != O_symbol)
9133 if (S_IS_LOCAL (exp->X_add_symbol)
9134 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9135 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9136 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9137 exp->X_op = O_subtract;
9138 exp->X_op_symbol = GOT_symbol;
9139 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9140 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9141 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9142 i.reloc[this_operand] = BFD_RELOC_64;
9144 i.reloc[this_operand] = BFD_RELOC_32;
9147 else if (exp->X_op == O_absent
9148 || exp->X_op == O_illegal
9149 || exp->X_op == O_big)
9152 as_bad (_("missing or invalid displacement expression `%s'"),
9157 else if (flag_code == CODE_64BIT
9158 && !i.prefix[ADDR_PREFIX]
9159 && exp->X_op == O_constant)
9161 /* Since displacement is signed extended to 64bit, don't allow
9162 disp32 and turn off disp32s if they are out of range. */
9163 i.types[this_operand].bitfield.disp32 = 0;
9164 if (!fits_in_signed_long (exp->X_add_number))
9166 i.types[this_operand].bitfield.disp32s = 0;
9167 if (i.types[this_operand].bitfield.baseindex)
9169 as_bad (_("0x%lx out range of signed 32bit displacement"),
9170 (long) exp->X_add_number);
9176 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9177 else if (exp->X_op != O_constant
9178 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9179 && exp_seg != absolute_section
9180 && exp_seg != text_section
9181 && exp_seg != data_section
9182 && exp_seg != bss_section
9183 && exp_seg != undefined_section
9184 && !bfd_is_com_section (exp_seg))
9186 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9191 /* Check if this is a displacement only operand. */
9192 bigdisp = i.types[this_operand];
9193 bigdisp.bitfield.disp8 = 0;
9194 bigdisp.bitfield.disp16 = 0;
9195 bigdisp.bitfield.disp32 = 0;
9196 bigdisp.bitfield.disp32s = 0;
9197 bigdisp.bitfield.disp64 = 0;
9198 if (operand_type_all_zero (&bigdisp))
9199 i.types[this_operand] = operand_type_and (i.types[this_operand],
9205 /* Return the active addressing mode, taking address override and
9206 registers forming the address into consideration. Update the
9207 address override prefix if necessary. */
9209 static enum flag_code
9210 i386_addressing_mode (void)
9212 enum flag_code addr_mode;
9214 if (i.prefix[ADDR_PREFIX])
9215 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9218 addr_mode = flag_code;
9220 #if INFER_ADDR_PREFIX
9221 if (i.mem_operands == 0)
9223 /* Infer address prefix from the first memory operand. */
9224 const reg_entry *addr_reg = i.base_reg;
9226 if (addr_reg == NULL)
9227 addr_reg = i.index_reg;
9231 if (addr_reg->reg_num == RegEip
9232 || addr_reg->reg_num == RegEiz
9233 || addr_reg->reg_type.bitfield.dword)
9234 addr_mode = CODE_32BIT;
9235 else if (flag_code != CODE_64BIT
9236 && addr_reg->reg_type.bitfield.word)
9237 addr_mode = CODE_16BIT;
9239 if (addr_mode != flag_code)
9241 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9243 /* Change the size of any displacement too. At most one
9244 of Disp16 or Disp32 is set.
9245 FIXME. There doesn't seem to be any real need for
9246 separate Disp16 and Disp32 flags. The same goes for
9247 Imm16 and Imm32. Removing them would probably clean
9248 up the code quite a lot. */
9249 if (flag_code != CODE_64BIT
9250 && (i.types[this_operand].bitfield.disp16
9251 || i.types[this_operand].bitfield.disp32))
9252 i.types[this_operand]
9253 = operand_type_xor (i.types[this_operand], disp16_32);
9263 /* Make sure the memory operand we've been dealt is valid.
9264 Return 1 on success, 0 on a failure. */
9267 i386_index_check (const char *operand_string)
9269 const char *kind = "base/index";
9270 enum flag_code addr_mode = i386_addressing_mode ();
9272 if (current_templates->start->opcode_modifier.isstring
9273 && !current_templates->start->opcode_modifier.immext
9274 && (current_templates->end[-1].opcode_modifier.isstring
9277 /* Memory operands of string insns are special in that they only allow
9278 a single register (rDI, rSI, or rBX) as their memory address. */
9279 const reg_entry *expected_reg;
9280 static const char *di_si[][2] =
9286 static const char *bx[] = { "ebx", "bx", "rbx" };
9288 kind = "string address";
9290 if (current_templates->start->opcode_modifier.repprefixok)
9292 i386_operand_type type = current_templates->end[-1].operand_types[0];
9294 if (!type.bitfield.baseindex
9295 || ((!i.mem_operands != !intel_syntax)
9296 && current_templates->end[-1].operand_types[1]
9297 .bitfield.baseindex))
9298 type = current_templates->end[-1].operand_types[1];
9299 expected_reg = hash_find (reg_hash,
9300 di_si[addr_mode][type.bitfield.esseg]);
9304 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9306 if (i.base_reg != expected_reg
9308 || operand_type_check (i.types[this_operand], disp))
9310 /* The second memory operand must have the same size as
9314 && !((addr_mode == CODE_64BIT
9315 && i.base_reg->reg_type.bitfield.qword)
9316 || (addr_mode == CODE_32BIT
9317 ? i.base_reg->reg_type.bitfield.dword
9318 : i.base_reg->reg_type.bitfield.word)))
9321 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9323 intel_syntax ? '[' : '(',
9325 expected_reg->reg_name,
9326 intel_syntax ? ']' : ')');
9333 as_bad (_("`%s' is not a valid %s expression"),
9334 operand_string, kind);
9339 if (addr_mode != CODE_16BIT)
9341 /* 32-bit/64-bit checks. */
9343 && (addr_mode == CODE_64BIT
9344 ? !i.base_reg->reg_type.bitfield.qword
9345 : !i.base_reg->reg_type.bitfield.dword)
9347 || (i.base_reg->reg_num
9348 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9350 && !i.index_reg->reg_type.bitfield.xmmword
9351 && !i.index_reg->reg_type.bitfield.ymmword
9352 && !i.index_reg->reg_type.bitfield.zmmword
9353 && ((addr_mode == CODE_64BIT
9354 ? !(i.index_reg->reg_type.bitfield.qword
9355 || i.index_reg->reg_num == RegRiz)
9356 : !(i.index_reg->reg_type.bitfield.dword
9357 || i.index_reg->reg_num == RegEiz))
9358 || !i.index_reg->reg_type.bitfield.baseindex)))
9361 /* bndmk, bndldx, and bndstx have special restrictions. */
9362 if (current_templates->start->base_opcode == 0xf30f1b
9363 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9365 /* They cannot use RIP-relative addressing. */
9366 if (i.base_reg && i.base_reg->reg_num == RegRip)
9368 as_bad (_("`%s' cannot be used here"), operand_string);
9372 /* bndldx and bndstx ignore their scale factor. */
9373 if (current_templates->start->base_opcode != 0xf30f1b
9374 && i.log2_scale_factor)
9375 as_warn (_("register scaling is being ignored here"));
9380 /* 16-bit checks. */
9382 && (!i.base_reg->reg_type.bitfield.word
9383 || !i.base_reg->reg_type.bitfield.baseindex))
9385 && (!i.index_reg->reg_type.bitfield.word
9386 || !i.index_reg->reg_type.bitfield.baseindex
9388 && i.base_reg->reg_num < 6
9389 && i.index_reg->reg_num >= 6
9390 && i.log2_scale_factor == 0))))
9397 /* Handle vector immediates. */
9400 RC_SAE_immediate (const char *imm_start)
9402 unsigned int match_found, j;
9403 const char *pstr = imm_start;
9411 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9413 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9417 rc_op.type = RC_NamesTable[j].type;
9418 rc_op.operand = this_operand;
9419 i.rounding = &rc_op;
9423 as_bad (_("duplicated `%s'"), imm_start);
9426 pstr += RC_NamesTable[j].len;
9436 as_bad (_("Missing '}': '%s'"), imm_start);
9439 /* RC/SAE immediate string should contain nothing more. */;
9442 as_bad (_("Junk after '}': '%s'"), imm_start);
9446 exp = &im_expressions[i.imm_operands++];
9447 i.op[this_operand].imms = exp;
9449 exp->X_op = O_constant;
9450 exp->X_add_number = 0;
9451 exp->X_add_symbol = (symbolS *) 0;
9452 exp->X_op_symbol = (symbolS *) 0;
9454 i.types[this_operand].bitfield.imm8 = 1;
9458 /* Only string instructions can have a second memory operand, so
9459 reduce current_templates to just those if it contains any. */
9461 maybe_adjust_templates (void)
9463 const insn_template *t;
9465 gas_assert (i.mem_operands == 1);
9467 for (t = current_templates->start; t < current_templates->end; ++t)
9468 if (t->opcode_modifier.isstring)
9471 if (t < current_templates->end)
9473 static templates aux_templates;
9474 bfd_boolean recheck;
9476 aux_templates.start = t;
9477 for (; t < current_templates->end; ++t)
9478 if (!t->opcode_modifier.isstring)
9480 aux_templates.end = t;
9482 /* Determine whether to re-check the first memory operand. */
9483 recheck = (aux_templates.start != current_templates->start
9484 || t != current_templates->end);
9486 current_templates = &aux_templates;
9491 if (i.memop1_string != NULL
9492 && i386_index_check (i.memop1_string) == 0)
9501 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9505 i386_att_operand (char *operand_string)
9509 char *op_string = operand_string;
9511 if (is_space_char (*op_string))
9514 /* We check for an absolute prefix (differentiating,
9515 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9516 if (*op_string == ABSOLUTE_PREFIX)
9519 if (is_space_char (*op_string))
9521 i.types[this_operand].bitfield.jumpabsolute = 1;
9524 /* Check if operand is a register. */
9525 if ((r = parse_register (op_string, &end_op)) != NULL)
9527 i386_operand_type temp;
9529 /* Check for a segment override by searching for ':' after a
9530 segment register. */
9532 if (is_space_char (*op_string))
9534 if (*op_string == ':'
9535 && (r->reg_type.bitfield.sreg2
9536 || r->reg_type.bitfield.sreg3))
9541 i.seg[i.mem_operands] = &es;
9544 i.seg[i.mem_operands] = &cs;
9547 i.seg[i.mem_operands] = &ss;
9550 i.seg[i.mem_operands] = &ds;
9553 i.seg[i.mem_operands] = &fs;
9556 i.seg[i.mem_operands] = &gs;
9560 /* Skip the ':' and whitespace. */
9562 if (is_space_char (*op_string))
9565 if (!is_digit_char (*op_string)
9566 && !is_identifier_char (*op_string)
9567 && *op_string != '('
9568 && *op_string != ABSOLUTE_PREFIX)
9570 as_bad (_("bad memory operand `%s'"), op_string);
9573 /* Handle case of %es:*foo. */
9574 if (*op_string == ABSOLUTE_PREFIX)
9577 if (is_space_char (*op_string))
9579 i.types[this_operand].bitfield.jumpabsolute = 1;
9581 goto do_memory_reference;
9584 /* Handle vector operations. */
9585 if (*op_string == '{')
9587 op_string = check_VecOperations (op_string, NULL);
9588 if (op_string == NULL)
9594 as_bad (_("junk `%s' after register"), op_string);
9598 temp.bitfield.baseindex = 0;
9599 i.types[this_operand] = operand_type_or (i.types[this_operand],
9601 i.types[this_operand].bitfield.unspecified = 0;
9602 i.op[this_operand].regs = r;
9605 else if (*op_string == REGISTER_PREFIX)
9607 as_bad (_("bad register name `%s'"), op_string);
9610 else if (*op_string == IMMEDIATE_PREFIX)
9613 if (i.types[this_operand].bitfield.jumpabsolute)
9615 as_bad (_("immediate operand illegal with absolute jump"));
9618 if (!i386_immediate (op_string))
9621 else if (RC_SAE_immediate (operand_string))
9623 /* If it is a RC or SAE immediate, do nothing. */
9626 else if (is_digit_char (*op_string)
9627 || is_identifier_char (*op_string)
9628 || *op_string == '"'
9629 || *op_string == '(')
9631 /* This is a memory reference of some sort. */
9634 /* Start and end of displacement string expression (if found). */
9635 char *displacement_string_start;
9636 char *displacement_string_end;
9639 do_memory_reference:
9640 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9642 if ((i.mem_operands == 1
9643 && !current_templates->start->opcode_modifier.isstring)
9644 || i.mem_operands == 2)
9646 as_bad (_("too many memory references for `%s'"),
9647 current_templates->start->name);
9651 /* Check for base index form. We detect the base index form by
9652 looking for an ')' at the end of the operand, searching
9653 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9655 base_string = op_string + strlen (op_string);
9657 /* Handle vector operations. */
9658 vop_start = strchr (op_string, '{');
9659 if (vop_start && vop_start < base_string)
9661 if (check_VecOperations (vop_start, base_string) == NULL)
9663 base_string = vop_start;
9667 if (is_space_char (*base_string))
9670 /* If we only have a displacement, set-up for it to be parsed later. */
9671 displacement_string_start = op_string;
9672 displacement_string_end = base_string + 1;
9674 if (*base_string == ')')
9677 unsigned int parens_balanced = 1;
9678 /* We've already checked that the number of left & right ()'s are
9679 equal, so this loop will not be infinite. */
9683 if (*base_string == ')')
9685 if (*base_string == '(')
9688 while (parens_balanced);
9690 temp_string = base_string;
9692 /* Skip past '(' and whitespace. */
9694 if (is_space_char (*base_string))
9697 if (*base_string == ','
9698 || ((i.base_reg = parse_register (base_string, &end_op))
9701 displacement_string_end = temp_string;
9703 i.types[this_operand].bitfield.baseindex = 1;
9707 base_string = end_op;
9708 if (is_space_char (*base_string))
9712 /* There may be an index reg or scale factor here. */
9713 if (*base_string == ',')
9716 if (is_space_char (*base_string))
9719 if ((i.index_reg = parse_register (base_string, &end_op))
9722 base_string = end_op;
9723 if (is_space_char (*base_string))
9725 if (*base_string == ',')
9728 if (is_space_char (*base_string))
9731 else if (*base_string != ')')
9733 as_bad (_("expecting `,' or `)' "
9734 "after index register in `%s'"),
9739 else if (*base_string == REGISTER_PREFIX)
9741 end_op = strchr (base_string, ',');
9744 as_bad (_("bad register name `%s'"), base_string);
9748 /* Check for scale factor. */
9749 if (*base_string != ')')
9751 char *end_scale = i386_scale (base_string);
9756 base_string = end_scale;
9757 if (is_space_char (*base_string))
9759 if (*base_string != ')')
9761 as_bad (_("expecting `)' "
9762 "after scale factor in `%s'"),
9767 else if (!i.index_reg)
9769 as_bad (_("expecting index register or scale factor "
9770 "after `,'; got '%c'"),
9775 else if (*base_string != ')')
9777 as_bad (_("expecting `,' or `)' "
9778 "after base register in `%s'"),
9783 else if (*base_string == REGISTER_PREFIX)
9785 end_op = strchr (base_string, ',');
9788 as_bad (_("bad register name `%s'"), base_string);
9793 /* If there's an expression beginning the operand, parse it,
9794 assuming displacement_string_start and
9795 displacement_string_end are meaningful. */
9796 if (displacement_string_start != displacement_string_end)
9798 if (!i386_displacement (displacement_string_start,
9799 displacement_string_end))
9803 /* Special case for (%dx) while doing input/output op. */
9805 && i.base_reg->reg_type.bitfield.inoutportreg
9807 && i.log2_scale_factor == 0
9808 && i.seg[i.mem_operands] == 0
9809 && !operand_type_check (i.types[this_operand], disp))
9811 i.types[this_operand] = i.base_reg->reg_type;
9815 if (i386_index_check (operand_string) == 0)
9817 i.types[this_operand].bitfield.mem = 1;
9818 if (i.mem_operands == 0)
9819 i.memop1_string = xstrdup (operand_string);
9824 /* It's not a memory operand; argh! */
9825 as_bad (_("invalid char %s beginning operand %d `%s'"),
9826 output_invalid (*op_string),
9831 return 1; /* Normal return. */
9834 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9835 that an rs_machine_dependent frag may reach. */
9838 i386_frag_max_var (fragS *frag)
9840 /* The only relaxable frags are for jumps.
9841 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9842 gas_assert (frag->fr_type == rs_machine_dependent);
9843 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9846 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9848 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9850 /* STT_GNU_IFUNC symbol must go through PLT. */
9851 if ((symbol_get_bfdsym (fr_symbol)->flags
9852 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9855 if (!S_IS_EXTERNAL (fr_symbol))
9856 /* Symbol may be weak or local. */
9857 return !S_IS_WEAK (fr_symbol);
9859 /* Global symbols with non-default visibility can't be preempted. */
9860 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9863 if (fr_var != NO_RELOC)
9864 switch ((enum bfd_reloc_code_real) fr_var)
9866 case BFD_RELOC_386_PLT32:
9867 case BFD_RELOC_X86_64_PLT32:
9868 /* Symbol with PLT relocation may be preempted. */
9874 /* Global symbols with default visibility in a shared library may be
9875 preempted by another definition. */
9880 /* md_estimate_size_before_relax()
9882 Called just before relax() for rs_machine_dependent frags. The x86
9883 assembler uses these frags to handle variable size jump
9886 Any symbol that is now undefined will not become defined.
9887 Return the correct fr_subtype in the frag.
9888 Return the initial "guess for variable size of frag" to caller.
9889 The guess is actually the growth beyond the fixed part. Whatever
9890 we do to grow the fixed or variable part contributes to our
9894 md_estimate_size_before_relax (fragS *fragP, segT segment)
9896 /* We've already got fragP->fr_subtype right; all we have to do is
9897 check for un-relaxable symbols. On an ELF system, we can't relax
9898 an externally visible symbol, because it may be overridden by a
9900 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9903 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9906 #if defined (OBJ_COFF) && defined (TE_PE)
9907 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9908 && S_IS_WEAK (fragP->fr_symbol))
9912 /* Symbol is undefined in this segment, or we need to keep a
9913 reloc so that weak symbols can be overridden. */
9914 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9915 enum bfd_reloc_code_real reloc_type;
9916 unsigned char *opcode;
9919 if (fragP->fr_var != NO_RELOC)
9920 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9922 reloc_type = BFD_RELOC_16_PCREL;
9923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9924 else if (need_plt32_p (fragP->fr_symbol))
9925 reloc_type = BFD_RELOC_X86_64_PLT32;
9928 reloc_type = BFD_RELOC_32_PCREL;
9930 old_fr_fix = fragP->fr_fix;
9931 opcode = (unsigned char *) fragP->fr_opcode;
9933 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9936 /* Make jmp (0xeb) a (d)word displacement jump. */
9938 fragP->fr_fix += size;
9939 fix_new (fragP, old_fr_fix, size,
9941 fragP->fr_offset, 1,
9947 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9949 /* Negate the condition, and branch past an
9950 unconditional jump. */
9953 /* Insert an unconditional jump. */
9955 /* We added two extra opcode bytes, and have a two byte
9957 fragP->fr_fix += 2 + 2;
9958 fix_new (fragP, old_fr_fix + 2, 2,
9960 fragP->fr_offset, 1,
9967 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9972 fixP = fix_new (fragP, old_fr_fix, 1,
9974 fragP->fr_offset, 1,
9976 fixP->fx_signed = 1;
9980 /* This changes the byte-displacement jump 0x7N
9981 to the (d)word-displacement jump 0x0f,0x8N. */
9982 opcode[1] = opcode[0] + 0x10;
9983 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9984 /* We've added an opcode byte. */
9985 fragP->fr_fix += 1 + size;
9986 fix_new (fragP, old_fr_fix + 1, size,
9988 fragP->fr_offset, 1,
9993 BAD_CASE (fragP->fr_subtype);
9997 return fragP->fr_fix - old_fr_fix;
10000 /* Guess size depending on current relax state. Initially the relax
10001 state will correspond to a short jump and we return 1, because
10002 the variable part of the frag (the branch offset) is one byte
10003 long. However, we can relax a section more than once and in that
10004 case we must either set fr_subtype back to the unrelaxed state,
10005 or return the value for the appropriate branch. */
10006 return md_relax_table[fragP->fr_subtype].rlx_length;
10009 /* Called after relax() is finished.
10011 In: Address of frag.
10012 fr_type == rs_machine_dependent.
10013 fr_subtype is what the address relaxed to.
10015 Out: Any fixSs and constants are set up.
10016 Caller will turn frag into a ".space 0". */
10019 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10022 unsigned char *opcode;
10023 unsigned char *where_to_put_displacement = NULL;
10024 offsetT target_address;
10025 offsetT opcode_address;
10026 unsigned int extension = 0;
10027 offsetT displacement_from_opcode_start;
10029 opcode = (unsigned char *) fragP->fr_opcode;
10031 /* Address we want to reach in file space. */
10032 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10034 /* Address opcode resides at in file space. */
10035 opcode_address = fragP->fr_address + fragP->fr_fix;
10037 /* Displacement from opcode start to fill into instruction. */
10038 displacement_from_opcode_start = target_address - opcode_address;
10040 if ((fragP->fr_subtype & BIG) == 0)
10042 /* Don't have to change opcode. */
10043 extension = 1; /* 1 opcode + 1 displacement */
10044 where_to_put_displacement = &opcode[1];
10048 if (no_cond_jump_promotion
10049 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10050 as_warn_where (fragP->fr_file, fragP->fr_line,
10051 _("long jump required"));
10053 switch (fragP->fr_subtype)
10055 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10056 extension = 4; /* 1 opcode + 4 displacement */
10058 where_to_put_displacement = &opcode[1];
10061 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10062 extension = 2; /* 1 opcode + 2 displacement */
10064 where_to_put_displacement = &opcode[1];
10067 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10068 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10069 extension = 5; /* 2 opcode + 4 displacement */
10070 opcode[1] = opcode[0] + 0x10;
10071 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10072 where_to_put_displacement = &opcode[2];
10075 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10076 extension = 3; /* 2 opcode + 2 displacement */
10077 opcode[1] = opcode[0] + 0x10;
10078 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10079 where_to_put_displacement = &opcode[2];
10082 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10087 where_to_put_displacement = &opcode[3];
10091 BAD_CASE (fragP->fr_subtype);
10096 /* If size if less then four we are sure that the operand fits,
10097 but if it's 4, then it could be that the displacement is larger
10099 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10101 && ((addressT) (displacement_from_opcode_start - extension
10102 + ((addressT) 1 << 31))
10103 > (((addressT) 2 << 31) - 1)))
10105 as_bad_where (fragP->fr_file, fragP->fr_line,
10106 _("jump target out of range"));
10107 /* Make us emit 0. */
10108 displacement_from_opcode_start = extension;
10110 /* Now put displacement after opcode. */
10111 md_number_to_chars ((char *) where_to_put_displacement,
10112 (valueT) (displacement_from_opcode_start - extension),
10113 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10114 fragP->fr_fix += extension;
10117 /* Apply a fixup (fixP) to segment data, once it has been determined
10118 by our caller that we have all the info we need to fix it up.
10120 Parameter valP is the pointer to the value of the bits.
10122 On the 386, immediates, displacements, and data pointers are all in
10123 the same (little-endian) format, so we don't need to care about which
10124 we are handling. */
10127 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10129 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10130 valueT value = *valP;
10132 #if !defined (TE_Mach)
10133 if (fixP->fx_pcrel)
10135 switch (fixP->fx_r_type)
10141 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10144 case BFD_RELOC_X86_64_32S:
10145 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10148 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10151 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10156 if (fixP->fx_addsy != NULL
10157 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10158 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10159 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10160 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10161 && !use_rela_relocations)
10163 /* This is a hack. There should be a better way to handle this.
10164 This covers for the fact that bfd_install_relocation will
10165 subtract the current location (for partial_inplace, PC relative
10166 relocations); see more below. */
10170 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10173 value += fixP->fx_where + fixP->fx_frag->fr_address;
10175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10178 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10180 if ((sym_seg == seg
10181 || (symbol_section_p (fixP->fx_addsy)
10182 && sym_seg != absolute_section))
10183 && !generic_force_reloc (fixP))
10185 /* Yes, we add the values in twice. This is because
10186 bfd_install_relocation subtracts them out again. I think
10187 bfd_install_relocation is broken, but I don't dare change
10189 value += fixP->fx_where + fixP->fx_frag->fr_address;
10193 #if defined (OBJ_COFF) && defined (TE_PE)
10194 /* For some reason, the PE format does not store a
10195 section address offset for a PC relative symbol. */
10196 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10197 || S_IS_WEAK (fixP->fx_addsy))
10198 value += md_pcrel_from (fixP);
10201 #if defined (OBJ_COFF) && defined (TE_PE)
10202 if (fixP->fx_addsy != NULL
10203 && S_IS_WEAK (fixP->fx_addsy)
10204 /* PR 16858: Do not modify weak function references. */
10205 && ! fixP->fx_pcrel)
10207 #if !defined (TE_PEP)
10208 /* For x86 PE weak function symbols are neither PC-relative
10209 nor do they set S_IS_FUNCTION. So the only reliable way
10210 to detect them is to check the flags of their containing
10212 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10213 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10217 value -= S_GET_VALUE (fixP->fx_addsy);
10221 /* Fix a few things - the dynamic linker expects certain values here,
10222 and we must not disappoint it. */
10223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10224 if (IS_ELF && fixP->fx_addsy)
10225 switch (fixP->fx_r_type)
10227 case BFD_RELOC_386_PLT32:
10228 case BFD_RELOC_X86_64_PLT32:
10229 /* Make the jump instruction point to the address of the operand. At
10230 runtime we merely add the offset to the actual PLT entry. */
10234 case BFD_RELOC_386_TLS_GD:
10235 case BFD_RELOC_386_TLS_LDM:
10236 case BFD_RELOC_386_TLS_IE_32:
10237 case BFD_RELOC_386_TLS_IE:
10238 case BFD_RELOC_386_TLS_GOTIE:
10239 case BFD_RELOC_386_TLS_GOTDESC:
10240 case BFD_RELOC_X86_64_TLSGD:
10241 case BFD_RELOC_X86_64_TLSLD:
10242 case BFD_RELOC_X86_64_GOTTPOFF:
10243 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10244 value = 0; /* Fully resolved at runtime. No addend. */
10246 case BFD_RELOC_386_TLS_LE:
10247 case BFD_RELOC_386_TLS_LDO_32:
10248 case BFD_RELOC_386_TLS_LE_32:
10249 case BFD_RELOC_X86_64_DTPOFF32:
10250 case BFD_RELOC_X86_64_DTPOFF64:
10251 case BFD_RELOC_X86_64_TPOFF32:
10252 case BFD_RELOC_X86_64_TPOFF64:
10253 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10256 case BFD_RELOC_386_TLS_DESC_CALL:
10257 case BFD_RELOC_X86_64_TLSDESC_CALL:
10258 value = 0; /* Fully resolved at runtime. No addend. */
10259 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10263 case BFD_RELOC_VTABLE_INHERIT:
10264 case BFD_RELOC_VTABLE_ENTRY:
10271 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10273 #endif /* !defined (TE_Mach) */
10275 /* Are we finished with this relocation now? */
10276 if (fixP->fx_addsy == NULL)
10278 #if defined (OBJ_COFF) && defined (TE_PE)
10279 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10282 /* Remember value for tc_gen_reloc. */
10283 fixP->fx_addnumber = value;
10284 /* Clear out the frag for now. */
10288 else if (use_rela_relocations)
10290 fixP->fx_no_overflow = 1;
10291 /* Remember value for tc_gen_reloc. */
10292 fixP->fx_addnumber = value;
10296 md_number_to_chars (p, value, fixP->fx_size);
10300 md_atof (int type, char *litP, int *sizeP)
10302 /* This outputs the LITTLENUMs in REVERSE order;
10303 in accord with the bigendian 386. */
10304 return ieee_md_atof (type, litP, sizeP, FALSE);
10307 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10310 output_invalid (int c)
10313 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10316 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10317 "(0x%x)", (unsigned char) c);
10318 return output_invalid_buf;
10321 /* REG_STRING starts *before* REGISTER_PREFIX. */
10323 static const reg_entry *
10324 parse_real_register (char *reg_string, char **end_op)
10326 char *s = reg_string;
10328 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10329 const reg_entry *r;
10331 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10332 if (*s == REGISTER_PREFIX)
10335 if (is_space_char (*s))
10338 p = reg_name_given;
10339 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10341 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10342 return (const reg_entry *) NULL;
10346 /* For naked regs, make sure that we are not dealing with an identifier.
10347 This prevents confusing an identifier like `eax_var' with register
10349 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10350 return (const reg_entry *) NULL;
10354 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10356 /* Handle floating point regs, allowing spaces in the (i) part. */
10357 if (r == i386_regtab /* %st is first entry of table */)
10359 if (!cpu_arch_flags.bitfield.cpu8087
10360 && !cpu_arch_flags.bitfield.cpu287
10361 && !cpu_arch_flags.bitfield.cpu387)
10362 return (const reg_entry *) NULL;
10364 if (is_space_char (*s))
10369 if (is_space_char (*s))
10371 if (*s >= '0' && *s <= '7')
10373 int fpr = *s - '0';
10375 if (is_space_char (*s))
10380 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10385 /* We have "%st(" then garbage. */
10386 return (const reg_entry *) NULL;
10390 if (r == NULL || allow_pseudo_reg)
10393 if (operand_type_all_zero (&r->reg_type))
10394 return (const reg_entry *) NULL;
10396 if ((r->reg_type.bitfield.dword
10397 || r->reg_type.bitfield.sreg3
10398 || r->reg_type.bitfield.control
10399 || r->reg_type.bitfield.debug
10400 || r->reg_type.bitfield.test)
10401 && !cpu_arch_flags.bitfield.cpui386)
10402 return (const reg_entry *) NULL;
10404 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10405 return (const reg_entry *) NULL;
10407 if (!cpu_arch_flags.bitfield.cpuavx512f)
10409 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10410 return (const reg_entry *) NULL;
10412 if (!cpu_arch_flags.bitfield.cpuavx)
10414 if (r->reg_type.bitfield.ymmword)
10415 return (const reg_entry *) NULL;
10417 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10418 return (const reg_entry *) NULL;
10422 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10423 return (const reg_entry *) NULL;
10425 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10426 if (!allow_index_reg
10427 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10428 return (const reg_entry *) NULL;
10430 /* Upper 16 vector registers are only available with VREX in 64bit
10431 mode, and require EVEX encoding. */
10432 if (r->reg_flags & RegVRex)
10434 if (!cpu_arch_flags.bitfield.cpuavx512f
10435 || flag_code != CODE_64BIT)
10436 return (const reg_entry *) NULL;
10438 i.vec_encoding = vex_encoding_evex;
10441 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10442 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10443 && flag_code != CODE_64BIT)
10444 return (const reg_entry *) NULL;
10446 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10447 return (const reg_entry *) NULL;
10452 /* REG_STRING starts *before* REGISTER_PREFIX. */
10454 static const reg_entry *
10455 parse_register (char *reg_string, char **end_op)
10457 const reg_entry *r;
10459 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10460 r = parse_real_register (reg_string, end_op);
10465 char *save = input_line_pointer;
10469 input_line_pointer = reg_string;
10470 c = get_symbol_name (®_string);
10471 symbolP = symbol_find (reg_string);
10472 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10474 const expressionS *e = symbol_get_value_expression (symbolP);
10476 know (e->X_op == O_register);
10477 know (e->X_add_number >= 0
10478 && (valueT) e->X_add_number < i386_regtab_size);
10479 r = i386_regtab + e->X_add_number;
10480 if ((r->reg_flags & RegVRex))
10481 i.vec_encoding = vex_encoding_evex;
10482 *end_op = input_line_pointer;
10484 *input_line_pointer = c;
10485 input_line_pointer = save;
10491 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10493 const reg_entry *r;
10494 char *end = input_line_pointer;
10497 r = parse_register (name, &input_line_pointer);
10498 if (r && end <= input_line_pointer)
10500 *nextcharP = *input_line_pointer;
10501 *input_line_pointer = 0;
10502 e->X_op = O_register;
10503 e->X_add_number = r - i386_regtab;
10506 input_line_pointer = end;
10508 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10512 md_operand (expressionS *e)
10515 const reg_entry *r;
10517 switch (*input_line_pointer)
10519 case REGISTER_PREFIX:
10520 r = parse_real_register (input_line_pointer, &end);
10523 e->X_op = O_register;
10524 e->X_add_number = r - i386_regtab;
10525 input_line_pointer = end;
10530 gas_assert (intel_syntax);
10531 end = input_line_pointer++;
10533 if (*input_line_pointer == ']')
10535 ++input_line_pointer;
10536 e->X_op_symbol = make_expr_symbol (e);
10537 e->X_add_symbol = NULL;
10538 e->X_add_number = 0;
10543 e->X_op = O_absent;
10544 input_line_pointer = end;
10551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10552 const char *md_shortopts = "kVQ:sqnO::";
10554 const char *md_shortopts = "qnO::";
10557 #define OPTION_32 (OPTION_MD_BASE + 0)
10558 #define OPTION_64 (OPTION_MD_BASE + 1)
10559 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10560 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10561 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10562 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10563 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10564 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10565 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10566 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10567 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10568 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10569 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10570 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10571 #define OPTION_X32 (OPTION_MD_BASE + 14)
10572 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10573 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10574 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10575 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10576 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10577 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10578 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10579 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10580 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10581 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10583 struct option md_longopts[] =
10585 {"32", no_argument, NULL, OPTION_32},
10586 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10587 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10588 {"64", no_argument, NULL, OPTION_64},
10590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10591 {"x32", no_argument, NULL, OPTION_X32},
10592 {"mshared", no_argument, NULL, OPTION_MSHARED},
10594 {"divide", no_argument, NULL, OPTION_DIVIDE},
10595 {"march", required_argument, NULL, OPTION_MARCH},
10596 {"mtune", required_argument, NULL, OPTION_MTUNE},
10597 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10598 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10599 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10600 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10601 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10602 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10603 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10604 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10605 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10606 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10607 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10608 # if defined (TE_PE) || defined (TE_PEP)
10609 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10611 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10612 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10613 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10614 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10615 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10616 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10617 {NULL, no_argument, NULL, 0}
10619 size_t md_longopts_size = sizeof (md_longopts);
10622 md_parse_option (int c, const char *arg)
10625 char *arch, *next, *saved;
10630 optimize_align_code = 0;
10634 quiet_warnings = 1;
10637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10638 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10639 should be emitted or not. FIXME: Not implemented. */
10643 /* -V: SVR4 argument to print version ID. */
10645 print_version_id ();
10648 /* -k: Ignore for FreeBSD compatibility. */
10653 /* -s: On i386 Solaris, this tells the native assembler to use
10654 .stab instead of .stab.excl. We always use .stab anyhow. */
10657 case OPTION_MSHARED:
10661 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10662 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10665 const char **list, **l;
10667 list = bfd_target_list ();
10668 for (l = list; *l != NULL; l++)
10669 if (CONST_STRNEQ (*l, "elf64-x86-64")
10670 || strcmp (*l, "coff-x86-64") == 0
10671 || strcmp (*l, "pe-x86-64") == 0
10672 || strcmp (*l, "pei-x86-64") == 0
10673 || strcmp (*l, "mach-o-x86-64") == 0)
10675 default_arch = "x86_64";
10679 as_fatal (_("no compiled in support for x86_64"));
10685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10689 const char **list, **l;
10691 list = bfd_target_list ();
10692 for (l = list; *l != NULL; l++)
10693 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10695 default_arch = "x86_64:32";
10699 as_fatal (_("no compiled in support for 32bit x86_64"));
10703 as_fatal (_("32bit x86_64 is only supported for ELF"));
10708 default_arch = "i386";
10711 case OPTION_DIVIDE:
10712 #ifdef SVR4_COMMENT_CHARS
10717 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10719 for (s = i386_comment_chars; *s != '\0'; s++)
10723 i386_comment_chars = n;
10729 saved = xstrdup (arg);
10731 /* Allow -march=+nosse. */
10737 as_fatal (_("invalid -march= option: `%s'"), arg);
10738 next = strchr (arch, '+');
10741 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10743 if (strcmp (arch, cpu_arch [j].name) == 0)
10746 if (! cpu_arch[j].flags.bitfield.cpui386)
10749 cpu_arch_name = cpu_arch[j].name;
10750 cpu_sub_arch_name = NULL;
10751 cpu_arch_flags = cpu_arch[j].flags;
10752 cpu_arch_isa = cpu_arch[j].type;
10753 cpu_arch_isa_flags = cpu_arch[j].flags;
10754 if (!cpu_arch_tune_set)
10756 cpu_arch_tune = cpu_arch_isa;
10757 cpu_arch_tune_flags = cpu_arch_isa_flags;
10761 else if (*cpu_arch [j].name == '.'
10762 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10764 /* ISA extension. */
10765 i386_cpu_flags flags;
10767 flags = cpu_flags_or (cpu_arch_flags,
10768 cpu_arch[j].flags);
10770 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10772 if (cpu_sub_arch_name)
10774 char *name = cpu_sub_arch_name;
10775 cpu_sub_arch_name = concat (name,
10777 (const char *) NULL);
10781 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10782 cpu_arch_flags = flags;
10783 cpu_arch_isa_flags = flags;
10787 = cpu_flags_or (cpu_arch_isa_flags,
10788 cpu_arch[j].flags);
10793 if (j >= ARRAY_SIZE (cpu_arch))
10795 /* Disable an ISA extension. */
10796 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10797 if (strcmp (arch, cpu_noarch [j].name) == 0)
10799 i386_cpu_flags flags;
10801 flags = cpu_flags_and_not (cpu_arch_flags,
10802 cpu_noarch[j].flags);
10803 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10805 if (cpu_sub_arch_name)
10807 char *name = cpu_sub_arch_name;
10808 cpu_sub_arch_name = concat (arch,
10809 (const char *) NULL);
10813 cpu_sub_arch_name = xstrdup (arch);
10814 cpu_arch_flags = flags;
10815 cpu_arch_isa_flags = flags;
10820 if (j >= ARRAY_SIZE (cpu_noarch))
10821 j = ARRAY_SIZE (cpu_arch);
10824 if (j >= ARRAY_SIZE (cpu_arch))
10825 as_fatal (_("invalid -march= option: `%s'"), arg);
10829 while (next != NULL);
10835 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10836 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10838 if (strcmp (arg, cpu_arch [j].name) == 0)
10840 cpu_arch_tune_set = 1;
10841 cpu_arch_tune = cpu_arch [j].type;
10842 cpu_arch_tune_flags = cpu_arch[j].flags;
10846 if (j >= ARRAY_SIZE (cpu_arch))
10847 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10850 case OPTION_MMNEMONIC:
10851 if (strcasecmp (arg, "att") == 0)
10852 intel_mnemonic = 0;
10853 else if (strcasecmp (arg, "intel") == 0)
10854 intel_mnemonic = 1;
10856 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10859 case OPTION_MSYNTAX:
10860 if (strcasecmp (arg, "att") == 0)
10862 else if (strcasecmp (arg, "intel") == 0)
10865 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10868 case OPTION_MINDEX_REG:
10869 allow_index_reg = 1;
10872 case OPTION_MNAKED_REG:
10873 allow_naked_reg = 1;
10876 case OPTION_MSSE2AVX:
10880 case OPTION_MSSE_CHECK:
10881 if (strcasecmp (arg, "error") == 0)
10882 sse_check = check_error;
10883 else if (strcasecmp (arg, "warning") == 0)
10884 sse_check = check_warning;
10885 else if (strcasecmp (arg, "none") == 0)
10886 sse_check = check_none;
10888 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10891 case OPTION_MOPERAND_CHECK:
10892 if (strcasecmp (arg, "error") == 0)
10893 operand_check = check_error;
10894 else if (strcasecmp (arg, "warning") == 0)
10895 operand_check = check_warning;
10896 else if (strcasecmp (arg, "none") == 0)
10897 operand_check = check_none;
10899 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10902 case OPTION_MAVXSCALAR:
10903 if (strcasecmp (arg, "128") == 0)
10904 avxscalar = vex128;
10905 else if (strcasecmp (arg, "256") == 0)
10906 avxscalar = vex256;
10908 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10911 case OPTION_MADD_BND_PREFIX:
10912 add_bnd_prefix = 1;
10915 case OPTION_MEVEXLIG:
10916 if (strcmp (arg, "128") == 0)
10917 evexlig = evexl128;
10918 else if (strcmp (arg, "256") == 0)
10919 evexlig = evexl256;
10920 else if (strcmp (arg, "512") == 0)
10921 evexlig = evexl512;
10923 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10926 case OPTION_MEVEXRCIG:
10927 if (strcmp (arg, "rne") == 0)
10929 else if (strcmp (arg, "rd") == 0)
10931 else if (strcmp (arg, "ru") == 0)
10933 else if (strcmp (arg, "rz") == 0)
10936 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10939 case OPTION_MEVEXWIG:
10940 if (strcmp (arg, "0") == 0)
10942 else if (strcmp (arg, "1") == 0)
10945 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10948 # if defined (TE_PE) || defined (TE_PEP)
10949 case OPTION_MBIG_OBJ:
10954 case OPTION_MOMIT_LOCK_PREFIX:
10955 if (strcasecmp (arg, "yes") == 0)
10956 omit_lock_prefix = 1;
10957 else if (strcasecmp (arg, "no") == 0)
10958 omit_lock_prefix = 0;
10960 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10963 case OPTION_MFENCE_AS_LOCK_ADD:
10964 if (strcasecmp (arg, "yes") == 0)
10966 else if (strcasecmp (arg, "no") == 0)
10969 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10972 case OPTION_MRELAX_RELOCATIONS:
10973 if (strcasecmp (arg, "yes") == 0)
10974 generate_relax_relocations = 1;
10975 else if (strcasecmp (arg, "no") == 0)
10976 generate_relax_relocations = 0;
10978 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10981 case OPTION_MAMD64:
10985 case OPTION_MINTEL64:
10993 /* Turn off -Os. */
10994 optimize_for_space = 0;
10996 else if (*arg == 's')
10998 optimize_for_space = 1;
10999 /* Turn on all encoding optimizations. */
11004 optimize = atoi (arg);
11005 /* Turn off -Os. */
11006 optimize_for_space = 0;
11016 #define MESSAGE_TEMPLATE \
11020 output_message (FILE *stream, char *p, char *message, char *start,
11021 int *left_p, const char *name, int len)
11023 int size = sizeof (MESSAGE_TEMPLATE);
11024 int left = *left_p;
11026 /* Reserve 2 spaces for ", " or ",\0" */
11029 /* Check if there is any room. */
11037 p = mempcpy (p, name, len);
11041 /* Output the current message now and start a new one. */
11044 fprintf (stream, "%s\n", message);
11046 left = size - (start - message) - len - 2;
11048 gas_assert (left >= 0);
11050 p = mempcpy (p, name, len);
11058 show_arch (FILE *stream, int ext, int check)
11060 static char message[] = MESSAGE_TEMPLATE;
11061 char *start = message + 27;
11063 int size = sizeof (MESSAGE_TEMPLATE);
11070 left = size - (start - message);
11071 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11073 /* Should it be skipped? */
11074 if (cpu_arch [j].skip)
11077 name = cpu_arch [j].name;
11078 len = cpu_arch [j].len;
11081 /* It is an extension. Skip if we aren't asked to show it. */
11092 /* It is an processor. Skip if we show only extension. */
11095 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11097 /* It is an impossible processor - skip. */
11101 p = output_message (stream, p, message, start, &left, name, len);
11104 /* Display disabled extensions. */
11106 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11108 name = cpu_noarch [j].name;
11109 len = cpu_noarch [j].len;
11110 p = output_message (stream, p, message, start, &left, name,
11115 fprintf (stream, "%s\n", message);
11119 md_show_usage (FILE *stream)
11121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11122 fprintf (stream, _("\
11124 -V print assembler version number\n\
11127 fprintf (stream, _("\
11128 -n Do not optimize code alignment\n\
11129 -q quieten some warnings\n"));
11130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11131 fprintf (stream, _("\
11134 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11135 || defined (TE_PE) || defined (TE_PEP))
11136 fprintf (stream, _("\
11137 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11139 #ifdef SVR4_COMMENT_CHARS
11140 fprintf (stream, _("\
11141 --divide do not treat `/' as a comment character\n"));
11143 fprintf (stream, _("\
11144 --divide ignored\n"));
11146 fprintf (stream, _("\
11147 -march=CPU[,+EXTENSION...]\n\
11148 generate code for CPU and EXTENSION, CPU is one of:\n"));
11149 show_arch (stream, 0, 1);
11150 fprintf (stream, _("\
11151 EXTENSION is combination of:\n"));
11152 show_arch (stream, 1, 0);
11153 fprintf (stream, _("\
11154 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11155 show_arch (stream, 0, 0);
11156 fprintf (stream, _("\
11157 -msse2avx encode SSE instructions with VEX prefix\n"));
11158 fprintf (stream, _("\
11159 -msse-check=[none|error|warning]\n\
11160 check SSE instructions\n"));
11161 fprintf (stream, _("\
11162 -moperand-check=[none|error|warning]\n\
11163 check operand combinations for validity\n"));
11164 fprintf (stream, _("\
11165 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11167 fprintf (stream, _("\
11168 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11170 fprintf (stream, _("\
11171 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11172 for EVEX.W bit ignored instructions\n"));
11173 fprintf (stream, _("\
11174 -mevexrcig=[rne|rd|ru|rz]\n\
11175 encode EVEX instructions with specific EVEX.RC value\n\
11176 for SAE-only ignored instructions\n"));
11177 fprintf (stream, _("\
11178 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11179 fprintf (stream, _("\
11180 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11181 fprintf (stream, _("\
11182 -mindex-reg support pseudo index registers\n"));
11183 fprintf (stream, _("\
11184 -mnaked-reg don't require `%%' prefix for registers\n"));
11185 fprintf (stream, _("\
11186 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11187 fprintf (stream, _("\
11188 -mshared disable branch optimization for shared code\n"));
11189 # if defined (TE_PE) || defined (TE_PEP)
11190 fprintf (stream, _("\
11191 -mbig-obj generate big object files\n"));
11193 fprintf (stream, _("\
11194 -momit-lock-prefix=[no|yes]\n\
11195 strip all lock prefixes\n"));
11196 fprintf (stream, _("\
11197 -mfence-as-lock-add=[no|yes]\n\
11198 encode lfence, mfence and sfence as\n\
11199 lock addl $0x0, (%%{re}sp)\n"));
11200 fprintf (stream, _("\
11201 -mrelax-relocations=[no|yes]\n\
11202 generate relax relocations\n"));
11203 fprintf (stream, _("\
11204 -mamd64 accept only AMD64 ISA\n"));
11205 fprintf (stream, _("\
11206 -mintel64 accept only Intel64 ISA\n"));
11209 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11210 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11211 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11213 /* Pick the target format to use. */
11216 i386_target_format (void)
11218 if (!strncmp (default_arch, "x86_64", 6))
11220 update_code_flag (CODE_64BIT, 1);
11221 if (default_arch[6] == '\0')
11222 x86_elf_abi = X86_64_ABI;
11224 x86_elf_abi = X86_64_X32_ABI;
11226 else if (!strcmp (default_arch, "i386"))
11227 update_code_flag (CODE_32BIT, 1);
11228 else if (!strcmp (default_arch, "iamcu"))
11230 update_code_flag (CODE_32BIT, 1);
11231 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11233 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11234 cpu_arch_name = "iamcu";
11235 cpu_sub_arch_name = NULL;
11236 cpu_arch_flags = iamcu_flags;
11237 cpu_arch_isa = PROCESSOR_IAMCU;
11238 cpu_arch_isa_flags = iamcu_flags;
11239 if (!cpu_arch_tune_set)
11241 cpu_arch_tune = cpu_arch_isa;
11242 cpu_arch_tune_flags = cpu_arch_isa_flags;
11245 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11246 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11250 as_fatal (_("unknown architecture"));
11252 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11253 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11254 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11255 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11257 switch (OUTPUT_FLAVOR)
11259 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11260 case bfd_target_aout_flavour:
11261 return AOUT_TARGET_FORMAT;
11263 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11264 # if defined (TE_PE) || defined (TE_PEP)
11265 case bfd_target_coff_flavour:
11266 if (flag_code == CODE_64BIT)
11267 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11270 # elif defined (TE_GO32)
11271 case bfd_target_coff_flavour:
11272 return "coff-go32";
11274 case bfd_target_coff_flavour:
11275 return "coff-i386";
11278 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11279 case bfd_target_elf_flavour:
11281 const char *format;
11283 switch (x86_elf_abi)
11286 format = ELF_TARGET_FORMAT;
11289 use_rela_relocations = 1;
11291 format = ELF_TARGET_FORMAT64;
11293 case X86_64_X32_ABI:
11294 use_rela_relocations = 1;
11296 disallow_64bit_reloc = 1;
11297 format = ELF_TARGET_FORMAT32;
11300 if (cpu_arch_isa == PROCESSOR_L1OM)
11302 if (x86_elf_abi != X86_64_ABI)
11303 as_fatal (_("Intel L1OM is 64bit only"));
11304 return ELF_TARGET_L1OM_FORMAT;
11306 else if (cpu_arch_isa == PROCESSOR_K1OM)
11308 if (x86_elf_abi != X86_64_ABI)
11309 as_fatal (_("Intel K1OM is 64bit only"));
11310 return ELF_TARGET_K1OM_FORMAT;
11312 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11314 if (x86_elf_abi != I386_ABI)
11315 as_fatal (_("Intel MCU is 32bit only"));
11316 return ELF_TARGET_IAMCU_FORMAT;
11322 #if defined (OBJ_MACH_O)
11323 case bfd_target_mach_o_flavour:
11324 if (flag_code == CODE_64BIT)
11326 use_rela_relocations = 1;
11328 return "mach-o-x86-64";
11331 return "mach-o-i386";
11339 #endif /* OBJ_MAYBE_ more than one */
11342 md_undefined_symbol (char *name)
11344 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11345 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11346 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11347 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11351 if (symbol_find (name))
11352 as_bad (_("GOT already in symbol table"));
11353 GOT_symbol = symbol_new (name, undefined_section,
11354 (valueT) 0, &zero_address_frag);
11361 /* Round up a section size to the appropriate boundary. */
11364 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11366 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11367 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11369 /* For a.out, force the section size to be aligned. If we don't do
11370 this, BFD will align it for us, but it will not write out the
11371 final bytes of the section. This may be a bug in BFD, but it is
11372 easier to fix it here since that is how the other a.out targets
11376 align = bfd_get_section_alignment (stdoutput, segment);
11377 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11384 /* On the i386, PC-relative offsets are relative to the start of the
11385 next instruction. That is, the address of the offset, plus its
11386 size, since the offset is always the last part of the insn. */
11389 md_pcrel_from (fixS *fixP)
11391 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11397 s_bss (int ignore ATTRIBUTE_UNUSED)
11401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11403 obj_elf_section_change_hook ();
11405 temp = get_absolute_expression ();
11406 subseg_set (bss_section, (subsegT) temp);
11407 demand_empty_rest_of_line ();
11413 i386_validate_fix (fixS *fixp)
11415 if (fixp->fx_subsy)
11417 if (fixp->fx_subsy == GOT_symbol)
11419 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11424 if (fixp->fx_tcbit2)
11425 fixp->fx_r_type = (fixp->fx_tcbit
11426 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11427 : BFD_RELOC_X86_64_GOTPCRELX);
11430 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11435 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11437 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11439 fixp->fx_subsy = 0;
11442 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11443 else if (!object_64bit)
11445 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11446 && fixp->fx_tcbit2)
11447 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11453 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11456 bfd_reloc_code_real_type code;
11458 switch (fixp->fx_r_type)
11460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11461 case BFD_RELOC_SIZE32:
11462 case BFD_RELOC_SIZE64:
11463 if (S_IS_DEFINED (fixp->fx_addsy)
11464 && !S_IS_EXTERNAL (fixp->fx_addsy))
11466 /* Resolve size relocation against local symbol to size of
11467 the symbol plus addend. */
11468 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11469 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11470 && !fits_in_unsigned_long (value))
11471 as_bad_where (fixp->fx_file, fixp->fx_line,
11472 _("symbol size computation overflow"));
11473 fixp->fx_addsy = NULL;
11474 fixp->fx_subsy = NULL;
11475 md_apply_fix (fixp, (valueT *) &value, NULL);
11479 /* Fall through. */
11481 case BFD_RELOC_X86_64_PLT32:
11482 case BFD_RELOC_X86_64_GOT32:
11483 case BFD_RELOC_X86_64_GOTPCREL:
11484 case BFD_RELOC_X86_64_GOTPCRELX:
11485 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11486 case BFD_RELOC_386_PLT32:
11487 case BFD_RELOC_386_GOT32:
11488 case BFD_RELOC_386_GOT32X:
11489 case BFD_RELOC_386_GOTOFF:
11490 case BFD_RELOC_386_GOTPC:
11491 case BFD_RELOC_386_TLS_GD:
11492 case BFD_RELOC_386_TLS_LDM:
11493 case BFD_RELOC_386_TLS_LDO_32:
11494 case BFD_RELOC_386_TLS_IE_32:
11495 case BFD_RELOC_386_TLS_IE:
11496 case BFD_RELOC_386_TLS_GOTIE:
11497 case BFD_RELOC_386_TLS_LE_32:
11498 case BFD_RELOC_386_TLS_LE:
11499 case BFD_RELOC_386_TLS_GOTDESC:
11500 case BFD_RELOC_386_TLS_DESC_CALL:
11501 case BFD_RELOC_X86_64_TLSGD:
11502 case BFD_RELOC_X86_64_TLSLD:
11503 case BFD_RELOC_X86_64_DTPOFF32:
11504 case BFD_RELOC_X86_64_DTPOFF64:
11505 case BFD_RELOC_X86_64_GOTTPOFF:
11506 case BFD_RELOC_X86_64_TPOFF32:
11507 case BFD_RELOC_X86_64_TPOFF64:
11508 case BFD_RELOC_X86_64_GOTOFF64:
11509 case BFD_RELOC_X86_64_GOTPC32:
11510 case BFD_RELOC_X86_64_GOT64:
11511 case BFD_RELOC_X86_64_GOTPCREL64:
11512 case BFD_RELOC_X86_64_GOTPC64:
11513 case BFD_RELOC_X86_64_GOTPLT64:
11514 case BFD_RELOC_X86_64_PLTOFF64:
11515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11516 case BFD_RELOC_X86_64_TLSDESC_CALL:
11517 case BFD_RELOC_RVA:
11518 case BFD_RELOC_VTABLE_ENTRY:
11519 case BFD_RELOC_VTABLE_INHERIT:
11521 case BFD_RELOC_32_SECREL:
11523 code = fixp->fx_r_type;
11525 case BFD_RELOC_X86_64_32S:
11526 if (!fixp->fx_pcrel)
11528 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11529 code = fixp->fx_r_type;
11532 /* Fall through. */
11534 if (fixp->fx_pcrel)
11536 switch (fixp->fx_size)
11539 as_bad_where (fixp->fx_file, fixp->fx_line,
11540 _("can not do %d byte pc-relative relocation"),
11542 code = BFD_RELOC_32_PCREL;
11544 case 1: code = BFD_RELOC_8_PCREL; break;
11545 case 2: code = BFD_RELOC_16_PCREL; break;
11546 case 4: code = BFD_RELOC_32_PCREL; break;
11548 case 8: code = BFD_RELOC_64_PCREL; break;
11554 switch (fixp->fx_size)
11557 as_bad_where (fixp->fx_file, fixp->fx_line,
11558 _("can not do %d byte relocation"),
11560 code = BFD_RELOC_32;
11562 case 1: code = BFD_RELOC_8; break;
11563 case 2: code = BFD_RELOC_16; break;
11564 case 4: code = BFD_RELOC_32; break;
11566 case 8: code = BFD_RELOC_64; break;
11573 if ((code == BFD_RELOC_32
11574 || code == BFD_RELOC_32_PCREL
11575 || code == BFD_RELOC_X86_64_32S)
11577 && fixp->fx_addsy == GOT_symbol)
11580 code = BFD_RELOC_386_GOTPC;
11582 code = BFD_RELOC_X86_64_GOTPC32;
11584 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11586 && fixp->fx_addsy == GOT_symbol)
11588 code = BFD_RELOC_X86_64_GOTPC64;
11591 rel = XNEW (arelent);
11592 rel->sym_ptr_ptr = XNEW (asymbol *);
11593 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11595 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11597 if (!use_rela_relocations)
11599 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11600 vtable entry to be used in the relocation's section offset. */
11601 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11602 rel->address = fixp->fx_offset;
11603 #if defined (OBJ_COFF) && defined (TE_PE)
11604 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11605 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11610 /* Use the rela in 64bit mode. */
11613 if (disallow_64bit_reloc)
11616 case BFD_RELOC_X86_64_DTPOFF64:
11617 case BFD_RELOC_X86_64_TPOFF64:
11618 case BFD_RELOC_64_PCREL:
11619 case BFD_RELOC_X86_64_GOTOFF64:
11620 case BFD_RELOC_X86_64_GOT64:
11621 case BFD_RELOC_X86_64_GOTPCREL64:
11622 case BFD_RELOC_X86_64_GOTPC64:
11623 case BFD_RELOC_X86_64_GOTPLT64:
11624 case BFD_RELOC_X86_64_PLTOFF64:
11625 as_bad_where (fixp->fx_file, fixp->fx_line,
11626 _("cannot represent relocation type %s in x32 mode"),
11627 bfd_get_reloc_code_name (code));
11633 if (!fixp->fx_pcrel)
11634 rel->addend = fixp->fx_offset;
11638 case BFD_RELOC_X86_64_PLT32:
11639 case BFD_RELOC_X86_64_GOT32:
11640 case BFD_RELOC_X86_64_GOTPCREL:
11641 case BFD_RELOC_X86_64_GOTPCRELX:
11642 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11643 case BFD_RELOC_X86_64_TLSGD:
11644 case BFD_RELOC_X86_64_TLSLD:
11645 case BFD_RELOC_X86_64_GOTTPOFF:
11646 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11647 case BFD_RELOC_X86_64_TLSDESC_CALL:
11648 rel->addend = fixp->fx_offset - fixp->fx_size;
11651 rel->addend = (section->vma
11653 + fixp->fx_addnumber
11654 + md_pcrel_from (fixp));
11659 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11660 if (rel->howto == NULL)
11662 as_bad_where (fixp->fx_file, fixp->fx_line,
11663 _("cannot represent relocation type %s"),
11664 bfd_get_reloc_code_name (code));
11665 /* Set howto to a garbage value so that we can keep going. */
11666 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11667 gas_assert (rel->howto != NULL);
11673 #include "tc-i386-intel.c"
11676 tc_x86_parse_to_dw2regnum (expressionS *exp)
11678 int saved_naked_reg;
11679 char saved_register_dot;
11681 saved_naked_reg = allow_naked_reg;
11682 allow_naked_reg = 1;
11683 saved_register_dot = register_chars['.'];
11684 register_chars['.'] = '.';
11685 allow_pseudo_reg = 1;
11686 expression_and_evaluate (exp);
11687 allow_pseudo_reg = 0;
11688 register_chars['.'] = saved_register_dot;
11689 allow_naked_reg = saved_naked_reg;
11691 if (exp->X_op == O_register && exp->X_add_number >= 0)
11693 if ((addressT) exp->X_add_number < i386_regtab_size)
11695 exp->X_op = O_constant;
11696 exp->X_add_number = i386_regtab[exp->X_add_number]
11697 .dw2_regnum[flag_code >> 1];
11700 exp->X_op = O_illegal;
11705 tc_x86_frame_initial_instructions (void)
11707 static unsigned int sp_regno[2];
11709 if (!sp_regno[flag_code >> 1])
11711 char *saved_input = input_line_pointer;
11712 char sp[][4] = {"esp", "rsp"};
11715 input_line_pointer = sp[flag_code >> 1];
11716 tc_x86_parse_to_dw2regnum (&exp);
11717 gas_assert (exp.X_op == O_constant);
11718 sp_regno[flag_code >> 1] = exp.X_add_number;
11719 input_line_pointer = saved_input;
11722 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11723 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11727 x86_dwarf2_addr_size (void)
11729 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11730 if (x86_elf_abi == X86_64_X32_ABI)
11733 return bfd_arch_bits_per_address (stdoutput) / 8;
11737 i386_elf_section_type (const char *str, size_t len)
11739 if (flag_code == CODE_64BIT
11740 && len == sizeof ("unwind") - 1
11741 && strncmp (str, "unwind", 6) == 0)
11742 return SHT_X86_64_UNWIND;
11749 i386_solaris_fix_up_eh_frame (segT sec)
11751 if (flag_code == CODE_64BIT)
11752 elf_section_type (sec) = SHT_X86_64_UNWIND;
11758 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11762 exp.X_op = O_secrel;
11763 exp.X_add_symbol = symbol;
11764 exp.X_add_number = 0;
11765 emit_expr (&exp, size);
11769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11770 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11773 x86_64_section_letter (int letter, const char **ptr_msg)
11775 if (flag_code == CODE_64BIT)
11778 return SHF_X86_64_LARGE;
11780 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11783 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11788 x86_64_section_word (char *str, size_t len)
11790 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11791 return SHF_X86_64_LARGE;
11797 handle_large_common (int small ATTRIBUTE_UNUSED)
11799 if (flag_code != CODE_64BIT)
11801 s_comm_internal (0, elf_common_parse);
11802 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11806 static segT lbss_section;
11807 asection *saved_com_section_ptr = elf_com_section_ptr;
11808 asection *saved_bss_section = bss_section;
11810 if (lbss_section == NULL)
11812 flagword applicable;
11813 segT seg = now_seg;
11814 subsegT subseg = now_subseg;
11816 /* The .lbss section is for local .largecomm symbols. */
11817 lbss_section = subseg_new (".lbss", 0);
11818 applicable = bfd_applicable_section_flags (stdoutput);
11819 bfd_set_section_flags (stdoutput, lbss_section,
11820 applicable & SEC_ALLOC);
11821 seg_info (lbss_section)->bss = 1;
11823 subseg_set (seg, subseg);
11826 elf_com_section_ptr = &_bfd_elf_large_com_section;
11827 bss_section = lbss_section;
11829 s_comm_internal (0, elf_common_parse);
11831 elf_com_section_ptr = saved_com_section_ptr;
11832 bss_section = saved_bss_section;
11835 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */