1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry *parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry *build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS *, offsetT);
95 static void output_disp (fragS *, offsetT);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED);
103 static const char *default_arch = DEFAULT_ARCH;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry *regs;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types[MAX_OPERANDS];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op[MAX_OPERANDS];
140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry *seg[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars = "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars = "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars[] = "#/";
212 const char line_separator_chars[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars[256];
225 static char register_chars[256];
226 static char operand_chars[256];
227 static char identifier_chars[256];
228 static char digit_chars[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack[32];
246 static char *save_stack_p;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates *current_templates;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
262 /* Current operand we are working on. */
263 static int this_operand;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code;
275 static unsigned int object_64bit;
276 static int use_rela_relocations = 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names[] =
286 /* 1 for intel syntax,
288 static int intel_syntax = 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg = 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix = "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size = '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code = 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings = 0;
308 static const char *cpu_arch_name = NULL;
309 static const char *cpu_sub_arch_name = NULL;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set = 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags = 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags = 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion = 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS *GOT_symbol;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch[] =
423 {"generic32", PROCESSOR_GENERIC32,
424 Cpu186|Cpu286|Cpu386},
425 {"generic64", PROCESSOR_GENERIC64,
426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
430 {"i186", PROCESSOR_UNKNOWN,
432 {"i286", PROCESSOR_UNKNOWN,
434 {"i386", PROCESSOR_GENERIC32,
435 Cpu186|Cpu286|Cpu386},
436 {"i486", PROCESSOR_I486,
437 Cpu186|Cpu286|Cpu386|Cpu486},
438 {"i586", PROCESSOR_PENTIUM,
439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
440 {"i686", PROCESSOR_PENTIUMPRO,
441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
442 {"pentium", PROCESSOR_PENTIUM,
443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
446 {"pentiumii", PROCESSOR_PENTIUMPRO,
447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
450 {"pentium4", PROCESSOR_PENTIUM4,
451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
459 {"yonah", PROCESSOR_CORE,
460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
462 {"core", PROCESSOR_CORE,
463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
473 {"k6_2", PROCESSOR_K6,
474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
475 {"athlon", PROCESSOR_ATHLON,
476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
487 {"amdfam10", PROCESSOR_AMDFAM10,
488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN,
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
501 {".3dnow", PROCESSOR_UNKNOWN,
503 {".3dnowa", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
505 {".padlock", PROCESSOR_UNKNOWN,
507 {".pacifica", PROCESSOR_UNKNOWN,
509 {".svme", PROCESSOR_UNKNOWN,
511 {".sse4a", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
513 {".abm", PROCESSOR_UNKNOWN,
517 const pseudo_typeS md_pseudo_table[] =
519 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
520 {"align", s_align_bytes, 0},
522 {"align", s_align_ptwo, 0},
524 {"arch", set_cpu_arch, 0},
528 {"ffloat", float_cons, 'f'},
529 {"dfloat", float_cons, 'd'},
530 {"tfloat", float_cons, 'x'},
532 {"slong", signed_cons, 4},
533 {"noopt", s_ignore, 0},
534 {"optim", s_ignore, 0},
535 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
536 {"code16", set_code_flag, CODE_16BIT},
537 {"code32", set_code_flag, CODE_32BIT},
538 {"code64", set_code_flag, CODE_64BIT},
539 {"intel_syntax", set_intel_syntax, 1},
540 {"att_syntax", set_intel_syntax, 0},
541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
542 {"largecomm", handle_large_common, 0},
544 {"file", (void (*) (int)) dwarf2_directive_file, 0},
545 {"loc", dwarf2_directive_loc, 0},
546 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
549 {"secrel32", pe_directive_secrel, 0},
554 /* For interface with expression (). */
555 extern char *input_line_pointer;
557 /* Hash table for instruction mnemonic lookup. */
558 static struct hash_control *op_hash;
560 /* Hash table for register lookup. */
561 static struct hash_control *reg_hash;
564 i386_align_code (fragS *fragP, int count)
566 /* Various efficient no-op patterns for aligning code labels.
567 Note: Don't try to assemble the instructions in the comments.
568 0L and 0w are not legal. */
569 static const char f32_1[] =
571 static const char f32_2[] =
572 {0x66,0x90}; /* xchg %ax,%ax */
573 static const char f32_3[] =
574 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
575 static const char f32_4[] =
576 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
577 static const char f32_5[] =
579 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
580 static const char f32_6[] =
581 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
582 static const char f32_7[] =
583 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
584 static const char f32_8[] =
586 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
587 static const char f32_9[] =
588 {0x89,0xf6, /* movl %esi,%esi */
589 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
590 static const char f32_10[] =
591 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
592 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
593 static const char f32_11[] =
594 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_12[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
598 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
599 static const char f32_13[] =
600 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_14[] =
603 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_15[] =
606 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
607 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
608 static const char f16_3[] =
609 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
610 static const char f16_4[] =
611 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
612 static const char f16_5[] =
614 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_6[] =
616 {0x89,0xf6, /* mov %si,%si */
617 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
618 static const char f16_7[] =
619 {0x8d,0x74,0x00, /* lea 0(%si),%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_8[] =
622 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
628 static const char *const f16_patt[] = {
629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
630 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
633 static const char alt_3[] =
635 /* nopl 0(%[re]ax) */
636 static const char alt_4[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11[] =
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13[] =
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14[] =
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15[] =
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
713 static const char alt_short_13[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 static const char alt_short_14[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt[] = {
727 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
728 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
729 alt_short_14, alt_short_15
731 static const char *const alt_long_patt[] = {
732 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
733 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
734 alt_long_14, alt_long_15
737 if (count <= 0 || count > 15)
740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
743 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
744 f32_patt will be used.
745 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
746 0x66 prefix will be used.
747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code == CODE_16BIT)
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
776 for (i = 0; i < remains; i++)
778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
782 for (; i < nnops; i++)
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
791 const char *const *patt = NULL;
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
806 case PROCESSOR_CORE2:
807 patt = alt_long_patt;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
814 case PROCESSOR_ATHLON:
816 case PROCESSOR_GENERIC64:
817 case PROCESSOR_AMDFAM10:
818 patt = alt_short_patt;
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
829 switch (cpu_arch_tune)
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
844 case PROCESSOR_ATHLON:
846 case PROCESSOR_AMDFAM10:
847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
855 case PROCESSOR_CORE2:
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
867 memcpy (fragP->fr_literal + fragP->fr_fix,
868 patt[count - 1], count);
870 fragP->fr_var = count;
873 static INLINE unsigned int
874 mode_from_disp_size (unsigned int t)
876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
880 fits_in_signed_byte (offsetT num)
882 return (num >= -128) && (num <= 127);
886 fits_in_unsigned_byte (offsetT num)
888 return (num & 0xff) == num;
892 fits_in_unsigned_word (offsetT num)
894 return (num & 0xffff) == num;
898 fits_in_signed_word (offsetT num)
900 return (-32768 <= num) && (num <= 32767);
904 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
912 } /* fits_in_signed_long() */
915 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
922 } /* fits_in_unsigned_long() */
925 smallest_imm_type (offsetT num)
927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
937 return (fits_in_signed_byte (num)
938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
939 : fits_in_unsigned_byte (num)
940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
951 offset_in_range (offsetT val, int size)
957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
959 case 4: mask = ((addressT) 2 << 31) - 1; break;
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
966 /* If BFD64, sign extend val. */
967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
973 char buf1[40], buf2[40];
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
982 /* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
986 add_prefix (unsigned int prefix)
991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
994 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
995 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
996 && (prefix & (REX_R | REX_X | REX_B))))
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1020 case LOCK_PREFIX_OPCODE:
1028 case ADDR_PREFIX_OPCODE:
1032 case DATA_PREFIX_OPCODE:
1036 if (i.prefix[q] != 0)
1044 i.prefix[q] |= prefix;
1047 as_bad (_("same type of prefix used twice"));
1053 set_code_flag (int value)
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1060 as_bad (_("64bit mode not supported on this CPU."));
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1064 as_bad (_("32bit mode not supported on this CPU."));
1066 stackop_size = '\0';
1070 set_16bit_gcc_code_flag (int new_code_flag)
1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1075 stackop_size = LONG_MNEM_SUFFIX;
1079 set_intel_syntax (int syntax_flag)
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1090 if (strcmp (string, "prefix") == 0)
1092 else if (strcmp (string, "noprefix") == 0)
1095 as_bad (_("bad argument to syntax directive."));
1096 *input_line_pointer = e;
1098 demand_empty_rest_of_line ();
1100 intel_syntax = syntax_flag;
1102 if (ask_naked_reg == 0)
1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1106 allow_naked_reg = (ask_naked_reg < 0);
1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
1110 register_prefix = allow_naked_reg ? "" : "%";
1114 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
1133 | (flag_code == CODE_64BIT
1134 ? Cpu64 : CpuNo64));
1135 cpu_arch_isa = cpu_arch[i].type;
1136 cpu_arch_isa_flags = cpu_arch[i].flags;
1137 if (!cpu_arch_tune_set)
1139 cpu_arch_tune = cpu_arch_isa;
1140 cpu_arch_tune_flags = cpu_arch_isa_flags;
1144 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1146 cpu_sub_arch_name = cpu_arch[i].name;
1147 cpu_arch_flags |= cpu_arch[i].flags;
1149 *input_line_pointer = e;
1150 demand_empty_rest_of_line ();
1154 if (i >= ARRAY_SIZE (cpu_arch))
1155 as_bad (_("no such architecture: `%s'"), string);
1157 *input_line_pointer = e;
1160 as_bad (_("missing cpu architecture"));
1162 no_cond_jump_promotion = 0;
1163 if (*input_line_pointer == ','
1164 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1166 char *string = ++input_line_pointer;
1167 int e = get_symbol_end ();
1169 if (strcmp (string, "nojumps") == 0)
1170 no_cond_jump_promotion = 1;
1171 else if (strcmp (string, "jumps") == 0)
1174 as_bad (_("no such architecture modifier: `%s'"), string);
1176 *input_line_pointer = e;
1179 demand_empty_rest_of_line ();
1185 if (!strcmp (default_arch, "x86_64"))
1186 return bfd_mach_x86_64;
1187 else if (!strcmp (default_arch, "i386"))
1188 return bfd_mach_i386_i386;
1190 as_fatal (_("Unknown architecture"));
1196 const char *hash_err;
1198 /* Initialize op_hash hash table. */
1199 op_hash = hash_new ();
1202 const template *optab;
1203 templates *core_optab;
1205 /* Setup for loop. */
1207 core_optab = (templates *) xmalloc (sizeof (templates));
1208 core_optab->start = optab;
1213 if (optab->name == NULL
1214 || strcmp (optab->name, (optab - 1)->name) != 0)
1216 /* different name --> ship out current template list;
1217 add to hash table; & begin anew. */
1218 core_optab->end = optab;
1219 hash_err = hash_insert (op_hash,
1224 as_fatal (_("Internal Error: Can't hash %s: %s"),
1228 if (optab->name == NULL)
1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1236 /* Initialize reg_hash hash table. */
1237 reg_hash = hash_new ();
1239 const reg_entry *regtab;
1240 unsigned int regtab_size = i386_regtab_size;
1242 for (regtab = i386_regtab; regtab_size--; regtab++)
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1257 for (c = 0; c < 256; c++)
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1266 else if (ISLOWER (c))
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1272 else if (ISUPPER (c))
1274 mnemonic_chars[c] = TOLOWER (c);
1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1279 if (ISALPHA (c) || ISDIGIT (c))
1280 identifier_chars[c] = c;
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1289 identifier_chars['@'] = '@';
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
1295 digit_chars['-'] = '-';
1296 mnemonic_chars['-'] = '-';
1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1313 if (flag_code == CODE_64BIT)
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1326 i386_print_statistics (FILE *file)
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1334 /* Debugging routines for md_assemble. */
1335 static void pte (template *);
1336 static void pt (unsigned int);
1337 static void pe (expressionS *);
1338 static void ps (symbolS *);
1341 pi (char *line, i386_insn *x)
1345 fprintf (stdout, "%s: template ", line);
1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1352 x->rm.mode, x->rm.reg, x->rm.regmem);
1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1356 (x->rex & REX_W) != 0,
1357 (x->rex & REX_R) != 0,
1358 (x->rex & REX_X) != 0,
1359 (x->rex & REX_B) != 0);
1360 for (i = 0; i < x->operands; i++)
1362 fprintf (stdout, " #%d: ", i + 1);
1364 fprintf (stdout, "\n");
1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1368 if (x->types[i] & Imm)
1370 if (x->types[i] & Disp)
1371 pe (x->op[i].disps);
1379 fprintf (stdout, " %d operands ", t->operands);
1380 fprintf (stdout, "opcode %x ", t->base_opcode);
1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1399 fprintf (stdout, " operation %d\n", e->X_op);
1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
1402 if (e->X_add_symbol)
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1419 fprintf (stdout, "%s type %s%s",
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1425 static struct type_name
1430 const type_names[] =
1443 { BaseIndex, "BaseIndex" },
1447 { Disp32S, "d32s" },
1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1459 { JumpAbsolute, "Jump Absolute" },
1470 const struct type_name *ty;
1472 for (ty = type_names; ty->mask; ty++)
1474 fprintf (stdout, "%s, ", ty->tname);
1478 #endif /* DEBUG386 */
1480 static bfd_reloc_code_real_type
1481 reloc (unsigned int size,
1484 bfd_reloc_code_real_type other)
1486 if (other != NO_RELOC)
1488 reloc_howto_type *reloc;
1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
1532 as_bad (_("relocated field and relocation type differ in signedness"));
1541 as_bad (_("there are no unsigned pc-relative relocations"));
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
1547 case 8: return BFD_RELOC_64_PCREL;
1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1556 case 4: return BFD_RELOC_X86_64_32S;
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
1571 return BFD_RELOC_NONE;
1574 /* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1580 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
1582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1599 /* adjust_reloc_syms doesn't know about the GOT. */
1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1634 intel_float_operand (const char *mnemonic)
1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1643 switch (mnemonic[1])
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1649 return 2 /* integer op */;
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1667 switch (mnemonic[3])
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1686 /* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1695 char mnemonic[MAX_MNEM_SIZE];
1697 /* Initialize globals. */
1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1700 i.reloc[j] = NO_RELOC;
1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
1703 save_stack_p = save_stack;
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
1707 start of a (possibly prefixed) mnemonic. */
1709 line = parse_insn (line, mnemonic);
1713 line = parse_operands (line, mnemonic);
1717 /* The order of the immediates should be reversed
1718 for 2 immediates extrq and insertq instructions */
1719 if ((i.imm_operands == 2)
1720 && ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
1723 swap_2_operands (0, 1);
1724 /* "extrq" and insertq" are the only two instructions whose operands
1725 have to be reversed even though they have two immediate operands.
1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
1737 precedes the offset, as it does when in AT&T mode. */
1740 && (strcmp (mnemonic, "bound") != 0)
1741 && (strcmp (mnemonic, "invlpga") != 0)
1742 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1748 /* Don't optimize displacement for movabs since it only takes 64bit
1751 && (flag_code != CODE_64BIT
1752 || strcmp (mnemonic, "movabs") != 0))
1755 /* Next, we find a template that matches the given insn,
1756 making sure the overlap of the given operands types is consistent
1757 with the template operand types. */
1759 if (!match_template ())
1764 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1766 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1767 i.tm.base_opcode ^= Opcode_FloatR;
1769 /* Zap movzx and movsx suffix. The suffix may have been set from
1770 "word ptr" or "byte ptr" on the source operand, but we'll use
1771 the suffix later to choose the destination register. */
1772 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1774 if (i.reg_operands < 2
1776 && (~i.tm.opcode_modifier
1783 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1789 if (i.tm.opcode_modifier & FWait)
1790 if (!add_prefix (FWAIT_OPCODE))
1793 /* Check string instruction segment overrides. */
1794 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1796 if (!check_string ())
1800 if (!process_suffix ())
1803 /* Make still unresolved immediate matches conform to size of immediate
1804 given in i.suffix. */
1805 if (!finalize_imm ())
1808 if (i.types[0] & Imm1)
1809 i.imm_operands = 0; /* kludge for shift insns. */
1810 if (i.types[0] & ImplicitRegister)
1812 if (i.types[1] & ImplicitRegister)
1814 if (i.types[2] & ImplicitRegister)
1817 if (i.tm.opcode_modifier & ImmExt)
1821 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
1823 /* Streaming SIMD extensions 3 Instructions have the fixed
1824 operands with an opcode suffix which is coded in the same
1825 place as an 8-bit immediate field would be. Here we check
1826 those operands and remove them afterwards. */
1829 for (x = 0; x < i.operands; x++)
1830 if (i.op[x].regs->reg_num != x)
1831 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1832 i.op[x].regs->reg_name, x + 1, i.tm.name);
1836 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1837 opcode suffix which is coded in the same place as an 8-bit
1838 immediate field would be. Here we fake an 8-bit immediate
1839 operand from the opcode suffix stored in tm.extension_opcode. */
1841 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1843 exp = &im_expressions[i.imm_operands++];
1844 i.op[i.operands].imms = exp;
1845 i.types[i.operands++] = Imm8;
1846 exp->X_op = O_constant;
1847 exp->X_add_number = i.tm.extension_opcode;
1848 i.tm.extension_opcode = None;
1851 /* For insns with operands there are more diddles to do to the opcode. */
1854 if (!process_operands ())
1857 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1859 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1860 as_warn (_("translating to `%sp'"), i.tm.name);
1863 /* Handle conversion of 'int $3' --> special int3 insn. */
1864 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1866 i.tm.base_opcode = INT3_OPCODE;
1870 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1871 && i.op[0].disps->X_op == O_constant)
1873 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1874 the absolute address given by the constant. Since ix86 jumps and
1875 calls are pc relative, we need to generate a reloc. */
1876 i.op[0].disps->X_add_symbol = &abs_symbol;
1877 i.op[0].disps->X_op = O_symbol;
1880 if ((i.tm.opcode_modifier & Rex64) != 0)
1883 /* For 8 bit registers we need an empty rex prefix. Also if the
1884 instruction already has a prefix, we need to convert old
1885 registers to new ones. */
1887 if (((i.types[0] & Reg8) != 0
1888 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1889 || ((i.types[1] & Reg8) != 0
1890 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1891 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1896 i.rex |= REX_OPCODE;
1897 for (x = 0; x < 2; x++)
1899 /* Look for 8 bit operand that uses old registers. */
1900 if ((i.types[x] & Reg8) != 0
1901 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1903 /* In case it is "hi" register, give up. */
1904 if (i.op[x].regs->reg_num > 3)
1905 as_bad (_("can't encode register '%%%s' in an "
1906 "instruction requiring REX prefix."),
1907 i.op[x].regs->reg_name);
1909 /* Otherwise it is equivalent to the extended register.
1910 Since the encoding doesn't change this is merely
1911 cosmetic cleanup for debug output. */
1913 i.op[x].regs = i.op[x].regs + 8;
1919 add_prefix (REX_OPCODE | i.rex);
1921 /* We are ready to output the insn. */
1926 parse_insn (char *line, char *mnemonic)
1929 char *token_start = l;
1934 /* Non-zero if we found a prefix only acceptable with string insns. */
1935 const char *expecting_string_instruction = NULL;
1940 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1943 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1945 as_bad (_("no such instruction: `%s'"), token_start);
1950 if (!is_space_char (*l)
1951 && *l != END_OF_INSN
1953 || (*l != PREFIX_SEPARATOR
1956 as_bad (_("invalid character %s in mnemonic"),
1957 output_invalid (*l));
1960 if (token_start == l)
1962 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1963 as_bad (_("expecting prefix; got nothing"));
1965 as_bad (_("expecting mnemonic; got nothing"));
1969 /* Look up instruction (or prefix) via hash table. */
1970 current_templates = hash_find (op_hash, mnemonic);
1972 if (*l != END_OF_INSN
1973 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1974 && current_templates
1975 && (current_templates->start->opcode_modifier & IsPrefix))
1977 if (current_templates->start->cpu_flags
1978 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1980 as_bad ((flag_code != CODE_64BIT
1981 ? _("`%s' is only supported in 64-bit mode")
1982 : _("`%s' is not supported in 64-bit mode")),
1983 current_templates->start->name);
1986 /* If we are in 16-bit mode, do not allow addr16 or data16.
1987 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1988 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1989 && flag_code != CODE_64BIT
1990 && (((current_templates->start->opcode_modifier & Size32) != 0)
1991 ^ (flag_code == CODE_16BIT)))
1993 as_bad (_("redundant %s prefix"),
1994 current_templates->start->name);
1997 /* Add prefix, checking for repeated prefixes. */
1998 switch (add_prefix (current_templates->start->base_opcode))
2003 expecting_string_instruction = current_templates->start->name;
2006 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2013 if (!current_templates)
2015 /* See if we can get a match by trimming off a suffix. */
2018 case WORD_MNEM_SUFFIX:
2019 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2020 i.suffix = SHORT_MNEM_SUFFIX;
2022 case BYTE_MNEM_SUFFIX:
2023 case QWORD_MNEM_SUFFIX:
2024 i.suffix = mnem_p[-1];
2026 current_templates = hash_find (op_hash, mnemonic);
2028 case SHORT_MNEM_SUFFIX:
2029 case LONG_MNEM_SUFFIX:
2032 i.suffix = mnem_p[-1];
2034 current_templates = hash_find (op_hash, mnemonic);
2042 if (intel_float_operand (mnemonic) == 1)
2043 i.suffix = SHORT_MNEM_SUFFIX;
2045 i.suffix = LONG_MNEM_SUFFIX;
2047 current_templates = hash_find (op_hash, mnemonic);
2051 if (!current_templates)
2053 as_bad (_("no such instruction: `%s'"), token_start);
2058 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2060 /* Check for a branch hint. We allow ",pt" and ",pn" for
2061 predict taken and predict not taken respectively.
2062 I'm not sure that branch hints actually do anything on loop
2063 and jcxz insns (JumpByte) for current Pentium4 chips. They
2064 may work in the future and it doesn't hurt to accept them
2066 if (l[0] == ',' && l[1] == 'p')
2070 if (!add_prefix (DS_PREFIX_OPCODE))
2074 else if (l[2] == 'n')
2076 if (!add_prefix (CS_PREFIX_OPCODE))
2082 /* Any other comma loses. */
2085 as_bad (_("invalid character %s in mnemonic"),
2086 output_invalid (*l));
2090 /* Check if instruction is supported on specified architecture. */
2092 for (t = current_templates->start; t < current_templates->end; ++t)
2094 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2095 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2097 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2100 if (!(supported & 2))
2102 as_bad (flag_code == CODE_64BIT
2103 ? _("`%s' is not supported in 64-bit mode")
2104 : _("`%s' is only supported in 64-bit mode"),
2105 current_templates->start->name);
2108 if (!(supported & 1))
2110 as_warn (_("`%s' is not supported on `%s%s'"),
2111 current_templates->start->name,
2113 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2115 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2117 as_warn (_("use .code16 to ensure correct addressing mode"));
2120 /* Check for rep/repne without a string instruction. */
2121 if (expecting_string_instruction)
2123 static templates override;
2125 for (t = current_templates->start; t < current_templates->end; ++t)
2126 if (t->opcode_modifier & IsString)
2128 if (t >= current_templates->end)
2130 as_bad (_("expecting string instruction after `%s'"),
2131 expecting_string_instruction);
2134 for (override.start = t; t < current_templates->end; ++t)
2135 if (!(t->opcode_modifier & IsString))
2138 current_templates = &override;
2145 parse_operands (char *l, const char *mnemonic)
2149 /* 1 if operand is pending after ','. */
2150 unsigned int expecting_operand = 0;
2152 /* Non-zero if operand parens not balanced. */
2153 unsigned int paren_not_balanced;
2155 while (*l != END_OF_INSN)
2157 /* Skip optional white space before operand. */
2158 if (is_space_char (*l))
2160 if (!is_operand_char (*l) && *l != END_OF_INSN)
2162 as_bad (_("invalid character %s before operand %d"),
2163 output_invalid (*l),
2167 token_start = l; /* after white space */
2168 paren_not_balanced = 0;
2169 while (paren_not_balanced || *l != ',')
2171 if (*l == END_OF_INSN)
2173 if (paren_not_balanced)
2176 as_bad (_("unbalanced parenthesis in operand %d."),
2179 as_bad (_("unbalanced brackets in operand %d."),
2184 break; /* we are done */
2186 else if (!is_operand_char (*l) && !is_space_char (*l))
2188 as_bad (_("invalid character %s in operand %d"),
2189 output_invalid (*l),
2196 ++paren_not_balanced;
2198 --paren_not_balanced;
2203 ++paren_not_balanced;
2205 --paren_not_balanced;
2209 if (l != token_start)
2210 { /* Yes, we've read in another operand. */
2211 unsigned int operand_ok;
2212 this_operand = i.operands++;
2213 if (i.operands > MAX_OPERANDS)
2215 as_bad (_("spurious operands; (%d operands/instruction max)"),
2219 /* Now parse operand adding info to 'i' as we go along. */
2220 END_STRING_AND_SAVE (l);
2224 i386_intel_operand (token_start,
2225 intel_float_operand (mnemonic));
2227 operand_ok = i386_operand (token_start);
2229 RESTORE_END_STRING (l);
2235 if (expecting_operand)
2237 expecting_operand_after_comma:
2238 as_bad (_("expecting operand after ','; got nothing"));
2243 as_bad (_("expecting operand before ','; got nothing"));
2248 /* Now *l must be either ',' or END_OF_INSN. */
2251 if (*++l == END_OF_INSN)
2253 /* Just skip it, if it's \n complain. */
2254 goto expecting_operand_after_comma;
2256 expecting_operand = 1;
2263 swap_2_operands (int xchg1, int xchg2)
2265 union i386_op temp_op;
2266 unsigned int temp_type;
2267 enum bfd_reloc_code_real temp_reloc;
2269 temp_type = i.types[xchg2];
2270 i.types[xchg2] = i.types[xchg1];
2271 i.types[xchg1] = temp_type;
2272 temp_op = i.op[xchg2];
2273 i.op[xchg2] = i.op[xchg1];
2274 i.op[xchg1] = temp_op;
2275 temp_reloc = i.reloc[xchg2];
2276 i.reloc[xchg2] = i.reloc[xchg1];
2277 i.reloc[xchg1] = temp_reloc;
2281 swap_operands (void)
2286 swap_2_operands (1, i.operands - 2);
2289 swap_2_operands (0, i.operands - 1);
2295 if (i.mem_operands == 2)
2297 const seg_entry *temp_seg;
2298 temp_seg = i.seg[0];
2299 i.seg[0] = i.seg[1];
2300 i.seg[1] = temp_seg;
2304 /* Try to ensure constant immediates are represented in the smallest
2309 char guess_suffix = 0;
2313 guess_suffix = i.suffix;
2314 else if (i.reg_operands)
2316 /* Figure out a suffix from the last register operand specified.
2317 We can't do this properly yet, ie. excluding InOutPortReg,
2318 but the following works for instructions with immediates.
2319 In any case, we can't set i.suffix yet. */
2320 for (op = i.operands; --op >= 0;)
2321 if (i.types[op] & Reg)
2323 if (i.types[op] & Reg8)
2324 guess_suffix = BYTE_MNEM_SUFFIX;
2325 else if (i.types[op] & Reg16)
2326 guess_suffix = WORD_MNEM_SUFFIX;
2327 else if (i.types[op] & Reg32)
2328 guess_suffix = LONG_MNEM_SUFFIX;
2329 else if (i.types[op] & Reg64)
2330 guess_suffix = QWORD_MNEM_SUFFIX;
2334 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2335 guess_suffix = WORD_MNEM_SUFFIX;
2337 for (op = i.operands; --op >= 0;)
2338 if (i.types[op] & Imm)
2340 switch (i.op[op].imms->X_op)
2343 /* If a suffix is given, this operand may be shortened. */
2344 switch (guess_suffix)
2346 case LONG_MNEM_SUFFIX:
2347 i.types[op] |= Imm32 | Imm64;
2349 case WORD_MNEM_SUFFIX:
2350 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2352 case BYTE_MNEM_SUFFIX:
2353 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2357 /* If this operand is at most 16 bits, convert it
2358 to a signed 16 bit number before trying to see
2359 whether it will fit in an even smaller size.
2360 This allows a 16-bit operand such as $0xffe0 to
2361 be recognised as within Imm8S range. */
2362 if ((i.types[op] & Imm16)
2363 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2365 i.op[op].imms->X_add_number =
2366 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2368 if ((i.types[op] & Imm32)
2369 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2372 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2373 ^ ((offsetT) 1 << 31))
2374 - ((offsetT) 1 << 31));
2376 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2378 /* We must avoid matching of Imm32 templates when 64bit
2379 only immediate is available. */
2380 if (guess_suffix == QWORD_MNEM_SUFFIX)
2381 i.types[op] &= ~Imm32;
2388 /* Symbols and expressions. */
2390 /* Convert symbolic operand to proper sizes for matching, but don't
2391 prevent matching a set of insns that only supports sizes other
2392 than those matching the insn suffix. */
2394 unsigned int mask, allowed = 0;
2397 for (t = current_templates->start;
2398 t < current_templates->end;
2400 allowed |= t->operand_types[op];
2401 switch (guess_suffix)
2403 case QWORD_MNEM_SUFFIX:
2404 mask = Imm64 | Imm32S;
2406 case LONG_MNEM_SUFFIX:
2409 case WORD_MNEM_SUFFIX:
2412 case BYTE_MNEM_SUFFIX:
2420 i.types[op] &= mask;
2427 /* Try to use the smallest displacement type too. */
2429 optimize_disp (void)
2433 for (op = i.operands; --op >= 0;)
2434 if (i.types[op] & Disp)
2436 if (i.op[op].disps->X_op == O_constant)
2438 offsetT disp = i.op[op].disps->X_add_number;
2440 if ((i.types[op] & Disp16)
2441 && (disp & ~(offsetT) 0xffff) == 0)
2443 /* If this operand is at most 16 bits, convert
2444 to a signed 16 bit number and don't use 64bit
2446 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2447 i.types[op] &= ~Disp64;
2449 if ((i.types[op] & Disp32)
2450 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2452 /* If this operand is at most 32 bits, convert
2453 to a signed 32 bit number and don't use 64bit
2455 disp &= (((offsetT) 2 << 31) - 1);
2456 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2457 i.types[op] &= ~Disp64;
2459 if (!disp && (i.types[op] & BaseIndex))
2461 i.types[op] &= ~Disp;
2465 else if (flag_code == CODE_64BIT)
2467 if (fits_in_signed_long (disp))
2469 i.types[op] &= ~Disp64;
2470 i.types[op] |= Disp32S;
2472 if (fits_in_unsigned_long (disp))
2473 i.types[op] |= Disp32;
2475 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2476 && fits_in_signed_byte (disp))
2477 i.types[op] |= Disp8;
2479 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2480 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2482 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2483 i.op[op].disps, 0, i.reloc[op]);
2484 i.types[op] &= ~Disp;
2487 /* We only support 64bit displacement on constants. */
2488 i.types[op] &= ~Disp64;
2493 match_template (void)
2495 /* Points to template once we've found it. */
2497 unsigned int overlap0, overlap1, overlap2, overlap3;
2498 unsigned int found_reverse_match;
2500 unsigned int operand_types [MAX_OPERANDS];
2501 int addr_prefix_disp;
2504 #if MAX_OPERANDS != 4
2505 # error "MAX_OPERANDS must be 4."
2508 #define MATCH(overlap, given, template) \
2509 ((overlap & ~JumpAbsolute) \
2510 && (((given) & (BaseIndex | JumpAbsolute)) \
2511 == ((overlap) & (BaseIndex | JumpAbsolute))))
2513 /* If given types r0 and r1 are registers they must be of the same type
2514 unless the expected operand type register overlap is null.
2515 Note that Acc in a template matches every size of reg. */
2516 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2517 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2518 || ((g0) & Reg) == ((g1) & Reg) \
2519 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2525 found_reverse_match = 0;
2526 for (j = 0; j < MAX_OPERANDS; j++)
2527 operand_types [j] = 0;
2528 addr_prefix_disp = -1;
2529 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2531 : (i.suffix == WORD_MNEM_SUFFIX
2533 : (i.suffix == SHORT_MNEM_SUFFIX
2535 : (i.suffix == LONG_MNEM_SUFFIX
2537 : (i.suffix == QWORD_MNEM_SUFFIX
2539 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2540 ? No_xSuf : 0))))));
2542 for (t = current_templates->start; t < current_templates->end; t++)
2544 addr_prefix_disp = -1;
2546 /* Must have right number of operands. */
2547 if (i.operands != t->operands)
2550 /* Check the suffix, except for some instructions in intel mode. */
2551 if ((t->opcode_modifier & suffix_check)
2553 && (t->opcode_modifier & IgnoreSize)))
2556 for (j = 0; j < MAX_OPERANDS; j++)
2557 operand_types [j] = t->operand_types [j];
2559 /* In general, don't allow 64-bit operands in 32-bit mode. */
2560 if (i.suffix == QWORD_MNEM_SUFFIX
2561 && flag_code != CODE_64BIT
2563 ? (!(t->opcode_modifier & IgnoreSize)
2564 && !intel_float_operand (t->name))
2565 : intel_float_operand (t->name) != 2)
2566 && (!(operand_types[0] & (RegMMX | RegXMM))
2567 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2568 && (t->base_opcode != 0x0fc7
2569 || t->extension_opcode != 1 /* cmpxchg8b */))
2572 /* Do not verify operands when there are none. */
2573 else if (!t->operands)
2575 if (t->cpu_flags & ~cpu_arch_flags)
2577 /* We've found a match; break out of loop. */
2581 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2582 into Disp32/Disp16/Disp32 operand. */
2583 if (i.prefix[ADDR_PREFIX] != 0)
2585 unsigned int DispOn = 0, DispOff = 0;
2603 for (j = 0; j < MAX_OPERANDS; j++)
2605 /* There should be only one Disp operand. */
2606 if ((operand_types[j] & DispOff))
2608 addr_prefix_disp = j;
2609 operand_types[j] |= DispOn;
2610 operand_types[j] &= ~DispOff;
2616 overlap0 = i.types[0] & operand_types[0];
2617 switch (t->operands)
2620 if (!MATCH (overlap0, i.types[0], operand_types[0]))
2624 /* xchg %eax, %eax is a special case. It is an aliase for nop
2625 only in 32bit mode and we can use opcode 0x90. In 64bit
2626 mode, we can't use 0x90 for xchg %eax, %eax since it should
2627 zero-extend %eax to %rax. */
2628 if (flag_code == CODE_64BIT
2629 && t->base_opcode == 0x90
2630 && i.types [0] == (Acc | Reg32)
2631 && i.types [1] == (Acc | Reg32))
2635 overlap1 = i.types[1] & operand_types[1];
2636 if (!MATCH (overlap0, i.types[0], operand_types[0])
2637 || !MATCH (overlap1, i.types[1], operand_types[1])
2638 /* monitor in SSE3 is a very special case. The first
2639 register and the second register may have different
2641 || !((t->base_opcode == 0x0f01
2642 && t->extension_opcode == 0xc8)
2643 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2645 overlap1, i.types[1],
2648 /* Check if other direction is valid ... */
2649 if ((t->opcode_modifier & (D | FloatD)) == 0)
2652 /* Try reversing direction of operands. */
2653 overlap0 = i.types[0] & operand_types[1];
2654 overlap1 = i.types[1] & operand_types[0];
2655 if (!MATCH (overlap0, i.types[0], operand_types[1])
2656 || !MATCH (overlap1, i.types[1], operand_types[0])
2657 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2659 overlap1, i.types[1],
2662 /* Does not match either direction. */
2665 /* found_reverse_match holds which of D or FloatDR
2667 if ((t->opcode_modifier & D))
2668 found_reverse_match = Opcode_D;
2669 else if ((t->opcode_modifier & FloatD))
2670 found_reverse_match = Opcode_FloatD;
2672 found_reverse_match = 0;
2673 if ((t->opcode_modifier & FloatR))
2674 found_reverse_match |= Opcode_FloatR;
2678 /* Found a forward 2 operand match here. */
2679 switch (t->operands)
2682 overlap3 = i.types[3] & operand_types[3];
2684 overlap2 = i.types[2] & operand_types[2];
2688 switch (t->operands)
2691 if (!MATCH (overlap3, i.types[3], operand_types[3])
2692 || !CONSISTENT_REGISTER_MATCH (overlap2,
2700 /* Here we make use of the fact that there are no
2701 reverse match 3 operand instructions, and all 3
2702 operand instructions only need to be checked for
2703 register consistency between operands 2 and 3. */
2704 if (!MATCH (overlap2, i.types[2], operand_types[2])
2705 || !CONSISTENT_REGISTER_MATCH (overlap1,
2715 /* Found either forward/reverse 2, 3 or 4 operand match here:
2716 slip through to break. */
2718 if (t->cpu_flags & ~cpu_arch_flags)
2720 found_reverse_match = 0;
2723 /* We've found a match; break out of loop. */
2727 if (t == current_templates->end)
2729 /* We found no match. */
2730 as_bad (_("suffix or operands invalid for `%s'"),
2731 current_templates->start->name);
2735 if (!quiet_warnings)
2738 && ((i.types[0] & JumpAbsolute)
2739 != (operand_types[0] & JumpAbsolute)))
2741 as_warn (_("indirect %s without `*'"), t->name);
2744 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2745 == (IsPrefix | IgnoreSize))
2747 /* Warn them that a data or address size prefix doesn't
2748 affect assembly of the next line of code. */
2749 as_warn (_("stand-alone `%s' prefix"), t->name);
2753 /* Copy the template we found. */
2756 if (addr_prefix_disp != -1)
2757 i.tm.operand_types[addr_prefix_disp]
2758 = operand_types[addr_prefix_disp];
2760 if (found_reverse_match)
2762 /* If we found a reverse match we must alter the opcode
2763 direction bit. found_reverse_match holds bits to change
2764 (different for int & float insns). */
2766 i.tm.base_opcode ^= found_reverse_match;
2768 i.tm.operand_types[0] = operand_types[1];
2769 i.tm.operand_types[1] = operand_types[0];
2778 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2779 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2781 if (i.seg[0] != NULL && i.seg[0] != &es)
2783 as_bad (_("`%s' operand %d must use `%%es' segment"),
2788 /* There's only ever one segment override allowed per instruction.
2789 This instruction possibly has a legal segment override on the
2790 second operand, so copy the segment to where non-string
2791 instructions store it, allowing common code. */
2792 i.seg[0] = i.seg[1];
2794 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2796 if (i.seg[1] != NULL && i.seg[1] != &es)
2798 as_bad (_("`%s' operand %d must use `%%es' segment"),
2808 process_suffix (void)
2810 /* If matched instruction specifies an explicit instruction mnemonic
2812 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2814 if (i.tm.opcode_modifier & Size16)
2815 i.suffix = WORD_MNEM_SUFFIX;
2816 else if (i.tm.opcode_modifier & Size64)
2817 i.suffix = QWORD_MNEM_SUFFIX;
2819 i.suffix = LONG_MNEM_SUFFIX;
2821 else if (i.reg_operands)
2823 /* If there's no instruction mnemonic suffix we try to invent one
2824 based on register operands. */
2827 /* We take i.suffix from the last register operand specified,
2828 Destination register type is more significant than source
2832 for (op = i.operands; --op >= 0;)
2833 if ((i.types[op] & Reg)
2834 && !(i.tm.operand_types[op] & InOutPortReg))
2836 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2837 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2838 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2843 else if (i.suffix == BYTE_MNEM_SUFFIX)
2845 if (!check_byte_reg ())
2848 else if (i.suffix == LONG_MNEM_SUFFIX)
2850 if (!check_long_reg ())
2853 else if (i.suffix == QWORD_MNEM_SUFFIX)
2855 if (!check_qword_reg ())
2858 else if (i.suffix == WORD_MNEM_SUFFIX)
2860 if (!check_word_reg ())
2863 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2864 /* Do nothing if the instruction is going to ignore the prefix. */
2869 else if ((i.tm.opcode_modifier & DefaultSize)
2871 /* exclude fldenv/frstor/fsave/fstenv */
2872 && (i.tm.opcode_modifier & No_sSuf))
2874 i.suffix = stackop_size;
2876 else if (intel_syntax
2878 && ((i.tm.operand_types[0] & JumpAbsolute)
2879 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2880 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2881 && i.tm.extension_opcode <= 3)))
2886 if (!(i.tm.opcode_modifier & No_qSuf))
2888 i.suffix = QWORD_MNEM_SUFFIX;
2892 if (!(i.tm.opcode_modifier & No_lSuf))
2893 i.suffix = LONG_MNEM_SUFFIX;
2896 if (!(i.tm.opcode_modifier & No_wSuf))
2897 i.suffix = WORD_MNEM_SUFFIX;
2906 if (i.tm.opcode_modifier & W)
2908 as_bad (_("no instruction mnemonic suffix given and "
2909 "no register operands; can't size instruction"));
2915 unsigned int suffixes = (~i.tm.opcode_modifier
2923 if ((i.tm.opcode_modifier & W)
2924 || ((suffixes & (suffixes - 1))
2925 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2927 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2933 /* Change the opcode based on the operand size given by i.suffix;
2934 We don't need to change things for byte insns. */
2936 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2938 /* It's not a byte, select word/dword operation. */
2939 if (i.tm.opcode_modifier & W)
2941 if (i.tm.opcode_modifier & ShortForm)
2942 i.tm.base_opcode |= 8;
2944 i.tm.base_opcode |= 1;
2947 /* Now select between word & dword operations via the operand
2948 size prefix, except for instructions that will ignore this
2950 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2952 /* monitor in SSE3 is a very special case. The default size
2953 of AX is the size of mode. The address size override
2954 prefix will change the size of AX. */
2955 if (i.op->regs[0].reg_type &
2956 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2957 if (!add_prefix (ADDR_PREFIX_OPCODE))
2960 else if (i.suffix != QWORD_MNEM_SUFFIX
2961 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2962 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2963 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2964 || (flag_code == CODE_64BIT
2965 && (i.tm.opcode_modifier & JumpByte))))
2967 unsigned int prefix = DATA_PREFIX_OPCODE;
2969 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2970 prefix = ADDR_PREFIX_OPCODE;
2972 if (!add_prefix (prefix))
2976 /* Set mode64 for an operand. */
2977 if (i.suffix == QWORD_MNEM_SUFFIX
2978 && flag_code == CODE_64BIT
2979 && (i.tm.opcode_modifier & NoRex64) == 0)
2981 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2984 || i.types [0] != (Acc | Reg64)
2985 || i.types [1] != (Acc | Reg64)
2986 || i.tm.base_opcode != 0x90)
2990 /* Size floating point instruction. */
2991 if (i.suffix == LONG_MNEM_SUFFIX)
2992 if (i.tm.opcode_modifier & FloatMF)
2993 i.tm.base_opcode ^= 4;
3000 check_byte_reg (void)
3004 for (op = i.operands; --op >= 0;)
3006 /* If this is an eight bit register, it's OK. If it's the 16 or
3007 32 bit version of an eight bit register, we will just use the
3008 low portion, and that's OK too. */
3009 if (i.types[op] & Reg8)
3012 /* movzx and movsx should not generate this warning. */
3014 && (i.tm.base_opcode == 0xfb7
3015 || i.tm.base_opcode == 0xfb6
3016 || i.tm.base_opcode == 0x63
3017 || i.tm.base_opcode == 0xfbe
3018 || i.tm.base_opcode == 0xfbf))
3021 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
3023 /* Prohibit these changes in the 64bit mode, since the
3024 lowering is more complicated. */
3025 if (flag_code == CODE_64BIT
3026 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3028 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3029 register_prefix, i.op[op].regs->reg_name,
3033 #if REGISTER_WARNINGS
3035 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3036 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3037 (i.op[op].regs + (i.types[op] & Reg16
3038 ? REGNAM_AL - REGNAM_AX
3039 : REGNAM_AL - REGNAM_EAX))->reg_name,
3040 i.op[op].regs->reg_name,
3045 /* Any other register is bad. */
3046 if (i.types[op] & (Reg | RegMMX | RegXMM
3048 | Control | Debug | Test
3049 | FloatReg | FloatAcc))
3051 as_bad (_("`%%%s' not allowed with `%s%c'"),
3052 i.op[op].regs->reg_name,
3062 check_long_reg (void)
3066 for (op = i.operands; --op >= 0;)
3067 /* Reject eight bit registers, except where the template requires
3068 them. (eg. movzb) */
3069 if ((i.types[op] & Reg8) != 0
3070 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3072 as_bad (_("`%%%s' not allowed with `%s%c'"),
3073 i.op[op].regs->reg_name,
3078 /* Warn if the e prefix on a general reg is missing. */
3079 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3080 && (i.types[op] & Reg16) != 0
3081 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3083 /* Prohibit these changes in the 64bit mode, since the
3084 lowering is more complicated. */
3085 if (flag_code == CODE_64BIT)
3087 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3088 register_prefix, i.op[op].regs->reg_name,
3092 #if REGISTER_WARNINGS
3094 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3095 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3096 i.op[op].regs->reg_name,
3100 /* Warn if the r prefix on a general reg is missing. */
3101 else if ((i.types[op] & Reg64) != 0
3102 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3104 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3105 register_prefix, i.op[op].regs->reg_name,
3113 check_qword_reg (void)
3117 for (op = i.operands; --op >= 0; )
3118 /* Reject eight bit registers, except where the template requires
3119 them. (eg. movzb) */
3120 if ((i.types[op] & Reg8) != 0
3121 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3123 as_bad (_("`%%%s' not allowed with `%s%c'"),
3124 i.op[op].regs->reg_name,
3129 /* Warn if the e prefix on a general reg is missing. */
3130 else if (((i.types[op] & Reg16) != 0
3131 || (i.types[op] & Reg32) != 0)
3132 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3134 /* Prohibit these changes in the 64bit mode, since the
3135 lowering is more complicated. */
3136 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3137 register_prefix, i.op[op].regs->reg_name,
3145 check_word_reg (void)
3148 for (op = i.operands; --op >= 0;)
3149 /* Reject eight bit registers, except where the template requires
3150 them. (eg. movzb) */
3151 if ((i.types[op] & Reg8) != 0
3152 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3154 as_bad (_("`%%%s' not allowed with `%s%c'"),
3155 i.op[op].regs->reg_name,
3160 /* Warn if the e prefix on a general reg is present. */
3161 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3162 && (i.types[op] & Reg32) != 0
3163 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3165 /* Prohibit these changes in the 64bit mode, since the
3166 lowering is more complicated. */
3167 if (flag_code == CODE_64BIT)
3169 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3170 register_prefix, i.op[op].regs->reg_name,
3175 #if REGISTER_WARNINGS
3176 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3177 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3178 i.op[op].regs->reg_name,
3188 unsigned int overlap0, overlap1, overlap2;
3190 overlap0 = i.types[0] & i.tm.operand_types[0];
3191 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3192 && overlap0 != Imm8 && overlap0 != Imm8S
3193 && overlap0 != Imm16 && overlap0 != Imm32S
3194 && overlap0 != Imm32 && overlap0 != Imm64)
3198 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3200 : (i.suffix == WORD_MNEM_SUFFIX
3202 : (i.suffix == QWORD_MNEM_SUFFIX
3206 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3207 || overlap0 == (Imm16 | Imm32)
3208 || overlap0 == (Imm16 | Imm32S))
3210 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3213 if (overlap0 != Imm8 && overlap0 != Imm8S
3214 && overlap0 != Imm16 && overlap0 != Imm32S
3215 && overlap0 != Imm32 && overlap0 != Imm64)
3217 as_bad (_("no instruction mnemonic suffix given; "
3218 "can't determine immediate size"));
3222 i.types[0] = overlap0;
3224 overlap1 = i.types[1] & i.tm.operand_types[1];
3225 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3226 && overlap1 != Imm8 && overlap1 != Imm8S
3227 && overlap1 != Imm16 && overlap1 != Imm32S
3228 && overlap1 != Imm32 && overlap1 != Imm64)
3232 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3234 : (i.suffix == WORD_MNEM_SUFFIX
3236 : (i.suffix == QWORD_MNEM_SUFFIX
3240 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3241 || overlap1 == (Imm16 | Imm32)
3242 || overlap1 == (Imm16 | Imm32S))
3244 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3247 if (overlap1 != Imm8 && overlap1 != Imm8S
3248 && overlap1 != Imm16 && overlap1 != Imm32S
3249 && overlap1 != Imm32 && overlap1 != Imm64)
3251 as_bad (_("no instruction mnemonic suffix given; "
3252 "can't determine immediate size %x %c"),
3253 overlap1, i.suffix);
3257 i.types[1] = overlap1;
3259 overlap2 = i.types[2] & i.tm.operand_types[2];
3260 assert ((overlap2 & Imm) == 0);
3261 i.types[2] = overlap2;
3267 process_operands (void)
3269 /* Default segment register this instruction will use for memory
3270 accesses. 0 means unknown. This is only for optimizing out
3271 unnecessary segment overrides. */
3272 const seg_entry *default_seg = 0;
3274 /* The imul $imm, %reg instruction is converted into
3275 imul $imm, %reg, %reg, and the clr %reg instruction
3276 is converted into xor %reg, %reg. */
3277 if (i.tm.opcode_modifier & regKludge)
3279 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3280 /* Pretend we saw the extra register operand. */
3281 assert (i.reg_operands == 1
3282 && i.op[first_reg_op + 1].regs == 0);
3283 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3284 i.types[first_reg_op + 1] = i.types[first_reg_op];
3289 if (i.tm.opcode_modifier & ShortForm)
3291 if (i.types[0] & (SReg2 | SReg3))
3293 if (i.tm.base_opcode == POP_SEG_SHORT
3294 && i.op[0].regs->reg_num == 1)
3296 as_bad (_("you can't `pop %%cs'"));
3299 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3300 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3305 /* The register or float register operand is in operand 0 or 1. */
3306 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3307 /* Register goes in low 3 bits of opcode. */
3308 i.tm.base_opcode |= i.op[op].regs->reg_num;
3309 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3311 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3313 /* Warn about some common errors, but press on regardless.
3314 The first case can be generated by gcc (<= 2.8.1). */
3315 if (i.operands == 2)
3317 /* Reversed arguments on faddp, fsubp, etc. */
3318 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3319 i.op[1].regs->reg_name,
3320 i.op[0].regs->reg_name);
3324 /* Extraneous `l' suffix on fp insn. */
3325 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3326 i.op[0].regs->reg_name);
3331 else if (i.tm.opcode_modifier & Modrm)
3333 /* The opcode is completed (modulo i.tm.extension_opcode which
3334 must be put into the modrm byte). Now, we make the modrm and
3335 index base bytes based on all the info we've collected. */
3337 default_seg = build_modrm_byte ();
3339 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
3343 else if ((i.tm.opcode_modifier & IsString) != 0)
3345 /* For the string instructions that allow a segment override
3346 on one of their operands, the default segment is ds. */
3350 if ((i.tm.base_opcode == 0x8d /* lea */
3351 || (i.tm.cpu_flags & CpuSVME))
3352 && i.seg[0] && !quiet_warnings)
3353 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3355 /* If a segment was explicitly specified, and the specified segment
3356 is not the default, use an opcode prefix to select it. If we
3357 never figured out what the default segment is, then default_seg
3358 will be zero at this point, and the specified segment prefix will
3360 if ((i.seg[0]) && (i.seg[0] != default_seg))
3362 if (!add_prefix (i.seg[0]->seg_prefix))
3368 static const seg_entry *
3369 build_modrm_byte (void)
3371 const seg_entry *default_seg = 0;
3373 /* i.reg_operands MUST be the number of real register operands;
3374 implicit registers do not count. */
3375 if (i.reg_operands == 2)
3377 unsigned int source, dest;
3385 /* When there are 3 operands, one of them may be immediate,
3386 which may be the first or the last operand. Otherwise,
3387 the first operand must be shift count register (cl). */
3388 assert (i.imm_operands == 1
3389 || (i.imm_operands == 0
3390 && (i.types[0] & ShiftCount)));
3391 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
3394 /* When there are 4 operands, the first two must be immediate
3395 operands. The source operand will be the 3rd one. */
3396 assert (i.imm_operands == 2
3397 && (i.types[0] & Imm)
3398 && (i.types[1] & Imm));
3408 /* One of the register operands will be encoded in the i.tm.reg
3409 field, the other in the combined i.tm.mode and i.tm.regmem
3410 fields. If no form of this instruction supports a memory
3411 destination operand, then we assume the source operand may
3412 sometimes be a memory operand and so we need to store the
3413 destination in the i.rm.reg field. */
3414 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3416 i.rm.reg = i.op[dest].regs->reg_num;
3417 i.rm.regmem = i.op[source].regs->reg_num;
3418 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3420 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3425 i.rm.reg = i.op[source].regs->reg_num;
3426 i.rm.regmem = i.op[dest].regs->reg_num;
3427 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3429 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3432 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
3434 if (!((i.types[0] | i.types[1]) & Control))
3436 i.rex &= ~(REX_R | REX_B);
3437 add_prefix (LOCK_PREFIX_OPCODE);
3441 { /* If it's not 2 reg operands... */
3444 unsigned int fake_zero_displacement = 0;
3447 for (op = 0; op < i.operands; op++)
3448 if ((i.types[op] & AnyMem))
3450 assert (op < i.operands);
3454 if (i.base_reg == 0)
3457 if (!i.disp_operands)
3458 fake_zero_displacement = 1;
3459 if (i.index_reg == 0)
3461 /* Operand is just <disp> */
3462 if (flag_code == CODE_64BIT)
3464 /* 64bit mode overwrites the 32bit absolute
3465 addressing by RIP relative addressing and
3466 absolute addressing is encoded by one of the
3467 redundant SIB forms. */
3468 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3469 i.sib.base = NO_BASE_REGISTER;
3470 i.sib.index = NO_INDEX_REGISTER;
3471 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3472 ? Disp32S : Disp32);
3474 else if ((flag_code == CODE_16BIT)
3475 ^ (i.prefix[ADDR_PREFIX] != 0))
3477 i.rm.regmem = NO_BASE_REGISTER_16;
3478 i.types[op] = Disp16;
3482 i.rm.regmem = NO_BASE_REGISTER;
3483 i.types[op] = Disp32;
3486 else /* !i.base_reg && i.index_reg */
3488 i.sib.index = i.index_reg->reg_num;
3489 i.sib.base = NO_BASE_REGISTER;
3490 i.sib.scale = i.log2_scale_factor;
3491 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3492 i.types[op] &= ~Disp;
3493 if (flag_code != CODE_64BIT)
3494 i.types[op] |= Disp32; /* Must be 32 bit */
3496 i.types[op] |= Disp32S;
3497 if ((i.index_reg->reg_flags & RegRex) != 0)
3501 /* RIP addressing for 64bit mode. */
3502 else if (i.base_reg->reg_type == BaseIndex)
3504 i.rm.regmem = NO_BASE_REGISTER;
3505 i.types[op] &= ~ Disp;
3506 i.types[op] |= Disp32S;
3507 i.flags[op] |= Operand_PCrel;
3508 if (! i.disp_operands)
3509 fake_zero_displacement = 1;
3511 else if (i.base_reg->reg_type & Reg16)
3513 switch (i.base_reg->reg_num)
3516 if (i.index_reg == 0)
3518 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3519 i.rm.regmem = i.index_reg->reg_num - 6;
3523 if (i.index_reg == 0)
3526 if ((i.types[op] & Disp) == 0)
3528 /* fake (%bp) into 0(%bp) */
3529 i.types[op] |= Disp8;
3530 fake_zero_displacement = 1;
3533 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3534 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3536 default: /* (%si) -> 4 or (%di) -> 5 */
3537 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3539 i.rm.mode = mode_from_disp_size (i.types[op]);
3541 else /* i.base_reg and 32/64 bit mode */
3543 if (flag_code == CODE_64BIT
3544 && (i.types[op] & Disp))
3545 i.types[op] = ((i.types[op] & Disp8)
3546 | (i.prefix[ADDR_PREFIX] == 0
3547 ? Disp32S : Disp32));
3549 i.rm.regmem = i.base_reg->reg_num;
3550 if ((i.base_reg->reg_flags & RegRex) != 0)
3552 i.sib.base = i.base_reg->reg_num;
3553 /* x86-64 ignores REX prefix bit here to avoid decoder
3555 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3558 if (i.disp_operands == 0)
3560 fake_zero_displacement = 1;
3561 i.types[op] |= Disp8;
3564 else if (i.base_reg->reg_num == ESP_REG_NUM)
3568 i.sib.scale = i.log2_scale_factor;
3569 if (i.index_reg == 0)
3571 /* <disp>(%esp) becomes two byte modrm with no index
3572 register. We've already stored the code for esp
3573 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3574 Any base register besides %esp will not use the
3575 extra modrm byte. */
3576 i.sib.index = NO_INDEX_REGISTER;
3577 #if !SCALE1_WHEN_NO_INDEX
3578 /* Another case where we force the second modrm byte. */
3579 if (i.log2_scale_factor)
3580 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3585 i.sib.index = i.index_reg->reg_num;
3586 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3587 if ((i.index_reg->reg_flags & RegRex) != 0)
3592 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3593 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3596 i.rm.mode = mode_from_disp_size (i.types[op]);
3599 if (fake_zero_displacement)
3601 /* Fakes a zero displacement assuming that i.types[op]
3602 holds the correct displacement size. */
3605 assert (i.op[op].disps == 0);
3606 exp = &disp_expressions[i.disp_operands++];
3607 i.op[op].disps = exp;
3608 exp->X_op = O_constant;
3609 exp->X_add_number = 0;
3610 exp->X_add_symbol = (symbolS *) 0;
3611 exp->X_op_symbol = (symbolS *) 0;
3615 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3616 (if any) based on i.tm.extension_opcode. Again, we must be
3617 careful to make sure that segment/control/debug/test/MMX
3618 registers are coded into the i.rm.reg field. */
3623 for (op = 0; op < i.operands; op++)
3624 if ((i.types[op] & (Reg | RegMMX | RegXMM
3626 | Control | Debug | Test)))
3628 assert (op < i.operands);
3630 /* If there is an extension opcode to put here, the register
3631 number must be put into the regmem field. */
3632 if (i.tm.extension_opcode != None)
3634 i.rm.regmem = i.op[op].regs->reg_num;
3635 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3640 i.rm.reg = i.op[op].regs->reg_num;
3641 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3645 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3646 must set it to 3 to indicate this is a register operand
3647 in the regmem field. */
3648 if (!i.mem_operands)
3652 /* Fill in i.rm.reg field with extension opcode (if any). */
3653 if (i.tm.extension_opcode != None)
3654 i.rm.reg = i.tm.extension_opcode;
3660 output_branch (void)
3665 relax_substateT subtype;
3670 if (flag_code == CODE_16BIT)
3674 if (i.prefix[DATA_PREFIX] != 0)
3680 /* Pentium4 branch hints. */
3681 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3682 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3687 if (i.prefix[REX_PREFIX] != 0)
3693 if (i.prefixes != 0 && !intel_syntax)
3694 as_warn (_("skipping prefixes on this instruction"));
3696 /* It's always a symbol; End frag & setup for relax.
3697 Make sure there is enough room in this frag for the largest
3698 instruction we may generate in md_convert_frag. This is 2
3699 bytes for the opcode and room for the prefix and largest
3701 frag_grow (prefix + 2 + 4);
3702 /* Prefix and 1 opcode byte go in fr_fix. */
3703 p = frag_more (prefix + 1);
3704 if (i.prefix[DATA_PREFIX] != 0)
3705 *p++ = DATA_PREFIX_OPCODE;
3706 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3707 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3708 *p++ = i.prefix[SEG_PREFIX];
3709 if (i.prefix[REX_PREFIX] != 0)
3710 *p++ = i.prefix[REX_PREFIX];
3711 *p = i.tm.base_opcode;
3713 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3714 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3715 else if ((cpu_arch_flags & Cpu386) != 0)
3716 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3718 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3721 sym = i.op[0].disps->X_add_symbol;
3722 off = i.op[0].disps->X_add_number;
3724 if (i.op[0].disps->X_op != O_constant
3725 && i.op[0].disps->X_op != O_symbol)
3727 /* Handle complex expressions. */
3728 sym = make_expr_symbol (i.op[0].disps);
3732 /* 1 possible extra opcode + 4 byte displacement go in var part.
3733 Pass reloc in fr_var. */
3734 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3744 if (i.tm.opcode_modifier & JumpByte)
3746 /* This is a loop or jecxz type instruction. */
3748 if (i.prefix[ADDR_PREFIX] != 0)
3750 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3753 /* Pentium4 branch hints. */
3754 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3755 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3757 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3766 if (flag_code == CODE_16BIT)
3769 if (i.prefix[DATA_PREFIX] != 0)
3771 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3781 if (i.prefix[REX_PREFIX] != 0)
3783 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3787 if (i.prefixes != 0 && !intel_syntax)
3788 as_warn (_("skipping prefixes on this instruction"));
3790 p = frag_more (1 + size);
3791 *p++ = i.tm.base_opcode;
3793 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3794 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3796 /* All jumps handled here are signed, but don't use a signed limit
3797 check for 32 and 16 bit jumps as we want to allow wrap around at
3798 4G and 64k respectively. */
3800 fixP->fx_signed = 1;
3804 output_interseg_jump (void)
3812 if (flag_code == CODE_16BIT)
3816 if (i.prefix[DATA_PREFIX] != 0)
3822 if (i.prefix[REX_PREFIX] != 0)
3832 if (i.prefixes != 0 && !intel_syntax)
3833 as_warn (_("skipping prefixes on this instruction"));
3835 /* 1 opcode; 2 segment; offset */
3836 p = frag_more (prefix + 1 + 2 + size);
3838 if (i.prefix[DATA_PREFIX] != 0)
3839 *p++ = DATA_PREFIX_OPCODE;
3841 if (i.prefix[REX_PREFIX] != 0)
3842 *p++ = i.prefix[REX_PREFIX];
3844 *p++ = i.tm.base_opcode;
3845 if (i.op[1].imms->X_op == O_constant)
3847 offsetT n = i.op[1].imms->X_add_number;
3850 && !fits_in_unsigned_word (n)
3851 && !fits_in_signed_word (n))
3853 as_bad (_("16-bit jump out of range"));
3856 md_number_to_chars (p, n, size);
3859 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3860 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3861 if (i.op[0].imms->X_op != O_constant)
3862 as_bad (_("can't handle non absolute segment in `%s'"),
3864 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3870 fragS *insn_start_frag;
3871 offsetT insn_start_off;
3873 /* Tie dwarf2 debug info to the address at the start of the insn.
3874 We can't do this after the insn has been output as the current
3875 frag may have been closed off. eg. by frag_var. */
3876 dwarf2_emit_insn (0);
3878 insn_start_frag = frag_now;
3879 insn_start_off = frag_now_fix ();
3882 if (i.tm.opcode_modifier & Jump)
3884 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3886 else if (i.tm.opcode_modifier & JumpInterSegment)
3887 output_interseg_jump ();
3890 /* Output normal instructions here. */
3893 unsigned int prefix;
3895 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3896 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3897 use one more higher byte to specify a prefix the instruction
3899 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3901 if (i.tm.base_opcode & 0xff000000)
3903 prefix = (i.tm.base_opcode >> 24) & 0xff;
3907 else if ((i.tm.base_opcode & 0xff0000) != 0)
3909 prefix = (i.tm.base_opcode >> 16) & 0xff;
3910 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3913 if (prefix != REPE_PREFIX_OPCODE
3914 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3915 add_prefix (prefix);
3918 add_prefix (prefix);
3921 /* The prefix bytes. */
3923 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3929 md_number_to_chars (p, (valueT) *q, 1);
3933 /* Now the opcode; be careful about word order here! */
3934 if (fits_in_unsigned_byte (i.tm.base_opcode))
3936 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3940 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3943 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3948 /* Put out high byte first: can't use md_number_to_chars! */
3949 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3950 *p = i.tm.base_opcode & 0xff;
3953 /* Now the modrm byte and sib byte (if present). */
3954 if (i.tm.opcode_modifier & Modrm)
3957 md_number_to_chars (p,
3958 (valueT) (i.rm.regmem << 0
3962 /* If i.rm.regmem == ESP (4)
3963 && i.rm.mode != (Register mode)
3965 ==> need second modrm byte. */
3966 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3968 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3971 md_number_to_chars (p,
3972 (valueT) (i.sib.base << 0
3974 | i.sib.scale << 6),
3979 if (i.disp_operands)
3980 output_disp (insn_start_frag, insn_start_off);
3983 output_imm (insn_start_frag, insn_start_off);
3989 pi ("" /*line*/, &i);
3991 #endif /* DEBUG386 */
3995 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
4000 for (n = 0; n < i.operands; n++)
4002 if (i.types[n] & Disp)
4004 if (i.op[n].disps->X_op == O_constant)
4010 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4013 if (i.types[n] & Disp8)
4015 if (i.types[n] & Disp64)
4018 val = offset_in_range (i.op[n].disps->X_add_number,
4020 p = frag_more (size);
4021 md_number_to_chars (p, val, size);
4025 enum bfd_reloc_code_real reloc_type;
4028 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4030 /* The PC relative address is computed relative
4031 to the instruction boundary, so in case immediate
4032 fields follows, we need to adjust the value. */
4033 if (pcrel && i.imm_operands)
4038 for (n1 = 0; n1 < i.operands; n1++)
4039 if (i.types[n1] & Imm)
4041 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
4044 if (i.types[n1] & (Imm8 | Imm8S))
4046 if (i.types[n1] & Imm64)
4051 /* We should find the immediate. */
4052 if (n1 == i.operands)
4054 i.op[n].disps->X_add_number -= imm_size;
4057 if (i.types[n] & Disp32S)
4060 if (i.types[n] & (Disp16 | Disp64))
4063 if (i.types[n] & Disp64)
4067 p = frag_more (size);
4068 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4070 && GOT_symbol == i.op[n].disps->X_add_symbol
4071 && (((reloc_type == BFD_RELOC_32
4072 || reloc_type == BFD_RELOC_X86_64_32S
4073 || (reloc_type == BFD_RELOC_64
4075 && (i.op[n].disps->X_op == O_symbol
4076 || (i.op[n].disps->X_op == O_add
4077 && ((symbol_get_value_expression
4078 (i.op[n].disps->X_op_symbol)->X_op)
4080 || reloc_type == BFD_RELOC_32_PCREL))
4084 if (insn_start_frag == frag_now)
4085 add = (p - frag_now->fr_literal) - insn_start_off;
4090 add = insn_start_frag->fr_fix - insn_start_off;
4091 for (fr = insn_start_frag->fr_next;
4092 fr && fr != frag_now; fr = fr->fr_next)
4094 add += p - frag_now->fr_literal;
4099 reloc_type = BFD_RELOC_386_GOTPC;
4100 i.op[n].imms->X_add_number += add;
4102 else if (reloc_type == BFD_RELOC_64)
4103 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4105 /* Don't do the adjustment for x86-64, as there
4106 the pcrel addressing is relative to the _next_
4107 insn, and that is taken care of in other code. */
4108 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4110 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4111 i.op[n].disps, pcrel, reloc_type);
4118 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4123 for (n = 0; n < i.operands; n++)
4125 if (i.types[n] & Imm)
4127 if (i.op[n].imms->X_op == O_constant)
4133 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4136 if (i.types[n] & (Imm8 | Imm8S))
4138 else if (i.types[n] & Imm64)
4141 val = offset_in_range (i.op[n].imms->X_add_number,
4143 p = frag_more (size);
4144 md_number_to_chars (p, val, size);
4148 /* Not absolute_section.
4149 Need a 32-bit fixup (don't support 8bit
4150 non-absolute imms). Try to support other
4152 enum bfd_reloc_code_real reloc_type;
4156 if ((i.types[n] & (Imm32S))
4157 && (i.suffix == QWORD_MNEM_SUFFIX
4158 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4160 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4163 if (i.types[n] & (Imm8 | Imm8S))
4165 if (i.types[n] & Imm64)
4169 p = frag_more (size);
4170 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4172 /* This is tough to explain. We end up with this one if we
4173 * have operands that look like
4174 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4175 * obtain the absolute address of the GOT, and it is strongly
4176 * preferable from a performance point of view to avoid using
4177 * a runtime relocation for this. The actual sequence of
4178 * instructions often look something like:
4183 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4185 * The call and pop essentially return the absolute address
4186 * of the label .L66 and store it in %ebx. The linker itself
4187 * will ultimately change the first operand of the addl so
4188 * that %ebx points to the GOT, but to keep things simple, the
4189 * .o file must have this operand set so that it generates not
4190 * the absolute address of .L66, but the absolute address of
4191 * itself. This allows the linker itself simply treat a GOTPC
4192 * relocation as asking for a pcrel offset to the GOT to be
4193 * added in, and the addend of the relocation is stored in the
4194 * operand field for the instruction itself.
4196 * Our job here is to fix the operand so that it would add
4197 * the correct offset so that %ebx would point to itself. The
4198 * thing that is tricky is that .-.L66 will point to the
4199 * beginning of the instruction, so we need to further modify
4200 * the operand so that it will point to itself. There are
4201 * other cases where you have something like:
4203 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4205 * and here no correction would be required. Internally in
4206 * the assembler we treat operands of this form as not being
4207 * pcrel since the '.' is explicitly mentioned, and I wonder
4208 * whether it would simplify matters to do it this way. Who
4209 * knows. In earlier versions of the PIC patches, the
4210 * pcrel_adjust field was used to store the correction, but
4211 * since the expression is not pcrel, I felt it would be
4212 * confusing to do it this way. */
4214 if ((reloc_type == BFD_RELOC_32
4215 || reloc_type == BFD_RELOC_X86_64_32S
4216 || reloc_type == BFD_RELOC_64)
4218 && GOT_symbol == i.op[n].imms->X_add_symbol
4219 && (i.op[n].imms->X_op == O_symbol
4220 || (i.op[n].imms->X_op == O_add
4221 && ((symbol_get_value_expression
4222 (i.op[n].imms->X_op_symbol)->X_op)
4227 if (insn_start_frag == frag_now)
4228 add = (p - frag_now->fr_literal) - insn_start_off;
4233 add = insn_start_frag->fr_fix - insn_start_off;
4234 for (fr = insn_start_frag->fr_next;
4235 fr && fr != frag_now; fr = fr->fr_next)
4237 add += p - frag_now->fr_literal;
4241 reloc_type = BFD_RELOC_386_GOTPC;
4243 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4245 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4246 i.op[n].imms->X_add_number += add;
4248 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4249 i.op[n].imms, 0, reloc_type);
4255 /* x86_cons_fix_new is called via the expression parsing code when a
4256 reloc is needed. We use this hook to get the correct .got reloc. */
4257 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4258 static int cons_sign = -1;
4261 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
4264 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4266 got_reloc = NO_RELOC;
4269 if (exp->X_op == O_secrel)
4271 exp->X_op = O_symbol;
4272 r = BFD_RELOC_32_SECREL;
4276 fix_new_exp (frag, off, len, exp, 0, r);
4279 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4280 # define lex_got(reloc, adjust, types) NULL
4282 /* Parse operands of the form
4283 <symbol>@GOTOFF+<nnn>
4284 and similar .plt or .got references.
4286 If we find one, set up the correct relocation in RELOC and copy the
4287 input string, minus the `@GOTOFF' into a malloc'd buffer for
4288 parsing by the calling routine. Return this buffer, and if ADJUST
4289 is non-null set it to the length of the string we removed from the
4290 input line. Otherwise return NULL. */
4292 lex_got (enum bfd_reloc_code_real *reloc,
4294 unsigned int *types)
4296 /* Some of the relocations depend on the size of what field is to
4297 be relocated. But in our callers i386_immediate and i386_displacement
4298 we don't yet know the operand size (this will be set by insn
4299 matching). Hence we record the word32 relocation here,
4300 and adjust the reloc according to the real size in reloc(). */
4301 static const struct {
4303 const enum bfd_reloc_code_real rel[2];
4304 const unsigned int types64;
4307 BFD_RELOC_X86_64_PLTOFF64 },
4309 { "PLT", { BFD_RELOC_386_PLT32,
4310 BFD_RELOC_X86_64_PLT32 },
4311 Imm32 | Imm32S | Disp32 },
4313 BFD_RELOC_X86_64_GOTPLT64 },
4315 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4316 BFD_RELOC_X86_64_GOTOFF64 },
4319 BFD_RELOC_X86_64_GOTPCREL },
4320 Imm32 | Imm32S | Disp32 },
4321 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4322 BFD_RELOC_X86_64_TLSGD },
4323 Imm32 | Imm32S | Disp32 },
4324 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4328 BFD_RELOC_X86_64_TLSLD },
4329 Imm32 | Imm32S | Disp32 },
4330 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4331 BFD_RELOC_X86_64_GOTTPOFF },
4332 Imm32 | Imm32S | Disp32 },
4333 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4334 BFD_RELOC_X86_64_TPOFF32 },
4335 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4336 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4339 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4340 BFD_RELOC_X86_64_DTPOFF32 },
4341 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4342 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4345 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4348 { "GOT", { BFD_RELOC_386_GOT32,
4349 BFD_RELOC_X86_64_GOT32 },
4350 Imm32 | Imm32S | Disp32 | Imm64 },
4351 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4352 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4353 Imm32 | Imm32S | Disp32 },
4354 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4355 BFD_RELOC_X86_64_TLSDESC_CALL },
4356 Imm32 | Imm32S | Disp32 }
4364 for (cp = input_line_pointer; *cp != '@'; cp++)
4365 if (is_end_of_line[(unsigned char) *cp])
4368 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4372 len = strlen (gotrel[j].str);
4373 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4375 if (gotrel[j].rel[object_64bit] != 0)
4378 char *tmpbuf, *past_reloc;
4380 *reloc = gotrel[j].rel[object_64bit];
4386 if (flag_code != CODE_64BIT)
4387 *types = Imm32 | Disp32;
4389 *types = gotrel[j].types64;
4392 if (GOT_symbol == NULL)
4393 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4395 /* Replace the relocation token with ' ', so that
4396 errors like foo@GOTOFF1 will be detected. */
4398 /* The length of the first part of our input line. */
4399 first = cp - input_line_pointer;
4401 /* The second part goes from after the reloc token until
4402 (and including) an end_of_line char. Don't use strlen
4403 here as the end_of_line char may not be a NUL. */
4404 past_reloc = cp + 1 + len;
4405 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4407 second = cp - past_reloc;
4409 /* Allocate and copy string. The trailing NUL shouldn't
4410 be necessary, but be safe. */
4411 tmpbuf = xmalloc (first + second + 2);
4412 memcpy (tmpbuf, input_line_pointer, first);
4413 tmpbuf[first] = ' ';
4414 memcpy (tmpbuf + first + 1, past_reloc, second);
4415 tmpbuf[first + second + 1] = '\0';
4419 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4420 gotrel[j].str, 1 << (5 + object_64bit));
4425 /* Might be a symbol version string. Don't as_bad here. */
4430 x86_cons (expressionS *exp, int size)
4432 if (size == 4 || (object_64bit && size == 8))
4434 /* Handle @GOTOFF and the like in an expression. */
4436 char *gotfree_input_line;
4439 save = input_line_pointer;
4440 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4441 if (gotfree_input_line)
4442 input_line_pointer = gotfree_input_line;
4446 if (gotfree_input_line)
4448 /* expression () has merrily parsed up to the end of line,
4449 or a comma - in the wrong buffer. Transfer how far
4450 input_line_pointer has moved to the right buffer. */
4451 input_line_pointer = (save
4452 + (input_line_pointer - gotfree_input_line)
4454 free (gotfree_input_line);
4462 static void signed_cons (int size)
4464 if (flag_code == CODE_64BIT)
4472 pe_directive_secrel (dummy)
4473 int dummy ATTRIBUTE_UNUSED;
4480 if (exp.X_op == O_symbol)
4481 exp.X_op = O_secrel;
4483 emit_expr (&exp, 4);
4485 while (*input_line_pointer++ == ',');
4487 input_line_pointer--;
4488 demand_empty_rest_of_line ();
4493 i386_immediate (char *imm_start)
4495 char *save_input_line_pointer;
4496 char *gotfree_input_line;
4499 unsigned int types = ~0U;
4501 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4503 as_bad (_("at most %d immediate operands are allowed"),
4504 MAX_IMMEDIATE_OPERANDS);
4508 exp = &im_expressions[i.imm_operands++];
4509 i.op[this_operand].imms = exp;
4511 if (is_space_char (*imm_start))
4514 save_input_line_pointer = input_line_pointer;
4515 input_line_pointer = imm_start;
4517 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4518 if (gotfree_input_line)
4519 input_line_pointer = gotfree_input_line;
4521 exp_seg = expression (exp);
4524 if (*input_line_pointer)
4525 as_bad (_("junk `%s' after expression"), input_line_pointer);
4527 input_line_pointer = save_input_line_pointer;
4528 if (gotfree_input_line)
4529 free (gotfree_input_line);
4531 if (exp->X_op == O_absent || exp->X_op == O_big)
4533 /* Missing or bad expr becomes absolute 0. */
4534 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4536 exp->X_op = O_constant;
4537 exp->X_add_number = 0;
4538 exp->X_add_symbol = (symbolS *) 0;
4539 exp->X_op_symbol = (symbolS *) 0;
4541 else if (exp->X_op == O_constant)
4543 /* Size it properly later. */
4544 i.types[this_operand] |= Imm64;
4545 /* If BFD64, sign extend val. */
4546 if (!use_rela_relocations
4547 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4549 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4551 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4552 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4553 && exp_seg != absolute_section
4554 && exp_seg != text_section
4555 && exp_seg != data_section
4556 && exp_seg != bss_section
4557 && exp_seg != undefined_section
4558 && !bfd_is_com_section (exp_seg))
4560 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4564 else if (!intel_syntax && exp->X_op == O_register)
4566 as_bad (_("illegal immediate register operand %s"), imm_start);
4571 /* This is an address. The size of the address will be
4572 determined later, depending on destination register,
4573 suffix, or the default for the section. */
4574 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4575 i.types[this_operand] &= types;
4582 i386_scale (char *scale)
4585 char *save = input_line_pointer;
4587 input_line_pointer = scale;
4588 val = get_absolute_expression ();
4593 i.log2_scale_factor = 0;
4596 i.log2_scale_factor = 1;
4599 i.log2_scale_factor = 2;
4602 i.log2_scale_factor = 3;
4606 char sep = *input_line_pointer;
4608 *input_line_pointer = '\0';
4609 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4611 *input_line_pointer = sep;
4612 input_line_pointer = save;
4616 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4618 as_warn (_("scale factor of %d without an index register"),
4619 1 << i.log2_scale_factor);
4620 #if SCALE1_WHEN_NO_INDEX
4621 i.log2_scale_factor = 0;
4624 scale = input_line_pointer;
4625 input_line_pointer = save;
4630 i386_displacement (char *disp_start, char *disp_end)
4634 char *save_input_line_pointer;
4635 char *gotfree_input_line;
4636 int bigdisp, override;
4637 unsigned int types = Disp;
4639 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4641 as_bad (_("at most %d displacement operands are allowed"),
4642 MAX_MEMORY_OPERANDS);
4646 if ((i.types[this_operand] & JumpAbsolute)
4647 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4650 override = (i.prefix[ADDR_PREFIX] != 0);
4654 /* For PC-relative branches, the width of the displacement
4655 is dependent upon data size, not address size. */
4657 override = (i.prefix[DATA_PREFIX] != 0);
4659 if (flag_code == CODE_64BIT)
4662 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4664 : Disp32S | Disp32);
4666 bigdisp = Disp64 | Disp32S | Disp32;
4673 override = (i.suffix == (flag_code != CODE_16BIT
4675 : LONG_MNEM_SUFFIX));
4678 if ((flag_code == CODE_16BIT) ^ override)
4681 i.types[this_operand] |= bigdisp;
4683 exp = &disp_expressions[i.disp_operands];
4684 i.op[this_operand].disps = exp;
4686 save_input_line_pointer = input_line_pointer;
4687 input_line_pointer = disp_start;
4688 END_STRING_AND_SAVE (disp_end);
4690 #ifndef GCC_ASM_O_HACK
4691 #define GCC_ASM_O_HACK 0
4694 END_STRING_AND_SAVE (disp_end + 1);
4695 if ((i.types[this_operand] & BaseIndex) != 0
4696 && displacement_string_end[-1] == '+')
4698 /* This hack is to avoid a warning when using the "o"
4699 constraint within gcc asm statements.
4702 #define _set_tssldt_desc(n,addr,limit,type) \
4703 __asm__ __volatile__ ( \
4705 "movw %w1,2+%0\n\t" \
4707 "movb %b1,4+%0\n\t" \
4708 "movb %4,5+%0\n\t" \
4709 "movb $0,6+%0\n\t" \
4710 "movb %h1,7+%0\n\t" \
4712 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4714 This works great except that the output assembler ends
4715 up looking a bit weird if it turns out that there is
4716 no offset. You end up producing code that looks like:
4729 So here we provide the missing zero. */
4731 *displacement_string_end = '0';
4734 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4735 if (gotfree_input_line)
4736 input_line_pointer = gotfree_input_line;
4738 exp_seg = expression (exp);
4741 if (*input_line_pointer)
4742 as_bad (_("junk `%s' after expression"), input_line_pointer);
4744 RESTORE_END_STRING (disp_end + 1);
4746 RESTORE_END_STRING (disp_end);
4747 input_line_pointer = save_input_line_pointer;
4748 if (gotfree_input_line)
4749 free (gotfree_input_line);
4751 /* We do this to make sure that the section symbol is in
4752 the symbol table. We will ultimately change the relocation
4753 to be relative to the beginning of the section. */
4754 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4755 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4756 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4758 if (exp->X_op != O_symbol)
4760 as_bad (_("bad expression used with @%s"),
4761 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4767 if (S_IS_LOCAL (exp->X_add_symbol)
4768 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4769 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4770 exp->X_op = O_subtract;
4771 exp->X_op_symbol = GOT_symbol;
4772 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4773 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4774 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4775 i.reloc[this_operand] = BFD_RELOC_64;
4777 i.reloc[this_operand] = BFD_RELOC_32;
4780 if (exp->X_op == O_absent || exp->X_op == O_big)
4782 /* Missing or bad expr becomes absolute 0. */
4783 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4785 exp->X_op = O_constant;
4786 exp->X_add_number = 0;
4787 exp->X_add_symbol = (symbolS *) 0;
4788 exp->X_op_symbol = (symbolS *) 0;
4791 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4792 if (exp->X_op != O_constant
4793 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4794 && exp_seg != absolute_section
4795 && exp_seg != text_section
4796 && exp_seg != data_section
4797 && exp_seg != bss_section
4798 && exp_seg != undefined_section
4799 && !bfd_is_com_section (exp_seg))
4801 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4806 if (!(i.types[this_operand] & ~Disp))
4807 i.types[this_operand] &= types;
4812 /* Make sure the memory operand we've been dealt is valid.
4813 Return 1 on success, 0 on a failure. */
4816 i386_index_check (const char *operand_string)
4819 #if INFER_ADDR_PREFIX
4825 if ((current_templates->start->cpu_flags & CpuSVME)
4826 && current_templates->end[-1].operand_types[0] == AnyMem)
4828 /* Memory operands of SVME insns are special in that they only allow
4829 rAX as their memory address and ignore any segment override. */
4832 /* SKINIT is even more restrictive: it always requires EAX. */
4833 if (strcmp (current_templates->start->name, "skinit") == 0)
4835 else if (flag_code == CODE_64BIT)
4836 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4838 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4842 || !(i.base_reg->reg_type & Acc)
4843 || !(i.base_reg->reg_type & RegXX)
4845 || (i.types[0] & Disp))
4848 else if (flag_code == CODE_64BIT)
4850 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4853 && ((i.base_reg->reg_type & RegXX) == 0)
4854 && (i.base_reg->reg_type != BaseIndex
4857 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4858 != (RegXX | BaseIndex))))
4863 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4867 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4868 != (Reg16 | BaseIndex)))
4870 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4871 != (Reg16 | BaseIndex))
4873 && i.base_reg->reg_num < 6
4874 && i.index_reg->reg_num >= 6
4875 && i.log2_scale_factor == 0))))
4882 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4884 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4885 != (Reg32 | BaseIndex))))
4891 #if INFER_ADDR_PREFIX
4892 if (i.prefix[ADDR_PREFIX] == 0)
4894 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4896 /* Change the size of any displacement too. At most one of
4897 Disp16 or Disp32 is set.
4898 FIXME. There doesn't seem to be any real need for separate
4899 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4900 Removing them would probably clean up the code quite a lot. */
4901 if (flag_code != CODE_64BIT
4902 && (i.types[this_operand] & (Disp16 | Disp32)))
4903 i.types[this_operand] ^= (Disp16 | Disp32);
4908 as_bad (_("`%s' is not a valid base/index expression"),
4912 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4914 flag_code_names[flag_code]);
4919 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4923 i386_operand (char *operand_string)
4927 char *op_string = operand_string;
4929 if (is_space_char (*op_string))
4932 /* We check for an absolute prefix (differentiating,
4933 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4934 if (*op_string == ABSOLUTE_PREFIX)
4937 if (is_space_char (*op_string))
4939 i.types[this_operand] |= JumpAbsolute;
4942 /* Check if operand is a register. */
4943 if ((r = parse_register (op_string, &end_op)) != NULL)
4945 /* Check for a segment override by searching for ':' after a
4946 segment register. */
4948 if (is_space_char (*op_string))
4950 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4955 i.seg[i.mem_operands] = &es;
4958 i.seg[i.mem_operands] = &cs;
4961 i.seg[i.mem_operands] = &ss;
4964 i.seg[i.mem_operands] = &ds;
4967 i.seg[i.mem_operands] = &fs;
4970 i.seg[i.mem_operands] = &gs;
4974 /* Skip the ':' and whitespace. */
4976 if (is_space_char (*op_string))
4979 if (!is_digit_char (*op_string)
4980 && !is_identifier_char (*op_string)
4981 && *op_string != '('
4982 && *op_string != ABSOLUTE_PREFIX)
4984 as_bad (_("bad memory operand `%s'"), op_string);
4987 /* Handle case of %es:*foo. */
4988 if (*op_string == ABSOLUTE_PREFIX)
4991 if (is_space_char (*op_string))
4993 i.types[this_operand] |= JumpAbsolute;
4995 goto do_memory_reference;
4999 as_bad (_("junk `%s' after register"), op_string);
5002 i.types[this_operand] |= r->reg_type & ~BaseIndex;
5003 i.op[this_operand].regs = r;
5006 else if (*op_string == REGISTER_PREFIX)
5008 as_bad (_("bad register name `%s'"), op_string);
5011 else if (*op_string == IMMEDIATE_PREFIX)
5014 if (i.types[this_operand] & JumpAbsolute)
5016 as_bad (_("immediate operand illegal with absolute jump"));
5019 if (!i386_immediate (op_string))
5022 else if (is_digit_char (*op_string)
5023 || is_identifier_char (*op_string)
5024 || *op_string == '(')
5026 /* This is a memory reference of some sort. */
5029 /* Start and end of displacement string expression (if found). */
5030 char *displacement_string_start;
5031 char *displacement_string_end;
5033 do_memory_reference:
5034 if ((i.mem_operands == 1
5035 && (current_templates->start->opcode_modifier & IsString) == 0)
5036 || i.mem_operands == 2)
5038 as_bad (_("too many memory references for `%s'"),
5039 current_templates->start->name);
5043 /* Check for base index form. We detect the base index form by
5044 looking for an ')' at the end of the operand, searching
5045 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5047 base_string = op_string + strlen (op_string);
5050 if (is_space_char (*base_string))
5053 /* If we only have a displacement, set-up for it to be parsed later. */
5054 displacement_string_start = op_string;
5055 displacement_string_end = base_string + 1;
5057 if (*base_string == ')')
5060 unsigned int parens_balanced = 1;
5061 /* We've already checked that the number of left & right ()'s are
5062 equal, so this loop will not be infinite. */
5066 if (*base_string == ')')
5068 if (*base_string == '(')
5071 while (parens_balanced);
5073 temp_string = base_string;
5075 /* Skip past '(' and whitespace. */
5077 if (is_space_char (*base_string))
5080 if (*base_string == ','
5081 || ((i.base_reg = parse_register (base_string, &end_op))
5084 displacement_string_end = temp_string;
5086 i.types[this_operand] |= BaseIndex;
5090 base_string = end_op;
5091 if (is_space_char (*base_string))
5095 /* There may be an index reg or scale factor here. */
5096 if (*base_string == ',')
5099 if (is_space_char (*base_string))
5102 if ((i.index_reg = parse_register (base_string, &end_op))
5105 base_string = end_op;
5106 if (is_space_char (*base_string))
5108 if (*base_string == ',')
5111 if (is_space_char (*base_string))
5114 else if (*base_string != ')')
5116 as_bad (_("expecting `,' or `)' "
5117 "after index register in `%s'"),
5122 else if (*base_string == REGISTER_PREFIX)
5124 as_bad (_("bad register name `%s'"), base_string);
5128 /* Check for scale factor. */
5129 if (*base_string != ')')
5131 char *end_scale = i386_scale (base_string);
5136 base_string = end_scale;
5137 if (is_space_char (*base_string))
5139 if (*base_string != ')')
5141 as_bad (_("expecting `)' "
5142 "after scale factor in `%s'"),
5147 else if (!i.index_reg)
5149 as_bad (_("expecting index register or scale factor "
5150 "after `,'; got '%c'"),
5155 else if (*base_string != ')')
5157 as_bad (_("expecting `,' or `)' "
5158 "after base register in `%s'"),
5163 else if (*base_string == REGISTER_PREFIX)
5165 as_bad (_("bad register name `%s'"), base_string);
5170 /* If there's an expression beginning the operand, parse it,
5171 assuming displacement_string_start and
5172 displacement_string_end are meaningful. */
5173 if (displacement_string_start != displacement_string_end)
5175 if (!i386_displacement (displacement_string_start,
5176 displacement_string_end))
5180 /* Special case for (%dx) while doing input/output op. */
5182 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5184 && i.log2_scale_factor == 0
5185 && i.seg[i.mem_operands] == 0
5186 && (i.types[this_operand] & Disp) == 0)
5188 i.types[this_operand] = InOutPortReg;
5192 if (i386_index_check (operand_string) == 0)
5198 /* It's not a memory operand; argh! */
5199 as_bad (_("invalid char %s beginning operand %d `%s'"),
5200 output_invalid (*op_string),
5205 return 1; /* Normal return. */
5208 /* md_estimate_size_before_relax()
5210 Called just before relax() for rs_machine_dependent frags. The x86
5211 assembler uses these frags to handle variable size jump
5214 Any symbol that is now undefined will not become defined.
5215 Return the correct fr_subtype in the frag.
5216 Return the initial "guess for variable size of frag" to caller.
5217 The guess is actually the growth beyond the fixed part. Whatever
5218 we do to grow the fixed or variable part contributes to our
5222 md_estimate_size_before_relax (fragP, segment)
5226 /* We've already got fragP->fr_subtype right; all we have to do is
5227 check for un-relaxable symbols. On an ELF system, we can't relax
5228 an externally visible symbol, because it may be overridden by a
5230 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5233 && (S_IS_EXTERNAL (fragP->fr_symbol)
5234 || S_IS_WEAK (fragP->fr_symbol)))
5238 /* Symbol is undefined in this segment, or we need to keep a
5239 reloc so that weak symbols can be overridden. */
5240 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5241 enum bfd_reloc_code_real reloc_type;
5242 unsigned char *opcode;
5245 if (fragP->fr_var != NO_RELOC)
5246 reloc_type = fragP->fr_var;
5248 reloc_type = BFD_RELOC_16_PCREL;
5250 reloc_type = BFD_RELOC_32_PCREL;
5252 old_fr_fix = fragP->fr_fix;
5253 opcode = (unsigned char *) fragP->fr_opcode;
5255 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5258 /* Make jmp (0xeb) a (d)word displacement jump. */
5260 fragP->fr_fix += size;
5261 fix_new (fragP, old_fr_fix, size,
5263 fragP->fr_offset, 1,
5269 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5271 /* Negate the condition, and branch past an
5272 unconditional jump. */
5275 /* Insert an unconditional jump. */
5277 /* We added two extra opcode bytes, and have a two byte
5279 fragP->fr_fix += 2 + 2;
5280 fix_new (fragP, old_fr_fix + 2, 2,
5282 fragP->fr_offset, 1,
5289 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5294 fixP = fix_new (fragP, old_fr_fix, 1,
5296 fragP->fr_offset, 1,
5298 fixP->fx_signed = 1;
5302 /* This changes the byte-displacement jump 0x7N
5303 to the (d)word-displacement jump 0x0f,0x8N. */
5304 opcode[1] = opcode[0] + 0x10;
5305 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5306 /* We've added an opcode byte. */
5307 fragP->fr_fix += 1 + size;
5308 fix_new (fragP, old_fr_fix + 1, size,
5310 fragP->fr_offset, 1,
5315 BAD_CASE (fragP->fr_subtype);
5319 return fragP->fr_fix - old_fr_fix;
5322 /* Guess size depending on current relax state. Initially the relax
5323 state will correspond to a short jump and we return 1, because
5324 the variable part of the frag (the branch offset) is one byte
5325 long. However, we can relax a section more than once and in that
5326 case we must either set fr_subtype back to the unrelaxed state,
5327 or return the value for the appropriate branch. */
5328 return md_relax_table[fragP->fr_subtype].rlx_length;
5331 /* Called after relax() is finished.
5333 In: Address of frag.
5334 fr_type == rs_machine_dependent.
5335 fr_subtype is what the address relaxed to.
5337 Out: Any fixSs and constants are set up.
5338 Caller will turn frag into a ".space 0". */
5341 md_convert_frag (abfd, sec, fragP)
5342 bfd *abfd ATTRIBUTE_UNUSED;
5343 segT sec ATTRIBUTE_UNUSED;
5346 unsigned char *opcode;
5347 unsigned char *where_to_put_displacement = NULL;
5348 offsetT target_address;
5349 offsetT opcode_address;
5350 unsigned int extension = 0;
5351 offsetT displacement_from_opcode_start;
5353 opcode = (unsigned char *) fragP->fr_opcode;
5355 /* Address we want to reach in file space. */
5356 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5358 /* Address opcode resides at in file space. */
5359 opcode_address = fragP->fr_address + fragP->fr_fix;
5361 /* Displacement from opcode start to fill into instruction. */
5362 displacement_from_opcode_start = target_address - opcode_address;
5364 if ((fragP->fr_subtype & BIG) == 0)
5366 /* Don't have to change opcode. */
5367 extension = 1; /* 1 opcode + 1 displacement */
5368 where_to_put_displacement = &opcode[1];
5372 if (no_cond_jump_promotion
5373 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5374 as_warn_where (fragP->fr_file, fragP->fr_line,
5375 _("long jump required"));
5377 switch (fragP->fr_subtype)
5379 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5380 extension = 4; /* 1 opcode + 4 displacement */
5382 where_to_put_displacement = &opcode[1];
5385 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5386 extension = 2; /* 1 opcode + 2 displacement */
5388 where_to_put_displacement = &opcode[1];
5391 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5392 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5393 extension = 5; /* 2 opcode + 4 displacement */
5394 opcode[1] = opcode[0] + 0x10;
5395 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5396 where_to_put_displacement = &opcode[2];
5399 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5400 extension = 3; /* 2 opcode + 2 displacement */
5401 opcode[1] = opcode[0] + 0x10;
5402 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5403 where_to_put_displacement = &opcode[2];
5406 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5411 where_to_put_displacement = &opcode[3];
5415 BAD_CASE (fragP->fr_subtype);
5420 /* If size if less then four we are sure that the operand fits,
5421 but if it's 4, then it could be that the displacement is larger
5423 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5425 && ((addressT) (displacement_from_opcode_start - extension
5426 + ((addressT) 1 << 31))
5427 > (((addressT) 2 << 31) - 1)))
5429 as_bad_where (fragP->fr_file, fragP->fr_line,
5430 _("jump target out of range"));
5431 /* Make us emit 0. */
5432 displacement_from_opcode_start = extension;
5434 /* Now put displacement after opcode. */
5435 md_number_to_chars ((char *) where_to_put_displacement,
5436 (valueT) (displacement_from_opcode_start - extension),
5437 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5438 fragP->fr_fix += extension;
5441 /* Size of byte displacement jmp. */
5442 int md_short_jump_size = 2;
5444 /* Size of dword displacement jmp. */
5445 int md_long_jump_size = 5;
5448 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5450 addressT from_addr, to_addr;
5451 fragS *frag ATTRIBUTE_UNUSED;
5452 symbolS *to_symbol ATTRIBUTE_UNUSED;
5456 offset = to_addr - (from_addr + 2);
5457 /* Opcode for byte-disp jump. */
5458 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5459 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5463 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5465 addressT from_addr, to_addr;
5466 fragS *frag ATTRIBUTE_UNUSED;
5467 symbolS *to_symbol ATTRIBUTE_UNUSED;
5471 offset = to_addr - (from_addr + 5);
5472 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5473 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5476 /* Apply a fixup (fixS) to segment data, once it has been determined
5477 by our caller that we have all the info we need to fix it up.
5479 On the 386, immediates, displacements, and data pointers are all in
5480 the same (little-endian) format, so we don't need to care about which
5484 md_apply_fix (fixP, valP, seg)
5485 /* The fix we're to put in. */
5487 /* Pointer to the value of the bits. */
5489 /* Segment fix is from. */
5490 segT seg ATTRIBUTE_UNUSED;
5492 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5493 valueT value = *valP;
5495 #if !defined (TE_Mach)
5498 switch (fixP->fx_r_type)
5504 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5507 case BFD_RELOC_X86_64_32S:
5508 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5511 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5514 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5519 if (fixP->fx_addsy != NULL
5520 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5521 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5522 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5523 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5524 && !use_rela_relocations)
5526 /* This is a hack. There should be a better way to handle this.
5527 This covers for the fact that bfd_install_relocation will
5528 subtract the current location (for partial_inplace, PC relative
5529 relocations); see more below. */
5533 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5536 value += fixP->fx_where + fixP->fx_frag->fr_address;
5538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5541 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5544 || (symbol_section_p (fixP->fx_addsy)
5545 && sym_seg != absolute_section))
5546 && !generic_force_reloc (fixP))
5548 /* Yes, we add the values in twice. This is because
5549 bfd_install_relocation subtracts them out again. I think
5550 bfd_install_relocation is broken, but I don't dare change
5552 value += fixP->fx_where + fixP->fx_frag->fr_address;
5556 #if defined (OBJ_COFF) && defined (TE_PE)
5557 /* For some reason, the PE format does not store a
5558 section address offset for a PC relative symbol. */
5559 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5560 || S_IS_WEAK (fixP->fx_addsy))
5561 value += md_pcrel_from (fixP);
5565 /* Fix a few things - the dynamic linker expects certain values here,
5566 and we must not disappoint it. */
5567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5568 if (IS_ELF && fixP->fx_addsy)
5569 switch (fixP->fx_r_type)
5571 case BFD_RELOC_386_PLT32:
5572 case BFD_RELOC_X86_64_PLT32:
5573 /* Make the jump instruction point to the address of the operand. At
5574 runtime we merely add the offset to the actual PLT entry. */
5578 case BFD_RELOC_386_TLS_GD:
5579 case BFD_RELOC_386_TLS_LDM:
5580 case BFD_RELOC_386_TLS_IE_32:
5581 case BFD_RELOC_386_TLS_IE:
5582 case BFD_RELOC_386_TLS_GOTIE:
5583 case BFD_RELOC_386_TLS_GOTDESC:
5584 case BFD_RELOC_X86_64_TLSGD:
5585 case BFD_RELOC_X86_64_TLSLD:
5586 case BFD_RELOC_X86_64_GOTTPOFF:
5587 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5588 value = 0; /* Fully resolved at runtime. No addend. */
5590 case BFD_RELOC_386_TLS_LE:
5591 case BFD_RELOC_386_TLS_LDO_32:
5592 case BFD_RELOC_386_TLS_LE_32:
5593 case BFD_RELOC_X86_64_DTPOFF32:
5594 case BFD_RELOC_X86_64_DTPOFF64:
5595 case BFD_RELOC_X86_64_TPOFF32:
5596 case BFD_RELOC_X86_64_TPOFF64:
5597 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5600 case BFD_RELOC_386_TLS_DESC_CALL:
5601 case BFD_RELOC_X86_64_TLSDESC_CALL:
5602 value = 0; /* Fully resolved at runtime. No addend. */
5603 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5607 case BFD_RELOC_386_GOT32:
5608 case BFD_RELOC_X86_64_GOT32:
5609 value = 0; /* Fully resolved at runtime. No addend. */
5612 case BFD_RELOC_VTABLE_INHERIT:
5613 case BFD_RELOC_VTABLE_ENTRY:
5620 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5622 #endif /* !defined (TE_Mach) */
5624 /* Are we finished with this relocation now? */
5625 if (fixP->fx_addsy == NULL)
5627 else if (use_rela_relocations)
5629 fixP->fx_no_overflow = 1;
5630 /* Remember value for tc_gen_reloc. */
5631 fixP->fx_addnumber = value;
5635 md_number_to_chars (p, value, fixP->fx_size);
5638 #define MAX_LITTLENUMS 6
5640 /* Turn the string pointed to by litP into a floating point constant
5641 of type TYPE, and emit the appropriate bytes. The number of
5642 LITTLENUMS emitted is stored in *SIZEP. An error message is
5643 returned, or NULL on OK. */
5646 md_atof (type, litP, sizeP)
5652 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5653 LITTLENUM_TYPE *wordP;
5675 return _("Bad call to md_atof ()");
5677 t = atof_ieee (input_line_pointer, type, words);
5679 input_line_pointer = t;
5681 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5682 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5683 the bigendian 386. */
5684 for (wordP = words + prec - 1; prec--;)
5686 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5687 litP += sizeof (LITTLENUM_TYPE);
5692 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5695 output_invalid (int c)
5698 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5701 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5702 "(0x%x)", (unsigned char) c);
5703 return output_invalid_buf;
5706 /* REG_STRING starts *before* REGISTER_PREFIX. */
5708 static const reg_entry *
5709 parse_real_register (char *reg_string, char **end_op)
5711 char *s = reg_string;
5713 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5716 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5717 if (*s == REGISTER_PREFIX)
5720 if (is_space_char (*s))
5724 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5726 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5727 return (const reg_entry *) NULL;
5731 /* For naked regs, make sure that we are not dealing with an identifier.
5732 This prevents confusing an identifier like `eax_var' with register
5734 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5735 return (const reg_entry *) NULL;
5739 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5741 /* Handle floating point regs, allowing spaces in the (i) part. */
5742 if (r == i386_regtab /* %st is first entry of table */)
5744 if (is_space_char (*s))
5749 if (is_space_char (*s))
5751 if (*s >= '0' && *s <= '7')
5753 r = &i386_float_regtab[*s - '0'];
5755 if (is_space_char (*s))
5763 /* We have "%st(" then garbage. */
5764 return (const reg_entry *) NULL;
5769 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5770 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5771 && flag_code != CODE_64BIT)
5772 return (const reg_entry *) NULL;
5777 /* REG_STRING starts *before* REGISTER_PREFIX. */
5779 static const reg_entry *
5780 parse_register (char *reg_string, char **end_op)
5784 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5785 r = parse_real_register (reg_string, end_op);
5790 char *save = input_line_pointer;
5794 input_line_pointer = reg_string;
5795 c = get_symbol_end ();
5796 symbolP = symbol_find (reg_string);
5797 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5799 const expressionS *e = symbol_get_value_expression (symbolP);
5801 know (e->X_op == O_register);
5802 know (e->X_add_number >= 0
5803 && (valueT) e->X_add_number < i386_regtab_size);
5804 r = i386_regtab + e->X_add_number;
5805 *end_op = input_line_pointer;
5807 *input_line_pointer = c;
5808 input_line_pointer = save;
5814 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5817 char *end = input_line_pointer;
5820 r = parse_register (name, &input_line_pointer);
5821 if (r && end <= input_line_pointer)
5823 *nextcharP = *input_line_pointer;
5824 *input_line_pointer = 0;
5825 e->X_op = O_register;
5826 e->X_add_number = r - i386_regtab;
5829 input_line_pointer = end;
5835 md_operand (expressionS *e)
5837 if (*input_line_pointer == REGISTER_PREFIX)
5840 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5844 e->X_op = O_register;
5845 e->X_add_number = r - i386_regtab;
5846 input_line_pointer = end;
5852 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5853 const char *md_shortopts = "kVQ:sqn";
5855 const char *md_shortopts = "qn";
5858 #define OPTION_32 (OPTION_MD_BASE + 0)
5859 #define OPTION_64 (OPTION_MD_BASE + 1)
5860 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5861 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5862 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5864 struct option md_longopts[] =
5866 {"32", no_argument, NULL, OPTION_32},
5867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5868 {"64", no_argument, NULL, OPTION_64},
5870 {"divide", no_argument, NULL, OPTION_DIVIDE},
5871 {"march", required_argument, NULL, OPTION_MARCH},
5872 {"mtune", required_argument, NULL, OPTION_MTUNE},
5873 {NULL, no_argument, NULL, 0}
5875 size_t md_longopts_size = sizeof (md_longopts);
5878 md_parse_option (int c, char *arg)
5885 optimize_align_code = 0;
5892 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5893 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5894 should be emitted or not. FIXME: Not implemented. */
5898 /* -V: SVR4 argument to print version ID. */
5900 print_version_id ();
5903 /* -k: Ignore for FreeBSD compatibility. */
5908 /* -s: On i386 Solaris, this tells the native assembler to use
5909 .stab instead of .stab.excl. We always use .stab anyhow. */
5912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5915 const char **list, **l;
5917 list = bfd_target_list ();
5918 for (l = list; *l != NULL; l++)
5919 if (CONST_STRNEQ (*l, "elf64-x86-64")
5920 || strcmp (*l, "coff-x86-64") == 0
5921 || strcmp (*l, "pe-x86-64") == 0
5922 || strcmp (*l, "pei-x86-64") == 0)
5924 default_arch = "x86_64";
5928 as_fatal (_("No compiled in support for x86_64"));
5935 default_arch = "i386";
5939 #ifdef SVR4_COMMENT_CHARS
5944 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5946 for (s = i386_comment_chars; *s != '\0'; s++)
5950 i386_comment_chars = n;
5957 as_fatal (_("Invalid -march= option: `%s'"), arg);
5958 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5960 if (strcmp (arg, cpu_arch [i].name) == 0)
5962 cpu_arch_isa = cpu_arch[i].type;
5963 cpu_arch_isa_flags = cpu_arch[i].flags;
5964 if (!cpu_arch_tune_set)
5966 cpu_arch_tune = cpu_arch_isa;
5967 cpu_arch_tune_flags = cpu_arch_isa_flags;
5972 if (i >= ARRAY_SIZE (cpu_arch))
5973 as_fatal (_("Invalid -march= option: `%s'"), arg);
5978 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5979 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5981 if (strcmp (arg, cpu_arch [i].name) == 0)
5983 cpu_arch_tune_set = 1;
5984 cpu_arch_tune = cpu_arch [i].type;
5985 cpu_arch_tune_flags = cpu_arch[i].flags;
5989 if (i >= ARRAY_SIZE (cpu_arch))
5990 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6000 md_show_usage (stream)
6003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6004 fprintf (stream, _("\
6006 -V print assembler version number\n\
6009 fprintf (stream, _("\
6010 -n Do not optimize code alignment\n\
6011 -q quieten some warnings\n"));
6012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6013 fprintf (stream, _("\
6016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6017 fprintf (stream, _("\
6018 --32/--64 generate 32bit/64bit code\n"));
6020 #ifdef SVR4_COMMENT_CHARS
6021 fprintf (stream, _("\
6022 --divide do not treat `/' as a comment character\n"));
6024 fprintf (stream, _("\
6025 --divide ignored\n"));
6027 fprintf (stream, _("\
6028 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6029 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6030 core, core2, k6, athlon, k8, generic32, generic64\n"));
6036 x86_64_target_format (void)
6038 if (strcmp (default_arch, "x86_64") == 0)
6040 set_code_flag (CODE_64BIT);
6041 return COFF_TARGET_FORMAT;
6043 else if (strcmp (default_arch, "i386") == 0)
6045 set_code_flag (CODE_32BIT);
6049 as_fatal (_("Unknown architecture"));
6054 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6055 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6057 /* Pick the target format to use. */
6060 i386_target_format (void)
6062 if (!strcmp (default_arch, "x86_64"))
6064 set_code_flag (CODE_64BIT);
6065 if (cpu_arch_isa_flags == 0)
6066 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
6067 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6069 if (cpu_arch_tune_flags == 0)
6070 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
6071 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6074 else if (!strcmp (default_arch, "i386"))
6076 set_code_flag (CODE_32BIT);
6077 if (cpu_arch_isa_flags == 0)
6078 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
6079 if (cpu_arch_tune_flags == 0)
6080 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
6083 as_fatal (_("Unknown architecture"));
6084 switch (OUTPUT_FLAVOR)
6086 #ifdef OBJ_MAYBE_AOUT
6087 case bfd_target_aout_flavour:
6088 return AOUT_TARGET_FORMAT;
6090 #ifdef OBJ_MAYBE_COFF
6091 case bfd_target_coff_flavour:
6094 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6095 case bfd_target_elf_flavour:
6097 if (flag_code == CODE_64BIT)
6100 use_rela_relocations = 1;
6102 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
6111 #endif /* OBJ_MAYBE_ more than one */
6113 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6115 i386_elf_emit_arch_note (void)
6117 if (IS_ELF && cpu_arch_name != NULL)
6120 asection *seg = now_seg;
6121 subsegT subseg = now_subseg;
6122 Elf_Internal_Note i_note;
6123 Elf_External_Note e_note;
6124 asection *note_secp;
6127 /* Create the .note section. */
6128 note_secp = subseg_new (".note", 0);
6129 bfd_set_section_flags (stdoutput,
6131 SEC_HAS_CONTENTS | SEC_READONLY);
6133 /* Process the arch string. */
6134 len = strlen (cpu_arch_name);
6136 i_note.namesz = len + 1;
6138 i_note.type = NT_ARCH;
6139 p = frag_more (sizeof (e_note.namesz));
6140 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6141 p = frag_more (sizeof (e_note.descsz));
6142 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6143 p = frag_more (sizeof (e_note.type));
6144 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6145 p = frag_more (len + 1);
6146 strcpy (p, cpu_arch_name);
6148 frag_align (2, 0, 0);
6150 subseg_set (seg, subseg);
6156 md_undefined_symbol (name)
6159 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6160 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6161 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6162 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6166 if (symbol_find (name))
6167 as_bad (_("GOT already in symbol table"));
6168 GOT_symbol = symbol_new (name, undefined_section,
6169 (valueT) 0, &zero_address_frag);
6176 /* Round up a section size to the appropriate boundary. */
6179 md_section_align (segment, size)
6180 segT segment ATTRIBUTE_UNUSED;
6183 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6184 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6186 /* For a.out, force the section size to be aligned. If we don't do
6187 this, BFD will align it for us, but it will not write out the
6188 final bytes of the section. This may be a bug in BFD, but it is
6189 easier to fix it here since that is how the other a.out targets
6193 align = bfd_get_section_alignment (stdoutput, segment);
6194 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6201 /* On the i386, PC-relative offsets are relative to the start of the
6202 next instruction. That is, the address of the offset, plus its
6203 size, since the offset is always the last part of the insn. */
6206 md_pcrel_from (fixS *fixP)
6208 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6214 s_bss (int ignore ATTRIBUTE_UNUSED)
6218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6220 obj_elf_section_change_hook ();
6222 temp = get_absolute_expression ();
6223 subseg_set (bss_section, (subsegT) temp);
6224 demand_empty_rest_of_line ();
6230 i386_validate_fix (fixS *fixp)
6232 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6234 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6238 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6243 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6245 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6252 tc_gen_reloc (section, fixp)
6253 asection *section ATTRIBUTE_UNUSED;
6257 bfd_reloc_code_real_type code;
6259 switch (fixp->fx_r_type)
6261 case BFD_RELOC_X86_64_PLT32:
6262 case BFD_RELOC_X86_64_GOT32:
6263 case BFD_RELOC_X86_64_GOTPCREL:
6264 case BFD_RELOC_386_PLT32:
6265 case BFD_RELOC_386_GOT32:
6266 case BFD_RELOC_386_GOTOFF:
6267 case BFD_RELOC_386_GOTPC:
6268 case BFD_RELOC_386_TLS_GD:
6269 case BFD_RELOC_386_TLS_LDM:
6270 case BFD_RELOC_386_TLS_LDO_32:
6271 case BFD_RELOC_386_TLS_IE_32:
6272 case BFD_RELOC_386_TLS_IE:
6273 case BFD_RELOC_386_TLS_GOTIE:
6274 case BFD_RELOC_386_TLS_LE_32:
6275 case BFD_RELOC_386_TLS_LE:
6276 case BFD_RELOC_386_TLS_GOTDESC:
6277 case BFD_RELOC_386_TLS_DESC_CALL:
6278 case BFD_RELOC_X86_64_TLSGD:
6279 case BFD_RELOC_X86_64_TLSLD:
6280 case BFD_RELOC_X86_64_DTPOFF32:
6281 case BFD_RELOC_X86_64_DTPOFF64:
6282 case BFD_RELOC_X86_64_GOTTPOFF:
6283 case BFD_RELOC_X86_64_TPOFF32:
6284 case BFD_RELOC_X86_64_TPOFF64:
6285 case BFD_RELOC_X86_64_GOTOFF64:
6286 case BFD_RELOC_X86_64_GOTPC32:
6287 case BFD_RELOC_X86_64_GOT64:
6288 case BFD_RELOC_X86_64_GOTPCREL64:
6289 case BFD_RELOC_X86_64_GOTPC64:
6290 case BFD_RELOC_X86_64_GOTPLT64:
6291 case BFD_RELOC_X86_64_PLTOFF64:
6292 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6293 case BFD_RELOC_X86_64_TLSDESC_CALL:
6295 case BFD_RELOC_VTABLE_ENTRY:
6296 case BFD_RELOC_VTABLE_INHERIT:
6298 case BFD_RELOC_32_SECREL:
6300 code = fixp->fx_r_type;
6302 case BFD_RELOC_X86_64_32S:
6303 if (!fixp->fx_pcrel)
6305 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6306 code = fixp->fx_r_type;
6312 switch (fixp->fx_size)
6315 as_bad_where (fixp->fx_file, fixp->fx_line,
6316 _("can not do %d byte pc-relative relocation"),
6318 code = BFD_RELOC_32_PCREL;
6320 case 1: code = BFD_RELOC_8_PCREL; break;
6321 case 2: code = BFD_RELOC_16_PCREL; break;
6322 case 4: code = BFD_RELOC_32_PCREL; break;
6324 case 8: code = BFD_RELOC_64_PCREL; break;
6330 switch (fixp->fx_size)
6333 as_bad_where (fixp->fx_file, fixp->fx_line,
6334 _("can not do %d byte relocation"),
6336 code = BFD_RELOC_32;
6338 case 1: code = BFD_RELOC_8; break;
6339 case 2: code = BFD_RELOC_16; break;
6340 case 4: code = BFD_RELOC_32; break;
6342 case 8: code = BFD_RELOC_64; break;
6349 if ((code == BFD_RELOC_32
6350 || code == BFD_RELOC_32_PCREL
6351 || code == BFD_RELOC_X86_64_32S)
6353 && fixp->fx_addsy == GOT_symbol)
6356 code = BFD_RELOC_386_GOTPC;
6358 code = BFD_RELOC_X86_64_GOTPC32;
6360 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6362 && fixp->fx_addsy == GOT_symbol)
6364 code = BFD_RELOC_X86_64_GOTPC64;
6367 rel = (arelent *) xmalloc (sizeof (arelent));
6368 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6369 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6371 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6373 if (!use_rela_relocations)
6375 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6376 vtable entry to be used in the relocation's section offset. */
6377 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6378 rel->address = fixp->fx_offset;
6382 /* Use the rela in 64bit mode. */
6385 if (!fixp->fx_pcrel)
6386 rel->addend = fixp->fx_offset;
6390 case BFD_RELOC_X86_64_PLT32:
6391 case BFD_RELOC_X86_64_GOT32:
6392 case BFD_RELOC_X86_64_GOTPCREL:
6393 case BFD_RELOC_X86_64_TLSGD:
6394 case BFD_RELOC_X86_64_TLSLD:
6395 case BFD_RELOC_X86_64_GOTTPOFF:
6396 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6397 case BFD_RELOC_X86_64_TLSDESC_CALL:
6398 rel->addend = fixp->fx_offset - fixp->fx_size;
6401 rel->addend = (section->vma
6403 + fixp->fx_addnumber
6404 + md_pcrel_from (fixp));
6409 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6410 if (rel->howto == NULL)
6412 as_bad_where (fixp->fx_file, fixp->fx_line,
6413 _("cannot represent relocation type %s"),
6414 bfd_get_reloc_code_name (code));
6415 /* Set howto to a garbage value so that we can keep going. */
6416 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6417 assert (rel->howto != NULL);
6424 /* Parse operands using Intel syntax. This implements a recursive descent
6425 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6428 FIXME: We do not recognize the full operand grammar defined in the MASM
6429 documentation. In particular, all the structure/union and
6430 high-level macro operands are missing.
6432 Uppercase words are terminals, lower case words are non-terminals.
6433 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6434 bars '|' denote choices. Most grammar productions are implemented in
6435 functions called 'intel_<production>'.
6437 Initial production is 'expr'.
6443 binOp & | AND | \| | OR | ^ | XOR
6445 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6447 constant digits [[ radixOverride ]]
6449 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6487 => expr expr cmpOp e04
6490 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6491 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6493 hexdigit a | b | c | d | e | f
6494 | A | B | C | D | E | F
6500 mulOp * | / | % | MOD | << | SHL | >> | SHR
6504 register specialRegister
6508 segmentRegister CS | DS | ES | FS | GS | SS
6510 specialRegister CR0 | CR2 | CR3 | CR4
6511 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6512 | TR3 | TR4 | TR5 | TR6 | TR7
6514 We simplify the grammar in obvious places (e.g., register parsing is
6515 done by calling parse_register) and eliminate immediate left recursion
6516 to implement a recursive-descent parser.
6520 expr' cmpOp e04 expr'
6571 /* Parsing structure for the intel syntax parser. Used to implement the
6572 semantic actions for the operand grammar. */
6573 struct intel_parser_s
6575 char *op_string; /* The string being parsed. */
6576 int got_a_float; /* Whether the operand is a float. */
6577 int op_modifier; /* Operand modifier. */
6578 int is_mem; /* 1 if operand is memory reference. */
6579 int in_offset; /* >=1 if parsing operand of offset. */
6580 int in_bracket; /* >=1 if parsing operand in brackets. */
6581 const reg_entry *reg; /* Last register reference found. */
6582 char *disp; /* Displacement string being built. */
6583 char *next_operand; /* Resume point when splitting operands. */
6586 static struct intel_parser_s intel_parser;
6588 /* Token structure for parsing intel syntax. */
6591 int code; /* Token code. */
6592 const reg_entry *reg; /* Register entry for register tokens. */
6593 char *str; /* String representation. */
6596 static struct intel_token cur_token, prev_token;
6598 /* Token codes for the intel parser. Since T_SHORT is already used
6599 by COFF, undefine it first to prevent a warning. */
6618 /* Prototypes for intel parser functions. */
6619 static int intel_match_token (int);
6620 static void intel_putback_token (void);
6621 static void intel_get_token (void);
6622 static int intel_expr (void);
6623 static int intel_e04 (void);
6624 static int intel_e05 (void);
6625 static int intel_e06 (void);
6626 static int intel_e09 (void);
6627 static int intel_e10 (void);
6628 static int intel_e11 (void);
6631 i386_intel_operand (char *operand_string, int got_a_float)
6636 p = intel_parser.op_string = xstrdup (operand_string);
6637 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6641 /* Initialize token holders. */
6642 cur_token.code = prev_token.code = T_NIL;
6643 cur_token.reg = prev_token.reg = NULL;
6644 cur_token.str = prev_token.str = NULL;
6646 /* Initialize parser structure. */
6647 intel_parser.got_a_float = got_a_float;
6648 intel_parser.op_modifier = 0;
6649 intel_parser.is_mem = 0;
6650 intel_parser.in_offset = 0;
6651 intel_parser.in_bracket = 0;
6652 intel_parser.reg = NULL;
6653 intel_parser.disp[0] = '\0';
6654 intel_parser.next_operand = NULL;
6656 /* Read the first token and start the parser. */
6658 ret = intel_expr ();
6663 if (cur_token.code != T_NIL)
6665 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6666 current_templates->start->name, cur_token.str);
6669 /* If we found a memory reference, hand it over to i386_displacement
6670 to fill in the rest of the operand fields. */
6671 else if (intel_parser.is_mem)
6673 if ((i.mem_operands == 1
6674 && (current_templates->start->opcode_modifier & IsString) == 0)
6675 || i.mem_operands == 2)
6677 as_bad (_("too many memory references for '%s'"),
6678 current_templates->start->name);
6683 char *s = intel_parser.disp;
6686 if (!quiet_warnings && intel_parser.is_mem < 0)
6687 /* See the comments in intel_bracket_expr. */
6688 as_warn (_("Treating `%s' as memory reference"), operand_string);
6690 /* Add the displacement expression. */
6692 ret = i386_displacement (s, s + strlen (s));
6695 /* Swap base and index in 16-bit memory operands like
6696 [si+bx]. Since i386_index_check is also used in AT&T
6697 mode we have to do that here. */
6700 && (i.base_reg->reg_type & Reg16)
6701 && (i.index_reg->reg_type & Reg16)
6702 && i.base_reg->reg_num >= 6
6703 && i.index_reg->reg_num < 6)
6705 const reg_entry *base = i.index_reg;
6707 i.index_reg = i.base_reg;
6710 ret = i386_index_check (operand_string);
6715 /* Constant and OFFSET expressions are handled by i386_immediate. */
6716 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6717 || intel_parser.reg == NULL)
6718 ret = i386_immediate (intel_parser.disp);
6720 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6722 if (!ret || !intel_parser.next_operand)
6724 intel_parser.op_string = intel_parser.next_operand;
6725 this_operand = i.operands++;
6729 free (intel_parser.disp);
6734 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6738 expr' cmpOp e04 expr'
6743 /* XXX Implement the comparison operators. */
6744 return intel_e04 ();
6761 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6762 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6764 if (cur_token.code == '+')
6766 else if (cur_token.code == '-')
6767 nregs = NUM_ADDRESS_REGS;
6771 strcat (intel_parser.disp, cur_token.str);
6772 intel_match_token (cur_token.code);
6783 int nregs = ~NUM_ADDRESS_REGS;
6790 if (cur_token.code == '&'
6791 || cur_token.code == '|'
6792 || cur_token.code == '^')
6796 str[0] = cur_token.code;
6798 strcat (intel_parser.disp, str);
6803 intel_match_token (cur_token.code);
6808 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6809 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6820 int nregs = ~NUM_ADDRESS_REGS;
6827 if (cur_token.code == '*'
6828 || cur_token.code == '/'
6829 || cur_token.code == '%')
6833 str[0] = cur_token.code;
6835 strcat (intel_parser.disp, str);
6837 else if (cur_token.code == T_SHL)
6838 strcat (intel_parser.disp, "<<");
6839 else if (cur_token.code == T_SHR)
6840 strcat (intel_parser.disp, ">>");
6844 intel_match_token (cur_token.code);
6849 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6850 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6868 int nregs = ~NUM_ADDRESS_REGS;
6873 /* Don't consume constants here. */
6874 if (cur_token.code == '+' || cur_token.code == '-')
6876 /* Need to look one token ahead - if the next token
6877 is a constant, the current token is its sign. */
6880 intel_match_token (cur_token.code);
6881 next_code = cur_token.code;
6882 intel_putback_token ();
6883 if (next_code == T_CONST)
6887 /* e09 OFFSET e09 */
6888 if (cur_token.code == T_OFFSET)
6891 ++intel_parser.in_offset;
6895 else if (cur_token.code == T_SHORT)
6896 intel_parser.op_modifier |= 1 << T_SHORT;
6899 else if (cur_token.code == '+')
6900 strcat (intel_parser.disp, "+");
6905 else if (cur_token.code == '-' || cur_token.code == '~')
6911 str[0] = cur_token.code;
6913 strcat (intel_parser.disp, str);
6920 intel_match_token (cur_token.code);
6928 /* e09' PTR e10 e09' */
6929 if (cur_token.code == T_PTR)
6933 if (prev_token.code == T_BYTE)
6934 suffix = BYTE_MNEM_SUFFIX;
6936 else if (prev_token.code == T_WORD)
6938 if (current_templates->start->name[0] == 'l'
6939 && current_templates->start->name[2] == 's'
6940 && current_templates->start->name[3] == 0)
6941 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6942 else if (intel_parser.got_a_float == 2) /* "fi..." */
6943 suffix = SHORT_MNEM_SUFFIX;
6945 suffix = WORD_MNEM_SUFFIX;
6948 else if (prev_token.code == T_DWORD)
6950 if (current_templates->start->name[0] == 'l'
6951 && current_templates->start->name[2] == 's'
6952 && current_templates->start->name[3] == 0)
6953 suffix = WORD_MNEM_SUFFIX;
6954 else if (flag_code == CODE_16BIT
6955 && (current_templates->start->opcode_modifier
6956 & (Jump | JumpDword)))
6957 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6958 else if (intel_parser.got_a_float == 1) /* "f..." */
6959 suffix = SHORT_MNEM_SUFFIX;
6961 suffix = LONG_MNEM_SUFFIX;
6964 else if (prev_token.code == T_FWORD)
6966 if (current_templates->start->name[0] == 'l'
6967 && current_templates->start->name[2] == 's'
6968 && current_templates->start->name[3] == 0)
6969 suffix = LONG_MNEM_SUFFIX;
6970 else if (!intel_parser.got_a_float)
6972 if (flag_code == CODE_16BIT)
6973 add_prefix (DATA_PREFIX_OPCODE);
6974 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6977 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6980 else if (prev_token.code == T_QWORD)
6982 if (intel_parser.got_a_float == 1) /* "f..." */
6983 suffix = LONG_MNEM_SUFFIX;
6985 suffix = QWORD_MNEM_SUFFIX;
6988 else if (prev_token.code == T_TBYTE)
6990 if (intel_parser.got_a_float == 1)
6991 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6993 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6996 else if (prev_token.code == T_XMMWORD)
6998 /* XXX ignored for now, but accepted since gcc uses it */
7004 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7008 /* Operands for jump/call using 'ptr' notation denote absolute
7010 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7011 i.types[this_operand] |= JumpAbsolute;
7013 if (current_templates->start->base_opcode == 0x8d /* lea */)
7017 else if (i.suffix != suffix)
7019 as_bad (_("Conflicting operand modifiers"));
7025 /* e09' : e10 e09' */
7026 else if (cur_token.code == ':')
7028 if (prev_token.code != T_REG)
7030 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7031 segment/group identifier (which we don't have), using comma
7032 as the operand separator there is even less consistent, since
7033 there all branches only have a single operand. */
7034 if (this_operand != 0
7035 || intel_parser.in_offset
7036 || intel_parser.in_bracket
7037 || (!(current_templates->start->opcode_modifier
7038 & (Jump|JumpDword|JumpInterSegment))
7039 && !(current_templates->start->operand_types[0]
7041 return intel_match_token (T_NIL);
7042 /* Remember the start of the 2nd operand and terminate 1st
7044 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7045 another expression), but it gets at least the simplest case
7046 (a plain number or symbol on the left side) right. */
7047 intel_parser.next_operand = intel_parser.op_string;
7048 *--intel_parser.op_string = '\0';
7049 return intel_match_token (':');
7057 intel_match_token (cur_token.code);
7063 --intel_parser.in_offset;
7066 if (NUM_ADDRESS_REGS > nregs)
7068 as_bad (_("Invalid operand to `OFFSET'"));
7071 intel_parser.op_modifier |= 1 << T_OFFSET;
7074 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7075 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7080 intel_bracket_expr (void)
7082 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7083 const char *start = intel_parser.op_string;
7086 if (i.op[this_operand].regs)
7087 return intel_match_token (T_NIL);
7089 intel_match_token ('[');
7091 /* Mark as a memory operand only if it's not already known to be an
7092 offset expression. If it's an offset expression, we need to keep
7094 if (!intel_parser.in_offset)
7096 ++intel_parser.in_bracket;
7098 /* Operands for jump/call inside brackets denote absolute addresses. */
7099 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7100 i.types[this_operand] |= JumpAbsolute;
7102 /* Unfortunately gas always diverged from MASM in a respect that can't
7103 be easily fixed without risking to break code sequences likely to be
7104 encountered (the testsuite even check for this): MASM doesn't consider
7105 an expression inside brackets unconditionally as a memory reference.
7106 When that is e.g. a constant, an offset expression, or the sum of the
7107 two, this is still taken as a constant load. gas, however, always
7108 treated these as memory references. As a compromise, we'll try to make
7109 offset expressions inside brackets work the MASM way (since that's
7110 less likely to be found in real world code), but make constants alone
7111 continue to work the traditional gas way. In either case, issue a
7113 intel_parser.op_modifier &= ~was_offset;
7116 strcat (intel_parser.disp, "[");
7118 /* Add a '+' to the displacement string if necessary. */
7119 if (*intel_parser.disp != '\0'
7120 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7121 strcat (intel_parser.disp, "+");
7124 && (len = intel_parser.op_string - start - 1,
7125 intel_match_token (']')))
7127 /* Preserve brackets when the operand is an offset expression. */
7128 if (intel_parser.in_offset)
7129 strcat (intel_parser.disp, "]");
7132 --intel_parser.in_bracket;
7133 if (i.base_reg || i.index_reg)
7134 intel_parser.is_mem = 1;
7135 if (!intel_parser.is_mem)
7137 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7138 /* Defer the warning until all of the operand was parsed. */
7139 intel_parser.is_mem = -1;
7140 else if (!quiet_warnings)
7141 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7142 len, start, len, start);
7145 intel_parser.op_modifier |= was_offset;
7162 while (cur_token.code == '[')
7164 if (!intel_bracket_expr ())
7189 switch (cur_token.code)
7193 intel_match_token ('(');
7194 strcat (intel_parser.disp, "(");
7196 if (intel_expr () && intel_match_token (')'))
7198 strcat (intel_parser.disp, ")");
7205 return intel_bracket_expr ();
7210 strcat (intel_parser.disp, cur_token.str);
7211 intel_match_token (cur_token.code);
7213 /* Mark as a memory operand only if it's not already known to be an
7214 offset expression. */
7215 if (!intel_parser.in_offset)
7216 intel_parser.is_mem = 1;
7223 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7225 intel_match_token (T_REG);
7227 /* Check for segment change. */
7228 if (cur_token.code == ':')
7230 if (!(reg->reg_type & (SReg2 | SReg3)))
7232 as_bad (_("`%s' is not a valid segment register"),
7236 else if (i.seg[i.mem_operands])
7237 as_warn (_("Extra segment override ignored"));
7240 if (!intel_parser.in_offset)
7241 intel_parser.is_mem = 1;
7242 switch (reg->reg_num)
7245 i.seg[i.mem_operands] = &es;
7248 i.seg[i.mem_operands] = &cs;
7251 i.seg[i.mem_operands] = &ss;
7254 i.seg[i.mem_operands] = &ds;
7257 i.seg[i.mem_operands] = &fs;
7260 i.seg[i.mem_operands] = &gs;
7266 /* Not a segment register. Check for register scaling. */
7267 else if (cur_token.code == '*')
7269 if (!intel_parser.in_bracket)
7271 as_bad (_("Register scaling only allowed in memory operands"));
7275 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7276 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7277 else if (i.index_reg)
7278 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7280 /* What follows must be a valid scale. */
7281 intel_match_token ('*');
7283 i.types[this_operand] |= BaseIndex;
7285 /* Set the scale after setting the register (otherwise,
7286 i386_scale will complain) */
7287 if (cur_token.code == '+' || cur_token.code == '-')
7289 char *str, sign = cur_token.code;
7290 intel_match_token (cur_token.code);
7291 if (cur_token.code != T_CONST)
7293 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7297 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7298 strcpy (str + 1, cur_token.str);
7300 if (!i386_scale (str))
7304 else if (!i386_scale (cur_token.str))
7306 intel_match_token (cur_token.code);
7309 /* No scaling. If this is a memory operand, the register is either a
7310 base register (first occurrence) or an index register (second
7312 else if (intel_parser.in_bracket)
7317 else if (!i.index_reg)
7321 as_bad (_("Too many register references in memory operand"));
7325 i.types[this_operand] |= BaseIndex;
7328 /* It's neither base nor index. */
7329 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7331 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7332 i.op[this_operand].regs = reg;
7337 as_bad (_("Invalid use of register"));
7341 /* Since registers are not part of the displacement string (except
7342 when we're parsing offset operands), we may need to remove any
7343 preceding '+' from the displacement string. */
7344 if (*intel_parser.disp != '\0'
7345 && !intel_parser.in_offset)
7347 char *s = intel_parser.disp;
7348 s += strlen (s) - 1;
7371 intel_match_token (cur_token.code);
7373 if (cur_token.code == T_PTR)
7376 /* It must have been an identifier. */
7377 intel_putback_token ();
7378 cur_token.code = T_ID;
7384 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7388 /* The identifier represents a memory reference only if it's not
7389 preceded by an offset modifier and if it's not an equate. */
7390 symbolP = symbol_find(cur_token.str);
7391 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7392 intel_parser.is_mem = 1;
7400 char *save_str, sign = 0;
7402 /* Allow constants that start with `+' or `-'. */
7403 if (cur_token.code == '-' || cur_token.code == '+')
7405 sign = cur_token.code;
7406 intel_match_token (cur_token.code);
7407 if (cur_token.code != T_CONST)
7409 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7415 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7416 strcpy (save_str + !!sign, cur_token.str);
7420 /* Get the next token to check for register scaling. */
7421 intel_match_token (cur_token.code);
7423 /* Check if this constant is a scaling factor for an
7425 if (cur_token.code == '*')
7427 if (intel_match_token ('*') && cur_token.code == T_REG)
7429 const reg_entry *reg = cur_token.reg;
7431 if (!intel_parser.in_bracket)
7433 as_bad (_("Register scaling only allowed "
7434 "in memory operands"));
7438 /* Disallow things like [1*si].
7439 sp and esp are invalid as index. */
7440 if (reg->reg_type & Reg16)
7441 reg = i386_regtab + REGNAM_AX + 4;
7442 else if (i.index_reg)
7443 reg = i386_regtab + REGNAM_EAX + 4;
7445 /* The constant is followed by `* reg', so it must be
7448 i.types[this_operand] |= BaseIndex;
7450 /* Set the scale after setting the register (otherwise,
7451 i386_scale will complain) */
7452 if (!i386_scale (save_str))
7454 intel_match_token (T_REG);
7456 /* Since registers are not part of the displacement
7457 string, we may need to remove any preceding '+' from
7458 the displacement string. */
7459 if (*intel_parser.disp != '\0')
7461 char *s = intel_parser.disp;
7462 s += strlen (s) - 1;
7472 /* The constant was not used for register scaling. Since we have
7473 already consumed the token following `*' we now need to put it
7474 back in the stream. */
7475 intel_putback_token ();
7478 /* Add the constant to the displacement string. */
7479 strcat (intel_parser.disp, save_str);
7486 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7490 /* Match the given token against cur_token. If they match, read the next
7491 token from the operand string. */
7493 intel_match_token (int code)
7495 if (cur_token.code == code)
7502 as_bad (_("Unexpected token `%s'"), cur_token.str);
7507 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7509 intel_get_token (void)
7512 const reg_entry *reg;
7513 struct intel_token new_token;
7515 new_token.code = T_NIL;
7516 new_token.reg = NULL;
7517 new_token.str = NULL;
7519 /* Free the memory allocated to the previous token and move
7520 cur_token to prev_token. */
7522 free (prev_token.str);
7524 prev_token = cur_token;
7526 /* Skip whitespace. */
7527 while (is_space_char (*intel_parser.op_string))
7528 intel_parser.op_string++;
7530 /* Return an empty token if we find nothing else on the line. */
7531 if (*intel_parser.op_string == '\0')
7533 cur_token = new_token;
7537 /* The new token cannot be larger than the remainder of the operand
7539 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7540 new_token.str[0] = '\0';
7542 if (strchr ("0123456789", *intel_parser.op_string))
7544 char *p = new_token.str;
7545 char *q = intel_parser.op_string;
7546 new_token.code = T_CONST;
7548 /* Allow any kind of identifier char to encompass floating point and
7549 hexadecimal numbers. */
7550 while (is_identifier_char (*q))
7554 /* Recognize special symbol names [0-9][bf]. */
7555 if (strlen (intel_parser.op_string) == 2
7556 && (intel_parser.op_string[1] == 'b'
7557 || intel_parser.op_string[1] == 'f'))
7558 new_token.code = T_ID;
7561 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7563 size_t len = end_op - intel_parser.op_string;
7565 new_token.code = T_REG;
7566 new_token.reg = reg;
7568 memcpy (new_token.str, intel_parser.op_string, len);
7569 new_token.str[len] = '\0';
7572 else if (is_identifier_char (*intel_parser.op_string))
7574 char *p = new_token.str;
7575 char *q = intel_parser.op_string;
7577 /* A '.' or '$' followed by an identifier char is an identifier.
7578 Otherwise, it's operator '.' followed by an expression. */
7579 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7581 new_token.code = '.';
7582 new_token.str[0] = '.';
7583 new_token.str[1] = '\0';
7587 while (is_identifier_char (*q) || *q == '@')
7591 if (strcasecmp (new_token.str, "NOT") == 0)
7592 new_token.code = '~';
7594 else if (strcasecmp (new_token.str, "MOD") == 0)
7595 new_token.code = '%';
7597 else if (strcasecmp (new_token.str, "AND") == 0)
7598 new_token.code = '&';
7600 else if (strcasecmp (new_token.str, "OR") == 0)
7601 new_token.code = '|';
7603 else if (strcasecmp (new_token.str, "XOR") == 0)
7604 new_token.code = '^';
7606 else if (strcasecmp (new_token.str, "SHL") == 0)
7607 new_token.code = T_SHL;
7609 else if (strcasecmp (new_token.str, "SHR") == 0)
7610 new_token.code = T_SHR;
7612 else if (strcasecmp (new_token.str, "BYTE") == 0)
7613 new_token.code = T_BYTE;
7615 else if (strcasecmp (new_token.str, "WORD") == 0)
7616 new_token.code = T_WORD;
7618 else if (strcasecmp (new_token.str, "DWORD") == 0)
7619 new_token.code = T_DWORD;
7621 else if (strcasecmp (new_token.str, "FWORD") == 0)
7622 new_token.code = T_FWORD;
7624 else if (strcasecmp (new_token.str, "QWORD") == 0)
7625 new_token.code = T_QWORD;
7627 else if (strcasecmp (new_token.str, "TBYTE") == 0
7628 /* XXX remove (gcc still uses it) */
7629 || strcasecmp (new_token.str, "XWORD") == 0)
7630 new_token.code = T_TBYTE;
7632 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7633 || strcasecmp (new_token.str, "OWORD") == 0)
7634 new_token.code = T_XMMWORD;
7636 else if (strcasecmp (new_token.str, "PTR") == 0)
7637 new_token.code = T_PTR;
7639 else if (strcasecmp (new_token.str, "SHORT") == 0)
7640 new_token.code = T_SHORT;
7642 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7644 new_token.code = T_OFFSET;
7646 /* ??? This is not mentioned in the MASM grammar but gcc
7647 makes use of it with -mintel-syntax. OFFSET may be
7648 followed by FLAT: */
7649 if (strncasecmp (q, " FLAT:", 6) == 0)
7650 strcat (new_token.str, " FLAT:");
7653 /* ??? This is not mentioned in the MASM grammar. */
7654 else if (strcasecmp (new_token.str, "FLAT") == 0)
7656 new_token.code = T_OFFSET;
7658 strcat (new_token.str, ":");
7660 as_bad (_("`:' expected"));
7664 new_token.code = T_ID;
7668 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7670 new_token.code = *intel_parser.op_string;
7671 new_token.str[0] = *intel_parser.op_string;
7672 new_token.str[1] = '\0';
7675 else if (strchr ("<>", *intel_parser.op_string)
7676 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7678 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7679 new_token.str[0] = *intel_parser.op_string;
7680 new_token.str[1] = *intel_parser.op_string;
7681 new_token.str[2] = '\0';
7685 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7687 intel_parser.op_string += strlen (new_token.str);
7688 cur_token = new_token;
7691 /* Put cur_token back into the token stream and make cur_token point to
7694 intel_putback_token (void)
7696 if (cur_token.code != T_NIL)
7698 intel_parser.op_string -= strlen (cur_token.str);
7699 free (cur_token.str);
7701 cur_token = prev_token;
7703 /* Forget prev_token. */
7704 prev_token.code = T_NIL;
7705 prev_token.reg = NULL;
7706 prev_token.str = NULL;
7710 tc_x86_regname_to_dw2regnum (char *regname)
7712 unsigned int regnum;
7713 unsigned int regnames_count;
7714 static const char *const regnames_32[] =
7716 "eax", "ecx", "edx", "ebx",
7717 "esp", "ebp", "esi", "edi",
7718 "eip", "eflags", NULL,
7719 "st0", "st1", "st2", "st3",
7720 "st4", "st5", "st6", "st7",
7722 "xmm0", "xmm1", "xmm2", "xmm3",
7723 "xmm4", "xmm5", "xmm6", "xmm7",
7724 "mm0", "mm1", "mm2", "mm3",
7725 "mm4", "mm5", "mm6", "mm7",
7726 "fcw", "fsw", "mxcsr",
7727 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7730 static const char *const regnames_64[] =
7732 "rax", "rdx", "rcx", "rbx",
7733 "rsi", "rdi", "rbp", "rsp",
7734 "r8", "r9", "r10", "r11",
7735 "r12", "r13", "r14", "r15",
7737 "xmm0", "xmm1", "xmm2", "xmm3",
7738 "xmm4", "xmm5", "xmm6", "xmm7",
7739 "xmm8", "xmm9", "xmm10", "xmm11",
7740 "xmm12", "xmm13", "xmm14", "xmm15",
7741 "st0", "st1", "st2", "st3",
7742 "st4", "st5", "st6", "st7",
7743 "mm0", "mm1", "mm2", "mm3",
7744 "mm4", "mm5", "mm6", "mm7",
7746 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7747 "fs.base", "gs.base", NULL, NULL,
7749 "mxcsr", "fcw", "fsw"
7751 const char *const *regnames;
7753 if (flag_code == CODE_64BIT)
7755 regnames = regnames_64;
7756 regnames_count = ARRAY_SIZE (regnames_64);
7760 regnames = regnames_32;
7761 regnames_count = ARRAY_SIZE (regnames_32);
7764 for (regnum = 0; regnum < regnames_count; regnum++)
7765 if (regnames[regnum] != NULL
7766 && strcmp (regname, regnames[regnum]) == 0)
7773 tc_x86_frame_initial_instructions (void)
7775 static unsigned int sp_regno;
7778 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7781 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7782 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7786 i386_elf_section_type (const char *str, size_t len)
7788 if (flag_code == CODE_64BIT
7789 && len == sizeof ("unwind") - 1
7790 && strncmp (str, "unwind", 6) == 0)
7791 return SHT_X86_64_UNWIND;
7798 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7802 expr.X_op = O_secrel;
7803 expr.X_add_symbol = symbol;
7804 expr.X_add_number = 0;
7805 emit_expr (&expr, size);
7809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7810 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7813 x86_64_section_letter (int letter, char **ptr_msg)
7815 if (flag_code == CODE_64BIT)
7818 return SHF_X86_64_LARGE;
7820 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7823 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7828 x86_64_section_word (char *str, size_t len)
7830 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
7831 return SHF_X86_64_LARGE;
7837 handle_large_common (int small ATTRIBUTE_UNUSED)
7839 if (flag_code != CODE_64BIT)
7841 s_comm_internal (0, elf_common_parse);
7842 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7846 static segT lbss_section;
7847 asection *saved_com_section_ptr = elf_com_section_ptr;
7848 asection *saved_bss_section = bss_section;
7850 if (lbss_section == NULL)
7852 flagword applicable;
7854 subsegT subseg = now_subseg;
7856 /* The .lbss section is for local .largecomm symbols. */
7857 lbss_section = subseg_new (".lbss", 0);
7858 applicable = bfd_applicable_section_flags (stdoutput);
7859 bfd_set_section_flags (stdoutput, lbss_section,
7860 applicable & SEC_ALLOC);
7861 seg_info (lbss_section)->bss = 1;
7863 subseg_set (seg, subseg);
7866 elf_com_section_ptr = &_bfd_elf_large_com_section;
7867 bss_section = lbss_section;
7869 s_comm_internal (0, elf_common_parse);
7871 elf_com_section_ptr = saved_com_section_ptr;
7872 bss_section = saved_bss_section;
7875 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */